Commit 0a068b68 authored by Jake Wang's avatar Jake Wang Committed by Alex Deucher
Browse files

drm/amd/display: Added HPO HW control shutdown support 



[Why]
HPO is only used for DP2.0. HPO HW control should be
disable when not being used to save power.

[How]
Shutdown HPO HW control during init hw.
Shutdown HPO HW control during stream disable.
Enable HPO HW control during stream enable if DP2.0.

Acked-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: default avatarJake Wang <haonan.wang2@amd.com>
Reviewed-by: default avatarNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent edcf52ca

drivers/gpu/drm/amd/display/dc/dc.h

+1 −0
Original line number Diff line number Diff line
@@ -675,6 +675,7 @@ struct dc_debug_options { 
#endif

	union mem_low_power_enable_options enable_mem_low_power;

	union root_clock_optimization_options root_clock_optimization;

	bool hpo_optimization;

	bool force_vblank_alignment;



	/* Enable dmub aux for legacy ddc */

drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h

+3 −1
Original line number Diff line number Diff line
@@ -671,6 +671,7 @@ struct dce_hwseq_registers { 
	uint32_t MC_VM_FB_LOCATION_BASE;

	uint32_t MC_VM_FB_LOCATION_TOP;

	uint32_t MC_VM_FB_OFFSET;

	uint32_t HPO_TOP_HW_CONTROL;

};

 /* set field name */

#define HWS_SF(blk_name, reg_name, field_name, post_fix)\
@@ -1152,7 +1153,8 @@ struct dce_hwseq_registers { 
	type DOMAIN_PGFSM_PWR_STATUS;\

	type HPO_HDMISTREAMCLK_G_GATE_DIS;\

	type DISABLE_HOSTVM_FORCE_ALLOW_PSTATE;\

	type I2C_LIGHT_SLEEP_FORCE;

	type I2C_LIGHT_SLEEP_FORCE;\

	type HPO_IO_EN;



struct dce_hwseq_shift {

	HWSEQ_REG_FIELD_LIST(uint8_t)

drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

+6 −0
Original line number Diff line number Diff line
@@ -1244,6 +1244,12 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx) 
#endif

	if (dc_is_dp_signal(pipe_ctx->stream->signal))

		dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_DISCONNECT_DIG_FE_BE);



#if defined(CONFIG_DRM_AMD_DC_DCN)

	if (dc->hwseq->funcs.setup_hpo_hw_control && is_dp_128b_132b_signal(pipe_ctx))

		dc->hwseq->funcs.setup_hpo_hw_control(dc->hwseq, false);

#endif



}



void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

+3 −0
Original line number Diff line number Diff line
@@ -2397,6 +2397,9 @@ void dcn20_enable_stream(struct pipe_ctx *pipe_ctx) 
	 * BY this, it is logic clean to separate stream and link

	 */

	if (is_dp_128b_132b_signal(pipe_ctx)) {

		if (pipe_ctx->stream->ctx->dc->hwseq->funcs.setup_hpo_hw_control)

			pipe_ctx->stream->ctx->dc->hwseq->funcs.setup_hpo_hw_control(

				pipe_ctx->stream->ctx->dc->hwseq, true);

		setup_dp_hpo_stream(pipe_ctx, true);

		pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->enable_stream(

				pipe_ctx->stream_res.hpo_dp_stream_enc);

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c

+9 −0
Original line number Diff line number Diff line
@@ -264,6 +264,9 @@ void dcn31_init_hw(struct dc *dc) 
	if (dc->debug.enable_mem_low_power.bits.i2c)

		REG_UPDATE(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, 1);



	if (hws->funcs.setup_hpo_hw_control)

		hws->funcs.setup_hpo_hw_control(hws, false);



	if (!dc->debug.disable_clock_gate) {

		/* enable all DCN clock gating */

		REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
@@ -597,3 +600,9 @@ void dcn31_reset_hw_ctx_wrap( 
	/* New dc_state in the process of being applied to hardware. */

	dc->current_state->res_ctx.link_enc_cfg_ctx.mode = LINK_ENC_CFG_TRANSIENT;

}



void dcn31_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable)

{

	if (hws->ctx->dc->debug.hpo_optimization)

		REG_UPDATE(HPO_TOP_HW_CONTROL, HPO_IO_EN, !!enable);

}