Commit edcf52ca authored by Wenjing Liu's avatar Wenjing Liu Committed by Alex Deucher
Browse files

drm/amd/display: fix register write sequence for LINK_SQUARE_PATTERN 



[why&how]
write LINK_SQUARE_PATTERN_num + 1 for square pulse pattern.
Specs requirement to write this register prior to write LINK_QUAL_LANEX_SET.

Acked-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: default avatarWenjing Liu <wenjing.liu@amd.com>
Reviewed-by: default avatarGeorge Shen <george.shen@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 589bd2f0

drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

+8 −0
Original line number Diff line number Diff line
@@ -5329,6 +5329,14 @@ bool dc_link_dp_set_test_pattern( 
			return false;



		if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {

#if defined(CONFIG_DRM_AMD_DC_DCN)

			if (test_pattern == DP_TEST_PATTERN_SQUARE_PULSE)

				core_link_write_dpcd(link,

						DP_LINK_SQUARE_PATTERN,

						p_custom_pattern,

						1);



#endif

			/* tell receiver that we are sending qualification

			 * pattern DP 1.2 or later - DP receiver's link quality

			 * pattern is set using DPCD LINK_QUAL_LANEx_SET

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

+3 −0
Original line number Diff line number Diff line
@@ -898,6 +898,9 @@ struct dpcd_usb4_dp_tunneling_info { 
#ifndef DP_DFP_CAPABILITY_EXTENSION_SUPPORT

#define DP_DFP_CAPABILITY_EXTENSION_SUPPORT		0x0A3

#endif

#ifndef DP_LINK_SQUARE_PATTERN

#define DP_LINK_SQUARE_PATTERN				0x10F

#endif

#ifndef DP_DSC_CONFIGURATION

#define DP_DSC_CONFIGURATION				0x161

#endif