LoongArch: Add memory management

/* SPDX-License-Identifier: GPL-2.0 */

/*

 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited

 */

#ifndef _ASM_CACHE_H

#define _ASM_CACHE_H

#define L1_CACHE_SHIFT		CONFIG_L1_CACHE_SHIFT

#define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)

#define __read_mostly __section(".data..read_mostly")

#endif /* _ASM_CACHE_H */

/* SPDX-License-Identifier: GPL-2.0 */

/*

 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited

 */

#ifndef _ASM_CACHEFLUSH_H

#define _ASM_CACHEFLUSH_H

#include <linux/mm.h>

#include <asm/cpu-features.h>

#include <asm/cacheops.h>

extern void local_flush_icache_range(unsigned long start, unsigned long end);

#define flush_icache_range	local_flush_icache_range

#define flush_icache_user_range	local_flush_icache_range

#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0

#define flush_cache_all()				do { } while (0)

#define flush_cache_mm(mm)				do { } while (0)

#define flush_cache_dup_mm(mm)				do { } while (0)

#define flush_cache_range(vma, start, end)		do { } while (0)

#define flush_cache_page(vma, vmaddr, pfn)		do { } while (0)

#define flush_cache_vmap(start, end)			do { } while (0)

#define flush_cache_vunmap(start, end)			do { } while (0)

#define flush_icache_page(vma, page)			do { } while (0)

#define flush_icache_user_page(vma, page, addr, len)	do { } while (0)

#define flush_dcache_page(page)				do { } while (0)

#define flush_dcache_mmap_lock(mapping)			do { } while (0)

#define flush_dcache_mmap_unlock(mapping)		do { } while (0)

#define cache_op(op, addr)						\

	__asm__ __volatile__(						\

	"	cacop	%0, %1					\n"	\

	:								\

	: "i" (op), "ZC" (*(unsigned char *)(addr)))

static inline void flush_icache_line_indexed(unsigned long addr)

{

	cache_op(Index_Invalidate_I, addr);

}

static inline void flush_dcache_line_indexed(unsigned long addr)

{

	cache_op(Index_Writeback_Inv_D, addr);

}

static inline void flush_vcache_line_indexed(unsigned long addr)

{

	cache_op(Index_Writeback_Inv_V, addr);

}

static inline void flush_scache_line_indexed(unsigned long addr)

{

	cache_op(Index_Writeback_Inv_S, addr);

}

static inline void flush_icache_line(unsigned long addr)

{

	cache_op(Hit_Invalidate_I, addr);

}

static inline void flush_dcache_line(unsigned long addr)

{

	cache_op(Hit_Writeback_Inv_D, addr);

}

static inline void flush_vcache_line(unsigned long addr)

{

	cache_op(Hit_Writeback_Inv_V, addr);

}

static inline void flush_scache_line(unsigned long addr)

{

	cache_op(Hit_Writeback_Inv_S, addr);

}

#include <asm-generic/cacheflush.h>

#endif /* _ASM_CACHEFLUSH_H */

/* SPDX-License-Identifier: GPL-2.0 */

/*

 * Cache operations for the cache instruction.

 *

 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited

 */

#ifndef __ASM_CACHEOPS_H

#define __ASM_CACHEOPS_H

/*

 * Most cache ops are split into a 2 bit field identifying the cache, and a 3

 * bit field identifying the cache operation.

 */

#define CacheOp_Cache			0x03

#define CacheOp_Op			0x1c

#define Cache_I				0x00

#define Cache_D				0x01

#define Cache_V				0x02

#define Cache_S				0x03

#define Index_Invalidate		0x08

#define Index_Writeback_Inv		0x08

#define Hit_Invalidate			0x10

#define Hit_Writeback_Inv		0x10

#define CacheOp_User_Defined		0x18

#define Index_Invalidate_I		(Cache_I | Index_Invalidate)

#define Index_Writeback_Inv_D		(Cache_D | Index_Writeback_Inv)

#define Index_Writeback_Inv_V		(Cache_V | Index_Writeback_Inv)

#define Index_Writeback_Inv_S		(Cache_S | Index_Writeback_Inv)

#define Hit_Invalidate_I		(Cache_I | Hit_Invalidate)

#define Hit_Writeback_Inv_D		(Cache_D | Hit_Writeback_Inv)

#define Hit_Writeback_Inv_V		(Cache_V | Hit_Writeback_Inv)

#define Hit_Writeback_Inv_S		(Cache_S | Hit_Writeback_Inv)

#endif	/* __ASM_CACHEOPS_H */

/* SPDX-License-Identifier: GPL-2.0 */

/*

 * fixmap.h: compile-time virtual memory allocation

 *

 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited

 */

#ifndef _ASM_FIXMAP_H

#define _ASM_FIXMAP_H

#define NR_FIX_BTMAPS 64

#endif

/* SPDX-License-Identifier: GPL-2.0 */

/*

 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited

 */

#ifndef __ASM_HUGETLB_H

#define __ASM_HUGETLB_H

#include <asm/page.h>

uint64_t pmd_to_entrylo(unsigned long pmd_val);

#define __HAVE_ARCH_PREPARE_HUGEPAGE_RANGE

static inline int prepare_hugepage_range(struct file *file,

					 unsigned long addr,

					 unsigned long len)

{

	unsigned long task_size = STACK_TOP;

	struct hstate *h = hstate_file(file);

	if (len & ~huge_page_mask(h))

		return -EINVAL;

	if (addr & ~huge_page_mask(h))

		return -EINVAL;

	if (len > task_size)

		return -ENOMEM;

	if (task_size - len < addr)

		return -EINVAL;

	return 0;

}

#define __HAVE_ARCH_HUGE_PTEP_GET_AND_CLEAR

static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,

					    unsigned long addr, pte_t *ptep)

{

	pte_t clear;

	pte_t pte = *ptep;

	pte_val(clear) = (unsigned long)invalid_pte_table;

	set_pte_at(mm, addr, ptep, clear);

	return pte;

}

#define __HAVE_ARCH_HUGE_PTEP_CLEAR_FLUSH

static inline pte_t huge_ptep_clear_flush(struct vm_area_struct *vma,

					  unsigned long addr, pte_t *ptep)

{

	pte_t pte;

	pte = huge_ptep_get_and_clear(vma->vm_mm, addr, ptep);

	flush_tlb_page(vma, addr);

	return pte;

}

#define __HAVE_ARCH_HUGE_PTE_NONE

static inline int huge_pte_none(pte_t pte)

{

	unsigned long val = pte_val(pte) & ~_PAGE_GLOBAL;

	return !val || (val == (unsigned long)invalid_pte_table);

}

#define __HAVE_ARCH_HUGE_PTEP_SET_ACCESS_FLAGS

static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,

					     unsigned long addr,

					     pte_t *ptep, pte_t pte,

					     int dirty)

{

	int changed = !pte_same(*ptep, pte);

	if (changed) {

		set_pte_at(vma->vm_mm, addr, ptep, pte);

		/*

		 * There could be some standard sized pages in there,

		 * get them all.

		 */

		flush_tlb_range(vma, addr, addr + HPAGE_SIZE);

	}

	return changed;

}

#include <asm-generic/hugetlb.h>

#endif /* __ASM_HUGETLB_H */