LoongArch: Add process management

/* SPDX-License-Identifier: GPL-2.0 */

/*

 * Author: Huacai Chen <chenhuacai@loongson.cn>

 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited

 */

#ifndef _ASM_FPU_H

#define _ASM_FPU_H

#include <linux/sched.h>

#include <linux/sched/task_stack.h>

#include <linux/ptrace.h>

#include <linux/thread_info.h>

#include <linux/bitops.h>

#include <asm/cpu.h>

#include <asm/cpu-features.h>

#include <asm/current.h>

#include <asm/loongarch.h>

#include <asm/processor.h>

#include <asm/ptrace.h>

struct sigcontext;

extern void _init_fpu(unsigned int);

extern void _save_fp(struct loongarch_fpu *);

extern void _restore_fp(struct loongarch_fpu *);

/*

 * Mask the FCSR Cause bits according to the Enable bits, observing

 * that Unimplemented is always enabled.

 */

static inline unsigned long mask_fcsr_x(unsigned long fcsr)

{

	return fcsr & ((fcsr & FPU_CSR_ALL_E) <<

			(ffs(FPU_CSR_ALL_X) - ffs(FPU_CSR_ALL_E)));

}

static inline int is_fp_enabled(void)

{

	return (csr_read32(LOONGARCH_CSR_EUEN) & CSR_EUEN_FPEN) ?

		1 : 0;

}

#define enable_fpu()		set_csr_euen(CSR_EUEN_FPEN)

#define disable_fpu()		clear_csr_euen(CSR_EUEN_FPEN)

#define clear_fpu_owner()	clear_thread_flag(TIF_USEDFPU)

static inline int is_fpu_owner(void)

{

	return test_thread_flag(TIF_USEDFPU);

}

static inline void __own_fpu(void)

{

	enable_fpu();

	set_thread_flag(TIF_USEDFPU);

	KSTK_EUEN(current) |= CSR_EUEN_FPEN;

}

static inline void own_fpu_inatomic(int restore)

{

	if (cpu_has_fpu && !is_fpu_owner()) {

		__own_fpu();

		if (restore)

			_restore_fp(&current->thread.fpu);

	}

}

static inline void own_fpu(int restore)

{

	preempt_disable();

	own_fpu_inatomic(restore);

	preempt_enable();

}

static inline void lose_fpu_inatomic(int save, struct task_struct *tsk)

{

	if (is_fpu_owner()) {

		if (save)

			_save_fp(&tsk->thread.fpu);

		disable_fpu();

		clear_tsk_thread_flag(tsk, TIF_USEDFPU);

	}

	KSTK_EUEN(tsk) &= ~(CSR_EUEN_FPEN | CSR_EUEN_LSXEN | CSR_EUEN_LASXEN);

}

static inline void lose_fpu(int save)

{

	preempt_disable();

	lose_fpu_inatomic(save, current);

	preempt_enable();

}

static inline void init_fpu(void)

{

	unsigned int fcsr = current->thread.fpu.fcsr;

	__own_fpu();

	_init_fpu(fcsr);

	set_used_math();

}

static inline void save_fp(struct task_struct *tsk)

{

	if (cpu_has_fpu)

		_save_fp(&tsk->thread.fpu);

}

static inline void restore_fp(struct task_struct *tsk)

{

	if (cpu_has_fpu)

		_restore_fp(&tsk->thread.fpu);

}

static inline union fpureg *get_fpu_regs(struct task_struct *tsk)

{

	if (tsk == current) {

		preempt_disable();

		if (is_fpu_owner())

			_save_fp(&current->thread.fpu);

		preempt_enable();

	}

	return tsk->thread.fpu.fpr;

}

#endif /* _ASM_FPU_H */

/* SPDX-License-Identifier: GPL-2.0 */

#ifndef __ASM_IDLE_H

#define __ASM_IDLE_H

#include <linux/linkage.h>

extern asmlinkage void __arch_cpu_idle(void);

#endif /* __ASM_IDLE_H  */

/* SPDX-License-Identifier: GPL-2.0 */

/*

 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited

 */

#ifndef __ASM_MMU_H

#define __ASM_MMU_H

#include <linux/atomic.h>

#include <linux/spinlock.h>

typedef struct {

	u64 asid[NR_CPUS];

	void *vdso;

} mm_context_t;

#endif /* __ASM_MMU_H */

/* SPDX-License-Identifier: GPL-2.0 */

/*

 * Switch a MMU context.

 *

 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited

 */

#ifndef _ASM_MMU_CONTEXT_H

#define _ASM_MMU_CONTEXT_H

#include <linux/errno.h>

#include <linux/sched.h>

#include <linux/mm_types.h>

#include <linux/smp.h>

#include <linux/slab.h>

#include <asm/cacheflush.h>

#include <asm/tlbflush.h>

#include <asm-generic/mm_hooks.h>

/*

 *  All unused by hardware upper bits will be considered

 *  as a software asid extension.

 */

static inline u64 asid_version_mask(unsigned int cpu)

{

	return ~(u64)(cpu_asid_mask(&cpu_data[cpu]));

}

static inline u64 asid_first_version(unsigned int cpu)

{

	return cpu_asid_mask(&cpu_data[cpu]) + 1;

}

#define cpu_context(cpu, mm)	((mm)->context.asid[cpu])

#define asid_cache(cpu)		(cpu_data[cpu].asid_cache)

#define cpu_asid(cpu, mm)	(cpu_context((cpu), (mm)) & cpu_asid_mask(&cpu_data[cpu]))

static inline int asid_valid(struct mm_struct *mm, unsigned int cpu)

{

	if ((cpu_context(cpu, mm) ^ asid_cache(cpu)) & asid_version_mask(cpu))

		return 0;

	return 1;

}

static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)

{

}

/* Normal, classic get_new_mmu_context */

static inline void

get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)

{

	u64 asid = asid_cache(cpu);

	if (!((++asid) & cpu_asid_mask(&cpu_data[cpu])))

		local_flush_tlb_user();	/* start new asid cycle */

	cpu_context(cpu, mm) = asid_cache(cpu) = asid;

}

/*

 * Initialize the context related info for a new mm_struct

 * instance.

 */

static inline int

init_new_context(struct task_struct *tsk, struct mm_struct *mm)

{

	int i;

	for_each_possible_cpu(i)

		cpu_context(i, mm) = 0;

	return 0;

}

static inline void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next,

				      struct task_struct *tsk)

{

	unsigned int cpu = smp_processor_id();

	/* Check if our ASID is of an older version and thus invalid */

	if (!asid_valid(next, cpu))

		get_new_mmu_context(next, cpu);

	write_csr_asid(cpu_asid(cpu, next));

	if (next != &init_mm)

		csr_write64((unsigned long)next->pgd, LOONGARCH_CSR_PGDL);

	else

		csr_write64((unsigned long)invalid_pg_dir, LOONGARCH_CSR_PGDL);

	/*

	 * Mark current->active_mm as not "active" anymore.

	 * We don't want to mislead possible IPI tlb flush routines.

	 */

	cpumask_set_cpu(cpu, mm_cpumask(next));

}

#define switch_mm_irqs_off switch_mm_irqs_off

static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,

			     struct task_struct *tsk)

{

	unsigned long flags;

	local_irq_save(flags);

	switch_mm_irqs_off(prev, next, tsk);

	local_irq_restore(flags);

}

/*

 * Destroy context related info for an mm_struct that is about

 * to be put to rest.

 */

static inline void destroy_context(struct mm_struct *mm)

{

}

#define activate_mm(prev, next)	switch_mm(prev, next, current)

#define deactivate_mm(task, mm)	do { } while (0)

/*

 * If mm is currently active, we can't really drop it.

 * Instead, we will get a new one for it.

 */

static inline void

drop_mmu_context(struct mm_struct *mm, unsigned int cpu)

{

	int asid;

	unsigned long flags;

	local_irq_save(flags);

	asid = read_csr_asid() & cpu_asid_mask(&current_cpu_data);

	if (asid == cpu_asid(cpu, mm)) {

		if (!current->mm || (current->mm == mm)) {

			get_new_mmu_context(mm, cpu);

			write_csr_asid(cpu_asid(cpu, mm));

			goto out;

		}

	}

	/* Will get a new context next time */

	cpu_context(cpu, mm) = 0;

	cpumask_clear_cpu(cpu, mm_cpumask(mm));

out:

	local_irq_restore(flags);

}

#endif /* _ASM_MMU_CONTEXT_H */

/* SPDX-License-Identifier: GPL-2.0 */

/*

 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited

 */

#ifndef _ASM_PROCESSOR_H

#define _ASM_PROCESSOR_H

#include <linux/atomic.h>

#include <linux/cpumask.h>

#include <linux/sizes.h>

#include <asm/cpu.h>

#include <asm/cpu-info.h>

#include <asm/loongarch.h>

#include <asm/vdso/processor.h>

#include <uapi/asm/ptrace.h>

#include <uapi/asm/sigcontext.h>

#ifdef CONFIG_32BIT

#define TASK_SIZE	0x80000000UL

#define TASK_SIZE_MIN	TASK_SIZE

#define STACK_TOP_MAX	TASK_SIZE

#define TASK_IS_32BIT_ADDR 1

#endif

#ifdef CONFIG_64BIT

#define TASK_SIZE32	0x100000000UL

#define TASK_SIZE64     (0x1UL << ((cpu_vabits > VA_BITS) ? VA_BITS : cpu_vabits))

#define TASK_SIZE	(test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)

#define TASK_SIZE_MIN	TASK_SIZE32

#define STACK_TOP_MAX	TASK_SIZE64

#define TASK_SIZE_OF(tsk)						\

	(test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)

#define TASK_IS_32BIT_ADDR test_thread_flag(TIF_32BIT_ADDR)

#endif

#define VDSO_RANDOMIZE_SIZE	(TASK_IS_32BIT_ADDR ? SZ_1M : SZ_64M)

unsigned long stack_top(void);

#define STACK_TOP stack_top()

/*

 * This decides where the kernel will search for a free chunk of vm

 * space during mmap's.

 */

#define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE / 3)

#define FPU_REG_WIDTH		256

#define FPU_ALIGN		__attribute__((aligned(32)))

union fpureg {

	__u32	val32[FPU_REG_WIDTH / 32];

	__u64	val64[FPU_REG_WIDTH / 64];

};

#define FPR_IDX(width, idx)	(idx)

#define BUILD_FPR_ACCESS(width) \

static inline u##width get_fpr##width(union fpureg *fpr, unsigned idx)	\

{									\

	return fpr->val##width[FPR_IDX(width, idx)];			\

}									\

									\

static inline void set_fpr##width(union fpureg *fpr, unsigned int idx,	\

				  u##width val)				\

{									\

	fpr->val##width[FPR_IDX(width, idx)] = val;			\

}

BUILD_FPR_ACCESS(32)

BUILD_FPR_ACCESS(64)

struct loongarch_fpu {

	unsigned int	fcsr;

	unsigned int	vcsr;

	uint64_t	fcc;	/* 8x8 */

	union fpureg	fpr[NUM_FPU_REGS];

};

#define INIT_CPUMASK { \

	{0,} \

}

#define ARCH_MIN_TASKALIGN	32

struct loongarch_vdso_info;

/*

 * If you change thread_struct remember to change the #defines below too!

 */

struct thread_struct {

	/* Main processor registers. */

	unsigned long reg01, reg03, reg22; /* ra sp fp */

	unsigned long reg23, reg24, reg25, reg26; /* s0-s3 */

	unsigned long reg27, reg28, reg29, reg30, reg31; /* s4-s8 */

	/* CSR registers */

	unsigned long csr_prmd;

	unsigned long csr_crmd;

	unsigned long csr_euen;

	unsigned long csr_ecfg;

	unsigned long csr_badvaddr;	/* Last user fault */

	/* Scratch registers */

	unsigned long scr0;

	unsigned long scr1;

	unsigned long scr2;

	unsigned long scr3;

	/* Eflags register */

	unsigned long eflags;

	/* Other stuff associated with the thread. */

	unsigned long trap_nr;

	unsigned long error_code;

	struct loongarch_vdso_info *vdso;

	/*

	 * FPU & vector registers, must be at last because

	 * they are conditionally copied at fork().

	 */

	struct loongarch_fpu fpu FPU_ALIGN;

};

#define INIT_THREAD  {						\

	/*							\

	 * Main processor registers				\

	 */							\

	.reg01			= 0,				\

	.reg03			= 0,				\

	.reg22			= 0,				\

	.reg23			= 0,				\

	.reg24			= 0,				\

	.reg25			= 0,				\

	.reg26			= 0,				\

	.reg27			= 0,				\

	.reg28			= 0,				\

	.reg29			= 0,				\

	.reg30			= 0,				\

	.reg31			= 0,				\

	.csr_crmd		= 0,				\

	.csr_prmd		= 0,				\

	.csr_euen		= 0,				\

	.csr_ecfg		= 0,				\

	.csr_badvaddr		= 0,				\

	/*							\

	 * Other stuff associated with the process		\

	 */							\

	.trap_nr		= 0,				\

	.error_code		= 0,				\

	/*							\

	 * FPU & vector registers				\

	 */							\

	.fpu			= {				\

		.fcsr		= 0,				\

		.vcsr		= 0,				\

		.fcc		= 0,				\

		.fpr		= {{{0,},},},			\

	},							\

}

struct task_struct;

/* Free all resources held by a thread. */

#define release_thread(thread) do { } while (0)

enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_HALT, IDLE_NOMWAIT, IDLE_POLL};

extern unsigned long		boot_option_idle_override;

/*

 * Do necessary setup to start up a newly executed thread.

 */

extern void start_thread(struct pt_regs *regs, unsigned long pc, unsigned long sp);

static inline void flush_thread(void)

{

}

unsigned long __get_wchan(struct task_struct *p);

#define __KSTK_TOS(tsk) ((unsigned long)task_stack_page(tsk) + \

			 THREAD_SIZE - 32 - sizeof(struct pt_regs))

#define task_pt_regs(tsk) ((struct pt_regs *)__KSTK_TOS(tsk))

#define KSTK_EIP(tsk) (task_pt_regs(tsk)->csr_era)

#define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[3])

#define KSTK_EUEN(tsk) (task_pt_regs(tsk)->csr_euen)

#define KSTK_ECFG(tsk) (task_pt_regs(tsk)->csr_ecfg)

#define return_address() ({__asm__ __volatile__("":::"$1"); __builtin_return_address(0);})

#ifdef CONFIG_CPU_HAS_PREFETCH

#define ARCH_HAS_PREFETCH

#define prefetch(x) __builtin_prefetch((x), 0, 1)

#define ARCH_HAS_PREFETCHW

#define prefetchw(x) __builtin_prefetch((x), 1, 1)

#endif

#endif /* _ASM_PROCESSOR_H */