Unverified Commit 096b524a authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
Browse files

!3045 crypto: hisilicon/zip - add zip comp high perf mode configuration 

Merge Pull Request from: @xiao_jiang_shui 
 
* 1. add zip comp high perf mode configuration
* 2. some bugfix and cleanup of round qm and sgl
issue: https://gitee.com/openeuler/kernel/issues/I8IVG6 
 
Link:https://gitee.com/openeuler/kernel/pulls/3045

 

Reviewed-by: default avatarYang Shen <shenyang39@huawei.com>
Signed-off-by: default avatarJialin Zhang <zhangjialin11@huawei.com>
parents b57e8bb1 60a0423a

Documentation/ABI/testing/debugfs-hisi-hpre

+1 −1
Original line number Diff line number Diff line
@@ -91,7 +91,7 @@ What: /sys/kernel/debug/hisi_hpre/<bdf>/qm/status 
Date:           Apr 2020

Contact:        linux-crypto@vger.kernel.org

Description:    Dump the status of the QM.

		Four states: initiated, started, stopped and closed.

		Two states: work, stop.

		Available for both PF and VF, and take no other effect on HPRE.



What:		/sys/kernel/debug/hisi_hpre/<bdf>/qm/dev_timeout

Documentation/ABI/testing/debugfs-hisi-sec

+1 −1
Original line number Diff line number Diff line
@@ -71,7 +71,7 @@ What: /sys/kernel/debug/hisi_sec2/<bdf>/qm/status 
Date:           Apr 2020

Contact:        linux-crypto@vger.kernel.org

Description:    Dump the status of the QM.

		Four states: initiated, started, stopped and closed.

		Two states: work, stop.

		Available for both PF and VF, and take no other effect on SEC.



What:		/sys/kernel/debug/hisi_sec2/<bdf>/qm/dev_timeout

Documentation/ABI/testing/debugfs-hisi-zip

+1 −1
Original line number Diff line number Diff line
@@ -84,7 +84,7 @@ What: /sys/kernel/debug/hisi_zip/<bdf>/qm/status 
Date:           Apr 2020

Contact:        linux-crypto@vger.kernel.org

Description:    Dump the status of the QM.

		Four states: initiated, started, stopped and closed.

		Two states: work, stop.

		Available for both PF and VF, and take no other effect on ZIP.



What:		/sys/kernel/debug/hisi_zip/<bdf>/qm/dev_timeout

drivers/crypto/hisilicon/debugfs.c

+29 −25
Original line number Diff line number Diff line
@@ -31,6 +31,10 @@ static const char * const qm_debug_file_name[] = { 
	[CLEAR_ENABLE] = "clear_enable",

};



static const char * const qm_s[] = {

	"work", "stop",

};



struct qm_dfx_item {

	const char *name;

	u32 offset;
@@ -53,34 +57,34 @@ static struct qm_dfx_item qm_dfx_files[] = { 
#define CNT_CYC_REGS_NUM		10

static const struct debugfs_reg32 qm_dfx_regs[] = {

	/* XXX_CNT are reading clear register */

	{"QM_ECC_1BIT_CNT               ",  0x104000ull},

	{"QM_ECC_MBIT_CNT               ",  0x104008ull},

	{"QM_DFX_MB_CNT                 ",  0x104018ull},

	{"QM_DFX_DB_CNT                 ",  0x104028ull},

	{"QM_DFX_SQE_CNT                ",  0x104038ull},

	{"QM_DFX_CQE_CNT                ",  0x104048ull},

	{"QM_DFX_SEND_SQE_TO_ACC_CNT    ",  0x104050ull},

	{"QM_DFX_WB_SQE_FROM_ACC_CNT    ",  0x104058ull},

	{"QM_DFX_ACC_FINISH_CNT         ",  0x104060ull},

	{"QM_DFX_CQE_ERR_CNT            ",  0x1040b4ull},

	{"QM_DFX_FUNS_ACTIVE_ST         ",  0x200ull},

	{"QM_ECC_1BIT_INF               ",  0x104004ull},

	{"QM_ECC_MBIT_INF               ",  0x10400cull},

	{"QM_DFX_ACC_RDY_VLD0           ",  0x1040a0ull},

	{"QM_DFX_ACC_RDY_VLD1           ",  0x1040a4ull},

	{"QM_DFX_AXI_RDY_VLD            ",  0x1040a8ull},

	{"QM_DFX_FF_ST0                 ",  0x1040c8ull},

	{"QM_DFX_FF_ST1                 ",  0x1040ccull},

	{"QM_DFX_FF_ST2                 ",  0x1040d0ull},

	{"QM_DFX_FF_ST3                 ",  0x1040d4ull},

	{"QM_DFX_FF_ST4                 ",  0x1040d8ull},

	{"QM_DFX_FF_ST5                 ",  0x1040dcull},

	{"QM_DFX_FF_ST6                 ",  0x1040e0ull},

	{"QM_IN_IDLE_ST                 ",  0x1040e4ull},

	{"QM_ECC_1BIT_CNT               ",  0x104000},

	{"QM_ECC_MBIT_CNT               ",  0x104008},

	{"QM_DFX_MB_CNT                 ",  0x104018},

	{"QM_DFX_DB_CNT                 ",  0x104028},

	{"QM_DFX_SQE_CNT                ",  0x104038},

	{"QM_DFX_CQE_CNT                ",  0x104048},

	{"QM_DFX_SEND_SQE_TO_ACC_CNT    ",  0x104050},

	{"QM_DFX_WB_SQE_FROM_ACC_CNT    ",  0x104058},

	{"QM_DFX_ACC_FINISH_CNT         ",  0x104060},

	{"QM_DFX_CQE_ERR_CNT            ",  0x1040b4},

	{"QM_DFX_FUNS_ACTIVE_ST         ",  0x200},

	{"QM_ECC_1BIT_INF               ",  0x104004},

	{"QM_ECC_MBIT_INF               ",  0x10400c},

	{"QM_DFX_ACC_RDY_VLD0           ",  0x1040a0},

	{"QM_DFX_ACC_RDY_VLD1           ",  0x1040a4},

	{"QM_DFX_AXI_RDY_VLD            ",  0x1040a8},

	{"QM_DFX_FF_ST0                 ",  0x1040c8},

	{"QM_DFX_FF_ST1                 ",  0x1040cc},

	{"QM_DFX_FF_ST2                 ",  0x1040d0},

	{"QM_DFX_FF_ST3                 ",  0x1040d4},

	{"QM_DFX_FF_ST4                 ",  0x1040d8},

	{"QM_DFX_FF_ST5                 ",  0x1040dc},

	{"QM_DFX_FF_ST6                 ",  0x1040e0},

	{"QM_IN_IDLE_ST                 ",  0x1040e4},

};



static const struct debugfs_reg32 qm_vf_dfx_regs[] = {

	{"QM_DFX_FUNS_ACTIVE_ST         ",  0x200ull},

	{"QM_DFX_FUNS_ACTIVE_ST         ",  0x200},

};



/* define the QM's dfx regs region and region length */

drivers/crypto/hisilicon/qm.c

+42 −121
Original line number Diff line number Diff line
@@ -131,16 +131,21 @@ 
#define QM_FIFO_OVERFLOW_TYPE		0xc0

#define QM_FIFO_OVERFLOW_TYPE_SHIFT	6

#define QM_FIFO_OVERFLOW_VF		0x3f

#define QM_FIFO_OVERFLOW_QP_SHIFT	16

#define QM_ABNORMAL_INF01		0x100014

#define QM_DB_TIMEOUT_TYPE		0xc0

#define QM_DB_TIMEOUT_TYPE_SHIFT	6

#define QM_DB_TIMEOUT_VF		0x3f

#define QM_DB_TIMEOUT_QP_SHIFT		16

#define QM_ABNORMAL_INF02		0x100018

#define QM_AXI_POISON_ERR		BIT(22)

#define QM_RAS_CE_ENABLE		0x1000ec

#define QM_RAS_FE_ENABLE		0x1000f0

#define QM_RAS_NFE_ENABLE		0x1000f4

#define QM_RAS_CE_THRESHOLD		0x1000f8

#define QM_RAS_CE_TIMES_PER_IRQ		1

#define QM_OOO_SHUTDOWN_SEL		0x1040f8

#define QM_AXI_RRESP_ERR		BIT(0)

#define QM_ECC_MBIT			BIT(2)

#define QM_DB_TIMEOUT			BIT(10)

#define QM_OF_FIFO_OF			BIT(11)
@@ -403,7 +408,6 @@ static const struct hisi_qm_hw_error qm_hw_error[] = { 
	{ .int_msk = BIT(12), .msg = "qm_db_random_invalid" },

	{ .int_msk = BIT(13), .msg = "qm_mailbox_timeout" },

	{ .int_msk = BIT(14), .msg = "qm_flr_timeout" },

	{ /* sentinel */ }

};



static const char * const qm_db_timeout[] = {
@@ -414,10 +418,6 @@ static const char * const qm_fifo_overflow[] = { 
	"cq", "eq", "aeq",

};



static const char * const qp_s[] = {

	"none", "init", "start", "stop", "close",

};



struct qm_typical_qos_table {

	u32 start;

	u32 end;
@@ -445,85 +445,6 @@ static struct qm_typical_qos_table shaper_cbs_s[] = { 


static void qm_irqs_unregister(struct hisi_qm *qm);



static bool qm_avail_state(struct hisi_qm *qm, enum qm_state new)

{

	enum qm_state curr = atomic_read(&qm->status.flags);

	bool avail = false;



	switch (curr) {

	case QM_INIT:

		if (new == QM_START || new == QM_CLOSE)

			avail = true;

		break;

	case QM_START:

		if (new == QM_STOP)

			avail = true;

		break;

	case QM_STOP:

		if (new == QM_CLOSE || new == QM_START)

			avail = true;

		break;

	default:

		break;

	}



	dev_dbg(&qm->pdev->dev, "change qm state from %s to %s\n",

		qm_s[curr], qm_s[new]);



	if (!avail)

		dev_warn(&qm->pdev->dev, "Can not change qm state from %s to %s\n",

			 qm_s[curr], qm_s[new]);



	return avail;

}



static bool qm_qp_avail_state(struct hisi_qm *qm, struct hisi_qp *qp,

			      enum qp_state new)

{

	enum qm_state qm_curr = atomic_read(&qm->status.flags);

	enum qp_state qp_curr = 0;

	bool avail = false;



	if (qp)

		qp_curr = atomic_read(&qp->qp_status.flags);



	switch (new) {

	case QP_INIT:

		if (qm_curr == QM_START || qm_curr == QM_INIT)

			avail = true;

		break;

	case QP_START:

		if ((qm_curr == QM_START && qp_curr == QP_INIT) ||

		    (qm_curr == QM_START && qp_curr == QP_STOP))

			avail = true;

		break;

	case QP_STOP:

		if ((qm_curr == QM_START && qp_curr == QP_START) ||

		    (qp_curr == QP_INIT))

			avail = true;

		break;

	case QP_CLOSE:

		if ((qm_curr == QM_START && qp_curr == QP_INIT) ||

		    (qm_curr == QM_START && qp_curr == QP_STOP) ||

		    (qm_curr == QM_STOP && qp_curr == QP_STOP)  ||

		    (qm_curr == QM_STOP && qp_curr == QP_INIT))

			avail = true;

		break;

	default:

		break;

	}



	dev_dbg(&qm->pdev->dev, "change qp state from %s to %s in QM %s\n",

		qp_s[qp_curr], qp_s[new], qm_s[qm_curr]);



	if (!avail)

		dev_warn(&qm->pdev->dev,

			 "Can not change qp state from %s to %s in QM %s\n",

			 qp_s[qp_curr], qp_s[new], qm_s[qm_curr]);



	return avail;

}



static u32 qm_get_hw_error_status(struct hisi_qm *qm)

{

	return readl(qm->io_base + QM_ABNORMAL_INT_STATUS);
@@ -1538,7 +1459,7 @@ static void qm_log_hw_error(struct hisi_qm *qm, u32 error_status) 
{

	const struct hisi_qm_hw_error *err;

	struct device *dev = &qm->pdev->dev;

	u32 reg_val, type, vf_num;

	u32 reg_val, type, vf_num, qp_id;

	int i;



	for (i = 0; i < ARRAY_SIZE(qm_hw_error); i++) {
@@ -1554,19 +1475,24 @@ static void qm_log_hw_error(struct hisi_qm *qm, u32 error_status) 
			type = (reg_val & QM_DB_TIMEOUT_TYPE) >>

			       QM_DB_TIMEOUT_TYPE_SHIFT;

			vf_num = reg_val & QM_DB_TIMEOUT_VF;

			dev_err(dev, "qm %s doorbell timeout in function %u\n",

				qm_db_timeout[type], vf_num);

			qp_id = reg_val >> QM_DB_TIMEOUT_QP_SHIFT;

			dev_err(dev, "qm %s doorbell timeout in function %u qp %u\n",

				qm_db_timeout[type], vf_num, qp_id);

		} else if (err->int_msk & QM_OF_FIFO_OF) {

			reg_val = readl(qm->io_base + QM_ABNORMAL_INF00);

			type = (reg_val & QM_FIFO_OVERFLOW_TYPE) >>

			       QM_FIFO_OVERFLOW_TYPE_SHIFT;

			vf_num = reg_val & QM_FIFO_OVERFLOW_VF;



			qp_id = reg_val >> QM_FIFO_OVERFLOW_QP_SHIFT;

			if (type < ARRAY_SIZE(qm_fifo_overflow))

				dev_err(dev, "qm %s fifo overflow in function %u\n",

					qm_fifo_overflow[type], vf_num);

				dev_err(dev, "qm %s fifo overflow in function %u qp %u\n",

					qm_fifo_overflow[type], vf_num, qp_id);

			else

				dev_err(dev, "unknown error type\n");

		} else if (err->int_msk & QM_AXI_RRESP_ERR) {

			reg_val = readl(qm->io_base + QM_ABNORMAL_INF02);

			if (reg_val & QM_AXI_POISON_ERR)

				dev_err(dev, "qm axi poison error happened\n");

		}

	}

}
@@ -1969,8 +1895,10 @@ static struct hisi_qp *qm_create_qp_nolock(struct hisi_qm *qm, u8 alg_type) 
	struct hisi_qp *qp;

	int qp_id;



	if (!qm_qp_avail_state(qm, NULL, QP_INIT))

	if (atomic_read(&qm->status.flags) == QM_STOP) {

		dev_info_ratelimited(dev, "failed to create qp as qm is stop!\n");

		return ERR_PTR(-EPERM);

	}



	if (qm->qp_in_used == qm->qp_num) {

		dev_info_ratelimited(dev, "All %u queues of QM are busy!\n",
@@ -1997,7 +1925,6 @@ static struct hisi_qp *qm_create_qp_nolock(struct hisi_qm *qm, u8 alg_type) 
	qp->alg_type = alg_type;

	qp->is_in_kernel = true;

	qm->qp_in_used++;

	atomic_set(&qp->qp_status.flags, QP_INIT);



	return qp;

}
@@ -2040,11 +1967,6 @@ static void hisi_qm_release_qp(struct hisi_qp *qp) 


	down_write(&qm->qps_lock);



	if (!qm_qp_avail_state(qm, qp, QP_CLOSE)) {

		up_write(&qm->qps_lock);

		return;

	}



	qm->qp_in_used--;

	idr_remove(&qm->qp_idr, qp->qp_id);
@@ -2096,6 +2018,11 @@ static int qm_cq_ctx_cfg(struct hisi_qp *qp, int qp_id, u32 pasid) 
		cqc.dw3 = cpu_to_le32(QM_MK_CQC_DW3_V2(QM_QC_CQE_SIZE, qp->cq_depth));

		cqc.w8 = 0; /* rand_qc */

	}

	/*

	 * Enable request finishing interrupts defaultly.

	 * So, there will be some interrupts until disabling

	 * this.

	 */

	cqc.dw6 = cpu_to_le32(1 << QM_CQ_PHASE_SHIFT | 1 << QM_CQ_FLAG_SHIFT);

	cqc.base_l = cpu_to_le32(lower_32_bits(qp->cqe_dma));

	cqc.base_h = cpu_to_le32(upper_32_bits(qp->cqe_dma));
@@ -2128,8 +2055,10 @@ static int qm_start_qp_nolock(struct hisi_qp *qp, unsigned long arg) 
	u32 pasid = arg;

	int ret;



	if (!qm_qp_avail_state(qm, qp, QP_START))

	if (atomic_read(&qm->status.flags) == QM_STOP) {

		dev_info_ratelimited(dev, "failed to start qp as qm is stop!\n");

		return -EPERM;

	}



	ret = qm_qp_ctx_cfg(qp, qp_id, pasid);

	if (ret)
@@ -2276,21 +2205,17 @@ static int qm_stop_qp_nolock(struct hisi_qp *qp) 
	 * is_resetting flag should be set negative so that this qp will not

	 * be restarted after reset.

	 */

	if (atomic_read(&qp->qp_status.flags) == QP_STOP) {

	if (atomic_read(&qp->qp_status.flags) != QP_START) {

		qp->is_resetting = false;

		return 0;

	}



	if (!qm_qp_avail_state(qp->qm, qp, QP_STOP))

		return -EPERM;



	atomic_set(&qp->qp_status.flags, QP_STOP);



	ret = qm_drain_qp(qp);

	if (ret)

		dev_err(dev, "Failed to drain out data for stopping!\n");





	flush_workqueue(qp->qm->wq);

	if (unlikely(qp->is_resetting && atomic_read(&qp->qp_status.used)))

		qp_stop_fail_cb(qp);
@@ -3098,13 +3023,8 @@ void hisi_qm_uninit(struct hisi_qm *qm) 
{

	qm_cmd_uninit(qm);

	hisi_qm_unint_work(qm);

	down_write(&qm->qps_lock);



	if (!qm_avail_state(qm, QM_CLOSE)) {

		up_write(&qm->qps_lock);

		return;

	}



	down_write(&qm->qps_lock);

	hisi_qm_memory_uninit(qm);

	hisi_qm_set_state(qm, QM_NOT_READY);

	up_write(&qm->qps_lock);
@@ -3275,11 +3195,6 @@ int hisi_qm_start(struct hisi_qm *qm) 


	down_write(&qm->qps_lock);



	if (!qm_avail_state(qm, QM_START)) {

		up_write(&qm->qps_lock);

		return -EPERM;

	}



	dev_dbg(dev, "qm start with %u queue pairs\n", qm->qp_num);



	if (!qm->qp_num) {
@@ -3289,10 +3204,12 @@ int hisi_qm_start(struct hisi_qm *qm) 
	}



	ret = __hisi_qm_start(qm);

	if (!ret)

		atomic_set(&qm->status.flags, QM_START);

	if (ret)

		goto err_unlock;



	atomic_set(&qm->status.flags, QM_WORK);

	hisi_qm_set_state(qm, QM_READY);



err_unlock:

	up_write(&qm->qps_lock);

	return ret;
@@ -3389,10 +3306,11 @@ int hisi_qm_stop(struct hisi_qm *qm, enum qm_stop_reason r) 
	down_write(&qm->qps_lock);



	qm->status.stop_reason = r;

	if (!qm_avail_state(qm, QM_STOP)) {

		ret = -EPERM;

	if (atomic_read(&qm->status.flags) == QM_STOP)

		goto err_unlock;

	}



	/* Stop all the request sending at first. */

	atomic_set(&qm->status.flags, QM_STOP);



	if (qm->status.stop_reason == QM_SOFT_RESET ||

	    qm->status.stop_reason == QM_DOWN) {
@@ -3416,7 +3334,6 @@ int hisi_qm_stop(struct hisi_qm *qm, enum qm_stop_reason r) 
	}



	qm_clear_queues(qm);

	atomic_set(&qm->status.flags, QM_STOP);



err_unlock:

	up_write(&qm->qps_lock);
@@ -4227,6 +4144,11 @@ static int qm_set_vf_mse(struct hisi_qm *qm, bool set) 
	int pos;

	int i;



	/*

	 * Since function qm_set_vf_mse is called only after SRIOV is enabled,

	 * pci_find_ext_capability cannot return 0, pos does not need to be

	 * checked.

	 */

	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);

	pci_read_config_word(pdev, pos + PCI_SRIOV_CTRL, &sriov_ctrl);

	if (set)
@@ -5648,7 +5570,6 @@ int hisi_qm_init(struct hisi_qm *qm) 
		goto err_free_qm_memory;



	qm_cmd_init(qm);

	atomic_set(&qm->status.flags, QM_INIT);



	return 0;