Commit 60a0423a authored by Weili Qian's avatar Weili Qian Committed by JiangShui
Browse files

crypto: hisilicon/qm - add comments and remove redundant 

driver inclusion
category: cleanup
bugzilla: https://gitee.com/openeuler/kernel/issues/I8IVG6


CVE: NA

----------------------------------------------------------------------

1. Remove redundant array element, prevent the size obtained by
ARRAY_SIZE() from qm_log_hw_error is greater than actual size.
2. Add comments in function qm_set_vf_mse() and qm_cq_ctx_cfg()
to make it easier to understand.

Signed-off-by: default avatarWeili Qian <qianweili@huawei.com>
Signed-off-by: default avatarJiangShui Yang <yangjiangshui@h-partners.com>
parent f2d1b956

drivers/crypto/hisilicon/qm.c

+10 −1
Original line number Diff line number Diff line
@@ -408,7 +408,6 @@ static const struct hisi_qm_hw_error qm_hw_error[] = { 
	{ .int_msk = BIT(12), .msg = "qm_db_random_invalid" },

	{ .int_msk = BIT(13), .msg = "qm_mailbox_timeout" },

	{ .int_msk = BIT(14), .msg = "qm_flr_timeout" },

	{ /* sentinel */ }

};



static const char * const qm_db_timeout[] = {
@@ -2019,6 +2018,11 @@ static int qm_cq_ctx_cfg(struct hisi_qp *qp, int qp_id, u32 pasid) 
		cqc.dw3 = cpu_to_le32(QM_MK_CQC_DW3_V2(QM_QC_CQE_SIZE, qp->cq_depth));

		cqc.w8 = 0; /* rand_qc */

	}

	/*

	 * Enable request finishing interrupts defaultly.

	 * So, there will be some interrupts until disabling

	 * this.

	 */

	cqc.dw6 = cpu_to_le32(1 << QM_CQ_PHASE_SHIFT | 1 << QM_CQ_FLAG_SHIFT);

	cqc.base_l = cpu_to_le32(lower_32_bits(qp->cqe_dma));

	cqc.base_h = cpu_to_le32(upper_32_bits(qp->cqe_dma));
@@ -4140,6 +4144,11 @@ static int qm_set_vf_mse(struct hisi_qm *qm, bool set) 
	int pos;

	int i;



	/*

	 * Since function qm_set_vf_mse is called only after SRIOV is enabled,

	 * pci_find_ext_capability cannot return 0, pos does not need to be

	 * checked.

	 */

	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);

	pci_read_config_word(pdev, pos + PCI_SRIOV_CTRL, &sriov_ctrl);

	if (set)