arm64: tlb: Adjust stride and type of TLBI according to mmu_gather

mainline inclusion
from mainline-4.20-rc1
commit: f270ab88
category: feature
feature: Reduce synchronous TLB invalidation on ARM64
bugzilla: NA
CVE: NA

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Now that the core mmu_gather code keeps track of both the levels of page
table cleared and also whether or not these entries correspond to
intermediate entries, we can use this in our tlb_flush() callback to
reduce the number of invalidations we issue as well as their scope.

Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Hanjun Guo <guohanjun@huawei.com>
Reviewed-by: Xuefeng Wang <wxf.wang@hisilicon.com>
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>