Commit 08b6e172 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/gfx9: move update_spm_vmid() out of rlc_init() 



rlc_init() is part of sw_init() so it should not touch hardware.
Additionally, calling the rlc update_spm_vmid() callback
directly invokes a gfx on/off cycle which could result in
powergating being enabled before hw init is complete.  Split
update_spm_vmid() into an internal implementation for local
use without gfxoff interaction and then the rlc callback
which includes gfxoff handling.  lbpw_init also touches
hardware so mvoe that to rlc_resume as well.

Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 6dda3f18

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+15 −19
Original line number Diff line number Diff line
@@ -762,6 +762,8 @@ static void gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev, 
static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev,

				     void *inject_if, uint32_t instance_mask);

static void gfx_v9_0_reset_ras_error_count(struct amdgpu_device *adev);

static void gfx_v9_0_update_spm_vmid_internal(struct amdgpu_device *adev,

					      unsigned int vmid);



static void gfx_v9_0_kiq_set_resources(struct amdgpu_ring *kiq_ring,

				uint64_t queue_mask)
@@ -1667,22 +1669,6 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device *adev) 
			return r;

	}



	switch (adev->ip_versions[GC_HWIP][0]) {

	case IP_VERSION(9, 2, 2):

	case IP_VERSION(9, 1, 0):

		gfx_v9_0_init_lbpw(adev);

		break;

	case IP_VERSION(9, 4, 0):

		gfx_v9_4_init_lbpw(adev);

		break;

	default:

		break;

	}



	/* init spm vmid with 0xf */

	if (adev->gfx.rlc.funcs->update_spm_vmid)

		adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);



	return 0;

}
@@ -2942,12 +2928,14 @@ static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev) 
	switch (adev->ip_versions[GC_HWIP][0]) {

	case IP_VERSION(9, 2, 2):

	case IP_VERSION(9, 1, 0):

		gfx_v9_0_init_lbpw(adev);

		if (amdgpu_lbpw == 0)

			gfx_v9_0_enable_lbpw(adev, false);

		else

			gfx_v9_0_enable_lbpw(adev, true);

		break;

	case IP_VERSION(9, 4, 0):

		gfx_v9_4_init_lbpw(adev);

		if (amdgpu_lbpw > 0)

			gfx_v9_0_enable_lbpw(adev, true);

		else
@@ -2957,6 +2945,8 @@ static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev) 
		break;

	}



	gfx_v9_0_update_spm_vmid_internal(adev, 0xf);



	adev->gfx.rlc.funcs->start(adev);



	return 0;
@@ -4881,12 +4871,11 @@ static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev, 
	return 0;

}



static void gfx_v9_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)

static void gfx_v9_0_update_spm_vmid_internal(struct amdgpu_device *adev,

					      unsigned int vmid)

{

	u32 reg, data;



	amdgpu_gfx_off_ctrl(adev, false);



	reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);

	if (amdgpu_sriov_is_pp_one_vf(adev))

		data = RREG32_NO_KIQ(reg);
@@ -4900,6 +4889,13 @@ static void gfx_v9_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) 
		WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);

	else

		WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);

}



static void gfx_v9_0_update_spm_vmid(struct amdgpu_device *adev, unsigned int vmid)

{

	amdgpu_gfx_off_ctrl(adev, false);



	gfx_v9_0_update_spm_vmid_internal(adev, vmid);



	amdgpu_gfx_off_ctrl(adev, true);

}