Commit 6dda3f18 authored by Srinivasan Shanmugam's avatar Srinivasan Shanmugam Committed by Alex Deucher
Browse files

drm/amdgpu: Fix errors & warnings in gfx_v10_0.c 



Fix the below checkpatch errors & warnings:

ERROR: that open brace { should be on the previous line
ERROR: space prohibited before that ',' (ctx:WxV)
ERROR: space required after that ',' (ctx:WxV)
ERROR: code indent should use tabs where possible
ERROR: switch and case should be at the same indent

WARNING: please, no spaces at the start of a line
WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
WARNING: space prohibited before semicolon
WARNING: Block comments use a trailing */ on a separate line
WARNING: Block comments use * on subsequent lines
WARNING: braces {} are not necessary for any arm of this statement
WARNING: Missing a blank line after declarations

Cc: Christian König <christian.koenig@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarSrinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent fe018cf2

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+81 −87
Original line number Diff line number Diff line
@@ -271,8 +271,7 @@ MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin"); 
MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin");

MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin");



static const struct soc15_reg_golden golden_settings_gc_10_1[] =

{

static const struct soc15_reg_golden golden_settings_gc_10_1[] = {

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
@@ -315,13 +314,11 @@ static const struct soc15_reg_golden golden_settings_gc_10_1[] = 
	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)

};



static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] =

{

static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] = {

	/* Pending on emulation bring up */

};



static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] =

{

static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] = {

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
@@ -1376,8 +1373,7 @@ static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] = 
	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)

};



static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =

{

static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = {

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
@@ -1418,8 +1414,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = 
	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),

};



static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =

{

static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = {

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
@@ -1464,13 +1459,11 @@ static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = 
	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000)

};



static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =

{

static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = {

	/* Pending on emulation bring up */

};



static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] =

{

static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] = {

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
@@ -2093,13 +2086,11 @@ static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] = 
	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)

};



static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] =

{

static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] = {

	/* Pending on emulation bring up */

};



static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] =

{

static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] = {

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
@@ -3154,8 +3145,7 @@ static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] = 
	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)

};



static const struct soc15_reg_golden golden_settings_gc_10_3[] =

{

static const struct soc15_reg_golden golden_settings_gc_10_3[] = {

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
@@ -3201,13 +3191,11 @@ static const struct soc15_reg_golden golden_settings_gc_10_3[] = 
	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)

};



static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] =

{

static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] = {

	/* Pending on emulation bring up */

};



static const struct soc15_reg_golden golden_settings_gc_10_3_2[] =

{

static const struct soc15_reg_golden golden_settings_gc_10_3_2[] = {

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
@@ -3254,8 +3242,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_3_2[] = 
	SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),

};



static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] =

{

static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] = {

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
@@ -3285,8 +3272,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] = 
	SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),

};



static const struct soc15_reg_golden golden_settings_gc_10_3_3[] =

{

static const struct soc15_reg_golden golden_settings_gc_10_3_3[] = {

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
@@ -3309,8 +3295,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_3_3[] = 
	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)

};



static const struct soc15_reg_golden golden_settings_gc_10_3_4[] =

{

static const struct soc15_reg_golden golden_settings_gc_10_3_4[] = {

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100),
@@ -3421,8 +3406,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_0_cyan_skillfish[] = 
	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000)

};



static const struct soc15_reg_golden golden_settings_gc_10_3_6[] =

{

static const struct soc15_reg_golden golden_settings_gc_10_3_6[] = {

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x00000044),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
@@ -3782,7 +3766,7 @@ static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring) 
	struct amdgpu_device *adev = ring->adev;

	uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);

	uint32_t tmp = 0;

	unsigned i;

	unsigned int i;

	int r;



	WREG32(scratch, 0xCAFEDEAD);
@@ -3820,7 +3804,7 @@ static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 
	struct amdgpu_device *adev = ring->adev;

	struct amdgpu_ib ib;

	struct dma_fence *f = NULL;

	unsigned index;

	unsigned int index;

	uint64_t gpu_addr;

	volatile uint32_t *cpu_ptr;

	long r;
@@ -4213,7 +4197,7 @@ static int gfx_v10_0_mec_init(struct amdgpu_device *adev) 
	int r;

	u32 *hpd;

	const __le32 *fw_data = NULL;

	unsigned fw_size;

	unsigned int fw_size;

	u32 *fw = NULL;

	size_t mec_hpd_size;
@@ -4295,7 +4279,8 @@ static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id 
{

	/* in gfx10 the SIMD_ID is specified as part of the INSTANCE

	 * field when performing a select_se_sh so it should be

	 * zero here */

	 * zero here

	 */

	WARN_ON(simd != 0);



	/* type 2 wave data */
@@ -4474,7 +4459,7 @@ static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 
static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,

				       int mec, int pipe, int queue)

{

	unsigned irq_type;

	unsigned int irq_type;

	struct amdgpu_ring *ring;

	unsigned int hw_prio;
@@ -4795,7 +4780,8 @@ static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *ade 
	uint32_t pa_sc_tile_steering_override;



	/* for ASICs that integrates GFX v10.3

	 * pa_sc_tile_steering_override should be set to 0 */

	 * pa_sc_tile_steering_override should be set to 0

	 */

	if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0))

		return 0;
@@ -4871,8 +4857,10 @@ static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev) 
	nv_grbm_select(adev, 0, 0, 0, 0);

	mutex_unlock(&adev->srbm_mutex);



	/* Initialize all compute VMIDs to have no GDS, GWS, or OA

	   access. These should be enabled by FW for target VMIDs. */

	/*

	 * Initialize all compute VMIDs to have no GDS, GWS, or OA

	 * access. These should be enabled by FW for target VMIDs.

	 */

	for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {

		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);

		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
@@ -5108,8 +5096,10 @@ static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 


static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)

{

	/* TODO: enable rlc & smu handshake until smu

	 * and gfxoff feature works as expected */

	/*

	 * TODO: enable rlc & smu handshake until smu

	 * and gfxoff feature works as expected

	 */

	if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))

		gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
@@ -5132,7 +5122,7 @@ static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev) 
{

	const struct rlc_firmware_header_v2_0 *hdr;

	const __le32 *fw_data;

	unsigned i, fw_size;

	unsigned int i, fw_size;



	if (!adev->gfx.rlc_fw)

		return -EINVAL;
@@ -5674,11 +5664,10 @@ static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 
	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);

	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);



	if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) {

	if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2))

		WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);

	} else {

	else

		WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);

	}



	if (adev->job_hang && !enable)

		return 0;
@@ -5700,7 +5689,7 @@ static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 
	int r;

	const struct gfx_firmware_header_v1_0 *pfp_hdr;

	const __le32 *fw_data;

	unsigned i, fw_size;

	unsigned int i, fw_size;

	uint32_t tmp;

	uint32_t usec_timeout = 50000;  /* wait for 50ms */
@@ -5778,7 +5767,7 @@ static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev) 
	int r;

	const struct gfx_firmware_header_v1_0 *ce_hdr;

	const __le32 *fw_data;

	unsigned i, fw_size;

	unsigned int i, fw_size;

	uint32_t tmp;

	uint32_t usec_timeout = 50000;  /* wait for 50ms */
@@ -5855,7 +5844,7 @@ static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 
	int r;

	const struct gfx_firmware_header_v1_0 *me_hdr;

	const __le32 *fw_data;

	unsigned i, fw_size;

	unsigned int i, fw_size;

	uint32_t tmp;

	uint32_t usec_timeout = 50000;  /* wait for 50ms */
@@ -6243,7 +6232,7 @@ static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev) 
{

	const struct gfx_firmware_header_v1_0 *mec_hdr;

	const __le32 *fw_data;

	unsigned i;

	unsigned int i;

	u32 tmp;

	u32 usec_timeout = 50000; /* Wait for 50 ms */
@@ -6922,8 +6911,10 @@ static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev) 
{

	uint32_t data, pattern = 0xDEADBEEF;



	/* check if mmVGT_ESGS_RING_SIZE_UMD

	 * has been remapped to mmVGT_ESGS_RING_SIZE */

	/*

	 * check if mmVGT_ESGS_RING_SIZE_UMD

	 * has been remapped to mmVGT_ESGS_RING_SIZE

	 */

	switch (adev->ip_versions[GC_HWIP][0]) {

	case IP_VERSION(10, 3, 0):

	case IP_VERSION(10, 3, 2):
@@ -6967,8 +6958,10 @@ static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev) 
	if (amdgpu_sriov_vf(adev))

		return;



	/* initialize cam_index to 0

	 * index will auto-inc after each data writting */

	/*

	 * Initialize cam_index to 0

	 * index will auto-inc after each data writing

	 */

	WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);



	switch (adev->ip_versions[GC_HWIP][0]) {
@@ -7098,6 +7091,7 @@ static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev) 
static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev)

{

	uint32_t data;



	data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG);

	data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK;

	WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data);
@@ -7214,7 +7208,7 @@ static bool gfx_v10_0_is_idle(void *handle) 


static int gfx_v10_0_wait_for_idle(void *handle)

{

	unsigned i;

	unsigned int i;

	u32 tmp;

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -7469,7 +7463,7 @@ static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev) 
static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id)

{

	uint32_t data;

	unsigned i;

	unsigned int i;



	data = RLC_SAFE_MODE__CMD_MASK;

	data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
@@ -7898,7 +7892,7 @@ static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev, 
	return 0;

}



static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)

static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned int vmid)

{

	u32 reg, data;
@@ -8295,7 +8289,7 @@ static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 
				       struct amdgpu_ib *ib,

				       uint32_t flags)

{

	unsigned vmid = AMDGPU_JOB_GET_VMID(job);

	unsigned int vmid = AMDGPU_JOB_GET_VMID(job);

	u32 header, control = 0;



	if (ib->flags & AMDGPU_IB_FLAG_CE)
@@ -8336,7 +8330,7 @@ static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 
					   struct amdgpu_ib *ib,

					   uint32_t flags)

{

	unsigned vmid = AMDGPU_JOB_GET_VMID(job);

	unsigned int vmid = AMDGPU_JOB_GET_VMID(job);

	u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);



	if (ring->is_mes_queue)
@@ -8371,7 +8365,7 @@ static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 
}



static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,

				     u64 seq, unsigned flags)

				     u64 seq, unsigned int flags)

{

	bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;

	bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
@@ -8427,7 +8421,7 @@ static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 
}



static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,

					 unsigned vmid, uint64_t pd_addr)

					 unsigned int vmid, uint64_t pd_addr)

{

	if (ring->is_mes_queue)

		gfx_v10_0_ring_invalidate_tlbs(ring, 0, 0, false, 0);
@@ -8509,9 +8503,9 @@ static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 
	amdgpu_ring_write(ring, 0);

}



static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)

static unsigned int gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)

{

	unsigned ret;

	unsigned int ret;



	amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));

	amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
@@ -8523,9 +8517,10 @@ static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) 
	return ret;

}



static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)

static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned int offset)

{

	unsigned cur;

	unsigned int cur;



	BUG_ON(offset > ring->buf_mask);

	BUG_ON(ring->ring[offset] != 0x55aa55aa);
@@ -8748,7 +8743,7 @@ static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 
}



static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,

					 unsigned vmid)

					 unsigned int vmid)

{

	struct amdgpu_device *adev = ring->adev;

	uint32_t value = 0;
@@ -8857,7 +8852,7 @@ static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev 


static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,

					    struct amdgpu_irq_src *src,

					    unsigned type,

					    unsigned int type,

					    enum amdgpu_interrupt_state state)

{

	switch (type) {
@@ -8954,7 +8949,7 @@ static int gfx_v10_0_eop_irq(struct amdgpu_device *adev, 


static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,

					      struct amdgpu_irq_src *source,

					      unsigned type,

					      unsigned int type,

					      enum amdgpu_interrupt_state state)

{

	switch (state) {
@@ -8973,7 +8968,7 @@ static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 


static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,

					       struct amdgpu_irq_src *source,

					       unsigned type,

					       unsigned int type,

					       enum amdgpu_interrupt_state state)

{

	switch (state) {
@@ -9340,7 +9335,7 @@ static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev) 


static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)

{

	unsigned total_cu = adev->gfx.config.max_cu_per_sh *

	unsigned int total_cu = adev->gfx.config.max_cu_per_sh *

			    adev->gfx.config.max_sh_per_se *

			    adev->gfx.config.max_shader_engines;
@@ -9421,7 +9416,7 @@ static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 
{

	int i, j, k, counter, active_cu_number = 0;

	u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;

	unsigned disable_masks[4 * 2];

	unsigned int disable_masks[4 * 2];



	if (!adev || !cu_info)

		return -EINVAL;
@@ -9538,8 +9533,7 @@ static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev) 
		     (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT));

}



const struct amdgpu_ip_block_version gfx_v10_0_ip_block =

{

const struct amdgpu_ip_block_version gfx_v10_0_ip_block = {

	.type = AMD_IP_BLOCK_TYPE_GFX,

	.major = 10,

	.minor = 0,