Commit 07bb2e36 authored by Adam Ford's avatar Adam Ford Committed by Shawn Guo
Browse files

arm64: dts: imx8mp: Fix video clock parents 



There are a few clocks whose parents are set in mipi_dsi
and lcdif nodes, but these clocks are used by the media_blk_ctrl
power domain.  This may cause an issue when re-parenting, because
the media_blk_ctrl may start the clocks before the reparent is
done resulting in a disp_pixel clock having the wrong parent and
rate.

Fix this by moving the assigned-clock-parents and rates to the
media_blk_ctrl node to configure these clocks before they are enabled.

After this patch, both disp1_pix_root and dixp2_pix_root clock
become children of the video_pll1.

video_pll1_ref_sel           24000000
  video_pll1               1039500000
    video_pll1_bypass        1039500000
      video_pll1_out           1039500000
        media_disp2_pix          1039500000
          media_disp2_pix_root_clk   1039500000
        media_disp1_pix          1039500000
          media_disp1_pix_root_clk   1039500000

Fixes: eda09fe1 ("arm64: dts: imx8mp: Add display pipeline components")
Signed-off-by: default avatarAdam Ford <aford173@gmail.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 91aa4b37

arch/arm64/boot/dts/freescale/imx8mp.dtsi

+9 −16
Original line number Diff line number Diff line
@@ -1211,13 +1211,6 @@ 
					 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,

					 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;

				clock-names = "pix", "axi", "disp_axi";

				assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,

						  <&clk IMX8MP_CLK_MEDIA_AXI>,

						  <&clk IMX8MP_CLK_MEDIA_APB>;

				assigned-clock-parents = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>,

							 <&clk IMX8MP_SYS_PLL2_1000M>,

							 <&clk IMX8MP_SYS_PLL1_800M>;

				assigned-clock-rates = <594000000>, <500000000>, <200000000>;

				interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;

				power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_1>;

				status = "disabled";
@@ -1237,11 +1230,6 @@ 
					 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,

					 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;

				clock-names = "pix", "axi", "disp_axi";

				assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>,

						  <&clk IMX8MP_VIDEO_PLL1>;

				assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>,

							 <&clk IMX8MP_VIDEO_PLL1_REF_SEL>;

				assigned-clock-rates = <0>, <1039500000>;

				power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_2>;

				status = "disabled";
@@ -1296,11 +1284,16 @@ 
					      "disp1", "disp2", "isp", "phy";



				assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,

						  <&clk IMX8MP_CLK_MEDIA_APB>;

						  <&clk IMX8MP_CLK_MEDIA_APB>,

						  <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>,

						  <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>,

						  <&clk IMX8MP_VIDEO_PLL1>;

				assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,

							 <&clk IMX8MP_SYS_PLL1_800M>;

				assigned-clock-rates = <500000000>, <200000000>;



							 <&clk IMX8MP_SYS_PLL1_800M>,

							 <&clk IMX8MP_VIDEO_PLL1_OUT>,

							 <&clk IMX8MP_VIDEO_PLL1_OUT>;

				assigned-clock-rates = <500000000>, <200000000>,

						       <0>, <0>, <1039500000>;

				#power-domain-cells = <1>;



				lvds_bridge: bridge@5c {