Commit eda09fe1 authored by Marek Vasut's avatar Marek Vasut Committed by Shawn Guo
Browse files

arm64: dts: imx8mp: Add display pipeline components 



Add LCDIF scanout engine and DSIM bridge nodes for i.MX8M Plus.
This makes the DSI display pipeline available on this SoC.

Reviewed-by: default avatarFabio Estevam <festevam@gmail.com>
Signed-off-by: default avatarMarek Vasut <marex@denx.de>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent d825fb64

arch/arm64/boot/dts/freescale/imx8mp.dtsi

+55 −0
Original line number Diff line number Diff line
@@ -1174,6 +1174,61 @@ 
			#size-cells = <1>;

			ranges;



			mipi_dsi: dsi@32e60000 {

				compatible = "fsl,imx8mp-mipi-dsim";

				reg = <0x32e60000 0x400>;

				clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,

					 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;

				clock-names = "bus_clk", "sclk_mipi";

				assigned-clocks = <&clk IMX8MP_CLK_MEDIA_APB>,

						  <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;

				assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,

							 <&clk IMX8MP_CLK_24M>;

				assigned-clock-rates = <200000000>, <24000000>;

				samsung,pll-clock-frequency = <24000000>;

				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;

				power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_DSI_1>;

				status = "disabled";



				ports {

					#address-cells = <1>;

					#size-cells = <0>;



					port@0 {

						reg = <0>;



						dsim_from_lcdif1: endpoint {

							remote-endpoint = <&lcdif1_to_dsim>;

						};

					};

				};

			};



			lcdif1: display-controller@32e80000 {

				compatible = "fsl,imx8mp-lcdif";

				reg = <0x32e80000 0x10000>;

				clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,

					 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,

					 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;

				clock-names = "pix", "axi", "disp_axi";

				assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,

						  <&clk IMX8MP_CLK_MEDIA_AXI>,

						  <&clk IMX8MP_CLK_MEDIA_APB>;

				assigned-clock-parents = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>,

							 <&clk IMX8MP_SYS_PLL2_1000M>,

							 <&clk IMX8MP_SYS_PLL1_800M>;

				assigned-clock-rates = <594000000>, <500000000>, <200000000>;

				interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;

				power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_1>;

				status = "disabled";



				port {

					lcdif1_to_dsim: endpoint {

						remote-endpoint = <&dsim_from_lcdif1>;

					};

				};

			};



			lcdif2: display-controller@32e90000 {

				compatible = "fsl,imx8mp-lcdif";

				reg = <0x32e90000 0x238>;