Commit 07a356bb authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau/msppp: switch to instanced constructor 



Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
Reviewed-by: default avatarLyude Paul <lyude@redhat.com>
parent 96321606

drivers/gpu/drm/nouveau/include/nvkm/core/device.h

+0 −2
Original line number Diff line number Diff line
@@ -60,7 +60,6 @@ struct nvkm_device { 
		struct notifier_block nb;

	} acpi;



	struct nvkm_engine *msppp;

	struct nvkm_engine *msvld;

	struct nvkm_nvenc *nvenc[3];

	struct nvkm_nvdec *nvdec[3];
@@ -110,7 +109,6 @@ struct nvkm_device_chip { 
#undef NVKM_LAYOUT_INST

#undef NVKM_LAYOUT_ONCE



	int (*msppp   )(struct nvkm_device *, int idx, struct nvkm_engine **);

	int (*msvld   )(struct nvkm_device *, int idx, struct nvkm_engine **);

	int (*nvenc[3])(struct nvkm_device *, int idx, struct nvkm_nvenc **);

	int (*nvdec[3])(struct nvkm_device *, int idx, struct nvkm_nvdec **);

drivers/gpu/drm/nouveau/include/nvkm/core/layout.h

+1 −0
Original line number Diff line number Diff line
@@ -37,4 +37,5 @@ NVKM_LAYOUT_ONCE(NVKM_ENGINE_ME , struct nvkm_engine , me) 
NVKM_LAYOUT_ONCE(NVKM_ENGINE_MPEG    , struct nvkm_engine  ,     mpeg)

NVKM_LAYOUT_ONCE(NVKM_ENGINE_MSENC   , struct nvkm_engine  ,    msenc)

NVKM_LAYOUT_ONCE(NVKM_ENGINE_MSPDEC  , struct nvkm_engine  ,   mspdec)

NVKM_LAYOUT_ONCE(NVKM_ENGINE_MSPPP   , struct nvkm_engine  ,    msppp)

NVKM_LAYOUT_ONCE(NVKM_ENGINE_VP      , struct nvkm_engine  ,       vp)

drivers/gpu/drm/nouveau/include/nvkm/engine/msppp.h

+3 −3
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ 
#ifndef __NVKM_MSPPP_H__

#define __NVKM_MSPPP_H__

#include <engine/falcon.h>

int g98_msppp_new(struct nvkm_device *, int, struct nvkm_engine **);

int gt215_msppp_new(struct nvkm_device *, int, struct nvkm_engine **);

int gf100_msppp_new(struct nvkm_device *, int, struct nvkm_engine **);

int g98_msppp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);

int gt215_msppp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);

int gf100_msppp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);

#endif

drivers/gpu/drm/nouveau/nvkm/core/subdev.c

+0 −1
Original line number Diff line number Diff line
@@ -33,7 +33,6 @@ nvkm_subdev_type[NVKM_SUBDEV_NR] = { 
#include <core/layout.h>

#undef NVKM_LAYOUT_ONCE

#undef NVKM_LAYOUT_INST

	[NVKM_ENGINE_MSPPP   ] = "msppp",

	[NVKM_ENGINE_MSVLD   ] = "msvld",

	[NVKM_ENGINE_NVENC0  ] = "nvenc0",

	[NVKM_ENGINE_NVENC1  ] = "nvenc1",

drivers/gpu/drm/nouveau/nvkm/engine/device/base.c

+23 −24
Original line number Diff line number Diff line
@@ -1099,7 +1099,7 @@ nv98_chipset = { 
	.fifo     = { 0x00000001, g84_fifo_new },

	.gr       = { 0x00000001, g84_gr_new },

	.mspdec   = { 0x00000001, g98_mspdec_new },

	.msppp = g98_msppp_new,

	.msppp    = { 0x00000001, g98_msppp_new },

	.msvld = g98_msvld_new,

	.pm = g84_pm_new,

	.sec = g98_sec_new,
@@ -1166,7 +1166,7 @@ nva3_chipset = { 
	.gr       = { 0x00000001, gt215_gr_new },

	.mpeg     = { 0x00000001, g84_mpeg_new },

	.mspdec   = { 0x00000001, gt215_mspdec_new },

	.msppp = gt215_msppp_new,

	.msppp    = { 0x00000001, gt215_msppp_new },

	.msvld = gt215_msvld_new,

	.pm = gt215_pm_new,

	.sw = nv50_sw_new,
@@ -1199,7 +1199,7 @@ nva5_chipset = { 
	.fifo     = { 0x00000001, g84_fifo_new },

	.gr       = { 0x00000001, gt215_gr_new },

	.mspdec   = { 0x00000001, gt215_mspdec_new },

	.msppp = gt215_msppp_new,

	.msppp    = { 0x00000001, gt215_msppp_new },

	.msvld = gt215_msvld_new,

	.pm = gt215_pm_new,

	.sw = nv50_sw_new,
@@ -1232,7 +1232,7 @@ nva8_chipset = { 
	.fifo     = { 0x00000001, g84_fifo_new },

	.gr       = { 0x00000001, gt215_gr_new },

	.mspdec   = { 0x00000001, gt215_mspdec_new },

	.msppp = gt215_msppp_new,

	.msppp    = { 0x00000001, gt215_msppp_new },

	.msvld = gt215_msvld_new,

	.pm = gt215_pm_new,

	.sw = nv50_sw_new,
@@ -1263,7 +1263,7 @@ nvaa_chipset = { 
	.fifo     = { 0x00000001, g84_fifo_new },

	.gr       = { 0x00000001, gt200_gr_new },

	.mspdec   = { 0x00000001, g98_mspdec_new },

	.msppp = g98_msppp_new,

	.msppp    = { 0x00000001, g98_msppp_new },

	.msvld = g98_msvld_new,

	.pm = g84_pm_new,

	.sec = g98_sec_new,
@@ -1295,7 +1295,7 @@ nvac_chipset = { 
	.fifo     = { 0x00000001, g84_fifo_new },

	.gr       = { 0x00000001, mcp79_gr_new },

	.mspdec   = { 0x00000001, g98_mspdec_new },

	.msppp = g98_msppp_new,

	.msppp    = { 0x00000001, g98_msppp_new },

	.msvld = g98_msvld_new,

	.pm = g84_pm_new,

	.sec = g98_sec_new,
@@ -1329,7 +1329,7 @@ nvaf_chipset = { 
	.fifo     = { 0x00000001, g84_fifo_new },

	.gr       = { 0x00000001, mcp89_gr_new },

	.mspdec   = { 0x00000001, gt215_mspdec_new },

	.msppp = gt215_msppp_new,

	.msppp    = { 0x00000001, gt215_msppp_new },

	.msvld = mcp89_msvld_new,

	.pm = gt215_pm_new,

	.sw = nv50_sw_new,
@@ -1365,7 +1365,7 @@ nvc0_chipset = { 
	.fifo     = { 0x00000001, gf100_fifo_new },

	.gr       = { 0x00000001, gf100_gr_new },

	.mspdec   = { 0x00000001, gf100_mspdec_new },

	.msppp = gf100_msppp_new,

	.msppp    = { 0x00000001, gf100_msppp_new },

	.msvld = gf100_msvld_new,

	.pm = gf100_pm_new,

	.sw = gf100_sw_new,
@@ -1401,7 +1401,7 @@ nvc1_chipset = { 
	.fifo     = { 0x00000001, gf100_fifo_new },

	.gr       = { 0x00000001, gf108_gr_new },

	.mspdec   = { 0x00000001, gf100_mspdec_new },

	.msppp = gf100_msppp_new,

	.msppp    = { 0x00000001, gf100_msppp_new },

	.msvld = gf100_msvld_new,

	.pm = gf108_pm_new,

	.sw = gf100_sw_new,
@@ -1437,7 +1437,7 @@ nvc3_chipset = { 
	.fifo     = { 0x00000001, gf100_fifo_new },

	.gr       = { 0x00000001, gf104_gr_new },

	.mspdec   = { 0x00000001, gf100_mspdec_new },

	.msppp = gf100_msppp_new,

	.msppp    = { 0x00000001, gf100_msppp_new },

	.msvld = gf100_msvld_new,

	.pm = gf100_pm_new,

	.sw = gf100_sw_new,
@@ -1473,7 +1473,7 @@ nvc4_chipset = { 
	.fifo     = { 0x00000001, gf100_fifo_new },

	.gr       = { 0x00000001, gf104_gr_new },

	.mspdec   = { 0x00000001, gf100_mspdec_new },

	.msppp = gf100_msppp_new,

	.msppp    = { 0x00000001, gf100_msppp_new },

	.msvld = gf100_msvld_new,

	.pm = gf100_pm_new,

	.sw = gf100_sw_new,
@@ -1509,7 +1509,7 @@ nvc8_chipset = { 
	.fifo     = { 0x00000001, gf100_fifo_new },

	.gr       = { 0x00000001, gf110_gr_new },

	.mspdec   = { 0x00000001, gf100_mspdec_new },

	.msppp = gf100_msppp_new,

	.msppp    = { 0x00000001, gf100_msppp_new },

	.msvld = gf100_msvld_new,

	.pm = gf100_pm_new,

	.sw = gf100_sw_new,
@@ -1545,7 +1545,7 @@ nvce_chipset = { 
	.fifo     = { 0x00000001, gf100_fifo_new },

	.gr       = { 0x00000001, gf104_gr_new },

	.mspdec   = { 0x00000001, gf100_mspdec_new },

	.msppp = gf100_msppp_new,

	.msppp    = { 0x00000001, gf100_msppp_new },

	.msvld = gf100_msvld_new,

	.pm = gf100_pm_new,

	.sw = gf100_sw_new,
@@ -1581,7 +1581,7 @@ nvcf_chipset = { 
	.fifo     = { 0x00000001, gf100_fifo_new },

	.gr       = { 0x00000001, gf104_gr_new },

	.mspdec   = { 0x00000001, gf100_mspdec_new },

	.msppp = gf100_msppp_new,

	.msppp    = { 0x00000001, gf100_msppp_new },

	.msvld = gf100_msvld_new,

	.pm = gf100_pm_new,

	.sw = gf100_sw_new,
@@ -1616,7 +1616,7 @@ nvd7_chipset = { 
	.fifo     = { 0x00000001, gf100_fifo_new },

	.gr       = { 0x00000001, gf117_gr_new },

	.mspdec   = { 0x00000001, gf100_mspdec_new },

	.msppp = gf100_msppp_new,

	.msppp    = { 0x00000001, gf100_msppp_new },

	.msvld = gf100_msvld_new,

	.pm = gf117_pm_new,

	.sw = gf100_sw_new,
@@ -1652,7 +1652,7 @@ nvd9_chipset = { 
	.fifo     = { 0x00000001, gf100_fifo_new },

	.gr       = { 0x00000001, gf119_gr_new },

	.mspdec   = { 0x00000001, gf100_mspdec_new },

	.msppp = gf100_msppp_new,

	.msppp    = { 0x00000001, gf100_msppp_new },

	.msvld = gf100_msvld_new,

	.pm = gf117_pm_new,

	.sw = gf100_sw_new,
@@ -1689,7 +1689,7 @@ nve4_chipset = { 
	.fifo     = { 0x00000001, gk104_fifo_new },

	.gr       = { 0x00000001, gk104_gr_new },

	.mspdec   = { 0x00000001, gk104_mspdec_new },

	.msppp = gf100_msppp_new,

	.msppp    = { 0x00000001, gf100_msppp_new },

	.msvld = gk104_msvld_new,

	.pm = gk104_pm_new,

	.sw = gf100_sw_new,
@@ -1726,7 +1726,7 @@ nve6_chipset = { 
	.fifo     = { 0x00000001, gk104_fifo_new },

	.gr       = { 0x00000001, gk104_gr_new },

	.mspdec   = { 0x00000001, gk104_mspdec_new },

	.msppp = gf100_msppp_new,

	.msppp    = { 0x00000001, gf100_msppp_new },

	.msvld = gk104_msvld_new,

	.pm = gk104_pm_new,

	.sw = gf100_sw_new,
@@ -1763,7 +1763,7 @@ nve7_chipset = { 
	.fifo     = { 0x00000001, gk104_fifo_new },

	.gr       = { 0x00000001, gk104_gr_new },

	.mspdec   = { 0x00000001, gk104_mspdec_new },

	.msppp = gf100_msppp_new,

	.msppp    = { 0x00000001, gf100_msppp_new },

	.msvld = gk104_msvld_new,

	.pm = gk104_pm_new,

	.sw = gf100_sw_new,
@@ -1825,7 +1825,7 @@ nvf0_chipset = { 
	.fifo     = { 0x00000001, gk110_fifo_new },

	.gr       = { 0x00000001, gk110_gr_new },

	.mspdec   = { 0x00000001, gk104_mspdec_new },

	.msppp = gf100_msppp_new,

	.msppp    = { 0x00000001, gf100_msppp_new },

	.msvld = gk104_msvld_new,

	.sw = gf100_sw_new,

};
@@ -1861,7 +1861,7 @@ nvf1_chipset = { 
	.fifo     = { 0x00000001, gk110_fifo_new },

	.gr       = { 0x00000001, gk110b_gr_new },

	.mspdec   = { 0x00000001, gk104_mspdec_new },

	.msppp = gf100_msppp_new,

	.msppp    = { 0x00000001, gf100_msppp_new },

	.msvld = gk104_msvld_new,

	.sw = gf100_sw_new,

};
@@ -1897,7 +1897,7 @@ nv106_chipset = { 
	.fifo     = { 0x00000001, gk208_fifo_new },

	.gr       = { 0x00000001, gk208_gr_new },

	.mspdec   = { 0x00000001, gk104_mspdec_new },

	.msppp = gf100_msppp_new,

	.msppp    = { 0x00000001, gf100_msppp_new },

	.msvld = gk104_msvld_new,

	.sw = gf100_sw_new,

};
@@ -1933,7 +1933,7 @@ nv108_chipset = { 
	.fifo     = { 0x00000001, gk208_fifo_new },

	.gr       = { 0x00000001, gk208_gr_new },

	.mspdec   = { 0x00000001, gk104_mspdec_new },

	.msppp = gf100_msppp_new,

	.msppp    = { 0x00000001, gf100_msppp_new },

	.msvld = gk104_msvld_new,

	.sw = gf100_sw_new,

};
@@ -3174,7 +3174,6 @@ nvkm_device_ctor(const struct nvkm_device_func *func, 
#include <core/layout.h>

#undef NVKM_LAYOUT_INST

#undef NVKM_LAYOUT_ONCE

		_(NVKM_ENGINE_MSPPP   ,    msppp);

		_(NVKM_ENGINE_MSVLD   ,    msvld);

		_(NVKM_ENGINE_NVENC0  , nvenc[0]);

		_(NVKM_ENGINE_NVENC1  , nvenc[1]);