Commit 068a0f5c authored by Matt Roper's avatar Matt Roper Committed by Radhakrishna Sripada
Browse files

drm/i915/mtl: Don't mask off CCS according to DSS fusing 



Unlike the Xe_HP platforms, MTL only has a single CCS engine; the
quad-based engine masking logic does not apply to this platform (or
presumably any future platforms that only have 0 or 1 CCS).

Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarRadhakrishna Sripada <radhakrishna.sripada@intel.com>
Reviewed-by: default avatarBalasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220818234202.451742-5-radhakrishna.sripada@intel.com
parent da30390b

drivers/gpu/drm/i915/gt/intel_engine_cs.c

+1 −1
Original line number Diff line number Diff line
@@ -672,7 +672,7 @@ static void engine_mask_apply_compute_fuses(struct intel_gt *gt) 
	unsigned long ccs_mask;

	unsigned int i;



	if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))

	if (hweight32(CCS_MASK(gt)) <= 1)

		return;



	ccs_mask = intel_slicemask_from_xehp_dssmask(info->sseu.compute_subslice_mask,