Commit da30390b authored by Matt Roper's avatar Matt Roper Committed by Radhakrishna Sripada
Browse files

drm/i915/mtl: MMIO range is now 4MB 



Previously only dgfx platforms had a 4MB MMIO range, but starting with
MTL we now use the larger range for all platforms.

Bspec: 63834, 63830
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarRadhakrishna Sripada <radhakrishna.sripada@intel.com>
Reviewed-by: default avatarBalasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220818234202.451742-4-radhakrishna.sripada@intel.com
parent 6509dd11

drivers/gpu/drm/i915/intel_uncore.c

+6 −5
Original line number Diff line number Diff line
@@ -2235,14 +2235,15 @@ int intel_uncore_setup_mmio(struct intel_uncore *uncore, phys_addr_t phys_addr) 
	 * clobbering the GTT which we want ioremap_wc instead. Fortunately,

	 * the register BAR remains the same size for all the earlier

	 * generations up to Ironlake.

	 * For dgfx chips register range is expanded to 4MB.

	 * For dgfx chips register range is expanded to 4MB, and this larger

	 * range is also used for integrated gpus beginning with Meteor Lake.

	 */

	if (GRAPHICS_VER(i915) < 5)

		mmio_size = 512 * 1024;

	else if (IS_DGFX(i915))

	if (IS_DGFX(i915) || GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))

		mmio_size = 4 * 1024 * 1024;

	else

	else if (GRAPHICS_VER(i915) >= 5)

		mmio_size = 2 * 1024 * 1024;

	else

		mmio_size = 512 * 1024;



	uncore->regs = ioremap(phys_addr, mmio_size);

	if (uncore->regs == NULL) {