Commit 05b57273 authored by Shawn Lin's avatar Shawn Lin Committed by Bjorn Helgaas
Browse files

dt-bindings: phy-rockchip-pcie: Convert to per-lane PHY model 



Deprecate the legacy Rockchip PCIe PHY and encourage users to use per-lane
PHY mode by setting #phy-cells to 1.

Signed-off-by: default avatarShawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: default avatarBrian Norris <briannorris@chromium.org>
Acked-by: default avatarRob Herring <robh@kernel.org>
parent 7a55b570

Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt

+6 −1
Original line number Diff line number Diff line
@@ -3,7 +3,6 @@ Rockchip PCIE PHY 


Required properties:

 - compatible: rockchip,rk3399-pcie-phy

 - #phy-cells: must be 0

 - clocks: Must contain an entry in clock-names.

	See ../clocks/clock-bindings.txt for details.

 - clock-names: Must be "refclk"
@@ -11,6 +10,12 @@ Required properties: 
	See ../reset/reset.txt for details.

 - reset-names: Must be "phy"



Required properties for legacy PHY mode (deprecated):

 - #phy-cells: must be 0



Required properties for per-lane PHY mode (preferred):

 - #phy-cells: must be 1



Example:



grf: syscon@ff770000 {