dt-bindings: PCI: rockchip: Convert to per-lane PHY model

	- "pm"

- msi-map: Maps a Requester ID to an MSI controller and associated

	msi-specifier data. See ./pci-msi.txt

- phys: From PHY bindings: Phandle for the Generic PHY for PCIe.

- phy-names:  MUST be "pcie-phy".

- interrupts: Three interrupt entries must be specified.

- interrupt-names: Must include the following names

	- "sys"

	interrupt source. The value must be 1.

- interrupt-map-mask and interrupt-map: standard PCI properties

Required properties for legacy PHY model (deprecated):

- phys: From PHY bindings: Phandle for the Generic PHY for PCIe.

- phy-names:  MUST be "pcie-phy".

Required properties for per-lane PHY model (preferred):

- phys: Must contain an phandle to a PHY for each entry in phy-names.

- phy-names: Must include 4 entries for all 4 lanes even if some of

  them won't be used for your cases. Entries are of the form "pcie-phy-N":

  where N ranges from 0 to 3.

  (see example below and you MUST also refer to ../phy/rockchip-pcie-phy.txt

  for changing the #phy-cells of phy node to support it)

Optional Property:

- aspm-no-l0s: RC won't support ASPM L0s. This property is needed if

	using 24MHz OSC for RC's PHY.

		 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;

	reset-names = "core", "mgmt", "mgmt-sticky", "pipe",

		      "pm", "pclk", "aclk";

	/* deprecated legacy PHY model */

	phys = <&pcie_phy>;

	phy-names = "pcie-phy";

	pinctrl-names = "default";

		#interrupt-cells = <1>;

	};

};

pcie0: pcie@f8000000 {

	...

	/* preferred per-lane PHY model */

	phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>;

	phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3";

	...

};