Commit 04985d00 authored by Dmitry Osipenko's avatar Dmitry Osipenko Committed by Thierry Reding
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ARM: tegra: Don't enable PLLX while resuming from LP1 on Tegra30 



PLLX may be kept disabled if cpufreq driver selects some other clock for
CPU. In that case PLLX will be disabled later in the resume path by the
CLK driver, which also can enable PLLX if necessary by itself. Thus there
is no need to enable PLLX early during resume. Tegra114/124 CLK drivers do
not manage PLLX on resume and thus they are left untouched by this patch.

Acked-by: default avatarPeter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: default avatarPeter Geis <pgwipeout@gmail.com>
Tested-by: default avatarMarcel Ziswiler <marcel@ziswiler.com>
Tested-by: default avatarJasper Korten <jja2000@gmail.com>
Tested-by: default avatarDavid Heidelberg <david@ixit.cz>
Tested-by: default avatarNicolas Chauvet <kwizart@gmail.com>
Signed-off-by: default avatarDmitry Osipenko <digetx@gmail.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent d3c32c04

arch/arm/mach-tegra/sleep-tegra30.S

+7 −2
Original line number Diff line number Diff line
@@ -361,7 +361,6 @@ _no_pll_iddq_exit: 


	pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC

	pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC

	pll_enable r1, r0, CLK_RESET_PLLX_BASE, CLK_RESET_PLLX_MISC



_pll_m_c_x_done:

	pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC
@@ -371,12 +370,18 @@ _pll_m_c_x_done: 
	pll_locked r1, r0, CLK_RESET_PLLP_BASE

	pll_locked r1, r0, CLK_RESET_PLLA_BASE

	pll_locked r1, r0, CLK_RESET_PLLC_BASE

	pll_locked r1, r0, CLK_RESET_PLLX_BASE



	/*

	 * CPUFreq driver could select other PLL for CPU. PLLX will be

	 * enabled by the Tegra30 CLK driver on an as-needed basis, see

	 * tegra30_cpu_clock_resume().

	 */

	tegra_get_soc_id TEGRA_APB_MISC_BASE, r1

	cmp	r1, #TEGRA30

	beq	1f



	pll_locked r1, r0, CLK_RESET_PLLX_BASE



	ldr	r1, [r0, #CLK_RESET_PLLP_BASE]

	bic	r1, r1, #(1<<31)	@ disable PllP bypass

	str	r1, [r0, #CLK_RESET_PLLP_BASE]