Commit d3c32c04 authored by Dmitry Osipenko's avatar Dmitry Osipenko Committed by Thierry Reding
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ARM: tegra: Switch CPU to PLLP on resume from LP1 on Tegra30/114/124 



The early-resume code shall not switch CPU to PLLX because PLLX
configuration could be unstable or PLLX should be simply disabled if
CPU enters into suspend running off some other PLL (the case if CPUFREQ
driver is active). The actual burst policy is restored by the clock
drivers.

Acked-by: default avatarPeter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: default avatarPeter Geis <pgwipeout@gmail.com>
Tested-by: default avatarMarcel Ziswiler <marcel@ziswiler.com>
Tested-by: default avatarJasper Korten <jja2000@gmail.com>
Tested-by: default avatarDavid Heidelberg <david@ixit.cz>
Tested-by: default avatarNicolas Chauvet <kwizart@gmail.com>
Signed-off-by: default avatarDmitry Osipenko <digetx@gmail.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 35509737

arch/arm/mach-tegra/sleep-tegra30.S

+2 −5
Original line number Diff line number Diff line
@@ -398,11 +398,8 @@ _pll_m_c_x_done: 
	ldr	r4, [r5, #0x1C]		@ restore SCLK_BURST

	str	r4, [r0, #CLK_RESET_SCLK_BURST]



	cmp	r10, #TEGRA30

	movweq	r4, #:lower16:((1 << 28) | (0x8))	@ burst policy is PLLX

	movteq	r4, #:upper16:((1 << 28) | (0x8))

	movwne	r4, #:lower16:((1 << 28) | (0xe))

	movtne	r4, #:upper16:((1 << 28) | (0xe))

	movw	r4, #:lower16:((1 << 28) | (0x4))	@ burst policy is PLLP

	movt	r4, #:upper16:((1 << 28) | (0x4))

	str	r4, [r0, #CLK_RESET_CCLK_BURST]



	/* Restore pad power state to normal */