Commit 03d2c54d authored by Matt Roper's avatar Matt Roper Committed by Joonas Lahtinen
Browse files

drm/i915/mtl: Use primary GT's irq lock for media GT 



When we hook up interrupts (in the next patch), interrupts for the media
GT are still processed as part of the primary GT's interrupt flow.  As
such, we should share the same IRQ lock with the primary GT.  Let's
convert gt->irq_lock into a pointer and just point the media GT's
instance at the same lock the primary GT is using.

v2:
 - Point media's gt->irq_lock at the primary GT lock properly.  (Daniele)
 - Fix jump target for intel_root_gt_init_early errors.  (Daniele)

Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220906234934.3655440-14-matthew.d.roper@intel.com


Signed-off-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
parent f0e2f00c

drivers/gpu/drm/i915/gt/intel_engine_cs.c

+4 −4
Original line number Diff line number Diff line
@@ -1688,9 +1688,9 @@ bool intel_engine_irq_enable(struct intel_engine_cs *engine) 
		return false;



	/* Caller disables interrupts */

	spin_lock(&engine->gt->irq_lock);

	spin_lock(engine->gt->irq_lock);

	engine->irq_enable(engine);

	spin_unlock(&engine->gt->irq_lock);

	spin_unlock(engine->gt->irq_lock);



	return true;

}
@@ -1701,9 +1701,9 @@ void intel_engine_irq_disable(struct intel_engine_cs *engine) 
		return;



	/* Caller disables interrupts */

	spin_lock(&engine->gt->irq_lock);

	spin_lock(engine->gt->irq_lock);

	engine->irq_disable(engine);

	spin_unlock(&engine->gt->irq_lock);

	spin_unlock(engine->gt->irq_lock);

}



void intel_engines_reset_default_submission(struct intel_gt *gt)

drivers/gpu/drm/i915/gt/intel_gt.c

+13 −2
Original line number Diff line number Diff line
@@ -37,7 +37,7 @@ 


void intel_gt_common_init_early(struct intel_gt *gt)

{

	spin_lock_init(&gt->irq_lock);

	spin_lock_init(gt->irq_lock);



	INIT_LIST_HEAD(&gt->closed_vma);

	spin_lock_init(&gt->closed_lock);
@@ -58,14 +58,19 @@ void intel_gt_common_init_early(struct intel_gt *gt) 
}



/* Preliminary initialization of Tile 0 */

void intel_root_gt_init_early(struct drm_i915_private *i915)

int intel_root_gt_init_early(struct drm_i915_private *i915)

{

	struct intel_gt *gt = to_gt(i915);



	gt->i915 = i915;

	gt->uncore = &i915->uncore;

	gt->irq_lock = drmm_kzalloc(&i915->drm, sizeof(*gt->irq_lock), GFP_KERNEL);

	if (!gt->irq_lock)

		return -ENOMEM;



	intel_gt_common_init_early(gt);



	return 0;

}



static int intel_gt_probe_lmem(struct intel_gt *gt)
@@ -782,12 +787,18 @@ static int intel_gt_tile_setup(struct intel_gt *gt, phys_addr_t phys_addr) 


	if (!gt_is_root(gt)) {

		struct intel_uncore *uncore;

		spinlock_t *irq_lock;



		uncore = drmm_kzalloc(&gt->i915->drm, sizeof(*uncore), GFP_KERNEL);

		if (!uncore)

			return -ENOMEM;



		irq_lock = drmm_kzalloc(&gt->i915->drm, sizeof(*irq_lock), GFP_KERNEL);

		if (!irq_lock)

			return -ENOMEM;



		gt->uncore = uncore;

		gt->irq_lock = irq_lock;



		intel_gt_common_init_early(gt);

	}

drivers/gpu/drm/i915/gt/intel_gt.h

+1 −1
Original line number Diff line number Diff line
@@ -45,7 +45,7 @@ static inline struct intel_gt *gsc_to_gt(struct intel_gsc *gsc) 
}



void intel_gt_common_init_early(struct intel_gt *gt);

void intel_root_gt_init_early(struct drm_i915_private *i915);

int intel_root_gt_init_early(struct drm_i915_private *i915);

int intel_gt_assign_ggtt(struct intel_gt *gt);

int intel_gt_init_mmio(struct intel_gt *gt);

int __must_check intel_gt_init_hw(struct intel_gt *gt);

drivers/gpu/drm/i915/gt/intel_gt_irq.c

+8 −8
Original line number Diff line number Diff line
@@ -29,7 +29,7 @@ gen11_gt_engine_identity(struct intel_gt *gt, 
	u32 timeout_ts;

	u32 ident;



	lockdep_assert_held(&gt->irq_lock);

	lockdep_assert_held(gt->irq_lock);



	raw_reg_write(regs, GEN11_IIR_REG_SELECTOR(bank), BIT(bit));
@@ -120,7 +120,7 @@ gen11_gt_bank_handler(struct intel_gt *gt, const unsigned int bank) 
	unsigned long intr_dw;

	unsigned int bit;



	lockdep_assert_held(&gt->irq_lock);

	lockdep_assert_held(gt->irq_lock);



	intr_dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank));
@@ -138,14 +138,14 @@ void gen11_gt_irq_handler(struct intel_gt *gt, const u32 master_ctl) 
{

	unsigned int bank;



	spin_lock(&gt->irq_lock);

	spin_lock(gt->irq_lock);



	for (bank = 0; bank < 2; bank++) {

		if (master_ctl & GEN11_GT_DW_IRQ(bank))

			gen11_gt_bank_handler(gt, bank);

	}



	spin_unlock(&gt->irq_lock);

	spin_unlock(gt->irq_lock);

}



bool gen11_gt_reset_one_iir(struct intel_gt *gt,
@@ -154,7 +154,7 @@ bool gen11_gt_reset_one_iir(struct intel_gt *gt, 
	void __iomem * const regs = gt->uncore->regs;

	u32 dw;



	lockdep_assert_held(&gt->irq_lock);

	lockdep_assert_held(gt->irq_lock);



	dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank));

	if (dw & BIT(bit)) {
@@ -310,9 +310,9 @@ static void gen7_parity_error_irq_handler(struct intel_gt *gt, u32 iir) 
	if (!HAS_L3_DPF(gt->i915))

		return;



	spin_lock(&gt->irq_lock);

	spin_lock(gt->irq_lock);

	gen5_gt_disable_irq(gt, GT_PARITY_ERROR(gt->i915));

	spin_unlock(&gt->irq_lock);

	spin_unlock(gt->irq_lock);



	if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)

		gt->i915->l3_parity.which_slice |= 1 << 1;
@@ -434,7 +434,7 @@ static void gen5_gt_update_irq(struct intel_gt *gt, 
			       u32 interrupt_mask,

			       u32 enabled_irq_mask)

{

	lockdep_assert_held(&gt->irq_lock);

	lockdep_assert_held(gt->irq_lock);



	GEM_BUG_ON(enabled_irq_mask & ~interrupt_mask);

drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c

+4 −4
Original line number Diff line number Diff line
@@ -37,7 +37,7 @@ static void gen6_gt_pm_update_irq(struct intel_gt *gt, 


	WARN_ON(enabled_irq_mask & ~interrupt_mask);



	lockdep_assert_held(&gt->irq_lock);

	lockdep_assert_held(gt->irq_lock);



	new_val = gt->pm_imr;

	new_val &= ~interrupt_mask;
@@ -64,7 +64,7 @@ void gen6_gt_pm_reset_iir(struct intel_gt *gt, u32 reset_mask) 
	struct intel_uncore *uncore = gt->uncore;

	i915_reg_t reg = GRAPHICS_VER(gt->i915) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;



	lockdep_assert_held(&gt->irq_lock);

	lockdep_assert_held(gt->irq_lock);



	intel_uncore_write(uncore, reg, reset_mask);

	intel_uncore_write(uncore, reg, reset_mask);
@@ -92,7 +92,7 @@ static void write_pm_ier(struct intel_gt *gt) 


void gen6_gt_pm_enable_irq(struct intel_gt *gt, u32 enable_mask)

{

	lockdep_assert_held(&gt->irq_lock);

	lockdep_assert_held(gt->irq_lock);



	gt->pm_ier |= enable_mask;

	write_pm_ier(gt);
@@ -101,7 +101,7 @@ void gen6_gt_pm_enable_irq(struct intel_gt *gt, u32 enable_mask) 


void gen6_gt_pm_disable_irq(struct intel_gt *gt, u32 disable_mask)

{

	lockdep_assert_held(&gt->irq_lock);

	lockdep_assert_held(gt->irq_lock);



	gt->pm_ier &= ~disable_mask;

	gen6_gt_pm_mask_irq(gt, disable_mask);