Unverified Commit 03b1be37 authored by Leilk Liu's avatar Leilk Liu Committed by Mark Brown
Browse files

spi: mediatek: support tick_delay without enhance_timing 



this patch support tick_delay bit[31:30] without enhance_timing feature.

Fixes: f84d866a("spi: mediatek: add tick_delay support")
Signed-off-by: default avatarLeilk Liu <leilk.liu@mediatek.com>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220315032411.2826-2-leilk.liu@mediatek.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 1889421a

drivers/spi/spi-mt65xx.c

+12 −3
Original line number Original line Diff line number Diff line
@@ -43,8 +43,11 @@ 
#define SPI_CFG1_PACKET_LOOP_OFFSET       8

#define SPI_CFG1_PACKET_LOOP_OFFSET       8

#define SPI_CFG1_PACKET_LENGTH_OFFSET     16

#define SPI_CFG1_PACKET_LENGTH_OFFSET     16

#define SPI_CFG1_GET_TICK_DLY_OFFSET      29

#define SPI_CFG1_GET_TICK_DLY_OFFSET      29

#define SPI_CFG1_GET_TICK_DLY_OFFSET_V1   30





#define SPI_CFG1_GET_TICK_DLY_MASK        0xe0000000

#define SPI_CFG1_GET_TICK_DLY_MASK        0xe0000000

#define SPI_CFG1_GET_TICK_DLY_MASK_V1     0xc0000000



#define SPI_CFG1_CS_IDLE_MASK             0xff

#define SPI_CFG1_CS_IDLE_MASK             0xff

#define SPI_CFG1_PACKET_LOOP_MASK         0xff00

#define SPI_CFG1_PACKET_LOOP_MASK         0xff00

#define SPI_CFG1_PACKET_LENGTH_MASK       0x3ff0000

#define SPI_CFG1_PACKET_LENGTH_MASK       0x3ff0000
@@ -346,9 +349,15 @@ static int mtk_spi_prepare_message(struct spi_master *master, 




	/* tick delay */

	/* tick delay */

	reg_val = readl(mdata->base + SPI_CFG1_REG);

	reg_val = readl(mdata->base + SPI_CFG1_REG);

	if (mdata->dev_comp->enhance_timing) {

		reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK;

		reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK;

		reg_val |= ((chip_config->tick_delay & 0x7)

		reg_val |= ((chip_config->tick_delay & 0x7)

			    << SPI_CFG1_GET_TICK_DLY_OFFSET);

			    << SPI_CFG1_GET_TICK_DLY_OFFSET);

	} else {

		reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK_V1;

		reg_val |= ((chip_config->tick_delay & 0x3)

			    << SPI_CFG1_GET_TICK_DLY_OFFSET_V1);

	}

	writel(reg_val, mdata->base + SPI_CFG1_REG);

	writel(reg_val, mdata->base + SPI_CFG1_REG);





	/* set hw cs timing */

	/* set hw cs timing */