Unverified Commit f84d866a authored by Mason Zhang's avatar Mason Zhang Committed by Mark Brown
Browse files

spi: mediatek: add tick_delay support 



This patch support tick_delay setting, some users need use
high-speed spi speed, which can use tick_delay to tuning spi clk timing.

Signed-off-by: default avatarMason Zhang <Mason.Zhang@mediatek.com>
Link: https://lore.kernel.org/r/20210713114048.29509-1-mason.zhang@mediatek.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 65ab894f

drivers/spi/spi-mt65xx.c

+10 −1
Original line number Diff line number Diff line
@@ -42,8 +42,9 @@ 
#define SPI_CFG1_CS_IDLE_OFFSET           0

#define SPI_CFG1_PACKET_LOOP_OFFSET       8

#define SPI_CFG1_PACKET_LENGTH_OFFSET     16

#define SPI_CFG1_GET_TICK_DLY_OFFSET      30

#define SPI_CFG1_GET_TICK_DLY_OFFSET      29



#define SPI_CFG1_GET_TICK_DLY_MASK        0xe0000000

#define SPI_CFG1_CS_IDLE_MASK             0xff

#define SPI_CFG1_PACKET_LOOP_MASK         0xff00

#define SPI_CFG1_PACKET_LENGTH_MASK       0x3ff0000
@@ -152,6 +153,7 @@ static const struct mtk_spi_compatible mt6893_compat = { 
 */

static const struct mtk_chip_config mtk_default_chip_info = {

	.sample_sel = 0,

	.tick_delay = 0,

};



static const struct of_device_id mtk_spi_of_match[] = {
@@ -275,6 +277,13 @@ static int mtk_spi_prepare_message(struct spi_master *master, 
		writel(mdata->pad_sel[spi->chip_select],

		       mdata->base + SPI_PAD_SEL_REG);



	/* tick delay */

	reg_val = readl(mdata->base + SPI_CFG1_REG);

	reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK;

	reg_val |= ((chip_config->tick_delay & 0x7)

		<< SPI_CFG1_GET_TICK_DLY_OFFSET);

	writel(reg_val, mdata->base + SPI_CFG1_REG);



	return 0;

}

include/linux/platform_data/spi-mt65xx.h

+1 −0
Original line number Diff line number Diff line
@@ -12,5 +12,6 @@ 
/* Board specific platform_data */

struct mtk_chip_config {

	u32 sample_sel;

	u32 tick_delay;

};

#endif