Commit 036e348f authored by Eric Huang's avatar Eric Huang Committed by Alex Deucher
Browse files

drm/amdkfd: add kfd2kgd debugger callbacks for GC v9.4.3 



Implement the similarities as GC v9.4.2, and the difference
for GC v9.4.3 HW spec, i.e. xcc instance.

Signed-off-by: default avatarJonathan Kim <jonathan.kim@amd.com>
Signed-off-by: default avatarEric Huang <jinhuieric.huang@amd.com>
Reviewed-by: default avatarJonathan Kim <jonathan.kim@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 9df88c81

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

+5 −3
Original line number Diff line number Diff line
@@ -23,6 +23,7 @@ 
#include "amdgpu_amdkfd.h"

#include "amdgpu_amdkfd_arcturus.h"

#include "amdgpu_amdkfd_gfx_v9.h"

#include "amdgpu_amdkfd_aldebaran.h"

#include "gc/gc_9_4_2_offset.h"

#include "gc/gc_9_4_2_sh_mask.h"

#include <uapi/linux/kfd_ioctl.h>
@@ -36,7 +37,7 @@ 
 * initialize the debug mode registers after it has disabled GFX off during the

 * debug session.

 */

static uint32_t kgd_aldebaran_enable_debug_trap(struct amdgpu_device *adev,

uint32_t kgd_aldebaran_enable_debug_trap(struct amdgpu_device *adev,

					    bool restore_dbg_registers,

					    uint32_t vmid)

{
@@ -107,7 +108,7 @@ static uint32_t kgd_aldebaran_set_wave_launch_trap_override(struct amdgpu_device 
	return data;

}



static uint32_t kgd_aldebaran_set_wave_launch_mode(struct amdgpu_device *adev,

uint32_t kgd_aldebaran_set_wave_launch_mode(struct amdgpu_device *adev,

					uint8_t wave_launch_mode,

					uint32_t vmid)

{
@@ -125,7 +126,8 @@ static uint32_t kgd_gfx_aldebaran_set_address_watch( 
					uint32_t watch_address_mask,

					uint32_t watch_id,

					uint32_t watch_mode,

					uint32_t debug_vmid)

					uint32_t debug_vmid,

					uint32_t inst)

{

	uint32_t watch_address_high;

	uint32_t watch_address_low;

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.h

0 → 100644
+27 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2023 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 */

uint32_t kgd_aldebaran_enable_debug_trap(struct amdgpu_device *adev,

					bool restore_dbg_registers,

					uint32_t vmid);

uint32_t kgd_aldebaran_set_wave_launch_mode(struct amdgpu_device *adev,

					uint8_t wave_launch_mode,

					uint32_t vmid);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

+165 −1
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ 
#include "amdgpu.h"

#include "amdgpu_amdkfd.h"

#include "amdgpu_amdkfd_gfx_v9.h"

#include "amdgpu_amdkfd_aldebaran.h"

#include "gc/gc_9_4_3_offset.h"

#include "gc/gc_9_4_3_sh_mask.h"

#include "athub/athub_1_8_0_offset.h"
@@ -32,6 +33,7 @@ 
#include "soc15.h"

#include "sdma/sdma_4_4_2_offset.h"

#include "sdma/sdma_4_4_2_sh_mask.h"

#include <uapi/linux/kfd_ioctl.h>



static inline struct v9_sdma_mqd *get_sdma_mqd(void *mqd)

{
@@ -361,6 +363,156 @@ static int kgd_gfx_v9_4_3_hqd_load(struct amdgpu_device *adev, void *mqd, 
	return 0;

}



/* returns TRAP_EN, EXCP_EN and EXCP_REPLACE. */

static uint32_t kgd_gfx_v9_4_3_disable_debug_trap(struct amdgpu_device *adev,

						bool keep_trap_enabled,

						uint32_t vmid)

{

	uint32_t data = 0;



	data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);

	data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, 0);

	data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, 0);



	return data;

}



static int kgd_gfx_v9_4_3_validate_trap_override_request(

				struct amdgpu_device *adev,

				uint32_t trap_override,

				uint32_t *trap_mask_supported)

{

	*trap_mask_supported &= KFD_DBG_TRAP_MASK_FP_INVALID |

				KFD_DBG_TRAP_MASK_FP_INPUT_DENORMAL |

				KFD_DBG_TRAP_MASK_FP_DIVIDE_BY_ZERO |

				KFD_DBG_TRAP_MASK_FP_OVERFLOW |

				KFD_DBG_TRAP_MASK_FP_UNDERFLOW |

				KFD_DBG_TRAP_MASK_FP_INEXACT |

				KFD_DBG_TRAP_MASK_INT_DIVIDE_BY_ZERO |

				KFD_DBG_TRAP_MASK_DBG_ADDRESS_WATCH |

				KFD_DBG_TRAP_MASK_DBG_MEMORY_VIOLATION |

				KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_START |

				KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_END;



	if (trap_override != KFD_DBG_TRAP_OVERRIDE_OR &&

			trap_override != KFD_DBG_TRAP_OVERRIDE_REPLACE)

		return -EPERM;



	return 0;

}



static uint32_t trap_mask_map_sw_to_hw(uint32_t mask)

{

	uint32_t trap_on_start = (mask & KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_START) ? 1 : 0;

	uint32_t trap_on_end = (mask & KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_END) ? 1 : 0;

	uint32_t excp_en = mask & (KFD_DBG_TRAP_MASK_FP_INVALID |

				KFD_DBG_TRAP_MASK_FP_INPUT_DENORMAL |

				KFD_DBG_TRAP_MASK_FP_DIVIDE_BY_ZERO |

				KFD_DBG_TRAP_MASK_FP_OVERFLOW |

				KFD_DBG_TRAP_MASK_FP_UNDERFLOW |

				KFD_DBG_TRAP_MASK_FP_INEXACT |

				KFD_DBG_TRAP_MASK_INT_DIVIDE_BY_ZERO |

				KFD_DBG_TRAP_MASK_DBG_ADDRESS_WATCH |

				KFD_DBG_TRAP_MASK_DBG_MEMORY_VIOLATION);

	uint32_t ret;



	ret = REG_SET_FIELD(0, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, excp_en);

	ret = REG_SET_FIELD(ret, SPI_GDBG_PER_VMID_CNTL, TRAP_ON_START, trap_on_start);

	ret = REG_SET_FIELD(ret, SPI_GDBG_PER_VMID_CNTL, TRAP_ON_END, trap_on_end);



	return ret;

}



static uint32_t trap_mask_map_hw_to_sw(uint32_t mask)

{

	uint32_t ret = REG_GET_FIELD(mask, SPI_GDBG_PER_VMID_CNTL, EXCP_EN);



	if (REG_GET_FIELD(mask, SPI_GDBG_PER_VMID_CNTL, TRAP_ON_START))

		ret |= KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_START;



	if (REG_GET_FIELD(mask, SPI_GDBG_PER_VMID_CNTL, TRAP_ON_END))

		ret |= KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_END;



	return ret;

}



/* returns TRAP_EN, EXCP_EN and EXCP_REPLACE. */

static uint32_t kgd_gfx_v9_4_3_set_wave_launch_trap_override(

				struct amdgpu_device *adev,

				uint32_t vmid,

				uint32_t trap_override,

				uint32_t trap_mask_bits,

				uint32_t trap_mask_request,

				uint32_t *trap_mask_prev,

				uint32_t kfd_dbg_trap_cntl_prev)



{

	uint32_t data = 0;



	*trap_mask_prev = trap_mask_map_hw_to_sw(kfd_dbg_trap_cntl_prev);



	data = (trap_mask_bits & trap_mask_request) |

	       (*trap_mask_prev & ~trap_mask_request);

	data = trap_mask_map_sw_to_hw(data);



	data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);

	data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, trap_override);



	return data;

}



#define TCP_WATCH_STRIDE (regTCP_WATCH1_ADDR_H - regTCP_WATCH0_ADDR_H)

static uint32_t kgd_gfx_v9_4_3_set_address_watch(

				struct amdgpu_device *adev,

				uint64_t watch_address,

				uint32_t watch_address_mask,

				uint32_t watch_id,

				uint32_t watch_mode,

				uint32_t debug_vmid,

				uint32_t inst)

{

	uint32_t watch_address_high;

	uint32_t watch_address_low;

	uint32_t watch_address_cntl;



	watch_address_cntl = 0;

	watch_address_low = lower_32_bits(watch_address);

	watch_address_high = upper_32_bits(watch_address) & 0xffff;



	watch_address_cntl = REG_SET_FIELD(watch_address_cntl,

			TCP_WATCH0_CNTL,

			MODE,

			watch_mode);



	watch_address_cntl = REG_SET_FIELD(watch_address_cntl,

			TCP_WATCH0_CNTL,

			MASK,

			watch_address_mask >> 7);



	watch_address_cntl = REG_SET_FIELD(watch_address_cntl,

			TCP_WATCH0_CNTL,

			VALID,

			1);



	WREG32_RLC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst),

			regTCP_WATCH0_ADDR_H) +

			(watch_id * TCP_WATCH_STRIDE)),

			watch_address_high);



	WREG32_RLC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst),

			regTCP_WATCH0_ADDR_L) +

			(watch_id * TCP_WATCH_STRIDE)),

			watch_address_low);



	return watch_address_cntl;

}



static uint32_t kgd_gfx_v9_4_3_clear_address_watch(struct amdgpu_device *adev,

				uint32_t watch_id)

{

	return 0;

}



const struct kfd2kgd_calls gc_9_4_3_kfd2kgd = {

	.program_sh_mem_settings = kgd_gfx_v9_program_sh_mem_settings,

	.set_pasid_vmid_mapping = kgd_gfx_v9_4_3_set_pasid_vmid_mapping,
@@ -381,5 +533,17 @@ const struct kfd2kgd_calls gc_9_4_3_kfd2kgd = { 
				kgd_gfx_v9_set_vm_context_page_table_base,

	.get_cu_occupancy = kgd_gfx_v9_get_cu_occupancy,

	.program_trap_handler_settings =

				kgd_gfx_v9_program_trap_handler_settings

				kgd_gfx_v9_program_trap_handler_settings,

	.build_grace_period_packet_info =

				kgd_gfx_v9_build_grace_period_packet_info,

	.get_iq_wait_times = kgd_gfx_v9_get_iq_wait_times,

	.enable_debug_trap = kgd_aldebaran_enable_debug_trap,

	.disable_debug_trap = kgd_gfx_v9_4_3_disable_debug_trap,

	.validate_trap_override_request =

			kgd_gfx_v9_4_3_validate_trap_override_request,

	.set_wave_launch_trap_override =

			kgd_gfx_v9_4_3_set_wave_launch_trap_override,

	.set_wave_launch_mode = kgd_aldebaran_set_wave_launch_mode,

	.set_address_watch = kgd_gfx_v9_4_3_set_address_watch,

	.clear_address_watch = kgd_gfx_v9_4_3_clear_address_watch

};

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

+6 −3
Original line number Diff line number Diff line
@@ -886,7 +886,8 @@ uint32_t kgd_gfx_v10_set_address_watch(struct amdgpu_device *adev, 
					uint32_t watch_address_mask,

					uint32_t watch_id,

					uint32_t watch_mode,

					uint32_t debug_vmid)

					uint32_t debug_vmid,

					uint32_t inst)

{

	uint32_t watch_address_high;

	uint32_t watch_address_low;
@@ -968,7 +969,8 @@ uint32_t kgd_gfx_v10_clear_address_watch(struct amdgpu_device *adev, 
 *     deq_retry_wait_time      -- Wait Count for Global Wave Syncs.

 */

void kgd_gfx_v10_get_iq_wait_times(struct amdgpu_device *adev,

					uint32_t *wait_times)

					uint32_t *wait_times,

					uint32_t inst)



{

	*wait_times = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_IQ_WAIT_TIME2));
@@ -978,7 +980,8 @@ void kgd_gfx_v10_build_grace_period_packet_info(struct amdgpu_device *adev, 
						uint32_t wait_times,

						uint32_t grace_period,

						uint32_t *reg_offset,

						uint32_t *reg_data)

						uint32_t *reg_data,

						uint32_t inst)

{

	*reg_data = wait_times;

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h

+7 −3
Original line number Diff line number Diff line
@@ -44,12 +44,16 @@ uint32_t kgd_gfx_v10_set_address_watch(struct amdgpu_device *adev, 
					uint32_t watch_address_mask,

					uint32_t watch_id,

					uint32_t watch_mode,

					uint32_t debug_vmid);

					uint32_t debug_vmid,

					uint32_t inst);

uint32_t kgd_gfx_v10_clear_address_watch(struct amdgpu_device *adev,

					uint32_t watch_id);

void kgd_gfx_v10_get_iq_wait_times(struct amdgpu_device *adev, uint32_t *wait_times);

void kgd_gfx_v10_get_iq_wait_times(struct amdgpu_device *adev,

				uint32_t *wait_times,

				uint32_t inst);

void kgd_gfx_v10_build_grace_period_packet_info(struct amdgpu_device *adev,

					       uint32_t wait_times,

					       uint32_t grace_period,

					       uint32_t *reg_offset,

					       uint32_t *reg_data);
 
					       uint32_t *reg_data,

					       uint32_t inst);