Commit 9df88c81 authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher
Browse files

drm/amd/pm: share the code around SMU13 pcie parameters update 



So that SMU13.0.0 and SMU13.0.7 do not need to have one copy each.

Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Signed-off-by: default avatarMario Limonciello <mario.limonciello@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 822130b5

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h

+4 −0
Original line number Diff line number Diff line
@@ -295,5 +295,9 @@ int smu_v13_0_get_pptable_from_firmware(struct smu_context *smu, 
					uint32_t *size,

					uint32_t pptable_id);



int smu_v13_0_update_pcie_parameters(struct smu_context *smu,

				     uint32_t pcie_gen_cap,

				     uint32_t pcie_width_cap);



#endif

#endif

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

+31 −0
Original line number Diff line number Diff line
@@ -2424,3 +2424,34 @@ int smu_v13_0_mode1_reset(struct smu_context *smu) 


	return ret;

}



int smu_v13_0_update_pcie_parameters(struct smu_context *smu,

				     uint32_t pcie_gen_cap,

				     uint32_t pcie_width_cap)

{

	struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;

	struct smu_13_0_pcie_table *pcie_table =

				&dpm_context->dpm_tables.pcie_table;

	uint32_t smu_pcie_arg;

	int ret, i;



	for (i = 0; i < pcie_table->num_of_link_levels; i++) {

		if (pcie_table->pcie_gen[i] > pcie_gen_cap)

			pcie_table->pcie_gen[i] = pcie_gen_cap;

		if (pcie_table->pcie_lane[i] > pcie_width_cap)

			pcie_table->pcie_lane[i] = pcie_width_cap;



		smu_pcie_arg = i << 16;

		smu_pcie_arg |= pcie_table->pcie_gen[i] << 8;

		smu_pcie_arg |= pcie_table->pcie_lane[i];



		ret = smu_cmn_send_smc_msg_with_param(smu,

						      SMU_MSG_OverridePcieParameters,

						      smu_pcie_arg,

						      NULL);

		if (ret)

			return ret;

	}



	return 0;

}

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

+1 −32
Original line number Diff line number Diff line
@@ -1645,37 +1645,6 @@ static int smu_v13_0_0_force_clk_levels(struct smu_context *smu, 
	return ret;

}



static int smu_v13_0_0_update_pcie_parameters(struct smu_context *smu,

					      uint32_t pcie_gen_cap,

					      uint32_t pcie_width_cap)

{

	struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;

	struct smu_13_0_pcie_table *pcie_table =

				&dpm_context->dpm_tables.pcie_table;

	uint32_t smu_pcie_arg;

	int ret, i;



	for (i = 0; i < pcie_table->num_of_link_levels; i++) {

		if (pcie_table->pcie_gen[i] > pcie_gen_cap)

			pcie_table->pcie_gen[i] = pcie_gen_cap;

		if (pcie_table->pcie_lane[i] > pcie_width_cap)

			pcie_table->pcie_lane[i] = pcie_width_cap;



		smu_pcie_arg = i << 16;

		smu_pcie_arg |= pcie_table->pcie_gen[i] << 8;

		smu_pcie_arg |= pcie_table->pcie_lane[i];



		ret = smu_cmn_send_smc_msg_with_param(smu,

						      SMU_MSG_OverridePcieParameters,

						      smu_pcie_arg,

						      NULL);

		if (ret)

			return ret;

	}



	return 0;

}



static const struct smu_temperature_range smu13_thermal_policy[] = {

	{-273150,  99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},

	{ 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
@@ -2654,7 +2623,7 @@ static const struct pptable_funcs smu_v13_0_0_ppt_funcs = { 
	.feature_is_enabled = smu_cmn_feature_is_enabled,

	.print_clk_levels = smu_v13_0_0_print_clk_levels,

	.force_clk_levels = smu_v13_0_0_force_clk_levels,

	.update_pcie_parameters = smu_v13_0_0_update_pcie_parameters,

	.update_pcie_parameters = smu_v13_0_update_pcie_parameters,

	.get_thermal_temperature_range = smu_v13_0_0_get_thermal_temperature_range,

	.register_irq_handler = smu_v13_0_register_irq_handler,

	.enable_thermal_alert = smu_v13_0_enable_thermal_alert,

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

+1 −32
Original line number Diff line number Diff line
@@ -1635,37 +1635,6 @@ static int smu_v13_0_7_force_clk_levels(struct smu_context *smu, 
	return ret;

}



static int smu_v13_0_7_update_pcie_parameters(struct smu_context *smu,

					      uint32_t pcie_gen_cap,

					      uint32_t pcie_width_cap)

{

	struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;

	struct smu_13_0_pcie_table *pcie_table =

				&dpm_context->dpm_tables.pcie_table;

	uint32_t smu_pcie_arg;

	int ret, i;



	for (i = 0; i < pcie_table->num_of_link_levels; i++) {

		if (pcie_table->pcie_gen[i] > pcie_gen_cap)

			pcie_table->pcie_gen[i] = pcie_gen_cap;

		if (pcie_table->pcie_lane[i] > pcie_width_cap)

			pcie_table->pcie_lane[i] = pcie_width_cap;



		smu_pcie_arg = i << 16;

		smu_pcie_arg |= pcie_table->pcie_gen[i] << 8;

		smu_pcie_arg |= pcie_table->pcie_lane[i];



		ret = smu_cmn_send_smc_msg_with_param(smu,

						      SMU_MSG_OverridePcieParameters,

						      smu_pcie_arg,

						      NULL);

		if (ret)

			return ret;

	}



	return 0;

}



static const struct smu_temperature_range smu13_thermal_policy[] =

{

	{-273150,  99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
@@ -2234,7 +2203,7 @@ static const struct pptable_funcs smu_v13_0_7_ppt_funcs = { 
	.feature_is_enabled = smu_cmn_feature_is_enabled,

	.print_clk_levels = smu_v13_0_7_print_clk_levels,

	.force_clk_levels = smu_v13_0_7_force_clk_levels,

	.update_pcie_parameters = smu_v13_0_7_update_pcie_parameters,

	.update_pcie_parameters = smu_v13_0_update_pcie_parameters,

	.get_thermal_temperature_range = smu_v13_0_7_get_thermal_temperature_range,

	.register_irq_handler = smu_v13_0_register_irq_handler,

	.enable_thermal_alert = smu_v13_0_enable_thermal_alert,