Commit 03110b46 authored by Luca Weiss's avatar Luca Weiss Committed by Bjorn Andersson
Browse files

ARM: dts: qcom: msm8974: re-add missing pinctrl 



As part of a recent cleanup commit, the pinctrl for a few uart and i2c
nodes was removed. Adjust the names and/or add it back and assign it to
the uart and i2c nodes.

Fixes: 1dfe967e ("ARM: dts: qcom-msm8974*: Consolidate I2C/UART/SDHCI")
Signed-off-by: default avatarLuca Weiss <luca@z3ntu.xyz>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220606160421.1641778-1-luca@z3ntu.xyz
parent f2906aa8

arch/arm/boot/dts/qcom-msm8974.dtsi

+26 −4
Original line number Diff line number Diff line
@@ -506,6 +506,8 @@ 
			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "core", "iface";

			pinctrl-names = "default";

			pinctrl-0 = <&blsp1_uart2_default>;

			status = "disabled";

		};
@@ -581,6 +583,9 @@ 
			interrupts = <GIC_SPI 113 IRQ_TYPE_NONE>;

			clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;

			clock-names = "core", "iface";

			pinctrl-names = "default", "sleep";

			pinctrl-0 = <&blsp2_uart1_default>;

			pinctrl-1 = <&blsp2_uart1_sleep>;

			status = "disabled";

		};
@@ -599,6 +604,8 @@ 
			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP2_UART4_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;

			clock-names = "core", "iface";

			pinctrl-names = "default";

			pinctrl-0 = <&blsp2_uart4_default>;

			status = "disabled";

		};
@@ -639,6 +646,9 @@ 
			interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;

			clock-names = "core", "iface";

			pinctrl-names = "default", "sleep";

			pinctrl-0 = <&blsp2_i2c6_default>;

			pinctrl-1 = <&blsp2_i2c6_sleep>;

			#address-cells = <1>;

			#size-cells = <0>;

		};
@@ -1256,7 +1266,7 @@ 
				};

			};



			blsp1_uart2_active: blsp1-uart2-active {

			blsp1_uart2_default: blsp1-uart2-default {

				rx {

					pins = "gpio5";

					function = "blsp_uart2";
@@ -1272,7 +1282,7 @@ 
				};

			};



			blsp2_uart1_active: blsp2-uart1-active {

			blsp2_uart1_default: blsp2-uart1-default {

				tx-rts {

					pins = "gpio41", "gpio44";

					function = "blsp_uart7";
@@ -1295,7 +1305,7 @@ 
				bias-pull-down;

			};



			blsp2_uart4_active: blsp2-uart4-active {

			blsp2_uart4_default: blsp2-uart4-default {

				tx-rts {

					pins = "gpio53", "gpio56";

					function = "blsp_uart10";
@@ -1406,7 +1416,19 @@ 
				bias-pull-up;

			};



			/* BLSP2_I2C6 info is missing - nobody uses it though? */

			blsp2_i2c6_default: blsp2-i2c6-default {

				pins = "gpio87", "gpio88";

				function = "blsp_i2c12";

				drive-strength = <2>;

				bias-disable;

			};



			blsp2_i2c6_sleep: blsp2-i2c6-sleep {

				pins = "gpio87", "gpio88";

				function = "blsp_i2c12";

				drive-strength = <2>;

				bias-pull-up;

			};



			spi8_default: spi8_default {

				mosi {