Unverified Commit 02c98b16 authored by Dave Stevenson's avatar Dave Stevenson Committed by Maxime Ripard
Browse files

drm/vc4: plane: Allow using 0 as a pixel order value 



vc4_plane_mode_set for HVS5 was using pixel_order unless pixel_order_hvs5
was non-zero, except 0 is a valid value for the pixel_order.

Specify pixel_order_hvs5 for all formats and remove the conditional.

Signed-off-by: default avatarDave Stevenson <dave.stevenson@raspberrypi.com>
Link: https://lore.kernel.org/r/20221207-rpi-hvs-crtc-misc-v1-9-1f8e0770798b@cerno.tech


Signed-off-by: default avatarMaxime Ripard <maxime@cerno.tech>
parent 92c17d16

drivers/gpu/drm/vc4/vc4_plane.c

+14 −6
Original line number Diff line number Diff line
@@ -65,11 +65,13 @@ static const struct hvs_format { 
		.drm = DRM_FORMAT_RGB565,

		.hvs = HVS_PIXEL_FORMAT_RGB565,

		.pixel_order = HVS_PIXEL_ORDER_XRGB,

		.pixel_order_hvs5 = HVS_PIXEL_ORDER_XRGB,

	},

	{

		.drm = DRM_FORMAT_BGR565,

		.hvs = HVS_PIXEL_FORMAT_RGB565,

		.pixel_order = HVS_PIXEL_ORDER_XBGR,

		.pixel_order_hvs5 = HVS_PIXEL_ORDER_XBGR,

	},

	{

		.drm = DRM_FORMAT_ARGB1555,
@@ -87,56 +89,67 @@ static const struct hvs_format { 
		.drm = DRM_FORMAT_RGB888,

		.hvs = HVS_PIXEL_FORMAT_RGB888,

		.pixel_order = HVS_PIXEL_ORDER_XRGB,

		.pixel_order_hvs5 = HVS_PIXEL_ORDER_XRGB,

	},

	{

		.drm = DRM_FORMAT_BGR888,

		.hvs = HVS_PIXEL_FORMAT_RGB888,

		.pixel_order = HVS_PIXEL_ORDER_XBGR,

		.pixel_order_hvs5 = HVS_PIXEL_ORDER_XBGR,

	},

	{

		.drm = DRM_FORMAT_YUV422,

		.hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE,

		.pixel_order = HVS_PIXEL_ORDER_XYCBCR,

		.pixel_order_hvs5 = HVS_PIXEL_ORDER_XYCBCR,

	},

	{

		.drm = DRM_FORMAT_YVU422,

		.hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE,

		.pixel_order = HVS_PIXEL_ORDER_XYCRCB,

		.pixel_order_hvs5 = HVS_PIXEL_ORDER_XYCRCB,

	},

	{

		.drm = DRM_FORMAT_YUV420,

		.hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE,

		.pixel_order = HVS_PIXEL_ORDER_XYCBCR,

		.pixel_order_hvs5 = HVS_PIXEL_ORDER_XYCBCR,

	},

	{

		.drm = DRM_FORMAT_YVU420,

		.hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE,

		.pixel_order = HVS_PIXEL_ORDER_XYCRCB,

		.pixel_order_hvs5 = HVS_PIXEL_ORDER_XYCRCB,

	},

	{

		.drm = DRM_FORMAT_NV12,

		.hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE,

		.pixel_order = HVS_PIXEL_ORDER_XYCBCR,

		.pixel_order_hvs5 = HVS_PIXEL_ORDER_XYCBCR,

	},

	{

		.drm = DRM_FORMAT_NV21,

		.hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE,

		.pixel_order = HVS_PIXEL_ORDER_XYCRCB,

		.pixel_order_hvs5 = HVS_PIXEL_ORDER_XYCRCB,

	},

	{

		.drm = DRM_FORMAT_NV16,

		.hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE,

		.pixel_order = HVS_PIXEL_ORDER_XYCBCR,

		.pixel_order_hvs5 = HVS_PIXEL_ORDER_XYCBCR,

	},

	{

		.drm = DRM_FORMAT_NV61,

		.hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE,

		.pixel_order = HVS_PIXEL_ORDER_XYCRCB,

		.pixel_order_hvs5 = HVS_PIXEL_ORDER_XYCRCB,

	},

	{

		.drm = DRM_FORMAT_P030,

		.hvs = HVS_PIXEL_FORMAT_YCBCR_10BIT,

		.pixel_order = HVS_PIXEL_ORDER_XYCBCR,

		.pixel_order_hvs5 = HVS_PIXEL_ORDER_XYCBCR,

		.hvs5_only = true,

	},

	{
@@ -1031,15 +1044,10 @@ static int vc4_plane_mode_set(struct drm_plane *plane, 
		vc4_dlist_write(vc4_state, 0xc0c0c0c0);



	} else {

		u32 hvs_pixel_order = format->pixel_order;



		if (format->pixel_order_hvs5)

			hvs_pixel_order = format->pixel_order_hvs5;



		/* Control word */

		vc4_dlist_write(vc4_state,

				SCALER_CTL0_VALID |

				(hvs_pixel_order << SCALER_CTL0_ORDER_SHIFT) |

				(format->pixel_order_hvs5 << SCALER_CTL0_ORDER_SHIFT) |

				(hvs_format << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |

				VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) |

				(vc4_state->is_unity ?