Commit 02b0bb51 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'stmmac-intel-cleanups' 



Wong Vee Khee says:

====================
stmmac: intel: minor clean-up

This patch series include two minor-cleanup patches:

  1. Move all the hardcoded DEFINEs to dwmac-intel header file.
  2. Fix the wrong kernel-doc on the intel_eth_pci_remove() function.

Since the changes are minor, only basic sanity tests are done on a
Intel TigerLake with Marvell88E2110 PHY:-

  - Link is up and able to perform ping.
  - phc2sys and ptp4l are running without errors.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents bf75213f 3c3ea630

drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c

+1 −17
Original line number Diff line number Diff line
@@ -10,22 +10,6 @@ 
#include "stmmac.h"

#include "stmmac_ptp.h"



#define INTEL_MGBE_ADHOC_ADDR	0x15

#define INTEL_MGBE_XPCS_ADDR	0x16



/* Selection for PTP Clock Freq belongs to PSE & PCH GbE */

#define PSE_PTP_CLK_FREQ_MASK		(GMAC_GPO0 | GMAC_GPO3)

#define PSE_PTP_CLK_FREQ_19_2MHZ	(GMAC_GPO0)

#define PSE_PTP_CLK_FREQ_200MHZ		(GMAC_GPO0 | GMAC_GPO3)

#define PSE_PTP_CLK_FREQ_256MHZ		(0)

#define PCH_PTP_CLK_FREQ_MASK		(GMAC_GPO0)

#define PCH_PTP_CLK_FREQ_19_2MHZ	(GMAC_GPO0)

#define PCH_PTP_CLK_FREQ_200MHZ		(0)



/* Cross-timestamping defines */

#define ART_CPUID_LEAF		0x15

#define EHL_PSE_ART_MHZ		19200000



struct intel_priv_data {

	int mdio_adhoc_addr;	/* mdio address for serdes & etc */

	unsigned long crossts_adj;
@@ -1103,7 +1087,7 @@ static int intel_eth_pci_probe(struct pci_dev *pdev, 
/**

 * intel_eth_pci_remove

 *

 * @pdev: platform device pointer

 * @pdev: pci device pointer

 * Description: this function calls the main to free the net resources

 * and releases the PCI resources.

 */

drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h

+16 −0
Original line number Diff line number Diff line
@@ -34,4 +34,20 @@ 
#define SERDES_RATE_PCIE_SHIFT	8

#define SERDES_PCLK_SHIFT	12



#define INTEL_MGBE_ADHOC_ADDR	0x15

#define INTEL_MGBE_XPCS_ADDR	0x16



/* Cross-timestamping defines */

#define ART_CPUID_LEAF		0x15

#define EHL_PSE_ART_MHZ		19200000



/* Selection for PTP Clock Freq belongs to PSE & PCH GbE */

#define PSE_PTP_CLK_FREQ_MASK		(GMAC_GPO0 | GMAC_GPO3)

#define PSE_PTP_CLK_FREQ_19_2MHZ	(GMAC_GPO0)

#define PSE_PTP_CLK_FREQ_200MHZ		(GMAC_GPO0 | GMAC_GPO3)

#define PSE_PTP_CLK_FREQ_256MHZ		(0)

#define PCH_PTP_CLK_FREQ_MASK		(GMAC_GPO0)

#define PCH_PTP_CLK_FREQ_19_2MHZ	(GMAC_GPO0)

#define PCH_PTP_CLK_FREQ_200MHZ		(0)



#endif /* __DWMAC_INTEL_H__ */