Commit 0037c30a authored by Michael Walle's avatar Michael Walle Committed by Rob Herring
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dt-bindings: interrupt-controller: fsl,ls-extirq: convert to YAML 



Convert the fsl,ls-extirq binding to the new YAML format.

In contrast to the original binding documentation, there are three
compatibles which are used in their corresponding device trees which
have a specific compatible and the (already documented) fallback
compatible:
 - "fsl,ls1046a-extirq", "fsl,ls1043a-extirq"
 - "fsl,ls2080a-extirq", "fsl,ls1088a-extirq"
 - "fsl,lx2160a-extirq", "fsl,ls1088a-extirq"

Depending on the number of the number of the external IRQs which is
usually 12 except for the LS1021A where there are only 6, the
interrupt-map-mask was reduced from 0xffffffff to 0xf and 0x7
respectively and the number of interrupt-map entries have to
match.

Signed-off-by: default avatarMichael Walle <michael@walle.cc>
Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: default avatarRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220427075338.1156449-4-michael@walle.cc
parent 4ae547ce

Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt

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* Freescale Layerscape external IRQs



Some Layerscape SOCs (LS1021A, LS1043A, LS1046A

LS1088A, LS208xA, LX216xA) support inverting

the polarity of certain external interrupt lines.



The device node must be a child of the node representing the

Supplemental Configuration Unit (SCFG).



Required properties:

- compatible: should be "fsl,<soc-name>-extirq", e.g. "fsl,ls1021a-extirq".

  "fsl,ls1043a-extirq": for LS1043A, LS1046A.

  "fsl,ls1088a-extirq": for LS1088A, LS208xA, LX216xA.

- #interrupt-cells: Must be 2. The first element is the index of the

  external interrupt line. The second element is the trigger type.

- #address-cells: Must be 0.

- interrupt-controller: Identifies the node as an interrupt controller

- reg: Specifies the Interrupt Polarity Control Register (INTPCR) in

  the SCFG or the External Interrupt Control Register (IRQCR) in

  the ISC.

- interrupt-map: Specifies the mapping from external interrupts to GIC

  interrupts.

- interrupt-map-mask: Must be <0xffffffff 0>.



Example:

	scfg: scfg@1570000 {

		compatible = "fsl,ls1021a-scfg", "syscon";

		reg = <0x0 0x1570000 0x0 0x10000>;

		big-endian;

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x0 0x0 0x1570000 0x10000>;



		extirq: interrupt-controller@1ac {

			compatible = "fsl,ls1021a-extirq";

			#interrupt-cells = <2>;

			#address-cells = <0>;

			interrupt-controller;

			reg = <0x1ac 4>;

			interrupt-map =

				<0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,

				<1 0 &gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,

				<2 0 &gic GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,

				<3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,

				<4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,

				<5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-map-mask = <0xffffffff 0x0>;

		};

	};





	interrupts-extended = <&gic GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,

			      <&extirq 1 IRQ_TYPE_LEVEL_LOW>;

Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/interrupt-controller/fsl,ls-extirq.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Freescale Layerscape External Interrupt Controller



maintainers:

  - Shawn Guo <shawnguo@kernel.org>

  - Li Yang <leoyang.li@nxp.com>



description: |

  Some Layerscape SOCs (LS1021A, LS1043A, LS1046A LS1088A, LS208xA,

  LX216xA) support inverting the polarity of certain external interrupt

  lines.



properties:

  compatible:

    oneOf:

      - enum:

          - fsl,ls1021a-extirq

          - fsl,ls1043a-extirq

          - fsl,ls1088a-extirq

      - items:

          - enum:

              - fsl,ls1046a-extirq

          - const: fsl,ls1043a-extirq

      - items:

          - enum:

              - fsl,ls2080a-extirq

              - fsl,lx2160a-extirq

          - const: fsl,ls1088a-extirq



  '#interrupt-cells':

    const: 2



  '#address-cells':

    const: 0



  interrupt-controller: true



  reg:

    maxItems: 1

    description:

      Specifies the Interrupt Polarity Control Register (INTPCR) in the

      SCFG or the External Interrupt Control Register (IRQCR) in the ISC.



  interrupt-map:

    description: Specifies the mapping from external interrupts to GIC interrupts.



  interrupt-map-mask: true



required:

  - compatible

  - '#interrupt-cells'

  - '#address-cells'

  - interrupt-controller

  - reg

  - interrupt-map

  - interrupt-map-mask



allOf:

  - if:

      properties:

        compatible:

          contains:

            enum:

              - fsl,ls1021a-extirq

    then:

      properties:

        interrupt-map:

          minItems: 6

          maxItems: 6

        interrupt-map-mask:

          items:

            - const: 0x7

            - const: 0

  - if:

      properties:

        compatible:

          contains:

            enum:

              - fsl,ls1043a-extirq

              - fsl,ls1046a-extirq

              - fsl,ls1088a-extirq

              - fsl,ls2080a-extirq

              - fsl,lx2160a-extirq

    then:

      properties:

        interrupt-map:

          minItems: 12

          maxItems: 12

        interrupt-map-mask:

          items:

            - const: 0xf

            - const: 0



additionalProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    interrupt-controller@1ac {

            compatible = "fsl,ls1021a-extirq";

            #interrupt-cells = <2>;

            #address-cells = <0>;

            interrupt-controller;

            reg = <0x1ac 4>;

            interrupt-map =

                    <0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,

                    <1 0 &gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,

                    <2 0 &gic GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,

                    <3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,

                    <4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,

                    <5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;

            interrupt-map-mask = <0x7 0x0>;

    };