Commit 4ae547ce authored by Yassine Oudjana's avatar Yassine Oudjana Committed by Rob Herring
Browse files

dt-bindings: arm: mediatek: infracfg: Convert to DT schema 



Convert infracfg bindings to DT schema format. Not all drivers
currently implement resets, so #reset-cells is made a required
property only for those that do. Using power-controller in the
example node name makes #power-domain-cells required causing
a dt_binding_check error. To solve this, the node is renamed to
syscon@10001000.

Signed-off-by: default avatarYassine Oudjana <y.oudjana@protonmail.com>
Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: default avatarRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220424084647.76577-4-y.oudjana@protonmail.com
parent 16a14673

Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt

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Mediatek infracfg controller

============================



The Mediatek infracfg controller provides various clocks and reset

outputs to the system.



Required Properties:



- compatible: Should be one of:

	- "mediatek,mt2701-infracfg", "syscon"

	- "mediatek,mt2712-infracfg", "syscon"

	- "mediatek,mt6765-infracfg", "syscon"

	- "mediatek,mt6779-infracfg_ao", "syscon"

	- "mediatek,mt6797-infracfg", "syscon"

	- "mediatek,mt7622-infracfg", "syscon"

	- "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon"

	- "mediatek,mt7629-infracfg", "syscon"

	- "mediatek,mt7986-infracfg", "syscon"

	- "mediatek,mt8135-infracfg", "syscon"

	- "mediatek,mt8167-infracfg", "syscon"

	- "mediatek,mt8173-infracfg", "syscon"

	- "mediatek,mt8183-infracfg", "syscon"

	- "mediatek,mt8516-infracfg", "syscon"

- #clock-cells: Must be 1

- #reset-cells: Must be 1



The infracfg controller uses the common clk binding from

Documentation/devicetree/bindings/clock/clock-bindings.txt

The available clocks are defined in dt-bindings/clock/mt*-clk.h.

Also it uses the common reset controller binding from

Documentation/devicetree/bindings/reset/reset.txt.

The available reset outputs are defined in

dt-bindings/reset/mt*-resets.h



Example:



infracfg: power-controller@10001000 {

	compatible = "mediatek,mt8173-infracfg", "syscon";

	reg = <0 0x10001000 0 0x1000>;

	#clock-cells = <1>;

	#reset-cells = <1>;

};

Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,infracfg.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: MediaTek Infrastructure System Configuration Controller



maintainers:

  - Matthias Brugger <matthias.bgg@gmail.com>



description:

  The Mediatek infracfg controller provides various clocks and reset outputs

  to the system. The clock values can be found in <dt-bindings/clock/mt*-clk.h>,

  and reset values in <dt-bindings/reset/mt*-reset.h> and

  <dt-bindings/reset/mt*-resets.h>.



properties:

  compatible:

    oneOf:

      - items:

          - enum:

              - mediatek,mt2701-infracfg

              - mediatek,mt2712-infracfg

              - mediatek,mt6765-infracfg

              - mediatek,mt6779-infracfg_ao

              - mediatek,mt6797-infracfg

              - mediatek,mt7622-infracfg

              - mediatek,mt7629-infracfg

              - mediatek,mt7986-infracfg

              - mediatek,mt8135-infracfg

              - mediatek,mt8167-infracfg

              - mediatek,mt8173-infracfg

              - mediatek,mt8183-infracfg

              - mediatek,mt8516-infracfg

          - const: syscon

      - items:

          - const: mediatek,mt7623-infracfg

          - const: mediatek,mt2701-infracfg

          - const: syscon



  reg:

    maxItems: 1



  '#clock-cells':

    const: 1



  '#reset-cells':

    const: 1



required:

  - compatible

  - reg

  - '#clock-cells'



if:

  properties:

    compatible:

      contains:

        enum:

          - mediatek,mt2701-infracfg

          - mediatek,mt2712-infracfg

          - mediatek,mt7622-infracfg

          - mediatek,mt7986-infracfg

          - mediatek,mt8135-infracfg

          - mediatek,mt8173-infracfg

          - mediatek,mt8183-infracfg

then:

  required:

    - '#reset-cells'



additionalProperties: false



examples:

  - |

    infracfg: clock-controller@10001000 {

        compatible = "mediatek,mt8173-infracfg", "syscon";

        reg = <0x10001000 0x1000>;

        #clock-cells = <1>;

        #reset-cells = <1>;

    };