Merge remote-tracking branch 'stable/linux-4.14.y' into rpi-4.14.y

# SPDX-License-Identifier: GPL-2.0

VERSION = 4

PATCHLEVEL = 14

SUBLEVEL = 69

SUBLEVEL = 70

EXTRAVERSION =

NAME = Petit Gorille

CONFIG_USB_CHIPIDEA=y

CONFIG_USB_CHIPIDEA_UDC=y

CONFIG_USB_CHIPIDEA_HOST=y

CONFIG_USB_CHIPIDEA_ULPI=y

CONFIG_USB_SERIAL=m

CONFIG_USB_SERIAL_GENERIC=y

CONFIG_USB_SERIAL_FTDI_SIO=m

CONFIG_USB_FUNCTIONFS=m

CONFIG_USB_MASS_STORAGE=m

CONFIG_USB_G_SERIAL=m

CONFIG_USB_ULPI_BUS=y

CONFIG_MMC=y

CONFIG_MMC_SDHCI=y

CONFIG_MMC_SDHCI_PLTFM=y

	select ARM_GLOBAL_TIMER

	select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK

	select ZONE_DMA if ARM_LPAE

	select PM

	help

	  Support for Rockchip's Cortex-A9 Single-to-Quad-Core-SoCs

	  containing the RK2928, RK30xx and RK31xx series.

	select GPIOLIB

	select PINCTRL

	select PINCTRL_ROCKCHIP

	select PM

	select ROCKCHIP_TIMER

	help

	  This enables support for the ARMv8 based Rockchip chipsets,

#define CTR_L1IP_SHIFT		14

#define CTR_L1IP_MASK		3

#define CTR_DMINLINE_SHIFT	16

#define CTR_IMINLINE_SHIFT	0

#define CTR_CWG_SHIFT		24

#define CTR_CWG_MASK		15

#define CTR_CACHE_MINLINE_MASK	\

	(0xf << CTR_DMINLINE_SHIFT | 0xf << CTR_IMINLINE_SHIFT)

#define CTR_L1IP(ctr)		(((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK)

#define ICACHE_POLICY_VPIPT	0