Commit f4daf06f authored by Will Deacon's avatar Will Deacon
Browse files

ARM: proc: add definition of cpu_reset for ARMv6 and ARMv7 cores 



This patch adds simple definitions of cpu_reset for ARMv6 and ARMv7
cores, which disable the MMU via the SCTLR.

Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent 14abd038

arch/arm/mm/proc-v6.S

+5 −0
Original line number Diff line number Diff line
@@ -56,6 +56,11 @@ ENTRY(cpu_v6_proc_fin) 
 */

	.align	5

ENTRY(cpu_v6_reset)

	mrc	p15, 0, r1, c1, c0, 0		@ ctrl register

	bic	r1, r1, #0x1			@ ...............m

	mcr	p15, 0, r1, c1, c0, 0		@ disable MMU

	mov	r1, #0

	mcr	p15, 0, r1, c7, c5, 4		@ ISB

	mov	pc, r0



/*

arch/arm/mm/proc-v7.S

+7 −0
Original line number Diff line number Diff line
@@ -58,9 +58,16 @@ ENDPROC(cpu_v7_proc_fin) 
 *	to what would be the reset vector.

 *

 *	- loc   - location to jump to for soft reset

 *

 *	This code must be executed using a flat identity mapping with

 *      caches disabled.

 */

	.align	5

ENTRY(cpu_v7_reset)

	mrc	p15, 0, r1, c1, c0, 0		@ ctrl register

	bic	r1, r1, #0x1			@ ...............m

	mcr	p15, 0, r1, c1, c0, 0		@ disable MMU

	isb

	mov	pc, r0

ENDPROC(cpu_v7_reset)