Loading arch/ia64/mm/fault.c +6 −3 Original line number Diff line number Diff line Loading @@ -209,10 +209,13 @@ ia64_do_page_fault (unsigned long address, unsigned long isr, struct pt_regs *re } no_context: if (isr & IA64_ISR_SP) { if ((isr & IA64_ISR_SP) || ((isr & IA64_ISR_NA) && (isr & IA64_ISR_CODE_MASK) == IA64_ISR_CODE_LFETCH)) { /* * This fault was due to a speculative load set the "ed" bit in the psr to * ensure forward progress (target register will get a NaT). * This fault was due to a speculative load or lfetch.fault, set the "ed" * bit in the psr to ensure forward progress. (Target register will get a * NaT for ld.s, lfetch will be canceled.) */ ia64_psr(regs)->ed = 1; return; Loading Loading
arch/ia64/mm/fault.c +6 −3 Original line number Diff line number Diff line Loading @@ -209,10 +209,13 @@ ia64_do_page_fault (unsigned long address, unsigned long isr, struct pt_regs *re } no_context: if (isr & IA64_ISR_SP) { if ((isr & IA64_ISR_SP) || ((isr & IA64_ISR_NA) && (isr & IA64_ISR_CODE_MASK) == IA64_ISR_CODE_LFETCH)) { /* * This fault was due to a speculative load set the "ed" bit in the psr to * ensure forward progress (target register will get a NaT). * This fault was due to a speculative load or lfetch.fault, set the "ed" * bit in the psr to ensure forward progress. (Target register will get a * NaT for ld.s, lfetch will be canceled.) */ ia64_psr(regs)->ed = 1; return; Loading