Loading arch/sparc/Kconfig +1 −0 Original line number Diff line number Diff line Loading @@ -55,6 +55,7 @@ config SPARC64 select PERF_USE_VMALLOC select IRQ_PREFLOW_FASTEOI select ARCH_HAVE_NMI_SAFE_CMPXCHG select HAVE_C_RECORDMCOUNT config ARCH_DEFCONFIG string Loading arch/sparc/include/asm/spinlock_32.h +9 −2 Original line number Diff line number Diff line Loading @@ -131,6 +131,15 @@ static inline void arch_write_lock(arch_rwlock_t *rw) *(volatile __u32 *)&lp->lock = ~0U; } static void inline arch_write_unlock(arch_rwlock_t *lock) { __asm__ __volatile__( " st %%g0, [%0]" : /* no outputs */ : "r" (lock) : "memory"); } static inline int arch_write_trylock(arch_rwlock_t *rw) { unsigned int val; Loading Loading @@ -175,8 +184,6 @@ static inline int __arch_read_trylock(arch_rwlock_t *rw) res; \ }) #define arch_write_unlock(rw) do { (rw)->lock = 0; } while(0) #define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock) #define arch_read_lock_flags(rw, flags) arch_read_lock(rw) #define arch_write_lock_flags(rw, flags) arch_write_lock(rw) Loading arch/sparc/include/asm/spinlock_64.h +0 −6 Original line number Diff line number Diff line Loading @@ -210,14 +210,8 @@ static int inline arch_write_trylock(arch_rwlock_t *lock) return result; } #define arch_read_lock(p) arch_read_lock(p) #define arch_read_lock_flags(p, f) arch_read_lock(p) #define arch_read_trylock(p) arch_read_trylock(p) #define arch_read_unlock(p) arch_read_unlock(p) #define arch_write_lock(p) arch_write_lock(p) #define arch_write_lock_flags(p, f) arch_write_lock(p) #define arch_write_unlock(p) arch_write_unlock(p) #define arch_write_trylock(p) arch_write_trylock(p) #define arch_read_can_lock(rw) (!((rw)->lock & 0x80000000UL)) #define arch_write_can_lock(rw) (!(rw)->lock) Loading Loading
arch/sparc/Kconfig +1 −0 Original line number Diff line number Diff line Loading @@ -55,6 +55,7 @@ config SPARC64 select PERF_USE_VMALLOC select IRQ_PREFLOW_FASTEOI select ARCH_HAVE_NMI_SAFE_CMPXCHG select HAVE_C_RECORDMCOUNT config ARCH_DEFCONFIG string Loading
arch/sparc/include/asm/spinlock_32.h +9 −2 Original line number Diff line number Diff line Loading @@ -131,6 +131,15 @@ static inline void arch_write_lock(arch_rwlock_t *rw) *(volatile __u32 *)&lp->lock = ~0U; } static void inline arch_write_unlock(arch_rwlock_t *lock) { __asm__ __volatile__( " st %%g0, [%0]" : /* no outputs */ : "r" (lock) : "memory"); } static inline int arch_write_trylock(arch_rwlock_t *rw) { unsigned int val; Loading Loading @@ -175,8 +184,6 @@ static inline int __arch_read_trylock(arch_rwlock_t *rw) res; \ }) #define arch_write_unlock(rw) do { (rw)->lock = 0; } while(0) #define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock) #define arch_read_lock_flags(rw, flags) arch_read_lock(rw) #define arch_write_lock_flags(rw, flags) arch_write_lock(rw) Loading
arch/sparc/include/asm/spinlock_64.h +0 −6 Original line number Diff line number Diff line Loading @@ -210,14 +210,8 @@ static int inline arch_write_trylock(arch_rwlock_t *lock) return result; } #define arch_read_lock(p) arch_read_lock(p) #define arch_read_lock_flags(p, f) arch_read_lock(p) #define arch_read_trylock(p) arch_read_trylock(p) #define arch_read_unlock(p) arch_read_unlock(p) #define arch_write_lock(p) arch_write_lock(p) #define arch_write_lock_flags(p, f) arch_write_lock(p) #define arch_write_unlock(p) arch_write_unlock(p) #define arch_write_trylock(p) arch_write_trylock(p) #define arch_read_can_lock(rw) (!((rw)->lock & 0x80000000UL)) #define arch_write_can_lock(rw) (!(rw)->lock) Loading