Commit d986d6f4 authored by Cyril Bur's avatar Cyril Bur Committed by Michael Ellerman
Browse files

powerpc: Remove do_load_up_transact_{fpu,altivec} 



Previous rework of TM code leaves these functions unused

Signed-off-by: default avatarCyril Bur <cyrilbur@gmail.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent 000ec280

arch/powerpc/include/asm/tm.h

+0 −5
Original line number Diff line number Diff line
@@ -9,11 +9,6 @@ 


#ifndef __ASSEMBLY__



#ifdef CONFIG_PPC_TRANSACTIONAL_MEM

extern void do_load_up_transact_fpu(struct thread_struct *thread);

extern void do_load_up_transact_altivec(struct thread_struct *thread);

#endif



extern void tm_enable(void);

extern void tm_reclaim(struct thread_struct *thread,

		       unsigned long orig_msr, uint8_t cause);

arch/powerpc/kernel/fpu.S

+0 −26
Original line number Diff line number Diff line
@@ -50,32 +50,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_VSX); \ 
#define REST_32FPVSRS(n,c,base) __REST_32FPVSRS(n,__REG_##c,__REG_##base)

#define SAVE_32FPVSRS(n,c,base) __SAVE_32FPVSRS(n,__REG_##c,__REG_##base)



#ifdef CONFIG_PPC_TRANSACTIONAL_MEM

/* void do_load_up_transact_fpu(struct thread_struct *thread)

 *

 * This is similar to load_up_fpu but for the transactional version of the FP

 * register set.  It doesn't mess with the task MSR or valid flags.

 * Furthermore, we don't do lazy FP with TM currently.

 */

_GLOBAL(do_load_up_transact_fpu)

	mfmsr	r6

	ori	r5,r6,MSR_FP

#ifdef CONFIG_VSX

BEGIN_FTR_SECTION

	oris	r5,r5,MSR_VSX@h

END_FTR_SECTION_IFSET(CPU_FTR_VSX)

#endif

	SYNC

	MTMSRD(r5)



	addi	r7,r3,THREAD_CKFPSTATE

	lfd	fr0,FPSTATE_FPSCR(r7)

	MTFSF_L(fr0)

	REST_32FPVSRS(0, R4, R7)



	blr

#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */



/*

 * Load state from memory into FP registers including FPSCR.

 * Assumes the caller has enabled FP in the MSR.

arch/powerpc/kernel/vector.S

+0 −25
Original line number Diff line number Diff line
@@ -7,31 +7,6 @@ 
#include <asm/page.h>

#include <asm/ptrace.h>



#ifdef CONFIG_PPC_TRANSACTIONAL_MEM

/* void do_load_up_transact_altivec(struct thread_struct *thread)

 *

 * This is similar to load_up_altivec but for the transactional version of the

 * vector regs.  It doesn't mess with the task MSR or valid flags.

 * Furthermore, VEC laziness is not supported with TM currently.

 */

_GLOBAL(do_load_up_transact_altivec)

	mfmsr	r6

	oris	r5,r6,MSR_VEC@h

	MTMSRD(r5)

	isync



	li	r4,1

	stw	r4,THREAD_USED_VR(r3)



	li	r10,THREAD_CKVRSTATE+VRSTATE_VSCR

	lvx	v0,r10,r3

	mtvscr	v0

	addi	r10,r3,THREAD_CKVRSTATE

	REST_32VRS(0,r4,r10)



	blr

#endif



/*

 * Load state from memory into VMX registers including VSCR.

 * Assumes the caller has enabled VMX in the MSR.