Commit d68a7454 authored by Nikola Cornij's avatar Nikola Cornij Committed by Alex Deucher
Browse files

drm/amd/display: Clear FEC_READY shadow register if DPCD write fails 



[why]
As a fail-safe, in case 'set FEC_READY' DPCD write fails, a HW shadow
register should be cleared and the internal FEC stat should be set to
'not ready'. This is to make sure HW settings will be consistent with
FEC_READY state on the RX.

Signed-off-by: default avatarNikola Cornij <nikola.cornij@amd.com>
Reviewed-by: default avatarJoshua Aberback <Joshua.Aberback@amd.com>
Acked-by: default avatarChris Park <Chris.Park@amd.com>
Acked-by: default avatarLeo Li <sunpeng.li@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent e752058b

drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

+2 −0
Original line number Diff line number Diff line
@@ -3174,6 +3174,8 @@ void dp_set_fec_ready(struct dc_link *link, bool ready) 
				link_enc->funcs->fec_set_ready(link_enc, true);

				link->fec_state = dc_link_fec_ready;

			} else {

				link->link_enc->funcs->fec_set_ready(link->link_enc, false);

				link->fec_state = dc_link_fec_not_ready;

				dm_error("dpcd write failed to set fec_ready");

			}

		} else if (link->fec_state == dc_link_fec_ready) {