Commit cea46462 authored by Matt Carlson's avatar Matt Carlson Committed by David S. Miller
Browse files

tg3: Disable CLKREQ in L2 



This patch disables CLKREQ in L2 to workaround a chipset bug.

Signed-off-by: default avatarMatt Carlson <mcarlson@broadcom.com>
Reviewed-by: default avatarMichael Chan <mchan@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent b6c6712a

drivers/net/tg3.c

+14 −0
Original line number Diff line number Diff line
@@ -7642,6 +7642,20 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) 
		tw32(GRC_MODE, grc_mode);

	}



	if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {

		u32 grc_mode = tr32(GRC_MODE);



		/* Access the lower 1K of PL PCIE block registers. */

		val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;

		tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);



		val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5);

		tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,

		     val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);



		tw32(GRC_MODE, grc_mode);

	}



	/* This works around an issue with Athlon chipsets on

	 * B3 tigon3 silicon.  This bit has no effect on any

	 * other revision.  But do not set this on PCI Express

drivers/net/tg3.h

+2 −0
Original line number Diff line number Diff line
@@ -1854,6 +1854,8 @@ 
#define TG3_PCIE_TLDLPL_PORT		0x00007c00

#define TG3_PCIE_PL_LO_PHYCTL1		 0x00000004

#define TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN	  0x00001000

#define TG3_PCIE_PL_LO_PHYCTL5		 0x00000014

#define TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ	  0x80000000



/* OTP bit definitions */

#define TG3_OTP_AGCTGT_MASK		0x000000e0