Commit ccaae273 authored by Tony Lindgren's avatar Tony Lindgren
Browse files

Merge branch 'pm-fixes' of... 

Merge branch 'pm-fixes' of master.kernel.org:/pub/scm/linux/kernel/git/khilman/linux-omap-pm into omap-fixes-for-linus
parents fa8d1d6c 6b34f9d4

arch/arm/mach-omap2/cpuidle34xx.c

+1 −1
Original line number Diff line number Diff line
@@ -137,7 +137,7 @@ return_sleep_time: 
	local_irq_enable();

	local_fiq_enable();



	return (u32)timespec_to_ns(&ts_idle)/1000;

	return ts_idle.tv_nsec / NSEC_PER_USEC + ts_idle.tv_sec * USEC_PER_SEC;

}



/**

arch/arm/mach-omap2/irq.c

+18 −0
Original line number Diff line number Diff line
@@ -274,4 +274,22 @@ void omap_intc_restore_context(void) 
	}

	/* MIRs are saved and restore with other PRCM registers */

}



void omap3_intc_suspend(void)

{

	/* A pending interrupt would prevent OMAP from entering suspend */

	omap_ack_irq(0);

}



void omap3_intc_prepare_idle(void)

{

	/* Disable autoidle as it can stall interrupt controller */

	intc_bank_write_reg(0, &irq_banks[0], INTC_SYSCONFIG);

}



void omap3_intc_resume_idle(void)

{

	/* Re-enable autoidle */

	intc_bank_write_reg(1, &irq_banks[0], INTC_SYSCONFIG);

}

#endif /* CONFIG_ARCH_OMAP3 */

arch/arm/mach-omap2/pm-debug.c

+6 −6
Original line number Diff line number Diff line
@@ -54,8 +54,6 @@ int omap2_pm_debug; 
	regs[reg_count++].val = \

			 __raw_readl(OMAP2_L4_IO_ADDRESS(0x480fe000 + (off)))



static int __init pm_dbg_init(void);



void omap2_pm_dump(int mode, int resume, unsigned int us)

{

	struct reg {
@@ -167,6 +165,8 @@ struct dentry *pm_dbg_dir; 


static int pm_dbg_init_done;



static int __init pm_dbg_init(void);



enum {

	DEBUG_FILE_COUNTERS = 0,

	DEBUG_FILE_TIMERS,
@@ -488,9 +488,11 @@ int pm_dbg_regset_init(int reg_set) 


static int pwrdm_suspend_get(void *data, u64 *val)

{

	*val = omap3_pm_get_suspend_state((struct powerdomain *)data);

	int ret;

	ret = omap3_pm_get_suspend_state((struct powerdomain *)data);

	*val = ret;



	if (*val >= 0)

	if (ret >= 0)

		return 0;

	return *val;

}
@@ -604,6 +606,4 @@ static int __init pm_dbg_init(void) 
}

arch_initcall(pm_dbg_init);



#else

void pm_dbg_update_time(struct powerdomain *pwrdm, int prev) {}

#endif

arch/arm/mach-omap2/pm.h

+6 −2
Original line number Diff line number Diff line
@@ -32,12 +32,16 @@ extern struct omap_dm_timer *gptimer_wakeup; 
#ifdef CONFIG_PM_DEBUG

extern void omap2_pm_dump(int mode, int resume, unsigned int us);

extern int omap2_pm_debug;

#else

#define omap2_pm_dump(mode, resume, us)		do {} while (0);

#define omap2_pm_debug				0

#endif



#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)

extern void pm_dbg_update_time(struct powerdomain *pwrdm, int prev);

extern int pm_dbg_regset_save(int reg_set);

extern int pm_dbg_regset_init(int reg_set);

#else

#define omap2_pm_dump(mode, resume, us)		do {} while (0);

#define omap2_pm_debug				0

#define pm_dbg_update_time(pwrdm, prev) do {} while (0);

#define pm_dbg_regset_save(reg_set) do {} while (0);

#define pm_dbg_regset_init(reg_set) do {} while (0);

arch/arm/mach-omap2/pm34xx.c

+26 −21
Original line number Diff line number Diff line
@@ -26,6 +26,7 @@ 
#include <linux/err.h>

#include <linux/gpio.h>

#include <linux/clk.h>

#include <linux/delay.h>



#include <plat/sram.h>

#include <plat/clockdomain.h>
@@ -126,7 +127,15 @@ static void omap3_core_save_context(void) 
	/* wait for the save to complete */

	while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)

			& PADCONF_SAVE_DONE))

		;

		udelay(1);



	/*

	 * Force write last pad into memory, as this can fail in some

	 * cases according to erratas 1.157, 1.185

	 */

	omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),

		OMAP343X_CONTROL_MEM_WKUP + 0x2a0);



	/* Save the Interrupt controller context */

	omap_intc_save_context();

	/* Save the GPMC context */
@@ -392,6 +401,7 @@ void omap_sram_idle(void) 
		prm_set_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);

		omap3_enable_io_chain();

	}

	omap3_intc_prepare_idle();



	/*

	* On EMU/HS devices ROM code restores a SRDC value
@@ -438,6 +448,7 @@ void omap_sram_idle(void) 
					       OMAP3430_GR_MOD,

					       OMAP3_PRM_VOLTCTRL_OFFSET);

	}

	omap3_intc_resume_idle();



	/* PER */

	if (per_next_state < PWRDM_POWER_ON) {
@@ -578,6 +589,8 @@ static int omap3_pm_suspend(void) 
	}



	omap_uart_prepare_suspend();

	omap3_intc_suspend();



	omap_sram_idle();



restore:
@@ -835,6 +848,8 @@ static void __init prcm_setup_regs(void) 
			CM_AUTOIDLE);

	}



	omap_ctrl_writel(OMAP3430_AUTOIDLE, OMAP2_CONTROL_SYSCONFIG);



	/*

	 * Set all plls to autoidle. This is needed until autoidle is

	 * enabled by clockfw
@@ -875,15 +890,23 @@ static void __init prcm_setup_regs(void) 
	prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN,

			  OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);



	/* Enable PM_WKEN to support DSS LPR */

	prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS,

				OMAP3430_DSS_MOD, PM_WKEN);



	/* Enable wakeups in PER */

	prm_write_mod_reg(OMAP3430_EN_GPIO2 | OMAP3430_EN_GPIO3 |

			  OMAP3430_EN_GPIO4 | OMAP3430_EN_GPIO5 |

			  OMAP3430_EN_GPIO6 | OMAP3430_EN_UART3,

			  OMAP3430_EN_GPIO6 | OMAP3430_EN_UART3 |

			  OMAP3430_EN_MCBSP2 | OMAP3430_EN_MCBSP3 |

			  OMAP3430_EN_MCBSP4,

			  OMAP3430_PER_MOD, PM_WKEN);

	/* and allow them to wake up MPU */

	prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2 | OMAP3430_EN_GPIO3 |

			  OMAP3430_GRPSEL_GPIO4 | OMAP3430_EN_GPIO5 |

			  OMAP3430_GRPSEL_GPIO6 | OMAP3430_EN_UART3,

			  OMAP3430_GRPSEL_GPIO6 | OMAP3430_EN_UART3 |

			  OMAP3430_EN_MCBSP2 | OMAP3430_EN_MCBSP3 |

			  OMAP3430_EN_MCBSP4,

			  OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);



	/* Don't attach IVA interrupts */
@@ -904,24 +927,6 @@ static void __init prcm_setup_regs(void) 
	/* Clear any pending PRCM interrupts */

	prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);



	/* Don't attach IVA interrupts */

	prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);

	prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);

	prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);

	prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);



	/* Clear any pending 'reset' flags */

	prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);

	prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);

	prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);

	prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);

	prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);

	prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);

	prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);



	/* Clear any pending PRCM interrupts */

	prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);



	omap3_iva_idle();

	omap3_d2d_idle();

}