From c2eaacd30565604bbf776ca6e83c9889ea87ea74 Mon Sep 17 00:00:00 2001
From: popcornmix <popcornmix@gmail.com>
Date: Tue, 17 Jan 2012 19:14:08 +0000
Subject: [PATCH] Add dwc_otg driver

Signed-off-by: popcornmix <popcornmix@gmail.com>
---
 drivers/usb/Makefile                          |    1 +
 drivers/usb/core/generic.c                    |    1 +
 drivers/usb/core/hub.c                        |   52 +-
 drivers/usb/core/message.c                    |   79 +
 drivers/usb/core/otg_whitelist.h              |  172 +-
 drivers/usb/gadget/Kconfig                    |   28 +
 drivers/usb/gadget/file_storage.c             |   70 +-
 drivers/usb/host/Kconfig                      |   13 +
 drivers/usb/host/Makefile                     |    2 +
 drivers/usb/host/dwc_common_port/Makefile     |   44 +
 .../usb/host/dwc_common_port/Makefile.linux   |   36 +
 .../usb/host/dwc_common_port/doc/doxygen.cfg  |  270 +
 .../dir_c13d72e45af28cdc461a5f284d3d36fc.html |   81 +
 .../host/dwc_common_port/doc/html/dirs.html   |   22 +
 .../host/dwc_common_port/doc/html/doxygen.css |  358 ++
 .../dwc_common_port/doc/html/dwc__cc_8h.html  |  709 +++
 .../doc/html/dwc__crypto_8c.html              |  435 ++
 .../doc/html/dwc__crypto_8h.html              |  618 ++
 .../dwc_common_port/doc/html/dwc__dh_8h.html  |  166 +
 .../doc/html/dwc__list_8h.html                | 1844 ++++++
 .../doc/html/dwc__modpow_8h.html              |   48 +
 .../doc/html/dwc__notifier_8h.html            |  306 +
 .../dwc_common_port/doc/html/dwc__os_8h.html  | 3090 ++++++++++
 .../host/dwc_common_port/doc/html/files.html  |   34 +
 .../dwc_common_port/doc/html/globals.html     |  163 +
 .../doc/html/globals_defs.html                |   41 +
 .../doc/html/globals_func.html                |  153 +
 .../doc/html/globals_type.html                |   41 +
 .../host/dwc_common_port/doc/html/index.html  |    8 +
 .../host/dwc_common_port/doc/html/main.html   |   45 +
 .../host/dwc_common_port/doc/html/pages.html  |   23 +
 .../host/dwc_common_port/doc/html/tabs.css    |  102 +
 .../host/dwc_common_port/doc/html/todo.html   |   23 +
 .../host/dwc_common_port/doc/html/tree.html   |   90 +
 drivers/usb/host/dwc_common_port/dwc_cc.c     |  506 ++
 drivers/usb/host/dwc_common_port/dwc_cc.h     |  209 +
 .../host/dwc_common_port/dwc_common_linux.c   | 1247 ++++
 drivers/usb/host/dwc_common_port/dwc_crypto.c |  306 +
 drivers/usb/host/dwc_common_port/dwc_crypto.h |  103 +
 drivers/usb/host/dwc_common_port/dwc_dh.c     |  286 +
 drivers/usb/host/dwc_common_port/dwc_dh.h     |   98 +
 drivers/usb/host/dwc_common_port/dwc_list.h   |  616 ++
 drivers/usb/host/dwc_common_port/dwc_mem.c    |  172 +
 drivers/usb/host/dwc_common_port/dwc_modpow.c |  622 ++
 drivers/usb/host/dwc_common_port/dwc_modpow.h |   26 +
 .../usb/host/dwc_common_port/dwc_notifier.c   |  256 +
 .../usb/host/dwc_common_port/dwc_notifier.h   |  112 +
 drivers/usb/host/dwc_common_port/dwc_os.h     |  924 +++
 drivers/usb/host/dwc_common_port/usb.h        |  850 +++
 drivers/usb/host/dwc_otg/Makefile             |   78 +
 drivers/usb/host/dwc_otg/doc/doxygen.cfg      |  224 +
 .../usb/host/dwc_otg/doc/html/annotated.html  |  120 +
 drivers/usb/host/dwc_otg/doc/html/doxygen.css |  358 ++
 .../doc/html/dummy__audio_8c-source.html      | 1550 +++++
 .../doc/html/dwc__cfi__common_8h-source.html  |  115 +
 .../dwc_otg/doc/html/dwc__cfi__common_8h.html |  119 +
 .../doc/html/dwc__otg__attr_8c-source.html    |  828 +++
 .../dwc_otg/doc/html/dwc__otg__attr_8c.html   |  485 ++
 .../doc/html/dwc__otg__attr_8h-source.html    |  105 +
 .../dwc_otg/doc/html/dwc__otg__attr_8h.html   |  116 +
 .../doc/html/dwc__otg__cfi_8c-source.html     | 1724 ++++++
 .../dwc_otg/doc/html/dwc__otg__cfi_8c.html    |   36 +
 .../doc/html/dwc__otg__cfi_8h-source.html     |  299 +
 .../dwc_otg/doc/html/dwc__otg__cfi_8h.html    |  302 +
 .../doc/html/dwc__otg__cil_8c-source.html     | 4922 +++++++++++++++
 .../dwc_otg/doc/html/dwc__otg__cil_8c.html    | 3103 ++++++++++
 .../doc/html/dwc__otg__cil_8h-source.html     |  709 +++
 .../dwc_otg/doc/html/dwc__otg__cil_8h.html    | 1844 ++++++
 .../html/dwc__otg__cil__intr_8c-source.html   |  742 +++
 .../doc/html/dwc__otg__cil__intr_8c.html      |  645 ++
 .../html/dwc__otg__core__if_8h-source.html    |  365 ++
 .../doc/html/dwc__otg__core__if_8h.html       | 1730 ++++++
 .../doc/html/dwc__otg__dbg_8h-source.html     |  100 +
 .../dwc_otg/doc/html/dwc__otg__dbg_8h.html    |  133 +
 .../doc/html/dwc__otg__driver_8c-source.html  | 1079 ++++
 .../dwc_otg/doc/html/dwc__otg__driver_8c.html |  719 +++
 .../doc/html/dwc__otg__driver_8h-source.html  |  110 +
 .../dwc_otg/doc/html/dwc__otg__driver_8h.html |   50 +
 .../doc/html/dwc__otg__hcd_8c-source.html     | 2946 +++++++++
 .../dwc_otg/doc/html/dwc__otg__hcd_8c.html    | 1837 ++++++
 .../doc/html/dwc__otg__hcd_8h-source.html     |  517 ++
 .../dwc_otg/doc/html/dwc__otg__hcd_8h.html    | 1310 ++++
 .../html/dwc__otg__hcd__ddma_8c-source.html   | 1070 ++++
 .../doc/html/dwc__otg__hcd__ddma_8c.html      |  311 +
 .../doc/html/dwc__otg__hcd__if_8h-source.html |  191 +
 .../doc/html/dwc__otg__hcd__if_8h.html        | 1381 +++++
 .../html/dwc__otg__hcd__intr_8c-source.html   | 1873 ++++++
 .../doc/html/dwc__otg__hcd__intr_8c.html      | 1252 ++++
 .../html/dwc__otg__hcd__linux_8c-source.html  |  726 +++
 .../doc/html/dwc__otg__hcd__linux_8c.html     |  514 ++
 .../html/dwc__otg__hcd__queue_8c-source.html  |  633 ++
 .../doc/html/dwc__otg__hcd__queue_8c.html     |  667 ++
 .../doc/html/dwc__otg__pcd_8c-source.html     | 1851 ++++++
 .../dwc_otg/doc/html/dwc__otg__pcd_8c.html    | 1343 ++++
 .../doc/html/dwc__otg__pcd_8h-source.html     |  171 +
 .../dwc_otg/doc/html/dwc__otg__pcd_8h.html    |  254 +
 .../doc/html/dwc__otg__pcd__if_8h-source.html |  174 +
 .../doc/html/dwc__otg__pcd__if_8h.html        |  976 +++
 .../html/dwc__otg__pcd__intr_8c-source.html   | 3629 +++++++++++
 .../doc/html/dwc__otg__pcd__intr_8c.html      | 1599 +++++
 .../html/dwc__otg__pcd__linux_8c-source.html  |  997 +++
 .../doc/html/dwc__otg__pcd__linux_8c.html     |  796 +++
 .../doc/html/dwc__otg__regs_8h-source.html    | 1260 ++++
 .../dwc_otg/doc/html/dwc__otg__regs_8h.html   | 1468 +++++
 drivers/usb/host/dwc_otg/doc/html/files.html  |   52 +
 .../usb/host/dwc_otg/doc/html/functions.html  |   82 +
 .../host/dwc_otg/doc/html/functions_0x62.html |   99 +
 .../host/dwc_otg/doc/html/functions_0x63.html |  110 +
 .../host/dwc_otg/doc/html/functions_0x64.html |  158 +
 .../host/dwc_otg/doc/html/functions_0x65.html |  109 +
 .../host/dwc_otg/doc/html/functions_0x66.html |   81 +
 .../host/dwc_otg/doc/html/functions_0x67.html |   95 +
 .../host/dwc_otg/doc/html/functions_0x68.html |  119 +
 .../host/dwc_otg/doc/html/functions_0x69.html |  121 +
 .../host/dwc_otg/doc/html/functions_0x6c.html |   74 +
 .../host/dwc_otg/doc/html/functions_0x6d.html |   79 +
 .../host/dwc_otg/doc/html/functions_0x6e.html |   99 +
 .../host/dwc_otg/doc/html/functions_0x6f.html |  101 +
 .../host/dwc_otg/doc/html/functions_0x70.html |  144 +
 .../host/dwc_otg/doc/html/functions_0x71.html |   71 +
 .../host/dwc_otg/doc/html/functions_0x72.html |  141 +
 .../host/dwc_otg/doc/html/functions_0x73.html |  128 +
 .../host/dwc_otg/doc/html/functions_0x74.html |   88 +
 .../host/dwc_otg/doc/html/functions_0x75.html |   78 +
 .../host/dwc_otg/doc/html/functions_0x76.html |   65 +
 .../host/dwc_otg/doc/html/functions_0x77.html |   79 +
 .../host/dwc_otg/doc/html/functions_0x78.html |   77 +
 .../host/dwc_otg/doc/html/functions_func.html |   36 +
 .../host/dwc_otg/doc/html/functions_vars.html |   82 +
 .../dwc_otg/doc/html/functions_vars_0x62.html |   99 +
 .../dwc_otg/doc/html/functions_vars_0x63.html |  110 +
 .../dwc_otg/doc/html/functions_vars_0x64.html |  157 +
 .../dwc_otg/doc/html/functions_vars_0x65.html |  109 +
 .../dwc_otg/doc/html/functions_vars_0x66.html |   81 +
 .../dwc_otg/doc/html/functions_vars_0x67.html |   95 +
 .../dwc_otg/doc/html/functions_vars_0x68.html |  119 +
 .../dwc_otg/doc/html/functions_vars_0x69.html |  121 +
 .../dwc_otg/doc/html/functions_vars_0x6c.html |   74 +
 .../dwc_otg/doc/html/functions_vars_0x6d.html |   79 +
 .../dwc_otg/doc/html/functions_vars_0x6e.html |   99 +
 .../dwc_otg/doc/html/functions_vars_0x6f.html |  101 +
 .../dwc_otg/doc/html/functions_vars_0x70.html |  144 +
 .../dwc_otg/doc/html/functions_vars_0x71.html |   71 +
 .../dwc_otg/doc/html/functions_vars_0x72.html |  141 +
 .../dwc_otg/doc/html/functions_vars_0x73.html |  128 +
 .../dwc_otg/doc/html/functions_vars_0x74.html |   88 +
 .../dwc_otg/doc/html/functions_vars_0x75.html |   78 +
 .../dwc_otg/doc/html/functions_vars_0x76.html |   65 +
 .../dwc_otg/doc/html/functions_vars_0x77.html |   79 +
 .../dwc_otg/doc/html/functions_vars_0x78.html |   77 +
 .../usb/host/dwc_otg/doc/html/globals.html    |   87 +
 .../host/dwc_otg/doc/html/globals_0x61.html   |   76 +
 .../host/dwc_otg/doc/html/globals_0x62.html   |   83 +
 .../host/dwc_otg/doc/html/globals_0x63.html   |  100 +
 .../host/dwc_otg/doc/html/globals_0x64.html   |  686 +++
 .../host/dwc_otg/doc/html/globals_0x65.html   |   78 +
 .../host/dwc_otg/doc/html/globals_0x66.html   |   87 +
 .../host/dwc_otg/doc/html/globals_0x67.html   |   93 +
 .../host/dwc_otg/doc/html/globals_0x68.html   |  129 +
 .../host/dwc_otg/doc/html/globals_0x69.html   |   76 +
 .../host/dwc_otg/doc/html/globals_0x6b.html   |   69 +
 .../host/dwc_otg/doc/html/globals_0x6d.html   |   84 +
 .../host/dwc_otg/doc/html/globals_0x6e.html   |   68 +
 .../host/dwc_otg/doc/html/globals_0x6f.html   |   73 +
 .../host/dwc_otg/doc/html/globals_0x70.html   |   84 +
 .../host/dwc_otg/doc/html/globals_0x71.html   |   70 +
 .../host/dwc_otg/doc/html/globals_0x72.html   |   94 +
 .../host/dwc_otg/doc/html/globals_0x73.html   |   85 +
 .../host/dwc_otg/doc/html/globals_0x74.html   |   68 +
 .../host/dwc_otg/doc/html/globals_0x75.html   |   80 +
 .../host/dwc_otg/doc/html/globals_0x76.html   |   75 +
 .../host/dwc_otg/doc/html/globals_0x77.html   |   74 +
 .../host/dwc_otg/doc/html/globals_defs.html   |   68 +
 .../dwc_otg/doc/html/globals_defs_0x61.html   |   64 +
 .../dwc_otg/doc/html/globals_defs_0x62.html   |   71 +
 .../dwc_otg/doc/html/globals_defs_0x63.html   |   74 +
 .../dwc_otg/doc/html/globals_defs_0x64.html   |  241 +
 .../dwc_otg/doc/html/globals_defs_0x66.html   |   71 +
 .../dwc_otg/doc/html/globals_defs_0x67.html   |   62 +
 .../dwc_otg/doc/html/globals_defs_0x68.html   |   63 +
 .../dwc_otg/doc/html/globals_defs_0x69.html   |   62 +
 .../dwc_otg/doc/html/globals_defs_0x6d.html   |   76 +
 .../dwc_otg/doc/html/globals_defs_0x6e.html   |   62 +
 .../dwc_otg/doc/html/globals_defs_0x6f.html   |   67 +
 .../dwc_otg/doc/html/globals_defs_0x72.html   |   66 +
 .../dwc_otg/doc/html/globals_defs_0x73.html   |   63 +
 .../dwc_otg/doc/html/globals_defs_0x75.html   |   64 +
 .../dwc_otg/doc/html/globals_defs_0x76.html   |   68 +
 .../host/dwc_otg/doc/html/globals_enum.html   |   44 +
 .../host/dwc_otg/doc/html/globals_eval.html   |   43 +
 .../host/dwc_otg/doc/html/globals_func.html   |   77 +
 .../dwc_otg/doc/html/globals_func_0x61.html   |   70 +
 .../dwc_otg/doc/html/globals_func_0x62.html   |   68 +
 .../dwc_otg/doc/html/globals_func_0x63.html   |   77 +
 .../dwc_otg/doc/html/globals_func_0x64.html   |  427 ++
 .../dwc_otg/doc/html/globals_func_0x65.html   |   73 +
 .../dwc_otg/doc/html/globals_func_0x66.html   |   72 +
 .../dwc_otg/doc/html/globals_func_0x67.html   |   78 +
 .../dwc_otg/doc/html/globals_func_0x68.html   |  101 +
 .../dwc_otg/doc/html/globals_func_0x69.html   |   71 +
 .../dwc_otg/doc/html/globals_func_0x6b.html   |   66 +
 .../dwc_otg/doc/html/globals_func_0x6d.html   |   66 +
 .../dwc_otg/doc/html/globals_func_0x70.html   |   78 +
 .../dwc_otg/doc/html/globals_func_0x71.html   |   67 +
 .../dwc_otg/doc/html/globals_func_0x72.html   |   80 +
 .../dwc_otg/doc/html/globals_func_0x73.html   |   77 +
 .../dwc_otg/doc/html/globals_func_0x75.html   |   73 +
 .../dwc_otg/doc/html/globals_func_0x76.html   |   65 +
 .../dwc_otg/doc/html/globals_func_0x77.html   |   70 +
 .../host/dwc_otg/doc/html/globals_type.html   |  175 +
 .../host/dwc_otg/doc/html/globals_vars.html   |  120 +
 drivers/usb/host/dwc_otg/doc/html/index.html  |    8 +
 .../doc/html/linux module attributes.html     |  130 +
 drivers/usb/host/dwc_otg/doc/html/main.html   |   21 +
 .../dwc_otg/doc/html/module parameters.html   |  189 +
 drivers/usb/host/dwc_otg/doc/html/pages.html  |   27 +
 .../struct__ddma__align__buffer__setup.html   |   46 +
 .../struct__ddma__concat__buffer__setup.html  |   46 +
 ...uct__ddma__concat__buffer__setup__hdr.html |   49 +
 .../html/struct__ddma__sg__buffer__setup.html |   57 +
 .../html/struct__rx__fifo__size__setup.html   |   43 +
 .../html/struct__tx__fifo__size__setup.html   |   46 +
 .../structcfi__all__features__header.html     |   75 +
 .../doc/html/structcfi__dma__buff.html        |   41 +
 .../host/dwc_otg/doc/html/structcfi__ep.html  |   69 +
 .../structcfi__feature__desc__header.html     |   60 +
 .../host/dwc_otg/doc/html/structcfi__ops.html |   64 +
 .../dwc_otg/doc/html/structcfi__string.html   |   48 +
 .../doc/html/structcfi__usb__ctrlrequest.html |   58 +
 .../dwc_otg/doc/html/structcfiobject.html     |   62 +
 .../host/dwc_otg/doc/html/structdwc__ep.html  |  192 +
 .../host/dwc_otg/doc/html/structdwc__hc.html  |  345 ++
 .../html/structdwc__otg__cil__callbacks.html  |   70 +
 .../structdwc__otg__core__global__regs.html   |  557 ++
 .../doc/html/structdwc__otg__core__if.html    |  190 +
 .../html/structdwc__otg__core__params.html    |  606 ++
 .../html/structdwc__otg__dev__dma__desc.html  |   50 +
 .../structdwc__otg__dev__global__regs.html    |  441 ++
 .../doc/html/structdwc__otg__dev__if.html     |  142 +
 .../structdwc__otg__dev__in__ep__regs.html    |  221 +
 .../structdwc__otg__dev__out__ep__regs.html   |  221 +
 .../doc/html/structdwc__otg__device.html      |   64 +
 ...tructdwc__otg__driver__module__params.html |  146 +
 .../doc/html/structdwc__otg__hc__regs.html    |  200 +
 .../dwc_otg/doc/html/structdwc__otg__hcd.html |  377 ++
 .../structdwc__otg__hcd__function__ops.html   |   53 +
 ...tructdwc__otg__hcd__iso__packet__desc.html |   47 +
 .../html/structdwc__otg__hcd__pipe__info.html |   50 +
 .../doc/html/structdwc__otg__hcd__urb.html    |   80 +
 .../html/structdwc__otg__host__dma__desc.html |   50 +
 .../structdwc__otg__host__global__regs.html   |  219 +
 .../doc/html/structdwc__otg__host__if.html    |   66 +
 .../dwc_otg/doc/html/structdwc__otg__pcd.html |  152 +
 .../doc/html/structdwc__otg__pcd__ep.html     |   77 +
 .../structdwc__otg__pcd__function__ops.html   |   73 +
 .../html/structdwc__otg__pcd__request.html    |   64 +
 .../dwc_otg/doc/html/structdwc__otg__qh.html  |  228 +
 .../dwc_otg/doc/html/structdwc__otg__qtd.html |  157 +
 .../doc/html/structgadget__wrapper.html       |   53 +
 .../doc/html/structiso__pkt__info.html        |   49 +
 .../doc/html/structwrapper__priv__data.html   |   38 +
 .../dwc_otg/doc/html/structzero__dev.html     |   56 +
 drivers/usb/host/dwc_otg/doc/html/tabs.css    |  102 +
 drivers/usb/host/dwc_otg/doc/html/todo.html   |  262 +
 drivers/usb/host/dwc_otg/doc/html/tree.html   |  201 +
 .../dwc_otg/doc/html/uniondaint__data.html    |  131 +
 .../dwc_otg/doc/html/uniondcfg__data.html     |   74 +
 .../dwc_otg/doc/html/uniondctl__data.html     |   96 +
 .../dwc_otg/doc/html/uniondepctl__data.html   |  139 +
 .../dwc_otg/doc/html/uniondeptsiz0__data.html |   69 +
 .../dwc_otg/doc/html/uniondeptsiz__data.html  |   63 +
 .../doc/html/uniondev__dma__desc__sts.html    |  140 +
 .../doc/html/uniondevice__grxsts__data.html   |   62 +
 .../dwc_otg/doc/html/uniondiepint__data.html  |   90 +
 .../dwc_otg/doc/html/uniondoepint__data.html  |   98 +
 .../dwc_otg/doc/html/uniondsts__data.html     |   68 +
 .../dwc_otg/doc/html/uniondthrctl__data.html  |  178 +
 .../dwc_otg/doc/html/uniondtknq1__data.html   |   86 +
 .../dwc_otg/doc/html/uniondtxfsts__data.html  |   56 +
 ...hcd_1_1dwc__otg__hcd__internal__flags.html |   66 +
 .../dwc_otg/doc/html/unionfifosize__data.html |   56 +
 .../dwc_otg/doc/html/uniongahbcfg__data.html  |   66 +
 .../dwc_otg/doc/html/uniongi2cctl__data.html  |   72 +
 .../dwc_otg/doc/html/uniongintmsk__data.html  |  114 +
 .../dwc_otg/doc/html/uniongintsts__data.html  |  114 +
 .../dwc_otg/doc/html/unionglpmctl__data.html  |  178 +
 .../dwc_otg/doc/html/uniongnptxsts__data.html |   69 +
 .../dwc_otg/doc/html/uniongotgctl__data.html  |   80 +
 .../dwc_otg/doc/html/uniongotgint__data.html  |   79 +
 .../dwc_otg/doc/html/uniongrstctl__data.html  |  249 +
 .../dwc_otg/doc/html/uniongusbcfg__data.html  |   98 +
 .../dwc_otg/doc/html/unionhaint__data.html    |   93 +
 .../dwc_otg/doc/html/unionhaintmsk__data.html |   93 +
 .../dwc_otg/doc/html/unionhcchar__data.html   |  123 +
 .../dwc_otg/doc/html/unionhcdma__data.html    |   78 +
 .../dwc_otg/doc/html/unionhcfg__data.html     |   72 +
 .../dwc_otg/doc/html/unionhcint__data.html    |   95 +
 .../dwc_otg/doc/html/unionhcintmsk__data.html |   82 +
 .../dwc_otg/doc/html/unionhcsplt__data.html   |   63 +
 .../dwc_otg/doc/html/unionhctsiz__data.html   |  105 +
 .../dwc_otg/doc/html/unionhfir__data.html     |   54 +
 .../dwc_otg/doc/html/unionhfnum__data.html    |   54 +
 .../doc/html/unionhost__dma__desc__sts.html   |  123 +
 .../doc/html/unionhost__grxsts__data.html     |   60 +
 .../dwc_otg/doc/html/unionhprt0__data.html    |   82 +
 .../dwc_otg/doc/html/unionhptxsts__data.html  |   62 +
 .../dwc_otg/doc/html/unionhwcfg1__data.html   |   84 +
 .../dwc_otg/doc/html/unionhwcfg2__data.html   |   82 +
 .../dwc_otg/doc/html/unionhwcfg3__data.html   |   76 +
 .../dwc_otg/doc/html/unionhwcfg4__data.html   |   80 +
 .../dwc_otg/doc/html/unionpcgcctl__data.html  |   78 +
 drivers/usb/host/dwc_otg/dummy_audio.c        | 1575 +++++
 drivers/usb/host/dwc_otg/dwc_cfi_common.h     |  142 +
 drivers/usb/host/dwc_otg/dwc_otg_attr.c       | 1316 ++++
 drivers/usb/host/dwc_otg/dwc_otg_attr.h       |   88 +
 drivers/usb/host/dwc_otg/dwc_otg_cfi.c        | 1876 ++++++
 drivers/usb/host/dwc_otg/dwc_otg_cfi.h        |  319 +
 drivers/usb/host/dwc_otg/dwc_otg_cil.c        | 5410 +++++++++++++++++
 drivers/usb/host/dwc_otg/dwc_otg_cil.h        | 1143 ++++
 drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c   |  846 +++
 drivers/usb/host/dwc_otg/dwc_otg_core_if.h    |  641 ++
 drivers/usb/host/dwc_otg/dwc_otg_dbg.h        |  113 +
 drivers/usb/host/dwc_otg/dwc_otg_driver.c     | 1577 +++++
 drivers/usb/host/dwc_otg/dwc_otg_driver.h     |  101 +
 drivers/usb/host/dwc_otg/dwc_otg_hcd.c        | 3330 ++++++++++
 drivers/usb/host/dwc_otg/dwc_otg_hcd.h        |  804 +++
 drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c   | 1106 ++++
 drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h     |  393 ++
 drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c   | 2065 +++++++
 drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c  |  840 +++
 drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c  |  732 +++
 drivers/usb/host/dwc_otg/dwc_otg_pcd.c        | 2067 +++++++
 drivers/usb/host/dwc_otg/dwc_otg_pcd.h        |  216 +
 drivers/usb/host/dwc_otg/dwc_otg_pcd_if.h     |  333 +
 drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c   | 4077 +++++++++++++
 drivers/usb/host/dwc_otg/dwc_otg_pcd_linux.c  | 1288 ++++
 drivers/usb/host/dwc_otg/dwc_otg_regs.h       | 2237 +++++++
 drivers/usb/host/dwc_otg/test/Makefile        |   16 +
 drivers/usb/host/dwc_otg/test/dwc_otg_test.pm |  337 +
 .../usb/host/dwc_otg/test/test_mod_param.pl   |  133 +
 drivers/usb/host/dwc_otg/test/test_sysfs.pl   |  193 +
 341 files changed, 124762 insertions(+), 59 deletions(-)
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 create mode 100644 drivers/usb/host/dwc_common_port/Makefile.linux
 create mode 100644 drivers/usb/host/dwc_common_port/doc/doxygen.cfg
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 create mode 100644 drivers/usb/host/dwc_otg/doc/html/structcfiobject.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/structdwc__ep.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/structdwc__hc.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/structdwc__otg__cil__callbacks.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/structdwc__otg__core__global__regs.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/structdwc__otg__core__if.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/structdwc__otg__core__params.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/structdwc__otg__dev__dma__desc.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/structdwc__otg__dev__global__regs.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/structdwc__otg__dev__if.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/structdwc__otg__dev__in__ep__regs.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/structdwc__otg__dev__out__ep__regs.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/structdwc__otg__device.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/structdwc__otg__driver__module__params.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/structdwc__otg__hc__regs.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/structdwc__otg__hcd.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/structdwc__otg__hcd__function__ops.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/structdwc__otg__hcd__iso__packet__desc.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/structdwc__otg__hcd__pipe__info.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/structdwc__otg__hcd__urb.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/structdwc__otg__host__dma__desc.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/structdwc__otg__host__global__regs.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/structdwc__otg__host__if.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/structdwc__otg__pcd.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/structdwc__otg__pcd__ep.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/structdwc__otg__pcd__function__ops.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/structdwc__otg__pcd__request.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/structdwc__otg__qh.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/structdwc__otg__qtd.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/structgadget__wrapper.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/structiso__pkt__info.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/structwrapper__priv__data.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/structzero__dev.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/tabs.css
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/todo.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/tree.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/uniondaint__data.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/uniondcfg__data.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/uniondctl__data.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/uniondepctl__data.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/uniondeptsiz0__data.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/uniondeptsiz__data.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/uniondev__dma__desc__sts.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/uniondevice__grxsts__data.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/uniondiepint__data.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/uniondoepint__data.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/uniondsts__data.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/uniondthrctl__data.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/uniondtknq1__data.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/uniondtxfsts__data.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/unionfifosize__data.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/uniongahbcfg__data.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/uniongi2cctl__data.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/uniongintmsk__data.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/uniongintsts__data.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/unionglpmctl__data.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/uniongnptxsts__data.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/uniongotgctl__data.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/uniongotgint__data.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/uniongrstctl__data.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/uniongusbcfg__data.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/unionhaint__data.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/unionhaintmsk__data.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/unionhcchar__data.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/unionhcdma__data.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/unionhcfg__data.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/unionhcint__data.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/unionhcintmsk__data.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/unionhcsplt__data.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/unionhctsiz__data.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/unionhfir__data.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/unionhfnum__data.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/unionhost__dma__desc__sts.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/unionhost__grxsts__data.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/unionhprt0__data.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/unionhptxsts__data.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/unionhwcfg1__data.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/unionhwcfg2__data.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/unionhwcfg3__data.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/unionhwcfg4__data.html
 create mode 100644 drivers/usb/host/dwc_otg/doc/html/unionpcgcctl__data.html
 create mode 100644 drivers/usb/host/dwc_otg/dummy_audio.c
 create mode 100644 drivers/usb/host/dwc_otg/dwc_cfi_common.h
 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_attr.c
 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_attr.h
 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_cfi.c
 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_cfi.h
 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_cil.c
 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_cil.h
 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c
 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_core_if.h
 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_dbg.h
 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_driver.c
 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_driver.h
 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd.c
 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd.h
 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c
 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h
 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c
 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c
 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c
 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_pcd.c
 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_pcd.h
 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_pcd_if.h
 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c
 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_pcd_linux.c
 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_regs.h
 create mode 100644 drivers/usb/host/dwc_otg/test/Makefile
 create mode 100644 drivers/usb/host/dwc_otg/test/dwc_otg_test.pm
 create mode 100644 drivers/usb/host/dwc_otg/test/test_mod_param.pl
 create mode 100644 drivers/usb/host/dwc_otg/test/test_sysfs.pl

diff --git a/drivers/usb/Makefile b/drivers/usb/Makefile
index 30ddf8dc4f72..e56ebae7b09a 100644
--- a/drivers/usb/Makefile
+++ b/drivers/usb/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_USB_U132_HCD)	+= host/
 obj-$(CONFIG_USB_R8A66597_HCD)	+= host/
 obj-$(CONFIG_USB_HWA_HCD)	+= host/
 obj-$(CONFIG_USB_ISP1760_HCD)	+= host/
+obj-$(CONFIG_USB_DWCOTG)	+= host/
 obj-$(CONFIG_USB_IMX21_HCD)	+= host/
 obj-$(CONFIG_USB_FSL_MPH_DR_OF)	+= host/
 
diff --git a/drivers/usb/core/generic.c b/drivers/usb/core/generic.c
index 69ecd3c92311..0431b4efef17 100644
--- a/drivers/usb/core/generic.c
+++ b/drivers/usb/core/generic.c
@@ -149,6 +149,7 @@ int usb_choose_configuration(struct usb_device *udev)
 		dev_warn(&udev->dev,
 			"no configuration chosen from %d choice%s\n",
 			num_configs, plural(num_configs));
+		dev_warn(&udev->dev, "No support over %dmA\n", udev->bus_mA);
 	}
 	return i;
 }
diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c
index 210e3597091a..badae51d2ff9 100644
--- a/drivers/usb/core/hub.c
+++ b/drivers/usb/core/hub.c
@@ -1071,6 +1071,8 @@ static int hub_configure(struct usb_hub *hub,
 	INIT_WORK(&hub->tt.clear_work, hub_tt_work);
 	switch (hdev->descriptor.bDeviceProtocol) {
 		case 0:
+			dev_dbg(hub_dev, "TT with no hub-specific protocol - "
+				"no TT\n");
 			break;
 		case 1:
 			dev_dbg(hub_dev, "Single TT\n");
@@ -1087,6 +1089,7 @@ static int hub_configure(struct usb_hub *hub,
 			hub->tt.hub = hdev;
 			break;
 		case 3:
+			dev_dbg(hub_dev, "USB 3.0 hub - no TT\n");
 			/* USB 3.0 hubs don't have a TT */
 			break;
 		default:
@@ -1724,6 +1727,12 @@ static inline void announce_device(struct usb_device *udev) { }
 #endif
 
 #ifdef	CONFIG_USB_OTG
+
+static int enable_whitelist;
+module_param(enable_whitelist, bool, S_IRUGO | S_IWUSR);
+MODULE_PARM_DESC(enable_whitelist,
+		 "only recognize devices in OTG whitelist if true");
+
 #include "otg_whitelist.h"
 #endif
 
@@ -1778,9 +1787,15 @@ static int usb_enumerate_device_otg(struct usb_device *udev)
 					dev_info(&udev->dev,
 						"can't set HNP mode: %d\n",
 						err);
+					dev_printk(KERN_CRIT, &udev->dev,
+						"Not Connected/Responding\n");
+
 					bus->b_hnp_enable = 0;
+				} else {
+					dev_info(&udev->dev,
+						"HNP Not Supported\n");
 				}
-			}
+                        }
 		}
 	}
 
@@ -1789,12 +1804,27 @@ static int usb_enumerate_device_otg(struct usb_device *udev)
 		/* Maybe it can talk to us, though we can't talk to it.
 		 * (Includes HNP test device.)
 		 */
-		if (udev->bus->b_hnp_enable || udev->bus->is_b_host) {
+		if (udev->bus->b_hnp_enable || udev->bus->is_b_host ||
+		    udev->descriptor.idVendor == 0x1a0a) {
 			err = usb_port_suspend(udev, PMSG_SUSPEND);
-			if (err < 0)
+			if (err < 0) {
 				dev_dbg(&udev->dev, "HNP fail, %d\n", err);
+			} else {
+			    /* Return Connection Refused(ECONNREFUSED)
+			     * instead of No Device(ENODEV) so that the
+			     * retry loop in hub_port_connect_change() is
+			     * exited without disabling the port
+			     */
+			    err = -ECONNREFUSED;
+			    goto fail;
+			}
 		}
-		err = -ENOTSUPP;
+		//err = -ENOTSUPP;
+		/* Return Not Connected (ENOTCONN) instead of No
+		 * Device(ENODEV) so that the retry loop in
+		 * hub_port_connect_change() is exited
+		 */
+		err = -ENOTCONN;
 		goto fail;
 	}
 fail:
@@ -2377,8 +2407,8 @@ int usb_port_suspend(struct usb_device *udev, pm_message_t msg)
 			status = 0;
 	} else {
 		/* device has up to 10 msec to fully suspend */
-		dev_dbg(&udev->dev, "usb %ssuspend\n",
-				(msg.event & PM_EVENT_AUTO ? "auto-" : ""));
+//		dev_dbg(&udev->dev, "usb %ssuspend\n",
+//				(msg.event & PM_EVENT_AUTO ? "auto-" : ""));
 		usb_set_device_state(udev, USB_STATE_SUSPENDED);
 		msleep(10);
 	}
@@ -2932,7 +2962,9 @@ hub_port_init (struct usb_hub *hub, struct usb_device *udev, int port1,
 				buf->bMaxPacketSize0 = 0;
 				r = usb_control_msg(udev, usb_rcvaddr0pipe(),
 					USB_REQ_GET_DESCRIPTOR, USB_DIR_IN,
-					USB_DT_DEVICE << 8, 0,
+					USB_DT_DEVICE << 8,
+					//USB_DT_DEVICE << 64, // DWC patch suggestion!
+					0,
 					buf, GET_DESCRIPTOR_BUFSIZE,
 					initial_descriptor_timeout);
 				switch (buf->bMaxPacketSize0) {
@@ -3353,8 +3385,10 @@ loop:
 		release_devnum(udev);
 		hub_free_dev(udev);
 		usb_put_dev(udev);
-		if ((status == -ENOTCONN) || (status == -ENOTSUPP))
-			break;
+		if (status == -ENOTCONN || status == -ENOTSUPP ||
+			status == -ECONNREFUSED)
+			// break; //DWC patch
+			return;
 	}
 	if (hub->hdev->parent ||
 			!hcd->driver->port_handed_over ||
diff --git a/drivers/usb/core/message.c b/drivers/usb/core/message.c
index 0b5ec234c787..1abe797e4a27 100644
--- a/drivers/usb/core/message.c
+++ b/drivers/usb/core/message.c
@@ -1836,6 +1836,85 @@ free_interfaces:
 	if (cp->string == NULL &&
 			!(dev->quirks & USB_QUIRK_CONFIG_INTF_STRINGS))
 		cp->string = usb_cache_string(dev, cp->desc.iConfiguration);
+/* Uncomment this define to enable the HS Electrical Test support */
+#define DWC_HS_ELECT_TST 1
+#ifdef DWC_HS_ELECT_TST
+		/* Here we implement the HS Electrical Test support. The
+		 * tester uses a vendor ID of 0x1A0A to indicate we should
+		 * run a special test sequence. The product ID tells us
+		 * which sequence to run. We invoke the test sequence by
+		 * sending a non-standard SetFeature command to our root
+		 * hub port. Our dwc_otg_hcd_hub_control() routine will
+		 * recognize the command and perform the desired test
+		 * sequence.
+		 */
+		if (dev->descriptor.idVendor == 0x1A0A) {
+			/* HSOTG Electrical Test */
+			dev_warn(&dev->dev, "VID from HSOTG Electrical Test Fixture\n");
+
+			if (dev->bus && dev->bus->root_hub) {
+				struct usb_device *hdev = dev->bus->root_hub;
+				dev_warn(&dev->dev, "Got PID 0x%x\n", dev->descriptor.idProduct);
+
+				switch (dev->descriptor.idProduct) {
+				case 0x0101:	/* TEST_SE0_NAK */
+					dev_warn(&dev->dev, "TEST_SE0_NAK\n");
+					usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
+							USB_REQ_SET_FEATURE, USB_RT_PORT,
+							USB_PORT_FEAT_TEST, 0x300, NULL, 0, HZ);
+					break;
+
+				case 0x0102:	/* TEST_J */
+					dev_warn(&dev->dev, "TEST_J\n");
+					usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
+							USB_REQ_SET_FEATURE, USB_RT_PORT,
+							USB_PORT_FEAT_TEST, 0x100, NULL, 0, HZ);
+					break;
+
+				case 0x0103:	/* TEST_K */
+					dev_warn(&dev->dev, "TEST_K\n");
+					usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
+							USB_REQ_SET_FEATURE, USB_RT_PORT,
+							USB_PORT_FEAT_TEST, 0x200, NULL, 0, HZ);
+					break;
+
+				case 0x0104:	/* TEST_PACKET */
+					dev_warn(&dev->dev, "TEST_PACKET\n");
+					usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
+							USB_REQ_SET_FEATURE, USB_RT_PORT,
+							USB_PORT_FEAT_TEST, 0x400, NULL, 0, HZ);
+					break;
+
+				case 0x0105:	/* TEST_FORCE_ENABLE */
+					dev_warn(&dev->dev, "TEST_FORCE_ENABLE\n");
+					usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
+							USB_REQ_SET_FEATURE, USB_RT_PORT,
+							USB_PORT_FEAT_TEST, 0x500, NULL, 0, HZ);
+					break;
+
+				case 0x0106:	/* HS_HOST_PORT_SUSPEND_RESUME */
+					dev_warn(&dev->dev, "HS_HOST_PORT_SUSPEND_RESUME\n");
+					usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
+							USB_REQ_SET_FEATURE, USB_RT_PORT,
+							USB_PORT_FEAT_TEST, 0x600, NULL, 0, 40 * HZ);
+					break;
+
+				case 0x0107:	/* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */
+					dev_warn(&dev->dev, "SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup\n");
+					usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
+							USB_REQ_SET_FEATURE, USB_RT_PORT,
+							USB_PORT_FEAT_TEST, 0x700, NULL, 0, 40 * HZ);
+					break;
+
+				case 0x0108:	/* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */
+					dev_warn(&dev->dev, "SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute\n");
+					usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
+							USB_REQ_SET_FEATURE, USB_RT_PORT,
+							USB_PORT_FEAT_TEST, 0x800, NULL, 0, 40 * HZ);
+				}
+			}
+		}
+#endif /* DWC_HS_ELECT_TST */
 
 	/* Now that all the interfaces are set up, register them
 	 * to trigger binding of drivers to interfaces.  probe()
diff --git a/drivers/usb/core/otg_whitelist.h b/drivers/usb/core/otg_whitelist.h
index e8cdce571bb1..3a0da17a459c 100644
--- a/drivers/usb/core/otg_whitelist.h
+++ b/drivers/usb/core/otg_whitelist.h
@@ -19,33 +19,82 @@
 static struct usb_device_id whitelist_table [] = {
 
 /* hubs are optional in OTG, but very handy ... */
+#define CERT_WITHOUT_HUBS
+#if defined(CERT_WITHOUT_HUBS)
+{ USB_DEVICE( 0x0000, 0x0000 ), }, /* Root HUB Only*/
+#else
 { USB_DEVICE_INFO(USB_CLASS_HUB, 0, 0), },
 { USB_DEVICE_INFO(USB_CLASS_HUB, 0, 1), },
+{ USB_DEVICE_INFO(USB_CLASS_HUB, 0, 2), },
+#endif
 
 #ifdef	CONFIG_USB_PRINTER		/* ignoring nonstatic linkage! */
 /* FIXME actually, printers are NOT supposed to use device classes;
  * they're supposed to use interface classes...
  */
-{ USB_DEVICE_INFO(7, 1, 1) },
-{ USB_DEVICE_INFO(7, 1, 2) },
-{ USB_DEVICE_INFO(7, 1, 3) },
+//{ USB_DEVICE_INFO(7, 1, 1) },
+//{ USB_DEVICE_INFO(7, 1, 2) },
+//{ USB_DEVICE_INFO(7, 1, 3) },
 #endif
 
 #ifdef	CONFIG_USB_NET_CDCETHER
 /* Linux-USB CDC Ethernet gadget */
-{ USB_DEVICE(0x0525, 0xa4a1), },
+//{ USB_DEVICE(0x0525, 0xa4a1), },
 /* Linux-USB CDC Ethernet + RNDIS gadget */
-{ USB_DEVICE(0x0525, 0xa4a2), },
+//{ USB_DEVICE(0x0525, 0xa4a2), },
 #endif
 
 #if	defined(CONFIG_USB_TEST) || defined(CONFIG_USB_TEST_MODULE)
 /* gadget zero, for testing */
-{ USB_DEVICE(0x0525, 0xa4a0), },
+//{ USB_DEVICE(0x0525, 0xa4a0), },
 #endif
+   
+/* OPT Tester */
+{ USB_DEVICE( 0x1a0a, 0x0101 ), }, /* TEST_SE0_NAK */
+{ USB_DEVICE( 0x1a0a, 0x0102 ), }, /* Test_J */
+{ USB_DEVICE( 0x1a0a, 0x0103 ), }, /* Test_K */
+{ USB_DEVICE( 0x1a0a, 0x0104 ), }, /* Test_PACKET */
+{ USB_DEVICE( 0x1a0a, 0x0105 ), }, /* Test_FORCE_ENABLE */
+{ USB_DEVICE( 0x1a0a, 0x0106 ), }, /* HS_PORT_SUSPEND_RESUME  */
+{ USB_DEVICE( 0x1a0a, 0x0107 ), }, /* SINGLE_STEP_GET_DESCRIPTOR setup */
+{ USB_DEVICE( 0x1a0a, 0x0108 ), }, /* SINGLE_STEP_GET_DESCRIPTOR execute */
+
+/* Sony cameras */        
+{ USB_DEVICE_VER(0x054c,0x0010,0x0410, 0x0500), },
+   
+/* Memory Devices */
+//{ USB_DEVICE( 0x0781, 0x5150 ), }, /* SanDisk */
+//{ USB_DEVICE( 0x05DC, 0x0080 ), }, /* Lexar */
+//{ USB_DEVICE( 0x4146, 0x9281 ), }, /* IOMEGA */
+//{ USB_DEVICE( 0x067b, 0x2507 ), }, /* Hammer 20GB External HD  */
+{ USB_DEVICE( 0x0EA0, 0x2168 ), }, /* Ours Technology Inc. (BUFFALO ClipDrive)*/
+//{ USB_DEVICE( 0x0457, 0x0150 ), }, /* Silicon Integrated Systems Corp. */
+
+/* HP Printers */
+//{ USB_DEVICE( 0x03F0, 0x1102 ), }, /* HP Photosmart 245 */
+//{ USB_DEVICE( 0x03F0, 0x1302 ), }, /* HP Photosmart 370 Series */
+
+/* Speakers */
+//{ USB_DEVICE( 0x0499, 0x3002 ), }, /* YAMAHA YST-MS35D USB Speakers */
+//{ USB_DEVICE( 0x0672, 0x1041 ), }, /* Labtec USB Headset */
 
 { }	/* Terminating entry */
 };
 
+static inline void report_errors(struct usb_device *dev)
+{
+	/* OTG MESSAGE: report errors here, customize to match your product */
+	dev_info(&dev->dev, "device Vendor:%04x Product:%04x is not supported\n",
+		 le16_to_cpu(dev->descriptor.idVendor),
+		 le16_to_cpu(dev->descriptor.idProduct));
+        if (USB_CLASS_HUB == dev->descriptor.bDeviceClass){
+                dev_printk(KERN_CRIT, &dev->dev, "Unsupported Hub Topology\n");
+        } else {        
+                dev_printk(KERN_CRIT, &dev->dev, "Attached Device is not Supported\n");
+        }
+}
+
+
 static int is_targeted(struct usb_device *dev)
 {
 	struct usb_device_id	*id = whitelist_table;
@@ -55,58 +104,83 @@ static int is_targeted(struct usb_device *dev)
 		return 1;
 
 	/* HNP test device is _never_ targeted (see OTG spec 6.6.6) */
-	if ((le16_to_cpu(dev->descriptor.idVendor) == 0x1a0a &&
-	     le16_to_cpu(dev->descriptor.idProduct) == 0xbadd))
-		return 0;
-
-	/* NOTE: can't use usb_match_id() since interface caches
-	 * aren't set up yet. this is cut/paste from that code.
-	 */
-	for (id = whitelist_table; id->match_flags; id++) {
-		if ((id->match_flags & USB_DEVICE_ID_MATCH_VENDOR) &&
-		    id->idVendor != le16_to_cpu(dev->descriptor.idVendor))
-			continue;
-
-		if ((id->match_flags & USB_DEVICE_ID_MATCH_PRODUCT) &&
-		    id->idProduct != le16_to_cpu(dev->descriptor.idProduct))
-			continue;
-
-		/* No need to test id->bcdDevice_lo != 0, since 0 is never
-		   greater than any unsigned number. */
-		if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_LO) &&
-		    (id->bcdDevice_lo > le16_to_cpu(dev->descriptor.bcdDevice)))
-			continue;
-
-		if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_HI) &&
-		    (id->bcdDevice_hi < le16_to_cpu(dev->descriptor.bcdDevice)))
-			continue;
-
-		if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_CLASS) &&
-		    (id->bDeviceClass != dev->descriptor.bDeviceClass))
-			continue;
-
-		if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_SUBCLASS) &&
-		    (id->bDeviceSubClass != dev->descriptor.bDeviceSubClass))
-			continue;
-
-		if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_PROTOCOL) &&
-		    (id->bDeviceProtocol != dev->descriptor.bDeviceProtocol))
-			continue;
+	if (dev->descriptor.idVendor == 0x1a0a && 
+            dev->descriptor.idProduct == 0xbadd) {
+                return 0;
+	} else if (!enable_whitelist) {
+		return 1;
+        } else {
+
+#ifdef DEBUG
+                dev_dbg(&dev->dev, "device V:%04x P:%04x DC:%04x SC:%04x PR:%04x \n",
+                        dev->descriptor.idVendor,
+                        dev->descriptor.idProduct,
+                        dev->descriptor.bDeviceClass,
+                        dev->descriptor.bDeviceSubClass,
+                        dev->descriptor.bDeviceProtocol);
+#endif
 
 		return 1;
+		/* NOTE: can't use usb_match_id() since interface caches
+		 * aren't set up yet. this is cut/paste from that code.
+		 */
+		for (id = whitelist_table; id->match_flags; id++) {
+#ifdef DEBUG
+			dev_dbg(&dev->dev, 
+				"ID: V:%04x P:%04x DC:%04x SC:%04x PR:%04x \n",
+				id->idVendor,
+				id->idProduct,
+				id->bDeviceClass,
+				id->bDeviceSubClass,
+				id->bDeviceProtocol);
+#endif			      
+
+			if ((id->match_flags & USB_DEVICE_ID_MATCH_VENDOR) &&
+			    id->idVendor != le16_to_cpu(dev->descriptor.idVendor))
+				continue;
+
+			if ((id->match_flags & USB_DEVICE_ID_MATCH_PRODUCT) &&
+			    id->idProduct != le16_to_cpu(dev->descriptor.idProduct))
+				continue;
+
+			/* No need to test id->bcdDevice_lo != 0, since 0 is never
+			   greater than any unsigned number. */
+			if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_LO) &&
+			    (id->bcdDevice_lo > le16_to_cpu(dev->descriptor.bcdDevice)))
+				continue;
+
+			if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_HI) &&
+			    (id->bcdDevice_hi < le16_to_cpu(dev->descriptor.bcdDevice)))
+				continue;
+
+			if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_CLASS) &&
+			    (id->bDeviceClass != dev->descriptor.bDeviceClass))
+				continue;
+
+			if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_SUBCLASS) &&
+			    (id->bDeviceSubClass != dev->descriptor.bDeviceSubClass))
+				continue;
+
+			if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_PROTOCOL) &&
+			    (id->bDeviceProtocol != dev->descriptor.bDeviceProtocol))
+				continue;
+
+			return 1;
+		}
 	}
 
 	/* add other match criteria here ... */
 
-
-	/* OTG MESSAGE: report errors here, customize to match your product */
-	dev_err(&dev->dev, "device v%04x p%04x is not supported\n",
-		le16_to_cpu(dev->descriptor.idVendor),
-		le16_to_cpu(dev->descriptor.idProduct));
 #ifdef	CONFIG_USB_OTG_WHITELIST
+	report_errors(dev);
 	return 0;
 #else
-	return 1;
+	if (enable_whitelist) {
+		report_errors(dev);
+		return 0;
+	} else {
+		return 1;
+	}
 #endif
 }
 
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index 6f5049156e17..83de3752aff8 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -525,6 +525,34 @@ config USB_GADGET_SUPERSPEED
 	depends on USB_GADGET
 	depends on USB_GADGET_DUALSPEED
 
+config USB_GADGET_SNPS_DWC_OTG
+	boolean "Synopsys Driver for DWC_otg Controller"
+	depends on USB && EXPERIMENTAL
+	select USB_OTG
+	select USB_GADGET_DUALSPEED
+	help
+	   Selects the Synopsys Driver for the DWC_otg Controller.
+
+config USB_DWC_OTG_LPM
+	boolean "Enable LPM support"
+	depends on USB && EXPERIMENTAL
+	help
+	   Enables LPM support.
+
+config USB_GADGET_SNPS_DWC_OTG
+	boolean "Synopsys Driver for DWC_otg Controller"
+	depends on USB && EXPERIMENTAL
+	select USB_OTG
+	select USB_GADGET_DUALSPEED
+	help
+	   Selects the Synopsys Driver for the DWC_otg Controller.
+
+config USB_DWC_OTG_LPM
+	boolean "Enable LPM support"
+	depends on USB && EXPERIMENTAL
+	help
+	   Enables LPM support.
+
 #
 # USB Gadget Drivers
 #
diff --git a/drivers/usb/gadget/file_storage.c b/drivers/usb/gadget/file_storage.c
index 639e14a2fd15..1554bc098d23 100644
--- a/drivers/usb/gadget/file_storage.c
+++ b/drivers/usb/gadget/file_storage.c
@@ -572,8 +572,37 @@ config_desc = {
 	.iConfiguration =	FSG_STRING_CONFIG,
 	.bmAttributes =		USB_CONFIG_ATT_ONE | USB_CONFIG_ATT_SELFPOWER,
 	.bMaxPower =		CONFIG_USB_GADGET_VBUS_DRAW / 2,
+        //.bMaxPower =		0, //unused suggestion by DWC patch
 };
 
+#ifdef CONFIG_USB_DWC_OTG_LPM
+#define USB_DEVICE_CAPABILITY_20_EXTENSION	0x02
+#define USB_20_EXT_LPM				0x02
+typedef struct usb_dev_cap_20_ext_desc {
+	__u8 bLength;
+	__u8 bDescriptorType;
+	__u8 bDevCapabilityType;
+	__le32 bmAttributes;
+} __attribute__ ((__packed__)) usb_dev_cap_20_ext_desc_t;
+
+static struct usb_bos_20_ext_desc {
+	struct usb_bos_descriptor bos_desc;
+	struct usb_dev_cap_20_ext_desc dev_cap_20_ext_desc;
+} __attribute__ ((__packed__)) bos_20_ext_desc = {
+	{
+		.bLength =		sizeof(struct usb_bos_descriptor),
+		.bDescriptorType =	USB_DT_BOS,
+		.wTotalLength =		sizeof(struct usb_bos_20_ext_desc),
+		.bNumDeviceCaps =	1,
+	},
+	{
+		.bLength =		sizeof(struct usb_dev_cap_20_ext_desc),
+		.bDescriptorType =	USB_DT_DEVICE_CAPABILITY,
+		.bDevCapabilityType =	USB_DEVICE_CAPABILITY_20_EXTENSION,
+		.bmAttributes =		USB_20_EXT_LPM,
+	},
+};
+#endif
 
 static struct usb_qualifier_descriptor
 dev_qualifier = {
@@ -967,6 +996,24 @@ get_config:
 			value = usb_gadget_get_string(&fsg_stringtab,
 					w_value & 0xff, req->buf);
 			break;
+#ifdef CONFIG_USB_DWC_OTG_LPM
+		case USB_DT_BOS:
+			/* When the PCD has LPM enabled set the LPM
+			 * Feature bit to 1 when not enabled set the
+			 * bit to 0. */
+			if (usb_gadget_test_lpm_support(fsg->gadget)) {
+				VDBG(fsg, "LPM support enabled in DWC UDC PCD\n");
+				bos_20_ext_desc.dev_cap_20_ext_desc.bmAttributes |= USB_20_EXT_LPM;
+			} else {
+				VDBG(fsg, "LPM support disabled in DWC UDC PCD\n");
+				bos_20_ext_desc.dev_cap_20_ext_desc.bmAttributes &= ~USB_20_EXT_LPM;
+			}
+			DBG(fsg, "sending BOS descriptor to host\n");
+			value = sizeof bos_20_ext_desc;
+			memcpy(req->buf, &bos_20_ext_desc, value);
+			break;
+#endif
+
 		}
 		break;
 
@@ -2630,6 +2677,9 @@ static int received_cbw(struct fsg_dev *fsg, struct fsg_buffhd *bh)
 			fsg_set_halt(fsg, fsg->bulk_out);
 			halt_bulk_in_endpoint(fsg);
 		}
+		fsg->bulk_in->ops->set_halt(fsg->bulk_in, 3);
+		fsg_set_halt(fsg, fsg->bulk_out);
+		fsg->bulk_out->ops->set_halt(fsg->bulk_out, 3);
 		return -EINVAL;
 	}
 
@@ -2986,7 +3036,8 @@ static void handle_exception(struct fsg_dev *fsg)
 		 * bulk endpoint, clear the halt now.  (The SuperH UDC
 		 * requires this.) */
 		if (test_and_clear_bit(IGNORE_BULK_OUT, &fsg->atomic_bitflags))
-			usb_ep_clear_halt(fsg->bulk_in);
+			//usb_ep_clear_halt(fsg->bulk_in); //DWC patch:
+			fsg->bulk_in->ops->set_halt(fsg->bulk_in, 2);
 
 		if (transport_is_bbb()) {
 			if (fsg->ep0_req_tag == exception_req_tag)
@@ -3060,6 +3111,9 @@ static int fsg_main_thread(void *fsg_)
 	 * that expects a __user pointer and it will work okay. */
 	set_fs(get_ds());
 
+	/* Setting this thread high priority */
+	set_user_nice(current, -20);
+
 	/* The main loop */
 	while (fsg->state != FSG_STATE_TERMINATED) {
 		if (exception_in_progress(fsg) || signal_pending(current)) {
@@ -3207,6 +3261,13 @@ static int __init check_parameters(struct fsg_dev *fsg)
 		gcnum = usb_gadget_controller_number(fsg->gadget);
 		if (gcnum >= 0)
 			mod_data.release = 0x0300 + gcnum;
+		else if (gadget_is_dwc_otg(fsg->gadget)) {
+			mod_data.release = __constant_cpu_to_le16 (0x0200);
+			mod_data.vendor  = __constant_cpu_to_le16 (0x053f);
+			if (mod_data.product == DRIVER_PRODUCT_ID) {
+				mod_data.product  = __constant_cpu_to_le16 (0x0000);
+			}
+		}
 		else {
 			WARNING(fsg, "controller '%s' not recognized\n",
 				fsg->gadget->name);
@@ -3450,6 +3511,13 @@ static int __init fsg_bind(struct usb_gadget *gadget)
 
 	rc = -ENOMEM;
 
+#ifdef CONFIG_USB_DWC_OTG_LPM
+	/* When LPM is enabled, Inform the host that the remote wake
+	 * up capability is supported. */
+	if (usb_gadget_test_lpm_support(fsg->gadget))
+		config_desc.bmAttributes |= USB_CONFIG_ATT_WAKEUP;
+#endif
+
 	/* Allocate the request and buffer for endpoint 0 */
 	fsg->ep0req = req = usb_ep_alloc_request(fsg->ep0, GFP_KERNEL);
 	if (!req)
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index ab085f12d570..3b8ea349394c 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -543,6 +543,19 @@ config USB_HWA_HCD
 	  To compile this driver a module, choose M here: the module
 	  will be called "hwa-hc".
 
+config USB_DWCOTG
+	tristate "Synopsis DWC host support"
+	depends on USB
+	help
+	  The Synopsis DWC controller is a dual-role
+	  host/peripheral/OTG ("On The Go") USB controllers.
+
+	  Enable this option to support this IP in host controller mode.
+	  If unsure, say N.
+
+	  To compile this driver as a module, choose M here: the
+	  modules built will be called dwc_otg and dwc_common_port.
+
 config USB_IMX21_HCD
        tristate "iMX21 HCD support"
        depends on USB && ARM && MACH_MX21
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 624a362f2fee..c4264cee6814 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -32,6 +32,8 @@ obj-$(CONFIG_USB_U132_HCD)	+= u132-hcd.o
 obj-$(CONFIG_USB_R8A66597_HCD)	+= r8a66597-hcd.o
 obj-$(CONFIG_USB_ISP1760_HCD)	+= isp1760.o
 obj-$(CONFIG_USB_HWA_HCD)	+= hwa-hc.o
+
+obj-$(CONFIG_USB_DWCOTG)        += dwc_otg/ dwc_common_port/
 obj-$(CONFIG_USB_IMX21_HCD)	+= imx21-hcd.o
 obj-$(CONFIG_USB_FSL_MPH_DR_OF)	+= fsl-mph-dr-of.o
 obj-$(CONFIG_USB_OCTEON2_COMMON) += octeon2-common.o
diff --git a/drivers/usb/host/dwc_common_port/Makefile b/drivers/usb/host/dwc_common_port/Makefile
new file mode 100644
index 000000000000..3b2ac7061261
--- /dev/null
+++ b/drivers/usb/host/dwc_common_port/Makefile
@@ -0,0 +1,44 @@
+#
+# Makefile for DWC_common library
+#
+
+ifneq ($(KERNELRELEASE),)
+
+#CPPFLAGS	+= -DDEBUG_MEMORY
+
+CPPFLAGS	+= -DDEBUG
+CPPFLAGS	+= -DDWC_LINUX
+
+obj-$(CONFIG_USB_DWCOTG)	+= dwc_common_port_lib.o
+dwc_common_port_lib-objs	:= dwc_cc.o dwc_modpow.o dwc_dh.o \
+				   dwc_crypto.o dwc_notifier.o \
+				   dwc_common_linux.o dwc_mem.o
+
+kernrelwd := $(subst ., ,$(KERNELRELEASE))
+kernrel3 := $(word 1,$(kernrelwd)).$(word 2,$(kernrelwd)).$(word 3,$(kernrelwd))
+
+ifneq ($(kernrel3),2.6.20)
+# grayg - I only know that we use EXTRA_CFLAGS in 2.6.31 actually
+EXTRA_CFLAGS += $(CPPFLAGS)
+endif
+
+else
+
+ifeq ($(DOXYGEN),)
+DOXYGEN		:= $(DOXYGEN)
+endif
+
+default:
+	$(MAKE) -C$(KDIR) M=$(PWD) modules
+
+docs:	$(wildcard *.[hc]) doc/doxygen.cfg
+	$(DOXYGEN) doc/doxygen.cfg
+
+tags:	$(wildcard *.[hc])
+	$(CTAGS) -e $(wildcard *.[hc]) $(wildcard linux/*.[hc]) $(wildcard $(KDIR)/include/linux/usb*.h)
+
+endif
+
+clean:
+	rm -rf   *.o *.ko .*cmd *.mod.c .tmp_versions Module.symvers
+
diff --git a/drivers/usb/host/dwc_common_port/Makefile.linux b/drivers/usb/host/dwc_common_port/Makefile.linux
new file mode 100644
index 000000000000..a553a9d52f86
--- /dev/null
+++ b/drivers/usb/host/dwc_common_port/Makefile.linux
@@ -0,0 +1,36 @@
+#
+# Makefile for DWC_common library
+#
+ifneq ($(KERNELRELEASE),)
+
+#CPPFLAGS	+= -DDEBUG_MEMORY
+
+#CPPFLAGS	+= -DDEBUG
+CPPFLAGS	+= -DDWC_LINUX
+
+obj-m		:= dwc_common_port_lib.o
+dwc_common_port_lib-objs	:= dwc_cc.o dwc_modpow.o dwc_dh.o \
+				   dwc_crypto.o dwc_notifier.o \
+				   dwc_common_linux.o dwc_mem.o
+
+else
+
+
+ifeq ($(DOXYGEN),)
+DOXYGEN		:= $(DOXYGEN)
+endif
+
+default:
+	$(MAKE) -C$(KDIR) M=$(PWD) modules
+
+docs:	$(wildcard *.[hc]) doc/doxygen.cfg
+	$(DOXYGEN) doc/doxygen.cfg
+
+tags:	$(wildcard *.[hc])
+	$(CTAGS) -e $(wildcard *.[hc]) $(wildcard linux/*.[hc]) $(wildcard $(KDIR)/include/linux/usb*.h)
+
+endif
+
+clean:
+	rm -rf   *.o *.ko .*cmd *.mod.c .tmp_versions Module.symvers
+
diff --git a/drivers/usb/host/dwc_common_port/doc/doxygen.cfg b/drivers/usb/host/dwc_common_port/doc/doxygen.cfg
new file mode 100644
index 000000000000..605b9dab94e5
--- /dev/null
+++ b/drivers/usb/host/dwc_common_port/doc/doxygen.cfg
@@ -0,0 +1,270 @@
+# Doxyfile 1.4.5
+
+#---------------------------------------------------------------------------
+# Project related configuration options
+#---------------------------------------------------------------------------
+PROJECT_NAME           = "Synopsys DWC Portability and Common Library for UWB"
+PROJECT_NUMBER         = 
+OUTPUT_DIRECTORY       = doc
+CREATE_SUBDIRS         = NO
+OUTPUT_LANGUAGE        = English
+BRIEF_MEMBER_DESC      = YES
+REPEAT_BRIEF           = YES
+ABBREVIATE_BRIEF       = "The $name class" \
+                         "The $name widget" \
+                         "The $name file" \
+                         is \
+                         provides \
+                         specifies \
+                         contains \
+                         represents \
+                         a \
+                         an \
+                         the
+ALWAYS_DETAILED_SEC    = YES
+INLINE_INHERITED_MEMB  = NO
+FULL_PATH_NAMES        = NO
+STRIP_FROM_PATH        = ..
+STRIP_FROM_INC_PATH    = 
+SHORT_NAMES            = NO
+JAVADOC_AUTOBRIEF      = YES
+MULTILINE_CPP_IS_BRIEF = NO
+DETAILS_AT_TOP         = YES
+INHERIT_DOCS           = YES
+SEPARATE_MEMBER_PAGES  = NO
+TAB_SIZE               = 8
+ALIASES                = 
+OPTIMIZE_OUTPUT_FOR_C  = YES
+OPTIMIZE_OUTPUT_JAVA   = NO
+BUILTIN_STL_SUPPORT    = NO
+DISTRIBUTE_GROUP_DOC   = NO
+SUBGROUPING            = NO
+#---------------------------------------------------------------------------
+# Build related configuration options
+#---------------------------------------------------------------------------
+EXTRACT_ALL            = NO
+EXTRACT_PRIVATE        = NO
+EXTRACT_STATIC         = YES
+EXTRACT_LOCAL_CLASSES  = NO
+EXTRACT_LOCAL_METHODS  = NO
+HIDE_UNDOC_MEMBERS     = NO
+HIDE_UNDOC_CLASSES     = NO
+HIDE_FRIEND_COMPOUNDS  = NO
+HIDE_IN_BODY_DOCS      = NO
+INTERNAL_DOCS          = NO
+CASE_SENSE_NAMES       = YES
+HIDE_SCOPE_NAMES       = NO
+SHOW_INCLUDE_FILES     = NO
+INLINE_INFO            = YES
+SORT_MEMBER_DOCS       = NO
+SORT_BRIEF_DOCS        = NO
+SORT_BY_SCOPE_NAME     = NO
+GENERATE_TODOLIST      = YES
+GENERATE_TESTLIST      = YES
+GENERATE_BUGLIST       = YES
+GENERATE_DEPRECATEDLIST= YES
+ENABLED_SECTIONS       = 
+MAX_INITIALIZER_LINES  = 30
+SHOW_USED_FILES        = YES
+SHOW_DIRECTORIES       = YES
+FILE_VERSION_FILTER    = 
+#---------------------------------------------------------------------------
+# configuration options related to warning and progress messages
+#---------------------------------------------------------------------------
+QUIET                  = YES
+WARNINGS               = YES
+WARN_IF_UNDOCUMENTED   = NO
+WARN_IF_DOC_ERROR      = YES
+WARN_NO_PARAMDOC       = YES
+WARN_FORMAT            = "$file:$line: $text"
+WARN_LOGFILE           = 
+#---------------------------------------------------------------------------
+# configuration options related to the input files
+#---------------------------------------------------------------------------
+INPUT                  = .
+FILE_PATTERNS          = *.c \
+                         *.cc \
+                         *.cxx \
+                         *.cpp \
+                         *.c++ \
+                         *.d \
+                         *.java \
+                         *.ii \
+                         *.ixx \
+                         *.ipp \
+                         *.i++ \
+                         *.inl \
+                         *.h \
+                         *.hh \
+                         *.hxx \
+                         *.hpp \
+                         *.h++ \
+                         *.idl \
+                         *.odl \
+                         *.cs \
+                         *.php \
+                         *.php3 \
+                         *.inc \
+                         *.m \
+                         *.mm \
+                         *.dox \
+                         *.py \
+                         *.C \
+                         *.CC \
+                         *.C++ \
+                         *.II \
+                         *.I++ \
+                         *.H \
+                         *.HH \
+                         *.H++ \
+                         *.CS \
+                         *.PHP \
+                         *.PHP3 \
+                         *.M \
+                         *.MM \
+                         *.PY
+RECURSIVE              = NO
+EXCLUDE                = 
+EXCLUDE_SYMLINKS       = NO
+EXCLUDE_PATTERNS       = 
+EXAMPLE_PATH           = 
+EXAMPLE_PATTERNS       = *
+EXAMPLE_RECURSIVE      = NO
+IMAGE_PATH             = 
+INPUT_FILTER           = 
+FILTER_PATTERNS        = 
+FILTER_SOURCE_FILES    = NO
+#---------------------------------------------------------------------------
+# configuration options related to source browsing
+#---------------------------------------------------------------------------
+SOURCE_BROWSER         = NO
+INLINE_SOURCES         = NO
+STRIP_CODE_COMMENTS    = YES
+REFERENCED_BY_RELATION = YES
+REFERENCES_RELATION    = YES
+USE_HTAGS              = NO
+VERBATIM_HEADERS       = NO
+#---------------------------------------------------------------------------
+# configuration options related to the alphabetical class index
+#---------------------------------------------------------------------------
+ALPHABETICAL_INDEX     = NO
+COLS_IN_ALPHA_INDEX    = 5
+IGNORE_PREFIX          = 
+#---------------------------------------------------------------------------
+# configuration options related to the HTML output
+#---------------------------------------------------------------------------
+GENERATE_HTML          = YES
+HTML_OUTPUT            = html
+HTML_FILE_EXTENSION    = .html
+HTML_HEADER            = 
+HTML_FOOTER            = 
+HTML_STYLESHEET        = 
+HTML_ALIGN_MEMBERS     = YES
+GENERATE_HTMLHELP      = NO
+CHM_FILE               = 
+HHC_LOCATION           = 
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diff --git a/drivers/usb/host/dwc_common_port/doc/html/dir_c13d72e45af28cdc461a5f284d3d36fc.html b/drivers/usb/host/dwc_common_port/doc/html/dir_c13d72e45af28cdc461a5f284d3d36fc.html
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+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Synopsys DWC Portability and Common Library for UWB: dwc_common_port/ Directory Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
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+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="dirs.html"><span>Directories</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="nav">
+<a class="el" href="dir_c13d72e45af28cdc461a5f284d3d36fc.html">dwc_common_port</a></div>
+<h1>dwc_common_port Directory Reference</h1>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Files</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">file &nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_cc.c</b></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">file &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__cc_8h.html">dwc_cc.h</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This file defines the Context Context library. <br></td></tr>
+
+<p>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">file &nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_common_linux.c</b></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">file &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__crypto_8c.html">dwc_crypto.c</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This file contains the WUSB cryptographic routines. <br></td></tr>
+
+<p>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">file &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__crypto_8h.html">dwc_crypto.h</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This file contains declarations for the WUSB Cryptographic routines as defined in the WUSB spec. <br></td></tr>
+
+<p>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">file &nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_dh.c</b></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">file &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__dh_8h.html">dwc_dh.h</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This file defines the common functions on device and host for performing numeric association as defined in the WUSB spec. <br></td></tr>
+
+<p>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">file &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__list_8h.html">dwc_list.h</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This file defines linked list operations. <br></td></tr>
+
+<p>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">file &nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_mem.c</b></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">file &nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_modpow.c</b></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">file &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__modpow_8h.html">dwc_modpow.h</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This file defines the module exponentiation function which is only used internally by the DWC UWB modules for calculation of PKs during numeric association. <br></td></tr>
+
+<p>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">file &nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_notifier.c</b></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">file &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__notifier_8h.html">dwc_notifier.h</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">A simple implementation of the Observer pattern. <br></td></tr>
+
+<p>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">file &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html">dwc_os.h</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">DWC portability library, low level os-wrapper functions. <br></td></tr>
+
+<p>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">file &nbsp;</td><td class="memItemRight" valign="bottom"><b>usb.h</b></td></tr>
+
+</table>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:50 2009 for Synopsys DWC Portability and Common Library for UWB by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_common_port/doc/html/dirs.html b/drivers/usb/host/dwc_common_port/doc/html/dirs.html
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index 000000000000..baaf2da9b481
--- /dev/null
+++ b/drivers/usb/host/dwc_common_port/doc/html/dirs.html
@@ -0,0 +1,22 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Synopsys DWC Portability and Common Library for UWB: Directory Hierarchy</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
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+<!-- Generated by Doxygen 1.4.7 -->
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+    <li id="current"><a href="dirs.html"><span>Directories</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<h1>Synopsys DWC Portability and Common Library for UWB Directories</h1>This directory hierarchy is sorted roughly, but not completely, alphabetically:<ul>
+<li><a class="el" href="dir_c13d72e45af28cdc461a5f284d3d36fc.html">dwc_common_port</a>
+</ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:50 2009 for Synopsys DWC Portability and Common Library for UWB by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
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+++ b/drivers/usb/host/dwc_common_port/doc/html/dwc__cc_8h.html
@@ -0,0 +1,709 @@
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+<title>Synopsys DWC Portability and Common Library for UWB: dwc_cc.h File Reference</title>
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+<a class="el" href="dir_c13d72e45af28cdc461a5f284d3d36fc.html">dwc_common_port</a></div>
+<h1>dwc_cc.h File Reference</h1><hr><a name="_details"></a><h2>Detailed Description</h2>
+This file defines the Context Context library. 
+<p>
+The main data structure is dwc_cc_if_t which is returned by either the dwc_cc_if_alloc function or returned by the module to the user via a provided function. The data structure is opaque and should only be manipulated via the functions provied in this API.<p>
+It manages a list of connection contexts and operations can be performed to add, remove, query, search, and change, those contexts. Additionally, a dwc_notifier_t object can be requested from the manager so that the user can be notified whenever the context list has changed. 
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Connection Context Operations</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">dwc_cc_if_t *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__cc_8h.html#bc9d8a8d9ef41b4167ff8c02d44c2d15">dwc_cc_if_alloc</a> (dwc_notifier_t *notifier, unsigned is_host)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function allocates memory for a dwc_cc_if_t structure, initializes fields to default values, and returns a pointer to the structure or NULL on error.  <a href="#bc9d8a8d9ef41b4167ff8c02d44c2d15"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__cc_8h.html#a4f59eb28ddb889c7bf072c6291f1b52">dwc_cc_if_free</a> (dwc_cc_if_t *cc_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Frees the memory for the specified CC structure allocated from <a class="el" href="dwc__cc_8h.html#bc9d8a8d9ef41b4167ff8c02d44c2d15">dwc_cc_if_alloc()</a>.  <a href="#a4f59eb28ddb889c7bf072c6291f1b52"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__cc_8h.html#ee140bfd74d33e7456bc4b2d8c23e834">dwc_cc_clear</a> (dwc_cc_if_t *cc_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Removes all contexts from the connection context list.  <a href="#ee140bfd74d33e7456bc4b2d8c23e834"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__cc_8h.html#2e04f137cbe68b5db7cdd432af50efea">dwc_cc_add</a> (dwc_cc_if_t *cc_if, uint8_t *chid, uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Adds a connection context (CHID, CK, CDID, Name) to the connection context list.  <a href="#2e04f137cbe68b5db7cdd432af50efea"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__cc_8h.html#c0009353a8c89d81c0df4d838687136a">dwc_cc_change</a> (dwc_cc_if_t *cc_if, int32_t id, uint8_t *chid, uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Changes the CHID, CK, CDID, or Name values of a connection context in the list, preserving any accumulated statistics.  <a href="#c0009353a8c89d81c0df4d838687136a"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__cc_8h.html#3c0b5c59eebbb92cededfa36bc8508d5">dwc_cc_remove</a> (dwc_cc_if_t *cc_if, int32_t id)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Remove the specified connection context.  <a href="#3c0b5c59eebbb92cededfa36bc8508d5"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint8_t *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__cc_8h.html#9804503a6ae17fa6650da86d94e3a11d">dwc_cc_data_for_save</a> (dwc_cc_if_t *cc_if, unsigned int *length)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get a binary block of data for the connection context list and attributes.  <a href="#9804503a6ae17fa6650da86d94e3a11d"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__cc_8h.html#0410780d5218fd44169bda226bfca65f">dwc_cc_restore_from_data</a> (dwc_cc_if_t *cc_if, uint8_t *data, unsigned int length)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Restore the connection context list from the binary data that was previously returned from a call to dwc_cc_data_for_save.  <a href="#0410780d5218fd44169bda226bfca65f"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__cc_8h.html#97b48adfc54eb821a1d904d66fa554f1">dwc_cc_match_chid</a> (dwc_cc_if_t *cc_if, uint8_t *chid)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Find the connection context from the specified CHID.  <a href="#97b48adfc54eb821a1d904d66fa554f1"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__cc_8h.html#bae07aa2652e5fad05d5dafa81009846">dwc_cc_match_cdid</a> (dwc_cc_if_t *cc_if, uint8_t *cdid)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Find the connection context from the specified CDID.  <a href="#bae07aa2652e5fad05d5dafa81009846"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint8_t *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__cc_8h.html#07124231ec335379a59eb4c8198da119">dwc_cc_ck</a> (dwc_cc_if_t *cc_if, int32_t id)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Retrieve the CK from the specified connection context.  <a href="#07124231ec335379a59eb4c8198da119"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint8_t *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__cc_8h.html#135f9661d688df3be90b57cf8fe0e171">dwc_cc_chid</a> (dwc_cc_if_t *cc_if, int32_t id)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Retrieve the CHID from the specified connection context.  <a href="#135f9661d688df3be90b57cf8fe0e171"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint8_t *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__cc_8h.html#667f32649b4dcd8210bc54a307589162">dwc_cc_cdid</a> (dwc_cc_if_t *cc_if, int32_t id)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Retrieve the CDID from the specified connection context.  <a href="#667f32649b4dcd8210bc54a307589162"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="a4de7adf817a7a2d4aa323fb2545139d"></a><!-- doxytag: member="dwc_cc.h::dwc_cc_name" ref="a4de7adf817a7a2d4aa323fb2545139d" args="(dwc_cc_if_t *cc_if, int32_t id, uint8_t *length)" -->
+uint8_t *&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_cc_name</b> (dwc_cc_if_t *cc_if, int32_t id, uint8_t *length)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static unsigned&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__cc_8h.html#f90b3442b6c53b3e89c0580e1fb20b8f">dwc_assoc_is_not_zero_id</a> (uint8_t *id)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Checks a buffer for non-zero.  <a href="#f90b3442b6c53b3e89c0580e1fb20b8f"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static unsigned&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__cc_8h.html#8485befd69b4bfbe5e9f13b9b24acda1">dwc_assoc_is_zero_id</a> (uint8_t *id)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Checks a buffer for zero.  <a href="#8485befd69b4bfbe5e9f13b9b24acda1"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__cc_8h.html#46be9c2781971918e4f7d0e19699fe9d">dwc_print_id_string</a> (char *buffer, uint8_t *id)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Prints an ASCII representation for the 16-byte chid, cdid, or ck, into buffer.  <a href="#46be9c2781971918e4f7d0e19699fe9d"></a><br></td></tr>
+<tr><td colspan="2"><br><h2>Defines</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e02c11fa4d80f6d2590207be1c0683fe"></a><!-- doxytag: member="dwc_cc.h::DWC_CC_LIST_CHANGED_NOTIFICATION" ref="e02c11fa4d80f6d2590207be1c0683fe" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_CC_LIST_CHANGED_NOTIFICATION</b>&nbsp;&nbsp;&nbsp;&quot;DWC_CC_LIST_CHANGED_NOTIFICATION&quot;</td></tr>
+
+<tr><td colspan="2"><br><h2>Typedefs</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="29bd8a8640eddddd07c7778dcbb57129"></a><!-- doxytag: member="dwc_cc.h::dwc_cc_if_t" ref="29bd8a8640eddddd07c7778dcbb57129" args="" -->
+typedef dwc_cc_if&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_cc_if_t</b></td></tr>
+
+</table>
+<hr><h2>Function Documentation</h2>
+<a class="anchor" name="bc9d8a8d9ef41b4167ff8c02d44c2d15"></a><!-- doxytag: member="dwc_cc.h::dwc_cc_if_alloc" ref="bc9d8a8d9ef41b4167ff8c02d44c2d15" args="(dwc_notifier_t *notifier, unsigned is_host)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">dwc_cc_if_t* dwc_cc_if_alloc           </td>
+          <td>(</td>
+          <td class="paramtype">dwc_notifier_t *&nbsp;</td>
+          <td class="paramname"> <em>notifier</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">unsigned&nbsp;</td>
+          <td class="paramname"> <em>is_host</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function allocates memory for a dwc_cc_if_t structure, initializes fields to default values, and returns a pointer to the structure or NULL on error. 
+<p>
+
+</div>
+</div><p>
+<a class="anchor" name="a4f59eb28ddb889c7bf072c6291f1b52"></a><!-- doxytag: member="dwc_cc.h::dwc_cc_if_free" ref="a4f59eb28ddb889c7bf072c6291f1b52" args="(dwc_cc_if_t *cc_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_cc_if_free           </td>
+          <td>(</td>
+          <td class="paramtype">dwc_cc_if_t *&nbsp;</td>
+          <td class="paramname"> <em>cc_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Frees the memory for the specified CC structure allocated from <a class="el" href="dwc__cc_8h.html#bc9d8a8d9ef41b4167ff8c02d44c2d15">dwc_cc_if_alloc()</a>. 
+<p>
+
+</div>
+</div><p>
+<a class="anchor" name="ee140bfd74d33e7456bc4b2d8c23e834"></a><!-- doxytag: member="dwc_cc.h::dwc_cc_clear" ref="ee140bfd74d33e7456bc4b2d8c23e834" args="(dwc_cc_if_t *cc_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_cc_clear           </td>
+          <td>(</td>
+          <td class="paramtype">dwc_cc_if_t *&nbsp;</td>
+          <td class="paramname"> <em>cc_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Removes all contexts from the connection context list. 
+<p>
+
+</div>
+</div><p>
+<a class="anchor" name="2e04f137cbe68b5db7cdd432af50efea"></a><!-- doxytag: member="dwc_cc.h::dwc_cc_add" ref="2e04f137cbe68b5db7cdd432af50efea" args="(dwc_cc_if_t *cc_if, uint8_t *chid, uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t dwc_cc_add           </td>
+          <td>(</td>
+          <td class="paramtype">dwc_cc_if_t *&nbsp;</td>
+          <td class="paramname"> <em>cc_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>chid</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>cdid</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>ck</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>name</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t&nbsp;</td>
+          <td class="paramname"> <em>length</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Adds a connection context (CHID, CK, CDID, Name) to the connection context list. 
+<p>
+If a CHID already exists, the CK and name are overwritten. Statistics are not overwritten.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>cc_if</em>&nbsp;</td><td>The cc_if structure. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>chid</em>&nbsp;</td><td>A pointer to the 16-byte CHID. This value will be copied. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ck</em>&nbsp;</td><td>A pointer to the 16-byte CK. This value will be copied. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>cdid</em>&nbsp;</td><td>A pointer to the 16-byte CDID. This value will be copied. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>name</em>&nbsp;</td><td>An optional host friendly name as defined in the association model spec. Must be a UTF16-LE unicode string. Can be NULL to indicated no name. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>length</em>&nbsp;</td><td>The length othe unicode string. </td></tr>
+  </table>
+</dl>
+<dl compact><dt><b>Returns:</b></dt><dd>A unique identifier used to refer to this context that is valid for as long as this context is still in the list. </dd></dl>
+
+</div>
+</div><p>
+<a class="anchor" name="c0009353a8c89d81c0df4d838687136a"></a><!-- doxytag: member="dwc_cc.h::dwc_cc_change" ref="c0009353a8c89d81c0df4d838687136a" args="(dwc_cc_if_t *cc_if, int32_t id, uint8_t *chid, uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_cc_change           </td>
+          <td>(</td>
+          <td class="paramtype">dwc_cc_if_t *&nbsp;</td>
+          <td class="paramname"> <em>cc_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&nbsp;</td>
+          <td class="paramname"> <em>id</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>chid</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>cdid</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>ck</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>name</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t&nbsp;</td>
+          <td class="paramname"> <em>length</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Changes the CHID, CK, CDID, or Name values of a connection context in the list, preserving any accumulated statistics. 
+<p>
+This would typically be called if the host decideds to change the context with a SET_CONNECTION request.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>cc_if</em>&nbsp;</td><td>The cc_if structure. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>id</em>&nbsp;</td><td>The identifier of the connection context. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>chid</em>&nbsp;</td><td>A pointer to the 16-byte CHID. This value will be copied. NULL indicates no change. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>cdid</em>&nbsp;</td><td>A pointer to the 16-byte CDID. This value will be copied. NULL indicates no change. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ck</em>&nbsp;</td><td>A pointer to the 16-byte CK. This value will be copied. NULL indicates no change. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>name</em>&nbsp;</td><td>Host friendly name UTF16-LE. NULL indicates no change. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>length</em>&nbsp;</td><td>Length of name. </td></tr>
+  </table>
+</dl>
+
+</div>
+</div><p>
+<a class="anchor" name="3c0b5c59eebbb92cededfa36bc8508d5"></a><!-- doxytag: member="dwc_cc.h::dwc_cc_remove" ref="3c0b5c59eebbb92cededfa36bc8508d5" args="(dwc_cc_if_t *cc_if, int32_t id)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_cc_remove           </td>
+          <td>(</td>
+          <td class="paramtype">dwc_cc_if_t *&nbsp;</td>
+          <td class="paramname"> <em>cc_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&nbsp;</td>
+          <td class="paramname"> <em>id</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Remove the specified connection context. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>cc_if</em>&nbsp;</td><td>The cc_if structure. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>id</em>&nbsp;</td><td>The identifier of the connection context to remove. </td></tr>
+  </table>
+</dl>
+
+</div>
+</div><p>
+<a class="anchor" name="9804503a6ae17fa6650da86d94e3a11d"></a><!-- doxytag: member="dwc_cc.h::dwc_cc_data_for_save" ref="9804503a6ae17fa6650da86d94e3a11d" args="(dwc_cc_if_t *cc_if, unsigned int *length)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint8_t* dwc_cc_data_for_save           </td>
+          <td>(</td>
+          <td class="paramtype">dwc_cc_if_t *&nbsp;</td>
+          <td class="paramname"> <em>cc_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">unsigned int *&nbsp;</td>
+          <td class="paramname"> <em>length</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Get a binary block of data for the connection context list and attributes. 
+<p>
+This data can be used by the OS specific driver to save the connection context list into non-volatile memory.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>cc_if</em>&nbsp;</td><td>The cc_if structure. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>length</em>&nbsp;</td><td>Return the length of the data buffer. </td></tr>
+  </table>
+</dl>
+<dl compact><dt><b>Returns:</b></dt><dd>A pointer to the data buffer. The memory for this buffer should be freed with DWC_FREE() after use. </dd></dl>
+
+</div>
+</div><p>
+<a class="anchor" name="0410780d5218fd44169bda226bfca65f"></a><!-- doxytag: member="dwc_cc.h::dwc_cc_restore_from_data" ref="0410780d5218fd44169bda226bfca65f" args="(dwc_cc_if_t *cc_if, uint8_t *data, unsigned int length)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_cc_restore_from_data           </td>
+          <td>(</td>
+          <td class="paramtype">dwc_cc_if_t *&nbsp;</td>
+          <td class="paramname"> <em>cc_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>data</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">unsigned int&nbsp;</td>
+          <td class="paramname"> <em>length</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Restore the connection context list from the binary data that was previously returned from a call to dwc_cc_data_for_save. 
+<p>
+This can be used by the OS specific driver to load a connection context list from non-volatile memory.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>cc_if</em>&nbsp;</td><td>The cc_if structure. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>data</em>&nbsp;</td><td>The data bytes as returned from dwc_cc_data_for_save. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>length</em>&nbsp;</td><td>The length of the data. </td></tr>
+  </table>
+</dl>
+
+</div>
+</div><p>
+<a class="anchor" name="97b48adfc54eb821a1d904d66fa554f1"></a><!-- doxytag: member="dwc_cc.h::dwc_cc_match_chid" ref="97b48adfc54eb821a1d904d66fa554f1" args="(dwc_cc_if_t *cc_if, uint8_t *chid)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t dwc_cc_match_chid           </td>
+          <td>(</td>
+          <td class="paramtype">dwc_cc_if_t *&nbsp;</td>
+          <td class="paramname"> <em>cc_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>chid</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Find the connection context from the specified CHID. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>cc_if</em>&nbsp;</td><td>The cc_if structure. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>chid</em>&nbsp;</td><td>A pointer to the CHID data. </td></tr>
+  </table>
+</dl>
+<dl compact><dt><b>Returns:</b></dt><dd>A non-zero identifier of the connection context if the CHID matches. Otherwise returns 0. </dd></dl>
+
+</div>
+</div><p>
+<a class="anchor" name="bae07aa2652e5fad05d5dafa81009846"></a><!-- doxytag: member="dwc_cc.h::dwc_cc_match_cdid" ref="bae07aa2652e5fad05d5dafa81009846" args="(dwc_cc_if_t *cc_if, uint8_t *cdid)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t dwc_cc_match_cdid           </td>
+          <td>(</td>
+          <td class="paramtype">dwc_cc_if_t *&nbsp;</td>
+          <td class="paramname"> <em>cc_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>cdid</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Find the connection context from the specified CDID. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>cc_if</em>&nbsp;</td><td>The cc_if structure. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>cdid</em>&nbsp;</td><td>A pointer to the CDID data. </td></tr>
+  </table>
+</dl>
+<dl compact><dt><b>Returns:</b></dt><dd>A non-zero identifier of the connection context if the CHID matches. Otherwise returns 0. </dd></dl>
+
+</div>
+</div><p>
+<a class="anchor" name="07124231ec335379a59eb4c8198da119"></a><!-- doxytag: member="dwc_cc.h::dwc_cc_ck" ref="07124231ec335379a59eb4c8198da119" args="(dwc_cc_if_t *cc_if, int32_t id)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint8_t* dwc_cc_ck           </td>
+          <td>(</td>
+          <td class="paramtype">dwc_cc_if_t *&nbsp;</td>
+          <td class="paramname"> <em>cc_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&nbsp;</td>
+          <td class="paramname"> <em>id</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Retrieve the CK from the specified connection context. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>cc_if</em>&nbsp;</td><td>The cc_if structure. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>id</em>&nbsp;</td><td>The identifier of the connection context. </td></tr>
+  </table>
+</dl>
+<dl compact><dt><b>Returns:</b></dt><dd>A pointer to the CK data. The memory does not need to be freed. </dd></dl>
+
+</div>
+</div><p>
+<a class="anchor" name="135f9661d688df3be90b57cf8fe0e171"></a><!-- doxytag: member="dwc_cc.h::dwc_cc_chid" ref="135f9661d688df3be90b57cf8fe0e171" args="(dwc_cc_if_t *cc_if, int32_t id)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint8_t* dwc_cc_chid           </td>
+          <td>(</td>
+          <td class="paramtype">dwc_cc_if_t *&nbsp;</td>
+          <td class="paramname"> <em>cc_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&nbsp;</td>
+          <td class="paramname"> <em>id</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Retrieve the CHID from the specified connection context. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>cc_if</em>&nbsp;</td><td>The cc_if structure. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>id</em>&nbsp;</td><td>The identifier of the connection context. </td></tr>
+  </table>
+</dl>
+<dl compact><dt><b>Returns:</b></dt><dd>A pointer to the CHID data. The memory does not need to be freed. </dd></dl>
+
+</div>
+</div><p>
+<a class="anchor" name="667f32649b4dcd8210bc54a307589162"></a><!-- doxytag: member="dwc_cc.h::dwc_cc_cdid" ref="667f32649b4dcd8210bc54a307589162" args="(dwc_cc_if_t *cc_if, int32_t id)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint8_t* dwc_cc_cdid           </td>
+          <td>(</td>
+          <td class="paramtype">dwc_cc_if_t *&nbsp;</td>
+          <td class="paramname"> <em>cc_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&nbsp;</td>
+          <td class="paramname"> <em>id</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Retrieve the CDID from the specified connection context. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>cc_if</em>&nbsp;</td><td>The cc_if structure. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>id</em>&nbsp;</td><td>The identifier of the connection context. </td></tr>
+  </table>
+</dl>
+<dl compact><dt><b>Returns:</b></dt><dd>A pointer to the CDID data. The memory does not need to be freed. </dd></dl>
+
+</div>
+</div><p>
+<a class="anchor" name="f90b3442b6c53b3e89c0580e1fb20b8f"></a><!-- doxytag: member="dwc_cc.h::dwc_assoc_is_not_zero_id" ref="f90b3442b6c53b3e89c0580e1fb20b8f" args="(uint8_t *id)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static unsigned dwc_assoc_is_not_zero_id           </td>
+          <td>(</td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>id</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [inline, static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Checks a buffer for non-zero. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>id</em>&nbsp;</td><td>A pointer to a 16 byte buffer. </td></tr>
+  </table>
+</dl>
+<dl compact><dt><b>Returns:</b></dt><dd>true if the 16 byte value is non-zero. </dd></dl>
+
+</div>
+</div><p>
+<a class="anchor" name="8485befd69b4bfbe5e9f13b9b24acda1"></a><!-- doxytag: member="dwc_cc.h::dwc_assoc_is_zero_id" ref="8485befd69b4bfbe5e9f13b9b24acda1" args="(uint8_t *id)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static unsigned dwc_assoc_is_zero_id           </td>
+          <td>(</td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>id</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [inline, static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Checks a buffer for zero. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>id</em>&nbsp;</td><td>A pointer to a 16 byte buffer. </td></tr>
+  </table>
+</dl>
+<dl compact><dt><b>Returns:</b></dt><dd>true if the 16 byte value is zero. </dd></dl>
+
+</div>
+</div><p>
+<a class="anchor" name="46be9c2781971918e4f7d0e19699fe9d"></a><!-- doxytag: member="dwc_cc.h::dwc_print_id_string" ref="46be9c2781971918e4f7d0e19699fe9d" args="(char *buffer, uint8_t *id)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static int dwc_print_id_string           </td>
+          <td>(</td>
+          <td class="paramtype">char *&nbsp;</td>
+          <td class="paramname"> <em>buffer</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>id</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [inline, static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Prints an ASCII representation for the 16-byte chid, cdid, or ck, into buffer. 
+<p>
+
+</div>
+</div><p>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:50 2009 for Synopsys DWC Portability and Common Library for UWB by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_common_port/doc/html/dwc__crypto_8c.html b/drivers/usb/host/dwc_common_port/doc/html/dwc__crypto_8c.html
new file mode 100644
index 000000000000..0e0e6e919b1b
--- /dev/null
+++ b/drivers/usb/host/dwc_common_port/doc/html/dwc__crypto_8c.html
@@ -0,0 +1,435 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Synopsys DWC Portability and Common Library for UWB: dwc_crypto.c File Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="dirs.html"><span>Directories</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="nav">
+<a class="el" href="dir_c13d72e45af28cdc461a5f284d3d36fc.html">dwc_common_port</a></div>
+<h1>dwc_crypto.c File Reference</h1><hr><a name="_details"></a><h2>Detailed Description</h2>
+This file contains the WUSB cryptographic routines. 
+<p>
+
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Functions</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="324bdad74366c72c0b42483dd8c3c538"></a><!-- doxytag: member="dwc_crypto.c::dump_bytes" ref="324bdad74366c72c0b42483dd8c3c538" args="(char *name, uint8_t *bytes, int len)" -->
+static void&nbsp;</td><td class="memItemRight" valign="bottom"><b>dump_bytes</b> (char *name, uint8_t *bytes, int len)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ea0e019e3f682dec4bb775a274196e45"></a><!-- doxytag: member="dwc_crypto.c::show_block" ref="ea0e019e3f682dec4bb775a274196e45" args="(const u8 *blk, const char *prefix, const char *suffix, int a)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><b>show_block</b> (const u8 *blk, const char *prefix, const char *suffix, int a)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__crypto_8c.html#b4591bca19d2bfc173d3f38d8a0f04e7">dwc_wusb_aes_encrypt</a> (u8 *src, u8 *key, u8 *dst)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Encrypts an array of bytes using the AES encryption engine.  <a href="#b4591bca19d2bfc173d3f38d8a0f04e7"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__crypto_8c.html#ebd0a4f3d48e8a5131125b080d402389">dwc_wusb_cmf</a> (u8 *key, u8 *nonce, char *label, u8 *bytes, int len, u8 *result)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">The CCM-MAC-FUNCTION described in section 6.5 of the WUSB spec.  <a href="#ebd0a4f3d48e8a5131125b080d402389"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__crypto_8c.html#a44578803c21449b5d98e6275e4a6f5f">dwc_wusb_prf</a> (int prf_len, u8 *key, u8 *nonce, char *label, u8 *bytes, int len, u8 *result)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">The PRF function described in section 6.5 of the WUSB spec.  <a href="#a44578803c21449b5d98e6275e4a6f5f"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__crypto_8c.html#74ae8ea78ee10c708d7c3e0c12665b0d">dwc_wusb_fill_ccm_nonce</a> (uint16_t haddr, uint16_t daddr, uint8_t *tkid, uint8_t *nonce)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Fills in CCM Nonce per the WUSB spec.  <a href="#74ae8ea78ee10c708d7c3e0c12665b0d"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__crypto_8c.html#79af51f4e6140e5a251041879b40ad03">dwc_wusb_gen_nonce</a> (uint16_t addr, uint8_t *nonce)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Generates a 16-byte cryptographic-grade random number for the Host/Device Nonce.  <a href="#79af51f4e6140e5a251041879b40ad03"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__crypto_8c.html#18f5b99bd27d2397550fbd340d39600a">dwc_wusb_gen_key</a> (uint8_t *ccm_nonce, uint8_t *mk, uint8_t *hnonce, uint8_t *dnonce, uint8_t *kck, uint8_t *ptk)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Generates the Session Key (PTK) and Key Confirmation Key (KCK) per the WUSB spec.  <a href="#18f5b99bd27d2397550fbd340d39600a"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__crypto_8c.html#ab0a16ae4126032ca99e1fbcaaa7c248">dwc_wusb_gen_mic</a> (uint8_t *ccm_nonce, uint8_t *kck, uint8_t *data, uint8_t *mic)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Generates the Message Integrity Code over the Handshake data per the WUSB spec.  <a href="#ab0a16ae4126032ca99e1fbcaaa7c248"></a><br></td></tr>
+</table>
+<hr><h2>Function Documentation</h2>
+<a class="anchor" name="b4591bca19d2bfc173d3f38d8a0f04e7"></a><!-- doxytag: member="dwc_crypto.c::dwc_wusb_aes_encrypt" ref="b4591bca19d2bfc173d3f38d8a0f04e7" args="(u8 *src, u8 *key, u8 *dst)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_wusb_aes_encrypt           </td>
+          <td>(</td>
+          <td class="paramtype">u8 *&nbsp;</td>
+          <td class="paramname"> <em>src</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8 *&nbsp;</td>
+          <td class="paramname"> <em>key</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8 *&nbsp;</td>
+          <td class="paramname"> <em>dst</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Encrypts an array of bytes using the AES encryption engine. 
+<p>
+If <code>dst</code> == <code>src</code>, then the bytes will be encrypted in-place.<p>
+<dl compact><dt><b>Returns:</b></dt><dd>0 on success, negative error code on error. </dd></dl>
+
+</div>
+</div><p>
+<a class="anchor" name="ebd0a4f3d48e8a5131125b080d402389"></a><!-- doxytag: member="dwc_crypto.c::dwc_wusb_cmf" ref="ebd0a4f3d48e8a5131125b080d402389" args="(u8 *key, u8 *nonce, char *label, u8 *bytes, int len, u8 *result)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_wusb_cmf           </td>
+          <td>(</td>
+          <td class="paramtype">u8 *&nbsp;</td>
+          <td class="paramname"> <em>key</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8 *&nbsp;</td>
+          <td class="paramname"> <em>nonce</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">char *&nbsp;</td>
+          <td class="paramname"> <em>label</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8 *&nbsp;</td>
+          <td class="paramname"> <em>bytes</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>len</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8 *&nbsp;</td>
+          <td class="paramname"> <em>result</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+The CCM-MAC-FUNCTION described in section 6.5 of the WUSB spec. 
+<p>
+This function takes a data string and returns the encrypted CBC Counter-mode MIC.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>key</em>&nbsp;</td><td>The 128-bit symmetric key. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>nonce</em>&nbsp;</td><td>The CCM nonce. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>label</em>&nbsp;</td><td>The unique 14-byte ASCII text label. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>bytes</em>&nbsp;</td><td>The byte array to be encrypted. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>len</em>&nbsp;</td><td>Length of the byte array. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>result</em>&nbsp;</td><td>Byte array to receive the 8-byte encrypted MIC. </td></tr>
+  </table>
+</dl>
+
+</div>
+</div><p>
+<a class="anchor" name="a44578803c21449b5d98e6275e4a6f5f"></a><!-- doxytag: member="dwc_crypto.c::dwc_wusb_prf" ref="a44578803c21449b5d98e6275e4a6f5f" args="(int prf_len, u8 *key, u8 *nonce, char *label, u8 *bytes, int len, u8 *result)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_wusb_prf           </td>
+          <td>(</td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>prf_len</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8 *&nbsp;</td>
+          <td class="paramname"> <em>key</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8 *&nbsp;</td>
+          <td class="paramname"> <em>nonce</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">char *&nbsp;</td>
+          <td class="paramname"> <em>label</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8 *&nbsp;</td>
+          <td class="paramname"> <em>bytes</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>len</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8 *&nbsp;</td>
+          <td class="paramname"> <em>result</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+The PRF function described in section 6.5 of the WUSB spec. 
+<p>
+This function concatenates MIC values returned from dwc_cmf() to create a value of the requested length.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>prf_len</em>&nbsp;</td><td>Length of the PRF function in bits (64, 128, or 256). </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>key,nonce,label,bytes,len</em>&nbsp;</td><td>Same as for dwc_cmf(). </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>result</em>&nbsp;</td><td>Byte array to receive the result. </td></tr>
+  </table>
+</dl>
+
+</div>
+</div><p>
+<a class="anchor" name="74ae8ea78ee10c708d7c3e0c12665b0d"></a><!-- doxytag: member="dwc_crypto.c::dwc_wusb_fill_ccm_nonce" ref="74ae8ea78ee10c708d7c3e0c12665b0d" args="(uint16_t haddr, uint16_t daddr, uint8_t *tkid, uint8_t *nonce)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_wusb_fill_ccm_nonce           </td>
+          <td>(</td>
+          <td class="paramtype">uint16_t&nbsp;</td>
+          <td class="paramname"> <em>haddr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint16_t&nbsp;</td>
+          <td class="paramname"> <em>daddr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>tkid</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>nonce</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Fills in CCM Nonce per the WUSB spec. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"><tt>[in]</tt>&nbsp;</td><td valign="top"><em>haddr</em>&nbsp;</td><td>Host address. </td></tr>
+    <tr><td valign="top"><tt>[in]</tt>&nbsp;</td><td valign="top"><em>daddr</em>&nbsp;</td><td>Device address. </td></tr>
+    <tr><td valign="top"><tt>[in]</tt>&nbsp;</td><td valign="top"><em>tkid</em>&nbsp;</td><td>Session Key(PTK) identifier. </td></tr>
+    <tr><td valign="top"><tt>[out]</tt>&nbsp;</td><td valign="top"><em>nonce</em>&nbsp;</td><td>Pointer to where the CCM Nonce output is to be written. </td></tr>
+  </table>
+</dl>
+
+</div>
+</div><p>
+<a class="anchor" name="79af51f4e6140e5a251041879b40ad03"></a><!-- doxytag: member="dwc_crypto.c::dwc_wusb_gen_nonce" ref="79af51f4e6140e5a251041879b40ad03" args="(uint16_t addr, uint8_t *nonce)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_wusb_gen_nonce           </td>
+          <td>(</td>
+          <td class="paramtype">uint16_t&nbsp;</td>
+          <td class="paramname"> <em>addr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>nonce</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Generates a 16-byte cryptographic-grade random number for the Host/Device Nonce. 
+<p>
+
+</div>
+</div><p>
+<a class="anchor" name="18f5b99bd27d2397550fbd340d39600a"></a><!-- doxytag: member="dwc_crypto.c::dwc_wusb_gen_key" ref="18f5b99bd27d2397550fbd340d39600a" args="(uint8_t *ccm_nonce, uint8_t *mk, uint8_t *hnonce, uint8_t *dnonce, uint8_t *kck, uint8_t *ptk)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_wusb_gen_key           </td>
+          <td>(</td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>ccm_nonce</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>mk</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>hnonce</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>dnonce</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>kck</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>ptk</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Generates the Session Key (PTK) and Key Confirmation Key (KCK) per the WUSB spec. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"><tt>[in]</tt>&nbsp;</td><td valign="top"><em>ccm_nonce</em>&nbsp;</td><td>Pointer to CCM Nonce. </td></tr>
+    <tr><td valign="top"><tt>[in]</tt>&nbsp;</td><td valign="top"><em>mk</em>&nbsp;</td><td>Master Key to derive the session from </td></tr>
+    <tr><td valign="top"><tt>[in]</tt>&nbsp;</td><td valign="top"><em>hnonce</em>&nbsp;</td><td>Pointer to Host Nonce. </td></tr>
+    <tr><td valign="top"><tt>[in]</tt>&nbsp;</td><td valign="top"><em>dnonce</em>&nbsp;</td><td>Pointer to Device Nonce. </td></tr>
+    <tr><td valign="top"><tt>[out]</tt>&nbsp;</td><td valign="top"><em>kck</em>&nbsp;</td><td>Pointer to where the KCK output is to be written. </td></tr>
+    <tr><td valign="top"><tt>[out]</tt>&nbsp;</td><td valign="top"><em>ptk</em>&nbsp;</td><td>Pointer to where the PTK output is to be written. </td></tr>
+  </table>
+</dl>
+
+</div>
+</div><p>
+<a class="anchor" name="ab0a16ae4126032ca99e1fbcaaa7c248"></a><!-- doxytag: member="dwc_crypto.c::dwc_wusb_gen_mic" ref="ab0a16ae4126032ca99e1fbcaaa7c248" args="(uint8_t *ccm_nonce, uint8_t *kck, uint8_t *data, uint8_t *mic)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_wusb_gen_mic           </td>
+          <td>(</td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>ccm_nonce</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>kck</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>data</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>mic</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Generates the Message Integrity Code over the Handshake data per the WUSB spec. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>ccm_nonce</em>&nbsp;</td><td>Pointer to CCM Nonce. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>kck</em>&nbsp;</td><td>Pointer to Key Confirmation Key. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>data</em>&nbsp;</td><td>Pointer to Handshake data to be checked. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>mic</em>&nbsp;</td><td>Pointer to where the MIC output is to be written. </td></tr>
+  </table>
+</dl>
+
+</div>
+</div><p>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:50 2009 for Synopsys DWC Portability and Common Library for UWB by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_common_port/doc/html/dwc__crypto_8h.html b/drivers/usb/host/dwc_common_port/doc/html/dwc__crypto_8h.html
new file mode 100644
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--- /dev/null
+++ b/drivers/usb/host/dwc_common_port/doc/html/dwc__crypto_8h.html
@@ -0,0 +1,618 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Synopsys DWC Portability and Common Library for UWB: dwc_crypto.h File Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="dirs.html"><span>Directories</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="nav">
+<a class="el" href="dir_c13d72e45af28cdc461a5f284d3d36fc.html">dwc_common_port</a></div>
+<h1>dwc_crypto.h File Reference</h1><hr><a name="_details"></a><h2>Detailed Description</h2>
+This file contains declarations for the WUSB Cryptographic routines as defined in the WUSB spec. 
+<p>
+They are only to be used internally by the DWC UWB modules. 
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Functions</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__crypto_8h.html#b4591bca19d2bfc173d3f38d8a0f04e7">dwc_wusb_aes_encrypt</a> (u8 *src, u8 *key, u8 *dst)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Encrypts an array of bytes using the AES encryption engine.  <a href="#b4591bca19d2bfc173d3f38d8a0f04e7"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__crypto_8h.html#ebd0a4f3d48e8a5131125b080d402389">dwc_wusb_cmf</a> (u8 *key, u8 *nonce, char *label, u8 *bytes, int len, u8 *result)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">The CCM-MAC-FUNCTION described in section 6.5 of the WUSB spec.  <a href="#ebd0a4f3d48e8a5131125b080d402389"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__crypto_8h.html#a44578803c21449b5d98e6275e4a6f5f">dwc_wusb_prf</a> (int prf_len, u8 *key, u8 *nonce, char *label, u8 *bytes, int len, u8 *result)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">The PRF function described in section 6.5 of the WUSB spec.  <a href="#a44578803c21449b5d98e6275e4a6f5f"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__crypto_8h.html#d205747d6fb9d87d3c243c2d270ec9d5">dwc_wusb_prf_64</a> (u8 *key, u8 *nonce, char *label, u8 *bytes, int len, u8 *result)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">The PRF-64 function described in section 6.5 of the WUSB spec.  <a href="#d205747d6fb9d87d3c243c2d270ec9d5"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__crypto_8h.html#a391ec8ab9719b8e6c0a97595a1379d9">dwc_wusb_prf_128</a> (u8 *key, u8 *nonce, char *label, u8 *bytes, int len, u8 *result)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">The PRF-128 function described in section 6.5 of the WUSB spec.  <a href="#a391ec8ab9719b8e6c0a97595a1379d9"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__crypto_8h.html#2f6fedbb1295662ebf8e65eecb1630c8">dwc_wusb_prf_256</a> (u8 *key, u8 *nonce, char *label, u8 *bytes, int len, u8 *result)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">The PRF-256 function described in section 6.5 of the WUSB spec.  <a href="#2f6fedbb1295662ebf8e65eecb1630c8"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__crypto_8h.html#74ae8ea78ee10c708d7c3e0c12665b0d">dwc_wusb_fill_ccm_nonce</a> (uint16_t haddr, uint16_t daddr, uint8_t *tkid, uint8_t *nonce)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Fills in CCM Nonce per the WUSB spec.  <a href="#74ae8ea78ee10c708d7c3e0c12665b0d"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__crypto_8h.html#79af51f4e6140e5a251041879b40ad03">dwc_wusb_gen_nonce</a> (uint16_t addr, uint8_t *nonce)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Generates a 16-byte cryptographic-grade random number for the Host/Device Nonce.  <a href="#79af51f4e6140e5a251041879b40ad03"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__crypto_8h.html#18f5b99bd27d2397550fbd340d39600a">dwc_wusb_gen_key</a> (uint8_t *ccm_nonce, uint8_t *mk, uint8_t *hnonce, uint8_t *dnonce, uint8_t *kck, uint8_t *ptk)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Generates the Session Key (PTK) and Key Confirmation Key (KCK) per the WUSB spec.  <a href="#18f5b99bd27d2397550fbd340d39600a"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__crypto_8h.html#ab0a16ae4126032ca99e1fbcaaa7c248">dwc_wusb_gen_mic</a> (uint8_t *ccm_nonce, uint8_t *kck, uint8_t *data, uint8_t *mic)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Generates the Message Integrity Code over the Handshake data per the WUSB spec.  <a href="#ab0a16ae4126032ca99e1fbcaaa7c248"></a><br></td></tr>
+</table>
+<hr><h2>Function Documentation</h2>
+<a class="anchor" name="b4591bca19d2bfc173d3f38d8a0f04e7"></a><!-- doxytag: member="dwc_crypto.h::dwc_wusb_aes_encrypt" ref="b4591bca19d2bfc173d3f38d8a0f04e7" args="(u8 *src, u8 *key, u8 *dst)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_wusb_aes_encrypt           </td>
+          <td>(</td>
+          <td class="paramtype">u8 *&nbsp;</td>
+          <td class="paramname"> <em>src</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8 *&nbsp;</td>
+          <td class="paramname"> <em>key</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8 *&nbsp;</td>
+          <td class="paramname"> <em>dst</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Encrypts an array of bytes using the AES encryption engine. 
+<p>
+If <code>dst</code> == <code>src</code>, then the bytes will be encrypted in-place.<p>
+<dl compact><dt><b>Returns:</b></dt><dd>0 on success, negative error code on error. </dd></dl>
+
+</div>
+</div><p>
+<a class="anchor" name="ebd0a4f3d48e8a5131125b080d402389"></a><!-- doxytag: member="dwc_crypto.h::dwc_wusb_cmf" ref="ebd0a4f3d48e8a5131125b080d402389" args="(u8 *key, u8 *nonce, char *label, u8 *bytes, int len, u8 *result)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_wusb_cmf           </td>
+          <td>(</td>
+          <td class="paramtype">u8 *&nbsp;</td>
+          <td class="paramname"> <em>key</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8 *&nbsp;</td>
+          <td class="paramname"> <em>nonce</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">char *&nbsp;</td>
+          <td class="paramname"> <em>label</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8 *&nbsp;</td>
+          <td class="paramname"> <em>bytes</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>len</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8 *&nbsp;</td>
+          <td class="paramname"> <em>result</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+The CCM-MAC-FUNCTION described in section 6.5 of the WUSB spec. 
+<p>
+This function takes a data string and returns the encrypted CBC Counter-mode MIC.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>key</em>&nbsp;</td><td>The 128-bit symmetric key. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>nonce</em>&nbsp;</td><td>The CCM nonce. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>label</em>&nbsp;</td><td>The unique 14-byte ASCII text label. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>bytes</em>&nbsp;</td><td>The byte array to be encrypted. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>len</em>&nbsp;</td><td>Length of the byte array. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>result</em>&nbsp;</td><td>Byte array to receive the 8-byte encrypted MIC. </td></tr>
+  </table>
+</dl>
+
+</div>
+</div><p>
+<a class="anchor" name="a44578803c21449b5d98e6275e4a6f5f"></a><!-- doxytag: member="dwc_crypto.h::dwc_wusb_prf" ref="a44578803c21449b5d98e6275e4a6f5f" args="(int prf_len, u8 *key, u8 *nonce, char *label, u8 *bytes, int len, u8 *result)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_wusb_prf           </td>
+          <td>(</td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>prf_len</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8 *&nbsp;</td>
+          <td class="paramname"> <em>key</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8 *&nbsp;</td>
+          <td class="paramname"> <em>nonce</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">char *&nbsp;</td>
+          <td class="paramname"> <em>label</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8 *&nbsp;</td>
+          <td class="paramname"> <em>bytes</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>len</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8 *&nbsp;</td>
+          <td class="paramname"> <em>result</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+The PRF function described in section 6.5 of the WUSB spec. 
+<p>
+This function concatenates MIC values returned from dwc_cmf() to create a value of the requested length.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>prf_len</em>&nbsp;</td><td>Length of the PRF function in bits (64, 128, or 256). </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>key,nonce,label,bytes,len</em>&nbsp;</td><td>Same as for dwc_cmf(). </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>result</em>&nbsp;</td><td>Byte array to receive the result. </td></tr>
+  </table>
+</dl>
+
+</div>
+</div><p>
+<a class="anchor" name="d205747d6fb9d87d3c243c2d270ec9d5"></a><!-- doxytag: member="dwc_crypto.h::dwc_wusb_prf_64" ref="d205747d6fb9d87d3c243c2d270ec9d5" args="(u8 *key, u8 *nonce, char *label, u8 *bytes, int len, u8 *result)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static void dwc_wusb_prf_64           </td>
+          <td>(</td>
+          <td class="paramtype">u8 *&nbsp;</td>
+          <td class="paramname"> <em>key</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8 *&nbsp;</td>
+          <td class="paramname"> <em>nonce</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">char *&nbsp;</td>
+          <td class="paramname"> <em>label</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8 *&nbsp;</td>
+          <td class="paramname"> <em>bytes</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>len</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8 *&nbsp;</td>
+          <td class="paramname"> <em>result</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [inline, static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+The PRF-64 function described in section 6.5 of the WUSB spec. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>key,nonce,label,bytes,len,result</em>&nbsp;</td><td>Same as for dwc_prf(). </td></tr>
+  </table>
+</dl>
+
+</div>
+</div><p>
+<a class="anchor" name="a391ec8ab9719b8e6c0a97595a1379d9"></a><!-- doxytag: member="dwc_crypto.h::dwc_wusb_prf_128" ref="a391ec8ab9719b8e6c0a97595a1379d9" args="(u8 *key, u8 *nonce, char *label, u8 *bytes, int len, u8 *result)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static void dwc_wusb_prf_128           </td>
+          <td>(</td>
+          <td class="paramtype">u8 *&nbsp;</td>
+          <td class="paramname"> <em>key</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8 *&nbsp;</td>
+          <td class="paramname"> <em>nonce</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">char *&nbsp;</td>
+          <td class="paramname"> <em>label</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8 *&nbsp;</td>
+          <td class="paramname"> <em>bytes</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>len</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8 *&nbsp;</td>
+          <td class="paramname"> <em>result</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [inline, static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+The PRF-128 function described in section 6.5 of the WUSB spec. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>key,nonce,label,bytes,len,result</em>&nbsp;</td><td>Same as for dwc_prf(). </td></tr>
+  </table>
+</dl>
+
+</div>
+</div><p>
+<a class="anchor" name="2f6fedbb1295662ebf8e65eecb1630c8"></a><!-- doxytag: member="dwc_crypto.h::dwc_wusb_prf_256" ref="2f6fedbb1295662ebf8e65eecb1630c8" args="(u8 *key, u8 *nonce, char *label, u8 *bytes, int len, u8 *result)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static void dwc_wusb_prf_256           </td>
+          <td>(</td>
+          <td class="paramtype">u8 *&nbsp;</td>
+          <td class="paramname"> <em>key</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8 *&nbsp;</td>
+          <td class="paramname"> <em>nonce</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">char *&nbsp;</td>
+          <td class="paramname"> <em>label</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8 *&nbsp;</td>
+          <td class="paramname"> <em>bytes</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>len</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">u8 *&nbsp;</td>
+          <td class="paramname"> <em>result</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [inline, static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+The PRF-256 function described in section 6.5 of the WUSB spec. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>key,nonce,label,bytes,len,result</em>&nbsp;</td><td>Same as for dwc_prf(). </td></tr>
+  </table>
+</dl>
+
+</div>
+</div><p>
+<a class="anchor" name="74ae8ea78ee10c708d7c3e0c12665b0d"></a><!-- doxytag: member="dwc_crypto.h::dwc_wusb_fill_ccm_nonce" ref="74ae8ea78ee10c708d7c3e0c12665b0d" args="(uint16_t haddr, uint16_t daddr, uint8_t *tkid, uint8_t *nonce)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_wusb_fill_ccm_nonce           </td>
+          <td>(</td>
+          <td class="paramtype">uint16_t&nbsp;</td>
+          <td class="paramname"> <em>haddr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint16_t&nbsp;</td>
+          <td class="paramname"> <em>daddr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>tkid</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>nonce</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Fills in CCM Nonce per the WUSB spec. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"><tt>[in]</tt>&nbsp;</td><td valign="top"><em>haddr</em>&nbsp;</td><td>Host address. </td></tr>
+    <tr><td valign="top"><tt>[in]</tt>&nbsp;</td><td valign="top"><em>daddr</em>&nbsp;</td><td>Device address. </td></tr>
+    <tr><td valign="top"><tt>[in]</tt>&nbsp;</td><td valign="top"><em>tkid</em>&nbsp;</td><td>Session Key(PTK) identifier. </td></tr>
+    <tr><td valign="top"><tt>[out]</tt>&nbsp;</td><td valign="top"><em>nonce</em>&nbsp;</td><td>Pointer to where the CCM Nonce output is to be written. </td></tr>
+  </table>
+</dl>
+
+</div>
+</div><p>
+<a class="anchor" name="79af51f4e6140e5a251041879b40ad03"></a><!-- doxytag: member="dwc_crypto.h::dwc_wusb_gen_nonce" ref="79af51f4e6140e5a251041879b40ad03" args="(uint16_t addr, uint8_t *nonce)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_wusb_gen_nonce           </td>
+          <td>(</td>
+          <td class="paramtype">uint16_t&nbsp;</td>
+          <td class="paramname"> <em>addr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>nonce</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Generates a 16-byte cryptographic-grade random number for the Host/Device Nonce. 
+<p>
+
+</div>
+</div><p>
+<a class="anchor" name="18f5b99bd27d2397550fbd340d39600a"></a><!-- doxytag: member="dwc_crypto.h::dwc_wusb_gen_key" ref="18f5b99bd27d2397550fbd340d39600a" args="(uint8_t *ccm_nonce, uint8_t *mk, uint8_t *hnonce, uint8_t *dnonce, uint8_t *kck, uint8_t *ptk)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_wusb_gen_key           </td>
+          <td>(</td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>ccm_nonce</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>mk</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>hnonce</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>dnonce</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>kck</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>ptk</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Generates the Session Key (PTK) and Key Confirmation Key (KCK) per the WUSB spec. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"><tt>[in]</tt>&nbsp;</td><td valign="top"><em>ccm_nonce</em>&nbsp;</td><td>Pointer to CCM Nonce. </td></tr>
+    <tr><td valign="top"><tt>[in]</tt>&nbsp;</td><td valign="top"><em>mk</em>&nbsp;</td><td>Master Key to derive the session from </td></tr>
+    <tr><td valign="top"><tt>[in]</tt>&nbsp;</td><td valign="top"><em>hnonce</em>&nbsp;</td><td>Pointer to Host Nonce. </td></tr>
+    <tr><td valign="top"><tt>[in]</tt>&nbsp;</td><td valign="top"><em>dnonce</em>&nbsp;</td><td>Pointer to Device Nonce. </td></tr>
+    <tr><td valign="top"><tt>[out]</tt>&nbsp;</td><td valign="top"><em>kck</em>&nbsp;</td><td>Pointer to where the KCK output is to be written. </td></tr>
+    <tr><td valign="top"><tt>[out]</tt>&nbsp;</td><td valign="top"><em>ptk</em>&nbsp;</td><td>Pointer to where the PTK output is to be written. </td></tr>
+  </table>
+</dl>
+
+</div>
+</div><p>
+<a class="anchor" name="ab0a16ae4126032ca99e1fbcaaa7c248"></a><!-- doxytag: member="dwc_crypto.h::dwc_wusb_gen_mic" ref="ab0a16ae4126032ca99e1fbcaaa7c248" args="(uint8_t *ccm_nonce, uint8_t *kck, uint8_t *data, uint8_t *mic)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_wusb_gen_mic           </td>
+          <td>(</td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>ccm_nonce</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>kck</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>data</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>mic</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Generates the Message Integrity Code over the Handshake data per the WUSB spec. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>ccm_nonce</em>&nbsp;</td><td>Pointer to CCM Nonce. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>kck</em>&nbsp;</td><td>Pointer to Key Confirmation Key. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>data</em>&nbsp;</td><td>Pointer to Handshake data to be checked. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>mic</em>&nbsp;</td><td>Pointer to where the MIC output is to be written. </td></tr>
+  </table>
+</dl>
+
+</div>
+</div><p>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:50 2009 for Synopsys DWC Portability and Common Library for UWB by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_common_port/doc/html/dwc__dh_8h.html b/drivers/usb/host/dwc_common_port/doc/html/dwc__dh_8h.html
new file mode 100644
index 000000000000..ce0ca7215e63
--- /dev/null
+++ b/drivers/usb/host/dwc_common_port/doc/html/dwc__dh_8h.html
@@ -0,0 +1,166 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Synopsys DWC Portability and Common Library for UWB: dwc_dh.h File Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="dirs.html"><span>Directories</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="nav">
+<a class="el" href="dir_c13d72e45af28cdc461a5f284d3d36fc.html">dwc_common_port</a></div>
+<h1>dwc_dh.h File Reference</h1><hr><a name="_details"></a><h2>Detailed Description</h2>
+This file defines the common functions on device and host for performing numeric association as defined in the WUSB spec. 
+<p>
+They are only to be used internally by the DWC UWB modules. 
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Functions</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="0d63fc8a3091cbd0425403e010837b9d"></a><!-- doxytag: member="dwc_dh.h::dwc_dh_sha256" ref="0d63fc8a3091cbd0425403e010837b9d" args="(uint8_t *message, uint32_t len, uint8_t *out)" -->
+int&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_dh_sha256</b> (uint8_t *message, uint32_t len, uint8_t *out)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c13681aa7efa5bb9e3887516053236e5"></a><!-- doxytag: member="dwc_dh.h::dwc_dh_hmac_sha256" ref="c13681aa7efa5bb9e3887516053236e5" args="(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t *out)" -->
+int&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_dh_hmac_sha256</b> (uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t *out)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="09444cd061da594d0ca93e0e39fc35f9"></a><!-- doxytag: member="dwc_dh.h::dwc_dh_modpow" ref="09444cd061da594d0ca93e0e39fc35f9" args="(void *num, uint32_t num_len, void *exp, uint32_t exp_len, void *mod, uint32_t mod_len, void *out)" -->
+int&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_dh_modpow</b> (void *num, uint32_t num_len, void *exp, uint32_t exp_len, void *mod, uint32_t mod_len, void *out)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__dh_8h.html#15463b3a65cead222814d0d5cce294cf">dwc_dh_pk</a> (uint8_t nd, uint8_t *exp, uint8_t *pkd, uint8_t *hash)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Computes PKD or PKH, and SHA-256(PKd || Nd).  <a href="#15463b3a65cead222814d0d5cce294cf"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__dh_8h.html#bfd81fd7b9a75f027d2bbcdc97e77e83">dwc_dh_derive_keys</a> (uint8_t nd, uint8_t *pkh, uint8_t *pkd, uint8_t *exp, int is_host, char *dd, uint8_t *ck, uint8_t *kdk)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Computes the DHKEY, and VD.  <a href="#bfd81fd7b9a75f027d2bbcdc97e77e83"></a><br></td></tr>
+</table>
+<hr><h2>Function Documentation</h2>
+<a class="anchor" name="15463b3a65cead222814d0d5cce294cf"></a><!-- doxytag: member="dwc_dh.h::dwc_dh_pk" ref="15463b3a65cead222814d0d5cce294cf" args="(uint8_t nd, uint8_t *exp, uint8_t *pkd, uint8_t *hash)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_dh_pk           </td>
+          <td>(</td>
+          <td class="paramtype">uint8_t&nbsp;</td>
+          <td class="paramname"> <em>nd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>exp</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>pkd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>hash</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Computes PKD or PKH, and SHA-256(PKd || Nd). 
+<p>
+PK = g^exp mod p.<p>
+Input: Nd = Number of digits on the device.<p>
+Output: exp = A 32-byte buffer to be filled with a randomly generated number. used as either A or B. pk = A 384-byte buffer to be filled with the PKH or PKD. hash = A 32-byte buffer to be filled with SHA-256(PK || ND). 
+</div>
+</div><p>
+<a class="anchor" name="bfd81fd7b9a75f027d2bbcdc97e77e83"></a><!-- doxytag: member="dwc_dh.h::dwc_dh_derive_keys" ref="bfd81fd7b9a75f027d2bbcdc97e77e83" args="(uint8_t nd, uint8_t *pkh, uint8_t *pkd, uint8_t *exp, int is_host, char *dd, uint8_t *ck, uint8_t *kdk)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_dh_derive_keys           </td>
+          <td>(</td>
+          <td class="paramtype">uint8_t&nbsp;</td>
+          <td class="paramname"> <em>nd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>pkh</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>pkd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>exp</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>is_host</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">char *&nbsp;</td>
+          <td class="paramname"> <em>dd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>ck</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>kdk</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Computes the DHKEY, and VD. 
+<p>
+If called from host, then it will comput DHKEY=PKD^exp % p. If called from device, then it will comput DHKEY=PKH^exp % p.<p>
+Input: pkd = The PKD value. pkh = The PKH value. exp = The A value (if device) or B value (if host) generated in dwc_wudev_dh_pk. is_host = Set to non zero if a WUSB host is calling this function.<p>
+Output:<p>
+dd = A pointer to an buffer to be set to the displayed digits string to be shown to the user. This buffer should be at 5 bytes long to hold 4 digits plus a null termination character. This buffer can be used directly for display. ck = A 16-byte buffer to be filled with the CK. kdk = A 32-byte buffer to be filled with the KDK. 
+</div>
+</div><p>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:50 2009 for Synopsys DWC Portability and Common Library for UWB by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_common_port/doc/html/dwc__list_8h.html b/drivers/usb/host/dwc_common_port/doc/html/dwc__list_8h.html
new file mode 100644
index 000000000000..04d7db6148a5
--- /dev/null
+++ b/drivers/usb/host/dwc_common_port/doc/html/dwc__list_8h.html
@@ -0,0 +1,1844 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Synopsys DWC Portability and Common Library for UWB: dwc_list.h File Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="dirs.html"><span>Directories</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="nav">
+<a class="el" href="dir_c13d72e45af28cdc461a5f284d3d36fc.html">dwc_common_port</a></div>
+<h1>dwc_list.h File Reference</h1><hr><a name="_details"></a><h2>Detailed Description</h2>
+This file defines linked list operations. 
+<p>
+It is derived from BSD with only the MACRO names being prefixed with DWC_. This is because a few of these names conflict with those on Linux. For documentation on use, see the inline comments in the source code. The original license for this source code applies and is preserved in the <a class="el" href="dwc__list_8h.html">dwc_list.h</a> source file. 
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Structures</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_list_link</b></td></tr>
+
+<tr><td colspan="2"><br><h2>Defines</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_LIST_INIT</b>(link)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="4cdcfefc7de29318313290019af6ca7b"></a><!-- doxytag: member="dwc_list.h::DWC_LIST_FIRST" ref="4cdcfefc7de29318313290019af6ca7b" args="(link)" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_LIST_FIRST</b>(link)&nbsp;&nbsp;&nbsp;((link)-&gt;next)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="2a5f10fab6256b33875476ded0bd7a99"></a><!-- doxytag: member="dwc_list.h::DWC_LIST_LAST" ref="2a5f10fab6256b33875476ded0bd7a99" args="(link)" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_LIST_LAST</b>(link)&nbsp;&nbsp;&nbsp;((link)-&gt;prev)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c889eb7e4f68ede76be8b991e6945816"></a><!-- doxytag: member="dwc_list.h::DWC_LIST_END" ref="c889eb7e4f68ede76be8b991e6945816" args="(link)" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_LIST_END</b>(link)&nbsp;&nbsp;&nbsp;(link)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e50ff1549637fb8f5e3d335c0f99b5da"></a><!-- doxytag: member="dwc_list.h::DWC_LIST_NEXT" ref="e50ff1549637fb8f5e3d335c0f99b5da" args="(link)" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_LIST_NEXT</b>(link)&nbsp;&nbsp;&nbsp;((link)-&gt;next)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="536ae6e57dad24349f1132dd119bd37c"></a><!-- doxytag: member="dwc_list.h::DWC_LIST_PREV" ref="536ae6e57dad24349f1132dd119bd37c" args="(link)" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_LIST_PREV</b>(link)&nbsp;&nbsp;&nbsp;((link)-&gt;prev)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3494c85995a74096dd253445ee42ac00"></a><!-- doxytag: member="dwc_list.h::DWC_LIST_EMPTY" ref="3494c85995a74096dd253445ee42ac00" args="(link)" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_LIST_EMPTY</b>(link)&nbsp;&nbsp;&nbsp;(DWC_LIST_FIRST(link) == DWC_LIST_END(link))</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_LIST_ENTRY</b>(link, type, field)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_LIST_INSERT_HEAD</b>(list, link)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_LIST_INSERT_TAIL</b>(list, link)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_LIST_REMOVE</b>(link)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_LIST_REMOVE_INIT</b>(link)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_LIST_MOVE_HEAD</b>(list, link)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_LIST_MOVE_TAIL</b>(list, link)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_LIST_FOREACH</b>(var, list)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_LIST_FOREACH_SAFE</b>(var, var2, list)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_LIST_FOREACH_REVERSE</b>(var, list)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_SLIST_HEAD</b>(name, type)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="72c1f56f4e8b689778b58660e0e79498"></a><!-- doxytag: member="dwc_list.h::DWC_SLIST_HEAD_INITIALIZER" ref="72c1f56f4e8b689778b58660e0e79498" args="(head)" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_SLIST_HEAD_INITIALIZER</b>(head)&nbsp;&nbsp;&nbsp;{ NULL }</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_SLIST_ENTRY</b>(type)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="1d55b83af01517fb209d0ea476d12262"></a><!-- doxytag: member="dwc_list.h::DWC_SLIST_FIRST" ref="1d55b83af01517fb209d0ea476d12262" args="(head)" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_SLIST_FIRST</b>(head)&nbsp;&nbsp;&nbsp;((head)-&gt;slh_first)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="99792b29e4c3fe61b873092b60e896cb"></a><!-- doxytag: member="dwc_list.h::DWC_SLIST_END" ref="99792b29e4c3fe61b873092b60e896cb" args="(head)" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_SLIST_END</b>(head)&nbsp;&nbsp;&nbsp;NULL</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b964b7b99b8c6d15f255a3dec20c9f60"></a><!-- doxytag: member="dwc_list.h::DWC_SLIST_EMPTY" ref="b964b7b99b8c6d15f255a3dec20c9f60" args="(head)" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_SLIST_EMPTY</b>(head)&nbsp;&nbsp;&nbsp;(SLIST_FIRST(head) == SLIST_END(head))</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c321b58e86c6ffc04a35088a312aa034"></a><!-- doxytag: member="dwc_list.h::DWC_SLIST_NEXT" ref="c321b58e86c6ffc04a35088a312aa034" args="(elm, field)" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_SLIST_NEXT</b>(elm, field)&nbsp;&nbsp;&nbsp;((elm)-&gt;field.sle_next)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_SLIST_FOREACH</b>(var, head, field)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_SLIST_FOREACH_PREVPTR</b>(var, varp, head, field)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_SLIST_INIT</b>(head)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_SLIST_INSERT_AFTER</b>(slistelm, elm, field)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_SLIST_INSERT_HEAD</b>(head, elm, field)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_SLIST_REMOVE_NEXT</b>(head, elm, field)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_SLIST_REMOVE_HEAD</b>(head, field)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_SLIST_REMOVE</b>(head, elm, type, field)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_SIMPLEQ_HEAD</b>(name, type)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e4c1ef38ad27fe7b4eec0e3689455860"></a><!-- doxytag: member="dwc_list.h::DWC_SIMPLEQ_HEAD_INITIALIZER" ref="e4c1ef38ad27fe7b4eec0e3689455860" args="(head)" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_SIMPLEQ_HEAD_INITIALIZER</b>(head)&nbsp;&nbsp;&nbsp;{ NULL, &amp;(head).sqh_first }</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_SIMPLEQ_ENTRY</b>(type)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="9f9874c3d870593e9b1d47f037a9f1a7"></a><!-- doxytag: member="dwc_list.h::DWC_SIMPLEQ_FIRST" ref="9f9874c3d870593e9b1d47f037a9f1a7" args="(head)" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_SIMPLEQ_FIRST</b>(head)&nbsp;&nbsp;&nbsp;((head)-&gt;sqh_first)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="216a17924b42b8235dcbaa0e6c5a2251"></a><!-- doxytag: member="dwc_list.h::DWC_SIMPLEQ_END" ref="216a17924b42b8235dcbaa0e6c5a2251" args="(head)" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_SIMPLEQ_END</b>(head)&nbsp;&nbsp;&nbsp;NULL</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="071978c5d8c9f02c819ef4f5a1d6d46d"></a><!-- doxytag: member="dwc_list.h::DWC_SIMPLEQ_EMPTY" ref="071978c5d8c9f02c819ef4f5a1d6d46d" args="(head)" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_SIMPLEQ_EMPTY</b>(head)&nbsp;&nbsp;&nbsp;(SIMPLEQ_FIRST(head) == SIMPLEQ_END(head))</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e56d106bde83ab6bb4a94537185cfdc3"></a><!-- doxytag: member="dwc_list.h::DWC_SIMPLEQ_NEXT" ref="e56d106bde83ab6bb4a94537185cfdc3" args="(elm, field)" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_SIMPLEQ_NEXT</b>(elm, field)&nbsp;&nbsp;&nbsp;((elm)-&gt;field.sqe_next)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_SIMPLEQ_FOREACH</b>(var, head, field)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_SIMPLEQ_INIT</b>(head)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_SIMPLEQ_INSERT_HEAD</b>(head, elm, field)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_SIMPLEQ_INSERT_TAIL</b>(head, elm, field)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_SIMPLEQ_INSERT_AFTER</b>(head, listelm, elm, field)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_SIMPLEQ_REMOVE_HEAD</b>(head, field)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_TAILQ_HEAD</b>(name, type)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="8e1888294218a34ca8444a3c89c1f045"></a><!-- doxytag: member="dwc_list.h::DWC_TAILQ_HEAD_INITIALIZER" ref="8e1888294218a34ca8444a3c89c1f045" args="(head)" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_TAILQ_HEAD_INITIALIZER</b>(head)&nbsp;&nbsp;&nbsp;{ NULL, &amp;(head).tqh_first }</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_TAILQ_ENTRY</b>(type)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="360e9accc553eb17ea8fdbc3226e6465"></a><!-- doxytag: member="dwc_list.h::DWC_TAILQ_FIRST" ref="360e9accc553eb17ea8fdbc3226e6465" args="(head)" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_TAILQ_FIRST</b>(head)&nbsp;&nbsp;&nbsp;((head)-&gt;tqh_first)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="5e72cbbdbfc11af2f258185c83e1af2e"></a><!-- doxytag: member="dwc_list.h::DWC_TAILQ_END" ref="5e72cbbdbfc11af2f258185c83e1af2e" args="(head)" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_TAILQ_END</b>(head)&nbsp;&nbsp;&nbsp;NULL</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c65e5d1410ae0ec012ad0d7de887c6ac"></a><!-- doxytag: member="dwc_list.h::DWC_TAILQ_NEXT" ref="c65e5d1410ae0ec012ad0d7de887c6ac" args="(elm, field)" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_TAILQ_NEXT</b>(elm, field)&nbsp;&nbsp;&nbsp;((elm)-&gt;field.tqe_next)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="be0eb28425b7e4abea3a5455a1e7fbac"></a><!-- doxytag: member="dwc_list.h::DWC_TAILQ_LAST" ref="be0eb28425b7e4abea3a5455a1e7fbac" args="(head, headname)" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_TAILQ_LAST</b>(head, headname)&nbsp;&nbsp;&nbsp;(*(((struct headname *)((head)-&gt;tqh_last))-&gt;tqh_last))</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="2de511f539f72687dd4c08526792ddd2"></a><!-- doxytag: member="dwc_list.h::DWC_TAILQ_PREV" ref="2de511f539f72687dd4c08526792ddd2" args="(elm, headname, field)" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_TAILQ_PREV</b>(elm, headname, field)&nbsp;&nbsp;&nbsp;(*(((struct headname *)((elm)-&gt;field.tqe_prev))-&gt;tqh_last))</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c2308f87d1720570cefe819a4aa0fb27"></a><!-- doxytag: member="dwc_list.h::DWC_TAILQ_EMPTY" ref="c2308f87d1720570cefe819a4aa0fb27" args="(head)" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_TAILQ_EMPTY</b>(head)&nbsp;&nbsp;&nbsp;(TAILQ_FIRST(head) == TAILQ_END(head))</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_TAILQ_FOREACH</b>(var, head, field)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_TAILQ_FOREACH_REVERSE</b>(var, head, headname, field)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_TAILQ_INIT</b>(head)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_TAILQ_INSERT_HEAD</b>(head, elm, field)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_TAILQ_INSERT_TAIL</b>(head, elm, field)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_TAILQ_INSERT_AFTER</b>(head, listelm, elm, field)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_TAILQ_INSERT_BEFORE</b>(listelm, elm, field)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_TAILQ_REMOVE</b>(head, elm, field)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_TAILQ_REPLACE</b>(head, elm, elm2, field)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_CIRCLEQ_HEAD</b>(name, type)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="0b3cea67afa93866b6162cb6e1f8c307"></a><!-- doxytag: member="dwc_list.h::DWC_CIRCLEQ_HEAD_INITIALIZER" ref="0b3cea67afa93866b6162cb6e1f8c307" args="(head)" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_CIRCLEQ_HEAD_INITIALIZER</b>(head)&nbsp;&nbsp;&nbsp;{ DWC_CIRCLEQ_END(&amp;head), DWC_CIRCLEQ_END(&amp;head) }</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_CIRCLEQ_ENTRY</b>(type)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="850a78adcaebdc05180649c7371765d4"></a><!-- doxytag: member="dwc_list.h::DWC_CIRCLEQ_FIRST" ref="850a78adcaebdc05180649c7371765d4" args="(head)" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_CIRCLEQ_FIRST</b>(head)&nbsp;&nbsp;&nbsp;((head)-&gt;cqh_first)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="90d4d450ae18ea704342163a06f3adf9"></a><!-- doxytag: member="dwc_list.h::DWC_CIRCLEQ_LAST" ref="90d4d450ae18ea704342163a06f3adf9" args="(head)" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_CIRCLEQ_LAST</b>(head)&nbsp;&nbsp;&nbsp;((head)-&gt;cqh_last)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="68ddfcc146a979e502e2c6ee08f4424a"></a><!-- doxytag: member="dwc_list.h::DWC_CIRCLEQ_END" ref="68ddfcc146a979e502e2c6ee08f4424a" args="(head)" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_CIRCLEQ_END</b>(head)&nbsp;&nbsp;&nbsp;((void *)(head))</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="a07ffdd5be4e6d32a7e470fb1cd08876"></a><!-- doxytag: member="dwc_list.h::DWC_CIRCLEQ_NEXT" ref="a07ffdd5be4e6d32a7e470fb1cd08876" args="(elm, field)" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_CIRCLEQ_NEXT</b>(elm, field)&nbsp;&nbsp;&nbsp;((elm)-&gt;field.cqe_next)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="78933371fd11e9c7bf00e4a1e1849e19"></a><!-- doxytag: member="dwc_list.h::DWC_CIRCLEQ_PREV" ref="78933371fd11e9c7bf00e4a1e1849e19" args="(elm, field)" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_CIRCLEQ_PREV</b>(elm, field)&nbsp;&nbsp;&nbsp;((elm)-&gt;field.cqe_prev)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="84e1dba431f779a022f56a8f2c72860d"></a><!-- doxytag: member="dwc_list.h::DWC_CIRCLEQ_EMPTY" ref="84e1dba431f779a022f56a8f2c72860d" args="(head)" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_CIRCLEQ_EMPTY</b>(head)&nbsp;&nbsp;&nbsp;(DWC_CIRCLEQ_FIRST(head) == DWC_CIRCLEQ_END(head))</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="5c153fca69ae9f70dc2268124b07aac4"></a><!-- doxytag: member="dwc_list.h::DWC_CIRCLEQ_EMPTY_ENTRY" ref="5c153fca69ae9f70dc2268124b07aac4" args="(elm, field)" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_CIRCLEQ_EMPTY_ENTRY</b>(elm, field)&nbsp;&nbsp;&nbsp;(((elm)-&gt;field.cqe_next == NULL) &amp;&amp; ((elm)-&gt;field.cqe_prev == NULL))</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_CIRCLEQ_FOREACH</b>(var, head, field)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_CIRCLEQ_FOREACH_SAFE</b>(var, var2, head, field)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_CIRCLEQ_FOREACH_REVERSE</b>(var, head, field)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_CIRCLEQ_INIT</b>(head)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_CIRCLEQ_INIT_ENTRY</b>(elm, field)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_CIRCLEQ_INSERT_AFTER</b>(head, listelm, elm, field)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_CIRCLEQ_INSERT_BEFORE</b>(head, listelm, elm, field)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_CIRCLEQ_INSERT_HEAD</b>(head, elm, field)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_CIRCLEQ_INSERT_TAIL</b>(head, elm, field)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_CIRCLEQ_REMOVE</b>(head, elm, field)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_CIRCLEQ_REMOVE_INIT</b>(head, elm, field)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_CIRCLEQ_REPLACE</b>(head, elm, elm2, field)</td></tr>
+
+<tr><td colspan="2"><br><h2>Typedefs</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b64250e0a637e58d5ebceada33ed3a57"></a><!-- doxytag: member="dwc_list.h::dwc_list_link_t" ref="b64250e0a637e58d5ebceada33ed3a57" args="" -->
+typedef dwc_list_link&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_list_link_t</b></td></tr>
+
+</table>
+<hr><h2>Define Documentation</h2>
+<a class="anchor" name="db96608dd5b25335667a98fec31c4136"></a><!-- doxytag: member="dwc_list.h::DWC_LIST_INIT" ref="db96608dd5b25335667a98fec31c4136" args="(link)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_LIST_INIT          </td>
+          <td>(</td>
+          <td class="paramtype">link&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keywordflow">do</span>{             \
+        (link)-&gt;next = (link);          \
+        (link)-&gt;prev = (link);          \
+} <span class="keywordflow">while</span>(0)
+</pre></div>
+</div>
+</div><p>
+<a class="anchor" name="eaa9ed2497b20c84d407bd9ded54d199"></a><!-- doxytag: member="dwc_list.h::DWC_LIST_ENTRY" ref="eaa9ed2497b20c84d407bd9ded54d199" args="(link, type, field)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_LIST_ENTRY          </td>
+          <td>(</td>
+          <td class="paramtype">link,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">type,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">field&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment">(type *)                \
+        ((uint8_t *)(link) - (size_t)(&amp;((type *)0)-&gt;field))
+</pre></div>
+</div>
+</div><p>
+<a class="anchor" name="d788413772e1456edd6cc420eb05aedb"></a><!-- doxytag: member="dwc_list.h::DWC_LIST_INSERT_HEAD" ref="d788413772e1456edd6cc420eb05aedb" args="(list, link)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_LIST_INSERT_HEAD          </td>
+          <td>(</td>
+          <td class="paramtype">list,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">link&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keywordflow">do</span> {                    \
+        (link)-&gt;next = (list)-&gt;next;                            \
+        (link)-&gt;prev = (list);                                  \
+        (list)-&gt;next-&gt;prev = link;                              \
+        (list)-&gt;next = link;                                    \
+} <span class="keywordflow">while</span>(0)
+</pre></div>
+</div>
+</div><p>
+<a class="anchor" name="3d3f93cb4280d9c49753c21c963b68a1"></a><!-- doxytag: member="dwc_list.h::DWC_LIST_INSERT_TAIL" ref="3d3f93cb4280d9c49753c21c963b68a1" args="(list, link)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_LIST_INSERT_TAIL          </td>
+          <td>(</td>
+          <td class="paramtype">list,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">link&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keywordflow">do</span> {                    \
+        (link)-&gt;next = list;                                    \
+        (link)-&gt;prev = (list)-&gt;prev;                            \
+        (list)-&gt;prev-&gt;next = link;                              \
+        (list)-&gt;prev = link;                                    \
+} <span class="keywordflow">while</span>(0)
+</pre></div>
+</div>
+</div><p>
+<a class="anchor" name="01ca12c3d49c0676f5465c70ffecf6e7"></a><!-- doxytag: member="dwc_list.h::DWC_LIST_REMOVE" ref="01ca12c3d49c0676f5465c70ffecf6e7" args="(link)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_LIST_REMOVE          </td>
+          <td>(</td>
+          <td class="paramtype">link&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keywordflow">do</span> {                            \
+        (link)-&gt;next-&gt;prev = (link)-&gt;prev;                      \
+        (link)-&gt;prev-&gt;next = (link)-&gt;next;                      \
+} <span class="keywordflow">while</span>(0)
+</pre></div>
+</div>
+</div><p>
+<a class="anchor" name="5773771dbac23301d7dbdeae32966036"></a><!-- doxytag: member="dwc_list.h::DWC_LIST_REMOVE_INIT" ref="5773771dbac23301d7dbdeae32966036" args="(link)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_LIST_REMOVE_INIT          </td>
+          <td>(</td>
+          <td class="paramtype">link&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keywordflow">do</span> {                            \
+        DWC_LIST_REMOVE(link);                                  \
+        DWC_LIST_INIT(link);                                    \
+} <span class="keywordflow">while</span>(0)
+</pre></div>
+</div>
+</div><p>
+<a class="anchor" name="5ddc1665823d28ffc465e1e6a6f142bd"></a><!-- doxytag: member="dwc_list.h::DWC_LIST_MOVE_HEAD" ref="5ddc1665823d28ffc465e1e6a6f142bd" args="(list, link)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_LIST_MOVE_HEAD          </td>
+          <td>(</td>
+          <td class="paramtype">list,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">link&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keywordflow">do</span> {                    \
+        DWC_LIST_REMOVE(link);                                  \
+        DWC_LIST_INSERT_HEAD(list, link);                       \
+} <span class="keywordflow">while</span>(0)
+</pre></div>
+</div>
+</div><p>
+<a class="anchor" name="221c4633cac8693a367a40e796df998c"></a><!-- doxytag: member="dwc_list.h::DWC_LIST_MOVE_TAIL" ref="221c4633cac8693a367a40e796df998c" args="(list, link)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_LIST_MOVE_TAIL          </td>
+          <td>(</td>
+          <td class="paramtype">list,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">link&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keywordflow">do</span> {                    \
+        DWC_LIST_REMOVE(link);                                  \
+        DWC_LIST_INSERT_TAIL(list, link);                       \
+} <span class="keywordflow">while</span>(0)
+</pre></div>
+</div>
+</div><p>
+<a class="anchor" name="284a932bf39968d2253e753b35381ec3"></a><!-- doxytag: member="dwc_list.h::DWC_LIST_FOREACH" ref="284a932bf39968d2253e753b35381ec3" args="(var, list)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_LIST_FOREACH          </td>
+          <td>(</td>
+          <td class="paramtype">var,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">list&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keywordflow">for</span>((var) = DWC_LIST_FIRST(list);                       \
+            (var) != DWC_LIST_END(list);                        \
+            (var) = DWC_LIST_NEXT(var))
+</pre></div>
+</div>
+</div><p>
+<a class="anchor" name="c9a6aad49e9c4e1bd110bffa2fd3f68a"></a><!-- doxytag: member="dwc_list.h::DWC_LIST_FOREACH_SAFE" ref="c9a6aad49e9c4e1bd110bffa2fd3f68a" args="(var, var2, list)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_LIST_FOREACH_SAFE          </td>
+          <td>(</td>
+          <td class="paramtype">var,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">var2,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">list&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keywordflow">for</span>((var) = DWC_LIST_FIRST(list), var2 = DWC_LIST_NEXT(var);    \
+            (var) != DWC_LIST_END(list);                        \
+            (var) = (var2), var2 = DWC_LIST_NEXT(var2))
+</pre></div>
+</div>
+</div><p>
+<a class="anchor" name="9dd8a4c0e2301213022e349505851150"></a><!-- doxytag: member="dwc_list.h::DWC_LIST_FOREACH_REVERSE" ref="9dd8a4c0e2301213022e349505851150" args="(var, list)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_LIST_FOREACH_REVERSE          </td>
+          <td>(</td>
+          <td class="paramtype">var,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">list&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keywordflow">for</span>((var) = DWC_LIST_LAST(list);                        \
+            (var) != DWC_LIST_END(list);                        \
+            (var) = DWC_LIST_PREV(var))
+</pre></div>
+</div>
+</div><p>
+<a class="anchor" name="b748aa81595d3bbf04cdb574c4796ced"></a><!-- doxytag: member="dwc_list.h::DWC_SLIST_HEAD" ref="b748aa81595d3bbf04cdb574c4796ced" args="(name, type)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_SLIST_HEAD          </td>
+          <td>(</td>
+          <td class="paramtype">name,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">type&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keyword">struct </span>name {                                                           \
+        <span class="keyword">struct </span>type *slh_first; <span class="comment">/* first element */</span>                     \
+}
+</pre></div>
+</div>
+</div><p>
+<a class="anchor" name="59862106cbc5005788612600a407a8aa"></a><!-- doxytag: member="dwc_list.h::DWC_SLIST_ENTRY" ref="59862106cbc5005788612600a407a8aa" args="(type)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_SLIST_ENTRY          </td>
+          <td>(</td>
+          <td class="paramtype">type&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keyword">struct </span>{                                                                \
+        <span class="keyword">struct </span>type *sle_next;  <span class="comment">/* next element */</span>                      \
+}
+</pre></div>
+</div>
+</div><p>
+<a class="anchor" name="658b0528cb95bdefdab94c153914550f"></a><!-- doxytag: member="dwc_list.h::DWC_SLIST_FOREACH" ref="658b0528cb95bdefdab94c153914550f" args="(var, head, field)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_SLIST_FOREACH          </td>
+          <td>(</td>
+          <td class="paramtype">var,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">head,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">field&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keywordflow">for</span>((var) = SLIST_FIRST(head);                                  \
+            (var) != SLIST_END(head);                                   \
+            (var) = SLIST_NEXT(var, field))
+</pre></div>
+</div>
+</div><p>
+<a class="anchor" name="bb68200c2f1e749f78dafd961618658f"></a><!-- doxytag: member="dwc_list.h::DWC_SLIST_FOREACH_PREVPTR" ref="bb68200c2f1e749f78dafd961618658f" args="(var, varp, head, field)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_SLIST_FOREACH_PREVPTR          </td>
+          <td>(</td>
+          <td class="paramtype">var,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">varp,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">head,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">field&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keywordflow">for</span> ((varp) = &amp;SLIST_FIRST((head));                             \
+            ((var) = *(varp)) != SLIST_END(head);                       \
+            (varp) = &amp;SLIST_NEXT((var), field))
+</pre></div>
+</div>
+</div><p>
+<a class="anchor" name="6c658e009fe41c60b7478b29a3710421"></a><!-- doxytag: member="dwc_list.h::DWC_SLIST_INIT" ref="6c658e009fe41c60b7478b29a3710421" args="(head)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_SLIST_INIT          </td>
+          <td>(</td>
+          <td class="paramtype">head&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment">{                                               \
+        SLIST_FIRST(head) = SLIST_END(head);                            \
+}
+</pre></div>
+</div>
+</div><p>
+<a class="anchor" name="a99f4c2d300a1b1425d8d127f193c9e7"></a><!-- doxytag: member="dwc_list.h::DWC_SLIST_INSERT_AFTER" ref="a99f4c2d300a1b1425d8d127f193c9e7" args="(slistelm, elm, field)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_SLIST_INSERT_AFTER          </td>
+          <td>(</td>
+          <td class="paramtype">slistelm,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">elm,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">field&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keywordflow">do</span> {                    \
+        (elm)-&gt;field.sle_next = (slistelm)-&gt;field.sle_next;             \
+        (slistelm)-&gt;field.sle_next = (elm);                             \
+} <span class="keywordflow">while</span> (0)
+</pre></div>
+</div>
+</div><p>
+<a class="anchor" name="6f8e90bc390f102965c13a24b362a5d2"></a><!-- doxytag: member="dwc_list.h::DWC_SLIST_INSERT_HEAD" ref="6f8e90bc390f102965c13a24b362a5d2" args="(head, elm, field)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_SLIST_INSERT_HEAD          </td>
+          <td>(</td>
+          <td class="paramtype">head,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">elm,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">field&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keywordflow">do</span> {                    \
+        (elm)-&gt;field.sle_next = (head)-&gt;slh_first;                      \
+        (head)-&gt;slh_first = (elm);                                      \
+} <span class="keywordflow">while</span> (0)
+</pre></div>
+</div>
+</div><p>
+<a class="anchor" name="b5569581d3fa3571e4febca2e6325ee2"></a><!-- doxytag: member="dwc_list.h::DWC_SLIST_REMOVE_NEXT" ref="b5569581d3fa3571e4febca2e6325ee2" args="(head, elm, field)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_SLIST_REMOVE_NEXT          </td>
+          <td>(</td>
+          <td class="paramtype">head,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">elm,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">field&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keywordflow">do</span> {                    \
+        (elm)-&gt;field.sle_next = (elm)-&gt;field.sle_next-&gt;field.sle_next;  \
+} <span class="keywordflow">while</span> (0)
+</pre></div>
+</div>
+</div><p>
+<a class="anchor" name="d5b2554735060a19b13d8c53ec2eb1af"></a><!-- doxytag: member="dwc_list.h::DWC_SLIST_REMOVE_HEAD" ref="d5b2554735060a19b13d8c53ec2eb1af" args="(head, field)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_SLIST_REMOVE_HEAD          </td>
+          <td>(</td>
+          <td class="paramtype">head,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">field&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keywordflow">do</span> {                            \
+        (head)-&gt;slh_first = (head)-&gt;slh_first-&gt;field.sle_next;          \
+} <span class="keywordflow">while</span> (0)
+</pre></div>
+</div>
+</div><p>
+<a class="anchor" name="c3483cadad0c9036227a212a75e5a0c7"></a><!-- doxytag: member="dwc_list.h::DWC_SLIST_REMOVE" ref="c3483cadad0c9036227a212a75e5a0c7" args="(head, elm, type, field)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_SLIST_REMOVE          </td>
+          <td>(</td>
+          <td class="paramtype">head,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">elm,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">type,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">field&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keywordflow">do</span> {                    \
+        <span class="keywordflow">if</span> ((head)-&gt;slh_first == (elm)) {                               \
+                SLIST_REMOVE_HEAD((head), field);                       \
+        }                                                               \
+        <span class="keywordflow">else</span> {                                                          \
+                <span class="keyword">struct </span>type *curelm = (head)-&gt;slh_first;                \
+                <span class="keywordflow">while</span>( curelm-&gt;field.sle_next != (elm) )                \
+                        curelm = curelm-&gt;field.sle_next;                \
+                curelm-&gt;field.sle_next =                                \
+                    curelm-&gt;field.sle_next-&gt;field.sle_next;             \
+        }                                                               \
+} <span class="keywordflow">while</span> (0)
+</pre></div>
+</div>
+</div><p>
+<a class="anchor" name="51e76ff4f0e7c5b0c86fe5676809fd8f"></a><!-- doxytag: member="dwc_list.h::DWC_SIMPLEQ_HEAD" ref="51e76ff4f0e7c5b0c86fe5676809fd8f" args="(name, type)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_SIMPLEQ_HEAD          </td>
+          <td>(</td>
+          <td class="paramtype">name,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">type&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keyword">struct </span>name {                                                           \
+        <span class="keyword">struct </span>type *sqh_first; <span class="comment">/* first element */</span>                     \
+        <span class="keyword">struct </span>type **sqh_last; <span class="comment">/* addr of last next element */</span>         \
+}
+</pre></div>
+</div>
+</div><p>
+<a class="anchor" name="3667d3b4432a9c1901fda50f3f95c09f"></a><!-- doxytag: member="dwc_list.h::DWC_SIMPLEQ_ENTRY" ref="3667d3b4432a9c1901fda50f3f95c09f" args="(type)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_SIMPLEQ_ENTRY          </td>
+          <td>(</td>
+          <td class="paramtype">type&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keyword">struct </span>{                                                                \
+        <span class="keyword">struct </span>type *sqe_next;  <span class="comment">/* next element */</span>                      \
+}
+</pre></div>
+</div>
+</div><p>
+<a class="anchor" name="7b0cfcd38d8f12d65626839ff24dd40b"></a><!-- doxytag: member="dwc_list.h::DWC_SIMPLEQ_FOREACH" ref="7b0cfcd38d8f12d65626839ff24dd40b" args="(var, head, field)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_SIMPLEQ_FOREACH          </td>
+          <td>(</td>
+          <td class="paramtype">var,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">head,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">field&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keywordflow">for</span>((var) = SIMPLEQ_FIRST(head);                                \
+            (var) != SIMPLEQ_END(head);                                 \
+            (var) = SIMPLEQ_NEXT(var, field))
+</pre></div>
+</div>
+</div><p>
+<a class="anchor" name="b8bef89d6c07dfd08f16598edc31e336"></a><!-- doxytag: member="dwc_list.h::DWC_SIMPLEQ_INIT" ref="b8bef89d6c07dfd08f16598edc31e336" args="(head)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_SIMPLEQ_INIT          </td>
+          <td>(</td>
+          <td class="paramtype">head&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keywordflow">do</span> {                                            \
+        (head)-&gt;sqh_first = NULL;                                       \
+        (head)-&gt;sqh_last = &amp;(head)-&gt;sqh_first;                          \
+} <span class="keywordflow">while</span> (0)
+</pre></div>
+</div>
+</div><p>
+<a class="anchor" name="80c5b0bcd82655713de77a3c38bababc"></a><!-- doxytag: member="dwc_list.h::DWC_SIMPLEQ_INSERT_HEAD" ref="80c5b0bcd82655713de77a3c38bababc" args="(head, elm, field)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_SIMPLEQ_INSERT_HEAD          </td>
+          <td>(</td>
+          <td class="paramtype">head,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">elm,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">field&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keywordflow">do</span> {                    \
+        <span class="keywordflow">if</span> (((elm)-&gt;field.sqe_next = (head)-&gt;sqh_first) == NULL)        \
+                (head)-&gt;sqh_last = &amp;(elm)-&gt;field.sqe_next;              \
+        (head)-&gt;sqh_first = (elm);                                      \
+} <span class="keywordflow">while</span> (0)
+</pre></div>
+</div>
+</div><p>
+<a class="anchor" name="0faea880cf1da248b6d5e857605b69f4"></a><!-- doxytag: member="dwc_list.h::DWC_SIMPLEQ_INSERT_TAIL" ref="0faea880cf1da248b6d5e857605b69f4" args="(head, elm, field)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_SIMPLEQ_INSERT_TAIL          </td>
+          <td>(</td>
+          <td class="paramtype">head,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">elm,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">field&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keywordflow">do</span> {                    \
+        (elm)-&gt;field.sqe_next = NULL;                                   \
+        *(head)-&gt;sqh_last = (elm);                                      \
+        (head)-&gt;sqh_last = &amp;(elm)-&gt;field.sqe_next;                      \
+} <span class="keywordflow">while</span> (0)
+</pre></div>
+</div>
+</div><p>
+<a class="anchor" name="bbe73d7cea269997226f937a3a077372"></a><!-- doxytag: member="dwc_list.h::DWC_SIMPLEQ_INSERT_AFTER" ref="bbe73d7cea269997226f937a3a077372" args="(head, listelm, elm, field)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_SIMPLEQ_INSERT_AFTER          </td>
+          <td>(</td>
+          <td class="paramtype">head,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">listelm,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">elm,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">field&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keywordflow">do</span> {            \
+        <span class="keywordflow">if</span> (((elm)-&gt;field.sqe_next = (listelm)-&gt;field.sqe_next) == NULL)\
+                (head)-&gt;sqh_last = &amp;(elm)-&gt;field.sqe_next;              \
+        (listelm)-&gt;field.sqe_next = (elm);                              \
+} <span class="keywordflow">while</span> (0)
+</pre></div>
+</div>
+</div><p>
+<a class="anchor" name="b8efee3c4850841ae94615102a3da7c9"></a><!-- doxytag: member="dwc_list.h::DWC_SIMPLEQ_REMOVE_HEAD" ref="b8efee3c4850841ae94615102a3da7c9" args="(head, field)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_SIMPLEQ_REMOVE_HEAD          </td>
+          <td>(</td>
+          <td class="paramtype">head,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">field&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keywordflow">do</span> {                    \
+        <span class="keywordflow">if</span> (((head)-&gt;sqh_first = (head)-&gt;sqh_first-&gt;field.sqe_next) == NULL) \
+                (head)-&gt;sqh_last = &amp;(head)-&gt;sqh_first;                  \
+} <span class="keywordflow">while</span> (0)
+</pre></div>
+</div>
+</div><p>
+<a class="anchor" name="917ff0e12fcacf531f8c3f05c43ebd88"></a><!-- doxytag: member="dwc_list.h::DWC_TAILQ_HEAD" ref="917ff0e12fcacf531f8c3f05c43ebd88" args="(name, type)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_TAILQ_HEAD          </td>
+          <td>(</td>
+          <td class="paramtype">name,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">type&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keyword">struct </span>name {                                                           \
+        <span class="keyword">struct </span>type *tqh_first; <span class="comment">/* first element */</span>                     \
+        <span class="keyword">struct </span>type **tqh_last; <span class="comment">/* addr of last next element */</span>         \
+}
+</pre></div>
+</div>
+</div><p>
+<a class="anchor" name="afb85d777a2437caf957b375dafd4118"></a><!-- doxytag: member="dwc_list.h::DWC_TAILQ_ENTRY" ref="afb85d777a2437caf957b375dafd4118" args="(type)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_TAILQ_ENTRY          </td>
+          <td>(</td>
+          <td class="paramtype">type&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keyword">struct </span>{                                                                \
+        <span class="keyword">struct </span>type *tqe_next;  <span class="comment">/* next element */</span>                      \
+        <span class="keyword">struct </span>type **tqe_prev; <span class="comment">/* address of previous next element */</span>  \
+}
+</pre></div>
+</div>
+</div><p>
+<a class="anchor" name="355d80909d6ec45980714d2e254d5a20"></a><!-- doxytag: member="dwc_list.h::DWC_TAILQ_FOREACH" ref="355d80909d6ec45980714d2e254d5a20" args="(var, head, field)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_TAILQ_FOREACH          </td>
+          <td>(</td>
+          <td class="paramtype">var,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">head,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">field&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keywordflow">for</span>((var) = TAILQ_FIRST(head);                                  \
+            (var) != TAILQ_END(head);                                   \
+            (var) = TAILQ_NEXT(var, field))
+</pre></div>
+</div>
+</div><p>
+<a class="anchor" name="2876a408796101321e6acfda6e87ed63"></a><!-- doxytag: member="dwc_list.h::DWC_TAILQ_FOREACH_REVERSE" ref="2876a408796101321e6acfda6e87ed63" args="(var, head, headname, field)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_TAILQ_FOREACH_REVERSE          </td>
+          <td>(</td>
+          <td class="paramtype">var,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">head,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">headname,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">field&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keywordflow">for</span>((var) = TAILQ_LAST(head, headname);                         \
+            (var) != TAILQ_END(head);                                   \
+            (var) = TAILQ_PREV(var, headname, field))
+</pre></div>
+</div>
+</div><p>
+<a class="anchor" name="550c4e9404ee61c07b0e5d739bcd183d"></a><!-- doxytag: member="dwc_list.h::DWC_TAILQ_INIT" ref="550c4e9404ee61c07b0e5d739bcd183d" args="(head)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_TAILQ_INIT          </td>
+          <td>(</td>
+          <td class="paramtype">head&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keywordflow">do</span> {                                            \
+        (head)-&gt;tqh_first = NULL;                                       \
+        (head)-&gt;tqh_last = &amp;(head)-&gt;tqh_first;                          \
+} <span class="keywordflow">while</span> (0)
+</pre></div>
+</div>
+</div><p>
+<a class="anchor" name="aa196b1b7ce962838f008abfb547aeb9"></a><!-- doxytag: member="dwc_list.h::DWC_TAILQ_INSERT_HEAD" ref="aa196b1b7ce962838f008abfb547aeb9" args="(head, elm, field)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_TAILQ_INSERT_HEAD          </td>
+          <td>(</td>
+          <td class="paramtype">head,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">elm,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">field&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keywordflow">do</span> {                    \
+        <span class="keywordflow">if</span> (((elm)-&gt;field.tqe_next = (head)-&gt;tqh_first) != NULL)        \
+                (head)-&gt;tqh_first-&gt;field.tqe_prev =                     \
+                    &amp;(elm)-&gt;field.tqe_next;                             \
+        <span class="keywordflow">else</span>                                                            \
+                (head)-&gt;tqh_last = &amp;(elm)-&gt;field.tqe_next;              \
+        (head)-&gt;tqh_first = (elm);                                      \
+        (elm)-&gt;field.tqe_prev = &amp;(head)-&gt;tqh_first;                     \
+} <span class="keywordflow">while</span> (0)
+</pre></div>
+</div>
+</div><p>
+<a class="anchor" name="5b884053909316017f1ba5c33e001152"></a><!-- doxytag: member="dwc_list.h::DWC_TAILQ_INSERT_TAIL" ref="5b884053909316017f1ba5c33e001152" args="(head, elm, field)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_TAILQ_INSERT_TAIL          </td>
+          <td>(</td>
+          <td class="paramtype">head,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">elm,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">field&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keywordflow">do</span> {                    \
+        (elm)-&gt;field.tqe_next = NULL;                                   \
+        (elm)-&gt;field.tqe_prev = (head)-&gt;tqh_last;                       \
+        *(head)-&gt;tqh_last = (elm);                                      \
+        (head)-&gt;tqh_last = &amp;(elm)-&gt;field.tqe_next;                      \
+} <span class="keywordflow">while</span> (0)
+</pre></div>
+</div>
+</div><p>
+<a class="anchor" name="30abc9c6b3e93e630da4cd6d9e41eb68"></a><!-- doxytag: member="dwc_list.h::DWC_TAILQ_INSERT_AFTER" ref="30abc9c6b3e93e630da4cd6d9e41eb68" args="(head, listelm, elm, field)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_TAILQ_INSERT_AFTER          </td>
+          <td>(</td>
+          <td class="paramtype">head,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">listelm,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">elm,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">field&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keywordflow">do</span> {            \
+        <span class="keywordflow">if</span> (((elm)-&gt;field.tqe_next = (listelm)-&gt;field.tqe_next) != NULL)\
+                (elm)-&gt;field.tqe_next-&gt;field.tqe_prev =                 \
+                    &amp;(elm)-&gt;field.tqe_next;                             \
+        <span class="keywordflow">else</span>                                                            \
+                (head)-&gt;tqh_last = &amp;(elm)-&gt;field.tqe_next;              \
+        (listelm)-&gt;field.tqe_next = (elm);                              \
+        (elm)-&gt;field.tqe_prev = &amp;(listelm)-&gt;field.tqe_next;             \
+} <span class="keywordflow">while</span> (0)
+</pre></div>
+</div>
+</div><p>
+<a class="anchor" name="ac728ce80ec874a2e27d96d18ef1e58e"></a><!-- doxytag: member="dwc_list.h::DWC_TAILQ_INSERT_BEFORE" ref="ac728ce80ec874a2e27d96d18ef1e58e" args="(listelm, elm, field)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_TAILQ_INSERT_BEFORE          </td>
+          <td>(</td>
+          <td class="paramtype">listelm,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">elm,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">field&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keywordflow">do</span> {                    \
+        (elm)-&gt;field.tqe_prev = (listelm)-&gt;field.tqe_prev;              \
+        (elm)-&gt;field.tqe_next = (listelm);                              \
+        *(listelm)-&gt;field.tqe_prev = (elm);                             \
+        (listelm)-&gt;field.tqe_prev = &amp;(elm)-&gt;field.tqe_next;             \
+} <span class="keywordflow">while</span> (0)
+</pre></div>
+</div>
+</div><p>
+<a class="anchor" name="fcd881052a95a285808c5794d248cb3c"></a><!-- doxytag: member="dwc_list.h::DWC_TAILQ_REMOVE" ref="fcd881052a95a285808c5794d248cb3c" args="(head, elm, field)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_TAILQ_REMOVE          </td>
+          <td>(</td>
+          <td class="paramtype">head,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">elm,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">field&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keywordflow">do</span> {                            \
+        <span class="keywordflow">if</span> (((elm)-&gt;field.tqe_next) != NULL)                            \
+                (elm)-&gt;field.tqe_next-&gt;field.tqe_prev =                 \
+                    (elm)-&gt;field.tqe_prev;                              \
+        <span class="keywordflow">else</span>                                                            \
+                (head)-&gt;tqh_last = (elm)-&gt;field.tqe_prev;               \
+        *(elm)-&gt;field.tqe_prev = (elm)-&gt;field.tqe_next;                 \
+} <span class="keywordflow">while</span> (0)
+</pre></div>
+</div>
+</div><p>
+<a class="anchor" name="d0ebdf1aafb2d2eb3989b5489064d668"></a><!-- doxytag: member="dwc_list.h::DWC_TAILQ_REPLACE" ref="d0ebdf1aafb2d2eb3989b5489064d668" args="(head, elm, elm2, field)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_TAILQ_REPLACE          </td>
+          <td>(</td>
+          <td class="paramtype">head,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">elm,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">elm2,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">field&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keywordflow">do</span> {                    \
+        <span class="keywordflow">if</span> (((elm2)-&gt;field.tqe_next = (elm)-&gt;field.tqe_next) != NULL)   \
+                (elm2)-&gt;field.tqe_next-&gt;field.tqe_prev =                \
+                    &amp;(elm2)-&gt;field.tqe_next;                            \
+        <span class="keywordflow">else</span>                                                            \
+                (head)-&gt;tqh_last = &amp;(elm2)-&gt;field.tqe_next;             \
+        (elm2)-&gt;field.tqe_prev = (elm)-&gt;field.tqe_prev;                 \
+        *(elm2)-&gt;field.tqe_prev = (elm2);                               \
+} <span class="keywordflow">while</span> (0)
+</pre></div>
+</div>
+</div><p>
+<a class="anchor" name="ce960b542755439455ae487d9446c5f8"></a><!-- doxytag: member="dwc_list.h::DWC_CIRCLEQ_HEAD" ref="ce960b542755439455ae487d9446c5f8" args="(name, type)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_CIRCLEQ_HEAD          </td>
+          <td>(</td>
+          <td class="paramtype">name,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">type&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keyword">struct </span>name {                                                           \
+        <span class="keyword">struct </span>type *cqh_first;         <span class="comment">/* first element */</span>             \
+        <span class="keyword">struct </span>type *cqh_last;          <span class="comment">/* last element */</span>              \
+}
+</pre></div>
+</div>
+</div><p>
+<a class="anchor" name="27139a7ccf1253dcdeb25296838b4a25"></a><!-- doxytag: member="dwc_list.h::DWC_CIRCLEQ_ENTRY" ref="27139a7ccf1253dcdeb25296838b4a25" args="(type)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_CIRCLEQ_ENTRY          </td>
+          <td>(</td>
+          <td class="paramtype">type&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keyword">struct </span>{                                                                \
+        <span class="keyword">struct </span>type *cqe_next;          <span class="comment">/* next element */</span>              \
+        <span class="keyword">struct </span>type *cqe_prev;          <span class="comment">/* previous element */</span>          \
+}
+</pre></div>
+</div>
+</div><p>
+<a class="anchor" name="f39a9f082624f4e4715e56d92eda4291"></a><!-- doxytag: member="dwc_list.h::DWC_CIRCLEQ_FOREACH" ref="f39a9f082624f4e4715e56d92eda4291" args="(var, head, field)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_CIRCLEQ_FOREACH          </td>
+          <td>(</td>
+          <td class="paramtype">var,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">head,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">field&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keywordflow">for</span>((var) = DWC_CIRCLEQ_FIRST(head);                            \
+            (var) != DWC_CIRCLEQ_END(head);                                     \
+            (var) = DWC_CIRCLEQ_NEXT(var, field))
+</pre></div>
+</div>
+</div><p>
+<a class="anchor" name="1992a17d91637ebddf391ab968fee3ba"></a><!-- doxytag: member="dwc_list.h::DWC_CIRCLEQ_FOREACH_SAFE" ref="1992a17d91637ebddf391ab968fee3ba" args="(var, var2, head, field)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_CIRCLEQ_FOREACH_SAFE          </td>
+          <td>(</td>
+          <td class="paramtype">var,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">var2,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">head,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">field&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keywordflow">for</span>((var) = DWC_CIRCLEQ_FIRST(head), var2 = DWC_CIRCLEQ_NEXT(var, field);                               \
+            (var) != DWC_CIRCLEQ_END(head);                                     \
+            (var) = var2, var2 = DWC_CIRCLEQ_NEXT(var, field))
+</pre></div>
+</div>
+</div><p>
+<a class="anchor" name="7e0db90e1c4e9236b591ab80c9ab24fc"></a><!-- doxytag: member="dwc_list.h::DWC_CIRCLEQ_FOREACH_REVERSE" ref="7e0db90e1c4e9236b591ab80c9ab24fc" args="(var, head, field)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_CIRCLEQ_FOREACH_REVERSE          </td>
+          <td>(</td>
+          <td class="paramtype">var,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">head,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">field&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keywordflow">for</span>((var) = DWC_CIRCLEQ_LAST(head);                                     \
+            (var) != DWC_CIRCLEQ_END(head);                                     \
+            (var) = DWC_CIRCLEQ_PREV(var, field))
+</pre></div>
+</div>
+</div><p>
+<a class="anchor" name="4f5ea3951b621688b07b6156000c847e"></a><!-- doxytag: member="dwc_list.h::DWC_CIRCLEQ_INIT" ref="4f5ea3951b621688b07b6156000c847e" args="(head)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_CIRCLEQ_INIT          </td>
+          <td>(</td>
+          <td class="paramtype">head&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keywordflow">do</span> {                                            \
+        (head)-&gt;cqh_first = DWC_CIRCLEQ_END(head);                              \
+        (head)-&gt;cqh_last = DWC_CIRCLEQ_END(head);                               \
+} <span class="keywordflow">while</span> (0)
+</pre></div>
+</div>
+</div><p>
+<a class="anchor" name="7e91f97ed2096c5ef3b4bdd4e9ee5de2"></a><!-- doxytag: member="dwc_list.h::DWC_CIRCLEQ_INIT_ENTRY" ref="7e91f97ed2096c5ef3b4bdd4e9ee5de2" args="(elm, field)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_CIRCLEQ_INIT_ENTRY          </td>
+          <td>(</td>
+          <td class="paramtype">elm,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">field&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keywordflow">do</span> { \
+        (elm)-&gt;field.cqe_next = NULL; \
+        (elm)-&gt;field.cqe_prev = NULL; \
+} <span class="keywordflow">while</span> (0)
+</pre></div>
+</div>
+</div><p>
+<a class="anchor" name="75c74db3aa4917586ac84fa7f0c24f4b"></a><!-- doxytag: member="dwc_list.h::DWC_CIRCLEQ_INSERT_AFTER" ref="75c74db3aa4917586ac84fa7f0c24f4b" args="(head, listelm, elm, field)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_CIRCLEQ_INSERT_AFTER          </td>
+          <td>(</td>
+          <td class="paramtype">head,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">listelm,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">elm,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">field&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keywordflow">do</span> {            \
+        (elm)-&gt;field.cqe_next = (listelm)-&gt;field.cqe_next;              \
+        (elm)-&gt;field.cqe_prev = (listelm);                              \
+        <span class="keywordflow">if</span> ((listelm)-&gt;field.cqe_next == DWC_CIRCLEQ_END(head))         \
+                (head)-&gt;cqh_last = (elm);                               \
+        <span class="keywordflow">else</span>                                                            \
+                (listelm)-&gt;field.cqe_next-&gt;field.cqe_prev = (elm);      \
+        (listelm)-&gt;field.cqe_next = (elm);                              \
+} <span class="keywordflow">while</span> (0)
+</pre></div>
+</div>
+</div><p>
+<a class="anchor" name="1fccf4da7aaf32131fd21b4bf1e0ca19"></a><!-- doxytag: member="dwc_list.h::DWC_CIRCLEQ_INSERT_BEFORE" ref="1fccf4da7aaf32131fd21b4bf1e0ca19" args="(head, listelm, elm, field)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_CIRCLEQ_INSERT_BEFORE          </td>
+          <td>(</td>
+          <td class="paramtype">head,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">listelm,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">elm,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">field&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keywordflow">do</span> {            \
+        (elm)-&gt;field.cqe_next = (listelm);                              \
+        (elm)-&gt;field.cqe_prev = (listelm)-&gt;field.cqe_prev;              \
+        <span class="keywordflow">if</span> ((listelm)-&gt;field.cqe_prev == DWC_CIRCLEQ_END(head))         \
+                (head)-&gt;cqh_first = (elm);                              \
+        <span class="keywordflow">else</span>                                                            \
+                (listelm)-&gt;field.cqe_prev-&gt;field.cqe_next = (elm);      \
+        (listelm)-&gt;field.cqe_prev = (elm);                              \
+} <span class="keywordflow">while</span> (0)
+</pre></div>
+</div>
+</div><p>
+<a class="anchor" name="6b40408cf6a0134fb4e967798721cd03"></a><!-- doxytag: member="dwc_list.h::DWC_CIRCLEQ_INSERT_HEAD" ref="6b40408cf6a0134fb4e967798721cd03" args="(head, elm, field)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_CIRCLEQ_INSERT_HEAD          </td>
+          <td>(</td>
+          <td class="paramtype">head,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">elm,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">field&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keywordflow">do</span> {                    \
+        (elm)-&gt;field.cqe_next = (head)-&gt;cqh_first;                      \
+        (elm)-&gt;field.cqe_prev = DWC_CIRCLEQ_END(head);                  \
+        <span class="keywordflow">if</span> ((head)-&gt;cqh_last == DWC_CIRCLEQ_END(head))                  \
+                (head)-&gt;cqh_last = (elm);                               \
+        <span class="keywordflow">else</span>                                                            \
+                (head)-&gt;cqh_first-&gt;field.cqe_prev = (elm);              \
+        (head)-&gt;cqh_first = (elm);                                      \
+} <span class="keywordflow">while</span> (0)
+</pre></div>
+</div>
+</div><p>
+<a class="anchor" name="b795ec80ba74019de3a8cb96a9456918"></a><!-- doxytag: member="dwc_list.h::DWC_CIRCLEQ_INSERT_TAIL" ref="b795ec80ba74019de3a8cb96a9456918" args="(head, elm, field)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_CIRCLEQ_INSERT_TAIL          </td>
+          <td>(</td>
+          <td class="paramtype">head,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">elm,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">field&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keywordflow">do</span> {                    \
+        (elm)-&gt;field.cqe_next = DWC_CIRCLEQ_END(head);                  \
+        (elm)-&gt;field.cqe_prev = (head)-&gt;cqh_last;                       \
+        <span class="keywordflow">if</span> ((head)-&gt;cqh_first == DWC_CIRCLEQ_END(head))                 \
+                (head)-&gt;cqh_first = (elm);                              \
+        <span class="keywordflow">else</span>                                                            \
+                (head)-&gt;cqh_last-&gt;field.cqe_next = (elm);               \
+        (head)-&gt;cqh_last = (elm);                                       \
+} <span class="keywordflow">while</span> (0)
+</pre></div>
+</div>
+</div><p>
+<a class="anchor" name="22ea9b7079bf8b554d5496c014ac94ce"></a><!-- doxytag: member="dwc_list.h::DWC_CIRCLEQ_REMOVE" ref="22ea9b7079bf8b554d5496c014ac94ce" args="(head, elm, field)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_CIRCLEQ_REMOVE          </td>
+          <td>(</td>
+          <td class="paramtype">head,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">elm,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">field&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keywordflow">do</span> {                            \
+        <span class="keywordflow">if</span> ((elm)-&gt;field.cqe_next == DWC_CIRCLEQ_END(head))                     \
+                (head)-&gt;cqh_last = (elm)-&gt;field.cqe_prev;               \
+        <span class="keywordflow">else</span>                                                            \
+                (elm)-&gt;field.cqe_next-&gt;field.cqe_prev =                 \
+                    (elm)-&gt;field.cqe_prev;                              \
+        <span class="keywordflow">if</span> ((elm)-&gt;field.cqe_prev == DWC_CIRCLEQ_END(head))                     \
+                (head)-&gt;cqh_first = (elm)-&gt;field.cqe_next;              \
+        <span class="keywordflow">else</span>                                                            \
+                (elm)-&gt;field.cqe_prev-&gt;field.cqe_next =                 \
+                    (elm)-&gt;field.cqe_next;                              \
+} <span class="keywordflow">while</span> (0)
+</pre></div>
+</div>
+</div><p>
+<a class="anchor" name="81a83513033d4cc6226ec3c071065e30"></a><!-- doxytag: member="dwc_list.h::DWC_CIRCLEQ_REMOVE_INIT" ref="81a83513033d4cc6226ec3c071065e30" args="(head, elm, field)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_CIRCLEQ_REMOVE_INIT          </td>
+          <td>(</td>
+          <td class="paramtype">head,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">elm,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">field&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keywordflow">do</span> { \
+        DWC_CIRCLEQ_REMOVE(head, elm, field); \
+        DWC_CIRCLEQ_INIT_ENTRY(elm, field); \
+} <span class="keywordflow">while</span> (0)
+</pre></div>
+</div>
+</div><p>
+<a class="anchor" name="496b6f083405a4e69b2ed4f18e995694"></a><!-- doxytag: member="dwc_list.h::DWC_CIRCLEQ_REPLACE" ref="496b6f083405a4e69b2ed4f18e995694" args="(head, elm, elm2, field)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_CIRCLEQ_REPLACE          </td>
+          <td>(</td>
+          <td class="paramtype">head,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">elm,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">elm2,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">field&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keywordflow">do</span> {                    \
+        <span class="keywordflow">if</span> (((elm2)-&gt;field.cqe_next = (elm)-&gt;field.cqe_next) ==         \
+            DWC_CIRCLEQ_END(head))                                              \
+                (head).cqh_last = (elm2);                               \
+        <span class="keywordflow">else</span>                                                            \
+                (elm2)-&gt;field.cqe_next-&gt;field.cqe_prev = (elm2);        \
+        <span class="keywordflow">if</span> (((elm2)-&gt;field.cqe_prev = (elm)-&gt;field.cqe_prev) ==         \
+            DWC_CIRCLEQ_END(head))                                              \
+                (head).cqh_first = (elm2);                              \
+        <span class="keywordflow">else</span>                                                            \
+                (elm2)-&gt;field.cqe_prev-&gt;field.cqe_next = (elm2);        \
+} <span class="keywordflow">while</span> (0)
+</pre></div>
+</div>
+</div><p>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:50 2009 for Synopsys DWC Portability and Common Library for UWB by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_common_port/doc/html/dwc__modpow_8h.html b/drivers/usb/host/dwc_common_port/doc/html/dwc__modpow_8h.html
new file mode 100644
index 000000000000..4f575c9608db
--- /dev/null
+++ b/drivers/usb/host/dwc_common_port/doc/html/dwc__modpow_8h.html
@@ -0,0 +1,48 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Synopsys DWC Portability and Common Library for UWB: dwc_modpow.h File Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="dirs.html"><span>Directories</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="nav">
+<a class="el" href="dir_c13d72e45af28cdc461a5f284d3d36fc.html">dwc_common_port</a></div>
+<h1>dwc_modpow.h File Reference</h1><hr><a name="_details"></a><h2>Detailed Description</h2>
+This file defines the module exponentiation function which is only used internally by the DWC UWB modules for calculation of PKs during numeric association. 
+<p>
+The routine is taken from the PUTTY, an open source terminal emulator. The PUTTY License is preserved in the dwc_modpow.c file. 
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Typedefs</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="206c270801543a205a07452d8f59fa68"></a><!-- doxytag: member="dwc_modpow.h::BignumInt" ref="206c270801543a205a07452d8f59fa68" args="" -->
+typedef uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><b>BignumInt</b></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e0d2180e525dc871ae17541bc041e5b2"></a><!-- doxytag: member="dwc_modpow.h::BignumDblInt" ref="e0d2180e525dc871ae17541bc041e5b2" args="" -->
+typedef uint64_t&nbsp;</td><td class="memItemRight" valign="bottom"><b>BignumDblInt</b></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3e0e0e90276316eb8781609c16748114"></a><!-- doxytag: member="dwc_modpow.h::Bignum" ref="3e0e0e90276316eb8781609c16748114" args="" -->
+typedef BignumInt *&nbsp;</td><td class="memItemRight" valign="bottom"><b>Bignum</b></td></tr>
+
+<tr><td colspan="2"><br><h2>Functions</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="9ac658f8ad9512d10f0e0c049c93a390"></a><!-- doxytag: member="dwc_modpow.h::dwc_modpow" ref="9ac658f8ad9512d10f0e0c049c93a390" args="(Bignum base_in, Bignum exp, Bignum mod)" -->
+Bignum&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_modpow</b> (Bignum base_in, Bignum exp, Bignum mod)</td></tr>
+
+</table>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:50 2009 for Synopsys DWC Portability and Common Library for UWB by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_common_port/doc/html/dwc__notifier_8h.html b/drivers/usb/host/dwc_common_port/doc/html/dwc__notifier_8h.html
new file mode 100644
index 000000000000..f67a0ee022e8
--- /dev/null
+++ b/drivers/usb/host/dwc_common_port/doc/html/dwc__notifier_8h.html
@@ -0,0 +1,306 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Synopsys DWC Portability and Common Library for UWB: dwc_notifier.h File Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="dirs.html"><span>Directories</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="nav">
+<a class="el" href="dir_c13d72e45af28cdc461a5f284d3d36fc.html">dwc_common_port</a></div>
+<h1>dwc_notifier.h File Reference</h1><hr><a name="_details"></a><h2>Detailed Description</h2>
+A simple implementation of the Observer pattern. 
+<p>
+Any "module" can register as an observer or notifier. The notion of "module" is abstract and can mean anything used to identify either an observer or notifier. Usually it will be a pointer to a data structure which contains some state, ie an object.<p>
+Before any notifiers can be added, the global notification manager must be brought up with <a class="el" href="dwc__notifier_8h.html#3c217d779cc8121d911c60e33c36de5c">dwc_alloc_notification_manager()</a>. <a class="el" href="dwc__notifier_8h.html#dc9553444a56bfc595be08592af6dee4">dwc_free_notification_manager()</a> will bring it down and free all resources. These would typically be called upon module load and unload. The notification manager is a single global instance that handles all registered observable modules and observers so this should be done only once.<p>
+A module can be observable by using Notifications to publicize some general information about it's state or operation. It does not care who listens, or even if anyone listens, or what they do with the information. The observable modules do not need to know any information about it's observers or their interface, or their state or data.<p>
+Any module can register to emit Notifications. It should publish a list of notifications that it can emit and their behavior, such as when they will get triggered, and what information will be provided to the observer. Then it should register itself as an observable module. See <a class="el" href="dwc__notifier_8h.html#40c4a4ad1f3466a135f708be3929a548">dwc_register_notifier()</a>.<p>
+Any module can observe any observable, registered module, provided it has a handle to the other module and knows what notifications to observe. See <a class="el" href="dwc__notifier_8h.html#2d1c0018894e606f7b123094fc363ddb">dwc_add_observer()</a>.<p>
+A function of type dwc_notifier_callback_t is called whenever a notification is triggered with one or more observers observing it. This function is called in it's own process so it may sleep or block if needed. It is guaranteed to be called sometime after the notification has occurred and will be called once per each time the notification is triggered. It will NOT be called in the same process context used to trigger the notification.<h2><a class="anchor" name="Limitiations">
+Limitiations</a></h2>
+Keep in mind that Notifications that can be triggered in rapid sucession may schedule too many processes too handle. Be aware of this limitation when designing to use notifications, and only add notifications for appropriate observable information.<p>
+Also Notification callbacks are not synchronous. If you need to synchronize the behavior between module/observer you must use other means. And perhaps that will mean Notifications are not the proper solution. 
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Typedefs</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="1df1148f04d1313a8e78fbe314959343"></a><!-- doxytag: member="dwc_notifier.h::dwc_notifier_t" ref="1df1148f04d1313a8e78fbe314959343" args="" -->
+typedef dwc_notifier&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_notifier_t</b></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef void(*)&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__notifier_8h.html#a8a84ad74a90bea39597283487b9cbfb">dwc_notifier_callback_t</a> (void *object, char *notification, void *observer, void *notification_data, void *user_data)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">The callback function must be of this type.  <a href="#a8a84ad74a90bea39597283487b9cbfb"></a><br></td></tr>
+<tr><td colspan="2"><br><h2>Functions</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__notifier_8h.html#3c217d779cc8121d911c60e33c36de5c">dwc_alloc_notification_manager</a> (void)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Brings up the notification manager.  <a href="#3c217d779cc8121d911c60e33c36de5c"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__notifier_8h.html#dc9553444a56bfc595be08592af6dee4">dwc_free_notification_manager</a> (void)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Brings down the notification manager.  <a href="#dc9553444a56bfc595be08592af6dee4"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">dwc_notifier_t *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__notifier_8h.html#40c4a4ad1f3466a135f708be3929a548">dwc_register_notifier</a> (void *object)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function register an observable module.  <a href="#40c4a4ad1f3466a135f708be3929a548"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__notifier_8h.html#0b607aa63fc2ab69baffad75b9fa37f4">dwc_unregister_notifier</a> (dwc_notifier_t *notifier)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function unregister an observable module.  <a href="#0b607aa63fc2ab69baffad75b9fa37f4"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__notifier_8h.html#2d1c0018894e606f7b123094fc363ddb">dwc_add_observer</a> (void *observer, void *object, char *notification, <a class="el" href="dwc__notifier_8h.html#a8a84ad74a90bea39597283487b9cbfb">dwc_notifier_callback_t</a> callback, void *user_data)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Add a module as an observer to the observable module.  <a href="#2d1c0018894e606f7b123094fc363ddb"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__notifier_8h.html#0bb13b5ac4ae9a31c458b4bb03585c96">dwc_remove_observer</a> (void *observer)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Removes the specified observer from all notifications that it is currently observing.  <a href="#0bb13b5ac4ae9a31c458b4bb03585c96"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__notifier_8h.html#58997c4e097d7c148312b3e0b84915f3">dwc_notify</a> (dwc_notifier_t *notifier, char *notification, void *notification_data)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function triggers a Notification.  <a href="#58997c4e097d7c148312b3e0b84915f3"></a><br></td></tr>
+</table>
+<hr><h2>Typedef Documentation</h2>
+<a class="anchor" name="a8a84ad74a90bea39597283487b9cbfb"></a><!-- doxytag: member="dwc_notifier.h::dwc_notifier_callback_t" ref="a8a84ad74a90bea39597283487b9cbfb" args="(void *object, char *notification, void *observer, void *notification_data, void *user_data)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef void(*) <a class="el" href="dwc__notifier_8h.html#a8a84ad74a90bea39597283487b9cbfb">dwc_notifier_callback_t</a>(void *object, char *notification, void *observer, void *notification_data, void *user_data)          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+The callback function must be of this type. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>object</em>&nbsp;</td><td>This is the object that is being observed. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>notification</em>&nbsp;</td><td>This is the notification that was triggered. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>observer</em>&nbsp;</td><td>This is the observer </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>notification_data</em>&nbsp;</td><td>This is notification-specific data that the notifier has included in this notification. The value of this should be published in the documentation of the observable module with the notifications. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>user_data</em>&nbsp;</td><td>This is any custom data that the observer provided when adding itself as an observer to the notification. </td></tr>
+  </table>
+</dl>
+
+</div>
+</div><p>
+<hr><h2>Function Documentation</h2>
+<a class="anchor" name="3c217d779cc8121d911c60e33c36de5c"></a><!-- doxytag: member="dwc_notifier.h::dwc_alloc_notification_manager" ref="3c217d779cc8121d911c60e33c36de5c" args="(void)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_alloc_notification_manager           </td>
+          <td>(</td>
+          <td class="paramtype">void&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Brings up the notification manager. 
+<p>
+
+</div>
+</div><p>
+<a class="anchor" name="dc9553444a56bfc595be08592af6dee4"></a><!-- doxytag: member="dwc_notifier.h::dwc_free_notification_manager" ref="dc9553444a56bfc595be08592af6dee4" args="(void)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_free_notification_manager           </td>
+          <td>(</td>
+          <td class="paramtype">void&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Brings down the notification manager. 
+<p>
+
+</div>
+</div><p>
+<a class="anchor" name="40c4a4ad1f3466a135f708be3929a548"></a><!-- doxytag: member="dwc_notifier.h::dwc_register_notifier" ref="40c4a4ad1f3466a135f708be3929a548" args="(void *object)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">dwc_notifier_t* dwc_register_notifier           </td>
+          <td>(</td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>object</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function register an observable module. 
+<p>
+A dwc_notifier_t object is returned to the observable module. This is an opaque object that is used by the observable module to trigger notifications. This object should only be accessible to functions that are authorized to trigger notifications for this module. Observers do not need this object. 
+</div>
+</div><p>
+<a class="anchor" name="0b607aa63fc2ab69baffad75b9fa37f4"></a><!-- doxytag: member="dwc_notifier.h::dwc_unregister_notifier" ref="0b607aa63fc2ab69baffad75b9fa37f4" args="(dwc_notifier_t *notifier)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_unregister_notifier           </td>
+          <td>(</td>
+          <td class="paramtype">dwc_notifier_t *&nbsp;</td>
+          <td class="paramname"> <em>notifier</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function unregister an observable module. 
+<p>
+All observers have to be removed prior to unregistration. 
+</div>
+</div><p>
+<a class="anchor" name="2d1c0018894e606f7b123094fc363ddb"></a><!-- doxytag: member="dwc_notifier.h::dwc_add_observer" ref="2d1c0018894e606f7b123094fc363ddb" args="(void *observer, void *object, char *notification, dwc_notifier_callback_t callback, void *user_data)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_add_observer           </td>
+          <td>(</td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>observer</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>object</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">char *&nbsp;</td>
+          <td class="paramname"> <em>notification</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="dwc__notifier_8h.html#a8a84ad74a90bea39597283487b9cbfb">dwc_notifier_callback_t</a>&nbsp;</td>
+          <td class="paramname"> <em>callback</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>user_data</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Add a module as an observer to the observable module. 
+<p>
+The observable module needs to have previously registered with the notification manager.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>observer</em>&nbsp;</td><td>The observer module </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>object</em>&nbsp;</td><td>The module to observe </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>notification</em>&nbsp;</td><td>The notification to observe </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>callback</em>&nbsp;</td><td>The callback function to call </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>user_data</em>&nbsp;</td><td>Any additional user data to pass into the callback function </td></tr>
+  </table>
+</dl>
+
+</div>
+</div><p>
+<a class="anchor" name="0bb13b5ac4ae9a31c458b4bb03585c96"></a><!-- doxytag: member="dwc_notifier.h::dwc_remove_observer" ref="0bb13b5ac4ae9a31c458b4bb03585c96" args="(void *observer)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_remove_observer           </td>
+          <td>(</td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>observer</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Removes the specified observer from all notifications that it is currently observing. 
+<p>
+
+</div>
+</div><p>
+<a class="anchor" name="58997c4e097d7c148312b3e0b84915f3"></a><!-- doxytag: member="dwc_notifier.h::dwc_notify" ref="58997c4e097d7c148312b3e0b84915f3" args="(dwc_notifier_t *notifier, char *notification, void *notification_data)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_notify           </td>
+          <td>(</td>
+          <td class="paramtype">dwc_notifier_t *&nbsp;</td>
+          <td class="paramname"> <em>notifier</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">char *&nbsp;</td>
+          <td class="paramname"> <em>notification</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>notification_data</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function triggers a Notification. 
+<p>
+It should be called by the observable module, or any module or library which the observable module allows to trigger notification on it's behalf. Such as the dwc_cc_t.<p>
+dwc_notify is a non-blocking function. Callbacks are scheduled called in their own process context for each trigger. Callbacks can be blocking. dwc_notify can be called from interrupt context if needed. 
+</div>
+</div><p>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:50 2009 for Synopsys DWC Portability and Common Library for UWB by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_common_port/doc/html/dwc__os_8h.html b/drivers/usb/host/dwc_common_port/doc/html/dwc__os_8h.html
new file mode 100644
index 000000000000..b7e2fb6ad2b1
--- /dev/null
+++ b/drivers/usb/host/dwc_common_port/doc/html/dwc__os_8h.html
@@ -0,0 +1,3090 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Synopsys DWC Portability and Common Library for UWB: dwc_os.h File Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="dirs.html"><span>Directories</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="nav">
+<a class="el" href="dir_c13d72e45af28cdc461a5f284d3d36fc.html">dwc_common_port</a></div>
+<h1>dwc_os.h File Reference</h1><hr><a name="_details"></a><h2>Detailed Description</h2>
+DWC portability library, low level os-wrapper functions. 
+<p>
+
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Primitive Types and Values</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ff77427579a471601a7a1b2f51286be7"></a><!-- doxytag: member="dwc_os.h::YES" ref="ff77427579a471601a7a1b2f51286be7" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>YES</b>&nbsp;&nbsp;&nbsp;1</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="5aa5e1dac3e5e32e103aabe817ed6861"></a><!-- doxytag: member="dwc_os.h::NO" ref="5aa5e1dac3e5e32e103aabe817ed6861" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>NO</b>&nbsp;&nbsp;&nbsp;0</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#e2374f0b1253fc63321e1b253ee61b1d">dwc_bool_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">We define a boolean type for consistency.  <a href="#e2374f0b1253fc63321e1b253ee61b1d"></a><br></td></tr>
+<tr><td colspan="2"><br><h2>Error Codes</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ef72c811ac92f14b32ca1c765611f59e"></a><!-- doxytag: member="dwc_os.h::DWC_E_INVALID" ref="ef72c811ac92f14b32ca1c765611f59e" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_E_INVALID</b>&nbsp;&nbsp;&nbsp;1001</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b2da7b297f5a72643d356c0eafe6e8a1"></a><!-- doxytag: member="dwc_os.h::DWC_E_NO_MEMORY" ref="b2da7b297f5a72643d356c0eafe6e8a1" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_E_NO_MEMORY</b>&nbsp;&nbsp;&nbsp;1002</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="93b33f41d613e389b538e33b53d76bd7"></a><!-- doxytag: member="dwc_os.h::DWC_E_NO_DEVICE" ref="93b33f41d613e389b538e33b53d76bd7" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_E_NO_DEVICE</b>&nbsp;&nbsp;&nbsp;1003</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="9f890fc718c7f391363b52dc3da8cc6d"></a><!-- doxytag: member="dwc_os.h::DWC_E_NOT_SUPPORTED" ref="9f890fc718c7f391363b52dc3da8cc6d" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_E_NOT_SUPPORTED</b>&nbsp;&nbsp;&nbsp;1004</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ebff6e395e16b544a713ae7a7ded391e"></a><!-- doxytag: member="dwc_os.h::DWC_E_TIMEOUT" ref="ebff6e395e16b544a713ae7a7ded391e" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_E_TIMEOUT</b>&nbsp;&nbsp;&nbsp;1005</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="158b0a343d04043b4c74f7634a3c73db"></a><!-- doxytag: member="dwc_os.h::DWC_E_BUSY" ref="158b0a343d04043b4c74f7634a3c73db" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_E_BUSY</b>&nbsp;&nbsp;&nbsp;1006</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f2237d2bd2185d92b124a141dbd45cd3"></a><!-- doxytag: member="dwc_os.h::DWC_E_AGAIN" ref="f2237d2bd2185d92b124a141dbd45cd3" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_E_AGAIN</b>&nbsp;&nbsp;&nbsp;1007</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="67d45c541a8e30f1f07d2ffcaaac27fc"></a><!-- doxytag: member="dwc_os.h::DWC_E_RESTART" ref="67d45c541a8e30f1f07d2ffcaaac27fc" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_E_RESTART</b>&nbsp;&nbsp;&nbsp;1008</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="56b3a11f62e1641600e42f20d60ba8bf"></a><!-- doxytag: member="dwc_os.h::DWC_E_ABORT" ref="56b3a11f62e1641600e42f20d60ba8bf" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_E_ABORT</b>&nbsp;&nbsp;&nbsp;1009</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="d9dd6a557f526077e550632424ee4fdc"></a><!-- doxytag: member="dwc_os.h::DWC_E_SHUTDOWN" ref="d9dd6a557f526077e550632424ee4fdc" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_E_SHUTDOWN</b>&nbsp;&nbsp;&nbsp;1010</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c3e9f401517519729015171b1a7ac19a"></a><!-- doxytag: member="dwc_os.h::DWC_E_NO_DATA" ref="c3e9f401517519729015171b1a7ac19a" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_E_NO_DATA</b>&nbsp;&nbsp;&nbsp;1011</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="4be0828cd5097ac2e9baea81a94e6721"></a><!-- doxytag: member="dwc_os.h::DWC_E_DISCONNECT" ref="4be0828cd5097ac2e9baea81a94e6721" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_E_DISCONNECT</b>&nbsp;&nbsp;&nbsp;2000</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="2c5e3b70282b25f79ddf7c285e8424a0"></a><!-- doxytag: member="dwc_os.h::DWC_E_UNKNOWN" ref="2c5e3b70282b25f79ddf7c285e8424a0" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_E_UNKNOWN</b>&nbsp;&nbsp;&nbsp;3000</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="de2d38dbb8efc7c1de46e3bcfd3f5d36"></a><!-- doxytag: member="dwc_os.h::DWC_E_NO_STREAM_RES" ref="de2d38dbb8efc7c1de46e3bcfd3f5d36" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_E_NO_STREAM_RES</b>&nbsp;&nbsp;&nbsp;4001</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="18b857a1d66e2bb1da024c72b795444a"></a><!-- doxytag: member="dwc_os.h::DWC_E_COMMUNICATION" ref="18b857a1d66e2bb1da024c72b795444a" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_E_COMMUNICATION</b>&nbsp;&nbsp;&nbsp;4002</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="4a5f5a784f4df8da94eee783b38fbf10"></a><!-- doxytag: member="dwc_os.h::DWC_E_OVERFLOW" ref="4a5f5a784f4df8da94eee783b38fbf10" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_E_OVERFLOW</b>&nbsp;&nbsp;&nbsp;4003</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3625d06e2961a58ddcf934efde2a3d17"></a><!-- doxytag: member="dwc_os.h::DWC_E_PROTOCOL" ref="3625d06e2961a58ddcf934efde2a3d17" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_E_PROTOCOL</b>&nbsp;&nbsp;&nbsp;4004</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f1a2b2ea196d6237d219acf09bca5f78"></a><!-- doxytag: member="dwc_os.h::DWC_E_IN_PROGRESS" ref="f1a2b2ea196d6237d219acf09bca5f78" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_E_IN_PROGRESS</b>&nbsp;&nbsp;&nbsp;4005</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="8aa84227305b9035a978a5dfe1562267"></a><!-- doxytag: member="dwc_os.h::DWC_E_PIPE" ref="8aa84227305b9035a978a5dfe1562267" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_E_PIPE</b>&nbsp;&nbsp;&nbsp;4006</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="bf67d78d875db13c1909316e7498b8fa"></a><!-- doxytag: member="dwc_os.h::DWC_E_IO" ref="bf67d78d875db13c1909316e7498b8fa" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_E_IO</b>&nbsp;&nbsp;&nbsp;4007</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="67535914f07e6fd1f96e767a1e16fe7b"></a><!-- doxytag: member="dwc_os.h::DWC_E_NO_SPACE" ref="67535914f07e6fd1f96e767a1e16fe7b" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_E_NO_SPACE</b>&nbsp;&nbsp;&nbsp;4008</td></tr>
+
+<tr><td colspan="2"><br><h2>Tracing/Logging Functions</h2></td></tr>
+<tr><td colspan="2">These function provide the capability to add tracing, debugging, and error messages, as well exceptions as assertions. The WUDEV uses these extensively. These could be logged to the main console, the serial port, an internal buffer, etc. These functions could also be no-op if they are too expensive on your system. By default undefining the DEBUG macro already no-ops some of these functions. <br><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f54e732daa2449830460d43c576754b4"></a><!-- doxytag: member="dwc_os.h::dwc_in_irq" ref="f54e732daa2449830460d43c576754b4" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_in_irq</b>&nbsp;&nbsp;&nbsp;DWC_IN_IRQ</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="31707f4d6e04bd29c9bdc86e128f62e6"></a><!-- doxytag: member="dwc_os.h::dwc_vprintf" ref="31707f4d6e04bd29c9bdc86e128f62e6" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_vprintf</b>&nbsp;&nbsp;&nbsp;DWC_VPRINTF</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="d170470212e81bf555e812a7f49f949e"></a><!-- doxytag: member="dwc_os.h::dwc_vsnprintf" ref="d170470212e81bf555e812a7f49f949e" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_vsnprintf</b>&nbsp;&nbsp;&nbsp;DWC_VSNPRINTF</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7335649071e8fad124c4b97d685331f7"></a><!-- doxytag: member="dwc_os.h::dwc_printf" ref="7335649071e8fad124c4b97d685331f7" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_printf</b>&nbsp;&nbsp;&nbsp;DWC_PRINTF</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="931a546d17453799a8642684022b3f16"></a><!-- doxytag: member="dwc_os.h::dwc_sprintf" ref="931a546d17453799a8642684022b3f16" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_sprintf</b>&nbsp;&nbsp;&nbsp;DWC_SPRINTF</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="36171104ece1d5ea69fac4ac9bba4c64"></a><!-- doxytag: member="dwc_os.h::dwc_snprintf" ref="36171104ece1d5ea69fac4ac9bba4c64" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_snprintf</b>&nbsp;&nbsp;&nbsp;DWC_SNPRINTF</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="a63c6fe3233f3eb4e8f6938f6ac23b8c"></a><!-- doxytag: member="dwc_os.h::dwc_exception" ref="a63c6fe3233f3eb4e8f6938f6ac23b8c" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_exception</b>&nbsp;&nbsp;&nbsp;DWC_EXCEPTION</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#c91431cc824741def21c86e778361e6b">DWC_DEBUG</a>(_format, _args...)&nbsp;&nbsp;&nbsp;__DWC_DEBUG(&quot;DEBUG:%s:%s: &quot; _format &quot;\n&quot;, __func__, dwc_irq(), ## _args)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Prints out a Debug message.  <a href="#c91431cc824741def21c86e778361e6b"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="5c8ef6e417fcae65d8455c11ceacdf8a"></a><!-- doxytag: member="dwc_os.h::dwc_debug" ref="5c8ef6e417fcae65d8455c11ceacdf8a" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_debug</b>&nbsp;&nbsp;&nbsp;DWC_DEBUG</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#f30c815ec9d3d710a4c0ccb993a84d86">DWC_INFO</a>(_format, _args...)&nbsp;&nbsp;&nbsp;DWC_PRINTF(&quot;INFO:%s: &quot; _format &quot;\n&quot;, dwc_irq(), ## _args)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Prints out an informative message.  <a href="#f30c815ec9d3d710a4c0ccb993a84d86"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7765b7acbfda5bb31981565ca31502d4"></a><!-- doxytag: member="dwc_os.h::dwc_info" ref="7765b7acbfda5bb31981565ca31502d4" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_info</b>&nbsp;&nbsp;&nbsp;DWC_INFO</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#d475a8dc748be355af32ad01de0c257a">DWC_WARN</a>(_format, _args...)&nbsp;&nbsp;&nbsp;__DWC_WARN(&quot;WARN:%s:%s:%d: &quot; _format &quot;\n&quot;, dwc_irq(), __func__, __LINE__, ## _args)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Prints out a warning message.  <a href="#d475a8dc748be355af32ad01de0c257a"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="57834f1b177a9e64ec26b70ef508af8b"></a><!-- doxytag: member="dwc_os.h::dwc_warn" ref="57834f1b177a9e64ec26b70ef508af8b" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_warn</b>&nbsp;&nbsp;&nbsp;DWC_WARN</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#7f87f33fab81a2ad602599e16db8b067">DWC_ERROR</a>(_format, _args...)&nbsp;&nbsp;&nbsp;__DWC_ERROR(&quot;ERROR:%s:%s:%d: &quot; _format &quot;\n&quot;, dwc_irq(), __func__, __LINE__, ## _args)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Prints out an error message.  <a href="#7f87f33fab81a2ad602599e16db8b067"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="a487304b0ae058e13c78857e40951de7"></a><!-- doxytag: member="dwc_os.h::dwc_error" ref="a487304b0ae058e13c78857e40951de7" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_error</b>&nbsp;&nbsp;&nbsp;DWC_ERROR</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="8c46d8d8c8990573a204626c52c734bf"></a><!-- doxytag: member="dwc_os.h::DWC_PROTO_ERROR" ref="8c46d8d8c8990573a204626c52c734bf" args="(_format, _args...)" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_PROTO_ERROR</b>(_format, _args...)&nbsp;&nbsp;&nbsp;__DWC_WARN(&quot;ERROR:%s:%s:%d: &quot; _format &quot;\n&quot;, dwc_irq(), __func__, __LINE__, ## _args)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="bb80aed3c75139c3b2655a7bcd911b1c"></a><!-- doxytag: member="dwc_os.h::dwc_proto_error" ref="bb80aed3c75139c3b2655a7bcd911b1c" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_proto_error</b>&nbsp;&nbsp;&nbsp;DWC_PROTO_ERROR</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#1dd30b105001754e01596cfb0a01e572">DWC_ASSERT</a>(_expr, _format, _args...)&nbsp;&nbsp;&nbsp;if (!(_expr)) { DWC_EXCEPTION(&quot;%s:%s:%d: &quot; _format &quot;\n&quot;, dwc_irq(), __FILE__, __LINE__, ## _args); }</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Prints out a exception error message if the _expr expression fails.  <a href="#1dd30b105001754e01596cfb0a01e572"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="d0fe3e4d9eb8ad9b253540ed9817386d"></a><!-- doxytag: member="dwc_os.h::dwc_assert" ref="d0fe3e4d9eb8ad9b253540ed9817386d" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_assert</b>&nbsp;&nbsp;&nbsp;DWC_ASSERT</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="el" href="dwc__os_8h.html#e2374f0b1253fc63321e1b253ee61b1d">dwc_bool_t</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#830b5c18c8b32f36ef5948df9b310959">DWC_IN_IRQ</a> (void)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Returns non-zero if in interrupt context.  <a href="#830b5c18c8b32f36ef5948df9b310959"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static char *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#9df340bcf2f004c69b9d917724e22955">dwc_irq</a> (void)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Returns "IRQ" if DWC_IN_IRQ is true.  <a href="#9df340bcf2f004c69b9d917724e22955"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#dedf4a24c1af865c0a73b685a807383d">DWC_VPRINTF</a> (char *format, va_list args)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">A vprintf() clone.  <a href="#dedf4a24c1af865c0a73b685a807383d"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#8fdc0abfec4f97c78b59cece02718f35">DWC_VSNPRINTF</a> (char *str, int size, char *format, va_list args)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">A vsnprintf() clone.  <a href="#8fdc0abfec4f97c78b59cece02718f35"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#ff25ba1e8c8760561e74df4faa45a3c7">DWC_PRINTF</a> (char *format,...)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">printf() clone.  <a href="#ff25ba1e8c8760561e74df4faa45a3c7"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#6bc72ec00a8247404cda1ad5fa88fb86">DWC_SPRINTF</a> (char *string, char *format,...)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">sprintf() clone.  <a href="#6bc72ec00a8247404cda1ad5fa88fb86"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#f9d4dbc0799ef36f89e78eea0a60b563">DWC_SNPRINTF</a> (char *string, int size, char *format,...)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">snprintf() clone.  <a href="#f9d4dbc0799ef36f89e78eea0a60b563"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#da29736470afbdc41a0f7c7e8d9a2f0d">__DWC_WARN</a> (char *format,...)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Prints a WARNING message.  <a href="#da29736470afbdc41a0f7c7e8d9a2f0d"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#54dcd8d8647879b6803585f98bcc3c71">__DWC_ERROR</a> (char *format,...)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Prints an error message.  <a href="#54dcd8d8647879b6803585f98bcc3c71"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#96ee4cab04e3ec11f47beedaea6fe752">DWC_EXCEPTION</a> (char *format,...)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Prints an exception error message and takes some user-defined action such as print out a backtrace or trigger a breakpoint.  <a href="#96ee4cab04e3ec11f47beedaea6fe752"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#24c83900d9653d50bf5874fb3b787e07">__DWC_DEBUG</a> (char *format,...)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Prints out a debug message.  <a href="#24c83900d9653d50bf5874fb3b787e07"></a><br></td></tr>
+<tr><td colspan="2"><br><h2>Byter Ordering</h2></td></tr>
+<tr><td colspan="2">The following functions are for conversions between processor's byte ordering and specific ordering you want. <br><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7c68e40dbf92cb7c02c14d6f3b8dce2a"></a><!-- doxytag: member="dwc_os.h::dwc_cpu_to_le32" ref="7c68e40dbf92cb7c02c14d6f3b8dce2a" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_cpu_to_le32</b>&nbsp;&nbsp;&nbsp;DWC_CPU_TO_LE32</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="6b84005f933736a0e7a9e95c60f1a2e6"></a><!-- doxytag: member="dwc_os.h::dwc_cpu_to_be32" ref="6b84005f933736a0e7a9e95c60f1a2e6" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_cpu_to_be32</b>&nbsp;&nbsp;&nbsp;DWC_CPU_TO_BE32</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="2c212225a4da2ae63601649049ebfc2b"></a><!-- doxytag: member="dwc_os.h::dwc_le32_to_cpu" ref="2c212225a4da2ae63601649049ebfc2b" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_le32_to_cpu</b>&nbsp;&nbsp;&nbsp;DWC_LE32_TO_CPU</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3a06f3d5c2b5f5db73587385f70087fd"></a><!-- doxytag: member="dwc_os.h::dwc_be32_to_cpu" ref="3a06f3d5c2b5f5db73587385f70087fd" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_be32_to_cpu</b>&nbsp;&nbsp;&nbsp;DWC_BE32_TO_CPU</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="30870d4d5db6e2a1e48d286fdb0ef2f0"></a><!-- doxytag: member="dwc_os.h::dwc_cpu_to_le16" ref="30870d4d5db6e2a1e48d286fdb0ef2f0" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_cpu_to_le16</b>&nbsp;&nbsp;&nbsp;DWC_CPU_TO_LE16</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f52249626f9fb77ee04eb5bf73bc2d87"></a><!-- doxytag: member="dwc_os.h::dwc_cpu_to_be16" ref="f52249626f9fb77ee04eb5bf73bc2d87" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_cpu_to_be16</b>&nbsp;&nbsp;&nbsp;DWC_CPU_TO_BE16</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="a034c92a31a7c1d624bde88f9b4466af"></a><!-- doxytag: member="dwc_os.h::dwc_le16_to_cpu" ref="a034c92a31a7c1d624bde88f9b4466af" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_le16_to_cpu</b>&nbsp;&nbsp;&nbsp;DWC_LE16_TO_CPU</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="05162660a972f1d6a80ce7805a9d5e08"></a><!-- doxytag: member="dwc_os.h::dwc_be16_to_cpu" ref="05162660a972f1d6a80ce7805a9d5e08" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_be16_to_cpu</b>&nbsp;&nbsp;&nbsp;DWC_BE16_TO_CPU</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#e3f5dbab365dc4e3aab74d95fe26c654">DWC_CPU_TO_LE32</a> (void *p)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Converts 32 bit data in CPU byte ordering to little endian.  <a href="#e3f5dbab365dc4e3aab74d95fe26c654"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#5504b62058f8a69ffa9dfd28712a9ea0">DWC_CPU_TO_BE32</a> (void *p)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Converts 32 bit data in CPU byte orderint to big endian.  <a href="#5504b62058f8a69ffa9dfd28712a9ea0"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#7e6e45719874b966f5eead1079dce589">DWC_LE32_TO_CPU</a> (void *p)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Converts 32 bit little endian data to CPU byte ordering.  <a href="#7e6e45719874b966f5eead1079dce589"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#ac5cda361023e4b10ff059bce576d2b4">DWC_BE32_TO_CPU</a> (void *p)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Converts 32 bit big endian data to CPU byte ordering.  <a href="#ac5cda361023e4b10ff059bce576d2b4"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint16_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#0ee58f208f5b2ec70aed9a0133d33479">DWC_CPU_TO_LE16</a> (void *p)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Converts 16 bit data in CPU byte ordering to little endian.  <a href="#0ee58f208f5b2ec70aed9a0133d33479"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint16_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#4b7cb22cfd1ec8f87965c9e2de43838f">DWC_CPU_TO_BE16</a> (void *p)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Converts 16 bit data in CPU byte orderint to big endian.  <a href="#4b7cb22cfd1ec8f87965c9e2de43838f"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint16_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#157b0438d386b5529abcc54c886b7ddc">DWC_LE16_TO_CPU</a> (void *p)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Converts 16 bit little endian data to CPU byte ordering.  <a href="#157b0438d386b5529abcc54c886b7ddc"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint16_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#039677525ccd7b262a486a788523a4fa">DWC_BE16_TO_CPU</a> (void *p)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Converts 16 bit bi endian data to CPU byte ordering.  <a href="#039677525ccd7b262a486a788523a4fa"></a><br></td></tr>
+<tr><td colspan="2"><br><h2>Register Read/Write</h2></td></tr>
+<tr><td colspan="2">The following five functions should be implemented to read/write registers of 32-bit and 64-bit sizes. All modules use this to read/write register values. The reg value is a pointer to the register calculated from the void *base variable passed into the driver when it is started. <br><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e26d0e0aa0e414b8ccab1f92008dbb11"></a><!-- doxytag: member="dwc_os.h::dwc_read_reg32" ref="e26d0e0aa0e414b8ccab1f92008dbb11" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_read_reg32</b>&nbsp;&nbsp;&nbsp;DWC_READ_REG32</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="5607ccc0fe44095e9b0d050b9c8f7cc4"></a><!-- doxytag: member="dwc_os.h::dwc_read_reg64" ref="5607ccc0fe44095e9b0d050b9c8f7cc4" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_read_reg64</b>&nbsp;&nbsp;&nbsp;DWC_READ_REG64</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="327728d4e2151a003b901979d1191331"></a><!-- doxytag: member="dwc_os.h::dwc_write_reg32" ref="327728d4e2151a003b901979d1191331" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_write_reg32</b>&nbsp;&nbsp;&nbsp;DWC_WRITE_REG32</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="76a7550130cafd724e82391cfd364126"></a><!-- doxytag: member="dwc_os.h::dwc_write_reg64" ref="76a7550130cafd724e82391cfd364126" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_write_reg64</b>&nbsp;&nbsp;&nbsp;DWC_WRITE_REG64</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3532caad3461f6c10ea9baeb0e623605"></a><!-- doxytag: member="dwc_os.h::dwc_modify_reg32" ref="3532caad3461f6c10ea9baeb0e623605" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_modify_reg32</b>&nbsp;&nbsp;&nbsp;DWC_MODIFY_REG32</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#998a1b27461c926d8c19de202f0e05ca">DWC_READ_REG32</a> (uint32_t volatile *reg)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Reads the content of a 32-bit register.  <a href="#998a1b27461c926d8c19de202f0e05ca"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint64_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#04a809b4ec80265acf393a6d2bff8916">DWC_READ_REG64</a> (uint64_t volatile *reg)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Reads the content of a 64-bit register.  <a href="#04a809b4ec80265acf393a6d2bff8916"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#9166df012531473304420325a61302cf">DWC_WRITE_REG32</a> (uint32_t volatile *reg, uint32_t value)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Writes to a 32-bit register.  <a href="#9166df012531473304420325a61302cf"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#59ef876d933b94b75a659c1614946496">DWC_WRITE_REG64</a> (uint64_t volatile *reg, uint64_t value)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Writes to a 64-bit register.  <a href="#59ef876d933b94b75a659c1614946496"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#a0be0db1cab4dcc65c7d508b15e5d209">DWC_MODIFY_REG32</a> (uint32_t volatile *reg, uint32_t clear_mask, uint32_t set_mask)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Modify bit values in a register.  <a href="#a0be0db1cab4dcc65c7d508b15e5d209"></a><br></td></tr>
+<tr><td colspan="2"><br><h2>Crypto Functions</h2></td></tr>
+<tr><td colspan="2">These are the low-level cryptographic functions used by the driver. <br><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="30ed35a7e94cf498efcee24ec67cdf4f"></a><!-- doxytag: member="dwc_os.h::dwc_aes_cbc" ref="30ed35a7e94cf498efcee24ec67cdf4f" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_aes_cbc</b>&nbsp;&nbsp;&nbsp;DWC_AES_CBC</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="01919ef94bc85db8dfc35aa200fb8862"></a><!-- doxytag: member="dwc_os.h::dwc_random_bytes" ref="01919ef94bc85db8dfc35aa200fb8862" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_random_bytes</b>&nbsp;&nbsp;&nbsp;DWC_RANDOM_BYTES</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ece1dd4462e3225d9f3c938cdcc39808"></a><!-- doxytag: member="dwc_os.h::dwc_sha256" ref="ece1dd4462e3225d9f3c938cdcc39808" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_sha256</b>&nbsp;&nbsp;&nbsp;DWC_SHA256</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="8dab2f2ce31d3f1b7ef560a8a9a3e0ac"></a><!-- doxytag: member="dwc_os.h::dwc_hmac_sha256" ref="8dab2f2ce31d3f1b7ef560a8a9a3e0ac" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_hmac_sha256</b>&nbsp;&nbsp;&nbsp;DWC_HMAC_SHA256</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#d25677e4a3299c7ae65e520015172124">DWC_AES_CBC</a> (uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Perform AES CBC.  <a href="#d25677e4a3299c7ae65e520015172124"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#3e85fc1609d2791628e718c284f3a37f">DWC_RANDOM_BYTES</a> (uint8_t *buffer, uint32_t length)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Fill the provided buffer with random bytes.  <a href="#3e85fc1609d2791628e718c284f3a37f"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#30bc2a37980e41bea58057131229d543">DWC_SHA256</a> (uint8_t *message, uint32_t len, uint8_t *out)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Perform the SHA-256 hash function.  <a href="#30bc2a37980e41bea58057131229d543"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#b312283cc1cec404b8753eb0a3d9d051">DWC_HMAC_SHA256</a> (uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t *out)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Calculated the HMAC-SHA256.  <a href="#b312283cc1cec404b8753eb0a3d9d051"></a><br></td></tr>
+<tr><td colspan="2"><br><h2>Memory Allocation</h2></td></tr>
+<tr><td colspan="2">These function provide access to memory allocation. There are only 2 DMA functions and 3 Regular memory functions that need to be implemented. None of the memory debugging routines need to be implemented. The allocation routines all ZERO the contents of the memory.<p>
+Defining DEBUG_MEMORY turns on memory debugging and statistic gathering. This checks for memory leaks, keeping track of alloc/free pairs. It also keeps track of how much memory the driver is using at any given time. <br><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="90e4d99c3a7cd33b402b0c050c73c6fc"></a><!-- doxytag: member="dwc_os.h::DWC_PAGE_SIZE" ref="90e4d99c3a7cd33b402b0c050c73c6fc" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_PAGE_SIZE</b>&nbsp;&nbsp;&nbsp;4096</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="4ca96cb190e1211c0557d5d619a5555a"></a><!-- doxytag: member="dwc_os.h::DWC_PAGE_OFFSET" ref="4ca96cb190e1211c0557d5d619a5555a" args="(addr)" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_PAGE_OFFSET</b>(addr)&nbsp;&nbsp;&nbsp;(((uint32_t)addr) &amp; 0xfff)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="77fa0bf3aceb22439a7336ec45dbd583"></a><!-- doxytag: member="dwc_os.h::DWC_PAGE_ALIGNED" ref="77fa0bf3aceb22439a7336ec45dbd583" args="(addr)" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_PAGE_ALIGNED</b>(addr)&nbsp;&nbsp;&nbsp;((((uint32_t)addr) &amp; 0xfff) == 0)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b3d23ae4fccd06b3cd87198c0604970b"></a><!-- doxytag: member="dwc_os.h::DWC_INVALID_DMA_ADDR" ref="b3d23ae4fccd06b3cd87198c0604970b" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_INVALID_DMA_ADDR</b>&nbsp;&nbsp;&nbsp;0x0</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7796bbb3f4961276a7d70d9fdac8851c"></a><!-- doxytag: member="dwc_os.h::DWC_ALLOC" ref="7796bbb3f4961276a7d70d9fdac8851c" args="(_size_)" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_ALLOC</b>(_size_)&nbsp;&nbsp;&nbsp;(dwc_alloc_debug(_size_, __func__, __LINE__))</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="a26f6c011b9301057ab987b0307d052a"></a><!-- doxytag: member="dwc_os.h::DWC_ALLOC_ATOMIC" ref="a26f6c011b9301057ab987b0307d052a" args="(_size_)" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_ALLOC_ATOMIC</b>(_size_)&nbsp;&nbsp;&nbsp;(dwc_alloc_atomic_debug(_size_, __func__, __LINE__))</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="511c429e724887b43a86ca9df3310e37"></a><!-- doxytag: member="dwc_os.h::DWC_FREE" ref="511c429e724887b43a86ca9df3310e37" args="(_addr_)" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_FREE</b>(_addr_)&nbsp;&nbsp;&nbsp;(dwc_free_debug(_addr_, __func__, __LINE__))</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="a36afbc96cb70bb442705067b32bc868"></a><!-- doxytag: member="dwc_os.h::DWC_DMA_ALLOC" ref="a36afbc96cb70bb442705067b32bc868" args="(_size_, _dma_)" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_DMA_ALLOC</b>(_size_, _dma_)&nbsp;&nbsp;&nbsp;dwc_dma_alloc_debug(_size_, _dma_, __func__, __LINE__)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="4250592f2f40c700b3a047ccfbd90544"></a><!-- doxytag: member="dwc_os.h::DWC_DMA_FREE" ref="4250592f2f40c700b3a047ccfbd90544" args="(_size_, _virt_, _dma_)" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_DMA_FREE</b>(_size_, _virt_, _dma_)&nbsp;&nbsp;&nbsp;dwc_dma_free_debug(_size_, _virt_, _dma_, __func__, __LINE__)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="539008cd02ad95f749c29cdcbb9ba754"></a><!-- doxytag: member="dwc_os.h::dwc_alloc" ref="539008cd02ad95f749c29cdcbb9ba754" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_alloc</b>&nbsp;&nbsp;&nbsp;DWC_ALLOC</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="79a5b2eb218c23d9440c1f9b7e731f94"></a><!-- doxytag: member="dwc_os.h::dwc_alloc_atomic" ref="79a5b2eb218c23d9440c1f9b7e731f94" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_alloc_atomic</b>&nbsp;&nbsp;&nbsp;DWC_ALLOC_ATOMIC</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f3f99170f156b7e93639cb9a65254555"></a><!-- doxytag: member="dwc_os.h::dwc_free" ref="f3f99170f156b7e93639cb9a65254555" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_free</b>&nbsp;&nbsp;&nbsp;DWC_FREE</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="1c5ebcc6b9607da2e63f744b606326fd"></a><!-- doxytag: member="dwc_os.h::dwc_dma_alloc" ref="1c5ebcc6b9607da2e63f744b606326fd" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_dma_alloc</b>&nbsp;&nbsp;&nbsp;DWC_DMA_ALLOC</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="36d270fefc823b70565ca919b3f82d91"></a><!-- doxytag: member="dwc_os.h::dwc_dma_free" ref="36d270fefc823b70565ca919b3f82d91" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_dma_free</b>&nbsp;&nbsp;&nbsp;DWC_DMA_FREE</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c5ca9967c698940076a70670c7d80006"></a><!-- doxytag: member="dwc_os.h::dwc_dma_t" ref="c5ca9967c698940076a70670c7d80006" args="" -->
+typedef uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_dma_t</b></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#f74ba85fa4f2dcb59886b2f3d4ef709f">__DWC_DMA_ALLOC</a> (uint32_t size, dwc_dma_t *dma_addr)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Allocates a DMA capable buffer and zeroes its contents.  <a href="#f74ba85fa4f2dcb59886b2f3d4ef709f"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#04a8867a0602eccf0d759206d89bde96">__DWC_DMA_FREE</a> (uint32_t size, void *virt_addr, dwc_dma_t dma_addr)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Frees a previosly allocated buffer.  <a href="#04a8867a0602eccf0d759206d89bde96"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#f0da81fbd5a3822ded21f74e650b6f56">__DWC_ALLOC</a> (uint32_t size)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Allocates a block of memory and zeroes its contents.  <a href="#f0da81fbd5a3822ded21f74e650b6f56"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#ce6c64a02c1b62bdd693f827c06803e1">__DWC_ALLOC_ATOMIC</a> (uint32_t size)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Allocates a block of memory and zeroes its contents, in an atomic manner which can be used inside interrupt context.  <a href="#ce6c64a02c1b62bdd693f827c06803e1"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#578dd2d0619aab9c86e31f4828a9afe5">__DWC_FREE</a> (void *addr)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Frees a previously allocated buffer.  <a href="#578dd2d0619aab9c86e31f4828a9afe5"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e5edeb91647b84092ba922ddb882412d"></a><!-- doxytag: member="dwc_os.h::dwc_alloc_debug" ref="e5edeb91647b84092ba922ddb882412d" args="(uint32_t size, char const *func, int line)" -->
+void *&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_alloc_debug</b> (uint32_t size, char const *func, int line)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="d64aaee8796e1add83359fd1d24cff7c"></a><!-- doxytag: member="dwc_os.h::dwc_alloc_atomic_debug" ref="d64aaee8796e1add83359fd1d24cff7c" args="(uint32_t size, char const *func, int line)" -->
+void *&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_alloc_atomic_debug</b> (uint32_t size, char const *func, int line)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="070119931856afabe421cb7698ab23d8"></a><!-- doxytag: member="dwc_os.h::dwc_free_debug" ref="070119931856afabe421cb7698ab23d8" args="(void *addr, char const *func, int line)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_free_debug</b> (void *addr, char const *func, int line)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="d681fce139f1690eec56703b966c8201"></a><!-- doxytag: member="dwc_os.h::dwc_dma_alloc_debug" ref="d681fce139f1690eec56703b966c8201" args="(uint32_t size, dwc_dma_t *dma_addr, char const *func, int line)" -->
+void *&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_dma_alloc_debug</b> (uint32_t size, dwc_dma_t *dma_addr, char const *func, int line)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b9f003b96ece2f49ba822f58e0f20051"></a><!-- doxytag: member="dwc_os.h::dwc_dma_free_debug" ref="b9f003b96ece2f49ba822f58e0f20051" args="(uint32_t size, void *virt_addr, dwc_dma_t dma_addr, char const *func, int line)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_dma_free_debug</b> (uint32_t size, void *virt_addr, dwc_dma_t dma_addr, char const *func, int line)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="963f17eb83a90d837ba30a8cb1d00364"></a><!-- doxytag: member="dwc_os.h::dwc_memory_debug_start" ref="963f17eb83a90d837ba30a8cb1d00364" args="(void)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_memory_debug_start</b> (void)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="bb71a7333405527f98f00cbd8a9994d4"></a><!-- doxytag: member="dwc_os.h::dwc_memory_debug_stop" ref="bb71a7333405527f98f00cbd8a9994d4" args="(void)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_memory_debug_stop</b> (void)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="d400ce9e818a5c1ccb13d1c7649d7230"></a><!-- doxytag: member="dwc_os.h::dwc_memory_debug_report" ref="d400ce9e818a5c1ccb13d1c7649d7230" args="(void)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_memory_debug_report</b> (void)</td></tr>
+
+<tr><td colspan="2"><br><h2>Memory and String Processing</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="95e2c3a03f276d93c7258dc526cf543d"></a><!-- doxytag: member="dwc_os.h::dwc_memset" ref="95e2c3a03f276d93c7258dc526cf543d" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_memset</b>&nbsp;&nbsp;&nbsp;DWC_MEMSET</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f1045360934470228a9c85ddc41240df"></a><!-- doxytag: member="dwc_os.h::dwc_memcpy" ref="f1045360934470228a9c85ddc41240df" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_memcpy</b>&nbsp;&nbsp;&nbsp;DWC_MEMCPY</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="cdc5000f62ab01fdaf7a203c586fddb7"></a><!-- doxytag: member="dwc_os.h::dwc_memmove" ref="cdc5000f62ab01fdaf7a203c586fddb7" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_memmove</b>&nbsp;&nbsp;&nbsp;DWC_MEMMOVE</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="44dacb0cdbbb342d0e533bb6c8efb835"></a><!-- doxytag: member="dwc_os.h::dwc_memcmp" ref="44dacb0cdbbb342d0e533bb6c8efb835" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_memcmp</b>&nbsp;&nbsp;&nbsp;DWC_MEMCMP</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="05f7adc8b459243f27422368171e9beb"></a><!-- doxytag: member="dwc_os.h::dwc_strcmp" ref="05f7adc8b459243f27422368171e9beb" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_strcmp</b>&nbsp;&nbsp;&nbsp;DWC_STRCMP</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="538cd96e04043ab297ae437ba3ac1ef3"></a><!-- doxytag: member="dwc_os.h::dwc_strncmp" ref="538cd96e04043ab297ae437ba3ac1ef3" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_strncmp</b>&nbsp;&nbsp;&nbsp;DWC_STRNCMP</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="eada3d77d2b564ac3a4f88e556d129de"></a><!-- doxytag: member="dwc_os.h::dwc_strlen" ref="eada3d77d2b564ac3a4f88e556d129de" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_strlen</b>&nbsp;&nbsp;&nbsp;DWC_STRLEN</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b08ffa0260f2fe619891d813af7c5c8b"></a><!-- doxytag: member="dwc_os.h::dwc_strcpy" ref="b08ffa0260f2fe619891d813af7c5c8b" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_strcpy</b>&nbsp;&nbsp;&nbsp;DWC_STRCPY</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="cd29926d7fb837d7976ac4ca71587f16"></a><!-- doxytag: member="dwc_os.h::dwc_strdup" ref="cd29926d7fb837d7976ac4ca71587f16" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_strdup</b>&nbsp;&nbsp;&nbsp;DWC_STRDUP</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="a4a7b7a391c98b98e0ba9252f9860a4b"></a><!-- doxytag: member="dwc_os.h::dwc_atoi" ref="a4a7b7a391c98b98e0ba9252f9860a4b" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_atoi</b>&nbsp;&nbsp;&nbsp;DWC_ATOI</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="355723acf10b682156f4ee9abf9c0753"></a><!-- doxytag: member="dwc_os.h::dwc_atoui" ref="355723acf10b682156f4ee9abf9c0753" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_atoui</b>&nbsp;&nbsp;&nbsp;DWC_ATOUI</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="81307e67c347c3df73a60191c74aa30b"></a><!-- doxytag: member="dwc_os.h::dwc_utf8_to_utf16le" ref="81307e67c347c3df73a60191c74aa30b" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_utf8_to_utf16le</b>&nbsp;&nbsp;&nbsp;DWC_UTF8_TO_UTF16LE</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#d14e248de8bd334f6065bb9c09305a65">DWC_MEMSET</a> (void *dest, uint8_t byte, uint32_t size)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">memset() clone  <a href="#d14e248de8bd334f6065bb9c09305a65"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#37c1b18d623367a7ca438e4d2a698ed5">DWC_MEMCPY</a> (void *dest, void const *src, uint32_t size)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">memcpy() clone  <a href="#37c1b18d623367a7ca438e4d2a698ed5"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#2bc77081fca508dab31a245d0dd214d9">DWC_MEMMOVE</a> (void *dest, void *src, uint32_t size)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">memmove() clone  <a href="#2bc77081fca508dab31a245d0dd214d9"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#7a80d4bef3bc0f3d6297400b3858b80e">DWC_MEMCMP</a> (void *m1, void *m2, uint32_t size)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">memcmp() clone  <a href="#7a80d4bef3bc0f3d6297400b3858b80e"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#3f175e77ff50e30a9444d377bf16cb07">DWC_STRCMP</a> (void *s1, void *s2)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">strcmp() clone  <a href="#3f175e77ff50e30a9444d377bf16cb07"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#5692e7d364b935378e15a8f6a5b45afb">DWC_STRNCMP</a> (void *s1, void *s2, uint32_t size)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">strncmp() clone  <a href="#5692e7d364b935378e15a8f6a5b45afb"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#4605aef85763dd32580d13a462ad9add">DWC_STRLEN</a> (char const *str)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">strlen() clone, for NULL terminated ASCII strings  <a href="#4605aef85763dd32580d13a462ad9add"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">char *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#8c89eecb8b1b4c4330aac7ecc54f5be4">DWC_STRCPY</a> (char *to, const char *from)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">strcpy() clone, for NULL terminated ASCII strings  <a href="#8c89eecb8b1b4c4330aac7ecc54f5be4"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">char *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#d4b956a8a4bea03a73b1ca2bafe94231">DWC_STRDUP</a> (char const *str)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">strdup() clone.  <a href="#d4b956a8a4bea03a73b1ca2bafe94231"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#d7080682441edd663b576334e307ebfe">DWC_ATOI</a> (char *str, int32_t *value)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">NOT an atoi() clone.  <a href="#d7080682441edd663b576334e307ebfe"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#f6a3d4b637d16e25f1f69cce51d2184e">DWC_ATOUI</a> (char *str, uint32_t *value)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Same as above but for unsigned.  <a href="#f6a3d4b637d16e25f1f69cce51d2184e"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#0e7deede6fcd5a48347fb1714259375b">DWC_UTF8_TO_UTF16LE</a> (uint8_t const *utf8string, uint16_t *utf16string, unsigned len)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This routine returns a UTF16LE unicode encoded string from a UTF8 string.  <a href="#0e7deede6fcd5a48347fb1714259375b"></a><br></td></tr>
+<tr><td colspan="2"><br><h2>Wait queues</h2></td></tr>
+<tr><td colspan="2">Wait queues provide a means of synchronizing between threads or processes. A process can block on a waitq if some condition is not true, waiting for it to become true. When the waitq is triggered all waiting process will get unblocked and the condition will be check again. Waitqs should be triggered every time a condition can potentially change. <br><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="2f85d02a372709e501800f12f6d6ac49"></a><!-- doxytag: member="dwc_os.h::dwc_waitq_alloc" ref="2f85d02a372709e501800f12f6d6ac49" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_waitq_alloc</b>&nbsp;&nbsp;&nbsp;DWC_WAITQ_ALLOC</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="53bc86fb3e8bdcf39951e724bc09639c"></a><!-- doxytag: member="dwc_os.h::dwc_waitq_free" ref="53bc86fb3e8bdcf39951e724bc09639c" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_waitq_free</b>&nbsp;&nbsp;&nbsp;DWC_WAITQ_FREE</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="a58219bc813dc1a9bd26be66fb52fee4"></a><!-- doxytag: member="dwc_os.h::dwc_waitq_wait" ref="a58219bc813dc1a9bd26be66fb52fee4" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_waitq_wait</b>&nbsp;&nbsp;&nbsp;DWC_WAITQ_WAIT;</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="4d2ea8f29762412affff44d36610cd5a"></a><!-- doxytag: member="dwc_os.h::dwc_waitq_wait_timeout" ref="4d2ea8f29762412affff44d36610cd5a" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_waitq_wait_timeout</b>&nbsp;&nbsp;&nbsp;DWC_WAITQ_WAIT_TIMEOUT</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="02dba69e1201e041ff570ef3c68810c3"></a><!-- doxytag: member="dwc_os.h::dwc_waitq_trigger" ref="02dba69e1201e041ff570ef3c68810c3" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_waitq_trigger</b>&nbsp;&nbsp;&nbsp;DWC_WAITQ_TRIGGER</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="26bef7085e7bb37f90f4bc786cce4401"></a><!-- doxytag: member="dwc_os.h::dwc_waitq_abort" ref="26bef7085e7bb37f90f4bc786cce4401" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_waitq_abort</b>&nbsp;&nbsp;&nbsp;DWC_WAITQ_ABORT</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="a34142745c9589ccb6c8a3994bef1d9d"></a><!-- doxytag: member="dwc_os.h::dwc_waitq_t" ref="a34142745c9589ccb6c8a3994bef1d9d" args="" -->
+typedef dwc_waitq&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_waitq_t</b></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef int(*)&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#b361f6bc4eff88c0ddda059569da125f">dwc_waitq_condition_t</a> (void *data)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">The type of waitq condition callback function.  <a href="#b361f6bc4eff88c0ddda059569da125f"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">dwc_waitq_t *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#4c5d74e3fd7f8f32b3129ce47e8d5c0c">DWC_WAITQ_ALLOC</a> (void)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Allocate a waitq.  <a href="#4c5d74e3fd7f8f32b3129ce47e8d5c0c"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#7b731581f7ab4db7ec2e8874bfd200ee">DWC_WAITQ_FREE</a> (dwc_waitq_t *wq)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Free a waitq.  <a href="#7b731581f7ab4db7ec2e8874bfd200ee"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#29bfbfd7ed787ea71828f3902dcaec92">DWC_WAITQ_WAIT</a> (dwc_waitq_t *wq, <a class="el" href="dwc__os_8h.html#b361f6bc4eff88c0ddda059569da125f">dwc_waitq_condition_t</a> condition, void *data)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Check the condition and if it is false, block on the waitq.  <a href="#29bfbfd7ed787ea71828f3902dcaec92"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#56c898b4f49f0e992905e6e4be2034f0">DWC_WAITQ_WAIT_TIMEOUT</a> (dwc_waitq_t *wq, <a class="el" href="dwc__os_8h.html#b361f6bc4eff88c0ddda059569da125f">dwc_waitq_condition_t</a> condition, void *data, int32_t msecs)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Check the condition and if it is false, block on the waitq.  <a href="#56c898b4f49f0e992905e6e4be2034f0"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#7a9ddcd9fc2a6014fee4c8e162ca675a">DWC_WAITQ_TRIGGER</a> (dwc_waitq_t *wq)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Trigger a waitq, unblocking all processes.  <a href="#7a9ddcd9fc2a6014fee4c8e162ca675a"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#e6010b0efd088e31791cc2eece7f4aa6">DWC_WAITQ_ABORT</a> (dwc_waitq_t *wq)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Unblock all processes waiting on the waitq with an ABORTED result.  <a href="#e6010b0efd088e31791cc2eece7f4aa6"></a><br></td></tr>
+<tr><td colspan="2"><br><h2>Threads</h2></td></tr>
+<tr><td colspan="2">A thread must be explicitly stopped. It must check DWC_THREAD_SHOULD_STOP whenever it is woken up, and then return. The DWC_THREAD_STOP function returns the value from the thread. <br><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3602f2ede5e6526bd53fd61d86214f95"></a><!-- doxytag: member="dwc_os.h::dwc_thread_run" ref="3602f2ede5e6526bd53fd61d86214f95" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_thread_run</b>&nbsp;&nbsp;&nbsp;DWC_THREAD_RUN</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e96234f2c87d8e0572dc8bf2dd7c819a"></a><!-- doxytag: member="dwc_os.h::dwc_thread_stop" ref="e96234f2c87d8e0572dc8bf2dd7c819a" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_thread_stop</b>&nbsp;&nbsp;&nbsp;DWC_THREAD_STOP</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b4a7f42c6cc0a65d38b6d946bc4db1d2"></a><!-- doxytag: member="dwc_os.h::dwc_thread_should_stop" ref="b4a7f42c6cc0a65d38b6d946bc4db1d2" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_thread_should_stop</b>&nbsp;&nbsp;&nbsp;DWC_THREAD_SHOULD_STOP</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="bf1eb14ec218f7acdfa8ef7c9f4f8ef5"></a><!-- doxytag: member="dwc_os.h::dwc_thread_t" ref="bf1eb14ec218f7acdfa8ef7c9f4f8ef5" args="" -->
+typedef dwc_thread&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_thread_t</b></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef int(*)&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#d34bdab089ddbc0e479c9fead16ca7ac">dwc_thread_function_t</a> (void *data)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">The thread function.  <a href="#d34bdab089ddbc0e479c9fead16ca7ac"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">dwc_thread_t *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#bd9f02558a1f945a13029eeb3db69665">DWC_THREAD_RUN</a> (<a class="el" href="dwc__os_8h.html#d34bdab089ddbc0e479c9fead16ca7ac">dwc_thread_function_t</a> thread_function, char *name, void *data)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Create a thread and start it running the thread_function.  <a href="#bd9f02558a1f945a13029eeb3db69665"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#b67d33899c4114d53fd6b327054ffdf4">DWC_THREAD_STOP</a> (dwc_thread_t *thread)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Stops a thread.  <a href="#b67d33899c4114d53fd6b327054ffdf4"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="el" href="dwc__os_8h.html#e2374f0b1253fc63321e1b253ee61b1d">dwc_bool_t</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#5e9b5e2258135bbb0612b36e798d9d70">DWC_THREAD_SHOULD_STOP</a> (void)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Signifies to the thread that it must stop.  <a href="#5e9b5e2258135bbb0612b36e798d9d70"></a><br></td></tr>
+<tr><td colspan="2"><br><h2>Work queues</h2></td></tr>
+<tr><td colspan="2">Workqs are used to queue a callback function to be called at some later time, in another thread. <br><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="298e0a8398166a349101e2dfc39a5b57"></a><!-- doxytag: member="dwc_os.h::dwc_workq_alloc" ref="298e0a8398166a349101e2dfc39a5b57" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_workq_alloc</b>&nbsp;&nbsp;&nbsp;DWC_WORKQ_ALLOC</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="fe7718b6389cb33c3ed8a19f2e98352b"></a><!-- doxytag: member="dwc_os.h::dwc_workq_free" ref="fe7718b6389cb33c3ed8a19f2e98352b" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_workq_free</b>&nbsp;&nbsp;&nbsp;DWC_WORKQ_FREE</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="be6a9df860d4c34cb820d203b5f8499b"></a><!-- doxytag: member="dwc_os.h::dwc_workq_schedule" ref="be6a9df860d4c34cb820d203b5f8499b" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_workq_schedule</b>&nbsp;&nbsp;&nbsp;DWC_WORKQ_SCHEDULE</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="8834e2fa2c020fda4fd52a1feffae42a"></a><!-- doxytag: member="dwc_os.h::dwc_workq_schedule_delayed" ref="8834e2fa2c020fda4fd52a1feffae42a" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_workq_schedule_delayed</b>&nbsp;&nbsp;&nbsp;DWC_WORKQ_SCHEDULE_DELAYED</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b95abea1754323e455dc1f4fc4c7a3ca"></a><!-- doxytag: member="dwc_os.h::dwc_workq_pending" ref="b95abea1754323e455dc1f4fc4c7a3ca" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_workq_pending</b>&nbsp;&nbsp;&nbsp;DWC_WORKQ_PENDING</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f97af7f5aeedc3b1774054af4b800c6b"></a><!-- doxytag: member="dwc_os.h::dwc_workq_wait_work_done" ref="f97af7f5aeedc3b1774054af4b800c6b" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_workq_wait_work_done</b>&nbsp;&nbsp;&nbsp;DWC_WORKQ_WAIT_WORK_DONE</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b53323a2d8b11432103c432b58e30acb"></a><!-- doxytag: member="dwc_os.h::dwc_workq_t" ref="b53323a2d8b11432103c432b58e30acb" args="" -->
+typedef dwc_workq&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_workq_t</b></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef void(*)&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#c67973a4ac14764ed66a82103a357c06">dwc_work_callback_t</a> (void *data)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">The type of the callback function to be called.  <a href="#c67973a4ac14764ed66a82103a357c06"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">dwc_workq_t *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#7a1f0611831c9ea4438ba6bdaf4c1e59">DWC_WORKQ_ALLOC</a> (char *name)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Allocate a workq.  <a href="#7a1f0611831c9ea4438ba6bdaf4c1e59"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#680e3852c4fb8e14e63220dab9b714d3">DWC_WORKQ_FREE</a> (dwc_workq_t *workq)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Free a workq.  <a href="#680e3852c4fb8e14e63220dab9b714d3"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#95363f7dc5b0d38e0a3dd5cd120f8b99">DWC_WORKQ_SCHEDULE</a> (dwc_workq_t *workq, <a class="el" href="dwc__os_8h.html#c67973a4ac14764ed66a82103a357c06">dwc_work_callback_t</a> work_cb, void *data, char *format,...)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Schedule a callback on the workq, passing in data.  <a href="#95363f7dc5b0d38e0a3dd5cd120f8b99"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#cf7ea7e0bb106fd0579f006d184e3bac">DWC_WORKQ_SCHEDULE_DELAYED</a> (dwc_workq_t *workq, <a class="el" href="dwc__os_8h.html#c67973a4ac14764ed66a82103a357c06">dwc_work_callback_t</a> work_cb, void *data, uint32_t time, char *format,...)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Schedule a callback on the workq, that will be called until at least given number miliseconds have passed.  <a href="#cf7ea7e0bb106fd0579f006d184e3bac"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#78913f99b2219b3d56b330eb435874a5">DWC_WORKQ_PENDING</a> (dwc_workq_t *workq)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">The number of processes in the workq.  <a href="#78913f99b2219b3d56b330eb435874a5"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#796e99dd77f1370cfcab7170a3319100">DWC_WORKQ_WAIT_WORK_DONE</a> (dwc_workq_t *workq, int timeout)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Blocks until all the work in the workq is complete or timed out.  <a href="#796e99dd77f1370cfcab7170a3319100"></a><br></td></tr>
+<tr><td colspan="2"><br><h2>Tasklets</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="4bac5a4b3444d8386be958e23cbbf9df"></a><!-- doxytag: member="dwc_os.h::dwc_task_alloc" ref="4bac5a4b3444d8386be958e23cbbf9df" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_task_alloc</b>&nbsp;&nbsp;&nbsp;DWC_TASK_ALLOC</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7f9c132269cfc7c8f884d782244aef3a"></a><!-- doxytag: member="dwc_os.h::dwc_task_free" ref="7f9c132269cfc7c8f884d782244aef3a" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_task_free</b>&nbsp;&nbsp;&nbsp;DWC_TASK_FREE</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="cffeb0b3025129c685b322b3c3e31b5b"></a><!-- doxytag: member="dwc_os.h::dwc_task_schedule" ref="cffeb0b3025129c685b322b3c3e31b5b" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_task_schedule</b>&nbsp;&nbsp;&nbsp;DWC_TASK_SCHEDULE</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="d7acd8b06b68817089ea013bd38bc152"></a><!-- doxytag: member="dwc_os.h::dwc_tasklet_t" ref="d7acd8b06b68817089ea013bd38bc152" args="" -->
+typedef dwc_tasklet&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_tasklet_t</b></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="8751d60dbec32061b8e9110f682c8e2b"></a><!-- doxytag: member="dwc_os.h::dwc_tasklet_callback_t" ref="8751d60dbec32061b8e9110f682c8e2b" args="(void *data)" -->
+typedef void(*)&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_tasklet_callback_t</b> (void *data)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="6e55b9093c8461720ace6cce85c0fc8d"></a><!-- doxytag: member="dwc_os.h::DWC_TASK_ALLOC" ref="6e55b9093c8461720ace6cce85c0fc8d" args="(dwc_tasklet_callback_t cb, void *data)" -->
+dwc_tasklet_t *&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_TASK_ALLOC</b> (dwc_tasklet_callback_t cb, void *data)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="6744f603216b19547a91097d0a0ca21c"></a><!-- doxytag: member="dwc_os.h::DWC_TASK_FREE" ref="6744f603216b19547a91097d0a0ca21c" args="(dwc_tasklet_t *t)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_TASK_FREE</b> (dwc_tasklet_t *t)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="99799fce55de6434ed75017cd62f34f7"></a><!-- doxytag: member="dwc_os.h::DWC_TASK_SCHEDULE" ref="99799fce55de6434ed75017cd62f34f7" args="(dwc_tasklet_t *task)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_TASK_SCHEDULE</b> (dwc_tasklet_t *task)</td></tr>
+
+<tr><td colspan="2"><br><h2>Timer</h2></td></tr>
+<tr><td colspan="2">Callbacks must be small and atomic. <br><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c8c6f6aee73e40ed44c0dff6a96fdbd7"></a><!-- doxytag: member="dwc_os.h::dwc_timer_alloc" ref="c8c6f6aee73e40ed44c0dff6a96fdbd7" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_timer_alloc</b>&nbsp;&nbsp;&nbsp;DWC_TIMER_ALLOC</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="2e773c6ddb48d0da29fad64306039211"></a><!-- doxytag: member="dwc_os.h::dwc_timer_free" ref="2e773c6ddb48d0da29fad64306039211" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_timer_free</b>&nbsp;&nbsp;&nbsp;DWC_TIMER_FREE</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="239677ac3dde1a0adb3922542077a013"></a><!-- doxytag: member="dwc_os.h::dwc_timer_schedule" ref="239677ac3dde1a0adb3922542077a013" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_timer_schedule</b>&nbsp;&nbsp;&nbsp;DWC_TIMER_SCHEDULE</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3346c44633b61bfe75ded677ad344fef"></a><!-- doxytag: member="dwc_os.h::dwc_timer_cancel" ref="3346c44633b61bfe75ded677ad344fef" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_timer_cancel</b>&nbsp;&nbsp;&nbsp;DWC_TIMER_CANCEL</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="db9852816f9e6b108e089d111e8914a1"></a><!-- doxytag: member="dwc_os.h::dwc_timer_t" ref="db9852816f9e6b108e089d111e8914a1" args="" -->
+typedef dwc_timer&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_timer_t</b></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="930603062084a9f4f6173fb8f203091e"></a><!-- doxytag: member="dwc_os.h::dwc_timer_callback_t" ref="930603062084a9f4f6173fb8f203091e" args="(void *data)" -->
+typedef void(*)&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_timer_callback_t</b> (void *data)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ef3dad19ef44fc369a48720190d37e9a"></a><!-- doxytag: member="dwc_os.h::DWC_TIMER_ALLOC" ref="ef3dad19ef44fc369a48720190d37e9a" args="(char *name, dwc_timer_callback_t cb, void *data)" -->
+dwc_timer_t *&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_TIMER_ALLOC</b> (char *name, dwc_timer_callback_t cb, void *data)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="a629b4c6886c841949660704daf9c0ce"></a><!-- doxytag: member="dwc_os.h::DWC_TIMER_FREE" ref="a629b4c6886c841949660704daf9c0ce" args="(dwc_timer_t *timer)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_TIMER_FREE</b> (dwc_timer_t *timer)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#fc7f822dbb92bfe8f39d58f56424d690">DWC_TIMER_SCHEDULE</a> (dwc_timer_t *timer, uint32_t time)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Schedules the timer to run at time ms from now.  <a href="#fc7f822dbb92bfe8f39d58f56424d690"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#e3b250c6df138b515ac0c14e34331c20">DWC_TIMER_CANCEL</a> (dwc_timer_t *timer)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Disables the timer from execution.  <a href="#e3b250c6df138b515ac0c14e34331c20"></a><br></td></tr>
+<tr><td colspan="2"><br><h2>Spinlocks</h2></td></tr>
+<tr><td colspan="2">These locks are used when the work between the lock/unlock is atomic and short. Interrupts are also disabled during the lock/unlock and thus they are suitable to lock between interrupt/non-interrupt context. They also lock between processes if you have multiple CPUs or Preemption. If you don't have multiple CPUS or Preemption, then the you can simply implement the DWC_SPINLOCK and DWC_SPINUNLOCK to disable and enable interrupts. Because the work between the lock/unlock is atomic, the process context will never change, and so you never have to lock between processes. <br><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f3818d9d3981697579fab72c4a1e84a4"></a><!-- doxytag: member="dwc_os.h::dwc_spinlock_alloc" ref="f3818d9d3981697579fab72c4a1e84a4" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_spinlock_alloc</b>&nbsp;&nbsp;&nbsp;DWC_SPINLOCK_ALLOC</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="4db354695aa17752b132b64befd34105"></a><!-- doxytag: member="dwc_os.h::dwc_spinlock_free" ref="4db354695aa17752b132b64befd34105" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_spinlock_free</b>&nbsp;&nbsp;&nbsp;DWC_SPINLOCK_FREE</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="6e89662682039814f0b43b0d0daa33b7"></a><!-- doxytag: member="dwc_os.h::dwc_spinlock_irqsave" ref="6e89662682039814f0b43b0d0daa33b7" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_spinlock_irqsave</b>&nbsp;&nbsp;&nbsp;DWC_SPINLOCK_IRQSAVE</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="48fcd748bf04ff4cb1cb4d2dea76abbd"></a><!-- doxytag: member="dwc_os.h::dwc_spinunlock_irqrestore" ref="48fcd748bf04ff4cb1cb4d2dea76abbd" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_spinunlock_irqrestore</b>&nbsp;&nbsp;&nbsp;DWC_SPINUNLOCK_IRQRESTORE</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="2bbd2ea5515a81630e4f8e0c3ddd154d"></a><!-- doxytag: member="dwc_os.h::dwc_spinlock" ref="2bbd2ea5515a81630e4f8e0c3ddd154d" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_spinlock</b>&nbsp;&nbsp;&nbsp;DWC_SPINLOCK</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="91d54ca74da0821f045496d88bf51950"></a><!-- doxytag: member="dwc_os.h::dwc_spinunlock" ref="91d54ca74da0821f045496d88bf51950" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_spinunlock</b>&nbsp;&nbsp;&nbsp;DWC_SPINUNLOCK</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="5e7560e8c3b2d743b63af3d968772483"></a><!-- doxytag: member="dwc_os.h::dwc_spinlock_t" ref="5e7560e8c3b2d743b63af3d968772483" args="" -->
+typedef dwc_spinlock&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_spinlock_t</b></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">dwc_spinlock_t *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#9835746177a3943b5042b7ee372d51b7">DWC_SPINLOCK_ALLOC</a> (void)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Returns an initialized lock variable.  <a href="#9835746177a3943b5042b7ee372d51b7"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#d14d73128f7d826a5b5d134c5ed68ee3">DWC_SPINLOCK_FREE</a> (dwc_spinlock_t *lock)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Frees an initialized lock variable.  <a href="#d14d73128f7d826a5b5d134c5ed68ee3"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#669a98495836ed25385ce90ce187e169">DWC_SPINLOCK_IRQSAVE</a> (dwc_spinlock_t *lock, uint64_t *flags)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Disables interrupts and blocks until it acquires the lock.  <a href="#669a98495836ed25385ce90ce187e169"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#34f4a1c6a12c226efb0ced4c270ccf44">DWC_SPINUNLOCK_IRQRESTORE</a> (dwc_spinlock_t *lock, uint64_t flags)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Re-enables the interrupt and releases the lock.  <a href="#34f4a1c6a12c226efb0ced4c270ccf44"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#2403e448ef5c0f70c5c58e918090af21">DWC_SPINLOCK</a> (dwc_spinlock_t *lock)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Blocks until it acquires the lock.  <a href="#2403e448ef5c0f70c5c58e918090af21"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#a50b0e7e31e47fd302b37fadaa0bf925">DWC_SPINUNLOCK</a> (dwc_spinlock_t *lock)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Releases the lock.  <a href="#a50b0e7e31e47fd302b37fadaa0bf925"></a><br></td></tr>
+<tr><td colspan="2"><br><h2>Mutexes</h2></td></tr>
+<tr><td colspan="2">Unlike spinlocks Mutexes lock only between processes and the work between the lock/unlock CAN block, therefore it CANNOT be called from interrupt context. <br><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3bbd558ccf907313430a001678ebba24"></a><!-- doxytag: member="dwc_os.h::dwc_mutex_alloc" ref="3bbd558ccf907313430a001678ebba24" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_mutex_alloc</b>&nbsp;&nbsp;&nbsp;DWC_MUTEX_ALLOC</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="409f3279aaeaf0ada67dde59a71f1f22"></a><!-- doxytag: member="dwc_os.h::dwc_mutex_free" ref="409f3279aaeaf0ada67dde59a71f1f22" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_mutex_free</b>&nbsp;&nbsp;&nbsp;DWC_MUTEX_FREE</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="dd737fa7af696d2ffdd16b180156ec0f"></a><!-- doxytag: member="dwc_os.h::dwc_mutex_lock" ref="dd737fa7af696d2ffdd16b180156ec0f" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_mutex_lock</b>&nbsp;&nbsp;&nbsp;DWC_MUTEX_LOCK</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="df59369a9ee1845e8597c2aa4e8a1b43"></a><!-- doxytag: member="dwc_os.h::dwc_mutex_trylock" ref="df59369a9ee1845e8597c2aa4e8a1b43" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_mutex_trylock</b>&nbsp;&nbsp;&nbsp;DWC_MUTEX_TRYLOCK</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="1a23dff996207ed44531a209170cca91"></a><!-- doxytag: member="dwc_os.h::dwc_mutex_unlock" ref="1a23dff996207ed44531a209170cca91" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_mutex_unlock</b>&nbsp;&nbsp;&nbsp;DWC_MUTEX_UNLOCK</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="74d03028b581f07a995114462af89bd0"></a><!-- doxytag: member="dwc_os.h::dwc_mutex_t" ref="74d03028b581f07a995114462af89bd0" args="" -->
+typedef dwc_mutex&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_mutex_t</b></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3c7926f7943915bdfdc7846cce93ffe7"></a><!-- doxytag: member="dwc_os.h::DWC_MUTEX_ALLOC" ref="3c7926f7943915bdfdc7846cce93ffe7" args="(void)" -->
+dwc_mutex_t *&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_MUTEX_ALLOC</b> (void)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3649b547a9b4dcc7121c1f75a1b79bec"></a><!-- doxytag: member="dwc_os.h::DWC_MUTEX_FREE" ref="3649b547a9b4dcc7121c1f75a1b79bec" args="(dwc_mutex_t *mutex)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_MUTEX_FREE</b> (dwc_mutex_t *mutex)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="368431e69cf3a8fddbfc9db0d6d31d88"></a><!-- doxytag: member="dwc_os.h::DWC_MUTEX_LOCK" ref="368431e69cf3a8fddbfc9db0d6d31d88" args="(dwc_mutex_t *mutex)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_MUTEX_LOCK</b> (dwc_mutex_t *mutex)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#aac499623d39831c288e60d6034279c0">DWC_MUTEX_TRYLOCK</a> (dwc_mutex_t *mutex)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Non-blocking lock returns 1 on successful lock.  <a href="#aac499623d39831c288e60d6034279c0"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7aed0381b6584da02141b3af5dd37db0"></a><!-- doxytag: member="dwc_os.h::DWC_MUTEX_UNLOCK" ref="7aed0381b6584da02141b3af5dd37db0" args="(dwc_mutex_t *mutex)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_MUTEX_UNLOCK</b> (dwc_mutex_t *mutex)</td></tr>
+
+<tr><td colspan="2"><br><h2>Time</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e343fbe0b9f5b5737e96ff68fcf39771"></a><!-- doxytag: member="dwc_os.h::dwc_udelay" ref="e343fbe0b9f5b5737e96ff68fcf39771" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_udelay</b>&nbsp;&nbsp;&nbsp;DWC_UDELAY</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="2286135b538d0ec988fbfb99cf15fce3"></a><!-- doxytag: member="dwc_os.h::dwc_mdelay" ref="2286135b538d0ec988fbfb99cf15fce3" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_mdelay</b>&nbsp;&nbsp;&nbsp;DWC_MDELAY</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="40fabe9c53322b3c930b28269524a8df"></a><!-- doxytag: member="dwc_os.h::dwc_msleep" ref="40fabe9c53322b3c930b28269524a8df" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_msleep</b>&nbsp;&nbsp;&nbsp;DWC_MSLEEP</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="5e9651b0f63c2fd06319db913895364e"></a><!-- doxytag: member="dwc_os.h::dwc_time" ref="5e9651b0f63c2fd06319db913895364e" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_time</b>&nbsp;&nbsp;&nbsp;DWC_TIME</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#4346ef090ef63e6eebc943372e77c4ae">DWC_UDELAY</a> (uint32_t usecs)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Microsecond delay.  <a href="#4346ef090ef63e6eebc943372e77c4ae"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#82dc3d687003425801fb384311e4c608">DWC_MDELAY</a> (uint32_t msecs)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Millisecond delay.  <a href="#82dc3d687003425801fb384311e4c608"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__os_8h.html#6e9ddb27d45df5f5cfa34ed9ebb1c8d0">DWC_MSLEEP</a> (uint32_t msecs)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Non-busy waiting.  <a href="#6e9ddb27d45df5f5cfa34ed9ebb1c8d0"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="153056b13a7d7bdc9b033f9e19170119"></a><!-- doxytag: member="dwc_os.h::DWC_TIME" ref="153056b13a7d7bdc9b033f9e19170119" args="(void)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_TIME</b> (void)</td></tr>
+
+</table>
+<hr><h2>Define Documentation</h2>
+<a class="anchor" name="c91431cc824741def21c86e778361e6b"></a><!-- doxytag: member="dwc_os.h::DWC_DEBUG" ref="c91431cc824741def21c86e778361e6b" args="(_format, _args...)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_DEBUG          </td>
+          <td>(</td>
+          <td class="paramtype">_format,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">_args...&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%">&nbsp;&nbsp;&nbsp;__DWC_DEBUG(&quot;DEBUG:%s:%s: &quot; _format &quot;\n&quot;, __func__, dwc_irq(), ## _args)</td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Prints out a Debug message. 
+<p>
+
+</div>
+</div><p>
+<a class="anchor" name="f30c815ec9d3d710a4c0ccb993a84d86"></a><!-- doxytag: member="dwc_os.h::DWC_INFO" ref="f30c815ec9d3d710a4c0ccb993a84d86" args="(_format, _args...)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_INFO          </td>
+          <td>(</td>
+          <td class="paramtype">_format,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">_args...&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%">&nbsp;&nbsp;&nbsp;DWC_PRINTF(&quot;INFO:%s: &quot; _format &quot;\n&quot;, dwc_irq(), ## _args)</td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Prints out an informative message. 
+<p>
+
+</div>
+</div><p>
+<a class="anchor" name="d475a8dc748be355af32ad01de0c257a"></a><!-- doxytag: member="dwc_os.h::DWC_WARN" ref="d475a8dc748be355af32ad01de0c257a" args="(_format, _args...)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_WARN          </td>
+          <td>(</td>
+          <td class="paramtype">_format,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">_args...&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%">&nbsp;&nbsp;&nbsp;__DWC_WARN(&quot;WARN:%s:%s:%d: &quot; _format &quot;\n&quot;, dwc_irq(), __func__, __LINE__, ## _args)</td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Prints out a warning message. 
+<p>
+
+</div>
+</div><p>
+<a class="anchor" name="7f87f33fab81a2ad602599e16db8b067"></a><!-- doxytag: member="dwc_os.h::DWC_ERROR" ref="7f87f33fab81a2ad602599e16db8b067" args="(_format, _args...)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_ERROR          </td>
+          <td>(</td>
+          <td class="paramtype">_format,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">_args...&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%">&nbsp;&nbsp;&nbsp;__DWC_ERROR(&quot;ERROR:%s:%s:%d: &quot; _format &quot;\n&quot;, dwc_irq(), __func__, __LINE__, ## _args)</td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Prints out an error message. 
+<p>
+
+</div>
+</div><p>
+<a class="anchor" name="1dd30b105001754e01596cfb0a01e572"></a><!-- doxytag: member="dwc_os.h::DWC_ASSERT" ref="1dd30b105001754e01596cfb0a01e572" args="(_expr, _format, _args...)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_ASSERT          </td>
+          <td>(</td>
+          <td class="paramtype">_expr,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">_format,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">_args...&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%">&nbsp;&nbsp;&nbsp;if (!(_expr)) { DWC_EXCEPTION(&quot;%s:%s:%d: &quot; _format &quot;\n&quot;, dwc_irq(), __FILE__, __LINE__, ## _args); }</td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Prints out a exception error message if the _expr expression fails. 
+<p>
+Disabled if DEBUG is not enabled. 
+</div>
+</div><p>
+<hr><h2>Typedef Documentation</h2>
+<a class="anchor" name="e2374f0b1253fc63321e1b253ee61b1d"></a><!-- doxytag: member="dwc_os.h::dwc_bool_t" ref="e2374f0b1253fc63321e1b253ee61b1d" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef uint8_t <a class="el" href="dwc__os_8h.html#e2374f0b1253fc63321e1b253ee61b1d">dwc_bool_t</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+We define a boolean type for consistency. 
+<p>
+Can be either YES or NO 
+</div>
+</div><p>
+<a class="anchor" name="b361f6bc4eff88c0ddda059569da125f"></a><!-- doxytag: member="dwc_os.h::dwc_waitq_condition_t" ref="b361f6bc4eff88c0ddda059569da125f" args="(void *data)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef int(*) <a class="el" href="dwc__os_8h.html#b361f6bc4eff88c0ddda059569da125f">dwc_waitq_condition_t</a>(void *data)          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+The type of waitq condition callback function. 
+<p>
+This is called every time condition is evaluated. 
+</div>
+</div><p>
+<a class="anchor" name="d34bdab089ddbc0e479c9fead16ca7ac"></a><!-- doxytag: member="dwc_os.h::dwc_thread_function_t" ref="d34bdab089ddbc0e479c9fead16ca7ac" args="(void *data)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef int(*) <a class="el" href="dwc__os_8h.html#d34bdab089ddbc0e479c9fead16ca7ac">dwc_thread_function_t</a>(void *data)          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+The thread function. 
+<p>
+
+</div>
+</div><p>
+<a class="anchor" name="c67973a4ac14764ed66a82103a357c06"></a><!-- doxytag: member="dwc_os.h::dwc_work_callback_t" ref="c67973a4ac14764ed66a82103a357c06" args="(void *data)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef void(*) <a class="el" href="dwc__os_8h.html#c67973a4ac14764ed66a82103a357c06">dwc_work_callback_t</a>(void *data)          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+The type of the callback function to be called. 
+<p>
+
+</div>
+</div><p>
+<hr><h2>Function Documentation</h2>
+<a class="anchor" name="830b5c18c8b32f36ef5948df9b310959"></a><!-- doxytag: member="dwc_os.h::DWC_IN_IRQ" ref="830b5c18c8b32f36ef5948df9b310959" args="(void)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="dwc__os_8h.html#e2374f0b1253fc63321e1b253ee61b1d">dwc_bool_t</a> DWC_IN_IRQ           </td>
+          <td>(</td>
+          <td class="paramtype">void&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Returns non-zero if in interrupt context. 
+<p>
+
+</div>
+</div><p>
+<a class="anchor" name="9df340bcf2f004c69b9d917724e22955"></a><!-- doxytag: member="dwc_os.h::dwc_irq" ref="9df340bcf2f004c69b9d917724e22955" args="(void)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static char* dwc_irq           </td>
+          <td>(</td>
+          <td class="paramtype">void&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [inline, static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Returns "IRQ" if DWC_IN_IRQ is true. 
+<p>
+
+</div>
+</div><p>
+<a class="anchor" name="dedf4a24c1af865c0a73b685a807383d"></a><!-- doxytag: member="dwc_os.h::DWC_VPRINTF" ref="dedf4a24c1af865c0a73b685a807383d" args="(char *format, va_list args)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void DWC_VPRINTF           </td>
+          <td>(</td>
+          <td class="paramtype">char *&nbsp;</td>
+          <td class="paramname"> <em>format</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">va_list&nbsp;</td>
+          <td class="paramname"> <em>args</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+A vprintf() clone. 
+<p>
+Just call vprintf if you've got it. 
+</div>
+</div><p>
+<a class="anchor" name="8fdc0abfec4f97c78b59cece02718f35"></a><!-- doxytag: member="dwc_os.h::DWC_VSNPRINTF" ref="8fdc0abfec4f97c78b59cece02718f35" args="(char *str, int size, char *format, va_list args)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int DWC_VSNPRINTF           </td>
+          <td>(</td>
+          <td class="paramtype">char *&nbsp;</td>
+          <td class="paramname"> <em>str</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>size</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">char *&nbsp;</td>
+          <td class="paramname"> <em>format</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">va_list&nbsp;</td>
+          <td class="paramname"> <em>args</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+A vsnprintf() clone. 
+<p>
+Just call vprintf if you've got it. 
+</div>
+</div><p>
+<a class="anchor" name="ff25ba1e8c8760561e74df4faa45a3c7"></a><!-- doxytag: member="dwc_os.h::DWC_PRINTF" ref="ff25ba1e8c8760561e74df4faa45a3c7" args="(char *format,...)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void DWC_PRINTF           </td>
+          <td>(</td>
+          <td class="paramtype">char *&nbsp;</td>
+          <td class="paramname"> <em>format</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&nbsp;</td>
+          <td class="paramname"> <em>...</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+printf() clone. 
+<p>
+Just call printf if you've go it. 
+</div>
+</div><p>
+<a class="anchor" name="6bc72ec00a8247404cda1ad5fa88fb86"></a><!-- doxytag: member="dwc_os.h::DWC_SPRINTF" ref="6bc72ec00a8247404cda1ad5fa88fb86" args="(char *string, char *format,...)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int DWC_SPRINTF           </td>
+          <td>(</td>
+          <td class="paramtype">char *&nbsp;</td>
+          <td class="paramname"> <em>string</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">char *&nbsp;</td>
+          <td class="paramname"> <em>format</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&nbsp;</td>
+          <td class="paramname"> <em>...</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+sprintf() clone. 
+<p>
+Just call sprintf if you've got it. 
+</div>
+</div><p>
+<a class="anchor" name="f9d4dbc0799ef36f89e78eea0a60b563"></a><!-- doxytag: member="dwc_os.h::DWC_SNPRINTF" ref="f9d4dbc0799ef36f89e78eea0a60b563" args="(char *string, int size, char *format,...)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int DWC_SNPRINTF           </td>
+          <td>(</td>
+          <td class="paramtype">char *&nbsp;</td>
+          <td class="paramname"> <em>string</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>size</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">char *&nbsp;</td>
+          <td class="paramname"> <em>format</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&nbsp;</td>
+          <td class="paramname"> <em>...</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+snprintf() clone. 
+<p>
+Just call snprintf if you've got it. 
+</div>
+</div><p>
+<a class="anchor" name="da29736470afbdc41a0f7c7e8d9a2f0d"></a><!-- doxytag: member="dwc_os.h::__DWC_WARN" ref="da29736470afbdc41a0f7c7e8d9a2f0d" args="(char *format,...)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void __DWC_WARN           </td>
+          <td>(</td>
+          <td class="paramtype">char *&nbsp;</td>
+          <td class="paramname"> <em>format</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&nbsp;</td>
+          <td class="paramname"> <em>...</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Prints a WARNING message. 
+<p>
+On systems that don't differentiate between warnings and regular log messages, just print it. Indicates that something may be wrong with the driver. Works like printf().<p>
+Use the DWC_WARN macro to call this function. 
+</div>
+</div><p>
+<a class="anchor" name="54dcd8d8647879b6803585f98bcc3c71"></a><!-- doxytag: member="dwc_os.h::__DWC_ERROR" ref="54dcd8d8647879b6803585f98bcc3c71" args="(char *format,...)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void __DWC_ERROR           </td>
+          <td>(</td>
+          <td class="paramtype">char *&nbsp;</td>
+          <td class="paramname"> <em>format</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&nbsp;</td>
+          <td class="paramname"> <em>...</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Prints an error message. 
+<p>
+On systems that don't differentiate between errors and regular log messages, just print it. Indicates that something went wrong with the driver, but it can be recovered from. Works like printf().<p>
+Use the DWC_ERROR macro to call this function. 
+</div>
+</div><p>
+<a class="anchor" name="96ee4cab04e3ec11f47beedaea6fe752"></a><!-- doxytag: member="dwc_os.h::DWC_EXCEPTION" ref="96ee4cab04e3ec11f47beedaea6fe752" args="(char *format,...)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void DWC_EXCEPTION           </td>
+          <td>(</td>
+          <td class="paramtype">char *&nbsp;</td>
+          <td class="paramname"> <em>format</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&nbsp;</td>
+          <td class="paramname"> <em>...</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Prints an exception error message and takes some user-defined action such as print out a backtrace or trigger a breakpoint. 
+<p>
+Indicates that something went abnormally wrong with the driver such as programmer error, or other exceptional condition. It should not be ignored so even on systems without printing capability, some action should be taken to notify the developer of it. Works like printf(). 
+</div>
+</div><p>
+<a class="anchor" name="24c83900d9653d50bf5874fb3b787e07"></a><!-- doxytag: member="dwc_os.h::__DWC_DEBUG" ref="24c83900d9653d50bf5874fb3b787e07" args="(char *format,...)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void __DWC_DEBUG           </td>
+          <td>(</td>
+          <td class="paramtype">char *&nbsp;</td>
+          <td class="paramname"> <em>format</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&nbsp;</td>
+          <td class="paramname"> <em>...</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Prints out a debug message. 
+<p>
+Used for logging/trace messages.<p>
+Use the DWC_DEBUG macro to call this function 
+</div>
+</div><p>
+<a class="anchor" name="e3f5dbab365dc4e3aab74d95fe26c654"></a><!-- doxytag: member="dwc_os.h::DWC_CPU_TO_LE32" ref="e3f5dbab365dc4e3aab74d95fe26c654" args="(void *p)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t DWC_CPU_TO_LE32           </td>
+          <td>(</td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>p</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Converts 32 bit data in CPU byte ordering to little endian. 
+<p>
+
+</div>
+</div><p>
+<a class="anchor" name="5504b62058f8a69ffa9dfd28712a9ea0"></a><!-- doxytag: member="dwc_os.h::DWC_CPU_TO_BE32" ref="5504b62058f8a69ffa9dfd28712a9ea0" args="(void *p)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t DWC_CPU_TO_BE32           </td>
+          <td>(</td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>p</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Converts 32 bit data in CPU byte orderint to big endian. 
+<p>
+
+</div>
+</div><p>
+<a class="anchor" name="7e6e45719874b966f5eead1079dce589"></a><!-- doxytag: member="dwc_os.h::DWC_LE32_TO_CPU" ref="7e6e45719874b966f5eead1079dce589" args="(void *p)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t DWC_LE32_TO_CPU           </td>
+          <td>(</td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>p</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Converts 32 bit little endian data to CPU byte ordering. 
+<p>
+
+</div>
+</div><p>
+<a class="anchor" name="ac5cda361023e4b10ff059bce576d2b4"></a><!-- doxytag: member="dwc_os.h::DWC_BE32_TO_CPU" ref="ac5cda361023e4b10ff059bce576d2b4" args="(void *p)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t DWC_BE32_TO_CPU           </td>
+          <td>(</td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>p</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Converts 32 bit big endian data to CPU byte ordering. 
+<p>
+
+</div>
+</div><p>
+<a class="anchor" name="0ee58f208f5b2ec70aed9a0133d33479"></a><!-- doxytag: member="dwc_os.h::DWC_CPU_TO_LE16" ref="0ee58f208f5b2ec70aed9a0133d33479" args="(void *p)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint16_t DWC_CPU_TO_LE16           </td>
+          <td>(</td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>p</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Converts 16 bit data in CPU byte ordering to little endian. 
+<p>
+
+</div>
+</div><p>
+<a class="anchor" name="4b7cb22cfd1ec8f87965c9e2de43838f"></a><!-- doxytag: member="dwc_os.h::DWC_CPU_TO_BE16" ref="4b7cb22cfd1ec8f87965c9e2de43838f" args="(void *p)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint16_t DWC_CPU_TO_BE16           </td>
+          <td>(</td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>p</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Converts 16 bit data in CPU byte orderint to big endian. 
+<p>
+
+</div>
+</div><p>
+<a class="anchor" name="157b0438d386b5529abcc54c886b7ddc"></a><!-- doxytag: member="dwc_os.h::DWC_LE16_TO_CPU" ref="157b0438d386b5529abcc54c886b7ddc" args="(void *p)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint16_t DWC_LE16_TO_CPU           </td>
+          <td>(</td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>p</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Converts 16 bit little endian data to CPU byte ordering. 
+<p>
+
+</div>
+</div><p>
+<a class="anchor" name="039677525ccd7b262a486a788523a4fa"></a><!-- doxytag: member="dwc_os.h::DWC_BE16_TO_CPU" ref="039677525ccd7b262a486a788523a4fa" args="(void *p)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint16_t DWC_BE16_TO_CPU           </td>
+          <td>(</td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>p</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Converts 16 bit bi endian data to CPU byte ordering. 
+<p>
+
+</div>
+</div><p>
+<a class="anchor" name="998a1b27461c926d8c19de202f0e05ca"></a><!-- doxytag: member="dwc_os.h::DWC_READ_REG32" ref="998a1b27461c926d8c19de202f0e05ca" args="(uint32_t volatile *reg)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t DWC_READ_REG32           </td>
+          <td>(</td>
+          <td class="paramtype">uint32_t volatile *&nbsp;</td>
+          <td class="paramname"> <em>reg</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Reads the content of a 32-bit register. 
+<p>
+
+</div>
+</div><p>
+<a class="anchor" name="04a809b4ec80265acf393a6d2bff8916"></a><!-- doxytag: member="dwc_os.h::DWC_READ_REG64" ref="04a809b4ec80265acf393a6d2bff8916" args="(uint64_t volatile *reg)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint64_t DWC_READ_REG64           </td>
+          <td>(</td>
+          <td class="paramtype">uint64_t volatile *&nbsp;</td>
+          <td class="paramname"> <em>reg</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Reads the content of a 64-bit register. 
+<p>
+
+</div>
+</div><p>
+<a class="anchor" name="9166df012531473304420325a61302cf"></a><!-- doxytag: member="dwc_os.h::DWC_WRITE_REG32" ref="9166df012531473304420325a61302cf" args="(uint32_t volatile *reg, uint32_t value)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void DWC_WRITE_REG32           </td>
+          <td>(</td>
+          <td class="paramtype">uint32_t volatile *&nbsp;</td>
+          <td class="paramname"> <em>reg</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint32_t&nbsp;</td>
+          <td class="paramname"> <em>value</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Writes to a 32-bit register. 
+<p>
+
+</div>
+</div><p>
+<a class="anchor" name="59ef876d933b94b75a659c1614946496"></a><!-- doxytag: member="dwc_os.h::DWC_WRITE_REG64" ref="59ef876d933b94b75a659c1614946496" args="(uint64_t volatile *reg, uint64_t value)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void DWC_WRITE_REG64           </td>
+          <td>(</td>
+          <td class="paramtype">uint64_t volatile *&nbsp;</td>
+          <td class="paramname"> <em>reg</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint64_t&nbsp;</td>
+          <td class="paramname"> <em>value</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Writes to a 64-bit register. 
+<p>
+
+</div>
+</div><p>
+<a class="anchor" name="a0be0db1cab4dcc65c7d508b15e5d209"></a><!-- doxytag: member="dwc_os.h::DWC_MODIFY_REG32" ref="a0be0db1cab4dcc65c7d508b15e5d209" args="(uint32_t volatile *reg, uint32_t clear_mask, uint32_t set_mask)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void DWC_MODIFY_REG32           </td>
+          <td>(</td>
+          <td class="paramtype">uint32_t volatile *&nbsp;</td>
+          <td class="paramname"> <em>reg</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint32_t&nbsp;</td>
+          <td class="paramname"> <em>clear_mask</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint32_t&nbsp;</td>
+          <td class="paramname"> <em>set_mask</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Modify bit values in a register. 
+<p>
+Using the algorithm: (reg_contents &amp; ~clear_mask) | set_mask. 
+</div>
+</div><p>
+<a class="anchor" name="d25677e4a3299c7ae65e520015172124"></a><!-- doxytag: member="dwc_os.h::DWC_AES_CBC" ref="d25677e4a3299c7ae65e520015172124" args="(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int DWC_AES_CBC           </td>
+          <td>(</td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>message</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint32_t&nbsp;</td>
+          <td class="paramname"> <em>messagelen</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>key</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint32_t&nbsp;</td>
+          <td class="paramname"> <em>keylen</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t&nbsp;</td>
+          <td class="paramname"> <em>iv</em>[16], </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>out</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Perform AES CBC. 
+<p>
+
+</div>
+</div><p>
+<a class="anchor" name="3e85fc1609d2791628e718c284f3a37f"></a><!-- doxytag: member="dwc_os.h::DWC_RANDOM_BYTES" ref="3e85fc1609d2791628e718c284f3a37f" args="(uint8_t *buffer, uint32_t length)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void DWC_RANDOM_BYTES           </td>
+          <td>(</td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>buffer</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint32_t&nbsp;</td>
+          <td class="paramname"> <em>length</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Fill the provided buffer with random bytes. 
+<p>
+These should be cryptographic grade random numbers. 
+</div>
+</div><p>
+<a class="anchor" name="30bc2a37980e41bea58057131229d543"></a><!-- doxytag: member="dwc_os.h::DWC_SHA256" ref="30bc2a37980e41bea58057131229d543" args="(uint8_t *message, uint32_t len, uint8_t *out)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int DWC_SHA256           </td>
+          <td>(</td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>message</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint32_t&nbsp;</td>
+          <td class="paramname"> <em>len</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>out</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Perform the SHA-256 hash function. 
+<p>
+
+</div>
+</div><p>
+<a class="anchor" name="b312283cc1cec404b8753eb0a3d9d051"></a><!-- doxytag: member="dwc_os.h::DWC_HMAC_SHA256" ref="b312283cc1cec404b8753eb0a3d9d051" args="(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t *out)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int DWC_HMAC_SHA256           </td>
+          <td>(</td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>message</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint32_t&nbsp;</td>
+          <td class="paramname"> <em>messagelen</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>key</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint32_t&nbsp;</td>
+          <td class="paramname"> <em>keylen</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>out</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Calculated the HMAC-SHA256. 
+<p>
+
+</div>
+</div><p>
+<a class="anchor" name="f74ba85fa4f2dcb59886b2f3d4ef709f"></a><!-- doxytag: member="dwc_os.h::__DWC_DMA_ALLOC" ref="f74ba85fa4f2dcb59886b2f3d4ef709f" args="(uint32_t size, dwc_dma_t *dma_addr)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void* __DWC_DMA_ALLOC           </td>
+          <td>(</td>
+          <td class="paramtype">uint32_t&nbsp;</td>
+          <td class="paramname"> <em>size</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">dwc_dma_t *&nbsp;</td>
+          <td class="paramname"> <em>dma_addr</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Allocates a DMA capable buffer and zeroes its contents. 
+<p>
+
+</div>
+</div><p>
+<a class="anchor" name="04a8867a0602eccf0d759206d89bde96"></a><!-- doxytag: member="dwc_os.h::__DWC_DMA_FREE" ref="04a8867a0602eccf0d759206d89bde96" args="(uint32_t size, void *virt_addr, dwc_dma_t dma_addr)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void __DWC_DMA_FREE           </td>
+          <td>(</td>
+          <td class="paramtype">uint32_t&nbsp;</td>
+          <td class="paramname"> <em>size</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>virt_addr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">dwc_dma_t&nbsp;</td>
+          <td class="paramname"> <em>dma_addr</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Frees a previosly allocated buffer. 
+<p>
+
+</div>
+</div><p>
+<a class="anchor" name="f0da81fbd5a3822ded21f74e650b6f56"></a><!-- doxytag: member="dwc_os.h::__DWC_ALLOC" ref="f0da81fbd5a3822ded21f74e650b6f56" args="(uint32_t size)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void* __DWC_ALLOC           </td>
+          <td>(</td>
+          <td class="paramtype">uint32_t&nbsp;</td>
+          <td class="paramname"> <em>size</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Allocates a block of memory and zeroes its contents. 
+<p>
+
+</div>
+</div><p>
+<a class="anchor" name="ce6c64a02c1b62bdd693f827c06803e1"></a><!-- doxytag: member="dwc_os.h::__DWC_ALLOC_ATOMIC" ref="ce6c64a02c1b62bdd693f827c06803e1" args="(uint32_t size)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void* __DWC_ALLOC_ATOMIC           </td>
+          <td>(</td>
+          <td class="paramtype">uint32_t&nbsp;</td>
+          <td class="paramname"> <em>size</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Allocates a block of memory and zeroes its contents, in an atomic manner which can be used inside interrupt context. 
+<p>
+The size should be sufficiently small, a few KB at most, such that failures are not likely to occur. Can just call __DWC_ALLOC if it is atomic. 
+</div>
+</div><p>
+<a class="anchor" name="578dd2d0619aab9c86e31f4828a9afe5"></a><!-- doxytag: member="dwc_os.h::__DWC_FREE" ref="578dd2d0619aab9c86e31f4828a9afe5" args="(void *addr)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void __DWC_FREE           </td>
+          <td>(</td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>addr</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Frees a previously allocated buffer. 
+<p>
+
+</div>
+</div><p>
+<a class="anchor" name="d14e248de8bd334f6065bb9c09305a65"></a><!-- doxytag: member="dwc_os.h::DWC_MEMSET" ref="d14e248de8bd334f6065bb9c09305a65" args="(void *dest, uint8_t byte, uint32_t size)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void* DWC_MEMSET           </td>
+          <td>(</td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>dest</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t&nbsp;</td>
+          <td class="paramname"> <em>byte</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint32_t&nbsp;</td>
+          <td class="paramname"> <em>size</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+memset() clone 
+<p>
+
+</div>
+</div><p>
+<a class="anchor" name="37c1b18d623367a7ca438e4d2a698ed5"></a><!-- doxytag: member="dwc_os.h::DWC_MEMCPY" ref="37c1b18d623367a7ca438e4d2a698ed5" args="(void *dest, void const *src, uint32_t size)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void* DWC_MEMCPY           </td>
+          <td>(</td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>dest</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void const *&nbsp;</td>
+          <td class="paramname"> <em>src</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint32_t&nbsp;</td>
+          <td class="paramname"> <em>size</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+memcpy() clone 
+<p>
+
+</div>
+</div><p>
+<a class="anchor" name="2bc77081fca508dab31a245d0dd214d9"></a><!-- doxytag: member="dwc_os.h::DWC_MEMMOVE" ref="2bc77081fca508dab31a245d0dd214d9" args="(void *dest, void *src, uint32_t size)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void* DWC_MEMMOVE           </td>
+          <td>(</td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>dest</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>src</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint32_t&nbsp;</td>
+          <td class="paramname"> <em>size</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+memmove() clone 
+<p>
+
+</div>
+</div><p>
+<a class="anchor" name="7a80d4bef3bc0f3d6297400b3858b80e"></a><!-- doxytag: member="dwc_os.h::DWC_MEMCMP" ref="7a80d4bef3bc0f3d6297400b3858b80e" args="(void *m1, void *m2, uint32_t size)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int DWC_MEMCMP           </td>
+          <td>(</td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>m1</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>m2</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint32_t&nbsp;</td>
+          <td class="paramname"> <em>size</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+memcmp() clone 
+<p>
+
+</div>
+</div><p>
+<a class="anchor" name="3f175e77ff50e30a9444d377bf16cb07"></a><!-- doxytag: member="dwc_os.h::DWC_STRCMP" ref="3f175e77ff50e30a9444d377bf16cb07" args="(void *s1, void *s2)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int DWC_STRCMP           </td>
+          <td>(</td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>s1</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>s2</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+strcmp() clone 
+<p>
+
+</div>
+</div><p>
+<a class="anchor" name="5692e7d364b935378e15a8f6a5b45afb"></a><!-- doxytag: member="dwc_os.h::DWC_STRNCMP" ref="5692e7d364b935378e15a8f6a5b45afb" args="(void *s1, void *s2, uint32_t size)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int DWC_STRNCMP           </td>
+          <td>(</td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>s1</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>s2</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint32_t&nbsp;</td>
+          <td class="paramname"> <em>size</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+strncmp() clone 
+<p>
+
+</div>
+</div><p>
+<a class="anchor" name="4605aef85763dd32580d13a462ad9add"></a><!-- doxytag: member="dwc_os.h::DWC_STRLEN" ref="4605aef85763dd32580d13a462ad9add" args="(char const *str)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int DWC_STRLEN           </td>
+          <td>(</td>
+          <td class="paramtype">char const *&nbsp;</td>
+          <td class="paramname"> <em>str</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+strlen() clone, for NULL terminated ASCII strings 
+<p>
+
+</div>
+</div><p>
+<a class="anchor" name="8c89eecb8b1b4c4330aac7ecc54f5be4"></a><!-- doxytag: member="dwc_os.h::DWC_STRCPY" ref="8c89eecb8b1b4c4330aac7ecc54f5be4" args="(char *to, const char *from)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">char* DWC_STRCPY           </td>
+          <td>(</td>
+          <td class="paramtype">char *&nbsp;</td>
+          <td class="paramname"> <em>to</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">const char *&nbsp;</td>
+          <td class="paramname"> <em>from</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+strcpy() clone, for NULL terminated ASCII strings 
+<p>
+
+</div>
+</div><p>
+<a class="anchor" name="d4b956a8a4bea03a73b1ca2bafe94231"></a><!-- doxytag: member="dwc_os.h::DWC_STRDUP" ref="d4b956a8a4bea03a73b1ca2bafe94231" args="(char const *str)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">char* DWC_STRDUP           </td>
+          <td>(</td>
+          <td class="paramtype">char const *&nbsp;</td>
+          <td class="paramname"> <em>str</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+strdup() clone. 
+<p>
+If you wish to use memory allocation debugging, this implementation of strdup should use the DWC_* memory routines instead of calling a predefined strdup. Otherwise the memory allocated by this routine will not be seen by the debugging routines. 
+</div>
+</div><p>
+<a class="anchor" name="d7080682441edd663b576334e307ebfe"></a><!-- doxytag: member="dwc_os.h::DWC_ATOI" ref="d7080682441edd663b576334e307ebfe" args="(char *str, int32_t *value)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int DWC_ATOI           </td>
+          <td>(</td>
+          <td class="paramtype">char *&nbsp;</td>
+          <td class="paramname"> <em>str</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t *&nbsp;</td>
+          <td class="paramname"> <em>value</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+NOT an atoi() clone. 
+<p>
+Read the description carefully. Returns an integer converted from the string str in base 10 unless the string begins with a "0x" in which case it is base 16. String must be a NULL terminated sequence of ASCII characters and may optionally begin with whitespace, a + or -, and a "0x" prefix if base 16. The remaining characters must be valid digits for the number and end with a NULL character. If any invalid characters are encountered or it returns with a negative error code and the results of the conversion are undefined. On sucess it returns 0. Overflow conditions are undefined. An example implementation using atoi() can be referenced from the Linux implementation. 
+</div>
+</div><p>
+<a class="anchor" name="f6a3d4b637d16e25f1f69cce51d2184e"></a><!-- doxytag: member="dwc_os.h::DWC_ATOUI" ref="f6a3d4b637d16e25f1f69cce51d2184e" args="(char *str, uint32_t *value)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int DWC_ATOUI           </td>
+          <td>(</td>
+          <td class="paramtype">char *&nbsp;</td>
+          <td class="paramname"> <em>str</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint32_t *&nbsp;</td>
+          <td class="paramname"> <em>value</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Same as above but for unsigned. 
+<p>
+
+</div>
+</div><p>
+<a class="anchor" name="0e7deede6fcd5a48347fb1714259375b"></a><!-- doxytag: member="dwc_os.h::DWC_UTF8_TO_UTF16LE" ref="0e7deede6fcd5a48347fb1714259375b" args="(uint8_t const *utf8string, uint16_t *utf16string, unsigned len)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int DWC_UTF8_TO_UTF16LE           </td>
+          <td>(</td>
+          <td class="paramtype">uint8_t const *&nbsp;</td>
+          <td class="paramname"> <em>utf8string</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint16_t *&nbsp;</td>
+          <td class="paramname"> <em>utf16string</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">unsigned&nbsp;</td>
+          <td class="paramname"> <em>len</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This routine returns a UTF16LE unicode encoded string from a UTF8 string. 
+<p>
+
+</div>
+</div><p>
+<a class="anchor" name="4c5d74e3fd7f8f32b3129ce47e8d5c0c"></a><!-- doxytag: member="dwc_os.h::DWC_WAITQ_ALLOC" ref="4c5d74e3fd7f8f32b3129ce47e8d5c0c" args="(void)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">dwc_waitq_t* DWC_WAITQ_ALLOC           </td>
+          <td>(</td>
+          <td class="paramtype">void&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Allocate a waitq. 
+<p>
+
+</div>
+</div><p>
+<a class="anchor" name="7b731581f7ab4db7ec2e8874bfd200ee"></a><!-- doxytag: member="dwc_os.h::DWC_WAITQ_FREE" ref="7b731581f7ab4db7ec2e8874bfd200ee" args="(dwc_waitq_t *wq)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void DWC_WAITQ_FREE           </td>
+          <td>(</td>
+          <td class="paramtype">dwc_waitq_t *&nbsp;</td>
+          <td class="paramname"> <em>wq</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Free a waitq. 
+<p>
+
+</div>
+</div><p>
+<a class="anchor" name="29bfbfd7ed787ea71828f3902dcaec92"></a><!-- doxytag: member="dwc_os.h::DWC_WAITQ_WAIT" ref="29bfbfd7ed787ea71828f3902dcaec92" args="(dwc_waitq_t *wq, dwc_waitq_condition_t condition, void *data)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t DWC_WAITQ_WAIT           </td>
+          <td>(</td>
+          <td class="paramtype">dwc_waitq_t *&nbsp;</td>
+          <td class="paramname"> <em>wq</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="dwc__os_8h.html#b361f6bc4eff88c0ddda059569da125f">dwc_waitq_condition_t</a>&nbsp;</td>
+          <td class="paramname"> <em>condition</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>data</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Check the condition and if it is false, block on the waitq. 
+<p>
+When unblocked, check the condition again. The function returns when the condition becomes true. The return value is 0 on condition true, DWC_WAITQ_ABORTED on abort or killed, or DWC_WAITQ_UNKNOWN on error. 
+</div>
+</div><p>
+<a class="anchor" name="56c898b4f49f0e992905e6e4be2034f0"></a><!-- doxytag: member="dwc_os.h::DWC_WAITQ_WAIT_TIMEOUT" ref="56c898b4f49f0e992905e6e4be2034f0" args="(dwc_waitq_t *wq, dwc_waitq_condition_t condition, void *data, int32_t msecs)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t DWC_WAITQ_WAIT_TIMEOUT           </td>
+          <td>(</td>
+          <td class="paramtype">dwc_waitq_t *&nbsp;</td>
+          <td class="paramname"> <em>wq</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="dwc__os_8h.html#b361f6bc4eff88c0ddda059569da125f">dwc_waitq_condition_t</a>&nbsp;</td>
+          <td class="paramname"> <em>condition</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>data</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&nbsp;</td>
+          <td class="paramname"> <em>msecs</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Check the condition and if it is false, block on the waitq. 
+<p>
+When unblocked, check the condition again. The function returns when the condition become true or the timeout has passed. The return value is 0 on condition true or DWC_TIMED_OUT on timeout, or DWC_WAITQ_ABORTED, or DWC_WAITQ_UNKNOWN on error. 
+</div>
+</div><p>
+<a class="anchor" name="7a9ddcd9fc2a6014fee4c8e162ca675a"></a><!-- doxytag: member="dwc_os.h::DWC_WAITQ_TRIGGER" ref="7a9ddcd9fc2a6014fee4c8e162ca675a" args="(dwc_waitq_t *wq)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void DWC_WAITQ_TRIGGER           </td>
+          <td>(</td>
+          <td class="paramtype">dwc_waitq_t *&nbsp;</td>
+          <td class="paramname"> <em>wq</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Trigger a waitq, unblocking all processes. 
+<p>
+This should be called whenever a condition has potentially changed. 
+</div>
+</div><p>
+<a class="anchor" name="e6010b0efd088e31791cc2eece7f4aa6"></a><!-- doxytag: member="dwc_os.h::DWC_WAITQ_ABORT" ref="e6010b0efd088e31791cc2eece7f4aa6" args="(dwc_waitq_t *wq)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void DWC_WAITQ_ABORT           </td>
+          <td>(</td>
+          <td class="paramtype">dwc_waitq_t *&nbsp;</td>
+          <td class="paramname"> <em>wq</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Unblock all processes waiting on the waitq with an ABORTED result. 
+<p>
+
+</div>
+</div><p>
+<a class="anchor" name="bd9f02558a1f945a13029eeb3db69665"></a><!-- doxytag: member="dwc_os.h::DWC_THREAD_RUN" ref="bd9f02558a1f945a13029eeb3db69665" args="(dwc_thread_function_t thread_function, char *name, void *data)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">dwc_thread_t* DWC_THREAD_RUN           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="dwc__os_8h.html#d34bdab089ddbc0e479c9fead16ca7ac">dwc_thread_function_t</a>&nbsp;</td>
+          <td class="paramname"> <em>thread_function</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">char *&nbsp;</td>
+          <td class="paramname"> <em>name</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>data</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Create a thread and start it running the thread_function. 
+<p>
+Returns a handle to the thread 
+</div>
+</div><p>
+<a class="anchor" name="b67d33899c4114d53fd6b327054ffdf4"></a><!-- doxytag: member="dwc_os.h::DWC_THREAD_STOP" ref="b67d33899c4114d53fd6b327054ffdf4" args="(dwc_thread_t *thread)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int DWC_THREAD_STOP           </td>
+          <td>(</td>
+          <td class="paramtype">dwc_thread_t *&nbsp;</td>
+          <td class="paramname"> <em>thread</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Stops a thread. 
+<p>
+Return the value returned by the thread. Or will return DWC_ABORT if the thread never started. 
+</div>
+</div><p>
+<a class="anchor" name="5e9b5e2258135bbb0612b36e798d9d70"></a><!-- doxytag: member="dwc_os.h::DWC_THREAD_SHOULD_STOP" ref="5e9b5e2258135bbb0612b36e798d9d70" args="(void)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="dwc__os_8h.html#e2374f0b1253fc63321e1b253ee61b1d">dwc_bool_t</a> DWC_THREAD_SHOULD_STOP           </td>
+          <td>(</td>
+          <td class="paramtype">void&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Signifies to the thread that it must stop. 
+<p>
+
+</div>
+</div><p>
+<a class="anchor" name="7a1f0611831c9ea4438ba6bdaf4c1e59"></a><!-- doxytag: member="dwc_os.h::DWC_WORKQ_ALLOC" ref="7a1f0611831c9ea4438ba6bdaf4c1e59" args="(char *name)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">dwc_workq_t* DWC_WORKQ_ALLOC           </td>
+          <td>(</td>
+          <td class="paramtype">char *&nbsp;</td>
+          <td class="paramname"> <em>name</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Allocate a workq. 
+<p>
+
+</div>
+</div><p>
+<a class="anchor" name="680e3852c4fb8e14e63220dab9b714d3"></a><!-- doxytag: member="dwc_os.h::DWC_WORKQ_FREE" ref="680e3852c4fb8e14e63220dab9b714d3" args="(dwc_workq_t *workq)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void DWC_WORKQ_FREE           </td>
+          <td>(</td>
+          <td class="paramtype">dwc_workq_t *&nbsp;</td>
+          <td class="paramname"> <em>workq</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Free a workq. 
+<p>
+All work must be completed before being freed. 
+</div>
+</div><p>
+<a class="anchor" name="95363f7dc5b0d38e0a3dd5cd120f8b99"></a><!-- doxytag: member="dwc_os.h::DWC_WORKQ_SCHEDULE" ref="95363f7dc5b0d38e0a3dd5cd120f8b99" args="(dwc_workq_t *workq, dwc_work_callback_t work_cb, void *data, char *format,...)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void DWC_WORKQ_SCHEDULE           </td>
+          <td>(</td>
+          <td class="paramtype">dwc_workq_t *&nbsp;</td>
+          <td class="paramname"> <em>workq</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="dwc__os_8h.html#c67973a4ac14764ed66a82103a357c06">dwc_work_callback_t</a>&nbsp;</td>
+          <td class="paramname"> <em>work_cb</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>data</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">char *&nbsp;</td>
+          <td class="paramname"> <em>format</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&nbsp;</td>
+          <td class="paramname"> <em>...</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Schedule a callback on the workq, passing in data. 
+<p>
+The function will be scheduled at some later time. 
+</div>
+</div><p>
+<a class="anchor" name="cf7ea7e0bb106fd0579f006d184e3bac"></a><!-- doxytag: member="dwc_os.h::DWC_WORKQ_SCHEDULE_DELAYED" ref="cf7ea7e0bb106fd0579f006d184e3bac" args="(dwc_workq_t *workq, dwc_work_callback_t work_cb, void *data, uint32_t time, char *format,...)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void DWC_WORKQ_SCHEDULE_DELAYED           </td>
+          <td>(</td>
+          <td class="paramtype">dwc_workq_t *&nbsp;</td>
+          <td class="paramname"> <em>workq</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="dwc__os_8h.html#c67973a4ac14764ed66a82103a357c06">dwc_work_callback_t</a>&nbsp;</td>
+          <td class="paramname"> <em>work_cb</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>data</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint32_t&nbsp;</td>
+          <td class="paramname"> <em>time</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">char *&nbsp;</td>
+          <td class="paramname"> <em>format</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&nbsp;</td>
+          <td class="paramname"> <em>...</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Schedule a callback on the workq, that will be called until at least given number miliseconds have passed. 
+<p>
+
+</div>
+</div><p>
+<a class="anchor" name="78913f99b2219b3d56b330eb435874a5"></a><!-- doxytag: member="dwc_os.h::DWC_WORKQ_PENDING" ref="78913f99b2219b3d56b330eb435874a5" args="(dwc_workq_t *workq)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int DWC_WORKQ_PENDING           </td>
+          <td>(</td>
+          <td class="paramtype">dwc_workq_t *&nbsp;</td>
+          <td class="paramname"> <em>workq</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+The number of processes in the workq. 
+<p>
+
+</div>
+</div><p>
+<a class="anchor" name="796e99dd77f1370cfcab7170a3319100"></a><!-- doxytag: member="dwc_os.h::DWC_WORKQ_WAIT_WORK_DONE" ref="796e99dd77f1370cfcab7170a3319100" args="(dwc_workq_t *workq, int timeout)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int DWC_WORKQ_WAIT_WORK_DONE           </td>
+          <td>(</td>
+          <td class="paramtype">dwc_workq_t *&nbsp;</td>
+          <td class="paramname"> <em>workq</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>timeout</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Blocks until all the work in the workq is complete or timed out. 
+<p>
+Returns &lt; 0 on timeout. 
+</div>
+</div><p>
+<a class="anchor" name="fc7f822dbb92bfe8f39d58f56424d690"></a><!-- doxytag: member="dwc_os.h::DWC_TIMER_SCHEDULE" ref="fc7f822dbb92bfe8f39d58f56424d690" args="(dwc_timer_t *timer, uint32_t time)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void DWC_TIMER_SCHEDULE           </td>
+          <td>(</td>
+          <td class="paramtype">dwc_timer_t *&nbsp;</td>
+          <td class="paramname"> <em>timer</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint32_t&nbsp;</td>
+          <td class="paramname"> <em>time</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Schedules the timer to run at time ms from now. 
+<p>
+And will repeat at every repeat_interval msec therafter<p>
+Modifies a timer that is still awaiting execution to a new expiration time. The mod_time is added to the old time. 
+</div>
+</div><p>
+<a class="anchor" name="e3b250c6df138b515ac0c14e34331c20"></a><!-- doxytag: member="dwc_os.h::DWC_TIMER_CANCEL" ref="e3b250c6df138b515ac0c14e34331c20" args="(dwc_timer_t *timer)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void DWC_TIMER_CANCEL           </td>
+          <td>(</td>
+          <td class="paramtype">dwc_timer_t *&nbsp;</td>
+          <td class="paramname"> <em>timer</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Disables the timer from execution. 
+<p>
+
+</div>
+</div><p>
+<a class="anchor" name="9835746177a3943b5042b7ee372d51b7"></a><!-- doxytag: member="dwc_os.h::DWC_SPINLOCK_ALLOC" ref="9835746177a3943b5042b7ee372d51b7" args="(void)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">dwc_spinlock_t* DWC_SPINLOCK_ALLOC           </td>
+          <td>(</td>
+          <td class="paramtype">void&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Returns an initialized lock variable. 
+<p>
+This function should allocate and initialize the OS-specific data structure used for locking. This data structure is to be used for the DWC_LOCK and DWC_UNLOCK functions and should be freed by the DWC_FREE_LOCK when it is no longer used. 
+</div>
+</div><p>
+<a class="anchor" name="d14d73128f7d826a5b5d134c5ed68ee3"></a><!-- doxytag: member="dwc_os.h::DWC_SPINLOCK_FREE" ref="d14d73128f7d826a5b5d134c5ed68ee3" args="(dwc_spinlock_t *lock)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void DWC_SPINLOCK_FREE           </td>
+          <td>(</td>
+          <td class="paramtype">dwc_spinlock_t *&nbsp;</td>
+          <td class="paramname"> <em>lock</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Frees an initialized lock variable. 
+<p>
+
+</div>
+</div><p>
+<a class="anchor" name="669a98495836ed25385ce90ce187e169"></a><!-- doxytag: member="dwc_os.h::DWC_SPINLOCK_IRQSAVE" ref="669a98495836ed25385ce90ce187e169" args="(dwc_spinlock_t *lock, uint64_t *flags)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void DWC_SPINLOCK_IRQSAVE           </td>
+          <td>(</td>
+          <td class="paramtype">dwc_spinlock_t *&nbsp;</td>
+          <td class="paramname"> <em>lock</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint64_t *&nbsp;</td>
+          <td class="paramname"> <em>flags</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Disables interrupts and blocks until it acquires the lock. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>lock</em>&nbsp;</td><td>Pointer to the spinlock. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>flags</em>&nbsp;</td><td>Unsigned long for irq flags storage. </td></tr>
+  </table>
+</dl>
+
+</div>
+</div><p>
+<a class="anchor" name="34f4a1c6a12c226efb0ced4c270ccf44"></a><!-- doxytag: member="dwc_os.h::DWC_SPINUNLOCK_IRQRESTORE" ref="34f4a1c6a12c226efb0ced4c270ccf44" args="(dwc_spinlock_t *lock, uint64_t flags)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void DWC_SPINUNLOCK_IRQRESTORE           </td>
+          <td>(</td>
+          <td class="paramtype">dwc_spinlock_t *&nbsp;</td>
+          <td class="paramname"> <em>lock</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint64_t&nbsp;</td>
+          <td class="paramname"> <em>flags</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Re-enables the interrupt and releases the lock. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>lock</em>&nbsp;</td><td>Pointer to the spinlock. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>flags</em>&nbsp;</td><td>Unsigned long for irq flags storage. Must be the same as was passed into DWC_LOCK. </td></tr>
+  </table>
+</dl>
+
+</div>
+</div><p>
+<a class="anchor" name="2403e448ef5c0f70c5c58e918090af21"></a><!-- doxytag: member="dwc_os.h::DWC_SPINLOCK" ref="2403e448ef5c0f70c5c58e918090af21" args="(dwc_spinlock_t *lock)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void DWC_SPINLOCK           </td>
+          <td>(</td>
+          <td class="paramtype">dwc_spinlock_t *&nbsp;</td>
+          <td class="paramname"> <em>lock</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Blocks until it acquires the lock. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>lock</em>&nbsp;</td><td>Pointer to the spinlock. </td></tr>
+  </table>
+</dl>
+
+</div>
+</div><p>
+<a class="anchor" name="a50b0e7e31e47fd302b37fadaa0bf925"></a><!-- doxytag: member="dwc_os.h::DWC_SPINUNLOCK" ref="a50b0e7e31e47fd302b37fadaa0bf925" args="(dwc_spinlock_t *lock)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void DWC_SPINUNLOCK           </td>
+          <td>(</td>
+          <td class="paramtype">dwc_spinlock_t *&nbsp;</td>
+          <td class="paramname"> <em>lock</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Releases the lock. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>lock</em>&nbsp;</td><td>Pointer to the spinlock. </td></tr>
+  </table>
+</dl>
+
+</div>
+</div><p>
+<a class="anchor" name="aac499623d39831c288e60d6034279c0"></a><!-- doxytag: member="dwc_os.h::DWC_MUTEX_TRYLOCK" ref="aac499623d39831c288e60d6034279c0" args="(dwc_mutex_t *mutex)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int DWC_MUTEX_TRYLOCK           </td>
+          <td>(</td>
+          <td class="paramtype">dwc_mutex_t *&nbsp;</td>
+          <td class="paramname"> <em>mutex</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Non-blocking lock returns 1 on successful lock. 
+<p>
+
+</div>
+</div><p>
+<a class="anchor" name="4346ef090ef63e6eebc943372e77c4ae"></a><!-- doxytag: member="dwc_os.h::DWC_UDELAY" ref="4346ef090ef63e6eebc943372e77c4ae" args="(uint32_t usecs)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void DWC_UDELAY           </td>
+          <td>(</td>
+          <td class="paramtype">uint32_t&nbsp;</td>
+          <td class="paramname"> <em>usecs</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Microsecond delay. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>usecs</em>&nbsp;</td><td>Microseconds to delay. </td></tr>
+  </table>
+</dl>
+
+</div>
+</div><p>
+<a class="anchor" name="82dc3d687003425801fb384311e4c608"></a><!-- doxytag: member="dwc_os.h::DWC_MDELAY" ref="82dc3d687003425801fb384311e4c608" args="(uint32_t msecs)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void DWC_MDELAY           </td>
+          <td>(</td>
+          <td class="paramtype">uint32_t&nbsp;</td>
+          <td class="paramname"> <em>msecs</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Millisecond delay. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>msecs</em>&nbsp;</td><td>Milliseconds to delay. </td></tr>
+  </table>
+</dl>
+
+</div>
+</div><p>
+<a class="anchor" name="6e9ddb27d45df5f5cfa34ed9ebb1c8d0"></a><!-- doxytag: member="dwc_os.h::DWC_MSLEEP" ref="6e9ddb27d45df5f5cfa34ed9ebb1c8d0" args="(uint32_t msecs)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void DWC_MSLEEP           </td>
+          <td>(</td>
+          <td class="paramtype">uint32_t&nbsp;</td>
+          <td class="paramname"> <em>msecs</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Non-busy waiting. 
+<p>
+Sleeps for specified number of milliseconds.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>msecs</em>&nbsp;</td><td>Milliseconds to sleep. </td></tr>
+  </table>
+</dl>
+
+</div>
+</div><p>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:50 2009 for Synopsys DWC Portability and Common Library for UWB by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_common_port/doc/html/files.html b/drivers/usb/host/dwc_common_port/doc/html/files.html
new file mode 100644
index 000000000000..da3c83bf1a05
--- /dev/null
+++ b/drivers/usb/host/dwc_common_port/doc/html/files.html
@@ -0,0 +1,34 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Synopsys DWC Portability and Common Library for UWB: File Index</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="dirs.html"><span>Directories</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li id="current"><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<h1>Synopsys DWC Portability and Common Library for UWB File List</h1>Here is a list of all documented files with brief descriptions:<table>
+  <tr><td class="indexkey"><a class="el" href="dwc__cc_8h.html">dwc_cc.h</a></td><td class="indexvalue">This file defines the Context Context library </td></tr>
+  <tr><td class="indexkey"><a class="el" href="dwc__crypto_8c.html">dwc_crypto.c</a></td><td class="indexvalue">This file contains the WUSB cryptographic routines </td></tr>
+  <tr><td class="indexkey"><a class="el" href="dwc__crypto_8h.html">dwc_crypto.h</a></td><td class="indexvalue">This file contains declarations for the WUSB Cryptographic routines as defined in the WUSB spec </td></tr>
+  <tr><td class="indexkey"><a class="el" href="dwc__dh_8h.html">dwc_dh.h</a></td><td class="indexvalue">This file defines the common functions on device and host for performing numeric association as defined in the WUSB spec </td></tr>
+  <tr><td class="indexkey"><a class="el" href="dwc__list_8h.html">dwc_list.h</a></td><td class="indexvalue">This file defines linked list operations </td></tr>
+  <tr><td class="indexkey"><a class="el" href="dwc__modpow_8h.html">dwc_modpow.h</a></td><td class="indexvalue">This file defines the module exponentiation function which is only used internally by the DWC UWB modules for calculation of PKs during numeric association </td></tr>
+  <tr><td class="indexkey"><a class="el" href="dwc__notifier_8h.html">dwc_notifier.h</a></td><td class="indexvalue">A simple implementation of the Observer pattern </td></tr>
+  <tr><td class="indexkey"><a class="el" href="dwc__os_8h.html">dwc_os.h</a></td><td class="indexvalue">DWC portability library, low level os-wrapper functions </td></tr>
+</table>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:50 2009 for Synopsys DWC Portability and Common Library for UWB by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_common_port/doc/html/globals.html b/drivers/usb/host/dwc_common_port/doc/html/globals.html
new file mode 100644
index 000000000000..1149474d792f
--- /dev/null
+++ b/drivers/usb/host/dwc_common_port/doc/html/globals.html
@@ -0,0 +1,163 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Synopsys DWC Portability and Common Library for UWB: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="dirs.html"><span>Directories</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li id="current"><a href="globals.html"><span>All</span></a></li>
+    <li><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="#index__"><span>_</span></a></li>
+    <li><a href="#index_d"><span>d</span></a></li>
+  </ul>
+</div>
+
+<p>
+Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:
+<p>
+<h3><a class="anchor" name="index__">- _ -</a></h3><ul>
+<li>__DWC_ALLOC()
+: <a class="el" href="dwc__os_8h.html#f0da81fbd5a3822ded21f74e650b6f56">dwc_os.h</a><li>__DWC_ALLOC_ATOMIC()
+: <a class="el" href="dwc__os_8h.html#ce6c64a02c1b62bdd693f827c06803e1">dwc_os.h</a><li>__DWC_DEBUG()
+: <a class="el" href="dwc__os_8h.html#24c83900d9653d50bf5874fb3b787e07">dwc_os.h</a><li>__DWC_DMA_ALLOC()
+: <a class="el" href="dwc__os_8h.html#f74ba85fa4f2dcb59886b2f3d4ef709f">dwc_os.h</a><li>__DWC_DMA_FREE()
+: <a class="el" href="dwc__os_8h.html#04a8867a0602eccf0d759206d89bde96">dwc_os.h</a><li>__DWC_ERROR()
+: <a class="el" href="dwc__os_8h.html#54dcd8d8647879b6803585f98bcc3c71">dwc_os.h</a><li>__DWC_FREE()
+: <a class="el" href="dwc__os_8h.html#578dd2d0619aab9c86e31f4828a9afe5">dwc_os.h</a><li>__DWC_WARN()
+: <a class="el" href="dwc__os_8h.html#da29736470afbdc41a0f7c7e8d9a2f0d">dwc_os.h</a></ul>
+<h3><a class="anchor" name="index_d">- d -</a></h3><ul>
+<li>dwc_add_observer()
+: <a class="el" href="dwc__notifier_8h.html#2d1c0018894e606f7b123094fc363ddb">dwc_notifier.h</a><li>DWC_AES_CBC()
+: <a class="el" href="dwc__os_8h.html#d25677e4a3299c7ae65e520015172124">dwc_os.h</a><li>dwc_alloc_notification_manager()
+: <a class="el" href="dwc__notifier_8h.html#3c217d779cc8121d911c60e33c36de5c">dwc_notifier.h</a><li>DWC_ASSERT
+: <a class="el" href="dwc__os_8h.html#1dd30b105001754e01596cfb0a01e572">dwc_os.h</a><li>dwc_assoc_is_not_zero_id()
+: <a class="el" href="dwc__cc_8h.html#f90b3442b6c53b3e89c0580e1fb20b8f">dwc_cc.h</a><li>dwc_assoc_is_zero_id()
+: <a class="el" href="dwc__cc_8h.html#8485befd69b4bfbe5e9f13b9b24acda1">dwc_cc.h</a><li>DWC_ATOI()
+: <a class="el" href="dwc__os_8h.html#d7080682441edd663b576334e307ebfe">dwc_os.h</a><li>DWC_ATOUI()
+: <a class="el" href="dwc__os_8h.html#f6a3d4b637d16e25f1f69cce51d2184e">dwc_os.h</a><li>DWC_BE16_TO_CPU()
+: <a class="el" href="dwc__os_8h.html#039677525ccd7b262a486a788523a4fa">dwc_os.h</a><li>DWC_BE32_TO_CPU()
+: <a class="el" href="dwc__os_8h.html#ac5cda361023e4b10ff059bce576d2b4">dwc_os.h</a><li>dwc_bool_t
+: <a class="el" href="dwc__os_8h.html#e2374f0b1253fc63321e1b253ee61b1d">dwc_os.h</a><li>dwc_cc_add()
+: <a class="el" href="dwc__cc_8h.html#2e04f137cbe68b5db7cdd432af50efea">dwc_cc.h</a><li>dwc_cc_cdid()
+: <a class="el" href="dwc__cc_8h.html#667f32649b4dcd8210bc54a307589162">dwc_cc.h</a><li>dwc_cc_change()
+: <a class="el" href="dwc__cc_8h.html#c0009353a8c89d81c0df4d838687136a">dwc_cc.h</a><li>dwc_cc_chid()
+: <a class="el" href="dwc__cc_8h.html#135f9661d688df3be90b57cf8fe0e171">dwc_cc.h</a><li>dwc_cc_ck()
+: <a class="el" href="dwc__cc_8h.html#07124231ec335379a59eb4c8198da119">dwc_cc.h</a><li>dwc_cc_clear()
+: <a class="el" href="dwc__cc_8h.html#ee140bfd74d33e7456bc4b2d8c23e834">dwc_cc.h</a><li>dwc_cc_data_for_save()
+: <a class="el" href="dwc__cc_8h.html#9804503a6ae17fa6650da86d94e3a11d">dwc_cc.h</a><li>dwc_cc_if_alloc()
+: <a class="el" href="dwc__cc_8h.html#bc9d8a8d9ef41b4167ff8c02d44c2d15">dwc_cc.h</a><li>dwc_cc_if_free()
+: <a class="el" href="dwc__cc_8h.html#a4f59eb28ddb889c7bf072c6291f1b52">dwc_cc.h</a><li>dwc_cc_match_cdid()
+: <a class="el" href="dwc__cc_8h.html#bae07aa2652e5fad05d5dafa81009846">dwc_cc.h</a><li>dwc_cc_match_chid()
+: <a class="el" href="dwc__cc_8h.html#97b48adfc54eb821a1d904d66fa554f1">dwc_cc.h</a><li>dwc_cc_remove()
+: <a class="el" href="dwc__cc_8h.html#3c0b5c59eebbb92cededfa36bc8508d5">dwc_cc.h</a><li>dwc_cc_restore_from_data()
+: <a class="el" href="dwc__cc_8h.html#0410780d5218fd44169bda226bfca65f">dwc_cc.h</a><li>DWC_CPU_TO_BE16()
+: <a class="el" href="dwc__os_8h.html#4b7cb22cfd1ec8f87965c9e2de43838f">dwc_os.h</a><li>DWC_CPU_TO_BE32()
+: <a class="el" href="dwc__os_8h.html#5504b62058f8a69ffa9dfd28712a9ea0">dwc_os.h</a><li>DWC_CPU_TO_LE16()
+: <a class="el" href="dwc__os_8h.html#0ee58f208f5b2ec70aed9a0133d33479">dwc_os.h</a><li>DWC_CPU_TO_LE32()
+: <a class="el" href="dwc__os_8h.html#e3f5dbab365dc4e3aab74d95fe26c654">dwc_os.h</a><li>DWC_DEBUG
+: <a class="el" href="dwc__os_8h.html#c91431cc824741def21c86e778361e6b">dwc_os.h</a><li>dwc_dh_derive_keys()
+: <a class="el" href="dwc__dh_8h.html#bfd81fd7b9a75f027d2bbcdc97e77e83">dwc_dh.h</a><li>dwc_dh_pk()
+: <a class="el" href="dwc__dh_8h.html#15463b3a65cead222814d0d5cce294cf">dwc_dh.h</a><li>DWC_ERROR
+: <a class="el" href="dwc__os_8h.html#7f87f33fab81a2ad602599e16db8b067">dwc_os.h</a><li>DWC_EXCEPTION()
+: <a class="el" href="dwc__os_8h.html#96ee4cab04e3ec11f47beedaea6fe752">dwc_os.h</a><li>dwc_free_notification_manager()
+: <a class="el" href="dwc__notifier_8h.html#dc9553444a56bfc595be08592af6dee4">dwc_notifier.h</a><li>DWC_HMAC_SHA256()
+: <a class="el" href="dwc__os_8h.html#b312283cc1cec404b8753eb0a3d9d051">dwc_os.h</a><li>DWC_IN_IRQ()
+: <a class="el" href="dwc__os_8h.html#830b5c18c8b32f36ef5948df9b310959">dwc_os.h</a><li>DWC_INFO
+: <a class="el" href="dwc__os_8h.html#f30c815ec9d3d710a4c0ccb993a84d86">dwc_os.h</a><li>dwc_irq()
+: <a class="el" href="dwc__os_8h.html#9df340bcf2f004c69b9d917724e22955">dwc_os.h</a><li>DWC_LE16_TO_CPU()
+: <a class="el" href="dwc__os_8h.html#157b0438d386b5529abcc54c886b7ddc">dwc_os.h</a><li>DWC_LE32_TO_CPU()
+: <a class="el" href="dwc__os_8h.html#7e6e45719874b966f5eead1079dce589">dwc_os.h</a><li>DWC_MDELAY()
+: <a class="el" href="dwc__os_8h.html#82dc3d687003425801fb384311e4c608">dwc_os.h</a><li>DWC_MEMCMP()
+: <a class="el" href="dwc__os_8h.html#7a80d4bef3bc0f3d6297400b3858b80e">dwc_os.h</a><li>DWC_MEMCPY()
+: <a class="el" href="dwc__os_8h.html#37c1b18d623367a7ca438e4d2a698ed5">dwc_os.h</a><li>DWC_MEMMOVE()
+: <a class="el" href="dwc__os_8h.html#2bc77081fca508dab31a245d0dd214d9">dwc_os.h</a><li>DWC_MEMSET()
+: <a class="el" href="dwc__os_8h.html#d14e248de8bd334f6065bb9c09305a65">dwc_os.h</a><li>DWC_MODIFY_REG32()
+: <a class="el" href="dwc__os_8h.html#a0be0db1cab4dcc65c7d508b15e5d209">dwc_os.h</a><li>DWC_MSLEEP()
+: <a class="el" href="dwc__os_8h.html#6e9ddb27d45df5f5cfa34ed9ebb1c8d0">dwc_os.h</a><li>DWC_MUTEX_TRYLOCK()
+: <a class="el" href="dwc__os_8h.html#aac499623d39831c288e60d6034279c0">dwc_os.h</a><li>dwc_notifier_callback_t
+: <a class="el" href="dwc__notifier_8h.html#a8a84ad74a90bea39597283487b9cbfb">dwc_notifier.h</a><li>dwc_notify()
+: <a class="el" href="dwc__notifier_8h.html#58997c4e097d7c148312b3e0b84915f3">dwc_notifier.h</a><li>dwc_print_id_string()
+: <a class="el" href="dwc__cc_8h.html#46be9c2781971918e4f7d0e19699fe9d">dwc_cc.h</a><li>DWC_PRINTF()
+: <a class="el" href="dwc__os_8h.html#ff25ba1e8c8760561e74df4faa45a3c7">dwc_os.h</a><li>DWC_RANDOM_BYTES()
+: <a class="el" href="dwc__os_8h.html#3e85fc1609d2791628e718c284f3a37f">dwc_os.h</a><li>DWC_READ_REG32()
+: <a class="el" href="dwc__os_8h.html#998a1b27461c926d8c19de202f0e05ca">dwc_os.h</a><li>DWC_READ_REG64()
+: <a class="el" href="dwc__os_8h.html#04a809b4ec80265acf393a6d2bff8916">dwc_os.h</a><li>dwc_register_notifier()
+: <a class="el" href="dwc__notifier_8h.html#40c4a4ad1f3466a135f708be3929a548">dwc_notifier.h</a><li>dwc_remove_observer()
+: <a class="el" href="dwc__notifier_8h.html#0bb13b5ac4ae9a31c458b4bb03585c96">dwc_notifier.h</a><li>DWC_SHA256()
+: <a class="el" href="dwc__os_8h.html#30bc2a37980e41bea58057131229d543">dwc_os.h</a><li>DWC_SNPRINTF()
+: <a class="el" href="dwc__os_8h.html#f9d4dbc0799ef36f89e78eea0a60b563">dwc_os.h</a><li>DWC_SPINLOCK()
+: <a class="el" href="dwc__os_8h.html#2403e448ef5c0f70c5c58e918090af21">dwc_os.h</a><li>DWC_SPINLOCK_ALLOC()
+: <a class="el" href="dwc__os_8h.html#9835746177a3943b5042b7ee372d51b7">dwc_os.h</a><li>DWC_SPINLOCK_FREE()
+: <a class="el" href="dwc__os_8h.html#d14d73128f7d826a5b5d134c5ed68ee3">dwc_os.h</a><li>DWC_SPINLOCK_IRQSAVE()
+: <a class="el" href="dwc__os_8h.html#669a98495836ed25385ce90ce187e169">dwc_os.h</a><li>DWC_SPINUNLOCK()
+: <a class="el" href="dwc__os_8h.html#a50b0e7e31e47fd302b37fadaa0bf925">dwc_os.h</a><li>DWC_SPINUNLOCK_IRQRESTORE()
+: <a class="el" href="dwc__os_8h.html#34f4a1c6a12c226efb0ced4c270ccf44">dwc_os.h</a><li>DWC_SPRINTF()
+: <a class="el" href="dwc__os_8h.html#6bc72ec00a8247404cda1ad5fa88fb86">dwc_os.h</a><li>DWC_STRCMP()
+: <a class="el" href="dwc__os_8h.html#3f175e77ff50e30a9444d377bf16cb07">dwc_os.h</a><li>DWC_STRCPY()
+: <a class="el" href="dwc__os_8h.html#8c89eecb8b1b4c4330aac7ecc54f5be4">dwc_os.h</a><li>DWC_STRDUP()
+: <a class="el" href="dwc__os_8h.html#d4b956a8a4bea03a73b1ca2bafe94231">dwc_os.h</a><li>DWC_STRLEN()
+: <a class="el" href="dwc__os_8h.html#4605aef85763dd32580d13a462ad9add">dwc_os.h</a><li>DWC_STRNCMP()
+: <a class="el" href="dwc__os_8h.html#5692e7d364b935378e15a8f6a5b45afb">dwc_os.h</a><li>dwc_thread_function_t
+: <a class="el" href="dwc__os_8h.html#d34bdab089ddbc0e479c9fead16ca7ac">dwc_os.h</a><li>DWC_THREAD_RUN()
+: <a class="el" href="dwc__os_8h.html#bd9f02558a1f945a13029eeb3db69665">dwc_os.h</a><li>DWC_THREAD_SHOULD_STOP()
+: <a class="el" href="dwc__os_8h.html#5e9b5e2258135bbb0612b36e798d9d70">dwc_os.h</a><li>DWC_THREAD_STOP()
+: <a class="el" href="dwc__os_8h.html#b67d33899c4114d53fd6b327054ffdf4">dwc_os.h</a><li>DWC_TIMER_CANCEL()
+: <a class="el" href="dwc__os_8h.html#e3b250c6df138b515ac0c14e34331c20">dwc_os.h</a><li>DWC_TIMER_SCHEDULE()
+: <a class="el" href="dwc__os_8h.html#fc7f822dbb92bfe8f39d58f56424d690">dwc_os.h</a><li>DWC_UDELAY()
+: <a class="el" href="dwc__os_8h.html#4346ef090ef63e6eebc943372e77c4ae">dwc_os.h</a><li>dwc_unregister_notifier()
+: <a class="el" href="dwc__notifier_8h.html#0b607aa63fc2ab69baffad75b9fa37f4">dwc_notifier.h</a><li>DWC_UTF8_TO_UTF16LE()
+: <a class="el" href="dwc__os_8h.html#0e7deede6fcd5a48347fb1714259375b">dwc_os.h</a><li>DWC_VPRINTF()
+: <a class="el" href="dwc__os_8h.html#dedf4a24c1af865c0a73b685a807383d">dwc_os.h</a><li>DWC_VSNPRINTF()
+: <a class="el" href="dwc__os_8h.html#8fdc0abfec4f97c78b59cece02718f35">dwc_os.h</a><li>DWC_WAITQ_ABORT()
+: <a class="el" href="dwc__os_8h.html#e6010b0efd088e31791cc2eece7f4aa6">dwc_os.h</a><li>DWC_WAITQ_ALLOC()
+: <a class="el" href="dwc__os_8h.html#4c5d74e3fd7f8f32b3129ce47e8d5c0c">dwc_os.h</a><li>dwc_waitq_condition_t
+: <a class="el" href="dwc__os_8h.html#b361f6bc4eff88c0ddda059569da125f">dwc_os.h</a><li>DWC_WAITQ_FREE()
+: <a class="el" href="dwc__os_8h.html#7b731581f7ab4db7ec2e8874bfd200ee">dwc_os.h</a><li>DWC_WAITQ_TRIGGER()
+: <a class="el" href="dwc__os_8h.html#7a9ddcd9fc2a6014fee4c8e162ca675a">dwc_os.h</a><li>DWC_WAITQ_WAIT()
+: <a class="el" href="dwc__os_8h.html#29bfbfd7ed787ea71828f3902dcaec92">dwc_os.h</a><li>DWC_WAITQ_WAIT_TIMEOUT()
+: <a class="el" href="dwc__os_8h.html#56c898b4f49f0e992905e6e4be2034f0">dwc_os.h</a><li>DWC_WARN
+: <a class="el" href="dwc__os_8h.html#d475a8dc748be355af32ad01de0c257a">dwc_os.h</a><li>dwc_work_callback_t
+: <a class="el" href="dwc__os_8h.html#c67973a4ac14764ed66a82103a357c06">dwc_os.h</a><li>DWC_WORKQ_ALLOC()
+: <a class="el" href="dwc__os_8h.html#7a1f0611831c9ea4438ba6bdaf4c1e59">dwc_os.h</a><li>DWC_WORKQ_FREE()
+: <a class="el" href="dwc__os_8h.html#680e3852c4fb8e14e63220dab9b714d3">dwc_os.h</a><li>DWC_WORKQ_PENDING()
+: <a class="el" href="dwc__os_8h.html#78913f99b2219b3d56b330eb435874a5">dwc_os.h</a><li>DWC_WORKQ_SCHEDULE()
+: <a class="el" href="dwc__os_8h.html#95363f7dc5b0d38e0a3dd5cd120f8b99">dwc_os.h</a><li>DWC_WORKQ_SCHEDULE_DELAYED()
+: <a class="el" href="dwc__os_8h.html#cf7ea7e0bb106fd0579f006d184e3bac">dwc_os.h</a><li>DWC_WORKQ_WAIT_WORK_DONE()
+: <a class="el" href="dwc__os_8h.html#796e99dd77f1370cfcab7170a3319100">dwc_os.h</a><li>DWC_WRITE_REG32()
+: <a class="el" href="dwc__os_8h.html#9166df012531473304420325a61302cf">dwc_os.h</a><li>DWC_WRITE_REG64()
+: <a class="el" href="dwc__os_8h.html#59ef876d933b94b75a659c1614946496">dwc_os.h</a><li>dwc_wusb_aes_encrypt()
+: <a class="el" href="dwc__crypto_8h.html#b4591bca19d2bfc173d3f38d8a0f04e7">dwc_crypto.h</a>, <a class="el" href="dwc__crypto_8c.html#b4591bca19d2bfc173d3f38d8a0f04e7">dwc_crypto.c</a><li>dwc_wusb_cmf()
+: <a class="el" href="dwc__crypto_8h.html#ebd0a4f3d48e8a5131125b080d402389">dwc_crypto.h</a>, <a class="el" href="dwc__crypto_8c.html#ebd0a4f3d48e8a5131125b080d402389">dwc_crypto.c</a><li>dwc_wusb_fill_ccm_nonce()
+: <a class="el" href="dwc__crypto_8h.html#74ae8ea78ee10c708d7c3e0c12665b0d">dwc_crypto.h</a>, <a class="el" href="dwc__crypto_8c.html#74ae8ea78ee10c708d7c3e0c12665b0d">dwc_crypto.c</a><li>dwc_wusb_gen_key()
+: <a class="el" href="dwc__crypto_8h.html#18f5b99bd27d2397550fbd340d39600a">dwc_crypto.h</a>, <a class="el" href="dwc__crypto_8c.html#18f5b99bd27d2397550fbd340d39600a">dwc_crypto.c</a><li>dwc_wusb_gen_mic()
+: <a class="el" href="dwc__crypto_8h.html#ab0a16ae4126032ca99e1fbcaaa7c248">dwc_crypto.h</a>, <a class="el" href="dwc__crypto_8c.html#ab0a16ae4126032ca99e1fbcaaa7c248">dwc_crypto.c</a><li>dwc_wusb_gen_nonce()
+: <a class="el" href="dwc__crypto_8h.html#79af51f4e6140e5a251041879b40ad03">dwc_crypto.h</a>, <a class="el" href="dwc__crypto_8c.html#79af51f4e6140e5a251041879b40ad03">dwc_crypto.c</a><li>dwc_wusb_prf()
+: <a class="el" href="dwc__crypto_8h.html#a44578803c21449b5d98e6275e4a6f5f">dwc_crypto.h</a>, <a class="el" href="dwc__crypto_8c.html#a44578803c21449b5d98e6275e4a6f5f">dwc_crypto.c</a><li>dwc_wusb_prf_128()
+: <a class="el" href="dwc__crypto_8h.html#a391ec8ab9719b8e6c0a97595a1379d9">dwc_crypto.h</a><li>dwc_wusb_prf_256()
+: <a class="el" href="dwc__crypto_8h.html#2f6fedbb1295662ebf8e65eecb1630c8">dwc_crypto.h</a><li>dwc_wusb_prf_64()
+: <a class="el" href="dwc__crypto_8h.html#d205747d6fb9d87d3c243c2d270ec9d5">dwc_crypto.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:50 2009 for Synopsys DWC Portability and Common Library for UWB by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_common_port/doc/html/globals_defs.html b/drivers/usb/host/dwc_common_port/doc/html/globals_defs.html
new file mode 100644
index 000000000000..c7dea18895fd
--- /dev/null
+++ b/drivers/usb/host/dwc_common_port/doc/html/globals_defs.html
@@ -0,0 +1,41 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Synopsys DWC Portability and Common Library for UWB: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="dirs.html"><span>Directories</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html"><span>All</span></a></li>
+    <li><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li id="current"><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+&nbsp;
+<p>
+<ul>
+<li>DWC_ASSERT
+: <a class="el" href="dwc__os_8h.html#1dd30b105001754e01596cfb0a01e572">dwc_os.h</a><li>DWC_DEBUG
+: <a class="el" href="dwc__os_8h.html#c91431cc824741def21c86e778361e6b">dwc_os.h</a><li>DWC_ERROR
+: <a class="el" href="dwc__os_8h.html#7f87f33fab81a2ad602599e16db8b067">dwc_os.h</a><li>DWC_INFO
+: <a class="el" href="dwc__os_8h.html#f30c815ec9d3d710a4c0ccb993a84d86">dwc_os.h</a><li>DWC_WARN
+: <a class="el" href="dwc__os_8h.html#d475a8dc748be355af32ad01de0c257a">dwc_os.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:50 2009 for Synopsys DWC Portability and Common Library for UWB by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_common_port/doc/html/globals_func.html b/drivers/usb/host/dwc_common_port/doc/html/globals_func.html
new file mode 100644
index 000000000000..ee875e83a22b
--- /dev/null
+++ b/drivers/usb/host/dwc_common_port/doc/html/globals_func.html
@@ -0,0 +1,153 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Synopsys DWC Portability and Common Library for UWB: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="dirs.html"><span>Directories</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html"><span>All</span></a></li>
+    <li id="current"><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="#index__"><span>_</span></a></li>
+    <li><a href="#index_d"><span>d</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index__">- _ -</a></h3><ul>
+<li>__DWC_ALLOC()
+: <a class="el" href="dwc__os_8h.html#f0da81fbd5a3822ded21f74e650b6f56">dwc_os.h</a><li>__DWC_ALLOC_ATOMIC()
+: <a class="el" href="dwc__os_8h.html#ce6c64a02c1b62bdd693f827c06803e1">dwc_os.h</a><li>__DWC_DEBUG()
+: <a class="el" href="dwc__os_8h.html#24c83900d9653d50bf5874fb3b787e07">dwc_os.h</a><li>__DWC_DMA_ALLOC()
+: <a class="el" href="dwc__os_8h.html#f74ba85fa4f2dcb59886b2f3d4ef709f">dwc_os.h</a><li>__DWC_DMA_FREE()
+: <a class="el" href="dwc__os_8h.html#04a8867a0602eccf0d759206d89bde96">dwc_os.h</a><li>__DWC_ERROR()
+: <a class="el" href="dwc__os_8h.html#54dcd8d8647879b6803585f98bcc3c71">dwc_os.h</a><li>__DWC_FREE()
+: <a class="el" href="dwc__os_8h.html#578dd2d0619aab9c86e31f4828a9afe5">dwc_os.h</a><li>__DWC_WARN()
+: <a class="el" href="dwc__os_8h.html#da29736470afbdc41a0f7c7e8d9a2f0d">dwc_os.h</a></ul>
+<h3><a class="anchor" name="index_d">- d -</a></h3><ul>
+<li>dwc_add_observer()
+: <a class="el" href="dwc__notifier_8h.html#2d1c0018894e606f7b123094fc363ddb">dwc_notifier.h</a><li>DWC_AES_CBC()
+: <a class="el" href="dwc__os_8h.html#d25677e4a3299c7ae65e520015172124">dwc_os.h</a><li>dwc_alloc_notification_manager()
+: <a class="el" href="dwc__notifier_8h.html#3c217d779cc8121d911c60e33c36de5c">dwc_notifier.h</a><li>dwc_assoc_is_not_zero_id()
+: <a class="el" href="dwc__cc_8h.html#f90b3442b6c53b3e89c0580e1fb20b8f">dwc_cc.h</a><li>dwc_assoc_is_zero_id()
+: <a class="el" href="dwc__cc_8h.html#8485befd69b4bfbe5e9f13b9b24acda1">dwc_cc.h</a><li>DWC_ATOI()
+: <a class="el" href="dwc__os_8h.html#d7080682441edd663b576334e307ebfe">dwc_os.h</a><li>DWC_ATOUI()
+: <a class="el" href="dwc__os_8h.html#f6a3d4b637d16e25f1f69cce51d2184e">dwc_os.h</a><li>DWC_BE16_TO_CPU()
+: <a class="el" href="dwc__os_8h.html#039677525ccd7b262a486a788523a4fa">dwc_os.h</a><li>DWC_BE32_TO_CPU()
+: <a class="el" href="dwc__os_8h.html#ac5cda361023e4b10ff059bce576d2b4">dwc_os.h</a><li>dwc_cc_add()
+: <a class="el" href="dwc__cc_8h.html#2e04f137cbe68b5db7cdd432af50efea">dwc_cc.h</a><li>dwc_cc_cdid()
+: <a class="el" href="dwc__cc_8h.html#667f32649b4dcd8210bc54a307589162">dwc_cc.h</a><li>dwc_cc_change()
+: <a class="el" href="dwc__cc_8h.html#c0009353a8c89d81c0df4d838687136a">dwc_cc.h</a><li>dwc_cc_chid()
+: <a class="el" href="dwc__cc_8h.html#135f9661d688df3be90b57cf8fe0e171">dwc_cc.h</a><li>dwc_cc_ck()
+: <a class="el" href="dwc__cc_8h.html#07124231ec335379a59eb4c8198da119">dwc_cc.h</a><li>dwc_cc_clear()
+: <a class="el" href="dwc__cc_8h.html#ee140bfd74d33e7456bc4b2d8c23e834">dwc_cc.h</a><li>dwc_cc_data_for_save()
+: <a class="el" href="dwc__cc_8h.html#9804503a6ae17fa6650da86d94e3a11d">dwc_cc.h</a><li>dwc_cc_if_alloc()
+: <a class="el" href="dwc__cc_8h.html#bc9d8a8d9ef41b4167ff8c02d44c2d15">dwc_cc.h</a><li>dwc_cc_if_free()
+: <a class="el" href="dwc__cc_8h.html#a4f59eb28ddb889c7bf072c6291f1b52">dwc_cc.h</a><li>dwc_cc_match_cdid()
+: <a class="el" href="dwc__cc_8h.html#bae07aa2652e5fad05d5dafa81009846">dwc_cc.h</a><li>dwc_cc_match_chid()
+: <a class="el" href="dwc__cc_8h.html#97b48adfc54eb821a1d904d66fa554f1">dwc_cc.h</a><li>dwc_cc_remove()
+: <a class="el" href="dwc__cc_8h.html#3c0b5c59eebbb92cededfa36bc8508d5">dwc_cc.h</a><li>dwc_cc_restore_from_data()
+: <a class="el" href="dwc__cc_8h.html#0410780d5218fd44169bda226bfca65f">dwc_cc.h</a><li>DWC_CPU_TO_BE16()
+: <a class="el" href="dwc__os_8h.html#4b7cb22cfd1ec8f87965c9e2de43838f">dwc_os.h</a><li>DWC_CPU_TO_BE32()
+: <a class="el" href="dwc__os_8h.html#5504b62058f8a69ffa9dfd28712a9ea0">dwc_os.h</a><li>DWC_CPU_TO_LE16()
+: <a class="el" href="dwc__os_8h.html#0ee58f208f5b2ec70aed9a0133d33479">dwc_os.h</a><li>DWC_CPU_TO_LE32()
+: <a class="el" href="dwc__os_8h.html#e3f5dbab365dc4e3aab74d95fe26c654">dwc_os.h</a><li>dwc_dh_derive_keys()
+: <a class="el" href="dwc__dh_8h.html#bfd81fd7b9a75f027d2bbcdc97e77e83">dwc_dh.h</a><li>dwc_dh_pk()
+: <a class="el" href="dwc__dh_8h.html#15463b3a65cead222814d0d5cce294cf">dwc_dh.h</a><li>DWC_EXCEPTION()
+: <a class="el" href="dwc__os_8h.html#96ee4cab04e3ec11f47beedaea6fe752">dwc_os.h</a><li>dwc_free_notification_manager()
+: <a class="el" href="dwc__notifier_8h.html#dc9553444a56bfc595be08592af6dee4">dwc_notifier.h</a><li>DWC_HMAC_SHA256()
+: <a class="el" href="dwc__os_8h.html#b312283cc1cec404b8753eb0a3d9d051">dwc_os.h</a><li>DWC_IN_IRQ()
+: <a class="el" href="dwc__os_8h.html#830b5c18c8b32f36ef5948df9b310959">dwc_os.h</a><li>dwc_irq()
+: <a class="el" href="dwc__os_8h.html#9df340bcf2f004c69b9d917724e22955">dwc_os.h</a><li>DWC_LE16_TO_CPU()
+: <a class="el" href="dwc__os_8h.html#157b0438d386b5529abcc54c886b7ddc">dwc_os.h</a><li>DWC_LE32_TO_CPU()
+: <a class="el" href="dwc__os_8h.html#7e6e45719874b966f5eead1079dce589">dwc_os.h</a><li>DWC_MDELAY()
+: <a class="el" href="dwc__os_8h.html#82dc3d687003425801fb384311e4c608">dwc_os.h</a><li>DWC_MEMCMP()
+: <a class="el" href="dwc__os_8h.html#7a80d4bef3bc0f3d6297400b3858b80e">dwc_os.h</a><li>DWC_MEMCPY()
+: <a class="el" href="dwc__os_8h.html#37c1b18d623367a7ca438e4d2a698ed5">dwc_os.h</a><li>DWC_MEMMOVE()
+: <a class="el" href="dwc__os_8h.html#2bc77081fca508dab31a245d0dd214d9">dwc_os.h</a><li>DWC_MEMSET()
+: <a class="el" href="dwc__os_8h.html#d14e248de8bd334f6065bb9c09305a65">dwc_os.h</a><li>DWC_MODIFY_REG32()
+: <a class="el" href="dwc__os_8h.html#a0be0db1cab4dcc65c7d508b15e5d209">dwc_os.h</a><li>DWC_MSLEEP()
+: <a class="el" href="dwc__os_8h.html#6e9ddb27d45df5f5cfa34ed9ebb1c8d0">dwc_os.h</a><li>DWC_MUTEX_TRYLOCK()
+: <a class="el" href="dwc__os_8h.html#aac499623d39831c288e60d6034279c0">dwc_os.h</a><li>dwc_notify()
+: <a class="el" href="dwc__notifier_8h.html#58997c4e097d7c148312b3e0b84915f3">dwc_notifier.h</a><li>dwc_print_id_string()
+: <a class="el" href="dwc__cc_8h.html#46be9c2781971918e4f7d0e19699fe9d">dwc_cc.h</a><li>DWC_PRINTF()
+: <a class="el" href="dwc__os_8h.html#ff25ba1e8c8760561e74df4faa45a3c7">dwc_os.h</a><li>DWC_RANDOM_BYTES()
+: <a class="el" href="dwc__os_8h.html#3e85fc1609d2791628e718c284f3a37f">dwc_os.h</a><li>DWC_READ_REG32()
+: <a class="el" href="dwc__os_8h.html#998a1b27461c926d8c19de202f0e05ca">dwc_os.h</a><li>DWC_READ_REG64()
+: <a class="el" href="dwc__os_8h.html#04a809b4ec80265acf393a6d2bff8916">dwc_os.h</a><li>dwc_register_notifier()
+: <a class="el" href="dwc__notifier_8h.html#40c4a4ad1f3466a135f708be3929a548">dwc_notifier.h</a><li>dwc_remove_observer()
+: <a class="el" href="dwc__notifier_8h.html#0bb13b5ac4ae9a31c458b4bb03585c96">dwc_notifier.h</a><li>DWC_SHA256()
+: <a class="el" href="dwc__os_8h.html#30bc2a37980e41bea58057131229d543">dwc_os.h</a><li>DWC_SNPRINTF()
+: <a class="el" href="dwc__os_8h.html#f9d4dbc0799ef36f89e78eea0a60b563">dwc_os.h</a><li>DWC_SPINLOCK()
+: <a class="el" href="dwc__os_8h.html#2403e448ef5c0f70c5c58e918090af21">dwc_os.h</a><li>DWC_SPINLOCK_ALLOC()
+: <a class="el" href="dwc__os_8h.html#9835746177a3943b5042b7ee372d51b7">dwc_os.h</a><li>DWC_SPINLOCK_FREE()
+: <a class="el" href="dwc__os_8h.html#d14d73128f7d826a5b5d134c5ed68ee3">dwc_os.h</a><li>DWC_SPINLOCK_IRQSAVE()
+: <a class="el" href="dwc__os_8h.html#669a98495836ed25385ce90ce187e169">dwc_os.h</a><li>DWC_SPINUNLOCK()
+: <a class="el" href="dwc__os_8h.html#a50b0e7e31e47fd302b37fadaa0bf925">dwc_os.h</a><li>DWC_SPINUNLOCK_IRQRESTORE()
+: <a class="el" href="dwc__os_8h.html#34f4a1c6a12c226efb0ced4c270ccf44">dwc_os.h</a><li>DWC_SPRINTF()
+: <a class="el" href="dwc__os_8h.html#6bc72ec00a8247404cda1ad5fa88fb86">dwc_os.h</a><li>DWC_STRCMP()
+: <a class="el" href="dwc__os_8h.html#3f175e77ff50e30a9444d377bf16cb07">dwc_os.h</a><li>DWC_STRCPY()
+: <a class="el" href="dwc__os_8h.html#8c89eecb8b1b4c4330aac7ecc54f5be4">dwc_os.h</a><li>DWC_STRDUP()
+: <a class="el" href="dwc__os_8h.html#d4b956a8a4bea03a73b1ca2bafe94231">dwc_os.h</a><li>DWC_STRLEN()
+: <a class="el" href="dwc__os_8h.html#4605aef85763dd32580d13a462ad9add">dwc_os.h</a><li>DWC_STRNCMP()
+: <a class="el" href="dwc__os_8h.html#5692e7d364b935378e15a8f6a5b45afb">dwc_os.h</a><li>DWC_THREAD_RUN()
+: <a class="el" href="dwc__os_8h.html#bd9f02558a1f945a13029eeb3db69665">dwc_os.h</a><li>DWC_THREAD_SHOULD_STOP()
+: <a class="el" href="dwc__os_8h.html#5e9b5e2258135bbb0612b36e798d9d70">dwc_os.h</a><li>DWC_THREAD_STOP()
+: <a class="el" href="dwc__os_8h.html#b67d33899c4114d53fd6b327054ffdf4">dwc_os.h</a><li>DWC_TIMER_CANCEL()
+: <a class="el" href="dwc__os_8h.html#e3b250c6df138b515ac0c14e34331c20">dwc_os.h</a><li>DWC_TIMER_SCHEDULE()
+: <a class="el" href="dwc__os_8h.html#fc7f822dbb92bfe8f39d58f56424d690">dwc_os.h</a><li>DWC_UDELAY()
+: <a class="el" href="dwc__os_8h.html#4346ef090ef63e6eebc943372e77c4ae">dwc_os.h</a><li>dwc_unregister_notifier()
+: <a class="el" href="dwc__notifier_8h.html#0b607aa63fc2ab69baffad75b9fa37f4">dwc_notifier.h</a><li>DWC_UTF8_TO_UTF16LE()
+: <a class="el" href="dwc__os_8h.html#0e7deede6fcd5a48347fb1714259375b">dwc_os.h</a><li>DWC_VPRINTF()
+: <a class="el" href="dwc__os_8h.html#dedf4a24c1af865c0a73b685a807383d">dwc_os.h</a><li>DWC_VSNPRINTF()
+: <a class="el" href="dwc__os_8h.html#8fdc0abfec4f97c78b59cece02718f35">dwc_os.h</a><li>DWC_WAITQ_ABORT()
+: <a class="el" href="dwc__os_8h.html#e6010b0efd088e31791cc2eece7f4aa6">dwc_os.h</a><li>DWC_WAITQ_ALLOC()
+: <a class="el" href="dwc__os_8h.html#4c5d74e3fd7f8f32b3129ce47e8d5c0c">dwc_os.h</a><li>DWC_WAITQ_FREE()
+: <a class="el" href="dwc__os_8h.html#7b731581f7ab4db7ec2e8874bfd200ee">dwc_os.h</a><li>DWC_WAITQ_TRIGGER()
+: <a class="el" href="dwc__os_8h.html#7a9ddcd9fc2a6014fee4c8e162ca675a">dwc_os.h</a><li>DWC_WAITQ_WAIT()
+: <a class="el" href="dwc__os_8h.html#29bfbfd7ed787ea71828f3902dcaec92">dwc_os.h</a><li>DWC_WAITQ_WAIT_TIMEOUT()
+: <a class="el" href="dwc__os_8h.html#56c898b4f49f0e992905e6e4be2034f0">dwc_os.h</a><li>DWC_WORKQ_ALLOC()
+: <a class="el" href="dwc__os_8h.html#7a1f0611831c9ea4438ba6bdaf4c1e59">dwc_os.h</a><li>DWC_WORKQ_FREE()
+: <a class="el" href="dwc__os_8h.html#680e3852c4fb8e14e63220dab9b714d3">dwc_os.h</a><li>DWC_WORKQ_PENDING()
+: <a class="el" href="dwc__os_8h.html#78913f99b2219b3d56b330eb435874a5">dwc_os.h</a><li>DWC_WORKQ_SCHEDULE()
+: <a class="el" href="dwc__os_8h.html#95363f7dc5b0d38e0a3dd5cd120f8b99">dwc_os.h</a><li>DWC_WORKQ_SCHEDULE_DELAYED()
+: <a class="el" href="dwc__os_8h.html#cf7ea7e0bb106fd0579f006d184e3bac">dwc_os.h</a><li>DWC_WORKQ_WAIT_WORK_DONE()
+: <a class="el" href="dwc__os_8h.html#796e99dd77f1370cfcab7170a3319100">dwc_os.h</a><li>DWC_WRITE_REG32()
+: <a class="el" href="dwc__os_8h.html#9166df012531473304420325a61302cf">dwc_os.h</a><li>DWC_WRITE_REG64()
+: <a class="el" href="dwc__os_8h.html#59ef876d933b94b75a659c1614946496">dwc_os.h</a><li>dwc_wusb_aes_encrypt()
+: <a class="el" href="dwc__crypto_8h.html#b4591bca19d2bfc173d3f38d8a0f04e7">dwc_crypto.h</a>, <a class="el" href="dwc__crypto_8c.html#b4591bca19d2bfc173d3f38d8a0f04e7">dwc_crypto.c</a><li>dwc_wusb_cmf()
+: <a class="el" href="dwc__crypto_8h.html#ebd0a4f3d48e8a5131125b080d402389">dwc_crypto.h</a>, <a class="el" href="dwc__crypto_8c.html#ebd0a4f3d48e8a5131125b080d402389">dwc_crypto.c</a><li>dwc_wusb_fill_ccm_nonce()
+: <a class="el" href="dwc__crypto_8h.html#74ae8ea78ee10c708d7c3e0c12665b0d">dwc_crypto.h</a>, <a class="el" href="dwc__crypto_8c.html#74ae8ea78ee10c708d7c3e0c12665b0d">dwc_crypto.c</a><li>dwc_wusb_gen_key()
+: <a class="el" href="dwc__crypto_8h.html#18f5b99bd27d2397550fbd340d39600a">dwc_crypto.h</a>, <a class="el" href="dwc__crypto_8c.html#18f5b99bd27d2397550fbd340d39600a">dwc_crypto.c</a><li>dwc_wusb_gen_mic()
+: <a class="el" href="dwc__crypto_8h.html#ab0a16ae4126032ca99e1fbcaaa7c248">dwc_crypto.h</a>, <a class="el" href="dwc__crypto_8c.html#ab0a16ae4126032ca99e1fbcaaa7c248">dwc_crypto.c</a><li>dwc_wusb_gen_nonce()
+: <a class="el" href="dwc__crypto_8h.html#79af51f4e6140e5a251041879b40ad03">dwc_crypto.h</a>, <a class="el" href="dwc__crypto_8c.html#79af51f4e6140e5a251041879b40ad03">dwc_crypto.c</a><li>dwc_wusb_prf()
+: <a class="el" href="dwc__crypto_8h.html#a44578803c21449b5d98e6275e4a6f5f">dwc_crypto.h</a>, <a class="el" href="dwc__crypto_8c.html#a44578803c21449b5d98e6275e4a6f5f">dwc_crypto.c</a><li>dwc_wusb_prf_128()
+: <a class="el" href="dwc__crypto_8h.html#a391ec8ab9719b8e6c0a97595a1379d9">dwc_crypto.h</a><li>dwc_wusb_prf_256()
+: <a class="el" href="dwc__crypto_8h.html#2f6fedbb1295662ebf8e65eecb1630c8">dwc_crypto.h</a><li>dwc_wusb_prf_64()
+: <a class="el" href="dwc__crypto_8h.html#d205747d6fb9d87d3c243c2d270ec9d5">dwc_crypto.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:50 2009 for Synopsys DWC Portability and Common Library for UWB by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_common_port/doc/html/globals_type.html b/drivers/usb/host/dwc_common_port/doc/html/globals_type.html
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+++ b/drivers/usb/host/dwc_common_port/doc/html/globals_type.html
@@ -0,0 +1,41 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Synopsys DWC Portability and Common Library for UWB: Data Fields</title>
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+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
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+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="dirs.html"><span>Directories</span></a></li>
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+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html"><span>All</span></a></li>
+    <li><a href="globals_func.html"><span>Functions</span></a></li>
+    <li id="current"><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+&nbsp;
+<p>
+<ul>
+<li>dwc_bool_t
+: <a class="el" href="dwc__os_8h.html#e2374f0b1253fc63321e1b253ee61b1d">dwc_os.h</a><li>dwc_notifier_callback_t
+: <a class="el" href="dwc__notifier_8h.html#a8a84ad74a90bea39597283487b9cbfb">dwc_notifier.h</a><li>dwc_thread_function_t
+: <a class="el" href="dwc__os_8h.html#d34bdab089ddbc0e479c9fead16ca7ac">dwc_os.h</a><li>dwc_waitq_condition_t
+: <a class="el" href="dwc__os_8h.html#b361f6bc4eff88c0ddda059569da125f">dwc_os.h</a><li>dwc_work_callback_t
+: <a class="el" href="dwc__os_8h.html#c67973a4ac14764ed66a82103a357c06">dwc_os.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:50 2009 for Synopsys DWC Portability and Common Library for UWB by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_common_port/doc/html/index.html b/drivers/usb/host/dwc_common_port/doc/html/index.html
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+++ b/drivers/usb/host/dwc_common_port/doc/html/index.html
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+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
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diff --git a/drivers/usb/host/dwc_common_port/doc/html/main.html b/drivers/usb/host/dwc_common_port/doc/html/main.html
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+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Synopsys DWC Portability and Common Library for UWB: DWC Portability and Common Library</title>
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+<link href="tabs.css" rel="stylesheet" type="text/css">
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+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<h1>DWC Portability and Common Library</h1>
+<p>
+This is the documentation for the DWC Portability and Common Library.<h2><a class="anchor" name="intro">
+Introduction</a></h2>
+The DWC Portability library consists of wrapper calls and data structures to all low-level functions which are typically provided by the OS. The WUDEV driver uses only these functions. In order to port the WUDEV driver, only the functions in this library need to be re-implemented, with the same behavior as documented here.<p>
+The Common library consists of higher level functions, which rely only on calling the functions from the DWC Portability library. These common routines are shared across modules. Some of the common libraries need to be used directly by the driver programmer when porting WUDEV. Such as the parameter and notification libraries.<h2><a class="anchor" name="low">
+Portability Library OS Wrapper Functions</a></h2>
+Any function starting with DWC and in all CAPS is a low-level OS-wrapper that needs to be implemented when porting, for example DWC_MUTEX_ALLOC(). All of these functions are included in the <a class="el" href="dwc__os_8h.html">dwc_os.h</a> file.<p>
+There are many functions here covering a wide array of OS services. Please see <a class="el" href="dwc__os_8h.html">dwc_os.h</a> for details, and implementation notes for each function.<h2><a class="anchor" name="common">
+Common Library Functions</a></h2>
+Any function starting with dwc and in all lowercase is a common library routine. These functions have a portable implementation and do not need to be reimplemented when porting. The common routines can be used by any driver, and some must be used by the end user to control the drivers. For example, you must use the Parameter common library in order to set the parameters in the WUDEV module.<p>
+The common libraries consist of the following:<p>
+<ul>
+<li>Connection Contexts - Used internally and can be used by end-user. See <a class="el" href="dwc__cc_8h.html">dwc_cc.h</a></li><li>Parameters - Used internally and can be used by end-user. See dwc_params.h</li><li>Notifications - Used internally and can be used by end-user. See <a class="el" href="dwc__notifier_8h.html">dwc_notifier.h</a></li><li>Lists - Used internally and can be used by end-user. See <a class="el" href="dwc__list_8h.html">dwc_list.h</a></li><li>Memory Debugging - Used internally and can be used by end-user. See <a class="el" href="dwc__os_8h.html">dwc_os.h</a></li><li>Modpow - Used internally only. See <a class="el" href="dwc__modpow_8h.html">dwc_modpow.h</a></li><li>DH - Used internally only. See <a class="el" href="dwc__dh_8h.html">dwc_dh.h</a></li><li>Crypto - Used internally only. See <a class="el" href="dwc__crypto_8h.html">dwc_crypto.h</a></li></ul>
+<h2><a class="anchor" name="prereq">
+Prerequistes For dwc_os.h</a></h2>
+<h3><a class="anchor" name="types">
+Data Types</a></h3>
+The <a class="el" href="dwc__os_8h.html">dwc_os.h</a> file assumes that several low-level data types are pre defined for the compilation environment. These data types are:<p>
+<ul>
+<li>uint8_t - unsigned 8-bit data type</li><li>int8_t - signed 8-bit data type</li><li>uint16_t - unsigned 16-bit data type</li><li>int16_t - signed 16-bit data type</li><li>uint32_t - unsigned 32-bit data type</li><li>int32_t - signed 32-bit data type</li><li>uint64_t - unsigned 64-bit data type</li><li>int64_t - signed 64-bit data type</li></ul>
+<p>
+Ensure that these are defined before using <a class="el" href="dwc__os_8h.html">dwc_os.h</a>. The easiest way to do that is to modify the top of the file to include the appropriate header. This is already done for the Linux environment. If the DWC_LINUX macro is defined, the correct header will be added. A standard header &lt;stdint.h&gt; is also used for environments where standard C headers are available.<h3><a class="anchor" name="stdarg">
+Variable Arguments</a></h3>
+Variable arguments are provided by a standard C header &lt;stdarg.h&gt;. it is available in Both the Linux and ANSI C enviornment. An equivalent must be provided in your enviornment in order to use <a class="el" href="dwc__os_8h.html">dwc_os.h</a> with the debug and tracing message functionality.<h3><a class="anchor" name="thread">
+Threading</a></h3>
+WUDEV Core must be run on an operating system that provides for multiple threads/processes. Threading can be implemented in many ways, even in embedded systems without an operating system. At the bare minimum, the system should be able to start any number of processes at any time to handle special work. It need not be a pre-emptive system. Process context can change upon a call to a blocking function. The hardware interrupt context that calls the module's ISR() function must be differentiable from process context, even if your processes are impemented via a hardware interrupt. Further locking mechanism between process must exist (or be implemented), and process context must have a way to disable interrupts for a period of time to lock them out. If all of this exists, the functions in <a class="el" href="dwc__os_8h.html">dwc_os.h</a> related to threading should be able to be implemented with the defined behavior. <hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:50 2009 for Synopsys DWC Portability and Common Library for UWB by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_common_port/doc/html/pages.html b/drivers/usb/host/dwc_common_port/doc/html/pages.html
new file mode 100644
index 000000000000..09e4bb0fa605
--- /dev/null
+++ b/drivers/usb/host/dwc_common_port/doc/html/pages.html
@@ -0,0 +1,23 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Synopsys DWC Portability and Common Library for UWB: Page Index</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="dirs.html"><span>Directories</span></a></li>
+    <li id="current"><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<h1>Synopsys DWC Portability and Common Library for UWB Related Pages</h1>Here is a list of all related documentation pages:<ul>
+<li><a class="el" href="todo.html">Todo List</a>
+
+</ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:50 2009 for Synopsys DWC Portability and Common Library for UWB by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_common_port/doc/html/tabs.css b/drivers/usb/host/dwc_common_port/doc/html/tabs.css
new file mode 100644
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--- /dev/null
+++ b/drivers/usb/host/dwc_common_port/doc/html/tabs.css
@@ -0,0 +1,102 @@
+/* tabs styles, based on http://www.alistapart.com/articles/slidingdoors */
+
+DIV.tabs
+{
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+   margin-bottom    : 4px;
+}
+
+DIV.tabs UL
+{
+   margin           : 0px;
+   padding-left     : 10px;
+   list-style       : none;
+}
+
+DIV.tabs LI, DIV.tabs FORM
+{
+   display          : inline;
+   margin           : 0px;
+   padding          : 0px;
+}
+
+DIV.tabs FORM
+{
+   float            : right;
+}
+
+DIV.tabs A
+{
+   float            : left;
+   background       : url("tab_r.gif") no-repeat right top;
+   border-bottom    : 1px solid #84B0C7;
+   font-size        : x-small;
+   font-weight      : bold;
+   text-decoration  : none;
+}
+
+DIV.tabs A:hover
+{
+   background-position: 100% -150px;
+}
+
+DIV.tabs A:link, DIV.tabs A:visited,
+DIV.tabs A:active, DIV.tabs A:hover
+{
+       color: #1A419D;
+}
+
+DIV.tabs SPAN
+{
+   float            : left;
+   display          : block;
+   background       : url("tab_l.gif") no-repeat left top;
+   padding          : 5px 9px;
+   white-space      : nowrap;
+}
+
+DIV.tabs INPUT
+{
+   float            : right;
+   display          : inline;
+   font-size        : 1em;
+}
+
+DIV.tabs TD
+{
+   font-size        : x-small;
+   font-weight      : bold;
+   text-decoration  : none;
+}
+
+
+
+/* Commented Backslash Hack hides rule from IE5-Mac \*/
+DIV.tabs SPAN {float : none;}
+/* End IE5-Mac hack */
+
+DIV.tabs A:hover SPAN
+{
+   background-position: 0% -150px;
+}
+
+DIV.tabs LI#current A
+{
+   background-position: 100% -150px;
+   border-width     : 0px;
+}
+
+DIV.tabs LI#current SPAN
+{
+   background-position: 0% -150px;
+   padding-bottom   : 6px;
+}
+
+DIV.nav
+{
+   background       : none;
+   border           : none;
+   border-bottom    : 1px solid #84B0C7;
+}
diff --git a/drivers/usb/host/dwc_common_port/doc/html/todo.html b/drivers/usb/host/dwc_common_port/doc/html/todo.html
new file mode 100644
index 000000000000..c976dc2505d3
--- /dev/null
+++ b/drivers/usb/host/dwc_common_port/doc/html/todo.html
@@ -0,0 +1,23 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Synopsys DWC Portability and Common Library for UWB: Todo List</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="dirs.html"><span>Directories</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<h1><a class="anchor" name="todo">Todo List</a></h1><a class="anchor" name="_todo000002"></a> <dl>
+<dt>Global <a class="el" href="dwc__os_8h.html#f74ba85fa4f2dcb59886b2f3d4ef709f">__DWC_DMA_ALLOC</a>  </dt>
+<dd>these functions will be added in the future </dd>
+</dl>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:50 2009 for Synopsys DWC Portability and Common Library for UWB by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_common_port/doc/html/tree.html b/drivers/usb/host/dwc_common_port/doc/html/tree.html
new file mode 100644
index 000000000000..ec0914f7bddf
--- /dev/null
+++ b/drivers/usb/host/dwc_common_port/doc/html/tree.html
@@ -0,0 +1,90 @@
+<html xmlns="http://www.w3.org/1999/xhtml" xml:lang="en" lang="en">
+  <head>
+    <meta http-equiv="Content-Type" content="text/xhtml;charset=iso-8859-1" />
+    <meta http-equiv="Content-Style-Type" content="text/css" />
+    <meta http-equiv="Content-Language" content="en" />
+    <link rel="stylesheet" href="doxygen.css">
+    <title>TreeView</title>
+    <script type="text/javascript">
+    <!-- // Hide script from old browsers
+    
+    function toggleFolder(id, imageNode) 
+    {
+      var folder = document.getElementById(id);
+      var l = imageNode.src.length;
+      if (imageNode.src.substring(l-20,l)=="ftv2folderclosed.png" || 
+          imageNode.src.substring(l-18,l)=="ftv2folderopen.png")
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+        imageNode = imageNode.previousSibling;
+        l = imageNode.src.length;
+      }
+      if (folder == null) 
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+      {
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+          imageNode.nextSibling.src = "ftv2folderclosed.png";
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+            imageNode.src = "ftv2pnode.png";
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+            imageNode.src = "ftv2mnode.png";
+          }
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+    }
+
+    // End script hiding -->        
+    </script>
+  </head>
+
+  <body class="ftvtree">
+    <div class="directory">
+      <h3>Synopsys DWC Portability and Common Library for UWB</h3>
+      <div style="display: block;">
+        <p><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="main.html" target="basefrm">DWC Portability and Common Library</a></p>
+        <p><img src="ftv2pnode.png" alt="o" width=16 height=22 onclick="toggleFolder('folder1', this)"/><img src="ftv2folderclosed.png" alt="+" width=24 height=22 onclick="toggleFolder('folder1', this)"/><a class="el" href="files.html" target="basefrm">File List</a></p>
+        <div id="folder1">
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="dwc__cc_8h.html" target="basefrm">dwc_cc.h</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="dwc__crypto_8c.html" target="basefrm">dwc_crypto.c</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="dwc__crypto_8h.html" target="basefrm">dwc_crypto.h</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="dwc__dh_8h.html" target="basefrm">dwc_dh.h</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="dwc__list_8h.html" target="basefrm">dwc_list.h</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="dwc__modpow_8h.html" target="basefrm">dwc_modpow.h</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="dwc__notifier_8h.html" target="basefrm">dwc_notifier.h</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2lastnode.png" alt="\" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="dwc__os_8h.html" target="basefrm">dwc_os.h</a></p>
+        </div>
+        <p><img src="ftv2pnode.png" alt="o" width=16 height=22 onclick="toggleFolder('folder2', this)"/><img src="ftv2folderclosed.png" alt="+" width=24 height=22 onclick="toggleFolder('folder2', this)"/><a class="el" href="dirs.html" target="basefrm">Directories</a></p>
+        <div id="folder2">
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2lastnode.png" alt="\" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="dir_c13d72e45af28cdc461a5f284d3d36fc.html" target="basefrm">dwc_common_port</a></p>
+        </div>
+        <p><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="globals.html" target="basefrm">Globals</a></p>
+        <p><img src="ftv2plastnode.png" alt="\" width=16 height=22 onclick="toggleFolder('folder3', this)"/><img src="ftv2folderclosed.png" alt="+" width=24 height=22 onclick="toggleFolder('folder3', this)"/><a class="el" href="pages.html" target="basefrm">Related Pages</a></p>
+        <div id="folder3">
+          <p><img src="ftv2blank.png" alt="&nbsp;" width=16 height=22 /><img src="ftv2lastnode.png" alt="\" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="todo.html" target="basefrm">Todo List</a></p>
+        </div>
+      </div>
+    </div>
+  </body>
+</html>
diff --git a/drivers/usb/host/dwc_common_port/dwc_cc.c b/drivers/usb/host/dwc_common_port/dwc_cc.c
new file mode 100644
index 000000000000..3a7dd711ce60
--- /dev/null
+++ b/drivers/usb/host/dwc_common_port/dwc_cc.c
@@ -0,0 +1,506 @@
+/* =========================================================================
+ * $File: //dwh/usb_iip/dev/software/dwc_common_port/dwc_cc.c $
+ * $Revision: #1 $
+ * $Date: 2008/12/21 $
+ * $Change: 1156609 $
+ *
+ * Synopsys Portability Library Software and documentation
+ * (hereinafter, "Software") is an Unsupported proprietary work of
+ * Synopsys, Inc. unless otherwise expressly agreed to in writing
+ * between Synopsys and you.
+ *
+ * The Software IS NOT an item of Licensed Software or Licensed Product
+ * under any End User Software License Agreement or Agreement for
+ * Licensed Product with Synopsys or any supplement thereto. You are
+ * permitted to use and redistribute this Software in source and binary
+ * forms, with or without modification, provided that redistributions
+ * of source code must retain this notice. You may not view, use,
+ * disclose, copy or distribute this file or any information contained
+ * herein except pursuant to this license grant from Synopsys. If you
+ * do not agree with this notice, including the disclaimer below, then
+ * you are not authorized to use the Software.
+ *
+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
+ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
+ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ * ========================================================================= */
+#include "dwc_cc.h"
+
+typedef struct dwc_cc
+{
+	uint32_t uid;
+	uint8_t chid[16];
+	uint8_t cdid[16];
+	uint8_t ck[16];
+	uint8_t *name;
+	uint8_t length;
+        DWC_CIRCLEQ_ENTRY(dwc_cc) list_entry;
+} dwc_cc_t;
+
+DWC_CIRCLEQ_HEAD(context_list, dwc_cc);
+
+/** The main structure for CC management.  */
+struct dwc_cc_if
+{
+	dwc_mutex_t *mutex;
+	char *filename;
+
+	unsigned is_host:1;
+
+	dwc_notifier_t *notifier;
+
+	struct context_list list;
+};
+
+#ifdef DEBUG
+static inline void dump_bytes(char *name, uint8_t *bytes, int len)
+{
+	int i;
+	DWC_PRINTF("%s: ", name);
+	for (i=0; i<len; i++) {
+		DWC_PRINTF("%02x ", bytes[i]);
+	}
+	DWC_PRINTF("\n");
+}
+#else
+#define dump_bytes(x...)
+#endif
+
+static dwc_cc_t *alloc_cc(uint8_t *name, uint32_t length)
+{
+	dwc_cc_t *cc = DWC_ALLOC(sizeof(dwc_cc_t));
+	if (!cc) {
+		return NULL;
+	}
+	DWC_MEMSET(cc, 0, sizeof(dwc_cc_t));
+
+	if (name) {
+		cc->length = length;
+		cc->name = DWC_ALLOC(length);
+		DWC_MEMCPY(cc->name, name, length);
+	}
+
+	return cc;
+}
+
+static void free_cc(dwc_cc_t *cc)
+{
+	if (cc->name) {
+		DWC_FREE(cc->name);
+	}
+	DWC_FREE(cc);
+}
+
+static uint32_t next_uid(dwc_cc_if_t *cc_if)
+{
+	uint32_t uid = 0;
+	dwc_cc_t *cc;
+	DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {
+		if (cc->uid > uid) {
+			uid = cc->uid;
+		}
+	}
+
+	if (uid == 0) {
+		uid = 255;
+	}
+
+	return uid + 1;
+}
+
+static dwc_cc_t *cc_find(dwc_cc_if_t *cc_if, uint32_t uid)
+{
+	dwc_cc_t *cc;
+	DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {
+		if (cc->uid == uid) {
+			return cc;
+		}
+	}
+	return NULL;
+}
+
+static unsigned int cc_data_size(dwc_cc_if_t *cc_if)
+{
+	unsigned int size = 0;
+	dwc_cc_t *cc;
+	DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {
+		size += (48 + 1);
+		if (cc->name) {
+			size += cc->length;
+		}
+	}
+	return size;
+}
+
+static uint32_t cc_match_chid(dwc_cc_if_t *cc_if, uint8_t *chid)
+{
+	uint32_t uid = 0;
+	dwc_cc_t *cc;
+
+	DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {
+		if (DWC_MEMCMP(cc->chid, chid, 16) == 0) {
+			uid = cc->uid;
+			break;
+		}
+	}
+	return uid;
+}
+static uint32_t cc_match_cdid(dwc_cc_if_t *cc_if, uint8_t *cdid)
+{
+	uint32_t uid = 0;
+	dwc_cc_t *cc;
+
+	DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {
+		if (DWC_MEMCMP(cc->cdid, cdid, 16) == 0) {
+			uid = cc->uid;
+			break;
+		}
+	}
+	return uid;
+}
+
+/* Internal cc_add */
+static int32_t cc_add(dwc_cc_if_t *cc_if, uint8_t *chid, uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length)
+{
+	dwc_cc_t *cc;
+	uint32_t uid;
+
+	if (cc_if->is_host) {
+		uid = cc_match_cdid(cc_if, cdid);
+	}
+	else {
+		uid = cc_match_chid(cc_if, chid);
+	}
+
+	if (uid) {
+		DWC_DEBUG("Replacing previous connection context id=%d name=%p name_len=%d", uid, name, length);
+		cc = cc_find(cc_if, uid);
+	}
+	else {
+		cc = alloc_cc(name, length);
+		cc->uid = next_uid(cc_if);
+		DWC_CIRCLEQ_INSERT_TAIL(&cc_if->list, cc, list_entry);
+	}
+
+	DWC_MEMCPY(&(cc->chid[0]), chid, 16);
+	DWC_MEMCPY(&(cc->cdid[0]), cdid, 16);
+	DWC_MEMCPY(&(cc->ck[0]), ck, 16);
+
+	DWC_DEBUG("Added connection context id=%d name=%p name_len=%d", cc->uid, name, length);
+	dump_bytes("CHID", cc->chid, 16);
+	dump_bytes("CDID", cc->cdid, 16);
+	dump_bytes("CK", cc->ck, 16);
+	return cc->uid;
+}
+
+/* Internal cc_clear */
+static void cc_clear(dwc_cc_if_t *cc_if)
+{
+	while (!DWC_CIRCLEQ_EMPTY(&cc_if->list)) {
+		dwc_cc_t *cc = DWC_CIRCLEQ_FIRST(&cc_if->list);
+		DWC_CIRCLEQ_REMOVE_INIT(&cc_if->list, cc, list_entry);
+		free_cc(cc);
+	}
+}
+
+dwc_cc_if_t *dwc_cc_if_alloc(dwc_notifier_t *notifier, unsigned is_host)
+{
+	dwc_cc_if_t *cc_if = NULL;
+
+	/* Allocate a common_cc_if structure */
+	cc_if = DWC_ALLOC(sizeof(dwc_cc_if_t));
+
+	if(!cc_if)
+		return NULL;
+
+#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES))
+	DWC_MUTEX_ALLOC_LINUX_DEBUG(cc_if->mutex);
+#else
+	cc_if->mutex = DWC_MUTEX_ALLOC();
+#endif
+	DWC_CIRCLEQ_INIT(&cc_if->list);
+	cc_if->is_host = is_host;
+	cc_if->notifier = notifier;
+	return cc_if;
+}
+
+void dwc_cc_if_free(dwc_cc_if_t *cc_if)
+{
+	DWC_MUTEX_FREE(cc_if->mutex);
+	cc_clear(cc_if);
+	DWC_FREE(cc_if);
+}
+
+static void cc_changed(dwc_cc_if_t *cc_if)
+{
+	if (cc_if->notifier) {
+		dwc_notify(cc_if->notifier, DWC_CC_LIST_CHANGED_NOTIFICATION, cc_if);
+	}
+}
+
+void dwc_cc_clear(dwc_cc_if_t *cc_if)
+{
+	DWC_MUTEX_LOCK(cc_if->mutex);
+	cc_clear(cc_if);
+	DWC_MUTEX_UNLOCK(cc_if->mutex);
+	cc_changed(cc_if);
+}
+
+int32_t dwc_cc_add(dwc_cc_if_t *cc_if, uint8_t *chid, uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length)
+{
+	uint32_t uid;
+
+	DWC_MUTEX_LOCK(cc_if->mutex);
+	uid = cc_add(cc_if, chid, cdid, ck, name, length);
+	DWC_MUTEX_UNLOCK(cc_if->mutex);
+	cc_changed(cc_if);
+
+	return uid;
+}
+
+void dwc_cc_change(dwc_cc_if_t *cc_if, int32_t id,
+			  uint8_t *chid, uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length)
+{
+	dwc_cc_t* cc;
+
+	DWC_DEBUG("Change connection context %d", id);
+
+	DWC_MUTEX_LOCK(cc_if->mutex);
+	cc = cc_find(cc_if, id);
+	if (!cc) {
+		DWC_ERROR("Uid %d not found in cc list", id);
+		DWC_MUTEX_UNLOCK(cc_if->mutex);
+		return;
+	}
+
+	if (chid) {
+		DWC_MEMCPY(&(cc->chid[0]), chid, 16);
+	}
+	if (cdid) {
+		DWC_MEMCPY(&(cc->cdid[0]), cdid, 16);
+	}
+	if (ck) {
+		DWC_MEMCPY(&(cc->ck[0]), ck, 16);
+	}
+
+	if (name) {
+		if (cc->name) {
+			DWC_FREE(cc->name);
+		}
+		cc->name = DWC_ALLOC(length);
+		cc->length = length;
+		DWC_MEMCPY(cc->name, name, length);
+	}
+
+	DWC_MUTEX_UNLOCK(cc_if->mutex);
+
+	cc_changed(cc_if);
+
+	DWC_DEBUG("Changed connection context id=%d\n", id);
+	dump_bytes("New CHID", cc->chid, 16);
+	dump_bytes("New CDID", cc->cdid, 16);
+	dump_bytes("New CK", cc->ck, 16);
+}
+
+void dwc_cc_remove(dwc_cc_if_t *cc_if, int32_t id)
+{
+	dwc_cc_t *cc;
+
+	DWC_DEBUG("Removing connection context %d", id);
+
+	DWC_MUTEX_LOCK(cc_if->mutex);
+	cc = cc_find(cc_if, id);
+	if (!cc) {
+		DWC_ERROR("Uid %d not found in cc list", id);
+		DWC_MUTEX_UNLOCK(cc_if->mutex);
+		return;
+	}
+
+	DWC_CIRCLEQ_REMOVE_INIT(&cc_if->list, cc, list_entry);
+	DWC_MUTEX_UNLOCK(cc_if->mutex);
+	free_cc(cc);
+
+	cc_changed(cc_if);
+}
+
+uint8_t *dwc_cc_data_for_save(dwc_cc_if_t *cc_if, unsigned int *length)
+{
+	uint8_t *buf, *x;
+	uint8_t zero = 0;
+	dwc_cc_t *cc;
+
+	DWC_MUTEX_LOCK(cc_if->mutex);
+	*length = cc_data_size(cc_if);
+	if (!(*length)) {
+		DWC_MUTEX_UNLOCK(cc_if->mutex);
+		return NULL;
+	}
+
+	DWC_DEBUG("Creating data for saving (length=%d)", *length);
+
+	buf = DWC_ALLOC(*length);
+	if (!buf) {
+		*length = 0;
+		DWC_MUTEX_UNLOCK(cc_if->mutex);
+		return NULL;
+	}
+
+	x = buf;
+	DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {
+		DWC_MEMCPY(x, cc->chid, 16);
+		x += 16;
+		DWC_MEMCPY(x, cc->cdid, 16);
+		x += 16;
+		DWC_MEMCPY(x, cc->ck, 16);
+		x += 16;
+		if (cc->name) {
+			DWC_MEMCPY(x, &cc->length, 1);
+			x += 1;
+			DWC_MEMCPY(x, cc->name, cc->length);
+			x += cc->length;
+		}
+		else {
+			DWC_MEMCPY(x, &zero, 1);
+			x += 1;
+		}
+	}
+	DWC_MUTEX_UNLOCK(cc_if->mutex);
+
+	return buf;
+}
+
+void dwc_cc_restore_from_data(dwc_cc_if_t *cc_if, uint8_t *data, uint32_t length)
+{
+	uint8_t name_length;
+	uint8_t *name;
+	uint8_t *chid;
+	uint8_t *cdid;
+	uint8_t *ck;
+	uint32_t i = 0;
+
+	DWC_MUTEX_LOCK(cc_if->mutex);
+	cc_clear(cc_if);
+
+	while (i < length) {
+		chid = &data[i];
+		i += 16;
+		cdid = &data[i];
+		i += 16;
+		ck = &data[i];
+		i += 16;
+
+		name_length = data[i];
+		i ++;
+
+		if (name_length) {
+			name = &data[i];
+			i += name_length;
+		}
+		else {
+			name = NULL;
+		}
+
+		/* check to see if we haven't overflown the buffer */
+		if (i > length) {
+			DWC_ERROR("Data format error while attempting to load CCs "
+				  "(nlen=%d, iter=%d, buflen=%d).", name_length, i, length);
+			break;
+		}
+
+		cc_add(cc_if, chid, cdid, ck, name, name_length);
+	}
+	DWC_MUTEX_UNLOCK(cc_if->mutex);
+
+	cc_changed(cc_if);
+}
+
+uint32_t dwc_cc_match_chid(dwc_cc_if_t *cc_if, uint8_t *chid)
+{
+	uint32_t uid = 0;
+
+	DWC_MUTEX_LOCK(cc_if->mutex);
+	uid = cc_match_chid(cc_if, chid);
+	DWC_MUTEX_UNLOCK(cc_if->mutex);
+	return uid;
+}
+uint32_t dwc_cc_match_cdid(dwc_cc_if_t *cc_if, uint8_t *cdid)
+{
+	uint32_t uid = 0;
+
+	DWC_MUTEX_LOCK(cc_if->mutex);
+	uid = cc_match_cdid(cc_if, cdid);
+	DWC_MUTEX_UNLOCK(cc_if->mutex);
+	return uid;
+}
+
+uint8_t *dwc_cc_ck(dwc_cc_if_t *cc_if, int32_t id)
+{
+	uint8_t *ck = NULL;
+	dwc_cc_t *cc;
+
+	DWC_MUTEX_LOCK(cc_if->mutex);
+	cc = cc_find(cc_if, id);
+	if (cc) {
+		ck = cc->ck;
+	}
+	DWC_MUTEX_UNLOCK(cc_if->mutex);
+
+	return ck;
+
+}
+
+uint8_t *dwc_cc_chid(dwc_cc_if_t *cc_if, int32_t id)
+{
+	uint8_t *retval = NULL;
+	dwc_cc_t *cc;
+
+	DWC_MUTEX_LOCK(cc_if->mutex);
+	cc = cc_find(cc_if, id);
+	if (cc) {
+		retval = cc->chid;
+	}
+	DWC_MUTEX_UNLOCK(cc_if->mutex);
+
+	return retval;
+}
+
+uint8_t *dwc_cc_cdid(dwc_cc_if_t *cc_if, int32_t id)
+{
+	uint8_t *retval = NULL;
+	dwc_cc_t *cc;
+
+	DWC_MUTEX_LOCK(cc_if->mutex);
+	cc = cc_find(cc_if, id);
+	if (cc) {
+		retval = cc->cdid;
+	}
+	DWC_MUTEX_UNLOCK(cc_if->mutex);
+
+	return retval;
+}
+
+uint8_t *dwc_cc_name(dwc_cc_if_t *cc_if, int32_t id, uint8_t *length)
+{
+	uint8_t *retval = NULL;
+	dwc_cc_t *cc;
+
+	DWC_MUTEX_LOCK(cc_if->mutex);
+	*length = 0;
+	cc = cc_find(cc_if, id);
+	if (cc) {
+		*length = cc->length;
+		retval = cc->name;
+	}
+	DWC_MUTEX_UNLOCK(cc_if->mutex);
+
+	return retval;
+}
diff --git a/drivers/usb/host/dwc_common_port/dwc_cc.h b/drivers/usb/host/dwc_common_port/dwc_cc.h
new file mode 100644
index 000000000000..6b4641918f62
--- /dev/null
+++ b/drivers/usb/host/dwc_common_port/dwc_cc.h
@@ -0,0 +1,209 @@
+/* =========================================================================
+ * $File: //dwh/usb_iip/dev/software/dwc_common_port/dwc_cc.h $
+ * $Revision: #1 $
+ * $Date: 2008/12/21 $
+ * $Change: 1156609 $
+ *
+ * Synopsys Portability Library Software and documentation
+ * (hereinafter, "Software") is an Unsupported proprietary work of
+ * Synopsys, Inc. unless otherwise expressly agreed to in writing
+ * between Synopsys and you.
+ *
+ * The Software IS NOT an item of Licensed Software or Licensed Product
+ * under any End User Software License Agreement or Agreement for
+ * Licensed Product with Synopsys or any supplement thereto. You are
+ * permitted to use and redistribute this Software in source and binary
+ * forms, with or without modification, provided that redistributions
+ * of source code must retain this notice. You may not view, use,
+ * disclose, copy or distribute this file or any information contained
+ * herein except pursuant to this license grant from Synopsys. If you
+ * do not agree with this notice, including the disclaimer below, then
+ * you are not authorized to use the Software.
+ *
+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
+ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
+ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ * ========================================================================= */
+#ifndef _DWC_CC_H_
+#define _DWC_CC_H_
+
+/** @file
+ *
+ * This file defines the Context Context library.
+ *
+ * The main data structure is dwc_cc_if_t which is returned by either the
+ * dwc_cc_if_alloc function or returned by the module to the user via a provided
+ * function. The data structure is opaque and should only be manipulated via the
+ * functions provied in this API.
+ *
+ * It manages a list of connection contexts and operations can be performed to
+ * add, remove, query, search, and change, those contexts.  Additionally,
+ * a dwc_notifier_t object can be requested from the manager so that
+ * the user can be notified whenever the context list has changed.
+ */
+
+#include "dwc_os.h"
+#include "dwc_list.h"
+#include "dwc_notifier.h"
+
+
+/* Notifications */
+#define DWC_CC_LIST_CHANGED_NOTIFICATION "DWC_CC_LIST_CHANGED_NOTIFICATION"
+
+struct dwc_cc_if;
+typedef struct dwc_cc_if dwc_cc_if_t;
+
+
+/** @name Connection Context Operations */
+/** @{ */
+
+/** This function allocates memory for a dwc_cc_if_t structure, initializes
+ * fields to default values, and returns a pointer to the structure or NULL on
+ * error. */
+extern dwc_cc_if_t *dwc_cc_if_alloc(dwc_notifier_t *notifier, unsigned is_host);
+
+/** Frees the memory for the specified CC structure allocated from
+ * dwc_cc_if_alloc(). */
+extern void dwc_cc_if_free(dwc_cc_if_t *cc_if);
+
+/** Removes all contexts from the connection context list */
+extern void dwc_cc_clear(dwc_cc_if_t *cc_if);
+
+/** Adds a connection context (CHID, CK, CDID, Name) to the connection context list.
+ * If a CHID already exists, the CK and name are overwritten.  Statistics are
+ * not overwritten.
+ *
+ * @param cc_if The cc_if structure.
+ * @param chid A pointer to the 16-byte CHID.  This value will be copied.
+ * @param ck A pointer to the 16-byte CK.  This value will be copied.
+ * @param cdid A pointer to the 16-byte CDID.  This value will be copied.
+ * @param name An optional host friendly name as defined in the association model
+ * spec.  Must be a UTF16-LE unicode string.  Can be NULL to indicated no name.
+ * @param length The length othe unicode string.
+ * @return A unique identifier used to refer to this context that is valid for
+ * as long as this context is still in the list. */
+extern int32_t dwc_cc_add(dwc_cc_if_t *cc_if, uint8_t *chid, uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length);
+
+/** Changes the CHID, CK, CDID, or Name values of a connection context in the
+ * list, preserving any accumulated statistics.  This would typically be called
+ * if the host decideds to change the context with a SET_CONNECTION request.
+ *
+ * @param cc_if The cc_if structure.
+ * @param id The identifier of the connection context.
+ * @param chid A pointer to the 16-byte CHID.  This value will be copied.  NULL
+ * indicates no change.
+ * @param cdid A pointer to the 16-byte CDID.  This value will be copied.  NULL
+ * indicates no change.
+ * @param ck A pointer to the 16-byte CK.  This value will be copied.  NULL
+ * indicates no change.
+ * @param name Host friendly name UTF16-LE.  NULL indicates no change.
+ * @param length Length of name. */
+extern void dwc_cc_change(dwc_cc_if_t *cc_if, int32_t id, uint8_t *chid, uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length);
+
+/** Remove the specified connection context.
+ * @param cc_if The cc_if structure.
+ * @param id The identifier of the connection context to remove. */
+extern void dwc_cc_remove(dwc_cc_if_t *cc_if, int32_t id);
+
+/** Get a binary block of data for the connection context list and attributes.
+ * This data can be used by the OS specific driver to save the connection
+ * context list into non-volatile memory.
+ *
+ * @param cc_if The cc_if structure.
+ * @param length Return the length of the data buffer.
+ * @return A pointer to the data buffer.  The memory for this buffer should be freed with DWC_FREE() after use. */
+extern uint8_t *dwc_cc_data_for_save(dwc_cc_if_t *cc_if, unsigned int *length);
+
+/** Restore the connection context list from the binary data that was previously
+ * returned from a call to dwc_cc_data_for_save.  This can be used by the OS specific
+ * driver to load a connection context list from non-volatile memory.
+ *
+ * @param cc_if The cc_if structure.
+ * @param data The data bytes as returned from dwc_cc_data_for_save.
+ * @param length The length of the data. */
+extern void dwc_cc_restore_from_data(dwc_cc_if_t *cc_if, uint8_t *data, unsigned int length);
+
+/** Find the connection context from the specified CHID.
+ *
+ * @param cc_if The cc_if structure.
+ * @param chid A pointer to the CHID data.
+ * @return A non-zero identifier of the connection context if the CHID matches.
+ * Otherwise returns 0. */
+extern uint32_t dwc_cc_match_chid(dwc_cc_if_t *cc_if, uint8_t *chid);
+
+/** Find the connection context from the specified CDID.
+ *
+ * @param cc_if The cc_if structure.
+ * @param cdid A pointer to the CDID data.
+ * @return A non-zero identifier of the connection context if the CHID matches.
+ * Otherwise returns 0. */
+extern uint32_t dwc_cc_match_cdid(dwc_cc_if_t *cc_if, uint8_t *cdid);
+
+/** Retrieve the CK from the specified connection context.
+ *
+ * @param cc_if The cc_if structure.
+ * @param id The identifier of the connection context.
+ * @return A pointer to the CK data.  The memory does not need to be freed. */
+extern uint8_t *dwc_cc_ck(dwc_cc_if_t *cc_if, int32_t id);
+
+/** Retrieve the CHID from the specified connection context.
+ *
+ * @param cc_if The cc_if structure.
+ * @param id The identifier of the connection context.
+ * @return A pointer to the CHID data.  The memory does not need to be freed. */
+extern uint8_t *dwc_cc_chid(dwc_cc_if_t *cc_if, int32_t id);
+
+/** Retrieve the CDID from the specified connection context.
+ *
+ * @param cc_if The cc_if structure.
+ * @param id The identifier of the connection context.
+ * @return A pointer to the CDID data.  The memory does not need to be freed. */
+extern uint8_t *dwc_cc_cdid(dwc_cc_if_t *cc_if, int32_t id);
+
+extern uint8_t *dwc_cc_name(dwc_cc_if_t *cc_if, int32_t id, uint8_t *length);
+
+/** Checks a buffer for non-zero.
+ * @param id A pointer to a 16 byte buffer. 
+ * @return true if the 16 byte value is non-zero. */
+static inline unsigned dwc_assoc_is_not_zero_id(uint8_t *id) {
+	int i;
+	for (i=0; i<16; i++) {
+		if (id[i]) return 1;
+	}
+	return 0;
+}
+
+/** Checks a buffer for zero.
+ * @param id A pointer to a 16 byte buffer. 
+ * @return true if the 16 byte value is zero. */
+static inline unsigned dwc_assoc_is_zero_id(uint8_t *id) {
+	return !dwc_assoc_is_not_zero_id(id);
+}
+
+/** Prints an ASCII representation for the 16-byte chid, cdid, or ck, into
+ * buffer. */
+static inline int dwc_print_id_string(char *buffer, uint8_t *id) {
+	char *ptr = buffer;
+	int i;
+	for (i=0; i<16; i++) {
+		ptr += DWC_SPRINTF(ptr, "%02x", id[i]);
+		if (i < 15) {
+			ptr += DWC_SPRINTF(ptr, " ");
+		}
+	}
+	return ptr - buffer;
+}
+
+/** @} */
+
+#endif /* _DWC_CC_H_ */
+
diff --git a/drivers/usb/host/dwc_common_port/dwc_common_linux.c b/drivers/usb/host/dwc_common_port/dwc_common_linux.c
new file mode 100644
index 000000000000..cef068fb46c3
--- /dev/null
+++ b/drivers/usb/host/dwc_common_port/dwc_common_linux.c
@@ -0,0 +1,1247 @@
+#include "dwc_cc.h"
+#include "dwc_modpow.h"
+#include "dwc_dh.h"
+#include "dwc_crypto.h"
+#include "dwc_notifier.h"
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kthread.h>
+
+MODULE_DESCRIPTION("DWC Common Library - Portable version");
+MODULE_AUTHOR("Synopsys Inc.");
+MODULE_LICENSE ("GPL");
+
+static int dwc_common_port_init_module(void)
+{
+	printk( KERN_DEBUG "Module dwc_common_port init\n" );
+#ifdef DEBUG_MEMORY
+	dwc_memory_debug_start();
+#endif
+	dwc_alloc_notification_manager();
+	return 0;
+}
+
+static void dwc_common_port_exit_module(void)
+{
+	printk( KERN_DEBUG "Module dwc_common_port exit\n" );
+	dwc_free_notification_manager();
+#ifdef DEBUG_MEMORY
+	dwc_memory_debug_stop();
+#endif
+}
+
+module_init(dwc_common_port_init_module);
+module_exit(dwc_common_port_exit_module);
+
+/* CC */
+EXPORT_SYMBOL(dwc_cc_if_alloc);
+EXPORT_SYMBOL(dwc_cc_if_free);
+EXPORT_SYMBOL(dwc_cc_clear);
+EXPORT_SYMBOL(dwc_cc_add);
+EXPORT_SYMBOL(dwc_cc_remove);
+EXPORT_SYMBOL(dwc_cc_change);
+EXPORT_SYMBOL(dwc_cc_data_for_save);
+EXPORT_SYMBOL(dwc_cc_restore_from_data);
+EXPORT_SYMBOL(dwc_cc_match_chid);
+EXPORT_SYMBOL(dwc_cc_match_cdid);
+EXPORT_SYMBOL(dwc_cc_ck);
+EXPORT_SYMBOL(dwc_cc_chid);
+EXPORT_SYMBOL(dwc_cc_cdid);
+EXPORT_SYMBOL(dwc_cc_name);
+
+#ifndef CONFIG_MACH_IPMATE
+/* Modpow */
+EXPORT_SYMBOL(dwc_modpow);
+/* DH */
+EXPORT_SYMBOL(dwc_dh_modpow);
+EXPORT_SYMBOL(dwc_dh_derive_keys);
+EXPORT_SYMBOL(dwc_dh_pk);
+#endif /* CONFIG_MACH_IPMATE  */
+/* Crypto */
+EXPORT_SYMBOL(dwc_wusb_aes_encrypt);
+EXPORT_SYMBOL(dwc_wusb_cmf);
+EXPORT_SYMBOL(dwc_wusb_prf);
+EXPORT_SYMBOL(dwc_wusb_fill_ccm_nonce);
+EXPORT_SYMBOL(dwc_wusb_gen_nonce);
+EXPORT_SYMBOL(dwc_wusb_gen_key);
+EXPORT_SYMBOL(dwc_wusb_gen_mic);
+
+
+/* Notification */
+EXPORT_SYMBOL(dwc_alloc_notification_manager);
+EXPORT_SYMBOL(dwc_free_notification_manager);
+EXPORT_SYMBOL(dwc_register_notifier);
+EXPORT_SYMBOL(dwc_unregister_notifier);
+EXPORT_SYMBOL(dwc_add_observer);
+EXPORT_SYMBOL(dwc_remove_observer);
+EXPORT_SYMBOL(dwc_notify);
+
+/* Memory Debugging Routines */
+#ifdef DEBUG_MEMORY
+EXPORT_SYMBOL(dwc_alloc_debug);
+EXPORT_SYMBOL(dwc_alloc_atomic_debug);
+EXPORT_SYMBOL(dwc_free_debug);
+EXPORT_SYMBOL(dwc_dma_alloc_debug);
+EXPORT_SYMBOL(dwc_dma_alloc_atomic_debug);
+EXPORT_SYMBOL(dwc_dma_free_debug);
+#endif
+
+/* OS-Level Implementations */
+
+/* This is the Linux kernel implementation of the DWC platform library. */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/ctype.h>
+#include <linux/crypto.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/dma-mapping.h>
+#include <linux/cdev.h>
+#include <linux/errno.h>
+#include <linux/interrupt.h>
+#include <linux/jiffies.h>
+#include <linux/list.h>
+#include <linux/pci.h>
+#include <linux/slab.h>
+#include <linux/stat.h>
+#include <linux/string.h>
+#include <linux/timer.h>
+#include <linux/version.h>
+#include <linux/usb.h>
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30))
+#include <linux/usb_gadget.h>
+#else
+#include <linux/usb/gadget.h>
+#endif
+#include <linux/random.h>
+#include <asm/io.h>
+#include <asm/page.h>
+#include <asm/uaccess.h>
+#include <asm/unaligned.h>
+#include <asm/page.h>
+#include <linux/scatterlist.h>
+
+/* MISC */
+
+void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size)
+{
+	return memset(dest, byte, size);
+}
+EXPORT_SYMBOL(DWC_MEMSET);
+
+void *DWC_MEMCPY(void *dest, void const *src, uint32_t size)
+{
+	return memcpy(dest, src, size);
+}
+EXPORT_SYMBOL(DWC_MEMCPY);
+
+void *DWC_MEMMOVE(void *dest, void *src, uint32_t size)
+{
+	return memmove(dest, src, size);
+}
+EXPORT_SYMBOL(DWC_MEMMOVE);
+
+int DWC_MEMCMP(void *m1, void *m2, uint32_t size)
+{
+	return memcmp(m1, m2, size);
+}
+EXPORT_SYMBOL(DWC_MEMCMP);
+
+int DWC_STRNCMP(void *s1, void *s2, uint32_t size)
+{
+	return strncmp(s1, s2, size);
+}
+EXPORT_SYMBOL(DWC_STRNCMP);
+
+int DWC_STRCMP(void *s1, void *s2)
+{
+	return strcmp(s1, s2);
+}
+EXPORT_SYMBOL(DWC_STRCMP);
+
+int DWC_STRLEN(char const *str)
+{
+	return strlen(str);
+}
+EXPORT_SYMBOL(DWC_STRLEN);
+
+char *DWC_STRCPY(char *to, const char *from)
+{
+	return strcpy(to, from);
+}
+EXPORT_SYMBOL(DWC_STRCPY);
+
+char *DWC_STRDUP(char const *str)
+{
+	int len = DWC_STRLEN(str) + 1;
+	char *new = DWC_ALLOC_ATOMIC(len);
+	if (!new) {
+		return NULL;
+	}
+	DWC_MEMCPY(new, str, len);
+	return new;
+}
+EXPORT_SYMBOL(DWC_STRDUP);
+
+int DWC_ATOI(char *str, int32_t *value)
+{
+	char *end = NULL;
+	*value = simple_strtol(str, &end, 0);
+	if (*end == '\0') {
+		return 0;
+	}
+	return -1;
+}
+EXPORT_SYMBOL(DWC_ATOI);
+
+int DWC_ATOUI(char *str, uint32_t *value)
+{
+	char *end = NULL;
+	*value = simple_strtoul(str, &end, 0);
+	if (*end == '\0') {
+		return 0;
+	}
+	return -1;
+}
+EXPORT_SYMBOL(DWC_ATOUI);
+
+
+/* From usbstring.c */
+int DWC_UTF8_TO_UTF16LE(uint8_t const *s, uint16_t *cp, unsigned len)
+{
+	int	count = 0;
+	u8	c;
+	u16	uchar;
+
+	/* this insists on correct encodings, though not minimal ones.
+	 * BUT it currently rejects legit 4-byte UTF-8 code points,
+	 * which need surrogate pairs.  (Unicode 3.1 can use them.)
+	 */
+	while (len != 0 && (c = (u8) *s++) != 0) {
+		if (unlikely(c & 0x80)) {
+			// 2-byte sequence:
+			// 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx
+			if ((c & 0xe0) == 0xc0) {
+				uchar = (c & 0x1f) << 6;
+
+				c = (u8) *s++;
+				if ((c & 0xc0) != 0xc0)
+					goto fail;
+				c &= 0x3f;
+				uchar |= c;
+
+			// 3-byte sequence (most CJKV characters):
+			// zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx
+			} else if ((c & 0xf0) == 0xe0) {
+				uchar = (c & 0x0f) << 12;
+
+				c = (u8) *s++;
+				if ((c & 0xc0) != 0xc0)
+					goto fail;
+				c &= 0x3f;
+				uchar |= c << 6;
+
+				c = (u8) *s++;
+				if ((c & 0xc0) != 0xc0)
+					goto fail;
+				c &= 0x3f;
+				uchar |= c;
+
+				/* no bogus surrogates */
+				if (0xd800 <= uchar && uchar <= 0xdfff)
+					goto fail;
+
+			// 4-byte sequence (surrogate pairs, currently rare):
+			// 11101110wwwwzzzzyy + 110111yyyyxxxxxx
+			//     = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx
+			// (uuuuu = wwww + 1)
+			// FIXME accept the surrogate code points (only)
+
+			} else
+				goto fail;
+		} else
+			uchar = c;
+		put_unaligned (cpu_to_le16 (uchar), cp++);
+		count++;
+		len--;
+	}
+	return count;
+fail:
+	return -1;
+}
+EXPORT_SYMBOL(DWC_UTF8_TO_UTF16LE);
+
+/* dwc_debug.h */
+
+dwc_bool_t DWC_IN_IRQ(void)
+{
+	return in_irq();
+}
+EXPORT_SYMBOL(DWC_IN_IRQ);
+
+int DWC_IN_BH(void)
+{
+	return in_softirq();
+}
+EXPORT_SYMBOL(DWC_IN_BH);
+
+void DWC_VPRINTF(char *format, va_list args)
+{
+	vprintk(format, args);
+}
+EXPORT_SYMBOL(DWC_VPRINTF);
+
+int DWC_VSNPRINTF(char *str, int size, char *format, va_list args)
+{
+	return vsnprintf(str, size, format, args);
+}
+
+void DWC_PRINTF(char *format, ...)
+{
+	va_list args;
+	va_start(args, format);
+	DWC_VPRINTF(format, args);
+	va_end(args);
+}
+EXPORT_SYMBOL(DWC_PRINTF);
+
+int DWC_SPRINTF(char *buffer, char *format, ...)
+{
+	int retval;
+	va_list args;
+	va_start(args, format);
+	retval = vsprintf(buffer, format, args);
+	va_end(args);
+	return retval;
+}
+EXPORT_SYMBOL(DWC_SPRINTF);
+
+int DWC_SNPRINTF(char *buffer, int size, char *format, ...)
+{
+	int retval;
+	va_list args;
+	va_start(args, format);
+	retval = vsnprintf(buffer, size, format, args);
+	va_end(args);
+	return retval;
+}
+EXPORT_SYMBOL(DWC_SNPRINTF);
+
+void __DWC_WARN(char *format, ...)
+{
+	va_list args;
+	va_start(args, format);
+	DWC_PRINTF(KERN_WARNING);
+	DWC_VPRINTF(format, args);
+	va_end(args);
+}
+EXPORT_SYMBOL(__DWC_WARN);
+
+void __DWC_ERROR(char *format, ...)
+{
+	va_list args;
+	va_start(args, format);
+	DWC_PRINTF(KERN_ERR);
+	DWC_VPRINTF(format, args);
+	va_end(args);
+}
+EXPORT_SYMBOL(__DWC_ERROR);
+
+void DWC_EXCEPTION(char *format, ...)
+{
+	va_list args;
+	va_start(args, format);
+	DWC_PRINTF(KERN_ERR);
+	DWC_VPRINTF(format, args);
+	va_end(args);
+	BUG_ON(1);
+}
+EXPORT_SYMBOL(DWC_EXCEPTION);
+
+#ifdef DEBUG
+void __DWC_DEBUG(char *format, ...)
+{
+	va_list args;
+	va_start(args, format);
+	DWC_PRINTF(KERN_DEBUG);
+	DWC_VPRINTF(format, args);
+	va_end(args);
+}
+EXPORT_SYMBOL(__DWC_DEBUG);
+#endif
+
+
+
+/* dwc_mem.h */
+
+#if 0
+dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size,
+				uint32_t align,
+				uint32_t alloc)
+{
+	struct dma_pool *pool = dma_pool_create("Pool", NULL,
+						size, align, alloc);
+	return (dwc_pool_t *)pool;
+}
+
+void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool)
+{
+	dma_pool_destroy((struct dma_pool *)pool);
+}
+
+void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, U64 *dma_addr)
+{
+	return dma_pool_alloc((struct dma_pool *)pool, GFP_KERNEL, dma_addr);
+}
+
+void *DWC_DMA_POOL_ZALLOC(dwc_pool_t *pool, U64 *dma_addr)
+{
+	void *vaddr = DWC_DMA_POOL_ALLOC(pool, dma_addr);
+	memset();
+}
+
+void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr)
+{
+	dma_pool_free(pool, vaddr, daddr);
+}
+
+#endif
+
+void *__DWC_DMA_ALLOC(uint32_t size, dwc_dma_t *dma_addr)
+{
+	void *buf = dma_alloc_coherent(NULL, (size_t)size, dma_addr, GFP_KERNEL);
+	if (!buf) {
+		return NULL;
+	}
+	memset(buf, 0, (size_t)size);
+	return buf;
+}
+EXPORT_SYMBOL(__DWC_DMA_ALLOC);
+
+void __DWC_DMA_FREE(uint32_t size, void *virt_addr, dwc_dma_t dma_addr)
+{
+	dma_free_coherent(NULL, size, virt_addr, dma_addr);
+}
+EXPORT_SYMBOL(__DWC_DMA_FREE);
+
+void *__DWC_DMA_ALLOC_ATOMIC(uint32_t size, dwc_dma_t *dma_addr)
+{
+	void *buf = dma_alloc_coherent(NULL, (size_t)size, dma_addr, GFP_ATOMIC);
+	if (!buf) {
+		return NULL;
+	}
+	memset(buf, 0, (size_t)size);
+	return buf;
+}
+EXPORT_SYMBOL(__DWC_DMA_ALLOC_ATOMIC);
+
+void *__DWC_ALLOC(uint32_t size)
+{
+	return kzalloc(size, GFP_KERNEL);
+}
+EXPORT_SYMBOL(__DWC_ALLOC);
+
+void *__DWC_ALLOC_ATOMIC(uint32_t size)
+{
+	return kzalloc(size, GFP_ATOMIC);
+}
+EXPORT_SYMBOL(__DWC_ALLOC_ATOMIC);
+
+void __DWC_FREE(void *addr)
+{
+	kfree(addr);
+}
+EXPORT_SYMBOL(__DWC_FREE);
+
+/* dwc_crypto.h */
+
+void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length)
+{
+	get_random_bytes(buffer, length);
+}
+EXPORT_SYMBOL(DWC_RANDOM_BYTES);
+
+int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out)
+{
+	struct crypto_blkcipher *tfm;
+	struct blkcipher_desc desc;
+	struct scatterlist sgd;
+	struct scatterlist sgs;
+
+	tfm = crypto_alloc_blkcipher("cbc(aes)", 0, CRYPTO_ALG_ASYNC);
+	if (tfm == NULL) {
+		printk("failed to load transform for aes CBC\n");
+		return -1;
+	}
+
+	crypto_blkcipher_setkey(tfm, key, keylen);
+	crypto_blkcipher_set_iv(tfm, iv, 16);
+
+	sg_init_one(&sgd, out, messagelen);
+	sg_init_one(&sgs, message, messagelen);
+
+	desc.tfm = tfm;
+	desc.flags = 0;
+
+	if(crypto_blkcipher_encrypt(&desc, &sgd, &sgs, messagelen)) {
+		crypto_free_blkcipher(tfm);
+		DWC_ERROR("AES CBC encryption failed");
+		return -1;
+	}
+
+	crypto_free_blkcipher(tfm);
+	return 0;
+}
+EXPORT_SYMBOL(DWC_AES_CBC);
+
+int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out)
+{
+	struct crypto_hash *tfm;
+	struct hash_desc desc;
+	struct scatterlist sg;
+
+	tfm = crypto_alloc_hash("sha256", 0, CRYPTO_ALG_ASYNC);
+	if (IS_ERR(tfm)) {
+		DWC_ERROR("Failed to load transform for sha256: %ld\n", PTR_ERR(tfm));
+		return 0;
+	}
+	desc.tfm = tfm;
+	desc.flags = 0;
+
+	sg_init_one(&sg, message, len);
+	crypto_hash_digest(&desc, &sg, len, out);
+	crypto_free_hash(tfm);
+
+	return 1;
+}
+EXPORT_SYMBOL(DWC_SHA256);
+
+int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen,
+		    uint8_t *key, uint32_t keylen, uint8_t *out)
+{
+	struct crypto_hash *tfm;
+	struct hash_desc desc;
+	struct scatterlist sg;
+
+	tfm = crypto_alloc_hash("hmac(sha256)", 0, CRYPTO_ALG_ASYNC);
+	if (IS_ERR(tfm)) {
+		DWC_ERROR("Failed to load transform for hmac(sha256): %ld\n", PTR_ERR(tfm));
+		return 0;
+	}
+	desc.tfm = tfm;
+	desc.flags = 0;
+
+	sg_init_one(&sg, message, messagelen);
+	crypto_hash_setkey(tfm, key, keylen);
+	crypto_hash_digest(&desc, &sg, messagelen, out);
+	crypto_free_hash(tfm);
+
+	return 1;
+}
+EXPORT_SYMBOL(DWC_HMAC_SHA256);
+
+/* Byte Ordering Conversions. */
+uint32_t DWC_CPU_TO_LE32(void *p)
+{
+#ifdef __LITTLE_ENDIAN
+	return *((uint32_t *)p);
+#else
+	uint8_t *u_p = (uint8_t *)p;
+
+	return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
+#endif
+}
+EXPORT_SYMBOL(DWC_CPU_TO_LE32);
+
+uint32_t DWC_CPU_TO_BE32(void *p)
+{
+#ifdef __BIG_ENDIAN
+	return *((uint32_t *)p);
+#else
+	uint8_t *u_p = (uint8_t *)p;
+
+	return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
+#endif
+}
+EXPORT_SYMBOL(DWC_CPU_TO_BE32);
+
+uint32_t DWC_LE32_TO_CPU(void *p)
+{
+#ifdef __LITTLE_ENDIAN
+	return *((uint32_t *)p);
+#else
+	uint8_t *u_p = (uint8_t *)p;
+
+	return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
+
+#endif
+}
+EXPORT_SYMBOL(DWC_LE32_TO_CPU);
+
+uint32_t DWC_BE32_TO_CPU(void *p)
+{
+#ifdef __BIG_ENDIAN
+	return *((uint32_t *)p);
+#else
+	uint8_t *u_p = (uint8_t *)p;
+
+	return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
+#endif
+}
+EXPORT_SYMBOL(DWC_BE32_TO_CPU);
+
+uint16_t DWC_CPU_TO_LE16(void *p)
+{
+#ifdef __LITTLE_ENDIAN
+	return *((uint16_t *)p);
+#else
+	uint8_t *u_p = (uint8_t *)p;
+	return (u_p[1] | (u_p[0] << 8));
+#endif
+}
+EXPORT_SYMBOL(DWC_CPU_TO_LE16);
+
+uint16_t DWC_CPU_TO_BE16(void *p)
+{
+#ifdef __BIG_ENDIAN
+	return *((uint16_t *)p);
+#else
+	uint8_t *u_p = (uint8_t *)p;
+	return (u_p[1] | (u_p[0] << 8));
+#endif
+}
+EXPORT_SYMBOL(DWC_CPU_TO_BE16);
+
+uint16_t DWC_LE16_TO_CPU(void *p)
+{
+#ifdef __LITTLE_ENDIAN
+	return *((uint16_t *)p);
+#else
+	uint8_t *u_p = (uint8_t *)p;
+	return (u_p[1] | (u_p[0] << 8));
+#endif
+}
+EXPORT_SYMBOL(DWC_LE16_TO_CPU);
+
+uint16_t DWC_BE16_TO_CPU(void *p)
+{
+#ifdef __BIG_ENDIAN
+	return *((uint16_t *p)p);
+#else
+	uint8_t *u_p = (uint8_t *)p;
+	return (u_p[1] | (u_p[0] << 8));
+#endif
+}
+EXPORT_SYMBOL(DWC_BE16_TO_CPU);
+
+
+/* Registers */
+
+uint32_t DWC_READ_REG32(uint32_t volatile *reg)
+{
+	return readl(reg);
+}
+EXPORT_SYMBOL(DWC_READ_REG32);
+
+#if 0
+uint64_t DWC_READ_REG64(uint64_t volatile *reg)
+{
+}
+#endif
+
+void DWC_WRITE_REG32(uint32_t volatile *reg, uint32_t value)
+{
+	writel(value, reg);
+}
+EXPORT_SYMBOL(DWC_WRITE_REG32);
+
+#if 0
+void DWC_WRITE_REG64(uint64_t volatile *reg, uint64_t value)
+{
+}
+#endif
+
+void DWC_MODIFY_REG32(uint32_t volatile *reg, uint32_t clear_mask, uint32_t set_mask)
+{
+	writel( (readl(reg) & ~clear_mask) | set_mask, reg );
+}
+EXPORT_SYMBOL(DWC_MODIFY_REG32);
+
+#if 0
+void DWC_MODIFY_REG64(uint64_t volatile *reg, uint64_t value)
+{
+}
+#endif
+
+
+
+/* Threading */
+
+typedef struct work_container
+{
+	dwc_work_callback_t cb;
+	void *data;
+	dwc_workq_t *wq;
+	char *name;
+
+#ifdef DEBUG
+	DWC_CIRCLEQ_ENTRY(work_container) entry;
+#endif
+
+	struct delayed_work work;
+} work_container_t;
+
+#ifdef DEBUG
+DWC_CIRCLEQ_HEAD(work_container_queue, work_container);
+#endif
+
+struct dwc_workq
+{
+	struct workqueue_struct *wq;
+	int pending;
+	dwc_spinlock_t *lock;
+	dwc_waitq_t *waitq;
+
+#ifdef DEBUG
+	struct work_container_queue entries;
+#endif
+};
+
+static void do_work(struct work_struct *work)
+{
+	int64_t flags;
+	struct delayed_work *dw = container_of(work, struct delayed_work, work);
+	work_container_t *container = container_of(dw, struct work_container, work);
+	dwc_workq_t *wq = container->wq;
+
+	container->cb(container->data);
+
+#ifdef DEBUG
+	DWC_CIRCLEQ_REMOVE(&wq->entries, container, entry);
+#endif
+
+	if (container->name) {
+        	DWC_DEBUG("Work done: %s, container=%p",
+                          container->name, container); //GRAYG
+		DWC_FREE(container->name);
+	}
+	DWC_FREE(container);
+
+	DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
+	wq->pending --;
+	DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
+	DWC_WAITQ_TRIGGER(wq->waitq);
+}
+
+static int work_done(void *data)
+{
+	dwc_workq_t *workq = (dwc_workq_t *)data;
+	return workq->pending == 0;
+}
+
+int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout)
+{
+	return DWC_WAITQ_WAIT_TIMEOUT(workq->waitq, work_done, workq, timeout);
+}
+EXPORT_SYMBOL(DWC_WORKQ_WAIT_WORK_DONE);
+
+dwc_workq_t *DWC_WORKQ_ALLOC(char *name)
+{
+	dwc_workq_t *wq = DWC_ALLOC(sizeof(*wq));
+	wq->wq = create_singlethread_workqueue(name);
+	wq->pending = 0;
+	wq->lock = DWC_SPINLOCK_ALLOC();
+	wq->waitq = DWC_WAITQ_ALLOC();
+#ifdef DEBUG
+	DWC_CIRCLEQ_INIT(&wq->entries);
+#endif
+	return wq;
+}
+EXPORT_SYMBOL(DWC_WORKQ_ALLOC);
+
+void DWC_WORKQ_FREE(dwc_workq_t *wq)
+{
+#ifdef DEBUG
+	if (wq->pending != 0) {
+		struct work_container *wc;
+		DWC_ERROR("Destroying work queue with pending work");
+		DWC_CIRCLEQ_FOREACH(wc, &wq->entries, entry) {
+			DWC_ERROR("Work %s still pending", wc->name);
+		}
+	}
+#endif
+	destroy_workqueue((struct workqueue_struct *)wq->wq);
+	DWC_SPINLOCK_FREE(wq->lock);
+	DWC_WAITQ_FREE(wq->waitq);
+	DWC_FREE(wq);
+}
+EXPORT_SYMBOL(DWC_WORKQ_FREE);
+
+void DWC_WORKQ_SCHEDULE(dwc_workq_t *wq, dwc_work_callback_t work_cb, void *data, char *format, ...)
+{
+	int64_t flags;
+	work_container_t *container;
+	static char name[128];
+
+	va_list args;
+	va_start(args, format);
+        if (format)
+        	DWC_VSNPRINTF(name, 128, format, args);
+	va_end(args);
+
+	DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
+	wq->pending ++;
+	DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
+	DWC_WAITQ_TRIGGER(wq->waitq);
+
+	container = DWC_ALLOC_ATOMIC(sizeof(*container));
+
+	container->data = data;
+	container->cb = work_cb;
+	container->wq = wq;
+        if (format) {
+                container->name = DWC_STRDUP(name);
+                DWC_DEBUG("Queueing work: %s, contianer=%p",
+                          container->name, container);
+        } else
+                container->name = NULL;
+        
+	INIT_WORK(&container->work.work, do_work);
+
+#ifdef DEBUG
+	DWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry);
+#endif
+
+	queue_work(wq->wq, &container->work.work);
+
+}
+EXPORT_SYMBOL(DWC_WORKQ_SCHEDULE);
+
+void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *wq, dwc_work_callback_t work_cb, void *data, uint32_t time, char *format, ...)
+{
+	int64_t flags;
+	work_container_t *container;
+	static char name[128];
+
+	va_list args;
+	va_start(args, format);
+        if (format)
+        	DWC_VSNPRINTF(name, 128, format, args);
+	va_end(args);
+
+	DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
+	wq->pending ++;
+	DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
+	DWC_WAITQ_TRIGGER(wq->waitq);
+
+	container = DWC_ALLOC_ATOMIC(sizeof(*container));
+
+	container->data = data;
+	container->cb = work_cb;
+	container->wq = wq;
+        if (format) { //GRAYG
+        	container->name = DWC_STRDUP(name);
+                DWC_DEBUG("Queueing work: %s, contianer=%p",
+                          container->name, container);
+        } else
+           container->name = NULL;
+	INIT_DELAYED_WORK(&container->work, do_work);
+
+#ifdef DEBUG
+	DWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry);
+#endif
+
+	queue_delayed_work(wq->wq, &container->work, msecs_to_jiffies(time));
+
+}
+EXPORT_SYMBOL(DWC_WORKQ_SCHEDULE_DELAYED);
+
+
+int DWC_WORKQ_PENDING(dwc_workq_t *wq)
+{
+	return wq->pending;
+}
+EXPORT_SYMBOL(DWC_WORKQ_PENDING);
+
+dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void)
+{
+	spinlock_t *sl = (spinlock_t *)1;
+#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)
+	sl = DWC_ALLOC(sizeof(*sl));
+	spin_lock_init(sl);
+#endif
+	return (dwc_spinlock_t *)sl;
+}
+EXPORT_SYMBOL(DWC_SPINLOCK_ALLOC);
+
+void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock)
+{
+#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)
+	DWC_FREE(lock);
+#endif
+}
+EXPORT_SYMBOL(DWC_SPINLOCK_FREE);
+
+void DWC_SPINLOCK(dwc_spinlock_t *lock)
+{
+#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)
+	spin_lock((spinlock_t *)lock);
+#endif
+}
+EXPORT_SYMBOL(DWC_SPINLOCK);
+
+void DWC_SPINUNLOCK(dwc_spinlock_t *lock)
+{
+#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)
+	spin_unlock((spinlock_t *)lock);
+#endif
+}
+EXPORT_SYMBOL(DWC_SPINUNLOCK);
+
+void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, uint64_t *flags)
+{
+	unsigned long f;
+#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)
+        spin_lock_irqsave((spinlock_t *)lock, f);
+#else
+	local_irq_save(f);
+#endif
+        *flags = f;
+}
+EXPORT_SYMBOL(DWC_SPINLOCK_IRQSAVE);
+
+void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, uint64_t flags)
+{
+#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)
+        spin_unlock_irqrestore((spinlock_t *)lock, flags);
+#else
+        // in kernel 2.6.31, at least, we check for unsigned long
+        local_irq_restore((unsigned long)flags);
+#endif
+}
+EXPORT_SYMBOL(DWC_SPINUNLOCK_IRQRESTORE);
+
+dwc_mutex_t *DWC_MUTEX_ALLOC(void)
+{
+	dwc_mutex_t *mutex = (dwc_mutex_t*)DWC_ALLOC(sizeof(struct mutex));
+	struct mutex *m = (struct mutex *)mutex;
+	mutex_init(m);
+	return mutex;
+}
+EXPORT_SYMBOL(DWC_MUTEX_ALLOC);
+
+#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES))
+#else
+void DWC_MUTEX_FREE(dwc_mutex_t *mutex)
+{
+	mutex_destroy((struct mutex *)mutex);
+	DWC_FREE(mutex);
+}
+EXPORT_SYMBOL(DWC_MUTEX_FREE);
+#endif
+
+void DWC_MUTEX_LOCK(dwc_mutex_t *mutex)
+{
+	struct mutex *m = (struct mutex *)mutex;
+	mutex_lock(m);
+}
+EXPORT_SYMBOL(DWC_MUTEX_LOCK);
+
+int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex)
+{
+	struct mutex *m = (struct mutex *)mutex;
+	return mutex_trylock(m);
+}
+EXPORT_SYMBOL(DWC_MUTEX_TRYLOCK);
+
+void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex)
+{
+	struct mutex *m = (struct mutex *)mutex;
+	mutex_unlock(m);
+}
+EXPORT_SYMBOL(DWC_MUTEX_UNLOCK);
+
+dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t thread_function, char *name, void *data)
+{
+	struct task_struct *thread = kthread_run(thread_function, data, name);
+	if (thread == ERR_PTR(-ENOMEM)) {
+		return NULL;
+	}
+	return (dwc_thread_t *)thread;
+}
+EXPORT_SYMBOL(DWC_THREAD_RUN);
+
+int DWC_THREAD_STOP(dwc_thread_t *thread)
+{
+	return kthread_stop((struct task_struct *)thread);
+}
+EXPORT_SYMBOL(DWC_THREAD_STOP);
+
+dwc_bool_t DWC_THREAD_SHOULD_STOP()
+{
+	return kthread_should_stop();
+}
+EXPORT_SYMBOL(DWC_THREAD_SHOULD_STOP);
+
+/* Timers */
+
+struct dwc_timer
+{
+	struct timer_list *t;
+	char *name;
+	dwc_timer_callback_t cb;
+	void *data;
+	uint8_t scheduled;
+	dwc_spinlock_t *lock;
+};
+
+static void set_scheduled(dwc_timer_t *t, int s)
+{
+	uint64_t flags;
+	DWC_SPINLOCK_IRQSAVE(t->lock, &flags);
+	t->scheduled = s;
+	DWC_SPINUNLOCK_IRQRESTORE(t->lock, flags);
+}
+
+static int get_scheduled(dwc_timer_t *t)
+{
+	int s;
+	uint64_t flags;
+	DWC_SPINLOCK_IRQSAVE(t->lock, &flags);
+	s = t->scheduled;
+	DWC_SPINUNLOCK_IRQRESTORE(t->lock, flags);
+	return s;
+}
+
+static void timer_callback(unsigned long data)
+{
+	dwc_timer_t *timer = (dwc_timer_t *)data;
+	set_scheduled(timer, 0);
+	DWC_DEBUG("Timer %s callback", timer->name);
+	timer->cb(timer->data);
+}
+
+dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data)
+{
+	dwc_timer_t *t = DWC_ALLOC(sizeof(*t));
+	if (!t) {
+		DWC_ERROR("Cannot allocate memory for timer");
+		return NULL;
+	}
+	t->t = DWC_ALLOC(sizeof(*t->t));
+	if (!t->t) {
+		DWC_ERROR("Cannot allocate memory for timer->t");
+		goto no_timer;
+	}
+
+	t->name = DWC_STRDUP(name);
+	if (!t->name) {
+		DWC_ERROR("Cannot allocate memory for timer->name");
+		goto no_name;
+	}
+
+	t->lock = DWC_SPINLOCK_ALLOC();
+	if (!t->lock) {
+		DWC_ERROR("Cannot allocate memory for lock");
+		goto no_lock;
+	}
+	t->scheduled = 0;
+	t->t->base = &boot_tvec_bases;
+	t->t->expires = jiffies;
+	setup_timer(t->t, timer_callback, (unsigned long)t);
+
+	t->cb = cb;
+	t->data = data;
+
+	return t;
+
+ no_lock:
+	DWC_FREE(t->name);
+ no_name:
+	DWC_FREE(t->t);
+ no_timer:
+	DWC_FREE(t);
+	return NULL;
+}
+EXPORT_SYMBOL(DWC_TIMER_ALLOC);
+
+void DWC_TIMER_FREE(dwc_timer_t *timer)
+{
+	if (get_scheduled(timer)) {
+		del_timer(timer->t);
+	}
+
+	DWC_SPINLOCK_FREE(timer->lock);
+	DWC_FREE(timer->t);
+	DWC_FREE(timer->name);
+	DWC_FREE(timer);
+}
+EXPORT_SYMBOL(DWC_TIMER_FREE);
+
+void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time)
+{
+	if (!get_scheduled(timer)) {
+		set_scheduled(timer, 1);
+		//cgg: DWC_DEBUG("Scheduling timer %s to expire in +%d msec", timer->name, time);
+		timer->t->expires = jiffies + msecs_to_jiffies(time);
+		add_timer(timer->t);
+	}
+	else {
+                //cgg: DWC_DEBUG("Modifying timer %s to expire in +%d msec", timer->name, time);
+		mod_timer(timer->t, jiffies + msecs_to_jiffies(time));
+	}
+}
+EXPORT_SYMBOL(DWC_TIMER_SCHEDULE);
+
+void DWC_TIMER_CANCEL(dwc_timer_t *timer)
+{
+	del_timer(timer->t);
+}
+EXPORT_SYMBOL(DWC_TIMER_CANCEL);
+
+struct dwc_tasklet
+{
+	struct tasklet_struct t;
+	dwc_tasklet_callback_t cb; 
+	void *data;
+};
+
+static void tasklet_callback(unsigned long data)
+{
+	dwc_tasklet_t *t = (dwc_tasklet_t *)data;
+	t->cb(t->data);
+}
+
+dwc_tasklet_t *DWC_TASK_ALLOC(dwc_tasklet_callback_t cb, void *data)
+{
+	dwc_tasklet_t *t = DWC_ALLOC(sizeof(*t));
+	
+	if(t) {
+		t->data = data;
+		t->cb = cb;
+		tasklet_init(&t->t, tasklet_callback, (unsigned long)t);
+	} else {
+		DWC_ERROR("Cannot allocate memory for tasklet\n");
+	}
+	
+	return t;
+}
+EXPORT_SYMBOL(DWC_TASK_ALLOC);
+
+void DWC_TASK_FREE(dwc_tasklet_t *t)
+{
+	DWC_FREE(t);
+}
+EXPORT_SYMBOL(DWC_TASK_FREE);
+
+void DWC_TASK_SCHEDULE(dwc_tasklet_t *task)
+{
+	tasklet_schedule(&task->t);
+}
+EXPORT_SYMBOL(DWC_TASK_SCHEDULE);
+
+/* Timing */
+
+void DWC_UDELAY(uint32_t usecs)
+{
+	udelay(usecs);
+}
+EXPORT_SYMBOL(DWC_UDELAY);
+
+void DWC_MDELAY(uint32_t msecs)
+{
+	mdelay(msecs);
+}
+EXPORT_SYMBOL(DWC_MDELAY);
+
+void DWC_MSLEEP(uint32_t msecs)
+{
+	msleep(msecs);
+}
+EXPORT_SYMBOL(DWC_MSLEEP);
+
+uint32_t DWC_TIME(void)
+{
+	return jiffies_to_msecs(jiffies);
+}
+EXPORT_SYMBOL(DWC_TIME);
+
+
+/* Wait Queues */
+
+struct dwc_waitq
+{
+	wait_queue_head_t queue;
+	int abort;
+};
+
+dwc_waitq_t *DWC_WAITQ_ALLOC(void)
+{
+	dwc_waitq_t *wq = DWC_ALLOC(sizeof(*wq));
+	init_waitqueue_head(&wq->queue);
+	wq->abort = 0;
+	return wq;
+}
+EXPORT_SYMBOL(DWC_WAITQ_ALLOC);
+
+void DWC_WAITQ_FREE(dwc_waitq_t *wq)
+{
+	DWC_FREE(wq);
+}
+EXPORT_SYMBOL(DWC_WAITQ_FREE);
+
+static int32_t check_result(dwc_waitq_t *wq, int result)
+{	int32_t msecs;
+	if (result > 0) {
+		msecs = jiffies_to_msecs(result);
+		if (!msecs) {
+			return 1;
+		}
+		return msecs;
+	}
+
+	if (result == 0) {
+		return -DWC_E_TIMEOUT;
+	}
+
+	if ((result == -ERESTARTSYS) || (wq->abort == 1)) {
+		return -DWC_E_ABORT;
+	}
+
+	return -DWC_E_UNKNOWN;
+}
+
+int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t condition, void *data)
+{
+	int result = wait_event_interruptible(wq->queue,
+						  condition(data) || wq->abort);
+	return check_result(wq, result);
+}
+EXPORT_SYMBOL(DWC_WAITQ_WAIT);
+
+int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t condition,
+			       void *data, int32_t msecs)
+{
+	int result = wait_event_interruptible_timeout(wq->queue,
+							  condition(data) || wq->abort,
+							  msecs_to_jiffies(msecs));
+	return check_result(wq, result);
+}
+EXPORT_SYMBOL(DWC_WAITQ_WAIT_TIMEOUT);
+
+void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq)
+{
+	wake_up_interruptible(&wq->queue);
+}
+EXPORT_SYMBOL(DWC_WAITQ_TRIGGER);
+
+void DWC_WAITQ_ABORT(dwc_waitq_t *wq)
+{
+	wq->abort = 1;
+	DWC_WAITQ_TRIGGER(wq);
+}
+EXPORT_SYMBOL(DWC_WAITQ_ABORT);
diff --git a/drivers/usb/host/dwc_common_port/dwc_crypto.c b/drivers/usb/host/dwc_common_port/dwc_crypto.c
new file mode 100644
index 000000000000..747840e653a2
--- /dev/null
+++ b/drivers/usb/host/dwc_common_port/dwc_crypto.c
@@ -0,0 +1,306 @@
+/* =========================================================================
+ * $File: //dwh/usb_iip/dev/software/dwc_common_port/dwc_crypto.c $
+ * $Revision: #1 $
+ * $Date: 2008/12/21 $
+ * $Change: 1156609 $
+ *
+ * Synopsys Portability Library Software and documentation
+ * (hereinafter, "Software") is an Unsupported proprietary work of
+ * Synopsys, Inc. unless otherwise expressly agreed to in writing
+ * between Synopsys and you.
+ *
+ * The Software IS NOT an item of Licensed Software or Licensed Product
+ * under any End User Software License Agreement or Agreement for
+ * Licensed Product with Synopsys or any supplement thereto. You are
+ * permitted to use and redistribute this Software in source and binary
+ * forms, with or without modification, provided that redistributions
+ * of source code must retain this notice. You may not view, use,
+ * disclose, copy or distribute this file or any information contained
+ * herein except pursuant to this license grant from Synopsys. If you
+ * do not agree with this notice, including the disclaimer below, then
+ * you are not authorized to use the Software.
+ *
+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
+ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
+ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ * ========================================================================= */
+
+/** @file
+ * This file contains the WUSB cryptographic routines.
+ */
+
+#include "dwc_crypto.h"
+#include "usb.h"
+
+#ifdef DEBUG
+static inline void dump_bytes(char *name, uint8_t *bytes, int len)
+{
+	int i;
+	DWC_PRINTF("%s: ", name);
+	for (i=0; i<len; i++) {
+		DWC_PRINTF("%02x ", bytes[i]);
+	}
+	DWC_PRINTF("\n");
+}
+#else
+#define dump_bytes(x...)
+#endif
+
+/* Display a block */
+void show_block(const u8 *blk, const char *prefix, const char *suffix, int a)
+{
+#ifdef DEBUG_CRYPTO
+	int i, blksize = 16;
+
+	DWC_DEBUG("%s", prefix);
+
+	if (suffix == NULL) {
+		suffix = "\n";
+		blksize = a;
+	}
+
+	for (i = 0; i < blksize; i++)
+		DWC_PRINT("%02x%s", *blk++, ((i & 3) == 3) ? "  " : " ");
+	DWC_PRINT(suffix);
+
+#endif
+}
+
+/**
+ * Encrypts an array of bytes using the AES encryption engine.
+ * If <code>dst</code> == <code>src</code>, then the bytes will be encrypted
+ * in-place.
+ *
+ * @return  0 on success, negative error code on error.
+ */
+int dwc_wusb_aes_encrypt(u8 *src, u8 *key, u8 *dst)
+{
+	u8 block_t[16];
+	DWC_MEMSET(block_t, 0, 16);
+
+	return DWC_AES_CBC(src, 16, key, 16, block_t, dst);
+}
+
+/**
+ * The CCM-MAC-FUNCTION described in section 6.5 of the WUSB spec.
+ * This function takes a data string and returns the encrypted CBC
+ * Counter-mode MIC.
+ *
+ * @param key     The 128-bit symmetric key.
+ * @param nonce   The CCM nonce.
+ * @param label   The unique 14-byte ASCII text label.
+ * @param bytes   The byte array to be encrypted.
+ * @param len     Length of the byte array.
+ * @param result  Byte array to receive the 8-byte encrypted MIC.
+ */
+void dwc_wusb_cmf(u8 *key, u8 *nonce,
+		  char *label, u8 *bytes, int len, u8 *result)
+{
+	u8 block_m[16];
+	u8 block_x[16];
+	u8 block_t[8];
+	int idx, blkNum;
+	u16 la = (u16)(len + 14);
+
+	/* Set the AES-128 key */
+	//dwc_aes_setkey(tfm, key, 16);
+
+	/* Fill block B0 from flags = 0x59, N, and l(m) = 0 */
+	block_m[0] = 0x59;
+	for (idx = 0; idx < 13; idx++)
+		block_m[idx + 1] = nonce[idx];
+	block_m[14] = 0;
+	block_m[15] = 0;
+
+	/* Produce the CBC IV */
+	dwc_wusb_aes_encrypt(block_m, key, block_x);
+	show_block(block_m, "CBC IV in: ", "\n", 0);
+	show_block(block_x, "CBC IV out:", "\n", 0);
+
+	/* Fill block B1 from l(a) = Blen + 14, and A */
+	block_x[0] ^= (u8)(la >> 8);
+	block_x[1] ^= (u8)la;
+	for (idx = 0; idx < 14; idx++)
+		block_x[idx + 2] ^= label[idx];
+	show_block(block_x, "After xor: ", "b1\n", 16);
+
+	dwc_wusb_aes_encrypt(block_x, key, block_x);
+	show_block(block_x, "After AES: ", "b1\n", 16);
+
+	idx = 0;
+	blkNum = 0;
+
+	/* Fill remaining blocks with B */
+	while (len-- > 0) {
+		block_x[idx] ^= *bytes++;
+		if (++idx >= 16) {
+			idx = 0;
+			show_block(block_x, "After xor: ", "\n", blkNum);
+			dwc_wusb_aes_encrypt(block_x, key, block_x);
+			show_block(block_x, "After AES: ", "\n", blkNum);
+			blkNum++;
+		}
+	}
+
+	/* Handle partial last block */
+	if (idx > 0) {
+		show_block(block_x, "After xor: ", "\n", blkNum);
+		dwc_wusb_aes_encrypt(block_x, key, block_x);
+		show_block(block_x, "After AES: ", "\n", blkNum);
+	}
+
+	/* Save the MIC tag */
+	DWC_MEMCPY(block_t, block_x, 8);
+	show_block(block_t, "MIC tag  : ", NULL, 8);
+
+	/* Fill block A0 from flags = 0x01, N, and counter = 0 */
+	block_m[0] = 0x01;
+	block_m[14] = 0;
+	block_m[15] = 0;
+
+	/* Encrypt the counter */
+	dwc_wusb_aes_encrypt(block_m, key, block_x);
+	show_block(block_x, "CTR[MIC] : ", NULL, 8);
+
+	/* XOR with MIC tag */
+	for (idx = 0; idx < 8; idx++) {
+		block_t[idx] ^= block_x[idx];
+	}
+
+	/* Return result to caller */
+	DWC_MEMCPY(result, block_t, 8);
+	show_block(result, "CCM-MIC  : ", NULL, 8);
+
+}
+
+/**
+ * The PRF function described in section 6.5 of the WUSB spec. This function
+ * concatenates MIC values returned from dwc_cmf() to create a value of
+ * the requested length.
+ *
+ * @param prf_len  Length of the PRF function in bits (64, 128, or 256).
+ * @param key, nonce, label, bytes, len  Same as for dwc_cmf().
+ * @param result   Byte array to receive the result.
+ */
+void dwc_wusb_prf(int prf_len, u8 *key,
+		  u8 *nonce, char *label, u8 *bytes, int len, u8 *result)
+{
+	int i;
+
+	nonce[0] = 0;
+	for (i = 0; i < prf_len >> 6; i++, nonce[0]++) {
+		dwc_wusb_cmf(key, nonce, label, bytes, len, result);
+		result += 8;
+	}
+}
+
+/**
+ * Fills in CCM Nonce per the WUSB spec.
+ *
+ * @param[in] haddr Host address.
+ * @param[in] daddr Device address.
+ * @param[in] tkid Session Key(PTK) identifier.
+ * @param[out] nonce Pointer to where the CCM Nonce output is to be written.
+ */
+void dwc_wusb_fill_ccm_nonce(uint16_t haddr, uint16_t daddr, uint8_t *tkid,
+			     uint8_t *nonce)
+{
+
+	DWC_DEBUG("%s %x %x\n", __func__, daddr, haddr);
+
+	DWC_MEMSET(&nonce[0], 0, 16);
+
+	DWC_MEMCPY(&nonce[6], tkid, 3);
+	nonce[9] = daddr & 0xFF;
+	nonce[10] = (daddr >> 8) & 0xFF;
+	nonce[11] = haddr & 0xFF;
+	nonce[12] = (haddr >> 8) & 0xFF;
+
+	dump_bytes("CCM nonce", nonce, 16);
+}
+
+/**
+ * Generates a 16-byte cryptographic-grade random number for the Host/Device
+ * Nonce.
+ */
+void dwc_wusb_gen_nonce(uint16_t addr, uint8_t *nonce)
+{
+	uint8_t inonce[16];
+	uint32_t temp[4];
+
+	/* Fill in the Nonce */
+	DWC_MEMSET(&inonce[0], 0, sizeof(inonce));
+	inonce[9] = addr & 0xFF;
+	inonce[10] = (addr >> 8) & 0xFF;
+	inonce[11] = inonce[9];
+	inonce[12] = inonce[10];
+
+	/* Collect "randomness samples" */
+	DWC_RANDOM_BYTES((uint8_t *)temp, 16);
+
+	dwc_wusb_prf_128((uint8_t *)temp, nonce,
+			 "Random Numbers", (uint8_t *)temp, sizeof(temp),
+			 nonce);
+}
+
+/**
+ * Generates the Session Key (PTK) and Key Confirmation Key (KCK) per the
+ * WUSB spec.
+ *
+ * @param[in] ccm_nonce Pointer to CCM Nonce.
+ * @param[in] mk Master Key to derive the session from
+ * @param[in] hnonce Pointer to Host Nonce.
+ * @param[in] dnonce Pointer to Device Nonce.
+ * @param[out] kck Pointer to where the KCK output is to be written.
+ * @param[out] ptk Pointer to where the PTK output is to be written.
+ */
+void dwc_wusb_gen_key(uint8_t *ccm_nonce, uint8_t *mk, uint8_t *hnonce,
+		      uint8_t *dnonce, uint8_t *kck, uint8_t *ptk)
+{
+	uint8_t idata[32];
+	uint8_t odata[32];
+
+	dump_bytes("ck", mk, 16);
+	dump_bytes("hnonce", hnonce, 16);
+	dump_bytes("dnonce", dnonce, 16);
+
+	/* The data is the HNonce and DNonce concatenated */
+	DWC_MEMCPY(&idata[0], hnonce, 16);
+	DWC_MEMCPY(&idata[16], dnonce, 16);
+
+	dwc_wusb_prf_256(mk, ccm_nonce, "Pair-wise keys", idata, 32, odata);
+
+	/* Low 16 bytes of the result is the KCK, high 16 is the PTK */
+	DWC_MEMCPY(kck, &odata[0], 16);
+	DWC_MEMCPY(ptk, &odata[16], 16);
+
+	dump_bytes("kck", kck, 16);
+	dump_bytes("ptk", ptk, 16);
+}
+
+/**
+ * Generates the Message Integrity Code over the Handshake data per the
+ * WUSB spec.
+ *
+ * @param ccm_nonce Pointer to CCM Nonce.
+ * @param kck   Pointer to Key Confirmation Key.
+ * @param data  Pointer to Handshake data to be checked.
+ * @param mic   Pointer to where the MIC output is to be written.
+ */
+void dwc_wusb_gen_mic(uint8_t *ccm_nonce, uint8_t *kck,
+		      uint8_t *data, uint8_t *mic)
+{
+
+	dwc_wusb_prf_64(kck, ccm_nonce, "out-of-bandMIC",
+			data, WUSB_HANDSHAKE_LEN_FOR_MIC, mic);
+}
+
diff --git a/drivers/usb/host/dwc_common_port/dwc_crypto.h b/drivers/usb/host/dwc_common_port/dwc_crypto.h
new file mode 100644
index 000000000000..219d9619afd1
--- /dev/null
+++ b/drivers/usb/host/dwc_common_port/dwc_crypto.h
@@ -0,0 +1,103 @@
+/* =========================================================================
+ * $File: //dwh/usb_iip/dev/software/dwc_common_port/dwc_crypto.h $
+ * $Revision: #1 $
+ * $Date: 2008/12/21 $
+ * $Change: 1156609 $
+ *
+ * Synopsys Portability Library Software and documentation
+ * (hereinafter, "Software") is an Unsupported proprietary work of
+ * Synopsys, Inc. unless otherwise expressly agreed to in writing
+ * between Synopsys and you.
+ *
+ * The Software IS NOT an item of Licensed Software or Licensed Product
+ * under any End User Software License Agreement or Agreement for
+ * Licensed Product with Synopsys or any supplement thereto. You are
+ * permitted to use and redistribute this Software in source and binary
+ * forms, with or without modification, provided that redistributions
+ * of source code must retain this notice. You may not view, use,
+ * disclose, copy or distribute this file or any information contained
+ * herein except pursuant to this license grant from Synopsys. If you
+ * do not agree with this notice, including the disclaimer below, then
+ * you are not authorized to use the Software.
+ *
+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
+ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
+ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ * ========================================================================= */
+
+#ifndef _DWC_CRYPTO_H_
+#define _DWC_CRYPTO_H_
+
+/** @file
+ *
+ * This file contains declarations for the WUSB Cryptographic routines as
+ * defined in the WUSB spec.  They are only to be used internally by the DWC UWB
+ * modules.
+ */
+
+#include "dwc_os.h"
+
+int dwc_wusb_aes_encrypt(u8 *src, u8 *key, u8 *dst);
+
+void dwc_wusb_cmf(u8 *key, u8 *nonce,
+		  char *label, u8 *bytes, int len, u8 *result);
+void dwc_wusb_prf(int prf_len, u8 *key,
+		  u8 *nonce, char *label, u8 *bytes, int len, u8 *result);
+
+/**
+ * The PRF-64 function described in section 6.5 of the WUSB spec.
+ *
+ * @param key, nonce, label, bytes, len, result  Same as for dwc_prf().
+ */
+static inline void dwc_wusb_prf_64(u8 *key, u8 *nonce,
+				   char *label, u8 *bytes, int len, u8 *result)
+{
+	dwc_wusb_prf(64, key, nonce, label, bytes, len, result);
+}
+
+/**
+ * The PRF-128 function described in section 6.5 of the WUSB spec.
+ *
+ * @param key, nonce, label, bytes, len, result  Same as for dwc_prf().
+ */
+static inline void dwc_wusb_prf_128(u8 *key, u8 *nonce,
+				    char *label, u8 *bytes, int len, u8 *result)
+{
+	dwc_wusb_prf(128, key, nonce, label, bytes, len, result);
+}
+
+/**
+ * The PRF-256 function described in section 6.5 of the WUSB spec.
+ *
+ * @param key, nonce, label, bytes, len, result  Same as for dwc_prf().
+ */
+static inline void dwc_wusb_prf_256(u8 *key, u8 *nonce,
+				    char *label, u8 *bytes, int len, u8 *result)
+{
+	dwc_wusb_prf(256, key, nonce, label, bytes, len, result);
+}
+
+
+void dwc_wusb_fill_ccm_nonce(uint16_t haddr, uint16_t daddr, uint8_t *tkid,
+			       uint8_t *nonce);
+void dwc_wusb_gen_nonce(uint16_t addr,
+			  uint8_t *nonce);
+
+void dwc_wusb_gen_key(uint8_t *ccm_nonce, uint8_t *mk,
+			uint8_t *hnonce, uint8_t *dnonce,
+			uint8_t *kck, uint8_t *ptk);
+
+
+void dwc_wusb_gen_mic(uint8_t *ccm_nonce, uint8_t
+			*kck, uint8_t *data, uint8_t *mic);
+
+#endif /* _DWC_CRYPTO_H_ */
diff --git a/drivers/usb/host/dwc_common_port/dwc_dh.c b/drivers/usb/host/dwc_common_port/dwc_dh.c
new file mode 100644
index 000000000000..9529b6a32341
--- /dev/null
+++ b/drivers/usb/host/dwc_common_port/dwc_dh.c
@@ -0,0 +1,286 @@
+/* =========================================================================
+ * $File: //dwh/usb_iip/dev/software/dwc_common_port/dwc_dh.c $
+ * $Revision: #1 $
+ * $Date: 2008/12/21 $
+ * $Change: 1156609 $
+ *
+ * Synopsys Portability Library Software and documentation
+ * (hereinafter, "Software") is an Unsupported proprietary work of
+ * Synopsys, Inc. unless otherwise expressly agreed to in writing
+ * between Synopsys and you.
+ *
+ * The Software IS NOT an item of Licensed Software or Licensed Product
+ * under any End User Software License Agreement or Agreement for
+ * Licensed Product with Synopsys or any supplement thereto. You are
+ * permitted to use and redistribute this Software in source and binary
+ * forms, with or without modification, provided that redistributions
+ * of source code must retain this notice. You may not view, use,
+ * disclose, copy or distribute this file or any information contained
+ * herein except pursuant to this license grant from Synopsys. If you
+ * do not agree with this notice, including the disclaimer below, then
+ * you are not authorized to use the Software.
+ *
+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
+ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
+ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ * ========================================================================= */
+#ifndef CONFIG_MACH_IPMATE
+#include "dwc_dh.h"
+#include "dwc_modpow.h"
+
+#ifdef DEBUG
+/* This function prints out a buffer in the format described in the Association
+ * Model specification. */
+static void dh_dump(char *str, void *_num, int len)
+{
+	uint8_t *num = _num;
+	int i;
+	DWC_PRINTF("%s\n", str);
+	for (i = 0; i < len; i ++) {
+		DWC_PRINTF("%02x", num[i]);
+		if (((i + 1) % 2) == 0) DWC_PRINTF(" ");
+		if (((i + 1) % 26) == 0) DWC_PRINTF("\n");
+	}
+
+	DWC_PRINTF("\n");
+}
+#else
+#define dh_dump(_x...) do {; } while(0)
+#endif
+
+/* Constant g value */
+static __u32 dh_g[] = {
+	0x02000000,
+};
+
+/* Constant p value */
+static __u32 dh_p[] = {
+	0xFFFFFFFF, 0xFFFFFFFF, 0xA2DA0FC9, 0x34C26821, 0x8B62C6C4, 0xD11CDC80, 0x084E0229, 0x74CC678A,
+	0xA6BE0B02, 0x229B133B, 0x79084A51, 0xDD04348E, 0xB31995EF, 0x1B433ACD, 0x6D0A2B30, 0x37145FF2,
+	0x6D35E14F, 0x45C2516D, 0x76B585E4, 0xC67E5E62, 0xE9424CF4, 0x6BED37A6, 0xB65CFF0B, 0xEDB706F4,
+	0xFB6B38EE, 0xA59F895A, 0x11249FAE, 0xE61F4B7C, 0x51662849, 0x3D5BE4EC, 0xB87C00C2, 0x05BF63A1,
+	0x3648DA98, 0x9AD3551C, 0xA83F1669, 0x5FCF24FD, 0x235D6583, 0x96ADA3DC, 0x56F3621C, 0xBB528520,
+	0x0729D59E, 0x6D969670, 0x4E350C67, 0x0498BC4A, 0x086C74F1, 0x7C2118CA, 0x465E9032, 0x3BCE362E,
+	0x2C779EE3, 0x03860E18, 0xA283279B, 0x8FA207EC, 0xF05DC5B5, 0xC9524C6F, 0xF6CB2BDE, 0x18175895,
+	0x7C499539, 0xE56A95EA, 0x1826D215, 0x1005FA98, 0x5A8E7215, 0x2DC4AA8A, 0x0D1733AD, 0x337A5004,
+	0xAB2155A8, 0x64BA1CDF, 0x0485FBEC, 0x0AEFDB58, 0x5771EA8A, 0x7D0C065D, 0x850F97B3, 0xC7E4E1A6,
+	0x8CAEF5AB, 0xD73309DB, 0xE0948C1E, 0x9D61254A, 0x26D2E3CE, 0x6BEED21A, 0x06FA2FF1, 0x64088AD9,
+	0x730276D8, 0x646AC83E, 0x182B1F52, 0x0C207B17, 0x5717E1BB, 0x6C5D617A, 0xC0880977, 0xE246D9BA,
+	0xA04FE208, 0x31ABE574, 0xFC5BDB43, 0x8E10FDE0, 0x20D1824B, 0xCAD23AA9, 0xFFFFFFFF, 0xFFFFFFFF,
+};
+
+static void dh_swap_bytes(void *_in, void *_out, uint32_t len)
+{
+	uint8_t *in = _in;
+	uint8_t *out = _out;
+	int i;
+	for (i=0; i<len; i++) {
+		out[i] = in[len-1-i];
+	}
+}
+
+/* Computes the modular exponentiation (num^exp % mod).  num, exp, and mod are
+ * big endian numbers of size len, in bytes.  Each len value must be a multiple
+ * of 4. */
+int dwc_dh_modpow(void *num, uint32_t num_len,
+			 void *exp, uint32_t exp_len,
+			 void *mod, uint32_t mod_len,
+			 void *out)
+{
+	/* modpow() takes little endian numbers.  AM uses big-endian.  This
+	 * function swaps bytes of numbers before passing onto modpow. */
+
+	int retval = 0;
+	uint32_t *result;
+
+	uint32_t *bignum_num = DWC_ALLOC(num_len + 4);
+	uint32_t *bignum_exp = DWC_ALLOC(exp_len + 4);
+	uint32_t *bignum_mod = DWC_ALLOC(mod_len + 4);
+
+	dh_swap_bytes(num, &bignum_num[1], num_len);
+	bignum_num[0] = num_len / 4;
+
+	dh_swap_bytes(exp, &bignum_exp[1], exp_len);
+	bignum_exp[0] = exp_len / 4;
+
+	dh_swap_bytes(mod, &bignum_mod[1], mod_len);
+	bignum_mod[0] = mod_len / 4;
+
+	result = dwc_modpow(bignum_num, bignum_exp, bignum_mod);
+	if (!result) {
+		retval = -1;
+		goto dh_modpow_nomem;
+	}
+
+	dh_swap_bytes(&result[1], out, result[0] * 4);
+	DWC_FREE(result);
+
+ dh_modpow_nomem:
+	DWC_FREE(bignum_num);
+	DWC_FREE(bignum_exp);
+	DWC_FREE(bignum_mod);
+	return retval;
+}
+
+
+int dwc_dh_pk(uint8_t nd, uint8_t *exp, uint8_t *pk, uint8_t *hash)
+{
+	int retval;
+	uint8_t m3[385];
+
+#ifndef DH_TEST_VECTORS
+	DWC_RANDOM_BYTES(exp, 32);
+#endif
+
+	/* Compute the pkd */
+	if ((retval = dwc_dh_modpow(dh_g, 4,
+					  exp, 32,
+					  dh_p, 384, pk))) {
+		return retval;
+	}
+
+	m3[384] = nd;
+	DWC_MEMCPY(&m3[0], pk, 384);
+	DWC_SHA256(m3, 385, hash);
+
+ 	dh_dump("PK", pk, 384);
+ 	dh_dump("SHA-256(M3)", hash, 32);
+	return 0;
+}
+
+int dwc_dh_derive_keys(uint8_t nd, uint8_t *pkh, uint8_t *pkd,
+			     uint8_t *exp, int is_host,
+			     char *dd, uint8_t *ck, uint8_t *kdk)
+{
+	int retval;
+	uint8_t mv[784];
+	uint8_t sha_result[32];
+	uint8_t dhkey[384];
+	uint8_t shared_secret[384];
+	char *message;
+	uint32_t vd;
+
+	uint8_t *pk;
+
+	if (is_host) {
+		pk = pkd;
+	}
+	else {
+		pk = pkh;
+	}
+
+	if ((retval = dwc_dh_modpow(pk, 384,
+					  exp, 32,
+					  dh_p, 384, shared_secret))) {
+		return retval;
+	}
+	dh_dump("Shared Secret", shared_secret, 384);
+
+	DWC_SHA256(shared_secret, 384, dhkey);
+	dh_dump("DHKEY", dhkey, 384);
+
+	DWC_MEMCPY(&mv[0], pkd, 384);
+	DWC_MEMCPY(&mv[384], pkh, 384);
+	DWC_MEMCPY(&mv[768], "displayed digest", 16);
+	dh_dump("MV", mv, 784);
+
+	DWC_SHA256(mv, 784, sha_result);
+	dh_dump("SHA-256(MV)", sha_result, 32);
+	dh_dump("First 32-bits of SHA-256(MV)", sha_result, 4);
+
+	dh_swap_bytes(sha_result, &vd, 4);
+#ifdef DEBUG
+	DWC_PRINTF("Vd (decimal) = %d\n", vd);
+#endif
+
+	switch (nd) {
+	case 2:
+		vd = vd % 100;
+		DWC_SPRINTF(dd, "%02d", vd);
+		break;
+	case 3:
+		vd = vd % 1000;
+		DWC_SPRINTF(dd, "%03d", vd);
+		break;
+	case 4:
+		vd = vd % 10000;
+		DWC_SPRINTF(dd, "%04d", vd);
+		break;
+	}
+#ifdef DEBUG
+	DWC_PRINTF("Display Digits: %s\n", dd);
+#endif
+
+	message = "connection key";
+	DWC_HMAC_SHA256(message, DWC_STRLEN(message), dhkey, 32, sha_result);
+ 	dh_dump("HMAC(SHA-256, DHKey, connection key)", sha_result, 32);
+	DWC_MEMCPY(ck, sha_result, 16);
+
+	message = "key derivation key";
+	DWC_HMAC_SHA256(message, DWC_STRLEN(message), dhkey, 32, sha_result);
+ 	dh_dump("HMAC(SHA-256, DHKey, key derivation key)", sha_result, 32);
+	DWC_MEMCPY(kdk, sha_result, 32);
+
+	return 0;
+}
+
+
+#ifdef DH_TEST_VECTORS
+
+static __u8 dh_a[] = {
+	0x44, 0x00, 0x51, 0xd6,
+	0xf0, 0xb5, 0x5e, 0xa9,
+	0x67, 0xab, 0x31, 0xc6,
+	0x8a, 0x8b, 0x5e, 0x37,
+	0xd9, 0x10, 0xda, 0xe0,
+	0xe2, 0xd4, 0x59, 0xa4,
+	0x86, 0x45, 0x9c, 0xaa,
+	0xdf, 0x36, 0x75, 0x16,
+};
+
+static __u8 dh_b[] = {
+	0x5d, 0xae, 0xc7, 0x86,
+	0x79, 0x80, 0xa3, 0x24,
+	0x8c, 0xe3, 0x57, 0x8f,
+	0xc7, 0x5f, 0x1b, 0x0f,
+	0x2d, 0xf8, 0x9d, 0x30,
+	0x6f, 0xa4, 0x52, 0xcd,
+	0xe0, 0x7a, 0x04, 0x8a,
+	0xde, 0xd9, 0x26, 0x56,
+};
+
+void dwc_run_dh_test_vectors(void)
+{
+	uint8_t pkd[384];
+	uint8_t pkh[384];
+	uint8_t hashd[32];
+	uint8_t hashh[32];
+	uint8_t ck[16];
+	uint8_t kdk[32];
+	char dd[5];
+
+	DWC_PRINTF("\n\n\nDH_TEST_VECTORS\n\n");
+
+	/* compute the PKd and SHA-256(PKd || Nd) */
+	DWC_PRINTF("Computing PKd\n");
+	dwc_dh_pk(2, dh_a, pkd, hashd);
+
+	/* compute the PKd and SHA-256(PKh || Nd) */
+	DWC_PRINTF("Computing PKh\n");
+	dwc_dh_pk(2, dh_b, pkh, hashh);
+
+	/* compute the dhkey */
+	dwc_dh_derive_keys(2, pkh, pkd, dh_a, 0, dd, ck, kdk);
+}
+#endif /* DH_TEST_VECTORS */
+
+#endif /* CONFIG_IPMATE_MACH */
diff --git a/drivers/usb/host/dwc_common_port/dwc_dh.h b/drivers/usb/host/dwc_common_port/dwc_dh.h
new file mode 100644
index 000000000000..5a0e0cd1962a
--- /dev/null
+++ b/drivers/usb/host/dwc_common_port/dwc_dh.h
@@ -0,0 +1,98 @@
+/* =========================================================================
+ * $File: //dwh/usb_iip/dev/software/dwc_common_port/dwc_dh.h $
+ * $Revision: #1 $
+ * $Date: 2008/12/21 $
+ * $Change: 1156609 $
+ *
+ * Synopsys Portability Library Software and documentation
+ * (hereinafter, "Software") is an Unsupported proprietary work of
+ * Synopsys, Inc. unless otherwise expressly agreed to in writing
+ * between Synopsys and you.
+ *
+ * The Software IS NOT an item of Licensed Software or Licensed Product
+ * under any End User Software License Agreement or Agreement for
+ * Licensed Product with Synopsys or any supplement thereto. You are
+ * permitted to use and redistribute this Software in source and binary
+ * forms, with or without modification, provided that redistributions
+ * of source code must retain this notice. You may not view, use,
+ * disclose, copy or distribute this file or any information contained
+ * herein except pursuant to this license grant from Synopsys. If you
+ * do not agree with this notice, including the disclaimer below, then
+ * you are not authorized to use the Software.
+ *
+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
+ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
+ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ * ========================================================================= */
+#ifndef _DWC_DH_H_
+#define _DWC_DH_H_
+
+#include "dwc_os.h"
+
+/** @file
+ *
+ * This file defines the common functions on device and host for performing
+ * numeric association as defined in the WUSB spec.  They are only to be
+ * used internally by the DWC UWB modules. */
+
+extern int dwc_dh_sha256(uint8_t *message, uint32_t len, uint8_t *out);
+extern int dwc_dh_hmac_sha256(uint8_t *message, uint32_t messagelen,
+				     uint8_t *key, uint32_t keylen,
+				     uint8_t *out);
+extern int dwc_dh_modpow(void *num, uint32_t num_len,
+			       void *exp, uint32_t exp_len,
+			       void *mod, uint32_t mod_len,
+			       void *out);
+
+/** Computes PKD or PKH, and SHA-256(PKd || Nd)
+ *
+ * PK = g^exp mod p.
+ *
+ * Input:
+ * Nd = Number of digits on the device.
+ *
+ * Output:
+ * exp = A 32-byte buffer to be filled with a randomly generated number.
+ *       used as either A or B.
+ * pk = A 384-byte buffer to be filled with the PKH or PKD.
+ * hash = A 32-byte buffer to be filled with SHA-256(PK || ND).
+ */
+extern int dwc_dh_pk(uint8_t nd, uint8_t *exp, uint8_t *pkd, uint8_t *hash);
+
+/** Computes the DHKEY, and VD.
+ *
+ * If called from host, then it will comput DHKEY=PKD^exp % p.
+ * If called from device, then it will comput DHKEY=PKH^exp % p.
+ *
+ * Input:
+ * pkd = The PKD value.
+ * pkh = The PKH value.
+ * exp = The A value (if device) or B value (if host) generated in dwc_wudev_dh_pk.
+ * is_host = Set to non zero if a WUSB host is calling this function.
+ *
+ * Output:
+
+ * dd = A pointer to an buffer to be set to the displayed digits string to be shown
+ *      to the user.  This buffer should be at 5 bytes long to hold 4 digits plus a
+ *      null termination character.  This buffer can be used directly for display.
+ * ck = A 16-byte buffer to be filled with the CK.
+ * kdk = A 32-byte buffer to be filled with the KDK.
+ */
+extern int dwc_dh_derive_keys(uint8_t nd, uint8_t *pkh, uint8_t *pkd,
+			      uint8_t *exp, int is_host,
+			      char *dd, uint8_t *ck, uint8_t *kdk);
+
+#ifdef DH_TEST_VECTORS
+extern void dwc_run_dh_test_vectors(void);
+#endif
+
+#endif /* _DWC_DH_H_ */
diff --git a/drivers/usb/host/dwc_common_port/dwc_list.h b/drivers/usb/host/dwc_common_port/dwc_list.h
new file mode 100644
index 000000000000..b29afe007719
--- /dev/null
+++ b/drivers/usb/host/dwc_common_port/dwc_list.h
@@ -0,0 +1,616 @@
+/*	$OpenBSD: queue.h,v 1.26 2004/05/04 16:59:32 grange Exp $	*/
+/*	$NetBSD: queue.h,v 1.11 1996/05/16 05:17:14 mycroft Exp $	*/
+
+/*
+ * Copyright (c) 1991, 1993
+ *	The Regents of the University of California.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	@(#)queue.h	8.5 (Berkeley) 8/20/94
+ */
+
+#ifndef	_SYS_QUEUE_H_
+#define	_SYS_QUEUE_H_
+
+
+/** @file
+ *
+ * This file defines linked list operations.  It is derived from BSD with
+ * only the MACRO names being prefixed with DWC_.  This is because a few of
+ * these names conflict with those on Linux.  For documentation on use, see the
+ * inline comments in the source code.  The original license for this source
+ * code applies and is preserved in the dwc_list.h source file.
+ */
+
+/*
+ * This file defines five types of data structures: singly-linked lists, 
+ * lists, simple queues, tail queues, and circular queues.
+ *
+ *
+ * A singly-linked list is headed by a single forward pointer. The elements
+ * are singly linked for minimum space and pointer manipulation overhead at
+ * the expense of O(n) removal for arbitrary elements. New elements can be
+ * added to the list after an existing element or at the head of the list.
+ * Elements being removed from the head of the list should use the explicit
+ * macro for this purpose for optimum efficiency. A singly-linked list may
+ * only be traversed in the forward direction.  Singly-linked lists are ideal
+ * for applications with large datasets and few or no removals or for
+ * implementing a LIFO queue.
+ *
+ * A list is headed by a single forward pointer (or an array of forward
+ * pointers for a hash table header). The elements are doubly linked
+ * so that an arbitrary element can be removed without a need to
+ * traverse the list. New elements can be added to the list before
+ * or after an existing element or at the head of the list. A list
+ * may only be traversed in the forward direction.
+ *
+ * A simple queue is headed by a pair of pointers, one the head of the
+ * list and the other to the tail of the list. The elements are singly
+ * linked to save space, so elements can only be removed from the
+ * head of the list. New elements can be added to the list before or after
+ * an existing element, at the head of the list, or at the end of the
+ * list. A simple queue may only be traversed in the forward direction.
+ * 
+ * A tail queue is headed by a pair of pointers, one to the head of the
+ * list and the other to the tail of the list. The elements are doubly
+ * linked so that an arbitrary element can be removed without a need to
+ * traverse the list. New elements can be added to the list before or
+ * after an existing element, at the head of the list, or at the end of
+ * the list. A tail queue may be traversed in either direction.
+ *
+ * A circle queue is headed by a pair of pointers, one to the head of the
+ * list and the other to the tail of the list. The elements are doubly
+ * linked so that an arbitrary element can be removed without a need to
+ * traverse the list. New elements can be added to the list before or after
+ * an existing element, at the head of the list, or at the end of the list.
+ * A circle queue may be traversed in either direction, but has a more
+ * complex end of list detection.
+ *
+ * For details on the use of these macros, see the queue(3) manual page.
+ */
+
+/*
+ * Double-linked List.
+ */
+
+typedef struct dwc_list_link {
+	struct dwc_list_link *next;
+	struct dwc_list_link *prev;
+} dwc_list_link_t;
+
+#define DWC_LIST_INIT(link) do{		\
+	(link)->next = (link);		\
+	(link)->prev = (link);		\
+} while(0)
+
+#define DWC_LIST_FIRST(link)	((link)->next)
+#define DWC_LIST_LAST(link)	((link)->prev)
+#define DWC_LIST_END(link)	(link)
+#define DWC_LIST_NEXT(link)	((link)->next)
+#define DWC_LIST_PREV(link)	((link)->prev)
+#define DWC_LIST_EMPTY(link)	\
+	(DWC_LIST_FIRST(link) == DWC_LIST_END(link))
+#define DWC_LIST_ENTRY(link, type, field) (type *)		\
+	((uint8_t *)(link) - (size_t)(&((type *)0)->field))
+
+#define DWC_LIST_INSERT_HEAD(list, link) do {			\
+	(link)->next = (list)->next;				\
+	(link)->prev = (list);					\
+	(list)->next->prev = link;				\
+	(list)->next = link;					\
+} while(0)
+
+#define DWC_LIST_INSERT_TAIL(list, link) do {			\
+	(link)->next = list;					\
+	(link)->prev = (list)->prev;				\
+	(list)->prev->next = link;				\
+	(list)->prev = link;					\
+} while(0)
+
+#define DWC_LIST_REMOVE(link) do {				\
+	(link)->next->prev = (link)->prev;			\
+	(link)->prev->next = (link)->next;			\
+} while(0)
+
+#define DWC_LIST_REMOVE_INIT(link) do {				\
+	DWC_LIST_REMOVE(link);					\
+	DWC_LIST_INIT(link);					\
+} while(0)
+
+#define DWC_LIST_MOVE_HEAD(list, link) do {			\
+	DWC_LIST_REMOVE(link);					\
+	DWC_LIST_INSERT_HEAD(list, link);			\
+} while(0)
+
+#define DWC_LIST_MOVE_TAIL(list, link) do {			\
+	DWC_LIST_REMOVE(link);					\
+	DWC_LIST_INSERT_TAIL(list, link);			\
+} while(0)
+
+#define DWC_LIST_FOREACH(var, list)				\
+	for((var) = DWC_LIST_FIRST(list);			\
+	    (var) != DWC_LIST_END(list);			\
+	    (var) = DWC_LIST_NEXT(var))
+
+#define DWC_LIST_FOREACH_SAFE(var, var2, list)			\
+	for((var) = DWC_LIST_FIRST(list), var2 = DWC_LIST_NEXT(var);	\
+	    (var) != DWC_LIST_END(list);			\
+	    (var) = (var2), var2 = DWC_LIST_NEXT(var2))
+
+#define DWC_LIST_FOREACH_REVERSE(var, list)			\
+	for((var) = DWC_LIST_LAST(list);			\
+	    (var) != DWC_LIST_END(list);			\
+	    (var) = DWC_LIST_PREV(var))
+
+/*
+ * Singly-linked List definitions.
+ */
+#define DWC_SLIST_HEAD(name, type)					\
+struct name {								\
+	struct type *slh_first;	/* first element */			\
+}
+ 
+#define	DWC_SLIST_HEAD_INITIALIZER(head)					\
+	{ NULL }
+ 
+#define DWC_SLIST_ENTRY(type)						\
+struct {								\
+	struct type *sle_next;	/* next element */			\
+}
+ 
+/*
+ * Singly-linked List access methods.
+ */
+#define DWC_SLIST_FIRST(head)	((head)->slh_first)
+#define DWC_SLIST_END(head)		NULL
+#define DWC_SLIST_EMPTY(head)	(SLIST_FIRST(head) == SLIST_END(head))
+#define DWC_SLIST_NEXT(elm, field)	((elm)->field.sle_next)
+
+#define DWC_SLIST_FOREACH(var, head, field)					\
+	for((var) = SLIST_FIRST(head);					\
+	    (var) != SLIST_END(head);					\
+	    (var) = SLIST_NEXT(var, field))
+
+#define DWC_SLIST_FOREACH_PREVPTR(var, varp, head, field)			\
+	for ((varp) = &SLIST_FIRST((head));				\
+	    ((var) = *(varp)) != SLIST_END(head);			\
+	    (varp) = &SLIST_NEXT((var), field))
+
+/*
+ * Singly-linked List functions.
+ */
+#define DWC_SLIST_INIT(head) {						\
+	SLIST_FIRST(head) = SLIST_END(head);				\
+}
+
+#define DWC_SLIST_INSERT_AFTER(slistelm, elm, field) do {			\
+	(elm)->field.sle_next = (slistelm)->field.sle_next;		\
+	(slistelm)->field.sle_next = (elm);				\
+} while (0)
+
+#define DWC_SLIST_INSERT_HEAD(head, elm, field) do {			\
+	(elm)->field.sle_next = (head)->slh_first;			\
+	(head)->slh_first = (elm);					\
+} while (0)
+
+#define DWC_SLIST_REMOVE_NEXT(head, elm, field) do {			\
+	(elm)->field.sle_next = (elm)->field.sle_next->field.sle_next;	\
+} while (0)
+
+#define DWC_SLIST_REMOVE_HEAD(head, field) do {				\
+	(head)->slh_first = (head)->slh_first->field.sle_next;		\
+} while (0)
+
+#define DWC_SLIST_REMOVE(head, elm, type, field) do {			\
+	if ((head)->slh_first == (elm)) {				\
+		SLIST_REMOVE_HEAD((head), field);			\
+	}								\
+	else {								\
+		struct type *curelm = (head)->slh_first;		\
+		while( curelm->field.sle_next != (elm) )		\
+			curelm = curelm->field.sle_next;		\
+		curelm->field.sle_next =				\
+		    curelm->field.sle_next->field.sle_next;		\
+	}								\
+} while (0)
+
+#if 0
+
+/*
+ * List definitions.
+ */
+#define DWC_LIST_HEAD(name, type)						\
+struct name {								\
+	struct type *lh_first;	/* first element */			\
+}
+
+#define DWC_LIST_HEAD_INITIALIZER(head)					\
+	{ NULL }
+
+#define DWC_LIST_ENTRY(type)						\
+struct {								\
+	struct type *le_next;	/* next element */			\
+	struct type **le_prev;	/* address of previous next element */	\
+}
+
+/*
+ * List access methods
+ */
+#define DWC_LIST_FIRST(head)		((head)->lh_first)
+#define DWC_LIST_END(head)			NULL
+#define DWC_LIST_EMPTY(head)		(DWC_LIST_FIRST(head) == DWC_LIST_END(head))
+#define DWC_LIST_NEXT(elm, field)		((elm)->field.le_next)
+
+#define DWC_LIST_FOREACH(var, head, field)					\
+	for((var) = DWC_LIST_FIRST(head);					\
+	    (var)!= DWC_LIST_END(head);					\
+	    (var) = DWC_LIST_NEXT(var, field))
+#define DWC_LIST_FOREACH_SAFE(var, var2, head, field)				\
+	for((var) = DWC_LIST_FIRST(head), var2 = DWC_LIST_NEXT(var, field);				\
+	    (var) != DWC_LIST_END(head);					\
+	    (var) = var2, var2 = DWC_LIST_NEXT(var, field))
+
+/*
+ * List functions.
+ */
+#define DWC_LIST_INIT(head) do {						\
+	DWC_LIST_FIRST(head) = DWC_LIST_END(head);				\
+} while (0)
+
+#define DWC_LIST_INSERT_AFTER(listelm, elm, field) do {			\
+	if (((elm)->field.le_next = (listelm)->field.le_next) != NULL)	\
+		(listelm)->field.le_next->field.le_prev =		\
+		    &(elm)->field.le_next;				\
+	(listelm)->field.le_next = (elm);				\
+	(elm)->field.le_prev = &(listelm)->field.le_next;		\
+} while (0)
+
+#define DWC_LIST_INSERT_BEFORE(listelm, elm, field) do {			\
+	(elm)->field.le_prev = (listelm)->field.le_prev;		\
+	(elm)->field.le_next = (listelm);				\
+	*(listelm)->field.le_prev = (elm);				\
+	(listelm)->field.le_prev = &(elm)->field.le_next;		\
+} while (0)
+
+#define DWC_LIST_INSERT_HEAD(head, elm, field) do {				\
+	if (((elm)->field.le_next = (head)->lh_first) != NULL)		\
+		(head)->lh_first->field.le_prev = &(elm)->field.le_next;\
+	(head)->lh_first = (elm);					\
+	(elm)->field.le_prev = &(head)->lh_first;			\
+} while (0)
+
+#define DWC_LIST_REMOVE(elm, field) do {					\
+	if ((elm)->field.le_next != NULL)				\
+		(elm)->field.le_next->field.le_prev =			\
+		    (elm)->field.le_prev;				\
+	*(elm)->field.le_prev = (elm)->field.le_next;			\
+} while (0)
+
+#define DWC_LIST_REPLACE(elm, elm2, field) do {				\
+	if (((elm2)->field.le_next = (elm)->field.le_next) != NULL)	\
+		(elm2)->field.le_next->field.le_prev =			\
+		    &(elm2)->field.le_next;				\
+	(elm2)->field.le_prev = (elm)->field.le_prev;			\
+	*(elm2)->field.le_prev = (elm2);				\
+} while (0)
+
+#endif
+
+/*
+ * Simple queue definitions.
+ */
+#define DWC_SIMPLEQ_HEAD(name, type)					\
+struct name {								\
+	struct type *sqh_first;	/* first element */			\
+	struct type **sqh_last;	/* addr of last next element */		\
+}
+
+#define DWC_SIMPLEQ_HEAD_INITIALIZER(head)					\
+	{ NULL, &(head).sqh_first }
+
+#define DWC_SIMPLEQ_ENTRY(type)						\
+struct {								\
+	struct type *sqe_next;	/* next element */			\
+}
+
+/*
+ * Simple queue access methods.
+ */
+#define DWC_SIMPLEQ_FIRST(head)	    ((head)->sqh_first)
+#define DWC_SIMPLEQ_END(head)	    NULL
+#define DWC_SIMPLEQ_EMPTY(head)	    (SIMPLEQ_FIRST(head) == SIMPLEQ_END(head))
+#define DWC_SIMPLEQ_NEXT(elm, field)    ((elm)->field.sqe_next)
+
+#define DWC_SIMPLEQ_FOREACH(var, head, field)				\
+	for((var) = SIMPLEQ_FIRST(head);				\
+	    (var) != SIMPLEQ_END(head);					\
+	    (var) = SIMPLEQ_NEXT(var, field))
+
+/*
+ * Simple queue functions.
+ */
+#define DWC_SIMPLEQ_INIT(head) do {						\
+	(head)->sqh_first = NULL;					\
+	(head)->sqh_last = &(head)->sqh_first;				\
+} while (0)
+
+#define DWC_SIMPLEQ_INSERT_HEAD(head, elm, field) do {			\
+	if (((elm)->field.sqe_next = (head)->sqh_first) == NULL)	\
+		(head)->sqh_last = &(elm)->field.sqe_next;		\
+	(head)->sqh_first = (elm);					\
+} while (0)
+
+#define DWC_SIMPLEQ_INSERT_TAIL(head, elm, field) do {			\
+	(elm)->field.sqe_next = NULL;					\
+	*(head)->sqh_last = (elm);					\
+	(head)->sqh_last = &(elm)->field.sqe_next;			\
+} while (0)
+
+#define DWC_SIMPLEQ_INSERT_AFTER(head, listelm, elm, field) do {		\
+	if (((elm)->field.sqe_next = (listelm)->field.sqe_next) == NULL)\
+		(head)->sqh_last = &(elm)->field.sqe_next;		\
+	(listelm)->field.sqe_next = (elm);				\
+} while (0)
+
+#define DWC_SIMPLEQ_REMOVE_HEAD(head, field) do {			\
+	if (((head)->sqh_first = (head)->sqh_first->field.sqe_next) == NULL) \
+		(head)->sqh_last = &(head)->sqh_first;			\
+} while (0)
+
+/*
+ * Tail queue definitions.
+ */
+#define DWC_TAILQ_HEAD(name, type)						\
+struct name {								\
+	struct type *tqh_first;	/* first element */			\
+	struct type **tqh_last;	/* addr of last next element */		\
+}
+
+#define DWC_TAILQ_HEAD_INITIALIZER(head)					\
+	{ NULL, &(head).tqh_first }
+
+#define DWC_TAILQ_ENTRY(type)						\
+struct {								\
+	struct type *tqe_next;	/* next element */			\
+	struct type **tqe_prev;	/* address of previous next element */	\
+}
+
+/* 
+ * tail queue access methods 
+ */
+#define DWC_TAILQ_FIRST(head)		((head)->tqh_first)
+#define DWC_TAILQ_END(head)			NULL
+#define DWC_TAILQ_NEXT(elm, field)		((elm)->field.tqe_next)
+#define DWC_TAILQ_LAST(head, headname)					\
+	(*(((struct headname *)((head)->tqh_last))->tqh_last))
+/* XXX */
+#define DWC_TAILQ_PREV(elm, headname, field)				\
+	(*(((struct headname *)((elm)->field.tqe_prev))->tqh_last))
+#define DWC_TAILQ_EMPTY(head)						\
+	(TAILQ_FIRST(head) == TAILQ_END(head))
+
+#define DWC_TAILQ_FOREACH(var, head, field)					\
+	for((var) = TAILQ_FIRST(head);					\
+	    (var) != TAILQ_END(head);					\
+	    (var) = TAILQ_NEXT(var, field))
+
+#define DWC_TAILQ_FOREACH_REVERSE(var, head, headname, field)		\
+	for((var) = TAILQ_LAST(head, headname);				\
+	    (var) != TAILQ_END(head);					\
+	    (var) = TAILQ_PREV(var, headname, field))
+
+/*
+ * Tail queue functions.
+ */
+#define DWC_TAILQ_INIT(head) do {						\
+	(head)->tqh_first = NULL;					\
+	(head)->tqh_last = &(head)->tqh_first;				\
+} while (0)
+
+#define DWC_TAILQ_INSERT_HEAD(head, elm, field) do {			\
+	if (((elm)->field.tqe_next = (head)->tqh_first) != NULL)	\
+		(head)->tqh_first->field.tqe_prev =			\
+		    &(elm)->field.tqe_next;				\
+	else								\
+		(head)->tqh_last = &(elm)->field.tqe_next;		\
+	(head)->tqh_first = (elm);					\
+	(elm)->field.tqe_prev = &(head)->tqh_first;			\
+} while (0)
+
+#define DWC_TAILQ_INSERT_TAIL(head, elm, field) do {			\
+	(elm)->field.tqe_next = NULL;					\
+	(elm)->field.tqe_prev = (head)->tqh_last;			\
+	*(head)->tqh_last = (elm);					\
+	(head)->tqh_last = &(elm)->field.tqe_next;			\
+} while (0)
+
+#define DWC_TAILQ_INSERT_AFTER(head, listelm, elm, field) do {		\
+	if (((elm)->field.tqe_next = (listelm)->field.tqe_next) != NULL)\
+		(elm)->field.tqe_next->field.tqe_prev =			\
+		    &(elm)->field.tqe_next;				\
+	else								\
+		(head)->tqh_last = &(elm)->field.tqe_next;		\
+	(listelm)->field.tqe_next = (elm);				\
+	(elm)->field.tqe_prev = &(listelm)->field.tqe_next;		\
+} while (0)
+
+#define DWC_TAILQ_INSERT_BEFORE(listelm, elm, field) do {			\
+	(elm)->field.tqe_prev = (listelm)->field.tqe_prev;		\
+	(elm)->field.tqe_next = (listelm);				\
+	*(listelm)->field.tqe_prev = (elm);				\
+	(listelm)->field.tqe_prev = &(elm)->field.tqe_next;		\
+} while (0)
+
+#define DWC_TAILQ_REMOVE(head, elm, field) do {				\
+	if (((elm)->field.tqe_next) != NULL)				\
+		(elm)->field.tqe_next->field.tqe_prev =			\
+		    (elm)->field.tqe_prev;				\
+	else								\
+		(head)->tqh_last = (elm)->field.tqe_prev;		\
+	*(elm)->field.tqe_prev = (elm)->field.tqe_next;			\
+} while (0)
+
+#define DWC_TAILQ_REPLACE(head, elm, elm2, field) do {			\
+	if (((elm2)->field.tqe_next = (elm)->field.tqe_next) != NULL)	\
+		(elm2)->field.tqe_next->field.tqe_prev =		\
+		    &(elm2)->field.tqe_next;				\
+	else								\
+		(head)->tqh_last = &(elm2)->field.tqe_next;		\
+	(elm2)->field.tqe_prev = (elm)->field.tqe_prev;			\
+	*(elm2)->field.tqe_prev = (elm2);				\
+} while (0)
+
+/*
+ * Circular queue definitions.
+ */
+#define DWC_CIRCLEQ_HEAD(name, type)					\
+struct name {								\
+	struct type *cqh_first;		/* first element */		\
+	struct type *cqh_last;		/* last element */		\
+}
+
+#define DWC_CIRCLEQ_HEAD_INITIALIZER(head)					\
+	{ DWC_CIRCLEQ_END(&head), DWC_CIRCLEQ_END(&head) }
+
+#define DWC_CIRCLEQ_ENTRY(type)						\
+struct {								\
+	struct type *cqe_next;		/* next element */		\
+	struct type *cqe_prev;		/* previous element */		\
+}
+
+/*
+ * Circular queue access methods 
+ */
+#define DWC_CIRCLEQ_FIRST(head)		((head)->cqh_first)
+#define DWC_CIRCLEQ_LAST(head)		((head)->cqh_last)
+#define DWC_CIRCLEQ_END(head)		((void *)(head))
+#define DWC_CIRCLEQ_NEXT(elm, field)	((elm)->field.cqe_next)
+#define DWC_CIRCLEQ_PREV(elm, field)	((elm)->field.cqe_prev)
+#define DWC_CIRCLEQ_EMPTY(head)						\
+	(DWC_CIRCLEQ_FIRST(head) == DWC_CIRCLEQ_END(head))
+
+#define DWC_CIRCLEQ_EMPTY_ENTRY(elm, field) (((elm)->field.cqe_next == NULL) && ((elm)->field.cqe_prev == NULL))
+
+#define DWC_CIRCLEQ_FOREACH(var, head, field)				\
+	for((var) = DWC_CIRCLEQ_FIRST(head);				\
+	    (var) != DWC_CIRCLEQ_END(head);					\
+	    (var) = DWC_CIRCLEQ_NEXT(var, field))
+
+#define DWC_CIRCLEQ_FOREACH_SAFE(var, var2, head, field)				\
+	for((var) = DWC_CIRCLEQ_FIRST(head), var2 = DWC_CIRCLEQ_NEXT(var, field);				\
+	    (var) != DWC_CIRCLEQ_END(head);					\
+	    (var) = var2, var2 = DWC_CIRCLEQ_NEXT(var, field))
+
+#define DWC_CIRCLEQ_FOREACH_REVERSE(var, head, field)			\
+	for((var) = DWC_CIRCLEQ_LAST(head);					\
+	    (var) != DWC_CIRCLEQ_END(head);					\
+	    (var) = DWC_CIRCLEQ_PREV(var, field))
+
+/*
+ * Circular queue functions.
+ */
+#define DWC_CIRCLEQ_INIT(head) do {						\
+	(head)->cqh_first = DWC_CIRCLEQ_END(head);				\
+	(head)->cqh_last = DWC_CIRCLEQ_END(head);				\
+} while (0)
+
+#define DWC_CIRCLEQ_INIT_ENTRY(elm, field) do { \
+	(elm)->field.cqe_next = NULL; \
+	(elm)->field.cqe_prev = NULL; \
+} while (0)
+
+#define DWC_CIRCLEQ_INSERT_AFTER(head, listelm, elm, field) do {		\
+	(elm)->field.cqe_next = (listelm)->field.cqe_next;		\
+	(elm)->field.cqe_prev = (listelm);				\
+	if ((listelm)->field.cqe_next == DWC_CIRCLEQ_END(head))		\
+		(head)->cqh_last = (elm);				\
+	else								\
+		(listelm)->field.cqe_next->field.cqe_prev = (elm);	\
+	(listelm)->field.cqe_next = (elm);				\
+} while (0)
+
+#define DWC_CIRCLEQ_INSERT_BEFORE(head, listelm, elm, field) do {		\
+	(elm)->field.cqe_next = (listelm);				\
+	(elm)->field.cqe_prev = (listelm)->field.cqe_prev;		\
+	if ((listelm)->field.cqe_prev == DWC_CIRCLEQ_END(head))		\
+		(head)->cqh_first = (elm);				\
+	else								\
+		(listelm)->field.cqe_prev->field.cqe_next = (elm);	\
+	(listelm)->field.cqe_prev = (elm);				\
+} while (0)
+
+#define DWC_CIRCLEQ_INSERT_HEAD(head, elm, field) do {			\
+	(elm)->field.cqe_next = (head)->cqh_first;			\
+	(elm)->field.cqe_prev = DWC_CIRCLEQ_END(head);			\
+	if ((head)->cqh_last == DWC_CIRCLEQ_END(head))			\
+		(head)->cqh_last = (elm);				\
+	else								\
+		(head)->cqh_first->field.cqe_prev = (elm);		\
+	(head)->cqh_first = (elm);					\
+} while (0)
+
+#define DWC_CIRCLEQ_INSERT_TAIL(head, elm, field) do {			\
+	(elm)->field.cqe_next = DWC_CIRCLEQ_END(head);			\
+	(elm)->field.cqe_prev = (head)->cqh_last;			\
+	if ((head)->cqh_first == DWC_CIRCLEQ_END(head))			\
+		(head)->cqh_first = (elm);				\
+	else								\
+		(head)->cqh_last->field.cqe_next = (elm);		\
+	(head)->cqh_last = (elm);					\
+} while (0)
+
+#define DWC_CIRCLEQ_REMOVE(head, elm, field) do {				\
+	if ((elm)->field.cqe_next == DWC_CIRCLEQ_END(head))			\
+		(head)->cqh_last = (elm)->field.cqe_prev;		\
+	else								\
+		(elm)->field.cqe_next->field.cqe_prev =			\
+		    (elm)->field.cqe_prev;				\
+	if ((elm)->field.cqe_prev == DWC_CIRCLEQ_END(head))			\
+		(head)->cqh_first = (elm)->field.cqe_next;		\
+	else								\
+		(elm)->field.cqe_prev->field.cqe_next =			\
+		    (elm)->field.cqe_next;				\
+} while (0)
+
+#define DWC_CIRCLEQ_REMOVE_INIT(head, elm, field) do { \
+	DWC_CIRCLEQ_REMOVE(head, elm, field); \
+	DWC_CIRCLEQ_INIT_ENTRY(elm, field); \
+} while (0)
+
+#define DWC_CIRCLEQ_REPLACE(head, elm, elm2, field) do {			\
+	if (((elm2)->field.cqe_next = (elm)->field.cqe_next) ==		\
+	    DWC_CIRCLEQ_END(head))						\
+		(head).cqh_last = (elm2);				\
+	else								\
+		(elm2)->field.cqe_next->field.cqe_prev = (elm2);	\
+	if (((elm2)->field.cqe_prev = (elm)->field.cqe_prev) ==		\
+	    DWC_CIRCLEQ_END(head))						\
+		(head).cqh_first = (elm2);				\
+	else								\
+		(elm2)->field.cqe_prev->field.cqe_next = (elm2);	\
+} while (0)
+
+#endif	/* !_SYS_QUEUE_H_ */
diff --git a/drivers/usb/host/dwc_common_port/dwc_mem.c b/drivers/usb/host/dwc_common_port/dwc_mem.c
new file mode 100644
index 000000000000..f2f9bc694d21
--- /dev/null
+++ b/drivers/usb/host/dwc_common_port/dwc_mem.c
@@ -0,0 +1,172 @@
+#include "dwc_os.h"
+#include "dwc_list.h"
+
+/* Memory Debugging */
+#ifdef DEBUG_MEMORY
+
+struct allocation
+{
+	void *addr;
+	char *func;
+	int line;
+	uint32_t size;
+	int dma;
+	DWC_CIRCLEQ_ENTRY(allocation) entry;
+};
+
+DWC_CIRCLEQ_HEAD(allocation_queue, allocation);
+
+struct allocation_manager
+{
+	struct allocation_queue allocations;
+
+	/* statistics */
+	int num;
+	int num_freed;
+	int num_active;
+	uint32_t total;
+	uint32_t current;
+	uint32_t max;
+};
+
+
+static struct allocation_manager *manager = NULL;
+
+static void add_allocation(uint32_t size, char const* func, int line, void *addr, int dma)
+{
+	struct allocation *a = __DWC_ALLOC_ATOMIC(sizeof(*a));
+	a->func = __DWC_ALLOC_ATOMIC(DWC_STRLEN(func)+1);
+	DWC_MEMCPY(a->func, func, DWC_STRLEN(func)+1);
+	a->line = line;
+	a->size = size;
+	a->addr = addr;
+	a->dma = dma;
+	DWC_CIRCLEQ_INSERT_TAIL(&manager->allocations, a, entry);
+
+	/* Update stats */
+	manager->num ++;
+	manager->num_active ++;
+	manager->total += size;
+	manager->current += size;
+	if (manager->max < manager->current) {
+		manager->max = manager->current;
+	}
+}
+
+static struct allocation *find_allocation(void *addr)
+{
+	struct allocation *a;
+	DWC_CIRCLEQ_FOREACH(a, &manager->allocations, entry) {
+		if (a->addr == addr) {
+			return a;
+		}
+	}
+	return NULL;
+}
+
+static void free_allocation(void *addr, char const* func, int line)
+{
+	struct allocation *a = find_allocation(addr);
+	if (!a && func && (line >= 0)) {
+		DWC_ASSERT(0, "Free of address %p that was never allocated or already freed %s:%d", addr, func, line);
+		return;
+	}
+	DWC_CIRCLEQ_REMOVE(&manager->allocations, a, entry);
+
+	manager->num_active --;
+	manager->num_freed ++;
+	manager->current -= a->size;
+	__DWC_FREE(a->func);
+	__DWC_FREE(a);
+}
+
+void dwc_memory_debug_start(void)
+{
+	DWC_ASSERT(manager == NULL, "Memory debugging has already started\n");
+	if (manager == NULL) {
+		manager = __DWC_ALLOC(sizeof(*manager));
+	}
+
+	DWC_CIRCLEQ_INIT(&manager->allocations);
+	manager->num = 0;
+	manager->num_freed = 0;
+	manager->num_active = 0;
+	manager->total = 0;
+	manager->current = 0;
+	manager->max = 0;
+}
+
+void dwc_memory_debug_stop(void)
+{
+	struct allocation *a;
+	dwc_memory_debug_report();
+
+	DWC_CIRCLEQ_FOREACH(a, &manager->allocations, entry) {
+		DWC_ERROR("Memory leaked from %s:%d\n", a->func, a->line);
+		free_allocation(a->addr, NULL, -1);
+	}
+
+	__DWC_FREE(manager);
+}
+
+void dwc_memory_debug_report(void)
+{
+	struct allocation *a;
+	DWC_PRINTF("\n\n\n----------------- Memory Debugging Report -----------------\n\n");
+	DWC_PRINTF("Num Allocations = %d\n", manager->num);
+	DWC_PRINTF("Freed = %d\n", manager->num_freed);
+	DWC_PRINTF("Active = %d\n", manager->num_active);
+	DWC_PRINTF("Current Memory Used = %d\n", manager->current);
+	DWC_PRINTF("Total Memory Used = %d\n", manager->total);
+	DWC_PRINTF("Maximum Memory Used at Once = %d\n", manager->max);
+	DWC_PRINTF("Unfreed allocations:\n");
+
+	DWC_CIRCLEQ_FOREACH(a, &manager->allocations, entry) {
+		DWC_PRINTF("    addr=%p, size=%d from %s:%d, DMA=%d\n", a->addr, a->size, a->func, a->line, a->dma);
+	}
+}
+
+
+
+/* The replacement functions */
+void *dwc_alloc_debug(uint32_t size, char const* func, int line)
+{
+	void *addr = __DWC_ALLOC(size);
+	add_allocation(size, func, line, addr, 0);
+	return addr;
+}
+
+void *dwc_alloc_atomic_debug(uint32_t size, char const* func, int line)
+{
+	void *addr = __DWC_ALLOC_ATOMIC(size);
+	add_allocation(size, func, line, addr, 0);
+	return addr;
+}
+
+void dwc_free_debug(void *addr, char const* func, int line)
+{
+	free_allocation(addr, func, line);
+	__DWC_FREE(addr);
+}
+
+void *dwc_dma_alloc_debug(uint32_t size, dwc_dma_t *dma_addr, char const *func, int line)
+{
+	void *addr = __DWC_DMA_ALLOC(size, dma_addr);
+	add_allocation(size, func, line, addr, 1);
+	return addr;
+}
+
+void *dwc_dma_alloc_atomic_debug(uint32_t size, dwc_dma_t *dma_addr, char const *func, int line)
+{
+	void *addr = __DWC_DMA_ALLOC_ATOMIC(size, dma_addr);
+	add_allocation(size, func, line, addr, 1);
+	return addr;
+}
+
+void dwc_dma_free_debug(uint32_t size, void *virt_addr, dwc_dma_t dma_addr, char const *func, int line)
+{
+	free_allocation(virt_addr, func, line);
+	__DWC_DMA_FREE(size, virt_addr, dma_addr);
+}
+
+#endif /* DEBUG_MEMORY */
diff --git a/drivers/usb/host/dwc_common_port/dwc_modpow.c b/drivers/usb/host/dwc_common_port/dwc_modpow.c
new file mode 100644
index 000000000000..563332d0c9e4
--- /dev/null
+++ b/drivers/usb/host/dwc_common_port/dwc_modpow.c
@@ -0,0 +1,622 @@
+/* Bignum routines adapted from PUTTY sources.  PuTTY copyright notice follows.
+ *
+ * PuTTY is copyright 1997-2007 Simon Tatham.
+ *
+ * Portions copyright Robert de Bath, Joris van Rantwijk, Delian
+ * Delchev, Andreas Schultz, Jeroen Massar, Wez Furlong, Nicolas Barry,
+ * Justin Bradford, Ben Harris, Malcolm Smith, Ahmad Khalifa, Markus
+ * Kuhn, and CORE SDI S.A.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT.  IN NO EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
+ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef CONFIG_MACH_IPMATE
+
+
+#include "dwc_modpow.h"
+
+#define BIGNUM_INT_MASK  0xFFFFFFFFUL
+#define BIGNUM_TOP_BIT   0x80000000UL
+#define BIGNUM_INT_BITS  32
+
+
+static void *snmalloc(size_t n, size_t size)
+{
+    void *p;
+    size *= n;
+    if (size == 0) size = 1;
+    p = DWC_ALLOC(size);
+    return p;
+}
+
+#define snewn(n, type) ((type *)snmalloc((n), sizeof(type)))
+#define sfree DWC_FREE
+
+/*
+ * Usage notes:
+ *  * Do not call the DIVMOD_WORD macro with expressions such as array
+ *    subscripts, as some implementations object to this (see below).
+ *  * Note that none of the division methods below will cope if the
+ *    quotient won't fit into BIGNUM_INT_BITS. Callers should be careful
+ *    to avoid this case.
+ *    If this condition occurs, in the case of the x86 DIV instruction,
+ *    an overflow exception will occur, which (according to a correspondent)
+ *    will manifest on Windows as something like
+ *      0xC0000095: Integer overflow
+ *    The C variant won't give the right answer, either.
+ */
+
+#define MUL_WORD(w1, w2) ((BignumDblInt)w1 * w2)
+
+#if defined __GNUC__ && defined __i386__
+#define DIVMOD_WORD(q, r, hi, lo, w) \
+    __asm__("div %2" : \
+	    "=d" (r), "=a" (q) : \
+	    "r" (w), "d" (hi), "a" (lo))
+#else
+#define DIVMOD_WORD(q, r, hi, lo, w) do { \
+    BignumDblInt n = (((BignumDblInt)hi) << BIGNUM_INT_BITS) | lo; \
+    q = n / w; \
+    r = n % w; \
+} while (0)
+#endif
+
+//    q = n / w;                                
+//    r = n % w;                                
+
+#define BIGNUM_INT_BYTES (BIGNUM_INT_BITS / 8)
+
+#define BIGNUM_INTERNAL
+
+static Bignum newbn(int length)
+{
+    Bignum b = snewn(length + 1, BignumInt);
+    //if (!b)
+    //abort();		       /* FIXME */
+    DWC_MEMSET(b, 0, (length + 1) * sizeof(*b));
+    b[0] = length;
+    return b;
+}
+
+void freebn(Bignum b)
+{
+    /*
+     * Burn the evidence, just in case.
+     */
+    DWC_MEMSET(b, 0, sizeof(b[0]) * (b[0] + 1));
+    sfree(b);
+}
+
+/*
+ * Compute c = a * b.
+ * Input is in the first len words of a and b.
+ * Result is returned in the first 2*len words of c.
+ */
+static void internal_mul(BignumInt *a, BignumInt *b,
+			 BignumInt *c, int len)
+{
+    int i, j;
+    BignumDblInt t;
+
+    for (j = 0; j < 2 * len; j++)
+	c[j] = 0;
+
+    for (i = len - 1; i >= 0; i--) {
+	t = 0;
+	for (j = len - 1; j >= 0; j--) {
+	    t += MUL_WORD(a[i], (BignumDblInt) b[j]);
+	    t += (BignumDblInt) c[i + j + 1];
+	    c[i + j + 1] = (BignumInt) t;
+	    t = t >> BIGNUM_INT_BITS;
+	}
+	c[i] = (BignumInt) t;
+    }
+}
+
+static void internal_add_shifted(BignumInt *number,
+				 unsigned n, int shift)
+{
+    int word = 1 + (shift / BIGNUM_INT_BITS);
+    int bshift = shift % BIGNUM_INT_BITS;
+    BignumDblInt addend;
+
+    addend = (BignumDblInt)n << bshift;
+
+    while (addend) {
+	addend += number[word];
+	number[word] = (BignumInt) addend & BIGNUM_INT_MASK;
+	addend >>= BIGNUM_INT_BITS;
+	word++;
+    }
+}
+
+/*
+ * Compute a = a % m.
+ * Input in first alen words of a and first mlen words of m.
+ * Output in first alen words of a
+ * (of which first alen-mlen words will be zero).
+ * The MSW of m MUST have its high bit set.
+ * Quotient is accumulated in the `quotient' array, which is a Bignum
+ * rather than the internal bigendian format. Quotient parts are shifted
+ * left by `qshift' before adding into quot.
+ */
+static void internal_mod(BignumInt *a, int alen,
+			 BignumInt *m, int mlen,
+			 BignumInt *quot, int qshift)
+{
+    BignumInt m0, m1;
+    unsigned int h;
+    int i, k;
+
+    m0 = m[0];
+    if (mlen > 1)
+	m1 = m[1];
+    else
+	m1 = 0;
+
+    for (i = 0; i <= alen - mlen; i++) {
+	BignumDblInt t;
+	unsigned int q, r, c, ai1;
+
+	if (i == 0) {
+	    h = 0;
+	} else {
+	    h = a[i - 1];
+	    a[i - 1] = 0;
+	}
+
+	if (i == alen - 1)
+	    ai1 = 0;
+	else
+	    ai1 = a[i + 1];
+
+	/* Find q = h:a[i] / m0 */
+	if (h >= m0) {
+	    /*
+	     * Special case.
+	     * 
+	     * To illustrate it, suppose a BignumInt is 8 bits, and
+	     * we are dividing (say) A1:23:45:67 by A1:B2:C3. Then
+	     * our initial division will be 0xA123 / 0xA1, which
+	     * will give a quotient of 0x100 and a divide overflow.
+	     * However, the invariants in this division algorithm
+	     * are not violated, since the full number A1:23:... is
+	     * _less_ than the quotient prefix A1:B2:... and so the
+	     * following correction loop would have sorted it out.
+	     * 
+	     * In this situation we set q to be the largest
+	     * quotient we _can_ stomach (0xFF, of course).
+	     */
+	    q = BIGNUM_INT_MASK;
+	} else {
+	    /* Macro doesn't want an array subscript expression passed
+	     * into it (see definition), so use a temporary. */
+	    BignumInt tmplo = a[i];
+	    DIVMOD_WORD(q, r, h, tmplo, m0);
+
+	    /* Refine our estimate of q by looking at
+	     h:a[i]:a[i+1] / m0:m1 */
+	    t = MUL_WORD(m1, q);
+	    if (t > ((BignumDblInt) r << BIGNUM_INT_BITS) + ai1) {
+		q--;
+		t -= m1;
+		r = (r + m0) & BIGNUM_INT_MASK;     /* overflow? */
+		if (r >= (BignumDblInt) m0 &&
+		    t > ((BignumDblInt) r << BIGNUM_INT_BITS) + ai1) q--;
+	    }
+	}
+
+	/* Subtract q * m from a[i...] */
+	c = 0;
+	for (k = mlen - 1; k >= 0; k--) {
+	    t = MUL_WORD(q, m[k]);
+	    t += c;
+	    c = (unsigned)(t >> BIGNUM_INT_BITS);
+	    if ((BignumInt) t > a[i + k])
+		c++;
+	    a[i + k] -= (BignumInt) t;
+	}
+
+	/* Add back m in case of borrow */
+	if (c != h) {
+	    t = 0;
+	    for (k = mlen - 1; k >= 0; k--) {
+		t += m[k];
+		t += a[i + k];
+		a[i + k] = (BignumInt) t;
+		t = t >> BIGNUM_INT_BITS;
+	    }
+	    q--;
+	}
+	if (quot)
+	    internal_add_shifted(quot, q, qshift + BIGNUM_INT_BITS * (alen - mlen - i));
+    }
+}
+
+/*
+ * Compute p % mod.
+ * The most significant word of mod MUST be non-zero.
+ * We assume that the result array is the same size as the mod array.
+ * We optionally write out a quotient if `quotient' is non-NULL.
+ * We can avoid writing out the result if `result' is NULL.
+ */
+void bigdivmod(Bignum p, Bignum mod, Bignum result, Bignum quotient)
+{
+    BignumInt *n, *m;
+    int mshift;
+    int plen, mlen, i, j;
+
+    /* Allocate m of size mlen, copy mod to m */
+    /* We use big endian internally */
+    mlen = mod[0];
+    m = snewn(mlen, BignumInt);
+    for (j = 0; j < mlen; j++)
+	m[j] = mod[mod[0] - j];
+
+    /* Shift m left to make msb bit set */
+    for (mshift = 0; mshift < BIGNUM_INT_BITS-1; mshift++)
+	if ((m[0] << mshift) & BIGNUM_TOP_BIT)
+	    break;
+    if (mshift) {
+	for (i = 0; i < mlen - 1; i++)
+	    m[i] = (m[i] << mshift) | (m[i + 1] >> (BIGNUM_INT_BITS - mshift));
+	m[mlen - 1] = m[mlen - 1] << mshift;
+    }
+
+    plen = p[0];
+    /* Ensure plen > mlen */
+    if (plen <= mlen)
+	plen = mlen + 1;
+
+    /* Allocate n of size plen, copy p to n */
+    n = snewn(plen, BignumInt);
+    for (j = 0; j < plen; j++)
+	n[j] = 0;
+    for (j = 1; j <= (int)p[0]; j++)
+	n[plen - j] = p[j];
+
+    /* Main computation */
+    internal_mod(n, plen, m, mlen, quotient, mshift);
+
+    /* Fixup result in case the modulus was shifted */
+    if (mshift) {
+	for (i = plen - mlen - 1; i < plen - 1; i++)
+	    n[i] = (n[i] << mshift) | (n[i + 1] >> (BIGNUM_INT_BITS - mshift));
+	n[plen - 1] = n[plen - 1] << mshift;
+	internal_mod(n, plen, m, mlen, quotient, 0);
+	for (i = plen - 1; i >= plen - mlen; i--)
+	    n[i] = (n[i] >> mshift) | (n[i - 1] << (BIGNUM_INT_BITS - mshift));
+    }
+
+    /* Copy result to buffer */
+    if (result) {
+	for (i = 1; i <= (int)result[0]; i++) {
+	    int j = plen - i;
+	    result[i] = j >= 0 ? n[j] : 0;
+	}
+    }
+
+    /* Free temporary arrays */
+    for (i = 0; i < mlen; i++)
+	m[i] = 0;
+    sfree(m);
+    for (i = 0; i < plen; i++)
+	n[i] = 0;
+    sfree(n);
+}
+
+/*
+ * Simple remainder.
+ */
+Bignum bigmod(Bignum a, Bignum b)
+{
+    Bignum r = newbn(b[0]);
+    bigdivmod(a, b, r, NULL);
+    return r;
+}
+
+/*
+ * Compute (base ^ exp) % mod.
+ */
+Bignum dwc_modpow(Bignum base_in, Bignum exp, Bignum mod)
+{
+    BignumInt *a, *b, *n, *m;
+    int mshift;
+    int mlen, i, j;
+    Bignum base, result;
+
+    /*
+     * The most significant word of mod needs to be non-zero. It
+     * should already be, but let's make sure.
+     */
+    //assert(mod[mod[0]] != 0);
+
+    /*
+     * Make sure the base is smaller than the modulus, by reducing
+     * it modulo the modulus if not.
+     */
+    base = bigmod(base_in, mod);
+
+    /* Allocate m of size mlen, copy mod to m */
+    /* We use big endian internally */
+    mlen = mod[0];
+    m = snewn(mlen, BignumInt);
+    for (j = 0; j < mlen; j++)
+	m[j] = mod[mod[0] - j];
+
+    /* Shift m left to make msb bit set */
+    for (mshift = 0; mshift < BIGNUM_INT_BITS - 1; mshift++)
+	if ((m[0] << mshift) & BIGNUM_TOP_BIT)
+	    break;
+    if (mshift) {
+	for (i = 0; i < mlen - 1; i++)
+	    m[i] =
+		(m[i] << mshift) | (m[i + 1] >>
+				    (BIGNUM_INT_BITS - mshift));
+	m[mlen - 1] = m[mlen - 1] << mshift;
+    }
+
+    /* Allocate n of size mlen, copy base to n */
+    n = snewn(mlen, BignumInt);
+    i = mlen - base[0];
+    for (j = 0; j < i; j++)
+	n[j] = 0;
+    for (j = 0; j < base[0]; j++)
+	n[i + j] = base[base[0] - j];
+
+    /* Allocate a and b of size 2*mlen. Set a = 1 */
+    a = snewn(2 * mlen, BignumInt);
+    b = snewn(2 * mlen, BignumInt);
+    for (i = 0; i < 2 * mlen; i++)
+	a[i] = 0;
+    a[2 * mlen - 1] = 1;
+
+    /* Skip leading zero bits of exp. */
+    i = 0;
+    j = BIGNUM_INT_BITS - 1;
+    while (i < exp[0] && (exp[exp[0] - i] & (1 << j)) == 0) {
+	j--;
+	if (j < 0) {
+	    i++;
+	    j = BIGNUM_INT_BITS - 1;
+	}
+    }
+
+    /* Main computation */
+    while (i < exp[0]) {
+	while (j >= 0) {
+	    internal_mul(a + mlen, a + mlen, b, mlen);
+	    internal_mod(b, mlen * 2, m, mlen, NULL, 0);
+	    if ((exp[exp[0] - i] & (1 << j)) != 0) {
+		internal_mul(b + mlen, n, a, mlen);
+		internal_mod(a, mlen * 2, m, mlen, NULL, 0);
+	    } else {
+		BignumInt *t;
+		t = a;
+		a = b;
+		b = t;
+	    }
+	    j--;
+	}
+	i++;
+	j = BIGNUM_INT_BITS - 1;
+    }
+
+    /* Fixup result in case the modulus was shifted */
+    if (mshift) {
+	for (i = mlen - 1; i < 2 * mlen - 1; i++)
+	    a[i] =
+		(a[i] << mshift) | (a[i + 1] >>
+				    (BIGNUM_INT_BITS - mshift));
+	a[2 * mlen - 1] = a[2 * mlen - 1] << mshift;
+	internal_mod(a, mlen * 2, m, mlen, NULL, 0);
+	for (i = 2 * mlen - 1; i >= mlen; i--)
+	    a[i] =
+		(a[i] >> mshift) | (a[i - 1] <<
+				    (BIGNUM_INT_BITS - mshift));
+    }
+
+    /* Copy result to buffer */
+    result = newbn(mod[0]);
+    for (i = 0; i < mlen; i++)
+	result[result[0] - i] = a[i + mlen];
+    while (result[0] > 1 && result[result[0]] == 0)
+	result[0]--;
+
+    /* Free temporary arrays */
+    for (i = 0; i < 2 * mlen; i++)
+	a[i] = 0;
+    sfree(a);
+    for (i = 0; i < 2 * mlen; i++)
+	b[i] = 0;
+    sfree(b);
+    for (i = 0; i < mlen; i++)
+	m[i] = 0;
+    sfree(m);
+    for (i = 0; i < mlen; i++)
+	n[i] = 0;
+    sfree(n);
+
+    freebn(base);
+
+    return result;
+}
+
+
+#ifdef UNITTEST
+
+static __u32 dh_p[] = {
+	96,
+	0xFFFFFFFF,
+	0xFFFFFFFF,
+	0xA93AD2CA,
+	0x4B82D120,
+	0xE0FD108E,
+	0x43DB5BFC,
+	0x74E5AB31,
+	0x08E24FA0,
+	0xBAD946E2,
+	0x770988C0,
+	0x7A615D6C,
+	0xBBE11757,
+	0x177B200C,
+	0x521F2B18,
+	0x3EC86A64,
+	0xD8760273,
+	0xD98A0864,
+	0xF12FFA06,
+	0x1AD2EE6B,
+	0xCEE3D226,
+	0x4A25619D,
+	0x1E8C94E0,
+	0xDB0933D7,
+	0xABF5AE8C,
+	0xA6E1E4C7,
+	0xB3970F85,
+	0x5D060C7D,
+	0x8AEA7157,
+	0x58DBEF0A,
+	0xECFB8504,
+	0xDF1CBA64,
+	0xA85521AB,
+	0x04507A33,
+	0xAD33170D,
+	0x8AAAC42D,
+	0x15728E5A,
+	0x98FA0510,
+	0x15D22618,
+	0xEA956AE5,
+	0x3995497C,
+	0x95581718,
+	0xDE2BCBF6,
+	0x6F4C52C9,
+	0xB5C55DF0,
+	0xEC07A28F,
+	0x9B2783A2,
+	0x180E8603,
+	0xE39E772C,
+	0x2E36CE3B,
+	0x32905E46,
+	0xCA18217C,
+	0xF1746C08,
+	0x4ABC9804,
+	0x670C354E,
+	0x7096966D,
+	0x9ED52907,
+	0x208552BB,
+	0x1C62F356,
+	0xDCA3AD96,
+	0x83655D23,
+	0xFD24CF5F,
+	0x69163FA8,
+	0x1C55D39A,
+	0x98DA4836,
+	0xA163BF05,
+	0xC2007CB8,
+	0xECE45B3D,
+	0x49286651,
+	0x7C4B1FE6,
+	0xAE9F2411,
+	0x5A899FA5,
+	0xEE386BFB,
+	0xF406B7ED,
+	0x0BFF5CB6,
+	0xA637ED6B,
+	0xF44C42E9,
+	0x625E7EC6,
+	0xE485B576,
+	0x6D51C245,
+	0x4FE1356D,
+	0xF25F1437,
+	0x302B0A6D,
+	0xCD3A431B,
+	0xEF9519B3,
+	0x8E3404DD,
+	0x514A0879,
+	0x3B139B22,
+	0x020BBEA6,
+	0x8A67CC74,
+	0x29024E08,
+	0x80DC1CD1,
+	0xC4C6628B,
+	0x2168C234,
+	0xC90FDAA2,
+	0xFFFFFFFF,
+	0xFFFFFFFF,
+};
+
+static __u32 dh_a[] = {
+	8,
+	0xdf367516,
+	0x86459caa,
+	0xe2d459a4,
+	0xd910dae0,
+	0x8a8b5e37,
+	0x67ab31c6,
+	0xf0b55ea9,
+	0x440051d6,
+};
+
+static __u32 dh_b[] = {
+	8,
+	0xded92656,
+	0xe07a048a,
+	0x6fa452cd,
+	0x2df89d30,
+	0xc75f1b0f,
+	0x8ce3578f, 
+	0x7980a324,
+	0x5daec786,
+};
+
+static __u32 dh_g[] = {
+	1,
+	2,
+};
+
+int main(void)
+{
+	int i;
+	__u32 *k;
+	k = modpow(dh_g, dh_a, dh_p);
+
+	printf("\n\n");
+	for (i=0; i<k[0]; i++) {
+		__u32 word32 = k[k[0] - i];
+		__u16 l = word32 & 0xffff;
+		__u16 m = (word32 & 0xffff0000) >> 16;
+		printf("%04x %04x ", m, l);
+		if (!((i + 1)%13)) printf("\n");
+	}
+	printf("\n\n");
+
+	if ((k[0] == 0x60) && (k[1] == 0x28e490e5) && (k[0x60] == 0x5a0d3d4e)) {
+		printf("PASS\n\n");
+	}
+	else {
+		printf("FAIL\n\n");
+	}
+
+}
+
+#endif /* UNITTEST */
+
+#endif /* CONFIG_MACH_IPMATE */
diff --git a/drivers/usb/host/dwc_common_port/dwc_modpow.h b/drivers/usb/host/dwc_common_port/dwc_modpow.h
new file mode 100644
index 000000000000..980f9f14f041
--- /dev/null
+++ b/drivers/usb/host/dwc_common_port/dwc_modpow.h
@@ -0,0 +1,26 @@
+/*
+ * dwc_modpow.h
+ * See dwc_modpow.c for license and changes
+ */
+#ifndef _DWC_MODPOW_H
+#define _DWC_MODPOW_H
+
+#include "dwc_os.h"
+
+/** @file
+ *
+ * This file defines the module exponentiation function which is only used
+ * internally by the DWC UWB modules for calculation of PKs during numeric
+ * association.  The routine is taken from the PUTTY, an open source terminal
+ * emulator.  The PUTTY License is preserved in the dwc_modpow.c file.
+ *
+ */
+
+typedef uint32_t BignumInt;
+typedef uint64_t BignumDblInt;
+typedef BignumInt *Bignum;
+
+/* Compute modular exponentiaion */
+extern Bignum dwc_modpow(Bignum base_in, Bignum exp, Bignum mod);
+
+#endif /* _LINUX_BIGNUM_H */
diff --git a/drivers/usb/host/dwc_common_port/dwc_notifier.c b/drivers/usb/host/dwc_common_port/dwc_notifier.c
new file mode 100644
index 000000000000..e44bb81dbc46
--- /dev/null
+++ b/drivers/usb/host/dwc_common_port/dwc_notifier.c
@@ -0,0 +1,256 @@
+#include "dwc_notifier.h"
+#include "dwc_list.h"
+
+typedef struct dwc_observer
+{
+	void *observer;
+	dwc_notifier_callback_t callback;
+	void *data;
+	char *notification;
+	DWC_CIRCLEQ_ENTRY(dwc_observer) list_entry;
+} observer_t;
+
+DWC_CIRCLEQ_HEAD(observer_queue, dwc_observer);
+
+typedef struct dwc_notifier
+{
+	void *object;
+	struct observer_queue observers;
+	DWC_CIRCLEQ_ENTRY(dwc_notifier) list_entry;
+} notifier_t;
+
+DWC_CIRCLEQ_HEAD(notifier_queue, dwc_notifier);
+
+typedef struct manager
+{
+	dwc_workq_t *wq;
+	dwc_mutex_t *mutex;
+	struct notifier_queue notifiers;
+} manager_t;
+
+static manager_t *manager = NULL;
+
+static void create_manager(void)
+{
+	manager = DWC_ALLOC(sizeof(manager_t));
+	DWC_CIRCLEQ_INIT(&manager->notifiers);
+	manager->wq = DWC_WORKQ_ALLOC("DWC Notification WorkQ");
+}
+
+static void free_manager(void)
+{
+	DWC_WORKQ_FREE(manager->wq);
+	/* All notifiers must have unregistered themselves before this module
+	 * can be removed.  Hitting this assertion indicates a programmer
+	 * error. */
+	DWC_ASSERT(DWC_CIRCLEQ_EMPTY(&manager->notifiers), "Notification manager being freed before all notifiers have been removed");
+	DWC_FREE(manager);
+}
+
+#ifdef DEBUG
+static void dump_manager(void)
+{
+	notifier_t *n;
+	observer_t *o;
+	DWC_ASSERT(manager, "Notification manager not found");
+	DWC_DEBUG("List of all notifiers and observers:");
+	DWC_CIRCLEQ_FOREACH(n, &manager->notifiers, list_entry) {
+		DWC_DEBUG("Notifier %p has observers:", n->object);
+		DWC_CIRCLEQ_FOREACH(o, &n->observers, list_entry) {
+			DWC_DEBUG("    %p watching %s", o->observer, o->notification);
+		}
+	}
+}
+#else
+#define dump_manager(...)
+#endif
+
+static observer_t *alloc_observer(void *observer, char *notification, dwc_notifier_callback_t callback, void *data)
+{
+	observer_t *new_observer = DWC_ALLOC(sizeof(observer_t));
+	DWC_CIRCLEQ_INIT_ENTRY(new_observer, list_entry);
+	new_observer->observer = observer;
+	new_observer->notification = notification;
+	new_observer->callback = callback;
+	new_observer->data = data;
+	return new_observer;
+}
+
+static void free_observer(observer_t *observer)
+{
+	DWC_FREE(observer);
+}
+
+static notifier_t *alloc_notifier(void *object)
+{
+	notifier_t *notifier;
+
+	if (!object) {
+		return NULL;
+	}
+
+	notifier = DWC_ALLOC(sizeof(notifier_t));
+	DWC_CIRCLEQ_INIT(&notifier->observers);
+	DWC_CIRCLEQ_INIT_ENTRY(notifier, list_entry);
+
+	notifier->object = object;
+	return notifier;
+}
+
+static void free_notifier(notifier_t *notifier)
+{
+	observer_t *observer;
+	DWC_CIRCLEQ_FOREACH(observer, &notifier->observers, list_entry) {
+		free_observer(observer);
+	}
+	DWC_FREE(notifier);
+}
+
+static notifier_t *find_notifier(void *object)
+{
+	notifier_t *notifier;
+	if (!object) {
+		return NULL;
+	}
+	DWC_ASSERT(manager, "Notification manager not found");
+	DWC_CIRCLEQ_FOREACH(notifier, &manager->notifiers, list_entry) {
+		if (notifier->object == object) {
+			return notifier;
+		}
+	}
+	return NULL;
+}
+
+void dwc_alloc_notification_manager(void)
+{
+	create_manager();
+}
+
+void dwc_free_notification_manager(void)
+{
+	free_manager();
+}
+
+dwc_notifier_t *dwc_register_notifier(void *object)
+{
+	notifier_t *notifier = find_notifier(object);
+	DWC_ASSERT(manager, "Notification manager not found");
+	if (notifier) {
+		DWC_ERROR("Notifier %p is already registered", object);
+		return NULL;
+	}
+
+	notifier = alloc_notifier(object);
+	DWC_CIRCLEQ_INSERT_TAIL(&manager->notifiers, notifier, list_entry);
+
+
+	DWC_INFO("Notifier %p registered", object);
+	dump_manager();
+
+	return notifier;
+}
+
+void dwc_unregister_notifier(dwc_notifier_t *notifier)
+{
+	DWC_ASSERT(manager, "Notification manager not found");
+	if (!DWC_CIRCLEQ_EMPTY(&notifier->observers)) {
+		observer_t *o;
+		DWC_ERROR("Notifier %p has active observers when removing", notifier->object);
+		DWC_CIRCLEQ_FOREACH(o, &notifier->observers, list_entry) {
+			DWC_DEBUG("    %p watching %s", o->observer, o->notification);
+		}
+		DWC_ASSERT(DWC_CIRCLEQ_EMPTY(&notifier->observers), "Notifier %p has active observers when removing", notifier);
+	}
+
+	DWC_CIRCLEQ_REMOVE_INIT(&manager->notifiers, notifier, list_entry);
+	free_notifier(notifier);
+
+	DWC_INFO("Notifier unregistered");
+	dump_manager();
+}
+
+/* Add an observer to observe the notifier for a particular state, event, or notification. */
+int dwc_add_observer(void *observer, void *object, char *notification, dwc_notifier_callback_t callback, void *data)
+{
+	notifier_t *notifier = find_notifier(object);
+	observer_t *new_observer;
+	if (!notifier) {
+		DWC_ERROR("Notifier %p is not found when adding observer", object);
+		return -1;
+	}
+
+	new_observer = alloc_observer(observer, notification, callback, data);
+
+	DWC_CIRCLEQ_INSERT_TAIL(&notifier->observers, new_observer, list_entry);
+
+	DWC_INFO("Added observer %p to notifier %p observing notification %s, callback=%p, data=%p",
+		 observer, object, notification, callback, data);
+
+	dump_manager();
+	return 0;
+}
+
+int dwc_remove_observer(void *observer)
+{
+	notifier_t *n;
+	DWC_ASSERT(manager, "Notification manager not found");
+	DWC_CIRCLEQ_FOREACH(n, &manager->notifiers, list_entry) {
+		observer_t *o;
+		observer_t *o2;
+		DWC_CIRCLEQ_FOREACH_SAFE(o, o2, &n->observers, list_entry) {
+			if (o->observer == observer) {
+				DWC_CIRCLEQ_REMOVE_INIT(&n->observers, o, list_entry);
+				DWC_INFO("Removing observer %p from notifier %p watching notification %s:",
+					 o->observer, n->object, o->notification);
+				free_observer(o);
+			}
+		}
+	}
+
+	dump_manager();
+	return 0;
+}
+
+typedef struct callback_data
+{
+	dwc_notifier_callback_t cb;
+	void *observer;
+	void *data;
+	void *object;
+	void *notification;
+	void *notification_data;
+} cb_data_t;
+
+static void cb_task(void *data)
+{
+	cb_data_t *cb = (cb_data_t *)data;
+	cb->cb(cb->object, cb->notification, cb->observer, cb->notification_data, cb->data);
+	DWC_FREE(cb);
+}
+
+void dwc_notify(dwc_notifier_t *notifier, char *notification, void *notification_data)
+{
+	observer_t *o;
+	DWC_ASSERT(manager, "Notification manager not found");
+	DWC_CIRCLEQ_FOREACH(o, &notifier->observers, list_entry) {
+		int len = DWC_STRLEN(notification);
+		if (DWC_STRLEN(o->notification) != len) {
+			continue;
+		}
+
+		if (DWC_STRNCMP(o->notification, notification, len) == 0) {
+			cb_data_t *cb_data = DWC_ALLOC(sizeof(cb_data_t));
+			cb_data->cb = o->callback;
+			cb_data->observer = o->observer;
+			cb_data->data = o->data;
+			cb_data->object = notifier->object;
+			cb_data->notification = notification;
+			cb_data->notification_data = notification_data;
+			DWC_DEBUG("Observer found %p for notification %s", o->observer, notification);
+			DWC_WORKQ_SCHEDULE(manager->wq, cb_task, cb_data,
+					   "Notify callback from %p for Notification %s, to observer %p",
+					   cb_data->object, notification, cb_data->observer);
+		}
+	}
+}
+
diff --git a/drivers/usb/host/dwc_common_port/dwc_notifier.h b/drivers/usb/host/dwc_common_port/dwc_notifier.h
new file mode 100644
index 000000000000..a1388d17d156
--- /dev/null
+++ b/drivers/usb/host/dwc_common_port/dwc_notifier.h
@@ -0,0 +1,112 @@
+
+#ifndef __DWC_NOTIFIER_H__
+#define __DWC_NOTIFIER_H__
+
+#include "dwc_os.h"
+
+/** @file
+ *
+ * A simple implementation of the Observer pattern.  Any "module" can
+ * register as an observer or notifier.  The notion of "module" is abstract and
+ * can mean anything used to identify either an observer or notifier.  Usually
+ * it will be a pointer to a data structure which contains some state, ie an
+ * object.
+ *
+ * Before any notifiers can be added, the global notification manager must be
+ * brought up with dwc_alloc_notification_manager().
+ * dwc_free_notification_manager() will bring it down and free all resources.
+ * These would typically be called upon module load and unload.  The
+ * notification manager is a single global instance that handles all registered
+ * observable modules and observers so this should be done only once.
+ *
+ * A module can be observable by using Notifications to publicize some general
+ * information about it's state or operation.  It does not care who listens, or
+ * even if anyone listens, or what they do with the information.  The observable
+ * modules do not need to know any information about it's observers or their
+ * interface, or their state or data.
+ *
+ * Any module can register to emit Notifications.  It should publish a list of
+ * notifications that it can emit and their behavior, such as when they will get
+ * triggered, and what information will be provided to the observer.  Then it
+ * should register itself as an observable module. See dwc_register_notifier().
+ *
+ * Any module can observe any observable, registered module, provided it has a
+ * handle to the other module and knows what notifications to observe.  See
+ * dwc_add_observer().
+ *
+ * A function of type dwc_notifier_callback_t is called whenever a notification
+ * is triggered with one or more observers observing it.  This function is
+ * called in it's own process so it may sleep or block if needed.  It is
+ * guaranteed to be called sometime after the notification has occurred and will
+ * be called once per each time the notification is triggered.  It will NOT be
+ * called in the same process context used to trigger the notification.
+ *
+ * @section Limitiations
+ *
+ * Keep in mind that Notifications that can be triggered in rapid sucession may
+ * schedule too many processes too handle.  Be aware of this limitation when
+ * designing to use notifications, and only add notifications for appropriate
+ * observable information.
+ *
+ * Also Notification callbacks are not synchronous.  If you need to synchronize
+ * the behavior between module/observer you must use other means.  And perhaps
+ * that will mean Notifications are not the proper solution.
+ */
+
+struct dwc_notifier;
+typedef struct dwc_notifier dwc_notifier_t;
+
+/** The callback function must be of this type.
+ *
+ * @param object This is the object that is being observed.
+ * @param notification This is the notification that was triggered.
+ * @param observer This is the observer
+ * @param notification_data This is notification-specific data that the notifier
+ * has included in this notification.  The value of this should be published in
+ * the documentation of the observable module with the notifications.
+ * @param user_data This is any custom data that the observer provided when
+ * adding itself as an observer to the notification. */
+typedef void (*dwc_notifier_callback_t)(void *object, char *notification, void *observer, void *notification_data, void *user_data);
+
+/** Brings up the notification manager. */
+extern void dwc_alloc_notification_manager(void);
+/** Brings down the notification manager. */
+extern void dwc_free_notification_manager(void);
+
+/** This function register an observable module.  A dwc_notifier_t object is
+ * returned to the observable module.  This is an opaque object that is used by
+ * the observable module to trigger notifications.  This object should only be
+ * accessible to functions that are authorized to trigger notifications for this
+ * module.  Observers do not need this object. */
+extern dwc_notifier_t *dwc_register_notifier(void *object);
+
+/** This function unregister an observable module.  All observers have to be
+ * removed prior to unregistration. */
+extern void dwc_unregister_notifier(dwc_notifier_t *notifier);
+
+/** Add a module as an observer to the observable module.  The observable module
+ * needs to have previously registered with the notification manager.
+ *
+ * @param observer The observer module
+ * @param object The module to observe
+ * @param notification The notification to observe
+ * @param callback The callback function to call
+ * @param user_data Any additional user data to pass into the callback function */
+extern int dwc_add_observer(void *observer, void *object, char *notification, dwc_notifier_callback_t callback, void *user_data);
+
+/** Removes the specified observer from all notifications that it is currently
+ * observing. */
+extern int dwc_remove_observer(void *observer);
+
+/** This function triggers a Notification.  It should be called by the
+ * observable module, or any module or library which the observable module
+ * allows to trigger notification on it's behalf.  Such as the dwc_cc_t.
+ *
+ * dwc_notify is a non-blocking function.  Callbacks are scheduled called in
+ * their own process context for each trigger.  Callbacks can be blocking.
+ * dwc_notify can be called from interrupt context if needed.
+ *
+ */
+void dwc_notify(dwc_notifier_t *notifier, char *notification, void *notification_data);
+
+#endif /* __DWC_NOTIFIER_H__ */
diff --git a/drivers/usb/host/dwc_common_port/dwc_os.h b/drivers/usb/host/dwc_common_port/dwc_os.h
new file mode 100644
index 000000000000..8d3801408335
--- /dev/null
+++ b/drivers/usb/host/dwc_common_port/dwc_os.h
@@ -0,0 +1,924 @@
+/* =========================================================================
+ * $File: //dwh/usb_iip/dev/software/dwc_common_port/dwc_os.h $
+ * $Revision: #2 $
+ * $Date: 2009/04/02 $
+ * $Change: 1224130 $
+ *
+ * Synopsys Portability Library Software and documentation
+ * (hereinafter, "Software") is an Unsupported proprietary work of
+ * Synopsys, Inc. unless otherwise expressly agreed to in writing
+ * between Synopsys and you.
+ *
+ * The Software IS NOT an item of Licensed Software or Licensed Product
+ * under any End User Software License Agreement or Agreement for
+ * Licensed Product with Synopsys or any supplement thereto. You are
+ * permitted to use and redistribute this Software in source and binary
+ * forms, with or without modification, provided that redistributions
+ * of source code must retain this notice. You may not view, use,
+ * disclose, copy or distribute this file or any information contained
+ * herein except pursuant to this license grant from Synopsys. If you
+ * do not agree with this notice, including the disclaimer below, then
+ * you are not authorized to use the Software.
+ *
+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
+ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
+ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ * ========================================================================= */
+#ifndef _DWC_OS_H_
+#define _DWC_OS_H_
+
+/** @file
+ *
+ * DWC portability library, low level os-wrapper functions
+ *
+ */
+
+/* These basic types need to be defined by some OS header file or custom header
+ * file for your specific target architecture.
+ *
+ * uint8_t, int8_t, uint16_t, int16_t, uint32_t, int32_t, uint64_t, int64_t
+ *
+ * Any custom or alternate header file must be added and enabled here.
+ */
+
+#ifdef DWC_LINUX
+#  include <linux/types.h>
+#  ifdef CONFIG_DEBUG_MUTEXES
+#    include <linux/mutex.h>
+#  endif
+#else
+#  include <stdint.h>
+#endif
+
+
+/** @name Primitive Types and Values */
+
+/** We define a boolean type for consistency.  Can be either YES or NO */
+typedef uint8_t dwc_bool_t;
+#define YES  1
+#define NO   0
+
+/** @todo make them positive and return the negative error code */
+/** @name Error Codes */
+#define DWC_E_INVALID         1001
+#define DWC_E_NO_MEMORY       1002
+#define DWC_E_NO_DEVICE       1003
+#define DWC_E_NOT_SUPPORTED   1004
+#define DWC_E_TIMEOUT         1005
+#define DWC_E_BUSY            1006
+#define DWC_E_AGAIN           1007
+#define DWC_E_RESTART         1008
+#define DWC_E_ABORT           1009
+#define DWC_E_SHUTDOWN        1010
+#define DWC_E_NO_DATA         1011
+#define DWC_E_DISCONNECT      2000
+#define DWC_E_UNKNOWN         3000
+#define DWC_E_NO_STREAM_RES   4001
+#define DWC_E_COMMUNICATION   4002
+#define DWC_E_OVERFLOW        4003
+#define DWC_E_PROTOCOL        4004
+#define DWC_E_IN_PROGRESS     4005
+#define DWC_E_PIPE            4006
+#define DWC_E_IO              4007
+#define DWC_E_NO_SPACE        4008
+
+/** @name Tracing/Logging Functions
+ *
+ * These function provide the capability to add tracing, debugging, and error
+ * messages, as well exceptions as assertions.  The WUDEV uses these
+ * extensively.  These could be logged to the main console, the serial port, an
+ * internal buffer, etc.  These functions could also be no-op if they are too
+ * expensive on your system.  By default undefining the DEBUG macro already
+ * no-ops some of these functions. */
+
+#include <stdarg.h>
+
+/** Returns non-zero if in interrupt context. */
+extern dwc_bool_t DWC_IN_IRQ(void);
+#define dwc_in_irq DWC_IN_IRQ
+
+/** Returns "IRQ" if DWC_IN_IRQ is true. */
+static inline char *dwc_irq(void) {
+	return DWC_IN_IRQ() ? "IRQ" : "";
+}
+
+/**
+ * A vprintf() clone.  Just call vprintf if you've got it.
+ */
+extern void DWC_VPRINTF(char *format, va_list args);
+#define dwc_vprintf DWC_VPRINTF
+
+/**
+ * A vsnprintf() clone.  Just call vprintf if you've got it.
+ */
+extern int DWC_VSNPRINTF(char *str, int size, char *format, va_list args);
+#define dwc_vsnprintf DWC_VSNPRINTF
+
+/**
+ * printf() clone.  Just call printf if you've go it.
+ */
+extern void DWC_PRINTF(char *format, ...)
+/* This provides compiler level static checking of the parameters if you're
+ * using GCC. */
+#ifdef __GNUC__
+	__attribute__ ((format(printf, 1, 2)));
+#else
+  ;
+#endif
+#define dwc_printf DWC_PRINTF
+
+/**
+ * sprintf() clone.  Just call sprintf if you've got it.
+ */
+extern int DWC_SPRINTF(char *string, char *format, ...)
+#ifdef __GNUC__
+     __attribute__ ((format(printf, 2, 3)));
+#else
+     ;
+#endif
+#define dwc_sprintf DWC_SPRINTF
+
+/**
+ * snprintf() clone.  Just call snprintf if you've got it.
+ */
+extern int DWC_SNPRINTF(char *string, int size, char *format, ...)
+#ifdef __GNUC__
+     __attribute__ ((format(printf, 3, 4)));
+#else
+     ;
+#endif
+#define dwc_snprintf DWC_SNPRINTF
+
+/**
+ * Prints a WARNING message.  On systems that don't differentiate between
+ * warnings and regular log messages, just print it.  Indicates that something
+ * may be wrong with the driver.  Works like printf().
+ *
+ * Use the DWC_WARN macro to call this function.
+ */
+extern void __DWC_WARN(char *format, ...)
+#ifdef __GNUC__
+     __attribute__ ((format(printf, 1, 2)));
+#else
+     ;
+#endif
+
+/**
+ * Prints an error message.  On systems that don't differentiate between errors
+ * and regular log messages, just print it.  Indicates that something went wrong
+ * with the driver, but it can be recovered from.  Works like printf().
+ *
+ * Use the DWC_ERROR macro to call this function.
+ */
+extern void __DWC_ERROR(char *format, ...)
+#ifdef __GNUC__
+     __attribute__ ((format(printf, 1, 2)));
+#else
+     ;
+#endif
+
+/**
+ * Prints an exception error message and takes some user-defined action such as
+ * print out a backtrace or trigger a breakpoint.  Indicates that something went
+ * abnormally wrong with the driver such as programmer error, or other
+ * exceptional condition.  It should not be ignored so even on systems without
+ * printing capability, some action should be taken to notify the developer of
+ * it.  Works like printf().
+ */
+extern void DWC_EXCEPTION(char *format, ...)
+#ifdef __GNUC__
+     __attribute__ ((format(printf, 1, 2)));
+#else
+     ;
+#endif
+#define dwc_exception DWC_EXCEPTION
+
+#ifdef DEBUG
+/**
+ * Prints out a debug message.  Used for logging/trace messages.
+ *
+ * Use the DWC_DEBUG macro to call this function
+ */
+extern void __DWC_DEBUG(char *format, ...)
+#ifdef __GNUC__
+     __attribute__ ((format(printf, 1, 2)));
+#else
+     ;
+#endif
+#else
+#define __DWC_DEBUG printk
+#endif
+
+/**
+ * Prints out a Debug message.
+ */
+#define DWC_DEBUG(_format, _args...) __DWC_DEBUG("DEBUG:%s:%s: " _format "\n", __func__, dwc_irq(), ## _args)
+#define dwc_debug DWC_DEBUG
+/**
+ * Prints out an informative message.
+ */
+#define DWC_INFO(_format, _args...) DWC_PRINTF("INFO:%s: " _format "\n", dwc_irq(), ## _args)
+#define dwc_info DWC_INFO
+/**
+ * Prints out a warning message.
+ */
+#define DWC_WARN(_format, _args...) __DWC_WARN("WARN:%s:%s:%d: " _format "\n", dwc_irq(), __func__, __LINE__, ## _args)
+#define dwc_warn DWC_WARN
+/**
+ * Prints out an error message.
+ */
+#define DWC_ERROR(_format, _args...) __DWC_ERROR("ERROR:%s:%s:%d: " _format "\n", dwc_irq(), __func__, __LINE__, ## _args)
+#define dwc_error DWC_ERROR
+
+#define DWC_PROTO_ERROR(_format, _args...) __DWC_WARN("ERROR:%s:%s:%d: " _format "\n", dwc_irq(), __func__, __LINE__, ## _args)
+#define dwc_proto_error DWC_PROTO_ERROR
+
+#ifdef DEBUG
+/** Prints out a exception error message if the _expr expression fails.  Disabled
+ * if DEBUG is not enabled. */
+#define DWC_ASSERT(_expr, _format, _args...) if (!(_expr)) { DWC_EXCEPTION("%s:%s:%d: " _format "\n", dwc_irq(), __FILE__, __LINE__, ## _args); }
+#else
+#define DWC_ASSERT(_x...)
+#endif
+#define dwc_assert DWC_ASSERT
+
+/** @name Byter Ordering
+ * The following functions are for conversions between processor's byte ordering
+ * and specific ordering you want.
+ */
+
+/** Converts 32 bit data in CPU byte ordering to little endian. */
+extern uint32_t DWC_CPU_TO_LE32(void *p);
+#define dwc_cpu_to_le32 DWC_CPU_TO_LE32
+/** Converts 32 bit data in CPU byte orderint to big endian. */
+extern uint32_t DWC_CPU_TO_BE32(void *p);
+#define dwc_cpu_to_be32 DWC_CPU_TO_BE32
+
+/** Converts 32 bit little endian data to CPU byte ordering. */
+extern uint32_t DWC_LE32_TO_CPU(void *p);
+#define dwc_le32_to_cpu DWC_LE32_TO_CPU
+/** Converts 32 bit big endian data to CPU byte ordering. */
+extern uint32_t DWC_BE32_TO_CPU(void *p);
+#define dwc_be32_to_cpu DWC_BE32_TO_CPU
+
+/** Converts 16 bit data in CPU byte ordering to little endian. */
+extern uint16_t DWC_CPU_TO_LE16(void *p);
+#define dwc_cpu_to_le16 DWC_CPU_TO_LE16
+/** Converts 16 bit data in CPU byte orderint to big endian. */
+extern uint16_t DWC_CPU_TO_BE16(void *p);
+#define dwc_cpu_to_be16 DWC_CPU_TO_BE16
+
+/** Converts 16 bit little endian data to CPU byte ordering. */
+extern uint16_t DWC_LE16_TO_CPU(void *p);
+#define dwc_le16_to_cpu DWC_LE16_TO_CPU
+/** Converts 16 bit bi endian data to CPU byte ordering. */
+extern uint16_t DWC_BE16_TO_CPU(void *p);
+#define dwc_be16_to_cpu DWC_BE16_TO_CPU
+
+/** @name Register Read/Write
+ *
+ * The following five functions should be implemented to read/write registers of
+ * 32-bit and 64-bit sizes.  All modules use this to read/write register values.
+ * The reg value is a pointer to the register calculated from the void *base
+ * variable passed into the driver when it is started.  */
+
+/** Reads the content of a 32-bit register. */
+extern uint32_t DWC_READ_REG32(uint32_t volatile *reg);
+#define dwc_read_reg32 DWC_READ_REG32
+/** Reads the content of a 64-bit register. */
+extern uint64_t DWC_READ_REG64(uint64_t volatile *reg);
+#define dwc_read_reg64 DWC_READ_REG64
+/** Writes to a 32-bit register. */
+extern void DWC_WRITE_REG32(uint32_t volatile *reg, uint32_t value);
+#define dwc_write_reg32 DWC_WRITE_REG32
+/** Writes to a 64-bit register. */
+extern void DWC_WRITE_REG64(uint64_t volatile *reg, uint64_t value);
+#define dwc_write_reg64 DWC_WRITE_REG64
+/**  
+ * Modify bit values in a register.  Using the
+ * algorithm: (reg_contents & ~clear_mask) | set_mask.
+ */
+extern void DWC_MODIFY_REG32(uint32_t volatile *reg, uint32_t clear_mask, uint32_t set_mask);
+#define dwc_modify_reg32 DWC_MODIFY_REG32
+
+/** @cond */
+
+/** @name Some convenience MACROS used internally.  Define DEBUG_REGS to log the
+ * register writes. */
+
+#ifdef DEBUG_REGS
+
+#define dwc_define_read_write_reg_n(_reg,_container_type) \
+static inline uint32_t dwc_read_##_reg##_n(_container_type *container, int num) { \
+	return DWC_READ_REG32(&container->regs->_reg[num]); \
+} \
+static inline void dwc_write_##_reg##_n(_container_type *container, int num, uint32_t data) { \
+        DWC_DEBUG("WRITING %8s[%d]: %p: %08x", #_reg, num, &(((uint32_t*)container->regs->_reg)[num]), data); \
+	DWC_WRITE_REG32(&(((uint32_t*)container->regs->_reg)[num]), data); \
+}
+
+#define dwc_define_read_write_reg(_reg,_container_type) \
+static inline uint32_t dwc_read_##_reg(_container_type *container) { \
+	return DWC_READ_REG32(&container->regs->_reg); \
+} \
+static inline void dwc_write_##_reg(_container_type *container, uint32_t data) { \
+        DWC_DEBUG("WRITING %11s: %p: %08x", #_reg, &container->regs->_reg, data); \
+	DWC_WRITE_REG32(&container->regs->_reg, data); \
+}
+
+#else
+
+#define dwc_define_read_write_reg_n(_reg,_container_type) \
+static inline uint32_t dwc_read_##_reg##_n(_container_type *container, int num) { \
+	return DWC_READ_REG32(&container->regs->_reg[num]); \
+} \
+static inline void dwc_write_##_reg##_n(_container_type *container, int num, uint32_t data) { \
+	DWC_WRITE_REG32(&(((uint32_t*)container->regs->_reg)[num]), data); \
+}
+
+#define dwc_define_read_write_reg(_reg,_container_type) \
+static inline uint32_t dwc_read_##_reg(_container_type *container) { \
+	return DWC_READ_REG32(&container->regs->_reg); \
+} \
+static inline void dwc_write_##_reg(_container_type *container, uint32_t data) { \
+	DWC_WRITE_REG32(&container->regs->_reg, data); \
+}
+
+#endif
+
+/** @endcond */
+
+
+/** @name Crypto Functions
+ *
+ * These are the low-level cryptographic functions used by the driver. */
+
+/** Perform AES CBC */
+extern int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out);
+#define dwc_aes_cbc DWC_AES_CBC
+/** Fill the provided buffer with random bytes.  These should be cryptographic grade random numbers. */
+extern void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length);
+#define dwc_random_bytes DWC_RANDOM_BYTES
+/** Perform the SHA-256 hash function */
+extern int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out);
+#define dwc_sha256 DWC_SHA256
+/** Calculated the HMAC-SHA256 */
+extern int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t *out);
+#define dwc_hmac_sha256 DWC_HMAC_SHA256
+
+
+/** @name Memory Allocation
+ *
+ * These function provide access to memory allocation.  There are only 2 DMA
+ * functions and 3 Regular memory functions that need to be implemented.  None
+ * of the memory debugging routines need to be implemented.  The allocation
+ * routines all ZERO the contents of the memory.
+ *
+ * Defining DEBUG_MEMORY turns on memory debugging and statistic gathering.
+ * This checks for memory leaks, keeping track of alloc/free pairs.  It also
+ * keeps track of how much memory the driver is using at any given time. */
+
+#define DWC_PAGE_SIZE 4096
+#define DWC_PAGE_OFFSET(addr) (((uint32_t)addr) & 0xfff)
+#define DWC_PAGE_ALIGNED(addr) ((((uint32_t)addr) & 0xfff) == 0)
+
+#define DWC_INVALID_DMA_ADDR 0x0
+
+typedef uint32_t dwc_dma_t;
+
+/** @todo these functions will be added in the future */
+#if 0
+/**
+ * Creates a DMA pool from which you can allocate DMA buffers.  Buffers
+ * allocated from this pool will be guaranteed to meet the size, alignment, and
+ * boundary requirements specified.
+ *
+ * @param[in] size Specifies the size of the buffers that will be allocated from
+ * this pool.
+ * @param[in] align Specifies the byte alignment requirements of the buffers
+ * allocated from this pool.  Must be a power of 2.
+ * @param[in] boundary Specifies the N-byte boundary that buffers allocated from
+ * this pool must not cross.
+ *
+ * @returns A pointer to an internal opaque structure which is not to be
+ * accessed outside of these library functions.  Use this handle to specify
+ * which pools to allocate/free DMA buffers from and also to destroy the pool,
+ * when you are done with it.
+ */
+extern dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size, uint32_t align, uint32_t boundary);
+/**
+ * Destroy a DMA pool.  All buffers allocated from that pool must be freed first.
+ */
+extern void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool);
+/**
+ * Allocate a buffer from the specified DMA pool and zeros its contents.
+ */
+extern void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr);
+/**
+ * Free a previously allocated buffer from the DMA pool.
+ */
+extern void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr);
+#endif
+
+
+/** Allocates a DMA capable buffer and zeroes its contents. */
+extern void *__DWC_DMA_ALLOC(uint32_t size, dwc_dma_t *dma_addr);
+
+/** Allocates a DMA capable buffer and zeroes its contents in atomic contest */
+extern void *__DWC_DMA_ALLOC_ATOMIC(uint32_t size, dwc_dma_t *dma_addr);
+
+/** Frees a previosly allocated buffer. */
+extern void __DWC_DMA_FREE(uint32_t size, void *virt_addr, dwc_dma_t dma_addr);
+
+/** Allocates a block of memory and zeroes its contents. */
+extern void *__DWC_ALLOC(uint32_t size);
+
+/** Allocates a block of memory and zeroes its contents, in an atomic manner
+ * which can be used inside interrupt context.  The size should be sufficiently
+ * small, a few KB at most, such that failures are not likely to occur.  Can just call
+ * __DWC_ALLOC if it is atomic. */
+extern void *__DWC_ALLOC_ATOMIC(uint32_t size);
+
+/** Frees a previously allocated buffer. */
+extern void __DWC_FREE(void *addr);
+
+#ifndef DEBUG_MEMORY
+
+#define DWC_ALLOC(_size_) __DWC_ALLOC(_size_)
+#define DWC_ALLOC_ATOMIC(_size_) __DWC_ALLOC_ATOMIC(_size_)
+#define DWC_FREE(_addr_) __DWC_FREE(_addr_)
+#define DWC_DMA_ALLOC(_size_,_dma_) __DWC_DMA_ALLOC(_size_,_dma_)
+#define DWC_DMA_ALLOC_ATOMIC(_size_,_dma_) __DWC_DMA_ALLOC_ATOMIC(_size_,_dma_)
+#define DWC_DMA_FREE(_size_,_virt_,_dma_) __DWC_DMA_FREE(_size_,_virt_,_dma_)
+
+#else
+
+extern void *dwc_alloc_debug(uint32_t size, char const *func, int line);
+extern void *dwc_alloc_atomic_debug(uint32_t size, char const *func, int line);
+extern void dwc_free_debug(void *addr, char const *func, int line);
+extern void *dwc_dma_alloc_debug(uint32_t size, dwc_dma_t *dma_addr, char const *func, int line);
+extern void *dwc_dma_alloc_atomic_debug(uint32_t size, dwc_dma_t *dma_addr, char const *func, int line);
+extern void dwc_dma_free_debug(uint32_t size, void *virt_addr, dwc_dma_t dma_addr, char const *func, int line);
+
+extern void dwc_memory_debug_start(void);
+extern void dwc_memory_debug_stop(void);
+extern void dwc_memory_debug_report(void);
+
+#define DWC_ALLOC(_size_) (dwc_alloc_debug(_size_, __func__, __LINE__))
+#define DWC_ALLOC_ATOMIC(_size_) (dwc_alloc_atomic_debug(_size_, __func__, __LINE__))
+#define DWC_FREE(_addr_) (dwc_free_debug(_addr_, __func__, __LINE__))
+#define DWC_DMA_ALLOC(_size_,_dma_) dwc_dma_alloc_debug(_size_, _dma_, __func__, __LINE__)
+#define DWC_DMA_ALLOC_ATOMIC(_size_,_dma_) dwc_dma_alloc_atomic_debug(_size_, _dma_, __func__, __LINE__)
+#define DWC_DMA_FREE(_size_,_virt_,_dma_) dwc_dma_free_debug(_size_, _virt_, _dma_, __func__, __LINE__)
+
+#endif /* DEBUG_MEMORY */
+
+#define dwc_alloc DWC_ALLOC
+#define dwc_alloc_atomic DWC_ALLOC_ATOMIC
+#define dwc_free DWC_FREE
+#define dwc_dma_alloc DWC_DMA_ALLOC
+#define dwc_dma_alloc_atomic DWC_DMA_ALLOC_ATOMIC
+#define dwc_dma_free DWC_DMA_FREE
+
+
+/** @name Memory and String Processing */
+
+/** memset() clone */
+extern void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size);
+#define dwc_memset DWC_MEMSET
+/** memcpy() clone */
+extern void *DWC_MEMCPY(void *dest, void const *src, uint32_t size);
+#define dwc_memcpy DWC_MEMCPY
+/** memmove() clone */
+extern void *DWC_MEMMOVE(void *dest, void *src, uint32_t size);
+#define dwc_memmove DWC_MEMMOVE
+/** memcmp() clone */
+extern int DWC_MEMCMP(void *m1, void *m2, uint32_t size);
+#define dwc_memcmp DWC_MEMCMP
+/** strcmp() clone */
+extern int DWC_STRCMP(void *s1, void *s2);
+#define dwc_strcmp DWC_STRCMP
+/** strncmp() clone */
+extern int DWC_STRNCMP(void *s1, void *s2, uint32_t size);
+#define dwc_strncmp DWC_STRNCMP
+/** strlen() clone, for NULL terminated ASCII strings */
+extern int DWC_STRLEN(char const *str);
+#define dwc_strlen DWC_STRLEN
+/** strcpy() clone, for NULL terminated ASCII strings */
+extern char *DWC_STRCPY(char *to, const char *from);
+#define dwc_strcpy DWC_STRCPY
+
+/** strdup() clone.  If you wish to use memory allocation debugging, this
+ * implementation of strdup should use the DWC_* memory routines instead of
+ * calling a predefined strdup.  Otherwise the memory allocated by this routine
+ * will not be seen by the debugging routines. */
+extern char *DWC_STRDUP(char const *str);
+#define dwc_strdup DWC_STRDUP
+
+/** NOT an atoi() clone.  Read the description carefully.  Returns an integer
+ * converted from the string str in base 10 unless the string begins with a "0x"
+ * in which case it is base 16.  String must be a NULL terminated sequence of
+ * ASCII characters and may optionally begin with whitespace, a + or -, and a
+ * "0x" prefix if base 16.  The remaining characters must be valid digits for
+ * the number and end with a NULL character.  If any invalid characters are
+ * encountered or it returns with a negative error code and the results of the
+ * conversion are undefined.  On sucess it returns 0.  Overflow conditions are
+ * undefined.  An example implementation using atoi() can be referenced from the
+ * Linux implementation. */
+extern int DWC_ATOI(char *str, int32_t *value);
+#define dwc_atoi DWC_ATOI
+/** Same as above but for unsigned. */
+extern int DWC_ATOUI(char *str, uint32_t *value);
+#define dwc_atoui DWC_ATOUI
+/** This routine returns a UTF16LE unicode encoded string from a UTF8 string. */
+extern int DWC_UTF8_TO_UTF16LE(uint8_t const *utf8string, uint16_t *utf16string, unsigned len);
+#define dwc_utf8_to_utf16le DWC_UTF8_TO_UTF16LE
+
+/** @name Wait queues
+ *
+ * Wait queues provide a means of synchronizing between threads or processes.  A
+ * process can block on a waitq if some condition is not true, waiting for it to
+ * become true.  When the waitq is triggered all waiting process will get
+ * unblocked and the condition will be check again.  Waitqs should be triggered
+ * every time a condition can potentially change.*/
+struct dwc_waitq;
+typedef struct dwc_waitq dwc_waitq_t;
+
+/** The type of waitq condition callback function.  This is called every time
+ * condition is evaluated. */
+typedef int (*dwc_waitq_condition_t)(void *data);
+
+/** Allocate a waitq */
+extern dwc_waitq_t *DWC_WAITQ_ALLOC(void);
+#define dwc_waitq_alloc DWC_WAITQ_ALLOC
+/** Free a waitq */
+extern void DWC_WAITQ_FREE(dwc_waitq_t *wq);
+#define dwc_waitq_free DWC_WAITQ_FREE
+
+/** Check the condition and if it is false, block on the waitq.  When unblocked, check the
+ * condition again.  The function returns when the condition becomes true.  The return value
+ * is 0 on condition true, DWC_WAITQ_ABORTED on abort or killed, or DWC_WAITQ_UNKNOWN on error. */
+extern int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t condition, void *data);
+#define dwc_waitq_wait DWC_WAITQ_WAIT;
+/** Check the condition and if it is false, block on the waitq.  When unblocked,
+ * check the condition again.  The function returns when the condition become
+ * true or the timeout has passed.  The return value is 0 on condition true or
+ * DWC_TIMED_OUT on timeout, or DWC_WAITQ_ABORTED, or DWC_WAITQ_UNKNOWN on
+ * error. */
+extern int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t condition, void *data, int32_t msecs);
+#define dwc_waitq_wait_timeout DWC_WAITQ_WAIT_TIMEOUT
+/** Trigger a waitq, unblocking all processes.  This should be called whenever a condition
+ * has potentially changed. */
+extern void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq);
+#define dwc_waitq_trigger DWC_WAITQ_TRIGGER
+/** Unblock all processes waiting on the waitq with an ABORTED result. */
+extern void DWC_WAITQ_ABORT(dwc_waitq_t *wq);
+#define dwc_waitq_abort DWC_WAITQ_ABORT
+
+/** @name Threads
+ *
+ * A thread must be explicitly stopped.  It must check DWC_THREAD_SHOULD_STOP
+ * whenever it is woken up, and then return.  The DWC_THREAD_STOP function
+ * returns the value from the thread.
+ */
+
+struct dwc_thread;
+typedef struct dwc_thread dwc_thread_t;
+
+/** The thread function */
+typedef int (*dwc_thread_function_t)(void *data);
+
+/** Create a thread and start it running the thread_function.  Returns a handle
+ * to the thread */
+extern dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t thread_function, char *name, void *data);
+#define dwc_thread_run DWC_THREAD_RUN
+/** Stops a thread.  Return the value returned by the thread.  Or will return
+ * DWC_ABORT if the thread never started. */
+extern int DWC_THREAD_STOP(dwc_thread_t *thread);
+#define dwc_thread_stop DWC_THREAD_STOP
+/** Signifies to the thread that it must stop. */
+extern dwc_bool_t DWC_THREAD_SHOULD_STOP(void);
+#define dwc_thread_should_stop DWC_THREAD_SHOULD_STOP
+
+/** @name Work queues
+ *
+ * Workqs are used to queue a callback function to be called at some later time,
+ * in another thread. */
+struct dwc_workq;
+typedef struct dwc_workq dwc_workq_t;
+
+/** The type of the callback function to be called. */
+typedef void (*dwc_work_callback_t)(void *data);
+
+/** Allocate a workq */
+extern dwc_workq_t *DWC_WORKQ_ALLOC(char *name);
+#define dwc_workq_alloc DWC_WORKQ_ALLOC
+/** Free a workq.  All work must be completed before being freed. */
+extern void DWC_WORKQ_FREE(dwc_workq_t *workq);
+#define dwc_workq_free DWC_WORKQ_FREE
+/** Schedule a callback on the workq, passing in data.  The function will be
+ * scheduled at some later time. */
+extern void DWC_WORKQ_SCHEDULE(dwc_workq_t *workq, dwc_work_callback_t work_cb, void *data, char *format, ...)
+#ifdef __GNUC__
+	__attribute__ ((format(printf, 4, 5)));
+#else
+  ;
+#endif
+#define dwc_workq_schedule DWC_WORKQ_SCHEDULE
+
+/** Schedule a callback on the workq, that will be called until at least 
+ * given number miliseconds have passed. */
+extern void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *workq, dwc_work_callback_t work_cb, void *data, uint32_t time, char *format, ...)
+#ifdef __GNUC__
+	__attribute__ ((format(printf, 5, 6)));
+#else
+  ;
+#endif
+#define dwc_workq_schedule_delayed DWC_WORKQ_SCHEDULE_DELAYED
+
+/** The number of processes in the workq */
+extern int DWC_WORKQ_PENDING(dwc_workq_t *workq);
+#define dwc_workq_pending DWC_WORKQ_PENDING
+/** Blocks until all the work in the workq is complete or timed out.  Returns <
+ * 0 on timeout. */
+extern int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout);
+#define dwc_workq_wait_work_done DWC_WORKQ_WAIT_WORK_DONE
+
+
+/** @name Tasklets
+ *
+ */
+struct dwc_tasklet;
+typedef struct dwc_tasklet dwc_tasklet_t;
+
+typedef void (*dwc_tasklet_callback_t)(void *data);
+
+extern dwc_tasklet_t *DWC_TASK_ALLOC(dwc_tasklet_callback_t cb, void *data);
+#define dwc_task_alloc DWC_TASK_ALLOC
+extern void DWC_TASK_FREE(dwc_tasklet_t *t);
+#define dwc_task_free DWC_TASK_FREE
+extern void DWC_TASK_SCHEDULE(dwc_tasklet_t *task);
+#define dwc_task_schedule DWC_TASK_SCHEDULE
+
+
+/** @name Timer
+ *
+ * Callbacks must be small and atomic.
+ */
+struct dwc_timer;
+typedef struct dwc_timer dwc_timer_t;
+
+typedef void (*dwc_timer_callback_t)(void *data);
+
+extern dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data);
+#define dwc_timer_alloc DWC_TIMER_ALLOC
+extern void DWC_TIMER_FREE(dwc_timer_t *timer);
+#define dwc_timer_free DWC_TIMER_FREE
+
+/** Schedules the timer to run at time ms from now.  And will repeat at every
+ * repeat_interval msec therafter
+ *
+ * Modifies a timer that is still awaiting execution to a new expiration time.
+ * The mod_time is added to the old time.  */
+extern void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time);
+#define dwc_timer_schedule DWC_TIMER_SCHEDULE
+
+/** Disables the timer from execution. */
+extern void DWC_TIMER_CANCEL(dwc_timer_t *timer);
+#define dwc_timer_cancel DWC_TIMER_CANCEL
+
+
+
+/** @name Spinlocks
+ *
+ * These locks are used when the work between the lock/unlock is atomic and
+ * short.  Interrupts are also disabled during the lock/unlock and thus they are
+ * suitable to lock between interrupt/non-interrupt context.  They also lock
+ * between processes if you have multiple CPUs or Preemption.  If you don't have
+ * multiple CPUS or Preemption, then the you can simply implement the
+ * DWC_SPINLOCK and DWC_SPINUNLOCK to disable and enable interrupts.  Because
+ * the work between the lock/unlock is atomic, the process context will never
+ * change, and so you never have to lock between processes.  */
+
+struct dwc_spinlock;
+typedef struct dwc_spinlock dwc_spinlock_t;
+
+/** Returns an initialized lock variable.  This function should allocate and
+ * initialize the OS-specific data structure used for locking.  This data
+ * structure is to be used for the DWC_LOCK and DWC_UNLOCK functions and should
+ * be freed by the DWC_FREE_LOCK when it is no longer used. */
+extern dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void);
+#define dwc_spinlock_alloc DWC_SPINLOCK_ALLOC
+
+/** Frees an initialized lock variable. */
+extern void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock);
+#define dwc_spinlock_free DWC_SPINLOCK_FREE
+
+/** Disables interrupts and blocks until it acquires the lock.
+ *
+ * @param lock Pointer to the spinlock.
+ * @param flags Unsigned long for irq flags storage.
+ */
+extern void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, uint64_t *flags);
+#define dwc_spinlock_irqsave DWC_SPINLOCK_IRQSAVE
+
+/** Re-enables the interrupt and releases the lock.
+ *
+ * @param lock Pointer to the spinlock.
+ * @param flags Unsigned long for irq flags storage.  Must be the same as was
+ * passed into DWC_LOCK.
+ */
+extern void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, uint64_t flags);
+#define dwc_spinunlock_irqrestore DWC_SPINUNLOCK_IRQRESTORE
+
+/** Blocks until it acquires the lock.
+ *
+ * @param lock Pointer to the spinlock.
+ */
+extern void DWC_SPINLOCK(dwc_spinlock_t *lock);
+#define dwc_spinlock DWC_SPINLOCK
+
+/** Releases the lock.
+ *
+ * @param lock Pointer to the spinlock.
+ */
+extern void DWC_SPINUNLOCK(dwc_spinlock_t *lock);
+#define dwc_spinunlock DWC_SPINUNLOCK
+
+/** @name Mutexes
+ *
+ * Unlike spinlocks Mutexes lock only between processes and the work between the
+ * lock/unlock CAN block, therefore it CANNOT be called from interrupt context.
+ */
+
+struct dwc_mutex;
+typedef struct dwc_mutex dwc_mutex_t;
+
+
+/* For Linux Mutex Debugging make it inline because the debugging routines use
+ * the symbol to determine recursive locking.  This makes it falsely think
+ * recursive locking occurs. */
+#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES))
+#define DWC_MUTEX_ALLOC_LINUX_DEBUG(__mutexp) ({ \
+	__mutexp = (dwc_mutex_t *)DWC_ALLOC(sizeof(struct mutex)); \
+	mutex_init((struct mutex *)__mutexp); \
+})
+#endif
+extern dwc_mutex_t *DWC_MUTEX_ALLOC(void);
+#define dwc_mutex_alloc DWC_MUTEX_ALLOC
+
+/* For memory leak debugging when using Linux Mutex Debugging */
+#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES))
+#define DWC_MUTEX_FREE(__mutexp) do { \
+	mutex_destroy((struct mutex *)__mutexp); \
+	DWC_FREE(__mutexp); \
+} while(0)
+#else
+extern void DWC_MUTEX_FREE(dwc_mutex_t *mutex);
+#define dwc_mutex_free DWC_MUTEX_FREE
+#endif
+
+extern void DWC_MUTEX_LOCK(dwc_mutex_t *mutex);
+#define dwc_mutex_lock DWC_MUTEX_LOCK
+/** Non-blocking lock returns 1 on successful lock. */
+extern int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex);
+#define dwc_mutex_trylock DWC_MUTEX_TRYLOCK
+extern void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex);
+#define dwc_mutex_unlock DWC_MUTEX_UNLOCK
+
+
+
+
+/** @name Time */
+
+/** Microsecond delay.
+ *
+ * @param usecs  Microseconds to delay.
+ */
+extern void DWC_UDELAY(uint32_t usecs);
+#define dwc_udelay DWC_UDELAY
+
+/** Millisecond delay.
+ *
+ * @param msecs  Milliseconds to delay.
+ */
+extern void DWC_MDELAY(uint32_t msecs);
+#define dwc_mdelay DWC_MDELAY
+
+/** Non-busy waiting.
+ * Sleeps for specified number of milliseconds.
+ *
+ * @param msecs Milliseconds to sleep.
+ */
+extern void DWC_MSLEEP(uint32_t msecs);
+#define dwc_msleep DWC_MSLEEP
+
+extern uint32_t DWC_TIME(void);
+#define dwc_time DWC_TIME
+
+#endif // _DWC_OS_H_
+
+
+
+
+/** @mainpage DWC Portability and Common Library
+ *
+ * This is the documentation for the DWC Portability and Common Library.
+ *
+ * @section intro Introduction
+ *
+ * The DWC Portability library consists of wrapper calls and data structures to
+ * all low-level functions which are typically provided by the OS.  The WUDEV
+ * driver uses only these functions.  In order to port the WUDEV driver, only
+ * the functions in this library need to be re-implemented, with the same
+ * behavior as documented here.
+ *
+ * The Common library consists of higher level functions, which rely only on
+ * calling the functions from the DWC Portability library.  These common
+ * routines are shared across modules.  Some of the common libraries need to be
+ * used directly by the driver programmer when porting WUDEV.  Such as the
+ * parameter and notification libraries.
+ *
+ * @section low Portability Library OS Wrapper Functions
+ *
+ * Any function starting with DWC and in all CAPS is a low-level OS-wrapper that
+ * needs to be implemented when porting, for example DWC_MUTEX_ALLOC().  All of
+ * these functions are included in the dwc_os.h file.
+ *
+ * There are many functions here covering a wide array of OS services.  Please
+ * see dwc_os.h for details, and implementation notes for each function.
+ *
+ * @section common Common Library Functions
+ *
+ * Any function starting with dwc and in all lowercase is a common library
+ * routine.  These functions have a portable implementation and do not need to
+ * be reimplemented when porting.  The common routines can be used by any
+ * driver, and some must be used by the end user to control the drivers.  For
+ * example, you must use the Parameter common library in order to set the
+ * parameters in the WUDEV module.
+ *
+ * The common libraries consist of the following:
+ *
+ * - Connection Contexts - Used internally and can be used by end-user.  See dwc_cc.h
+ * - Parameters - Used internally and can be used by end-user.  See dwc_params.h
+ * - Notifications - Used internally and can be used by end-user.  See dwc_notifier.h
+ * - Lists - Used internally and can be used by end-user.  See dwc_list.h
+ * - Memory Debugging - Used internally and can be used by end-user.  See dwc_os.h
+ * - Modpow - Used internally only.  See dwc_modpow.h
+ * - DH - Used internally only.  See dwc_dh.h
+ * - Crypto - Used internally only.  See dwc_crypto.h
+ *
+ *
+ * @section prereq Prerequistes For dwc_os.h
+ * @subsection types Data Types
+ *
+ * The dwc_os.h file assumes that several low-level data types are pre defined for the
+ * compilation environment.  These data types are:
+ *
+ * - uint8_t - unsigned 8-bit data type
+ * - int8_t - signed 8-bit data type
+ * - uint16_t - unsigned 16-bit data type
+ * - int16_t - signed 16-bit data type
+ * - uint32_t - unsigned 32-bit data type
+ * - int32_t - signed 32-bit data type
+ * - uint64_t - unsigned 64-bit data type
+ * - int64_t - signed 64-bit data type
+ *
+ * Ensure that these are defined before using dwc_os.h.  The easiest way to do
+ * that is to modify the top of the file to include the appropriate header.
+ * This is already done for the Linux environment.  If the DWC_LINUX macro is
+ * defined, the correct header will be added.  A standard header <stdint.h> is
+ * also used for environments where standard C headers are available.
+ *
+ * @subsection stdarg Variable Arguments
+ *
+ * Variable arguments are provided by a standard C header <stdarg.h>.  it is
+ * available in Both the Linux and ANSI C enviornment.  An equivalent must be
+ * provided in your enviornment in order to use dwc_os.h with the debug and
+ * tracing message functionality.
+ *
+ * @subsection thread Threading
+ *
+ * WUDEV Core must be run on an operating system that provides for multiple
+ * threads/processes.  Threading can be implemented in many ways, even in
+ * embedded systems without an operating system.  At the bare minimum, the
+ * system should be able to start any number of processes at any time to handle
+ * special work.  It need not be a pre-emptive system.  Process context can
+ * change upon a call to a blocking function.  The hardware interrupt context
+ * that calls the module's ISR() function must be differentiable from process
+ * context, even if your processes are impemented via a hardware interrupt.
+ * Further locking mechanism between process must exist (or be implemented), and
+ * process context must have a way to disable interrupts for a period of time to
+ * lock them out.  If all of this exists, the functions in dwc_os.h related to
+ * threading should be able to be implemented with the defined behavior.
+ *
+ */
diff --git a/drivers/usb/host/dwc_common_port/usb.h b/drivers/usb/host/dwc_common_port/usb.h
new file mode 100644
index 000000000000..2ee425239247
--- /dev/null
+++ b/drivers/usb/host/dwc_common_port/usb.h
@@ -0,0 +1,850 @@
+/*
+ * Copyright (c) 1998 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Lennart Augustsson (lennart@augustsson.net) at
+ * Carlstedt Research & Technology.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *        This product includes software developed by the NetBSD
+ *        Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Modified by Synopsys, Inc, 12/12/2007 */
+
+
+#ifndef _USB_H_
+#define _USB_H_
+
+#include "dwc_os.h"
+
+/*
+ * The USB records contain some unaligned little-endian word
+ * components.  The U[SG]ETW macros take care of both the alignment
+ * and endian problem and should always be used to access non-byte
+ * values.
+ */
+typedef u_int8_t uByte;
+typedef u_int8_t uWord[2];
+typedef u_int8_t uDWord[4];
+
+#define USETW2(w,h,l) ((w)[0] = (u_int8_t)(l), (w)[1] = (u_int8_t)(h))
+
+#if 1
+#define UGETW(w) ((w)[0] | ((w)[1] << 8))
+#define USETW(w,v) ((w)[0] = (u_int8_t)(v), (w)[1] = (u_int8_t)((v) >> 8))
+#define UGETDW(w) ((w)[0] | ((w)[1] << 8) | ((w)[2] << 16) | ((w)[3] << 24))
+#define USETDW(w,v) ((w)[0] = (u_int8_t)(v), \
+		     (w)[1] = (u_int8_t)((v) >> 8), \
+		     (w)[2] = (u_int8_t)((v) >> 16), \
+		     (w)[3] = (u_int8_t)((v) >> 24))
+#else
+/*
+ * On little-endian machines that can handle unanliged accesses
+ * (e.g. i386) these macros can be replaced by the following.
+ */
+#define UGETW(w) (*(u_int16_t *)(w))
+#define USETW(w,v) (*(u_int16_t *)(w) = (v))
+#define UGETDW(w) (*(u_int32_t *)(w))
+#define USETDW(w,v) (*(u_int32_t *)(w) = (v))
+#endif
+
+#define UPACKED __attribute__((__packed__))
+
+typedef struct {
+	uByte		bmRequestType;
+	uByte		bRequest;
+	uWord		wValue;
+	uWord		wIndex;
+	uWord		wLength;
+} UPACKED usb_device_request_t;
+
+#define UT_GET_DIR(a) ((a) & 0x80)
+#define UT_WRITE		0x00
+#define UT_READ			0x80
+
+#define UT_GET_TYPE(a) ((a) & 0x60)
+#define UT_STANDARD		0x00
+#define UT_CLASS		0x20
+#define UT_VENDOR		0x40
+
+#define UT_GET_RECIPIENT(a) ((a) & 0x1f)
+#define UT_DEVICE		0x00
+#define UT_INTERFACE		0x01
+#define UT_ENDPOINT		0x02
+#define UT_OTHER		0x03
+
+#define UT_READ_DEVICE		(UT_READ  | UT_STANDARD | UT_DEVICE)
+#define UT_READ_INTERFACE	(UT_READ  | UT_STANDARD | UT_INTERFACE)
+#define UT_READ_ENDPOINT	(UT_READ  | UT_STANDARD | UT_ENDPOINT)
+#define UT_WRITE_DEVICE		(UT_WRITE | UT_STANDARD | UT_DEVICE)
+#define UT_WRITE_INTERFACE	(UT_WRITE | UT_STANDARD | UT_INTERFACE)
+#define UT_WRITE_ENDPOINT	(UT_WRITE | UT_STANDARD | UT_ENDPOINT)
+#define UT_READ_CLASS_DEVICE	(UT_READ  | UT_CLASS | UT_DEVICE)
+#define UT_READ_CLASS_INTERFACE	(UT_READ  | UT_CLASS | UT_INTERFACE)
+#define UT_READ_CLASS_OTHER	(UT_READ  | UT_CLASS | UT_OTHER)
+#define UT_READ_CLASS_ENDPOINT	(UT_READ  | UT_CLASS | UT_ENDPOINT)
+#define UT_WRITE_CLASS_DEVICE	(UT_WRITE | UT_CLASS | UT_DEVICE)
+#define UT_WRITE_CLASS_INTERFACE (UT_WRITE | UT_CLASS | UT_INTERFACE)
+#define UT_WRITE_CLASS_OTHER	(UT_WRITE | UT_CLASS | UT_OTHER)
+#define UT_WRITE_CLASS_ENDPOINT	(UT_WRITE | UT_CLASS | UT_ENDPOINT)
+#define UT_READ_VENDOR_DEVICE	(UT_READ  | UT_VENDOR | UT_DEVICE)
+#define UT_READ_VENDOR_INTERFACE (UT_READ  | UT_VENDOR | UT_INTERFACE)
+#define UT_READ_VENDOR_OTHER	(UT_READ  | UT_VENDOR | UT_OTHER)
+#define UT_READ_VENDOR_ENDPOINT	(UT_READ  | UT_VENDOR | UT_ENDPOINT)
+#define UT_WRITE_VENDOR_DEVICE	(UT_WRITE | UT_VENDOR | UT_DEVICE)
+#define UT_WRITE_VENDOR_INTERFACE (UT_WRITE | UT_VENDOR | UT_INTERFACE)
+#define UT_WRITE_VENDOR_OTHER	(UT_WRITE | UT_VENDOR | UT_OTHER)
+#define UT_WRITE_VENDOR_ENDPOINT (UT_WRITE | UT_VENDOR | UT_ENDPOINT)
+
+/* Requests */
+#define UR_GET_STATUS		0x00
+#define  USTAT_STANDARD_STATUS  0x00
+#define  WUSTAT_WUSB_FEATURE    0x01
+#define  WUSTAT_CHANNEL_INFO    0x02
+#define  WUSTAT_RECEIVED_DATA   0x03
+#define  WUSTAT_MAS_AVAILABILITY 0x04
+#define  WUSTAT_CURRENT_TRANSMIT_POWER 0x05
+#define UR_CLEAR_FEATURE	0x01
+#define UR_SET_FEATURE		0x03
+#define UR_SET_AND_TEST_FEATURE 0x0c
+#define UR_SET_ADDRESS		0x05
+#define UR_GET_DESCRIPTOR	0x06
+#define  UDESC_DEVICE		0x01
+#define  UDESC_CONFIG		0x02
+#define  UDESC_STRING		0x03
+#define  UDESC_INTERFACE	0x04
+#define  UDESC_ENDPOINT		0x05
+#define  UDESC_DEVICE_QUALIFIER	0x06
+#define  UDESC_OTHER_SPEED_CONFIGURATION 0x07
+#define  UDESC_INTERFACE_POWER	0x08
+#define  UDESC_OTG		0x09
+#define  WUDESC_SECURITY	0x0c
+#define  WUDESC_KEY		0x0d
+#define   WUD_GET_KEY_INDEX(_wValue_) ((_wValue_) & 0xf)
+#define   WUD_GET_KEY_TYPE(_wValue_) (((_wValue_) & 0x30) >> 4)
+#define    WUD_KEY_TYPE_ASSOC    0x01
+#define    WUD_KEY_TYPE_GTK      0x02
+#define   WUD_GET_KEY_ORIGIN(_wValue_) (((_wValue_) & 0x40) >> 6)
+#define    WUD_KEY_ORIGIN_HOST   0x00
+#define    WUD_KEY_ORIGIN_DEVICE 0x01
+#define  WUDESC_ENCRYPTION_TYPE	0x0e
+#define  WUDESC_BOS		0x0f
+#define  WUDESC_DEVICE_CAPABILITY 0x10
+#define  WUDESC_WIRELESS_ENDPOINT_COMPANION 0x11
+#define  UDESC_CS_DEVICE	0x21	/* class specific */
+#define  UDESC_CS_CONFIG	0x22
+#define  UDESC_CS_STRING	0x23
+#define  UDESC_CS_INTERFACE	0x24
+#define  UDESC_CS_ENDPOINT	0x25
+#define  UDESC_HUB		0x29
+#define UR_SET_DESCRIPTOR	0x07
+#define UR_GET_CONFIG		0x08
+#define UR_SET_CONFIG		0x09
+#define UR_GET_INTERFACE	0x0a
+#define UR_SET_INTERFACE	0x0b
+#define UR_SYNCH_FRAME		0x0c
+#define WUR_SET_ENCRYPTION      0x0d
+#define WUR_GET_ENCRYPTION	0x0e
+#define WUR_SET_HANDSHAKE	0x0f
+#define WUR_GET_HANDSHAKE	0x10
+#define WUR_SET_CONNECTION	0x11
+#define WUR_SET_SECURITY_DATA	0x12
+#define WUR_GET_SECURITY_DATA	0x13
+#define WUR_SET_WUSB_DATA	0x14
+#define  WUDATA_DRPIE_INFO  0x01
+#define  WUDATA_TRANSMIT_DATA 0x02
+#define  WUDATA_TRANSMIT_PARAMS 0x03
+#define  WUDATA_RECEIVE_PARAMS 0x04
+#define  WUDATA_TRANSMIT_POWER 0x05
+#define WUR_LOOPBACK_DATA_WRITE	0x15
+#define WUR_LOOPBACK_DATA_READ	0x16
+#define WUR_SET_INTERFACE_DS	0x17
+
+/* Feature numbers */
+#define UF_ENDPOINT_HALT	0
+#define UF_DEVICE_REMOTE_WAKEUP	1
+#define UF_TEST_MODE		2
+#define UF_DEVICE_B_HNP_ENABLE	3
+#define UF_DEVICE_A_HNP_SUPPORT	4
+#define UF_DEVICE_A_ALT_HNP_SUPPORT 5
+#define WUF_WUSB                3
+#define  WUF_TX_DRPIE           0x0
+#define  WUF_DEV_XMIT_PACKET    0x1
+#define  WUF_COUNT_PACKETS      0x2
+#define  WUF_CAPTURE_PACKETS    0x3
+
+/* Class requests from the USB 2.0 hub spec, table 11-15 */
+#define UCR_CLEAR_HUB_FEATURE		(0x2000 | UR_CLEAR_FEATURE)
+#define UCR_CLEAR_PORT_FEATURE		(0x2300 | UR_CLEAR_FEATURE)
+#define UCR_GET_HUB_DESCRIPTOR		(0xa000 | UR_GET_DESCRIPTOR)
+#define UCR_GET_HUB_STATUS		(0xa000 | UR_GET_STATUS)
+#define UCR_GET_PORT_STATUS		(0xa300 | UR_GET_STATUS)
+#define UCR_SET_HUB_FEATURE		(0x2000 | UR_SET_FEATURE)
+#define UCR_SET_PORT_FEATURE		(0x2300 | UR_SET_FEATURE)
+#define UCR_SET_AND_TEST_PORT_FEATURE	(0xa300 | UR_SET_AND_TEST_FEATURE)
+
+typedef struct {
+	uByte		bLength;
+	uByte		bDescriptorType;
+	uByte		bDescriptorSubtype;
+} UPACKED usb_descriptor_t;
+
+typedef struct {
+	uByte		bLength;
+	uByte		bDescriptorType;
+	uWord		bcdUSB;
+#define UD_USB_2_0		0x0200
+#define UD_IS_USB2(d) (UGETW((d)->bcdUSB) >= UD_USB_2_0)
+	uByte		bDeviceClass;
+	uByte		bDeviceSubClass;
+	uByte		bDeviceProtocol;
+	uByte		bMaxPacketSize;
+	/* The fields below are not part of the initial descriptor. */
+	uWord		idVendor;
+	uWord		idProduct;
+	uWord		bcdDevice;
+	uByte		iManufacturer;
+	uByte		iProduct;
+	uByte		iSerialNumber;
+	uByte		bNumConfigurations;
+} UPACKED usb_device_descriptor_t;
+#define USB_DEVICE_DESCRIPTOR_SIZE 18
+
+typedef struct {
+	uByte		bLength;
+	uByte		bDescriptorType;
+	uWord		wTotalLength;
+	uByte		bNumInterface;
+	uByte		bConfigurationValue;
+	uByte		iConfiguration;
+	uByte		bmAttributes;
+#define UC_BUS_POWERED		0x80
+#define UC_SELF_POWERED		0x40
+#define UC_REMOTE_WAKEUP	0x20
+	uByte		bMaxPower; /* max current in 2 mA units */
+#define UC_POWER_FACTOR 2
+} UPACKED usb_config_descriptor_t;
+#define USB_CONFIG_DESCRIPTOR_SIZE 9
+
+typedef struct {
+	uByte		bLength;
+	uByte		bDescriptorType;
+	uByte		bInterfaceNumber;
+	uByte		bAlternateSetting;
+	uByte		bNumEndpoints;
+	uByte		bInterfaceClass;
+	uByte		bInterfaceSubClass;
+	uByte		bInterfaceProtocol;
+	uByte		iInterface;
+} UPACKED usb_interface_descriptor_t;
+#define USB_INTERFACE_DESCRIPTOR_SIZE 9
+
+typedef struct {
+	uByte		bLength;
+	uByte		bDescriptorType;
+	uByte		bEndpointAddress;
+#define UE_GET_DIR(a)	((a) & 0x80)
+#define UE_SET_DIR(a,d)	((a) | (((d)&1) << 7))
+#define UE_DIR_IN	0x80
+#define UE_DIR_OUT	0x00
+#define UE_ADDR		0x0f
+#define UE_GET_ADDR(a)	((a) & UE_ADDR)
+	uByte		bmAttributes;
+#define UE_XFERTYPE	0x03
+#define  UE_CONTROL	0x00
+#define  UE_ISOCHRONOUS	0x01
+#define  UE_BULK	0x02
+#define  UE_INTERRUPT	0x03
+#define UE_GET_XFERTYPE(a)	((a) & UE_XFERTYPE)
+#define UE_ISO_TYPE	0x0c
+#define  UE_ISO_ASYNC	0x04
+#define  UE_ISO_ADAPT	0x08
+#define  UE_ISO_SYNC	0x0c
+#define UE_GET_ISO_TYPE(a)	((a) & UE_ISO_TYPE)
+	uWord		wMaxPacketSize;
+	uByte		bInterval;
+} UPACKED usb_endpoint_descriptor_t;
+#define USB_ENDPOINT_DESCRIPTOR_SIZE 7
+
+typedef struct {
+	uByte		bLength;
+	uByte		bDescriptorType;
+	uWord		bString[127];
+} UPACKED usb_string_descriptor_t;
+#define USB_MAX_STRING_LEN 128
+#define USB_LANGUAGE_TABLE 0	/* # of the string language id table */
+
+/* Hub specific request */
+#define UR_GET_BUS_STATE	0x02
+#define UR_CLEAR_TT_BUFFER	0x08
+#define UR_RESET_TT		0x09
+#define UR_GET_TT_STATE		0x0a
+#define UR_STOP_TT		0x0b
+
+/* Hub features */
+#define UHF_C_HUB_LOCAL_POWER	0
+#define UHF_C_HUB_OVER_CURRENT	1
+#define UHF_PORT_CONNECTION	0
+#define UHF_PORT_ENABLE		1
+#define UHF_PORT_SUSPEND	2
+#define UHF_PORT_OVER_CURRENT	3
+#define UHF_PORT_RESET		4
+#define UHF_PORT_L1		5
+#define UHF_PORT_POWER		8
+#define UHF_PORT_LOW_SPEED	9
+#define UHF_PORT_HIGH_SPEED	10
+#define UHF_C_PORT_CONNECTION	16
+#define UHF_C_PORT_ENABLE	17
+#define UHF_C_PORT_SUSPEND	18
+#define UHF_C_PORT_OVER_CURRENT	19
+#define UHF_C_PORT_RESET	20
+#define UHF_C_PORT_L1		23
+#define UHF_PORT_TEST		21
+#define UHF_PORT_INDICATOR	22
+
+typedef struct {
+	uByte		bDescLength;
+	uByte		bDescriptorType;
+	uByte		bNbrPorts;
+	uWord		wHubCharacteristics;
+#define UHD_PWR			0x0003
+#define  UHD_PWR_GANGED		0x0000
+#define  UHD_PWR_INDIVIDUAL	0x0001
+#define  UHD_PWR_NO_SWITCH	0x0002
+#define UHD_COMPOUND		0x0004
+#define UHD_OC			0x0018
+#define  UHD_OC_GLOBAL		0x0000
+#define  UHD_OC_INDIVIDUAL	0x0008
+#define  UHD_OC_NONE		0x0010
+#define UHD_TT_THINK		0x0060
+#define  UHD_TT_THINK_8		0x0000
+#define  UHD_TT_THINK_16	0x0020
+#define  UHD_TT_THINK_24	0x0040
+#define  UHD_TT_THINK_32	0x0060
+#define UHD_PORT_IND		0x0080
+	uByte		bPwrOn2PwrGood;	/* delay in 2 ms units */
+#define UHD_PWRON_FACTOR 2
+	uByte		bHubContrCurrent;
+	uByte		DeviceRemovable[32]; /* max 255 ports */
+#define UHD_NOT_REMOV(desc, i) \
+    (((desc)->DeviceRemovable[(i)/8] >> ((i) % 8)) & 1)
+	/* deprecated */ uByte		PortPowerCtrlMask[1];
+} UPACKED usb_hub_descriptor_t;
+#define USB_HUB_DESCRIPTOR_SIZE 9 /* includes deprecated PortPowerCtrlMask */
+
+typedef struct {
+	uByte		bLength;
+	uByte		bDescriptorType;
+	uWord		bcdUSB;
+	uByte		bDeviceClass;
+	uByte		bDeviceSubClass;
+	uByte		bDeviceProtocol;
+	uByte		bMaxPacketSize0;
+	uByte		bNumConfigurations;
+	uByte		bReserved;
+} UPACKED usb_device_qualifier_t;
+#define USB_DEVICE_QUALIFIER_SIZE 10
+
+typedef struct {
+	uByte		bLength;
+	uByte		bDescriptorType;
+	uByte		bmAttributes;
+#define UOTG_SRP	0x01
+#define UOTG_HNP	0x02
+} UPACKED usb_otg_descriptor_t;
+
+/* OTG feature selectors */
+#define UOTG_B_HNP_ENABLE	3
+#define UOTG_A_HNP_SUPPORT	4
+#define UOTG_A_ALT_HNP_SUPPORT	5
+
+typedef struct {
+	uWord		wStatus;
+/* Device status flags */
+#define UDS_SELF_POWERED		0x0001
+#define UDS_REMOTE_WAKEUP		0x0002
+/* Endpoint status flags */
+#define UES_HALT			0x0001
+} UPACKED usb_status_t;
+
+typedef struct {
+	uWord		wHubStatus;
+#define UHS_LOCAL_POWER			0x0001
+#define UHS_OVER_CURRENT		0x0002
+	uWord		wHubChange;
+} UPACKED usb_hub_status_t;
+
+typedef struct {
+	uWord		wPortStatus;
+#define UPS_CURRENT_CONNECT_STATUS	0x0001
+#define UPS_PORT_ENABLED		0x0002
+#define UPS_SUSPEND			0x0004
+#define UPS_OVERCURRENT_INDICATOR	0x0008
+#define UPS_RESET			0x0010
+#define UPS_PORT_POWER			0x0100
+#define UPS_LOW_SPEED			0x0200
+#define UPS_HIGH_SPEED			0x0400
+#define UPS_PORT_TEST			0x0800
+#define UPS_PORT_INDICATOR		0x1000
+	uWord		wPortChange;
+#define UPS_C_CONNECT_STATUS		0x0001
+#define UPS_C_PORT_ENABLED		0x0002
+#define UPS_C_SUSPEND			0x0004
+#define UPS_C_OVERCURRENT_INDICATOR	0x0008
+#define UPS_C_PORT_RESET		0x0010
+} UPACKED usb_port_status_t;
+
+/* Device class codes */
+#define UDCLASS_IN_INTERFACE	0x00
+#define UDCLASS_COMM		0x02
+#define UDCLASS_HUB		0x09
+#define  UDSUBCLASS_HUB		0x00
+#define  UDPROTO_FSHUB		0x00
+#define  UDPROTO_HSHUBSTT	0x01
+#define  UDPROTO_HSHUBMTT	0x02
+#define UDCLASS_DIAGNOSTIC	0xdc
+#define UDCLASS_WIRELESS	0xe0
+#define  UDSUBCLASS_RF		0x01
+#define   UDPROTO_BLUETOOTH	0x01
+#define UDCLASS_VENDOR		0xff
+
+/* Interface class codes */
+#define UICLASS_UNSPEC		0x00
+
+#define UICLASS_AUDIO		0x01
+#define  UISUBCLASS_AUDIOCONTROL	1
+#define  UISUBCLASS_AUDIOSTREAM		2
+#define  UISUBCLASS_MIDISTREAM		3
+
+#define UICLASS_CDC		0x02 /* communication */
+#define	 UISUBCLASS_DIRECT_LINE_CONTROL_MODEL	1
+#define  UISUBCLASS_ABSTRACT_CONTROL_MODEL	2
+#define	 UISUBCLASS_TELEPHONE_CONTROL_MODEL	3
+#define	 UISUBCLASS_MULTICHANNEL_CONTROL_MODEL	4
+#define	 UISUBCLASS_CAPI_CONTROLMODEL		5
+#define	 UISUBCLASS_ETHERNET_NETWORKING_CONTROL_MODEL 6
+#define	 UISUBCLASS_ATM_NETWORKING_CONTROL_MODEL 7
+#define   UIPROTO_CDC_AT			1
+
+#define UICLASS_HID		0x03
+#define  UISUBCLASS_BOOT	1
+#define  UIPROTO_BOOT_KEYBOARD	1
+
+#define UICLASS_PHYSICAL	0x05
+
+#define UICLASS_IMAGE		0x06
+
+#define UICLASS_PRINTER		0x07
+#define  UISUBCLASS_PRINTER	1
+#define  UIPROTO_PRINTER_UNI	1
+#define  UIPROTO_PRINTER_BI	2
+#define  UIPROTO_PRINTER_1284	3
+
+#define UICLASS_MASS		0x08
+#define  UISUBCLASS_RBC		1
+#define  UISUBCLASS_SFF8020I	2
+#define  UISUBCLASS_QIC157	3
+#define  UISUBCLASS_UFI		4
+#define  UISUBCLASS_SFF8070I	5
+#define  UISUBCLASS_SCSI	6
+#define  UIPROTO_MASS_CBI_I	0
+#define  UIPROTO_MASS_CBI	1
+#define  UIPROTO_MASS_BBB_OLD	2	/* Not in the spec anymore */
+#define  UIPROTO_MASS_BBB	80	/* 'P' for the Iomega Zip drive */
+
+#define UICLASS_HUB		0x09
+#define  UISUBCLASS_HUB		0
+#define  UIPROTO_FSHUB		0
+#define  UIPROTO_HSHUBSTT	0 /* Yes, same as previous */
+#define  UIPROTO_HSHUBMTT	1
+
+#define UICLASS_CDC_DATA	0x0a
+#define  UISUBCLASS_DATA		0
+#define   UIPROTO_DATA_ISDNBRI		0x30    /* Physical iface */
+#define   UIPROTO_DATA_HDLC		0x31    /* HDLC */
+#define   UIPROTO_DATA_TRANSPARENT	0x32    /* Transparent */
+#define   UIPROTO_DATA_Q921M		0x50    /* Management for Q921 */
+#define   UIPROTO_DATA_Q921		0x51    /* Data for Q921 */
+#define   UIPROTO_DATA_Q921TM		0x52    /* TEI multiplexer for Q921 */
+#define   UIPROTO_DATA_V42BIS		0x90    /* Data compression */
+#define   UIPROTO_DATA_Q931		0x91    /* Euro-ISDN */
+#define   UIPROTO_DATA_V120		0x92    /* V.24 rate adaption */
+#define   UIPROTO_DATA_CAPI		0x93    /* CAPI 2.0 commands */
+#define   UIPROTO_DATA_HOST_BASED	0xfd    /* Host based driver */
+#define   UIPROTO_DATA_PUF		0xfe    /* see Prot. Unit Func. Desc.*/
+#define   UIPROTO_DATA_VENDOR		0xff    /* Vendor specific */
+
+#define UICLASS_SMARTCARD	0x0b
+
+/*#define UICLASS_FIRM_UPD	0x0c*/
+
+#define UICLASS_SECURITY	0x0d
+
+#define UICLASS_DIAGNOSTIC	0xdc
+
+#define UICLASS_WIRELESS	0xe0
+#define  UISUBCLASS_RF			0x01
+#define   UIPROTO_BLUETOOTH		0x01
+
+#define UICLASS_APPL_SPEC	0xfe
+#define  UISUBCLASS_FIRMWARE_DOWNLOAD	1
+#define  UISUBCLASS_IRDA		2
+#define  UIPROTO_IRDA			0
+
+#define UICLASS_VENDOR		0xff
+
+
+#define USB_HUB_MAX_DEPTH 5
+
+/*
+ * Minimum time a device needs to be powered down to go through
+ * a power cycle.  XXX Are these time in the spec?
+ */
+#define USB_POWER_DOWN_TIME	200 /* ms */
+#define USB_PORT_POWER_DOWN_TIME	100 /* ms */
+
+#if 0
+/* These are the values from the spec. */
+#define USB_PORT_RESET_DELAY	10  /* ms */
+#define USB_PORT_ROOT_RESET_DELAY 50  /* ms */
+#define USB_PORT_RESET_RECOVERY	10  /* ms */
+#define USB_PORT_POWERUP_DELAY	100 /* ms */
+#define USB_SET_ADDRESS_SETTLE	2   /* ms */
+#define USB_RESUME_DELAY	(20*5)  /* ms */
+#define USB_RESUME_WAIT		10  /* ms */
+#define USB_RESUME_RECOVERY	10  /* ms */
+#define USB_EXTRA_POWER_UP_TIME	0   /* ms */
+#else
+/* Allow for marginal (i.e. non-conforming) devices. */
+#define USB_PORT_RESET_DELAY	50  /* ms */
+#define USB_PORT_ROOT_RESET_DELAY 250  /* ms */
+#define USB_PORT_RESET_RECOVERY	250  /* ms */
+#define USB_PORT_POWERUP_DELAY	300 /* ms */
+#define USB_SET_ADDRESS_SETTLE	10  /* ms */
+#define USB_RESUME_DELAY	(50*5)  /* ms */
+#define USB_RESUME_WAIT		50  /* ms */
+#define USB_RESUME_RECOVERY	50  /* ms */
+#define USB_EXTRA_POWER_UP_TIME	20  /* ms */
+#endif
+
+#define USB_MIN_POWER		100 /* mA */
+#define USB_MAX_POWER		500 /* mA */
+
+#define USB_BUS_RESET_DELAY	100 /* ms XXX?*/
+
+
+#define USB_UNCONFIG_NO 0
+#define USB_UNCONFIG_INDEX (-1)
+
+/*** ioctl() related stuff ***/
+
+struct usb_ctl_request {
+	int	ucr_addr;
+	usb_device_request_t ucr_request;
+	void	*ucr_data;
+	int	ucr_flags;
+#define USBD_SHORT_XFER_OK	0x04	/* allow short reads */
+	int	ucr_actlen;		/* actual length transferred */
+};
+
+struct usb_alt_interface {
+	int	uai_config_index;
+	int	uai_interface_index;
+	int	uai_alt_no;
+};
+
+#define USB_CURRENT_CONFIG_INDEX (-1)
+#define USB_CURRENT_ALT_INDEX (-1)
+
+struct usb_config_desc {
+	int	ucd_config_index;
+	usb_config_descriptor_t ucd_desc;
+};
+
+struct usb_interface_desc {
+	int	uid_config_index;
+	int	uid_interface_index;
+	int	uid_alt_index;
+	usb_interface_descriptor_t uid_desc;
+};
+
+struct usb_endpoint_desc {
+	int	ued_config_index;
+	int	ued_interface_index;
+	int	ued_alt_index;
+	int	ued_endpoint_index;
+	usb_endpoint_descriptor_t ued_desc;
+};
+
+struct usb_full_desc {
+	int	ufd_config_index;
+	u_int	ufd_size;
+	u_char	*ufd_data;
+};
+
+struct usb_string_desc {
+	int	usd_string_index;
+	int	usd_language_id;
+	usb_string_descriptor_t usd_desc;
+};
+
+struct usb_ctl_report_desc {
+	int	ucrd_size;
+	u_char	ucrd_data[1024];	/* filled data size will vary */
+};
+
+typedef struct { u_int32_t cookie; } usb_event_cookie_t;
+
+#define USB_MAX_DEVNAMES 4
+#define USB_MAX_DEVNAMELEN 16
+struct usb_device_info {
+	u_int8_t	udi_bus;
+	u_int8_t	udi_addr;	/* device address */
+	usb_event_cookie_t udi_cookie;
+	char		udi_product[USB_MAX_STRING_LEN];
+	char		udi_vendor[USB_MAX_STRING_LEN];
+	char		udi_release[8];
+	u_int16_t	udi_productNo;
+	u_int16_t	udi_vendorNo;
+	u_int16_t	udi_releaseNo;
+	u_int8_t	udi_class;
+	u_int8_t	udi_subclass;
+	u_int8_t	udi_protocol;
+	u_int8_t	udi_config;
+	u_int8_t	udi_speed;
+#define USB_SPEED_LOW  1
+#define USB_SPEED_FULL 2
+#define USB_SPEED_HIGH 3
+	int		udi_power;	/* power consumption in mA, 0 if selfpowered */
+	int		udi_nports;
+	char		udi_devnames[USB_MAX_DEVNAMES][USB_MAX_DEVNAMELEN];
+	u_int8_t	udi_ports[16];/* hub only: addresses of devices on ports */
+#define USB_PORT_ENABLED 0xff
+#define USB_PORT_SUSPENDED 0xfe
+#define USB_PORT_POWERED 0xfd
+#define USB_PORT_DISABLED 0xfc
+};
+
+struct usb_ctl_report {
+	int	ucr_report;
+	u_char	ucr_data[1024];	/* filled data size will vary */
+};
+
+struct usb_device_stats {
+	u_long	uds_requests[4];	/* indexed by transfer type UE_* */
+};
+
+
+
+
+#define WUSB_MIN_IE			0x80
+#define WUSB_WCTA_IE			0x80
+#define WUSB_WCONNECTACK_IE		0x81
+#define WUSB_WHOSTINFO_IE		0x82
+#define  WUHI_GET_CA(_bmAttributes_) ((_bmAttributes_) & 0x3)
+#define   WUHI_CA_RECONN		        0x00
+#define   WUHI_CA_LIMITED	        0x01
+#define   WUHI_CA_ALL		        0x03
+#define  WUHI_GET_MLSI(_bmAttributes_) (((_bmAttributes_) & 0x38) >> 3)
+#define WUSB_WCHCHANGEANNOUNCE_IE	0x83
+#define WUSB_WDEV_DISCONNECT_IE		0x84
+#define WUSB_WHOST_DISCONNECT_IE	0x85
+#define WUSB_WRELEASE_CHANNEL_IE	0x86
+#define WUSB_WWORK_IE			0x87
+#define WUSB_WCHANNEL_STOP_IE		0x88
+#define WUSB_WDEV_KEEPALIVE_IE		0x89
+#define WUSB_WISOCH_DISCARD_IE		0x8A
+#define WUSB_WRESETDEVICE_IE		0x8B
+#define WUSB_WXMIT_PACKET_ADJUST_IE	0x8C
+#define WUSB_MAX_IE			0x8C
+
+/* Device Notification Types */
+
+#define WUSB_DN_MIN			0x01
+#define WUSB_DN_CONNECT			0x01
+# define WUSB_DA_OLDCONN	0x00
+# define WUSB_DA_NEWCONN	0x01
+# define WUSB_DA_SELF_BEACON	0x02
+# define WUSB_DA_DIR_BEACON	0x04
+# define WUSB_DA_NO_BEACON	0x06
+#define WUSB_DN_DISCONNECT		0x02
+#define WUSB_DN_EPRDY			0x03
+#define WUSB_DN_MASAVAILCHANGED		0x04
+#define WUSB_DN_REMOTEWAKEUP		0x05
+#define WUSB_DN_SLEEP			0x06
+#define WUSB_DN_ALIVE			0x07
+#define WUSB_DN_MAX			0x07
+
+
+/* WUSB Handshake Data.  Used during the SET/GET HANDSHAKE requests */
+typedef struct wusb_hndshk_data {
+	uint8_t bMessageNumber;
+	uint8_t bStatus;
+	uint8_t tTKID[3];
+	uint8_t bReserved;
+	uint8_t CDID[16];
+	uint8_t Nonce[16];
+	uint8_t MIC[8];
+} UPACKED wusb_hndshk_data_t;
+#define WUSB_HANDSHAKE_LEN_FOR_MIC	38
+
+/* WUSB Connection Context */
+typedef struct wusb_conn_context {
+	uint8_t CHID [16];
+	uint8_t CDID [16];
+	uint8_t CK [16];
+} UPACKED wusb_conn_context_t;
+
+/* WUSB Security Descriptor */
+typedef struct wusb_security_desc {
+	uint8_t bLength;
+	uint8_t bDescriptorType;
+	uint16_t wTotalLength;
+	uint8_t bNumEncryptionTypes;
+} UPACKED wusb_security_desc_t;
+
+/* WUSB Encryption Type Descriptor */
+typedef struct wusb_encrypt_type_desc {
+	uint8_t bLength;
+	uint8_t bDescriptorType;
+
+	uint8_t bEncryptionType;
+#define WUETD_UNSECURE	        0
+#define WUETD_WIRED		1
+#define WUETD_CCM_1		2
+#define WUETD_RSA_1		3
+
+	uint8_t bEncryptionValue;
+	uint8_t bAuthKeyIndex;
+} UPACKED wusb_encrypt_type_desc_t;
+
+/* WUSB Key Descriptor */
+typedef struct wusb_key_desc {
+	uint8_t bLength;
+	uint8_t bDescriptorType;
+	uint8_t tTKID[3];
+	uint8_t bReserved;
+	uint8_t KeyData[1];	/* variable length */
+} UPACKED wusb_key_desc_t;
+
+/* WUSB BOS Descriptor (Binary device Object Store) */
+typedef struct wusb_bos_desc {
+	uint8_t bLength;
+	uint8_t bDescriptorType;
+	uint16_t wTotalLength;
+	uint8_t bNumDeviceCaps;
+} UPACKED wusb_bos_desc_t;
+
+
+/* Device Capability Type Codes */
+#define WUSB_DEVICE_CAPABILITY_WIRELESS_USB 0x01
+
+/* Device Capability Descriptor */
+typedef struct wusb_dev_cap_desc {
+	uint8_t bLength;
+	uint8_t bDescriptorType;
+	uint8_t bDevCapabilityType;
+	uint8_t caps[1];	      /* Variable length */
+} UPACKED wusb_dev_cap_desc_t;
+
+/* Device Capability Descriptor */
+typedef struct wusb_dev_cap_uwb_desc {
+	uint8_t bLength;
+	uint8_t bDescriptorType;
+	uint8_t bDevCapabilityType;
+	uint8_t bmAttributes;
+	uint16_t wPHYRates;      /* Bitmap */
+	uint8_t bmTFITXPowerInfo;
+	uint8_t bmFFITXPowerInfo;
+	uint16_t bmBandGroup;
+	uint8_t bReserved;
+} UPACKED wusb_dev_cap_uwb_desc_t;
+
+/* Wireless USB Endpoint Companion Descriptor */
+typedef struct wusb_endpoint_companion_desc {
+	uint8_t bLength;
+	uint8_t bDescriptorType;
+	uint8_t bMaxBurst;
+	uint8_t bMaxSequence;
+	uint16_t wMaxStreamDelay;
+	uint16_t wOverTheAirPacketSize;
+	uint8_t bOverTheAirInterval;
+	uint8_t bmCompAttributes;
+} UPACKED wusb_endpoint_companion_desc_t;
+
+
+/* Wireless USB Numeric Association M1 Data Structure */
+typedef struct wusb_m1_data {
+	uint8_t version;
+	uint16_t langId;
+	uint8_t deviceFriendlyNameLength;
+	uint8_t sha_256_m3[32];
+	uint8_t deviceFriendlyName[256];
+} UPACKED wusb_m1_data_t;
+
+typedef struct wusb_m2_data {
+	uint8_t version;
+	uint16_t langId;
+	uint8_t hostFriendlyNameLength;
+	uint8_t pkh[384];
+	uint8_t hostFriendlyName[256];
+} UPACKED wusb_m2_data_t;
+
+typedef struct wusb_m3_data {
+	uint8_t pkd[384];
+	uint8_t nd;
+} UPACKED wusb_m3_data_t;
+
+typedef struct wusb_m4_data {
+	uint32_t _attributeTypeIdAndLength_1;
+	uint16_t associationTypeId;
+
+	uint32_t _attributeTypeIdAndLength_2;
+	uint16_t associationSubTypeId;
+
+	uint32_t _attributeTypeIdAndLength_3;
+	uint32_t length;
+
+	uint32_t _attributeTypeIdAndLength_4;
+	uint32_t associationStatus;
+
+	uint32_t _attributeTypeIdAndLength_5;
+	uint8_t chid[16];
+
+	uint32_t _attributeTypeIdAndLength_6;
+	uint8_t cdid[16];
+
+	uint32_t _attributeTypeIdAndLength_7;
+	uint8_t bandGroups[2];
+} UPACKED wusb_m4_data_t;
+
+
+
+
+#endif /* _USB_H_ */
diff --git a/drivers/usb/host/dwc_otg/Makefile b/drivers/usb/host/dwc_otg/Makefile
new file mode 100644
index 000000000000..161fe371c8aa
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/Makefile
@@ -0,0 +1,78 @@
+#
+# Makefile for DWC_otg Highspeed USB controller driver
+#
+
+ifneq ($(KERNELRELEASE),)
+
+ifeq ($(BUS_INTERFACE),)
+	# BUS_INTERFACE = -DLM_INTERFACE
+	BUS_INTERFACE = -DPLATFORM_INTERFACE=1
+endif
+
+CPPFLAGS	+= -DDEBUG 
+
+# Use one of the following flags to compile the software in host-only or
+# device-only mode.
+#CPPFLAGS        += -DDWC_HOST_ONLY
+#CPPFLAGS        += -DDWC_DEVICE_ONLY
+
+CPPFLAGS	+= -Dlinux -DDWC_HS_ELECT_TST
+#CGG: CPPFLAGS	+= -DDWC_EN_ISOC
+CPPFLAGS   	+= -I$(obj)/../dwc_common_port
+#CPPFLAGS   	+= -I$(PORTLIB)
+CPPFLAGS   	+= -DDWC_LINUX
+CPPFLAGS   	+= $(CFI)
+CPPFLAGS	+= $(BUS_INTERFACE)
+
+obj-$(CONFIG_USB_DWCOTG) += dwc_otg.o
+
+dwc_otg-objs	:= dwc_otg_driver.o dwc_otg_attr.o 
+dwc_otg-objs	+= dwc_otg_cil.o dwc_otg_cil_intr.o 
+dwc_otg-objs	+= dwc_otg_pcd_linux.o dwc_otg_pcd.o dwc_otg_pcd_intr.o 
+dwc_otg-objs	+= dwc_otg_hcd.o dwc_otg_hcd_linux.o dwc_otg_hcd_intr.o dwc_otg_hcd_queue.o dwc_otg_hcd_ddma.o
+ifneq ($(CFI),)
+dwc_otg-objs	+= dwc_otg_cfi.o
+endif
+
+kernrelwd := $(subst ., ,$(KERNELRELEASE))
+kernrel3 := $(word 1,$(kernrelwd)).$(word 2,$(kernrelwd)).$(word 3,$(kernrelwd))
+
+ifneq ($(kernrel3),2.6.20)
+EXTRA_CFLAGS += $(CPPFLAGS)
+endif
+
+else
+
+PWD		:= $(shell pwd)
+PORTLIB		:= $(PWD)/../dwc_common_port
+
+# Command paths
+CTAGS		:= $(CTAGS)
+DOXYGEN		:= $(DOXYGEN)
+
+default: portlib
+	$(MAKE) -C$(KDIR) M=$(PWD) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules
+
+install: default
+ifneq ($(INSTALL_MOD_PATH),)
+	$(MAKE) -C$(KDIR) M=$(PORTLIB) modules_install
+	$(MAKE) -C$(KDIR) M=$(PWD) modules_install	
+else
+	@echo "No install path defined"
+endif
+
+portlib:
+	$(MAKE) -C$(KDIR) M=$(PORTLIB) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules
+	cp $(PORTLIB)/Module.symvers $(PWD)/
+
+docs:	$(wildcard *.[hc]) doc/doxygen.cfg
+	$(DOXYGEN) doc/doxygen.cfg
+
+tags:	$(wildcard *.[hc])
+	$(CTAGS) -e $(wildcard *.[hc]) $(wildcard linux/*.[hc]) $(wildcard $(KDIR)/include/linux/usb*.h)
+
+
+clean:
+	rm -rf   *.o *.ko .*cmd *.mod.c .tmp_versions
+
+endif
diff --git a/drivers/usb/host/dwc_otg/doc/doxygen.cfg b/drivers/usb/host/dwc_otg/doc/doxygen.cfg
new file mode 100644
index 000000000000..ddd0a1013a4b
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/doxygen.cfg
@@ -0,0 +1,224 @@
+# Doxyfile 1.3.9.1
+
+#---------------------------------------------------------------------------
+# Project related configuration options
+#---------------------------------------------------------------------------
+PROJECT_NAME           = "DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver"
+PROJECT_NUMBER         = v2.90a
+OUTPUT_DIRECTORY       = ./doc/
+CREATE_SUBDIRS         = NO
+OUTPUT_LANGUAGE        = English
+BRIEF_MEMBER_DESC      = YES
+REPEAT_BRIEF           = YES
+ABBREVIATE_BRIEF       = "The $name class" \
+                         "The $name widget" \
+                         "The $name file" \
+                         is \
+                         provides \
+                         specifies \
+                         contains \
+                         represents \
+                         a \
+                         an \
+                         the
+ALWAYS_DETAILED_SEC    = NO
+INLINE_INHERITED_MEMB  = NO
+FULL_PATH_NAMES        = NO
+STRIP_FROM_PATH        = 
+STRIP_FROM_INC_PATH    = 
+SHORT_NAMES            = NO
+JAVADOC_AUTOBRIEF      = YES
+MULTILINE_CPP_IS_BRIEF = NO
+INHERIT_DOCS           = YES
+DISTRIBUTE_GROUP_DOC   = NO
+TAB_SIZE               = 8
+ALIASES                = 
+OPTIMIZE_OUTPUT_FOR_C  = YES
+OPTIMIZE_OUTPUT_JAVA   = NO
+SUBGROUPING            = YES
+#---------------------------------------------------------------------------
+# Build related configuration options
+#---------------------------------------------------------------------------
+EXTRACT_ALL            = NO
+EXTRACT_PRIVATE        = YES
+EXTRACT_STATIC         = YES
+EXTRACT_LOCAL_CLASSES  = YES
+EXTRACT_LOCAL_METHODS  = NO
+HIDE_UNDOC_MEMBERS     = NO
+HIDE_UNDOC_CLASSES     = NO
+HIDE_FRIEND_COMPOUNDS  = NO
+HIDE_IN_BODY_DOCS      = NO
+INTERNAL_DOCS          = NO
+CASE_SENSE_NAMES       = NO
+HIDE_SCOPE_NAMES       = NO
+SHOW_INCLUDE_FILES     = YES
+INLINE_INFO            = YES
+SORT_MEMBER_DOCS       = NO
+SORT_BRIEF_DOCS        = NO
+SORT_BY_SCOPE_NAME     = NO
+GENERATE_TODOLIST      = YES
+GENERATE_TESTLIST      = YES
+GENERATE_BUGLIST       = YES
+GENERATE_DEPRECATEDLIST= YES
+ENABLED_SECTIONS       = 
+MAX_INITIALIZER_LINES  = 30
+SHOW_USED_FILES        = YES
+SHOW_DIRECTORIES       = YES
+#---------------------------------------------------------------------------
+# configuration options related to warning and progress messages
+#---------------------------------------------------------------------------
+QUIET                  = YES
+WARNINGS               = YES
+WARN_IF_UNDOCUMENTED   = NO
+WARN_IF_DOC_ERROR      = YES
+WARN_FORMAT            = "$file:$line: $text"
+WARN_LOGFILE           = 
+#---------------------------------------------------------------------------
+# configuration options related to the input files
+#---------------------------------------------------------------------------
+INPUT                  = .
+FILE_PATTERNS          = *.c \
+                         *.h \
+                         ./linux/*.c \
+                         ./linux/*.h
+RECURSIVE              = NO
+EXCLUDE                = ./test/ \
+                         ./dwc_otg/.AppleDouble/
+EXCLUDE_SYMLINKS       = YES
+EXCLUDE_PATTERNS       = *.mod.*
+EXAMPLE_PATH           = 
+EXAMPLE_PATTERNS       = *
+EXAMPLE_RECURSIVE      = NO
+IMAGE_PATH             = 
+INPUT_FILTER           = 
+FILTER_PATTERNS        = 
+FILTER_SOURCE_FILES    = NO
+#---------------------------------------------------------------------------
+# configuration options related to source browsing
+#---------------------------------------------------------------------------
+SOURCE_BROWSER         = YES
+INLINE_SOURCES         = NO
+STRIP_CODE_COMMENTS    = YES
+REFERENCED_BY_RELATION = NO
+REFERENCES_RELATION    = NO
+VERBATIM_HEADERS       = NO
+#---------------------------------------------------------------------------
+# configuration options related to the alphabetical class index
+#---------------------------------------------------------------------------
+ALPHABETICAL_INDEX     = NO
+COLS_IN_ALPHA_INDEX    = 5
+IGNORE_PREFIX          = 
+#---------------------------------------------------------------------------
+# configuration options related to the HTML output
+#---------------------------------------------------------------------------
+GENERATE_HTML          = YES
+HTML_OUTPUT            = html
+HTML_FILE_EXTENSION    = .html
+HTML_HEADER            = 
+HTML_FOOTER            = 
+HTML_STYLESHEET        = 
+HTML_ALIGN_MEMBERS     = YES
+GENERATE_HTMLHELP      = NO
+CHM_FILE               = 
+HHC_LOCATION           = 
+GENERATE_CHI           = NO
+BINARY_TOC             = NO
+TOC_EXPAND             = NO
+DISABLE_INDEX          = NO
+ENUM_VALUES_PER_LINE   = 4
+GENERATE_TREEVIEW      = YES
+TREEVIEW_WIDTH         = 250
+#---------------------------------------------------------------------------
+# configuration options related to the LaTeX output
+#---------------------------------------------------------------------------
+GENERATE_LATEX         = NO
+LATEX_OUTPUT           = latex
+LATEX_CMD_NAME         = latex
+MAKEINDEX_CMD_NAME     = makeindex
+COMPACT_LATEX          = NO
+PAPER_TYPE             = a4wide
+EXTRA_PACKAGES         = 
+LATEX_HEADER           = 
+PDF_HYPERLINKS         = NO
+USE_PDFLATEX           = NO
+LATEX_BATCHMODE        = NO
+LATEX_HIDE_INDICES     = NO
+#---------------------------------------------------------------------------
+# configuration options related to the RTF output
+#---------------------------------------------------------------------------
+GENERATE_RTF           = NO
+RTF_OUTPUT             = rtf
+COMPACT_RTF            = NO
+RTF_HYPERLINKS         = NO
+RTF_STYLESHEET_FILE    = 
+RTF_EXTENSIONS_FILE    = 
+#---------------------------------------------------------------------------
+# configuration options related to the man page output
+#---------------------------------------------------------------------------
+GENERATE_MAN           = NO
+MAN_OUTPUT             = man
+MAN_EXTENSION          = .3
+MAN_LINKS              = NO
+#---------------------------------------------------------------------------
+# configuration options related to the XML output
+#---------------------------------------------------------------------------
+GENERATE_XML           = NO
+XML_OUTPUT             = xml
+XML_SCHEMA             = 
+XML_DTD                = 
+XML_PROGRAMLISTING     = YES
+#---------------------------------------------------------------------------
+# configuration options for the AutoGen Definitions output
+#---------------------------------------------------------------------------
+GENERATE_AUTOGEN_DEF   = NO
+#---------------------------------------------------------------------------
+# configuration options related to the Perl module output
+#---------------------------------------------------------------------------
+GENERATE_PERLMOD       = NO
+PERLMOD_LATEX          = NO
+PERLMOD_PRETTY         = YES
+PERLMOD_MAKEVAR_PREFIX = 
+#---------------------------------------------------------------------------
+# Configuration options related to the preprocessor   
+#---------------------------------------------------------------------------
+ENABLE_PREPROCESSING   = YES
+MACRO_EXPANSION        = YES
+EXPAND_ONLY_PREDEF     = YES
+SEARCH_INCLUDES        = YES
+INCLUDE_PATH           = 
+INCLUDE_FILE_PATTERNS  = 
+PREDEFINED             = DEVICE_ATTR DWC_EN_ISOC
+EXPAND_AS_DEFINED      = DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW DWC_OTG_DEVICE_ATTR_BITFIELD_STORE DWC_OTG_DEVICE_ATTR_BITFIELD_RW DWC_OTG_DEVICE_ATTR_BITFIELD_RO DWC_OTG_DEVICE_ATTR_REG_SHOW DWC_OTG_DEVICE_ATTR_REG_STORE DWC_OTG_DEVICE_ATTR_REG32_RW DWC_OTG_DEVICE_ATTR_REG32_RO DWC_EN_ISOC
+SKIP_FUNCTION_MACROS   = NO
+#---------------------------------------------------------------------------
+# Configuration::additions related to external references   
+#---------------------------------------------------------------------------
+TAGFILES               = 
+GENERATE_TAGFILE       = 
+ALLEXTERNALS           = NO
+EXTERNAL_GROUPS        = YES
+PERL_PATH              = /usr/bin/perl
+#---------------------------------------------------------------------------
+# Configuration options related to the dot tool   
+#---------------------------------------------------------------------------
+CLASS_DIAGRAMS         = YES
+HIDE_UNDOC_RELATIONS   = YES
+HAVE_DOT               = NO
+CLASS_GRAPH            = YES
+COLLABORATION_GRAPH    = YES
+UML_LOOK               = NO
+TEMPLATE_RELATIONS     = NO
+INCLUDE_GRAPH          = YES
+INCLUDED_BY_GRAPH      = YES
+CALL_GRAPH             = NO
+GRAPHICAL_HIERARCHY    = YES
+DOT_IMAGE_FORMAT       = png
+DOT_PATH               = 
+DOTFILE_DIRS           = 
+MAX_DOT_GRAPH_DEPTH    = 1000
+GENERATE_LEGEND        = YES
+DOT_CLEANUP            = YES
+#---------------------------------------------------------------------------
+# Configuration::additions related to the search engine   
+#---------------------------------------------------------------------------
+SEARCHENGINE           = NO
diff --git a/drivers/usb/host/dwc_otg/doc/html/annotated.html b/drivers/usb/host/dwc_otg/doc/html/annotated.html
new file mode 100644
index 000000000000..1ef51acd4ad7
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/annotated.html
@@ -0,0 +1,120 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Structures</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver Data Structures</h1>Here are the data structures with brief descriptions:<table>
+  <tr><td class="indexkey"><a class="el" href="struct__ddma__align__buffer__setup.html">_ddma_align_buffer_setup</a></td><td class="indexvalue">Descriptor DMA Alignment Buffer setup structure </td></tr>
+  <tr><td class="indexkey"><a class="el" href="struct__ddma__concat__buffer__setup.html">_ddma_concat_buffer_setup</a></td><td class="indexvalue">Descriptor DMA Concatenation Buffer setup structure </td></tr>
+  <tr><td class="indexkey"><a class="el" href="struct__ddma__concat__buffer__setup__hdr.html">_ddma_concat_buffer_setup_hdr</a></td><td class="indexvalue">Descriptor DMA Concatenation Buffer setup structure </td></tr>
+  <tr><td class="indexkey"><a class="el" href="struct__ddma__sg__buffer__setup.html">_ddma_sg_buffer_setup</a></td><td class="indexvalue">Descriptor DMA SG Buffer setup structure (SG buffer) </td></tr>
+  <tr><td class="indexkey"><a class="el" href="struct__rx__fifo__size__setup.html">_rx_fifo_size_setup</a></td><td class="indexvalue">Transmit FIFO Size setup structure </td></tr>
+  <tr><td class="indexkey"><a class="el" href="struct__tx__fifo__size__setup.html">_tx_fifo_size_setup</a></td><td class="indexvalue">Transmit FIFO Size setup structure </td></tr>
+  <tr><td class="indexkey"><a class="el" href="structcfi__all__features__header.html">cfi_all_features_header</a></td><td class="indexvalue">This structure is the header of the Core Features dataset returned to the Host </td></tr>
+  <tr><td class="indexkey"><a class="el" href="structcfi__dma__buff.html">cfi_dma_buff</a></td><td class="indexvalue"></td></tr>
+  <tr><td class="indexkey"><a class="el" href="structcfi__ep.html">cfi_ep</a></td><td class="indexvalue">The CFI wrapper of the enabled and activated <a class="el" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep</a> structures </td></tr>
+  <tr><td class="indexkey"><a class="el" href="structcfi__feature__desc__header.html">cfi_feature_desc_header</a></td><td class="indexvalue">This structure is a header of the Core Feature descriptor dataset returned to the Host after the VEN_CORE_GET_FEATURES request </td></tr>
+  <tr><td class="indexkey"><a class="el" href="structcfi__ops.html">cfi_ops</a></td><td class="indexvalue">This is the interface for the CFI operations </td></tr>
+  <tr><td class="indexkey"><a class="el" href="structcfi__string.html">cfi_string</a></td><td class="indexvalue">This structure describes a NULL terminated string referenced by its id field </td></tr>
+  <tr><td class="indexkey"><a class="el" href="structcfi__usb__ctrlrequest.html">cfi_usb_ctrlrequest</a></td><td class="indexvalue">Struct <a class="el" href="structcfi__usb__ctrlrequest.html">cfi_usb_ctrlrequest</a> - the CFI implementation of the struct usb_ctrlrequest This structure encapsulates the standard usb_ctrlrequest and adds a pointer to the data returned in the data stage of a 3-stage Control Write requests </td></tr>
+  <tr><td class="indexkey"><a class="el" href="structcfiobject.html">cfiobject</a></td><td class="indexvalue"></td></tr>
+  <tr><td class="indexkey"><a class="el" href="uniondaint__data.html">daint_data</a></td><td class="indexvalue">This union represents the bit fields in the Device All EP Interrupt and Mask Registers </td></tr>
+  <tr><td class="indexkey"><a class="el" href="uniondcfg__data.html">dcfg_data</a></td><td class="indexvalue">This union represents the bit fields in the Device Configuration Register </td></tr>
+  <tr><td class="indexkey"><a class="el" href="uniondctl__data.html">dctl_data</a></td><td class="indexvalue">This union represents the bit fields in the Device Control Register </td></tr>
+  <tr><td class="indexkey"><a class="el" href="uniondepctl__data.html">depctl_data</a></td><td class="indexvalue">This union represents the bit fields in the Device EP Control Register </td></tr>
+  <tr><td class="indexkey"><a class="el" href="uniondeptsiz0__data.html">deptsiz0_data</a></td><td class="indexvalue">This union represents the bit fields in the Device EP 0 Transfer Size Register </td></tr>
+  <tr><td class="indexkey"><a class="el" href="uniondeptsiz__data.html">deptsiz_data</a></td><td class="indexvalue">This union represents the bit fields in the Device EP Transfer Size Register </td></tr>
+  <tr><td class="indexkey"><a class="el" href="uniondev__dma__desc__sts.html">dev_dma_desc_sts</a></td><td class="indexvalue">This union represents the bit fields in the DMA Descriptor status quadlet </td></tr>
+  <tr><td class="indexkey"><a class="el" href="uniondevice__grxsts__data.html">device_grxsts_data</a></td><td class="indexvalue">This union represents the bit fields in the Device Receive Status Read and Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <em>d32</em> element then read out the bits using the <em>b</em>it elements </td></tr>
+  <tr><td class="indexkey"><a class="el" href="uniondiepint__data.html">diepint_data</a></td><td class="indexvalue">This union represents the bit fields in the Device IN EP Interrupt Register and the Device IN EP Common Mask Register </td></tr>
+  <tr><td class="indexkey"><a class="el" href="uniondoepint__data.html">doepint_data</a></td><td class="indexvalue">This union represents the bit fields in the Device OUT EP Interrupt Registerand Device OUT EP Common Interrupt Mask Register </td></tr>
+  <tr><td class="indexkey"><a class="el" href="uniondsts__data.html">dsts_data</a></td><td class="indexvalue">This union represents the bit fields in the Device Status Register </td></tr>
+  <tr><td class="indexkey"><a class="el" href="uniondthrctl__data.html">dthrctl_data</a></td><td class="indexvalue">This union represents Threshold control Register<ul>
+<li>Read and write the register into the <em>d32</em> member </li></ul>
+</td></tr>
+  <tr><td class="indexkey"><a class="el" href="uniondtknq1__data.html">dtknq1_data</a></td><td class="indexvalue">This union represents the bit fields in the Device IN Token Queue Read Registers </td></tr>
+  <tr><td class="indexkey"><a class="el" href="uniondtxfsts__data.html">dtxfsts_data</a></td><td class="indexvalue">This union represents the bit fields in the Transmit FIFO Status Register (DTXFSTS) </td></tr>
+  <tr><td class="indexkey"><a class="el" href="structdwc__ep.html">dwc_ep</a></td><td class="indexvalue">The <code><a class="el" href="structdwc__ep.html">dwc_ep</a></code> structure represents the state of a single endpoint when acting in device mode </td></tr>
+  <tr><td class="indexkey"><a class="el" href="structdwc__hc.html">dwc_hc</a></td><td class="indexvalue">Host channel descriptor </td></tr>
+  <tr><td class="indexkey"><a class="el" href="structdwc__otg__cil__callbacks.html">dwc_otg_cil_callbacks</a></td><td class="indexvalue">DWC_otg CIL callback structure </td></tr>
+  <tr><td class="indexkey"><a class="el" href="structdwc__otg__core__global__regs.html">dwc_otg_core_global_regs</a></td><td class="indexvalue">DWC_otg Core registers </td></tr>
+  <tr><td class="indexkey"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if</a></td><td class="indexvalue">The <code><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if</a></code> structure contains information needed to manage the DWC_otg controller acting in either host or device mode </td></tr>
+  <tr><td class="indexkey"><a class="el" href="structdwc__otg__core__params.html">dwc_otg_core_params</a></td><td class="indexvalue">The following parameters may be specified when starting the module </td></tr>
+  <tr><td class="indexkey"><a class="el" href="structdwc__otg__dev__dma__desc.html">dwc_otg_dev_dma_desc</a></td><td class="indexvalue">DMA Descriptor structure </td></tr>
+  <tr><td class="indexkey"><a class="el" href="structdwc__otg__dev__global__regs.html">dwc_otg_dev_global_regs</a></td><td class="indexvalue">Device Global Registers </td></tr>
+  <tr><td class="indexkey"><a class="el" href="structdwc__otg__dev__if.html">dwc_otg_dev_if</a></td><td class="indexvalue">The <a class="el" href="structdwc__otg__dev__if.html">dwc_otg_dev_if</a> structure contains information needed to manage the DWC_otg controller acting in device mode </td></tr>
+  <tr><td class="indexkey"><a class="el" href="structdwc__otg__dev__in__ep__regs.html">dwc_otg_dev_in_ep_regs</a></td><td class="indexvalue">Device Logical IN Endpoint-Specific Registers </td></tr>
+  <tr><td class="indexkey"><a class="el" href="structdwc__otg__dev__out__ep__regs.html">dwc_otg_dev_out_ep_regs</a></td><td class="indexvalue">Device Logical OUT Endpoint-Specific Registers </td></tr>
+  <tr><td class="indexkey"><a class="el" href="structdwc__otg__device.html">dwc_otg_device</a></td><td class="indexvalue">This structure is a wrapper that encapsulates the driver components used to manage a single DWC_otg controller </td></tr>
+  <tr><td class="indexkey"><a class="el" href="structdwc__otg__driver__module__params.html">dwc_otg_driver_module_params</a></td><td class="indexvalue"></td></tr>
+  <tr><td class="indexkey"><a class="el" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs</a></td><td class="indexvalue">Host Channel Specific Registers </td></tr>
+  <tr><td class="indexkey"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd</a></td><td class="indexvalue">This structure holds the state of the HCD, including the non-periodic and periodic schedules </td></tr>
+  <tr><td class="indexkey"><a class="el" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html">dwc_otg_hcd::dwc_otg_hcd_internal_flags</a></td><td class="indexvalue">Internal DWC HCD Flags </td></tr>
+  <tr><td class="indexkey"><a class="el" href="structdwc__otg__hcd__function__ops.html">dwc_otg_hcd_function_ops</a></td><td class="indexvalue"></td></tr>
+  <tr><td class="indexkey"><a class="el" href="structdwc__otg__hcd__iso__packet__desc.html">dwc_otg_hcd_iso_packet_desc</a></td><td class="indexvalue"></td></tr>
+  <tr><td class="indexkey"><a class="el" href="structdwc__otg__hcd__pipe__info.html">dwc_otg_hcd_pipe_info</a></td><td class="indexvalue"></td></tr>
+  <tr><td class="indexkey"><a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb</a></td><td class="indexvalue"></td></tr>
+  <tr><td class="indexkey"><a class="el" href="structdwc__otg__host__dma__desc.html">dwc_otg_host_dma_desc</a></td><td class="indexvalue">Host-mode DMA Descriptor structure </td></tr>
+  <tr><td class="indexkey"><a class="el" href="structdwc__otg__host__global__regs.html">dwc_otg_host_global_regs</a></td><td class="indexvalue">The Host Global Registers structure defines the size and relative field offsets for the Host Mode Global Registers </td></tr>
+  <tr><td class="indexkey"><a class="el" href="structdwc__otg__host__if.html">dwc_otg_host_if</a></td><td class="indexvalue">OTG Host Interface Structure </td></tr>
+  <tr><td class="indexkey"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd</a></td><td class="indexvalue">DWC_otg PCD Structure </td></tr>
+  <tr><td class="indexkey"><a class="el" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep</a></td><td class="indexvalue">PCD EP structure </td></tr>
+  <tr><td class="indexkey"><a class="el" href="structdwc__otg__pcd__function__ops.html">dwc_otg_pcd_function_ops</a></td><td class="indexvalue">Function Driver Ops Data Structure </td></tr>
+  <tr><td class="indexkey"><a class="el" href="structdwc__otg__pcd__request.html">dwc_otg_pcd_request</a></td><td class="indexvalue">DWC_otg request structure </td></tr>
+  <tr><td class="indexkey"><a class="el" href="structdwc__otg__qh.html">dwc_otg_qh</a></td><td class="indexvalue">A Queue Head (QH) holds the static characteristics of an endpoint and maintains a list of transfers (QTDs) for that endpoint </td></tr>
+  <tr><td class="indexkey"><a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd</a></td><td class="indexvalue">A Queue Transfer Descriptor (QTD) holds the state of a bulk, control, interrupt, or isochronous transfer </td></tr>
+  <tr><td class="indexkey"><a class="el" href="unionfifosize__data.html">fifosize_data</a></td><td class="indexvalue">This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ, GNPTXFSIZ, DPTXFSIZn, DIEPTXFn) </td></tr>
+  <tr><td class="indexkey"><a class="el" href="structgadget__wrapper.html">gadget_wrapper</a></td><td class="indexvalue"></td></tr>
+  <tr><td class="indexkey"><a class="el" href="uniongahbcfg__data.html">gahbcfg_data</a></td><td class="indexvalue">This union represents the bit fields of the Core AHB Configuration Register (GAHBCFG) </td></tr>
+  <tr><td class="indexkey"><a class="el" href="uniongi2cctl__data.html">gi2cctl_data</a></td><td class="indexvalue">This union represents the bit fields in the I2C Control Register (I2CCTL) </td></tr>
+  <tr><td class="indexkey"><a class="el" href="uniongintmsk__data.html">gintmsk_data</a></td><td class="indexvalue">This union represents the bit fields of the Core Interrupt Mask Register (GINTMSK) </td></tr>
+  <tr><td class="indexkey"><a class="el" href="uniongintsts__data.html">gintsts_data</a></td><td class="indexvalue">This union represents the bit fields of the Core Interrupt Register (GINTSTS) </td></tr>
+  <tr><td class="indexkey"><a class="el" href="unionglpmctl__data.html">glpmctl_data</a></td><td class="indexvalue">This union represents the bit fields of the Core LPM Configuration Register (GLPMCFG) </td></tr>
+  <tr><td class="indexkey"><a class="el" href="uniongnptxsts__data.html">gnptxsts_data</a></td><td class="indexvalue">This union represents the bit fields in the Non-Periodic Transmit FIFO/Queue Status Register (GNPTXSTS) </td></tr>
+  <tr><td class="indexkey"><a class="el" href="uniongotgctl__data.html">gotgctl_data</a></td><td class="indexvalue">This union represents the bit fields of the Core OTG Control and Status Register (GOTGCTL) </td></tr>
+  <tr><td class="indexkey"><a class="el" href="uniongotgint__data.html">gotgint_data</a></td><td class="indexvalue">This union represents the bit fields of the Core OTG Interrupt Register (GOTGINT) </td></tr>
+  <tr><td class="indexkey"><a class="el" href="uniongrstctl__data.html">grstctl_data</a></td><td class="indexvalue">This union represents the bit fields of the Core Reset Register (GRSTCTL) </td></tr>
+  <tr><td class="indexkey"><a class="el" href="uniongusbcfg__data.html">gusbcfg_data</a></td><td class="indexvalue">This union represents the bit fields of the Core USB Configuration Register (GUSBCFG) </td></tr>
+  <tr><td class="indexkey"><a class="el" href="unionhaint__data.html">haint_data</a></td><td class="indexvalue">This union represents the bit fields in the Host All Interrupt Register </td></tr>
+  <tr><td class="indexkey"><a class="el" href="unionhaintmsk__data.html">haintmsk_data</a></td><td class="indexvalue">This union represents the bit fields in the Host All Interrupt Register </td></tr>
+  <tr><td class="indexkey"><a class="el" href="unionhcchar__data.html">hcchar_data</a></td><td class="indexvalue">This union represents the bit fields in the Host Channel Characteristics Register </td></tr>
+  <tr><td class="indexkey"><a class="el" href="unionhcdma__data.html">hcdma_data</a></td><td class="indexvalue">This union represents the bit fields in the Host DMA Address Register used in Descriptor DMA mode </td></tr>
+  <tr><td class="indexkey"><a class="el" href="unionhcfg__data.html">hcfg_data</a></td><td class="indexvalue">This union represents the bit fields in the Host Configuration Register </td></tr>
+  <tr><td class="indexkey"><a class="el" href="unionhcint__data.html">hcint_data</a></td><td class="indexvalue">This union represents the bit fields in the Host All Interrupt Register </td></tr>
+  <tr><td class="indexkey"><a class="el" href="unionhcintmsk__data.html">hcintmsk_data</a></td><td class="indexvalue">This union represents the bit fields in the Host Channel Interrupt Mask Register </td></tr>
+  <tr><td class="indexkey"><a class="el" href="unionhcsplt__data.html">hcsplt_data</a></td><td class="indexvalue"></td></tr>
+  <tr><td class="indexkey"><a class="el" href="unionhctsiz__data.html">hctsiz_data</a></td><td class="indexvalue">This union represents the bit fields in the Host Channel Transfer Size Register </td></tr>
+  <tr><td class="indexkey"><a class="el" href="unionhfir__data.html">hfir_data</a></td><td class="indexvalue">This union represents the bit fields in the Host Frame Remaing/Number Register </td></tr>
+  <tr><td class="indexkey"><a class="el" href="unionhfnum__data.html">hfnum_data</a></td><td class="indexvalue">This union represents the bit fields in the Host Frame Remaing/Number Register </td></tr>
+  <tr><td class="indexkey"><a class="el" href="unionhost__dma__desc__sts.html">host_dma_desc_sts</a></td><td class="indexvalue">This union represents the bit fields in the DMA Descriptor status quadlet for host mode </td></tr>
+  <tr><td class="indexkey"><a class="el" href="unionhost__grxsts__data.html">host_grxsts_data</a></td><td class="indexvalue">This union represents the bit fields in the Host Receive Status Read and Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <em>d32</em> element then read out the bits using the <em>b</em>it elements </td></tr>
+  <tr><td class="indexkey"><a class="el" href="unionhprt0__data.html">hprt0_data</a></td><td class="indexvalue">This union represents the bit fields in the Host Port Control and Status Register </td></tr>
+  <tr><td class="indexkey"><a class="el" href="unionhptxsts__data.html">hptxsts_data</a></td><td class="indexvalue"></td></tr>
+  <tr><td class="indexkey"><a class="el" href="unionhwcfg1__data.html">hwcfg1_data</a></td><td class="indexvalue">This union represents the bit fields in the User HW Config1 Register </td></tr>
+  <tr><td class="indexkey"><a class="el" href="unionhwcfg2__data.html">hwcfg2_data</a></td><td class="indexvalue">This union represents the bit fields in the User HW Config2 Register </td></tr>
+  <tr><td class="indexkey"><a class="el" href="unionhwcfg3__data.html">hwcfg3_data</a></td><td class="indexvalue">This union represents the bit fields in the User HW Config3 Register </td></tr>
+  <tr><td class="indexkey"><a class="el" href="unionhwcfg4__data.html">hwcfg4_data</a></td><td class="indexvalue">This union represents the bit fields in the User HW Config4 Register </td></tr>
+  <tr><td class="indexkey"><a class="el" href="structiso__pkt__info.html">iso_pkt_info</a></td><td class="indexvalue">Information for each ISOC packet </td></tr>
+  <tr><td class="indexkey"><a class="el" href="unionpcgcctl__data.html">pcgcctl_data</a></td><td class="indexvalue">This union represents the bit fields in the Power and Clock Gating Control Register </td></tr>
+  <tr><td class="indexkey"><a class="el" href="structwrapper__priv__data.html">wrapper_priv_data</a></td><td class="indexvalue"></td></tr>
+  <tr><td class="indexkey"><a class="el" href="structzero__dev.html">zero_dev</a></td><td class="indexvalue"></td></tr>
+</table>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
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+.memname {
+  white-space: nowrap;
+  font-weight: bold;
+}
+.memdoc{
+  padding-left: 10px;
+}
+.memproto {
+  background-color: #d5e1e8;
+  width: 100%;
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+  border-style: solid;
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+  font-weight: bold;
+  -moz-border-radius: 8px 8px 8px 8px;
+}
+.paramkey {
+  text-align: right;
+}
+.paramtype {
+  white-space: nowrap;
+}
+.paramname {
+  color: #602020;
+  font-style: italic;
+}
+/* End Styling for detailed member documentation */
+
+/* for the tree view */
+.ftvtree {
+	font-family: sans-serif;
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+}
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+
diff --git a/drivers/usb/host/dwc_otg/doc/html/dummy__audio_8c-source.html b/drivers/usb/host/dwc_otg/doc/html/dummy__audio_8c-source.html
new file mode 100644
index 000000000000..061802dd818a
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/dummy__audio_8c-source.html
@@ -0,0 +1,1550 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dummy_audio.c Source File</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<h1>dummy_audio.c</h1><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">/*</span>
+<a name="l00002"></a>00002 <span class="comment"> * zero.c -- Gadget Zero, for USB development</span>
+<a name="l00003"></a>00003 <span class="comment"> *</span>
+<a name="l00004"></a>00004 <span class="comment"> * Copyright (C) 2003-2004 David Brownell</span>
+<a name="l00005"></a>00005 <span class="comment"> * All rights reserved.</span>
+<a name="l00006"></a>00006 <span class="comment"> *</span>
+<a name="l00007"></a>00007 <span class="comment"> * Redistribution and use in source and binary forms, with or without</span>
+<a name="l00008"></a>00008 <span class="comment"> * modification, are permitted provided that the following conditions</span>
+<a name="l00009"></a>00009 <span class="comment"> * are met:</span>
+<a name="l00010"></a>00010 <span class="comment"> * 1. Redistributions of source code must retain the above copyright</span>
+<a name="l00011"></a>00011 <span class="comment"> *    notice, this list of conditions, and the following disclaimer,</span>
+<a name="l00012"></a>00012 <span class="comment"> *    without modification.</span>
+<a name="l00013"></a>00013 <span class="comment"> * 2. Redistributions in binary form must reproduce the above copyright</span>
+<a name="l00014"></a>00014 <span class="comment"> *    notice, this list of conditions and the following disclaimer in the</span>
+<a name="l00015"></a>00015 <span class="comment"> *    documentation and/or other materials provided with the distribution.</span>
+<a name="l00016"></a>00016 <span class="comment"> * 3. The names of the above-listed copyright holders may not be used</span>
+<a name="l00017"></a>00017 <span class="comment"> *    to endorse or promote products derived from this software without</span>
+<a name="l00018"></a>00018 <span class="comment"> *    specific prior written permission.</span>
+<a name="l00019"></a>00019 <span class="comment"> *</span>
+<a name="l00020"></a>00020 <span class="comment"> * ALTERNATIVELY, this software may be distributed under the terms of the</span>
+<a name="l00021"></a>00021 <span class="comment"> * GNU General Public License ("GPL") as published by the Free Software</span>
+<a name="l00022"></a>00022 <span class="comment"> * Foundation, either version 2 of that License or (at your option) any</span>
+<a name="l00023"></a>00023 <span class="comment"> * later version.</span>
+<a name="l00024"></a>00024 <span class="comment"> *</span>
+<a name="l00025"></a>00025 <span class="comment"> * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS</span>
+<a name="l00026"></a>00026 <span class="comment"> * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,</span>
+<a name="l00027"></a>00027 <span class="comment"> * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR</span>
+<a name="l00028"></a>00028 <span class="comment"> * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR</span>
+<a name="l00029"></a>00029 <span class="comment"> * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,</span>
+<a name="l00030"></a>00030 <span class="comment"> * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,</span>
+<a name="l00031"></a>00031 <span class="comment"> * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR</span>
+<a name="l00032"></a>00032 <span class="comment"> * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF</span>
+<a name="l00033"></a>00033 <span class="comment"> * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING</span>
+<a name="l00034"></a>00034 <span class="comment"> * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS</span>
+<a name="l00035"></a>00035 <span class="comment"> * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.</span>
+<a name="l00036"></a>00036 <span class="comment"> */</span>
+<a name="l00037"></a>00037 
+<a name="l00038"></a>00038 
+<a name="l00039"></a>00039 <span class="comment">/*</span>
+<a name="l00040"></a>00040 <span class="comment"> * Gadget Zero only needs two bulk endpoints, and is an example of how you</span>
+<a name="l00041"></a>00041 <span class="comment"> * can write a hardware-agnostic gadget driver running inside a USB device.</span>
+<a name="l00042"></a>00042 <span class="comment"> *</span>
+<a name="l00043"></a>00043 <span class="comment"> * Hardware details are visible (see CONFIG_USB_ZERO_* below) but don't</span>
+<a name="l00044"></a>00044 <span class="comment"> * affect most of the driver.</span>
+<a name="l00045"></a>00045 <span class="comment"> *</span>
+<a name="l00046"></a>00046 <span class="comment"> * Use it with the Linux host/master side "usbtest" driver to get a basic</span>
+<a name="l00047"></a>00047 <span class="comment"> * functional test of your device-side usb stack, or with "usb-skeleton".</span>
+<a name="l00048"></a>00048 <span class="comment"> *</span>
+<a name="l00049"></a>00049 <span class="comment"> * It supports two similar configurations.  One sinks whatever the usb host</span>
+<a name="l00050"></a>00050 <span class="comment"> * writes, and in return sources zeroes.  The other loops whatever the host</span>
+<a name="l00051"></a>00051 <span class="comment"> * writes back, so the host can read it.  Module options include:</span>
+<a name="l00052"></a>00052 <span class="comment"> *</span>
+<a name="l00053"></a>00053 <span class="comment"> *   buflen=N           default N=4096, buffer size used</span>
+<a name="l00054"></a>00054 <span class="comment"> *   qlen=N             default N=32, how many buffers in the loopback queue</span>
+<a name="l00055"></a>00055 <span class="comment"> *   loopdefault        default false, list loopback config first</span>
+<a name="l00056"></a>00056 <span class="comment"> *</span>
+<a name="l00057"></a>00057 <span class="comment"> * Many drivers will only have one configuration, letting them be much</span>
+<a name="l00058"></a>00058 <span class="comment"> * simpler if they also don't support high speed operation (like this</span>
+<a name="l00059"></a>00059 <span class="comment"> * driver does).</span>
+<a name="l00060"></a>00060 <span class="comment"> */</span>
+<a name="l00061"></a>00061 
+<a name="l00062"></a>00062 <span class="preprocessor">#include &lt;linux/config.h&gt;</span>
+<a name="l00063"></a>00063 <span class="preprocessor">#include &lt;linux/module.h&gt;</span>
+<a name="l00064"></a>00064 <span class="preprocessor">#include &lt;linux/kernel.h&gt;</span>
+<a name="l00065"></a>00065 <span class="preprocessor">#include &lt;linux/delay.h&gt;</span>
+<a name="l00066"></a>00066 <span class="preprocessor">#include &lt;linux/ioport.h&gt;</span>
+<a name="l00067"></a>00067 <span class="preprocessor">#include &lt;linux/sched.h&gt;</span>
+<a name="l00068"></a>00068 <span class="preprocessor">#include &lt;linux/slab.h&gt;</span>
+<a name="l00069"></a>00069 <span class="preprocessor">#include &lt;linux/smp_lock.h&gt;</span>
+<a name="l00070"></a>00070 <span class="preprocessor">#include &lt;linux/errno.h&gt;</span>
+<a name="l00071"></a>00071 <span class="preprocessor">#include &lt;linux/init.h&gt;</span>
+<a name="l00072"></a>00072 <span class="preprocessor">#include &lt;linux/timer.h&gt;</span>
+<a name="l00073"></a>00073 <span class="preprocessor">#include &lt;linux/list.h&gt;</span>
+<a name="l00074"></a>00074 <span class="preprocessor">#include &lt;linux/interrupt.h&gt;</span>
+<a name="l00075"></a>00075 <span class="preprocessor">#include &lt;linux/uts.h&gt;</span>
+<a name="l00076"></a>00076 <span class="preprocessor">#include &lt;linux/version.h&gt;</span>
+<a name="l00077"></a>00077 <span class="preprocessor">#include &lt;linux/device.h&gt;</span>
+<a name="l00078"></a>00078 <span class="preprocessor">#include &lt;linux/moduleparam.h&gt;</span>
+<a name="l00079"></a>00079 <span class="preprocessor">#include &lt;linux/proc_fs.h&gt;</span>
+<a name="l00080"></a>00080 
+<a name="l00081"></a>00081 <span class="preprocessor">#include &lt;asm/byteorder.h&gt;</span>
+<a name="l00082"></a>00082 <span class="preprocessor">#include &lt;asm/io.h&gt;</span>
+<a name="l00083"></a>00083 <span class="preprocessor">#include &lt;asm/irq.h&gt;</span>
+<a name="l00084"></a>00084 <span class="preprocessor">#include &lt;asm/system.h&gt;</span>
+<a name="l00085"></a>00085 <span class="preprocessor">#include &lt;asm/unaligned.h&gt;</span>
+<a name="l00086"></a>00086 
+<a name="l00087"></a>00087 <span class="preprocessor">#if LINUX_VERSION_CODE &gt;= KERNEL_VERSION(2,6,21)</span>
+<a name="l00088"></a>00088 <span class="preprocessor"></span><span class="preprocessor"># include &lt;linux/usb/ch9.h&gt;</span>
+<a name="l00089"></a>00089 <span class="preprocessor">#else</span>
+<a name="l00090"></a>00090 <span class="preprocessor"></span><span class="preprocessor"># include &lt;linux/usb_ch9.h&gt;</span>
+<a name="l00091"></a>00091 <span class="preprocessor">#endif</span>
+<a name="l00092"></a>00092 <span class="preprocessor"></span>
+<a name="l00093"></a>00093 <span class="preprocessor">#include &lt;linux/usb_gadget.h&gt;</span>
+<a name="l00094"></a>00094 
+<a name="l00095"></a>00095 
+<a name="l00096"></a>00096 <span class="comment">/*-------------------------------------------------------------------------*/</span>
+<a name="l00097"></a>00097 <span class="comment">/*-------------------------------------------------------------------------*/</span>
+<a name="l00098"></a>00098 
+<a name="l00099"></a>00099 
+<a name="l00100"></a>00100 <span class="keyword">static</span> <span class="keywordtype">int</span> utf8_to_utf16le(<span class="keyword">const</span> <span class="keywordtype">char</span> *s, u16 *cp, <span class="keywordtype">unsigned</span> len)
+<a name="l00101"></a>00101 {
+<a name="l00102"></a>00102         <span class="keywordtype">int</span>     count = 0;
+<a name="l00103"></a>00103         u8      c;
+<a name="l00104"></a>00104         u16     uchar;
+<a name="l00105"></a>00105 
+<a name="l00106"></a>00106         <span class="comment">/* this insists on correct encodings, though not minimal ones.</span>
+<a name="l00107"></a>00107 <span class="comment">         * BUT it currently rejects legit 4-byte UTF-8 code points,</span>
+<a name="l00108"></a>00108 <span class="comment">         * which need surrogate pairs.  (Unicode 3.1 can use them.)</span>
+<a name="l00109"></a>00109 <span class="comment">         */</span>
+<a name="l00110"></a>00110         <span class="keywordflow">while</span> (len != 0 &amp;&amp; (c = (u8) *s++) != 0) {
+<a name="l00111"></a>00111                 <span class="keywordflow">if</span> (unlikely(c &amp; 0x80)) {
+<a name="l00112"></a>00112                         <span class="comment">// 2-byte sequence:</span>
+<a name="l00113"></a>00113                         <span class="comment">// 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx</span>
+<a name="l00114"></a>00114                         <span class="keywordflow">if</span> ((c &amp; 0xe0) == 0xc0) {
+<a name="l00115"></a>00115                                 uchar = (c &amp; 0x1f) &lt;&lt; 6;
+<a name="l00116"></a>00116 
+<a name="l00117"></a>00117                                 c = (u8) *s++;
+<a name="l00118"></a>00118                                 <span class="keywordflow">if</span> ((c &amp; 0xc0) != 0xc0)
+<a name="l00119"></a>00119                                         <span class="keywordflow">goto</span> fail;
+<a name="l00120"></a>00120                                 c &amp;= 0x3f;
+<a name="l00121"></a>00121                                 uchar |= c;
+<a name="l00122"></a>00122 
+<a name="l00123"></a>00123                         <span class="comment">// 3-byte sequence (most CJKV characters):</span>
+<a name="l00124"></a>00124                         <span class="comment">// zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx</span>
+<a name="l00125"></a>00125                         } <span class="keywordflow">else</span> <span class="keywordflow">if</span> ((c &amp; 0xf0) == 0xe0) {
+<a name="l00126"></a>00126                                 uchar = (c &amp; 0x0f) &lt;&lt; 12;
+<a name="l00127"></a>00127 
+<a name="l00128"></a>00128                                 c = (u8) *s++;
+<a name="l00129"></a>00129                                 <span class="keywordflow">if</span> ((c &amp; 0xc0) != 0xc0)
+<a name="l00130"></a>00130                                         <span class="keywordflow">goto</span> fail;
+<a name="l00131"></a>00131                                 c &amp;= 0x3f;
+<a name="l00132"></a>00132                                 uchar |= c &lt;&lt; 6;
+<a name="l00133"></a>00133 
+<a name="l00134"></a>00134                                 c = (u8) *s++;
+<a name="l00135"></a>00135                                 <span class="keywordflow">if</span> ((c &amp; 0xc0) != 0xc0)
+<a name="l00136"></a>00136                                         <span class="keywordflow">goto</span> fail;
+<a name="l00137"></a>00137                                 c &amp;= 0x3f;
+<a name="l00138"></a>00138                                 uchar |= c;
+<a name="l00139"></a>00139 
+<a name="l00140"></a>00140                                 <span class="comment">/* no bogus surrogates */</span>
+<a name="l00141"></a>00141                                 <span class="keywordflow">if</span> (0xd800 &lt;= uchar &amp;&amp; uchar &lt;= 0xdfff)
+<a name="l00142"></a>00142                                         <span class="keywordflow">goto</span> fail;
+<a name="l00143"></a>00143 
+<a name="l00144"></a>00144                         <span class="comment">// 4-byte sequence (surrogate pairs, currently rare):</span>
+<a name="l00145"></a>00145                         <span class="comment">// 11101110wwwwzzzzyy + 110111yyyyxxxxxx</span>
+<a name="l00146"></a>00146                         <span class="comment">//     = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx</span>
+<a name="l00147"></a>00147                         <span class="comment">// (uuuuu = wwww + 1)</span>
+<a name="l00148"></a>00148                         <span class="comment">// FIXME accept the surrogate code points (only)</span>
+<a name="l00149"></a>00149 
+<a name="l00150"></a>00150                         } <span class="keywordflow">else</span>
+<a name="l00151"></a>00151                                 <span class="keywordflow">goto</span> fail;
+<a name="l00152"></a>00152                 } <span class="keywordflow">else</span>
+<a name="l00153"></a>00153                         uchar = c;
+<a name="l00154"></a>00154                 put_unaligned (cpu_to_le16 (uchar), cp++);
+<a name="l00155"></a>00155                 count++;
+<a name="l00156"></a>00156                 len--;
+<a name="l00157"></a>00157         }
+<a name="l00158"></a>00158         <span class="keywordflow">return</span> count;
+<a name="l00159"></a>00159 fail:
+<a name="l00160"></a>00160         <span class="keywordflow">return</span> -1;
+<a name="l00161"></a>00161 }
+<a name="l00162"></a>00162 
+<a name="l00163"></a>00163 
+<a name="l00181"></a>00181 <span class="keywordtype">int</span>
+<a name="l00182"></a>00182 usb_gadget_get_string (<span class="keyword">struct</span> usb_gadget_strings *table, <span class="keywordtype">int</span> <span class="keywordtype">id</span>, u8 *buf)
+<a name="l00183"></a>00183 {
+<a name="l00184"></a>00184         <span class="keyword">struct </span>usb_string       *s;
+<a name="l00185"></a>00185         <span class="keywordtype">int</span>                     len;
+<a name="l00186"></a>00186 
+<a name="l00187"></a>00187         <span class="comment">/* descriptor 0 has the language id */</span>
+<a name="l00188"></a>00188         <span class="keywordflow">if</span> (<span class="keywordtype">id</span> == 0) {
+<a name="l00189"></a>00189                 buf [0] = 4;
+<a name="l00190"></a>00190                 buf [1] = USB_DT_STRING;
+<a name="l00191"></a>00191                 buf [2] = (u8) table-&gt;language;
+<a name="l00192"></a>00192                 buf [3] = (u8) (table-&gt;language &gt;&gt; 8);
+<a name="l00193"></a>00193                 <span class="keywordflow">return</span> 4;
+<a name="l00194"></a>00194         }
+<a name="l00195"></a>00195         <span class="keywordflow">for</span> (s = table-&gt;strings; s &amp;&amp; s-&gt;s; s++)
+<a name="l00196"></a>00196                 <span class="keywordflow">if</span> (s-&gt;id == <span class="keywordtype">id</span>)
+<a name="l00197"></a>00197                         <span class="keywordflow">break</span>;
+<a name="l00198"></a>00198 
+<a name="l00199"></a>00199         <span class="comment">/* unrecognized: stall. */</span>
+<a name="l00200"></a>00200         <span class="keywordflow">if</span> (!s || !s-&gt;s)
+<a name="l00201"></a>00201                 <span class="keywordflow">return</span> -EINVAL;
+<a name="l00202"></a>00202 
+<a name="l00203"></a>00203         <span class="comment">/* string descriptors have length, tag, then UTF16-LE text */</span>
+<a name="l00204"></a>00204         len = <a class="code" href="dwc__otg__cfi_8h.html#7c9949b9e692a8360832aedfa1843657">min</a> ((size_t) 126, strlen (s-&gt;s));
+<a name="l00205"></a>00205         memset (buf + 2, 0, 2 * len);   <span class="comment">/* zero all the bytes */</span>
+<a name="l00206"></a>00206         len = utf8_to_utf16le(s-&gt;s, (u16 *)&amp;buf[2], len);
+<a name="l00207"></a>00207         <span class="keywordflow">if</span> (len &lt; 0)
+<a name="l00208"></a>00208                 <span class="keywordflow">return</span> -EINVAL;
+<a name="l00209"></a>00209         buf [0] = (len + 1) * 2;
+<a name="l00210"></a>00210         buf [1] = USB_DT_STRING;
+<a name="l00211"></a>00211         <span class="keywordflow">return</span> buf [0];
+<a name="l00212"></a>00212 }
+<a name="l00213"></a>00213 
+<a name="l00214"></a>00214 
+<a name="l00215"></a>00215 <span class="comment">/*-------------------------------------------------------------------------*/</span>
+<a name="l00216"></a>00216 <span class="comment">/*-------------------------------------------------------------------------*/</span>
+<a name="l00217"></a>00217 
+<a name="l00218"></a>00218 
+<a name="l00231"></a>00231 <span class="keywordtype">int</span>
+<a name="l00232"></a>00232 usb_descriptor_fillbuf(<span class="keywordtype">void</span> *buf, <span class="keywordtype">unsigned</span> buflen,
+<a name="l00233"></a>00233                 <span class="keyword">const</span> <span class="keyword">struct</span> usb_descriptor_header **src)
+<a name="l00234"></a>00234 {
+<a name="l00235"></a>00235         u8      *dest = buf;
+<a name="l00236"></a>00236 
+<a name="l00237"></a>00237         <span class="keywordflow">if</span> (!src)
+<a name="l00238"></a>00238                 <span class="keywordflow">return</span> -EINVAL;
+<a name="l00239"></a>00239 
+<a name="l00240"></a>00240         <span class="comment">/* fill buffer from src[] until null descriptor ptr */</span>
+<a name="l00241"></a>00241         <span class="keywordflow">for</span> (; 0 != *src; src++) {
+<a name="l00242"></a>00242                 <span class="keywordtype">unsigned</span>                len = (*src)-&gt;bLength;
+<a name="l00243"></a>00243 
+<a name="l00244"></a>00244                 if (len &gt; buflen)
+<a name="l00245"></a>00245                         <span class="keywordflow">return</span> -EINVAL;
+<a name="l00246"></a>00246                 memcpy(dest, *src, len);
+<a name="l00247"></a>00247                 buflen -= len;
+<a name="l00248"></a>00248                 dest += len;
+<a name="l00249"></a>00249         }
+<a name="l00250"></a>00250         <span class="keywordflow">return</span> dest - (u8 *)buf;
+<a name="l00251"></a>00251 }
+<a name="l00252"></a>00252 
+<a name="l00253"></a>00253 
+<a name="l00274"></a>00274 <span class="keywordtype">int</span> usb_gadget_config_buf(
+<a name="l00275"></a>00275         <span class="keyword">const</span> <span class="keyword">struct</span> usb_config_descriptor      *config,
+<a name="l00276"></a>00276         <span class="keywordtype">void</span>                                    *buf,
+<a name="l00277"></a>00277         <span class="keywordtype">unsigned</span>                                length,
+<a name="l00278"></a>00278         <span class="keyword">const</span> <span class="keyword">struct</span> usb_descriptor_header      **desc
+<a name="l00279"></a>00279 )
+<a name="l00280"></a>00280 {
+<a name="l00281"></a>00281         <span class="keyword">struct </span>usb_config_descriptor            *cp = buf;
+<a name="l00282"></a>00282         <span class="keywordtype">int</span>                                     len;
+<a name="l00283"></a>00283 
+<a name="l00284"></a>00284         <span class="comment">/* config descriptor first */</span>
+<a name="l00285"></a>00285         <span class="keywordflow">if</span> (length &lt; USB_DT_CONFIG_SIZE || !desc)
+<a name="l00286"></a>00286                 <span class="keywordflow">return</span> -EINVAL;
+<a name="l00287"></a>00287         *cp = *config; 
+<a name="l00288"></a>00288 
+<a name="l00289"></a>00289         <span class="comment">/* then interface/endpoint/class/vendor/... */</span>
+<a name="l00290"></a>00290         len = usb_descriptor_fillbuf(USB_DT_CONFIG_SIZE + (u8*)buf,
+<a name="l00291"></a>00291                         length - USB_DT_CONFIG_SIZE, desc);
+<a name="l00292"></a>00292         <span class="keywordflow">if</span> (len &lt; 0)
+<a name="l00293"></a>00293                 <span class="keywordflow">return</span> len;
+<a name="l00294"></a>00294         len += USB_DT_CONFIG_SIZE;
+<a name="l00295"></a>00295         <span class="keywordflow">if</span> (len &gt; 0xffff)
+<a name="l00296"></a>00296                 <span class="keywordflow">return</span> -EINVAL;
+<a name="l00297"></a>00297 
+<a name="l00298"></a>00298         <span class="comment">/* patch up the config descriptor */</span>
+<a name="l00299"></a>00299         cp-&gt;bLength = USB_DT_CONFIG_SIZE;
+<a name="l00300"></a>00300         cp-&gt;bDescriptorType = USB_DT_CONFIG;
+<a name="l00301"></a>00301         cp-&gt;wTotalLength = cpu_to_le16(len);
+<a name="l00302"></a>00302         cp-&gt;bmAttributes |= USB_CONFIG_ATT_ONE;
+<a name="l00303"></a>00303         <span class="keywordflow">return</span> len;
+<a name="l00304"></a>00304 }
+<a name="l00305"></a>00305 
+<a name="l00306"></a>00306 <span class="comment">/*-------------------------------------------------------------------------*/</span>
+<a name="l00307"></a>00307 <span class="comment">/*-------------------------------------------------------------------------*/</span>
+<a name="l00308"></a>00308 
+<a name="l00309"></a>00309 
+<a name="l00310"></a>00310 <span class="preprocessor">#define RBUF_LEN (1024*1024)</span>
+<a name="l00311"></a>00311 <span class="preprocessor"></span><span class="keyword">static</span> <span class="keywordtype">int</span> rbuf_start;
+<a name="l00312"></a>00312 <span class="keyword">static</span> <span class="keywordtype">int</span> rbuf_len;
+<a name="l00313"></a>00313 <span class="keyword">static</span> __u8 rbuf[RBUF_LEN];
+<a name="l00314"></a>00314 
+<a name="l00315"></a>00315 <span class="comment">/*-------------------------------------------------------------------------*/</span>
+<a name="l00316"></a>00316 
+<a name="l00317"></a>00317 <span class="preprocessor">#define DRIVER_VERSION          "St Patrick's Day 2004"</span>
+<a name="l00318"></a>00318 <span class="preprocessor"></span>
+<a name="l00319"></a>00319 <span class="keyword">static</span> <span class="keyword">const</span> <span class="keywordtype">char</span> shortname [] = <span class="stringliteral">"zero"</span>;
+<a name="l00320"></a>00320 <span class="keyword">static</span> <span class="keyword">const</span> <span class="keywordtype">char</span> longname [] = <span class="stringliteral">"YAMAHA YST-MS35D USB Speaker  "</span>;
+<a name="l00321"></a>00321 
+<a name="l00322"></a>00322 <span class="keyword">static</span> <span class="keyword">const</span> <span class="keywordtype">char</span> source_sink [] = <span class="stringliteral">"source and sink data"</span>;
+<a name="l00323"></a>00323 <span class="keyword">static</span> <span class="keyword">const</span> <span class="keywordtype">char</span> loopback [] = <span class="stringliteral">"loop input to output"</span>;
+<a name="l00324"></a>00324 
+<a name="l00325"></a>00325 <span class="comment">/*-------------------------------------------------------------------------*/</span>
+<a name="l00326"></a>00326 
+<a name="l00327"></a>00327 <span class="comment">/*</span>
+<a name="l00328"></a>00328 <span class="comment"> * driver assumes self-powered hardware, and</span>
+<a name="l00329"></a>00329 <span class="comment"> * has no way for users to trigger remote wakeup.</span>
+<a name="l00330"></a>00330 <span class="comment"> *</span>
+<a name="l00331"></a>00331 <span class="comment"> * this version autoconfigures as much as possible,</span>
+<a name="l00332"></a>00332 <span class="comment"> * which is reasonable for most "bulk-only" drivers.</span>
+<a name="l00333"></a>00333 <span class="comment"> */</span>
+<a name="l00334"></a>00334 <span class="keyword">static</span> <span class="keyword">const</span> <span class="keywordtype">char</span> *EP_IN_NAME;          <span class="comment">/* source */</span>
+<a name="l00335"></a>00335 <span class="keyword">static</span> <span class="keyword">const</span> <span class="keywordtype">char</span> *EP_OUT_NAME;         <span class="comment">/* sink */</span>
+<a name="l00336"></a>00336 
+<a name="l00337"></a>00337 <span class="comment">/*-------------------------------------------------------------------------*/</span>
+<a name="l00338"></a>00338 
+<a name="l00339"></a>00339 <span class="comment">/* big enough to hold our biggest descriptor */</span>
+<a name="l00340"></a>00340 <span class="preprocessor">#define USB_BUFSIZ      512</span>
+<a name="l00341"></a>00341 <span class="preprocessor"></span>
+<a name="l00342"></a><a class="code" href="structzero__dev.html">00342</a> <span class="keyword">struct </span><a class="code" href="structzero__dev.html">zero_dev</a> {
+<a name="l00343"></a><a class="code" href="structzero__dev.html#712568d4b6a481845034ac6d87c0547d">00343</a>         spinlock_t              <a class="code" href="structzero__dev.html#712568d4b6a481845034ac6d87c0547d">lock</a>;
+<a name="l00344"></a><a class="code" href="structzero__dev.html#e0d019d6177afd1efa101aed63f1a174">00344</a>         <span class="keyword">struct </span>usb_gadget       *<a class="code" href="structzero__dev.html#e0d019d6177afd1efa101aed63f1a174">gadget</a>;
+<a name="l00345"></a><a class="code" href="structzero__dev.html#7dad5245ef3701a5521638e2499ebfe9">00345</a>         <span class="keyword">struct </span>usb_request      *<a class="code" href="structzero__dev.html#7dad5245ef3701a5521638e2499ebfe9">req</a>;           <span class="comment">/* for control responses */</span>
+<a name="l00346"></a>00346 
+<a name="l00347"></a>00347         <span class="comment">/* when configured, we have one of two configs:</span>
+<a name="l00348"></a>00348 <span class="comment">         * - source data (in to host) and sink it (out from host)</span>
+<a name="l00349"></a>00349 <span class="comment">         * - or loop it back (out from host back in to host)</span>
+<a name="l00350"></a>00350 <span class="comment">         */</span>
+<a name="l00351"></a><a class="code" href="structzero__dev.html#2481a8df9867ab54361cf4ffc7267484">00351</a>         u8                      config;
+<a name="l00352"></a><a class="code" href="structzero__dev.html#28a2079d55de6ac606cc69b79882223f">00352</a>         <span class="keyword">struct </span>usb_ep           *<a class="code" href="structzero__dev.html#8b35a5b8ce497d55d7369a4635d891df">in_ep</a>, *<a class="code" href="structzero__dev.html#28a2079d55de6ac606cc69b79882223f">out_ep</a>;
+<a name="l00353"></a>00353 
+<a name="l00354"></a>00354         <span class="comment">/* autoresume timer */</span>
+<a name="l00355"></a><a class="code" href="structzero__dev.html#5fcacdfb9a6b069c866d44d66dd566a4">00355</a>         <span class="keyword">struct </span>timer_list       resume;
+<a name="l00356"></a>00356 };
+<a name="l00357"></a>00357 
+<a name="l00358"></a>00358 <span class="preprocessor">#define xprintk(d,level,fmt,args...) \</span>
+<a name="l00359"></a>00359 <span class="preprocessor">        dev_printk(level , &amp;(d)-&gt;gadget-&gt;dev , fmt , ## args)</span>
+<a name="l00360"></a>00360 <span class="preprocessor"></span>
+<a name="l00361"></a>00361 <span class="preprocessor">#ifdef DEBUG</span>
+<a name="l00362"></a>00362 <span class="preprocessor"></span><span class="preprocessor">#define DBG(dev,fmt,args...) \</span>
+<a name="l00363"></a>00363 <span class="preprocessor">        xprintk(dev , KERN_DEBUG , fmt , ## args)</span>
+<a name="l00364"></a>00364 <span class="preprocessor"></span><span class="preprocessor">#else</span>
+<a name="l00365"></a>00365 <span class="preprocessor"></span><span class="preprocessor">#define DBG(dev,fmt,args...) \</span>
+<a name="l00366"></a>00366 <span class="preprocessor">        do { } while (0)</span>
+<a name="l00367"></a>00367 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/* DEBUG */</span>
+<a name="l00368"></a>00368 
+<a name="l00369"></a>00369 <span class="preprocessor">#ifdef VERBOSE</span>
+<a name="l00370"></a>00370 <span class="preprocessor"></span><span class="preprocessor">#define VDBG    DBG</span>
+<a name="l00371"></a>00371 <span class="preprocessor"></span><span class="preprocessor">#else</span>
+<a name="l00372"></a>00372 <span class="preprocessor"></span><span class="preprocessor">#define VDBG(dev,fmt,args...) \</span>
+<a name="l00373"></a>00373 <span class="preprocessor">        do { } while (0)</span>
+<a name="l00374"></a>00374 <span class="preprocessor"></span><span class="preprocessor">#endif </span><span class="comment">/* VERBOSE */</span>
+<a name="l00375"></a>00375 
+<a name="l00376"></a>00376 <span class="preprocessor">#define ERROR(dev,fmt,args...) \</span>
+<a name="l00377"></a>00377 <span class="preprocessor">        xprintk(dev , KERN_ERR , fmt , ## args)</span>
+<a name="l00378"></a>00378 <span class="preprocessor"></span><span class="preprocessor">#define WARN(dev,fmt,args...) \</span>
+<a name="l00379"></a>00379 <span class="preprocessor">        xprintk(dev , KERN_WARNING , fmt , ## args)</span>
+<a name="l00380"></a>00380 <span class="preprocessor"></span><span class="preprocessor">#define INFO(dev,fmt,args...) \</span>
+<a name="l00381"></a>00381 <span class="preprocessor">        xprintk(dev , KERN_INFO , fmt , ## args)</span>
+<a name="l00382"></a>00382 <span class="preprocessor"></span>
+<a name="l00383"></a>00383 <span class="comment">/*-------------------------------------------------------------------------*/</span>
+<a name="l00384"></a>00384 
+<a name="l00385"></a>00385 <span class="keyword">static</span> <span class="keywordtype">unsigned</span> buflen = 4096;
+<a name="l00386"></a>00386 <span class="keyword">static</span> <span class="keywordtype">unsigned</span> qlen = 32;
+<a name="l00387"></a>00387 <span class="keyword">static</span> <span class="keywordtype">unsigned</span> pattern = 0;
+<a name="l00388"></a>00388 
+<a name="l00389"></a>00389 module_param (buflen, uint, S_IRUGO|<a class="code" href="dwc__otg__attr_8c.html#ac2308832629daf78cb9dd123551cd8a">S_IWUSR</a>);
+<a name="l00390"></a>00390 module_param (qlen, uint, S_IRUGO|<a class="code" href="dwc__otg__attr_8c.html#ac2308832629daf78cb9dd123551cd8a">S_IWUSR</a>);
+<a name="l00391"></a>00391 module_param (pattern, uint, S_IRUGO|<a class="code" href="dwc__otg__attr_8c.html#ac2308832629daf78cb9dd123551cd8a">S_IWUSR</a>);
+<a name="l00392"></a>00392 
+<a name="l00393"></a>00393 <span class="comment">/*</span>
+<a name="l00394"></a>00394 <span class="comment"> * if it's nonzero, autoresume says how many seconds to wait</span>
+<a name="l00395"></a>00395 <span class="comment"> * before trying to wake up the host after suspend.</span>
+<a name="l00396"></a>00396 <span class="comment"> */</span>
+<a name="l00397"></a>00397 <span class="keyword">static</span> <span class="keywordtype">unsigned</span> autoresume = 0;
+<a name="l00398"></a>00398 module_param (autoresume, uint, 0);
+<a name="l00399"></a>00399 
+<a name="l00400"></a>00400 <span class="comment">/*</span>
+<a name="l00401"></a>00401 <span class="comment"> * Normally the "loopback" configuration is second (index 1) so</span>
+<a name="l00402"></a>00402 <span class="comment"> * it's not the default.  Here's where to change that order, to</span>
+<a name="l00403"></a>00403 <span class="comment"> * work better with hosts where config changes are problematic.</span>
+<a name="l00404"></a>00404 <span class="comment"> * Or controllers (like superh) that only support one config.</span>
+<a name="l00405"></a>00405 <span class="comment"> */</span>
+<a name="l00406"></a>00406 <span class="keyword">static</span> <span class="keywordtype">int</span> loopdefault = 0;
+<a name="l00407"></a>00407 
+<a name="l00408"></a>00408 module_param (loopdefault, <span class="keywordtype">bool</span>, S_IRUGO|<a class="code" href="dwc__otg__attr_8c.html#ac2308832629daf78cb9dd123551cd8a">S_IWUSR</a>);
+<a name="l00409"></a>00409 
+<a name="l00410"></a>00410 <span class="comment">/*-------------------------------------------------------------------------*/</span>
+<a name="l00411"></a>00411 
+<a name="l00412"></a>00412 <span class="comment">/* Thanks to NetChip Technologies for donating this product ID.</span>
+<a name="l00413"></a>00413 <span class="comment"> *</span>
+<a name="l00414"></a>00414 <span class="comment"> * DO NOT REUSE THESE IDs with a protocol-incompatible driver!!  Ever!!</span>
+<a name="l00415"></a>00415 <span class="comment"> * Instead:  allocate your own, using normal USB-IF procedures.</span>
+<a name="l00416"></a>00416 <span class="comment"> */</span>
+<a name="l00417"></a>00417 <span class="preprocessor">#ifndef CONFIG_USB_ZERO_HNPTEST</span>
+<a name="l00418"></a>00418 <span class="preprocessor"></span><span class="preprocessor">#define DRIVER_VENDOR_NUM       0x0525          </span><span class="comment">/* NetChip */</span>
+<a name="l00419"></a>00419 <span class="preprocessor">#define DRIVER_PRODUCT_NUM      0xa4a0          </span><span class="comment">/* Linux-USB "Gadget Zero" */</span>
+<a name="l00420"></a>00420 <span class="preprocessor">#else</span>
+<a name="l00421"></a>00421 <span class="preprocessor"></span><span class="preprocessor">#define DRIVER_VENDOR_NUM       0x1a0a          </span><span class="comment">/* OTG test device IDs */</span>
+<a name="l00422"></a>00422 <span class="preprocessor">#define DRIVER_PRODUCT_NUM      0xbadd</span>
+<a name="l00423"></a>00423 <span class="preprocessor"></span><span class="preprocessor">#endif</span>
+<a name="l00424"></a>00424 <span class="preprocessor"></span>
+<a name="l00425"></a>00425 <span class="comment">/*-------------------------------------------------------------------------*/</span>
+<a name="l00426"></a>00426 
+<a name="l00427"></a>00427 <span class="comment">/*</span>
+<a name="l00428"></a>00428 <span class="comment"> * DESCRIPTORS ... most are static, but strings and (full)</span>
+<a name="l00429"></a>00429 <span class="comment"> * configuration descriptors are built on demand.</span>
+<a name="l00430"></a>00430 <span class="comment"> */</span>
+<a name="l00431"></a>00431 
+<a name="l00432"></a>00432 <span class="comment">/*</span>
+<a name="l00433"></a>00433 <span class="comment">#define STRING_MANUFACTURER             25</span>
+<a name="l00434"></a>00434 <span class="comment">#define STRING_PRODUCT                  42</span>
+<a name="l00435"></a>00435 <span class="comment">#define STRING_SERIAL                   101</span>
+<a name="l00436"></a>00436 <span class="comment">*/</span>
+<a name="l00437"></a>00437 <span class="preprocessor">#define STRING_MANUFACTURER             1</span>
+<a name="l00438"></a>00438 <span class="preprocessor"></span><span class="preprocessor">#define STRING_PRODUCT                  2</span>
+<a name="l00439"></a>00439 <span class="preprocessor"></span><span class="preprocessor">#define STRING_SERIAL                   3</span>
+<a name="l00440"></a>00440 <span class="preprocessor"></span>
+<a name="l00441"></a>00441 <span class="preprocessor">#define STRING_SOURCE_SINK              250</span>
+<a name="l00442"></a>00442 <span class="preprocessor"></span><span class="preprocessor">#define STRING_LOOPBACK                 251</span>
+<a name="l00443"></a>00443 <span class="preprocessor"></span>
+<a name="l00444"></a>00444 <span class="comment">/*</span>
+<a name="l00445"></a>00445 <span class="comment"> * This device advertises two configurations; these numbers work</span>
+<a name="l00446"></a>00446 <span class="comment"> * on a pxa250 as well as more flexible hardware.</span>
+<a name="l00447"></a>00447 <span class="comment"> */</span>
+<a name="l00448"></a>00448 <span class="preprocessor">#define CONFIG_SOURCE_SINK      3</span>
+<a name="l00449"></a>00449 <span class="preprocessor"></span><span class="preprocessor">#define CONFIG_LOOPBACK         2</span>
+<a name="l00450"></a>00450 <span class="preprocessor"></span>
+<a name="l00451"></a>00451 <span class="comment">/*</span>
+<a name="l00452"></a>00452 <span class="comment">static struct usb_device_descriptor</span>
+<a name="l00453"></a>00453 <span class="comment">device_desc = {</span>
+<a name="l00454"></a>00454 <span class="comment">        .bLength =              sizeof device_desc,</span>
+<a name="l00455"></a>00455 <span class="comment">        .bDescriptorType =      USB_DT_DEVICE,</span>
+<a name="l00456"></a>00456 <span class="comment"></span>
+<a name="l00457"></a>00457 <span class="comment">        .bcdUSB =               __constant_cpu_to_le16 (0x0200),</span>
+<a name="l00458"></a>00458 <span class="comment">        .bDeviceClass =         USB_CLASS_VENDOR_SPEC,</span>
+<a name="l00459"></a>00459 <span class="comment"></span>
+<a name="l00460"></a>00460 <span class="comment">        .idVendor =             __constant_cpu_to_le16 (DRIVER_VENDOR_NUM),</span>
+<a name="l00461"></a>00461 <span class="comment">        .idProduct =            __constant_cpu_to_le16 (DRIVER_PRODUCT_NUM),</span>
+<a name="l00462"></a>00462 <span class="comment">        .iManufacturer =        STRING_MANUFACTURER,</span>
+<a name="l00463"></a>00463 <span class="comment">        .iProduct =             STRING_PRODUCT,</span>
+<a name="l00464"></a>00464 <span class="comment">        .iSerialNumber =        STRING_SERIAL,</span>
+<a name="l00465"></a>00465 <span class="comment">        .bNumConfigurations =   2,</span>
+<a name="l00466"></a>00466 <span class="comment">};</span>
+<a name="l00467"></a>00467 <span class="comment">*/</span>
+<a name="l00468"></a>00468 <span class="keyword">static</span> <span class="keyword">struct </span>usb_device_descriptor
+<a name="l00469"></a>00469 device_desc = {
+<a name="l00470"></a>00470         .bLength =              <span class="keyword">sizeof</span> device_desc,
+<a name="l00471"></a>00471         .bDescriptorType =      USB_DT_DEVICE,
+<a name="l00472"></a>00472         .bcdUSB =               __constant_cpu_to_le16 (0x0100),
+<a name="l00473"></a>00473         .bDeviceClass =         USB_CLASS_PER_INTERFACE,
+<a name="l00474"></a>00474         .bDeviceSubClass =      0,
+<a name="l00475"></a>00475         .bDeviceProtocol =      0,
+<a name="l00476"></a>00476         .bMaxPacketSize0 =      64,
+<a name="l00477"></a>00477         .bcdDevice =            __constant_cpu_to_le16 (0x0100),
+<a name="l00478"></a>00478         .idVendor =             __constant_cpu_to_le16 (0x0499),
+<a name="l00479"></a>00479         .idProduct =            __constant_cpu_to_le16 (0x3002),
+<a name="l00480"></a>00480         .iManufacturer =        STRING_MANUFACTURER,
+<a name="l00481"></a>00481         .iProduct =             STRING_PRODUCT,
+<a name="l00482"></a>00482         .iSerialNumber =        STRING_SERIAL,
+<a name="l00483"></a>00483         .bNumConfigurations =   1,
+<a name="l00484"></a>00484 };
+<a name="l00485"></a>00485 
+<a name="l00486"></a>00486 <span class="keyword">static</span> <span class="keyword">struct </span>usb_config_descriptor
+<a name="l00487"></a>00487 z_config = {
+<a name="l00488"></a>00488         .bLength =              <span class="keyword">sizeof</span> z_config,
+<a name="l00489"></a>00489         .bDescriptorType =      USB_DT_CONFIG,
+<a name="l00490"></a>00490 
+<a name="l00491"></a>00491         <span class="comment">/* compute wTotalLength on the fly */</span>
+<a name="l00492"></a>00492         .bNumInterfaces =       2,
+<a name="l00493"></a>00493         .bConfigurationValue =  1,
+<a name="l00494"></a>00494         .iConfiguration =       0,
+<a name="l00495"></a>00495         .bmAttributes =         0x40,
+<a name="l00496"></a>00496         .bMaxPower =            0,      <span class="comment">/* self-powered */</span>
+<a name="l00497"></a>00497 };
+<a name="l00498"></a>00498 
+<a name="l00499"></a>00499 
+<a name="l00500"></a>00500 <span class="keyword">static</span> <span class="keyword">struct </span>usb_otg_descriptor
+<a name="l00501"></a>00501 otg_descriptor = {
+<a name="l00502"></a>00502         .bLength =              <span class="keyword">sizeof</span> otg_descriptor,
+<a name="l00503"></a>00503         .bDescriptorType =      USB_DT_OTG,
+<a name="l00504"></a>00504 
+<a name="l00505"></a>00505         .bmAttributes =         USB_OTG_SRP,
+<a name="l00506"></a>00506 };
+<a name="l00507"></a>00507 
+<a name="l00508"></a>00508 <span class="comment">/* one interface in each configuration */</span>
+<a name="l00509"></a>00509 <span class="preprocessor">#ifdef  CONFIG_USB_GADGET_DUALSPEED</span>
+<a name="l00510"></a>00510 <span class="preprocessor"></span>
+<a name="l00511"></a>00511 <span class="comment">/*</span>
+<a name="l00512"></a>00512 <span class="comment"> * usb 2.0 devices need to expose both high speed and full speed</span>
+<a name="l00513"></a>00513 <span class="comment"> * descriptors, unless they only run at full speed.</span>
+<a name="l00514"></a>00514 <span class="comment"> *</span>
+<a name="l00515"></a>00515 <span class="comment"> * that means alternate endpoint descriptors (bigger packets)</span>
+<a name="l00516"></a>00516 <span class="comment"> * and a "device qualifier" ... plus more construction options</span>
+<a name="l00517"></a>00517 <span class="comment"> * for the config descriptor.</span>
+<a name="l00518"></a>00518 <span class="comment"> */</span>
+<a name="l00519"></a>00519 
+<a name="l00520"></a>00520 <span class="keyword">static</span> <span class="keyword">struct </span>usb_qualifier_descriptor
+<a name="l00521"></a>00521 dev_qualifier = {
+<a name="l00522"></a>00522         .bLength =              <span class="keyword">sizeof</span> dev_qualifier,
+<a name="l00523"></a>00523         .bDescriptorType =      USB_DT_DEVICE_QUALIFIER,
+<a name="l00524"></a>00524 
+<a name="l00525"></a>00525         .bcdUSB =               __constant_cpu_to_le16 (0x0200),
+<a name="l00526"></a>00526         .bDeviceClass =         USB_CLASS_VENDOR_SPEC,
+<a name="l00527"></a>00527 
+<a name="l00528"></a>00528         .bNumConfigurations =   2,
+<a name="l00529"></a>00529 };
+<a name="l00530"></a>00530 
+<a name="l00531"></a>00531 
+<a name="l00532"></a>00532 <span class="keyword">struct </span>usb_cs_as_general_descriptor {
+<a name="l00533"></a>00533         __u8  bLength;
+<a name="l00534"></a>00534         __u8  bDescriptorType;
+<a name="l00535"></a>00535 
+<a name="l00536"></a>00536         __u8  bDescriptorSubType;
+<a name="l00537"></a>00537         __u8  bTerminalLink;
+<a name="l00538"></a>00538         __u8  bDelay;
+<a name="l00539"></a>00539         __u16  wFormatTag;
+<a name="l00540"></a>00540 } __attribute__ ((<a class="code" href="dwc__otg__cfi_8h.html#1c517724be71d3c12952486ba172c0b6">packed</a>));
+<a name="l00541"></a>00541 
+<a name="l00542"></a>00542 <span class="keyword">struct </span>usb_cs_as_format_descriptor {
+<a name="l00543"></a>00543         __u8  bLength;
+<a name="l00544"></a>00544         __u8  bDescriptorType;
+<a name="l00545"></a>00545 
+<a name="l00546"></a>00546         __u8  bDescriptorSubType;
+<a name="l00547"></a>00547         __u8  bFormatType;
+<a name="l00548"></a>00548         __u8  bNrChannels;
+<a name="l00549"></a>00549         __u8  bSubframeSize;
+<a name="l00550"></a>00550         __u8  bBitResolution;
+<a name="l00551"></a>00551         __u8  bSamfreqType;
+<a name="l00552"></a>00552         __u8  tLowerSamFreq[3];
+<a name="l00553"></a>00553         __u8  tUpperSamFreq[3];
+<a name="l00554"></a>00554 } __attribute__ ((<a class="code" href="dwc__otg__cfi_8h.html#1c517724be71d3c12952486ba172c0b6">packed</a>));
+<a name="l00555"></a>00555 
+<a name="l00556"></a>00556 <span class="keyword">static</span> <span class="keyword">const</span> <span class="keyword">struct </span>usb_interface_descriptor
+<a name="l00557"></a>00557 z_audio_control_if_desc = {
+<a name="l00558"></a>00558         .bLength =              <span class="keyword">sizeof</span> z_audio_control_if_desc,
+<a name="l00559"></a>00559         .bDescriptorType =      USB_DT_INTERFACE,
+<a name="l00560"></a>00560         .bInterfaceNumber = 0,
+<a name="l00561"></a>00561         .bAlternateSetting = 0,
+<a name="l00562"></a>00562         .bNumEndpoints = 0,
+<a name="l00563"></a>00563         .bInterfaceClass = USB_CLASS_AUDIO,
+<a name="l00564"></a>00564         .bInterfaceSubClass = 0x1,
+<a name="l00565"></a>00565         .bInterfaceProtocol = 0,
+<a name="l00566"></a>00566         .iInterface = 0,
+<a name="l00567"></a>00567 };
+<a name="l00568"></a>00568 
+<a name="l00569"></a>00569 <span class="keyword">static</span> <span class="keyword">const</span> <span class="keyword">struct </span>usb_interface_descriptor
+<a name="l00570"></a>00570 z_audio_if_desc = {
+<a name="l00571"></a>00571         .bLength =              <span class="keyword">sizeof</span> z_audio_if_desc,
+<a name="l00572"></a>00572         .bDescriptorType =      USB_DT_INTERFACE,
+<a name="l00573"></a>00573         .bInterfaceNumber = 1,
+<a name="l00574"></a>00574         .bAlternateSetting = 0,
+<a name="l00575"></a>00575         .bNumEndpoints = 0,
+<a name="l00576"></a>00576         .bInterfaceClass = USB_CLASS_AUDIO,
+<a name="l00577"></a>00577         .bInterfaceSubClass = 0x2,
+<a name="l00578"></a>00578         .bInterfaceProtocol = 0,
+<a name="l00579"></a>00579         .iInterface = 0,
+<a name="l00580"></a>00580 };
+<a name="l00581"></a>00581 
+<a name="l00582"></a>00582 <span class="keyword">static</span> <span class="keyword">const</span> <span class="keyword">struct </span>usb_interface_descriptor
+<a name="l00583"></a>00583 z_audio_if_desc2 = {
+<a name="l00584"></a>00584         .bLength =              <span class="keyword">sizeof</span> z_audio_if_desc,
+<a name="l00585"></a>00585         .bDescriptorType =      USB_DT_INTERFACE,
+<a name="l00586"></a>00586         .bInterfaceNumber = 1,
+<a name="l00587"></a>00587         .bAlternateSetting = 1,
+<a name="l00588"></a>00588         .bNumEndpoints = 1,
+<a name="l00589"></a>00589         .bInterfaceClass = USB_CLASS_AUDIO,
+<a name="l00590"></a>00590         .bInterfaceSubClass = 0x2,
+<a name="l00591"></a>00591         .bInterfaceProtocol = 0,
+<a name="l00592"></a>00592         .iInterface = 0,
+<a name="l00593"></a>00593 };
+<a name="l00594"></a>00594 
+<a name="l00595"></a>00595 <span class="keyword">static</span> <span class="keyword">const</span> <span class="keyword">struct </span>usb_cs_as_general_descriptor
+<a name="l00596"></a>00596 z_audio_cs_as_if_desc = {
+<a name="l00597"></a>00597         .bLength = 7,
+<a name="l00598"></a>00598         .bDescriptorType = 0x24,
+<a name="l00599"></a>00599         
+<a name="l00600"></a>00600         .bDescriptorSubType = 0x01,
+<a name="l00601"></a>00601         .bTerminalLink = 0x01,
+<a name="l00602"></a>00602         .bDelay = 0x0,
+<a name="l00603"></a>00603         .wFormatTag = __constant_cpu_to_le16 (0x0001)
+<a name="l00604"></a>00604 };
+<a name="l00605"></a>00605 
+<a name="l00606"></a>00606 
+<a name="l00607"></a>00607 <span class="keyword">static</span> <span class="keyword">const</span> <span class="keyword">struct </span>usb_cs_as_format_descriptor 
+<a name="l00608"></a>00608 z_audio_cs_as_format_desc = {
+<a name="l00609"></a>00609         .bLength = 0xe,
+<a name="l00610"></a>00610         .bDescriptorType = 0x24,
+<a name="l00611"></a>00611         
+<a name="l00612"></a>00612         .bDescriptorSubType = 2,
+<a name="l00613"></a>00613         .bFormatType = 1,
+<a name="l00614"></a>00614         .bNrChannels = 1,
+<a name="l00615"></a>00615         .bSubframeSize = 1,
+<a name="l00616"></a>00616         .bBitResolution = 8,
+<a name="l00617"></a>00617         .bSamfreqType = 0,
+<a name="l00618"></a>00618         .tLowerSamFreq = {0x7e, 0x13, 0x00},
+<a name="l00619"></a>00619         .tUpperSamFreq = {0xe2, 0xd6, 0x00},
+<a name="l00620"></a>00620 };
+<a name="l00621"></a>00621 
+<a name="l00622"></a>00622 <span class="keyword">static</span> <span class="keyword">const</span> <span class="keyword">struct </span>usb_endpoint_descriptor 
+<a name="l00623"></a>00623 z_iso_ep = {
+<a name="l00624"></a>00624         .bLength = 0x09,
+<a name="l00625"></a>00625         .bDescriptorType = 0x05,
+<a name="l00626"></a>00626         .bEndpointAddress = 0x04,
+<a name="l00627"></a>00627         .bmAttributes = 0x09,
+<a name="l00628"></a>00628         .wMaxPacketSize = 0x0038,
+<a name="l00629"></a>00629         .bInterval = 0x01,
+<a name="l00630"></a>00630         .bRefresh = 0x00,
+<a name="l00631"></a>00631         .bSynchAddress = 0x00,  
+<a name="l00632"></a>00632 };
+<a name="l00633"></a>00633 
+<a name="l00634"></a>00634 <span class="keyword">static</span> <span class="keywordtype">char</span> z_iso_ep2[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
+<a name="l00635"></a>00635 
+<a name="l00636"></a>00636 <span class="comment">// 9 bytes</span>
+<a name="l00637"></a>00637 <span class="keyword">static</span> <span class="keywordtype">char</span> z_ac_interface_header_desc[] = 
+<a name="l00638"></a>00638 { 0x09, 0x24, 0x01, 0x00, 0x01, 0x2b, 0x00, 0x01, 0x01 };
+<a name="l00639"></a>00639 
+<a name="l00640"></a>00640 <span class="comment">// 12 bytes</span>
+<a name="l00641"></a>00641 <span class="keyword">static</span> <span class="keywordtype">char</span> z_0[] = {0x0c, 0x24, 0x02, 0x01, 0x01, 0x01, 0x00, 0x02, 
+<a name="l00642"></a>00642                      0x03, 0x00, 0x00, 0x00};
+<a name="l00643"></a>00643 <span class="comment">// 13 bytes</span>
+<a name="l00644"></a>00644 <span class="keyword">static</span> <span class="keywordtype">char</span> z_1[] = {0x0d, 0x24, 0x06, 0x02, 0x01, 0x02, 0x15, 0x00, 
+<a name="l00645"></a>00645                      0x02, 0x00, 0x02, 0x00, 0x00};
+<a name="l00646"></a>00646 <span class="comment">// 9 bytes</span>
+<a name="l00647"></a>00647 <span class="keyword">static</span> <span class="keywordtype">char</span> z_2[] = {0x09, 0x24, 0x03, 0x03, 0x01, 0x03, 0x00, 0x02, 
+<a name="l00648"></a>00648                      0x00};
+<a name="l00649"></a>00649 
+<a name="l00650"></a>00650 <span class="keyword">static</span> <span class="keywordtype">char</span> za_0[] = {0x09, 0x04, 0x01, 0x02, 0x01, 0x01, 0x02, 0x00, 
+<a name="l00651"></a>00651                       0x00};
+<a name="l00652"></a>00652 
+<a name="l00653"></a>00653 <span class="keyword">static</span> <span class="keywordtype">char</span> za_1[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
+<a name="l00654"></a>00654 
+<a name="l00655"></a>00655 <span class="keyword">static</span> <span class="keywordtype">char</span> za_2[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x01, 0x08, 0x00, 
+<a name="l00656"></a>00656                       0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
+<a name="l00657"></a>00657 
+<a name="l00658"></a>00658 <span class="keyword">static</span> <span class="keywordtype">char</span> za_3[] = {0x09, 0x05, 0x04, 0x09, 0x70, 0x00, 0x01, 0x00,
+<a name="l00659"></a>00659                       0x00};
+<a name="l00660"></a>00660 
+<a name="l00661"></a>00661 <span class="keyword">static</span> <span class="keywordtype">char</span> za_4[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
+<a name="l00662"></a>00662 
+<a name="l00663"></a>00663 <span class="keyword">static</span> <span class="keywordtype">char</span> za_5[] = {0x09, 0x04, 0x01, 0x03, 0x01, 0x01, 0x02, 0x00,
+<a name="l00664"></a>00664                       0x00};
+<a name="l00665"></a>00665 
+<a name="l00666"></a>00666 <span class="keyword">static</span> <span class="keywordtype">char</span> za_6[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
+<a name="l00667"></a>00667 
+<a name="l00668"></a>00668 <span class="keyword">static</span> <span class="keywordtype">char</span> za_7[] = {0x0e, 0x24, 0x02, 0x01, 0x01, 0x02, 0x10, 0x00,
+<a name="l00669"></a>00669                       0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
+<a name="l00670"></a>00670 
+<a name="l00671"></a>00671 <span class="keyword">static</span> <span class="keywordtype">char</span> za_8[] = {0x09, 0x05, 0x04, 0x09, 0x70, 0x00, 0x01, 0x00,
+<a name="l00672"></a>00672                       0x00};
+<a name="l00673"></a>00673 
+<a name="l00674"></a>00674 <span class="keyword">static</span> <span class="keywordtype">char</span> za_9[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
+<a name="l00675"></a>00675 
+<a name="l00676"></a>00676 <span class="keyword">static</span> <span class="keywordtype">char</span> za_10[] = {0x09, 0x04, 0x01, 0x04, 0x01, 0x01, 0x02, 0x00,
+<a name="l00677"></a>00677                        0x00};
+<a name="l00678"></a>00678 
+<a name="l00679"></a>00679 <span class="keyword">static</span> <span class="keywordtype">char</span> za_11[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
+<a name="l00680"></a>00680 
+<a name="l00681"></a>00681 <span class="keyword">static</span> <span class="keywordtype">char</span> za_12[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x02, 0x10, 0x00,
+<a name="l00682"></a>00682                        0x73, 0x13, 0x00, 0xe2, 0xd6, 0x00};
+<a name="l00683"></a>00683 
+<a name="l00684"></a>00684 <span class="keyword">static</span> <span class="keywordtype">char</span> za_13[] = {0x09, 0x05, 0x04, 0x09, 0xe0, 0x00, 0x01, 0x00,
+<a name="l00685"></a>00685                        0x00};
+<a name="l00686"></a>00686 
+<a name="l00687"></a>00687 <span class="keyword">static</span> <span class="keywordtype">char</span> za_14[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
+<a name="l00688"></a>00688 
+<a name="l00689"></a>00689 <span class="keyword">static</span> <span class="keywordtype">char</span> za_15[] = {0x09, 0x04, 0x01, 0x05, 0x01, 0x01, 0x02, 0x00, 
+<a name="l00690"></a>00690                        0x00};
+<a name="l00691"></a>00691 
+<a name="l00692"></a>00692 <span class="keyword">static</span> <span class="keywordtype">char</span> za_16[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
+<a name="l00693"></a>00693 
+<a name="l00694"></a>00694 <span class="keyword">static</span> <span class="keywordtype">char</span> za_17[] = {0x0e, 0x24, 0x02, 0x01, 0x01, 0x03, 0x14, 0x00, 
+<a name="l00695"></a>00695                        0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
+<a name="l00696"></a>00696 
+<a name="l00697"></a>00697 <span class="keyword">static</span> <span class="keywordtype">char</span> za_18[] = {0x09, 0x05, 0x04, 0x09, 0xa8, 0x00, 0x01, 0x00,
+<a name="l00698"></a>00698                        0x00};
+<a name="l00699"></a>00699 
+<a name="l00700"></a>00700 <span class="keyword">static</span> <span class="keywordtype">char</span> za_19[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
+<a name="l00701"></a>00701 
+<a name="l00702"></a>00702 <span class="keyword">static</span> <span class="keywordtype">char</span> za_20[] = {0x09, 0x04, 0x01, 0x06, 0x01, 0x01, 0x02, 0x00,
+<a name="l00703"></a>00703                        0x00};
+<a name="l00704"></a>00704 
+<a name="l00705"></a>00705 <span class="keyword">static</span> <span class="keywordtype">char</span> za_21[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
+<a name="l00706"></a>00706 
+<a name="l00707"></a>00707 <span class="keyword">static</span> <span class="keywordtype">char</span> za_22[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x03, 0x14, 0x00, 
+<a name="l00708"></a>00708                        0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
+<a name="l00709"></a>00709 
+<a name="l00710"></a>00710 <span class="keyword">static</span> <span class="keywordtype">char</span> za_23[] = {0x09, 0x05, 0x04, 0x09, 0x50, 0x01, 0x01, 0x00,
+<a name="l00711"></a>00711                        0x00};
+<a name="l00712"></a>00712 
+<a name="l00713"></a>00713 <span class="keyword">static</span> <span class="keywordtype">char</span> za_24[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
+<a name="l00714"></a>00714 
+<a name="l00715"></a>00715 
+<a name="l00716"></a>00716 
+<a name="l00717"></a>00717 <span class="keyword">static</span> <span class="keyword">const</span> <span class="keyword">struct </span>usb_descriptor_header *z_function [] = {
+<a name="l00718"></a>00718         (<span class="keyword">struct </span>usb_descriptor_header *) &amp;z_audio_control_if_desc,
+<a name="l00719"></a>00719         (<span class="keyword">struct</span> usb_descriptor_header *) &amp;z_ac_interface_header_desc,
+<a name="l00720"></a>00720         (<span class="keyword">struct </span>usb_descriptor_header *) &amp;z_0,
+<a name="l00721"></a>00721         (<span class="keyword">struct</span> usb_descriptor_header *) &amp;z_1,
+<a name="l00722"></a>00722         (<span class="keyword">struct </span>usb_descriptor_header *) &amp;z_2,
+<a name="l00723"></a>00723         (<span class="keyword">struct</span> usb_descriptor_header *) &amp;z_audio_if_desc,
+<a name="l00724"></a>00724         (<span class="keyword">struct </span>usb_descriptor_header *) &amp;z_audio_if_desc2,
+<a name="l00725"></a>00725         (<span class="keyword">struct</span> usb_descriptor_header *) &amp;z_audio_cs_as_if_desc,
+<a name="l00726"></a>00726         (<span class="keyword">struct </span>usb_descriptor_header *) &amp;z_audio_cs_as_format_desc,
+<a name="l00727"></a>00727         (<span class="keyword">struct</span> usb_descriptor_header *) &amp;z_iso_ep,
+<a name="l00728"></a>00728         (<span class="keyword">struct </span>usb_descriptor_header *) &amp;z_iso_ep2,
+<a name="l00729"></a>00729         (<span class="keyword">struct</span> usb_descriptor_header *) &amp;za_0,
+<a name="l00730"></a>00730         (<span class="keyword">struct </span>usb_descriptor_header *) &amp;za_1,
+<a name="l00731"></a>00731         (<span class="keyword">struct</span> usb_descriptor_header *) &amp;za_2,
+<a name="l00732"></a>00732         (<span class="keyword">struct </span>usb_descriptor_header *) &amp;za_3,
+<a name="l00733"></a>00733         (<span class="keyword">struct</span> usb_descriptor_header *) &amp;za_4,
+<a name="l00734"></a>00734         (<span class="keyword">struct </span>usb_descriptor_header *) &amp;za_5,
+<a name="l00735"></a>00735         (<span class="keyword">struct</span> usb_descriptor_header *) &amp;za_6,
+<a name="l00736"></a>00736         (<span class="keyword">struct </span>usb_descriptor_header *) &amp;za_7,
+<a name="l00737"></a>00737         (<span class="keyword">struct</span> usb_descriptor_header *) &amp;za_8,
+<a name="l00738"></a>00738         (<span class="keyword">struct </span>usb_descriptor_header *) &amp;za_9,
+<a name="l00739"></a>00739         (<span class="keyword">struct</span> usb_descriptor_header *) &amp;za_10,
+<a name="l00740"></a>00740         (<span class="keyword">struct </span>usb_descriptor_header *) &amp;za_11,
+<a name="l00741"></a>00741         (<span class="keyword">struct</span> usb_descriptor_header *) &amp;za_12,
+<a name="l00742"></a>00742         (<span class="keyword">struct </span>usb_descriptor_header *) &amp;za_13,
+<a name="l00743"></a>00743         (<span class="keyword">struct</span> usb_descriptor_header *) &amp;za_14,
+<a name="l00744"></a>00744         (<span class="keyword">struct </span>usb_descriptor_header *) &amp;za_15,
+<a name="l00745"></a>00745         (<span class="keyword">struct</span> usb_descriptor_header *) &amp;za_16,
+<a name="l00746"></a>00746         (<span class="keyword">struct </span>usb_descriptor_header *) &amp;za_17,
+<a name="l00747"></a>00747         (<span class="keyword">struct</span> usb_descriptor_header *) &amp;za_18,
+<a name="l00748"></a>00748         (<span class="keyword">struct </span>usb_descriptor_header *) &amp;za_19,
+<a name="l00749"></a>00749         (<span class="keyword">struct</span> usb_descriptor_header *) &amp;za_20,
+<a name="l00750"></a>00750         (<span class="keyword">struct </span>usb_descriptor_header *) &amp;za_21,
+<a name="l00751"></a>00751         (<span class="keyword">struct</span> usb_descriptor_header *) &amp;za_22,
+<a name="l00752"></a>00752         (<span class="keyword">struct </span>usb_descriptor_header *) &amp;za_23,
+<a name="l00753"></a>00753         (<span class="keyword">struct</span> usb_descriptor_header *) &amp;za_24,
+<a name="l00754"></a>00754         NULL,
+<a name="l00755"></a>00755 };
+<a name="l00756"></a>00756 
+<a name="l00757"></a>00757 <span class="comment">/* maxpacket and other transfer characteristics vary by speed. */</span>
+<a name="l00758"></a>00758 <span class="preprocessor">#define ep_desc(g,hs,fs) (((g)-&gt;speed==USB_SPEED_HIGH)?(hs):(fs))</span>
+<a name="l00759"></a>00759 <span class="preprocessor"></span>
+<a name="l00760"></a>00760 <span class="preprocessor">#else</span>
+<a name="l00761"></a>00761 <span class="preprocessor"></span>
+<a name="l00762"></a>00762 <span class="comment">/* if there's no high speed support, maxpacket doesn't change. */</span>
+<a name="l00763"></a>00763 <span class="preprocessor">#define ep_desc(g,hs,fs) fs</span>
+<a name="l00764"></a>00764 <span class="preprocessor"></span>
+<a name="l00765"></a>00765 <span class="preprocessor">#endif  </span><span class="comment">/* !CONFIG_USB_GADGET_DUALSPEED */</span>
+<a name="l00766"></a>00766 
+<a name="l00767"></a>00767 <span class="keyword">static</span> <span class="keywordtype">char</span>                             manufacturer [40];
+<a name="l00768"></a>00768 <span class="comment">//static char                           serial [40];</span>
+<a name="l00769"></a>00769 <span class="keyword">static</span> <span class="keywordtype">char</span>                             serial [] = <span class="stringliteral">"Ser 00 em"</span>;
+<a name="l00770"></a>00770 
+<a name="l00771"></a>00771 <span class="comment">/* static strings, in UTF-8 */</span>
+<a name="l00772"></a>00772 <span class="keyword">static</span> <span class="keyword">struct </span>usb_string                strings [] = {
+<a name="l00773"></a>00773         { STRING_MANUFACTURER, manufacturer, },
+<a name="l00774"></a>00774         { STRING_PRODUCT, longname, },
+<a name="l00775"></a>00775         { STRING_SERIAL, serial, },
+<a name="l00776"></a>00776         { STRING_LOOPBACK, loopback, },
+<a name="l00777"></a>00777         { STRING_SOURCE_SINK, source_sink, },
+<a name="l00778"></a>00778         {  }                    <span class="comment">/* end of list */</span>
+<a name="l00779"></a>00779 };
+<a name="l00780"></a>00780 
+<a name="l00781"></a>00781 <span class="keyword">static</span> <span class="keyword">struct </span>usb_gadget_strings        stringtab = {
+<a name="l00782"></a>00782         .language       = 0x0409,       <span class="comment">/* en-us */</span>
+<a name="l00783"></a>00783         .strings        = strings,
+<a name="l00784"></a>00784 };
+<a name="l00785"></a>00785 
+<a name="l00786"></a>00786 <span class="comment">/*</span>
+<a name="l00787"></a>00787 <span class="comment"> * config descriptors are also handcrafted.  these must agree with code</span>
+<a name="l00788"></a>00788 <span class="comment"> * that sets configurations, and with code managing interfaces and their</span>
+<a name="l00789"></a>00789 <span class="comment"> * altsettings.  other complexity may come from:</span>
+<a name="l00790"></a>00790 <span class="comment"> *</span>
+<a name="l00791"></a>00791 <span class="comment"> *  - high speed support, including "other speed config" rules</span>
+<a name="l00792"></a>00792 <span class="comment"> *  - multiple configurations</span>
+<a name="l00793"></a>00793 <span class="comment"> *  - interfaces with alternate settings</span>
+<a name="l00794"></a>00794 <span class="comment"> *  - embedded class or vendor-specific descriptors</span>
+<a name="l00795"></a>00795 <span class="comment"> *</span>
+<a name="l00796"></a>00796 <span class="comment"> * this handles high speed, and has a second config that could as easily</span>
+<a name="l00797"></a>00797 <span class="comment"> * have been an alternate interface setting (on most hardware).</span>
+<a name="l00798"></a>00798 <span class="comment"> *</span>
+<a name="l00799"></a>00799 <span class="comment"> * NOTE:  to demonstrate (and test) more USB capabilities, this driver</span>
+<a name="l00800"></a>00800 <span class="comment"> * should include an altsetting to test interrupt transfers, including</span>
+<a name="l00801"></a>00801 <span class="comment"> * high bandwidth modes at high speed.  (Maybe work like Intel's test</span>
+<a name="l00802"></a>00802 <span class="comment"> * device?)</span>
+<a name="l00803"></a>00803 <span class="comment"> */</span>
+<a name="l00804"></a>00804 <span class="keyword">static</span> <span class="keywordtype">int</span>
+<a name="l00805"></a>00805 config_buf (<span class="keyword">struct</span> usb_gadget *gadget, u8 *buf, u8 type, <span class="keywordtype">unsigned</span> index)
+<a name="l00806"></a>00806 {
+<a name="l00807"></a>00807         <span class="keywordtype">int</span> len;
+<a name="l00808"></a>00808         <span class="keyword">const</span> <span class="keyword">struct </span>usb_descriptor_header **function;
+<a name="l00809"></a>00809         
+<a name="l00810"></a>00810         function = z_function;
+<a name="l00811"></a>00811         len = usb_gadget_config_buf (&amp;z_config, buf, USB_BUFSIZ, function);
+<a name="l00812"></a>00812         <span class="keywordflow">if</span> (len &lt; 0)
+<a name="l00813"></a>00813                 <span class="keywordflow">return</span> len;
+<a name="l00814"></a>00814         ((<span class="keyword">struct </span>usb_config_descriptor *) buf)-&gt;bDescriptorType = type;
+<a name="l00815"></a>00815         <span class="keywordflow">return</span> len;
+<a name="l00816"></a>00816 }
+<a name="l00817"></a>00817 
+<a name="l00818"></a>00818 <span class="comment">/*-------------------------------------------------------------------------*/</span>
+<a name="l00819"></a>00819 
+<a name="l00820"></a>00820 <span class="keyword">static</span> <span class="keyword">struct </span>usb_request *
+<a name="l00821"></a>00821 alloc_ep_req (<span class="keyword">struct</span> usb_ep *ep, <span class="keywordtype">unsigned</span> length)
+<a name="l00822"></a>00822 {
+<a name="l00823"></a>00823         <span class="keyword">struct </span>usb_request      *req;
+<a name="l00824"></a>00824 
+<a name="l00825"></a>00825         req = usb_ep_alloc_request (ep, GFP_ATOMIC);
+<a name="l00826"></a>00826         <span class="keywordflow">if</span> (req) {
+<a name="l00827"></a>00827                 req-&gt;length = length;
+<a name="l00828"></a>00828                 req-&gt;buf = usb_ep_alloc_buffer (ep, length,
+<a name="l00829"></a>00829                                 &amp;req-&gt;dma, GFP_ATOMIC);
+<a name="l00830"></a>00830                 <span class="keywordflow">if</span> (!req-&gt;buf) {
+<a name="l00831"></a>00831                         usb_ep_free_request (ep, req);
+<a name="l00832"></a>00832                         req = NULL;
+<a name="l00833"></a>00833                 }
+<a name="l00834"></a>00834         }
+<a name="l00835"></a>00835         <span class="keywordflow">return</span> req;
+<a name="l00836"></a>00836 }
+<a name="l00837"></a>00837 
+<a name="l00838"></a>00838 <span class="keyword">static</span> <span class="keywordtype">void</span> free_ep_req (<span class="keyword">struct</span> usb_ep *ep, <span class="keyword">struct</span> usb_request *req)
+<a name="l00839"></a>00839 {
+<a name="l00840"></a>00840         <span class="keywordflow">if</span> (req-&gt;buf)
+<a name="l00841"></a>00841                 usb_ep_free_buffer (ep, req-&gt;buf, req-&gt;dma, req-&gt;length);
+<a name="l00842"></a>00842         usb_ep_free_request (ep, req);
+<a name="l00843"></a>00843 }
+<a name="l00844"></a>00844 
+<a name="l00845"></a>00845 <span class="comment">/*-------------------------------------------------------------------------*/</span>
+<a name="l00846"></a>00846 
+<a name="l00847"></a>00847 <span class="comment">/* optionally require specific source/sink data patterns  */</span>
+<a name="l00848"></a>00848 
+<a name="l00849"></a>00849 <span class="keyword">static</span> <span class="keywordtype">int</span>
+<a name="l00850"></a>00850 check_read_data (
+<a name="l00851"></a>00851         <span class="keyword">struct</span> <a class="code" href="structzero__dev.html">zero_dev</a>         *dev,
+<a name="l00852"></a>00852         <span class="keyword">struct</span> usb_ep           *ep,
+<a name="l00853"></a>00853         <span class="keyword">struct</span> usb_request      *req
+<a name="l00854"></a>00854 )
+<a name="l00855"></a>00855 {
+<a name="l00856"></a>00856         <span class="keywordtype">unsigned</span>        i;
+<a name="l00857"></a>00857         u8              *buf = req-&gt;buf;
+<a name="l00858"></a>00858 
+<a name="l00859"></a>00859         <span class="keywordflow">for</span> (i = 0; i &lt; req-&gt;actual; i++, buf++) {
+<a name="l00860"></a>00860                 <span class="keywordflow">switch</span> (pattern) {
+<a name="l00861"></a>00861                 <span class="comment">/* all-zeroes has no synchronization issues */</span>
+<a name="l00862"></a>00862                 <span class="keywordflow">case</span> 0:
+<a name="l00863"></a>00863                         <span class="keywordflow">if</span> (*buf == 0)
+<a name="l00864"></a>00864                                 <span class="keywordflow">continue</span>;
+<a name="l00865"></a>00865                         <span class="keywordflow">break</span>;
+<a name="l00866"></a>00866                 <span class="comment">/* mod63 stays in sync with short-terminated transfers,</span>
+<a name="l00867"></a>00867 <span class="comment">                 * or otherwise when host and gadget agree on how large</span>
+<a name="l00868"></a>00868 <span class="comment">                 * each usb transfer request should be.  resync is done</span>
+<a name="l00869"></a>00869 <span class="comment">                 * with set_interface or set_config.</span>
+<a name="l00870"></a>00870 <span class="comment">                 */</span>
+<a name="l00871"></a>00871                 <span class="keywordflow">case</span> 1:
+<a name="l00872"></a>00872                         <span class="keywordflow">if</span> (*buf == (u8)(i % 63))
+<a name="l00873"></a>00873                                 <span class="keywordflow">continue</span>;
+<a name="l00874"></a>00874                         <span class="keywordflow">break</span>;
+<a name="l00875"></a>00875                 }
+<a name="l00876"></a>00876                 ERROR (dev, <span class="stringliteral">"bad OUT byte, buf [%d] = %d\n"</span>, i, *buf);
+<a name="l00877"></a>00877                 usb_ep_set_halt (ep);
+<a name="l00878"></a>00878                 <span class="keywordflow">return</span> -EINVAL;
+<a name="l00879"></a>00879         }
+<a name="l00880"></a>00880         <span class="keywordflow">return</span> 0;
+<a name="l00881"></a>00881 }
+<a name="l00882"></a>00882 
+<a name="l00883"></a>00883 <span class="comment">/*-------------------------------------------------------------------------*/</span>
+<a name="l00884"></a>00884 
+<a name="l00885"></a>00885 <span class="keyword">static</span> <span class="keywordtype">void</span> zero_reset_config (<span class="keyword">struct</span> <a class="code" href="structzero__dev.html">zero_dev</a> *dev)
+<a name="l00886"></a>00886 {
+<a name="l00887"></a>00887         <span class="keywordflow">if</span> (dev-&gt;<a class="code" href="structzero__dev.html#2481a8df9867ab54361cf4ffc7267484">config</a> == 0)
+<a name="l00888"></a>00888                 <span class="keywordflow">return</span>;
+<a name="l00889"></a>00889 
+<a name="l00890"></a>00890         DBG (dev, <span class="stringliteral">"reset config\n"</span>);
+<a name="l00891"></a>00891 
+<a name="l00892"></a>00892         <span class="comment">/* just disable endpoints, forcing completion of pending i/o.</span>
+<a name="l00893"></a>00893 <span class="comment">         * all our completion handlers free their requests in this case.</span>
+<a name="l00894"></a>00894 <span class="comment">         */</span>
+<a name="l00895"></a>00895         <span class="keywordflow">if</span> (dev-&gt;<a class="code" href="structzero__dev.html#8b35a5b8ce497d55d7369a4635d891df">in_ep</a>) {
+<a name="l00896"></a>00896                 usb_ep_disable (dev-&gt;<a class="code" href="structzero__dev.html#8b35a5b8ce497d55d7369a4635d891df">in_ep</a>);
+<a name="l00897"></a>00897                 dev-&gt;<a class="code" href="structzero__dev.html#8b35a5b8ce497d55d7369a4635d891df">in_ep</a> = NULL;
+<a name="l00898"></a>00898         }
+<a name="l00899"></a>00899         <span class="keywordflow">if</span> (dev-&gt;<a class="code" href="structzero__dev.html#28a2079d55de6ac606cc69b79882223f">out_ep</a>) {
+<a name="l00900"></a>00900                 usb_ep_disable (dev-&gt;<a class="code" href="structzero__dev.html#28a2079d55de6ac606cc69b79882223f">out_ep</a>);
+<a name="l00901"></a>00901                 dev-&gt;<a class="code" href="structzero__dev.html#28a2079d55de6ac606cc69b79882223f">out_ep</a> = NULL;
+<a name="l00902"></a>00902         }
+<a name="l00903"></a>00903         dev-&gt;<a class="code" href="structzero__dev.html#2481a8df9867ab54361cf4ffc7267484">config</a> = 0;
+<a name="l00904"></a>00904         del_timer (&amp;dev-&gt;<a class="code" href="structzero__dev.html#5fcacdfb9a6b069c866d44d66dd566a4">resume</a>);
+<a name="l00905"></a>00905 }
+<a name="l00906"></a>00906 
+<a name="l00907"></a>00907 <span class="preprocessor">#define _write(f, buf, sz) (f-&gt;f_op-&gt;write(f, buf, sz, &amp;f-&gt;f_pos))</span>
+<a name="l00908"></a>00908 <span class="preprocessor"></span>
+<a name="l00909"></a>00909 <span class="keyword">static</span> <span class="keywordtype">void</span> 
+<a name="l00910"></a>00910 zero_isoc_complete (<span class="keyword">struct</span> usb_ep *ep, <span class="keyword">struct</span> usb_request *req)
+<a name="l00911"></a>00911 {
+<a name="l00912"></a>00912         <span class="keyword">struct </span><a class="code" href="structzero__dev.html">zero_dev</a> *dev = ep-&gt;driver_data;
+<a name="l00913"></a>00913         <span class="keywordtype">int</span>             status = req-&gt;status;
+<a name="l00914"></a>00914         <span class="keywordtype">int</span> i, j;
+<a name="l00915"></a>00915 
+<a name="l00916"></a>00916         <span class="keywordflow">switch</span> (status) {
+<a name="l00917"></a>00917 
+<a name="l00918"></a>00918         <span class="keywordflow">case</span> 0:                         <span class="comment">/* normal completion? */</span>
+<a name="l00919"></a>00919                 <span class="comment">//printk ("\nzero ---------------&gt; isoc normal completion %d bytes\n", req-&gt;actual);</span>
+<a name="l00920"></a>00920                 <span class="keywordflow">for</span> (i=0, j=rbuf_start; i&lt;req-&gt;actual; i++) {
+<a name="l00921"></a>00921                         <span class="comment">//printk ("%02x ", ((__u8*)req-&gt;buf)[i]);</span>
+<a name="l00922"></a>00922                         rbuf[j] = ((__u8*)req-&gt;buf)[i];
+<a name="l00923"></a>00923                         j++;
+<a name="l00924"></a>00924                         if (j &gt;= RBUF_LEN) j=0;
+<a name="l00925"></a>00925                 }
+<a name="l00926"></a>00926                 rbuf_start = j;
+<a name="l00927"></a>00927                 <span class="comment">//printk ("\n\n");</span>
+<a name="l00928"></a>00928 
+<a name="l00929"></a>00929                 <span class="keywordflow">if</span> (rbuf_len &lt; RBUF_LEN) {
+<a name="l00930"></a>00930                         rbuf_len += req-&gt;actual;
+<a name="l00931"></a>00931                         if (rbuf_len &gt; RBUF_LEN) {
+<a name="l00932"></a>00932                                 rbuf_len = RBUF_LEN;
+<a name="l00933"></a>00933                         }
+<a name="l00934"></a>00934                 }
+<a name="l00935"></a>00935 
+<a name="l00936"></a>00936                 <span class="keywordflow">break</span>;
+<a name="l00937"></a>00937 
+<a name="l00938"></a>00938         <span class="comment">/* this endpoint is normally active while we're configured */</span>
+<a name="l00939"></a>00939         <span class="keywordflow">case</span> -ECONNABORTED:             <span class="comment">/* hardware forced ep reset */</span>
+<a name="l00940"></a>00940         <span class="keywordflow">case</span> -ECONNRESET:               <span class="comment">/* request dequeued */</span>
+<a name="l00941"></a>00941         <span class="keywordflow">case</span> -ESHUTDOWN:                <span class="comment">/* disconnect from host */</span>
+<a name="l00942"></a>00942                 VDBG (dev, <span class="stringliteral">"%s gone (%d), %d/%d\n"</span>, ep-&gt;name, status,
+<a name="l00943"></a>00943                                 req-&gt;actual, req-&gt;length);
+<a name="l00944"></a>00944                 <span class="keywordflow">if</span> (ep == dev-&gt;<a class="code" href="structzero__dev.html#28a2079d55de6ac606cc69b79882223f">out_ep</a>)
+<a name="l00945"></a>00945                         check_read_data (dev, ep, req);
+<a name="l00946"></a>00946                 free_ep_req (ep, req);
+<a name="l00947"></a>00947                 <span class="keywordflow">return</span>;
+<a name="l00948"></a>00948 
+<a name="l00949"></a>00949         <span class="keywordflow">case</span> -EOVERFLOW:                <span class="comment">/* buffer overrun on read means that</span>
+<a name="l00950"></a>00950 <span class="comment">                                         * we didn't provide a big enough</span>
+<a name="l00951"></a>00951 <span class="comment">                                         * buffer.</span>
+<a name="l00952"></a>00952 <span class="comment">                                         */</span>
+<a name="l00953"></a>00953         <span class="keywordflow">default</span>:
+<a name="l00954"></a>00954 <span class="preprocessor">#if 1</span>
+<a name="l00955"></a>00955 <span class="preprocessor"></span>                DBG (dev, <span class="stringliteral">"%s complete --&gt; %d, %d/%d\n"</span>, ep-&gt;name,
+<a name="l00956"></a>00956                                 status, req-&gt;actual, req-&gt;length);
+<a name="l00957"></a>00957 <span class="preprocessor">#endif</span>
+<a name="l00958"></a>00958 <span class="preprocessor"></span>        <span class="keywordflow">case</span> -EREMOTEIO:                <span class="comment">/* short read */</span>
+<a name="l00959"></a>00959                 <span class="keywordflow">break</span>;
+<a name="l00960"></a>00960         }
+<a name="l00961"></a>00961 
+<a name="l00962"></a>00962         status = usb_ep_queue (ep, req, GFP_ATOMIC);
+<a name="l00963"></a>00963         <span class="keywordflow">if</span> (status) {
+<a name="l00964"></a>00964                 ERROR (dev, <span class="stringliteral">"kill %s:  resubmit %d bytes --&gt; %d\n"</span>,
+<a name="l00965"></a>00965                                 ep-&gt;name, req-&gt;length, status);
+<a name="l00966"></a>00966                 usb_ep_set_halt (ep);
+<a name="l00967"></a>00967                 <span class="comment">/* FIXME recover later ... somehow */</span>
+<a name="l00968"></a>00968         }
+<a name="l00969"></a>00969 }
+<a name="l00970"></a>00970 
+<a name="l00971"></a>00971 <span class="keyword">static</span> <span class="keyword">struct </span>usb_request *
+<a name="l00972"></a>00972 zero_start_isoc_ep (<span class="keyword">struct</span> usb_ep *ep, <span class="keywordtype">int</span> gfp_flags)
+<a name="l00973"></a>00973 {
+<a name="l00974"></a>00974         <span class="keyword">struct </span>usb_request      *req;
+<a name="l00975"></a>00975         <span class="keywordtype">int</span>                     status;
+<a name="l00976"></a>00976 
+<a name="l00977"></a>00977         req = alloc_ep_req (ep, 512);
+<a name="l00978"></a>00978         <span class="keywordflow">if</span> (!req)
+<a name="l00979"></a>00979                 <span class="keywordflow">return</span> NULL;
+<a name="l00980"></a>00980 
+<a name="l00981"></a>00981         req-&gt;complete = zero_isoc_complete;
+<a name="l00982"></a>00982 
+<a name="l00983"></a>00983         status = usb_ep_queue (ep, req, gfp_flags);
+<a name="l00984"></a>00984         <span class="keywordflow">if</span> (status) {
+<a name="l00985"></a>00985                 <span class="keyword">struct </span><a class="code" href="structzero__dev.html">zero_dev</a> *dev = ep-&gt;driver_data;
+<a name="l00986"></a>00986 
+<a name="l00987"></a>00987                 ERROR (dev, <span class="stringliteral">"start %s --&gt; %d\n"</span>, ep-&gt;name, status);
+<a name="l00988"></a>00988                 free_ep_req (ep, req);
+<a name="l00989"></a>00989                 req = NULL;
+<a name="l00990"></a>00990         }
+<a name="l00991"></a>00991 
+<a name="l00992"></a>00992         <span class="keywordflow">return</span> req;
+<a name="l00993"></a>00993 }
+<a name="l00994"></a>00994 
+<a name="l00995"></a>00995 <span class="comment">/* change our operational config.  this code must agree with the code</span>
+<a name="l00996"></a>00996 <span class="comment"> * that returns config descriptors, and altsetting code.</span>
+<a name="l00997"></a>00997 <span class="comment"> *</span>
+<a name="l00998"></a>00998 <span class="comment"> * it's also responsible for power management interactions. some</span>
+<a name="l00999"></a>00999 <span class="comment"> * configurations might not work with our current power sources.</span>
+<a name="l01000"></a>01000 <span class="comment"> *</span>
+<a name="l01001"></a>01001 <span class="comment"> * note that some device controller hardware will constrain what this</span>
+<a name="l01002"></a>01002 <span class="comment"> * code can do, perhaps by disallowing more than one configuration or</span>
+<a name="l01003"></a>01003 <span class="comment"> * by limiting configuration choices (like the pxa2xx).</span>
+<a name="l01004"></a>01004 <span class="comment"> */</span>
+<a name="l01005"></a>01005 <span class="keyword">static</span> <span class="keywordtype">int</span>
+<a name="l01006"></a>01006 zero_set_config (<span class="keyword">struct</span> <a class="code" href="structzero__dev.html">zero_dev</a> *dev, <span class="keywordtype">unsigned</span> number, <span class="keywordtype">int</span> gfp_flags)
+<a name="l01007"></a>01007 {
+<a name="l01008"></a>01008         <span class="keywordtype">int</span>                     result = 0;
+<a name="l01009"></a>01009         <span class="keyword">struct </span>usb_gadget       *gadget = dev-&gt;<a class="code" href="structzero__dev.html#e0d019d6177afd1efa101aed63f1a174">gadget</a>;
+<a name="l01010"></a>01010         <span class="keyword">const</span> <span class="keyword">struct </span>usb_endpoint_descriptor    *d;
+<a name="l01011"></a>01011         <span class="keyword">struct </span>usb_ep           *ep;
+<a name="l01012"></a>01012 
+<a name="l01013"></a>01013         <span class="keywordflow">if</span> (number == dev-&gt;<a class="code" href="structzero__dev.html#2481a8df9867ab54361cf4ffc7267484">config</a>)
+<a name="l01014"></a>01014                 <span class="keywordflow">return</span> 0;
+<a name="l01015"></a>01015 
+<a name="l01016"></a>01016         zero_reset_config (dev);
+<a name="l01017"></a>01017 
+<a name="l01018"></a>01018         gadget_for_each_ep (ep, gadget) {
+<a name="l01019"></a>01019 
+<a name="l01020"></a>01020                 <span class="keywordflow">if</span> (strcmp (ep-&gt;name, <span class="stringliteral">"ep4"</span>) == 0) {
+<a name="l01021"></a>01021 
+<a name="l01022"></a>01022                         d = (<span class="keyword">struct </span>usb_endpoint_descripter *)&amp;za_23; <span class="comment">// isoc ep desc for audio i/f alt setting 6</span>
+<a name="l01023"></a>01023                         result = usb_ep_enable (ep, d);
+<a name="l01024"></a>01024 
+<a name="l01025"></a>01025                         <span class="keywordflow">if</span> (result == 0) {
+<a name="l01026"></a>01026                                 ep-&gt;driver_data = dev;
+<a name="l01027"></a>01027                                 dev-&gt;<a class="code" href="structzero__dev.html#8b35a5b8ce497d55d7369a4635d891df">in_ep</a> = ep;
+<a name="l01028"></a>01028 
+<a name="l01029"></a>01029                                 <span class="keywordflow">if</span> (zero_start_isoc_ep (ep, gfp_flags) != 0) {
+<a name="l01030"></a>01030 
+<a name="l01031"></a>01031                                         dev-&gt;<a class="code" href="structzero__dev.html#8b35a5b8ce497d55d7369a4635d891df">in_ep</a> = ep;
+<a name="l01032"></a>01032                                         <span class="keywordflow">continue</span>;
+<a name="l01033"></a>01033                                 }
+<a name="l01034"></a>01034 
+<a name="l01035"></a>01035                                 usb_ep_disable (ep);
+<a name="l01036"></a>01036                                 result = -EIO;
+<a name="l01037"></a>01037                         }
+<a name="l01038"></a>01038                 }
+<a name="l01039"></a>01039 
+<a name="l01040"></a>01040         }
+<a name="l01041"></a>01041 
+<a name="l01042"></a>01042         dev-&gt;<a class="code" href="structzero__dev.html#2481a8df9867ab54361cf4ffc7267484">config</a> = number;
+<a name="l01043"></a>01043         <span class="keywordflow">return</span> result;
+<a name="l01044"></a>01044 }
+<a name="l01045"></a>01045 
+<a name="l01046"></a>01046 <span class="comment">/*-------------------------------------------------------------------------*/</span>
+<a name="l01047"></a>01047 
+<a name="l01048"></a>01048 <span class="keyword">static</span> <span class="keywordtype">void</span> zero_setup_complete (<span class="keyword">struct</span> usb_ep *ep, <span class="keyword">struct</span> usb_request *req)
+<a name="l01049"></a>01049 {
+<a name="l01050"></a>01050         <span class="keywordflow">if</span> (req-&gt;status || req-&gt;actual != req-&gt;length)
+<a name="l01051"></a>01051                 DBG ((<span class="keyword">struct</span> <a class="code" href="structzero__dev.html">zero_dev</a> *) ep-&gt;driver_data,
+<a name="l01052"></a>01052                                 <span class="stringliteral">"setup complete --&gt; %d, %d/%d\n"</span>,
+<a name="l01053"></a>01053                                 req-&gt;status, req-&gt;actual, req-&gt;length);
+<a name="l01054"></a>01054 }
+<a name="l01055"></a>01055 
+<a name="l01056"></a>01056 <span class="comment">/*</span>
+<a name="l01057"></a>01057 <span class="comment"> * The setup() callback implements all the ep0 functionality that's</span>
+<a name="l01058"></a>01058 <span class="comment"> * not handled lower down, in hardware or the hardware driver (like</span>
+<a name="l01059"></a>01059 <span class="comment"> * device and endpoint feature flags, and their status).  It's all</span>
+<a name="l01060"></a>01060 <span class="comment"> * housekeeping for the gadget function we're implementing.  Most of</span>
+<a name="l01061"></a>01061 <span class="comment"> * the work is in config-specific setup.</span>
+<a name="l01062"></a>01062 <span class="comment"> */</span>
+<a name="l01063"></a>01063 <span class="keyword">static</span> <span class="keywordtype">int</span>
+<a name="l01064"></a>01064 zero_setup (<span class="keyword">struct</span> usb_gadget *gadget, <span class="keyword">const</span> <span class="keyword">struct</span> usb_ctrlrequest *ctrl)
+<a name="l01065"></a>01065 {
+<a name="l01066"></a>01066         <span class="keyword">struct </span><a class="code" href="structzero__dev.html">zero_dev</a>         *dev = get_gadget_data (gadget);
+<a name="l01067"></a>01067         <span class="keyword">struct </span>usb_request      *req = dev-&gt;<a class="code" href="structzero__dev.html#7dad5245ef3701a5521638e2499ebfe9">req</a>;
+<a name="l01068"></a>01068         <span class="keywordtype">int</span>                     value = -EOPNOTSUPP;
+<a name="l01069"></a>01069 
+<a name="l01070"></a>01070         <span class="comment">/* usually this stores reply data in the pre-allocated ep0 buffer,</span>
+<a name="l01071"></a>01071 <span class="comment">         * but config change events will reconfigure hardware.</span>
+<a name="l01072"></a>01072 <span class="comment">         */</span>
+<a name="l01073"></a>01073         req-&gt;zero = 0;
+<a name="l01074"></a>01074         <span class="keywordflow">switch</span> (ctrl-&gt;bRequest) {
+<a name="l01075"></a>01075 
+<a name="l01076"></a>01076         <span class="keywordflow">case</span> USB_REQ_GET_DESCRIPTOR:
+<a name="l01077"></a>01077 
+<a name="l01078"></a>01078                 <span class="keywordflow">switch</span> (ctrl-&gt;wValue &gt;&gt; 8) {
+<a name="l01079"></a>01079 
+<a name="l01080"></a>01080                 <span class="keywordflow">case</span> USB_DT_DEVICE:
+<a name="l01081"></a>01081                         value = <a class="code" href="dwc__otg__cfi_8h.html#7c9949b9e692a8360832aedfa1843657">min</a> (ctrl-&gt;wLength, (u16) <span class="keyword">sizeof</span> device_desc);
+<a name="l01082"></a>01082                         memcpy (req-&gt;buf, &amp;device_desc, value);
+<a name="l01083"></a>01083                         <span class="keywordflow">break</span>;
+<a name="l01084"></a>01084 <span class="preprocessor">#ifdef CONFIG_USB_GADGET_DUALSPEED</span>
+<a name="l01085"></a>01085 <span class="preprocessor"></span>                <span class="keywordflow">case</span> USB_DT_DEVICE_QUALIFIER:
+<a name="l01086"></a>01086                         <span class="keywordflow">if</span> (!gadget-&gt;is_dualspeed)
+<a name="l01087"></a>01087                                 <span class="keywordflow">break</span>;
+<a name="l01088"></a>01088                         value = <a class="code" href="dwc__otg__cfi_8h.html#7c9949b9e692a8360832aedfa1843657">min</a> (ctrl-&gt;wLength, (u16) <span class="keyword">sizeof</span> dev_qualifier);
+<a name="l01089"></a>01089                         memcpy (req-&gt;buf, &amp;dev_qualifier, value);
+<a name="l01090"></a>01090                         <span class="keywordflow">break</span>;
+<a name="l01091"></a>01091 
+<a name="l01092"></a>01092                 <span class="keywordflow">case</span> USB_DT_OTHER_SPEED_CONFIG:
+<a name="l01093"></a>01093                         <span class="keywordflow">if</span> (!gadget-&gt;is_dualspeed)
+<a name="l01094"></a>01094                                 <span class="keywordflow">break</span>;
+<a name="l01095"></a>01095                         <span class="comment">// FALLTHROUGH</span>
+<a name="l01096"></a>01096 <span class="preprocessor">#endif </span><span class="comment">/* CONFIG_USB_GADGET_DUALSPEED */</span>
+<a name="l01097"></a>01097                 <span class="keywordflow">case</span> USB_DT_CONFIG:
+<a name="l01098"></a>01098                         value = config_buf (gadget, req-&gt;buf,
+<a name="l01099"></a>01099                                         ctrl-&gt;wValue &gt;&gt; 8,
+<a name="l01100"></a>01100                                         ctrl-&gt;wValue &amp; 0xff);
+<a name="l01101"></a>01101                         <span class="keywordflow">if</span> (value &gt;= 0)
+<a name="l01102"></a>01102                                 value = <a class="code" href="dwc__otg__cfi_8h.html#7c9949b9e692a8360832aedfa1843657">min</a> (ctrl-&gt;wLength, (u16) value);
+<a name="l01103"></a>01103                         <span class="keywordflow">break</span>;
+<a name="l01104"></a>01104 
+<a name="l01105"></a>01105                 <span class="keywordflow">case</span> USB_DT_STRING:
+<a name="l01106"></a>01106                         <span class="comment">/* wIndex == language code.</span>
+<a name="l01107"></a>01107 <span class="comment">                         * this driver only handles one language, you can</span>
+<a name="l01108"></a>01108 <span class="comment">                         * add string tables for other languages, using</span>
+<a name="l01109"></a>01109 <span class="comment">                         * any UTF-8 characters</span>
+<a name="l01110"></a>01110 <span class="comment">                         */</span>
+<a name="l01111"></a>01111                         value = usb_gadget_get_string (&amp;stringtab,
+<a name="l01112"></a>01112                                         ctrl-&gt;wValue &amp; 0xff, req-&gt;buf);
+<a name="l01113"></a>01113                         <span class="keywordflow">if</span> (value &gt;= 0) {
+<a name="l01114"></a>01114                                 value = <a class="code" href="dwc__otg__cfi_8h.html#7c9949b9e692a8360832aedfa1843657">min</a> (ctrl-&gt;wLength, (u16) value);
+<a name="l01115"></a>01115                         }
+<a name="l01116"></a>01116                         <span class="keywordflow">break</span>;
+<a name="l01117"></a>01117                 }
+<a name="l01118"></a>01118                 <span class="keywordflow">break</span>;
+<a name="l01119"></a>01119 
+<a name="l01120"></a>01120         <span class="comment">/* currently two configs, two speeds */</span>
+<a name="l01121"></a>01121         <span class="keywordflow">case</span> USB_REQ_SET_CONFIGURATION:
+<a name="l01122"></a>01122                 <span class="keywordflow">if</span> (ctrl-&gt;bRequestType != 0)
+<a name="l01123"></a>01123                         <span class="keywordflow">goto</span> unknown;
+<a name="l01124"></a>01124 
+<a name="l01125"></a>01125                 spin_lock (&amp;dev-&gt;<a class="code" href="structzero__dev.html#712568d4b6a481845034ac6d87c0547d">lock</a>);
+<a name="l01126"></a>01126                 value = zero_set_config (dev, ctrl-&gt;wValue, GFP_ATOMIC);
+<a name="l01127"></a>01127                 spin_unlock (&amp;dev-&gt;<a class="code" href="structzero__dev.html#712568d4b6a481845034ac6d87c0547d">lock</a>);
+<a name="l01128"></a>01128                 <span class="keywordflow">break</span>;
+<a name="l01129"></a>01129         <span class="keywordflow">case</span> USB_REQ_GET_CONFIGURATION:
+<a name="l01130"></a>01130                 <span class="keywordflow">if</span> (ctrl-&gt;bRequestType != USB_DIR_IN)
+<a name="l01131"></a>01131                         <span class="keywordflow">goto</span> unknown;
+<a name="l01132"></a>01132                 *(u8 *)req-&gt;buf = dev-&gt;<a class="code" href="structzero__dev.html#2481a8df9867ab54361cf4ffc7267484">config</a>;
+<a name="l01133"></a>01133                 value = <a class="code" href="dwc__otg__cfi_8h.html#7c9949b9e692a8360832aedfa1843657">min</a> (ctrl-&gt;wLength, (u16) 1);
+<a name="l01134"></a>01134                 <span class="keywordflow">break</span>;
+<a name="l01135"></a>01135 
+<a name="l01136"></a>01136         <span class="comment">/* until we add altsetting support, or other interfaces,</span>
+<a name="l01137"></a>01137 <span class="comment">         * only 0/0 are possible.  pxa2xx only supports 0/0 (poorly)</span>
+<a name="l01138"></a>01138 <span class="comment">         * and already killed pending endpoint I/O.</span>
+<a name="l01139"></a>01139 <span class="comment">         */</span>
+<a name="l01140"></a>01140         <span class="keywordflow">case</span> USB_REQ_SET_INTERFACE:
+<a name="l01141"></a>01141 
+<a name="l01142"></a>01142                 <span class="keywordflow">if</span> (ctrl-&gt;bRequestType != USB_RECIP_INTERFACE)
+<a name="l01143"></a>01143                         <span class="keywordflow">goto</span> unknown;
+<a name="l01144"></a>01144                 spin_lock (&amp;dev-&gt;<a class="code" href="structzero__dev.html#712568d4b6a481845034ac6d87c0547d">lock</a>);
+<a name="l01145"></a>01145                 <span class="keywordflow">if</span> (dev-&gt;<a class="code" href="structzero__dev.html#2481a8df9867ab54361cf4ffc7267484">config</a>) {
+<a name="l01146"></a>01146                         u8              config = dev-&gt;<a class="code" href="structzero__dev.html#2481a8df9867ab54361cf4ffc7267484">config</a>;
+<a name="l01147"></a>01147 
+<a name="l01148"></a>01148                         <span class="comment">/* resets interface configuration, forgets about</span>
+<a name="l01149"></a>01149 <span class="comment">                         * previous transaction state (queued bufs, etc)</span>
+<a name="l01150"></a>01150 <span class="comment">                         * and re-inits endpoint state (toggle etc)</span>
+<a name="l01151"></a>01151 <span class="comment">                         * no response queued, just zero status == success.</span>
+<a name="l01152"></a>01152 <span class="comment">                         * if we had more than one interface we couldn't</span>
+<a name="l01153"></a>01153 <span class="comment">                         * use this "reset the config" shortcut.</span>
+<a name="l01154"></a>01154 <span class="comment">                         */</span>
+<a name="l01155"></a>01155                         zero_reset_config (dev);
+<a name="l01156"></a>01156                         zero_set_config (dev, config, GFP_ATOMIC);
+<a name="l01157"></a>01157                         value = 0;
+<a name="l01158"></a>01158                 }
+<a name="l01159"></a>01159                 spin_unlock (&amp;dev-&gt;<a class="code" href="structzero__dev.html#712568d4b6a481845034ac6d87c0547d">lock</a>);
+<a name="l01160"></a>01160                 <span class="keywordflow">break</span>;
+<a name="l01161"></a>01161         <span class="keywordflow">case</span> USB_REQ_GET_INTERFACE:
+<a name="l01162"></a>01162                 <span class="keywordflow">if</span> ((ctrl-&gt;bRequestType == 0x21) &amp;&amp; (ctrl-&gt;wIndex == 0x02)) {
+<a name="l01163"></a>01163                         value = ctrl-&gt;wLength;
+<a name="l01164"></a>01164                         <span class="keywordflow">break</span>;
+<a name="l01165"></a>01165                 }
+<a name="l01166"></a>01166                 <span class="keywordflow">else</span> {
+<a name="l01167"></a>01167                         <span class="keywordflow">if</span> (ctrl-&gt;bRequestType != (USB_DIR_IN|USB_RECIP_INTERFACE))
+<a name="l01168"></a>01168                                 <span class="keywordflow">goto</span> unknown;
+<a name="l01169"></a>01169                         <span class="keywordflow">if</span> (!dev-&gt;<a class="code" href="structzero__dev.html#2481a8df9867ab54361cf4ffc7267484">config</a>)
+<a name="l01170"></a>01170                                 <span class="keywordflow">break</span>;
+<a name="l01171"></a>01171                         <span class="keywordflow">if</span> (ctrl-&gt;wIndex != 0) {
+<a name="l01172"></a>01172                                 value = -EDOM;
+<a name="l01173"></a>01173                                 <span class="keywordflow">break</span>;
+<a name="l01174"></a>01174                         }
+<a name="l01175"></a>01175                         *(u8 *)req-&gt;buf = 0;
+<a name="l01176"></a>01176                         value = <a class="code" href="dwc__otg__cfi_8h.html#7c9949b9e692a8360832aedfa1843657">min</a> (ctrl-&gt;wLength, (u16) 1);
+<a name="l01177"></a>01177                 }
+<a name="l01178"></a>01178                 <span class="keywordflow">break</span>;
+<a name="l01179"></a>01179 
+<a name="l01180"></a>01180         <span class="comment">/*</span>
+<a name="l01181"></a>01181 <span class="comment">         * These are the same vendor-specific requests supported by</span>
+<a name="l01182"></a>01182 <span class="comment">         * Intel's USB 2.0 compliance test devices.  We exceed that</span>
+<a name="l01183"></a>01183 <span class="comment">         * device spec by allowing multiple-packet requests.</span>
+<a name="l01184"></a>01184 <span class="comment">         */</span>
+<a name="l01185"></a>01185         <span class="keywordflow">case</span> 0x5b:      <span class="comment">/* control WRITE test -- fill the buffer */</span>
+<a name="l01186"></a>01186                 <span class="keywordflow">if</span> (ctrl-&gt;bRequestType != (USB_DIR_OUT|USB_TYPE_VENDOR))
+<a name="l01187"></a>01187                         <span class="keywordflow">goto</span> unknown;
+<a name="l01188"></a>01188                 <span class="keywordflow">if</span> (ctrl-&gt;wValue || ctrl-&gt;wIndex)
+<a name="l01189"></a>01189                         <span class="keywordflow">break</span>;
+<a name="l01190"></a>01190                 <span class="comment">/* just read that many bytes into the buffer */</span>
+<a name="l01191"></a>01191                 <span class="keywordflow">if</span> (ctrl-&gt;wLength &gt; USB_BUFSIZ)
+<a name="l01192"></a>01192                         <span class="keywordflow">break</span>;
+<a name="l01193"></a>01193                 value = ctrl-&gt;wLength;
+<a name="l01194"></a>01194                 <span class="keywordflow">break</span>;
+<a name="l01195"></a>01195         <span class="keywordflow">case</span> 0x5c:      <span class="comment">/* control READ test -- return the buffer */</span>
+<a name="l01196"></a>01196                 <span class="keywordflow">if</span> (ctrl-&gt;bRequestType != (USB_DIR_IN|USB_TYPE_VENDOR))
+<a name="l01197"></a>01197                         <span class="keywordflow">goto</span> unknown;
+<a name="l01198"></a>01198                 <span class="keywordflow">if</span> (ctrl-&gt;wValue || ctrl-&gt;wIndex)
+<a name="l01199"></a>01199                         <span class="keywordflow">break</span>;
+<a name="l01200"></a>01200                 <span class="comment">/* expect those bytes are still in the buffer; send back */</span>
+<a name="l01201"></a>01201                 <span class="keywordflow">if</span> (ctrl-&gt;wLength &gt; USB_BUFSIZ
+<a name="l01202"></a>01202                                 || ctrl-&gt;wLength != req-&gt;length)
+<a name="l01203"></a>01203                         <span class="keywordflow">break</span>;
+<a name="l01204"></a>01204                 value = ctrl-&gt;wLength;
+<a name="l01205"></a>01205                 <span class="keywordflow">break</span>;
+<a name="l01206"></a>01206 
+<a name="l01207"></a>01207         <span class="keywordflow">case</span> 0x01: <span class="comment">// SET_CUR</span>
+<a name="l01208"></a>01208         <span class="keywordflow">case</span> 0x02:
+<a name="l01209"></a>01209         <span class="keywordflow">case</span> 0x03:
+<a name="l01210"></a>01210         <span class="keywordflow">case</span> 0x04:
+<a name="l01211"></a>01211         <span class="keywordflow">case</span> 0x05:
+<a name="l01212"></a>01212                 value = ctrl-&gt;wLength;
+<a name="l01213"></a>01213                 <span class="keywordflow">break</span>;
+<a name="l01214"></a>01214         <span class="keywordflow">case</span> 0x81:
+<a name="l01215"></a>01215                 <span class="keywordflow">switch</span> (ctrl-&gt;wValue) {
+<a name="l01216"></a>01216                 <span class="keywordflow">case</span> 0x0201:
+<a name="l01217"></a>01217                 <span class="keywordflow">case</span> 0x0202:
+<a name="l01218"></a>01218                         ((u8*)req-&gt;buf)[0] = 0x00;
+<a name="l01219"></a>01219                         ((u8*)req-&gt;buf)[1] = 0xe3;
+<a name="l01220"></a>01220                         <span class="keywordflow">break</span>;
+<a name="l01221"></a>01221                 <span class="keywordflow">case</span> 0x0300:
+<a name="l01222"></a>01222                 <span class="keywordflow">case</span> 0x0500:
+<a name="l01223"></a>01223                         ((u8*)req-&gt;buf)[0] = 0x00;
+<a name="l01224"></a>01224                         <span class="keywordflow">break</span>;
+<a name="l01225"></a>01225                 }
+<a name="l01226"></a>01226                 <span class="comment">//((u8*)req-&gt;buf)[0] = 0x81;</span>
+<a name="l01227"></a>01227                 <span class="comment">//((u8*)req-&gt;buf)[1] = 0x81;</span>
+<a name="l01228"></a>01228                 value = ctrl-&gt;wLength;
+<a name="l01229"></a>01229                 <span class="keywordflow">break</span>;
+<a name="l01230"></a>01230         <span class="keywordflow">case</span> 0x82:
+<a name="l01231"></a>01231                 <span class="keywordflow">switch</span> (ctrl-&gt;wValue) {
+<a name="l01232"></a>01232                 <span class="keywordflow">case</span> 0x0201:
+<a name="l01233"></a>01233                 <span class="keywordflow">case</span> 0x0202:
+<a name="l01234"></a>01234                         ((u8*)req-&gt;buf)[0] = 0x00;
+<a name="l01235"></a>01235                         ((u8*)req-&gt;buf)[1] = 0xc3;
+<a name="l01236"></a>01236                         <span class="keywordflow">break</span>;
+<a name="l01237"></a>01237                 <span class="keywordflow">case</span> 0x0300:
+<a name="l01238"></a>01238                 <span class="keywordflow">case</span> 0x0500:
+<a name="l01239"></a>01239                         ((u8*)req-&gt;buf)[0] = 0x00;
+<a name="l01240"></a>01240                         <span class="keywordflow">break</span>;
+<a name="l01241"></a>01241                 }
+<a name="l01242"></a>01242                 <span class="comment">//((u8*)req-&gt;buf)[0] = 0x82;</span>
+<a name="l01243"></a>01243                 <span class="comment">//((u8*)req-&gt;buf)[1] = 0x82;</span>
+<a name="l01244"></a>01244                 value = ctrl-&gt;wLength;
+<a name="l01245"></a>01245                 <span class="keywordflow">break</span>;
+<a name="l01246"></a>01246         <span class="keywordflow">case</span> 0x83:
+<a name="l01247"></a>01247                 <span class="keywordflow">switch</span> (ctrl-&gt;wValue) {
+<a name="l01248"></a>01248                 <span class="keywordflow">case</span> 0x0201:
+<a name="l01249"></a>01249                 <span class="keywordflow">case</span> 0x0202:
+<a name="l01250"></a>01250                         ((u8*)req-&gt;buf)[0] = 0x00;
+<a name="l01251"></a>01251                         ((u8*)req-&gt;buf)[1] = 0x00;
+<a name="l01252"></a>01252                         <span class="keywordflow">break</span>;
+<a name="l01253"></a>01253                 <span class="keywordflow">case</span> 0x0300:
+<a name="l01254"></a>01254                         ((u8*)req-&gt;buf)[0] = 0x60;
+<a name="l01255"></a>01255                         <span class="keywordflow">break</span>;
+<a name="l01256"></a>01256                 <span class="keywordflow">case</span> 0x0500:    
+<a name="l01257"></a>01257                         ((u8*)req-&gt;buf)[0] = 0x18;
+<a name="l01258"></a>01258                         <span class="keywordflow">break</span>;
+<a name="l01259"></a>01259                 }
+<a name="l01260"></a>01260                 <span class="comment">//((u8*)req-&gt;buf)[0] = 0x83;</span>
+<a name="l01261"></a>01261                 <span class="comment">//((u8*)req-&gt;buf)[1] = 0x83;</span>
+<a name="l01262"></a>01262                 value = ctrl-&gt;wLength;
+<a name="l01263"></a>01263                 <span class="keywordflow">break</span>;
+<a name="l01264"></a>01264         <span class="keywordflow">case</span> 0x84:
+<a name="l01265"></a>01265                 <span class="keywordflow">switch</span> (ctrl-&gt;wValue) {
+<a name="l01266"></a>01266                 <span class="keywordflow">case</span> 0x0201:
+<a name="l01267"></a>01267                 <span class="keywordflow">case</span> 0x0202:
+<a name="l01268"></a>01268                         ((u8*)req-&gt;buf)[0] = 0x00;
+<a name="l01269"></a>01269                         ((u8*)req-&gt;buf)[1] = 0x01;
+<a name="l01270"></a>01270                         <span class="keywordflow">break</span>;
+<a name="l01271"></a>01271                 <span class="keywordflow">case</span> 0x0300:
+<a name="l01272"></a>01272                 <span class="keywordflow">case</span> 0x0500:
+<a name="l01273"></a>01273                         ((u8*)req-&gt;buf)[0] = 0x08;
+<a name="l01274"></a>01274                         <span class="keywordflow">break</span>;
+<a name="l01275"></a>01275                 }
+<a name="l01276"></a>01276                 <span class="comment">//((u8*)req-&gt;buf)[0] = 0x84;</span>
+<a name="l01277"></a>01277                 <span class="comment">//((u8*)req-&gt;buf)[1] = 0x84;</span>
+<a name="l01278"></a>01278                 value = ctrl-&gt;wLength;
+<a name="l01279"></a>01279                 <span class="keywordflow">break</span>;
+<a name="l01280"></a>01280         <span class="keywordflow">case</span> 0x85:
+<a name="l01281"></a>01281                 ((u8*)req-&gt;buf)[0] = 0x85;
+<a name="l01282"></a>01282                 ((u8*)req-&gt;buf)[1] = 0x85;
+<a name="l01283"></a>01283                 value = ctrl-&gt;wLength;
+<a name="l01284"></a>01284                 <span class="keywordflow">break</span>;
+<a name="l01285"></a>01285 
+<a name="l01286"></a>01286         
+<a name="l01287"></a>01287         <span class="keywordflow">default</span>:
+<a name="l01288"></a>01288 unknown:
+<a name="l01289"></a>01289                 printk(<span class="stringliteral">"unknown control req%02x.%02x v%04x i%04x l%d\n"</span>,
+<a name="l01290"></a>01290                         ctrl-&gt;bRequestType, ctrl-&gt;bRequest,
+<a name="l01291"></a>01291                         ctrl-&gt;wValue, ctrl-&gt;wIndex, ctrl-&gt;wLength);
+<a name="l01292"></a>01292         }
+<a name="l01293"></a>01293 
+<a name="l01294"></a>01294         <span class="comment">/* respond with data transfer before status phase? */</span>
+<a name="l01295"></a>01295         <span class="keywordflow">if</span> (value &gt;= 0) {
+<a name="l01296"></a>01296                 req-&gt;length = value;
+<a name="l01297"></a>01297                 req-&gt;zero = value &lt; ctrl-&gt;wLength
+<a name="l01298"></a>01298                                 &amp;&amp; (value % gadget-&gt;ep0-&gt;maxpacket) == 0;
+<a name="l01299"></a>01299                 value = usb_ep_queue (gadget-&gt;ep0, req, GFP_ATOMIC);
+<a name="l01300"></a>01300                 <span class="keywordflow">if</span> (value &lt; 0) {
+<a name="l01301"></a>01301                         DBG (dev, <span class="stringliteral">"ep_queue &lt; 0 --&gt; %d\n"</span>, value);
+<a name="l01302"></a>01302                         req-&gt;status = 0;
+<a name="l01303"></a>01303                         zero_setup_complete (gadget-&gt;ep0, req);
+<a name="l01304"></a>01304                 }
+<a name="l01305"></a>01305         }
+<a name="l01306"></a>01306 
+<a name="l01307"></a>01307         <span class="comment">/* device either stalls (value &lt; 0) or reports success */</span>
+<a name="l01308"></a>01308         <span class="keywordflow">return</span> value;
+<a name="l01309"></a>01309 }
+<a name="l01310"></a>01310 
+<a name="l01311"></a>01311 <span class="keyword">static</span> <span class="keywordtype">void</span>
+<a name="l01312"></a>01312 zero_disconnect (<span class="keyword">struct</span> usb_gadget *gadget)
+<a name="l01313"></a>01313 {
+<a name="l01314"></a>01314         <span class="keyword">struct </span><a class="code" href="structzero__dev.html">zero_dev</a>         *dev = get_gadget_data (gadget);
+<a name="l01315"></a>01315         <span class="keywordtype">unsigned</span> <span class="keywordtype">long</span>           flags;
+<a name="l01316"></a>01316 
+<a name="l01317"></a>01317         spin_lock_irqsave (&amp;dev-&gt;<a class="code" href="structzero__dev.html#712568d4b6a481845034ac6d87c0547d">lock</a>, flags);
+<a name="l01318"></a>01318         zero_reset_config (dev);
+<a name="l01319"></a>01319 
+<a name="l01320"></a>01320         <span class="comment">/* a more significant application might have some non-usb</span>
+<a name="l01321"></a>01321 <span class="comment">         * activities to quiesce here, saving resources like power</span>
+<a name="l01322"></a>01322 <span class="comment">         * or pushing the notification up a network stack.</span>
+<a name="l01323"></a>01323 <span class="comment">         */</span>
+<a name="l01324"></a>01324         spin_unlock_irqrestore (&amp;dev-&gt;<a class="code" href="structzero__dev.html#712568d4b6a481845034ac6d87c0547d">lock</a>, flags);
+<a name="l01325"></a>01325 
+<a name="l01326"></a>01326         <span class="comment">/* next we may get setup() calls to enumerate new connections;</span>
+<a name="l01327"></a>01327 <span class="comment">         * or an unbind() during shutdown (including removing module).</span>
+<a name="l01328"></a>01328 <span class="comment">         */</span>
+<a name="l01329"></a>01329 }
+<a name="l01330"></a>01330 
+<a name="l01331"></a>01331 <span class="keyword">static</span> <span class="keywordtype">void</span>
+<a name="l01332"></a>01332 zero_autoresume (<span class="keywordtype">unsigned</span> <span class="keywordtype">long</span> _dev)
+<a name="l01333"></a>01333 {
+<a name="l01334"></a>01334         <span class="keyword">struct </span><a class="code" href="structzero__dev.html">zero_dev</a> *dev = (<span class="keyword">struct </span><a class="code" href="structzero__dev.html">zero_dev</a> *) _dev;
+<a name="l01335"></a>01335         <span class="keywordtype">int</span>             status;
+<a name="l01336"></a>01336 
+<a name="l01337"></a>01337         <span class="comment">/* normally the host would be woken up for something</span>
+<a name="l01338"></a>01338 <span class="comment">         * more significant than just a timer firing...</span>
+<a name="l01339"></a>01339 <span class="comment">         */</span>
+<a name="l01340"></a>01340         <span class="keywordflow">if</span> (dev-&gt;<a class="code" href="structzero__dev.html#e0d019d6177afd1efa101aed63f1a174">gadget</a>-&gt;speed != USB_SPEED_UNKNOWN) {
+<a name="l01341"></a>01341                 status = usb_gadget_wakeup (dev-&gt;<a class="code" href="structzero__dev.html#e0d019d6177afd1efa101aed63f1a174">gadget</a>);
+<a name="l01342"></a>01342                 DBG (dev, <span class="stringliteral">"wakeup --&gt; %d\n"</span>, status);
+<a name="l01343"></a>01343         }
+<a name="l01344"></a>01344 }
+<a name="l01345"></a>01345 
+<a name="l01346"></a>01346 <span class="comment">/*-------------------------------------------------------------------------*/</span>
+<a name="l01347"></a>01347 
+<a name="l01348"></a>01348 <span class="keyword">static</span> <span class="keywordtype">void</span>
+<a name="l01349"></a>01349 zero_unbind (<span class="keyword">struct</span> usb_gadget *gadget)
+<a name="l01350"></a>01350 {
+<a name="l01351"></a>01351         <span class="keyword">struct </span><a class="code" href="structzero__dev.html">zero_dev</a>         *dev = get_gadget_data (gadget);
+<a name="l01352"></a>01352 
+<a name="l01353"></a>01353         DBG (dev, <span class="stringliteral">"unbind\n"</span>);
+<a name="l01354"></a>01354 
+<a name="l01355"></a>01355         <span class="comment">/* we've already been disconnected ... no i/o is active */</span>
+<a name="l01356"></a>01356         <span class="keywordflow">if</span> (dev-&gt;<a class="code" href="structzero__dev.html#7dad5245ef3701a5521638e2499ebfe9">req</a>)
+<a name="l01357"></a>01357                 free_ep_req (gadget-&gt;ep0, dev-&gt;<a class="code" href="structzero__dev.html#7dad5245ef3701a5521638e2499ebfe9">req</a>);
+<a name="l01358"></a>01358         del_timer_sync (&amp;dev-&gt;<a class="code" href="structzero__dev.html#5fcacdfb9a6b069c866d44d66dd566a4">resume</a>);
+<a name="l01359"></a>01359         kfree (dev);
+<a name="l01360"></a>01360         set_gadget_data (gadget, NULL);
+<a name="l01361"></a>01361 }
+<a name="l01362"></a>01362 
+<a name="l01363"></a>01363 <span class="keyword">static</span> <span class="keywordtype">int</span>
+<a name="l01364"></a>01364 zero_bind (<span class="keyword">struct</span> usb_gadget *gadget)
+<a name="l01365"></a>01365 {
+<a name="l01366"></a>01366         <span class="keyword">struct </span><a class="code" href="structzero__dev.html">zero_dev</a>         *dev;
+<a name="l01367"></a>01367         <span class="comment">//struct usb_ep         *ep;</span>
+<a name="l01368"></a>01368 
+<a name="l01369"></a>01369         printk(<span class="stringliteral">"binding\n"</span>);
+<a name="l01370"></a>01370         <span class="comment">/*</span>
+<a name="l01371"></a>01371 <span class="comment">         * DRIVER POLICY CHOICE:  you may want to do this differently.</span>
+<a name="l01372"></a>01372 <span class="comment">         * One thing to avoid is reusing a bcdDevice revision code</span>
+<a name="l01373"></a>01373 <span class="comment">         * with different host-visible configurations or behavior</span>
+<a name="l01374"></a>01374 <span class="comment">         * restrictions -- using ep1in/ep2out vs ep1out/ep3in, etc</span>
+<a name="l01375"></a>01375 <span class="comment">         */</span>
+<a name="l01376"></a>01376         <span class="comment">//device_desc.bcdDevice = __constant_cpu_to_le16 (0x0201);</span>
+<a name="l01377"></a>01377 
+<a name="l01378"></a>01378 
+<a name="l01379"></a>01379         <span class="comment">/* ok, we made sense of the hardware ... */</span>
+<a name="l01380"></a>01380         dev = kmalloc (<span class="keyword">sizeof</span> *dev, SLAB_KERNEL);
+<a name="l01381"></a>01381         <span class="keywordflow">if</span> (!dev)
+<a name="l01382"></a>01382                 <span class="keywordflow">return</span> -ENOMEM;
+<a name="l01383"></a>01383         memset (dev, 0, <span class="keyword">sizeof</span> *dev);
+<a name="l01384"></a>01384         spin_lock_init (&amp;dev-&gt;<a class="code" href="structzero__dev.html#712568d4b6a481845034ac6d87c0547d">lock</a>);
+<a name="l01385"></a>01385         dev-&gt;<a class="code" href="structzero__dev.html#e0d019d6177afd1efa101aed63f1a174">gadget</a> = gadget;
+<a name="l01386"></a>01386         set_gadget_data (gadget, dev);
+<a name="l01387"></a>01387 
+<a name="l01388"></a>01388         <span class="comment">/* preallocate control response and buffer */</span>
+<a name="l01389"></a>01389         dev-&gt;<a class="code" href="structzero__dev.html#7dad5245ef3701a5521638e2499ebfe9">req</a> = usb_ep_alloc_request (gadget-&gt;ep0, GFP_KERNEL);
+<a name="l01390"></a>01390         <span class="keywordflow">if</span> (!dev-&gt;<a class="code" href="structzero__dev.html#7dad5245ef3701a5521638e2499ebfe9">req</a>)
+<a name="l01391"></a>01391                 <span class="keywordflow">goto</span> enomem;
+<a name="l01392"></a>01392         dev-&gt;<a class="code" href="structzero__dev.html#7dad5245ef3701a5521638e2499ebfe9">req</a>-&gt;buf = usb_ep_alloc_buffer (gadget-&gt;ep0, USB_BUFSIZ,
+<a name="l01393"></a>01393                                 &amp;dev-&gt;<a class="code" href="structzero__dev.html#7dad5245ef3701a5521638e2499ebfe9">req</a>-&gt;dma, GFP_KERNEL);
+<a name="l01394"></a>01394         <span class="keywordflow">if</span> (!dev-&gt;<a class="code" href="structzero__dev.html#7dad5245ef3701a5521638e2499ebfe9">req</a>-&gt;buf)
+<a name="l01395"></a>01395                 <span class="keywordflow">goto</span> enomem;
+<a name="l01396"></a>01396 
+<a name="l01397"></a>01397         dev-&gt;<a class="code" href="structzero__dev.html#7dad5245ef3701a5521638e2499ebfe9">req</a>-&gt;complete = zero_setup_complete;
+<a name="l01398"></a>01398 
+<a name="l01399"></a>01399         device_desc.bMaxPacketSize0 = gadget-&gt;ep0-&gt;maxpacket;
+<a name="l01400"></a>01400 
+<a name="l01401"></a>01401 <span class="preprocessor">#ifdef CONFIG_USB_GADGET_DUALSPEED</span>
+<a name="l01402"></a>01402 <span class="preprocessor"></span>        <span class="comment">/* assume ep0 uses the same value for both speeds ... */</span>
+<a name="l01403"></a>01403         dev_qualifier.bMaxPacketSize0 = device_desc.bMaxPacketSize0;
+<a name="l01404"></a>01404 
+<a name="l01405"></a>01405         <span class="comment">/* and that all endpoints are dual-speed */</span>
+<a name="l01406"></a>01406         <span class="comment">//hs_source_desc.bEndpointAddress = fs_source_desc.bEndpointAddress;</span>
+<a name="l01407"></a>01407         <span class="comment">//hs_sink_desc.bEndpointAddress = fs_sink_desc.bEndpointAddress;</span>
+<a name="l01408"></a>01408 <span class="preprocessor">#endif</span>
+<a name="l01409"></a>01409 <span class="preprocessor"></span>
+<a name="l01410"></a>01410         usb_gadget_set_selfpowered (gadget);
+<a name="l01411"></a>01411 
+<a name="l01412"></a>01412         init_timer (&amp;dev-&gt;<a class="code" href="structzero__dev.html#5fcacdfb9a6b069c866d44d66dd566a4">resume</a>);
+<a name="l01413"></a>01413         dev-&gt;<a class="code" href="structzero__dev.html#5fcacdfb9a6b069c866d44d66dd566a4">resume</a>.function = zero_autoresume;
+<a name="l01414"></a>01414         dev-&gt;<a class="code" href="structzero__dev.html#5fcacdfb9a6b069c866d44d66dd566a4">resume</a>.data = (<span class="keywordtype">unsigned</span> long) dev;
+<a name="l01415"></a>01415 
+<a name="l01416"></a>01416         gadget-&gt;ep0-&gt;driver_data = dev;
+<a name="l01417"></a>01417 
+<a name="l01418"></a>01418         INFO (dev, <span class="stringliteral">"%s, version: "</span> DRIVER_VERSION <span class="stringliteral">"\n"</span>, longname);
+<a name="l01419"></a>01419         INFO (dev, <span class="stringliteral">"using %s, OUT %s IN %s\n"</span>, gadget-&gt;name,
+<a name="l01420"></a>01420                 EP_OUT_NAME, EP_IN_NAME);
+<a name="l01421"></a>01421 
+<a name="l01422"></a>01422         snprintf (manufacturer, <span class="keyword">sizeof</span> manufacturer,
+<a name="l01423"></a>01423                 UTS_SYSNAME <span class="stringliteral">" "</span> UTS_RELEASE <span class="stringliteral">" with %s"</span>,
+<a name="l01424"></a>01424                 gadget-&gt;name);
+<a name="l01425"></a>01425 
+<a name="l01426"></a>01426         <span class="keywordflow">return</span> 0;
+<a name="l01427"></a>01427 
+<a name="l01428"></a>01428 enomem:
+<a name="l01429"></a>01429         zero_unbind (gadget);
+<a name="l01430"></a>01430         <span class="keywordflow">return</span> -ENOMEM;
+<a name="l01431"></a>01431 }
+<a name="l01432"></a>01432 
+<a name="l01433"></a>01433 <span class="comment">/*-------------------------------------------------------------------------*/</span>
+<a name="l01434"></a>01434 
+<a name="l01435"></a>01435 <span class="keyword">static</span> <span class="keywordtype">void</span>
+<a name="l01436"></a>01436 zero_suspend (<span class="keyword">struct</span> usb_gadget *gadget)
+<a name="l01437"></a>01437 {
+<a name="l01438"></a>01438         <span class="keyword">struct </span><a class="code" href="structzero__dev.html">zero_dev</a>         *dev = get_gadget_data (gadget);
+<a name="l01439"></a>01439 
+<a name="l01440"></a>01440         <span class="keywordflow">if</span> (gadget-&gt;speed == USB_SPEED_UNKNOWN)
+<a name="l01441"></a>01441                 <span class="keywordflow">return</span>;
+<a name="l01442"></a>01442 
+<a name="l01443"></a>01443         <span class="keywordflow">if</span> (autoresume) {
+<a name="l01444"></a>01444                 mod_timer (&amp;dev-&gt;<a class="code" href="structzero__dev.html#5fcacdfb9a6b069c866d44d66dd566a4">resume</a>, jiffies + (HZ * autoresume));
+<a name="l01445"></a>01445                 DBG (dev, <span class="stringliteral">"suspend, wakeup in %d seconds\n"</span>, autoresume);
+<a name="l01446"></a>01446         } <span class="keywordflow">else</span>
+<a name="l01447"></a>01447                 DBG (dev, <span class="stringliteral">"suspend\n"</span>);
+<a name="l01448"></a>01448 }
+<a name="l01449"></a>01449 
+<a name="l01450"></a>01450 <span class="keyword">static</span> <span class="keywordtype">void</span>
+<a name="l01451"></a>01451 zero_resume (<span class="keyword">struct</span> usb_gadget *gadget)
+<a name="l01452"></a>01452 {
+<a name="l01453"></a>01453         <span class="keyword">struct </span><a class="code" href="structzero__dev.html">zero_dev</a>         *dev = get_gadget_data (gadget);
+<a name="l01454"></a>01454 
+<a name="l01455"></a>01455         DBG (dev, <span class="stringliteral">"resume\n"</span>);
+<a name="l01456"></a>01456         del_timer (&amp;dev-&gt;<a class="code" href="structzero__dev.html#5fcacdfb9a6b069c866d44d66dd566a4">resume</a>);
+<a name="l01457"></a>01457 }
+<a name="l01458"></a>01458 
+<a name="l01459"></a>01459 
+<a name="l01460"></a>01460 <span class="comment">/*-------------------------------------------------------------------------*/</span>
+<a name="l01461"></a>01461 
+<a name="l01462"></a>01462 <span class="keyword">static</span> <span class="keyword">struct </span>usb_gadget_driver zero_driver = {
+<a name="l01463"></a>01463 <span class="preprocessor">#ifdef CONFIG_USB_GADGET_DUALSPEED</span>
+<a name="l01464"></a>01464 <span class="preprocessor"></span>        .speed          = USB_SPEED_HIGH,
+<a name="l01465"></a>01465 <span class="preprocessor">#else</span>
+<a name="l01466"></a>01466 <span class="preprocessor"></span>        .speed          = USB_SPEED_FULL,
+<a name="l01467"></a>01467 <span class="preprocessor">#endif</span>
+<a name="l01468"></a>01468 <span class="preprocessor"></span>        .function       = (<span class="keywordtype">char</span> *) longname,
+<a name="l01469"></a>01469         .bind           = zero_bind,
+<a name="l01470"></a>01470         .unbind         = zero_unbind,
+<a name="l01471"></a>01471 
+<a name="l01472"></a>01472         .setup          = zero_setup,
+<a name="l01473"></a>01473         .disconnect     = zero_disconnect,
+<a name="l01474"></a>01474 
+<a name="l01475"></a>01475         .suspend        = zero_suspend,
+<a name="l01476"></a>01476         .resume         = zero_resume,
+<a name="l01477"></a>01477 
+<a name="l01478"></a>01478         .driver         = {
+<a name="l01479"></a>01479                 .name           = (<span class="keywordtype">char</span> *) shortname,
+<a name="l01480"></a>01480                 <span class="comment">// .shutdown = ...</span>
+<a name="l01481"></a>01481                 <span class="comment">// .suspend = ...</span>
+<a name="l01482"></a>01482                 <span class="comment">// .resume = ...</span>
+<a name="l01483"></a>01483         },
+<a name="l01484"></a>01484 };
+<a name="l01485"></a>01485 
+<a name="l01486"></a>01486 MODULE_AUTHOR (<span class="stringliteral">"David Brownell"</span>);
+<a name="l01487"></a>01487 MODULE_LICENSE (<span class="stringliteral">"Dual BSD/GPL"</span>);
+<a name="l01488"></a>01488 
+<a name="l01489"></a>01489 <span class="keyword">static</span> <span class="keyword">struct </span>proc_dir_entry *pdir, *pfile;
+<a name="l01490"></a>01490 
+<a name="l01491"></a>01491 <span class="keyword">static</span> <span class="keywordtype">int</span> isoc_read_data (<span class="keywordtype">char</span> *page, <span class="keywordtype">char</span> **start,
+<a name="l01492"></a>01492                            off_t off, <span class="keywordtype">int</span> count,
+<a name="l01493"></a>01493                            <span class="keywordtype">int</span> *eof, <span class="keywordtype">void</span> *data)
+<a name="l01494"></a>01494 {
+<a name="l01495"></a>01495         <span class="keywordtype">int</span> i;
+<a name="l01496"></a>01496         <span class="keyword">static</span> <span class="keywordtype">int</span> c = 0;
+<a name="l01497"></a>01497         <span class="keyword">static</span> <span class="keywordtype">int</span> done = 0;
+<a name="l01498"></a>01498         <span class="keyword">static</span> <span class="keywordtype">int</span> s = 0;
+<a name="l01499"></a>01499 
+<a name="l01500"></a>01500 <span class="comment">/*</span>
+<a name="l01501"></a>01501 <span class="comment">        printk ("\ncount: %d\n", count);</span>
+<a name="l01502"></a>01502 <span class="comment">        printk ("rbuf_start: %d\n", rbuf_start);</span>
+<a name="l01503"></a>01503 <span class="comment">        printk ("rbuf_len: %d\n", rbuf_len);</span>
+<a name="l01504"></a>01504 <span class="comment">        printk ("off: %d\n", off);</span>
+<a name="l01505"></a>01505 <span class="comment">        printk ("start: %p\n\n", *start);</span>
+<a name="l01506"></a>01506 <span class="comment">*/</span>
+<a name="l01507"></a>01507         <span class="keywordflow">if</span> (done) {
+<a name="l01508"></a>01508                 c = 0;
+<a name="l01509"></a>01509                 done = 0;
+<a name="l01510"></a>01510                 *eof = 1;
+<a name="l01511"></a>01511                 <span class="keywordflow">return</span> 0;
+<a name="l01512"></a>01512         }
+<a name="l01513"></a>01513 
+<a name="l01514"></a>01514         <span class="keywordflow">if</span> (c == 0) {
+<a name="l01515"></a>01515                 <span class="keywordflow">if</span> (rbuf_len == RBUF_LEN)
+<a name="l01516"></a>01516                         s = rbuf_start;
+<a name="l01517"></a>01517                 <span class="keywordflow">else</span> s = 0;
+<a name="l01518"></a>01518         }
+<a name="l01519"></a>01519 
+<a name="l01520"></a>01520         <span class="keywordflow">for</span> (i=0; i&lt;count &amp;&amp; c&lt;rbuf_len; i++, c++) {
+<a name="l01521"></a>01521                 page[i] = rbuf[(c+s) % RBUF_LEN];
+<a name="l01522"></a>01522         }
+<a name="l01523"></a>01523         *start = page;
+<a name="l01524"></a>01524         
+<a name="l01525"></a>01525         <span class="keywordflow">if</span> (c &gt;= rbuf_len) {
+<a name="l01526"></a>01526                 *eof = 1;
+<a name="l01527"></a>01527                 done = 1;
+<a name="l01528"></a>01528         }
+<a name="l01529"></a>01529 
+<a name="l01530"></a>01530 
+<a name="l01531"></a>01531         <span class="keywordflow">return</span> i;
+<a name="l01532"></a>01532 }
+<a name="l01533"></a>01533 
+<a name="l01534"></a>01534 <span class="keyword">static</span> <span class="keywordtype">int</span> __init init (<span class="keywordtype">void</span>)
+<a name="l01535"></a>01535 {
+<a name="l01536"></a>01536 
+<a name="l01537"></a>01537         <span class="keywordtype">int</span> retval = 0;
+<a name="l01538"></a>01538 
+<a name="l01539"></a>01539         pdir = proc_mkdir(<span class="stringliteral">"isoc_test"</span>, NULL);
+<a name="l01540"></a>01540         <span class="keywordflow">if</span>(pdir == NULL) {
+<a name="l01541"></a>01541                 retval = -ENOMEM;
+<a name="l01542"></a>01542                 printk(<span class="stringliteral">"Error creating dir\n"</span>);
+<a name="l01543"></a>01543                 <span class="keywordflow">goto</span> done;
+<a name="l01544"></a>01544         }
+<a name="l01545"></a>01545         pdir-&gt;owner = THIS_MODULE;
+<a name="l01546"></a>01546 
+<a name="l01547"></a>01547         pfile = create_proc_read_entry(<span class="stringliteral">"isoc_data"</span>,
+<a name="l01548"></a>01548                                        0444, pdir,
+<a name="l01549"></a>01549                                        isoc_read_data,
+<a name="l01550"></a>01550                                        NULL);
+<a name="l01551"></a>01551         <span class="keywordflow">if</span> (pfile == NULL) {
+<a name="l01552"></a>01552                 retval = -ENOMEM;
+<a name="l01553"></a>01553                 printk(<span class="stringliteral">"Error creating file\n"</span>);
+<a name="l01554"></a>01554                 <span class="keywordflow">goto</span> no_file;
+<a name="l01555"></a>01555         }
+<a name="l01556"></a>01556         pfile-&gt;owner = THIS_MODULE;
+<a name="l01557"></a>01557 
+<a name="l01558"></a>01558         <span class="keywordflow">return</span> <a class="code" href="dwc__otg__pcd__linux_8c.html#8c1ba129028b3b16909973eb30b85d2c">usb_gadget_register_driver</a> (&amp;zero_driver);
+<a name="l01559"></a>01559 
+<a name="l01560"></a>01560  no_file:
+<a name="l01561"></a>01561         remove_proc_entry(<span class="stringliteral">"isoc_data"</span>, NULL);
+<a name="l01562"></a>01562  done:
+<a name="l01563"></a>01563         <span class="keywordflow">return</span> retval;
+<a name="l01564"></a>01564 }
+<a name="l01565"></a>01565 module_init (init);
+<a name="l01566"></a>01566 
+<a name="l01567"></a>01567 <span class="keyword">static</span> <span class="keywordtype">void</span> __exit cleanup (<span class="keywordtype">void</span>)
+<a name="l01568"></a>01568 {
+<a name="l01569"></a>01569 
+<a name="l01570"></a>01570         <a class="code" href="dwc__otg__pcd__linux_8c.html#fa4a24d0806fbb6e3135d27d24a6a00d">usb_gadget_unregister_driver</a> (&amp;zero_driver);
+<a name="l01571"></a>01571         
+<a name="l01572"></a>01572         remove_proc_entry(<span class="stringliteral">"isoc_data"</span>, pdir);
+<a name="l01573"></a>01573         remove_proc_entry(<span class="stringliteral">"isoc_test"</span>, NULL);
+<a name="l01574"></a>01574 }
+<a name="l01575"></a>01575 module_exit (cleanup);
+</pre></div><hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/dwc__cfi__common_8h-source.html b/drivers/usb/host/dwc_otg/doc/html/dwc__cfi__common_8h-source.html
new file mode 100644
index 000000000000..d055a8e41284
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/dwc__cfi__common_8h-source.html
@@ -0,0 +1,115 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_cfi_common.h Source File</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<h1>dwc_cfi_common.h</h1><a href="dwc__cfi__common_8h.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">/* ==========================================================================</span>
+<a name="l00002"></a>00002 <span class="comment"> * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,</span>
+<a name="l00003"></a>00003 <span class="comment"> * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless</span>
+<a name="l00004"></a>00004 <span class="comment"> * otherwise expressly agreed to in writing between Synopsys and you.</span>
+<a name="l00005"></a>00005 <span class="comment"> * </span>
+<a name="l00006"></a>00006 <span class="comment"> * The Software IS NOT an item of Licensed Software or Licensed Product under</span>
+<a name="l00007"></a>00007 <span class="comment"> * any End User Software License Agreement or Agreement for Licensed Product</span>
+<a name="l00008"></a>00008 <span class="comment"> * with Synopsys or any supplement thereto. You are permitted to use and</span>
+<a name="l00009"></a>00009 <span class="comment"> * redistribute this Software in source and binary forms, with or without</span>
+<a name="l00010"></a>00010 <span class="comment"> * modification, provided that redistributions of source code must retain this</span>
+<a name="l00011"></a>00011 <span class="comment"> * notice. You may not view, use, disclose, copy or distribute this file or</span>
+<a name="l00012"></a>00012 <span class="comment"> * any information contained herein except pursuant to this license grant from</span>
+<a name="l00013"></a>00013 <span class="comment"> * Synopsys. If you do not agree with this notice, including the disclaimer</span>
+<a name="l00014"></a>00014 <span class="comment"> * below, then you are not authorized to use the Software.</span>
+<a name="l00015"></a>00015 <span class="comment"> * </span>
+<a name="l00016"></a>00016 <span class="comment"> * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS</span>
+<a name="l00017"></a>00017 <span class="comment"> * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE</span>
+<a name="l00018"></a>00018 <span class="comment"> * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE</span>
+<a name="l00019"></a>00019 <span class="comment"> * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,</span>
+<a name="l00020"></a>00020 <span class="comment"> * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES</span>
+<a name="l00021"></a>00021 <span class="comment"> * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR</span>
+<a name="l00022"></a>00022 <span class="comment"> * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER</span>
+<a name="l00023"></a>00023 <span class="comment"> * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT</span>
+<a name="l00024"></a>00024 <span class="comment"> * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY</span>
+<a name="l00025"></a>00025 <span class="comment"> * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH</span>
+<a name="l00026"></a>00026 <span class="comment"> * DAMAGE.</span>
+<a name="l00027"></a>00027 <span class="comment"> * ========================================================================== */</span>
+<a name="l00028"></a>00028 
+<a name="l00029"></a>00029 <span class="preprocessor">#if !defined(__DWC_CFI_COMMON_H__)</span>
+<a name="l00030"></a><a class="code" href="dwc__cfi__common_8h.html#50e76b6bdcb8e42b2b48aada9a1833e2">00030</a> <span class="preprocessor"></span><span class="preprocessor">#define __DWC_CFI_COMMON_H__</span>
+<a name="l00031"></a>00031 <span class="preprocessor"></span>
+<a name="l00032"></a>00032 <span class="comment">//#include &lt;linux/types.h&gt;</span>
+<a name="l00033"></a>00033 
+<a name="l00044"></a><a class="code" href="dwc__cfi__common_8h.html#b206fe3fb25aa96547a4bc0e47a864c6">00044</a> <span class="preprocessor">#define VEN_CORE_GET_FEATURES           0xB1</span>
+<a name="l00045"></a>00045 <span class="preprocessor"></span>
+<a name="l00047"></a><a class="code" href="dwc__cfi__common_8h.html#22bf207e476d086391240b18aacc0314">00047</a> <span class="preprocessor">#define VEN_CORE_GET_FEATURE            0xB2</span>
+<a name="l00048"></a>00048 <span class="preprocessor"></span>
+<a name="l00050"></a><a class="code" href="dwc__cfi__common_8h.html#ee7fb610a7fb2437df3425e2330e9d39">00050</a> <span class="preprocessor">#define VEN_CORE_SET_FEATURE            0xB3</span>
+<a name="l00051"></a>00051 <span class="preprocessor"></span>
+<a name="l00055"></a><a class="code" href="dwc__cfi__common_8h.html#f7551c9e324871e8258dacc4f4467846">00055</a> <span class="preprocessor">#define VEN_CORE_RESET_FEATURES         0xB4</span>
+<a name="l00056"></a>00056 <span class="preprocessor"></span>
+<a name="l00058"></a><a class="code" href="dwc__cfi__common_8h.html#1d1302d0d167f7c9580878fbfff847d4">00058</a> <span class="preprocessor">#define VEN_CORE_ACTIVATE_FEATURES      0xB5</span>
+<a name="l00059"></a>00059 <span class="preprocessor"></span>
+<a name="l00061"></a><a class="code" href="dwc__cfi__common_8h.html#8d4bf92524d3e5fd4b4b060fc1269ec6">00061</a> <span class="preprocessor">#define VEN_CORE_READ_REGISTER          0xB6</span>
+<a name="l00062"></a>00062 <span class="preprocessor"></span>
+<a name="l00064"></a><a class="code" href="dwc__cfi__common_8h.html#d132d545f74a408b62d44a34ba51426c">00064</a> <span class="preprocessor">#define VEN_CORE_WRITE_REGISTER         0xB7</span>
+<a name="l00065"></a>00065 <span class="preprocessor"></span>
+<a name="l00069"></a><a class="code" href="structcfi__all__features__header.html">00069</a> <span class="keyword">struct </span><a class="code" href="structcfi__all__features__header.html">cfi_all_features_header</a> {
+<a name="l00071"></a><a class="code" href="dwc__cfi__common_8h.html#b6c1d0a310ae1d0a89437b2cf92e57ba">00071</a> <span class="preprocessor">#define CFI_ALL_FEATURES_HDR_LEN                8</span>
+<a name="l00072"></a>00072 <span class="preprocessor"></span>
+<a name="l00075"></a><a class="code" href="structcfi__all__features__header.html#3973fa190311671de5bbd74a7b825f42">00075</a>         uint16_t <a class="code" href="structcfi__all__features__header.html#3973fa190311671de5bbd74a7b825f42">wTotalLen</a>;
+<a name="l00076"></a>00076 
+<a name="l00082"></a><a class="code" href="structcfi__all__features__header.html#3542d584c0c68a73351c7d2530f25c6d">00082</a>         uint16_t <a class="code" href="structcfi__all__features__header.html#3542d584c0c68a73351c7d2530f25c6d">wVersion</a>;
+<a name="l00083"></a>00083 
+<a name="l00085"></a><a class="code" href="structcfi__all__features__header.html#f6840858aad78617369b7decba6ef5e3">00085</a>         uint16_t <a class="code" href="structcfi__all__features__header.html#f6840858aad78617369b7decba6ef5e3">wCoreID</a>;
+<a name="l00086"></a><a class="code" href="dwc__cfi__common_8h.html#227fde38cd429d2ecaf3cd5bdd5d67d9">00086</a> <span class="preprocessor">#define CFI_CORE_ID_UDC         1</span>
+<a name="l00087"></a><a class="code" href="dwc__cfi__common_8h.html#4b0c4a003085148bef609d81fa3c1589">00087</a> <span class="preprocessor"></span><span class="preprocessor">#define CFI_CORE_ID_OTG         2</span>
+<a name="l00088"></a><a class="code" href="dwc__cfi__common_8h.html#b885f7a00a119d048803beaf41a5dc30">00088</a> <span class="preprocessor"></span><span class="preprocessor">#define CFI_CORE_ID_WUDEV       3</span>
+<a name="l00089"></a>00089 <span class="preprocessor"></span>
+<a name="l00091"></a><a class="code" href="structcfi__all__features__header.html#e7abb90105e5cfd6ddfe8ba5dfaf8fa1">00091</a>         uint16_t <a class="code" href="structcfi__all__features__header.html#e7abb90105e5cfd6ddfe8ba5dfaf8fa1">wNumFeatures</a>;
+<a name="l00092"></a>00092 } <a class="code" href="dwc__cfi__common_8h.html#ec5d43311fa60a5ef0519797208df057">UPACKED</a>;
+<a name="l00093"></a>00093 
+<a name="l00094"></a><a class="code" href="dwc__cfi__common_8h.html#23298b60a6c427f08efe303c0bb332f8">00094</a> <span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code" href="structcfi__all__features__header.html">cfi_all_features_header</a> <a class="code" href="dwc__cfi__common_8h.html#23298b60a6c427f08efe303c0bb332f8">cfi_all_features_header_t</a>;
+<a name="l00095"></a>00095 
+<a name="l00099"></a><a class="code" href="structcfi__feature__desc__header.html">00099</a> <span class="keyword">struct </span><a class="code" href="structcfi__feature__desc__header.html">cfi_feature_desc_header</a> {
+<a name="l00100"></a><a class="code" href="dwc__cfi__common_8h.html#7ec5e43b7d52a39b553fdfa8fb17d889">00100</a> <span class="preprocessor">#define CFI_FEATURE_DESC_HDR_LEN        8</span>
+<a name="l00101"></a>00101 <span class="preprocessor"></span>
+<a name="l00103"></a><a class="code" href="structcfi__feature__desc__header.html#f76e757383a5210368e599f872952170">00103</a>         uint16_t <a class="code" href="structcfi__feature__desc__header.html#f76e757383a5210368e599f872952170">wFeatureID</a>;
+<a name="l00104"></a>00104 
+<a name="l00108"></a><a class="code" href="structcfi__feature__desc__header.html#77769436c06687bdbe98c5e75e7641df">00108</a>         uint16_t <a class="code" href="structcfi__feature__desc__header.html#77769436c06687bdbe98c5e75e7641df">wLength</a>;
+<a name="l00109"></a>00109 
+<a name="l00111"></a><a class="code" href="structcfi__feature__desc__header.html#0f33193eaf5853b1d3454adce81105d4">00111</a>         uint16_t <a class="code" href="structcfi__feature__desc__header.html#0f33193eaf5853b1d3454adce81105d4">wDataLength</a>;
+<a name="l00112"></a>00112 
+<a name="l00119"></a><a class="code" href="structcfi__feature__desc__header.html#556f5723d7ed0a9c6a1260b1f2a3fd30">00119</a>         uint8_t <a class="code" href="structcfi__feature__desc__header.html#556f5723d7ed0a9c6a1260b1f2a3fd30">bmAttributes</a>;
+<a name="l00120"></a><a class="code" href="dwc__cfi__common_8h.html#45ffc2183d956983ca297033f9e527af">00120</a> <span class="preprocessor">#define CFI_FEATURE_ATTR_RO             1</span>
+<a name="l00121"></a><a class="code" href="dwc__cfi__common_8h.html#a4536fb9c1314c2f90a93cfcd082dbb9">00121</a> <span class="preprocessor"></span><span class="preprocessor">#define CFI_FEATURE_ATTR_RW             0</span>
+<a name="l00122"></a>00122 <span class="preprocessor"></span>
+<a name="l00124"></a><a class="code" href="structcfi__feature__desc__header.html#4e90b7a616a2efc24937fc6d5cff1347">00124</a>         uint8_t <a class="code" href="structcfi__feature__desc__header.html#4e90b7a616a2efc24937fc6d5cff1347">bNameLen</a>;
+<a name="l00125"></a>00125 
+<a name="l00127"></a>00127         <span class="comment">//uint8_t *name;</span>
+<a name="l00128"></a>00128 } <a class="code" href="dwc__cfi__common_8h.html#ec5d43311fa60a5ef0519797208df057">UPACKED</a>;
+<a name="l00129"></a>00129 
+<a name="l00130"></a><a class="code" href="dwc__cfi__common_8h.html#04466a29673dc59d190905db0db48266">00130</a> <span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code" href="structcfi__feature__desc__header.html">cfi_feature_desc_header</a> <a class="code" href="dwc__cfi__common_8h.html#04466a29673dc59d190905db0db48266">cfi_feature_desc_header_t</a>;
+<a name="l00131"></a>00131 
+<a name="l00136"></a><a class="code" href="structcfi__string.html">00136</a> <span class="keyword">struct </span><a class="code" href="structcfi__string.html">cfi_string</a> {
+<a name="l00137"></a><a class="code" href="structcfi__string.html#dc88ed81d4ff35c7a1c837708659afea">00137</a>         uint16_t <a class="code" href="structcfi__string.html#dc88ed81d4ff35c7a1c837708659afea">id</a>;
+<a name="l00138"></a><a class="code" href="structcfi__string.html#c852efd76029880787738fb474dd486e">00138</a>         <span class="keyword">const</span> uint8_t *<a class="code" href="structcfi__string.html#c852efd76029880787738fb474dd486e">s</a>;
+<a name="l00139"></a>00139 };
+<a name="l00140"></a><a class="code" href="dwc__cfi__common_8h.html#16bf31056d146243d486600ccbe8da85">00140</a> <span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code" href="structcfi__string.html">cfi_string</a> <a class="code" href="dwc__cfi__common_8h.html#16bf31056d146243d486600ccbe8da85">cfi_string_t</a>;
+<a name="l00141"></a>00141 
+<a name="l00142"></a>00142 <span class="preprocessor">#endif</span>
+</pre></div><hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/dwc__cfi__common_8h.html b/drivers/usb/host/dwc_otg/doc/html/dwc__cfi__common_8h.html
new file mode 100644
index 000000000000..d1e12d0d0dd8
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/dwc__cfi__common_8h.html
@@ -0,0 +1,119 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_cfi_common.h File Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<h1>dwc_cfi_common.h File Reference</h1>This file contains the CFI specific common constants, interfaces (functions and macros) and structures for Linux. <a href="#_details">More...</a>
+<p>
+
+<p>
+<a href="dwc__cfi__common_8h-source.html">Go to the source code of this file.</a><table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Structures</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcfi__all__features__header.html">cfi_all_features_header</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This structure is the header of the Core Features dataset returned to the Host.  <a href="structcfi__all__features__header.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcfi__feature__desc__header.html">cfi_feature_desc_header</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This structure is a header of the Core Feature descriptor dataset returned to the Host after the VEN_CORE_GET_FEATURES request.  <a href="structcfi__feature__desc__header.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcfi__string.html">cfi_string</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This structure describes a NULL terminated string referenced by its id field.  <a href="structcfi__string.html#_details">More...</a><br></td></tr>
+<tr><td colspan="2"><br><h2>Defines</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="50e76b6bdcb8e42b2b48aada9a1833e2"></a><!-- doxytag: member="dwc_cfi_common.h::__DWC_CFI_COMMON_H__" ref="50e76b6bdcb8e42b2b48aada9a1833e2" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__cfi__common_8h.html#50e76b6bdcb8e42b2b48aada9a1833e2">__DWC_CFI_COMMON_H__</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b206fe3fb25aa96547a4bc0e47a864c6"></a><!-- doxytag: member="dwc_cfi_common.h::VEN_CORE_GET_FEATURES" ref="b206fe3fb25aa96547a4bc0e47a864c6" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__cfi__common_8h.html#b206fe3fb25aa96547a4bc0e47a864c6">VEN_CORE_GET_FEATURES</a>&nbsp;&nbsp;&nbsp;0xB1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This is a request for all Core Features. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="22bf207e476d086391240b18aacc0314"></a><!-- doxytag: member="dwc_cfi_common.h::VEN_CORE_GET_FEATURE" ref="22bf207e476d086391240b18aacc0314" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__cfi__common_8h.html#22bf207e476d086391240b18aacc0314">VEN_CORE_GET_FEATURE</a>&nbsp;&nbsp;&nbsp;0xB2</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This is a request to get the value of a specific Core Feature. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ee7fb610a7fb2437df3425e2330e9d39"></a><!-- doxytag: member="dwc_cfi_common.h::VEN_CORE_SET_FEATURE" ref="ee7fb610a7fb2437df3425e2330e9d39" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__cfi__common_8h.html#ee7fb610a7fb2437df3425e2330e9d39">VEN_CORE_SET_FEATURE</a>&nbsp;&nbsp;&nbsp;0xB3</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This command allows the host to set the value of a specific Core Feature. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f7551c9e324871e8258dacc4f4467846"></a><!-- doxytag: member="dwc_cfi_common.h::VEN_CORE_RESET_FEATURES" ref="f7551c9e324871e8258dacc4f4467846" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__cfi__common_8h.html#f7551c9e324871e8258dacc4f4467846">VEN_CORE_RESET_FEATURES</a>&nbsp;&nbsp;&nbsp;0xB4</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This command allows the host to set the default values of either all or any specific Core Feature. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="1d1302d0d167f7c9580878fbfff847d4"></a><!-- doxytag: member="dwc_cfi_common.h::VEN_CORE_ACTIVATE_FEATURES" ref="1d1302d0d167f7c9580878fbfff847d4" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__cfi__common_8h.html#1d1302d0d167f7c9580878fbfff847d4">VEN_CORE_ACTIVATE_FEATURES</a>&nbsp;&nbsp;&nbsp;0xB5</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This command forces the PCD to write the deferred values of a Core Features. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="8d4bf92524d3e5fd4b4b060fc1269ec6"></a><!-- doxytag: member="dwc_cfi_common.h::VEN_CORE_READ_REGISTER" ref="8d4bf92524d3e5fd4b4b060fc1269ec6" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__cfi__common_8h.html#8d4bf92524d3e5fd4b4b060fc1269ec6">VEN_CORE_READ_REGISTER</a>&nbsp;&nbsp;&nbsp;0xB6</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This request reads a DWORD value from a register at the specified offset. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="d132d545f74a408b62d44a34ba51426c"></a><!-- doxytag: member="dwc_cfi_common.h::VEN_CORE_WRITE_REGISTER" ref="d132d545f74a408b62d44a34ba51426c" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__cfi__common_8h.html#d132d545f74a408b62d44a34ba51426c">VEN_CORE_WRITE_REGISTER</a>&nbsp;&nbsp;&nbsp;0xB7</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This request writes a DWORD value into a register at the specified offset. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b6c1d0a310ae1d0a89437b2cf92e57ba"></a><!-- doxytag: member="dwc_cfi_common.h::CFI_ALL_FEATURES_HDR_LEN" ref="b6c1d0a310ae1d0a89437b2cf92e57ba" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__cfi__common_8h.html#b6c1d0a310ae1d0a89437b2cf92e57ba">CFI_ALL_FEATURES_HDR_LEN</a>&nbsp;&nbsp;&nbsp;8</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">The features header structure length is. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="227fde38cd429d2ecaf3cd5bdd5d67d9"></a><!-- doxytag: member="dwc_cfi_common.h::CFI_CORE_ID_UDC" ref="227fde38cd429d2ecaf3cd5bdd5d67d9" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__cfi__common_8h.html#227fde38cd429d2ecaf3cd5bdd5d67d9">CFI_CORE_ID_UDC</a>&nbsp;&nbsp;&nbsp;1</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="4b0c4a003085148bef609d81fa3c1589"></a><!-- doxytag: member="dwc_cfi_common.h::CFI_CORE_ID_OTG" ref="4b0c4a003085148bef609d81fa3c1589" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__cfi__common_8h.html#4b0c4a003085148bef609d81fa3c1589">CFI_CORE_ID_OTG</a>&nbsp;&nbsp;&nbsp;2</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b885f7a00a119d048803beaf41a5dc30"></a><!-- doxytag: member="dwc_cfi_common.h::CFI_CORE_ID_WUDEV" ref="b885f7a00a119d048803beaf41a5dc30" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__cfi__common_8h.html#b885f7a00a119d048803beaf41a5dc30">CFI_CORE_ID_WUDEV</a>&nbsp;&nbsp;&nbsp;3</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7ec5e43b7d52a39b553fdfa8fb17d889"></a><!-- doxytag: member="dwc_cfi_common.h::CFI_FEATURE_DESC_HDR_LEN" ref="7ec5e43b7d52a39b553fdfa8fb17d889" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__cfi__common_8h.html#7ec5e43b7d52a39b553fdfa8fb17d889">CFI_FEATURE_DESC_HDR_LEN</a>&nbsp;&nbsp;&nbsp;8</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="45ffc2183d956983ca297033f9e527af"></a><!-- doxytag: member="dwc_cfi_common.h::CFI_FEATURE_ATTR_RO" ref="45ffc2183d956983ca297033f9e527af" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__cfi__common_8h.html#45ffc2183d956983ca297033f9e527af">CFI_FEATURE_ATTR_RO</a>&nbsp;&nbsp;&nbsp;1</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="a4536fb9c1314c2f90a93cfcd082dbb9"></a><!-- doxytag: member="dwc_cfi_common.h::CFI_FEATURE_ATTR_RW" ref="a4536fb9c1314c2f90a93cfcd082dbb9" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__cfi__common_8h.html#a4536fb9c1314c2f90a93cfcd082dbb9">CFI_FEATURE_ATTR_RW</a>&nbsp;&nbsp;&nbsp;0</td></tr>
+
+<tr><td colspan="2"><br><h2>Typedefs</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="23298b60a6c427f08efe303c0bb332f8"></a><!-- doxytag: member="dwc_cfi_common.h::cfi_all_features_header_t" ref="23298b60a6c427f08efe303c0bb332f8" args="" -->
+typedef <a class="el" href="structcfi__all__features__header.html">cfi_all_features_header</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__cfi__common_8h.html#23298b60a6c427f08efe303c0bb332f8">cfi_all_features_header_t</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="04466a29673dc59d190905db0db48266"></a><!-- doxytag: member="dwc_cfi_common.h::cfi_feature_desc_header_t" ref="04466a29673dc59d190905db0db48266" args="" -->
+typedef <a class="el" href="structcfi__feature__desc__header.html">cfi_feature_desc_header</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__cfi__common_8h.html#04466a29673dc59d190905db0db48266">cfi_feature_desc_header_t</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="16bf31056d146243d486600ccbe8da85"></a><!-- doxytag: member="dwc_cfi_common.h::cfi_string_t" ref="16bf31056d146243d486600ccbe8da85" args="" -->
+typedef <a class="el" href="structcfi__string.html">cfi_string</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__cfi__common_8h.html#16bf31056d146243d486600ccbe8da85">cfi_string_t</a></td></tr>
+
+<tr><td colspan="2"><br><h2>Variables</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ec5d43311fa60a5ef0519797208df057"></a><!-- doxytag: member="dwc_cfi_common.h::UPACKED" ref="ec5d43311fa60a5ef0519797208df057" args="" -->
+<a class="el" href="structcfi__all__features__header.html">cfi_all_features_header</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__cfi__common_8h.html#ec5d43311fa60a5ef0519797208df057">UPACKED</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This structure is the header of the Core Features dataset returned to the Host. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="6c83e2952dc5636d5cfc5336217dcfcd"></a><!-- doxytag: member="dwc_cfi_common.h::UPACKED" ref="6c83e2952dc5636d5cfc5336217dcfcd" args="" -->
+<a class="el" href="structcfi__feature__desc__header.html">cfi_feature_desc_header</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__cfi__common_8h.html#6c83e2952dc5636d5cfc5336217dcfcd">UPACKED</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This structure is a header of the Core Feature descriptor dataset returned to the Host after the VEN_CORE_GET_FEATURES request. <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This file contains the CFI specific common constants, interfaces (functions and macros) and structures for Linux. 
+<p>
+No PCD specific data structure or definition is to be included in this file. 
+<p>
+Definition in file <a class="el" href="dwc__cfi__common_8h-source.html">dwc_cfi_common.h</a>.<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/dwc__otg__attr_8c-source.html b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__attr_8c-source.html
new file mode 100644
index 000000000000..2602e5509a90
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__attr_8c-source.html
@@ -0,0 +1,828 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_attr.c Source File</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<h1>dwc_otg_attr.c</h1><a href="dwc__otg__attr_8c.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">/* ==========================================================================</span>
+<a name="l00002"></a>00002 <span class="comment"> * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.c $</span>
+<a name="l00003"></a>00003 <span class="comment"> * $Revision: #35 $</span>
+<a name="l00004"></a>00004 <span class="comment"> * $Date: 2009/04/03 $</span>
+<a name="l00005"></a>00005 <span class="comment"> * $Change: 1225160 $</span>
+<a name="l00006"></a>00006 <span class="comment"> *</span>
+<a name="l00007"></a>00007 <span class="comment"> * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,</span>
+<a name="l00008"></a>00008 <span class="comment"> * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless</span>
+<a name="l00009"></a>00009 <span class="comment"> * otherwise expressly agreed to in writing between Synopsys and you.</span>
+<a name="l00010"></a>00010 <span class="comment"> *</span>
+<a name="l00011"></a>00011 <span class="comment"> * The Software IS NOT an item of Licensed Software or Licensed Product under</span>
+<a name="l00012"></a>00012 <span class="comment"> * any End User Software License Agreement or Agreement for Licensed Product</span>
+<a name="l00013"></a>00013 <span class="comment"> * with Synopsys or any supplement thereto. You are permitted to use and</span>
+<a name="l00014"></a>00014 <span class="comment"> * redistribute this Software in source and binary forms, with or without</span>
+<a name="l00015"></a>00015 <span class="comment"> * modification, provided that redistributions of source code must retain this</span>
+<a name="l00016"></a>00016 <span class="comment"> * notice. You may not view, use, disclose, copy or distribute this file or</span>
+<a name="l00017"></a>00017 <span class="comment"> * any information contained herein except pursuant to this license grant from</span>
+<a name="l00018"></a>00018 <span class="comment"> * Synopsys. If you do not agree with this notice, including the disclaimer</span>
+<a name="l00019"></a>00019 <span class="comment"> * below, then you are not authorized to use the Software.</span>
+<a name="l00020"></a>00020 <span class="comment"> *</span>
+<a name="l00021"></a>00021 <span class="comment"> * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS</span>
+<a name="l00022"></a>00022 <span class="comment"> * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE</span>
+<a name="l00023"></a>00023 <span class="comment"> * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE</span>
+<a name="l00024"></a>00024 <span class="comment"> * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,</span>
+<a name="l00025"></a>00025 <span class="comment"> * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES</span>
+<a name="l00026"></a>00026 <span class="comment"> * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR</span>
+<a name="l00027"></a>00027 <span class="comment"> * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER</span>
+<a name="l00028"></a>00028 <span class="comment"> * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT</span>
+<a name="l00029"></a>00029 <span class="comment"> * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY</span>
+<a name="l00030"></a>00030 <span class="comment"> * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH</span>
+<a name="l00031"></a>00031 <span class="comment"> * DAMAGE.</span>
+<a name="l00032"></a>00032 <span class="comment"> * ========================================================================== */</span>
+<a name="l00033"></a>00033 
+<a name="l00286"></a>00286 <span class="preprocessor">#include &lt;linux/kernel.h&gt;</span>
+<a name="l00287"></a>00287 <span class="preprocessor">#include &lt;linux/module.h&gt;</span>
+<a name="l00288"></a>00288 <span class="preprocessor">#include &lt;linux/moduleparam.h&gt;</span>
+<a name="l00289"></a>00289 <span class="preprocessor">#include &lt;linux/init.h&gt;</span>
+<a name="l00290"></a>00290 <span class="preprocessor">#include &lt;linux/device.h&gt;</span>
+<a name="l00291"></a>00291 <span class="preprocessor">#include &lt;linux/errno.h&gt;</span>
+<a name="l00292"></a>00292 <span class="preprocessor">#include &lt;linux/types.h&gt;</span>
+<a name="l00293"></a>00293 <span class="preprocessor">#include &lt;linux/stat.h&gt;</span>         <span class="comment">/* permission constants */</span>
+<a name="l00294"></a>00294 <span class="preprocessor">#include &lt;linux/version.h&gt;</span>
+<a name="l00295"></a>00295 <span class="preprocessor">#include &lt;linux/param.h&gt;</span>
+<a name="l00296"></a>00296 <span class="preprocessor">#include &lt;linux/delay.h&gt;</span>
+<a name="l00297"></a>00297 <span class="preprocessor">#include &lt;linux/jiffies.h&gt;</span>
+<a name="l00298"></a>00298 
+<a name="l00299"></a>00299 
+<a name="l00300"></a>00300 <span class="preprocessor">#ifdef LM_INTERFACE</span>
+<a name="l00301"></a>00301 <span class="preprocessor"></span><span class="preprocessor">#include &lt;asm/sizes.h&gt;</span>
+<a name="l00302"></a>00302 <span class="preprocessor">#include &lt;asm/arch/lm.h&gt;</span>
+<a name="l00303"></a>00303 <span class="preprocessor">#endif</span>
+<a name="l00304"></a>00304 <span class="preprocessor"></span>
+<a name="l00305"></a>00305 <span class="preprocessor">#include &lt;asm/io.h&gt;</span>
+<a name="l00306"></a>00306 
+<a name="l00307"></a>00307 <span class="preprocessor">#include "dwc_os.h"</span>
+<a name="l00308"></a>00308 <span class="preprocessor">#include "<a class="code" href="dwc__otg__driver_8h.html">dwc_otg_driver.h</a>"</span>
+<a name="l00309"></a>00309 <span class="preprocessor">#include "<a class="code" href="dwc__otg__attr_8h.html">dwc_otg_attr.h</a>"</span>
+<a name="l00310"></a>00310 <span class="preprocessor">#include "<a class="code" href="dwc__otg__core__if_8h.html">dwc_otg_core_if.h</a>"</span>
+<a name="l00311"></a>00311 <span class="preprocessor">#include "<a class="code" href="dwc__otg__pcd__if_8h.html">dwc_otg_pcd_if.h</a>"</span>
+<a name="l00312"></a>00312 <span class="preprocessor">#include "<a class="code" href="dwc__otg__hcd__if_8h.html">dwc_otg_hcd_if.h</a>"</span>
+<a name="l00313"></a>00313 
+<a name="l00314"></a>00314 <span class="comment">/*</span>
+<a name="l00315"></a>00315 <span class="comment"> * MACROs for defining sysfs attribute</span>
+<a name="l00316"></a>00316 <span class="comment"> */</span>
+<a name="l00317"></a>00317 <span class="preprocessor">#ifdef LM_INTERFACE</span>
+<a name="l00318"></a>00318 <span class="preprocessor"></span>
+<a name="l00319"></a>00319 <span class="preprocessor">#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \</span>
+<a name="l00320"></a>00320 <span class="preprocessor">static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \</span>
+<a name="l00321"></a>00321 <span class="preprocessor">{ \</span>
+<a name="l00322"></a>00322 <span class="preprocessor">        struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \</span>
+<a name="l00323"></a>00323 <span class="preprocessor">        dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);             \</span>
+<a name="l00324"></a>00324 <span class="preprocessor">        uint32_t val; \</span>
+<a name="l00325"></a>00325 <span class="preprocessor">        val = dwc_otg_get_##_otg_attr_name_ (otg_dev-&gt;core_if); \</span>
+<a name="l00326"></a>00326 <span class="preprocessor">        return sprintf (buf, "%s = 0x%x\n", _string_, val); \</span>
+<a name="l00327"></a>00327 <span class="preprocessor">}</span>
+<a name="l00328"></a>00328 <span class="preprocessor"></span><span class="preprocessor">#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \</span>
+<a name="l00329"></a>00329 <span class="preprocessor">static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \</span>
+<a name="l00330"></a>00330 <span class="preprocessor">                                        const char *buf, size_t count) \</span>
+<a name="l00331"></a>00331 <span class="preprocessor">{ \</span>
+<a name="l00332"></a>00332 <span class="preprocessor">        struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \</span>
+<a name="l00333"></a>00333 <span class="preprocessor">        dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \</span>
+<a name="l00334"></a>00334 <span class="preprocessor">        uint32_t set = simple_strtoul(buf, NULL, 16); \</span>
+<a name="l00335"></a>00335 <span class="preprocessor">        dwc_otg_set_##_otg_attr_name_(otg_dev-&gt;core_if, set);\</span>
+<a name="l00336"></a>00336 <span class="preprocessor">        return count; \</span>
+<a name="l00337"></a>00337 <span class="preprocessor">}</span>
+<a name="l00338"></a>00338 <span class="preprocessor"></span>
+<a name="l00339"></a>00339 <span class="preprocessor">#elif PCI_INTERFACE</span>
+<a name="l00340"></a>00340 <span class="preprocessor"></span>
+<a name="l00341"></a>00341 <span class="preprocessor">#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \</span>
+<a name="l00342"></a>00342 <span class="preprocessor">static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \</span>
+<a name="l00343"></a>00343 <span class="preprocessor">{ \</span>
+<a name="l00344"></a>00344 <span class="preprocessor">        dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);      \</span>
+<a name="l00345"></a>00345 <span class="preprocessor">        uint32_t val; \</span>
+<a name="l00346"></a>00346 <span class="preprocessor">        val = dwc_otg_get_##_otg_attr_name_ (otg_dev-&gt;core_if); \</span>
+<a name="l00347"></a>00347 <span class="preprocessor">        return sprintf (buf, "%s = 0x%x\n", _string_, val); \</span>
+<a name="l00348"></a>00348 <span class="preprocessor">}</span>
+<a name="l00349"></a>00349 <span class="preprocessor"></span><span class="preprocessor">#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \</span>
+<a name="l00350"></a>00350 <span class="preprocessor">static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \</span>
+<a name="l00351"></a>00351 <span class="preprocessor">                                        const char *buf, size_t count) \</span>
+<a name="l00352"></a>00352 <span class="preprocessor">{ \</span>
+<a name="l00353"></a>00353 <span class="preprocessor">        dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);  \</span>
+<a name="l00354"></a>00354 <span class="preprocessor">        uint32_t set = simple_strtoul(buf, NULL, 16); \</span>
+<a name="l00355"></a>00355 <span class="preprocessor">        dwc_otg_set_##_otg_attr_name_(otg_dev-&gt;core_if, set);\</span>
+<a name="l00356"></a>00356 <span class="preprocessor">        return count; \</span>
+<a name="l00357"></a>00357 <span class="preprocessor">}</span>
+<a name="l00358"></a>00358 <span class="preprocessor"></span>
+<a name="l00359"></a>00359 <span class="preprocessor">#endif</span>
+<a name="l00360"></a>00360 <span class="preprocessor"></span>
+<a name="l00361"></a>00361 <span class="comment">/*</span>
+<a name="l00362"></a>00362 <span class="comment"> * MACROs for defining sysfs attribute for 32-bit registers</span>
+<a name="l00363"></a>00363 <span class="comment"> */</span>
+<a name="l00364"></a>00364 <span class="preprocessor">#ifdef LM_INTERFACE</span>
+<a name="l00365"></a>00365 <span class="preprocessor"></span><span class="preprocessor">#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \</span>
+<a name="l00366"></a>00366 <span class="preprocessor">static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \</span>
+<a name="l00367"></a>00367 <span class="preprocessor">{ \</span>
+<a name="l00368"></a>00368 <span class="preprocessor">        struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \</span>
+<a name="l00369"></a>00369 <span class="preprocessor">        dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \</span>
+<a name="l00370"></a>00370 <span class="preprocessor">        uint32_t val; \</span>
+<a name="l00371"></a>00371 <span class="preprocessor">        val = dwc_otg_get_##_otg_attr_name_ (otg_dev-&gt;core_if); \</span>
+<a name="l00372"></a>00372 <span class="preprocessor">        return sprintf (buf, "%s = 0x%08x\n", _string_, val); \</span>
+<a name="l00373"></a>00373 <span class="preprocessor">}</span>
+<a name="l00374"></a>00374 <span class="preprocessor"></span><span class="preprocessor">#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \</span>
+<a name="l00375"></a>00375 <span class="preprocessor">static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \</span>
+<a name="l00376"></a>00376 <span class="preprocessor">                                        const char *buf, size_t count) \</span>
+<a name="l00377"></a>00377 <span class="preprocessor">{ \</span>
+<a name="l00378"></a>00378 <span class="preprocessor">        struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \</span>
+<a name="l00379"></a>00379 <span class="preprocessor">        dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \</span>
+<a name="l00380"></a>00380 <span class="preprocessor">        uint32_t val = simple_strtoul(buf, NULL, 16); \</span>
+<a name="l00381"></a>00381 <span class="preprocessor">        dwc_otg_set_##_otg_attr_name_ (otg_dev-&gt;core_if, val); \</span>
+<a name="l00382"></a>00382 <span class="preprocessor">        return count; \</span>
+<a name="l00383"></a>00383 <span class="preprocessor">}</span>
+<a name="l00384"></a>00384 <span class="preprocessor"></span><span class="preprocessor">#elif PCI_INTERFACE</span>
+<a name="l00385"></a>00385 <span class="preprocessor"></span><span class="preprocessor">#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \</span>
+<a name="l00386"></a>00386 <span class="preprocessor">static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \</span>
+<a name="l00387"></a>00387 <span class="preprocessor">{ \</span>
+<a name="l00388"></a>00388 <span class="preprocessor">        dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);  \</span>
+<a name="l00389"></a>00389 <span class="preprocessor">        uint32_t val; \</span>
+<a name="l00390"></a>00390 <span class="preprocessor">        val = dwc_otg_get_##_otg_attr_name_ (otg_dev-&gt;core_if); \</span>
+<a name="l00391"></a>00391 <span class="preprocessor">        return sprintf (buf, "%s = 0x%08x\n", _string_, val); \</span>
+<a name="l00392"></a>00392 <span class="preprocessor">}</span>
+<a name="l00393"></a>00393 <span class="preprocessor"></span><span class="preprocessor">#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \</span>
+<a name="l00394"></a>00394 <span class="preprocessor">static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \</span>
+<a name="l00395"></a>00395 <span class="preprocessor">                                        const char *buf, size_t count) \</span>
+<a name="l00396"></a>00396 <span class="preprocessor">{ \</span>
+<a name="l00397"></a>00397 <span class="preprocessor">        dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);  \</span>
+<a name="l00398"></a>00398 <span class="preprocessor">        uint32_t val = simple_strtoul(buf, NULL, 16); \</span>
+<a name="l00399"></a>00399 <span class="preprocessor">        dwc_otg_set_##_otg_attr_name_ (otg_dev-&gt;core_if, val); \</span>
+<a name="l00400"></a>00400 <span class="preprocessor">        return count; \</span>
+<a name="l00401"></a>00401 <span class="preprocessor">}</span>
+<a name="l00402"></a>00402 <span class="preprocessor"></span>
+<a name="l00403"></a>00403 <span class="preprocessor">#endif</span>
+<a name="l00404"></a>00404 <span class="preprocessor"></span>
+<a name="l00405"></a><a class="code" href="dwc__otg__attr_8c.html#91eb9b8ec6d56698f0b6f4934573a41e">00405</a> <span class="preprocessor">#define DWC_OTG_DEVICE_ATTR_BITFIELD_RW(_otg_attr_name_,_string_) \</span>
+<a name="l00406"></a>00406 <span class="preprocessor">DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \</span>
+<a name="l00407"></a>00407 <span class="preprocessor">DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \</span>
+<a name="l00408"></a>00408 <span class="preprocessor">DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);</span>
+<a name="l00409"></a>00409 <span class="preprocessor"></span>
+<a name="l00410"></a><a class="code" href="dwc__otg__attr_8c.html#9bf160f54b6a1da72d213aa1aebfb444">00410</a> <span class="preprocessor">#define DWC_OTG_DEVICE_ATTR_BITFIELD_RO(_otg_attr_name_,_string_) \</span>
+<a name="l00411"></a>00411 <span class="preprocessor">DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \</span>
+<a name="l00412"></a>00412 <span class="preprocessor">DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);</span>
+<a name="l00413"></a>00413 <span class="preprocessor"></span>
+<a name="l00414"></a><a class="code" href="dwc__otg__attr_8c.html#b7106ee2e9d5f335e6c49013ca789467">00414</a> <span class="preprocessor">#define DWC_OTG_DEVICE_ATTR_REG32_RW(_otg_attr_name_,_addr_,_string_) \</span>
+<a name="l00415"></a>00415 <span class="preprocessor">DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \</span>
+<a name="l00416"></a>00416 <span class="preprocessor">DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \</span>
+<a name="l00417"></a>00417 <span class="preprocessor">DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);</span>
+<a name="l00418"></a>00418 <span class="preprocessor"></span>
+<a name="l00419"></a><a class="code" href="dwc__otg__attr_8c.html#471f9d3f4b4aa45b59be200e1b3beb87">00419</a> <span class="preprocessor">#define DWC_OTG_DEVICE_ATTR_REG32_RO(_otg_attr_name_,_addr_,_string_) \</span>
+<a name="l00420"></a>00420 <span class="preprocessor">DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \</span>
+<a name="l00421"></a>00421 <span class="preprocessor">DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);</span>
+<a name="l00422"></a>00422 <span class="preprocessor"></span>
+<a name="l00429"></a><a class="code" href="dwc__otg__attr_8c.html#ca58f009788e262a917c23784a84cb16">00429</a> <span class="keyword">static</span> ssize_t <a class="code" href="dwc__otg__attr_8c.html#a7cbb871229310176b4388cbf3f2e353">regoffset_show</a>(<span class="keyword">struct</span> device *_dev,
+<a name="l00430"></a>00430                               <span class="keyword">struct</span> device_attribute *attr, <span class="keywordtype">char</span> *buf)
+<a name="l00431"></a>00431 {
+<a name="l00432"></a>00432 <span class="preprocessor">#ifdef LM_INTERFACE</span>
+<a name="l00433"></a>00433 <span class="preprocessor"></span>        <span class="keyword">struct </span>lm_device *lm_dev = container_of(_dev, <span class="keyword">struct</span> lm_device, dev);
+<a name="l00434"></a>00434         <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = lm_get_drvdata(lm_dev);
+<a name="l00435"></a>00435 <span class="preprocessor">#elif PCI_INTERFACE</span>
+<a name="l00436"></a>00436 <span class="preprocessor"></span>        <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = dev_get_drvdata(_dev);
+<a name="l00437"></a>00437 <span class="preprocessor">#endif</span>
+<a name="l00438"></a>00438 <span class="preprocessor"></span>
+<a name="l00439"></a>00439         <span class="keywordflow">return</span> snprintf(buf, <span class="keyword">sizeof</span>(<span class="stringliteral">"0xFFFFFFFF\n"</span>) + 1, <span class="stringliteral">"0x%08x\n"</span>,
+<a name="l00440"></a>00440                         otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#d2701bc8589613bec5074968e57ce6ef">reg_offset</a>);
+<a name="l00441"></a>00441 }
+<a name="l00442"></a>00442 
+<a name="l00446"></a><a class="code" href="dwc__otg__attr_8c.html#fc5be3dbcd075f5087ca1730661c5dc2">00446</a> <span class="keyword">static</span> ssize_t <a class="code" href="dwc__otg__attr_8c.html#fede01598333be19cc7d8787aa05cfdf">regoffset_store</a>(<span class="keyword">struct</span> device *_dev,
+<a name="l00447"></a>00447                                <span class="keyword">struct</span> device_attribute *attr,
+<a name="l00448"></a>00448                                <span class="keyword">const</span> <span class="keywordtype">char</span> *buf, size_t count)
+<a name="l00449"></a>00449 {
+<a name="l00450"></a>00450 <span class="preprocessor">#ifdef LM_INTERFACE</span>
+<a name="l00451"></a>00451 <span class="preprocessor"></span>        <span class="keyword">struct </span>lm_device *lm_dev = container_of(_dev, <span class="keyword">struct</span> lm_device, dev);
+<a name="l00452"></a>00452         <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = lm_get_drvdata(lm_dev);
+<a name="l00453"></a>00453 <span class="preprocessor">#elif PCI_INTERFACE</span>
+<a name="l00454"></a>00454 <span class="preprocessor"></span>        <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = dev_get_drvdata(_dev);
+<a name="l00455"></a>00455 <span class="preprocessor">#endif</span>
+<a name="l00456"></a>00456 <span class="preprocessor"></span>
+<a name="l00457"></a>00457         uint32_t offset = simple_strtoul(buf, NULL, 16);
+<a name="l00458"></a>00458 <span class="preprocessor">#ifdef LM_INTERFACE</span>
+<a name="l00459"></a>00459 <span class="preprocessor"></span>        <span class="keywordflow">if</span> (offset &lt; SZ_256K) {
+<a name="l00460"></a>00460 <span class="preprocessor">#elif  PCI_INTERFACE</span>
+<a name="l00461"></a>00461 <span class="preprocessor"></span>        <span class="keywordflow">if</span> (offset &lt; 0x00040000) {
+<a name="l00462"></a>00462 <span class="preprocessor">#endif</span>
+<a name="l00463"></a>00463 <span class="preprocessor"></span>                otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#d2701bc8589613bec5074968e57ce6ef">reg_offset</a> = offset;
+<a name="l00464"></a>00464         } <span class="keywordflow">else</span> {
+<a name="l00465"></a>00465                 dev_err(_dev, <span class="stringliteral">"invalid offset\n"</span>);
+<a name="l00466"></a>00466         }
+<a name="l00467"></a>00467 
+<a name="l00468"></a><a class="code" href="dwc__otg__attr_8c.html#ac2308832629daf78cb9dd123551cd8a">00468</a>         <span class="keywordflow">return</span> count;
+<a name="l00469"></a>00469 }
+<a name="l00470"></a>00470 
+<a name="l00471"></a>00471 DEVICE_ATTR(<a class="code" href="dwc__otg__attr_8c.html#aeabf3d18b9b521d65b364cec3dcde45">regoffset</a>, S_IRUGO | <a class="code" href="dwc__otg__attr_8c.html#ac2308832629daf78cb9dd123551cd8a">S_IWUSR</a>, <a class="code" href="dwc__otg__attr_8c.html#a7cbb871229310176b4388cbf3f2e353">regoffset_show</a>, <a class="code" href="dwc__otg__attr_8c.html#fede01598333be19cc7d8787aa05cfdf">regoffset_store</a>);
+<a name="l00472"></a>00472 
+<a name="l00477"></a><a class="code" href="dwc__otg__attr_8c.html#bb38eb60bd43b1de364db80fd1bcdbcf">00477</a> <span class="keyword">static</span> ssize_t <a class="code" href="dwc__otg__attr_8c.html#d88d7abccfb5b9f0e2c9461a4c950114">regvalue_show</a>(<span class="keyword">struct</span> device *_dev,
+<a name="l00478"></a>00478                              <span class="keyword">struct</span> device_attribute *attr, <span class="keywordtype">char</span> *buf)
+<a name="l00479"></a>00479 {
+<a name="l00480"></a>00480 <span class="preprocessor">#ifdef LM_INTERFACE</span>
+<a name="l00481"></a>00481 <span class="preprocessor"></span>        <span class="keyword">struct </span>lm_device *lm_dev = container_of(_dev, <span class="keyword">struct</span> lm_device, dev);
+<a name="l00482"></a>00482         <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = lm_get_drvdata(lm_dev);
+<a name="l00483"></a>00483 <span class="preprocessor">#elif PCI_INTERFACE</span>
+<a name="l00484"></a>00484 <span class="preprocessor"></span>        <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = dev_get_drvdata(_dev);
+<a name="l00485"></a>00485 <span class="preprocessor">#endif</span>
+<a name="l00486"></a>00486 <span class="preprocessor"></span>
+<a name="l00487"></a>00487         uint32_t val;
+<a name="l00488"></a>00488         <span class="keyword">volatile</span> uint32_t *addr;
+<a name="l00489"></a>00489 
+<a name="l00490"></a>00490         <span class="keywordflow">if</span> (otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#d2701bc8589613bec5074968e57ce6ef">reg_offset</a> != 0xFFFFFFFF &amp;&amp; 0 != otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#ed96ed1109175f87fd83fa32a9c2c6fa">base</a>) {
+<a name="l00491"></a>00491                 <span class="comment">/* Calculate the address */</span>
+<a name="l00492"></a>00492                 addr = (uint32_t *) (otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#d2701bc8589613bec5074968e57ce6ef">reg_offset</a> +
+<a name="l00493"></a>00493                                      (uint8_t *) otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#ed96ed1109175f87fd83fa32a9c2c6fa">base</a>);
+<a name="l00494"></a>00494                 val = dwc_read_reg32(addr);
+<a name="l00495"></a>00495                 <span class="keywordflow">return</span> snprintf(buf,
+<a name="l00496"></a>00496                                 <span class="keyword">sizeof</span>(<span class="stringliteral">"Reg@0xFFFFFFFF = 0xFFFFFFFF\n"</span>) + 1,
+<a name="l00497"></a>00497                                 <span class="stringliteral">"Reg@0x%06x = 0x%08x\n"</span>, otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#d2701bc8589613bec5074968e57ce6ef">reg_offset</a>,
+<a name="l00498"></a>00498                                 val);
+<a name="l00499"></a>00499         } <span class="keywordflow">else</span> {
+<a name="l00500"></a>00500                 dev_err(_dev, <span class="stringliteral">"Invalid offset (0x%0x)\n"</span>, otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#d2701bc8589613bec5074968e57ce6ef">reg_offset</a>);
+<a name="l00501"></a>00501                 <span class="keywordflow">return</span> sprintf(buf, <span class="stringliteral">"invalid offset\n"</span>);
+<a name="l00502"></a>00502         }
+<a name="l00503"></a>00503 }
+<a name="l00504"></a>00504 
+<a name="l00510"></a><a class="code" href="dwc__otg__attr_8c.html#7db6b85ac60be49f52987e615a01408b">00510</a> <span class="keyword">static</span> ssize_t <a class="code" href="dwc__otg__attr_8c.html#decb71de8ca4344042f5230b8fdadc86">regvalue_store</a>(<span class="keyword">struct</span> device *_dev,
+<a name="l00511"></a>00511                               <span class="keyword">struct</span> device_attribute *attr,
+<a name="l00512"></a>00512                               <span class="keyword">const</span> <span class="keywordtype">char</span> *buf, size_t count)
+<a name="l00513"></a>00513 {
+<a name="l00514"></a>00514 <span class="preprocessor">#ifdef LM_INTERFACE</span>
+<a name="l00515"></a>00515 <span class="preprocessor"></span>        <span class="keyword">struct </span>lm_device *lm_dev = container_of(_dev, <span class="keyword">struct</span> lm_device, dev);
+<a name="l00516"></a>00516         <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = lm_get_drvdata(lm_dev);
+<a name="l00517"></a>00517 <span class="preprocessor">#elif PCI_INTERFACE</span>
+<a name="l00518"></a>00518 <span class="preprocessor"></span>        <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = dev_get_drvdata(_dev);
+<a name="l00519"></a>00519 <span class="preprocessor">#endif</span>
+<a name="l00520"></a>00520 <span class="preprocessor"></span>
+<a name="l00521"></a>00521         <span class="keyword">volatile</span> uint32_t *addr;
+<a name="l00522"></a>00522         uint32_t val = simple_strtoul(buf, NULL, 16);
+<a name="l00523"></a>00523         <span class="comment">//dev_dbg(_dev, "Offset=0x%08x Val=0x%08x\n", otg_dev-&gt;reg_offset, val);</span>
+<a name="l00524"></a>00524         <span class="keywordflow">if</span> (otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#d2701bc8589613bec5074968e57ce6ef">reg_offset</a> != 0xFFFFFFFF &amp;&amp; 0 != otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#ed96ed1109175f87fd83fa32a9c2c6fa">base</a>) {
+<a name="l00525"></a>00525                 <span class="comment">/* Calculate the address */</span>
+<a name="l00526"></a>00526                 addr = (uint32_t *) (otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#d2701bc8589613bec5074968e57ce6ef">reg_offset</a> +
+<a name="l00527"></a>00527                                      (uint8_t *) otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#ed96ed1109175f87fd83fa32a9c2c6fa">base</a>);
+<a name="l00528"></a>00528                 dwc_write_reg32(addr, val);
+<a name="l00529"></a>00529         } <span class="keywordflow">else</span> {
+<a name="l00530"></a>00530                 dev_err(_dev, <span class="stringliteral">"Invalid Register Offset (0x%08x)\n"</span>,
+<a name="l00531"></a>00531                         otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#d2701bc8589613bec5074968e57ce6ef">reg_offset</a>);
+<a name="l00532"></a>00532         }
+<a name="l00533"></a>00533         <span class="keywordflow">return</span> count;
+<a name="l00534"></a>00534 }
+<a name="l00535"></a>00535 
+<a name="l00536"></a><a class="code" href="dwc__otg__attr_8c.html#ac2308832629daf78cb9dd123551cd8a">00536</a> DEVICE_ATTR(<a class="code" href="dwc__otg__attr_8c.html#c246d9ba494611cb5b3054a71bf21d22">regvalue</a>, S_IRUGO | <a class="code" href="dwc__otg__attr_8c.html#ac2308832629daf78cb9dd123551cd8a">S_IWUSR</a>, <a class="code" href="dwc__otg__attr_8c.html#d88d7abccfb5b9f0e2c9461a4c950114">regvalue_show</a>, <a class="code" href="dwc__otg__attr_8c.html#decb71de8ca4344042f5230b8fdadc86">regvalue_store</a>);
+<a name="l00537"></a>00537 
+<a name="l00538"></a>00538 <span class="comment">/*</span>
+<a name="l00539"></a>00539 <span class="comment"> * Attributes</span>
+<a name="l00540"></a>00540 <span class="comment"> */</span>
+<a name="l00541"></a><a class="code" href="dwc__otg__attr_8c.html#a6ede17e817a37b1207d7a82147a8e57">00541</a> <a class="code" href="dwc__otg__attr_8c.html#9bf160f54b6a1da72d213aa1aebfb444">DWC_OTG_DEVICE_ATTR_BITFIELD_RO</a>(mode, <span class="stringliteral">"Mode"</span>);
+<a name="l00542"></a>00542 <a class="code" href="dwc__otg__attr_8c.html#91eb9b8ec6d56698f0b6f4934573a41e">DWC_OTG_DEVICE_ATTR_BITFIELD_RW</a>(hnpcapable, <span class="stringliteral">"HNPCapable"</span>);
+<a name="l00543"></a>00543 <a class="code" href="dwc__otg__attr_8c.html#91eb9b8ec6d56698f0b6f4934573a41e">DWC_OTG_DEVICE_ATTR_BITFIELD_RW</a>(srpcapable, <span class="stringliteral">"Mode"</span>);
+<a name="l00544"></a>00544 <a class="code" href="dwc__otg__attr_8c.html#91eb9b8ec6d56698f0b6f4934573a41e">DWC_OTG_DEVICE_ATTR_BITFIELD_RW</a>(hsic_connect, <span class="stringliteral">"HSIC Connect"</span>);
+<a name="l00545"></a>00545 <a class="code" href="dwc__otg__attr_8c.html#91eb9b8ec6d56698f0b6f4934573a41e">DWC_OTG_DEVICE_ATTR_BITFIELD_RW</a>(inv_sel_hsic, <span class="stringliteral">"Invert Select HSIC"</span>);
+<a name="l00546"></a>00546 
+<a name="l00547"></a>00547 <span class="comment">//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(buspower,&amp;(otg_dev-&gt;core_if-&gt;core_global_regs-&gt;gotgctl),(1&lt;&lt;8),8,"Mode");</span>
+<a name="l00548"></a>00548 <span class="comment">//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(bussuspend,&amp;(otg_dev-&gt;core_if-&gt;core_global_regs-&gt;gotgctl),(1&lt;&lt;8),8,"Mode");</span>
+<a name="l00549"></a>00549 <a class="code" href="dwc__otg__attr_8c.html#9bf160f54b6a1da72d213aa1aebfb444">DWC_OTG_DEVICE_ATTR_BITFIELD_RO</a>(busconnected, <span class="stringliteral">"Bus Connected"</span>);
+<a name="l00550"></a>00550 
+<a name="l00551"></a>00551 <a class="code" href="dwc__otg__attr_8c.html#b7106ee2e9d5f335e6c49013ca789467">DWC_OTG_DEVICE_ATTR_REG32_RW</a>(gotgctl, 0, <span class="stringliteral">"GOTGCTL"</span>);
+<a name="l00552"></a>00552 <a class="code" href="dwc__otg__attr_8c.html#b7106ee2e9d5f335e6c49013ca789467">DWC_OTG_DEVICE_ATTR_REG32_RW</a>(gusbcfg,
+<a name="l00553"></a>00553                              &amp;(otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#4cc7c9f6e473072c2ed0a5e6adb25ebe">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#ef39e181e246447df47c56aa4e37cc42">gusbcfg</a>),
+<a name="l00554"></a>00554                              <span class="stringliteral">"GUSBCFG"</span>);
+<a name="l00555"></a>00555 <a class="code" href="dwc__otg__attr_8c.html#b7106ee2e9d5f335e6c49013ca789467">DWC_OTG_DEVICE_ATTR_REG32_RW</a>(grxfsiz,
+<a name="l00556"></a>00556                              &amp;(otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#4cc7c9f6e473072c2ed0a5e6adb25ebe">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#b1a8cc07a9541c9a73e864579602b79b">grxfsiz</a>),
+<a name="l00557"></a>00557                              <span class="stringliteral">"GRXFSIZ"</span>);
+<a name="l00558"></a>00558 <a class="code" href="dwc__otg__attr_8c.html#b7106ee2e9d5f335e6c49013ca789467">DWC_OTG_DEVICE_ATTR_REG32_RW</a>(gnptxfsiz,
+<a name="l00559"></a>00559                              &amp;(otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#4cc7c9f6e473072c2ed0a5e6adb25ebe">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#20fb70fe34a1a65d085b1d4e5f8d9106">gnptxfsiz</a>),
+<a name="l00560"></a>00560                              <span class="stringliteral">"GNPTXFSIZ"</span>);
+<a name="l00561"></a>00561 <a class="code" href="dwc__otg__attr_8c.html#b7106ee2e9d5f335e6c49013ca789467">DWC_OTG_DEVICE_ATTR_REG32_RW</a>(gpvndctl,
+<a name="l00562"></a>00562                              &amp;(otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#4cc7c9f6e473072c2ed0a5e6adb25ebe">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#a12db668367caef8386d2ba20289e437">gpvndctl</a>),
+<a name="l00563"></a>00563                              <span class="stringliteral">"GPVNDCTL"</span>);
+<a name="l00564"></a>00564 <a class="code" href="dwc__otg__attr_8c.html#b7106ee2e9d5f335e6c49013ca789467">DWC_OTG_DEVICE_ATTR_REG32_RW</a>(ggpio,
+<a name="l00565"></a>00565                              &amp;(otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#4cc7c9f6e473072c2ed0a5e6adb25ebe">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#694546400c443d41b449772c8573f3e8">ggpio</a>),
+<a name="l00566"></a>00566                              <span class="stringliteral">"GGPIO"</span>);
+<a name="l00567"></a>00567 <a class="code" href="dwc__otg__attr_8c.html#b7106ee2e9d5f335e6c49013ca789467">DWC_OTG_DEVICE_ATTR_REG32_RW</a>(guid, &amp;(otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#4cc7c9f6e473072c2ed0a5e6adb25ebe">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#8735ca2e93c1e984ac2d5bcf0cda96d7">guid</a>),
+<a name="l00568"></a>00568                              <span class="stringliteral">"GUID"</span>);
+<a name="l00569"></a>00569 <a class="code" href="dwc__otg__attr_8c.html#471f9d3f4b4aa45b59be200e1b3beb87">DWC_OTG_DEVICE_ATTR_REG32_RO</a>(gsnpsid,
+<a name="l00570"></a>00570                              &amp;(otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#4cc7c9f6e473072c2ed0a5e6adb25ebe">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#30798436df220217c3960ac4a46710dc">gsnpsid</a>),
+<a name="l00571"></a>00571                              <span class="stringliteral">"GSNPSID"</span>);
+<a name="l00572"></a>00572 <a class="code" href="dwc__otg__attr_8c.html#91eb9b8ec6d56698f0b6f4934573a41e">DWC_OTG_DEVICE_ATTR_BITFIELD_RW</a>(devspeed, <span class="stringliteral">"Device Speed"</span>);
+<a name="l00573"></a>00573 <a class="code" href="dwc__otg__attr_8c.html#9bf160f54b6a1da72d213aa1aebfb444">DWC_OTG_DEVICE_ATTR_BITFIELD_RO</a>(enumspeed, <span class="stringliteral">"Device Enumeration Speed"</span>);
+<a name="l00574"></a>00574 
+<a name="l00575"></a>00575 <a class="code" href="dwc__otg__attr_8c.html#471f9d3f4b4aa45b59be200e1b3beb87">DWC_OTG_DEVICE_ATTR_REG32_RO</a>(hptxfsiz,
+<a name="l00576"></a>00576                              &amp;(otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#4cc7c9f6e473072c2ed0a5e6adb25ebe">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#94ae41f04d5a4244a8ebc23e51187e96">hptxfsiz</a>),
+<a name="l00577"></a>00577                              <span class="stringliteral">"HPTXFSIZ"</span>);
+<a name="l00578"></a>00578 <a class="code" href="dwc__otg__attr_8c.html#b7106ee2e9d5f335e6c49013ca789467">DWC_OTG_DEVICE_ATTR_REG32_RW</a>(hprt0, otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#4cc7c9f6e473072c2ed0a5e6adb25ebe">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#dc8fe33e0bb3829cafa884d5fc603c4d">hprt0</a>, <span class="stringliteral">"HPRT0"</span>);
+<a name="l00579"></a>00579 
+<a name="l00586"></a>00586 <span class="keyword">static</span> ssize_t <a class="code" href="dwc__otg__attr_8c.html#5ed0f5e2094b1db679075adf2f81e10a">hnp_show</a>(<span class="keyword">struct</span> device *_dev,
+<a name="l00587"></a>00587                         <span class="keyword">struct</span> device_attribute *attr, <span class="keywordtype">char</span> *buf)
+<a name="l00588"></a>00588 {
+<a name="l00589"></a>00589 <span class="preprocessor">#ifdef LM_INTERFACE</span>
+<a name="l00590"></a>00590 <span class="preprocessor"></span>        <span class="keyword">struct </span>lm_device *lm_dev = container_of(_dev, <span class="keyword">struct</span> lm_device, dev);
+<a name="l00591"></a>00591         <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = lm_get_drvdata(lm_dev);
+<a name="l00592"></a>00592 <span class="preprocessor">#elif PCI_INTERFACE</span>
+<a name="l00593"></a>00593 <span class="preprocessor"></span>        <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = dev_get_drvdata(_dev);
+<a name="l00594"></a>00594 <span class="preprocessor">#endif</span>
+<a name="l00595"></a>00595 <span class="preprocessor"></span>        <span class="keywordflow">return</span> sprintf(buf, <span class="stringliteral">"HstNegScs = 0x%x\n"</span>,
+<a name="l00596"></a>00596                        <a class="code" href="dwc__otg__cil_8c.html#df391379aafa69a8683bb1f88c413675">dwc_otg_get_hnpstatus</a>(otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#4cc7c9f6e473072c2ed0a5e6adb25ebe">core_if</a>));
+<a name="l00597"></a>00597 }
+<a name="l00598"></a>00598 
+<a name="l00602"></a><a class="code" href="dwc__otg__attr_8c.html#14b1910d541301f5456e2a15a3b4f0b0">00602</a> <span class="keyword">static</span> ssize_t <a class="code" href="dwc__otg__attr_8c.html#8c009b0959c53d9bc868afa4572db7a1">hnp_store</a>(<span class="keyword">struct</span> device *_dev,
+<a name="l00603"></a>00603                          <span class="keyword">struct</span> device_attribute *attr,
+<a name="l00604"></a>00604                          <span class="keyword">const</span> <span class="keywordtype">char</span> *buf, size_t count)
+<a name="l00605"></a>00605 {
+<a name="l00606"></a>00606 <span class="preprocessor">#ifdef LM_INTERFACE</span>
+<a name="l00607"></a>00607 <span class="preprocessor"></span>        <span class="keyword">struct </span>lm_device *lm_dev = container_of(_dev, <span class="keyword">struct</span> lm_device, dev);
+<a name="l00608"></a>00608         <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = lm_get_drvdata(lm_dev);
+<a name="l00609"></a>00609 <span class="preprocessor">#elif PCI_INTERFACE</span>
+<a name="l00610"></a>00610 <span class="preprocessor"></span>        <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = dev_get_drvdata(_dev);
+<a name="l00611"></a>00611 <span class="preprocessor">#endif</span>
+<a name="l00612"></a>00612 <span class="preprocessor"></span>        uint32_t in = simple_strtoul(buf, NULL, 16);
+<a name="l00613"></a>00613         <a class="code" href="dwc__otg__cil_8c.html#5cab27b65ed5a6a1e31c0e4df1650f0e">dwc_otg_set_hnpreq</a>(otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#4cc7c9f6e473072c2ed0a5e6adb25ebe">core_if</a>, in);
+<a name="l00614"></a>00614         <span class="keywordflow">return</span> count;
+<a name="l00615"></a>00615 }
+<a name="l00616"></a>00616 
+<a name="l00617"></a><a class="code" href="dwc__otg__attr_8c.html#8c009b0959c53d9bc868afa4572db7a1">00617</a> DEVICE_ATTR(<a class="code" href="dwc__otg__attr_8c.html#2d1cf91c8e20bcdd4f552c410b0aa6ba">hnp</a>, 0644, <a class="code" href="dwc__otg__attr_8c.html#5ed0f5e2094b1db679075adf2f81e10a">hnp_show</a>, <a class="code" href="dwc__otg__attr_8c.html#8c009b0959c53d9bc868afa4572db7a1">hnp_store</a>);
+<a name="l00618"></a>00618 
+<a name="l00625"></a><a class="code" href="dwc__otg__attr_8c.html#9e8313bb6a0f54484d279b2e28269712">00625</a> <span class="keyword">static</span> ssize_t <a class="code" href="dwc__otg__attr_8c.html#1ca3f5bc52a2523ca16a4fe5eafee0df">srp_show</a>(<span class="keyword">struct</span> device *_dev,
+<a name="l00626"></a>00626                         <span class="keyword">struct</span> device_attribute *attr, <span class="keywordtype">char</span> *buf)
+<a name="l00627"></a>00627 {
+<a name="l00628"></a>00628 <span class="preprocessor">#ifndef DWC_HOST_ONLY</span>
+<a name="l00629"></a>00629 <span class="preprocessor"></span><span class="preprocessor">#ifdef LM_INTERFACE</span>
+<a name="l00630"></a>00630 <span class="preprocessor"></span>        <span class="keyword">struct </span>lm_device *lm_dev = container_of(_dev, <span class="keyword">struct</span> lm_device, dev);
+<a name="l00631"></a>00631         <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = lm_get_drvdata(lm_dev);
+<a name="l00632"></a>00632 <span class="preprocessor">#elif PCI_INTERFACE</span>
+<a name="l00633"></a>00633 <span class="preprocessor"></span>        <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = dev_get_drvdata(_dev);
+<a name="l00634"></a>00634 <span class="preprocessor">#endif</span>
+<a name="l00635"></a>00635 <span class="preprocessor"></span>        <span class="keywordflow">return</span> sprintf(buf, <span class="stringliteral">"SesReqScs = 0x%x\n"</span>,
+<a name="l00636"></a>00636                        <a class="code" href="dwc__otg__cil_8c.html#b13eac2758aace478587df0f043e80f8">dwc_otg_get_srpstatus</a>(otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#4cc7c9f6e473072c2ed0a5e6adb25ebe">core_if</a>));
+<a name="l00637"></a>00637 <span class="preprocessor">#else</span>
+<a name="l00638"></a>00638 <span class="preprocessor"></span>        <span class="keywordflow">return</span> sprintf(buf, <span class="stringliteral">"Host Only Mode!\n"</span>);
+<a name="l00639"></a>00639 <span class="preprocessor">#endif</span>
+<a name="l00640"></a>00640 <span class="preprocessor"></span>}
+<a name="l00641"></a>00641 
+<a name="l00645"></a><a class="code" href="dwc__otg__attr_8c.html#80c785e24be4a8ce02d0b38a0ba5484a">00645</a> <span class="keyword">static</span> ssize_t <a class="code" href="dwc__otg__attr_8c.html#204d2d3c45a75706a28c57b396eb55c3">srp_store</a>(<span class="keyword">struct</span> device *_dev,
+<a name="l00646"></a>00646                          <span class="keyword">struct</span> device_attribute *attr,
+<a name="l00647"></a>00647                          <span class="keyword">const</span> <span class="keywordtype">char</span> *buf, size_t count)
+<a name="l00648"></a>00648 {
+<a name="l00649"></a>00649 <span class="preprocessor">#ifndef DWC_HOST_ONLY</span>
+<a name="l00650"></a>00650 <span class="preprocessor"></span><span class="preprocessor">#ifdef LM_INTERFACE</span>
+<a name="l00651"></a>00651 <span class="preprocessor"></span>        <span class="keyword">struct </span>lm_device *lm_dev = container_of(_dev, <span class="keyword">struct</span> lm_device, dev);
+<a name="l00652"></a>00652         <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = lm_get_drvdata(lm_dev);
+<a name="l00653"></a>00653 <span class="preprocessor">#elif PCI_INTERFACE</span>
+<a name="l00654"></a>00654 <span class="preprocessor"></span>        <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = dev_get_drvdata(_dev);
+<a name="l00655"></a>00655 <span class="preprocessor">#endif</span>
+<a name="l00656"></a>00656 <span class="preprocessor"></span>        <a class="code" href="dwc__otg__pcd_8c.html#4be3e59162a42a79705e3ea8dc5008fa">dwc_otg_pcd_initiate_srp</a>(otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#2a8eefbd03790ea0bbb70e0ac14e4786">pcd</a>);
+<a name="l00657"></a>00657 <span class="preprocessor">#endif</span>
+<a name="l00658"></a>00658 <span class="preprocessor"></span>        <span class="keywordflow">return</span> count;
+<a name="l00659"></a>00659 }
+<a name="l00660"></a>00660 
+<a name="l00661"></a><a class="code" href="dwc__otg__attr_8c.html#204d2d3c45a75706a28c57b396eb55c3">00661</a> DEVICE_ATTR(<a class="code" href="dwc__otg__attr_8c.html#0c2c4ba16770c40a82dbb1c33cbc2e4a">srp</a>, 0644, <a class="code" href="dwc__otg__attr_8c.html#1ca3f5bc52a2523ca16a4fe5eafee0df">srp_show</a>, <a class="code" href="dwc__otg__attr_8c.html#204d2d3c45a75706a28c57b396eb55c3">srp_store</a>);
+<a name="l00662"></a>00662 
+<a name="l00669"></a><a class="code" href="dwc__otg__attr_8c.html#6979f4909cde868d800dba13ef95aa8c">00669</a> <span class="keyword">static</span> ssize_t <a class="code" href="dwc__otg__attr_8c.html#d47a22e2b2f574a22c206f8b6d98e78a">buspower_show</a>(<span class="keyword">struct</span> device *_dev,
+<a name="l00670"></a>00670                              <span class="keyword">struct</span> device_attribute *attr, <span class="keywordtype">char</span> *buf)
+<a name="l00671"></a>00671 {
+<a name="l00672"></a>00672 <span class="preprocessor">#ifdef LM_INTERFACE</span>
+<a name="l00673"></a>00673 <span class="preprocessor"></span>        <span class="keyword">struct </span>lm_device *lm_dev = container_of(_dev, <span class="keyword">struct</span> lm_device, dev);
+<a name="l00674"></a>00674         <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = lm_get_drvdata(lm_dev);
+<a name="l00675"></a>00675 <span class="preprocessor">#elif PCI_INTERFACE</span>
+<a name="l00676"></a>00676 <span class="preprocessor"></span>        <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = dev_get_drvdata(_dev);
+<a name="l00677"></a>00677 <span class="preprocessor">#endif</span>
+<a name="l00678"></a>00678 <span class="preprocessor"></span>        <span class="keywordflow">return</span> sprintf(buf, <span class="stringliteral">"Bus Power = 0x%x\n"</span>,
+<a name="l00679"></a>00679                        <a class="code" href="dwc__otg__cil_8c.html#83a11dae1c9563aee56baea469cd6064">dwc_otg_get_prtpower</a>(otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#4cc7c9f6e473072c2ed0a5e6adb25ebe">core_if</a>));
+<a name="l00680"></a>00680 }
+<a name="l00681"></a>00681 
+<a name="l00685"></a><a class="code" href="dwc__otg__attr_8c.html#4514a396df18dae15f7f03f640f52ac7">00685</a> <span class="keyword">static</span> ssize_t <a class="code" href="dwc__otg__attr_8c.html#ccabb5758f6506d5b6e4120ffdc58a0e">buspower_store</a>(<span class="keyword">struct</span> device *_dev,
+<a name="l00686"></a>00686                               <span class="keyword">struct</span> device_attribute *attr,
+<a name="l00687"></a>00687                               <span class="keyword">const</span> <span class="keywordtype">char</span> *buf, size_t count)
+<a name="l00688"></a>00688 {
+<a name="l00689"></a>00689 <span class="preprocessor">#ifdef LM_INTERFACE</span>
+<a name="l00690"></a>00690 <span class="preprocessor"></span>        <span class="keyword">struct </span>lm_device *lm_dev = container_of(_dev, <span class="keyword">struct</span> lm_device, dev);
+<a name="l00691"></a>00691         <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = lm_get_drvdata(lm_dev);
+<a name="l00692"></a>00692 <span class="preprocessor">#elif PCI_INTERFACE</span>
+<a name="l00693"></a>00693 <span class="preprocessor"></span>        <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = dev_get_drvdata(_dev);
+<a name="l00694"></a>00694 <span class="preprocessor">#endif</span>
+<a name="l00695"></a>00695 <span class="preprocessor"></span>        uint32_t on = simple_strtoul(buf, NULL, 16);
+<a name="l00696"></a>00696         <a class="code" href="dwc__otg__cil_8c.html#63c880f915b4705a5c118b276e6e9567">dwc_otg_set_prtpower</a>(otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#4cc7c9f6e473072c2ed0a5e6adb25ebe">core_if</a>, on);
+<a name="l00697"></a>00697         <span class="keywordflow">return</span> count;
+<a name="l00698"></a>00698 }
+<a name="l00699"></a>00699 
+<a name="l00700"></a><a class="code" href="dwc__otg__attr_8c.html#ccabb5758f6506d5b6e4120ffdc58a0e">00700</a> DEVICE_ATTR(<a class="code" href="dwc__otg__attr_8c.html#1d54646ee79d4ce4f4acd08d7d4448ce">buspower</a>, 0644, <a class="code" href="dwc__otg__attr_8c.html#d47a22e2b2f574a22c206f8b6d98e78a">buspower_show</a>, <a class="code" href="dwc__otg__attr_8c.html#ccabb5758f6506d5b6e4120ffdc58a0e">buspower_store</a>);
+<a name="l00701"></a>00701 
+<a name="l00708"></a><a class="code" href="dwc__otg__attr_8c.html#ae1f7e3a17c5a0bcc5a93096aeb902d2">00708</a> <span class="keyword">static</span> ssize_t <a class="code" href="dwc__otg__attr_8c.html#638d5fb77692c7445831d1fe71bbc877">bussuspend_show</a>(<span class="keyword">struct</span> device *_dev,
+<a name="l00709"></a>00709                                <span class="keyword">struct</span> device_attribute *attr, <span class="keywordtype">char</span> *buf)
+<a name="l00710"></a>00710 {
+<a name="l00711"></a>00711 <span class="preprocessor">#ifdef LM_INTERFACE</span>
+<a name="l00712"></a>00712 <span class="preprocessor"></span>        <span class="keyword">struct </span>lm_device *lm_dev = container_of(_dev, <span class="keyword">struct</span> lm_device, dev);
+<a name="l00713"></a>00713         <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = lm_get_drvdata(lm_dev);
+<a name="l00714"></a>00714 <span class="preprocessor">#elif PCI_INTERFACE</span>
+<a name="l00715"></a>00715 <span class="preprocessor"></span>        <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = dev_get_drvdata(_dev);
+<a name="l00716"></a>00716 <span class="preprocessor">#endif</span>
+<a name="l00717"></a>00717 <span class="preprocessor"></span>
+<a name="l00718"></a>00718         <span class="keywordflow">return</span> sprintf(buf, <span class="stringliteral">"Bus Suspend = 0x%x\n"</span>,
+<a name="l00719"></a>00719                        <a class="code" href="dwc__otg__cil_8c.html#65b0861f7d5d604fb97e599adac62642">dwc_otg_get_prtsuspend</a>(otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#4cc7c9f6e473072c2ed0a5e6adb25ebe">core_if</a>));
+<a name="l00720"></a>00720 }
+<a name="l00721"></a>00721 
+<a name="l00725"></a><a class="code" href="dwc__otg__attr_8c.html#f218d7c4c611b97dfaa1e03ac2daa353">00725</a> <span class="keyword">static</span> ssize_t <a class="code" href="dwc__otg__attr_8c.html#6441ce2449145d6d2008a21a36f458a5">bussuspend_store</a>(<span class="keyword">struct</span> device *_dev,
+<a name="l00726"></a>00726                                 <span class="keyword">struct</span> device_attribute *attr,
+<a name="l00727"></a>00727                                 <span class="keyword">const</span> <span class="keywordtype">char</span> *buf, size_t count)
+<a name="l00728"></a>00728 {
+<a name="l00729"></a>00729 <span class="preprocessor">#ifdef LM_INTERFACE</span>
+<a name="l00730"></a>00730 <span class="preprocessor"></span>        <span class="keyword">struct </span>lm_device *lm_dev = container_of(_dev, <span class="keyword">struct</span> lm_device, dev);
+<a name="l00731"></a>00731         <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = lm_get_drvdata(lm_dev);
+<a name="l00732"></a>00732 <span class="preprocessor">#elif PCI_INTERFACE</span>
+<a name="l00733"></a>00733 <span class="preprocessor"></span>        <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = dev_get_drvdata(_dev);
+<a name="l00734"></a>00734 <span class="preprocessor">#endif</span>
+<a name="l00735"></a>00735 <span class="preprocessor"></span>
+<a name="l00736"></a>00736         uint32_t in = simple_strtoul(buf, NULL, 16);
+<a name="l00737"></a>00737         <a class="code" href="dwc__otg__cil_8c.html#c072cef5b7d3c5566ad3be010c6d49ed">dwc_otg_set_prtsuspend</a>(otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#4cc7c9f6e473072c2ed0a5e6adb25ebe">core_if</a>, in);
+<a name="l00738"></a>00738         <span class="keywordflow">return</span> count;
+<a name="l00739"></a>00739 }
+<a name="l00740"></a>00740 
+<a name="l00741"></a><a class="code" href="dwc__otg__attr_8c.html#6441ce2449145d6d2008a21a36f458a5">00741</a> DEVICE_ATTR(<a class="code" href="dwc__otg__attr_8c.html#e3c6534cdd3e1b7e83bf48e745d44c64">bussuspend</a>, 0644, <a class="code" href="dwc__otg__attr_8c.html#638d5fb77692c7445831d1fe71bbc877">bussuspend_show</a>, <a class="code" href="dwc__otg__attr_8c.html#6441ce2449145d6d2008a21a36f458a5">bussuspend_store</a>);
+<a name="l00742"></a>00742 
+<a name="l00746"></a><a class="code" href="dwc__otg__attr_8c.html#3321551071eb0987630d501c377ff095">00746</a> <span class="keyword">static</span> ssize_t <a class="code" href="dwc__otg__attr_8c.html#d3c8b864074e133b8d1a11ee88e69a05">remote_wakeup_show</a>(<span class="keyword">struct</span> device *_dev,
+<a name="l00747"></a>00747                                   <span class="keyword">struct</span> device_attribute *attr, <span class="keywordtype">char</span> *buf)
+<a name="l00748"></a>00748 {
+<a name="l00749"></a>00749 <span class="preprocessor">#ifndef DWC_HOST_ONLY</span>
+<a name="l00750"></a>00750 <span class="preprocessor"></span><span class="preprocessor">#ifdef LM_INTERFACE</span>
+<a name="l00751"></a>00751 <span class="preprocessor"></span>        <span class="keyword">struct </span>lm_device *lm_dev = container_of(_dev, <span class="keyword">struct</span> lm_device, dev);
+<a name="l00752"></a>00752         <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = lm_get_drvdata(lm_dev);
+<a name="l00753"></a>00753 <span class="preprocessor">#elif PCI_INTERFACE</span>
+<a name="l00754"></a>00754 <span class="preprocessor"></span>        <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = dev_get_drvdata(_dev);
+<a name="l00755"></a>00755 <span class="preprocessor">#endif</span>
+<a name="l00756"></a>00756 <span class="preprocessor"></span>
+<a name="l00757"></a>00757         <span class="keywordflow">return</span> sprintf(buf,
+<a name="l00758"></a>00758                        <span class="stringliteral">"Remote Wakeup Sig = %d Enabled = %d LPM Remote Wakeup = %d\n"</span>,
+<a name="l00759"></a>00759                        <a class="code" href="dwc__otg__cil_8c.html#285696198299e317222544aa912b2c35">dwc_otg_get_remotewakesig</a>(otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#4cc7c9f6e473072c2ed0a5e6adb25ebe">core_if</a>),
+<a name="l00760"></a>00760                        <a class="code" href="dwc__otg__pcd_8c.html#0107dd39d549d3e10fd388337e03aeb9">dwc_otg_pcd_get_rmwkup_enable</a>(otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#2a8eefbd03790ea0bbb70e0ac14e4786">pcd</a>),
+<a name="l00761"></a>00761                        <a class="code" href="dwc__otg__cil_8c.html#91d2a6b57c7216fd5c6dc981a5f0e1ae">dwc_otg_get_lpm_remotewakeenabled</a>(otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#4cc7c9f6e473072c2ed0a5e6adb25ebe">core_if</a>));
+<a name="l00762"></a>00762 <span class="preprocessor">#else</span>
+<a name="l00763"></a>00763 <span class="preprocessor"></span>        <span class="keywordflow">return</span> sprintf(buf, <span class="stringliteral">"Host Only Mode!\n"</span>);
+<a name="l00764"></a>00764 <span class="preprocessor">#endif </span><span class="comment">/* DWC_HOST_ONLY */</span>
+<a name="l00765"></a>00765 }
+<a name="l00766"></a>00766 
+<a name="l00773"></a><a class="code" href="dwc__otg__attr_8c.html#e64972f2160646d9d707a97366eba56c">00773</a> <span class="keyword">static</span> ssize_t <a class="code" href="dwc__otg__attr_8c.html#5fe962daf09b0bc23527817b51da4d01">remote_wakeup_store</a>(<span class="keyword">struct</span> device *_dev,
+<a name="l00774"></a>00774                                    <span class="keyword">struct</span> device_attribute *attr,
+<a name="l00775"></a>00775                                    <span class="keyword">const</span> <span class="keywordtype">char</span> *buf, size_t count)
+<a name="l00776"></a>00776 {
+<a name="l00777"></a>00777 <span class="preprocessor">#ifndef DWC_HOST_ONLY</span>
+<a name="l00778"></a>00778 <span class="preprocessor"></span><span class="preprocessor">#ifdef LM_INTERFACE</span>
+<a name="l00779"></a>00779 <span class="preprocessor"></span>        <span class="keyword">struct </span>lm_device *lm_dev = container_of(_dev, <span class="keyword">struct</span> lm_device, dev);
+<a name="l00780"></a>00780         <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = lm_get_drvdata(lm_dev);
+<a name="l00781"></a>00781 <span class="preprocessor">#elif PCI_INTERFACE</span>
+<a name="l00782"></a>00782 <span class="preprocessor"></span>        <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = dev_get_drvdata(_dev);
+<a name="l00783"></a>00783 <span class="preprocessor">#endif</span>
+<a name="l00784"></a>00784 <span class="preprocessor"></span>
+<a name="l00785"></a>00785         uint32_t val = simple_strtoul(buf, NULL, 16);
+<a name="l00786"></a>00786 
+<a name="l00787"></a>00787         <span class="keywordflow">if</span> (val &amp; 1) {
+<a name="l00788"></a>00788                 <a class="code" href="dwc__otg__pcd_8c.html#24cbdd57c573d864a09a30ae3ecda89a">dwc_otg_pcd_remote_wakeup</a>(otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#2a8eefbd03790ea0bbb70e0ac14e4786">pcd</a>, 1);
+<a name="l00789"></a>00789         } <span class="keywordflow">else</span> {
+<a name="l00790"></a>00790                 <a class="code" href="dwc__otg__pcd_8c.html#24cbdd57c573d864a09a30ae3ecda89a">dwc_otg_pcd_remote_wakeup</a>(otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#2a8eefbd03790ea0bbb70e0ac14e4786">pcd</a>, 0);
+<a name="l00791"></a>00791         }
+<a name="l00792"></a>00792 <span class="preprocessor">#endif </span><span class="comment">/* DWC_HOST_ONLY */</span>
+<a name="l00793"></a>00793         <span class="keywordflow">return</span> count;
+<a name="l00794"></a>00794 }
+<a name="l00795"></a>00795 
+<a name="l00796"></a><a class="code" href="dwc__otg__attr_8c.html#ac2308832629daf78cb9dd123551cd8a">00796</a> DEVICE_ATTR(<a class="code" href="dwc__otg__attr_8c.html#f3afff970133d773b5414f1f0f2becfe">remote_wakeup</a>, S_IRUGO | <a class="code" href="dwc__otg__attr_8c.html#ac2308832629daf78cb9dd123551cd8a">S_IWUSR</a>, <a class="code" href="dwc__otg__attr_8c.html#d3c8b864074e133b8d1a11ee88e69a05">remote_wakeup_show</a>,
+<a name="l00797"></a>00797             <a class="code" href="dwc__otg__attr_8c.html#5fe962daf09b0bc23527817b51da4d01">remote_wakeup_store</a>);
+<a name="l00798"></a>00798 
+<a name="l00803"></a><a class="code" href="dwc__otg__attr_8c.html#36728dcc762e9cbdbc9543c8b780df68">00803</a> <span class="keyword">static</span> ssize_t <a class="code" href="dwc__otg__attr_8c.html#51243ef08f84d463dbb4a1a564222229">regdump_show</a>(<span class="keyword">struct</span> device *_dev,
+<a name="l00804"></a>00804                             <span class="keyword">struct</span> device_attribute *attr, <span class="keywordtype">char</span> *buf)
+<a name="l00805"></a>00805 {
+<a name="l00806"></a>00806 <span class="preprocessor">#ifdef LM_INTERFACE</span>
+<a name="l00807"></a>00807 <span class="preprocessor"></span>        <span class="keyword">struct </span>lm_device *lm_dev = container_of(_dev, <span class="keyword">struct</span> lm_device, dev);
+<a name="l00808"></a>00808         <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = lm_get_drvdata(lm_dev);
+<a name="l00809"></a>00809 <span class="preprocessor">#elif PCI_INTERFACE</span>
+<a name="l00810"></a>00810 <span class="preprocessor"></span>        <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = dev_get_drvdata(_dev);
+<a name="l00811"></a>00811 <span class="preprocessor">#endif</span>
+<a name="l00812"></a>00812 <span class="preprocessor"></span>
+<a name="l00813"></a>00813         <a class="code" href="dwc__otg__cil_8c.html#118ecda931e2b745f76fde129ff707c2">dwc_otg_dump_global_registers</a>(otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#4cc7c9f6e473072c2ed0a5e6adb25ebe">core_if</a>);
+<a name="l00814"></a>00814         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#f0bfe5f933e21a94ea06c96ffc086e72">dwc_otg_is_host_mode</a>(otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#4cc7c9f6e473072c2ed0a5e6adb25ebe">core_if</a>)) {
+<a name="l00815"></a>00815                 <a class="code" href="dwc__otg__cil_8c.html#e85d3d04799b17226fcb00ea2074ca63">dwc_otg_dump_host_registers</a>(otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#4cc7c9f6e473072c2ed0a5e6adb25ebe">core_if</a>);
+<a name="l00816"></a>00816         } <span class="keywordflow">else</span> {
+<a name="l00817"></a>00817                 <a class="code" href="dwc__otg__cil_8c.html#ea3bce6af9d0bd9b2fb6de94f1c7a133">dwc_otg_dump_dev_registers</a>(otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#4cc7c9f6e473072c2ed0a5e6adb25ebe">core_if</a>);
+<a name="l00818"></a>00818 
+<a name="l00819"></a>00819         }
+<a name="l00820"></a>00820         <span class="keywordflow">return</span> sprintf(buf, <span class="stringliteral">"Register Dump\n"</span>);
+<a name="l00821"></a>00821 }
+<a name="l00822"></a>00822 
+<a name="l00823"></a><a class="code" href="dwc__otg__attr_8c.html#ac2308832629daf78cb9dd123551cd8a">00823</a> DEVICE_ATTR(<a class="code" href="dwc__otg__attr_8c.html#8db089dfccee4ac4de5f89814ddd42fc">regdump</a>, S_IRUGO | <a class="code" href="dwc__otg__attr_8c.html#ac2308832629daf78cb9dd123551cd8a">S_IWUSR</a>, <a class="code" href="dwc__otg__attr_8c.html#51243ef08f84d463dbb4a1a564222229">regdump_show</a>, 0);
+<a name="l00824"></a>00824 
+<a name="l00829"></a><a class="code" href="dwc__otg__attr_8c.html#e98e139afbb50f9d989ddbef2f0dbd6e">00829</a> <span class="keyword">static</span> ssize_t <a class="code" href="dwc__otg__attr_8c.html#5e7475d07adbb4380c57d019ab9e5af1">spramdump_show</a>(<span class="keyword">struct</span> device *_dev,
+<a name="l00830"></a>00830                               <span class="keyword">struct</span> device_attribute *attr, <span class="keywordtype">char</span> *buf)
+<a name="l00831"></a>00831 {
+<a name="l00832"></a>00832 <span class="preprocessor">#ifdef LM_INTERFACE</span>
+<a name="l00833"></a>00833 <span class="preprocessor"></span>        <span class="keyword">struct </span>lm_device *lm_dev = container_of(_dev, <span class="keyword">struct</span> lm_device, dev);
+<a name="l00834"></a>00834         <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = lm_get_drvdata(lm_dev);
+<a name="l00835"></a>00835 <span class="preprocessor">#elif PCI_INTERFACE</span>
+<a name="l00836"></a>00836 <span class="preprocessor"></span>        <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = dev_get_drvdata(_dev);
+<a name="l00837"></a>00837 <span class="preprocessor">#endif</span>
+<a name="l00838"></a>00838 <span class="preprocessor"></span>
+<a name="l00839"></a>00839         <a class="code" href="dwc__otg__cil_8c.html#393e65ddcbaed38935ea06fb7451167b">dwc_otg_dump_spram</a>(otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#4cc7c9f6e473072c2ed0a5e6adb25ebe">core_if</a>);
+<a name="l00840"></a>00840 
+<a name="l00841"></a>00841         <span class="keywordflow">return</span> sprintf(buf, <span class="stringliteral">"SPRAM Dump\n"</span>);
+<a name="l00842"></a>00842 }
+<a name="l00843"></a>00843 
+<a name="l00844"></a><a class="code" href="dwc__otg__attr_8c.html#5e7475d07adbb4380c57d019ab9e5af1">00844</a> DEVICE_ATTR(<a class="code" href="dwc__otg__attr_8c.html#d24c69237b2acf90968b763e467e9ec9">spramdump</a>, S_IRUGO | <a class="code" href="dwc__otg__attr_8c.html#ac2308832629daf78cb9dd123551cd8a">S_IWUSR</a>, <a class="code" href="dwc__otg__attr_8c.html#5e7475d07adbb4380c57d019ab9e5af1">spramdump_show</a>, 0);
+<a name="l00845"></a>00845 
+<a name="l00849"></a><a class="code" href="dwc__otg__attr_8c.html#e16d4439b6b733715ecc1d06ed999aa4">00849</a> <span class="keyword">static</span> ssize_t <a class="code" href="dwc__otg__attr_8c.html#51e3893bb30f2102c68b39ef361457b0">hcddump_show</a>(<span class="keyword">struct</span> device *_dev,
+<a name="l00850"></a>00850                             <span class="keyword">struct</span> device_attribute *attr, <span class="keywordtype">char</span> *buf)
+<a name="l00851"></a>00851 {
+<a name="l00852"></a>00852 <span class="preprocessor">#ifndef DWC_DEVICE_ONLY</span>
+<a name="l00853"></a>00853 <span class="preprocessor"></span><span class="preprocessor">#ifdef LM_INTERFACE</span>
+<a name="l00854"></a>00854 <span class="preprocessor"></span>        <span class="keyword">struct </span>lm_device *lm_dev = container_of(_dev, <span class="keyword">struct</span> lm_device, dev);
+<a name="l00855"></a>00855         <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = lm_get_drvdata(lm_dev);
+<a name="l00856"></a>00856 <span class="preprocessor">#elif PCI_INTERFACE</span>
+<a name="l00857"></a>00857 <span class="preprocessor"></span>        <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = dev_get_drvdata(_dev);
+<a name="l00858"></a>00858 <span class="preprocessor">#endif</span>
+<a name="l00859"></a>00859 <span class="preprocessor"></span>
+<a name="l00860"></a>00860         <a class="code" href="dwc__otg__hcd_8c.html#464f920221173fe04c756a9d6657f321">dwc_otg_hcd_dump_state</a>(otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#834ef28e884f0d7fcac68f3bdf5c4b33">hcd</a>);
+<a name="l00861"></a>00861 <span class="preprocessor">#endif </span><span class="comment">/* DWC_DEVICE_ONLY */</span>
+<a name="l00862"></a>00862         <span class="keywordflow">return</span> sprintf(buf, <span class="stringliteral">"HCD Dump\n"</span>);
+<a name="l00863"></a>00863 }
+<a name="l00864"></a>00864 
+<a name="l00865"></a><a class="code" href="dwc__otg__attr_8c.html#ac2308832629daf78cb9dd123551cd8a">00865</a> DEVICE_ATTR(<a class="code" href="dwc__otg__attr_8c.html#eb95151b5afaea479812773b61c402b4">hcddump</a>, S_IRUGO | <a class="code" href="dwc__otg__attr_8c.html#ac2308832629daf78cb9dd123551cd8a">S_IWUSR</a>, <a class="code" href="dwc__otg__attr_8c.html#51e3893bb30f2102c68b39ef361457b0">hcddump_show</a>, 0);
+<a name="l00866"></a>00866 
+<a name="l00872"></a><a class="code" href="dwc__otg__attr_8c.html#d1d9d9abd2011c79fe7453c20e03e31a">00872</a> <span class="keyword">static</span> ssize_t <a class="code" href="dwc__otg__attr_8c.html#95ea28023a1ac497504fc5868d3b4d66">hcd_frrem_show</a>(<span class="keyword">struct</span> device *_dev,
+<a name="l00873"></a>00873                               <span class="keyword">struct</span> device_attribute *attr, <span class="keywordtype">char</span> *buf)
+<a name="l00874"></a>00874 {
+<a name="l00875"></a>00875 <span class="preprocessor">#ifndef DWC_DEVICE_ONLY</span>
+<a name="l00876"></a>00876 <span class="preprocessor"></span><span class="preprocessor">#ifdef LM_INTERFACE</span>
+<a name="l00877"></a>00877 <span class="preprocessor"></span>        <span class="keyword">struct </span>lm_device *lm_dev = container_of(_dev, <span class="keyword">struct</span> lm_device, dev);
+<a name="l00878"></a>00878         <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = lm_get_drvdata(lm_dev);
+<a name="l00879"></a>00879 <span class="preprocessor">#elif PCI_INTERFACE</span>
+<a name="l00880"></a>00880 <span class="preprocessor"></span>        <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = dev_get_drvdata(_dev);
+<a name="l00881"></a>00881 <span class="preprocessor">#endif</span>
+<a name="l00882"></a>00882 <span class="preprocessor"></span>
+<a name="l00883"></a>00883         <a class="code" href="dwc__otg__hcd_8c.html#b2c46e92cdc57b1783f445ed60cc3f38">dwc_otg_hcd_dump_frrem</a>(otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#834ef28e884f0d7fcac68f3bdf5c4b33">hcd</a>);
+<a name="l00884"></a>00884 <span class="preprocessor">#endif </span><span class="comment">/* DWC_DEVICE_ONLY */</span>
+<a name="l00885"></a>00885         <span class="keywordflow">return</span> sprintf(buf, <span class="stringliteral">"HCD Dump Frame Remaining\n"</span>);
+<a name="l00886"></a>00886 }
+<a name="l00887"></a>00887 
+<a name="l00888"></a><a class="code" href="dwc__otg__attr_8c.html#ac2308832629daf78cb9dd123551cd8a">00888</a> DEVICE_ATTR(<a class="code" href="dwc__otg__attr_8c.html#98c5b16a6162e4c9057aee72a7216efb">hcd_frrem</a>, S_IRUGO | <a class="code" href="dwc__otg__attr_8c.html#ac2308832629daf78cb9dd123551cd8a">S_IWUSR</a>, <a class="code" href="dwc__otg__attr_8c.html#95ea28023a1ac497504fc5868d3b4d66">hcd_frrem_show</a>, 0);
+<a name="l00889"></a>00889 
+<a name="l00894"></a><a class="code" href="dwc__otg__attr_8c.html#5f954c85228b04a896cab754ab56358e">00894</a> <span class="preprocessor">#define RW_REG_COUNT 10000000</span>
+<a name="l00895"></a><a class="code" href="dwc__otg__attr_8c.html#4e04f10b5ae5b78f1bc8b3c2e8af8f92">00895</a> <span class="preprocessor"></span><span class="preprocessor">#define MSEC_PER_JIFFIE 1000/HZ</span>
+<a name="l00896"></a><a class="code" href="dwc__otg__attr_8c.html#81946b90c6e16e9596d9b9ccd1d54476">00896</a> <span class="preprocessor"></span><span class="keyword">static</span> ssize_t <a class="code" href="dwc__otg__attr_8c.html#3a4e297d31636537346c61e2e04de115">rd_reg_test_show</a>(<span class="keyword">struct</span> device *_dev,
+<a name="l00897"></a>00897                                 <span class="keyword">struct</span> device_attribute *attr, <span class="keywordtype">char</span> *buf)
+<a name="l00898"></a>00898 {
+<a name="l00899"></a>00899 <span class="preprocessor">#ifdef LM_INTERFACE</span>
+<a name="l00900"></a>00900 <span class="preprocessor"></span>        <span class="keyword">struct </span>lm_device *lm_dev = container_of(_dev, <span class="keyword">struct</span> lm_device, dev);
+<a name="l00901"></a>00901         <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = lm_get_drvdata(lm_dev);
+<a name="l00902"></a>00902 <span class="preprocessor">#elif PCI_INTERFACE</span>
+<a name="l00903"></a>00903 <span class="preprocessor"></span>        <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = dev_get_drvdata(_dev);
+<a name="l00904"></a>00904 <span class="preprocessor">#endif</span>
+<a name="l00905"></a>00905 <span class="preprocessor"></span>
+<a name="l00906"></a>00906         <span class="keywordtype">int</span> i;
+<a name="l00907"></a>00907         <span class="keywordtype">int</span> time;
+<a name="l00908"></a>00908         <span class="keywordtype">int</span> start_jiffies;
+<a name="l00909"></a>00909 
+<a name="l00910"></a>00910         printk(<span class="stringliteral">"HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n"</span>,
+<a name="l00911"></a>00911                HZ, <a class="code" href="dwc__otg__attr_8c.html#4e04f10b5ae5b78f1bc8b3c2e8af8f92">MSEC_PER_JIFFIE</a>, loops_per_jiffy);
+<a name="l00912"></a>00912         start_jiffies = jiffies;
+<a name="l00913"></a>00913         <span class="keywordflow">for</span> (i = 0; i &lt; <a class="code" href="dwc__otg__attr_8c.html#5f954c85228b04a896cab754ab56358e">RW_REG_COUNT</a>; i++) {
+<a name="l00914"></a>00914                 <a class="code" href="dwc__otg__cil_8c.html#3110e552598b04bbe6b30bcddadda98b">dwc_otg_get_gnptxfsiz</a>(otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#4cc7c9f6e473072c2ed0a5e6adb25ebe">core_if</a>);
+<a name="l00915"></a>00915         }
+<a name="l00916"></a>00916         time = jiffies - start_jiffies;
+<a name="l00917"></a>00917         <span class="keywordflow">return</span> sprintf(buf,
+<a name="l00918"></a>00918                        <span class="stringliteral">"Time to read GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n"</span>,
+<a name="l00919"></a>00919                        RW_REG_COUNT, time * <a class="code" href="dwc__otg__attr_8c.html#4e04f10b5ae5b78f1bc8b3c2e8af8f92">MSEC_PER_JIFFIE</a>, time);
+<a name="l00920"></a>00920 }
+<a name="l00921"></a>00921 
+<a name="l00922"></a><a class="code" href="dwc__otg__attr_8c.html#ac2308832629daf78cb9dd123551cd8a">00922</a> DEVICE_ATTR(<a class="code" href="dwc__otg__attr_8c.html#829fa87e3e65ff4038b6bc0eb2a93fb7">rd_reg_test</a>, S_IRUGO | <a class="code" href="dwc__otg__attr_8c.html#ac2308832629daf78cb9dd123551cd8a">S_IWUSR</a>, <a class="code" href="dwc__otg__attr_8c.html#3a4e297d31636537346c61e2e04de115">rd_reg_test_show</a>, 0);
+<a name="l00923"></a>00923 
+<a name="l00928"></a><a class="code" href="dwc__otg__attr_8c.html#9dd7132e3f334eed0e27e11ab5f7b0c4">00928</a> <span class="keyword">static</span> ssize_t <a class="code" href="dwc__otg__attr_8c.html#bc692a23b59ffdb09d9ef3fd468fbff7">wr_reg_test_show</a>(<span class="keyword">struct</span> device *_dev,
+<a name="l00929"></a>00929                                 <span class="keyword">struct</span> device_attribute *attr, <span class="keywordtype">char</span> *buf)
+<a name="l00930"></a>00930 {
+<a name="l00931"></a>00931 <span class="preprocessor">#ifdef LM_INTERFACE</span>
+<a name="l00932"></a>00932 <span class="preprocessor"></span>        <span class="keyword">struct </span>lm_device *lm_dev = container_of(_dev, <span class="keyword">struct</span> lm_device, dev);
+<a name="l00933"></a>00933         <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = lm_get_drvdata(lm_dev);
+<a name="l00934"></a>00934 <span class="preprocessor">#elif PCI_INTERFACE</span>
+<a name="l00935"></a>00935 <span class="preprocessor"></span>        <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = dev_get_drvdata(_dev);
+<a name="l00936"></a>00936 <span class="preprocessor">#endif</span>
+<a name="l00937"></a>00937 <span class="preprocessor"></span>
+<a name="l00938"></a>00938         uint32_t reg_val;
+<a name="l00939"></a>00939         <span class="keywordtype">int</span> i;
+<a name="l00940"></a>00940         <span class="keywordtype">int</span> time;
+<a name="l00941"></a>00941         <span class="keywordtype">int</span> start_jiffies;
+<a name="l00942"></a>00942 
+<a name="l00943"></a>00943         printk(<span class="stringliteral">"HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n"</span>,
+<a name="l00944"></a>00944                HZ, <a class="code" href="dwc__otg__attr_8c.html#4e04f10b5ae5b78f1bc8b3c2e8af8f92">MSEC_PER_JIFFIE</a>, loops_per_jiffy);
+<a name="l00945"></a>00945         reg_val = <a class="code" href="dwc__otg__cil_8c.html#3110e552598b04bbe6b30bcddadda98b">dwc_otg_get_gnptxfsiz</a>(otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#4cc7c9f6e473072c2ed0a5e6adb25ebe">core_if</a>);
+<a name="l00946"></a>00946         start_jiffies = jiffies;
+<a name="l00947"></a>00947         <span class="keywordflow">for</span> (i = 0; i &lt; <a class="code" href="dwc__otg__attr_8c.html#5f954c85228b04a896cab754ab56358e">RW_REG_COUNT</a>; i++) {
+<a name="l00948"></a>00948                 <a class="code" href="dwc__otg__cil_8c.html#48c625d569671523aac60af8e2d60d7a">dwc_otg_set_gnptxfsiz</a>(otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#4cc7c9f6e473072c2ed0a5e6adb25ebe">core_if</a>, reg_val);
+<a name="l00949"></a>00949         }
+<a name="l00950"></a>00950         time = jiffies - start_jiffies;
+<a name="l00951"></a>00951         <span class="keywordflow">return</span> sprintf(buf,
+<a name="l00952"></a>00952                        <span class="stringliteral">"Time to write GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n"</span>,
+<a name="l00953"></a>00953                        RW_REG_COUNT, time * <a class="code" href="dwc__otg__attr_8c.html#4e04f10b5ae5b78f1bc8b3c2e8af8f92">MSEC_PER_JIFFIE</a>, time);
+<a name="l00954"></a>00954 }
+<a name="l00955"></a>00955 
+<a name="l00956"></a><a class="code" href="dwc__otg__attr_8c.html#bc692a23b59ffdb09d9ef3fd468fbff7">00956</a> DEVICE_ATTR(<a class="code" href="dwc__otg__attr_8c.html#b46682cc35d8ddece607cdf93c124575">wr_reg_test</a>, S_IRUGO | <a class="code" href="dwc__otg__attr_8c.html#ac2308832629daf78cb9dd123551cd8a">S_IWUSR</a>, <a class="code" href="dwc__otg__attr_8c.html#bc692a23b59ffdb09d9ef3fd468fbff7">wr_reg_test_show</a>, 0);
+<a name="l00957"></a>00957 
+<a name="l00958"></a>00958 <span class="preprocessor">#ifdef CONFIG_USB_DWC_OTG_LPM</span>
+<a name="l00959"></a>00959 <span class="preprocessor"></span>
+<a name="l00963"></a>00963 <span class="keyword">static</span> ssize_t lpmresp_show(<span class="keyword">struct</span> device *_dev,
+<a name="l00964"></a>00964                             <span class="keyword">struct</span> device_attribute *attr, <span class="keywordtype">char</span> *buf)
+<a name="l00965"></a>00965 {
+<a name="l00966"></a>00966 <span class="preprocessor">#ifdef LM_INTERFACE</span>
+<a name="l00967"></a>00967 <span class="preprocessor"></span>        <span class="keyword">struct </span>lm_device *lm_dev = container_of(_dev, <span class="keyword">struct</span> lm_device, dev);
+<a name="l00968"></a>00968         <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = lm_get_drvdata(lm_dev);
+<a name="l00969"></a>00969 <span class="preprocessor">#elif PCI_INTERFACE</span>
+<a name="l00970"></a>00970 <span class="preprocessor"></span>        <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = dev_get_drvdata(_dev);
+<a name="l00971"></a>00971 <span class="preprocessor">#endif</span>
+<a name="l00972"></a>00972 <span class="preprocessor"></span>
+<a name="l00973"></a>00973         <span class="keywordflow">if</span> (!<a class="code" href="dwc__otg__cil_8c.html#0e0eb29733595730396da3ddf3d0ded5">dwc_otg_get_param_lpm_enable</a>(otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#4cc7c9f6e473072c2ed0a5e6adb25ebe">core_if</a>))
+<a name="l00974"></a>00974                 <span class="keywordflow">return</span> sprintf(buf, <span class="stringliteral">"** LPM is DISABLED **\n"</span>);
+<a name="l00975"></a>00975 
+<a name="l00976"></a>00976         <span class="keywordflow">if</span> (!<a class="code" href="dwc__otg__cil_8c.html#e83fb22890bc54c6b06cedb751430e77">dwc_otg_is_device_mode</a>(otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#4cc7c9f6e473072c2ed0a5e6adb25ebe">core_if</a>)) {
+<a name="l00977"></a>00977                 <span class="keywordflow">return</span> sprintf(buf, <span class="stringliteral">"** Current mode is not device mode\n"</span>);
+<a name="l00978"></a>00978         }
+<a name="l00979"></a>00979         <span class="keywordflow">return</span> sprintf(buf, <span class="stringliteral">"lpm_response = %d\n"</span>,
+<a name="l00980"></a>00980                        <a class="code" href="dwc__otg__cil_8c.html#86d921a91b7e2b143a305283282ce36d">dwc_otg_get_lpmresponse</a>(otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#4cc7c9f6e473072c2ed0a5e6adb25ebe">core_if</a>));
+<a name="l00981"></a>00981 }
+<a name="l00982"></a>00982 
+<a name="l00986"></a>00986 <span class="keyword">static</span> ssize_t lpmresp_store(<span class="keyword">struct</span> device *_dev,
+<a name="l00987"></a>00987                              <span class="keyword">struct</span> device_attribute *attr,
+<a name="l00988"></a>00988                              <span class="keyword">const</span> <span class="keywordtype">char</span> *buf, size_t count)
+<a name="l00989"></a>00989 {
+<a name="l00990"></a>00990 <span class="preprocessor">#ifdef LM_INTERFACE</span>
+<a name="l00991"></a>00991 <span class="preprocessor"></span>        <span class="keyword">struct </span>lm_device *lm_dev = container_of(_dev, <span class="keyword">struct</span> lm_device, dev);
+<a name="l00992"></a>00992         <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = lm_get_drvdata(lm_dev);
+<a name="l00993"></a>00993 <span class="preprocessor">#elif PCI_INTERFACE</span>
+<a name="l00994"></a>00994 <span class="preprocessor"></span>        <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = dev_get_drvdata(_dev);
+<a name="l00995"></a>00995 <span class="preprocessor">#endif</span>
+<a name="l00996"></a>00996 <span class="preprocessor"></span>
+<a name="l00997"></a>00997         uint32_t val = simple_strtoul(buf, NULL, 16);
+<a name="l00998"></a>00998 
+<a name="l00999"></a>00999         <span class="keywordflow">if</span> (!<a class="code" href="dwc__otg__cil_8c.html#0e0eb29733595730396da3ddf3d0ded5">dwc_otg_get_param_lpm_enable</a>(otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#4cc7c9f6e473072c2ed0a5e6adb25ebe">core_if</a>)) {
+<a name="l01000"></a>01000                 <span class="keywordflow">return</span> 0;
+<a name="l01001"></a>01001         }
+<a name="l01002"></a>01002 
+<a name="l01003"></a>01003         <span class="keywordflow">if</span> (!<a class="code" href="dwc__otg__cil_8c.html#e83fb22890bc54c6b06cedb751430e77">dwc_otg_is_device_mode</a>(otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#4cc7c9f6e473072c2ed0a5e6adb25ebe">core_if</a>)) {
+<a name="l01004"></a>01004                 <span class="keywordflow">return</span> 0;
+<a name="l01005"></a>01005         }
+<a name="l01006"></a>01006 
+<a name="l01007"></a>01007         <a class="code" href="dwc__otg__cil_8c.html#b19565bc2a8dbb258c3c2cb8c52240b8">dwc_otg_set_lpmresponse</a>(otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#4cc7c9f6e473072c2ed0a5e6adb25ebe">core_if</a>, val);
+<a name="l01008"></a>01008         <span class="keywordflow">return</span> count;
+<a name="l01009"></a>01009 }
+<a name="l01010"></a>01010 
+<a name="l01011"></a>01011 DEVICE_ATTR(lpm_response, S_IRUGO | <a class="code" href="dwc__otg__attr_8c.html#ac2308832629daf78cb9dd123551cd8a">S_IWUSR</a>, lpmresp_show, lpmresp_store);
+<a name="l01012"></a>01012 
+<a name="l01016"></a>01016 <span class="keyword">static</span> ssize_t sleepstatus_show(<span class="keyword">struct</span> device *_dev,
+<a name="l01017"></a>01017                                 <span class="keyword">struct</span> device_attribute *attr, <span class="keywordtype">char</span> *buf)
+<a name="l01018"></a>01018 {
+<a name="l01019"></a>01019 <span class="preprocessor">#ifdef LM_INTERFACE</span>
+<a name="l01020"></a>01020 <span class="preprocessor"></span>        <span class="keyword">struct </span>lm_device *lm_dev = container_of(_dev, <span class="keyword">struct</span> lm_device, dev);
+<a name="l01021"></a>01021         <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = lm_get_drvdata(lm_dev);
+<a name="l01022"></a>01022 <span class="preprocessor">#elif PCI_INTERFACE</span>
+<a name="l01023"></a>01023 <span class="preprocessor"></span>        <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = dev_get_drvdata(_dev);
+<a name="l01024"></a>01024 <span class="preprocessor">#endif</span>
+<a name="l01025"></a>01025 <span class="preprocessor"></span>
+<a name="l01026"></a>01026 
+<a name="l01027"></a>01027         <span class="keywordflow">return</span> sprintf(buf, <span class="stringliteral">"Sleep Status = %d\n"</span>,
+<a name="l01028"></a>01028                        <a class="code" href="dwc__otg__cil_8c.html#87d643973839554bac437d283a462e00">dwc_otg_get_lpm_portsleepstatus</a>(otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#4cc7c9f6e473072c2ed0a5e6adb25ebe">core_if</a>));
+<a name="l01029"></a>01029 }
+<a name="l01030"></a>01030 
+<a name="l01034"></a>01034 <span class="keyword">static</span> ssize_t sleepstatus_store(<span class="keyword">struct</span> device *_dev,
+<a name="l01035"></a>01035                                  <span class="keyword">struct</span> device_attribute *attr,
+<a name="l01036"></a>01036                                  <span class="keyword">const</span> <span class="keywordtype">char</span> *buf, size_t count)
+<a name="l01037"></a>01037 {
+<a name="l01038"></a>01038 <span class="preprocessor">#ifdef LM_INTERFACE</span>
+<a name="l01039"></a>01039 <span class="preprocessor"></span>        <span class="keyword">struct </span>lm_device *lm_dev = container_of(_dev, <span class="keyword">struct</span> lm_device, dev);
+<a name="l01040"></a>01040         <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = lm_get_drvdata(lm_dev);
+<a name="l01041"></a>01041 <span class="preprocessor">#elif PCI_INTERFACE</span>
+<a name="l01042"></a>01042 <span class="preprocessor"></span>        <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = dev_get_drvdata(_dev);
+<a name="l01043"></a>01043 <span class="preprocessor">#endif</span>
+<a name="l01044"></a>01044 <span class="preprocessor"></span>
+<a name="l01045"></a>01045         <a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if = otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#4cc7c9f6e473072c2ed0a5e6adb25ebe">core_if</a>;
+<a name="l01046"></a>01046 
+<a name="l01047"></a>01047         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#87d643973839554bac437d283a462e00">dwc_otg_get_lpm_portsleepstatus</a>(otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#4cc7c9f6e473072c2ed0a5e6adb25ebe">core_if</a>)) {
+<a name="l01048"></a>01048                 <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#f0bfe5f933e21a94ea06c96ffc086e72">dwc_otg_is_host_mode</a>(core_if)) {
+<a name="l01049"></a>01049 
+<a name="l01050"></a>01050                         DWC_PRINTF(<span class="stringliteral">"Host initiated resume\n"</span>);
+<a name="l01051"></a>01051                         <a class="code" href="dwc__otg__cil_8c.html#b6d6b18934ba5cd4ce2cf9e68be338f5">dwc_otg_set_prtresume</a>(otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#4cc7c9f6e473072c2ed0a5e6adb25ebe">core_if</a>, 1);
+<a name="l01052"></a>01052                 }
+<a name="l01053"></a>01053         }
+<a name="l01054"></a>01054 
+<a name="l01055"></a>01055         <span class="keywordflow">return</span> count;
+<a name="l01056"></a>01056 }
+<a name="l01057"></a>01057 
+<a name="l01058"></a>01058 DEVICE_ATTR(sleep_status, S_IRUGO | <a class="code" href="dwc__otg__attr_8c.html#ac2308832629daf78cb9dd123551cd8a">S_IWUSR</a>, sleepstatus_show,
+<a name="l01059"></a>01059             sleepstatus_store);
+<a name="l01060"></a>01060 
+<a name="l01061"></a>01061 <span class="preprocessor">#endif                          </span><span class="comment">/* CONFIG_USB_DWC_OTG_LPM_ENABLE */</span>
+<a name="l01062"></a>01062 
+<a name="l01068"></a><a class="code" href="dwc__otg__attr_8h.html#a0ccc83a12d3ee16db6436d0e2fab197">01068</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__attr_8c.html#792fccf68b5f00d193f800822a5d888b">dwc_otg_attr_create</a> (
+<a name="l01069"></a>01069 #ifdef LM_INTERFACE
+<a name="l01070"></a>01070         <span class="keyword">struct</span> lm_device *dev
+<a name="l01071"></a>01071 #elif  PCI_INTERFACE
+<a name="l01072"></a>01072         <span class="keyword">struct</span> pci_dev *dev
+<a name="l01073"></a>01073 #endif
+<a name="l01074"></a>01074         )
+<a name="l01075"></a>01075 
+<a name="l01076"></a>01076 {
+<a name="l01077"></a>01077         <span class="keywordtype">int</span> error;
+<a name="l01078"></a>01078 
+<a name="l01079"></a>01079         error = device_create_file(&amp;dev-&gt;dev, &amp;dev_attr_regoffset);
+<a name="l01080"></a>01080         error = device_create_file(&amp;dev-&gt;dev, &amp;dev_attr_regvalue);
+<a name="l01081"></a>01081         error = device_create_file(&amp;dev-&gt;dev, &amp;dev_attr_mode);
+<a name="l01082"></a>01082         error = device_create_file(&amp;dev-&gt;dev, &amp;dev_attr_hnpcapable);
+<a name="l01083"></a>01083         error = device_create_file(&amp;dev-&gt;dev, &amp;dev_attr_srpcapable);
+<a name="l01084"></a>01084         error = device_create_file(&amp;dev-&gt;dev, &amp;dev_attr_hsic_connect);
+<a name="l01085"></a>01085         error = device_create_file(&amp;dev-&gt;dev, &amp;dev_attr_inv_sel_hsic);
+<a name="l01086"></a>01086         error = device_create_file(&amp;dev-&gt;dev, &amp;dev_attr_hnp);
+<a name="l01087"></a>01087         error = device_create_file(&amp;dev-&gt;dev, &amp;dev_attr_srp);
+<a name="l01088"></a>01088         error = device_create_file(&amp;dev-&gt;dev, &amp;dev_attr_buspower);
+<a name="l01089"></a>01089         error = device_create_file(&amp;dev-&gt;dev, &amp;dev_attr_bussuspend);
+<a name="l01090"></a>01090         error = device_create_file(&amp;dev-&gt;dev, &amp;dev_attr_busconnected);
+<a name="l01091"></a>01091         error = device_create_file(&amp;dev-&gt;dev, &amp;dev_attr_gotgctl);
+<a name="l01092"></a>01092         error = device_create_file(&amp;dev-&gt;dev, &amp;dev_attr_gusbcfg);
+<a name="l01093"></a>01093         error = device_create_file(&amp;dev-&gt;dev, &amp;dev_attr_grxfsiz);
+<a name="l01094"></a>01094         error = device_create_file(&amp;dev-&gt;dev, &amp;dev_attr_gnptxfsiz);
+<a name="l01095"></a>01095         error = device_create_file(&amp;dev-&gt;dev, &amp;dev_attr_gpvndctl);
+<a name="l01096"></a>01096         error = device_create_file(&amp;dev-&gt;dev, &amp;dev_attr_ggpio);
+<a name="l01097"></a>01097         error = device_create_file(&amp;dev-&gt;dev, &amp;dev_attr_guid);
+<a name="l01098"></a>01098         error = device_create_file(&amp;dev-&gt;dev, &amp;dev_attr_gsnpsid);
+<a name="l01099"></a>01099         error = device_create_file(&amp;dev-&gt;dev, &amp;dev_attr_devspeed);
+<a name="l01100"></a>01100         error = device_create_file(&amp;dev-&gt;dev, &amp;dev_attr_enumspeed);
+<a name="l01101"></a>01101         error = device_create_file(&amp;dev-&gt;dev, &amp;dev_attr_hptxfsiz);
+<a name="l01102"></a>01102         error = device_create_file(&amp;dev-&gt;dev, &amp;dev_attr_hprt0);
+<a name="l01103"></a>01103         error = device_create_file(&amp;dev-&gt;dev, &amp;dev_attr_remote_wakeup);
+<a name="l01104"></a>01104         error = device_create_file(&amp;dev-&gt;dev, &amp;dev_attr_regdump);
+<a name="l01105"></a>01105         error = device_create_file(&amp;dev-&gt;dev, &amp;dev_attr_spramdump);
+<a name="l01106"></a>01106         error = device_create_file(&amp;dev-&gt;dev, &amp;dev_attr_hcddump);
+<a name="l01107"></a>01107         error = device_create_file(&amp;dev-&gt;dev, &amp;dev_attr_hcd_frrem);
+<a name="l01108"></a>01108         error = device_create_file(&amp;dev-&gt;dev, &amp;dev_attr_rd_reg_test);
+<a name="l01109"></a>01109         error = device_create_file(&amp;dev-&gt;dev, &amp;dev_attr_wr_reg_test);
+<a name="l01110"></a>01110 <span class="preprocessor">#ifdef CONFIG_USB_DWC_OTG_LPM</span>
+<a name="l01111"></a>01111 <span class="preprocessor"></span>        error = device_create_file(&amp;dev-&gt;dev, &amp;dev_attr_lpm_response);
+<a name="l01112"></a>01112         error = device_create_file(&amp;dev-&gt;dev, &amp;dev_attr_sleep_status);
+<a name="l01113"></a>01113 <span class="preprocessor">#endif</span>
+<a name="l01114"></a>01114 <span class="preprocessor"></span>}
+<a name="l01115"></a>01115 
+<a name="l01119"></a><a class="code" href="dwc__otg__attr_8h.html#4b0aa5ebf3661ec8ab5566b20c233674">01119</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__attr_8c.html#4b0aa5ebf3661ec8ab5566b20c233674">dwc_otg_attr_remove</a> (
+<a name="l01120"></a>01120 #ifdef LM_INTERFACE
+<a name="l01121"></a>01121         <span class="keyword">struct</span> lm_device *dev
+<a name="l01122"></a>01122 #elif  PCI_INTERFACE
+<a name="l01123"></a>01123         <span class="keyword">struct</span> pci_dev *dev
+<a name="l01124"></a>01124 #endif
+<a name="l01125"></a>01125        )
+<a name="l01126"></a>01126 
+<a name="l01127"></a>01127 {
+<a name="l01128"></a>01128         device_remove_file(&amp;dev-&gt;dev, &amp;dev_attr_regoffset);
+<a name="l01129"></a>01129         device_remove_file(&amp;dev-&gt;dev, &amp;dev_attr_regvalue);
+<a name="l01130"></a>01130         device_remove_file(&amp;dev-&gt;dev, &amp;dev_attr_mode);
+<a name="l01131"></a>01131         device_remove_file(&amp;dev-&gt;dev, &amp;dev_attr_hnpcapable);
+<a name="l01132"></a>01132         device_remove_file(&amp;dev-&gt;dev, &amp;dev_attr_srpcapable);
+<a name="l01133"></a>01133         device_remove_file(&amp;dev-&gt;dev, &amp;dev_attr_hsic_connect);
+<a name="l01134"></a>01134         device_remove_file(&amp;dev-&gt;dev, &amp;dev_attr_inv_sel_hsic);
+<a name="l01135"></a>01135         device_remove_file(&amp;dev-&gt;dev, &amp;dev_attr_hnp);
+<a name="l01136"></a>01136         device_remove_file(&amp;dev-&gt;dev, &amp;dev_attr_srp);
+<a name="l01137"></a>01137         device_remove_file(&amp;dev-&gt;dev, &amp;dev_attr_buspower);
+<a name="l01138"></a>01138         device_remove_file(&amp;dev-&gt;dev, &amp;dev_attr_bussuspend);
+<a name="l01139"></a>01139         device_remove_file(&amp;dev-&gt;dev, &amp;dev_attr_busconnected);
+<a name="l01140"></a>01140         device_remove_file(&amp;dev-&gt;dev, &amp;dev_attr_gotgctl);
+<a name="l01141"></a>01141         device_remove_file(&amp;dev-&gt;dev, &amp;dev_attr_gusbcfg);
+<a name="l01142"></a>01142         device_remove_file(&amp;dev-&gt;dev, &amp;dev_attr_grxfsiz);
+<a name="l01143"></a>01143         device_remove_file(&amp;dev-&gt;dev, &amp;dev_attr_gnptxfsiz);
+<a name="l01144"></a>01144         device_remove_file(&amp;dev-&gt;dev, &amp;dev_attr_gpvndctl);
+<a name="l01145"></a>01145         device_remove_file(&amp;dev-&gt;dev, &amp;dev_attr_ggpio);
+<a name="l01146"></a>01146         device_remove_file(&amp;dev-&gt;dev, &amp;dev_attr_guid);
+<a name="l01147"></a>01147         device_remove_file(&amp;dev-&gt;dev, &amp;dev_attr_gsnpsid);
+<a name="l01148"></a>01148         device_remove_file(&amp;dev-&gt;dev, &amp;dev_attr_devspeed);
+<a name="l01149"></a>01149         device_remove_file(&amp;dev-&gt;dev, &amp;dev_attr_enumspeed);
+<a name="l01150"></a>01150         device_remove_file(&amp;dev-&gt;dev, &amp;dev_attr_hptxfsiz);
+<a name="l01151"></a>01151         device_remove_file(&amp;dev-&gt;dev, &amp;dev_attr_hprt0);
+<a name="l01152"></a>01152         device_remove_file(&amp;dev-&gt;dev, &amp;dev_attr_remote_wakeup);
+<a name="l01153"></a>01153         device_remove_file(&amp;dev-&gt;dev, &amp;dev_attr_regdump);
+<a name="l01154"></a>01154         device_remove_file(&amp;dev-&gt;dev, &amp;dev_attr_spramdump);
+<a name="l01155"></a>01155         device_remove_file(&amp;dev-&gt;dev, &amp;dev_attr_hcddump);
+<a name="l01156"></a>01156         device_remove_file(&amp;dev-&gt;dev, &amp;dev_attr_hcd_frrem);
+<a name="l01157"></a>01157         device_remove_file(&amp;dev-&gt;dev, &amp;dev_attr_rd_reg_test);
+<a name="l01158"></a>01158         device_remove_file(&amp;dev-&gt;dev, &amp;dev_attr_wr_reg_test);
+<a name="l01159"></a>01159 <span class="preprocessor">#ifdef CONFIG_USB_DWC_OTG_LPM</span>
+<a name="l01160"></a>01160 <span class="preprocessor"></span>        device_remove_file(&amp;dev-&gt;dev, &amp;dev_attr_lpm_response);
+<a name="l01161"></a>01161         device_remove_file(&amp;dev-&gt;dev, &amp;dev_attr_sleep_status);
+<a name="l01162"></a>01162 <span class="preprocessor">#endif</span>
+<a name="l01163"></a>01163 <span class="preprocessor"></span>}
+</pre></div><hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/dwc__otg__attr_8c.html b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__attr_8c.html
new file mode 100644
index 000000000000..eafdd832cad6
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__attr_8c.html
@@ -0,0 +1,485 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_attr.c File Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<h1>dwc_otg_attr.c File Reference</h1>The diagnostic interface will provide access to the controller for bringing up the hardware and testing. <a href="#_details">More...</a>
+<p>
+<code>#include &lt;linux/kernel.h&gt;</code><br>
+<code>#include &lt;linux/module.h&gt;</code><br>
+<code>#include &lt;linux/moduleparam.h&gt;</code><br>
+<code>#include &lt;linux/init.h&gt;</code><br>
+<code>#include &lt;linux/device.h&gt;</code><br>
+<code>#include &lt;linux/errno.h&gt;</code><br>
+<code>#include &lt;linux/types.h&gt;</code><br>
+<code>#include &lt;linux/stat.h&gt;</code><br>
+<code>#include &lt;linux/version.h&gt;</code><br>
+<code>#include &lt;linux/param.h&gt;</code><br>
+<code>#include &lt;linux/delay.h&gt;</code><br>
+<code>#include &lt;linux/jiffies.h&gt;</code><br>
+<code>#include &lt;asm/io.h&gt;</code><br>
+<code>#include &quot;dwc_os.h&quot;</code><br>
+<code>#include &quot;<a class="el" href="dwc__otg__driver_8h-source.html">dwc_otg_driver.h</a>&quot;</code><br>
+<code>#include &quot;<a class="el" href="dwc__otg__attr_8h-source.html">dwc_otg_attr.h</a>&quot;</code><br>
+<code>#include &quot;<a class="el" href="dwc__otg__core__if_8h-source.html">dwc_otg_core_if.h</a>&quot;</code><br>
+<code>#include &quot;<a class="el" href="dwc__otg__pcd__if_8h-source.html">dwc_otg_pcd_if.h</a>&quot;</code><br>
+<code>#include &quot;<a class="el" href="dwc__otg__hcd__if_8h-source.html">dwc_otg_hcd_if.h</a>&quot;</code><br>
+
+<p>
+<a href="dwc__otg__attr_8c-source.html">Go to the source code of this file.</a><table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Functions for Show/Store of Attributes</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="5f954c85228b04a896cab754ab56358e"></a><!-- doxytag: member="dwc_otg_attr.c::RW_REG_COUNT" ref="5f954c85228b04a896cab754ab56358e" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__attr_8c.html#5f954c85228b04a896cab754ab56358e">RW_REG_COUNT</a>&nbsp;&nbsp;&nbsp;10000000</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Displays the time required to read the GNPTXFSIZ register many times (the output shows the number of times the register is read). <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="4e04f10b5ae5b78f1bc8b3c2e8af8f92"></a><!-- doxytag: member="dwc_otg_attr.c::MSEC_PER_JIFFIE" ref="4e04f10b5ae5b78f1bc8b3c2e8af8f92" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__attr_8c.html#4e04f10b5ae5b78f1bc8b3c2e8af8f92">MSEC_PER_JIFFIE</a>&nbsp;&nbsp;&nbsp;1000/HZ</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ca58f009788e262a917c23784a84cb16"></a><!-- doxytag: member="dwc_otg_attr.c::regoffset_show" ref="ca58f009788e262a917c23784a84cb16" args="(struct device *_dev, struct device_attribute *attr, char *buf)" -->
+static ssize_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__attr_8c.html#ca58f009788e262a917c23784a84cb16">regoffset_show</a> (struct device *_dev, struct device_attribute *attr, char *buf)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Show the register offset of the Register Access. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="fc5be3dbcd075f5087ca1730661c5dc2"></a><!-- doxytag: member="dwc_otg_attr.c::regoffset_store" ref="fc5be3dbcd075f5087ca1730661c5dc2" args="(struct device *_dev, struct device_attribute *attr, const char *buf, size_t count)" -->
+static ssize_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__attr_8c.html#fc5be3dbcd075f5087ca1730661c5dc2">regoffset_store</a> (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Set the register offset for the next Register Access Read/Write. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="bb38eb60bd43b1de364db80fd1bcdbcf"></a><!-- doxytag: member="dwc_otg_attr.c::regvalue_show" ref="bb38eb60bd43b1de364db80fd1bcdbcf" args="(struct device *_dev, struct device_attribute *attr, char *buf)" -->
+static ssize_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__attr_8c.html#bb38eb60bd43b1de364db80fd1bcdbcf">regvalue_show</a> (struct device *_dev, struct device_attribute *attr, char *buf)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Show the value of the register at the offset in the reg_offset attribute. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7db6b85ac60be49f52987e615a01408b"></a><!-- doxytag: member="dwc_otg_attr.c::regvalue_store" ref="7db6b85ac60be49f52987e615a01408b" args="(struct device *_dev, struct device_attribute *attr, const char *buf, size_t count)" -->
+static ssize_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__attr_8c.html#7db6b85ac60be49f52987e615a01408b">regvalue_store</a> (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Store the value in the register at the offset in the reg_offset attribute. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="a6ede17e817a37b1207d7a82147a8e57"></a><!-- doxytag: member="dwc_otg_attr.c::DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW" ref="a6ede17e817a37b1207d7a82147a8e57" args="(mode,&quot;Mode&quot;)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__attr_8c.html#a6ede17e817a37b1207d7a82147a8e57">DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW</a> (mode,&quot;Mode&quot;)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="14b1910d541301f5456e2a15a3b4f0b0"></a><!-- doxytag: member="dwc_otg_attr.c::hnp_store" ref="14b1910d541301f5456e2a15a3b4f0b0" args="(struct device *_dev, struct device_attribute *attr, const char *buf, size_t count)" -->
+static ssize_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__attr_8c.html#14b1910d541301f5456e2a15a3b4f0b0">hnp_store</a> (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Set the HNP Request bit. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="9e8313bb6a0f54484d279b2e28269712"></a><!-- doxytag: member="dwc_otg_attr.c::srp_show" ref="9e8313bb6a0f54484d279b2e28269712" args="(struct device *_dev, struct device_attribute *attr, char *buf)" -->
+static ssize_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__attr_8c.html#9e8313bb6a0f54484d279b2e28269712">srp_show</a> (struct device *_dev, struct device_attribute *attr, char *buf)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Show the SRP status bit. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="80c785e24be4a8ce02d0b38a0ba5484a"></a><!-- doxytag: member="dwc_otg_attr.c::srp_store" ref="80c785e24be4a8ce02d0b38a0ba5484a" args="(struct device *_dev, struct device_attribute *attr, const char *buf, size_t count)" -->
+static ssize_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__attr_8c.html#80c785e24be4a8ce02d0b38a0ba5484a">srp_store</a> (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Set the SRP Request bit. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="6979f4909cde868d800dba13ef95aa8c"></a><!-- doxytag: member="dwc_otg_attr.c::buspower_show" ref="6979f4909cde868d800dba13ef95aa8c" args="(struct device *_dev, struct device_attribute *attr, char *buf)" -->
+static ssize_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__attr_8c.html#6979f4909cde868d800dba13ef95aa8c">buspower_show</a> (struct device *_dev, struct device_attribute *attr, char *buf)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Show the Bus Power status. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="4514a396df18dae15f7f03f640f52ac7"></a><!-- doxytag: member="dwc_otg_attr.c::buspower_store" ref="4514a396df18dae15f7f03f640f52ac7" args="(struct device *_dev, struct device_attribute *attr, const char *buf, size_t count)" -->
+static ssize_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__attr_8c.html#4514a396df18dae15f7f03f640f52ac7">buspower_store</a> (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Set the Bus Power status. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ae1f7e3a17c5a0bcc5a93096aeb902d2"></a><!-- doxytag: member="dwc_otg_attr.c::bussuspend_show" ref="ae1f7e3a17c5a0bcc5a93096aeb902d2" args="(struct device *_dev, struct device_attribute *attr, char *buf)" -->
+static ssize_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__attr_8c.html#ae1f7e3a17c5a0bcc5a93096aeb902d2">bussuspend_show</a> (struct device *_dev, struct device_attribute *attr, char *buf)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Show the Bus Suspend status. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f218d7c4c611b97dfaa1e03ac2daa353"></a><!-- doxytag: member="dwc_otg_attr.c::bussuspend_store" ref="f218d7c4c611b97dfaa1e03ac2daa353" args="(struct device *_dev, struct device_attribute *attr, const char *buf, size_t count)" -->
+static ssize_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__attr_8c.html#f218d7c4c611b97dfaa1e03ac2daa353">bussuspend_store</a> (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Set the Bus Suspend status. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3321551071eb0987630d501c377ff095"></a><!-- doxytag: member="dwc_otg_attr.c::remote_wakeup_show" ref="3321551071eb0987630d501c377ff095" args="(struct device *_dev, struct device_attribute *attr, char *buf)" -->
+static ssize_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__attr_8c.html#3321551071eb0987630d501c377ff095">remote_wakeup_show</a> (struct device *_dev, struct device_attribute *attr, char *buf)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Show the status of Remote Wakeup. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static ssize_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__attr_8c.html#e64972f2160646d9d707a97366eba56c">remote_wakeup_store</a> (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Initiate a remote wakeup of the host.  <a href="#e64972f2160646d9d707a97366eba56c"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="36728dcc762e9cbdbc9543c8b780df68"></a><!-- doxytag: member="dwc_otg_attr.c::regdump_show" ref="36728dcc762e9cbdbc9543c8b780df68" args="(struct device *_dev, struct device_attribute *attr, char *buf)" -->
+static ssize_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__attr_8c.html#36728dcc762e9cbdbc9543c8b780df68">regdump_show</a> (struct device *_dev, struct device_attribute *attr, char *buf)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Dump global registers and either host or device registers (depending on the current mode of the core). <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e98e139afbb50f9d989ddbef2f0dbd6e"></a><!-- doxytag: member="dwc_otg_attr.c::spramdump_show" ref="e98e139afbb50f9d989ddbef2f0dbd6e" args="(struct device *_dev, struct device_attribute *attr, char *buf)" -->
+S_IRUGO static ssize_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__attr_8c.html#e98e139afbb50f9d989ddbef2f0dbd6e">spramdump_show</a> (struct device *_dev, struct device_attribute *attr, char *buf)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Dump global registers and either host or device registers (depending on the current mode of the core). <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e16d4439b6b733715ecc1d06ed999aa4"></a><!-- doxytag: member="dwc_otg_attr.c::hcddump_show" ref="e16d4439b6b733715ecc1d06ed999aa4" args="(struct device *_dev, struct device_attribute *attr, char *buf)" -->
+S_IRUGO static ssize_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__attr_8c.html#e16d4439b6b733715ecc1d06ed999aa4">hcddump_show</a> (struct device *_dev, struct device_attribute *attr, char *buf)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Dump the current hcd state. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">S_IRUGO static ssize_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__attr_8c.html#d1d9d9abd2011c79fe7453c20e03e31a">hcd_frrem_show</a> (struct device *_dev, struct device_attribute *attr, char *buf)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Dump the average frame remaining at SOF.  <a href="#d1d9d9abd2011c79fe7453c20e03e31a"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="81946b90c6e16e9596d9b9ccd1d54476"></a><!-- doxytag: member="dwc_otg_attr.c::rd_reg_test_show" ref="81946b90c6e16e9596d9b9ccd1d54476" args="(struct device *_dev, struct device_attribute *attr, char *buf)" -->
+static ssize_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__attr_8c.html#81946b90c6e16e9596d9b9ccd1d54476">rd_reg_test_show</a> (struct device *_dev, struct device_attribute *attr, char *buf)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="9dd7132e3f334eed0e27e11ab5f7b0c4"></a><!-- doxytag: member="dwc_otg_attr.c::wr_reg_test_show" ref="9dd7132e3f334eed0e27e11ab5f7b0c4" args="(struct device *_dev, struct device_attribute *attr, char *buf)" -->
+S_IRUGO static ssize_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__attr_8c.html#9dd7132e3f334eed0e27e11ab5f7b0c4">wr_reg_test_show</a> (struct device *_dev, struct device_attribute *attr, char *buf)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Displays the time required to write the GNPTXFSIZ register many times (the output shows the number of times the register is written). <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="aeabf3d18b9b521d65b364cec3dcde45"></a><!-- doxytag: member="dwc_otg_attr.c::regoffset" ref="aeabf3d18b9b521d65b364cec3dcde45" args="" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__attr_8c.html#aeabf3d18b9b521d65b364cec3dcde45">regoffset</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ac2308832629daf78cb9dd123551cd8a"></a><!-- doxytag: member="dwc_otg_attr.c::S_IWUSR" ref="ac2308832629daf78cb9dd123551cd8a" args="" -->
+S_IRUGO&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__attr_8c.html#ac2308832629daf78cb9dd123551cd8a">S_IWUSR</a></td></tr>
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+S_IRUGO&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__attr_8c.html#fede01598333be19cc7d8787aa05cfdf">regoffset_store</a></td></tr>
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+S_IRUGO&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__attr_8c.html#ac2308832629daf78cb9dd123551cd8a">S_IWUSR</a></td></tr>
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+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="d88d7abccfb5b9f0e2c9461a4c950114"></a><!-- doxytag: member="dwc_otg_attr.c::regvalue_show" ref="d88d7abccfb5b9f0e2c9461a4c950114" args="" -->
+S_IRUGO&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__attr_8c.html#d88d7abccfb5b9f0e2c9461a4c950114">regvalue_show</a></td></tr>
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+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="decb71de8ca4344042f5230b8fdadc86"></a><!-- doxytag: member="dwc_otg_attr.c::regvalue_store" ref="decb71de8ca4344042f5230b8fdadc86" args="" -->
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+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="2d1cf91c8e20bcdd4f552c410b0aa6ba"></a><!-- doxytag: member="dwc_otg_attr.c::hnp" ref="2d1cf91c8e20bcdd4f552c410b0aa6ba" args="" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__attr_8c.html#2d1cf91c8e20bcdd4f552c410b0aa6ba">hnp</a></td></tr>
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+&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__attr_8c.html#5ed0f5e2094b1db679075adf2f81e10a">hnp_show</a></td></tr>
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+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="8c009b0959c53d9bc868afa4572db7a1"></a><!-- doxytag: member="dwc_otg_attr.c::hnp_store" ref="8c009b0959c53d9bc868afa4572db7a1" args="" -->
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+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="0c2c4ba16770c40a82dbb1c33cbc2e4a"></a><!-- doxytag: member="dwc_otg_attr.c::srp" ref="0c2c4ba16770c40a82dbb1c33cbc2e4a" args="" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__attr_8c.html#0c2c4ba16770c40a82dbb1c33cbc2e4a">srp</a></td></tr>
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+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="1ca3f5bc52a2523ca16a4fe5eafee0df"></a><!-- doxytag: member="dwc_otg_attr.c::srp_show" ref="1ca3f5bc52a2523ca16a4fe5eafee0df" args="" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__attr_8c.html#1ca3f5bc52a2523ca16a4fe5eafee0df">srp_show</a></td></tr>
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+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="204d2d3c45a75706a28c57b396eb55c3"></a><!-- doxytag: member="dwc_otg_attr.c::srp_store" ref="204d2d3c45a75706a28c57b396eb55c3" args="" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__attr_8c.html#204d2d3c45a75706a28c57b396eb55c3">srp_store</a></td></tr>
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+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ac2308832629daf78cb9dd123551cd8a"></a><!-- doxytag: member="dwc_otg_attr.c::S_IWUSR" ref="ac2308832629daf78cb9dd123551cd8a" args="" -->
+S_IRUGO&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__attr_8c.html#ac2308832629daf78cb9dd123551cd8a">S_IWUSR</a></td></tr>
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+&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__attr_8c.html#829fa87e3e65ff4038b6bc0eb2a93fb7">rd_reg_test</a></td></tr>
+
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+S_IRUGO&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__attr_8c.html#ac2308832629daf78cb9dd123551cd8a">S_IWUSR</a></td></tr>
+
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+&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__attr_8c.html#b46682cc35d8ddece607cdf93c124575">wr_reg_test</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ac2308832629daf78cb9dd123551cd8a"></a><!-- doxytag: member="dwc_otg_attr.c::S_IWUSR" ref="ac2308832629daf78cb9dd123551cd8a" args="" -->
+S_IRUGO&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__attr_8c.html#ac2308832629daf78cb9dd123551cd8a">S_IWUSR</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="bc692a23b59ffdb09d9ef3fd468fbff7"></a><!-- doxytag: member="dwc_otg_attr.c::wr_reg_test_show" ref="bc692a23b59ffdb09d9ef3fd468fbff7" args="" -->
+S_IRUGO&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__attr_8c.html#bc692a23b59ffdb09d9ef3fd468fbff7">wr_reg_test_show</a></td></tr>
+
+<tr><td colspan="2"><br><h2>Defines</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__attr_8c.html#91eb9b8ec6d56698f0b6f4934573a41e">DWC_OTG_DEVICE_ATTR_BITFIELD_RW</a>(_otg_attr_name_, _string_)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__attr_8c.html#9bf160f54b6a1da72d213aa1aebfb444">DWC_OTG_DEVICE_ATTR_BITFIELD_RO</a>(_otg_attr_name_, _string_)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__attr_8c.html#b7106ee2e9d5f335e6c49013ca789467">DWC_OTG_DEVICE_ATTR_REG32_RW</a>(_otg_attr_name_, _addr_, _string_)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__attr_8c.html#471f9d3f4b4aa45b59be200e1b3beb87">DWC_OTG_DEVICE_ATTR_REG32_RO</a>(_otg_attr_name_, _addr_, _string_)</td></tr>
+
+<tr><td colspan="2"><br><h2>Functions</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="792fccf68b5f00d193f800822a5d888b"></a><!-- doxytag: member="dwc_otg_attr.c::dwc_otg_attr_create" ref="792fccf68b5f00d193f800822a5d888b" args="()" -->
+S_IRUGO void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__attr_8c.html#792fccf68b5f00d193f800822a5d888b">dwc_otg_attr_create</a> ()</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Create the device files. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="4b0aa5ebf3661ec8ab5566b20c233674"></a><!-- doxytag: member="dwc_otg_attr.c::dwc_otg_attr_remove" ref="4b0aa5ebf3661ec8ab5566b20c233674" args="()" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__attr_8c.html#4b0aa5ebf3661ec8ab5566b20c233674">dwc_otg_attr_remove</a> ()</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Remove the device files. <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+The diagnostic interface will provide access to the controller for bringing up the hardware and testing. 
+<p>
+The Linux driver attributes feature will be used to provide the Linux Diagnostic Interface. These attributes are accessed through sysfs. 
+<p>
+Definition in file <a class="el" href="dwc__otg__attr_8c-source.html">dwc_otg_attr.c</a>.<hr><h2>Define Documentation</h2>
+<a class="anchor" name="91eb9b8ec6d56698f0b6f4934573a41e"></a><!-- doxytag: member="dwc_otg_attr.c::DWC_OTG_DEVICE_ATTR_BITFIELD_RW" ref="91eb9b8ec6d56698f0b6f4934573a41e" args="(_otg_attr_name_, _string_)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_OTG_DEVICE_ATTR_BITFIELD_RW          </td>
+          <td>(</td>
+          <td class="paramtype">_otg_attr_name_,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">_string_&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><a class="code" href="dwc__otg__attr_8c.html#a6ede17e817a37b1207d7a82147a8e57">DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW</a>(_otg_attr_name_,_string_) \
+DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \
+DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
+</pre></div>
+<p>
+Definition at line <a class="el" href="dwc__otg__attr_8c-source.html#l00405">405</a> of file <a class="el" href="dwc__otg__attr_8c-source.html">dwc_otg_attr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="9bf160f54b6a1da72d213aa1aebfb444"></a><!-- doxytag: member="dwc_otg_attr.c::DWC_OTG_DEVICE_ATTR_BITFIELD_RO" ref="9bf160f54b6a1da72d213aa1aebfb444" args="(_otg_attr_name_, _string_)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_OTG_DEVICE_ATTR_BITFIELD_RO          </td>
+          <td>(</td>
+          <td class="paramtype">_otg_attr_name_,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">_string_&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><a class="code" href="dwc__otg__attr_8c.html#a6ede17e817a37b1207d7a82147a8e57">DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW</a>(_otg_attr_name_,_string_) \
+DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
+</pre></div>
+<p>
+Definition at line <a class="el" href="dwc__otg__attr_8c-source.html#l00410">410</a> of file <a class="el" href="dwc__otg__attr_8c-source.html">dwc_otg_attr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="b7106ee2e9d5f335e6c49013ca789467"></a><!-- doxytag: member="dwc_otg_attr.c::DWC_OTG_DEVICE_ATTR_REG32_RW" ref="b7106ee2e9d5f335e6c49013ca789467" args="(_otg_attr_name_, _addr_, _string_)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_OTG_DEVICE_ATTR_REG32_RW          </td>
+          <td>(</td>
+          <td class="paramtype">_otg_attr_name_,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">_addr_,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">_string_&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment">DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
+DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \
+DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
+</pre></div>
+<p>
+Definition at line <a class="el" href="dwc__otg__attr_8c-source.html#l00414">414</a> of file <a class="el" href="dwc__otg__attr_8c-source.html">dwc_otg_attr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="471f9d3f4b4aa45b59be200e1b3beb87"></a><!-- doxytag: member="dwc_otg_attr.c::DWC_OTG_DEVICE_ATTR_REG32_RO" ref="471f9d3f4b4aa45b59be200e1b3beb87" args="(_otg_attr_name_, _addr_, _string_)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_OTG_DEVICE_ATTR_REG32_RO          </td>
+          <td>(</td>
+          <td class="paramtype">_otg_attr_name_,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">_addr_,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">_string_&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment">DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
+DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
+</pre></div>
+<p>
+Definition at line <a class="el" href="dwc__otg__attr_8c-source.html#l00419">419</a> of file <a class="el" href="dwc__otg__attr_8c-source.html">dwc_otg_attr.c</a>.
+</div>
+</div><p>
+<hr><h2>Function Documentation</h2>
+<a class="anchor" name="e64972f2160646d9d707a97366eba56c"></a><!-- doxytag: member="dwc_otg_attr.c::remote_wakeup_store" ref="e64972f2160646d9d707a97366eba56c" args="(struct device *_dev, struct device_attribute *attr, const char *buf, size_t count)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static ssize_t remote_wakeup_store           </td>
+          <td>(</td>
+          <td class="paramtype">struct device *&nbsp;</td>
+          <td class="paramname"> <em>_dev</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">struct device_attribute *&nbsp;</td>
+          <td class="paramname"> <em>attr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">const char *&nbsp;</td>
+          <td class="paramname"> <em>buf</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">size_t&nbsp;</td>
+          <td class="paramname"> <em>count</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Initiate a remote wakeup of the host. 
+<p>
+The Device control register Remote Wakeup Signal bit is written if the PCD Remote wakeup enable flag is set. 
+<p>
+Definition at line <a class="el" href="dwc__otg__attr_8c-source.html#l00773">773</a> of file <a class="el" href="dwc__otg__attr_8c-source.html">dwc_otg_attr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="d1d9d9abd2011c79fe7453c20e03e31a"></a><!-- doxytag: member="dwc_otg_attr.c::hcd_frrem_show" ref="d1d9d9abd2011c79fe7453c20e03e31a" args="(struct device *_dev, struct device_attribute *attr, char *buf)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">S_IRUGO static ssize_t hcd_frrem_show           </td>
+          <td>(</td>
+          <td class="paramtype">struct device *&nbsp;</td>
+          <td class="paramname"> <em>_dev</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">struct device_attribute *&nbsp;</td>
+          <td class="paramname"> <em>attr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">char *&nbsp;</td>
+          <td class="paramname"> <em>buf</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Dump the average frame remaining at SOF. 
+<p>
+This can be used to determine average interrupt latency. Frame remaining is also shown for start transfer and two additional sample points. 
+<p>
+Definition at line <a class="el" href="dwc__otg__attr_8c-source.html#l00872">872</a> of file <a class="el" href="dwc__otg__attr_8c-source.html">dwc_otg_attr.c</a>.
+</div>
+</div><p>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/dwc__otg__attr_8h-source.html b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__attr_8h-source.html
new file mode 100644
index 000000000000..59c3fd3b4f36
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__attr_8h-source.html
@@ -0,0 +1,105 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_attr.h Source File</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<h1>dwc_otg_attr.h</h1><a href="dwc__otg__attr_8h.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">/* ==========================================================================</span>
+<a name="l00002"></a>00002 <span class="comment"> * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.h $</span>
+<a name="l00003"></a>00003 <span class="comment"> * $Revision: #11 $</span>
+<a name="l00004"></a>00004 <span class="comment"> * $Date: 2009/04/03 $</span>
+<a name="l00005"></a>00005 <span class="comment"> * $Change: 1225160 $</span>
+<a name="l00006"></a>00006 <span class="comment"> *</span>
+<a name="l00007"></a>00007 <span class="comment"> * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,</span>
+<a name="l00008"></a>00008 <span class="comment"> * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless</span>
+<a name="l00009"></a>00009 <span class="comment"> * otherwise expressly agreed to in writing between Synopsys and you.</span>
+<a name="l00010"></a>00010 <span class="comment"> * </span>
+<a name="l00011"></a>00011 <span class="comment"> * The Software IS NOT an item of Licensed Software or Licensed Product under</span>
+<a name="l00012"></a>00012 <span class="comment"> * any End User Software License Agreement or Agreement for Licensed Product</span>
+<a name="l00013"></a>00013 <span class="comment"> * with Synopsys or any supplement thereto. You are permitted to use and</span>
+<a name="l00014"></a>00014 <span class="comment"> * redistribute this Software in source and binary forms, with or without</span>
+<a name="l00015"></a>00015 <span class="comment"> * modification, provided that redistributions of source code must retain this</span>
+<a name="l00016"></a>00016 <span class="comment"> * notice. You may not view, use, disclose, copy or distribute this file or</span>
+<a name="l00017"></a>00017 <span class="comment"> * any information contained herein except pursuant to this license grant from</span>
+<a name="l00018"></a>00018 <span class="comment"> * Synopsys. If you do not agree with this notice, including the disclaimer</span>
+<a name="l00019"></a>00019 <span class="comment"> * below, then you are not authorized to use the Software.</span>
+<a name="l00020"></a>00020 <span class="comment"> * </span>
+<a name="l00021"></a>00021 <span class="comment"> * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS</span>
+<a name="l00022"></a>00022 <span class="comment"> * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE</span>
+<a name="l00023"></a>00023 <span class="comment"> * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE</span>
+<a name="l00024"></a>00024 <span class="comment"> * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,</span>
+<a name="l00025"></a>00025 <span class="comment"> * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES</span>
+<a name="l00026"></a>00026 <span class="comment"> * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR</span>
+<a name="l00027"></a>00027 <span class="comment"> * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER</span>
+<a name="l00028"></a>00028 <span class="comment"> * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT</span>
+<a name="l00029"></a>00029 <span class="comment"> * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY</span>
+<a name="l00030"></a>00030 <span class="comment"> * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH</span>
+<a name="l00031"></a>00031 <span class="comment"> * DAMAGE.</span>
+<a name="l00032"></a>00032 <span class="comment"> * ========================================================================== */</span>
+<a name="l00033"></a>00033 
+<a name="l00034"></a>00034 <span class="preprocessor">#if !defined(__DWC_OTG_ATTR_H__)</span>
+<a name="l00035"></a><a class="code" href="dwc__otg__attr_8h.html#338d875aceea377e37f82aa8fe743420">00035</a> <span class="preprocessor"></span><span class="preprocessor">#define __DWC_OTG_ATTR_H__</span>
+<a name="l00036"></a>00036 <span class="preprocessor"></span>
+<a name="l00040"></a>00040 <span class="keyword">extern</span> <span class="keyword">struct </span>device_attribute dev_attr_regoffset;
+<a name="l00041"></a>00041 <span class="keyword">extern</span> <span class="keyword">struct </span>device_attribute dev_attr_regvalue;
+<a name="l00042"></a>00042 
+<a name="l00043"></a>00043 <span class="keyword">extern</span> <span class="keyword">struct </span>device_attribute dev_attr_mode;
+<a name="l00044"></a>00044 <span class="keyword">extern</span> <span class="keyword">struct </span>device_attribute dev_attr_hnpcapable;
+<a name="l00045"></a>00045 <span class="keyword">extern</span> <span class="keyword">struct </span>device_attribute dev_attr_srpcapable;
+<a name="l00046"></a>00046 <span class="keyword">extern</span> <span class="keyword">struct </span>device_attribute dev_attr_hnp;
+<a name="l00047"></a>00047 <span class="keyword">extern</span> <span class="keyword">struct </span>device_attribute dev_attr_srp;
+<a name="l00048"></a>00048 <span class="keyword">extern</span> <span class="keyword">struct </span>device_attribute dev_attr_buspower;
+<a name="l00049"></a>00049 <span class="keyword">extern</span> <span class="keyword">struct </span>device_attribute dev_attr_bussuspend;
+<a name="l00050"></a>00050 <span class="keyword">extern</span> <span class="keyword">struct </span>device_attribute dev_attr_busconnected;
+<a name="l00051"></a>00051 <span class="keyword">extern</span> <span class="keyword">struct </span>device_attribute dev_attr_gotgctl;
+<a name="l00052"></a>00052 <span class="keyword">extern</span> <span class="keyword">struct </span>device_attribute dev_attr_gusbcfg;
+<a name="l00053"></a>00053 <span class="keyword">extern</span> <span class="keyword">struct </span>device_attribute dev_attr_grxfsiz;
+<a name="l00054"></a>00054 <span class="keyword">extern</span> <span class="keyword">struct </span>device_attribute dev_attr_gnptxfsiz;
+<a name="l00055"></a>00055 <span class="keyword">extern</span> <span class="keyword">struct </span>device_attribute dev_attr_gpvndctl;
+<a name="l00056"></a>00056 <span class="keyword">extern</span> <span class="keyword">struct </span>device_attribute dev_attr_ggpio;
+<a name="l00057"></a>00057 <span class="keyword">extern</span> <span class="keyword">struct </span>device_attribute dev_attr_guid;
+<a name="l00058"></a>00058 <span class="keyword">extern</span> <span class="keyword">struct </span>device_attribute dev_attr_gsnpsid;
+<a name="l00059"></a>00059 <span class="keyword">extern</span> <span class="keyword">struct </span>device_attribute dev_attr_devspeed;
+<a name="l00060"></a>00060 <span class="keyword">extern</span> <span class="keyword">struct </span>device_attribute dev_attr_enumspeed;
+<a name="l00061"></a>00061 <span class="keyword">extern</span> <span class="keyword">struct </span>device_attribute dev_attr_hptxfsiz;
+<a name="l00062"></a>00062 <span class="keyword">extern</span> <span class="keyword">struct </span>device_attribute dev_attr_hprt0;
+<a name="l00063"></a>00063 <span class="preprocessor">#ifdef CONFIG_USB_DWC_OTG_LPM</span>
+<a name="l00064"></a>00064 <span class="preprocessor"></span><span class="keyword">extern</span> <span class="keyword">struct </span>device_attribute dev_attr_lpm_response;
+<a name="l00065"></a>00065 <span class="keyword">extern</span> <span class="keyword">struct </span>device_attribute dev_attr_sleep_local_dev;
+<a name="l00066"></a>00066 <span class="keyword">extern</span> <span class="keyword">struct </span>device_attribute devi_attr_sleep_status;
+<a name="l00067"></a>00067 <span class="preprocessor">#endif</span>
+<a name="l00068"></a>00068 <span class="preprocessor"></span>
+<a name="l00069"></a>00069 <span class="keywordtype">void</span> <a class="code" href="dwc__otg__attr_8c.html#792fccf68b5f00d193f800822a5d888b">dwc_otg_attr_create</a> (
+<a name="l00070"></a>00070 #ifdef LM_INTERFACE
+<a name="l00071"></a>00071         <span class="keyword">struct</span> lm_device *dev
+<a name="l00072"></a>00072 #elif  PCI_INTERFACE
+<a name="l00073"></a>00073         <span class="keyword">struct</span> pci_dev *dev
+<a name="l00074"></a>00074 #endif
+<a name="l00075"></a>00075         );
+<a name="l00076"></a>00076 
+<a name="l00077"></a>00077 <span class="keywordtype">void</span> <a class="code" href="dwc__otg__attr_8c.html#4b0aa5ebf3661ec8ab5566b20c233674">dwc_otg_attr_remove</a> (
+<a name="l00078"></a>00078 #ifdef LM_INTERFACE
+<a name="l00079"></a>00079         <span class="keyword">struct</span> lm_device *dev
+<a name="l00080"></a>00080 #elif  PCI_INTERFACE
+<a name="l00081"></a>00081         <span class="keyword">struct</span> pci_dev *dev
+<a name="l00082"></a>00082 #endif
+<a name="l00083"></a>00083         );
+<a name="l00084"></a>00084 <span class="preprocessor">#endif</span>
+</pre></div><hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/dwc__otg__attr_8h.html b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__attr_8h.html
new file mode 100644
index 000000000000..2ef83afdf61e
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__attr_8h.html
@@ -0,0 +1,116 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_attr.h File Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<h1>dwc_otg_attr.h File Reference</h1>This file contains the interface to the Linux device attributes. <a href="#_details">More...</a>
+<p>
+
+<p>
+<a href="dwc__otg__attr_8h-source.html">Go to the source code of this file.</a><table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Defines</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="338d875aceea377e37f82aa8fe743420"></a><!-- doxytag: member="dwc_otg_attr.h::__DWC_OTG_ATTR_H__" ref="338d875aceea377e37f82aa8fe743420" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__attr_8h.html#338d875aceea377e37f82aa8fe743420">__DWC_OTG_ATTR_H__</a></td></tr>
+
+<tr><td colspan="2"><br><h2>Functions</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="a0ccc83a12d3ee16db6436d0e2fab197"></a><!-- doxytag: member="dwc_otg_attr.h::dwc_otg_attr_create" ref="a0ccc83a12d3ee16db6436d0e2fab197" args="()" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__attr_8h.html#a0ccc83a12d3ee16db6436d0e2fab197">dwc_otg_attr_create</a> ()</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Create the device files. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="4b0aa5ebf3661ec8ab5566b20c233674"></a><!-- doxytag: member="dwc_otg_attr.h::dwc_otg_attr_remove" ref="4b0aa5ebf3661ec8ab5566b20c233674" args="()" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__attr_8h.html#4b0aa5ebf3661ec8ab5566b20c233674">dwc_otg_attr_remove</a> ()</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Remove the device files. <br></td></tr>
+<tr><td colspan="2"><br><h2>Variables</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ae8ac5e0ad33894c80ebcf9a9721ae54"></a><!-- doxytag: member="dwc_otg_attr.h::dev_attr_regoffset" ref="ae8ac5e0ad33894c80ebcf9a9721ae54" args="" -->
+device_attribute&nbsp;</td><td class="memItemRight" valign="bottom"><b>dev_attr_regoffset</b></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f5f17d66e954634c82f6e98bc04640a3"></a><!-- doxytag: member="dwc_otg_attr.h::dev_attr_regvalue" ref="f5f17d66e954634c82f6e98bc04640a3" args="" -->
+device_attribute&nbsp;</td><td class="memItemRight" valign="bottom"><b>dev_attr_regvalue</b></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="0c78cf8d09103d2bad1239bed1a1b835"></a><!-- doxytag: member="dwc_otg_attr.h::dev_attr_mode" ref="0c78cf8d09103d2bad1239bed1a1b835" args="" -->
+device_attribute&nbsp;</td><td class="memItemRight" valign="bottom"><b>dev_attr_mode</b></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b7b0ae13436d26cca9c33bf9b7fd5cb9"></a><!-- doxytag: member="dwc_otg_attr.h::dev_attr_hnpcapable" ref="b7b0ae13436d26cca9c33bf9b7fd5cb9" args="" -->
+device_attribute&nbsp;</td><td class="memItemRight" valign="bottom"><b>dev_attr_hnpcapable</b></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="4cfeada4674bd20731630484b949823d"></a><!-- doxytag: member="dwc_otg_attr.h::dev_attr_srpcapable" ref="4cfeada4674bd20731630484b949823d" args="" -->
+device_attribute&nbsp;</td><td class="memItemRight" valign="bottom"><b>dev_attr_srpcapable</b></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3748f6e84a90628b8b6354387c33cf41"></a><!-- doxytag: member="dwc_otg_attr.h::dev_attr_hnp" ref="3748f6e84a90628b8b6354387c33cf41" args="" -->
+device_attribute&nbsp;</td><td class="memItemRight" valign="bottom"><b>dev_attr_hnp</b></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="8be7c24c9264e382d793e14f45165bc9"></a><!-- doxytag: member="dwc_otg_attr.h::dev_attr_srp" ref="8be7c24c9264e382d793e14f45165bc9" args="" -->
+device_attribute&nbsp;</td><td class="memItemRight" valign="bottom"><b>dev_attr_srp</b></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="59103f1dac92f1e9c9696fa53218fc2c"></a><!-- doxytag: member="dwc_otg_attr.h::dev_attr_buspower" ref="59103f1dac92f1e9c9696fa53218fc2c" args="" -->
+device_attribute&nbsp;</td><td class="memItemRight" valign="bottom"><b>dev_attr_buspower</b></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="5cc7fc997d1592986c4f32480b3f7599"></a><!-- doxytag: member="dwc_otg_attr.h::dev_attr_bussuspend" ref="5cc7fc997d1592986c4f32480b3f7599" args="" -->
+device_attribute&nbsp;</td><td class="memItemRight" valign="bottom"><b>dev_attr_bussuspend</b></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="1dead7e4cd816d06ea97d0c27e049358"></a><!-- doxytag: member="dwc_otg_attr.h::dev_attr_busconnected" ref="1dead7e4cd816d06ea97d0c27e049358" args="" -->
+device_attribute&nbsp;</td><td class="memItemRight" valign="bottom"><b>dev_attr_busconnected</b></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="5c42ba4215df7f83e967921526281496"></a><!-- doxytag: member="dwc_otg_attr.h::dev_attr_gotgctl" ref="5c42ba4215df7f83e967921526281496" args="" -->
+device_attribute&nbsp;</td><td class="memItemRight" valign="bottom"><b>dev_attr_gotgctl</b></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="833407ceb72c995575425f063e1c084f"></a><!-- doxytag: member="dwc_otg_attr.h::dev_attr_gusbcfg" ref="833407ceb72c995575425f063e1c084f" args="" -->
+device_attribute&nbsp;</td><td class="memItemRight" valign="bottom"><b>dev_attr_gusbcfg</b></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="2be1601638e91f964e8b93741c425db9"></a><!-- doxytag: member="dwc_otg_attr.h::dev_attr_grxfsiz" ref="2be1601638e91f964e8b93741c425db9" args="" -->
+device_attribute&nbsp;</td><td class="memItemRight" valign="bottom"><b>dev_attr_grxfsiz</b></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e75d1aeb6da53c9e4d59d09836496791"></a><!-- doxytag: member="dwc_otg_attr.h::dev_attr_gnptxfsiz" ref="e75d1aeb6da53c9e4d59d09836496791" args="" -->
+device_attribute&nbsp;</td><td class="memItemRight" valign="bottom"><b>dev_attr_gnptxfsiz</b></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="631e3ef0593c8b6d14c14223c0c8e603"></a><!-- doxytag: member="dwc_otg_attr.h::dev_attr_gpvndctl" ref="631e3ef0593c8b6d14c14223c0c8e603" args="" -->
+device_attribute&nbsp;</td><td class="memItemRight" valign="bottom"><b>dev_attr_gpvndctl</b></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="1648cedd28cb65f4e13da6fdf7e0b284"></a><!-- doxytag: member="dwc_otg_attr.h::dev_attr_ggpio" ref="1648cedd28cb65f4e13da6fdf7e0b284" args="" -->
+device_attribute&nbsp;</td><td class="memItemRight" valign="bottom"><b>dev_attr_ggpio</b></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b43eeb96f24bf312c4f5fd80c5ad7522"></a><!-- doxytag: member="dwc_otg_attr.h::dev_attr_guid" ref="b43eeb96f24bf312c4f5fd80c5ad7522" args="" -->
+device_attribute&nbsp;</td><td class="memItemRight" valign="bottom"><b>dev_attr_guid</b></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c2d6d844929a74e77db68044aae2b2cd"></a><!-- doxytag: member="dwc_otg_attr.h::dev_attr_gsnpsid" ref="c2d6d844929a74e77db68044aae2b2cd" args="" -->
+device_attribute&nbsp;</td><td class="memItemRight" valign="bottom"><b>dev_attr_gsnpsid</b></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="80714d261152fba73eef10293b0fa64a"></a><!-- doxytag: member="dwc_otg_attr.h::dev_attr_devspeed" ref="80714d261152fba73eef10293b0fa64a" args="" -->
+device_attribute&nbsp;</td><td class="memItemRight" valign="bottom"><b>dev_attr_devspeed</b></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f5c2f346250d1da49b8946bb17d06733"></a><!-- doxytag: member="dwc_otg_attr.h::dev_attr_enumspeed" ref="f5c2f346250d1da49b8946bb17d06733" args="" -->
+device_attribute&nbsp;</td><td class="memItemRight" valign="bottom"><b>dev_attr_enumspeed</b></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="99a904a3c03c74cb77bac5aa5d87d025"></a><!-- doxytag: member="dwc_otg_attr.h::dev_attr_hptxfsiz" ref="99a904a3c03c74cb77bac5aa5d87d025" args="" -->
+device_attribute&nbsp;</td><td class="memItemRight" valign="bottom"><b>dev_attr_hptxfsiz</b></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b181fc426dfc1fba731410a65da227eb"></a><!-- doxytag: member="dwc_otg_attr.h::dev_attr_hprt0" ref="b181fc426dfc1fba731410a65da227eb" args="" -->
+device_attribute&nbsp;</td><td class="memItemRight" valign="bottom"><b>dev_attr_hprt0</b></td></tr>
+
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This file contains the interface to the Linux device attributes. 
+<p>
+
+<p>
+Definition in file <a class="el" href="dwc__otg__attr_8h-source.html">dwc_otg_attr.h</a>.<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cfi_8c-source.html b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cfi_8c-source.html
new file mode 100644
index 000000000000..df7d3d38c565
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cfi_8c-source.html
@@ -0,0 +1,1724 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_cfi.c Source File</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<h1>dwc_otg_cfi.c</h1><a href="dwc__otg__cfi_8c.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">/* ==========================================================================</span>
+<a name="l00002"></a>00002 <span class="comment"> * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,</span>
+<a name="l00003"></a>00003 <span class="comment"> * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless</span>
+<a name="l00004"></a>00004 <span class="comment"> * otherwise expressly agreed to in writing between Synopsys and you.</span>
+<a name="l00005"></a>00005 <span class="comment"> * </span>
+<a name="l00006"></a>00006 <span class="comment"> * The Software IS NOT an item of Licensed Software or Licensed Product under</span>
+<a name="l00007"></a>00007 <span class="comment"> * any End User Software License Agreement or Agreement for Licensed Product</span>
+<a name="l00008"></a>00008 <span class="comment"> * with Synopsys or any supplement thereto. You are permitted to use and</span>
+<a name="l00009"></a>00009 <span class="comment"> * redistribute this Software in source and binary forms, with or without</span>
+<a name="l00010"></a>00010 <span class="comment"> * modification, provided that redistributions of source code must retain this</span>
+<a name="l00011"></a>00011 <span class="comment"> * notice. You may not view, use, disclose, copy or distribute this file or</span>
+<a name="l00012"></a>00012 <span class="comment"> * any information contained herein except pursuant to this license grant from</span>
+<a name="l00013"></a>00013 <span class="comment"> * Synopsys. If you do not agree with this notice, including the disclaimer</span>
+<a name="l00014"></a>00014 <span class="comment"> * below, then you are not authorized to use the Software.</span>
+<a name="l00015"></a>00015 <span class="comment"> * </span>
+<a name="l00016"></a>00016 <span class="comment"> * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS</span>
+<a name="l00017"></a>00017 <span class="comment"> * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE</span>
+<a name="l00018"></a>00018 <span class="comment"> * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE</span>
+<a name="l00019"></a>00019 <span class="comment"> * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,</span>
+<a name="l00020"></a>00020 <span class="comment"> * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES</span>
+<a name="l00021"></a>00021 <span class="comment"> * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR</span>
+<a name="l00022"></a>00022 <span class="comment"> * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER</span>
+<a name="l00023"></a>00023 <span class="comment"> * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT</span>
+<a name="l00024"></a>00024 <span class="comment"> * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY</span>
+<a name="l00025"></a>00025 <span class="comment"> * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH</span>
+<a name="l00026"></a>00026 <span class="comment"> * DAMAGE.</span>
+<a name="l00027"></a>00027 <span class="comment"> * ========================================================================== */</span>
+<a name="l00028"></a>00028 
+<a name="l00034"></a>00034 <span class="preprocessor">#ifdef DWC_UTE_CFI</span>
+<a name="l00035"></a>00035 <span class="preprocessor"></span>
+<a name="l00036"></a>00036 <span class="preprocessor">#include "<a class="code" href="dwc__otg__pcd_8h.html">dwc_otg_pcd.h</a>"</span>
+<a name="l00037"></a>00037 <span class="preprocessor">#include "<a class="code" href="dwc__otg__cfi_8h.html">dwc_otg_cfi.h</a>"</span>
+<a name="l00038"></a>00038 
+<a name="l00040"></a>00040 <span class="preprocessor">#define DWC_CONSTANT_CPU_TO_LE16(x) (x)</span>
+<a name="l00041"></a>00041 <span class="preprocessor"></span>
+<a name="l00042"></a>00042 <span class="keyword">extern</span> <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *<a class="code" href="dwc__otg__pcd__intr_8c.html#3c351d7f51d6242296d6ea3bb1a9775c">get_ep_by_addr</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd, u16 wIndex);
+<a name="l00043"></a>00043 
+<a name="l00044"></a>00044 <span class="keyword">static</span> <span class="keywordtype">int</span> cfi_core_features_buf(uint8_t * buf, uint16_t buflen);
+<a name="l00045"></a>00045 <span class="keyword">static</span> <span class="keywordtype">int</span> cfi_get_feature_value(uint8_t * buf, uint16_t buflen,
+<a name="l00046"></a>00046                                  <span class="keyword">struct</span> <a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd</a> *pcd,
+<a name="l00047"></a>00047                                  <span class="keyword">struct</span> <a class="code" href="structcfi__usb__ctrlrequest.html">cfi_usb_ctrlrequest</a> *ctrl_req);
+<a name="l00048"></a>00048 <span class="keyword">static</span> <span class="keywordtype">int</span> cfi_set_feature_value(<span class="keyword">struct</span> <a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd</a> *pcd);
+<a name="l00049"></a>00049 <span class="keyword">static</span> <span class="keywordtype">int</span> cfi_ep_get_sg_val(uint8_t * buf, <span class="keyword">struct</span> <a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd</a> *pcd,
+<a name="l00050"></a>00050                              <span class="keyword">struct</span> <a class="code" href="structcfi__usb__ctrlrequest.html">cfi_usb_ctrlrequest</a> *req);
+<a name="l00051"></a>00051 <span class="keyword">static</span> <span class="keywordtype">int</span> cfi_ep_get_concat_val(uint8_t * buf, <span class="keyword">struct</span> <a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd</a> *pcd,
+<a name="l00052"></a>00052                                  <span class="keyword">struct</span> <a class="code" href="structcfi__usb__ctrlrequest.html">cfi_usb_ctrlrequest</a> *req);
+<a name="l00053"></a>00053 <span class="keyword">static</span> <span class="keywordtype">int</span> cfi_ep_get_align_val(uint8_t * buf, <span class="keyword">struct</span> <a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd</a> *pcd,
+<a name="l00054"></a>00054                                 <span class="keyword">struct</span> <a class="code" href="structcfi__usb__ctrlrequest.html">cfi_usb_ctrlrequest</a> *req);
+<a name="l00055"></a>00055 <span class="keyword">static</span> <span class="keywordtype">int</span> cfi_preproc_reset(<span class="keyword">struct</span> <a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd</a> *pcd,
+<a name="l00056"></a>00056                              <span class="keyword">struct</span> <a class="code" href="structcfi__usb__ctrlrequest.html">cfi_usb_ctrlrequest</a> *req);
+<a name="l00057"></a>00057 <span class="keyword">static</span> <span class="keywordtype">void</span> cfi_free_ep_bs_dyn_data(<a class="code" href="structcfi__ep.html">cfi_ep_t</a> * cfiep);
+<a name="l00058"></a>00058 
+<a name="l00059"></a>00059 <span class="keyword">static</span> uint16_t get_dfifo_size(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if);
+<a name="l00060"></a>00060 <span class="keyword">static</span> int32_t get_rxfifo_size(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, uint16_t wValue);
+<a name="l00061"></a>00061 <span class="keyword">static</span> int32_t get_txfifo_size(<span class="keyword">struct</span> <a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd</a> *pcd, uint16_t wValue);
+<a name="l00062"></a>00062 
+<a name="l00063"></a>00063 <span class="keyword">static</span> uint8_t resize_fifos(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if);
+<a name="l00064"></a>00064 
+<a name="l00066"></a>00066 <span class="keyword">static</span> <a class="code" href="structcfi__all__features__header.html">cfi_all_features_header_t</a> all_props_desc_header = {
+<a name="l00067"></a>00067         .wVersion = DWC_CONSTANT_CPU_TO_LE16(0x100),
+<a name="l00068"></a>00068         .wCoreID = DWC_CONSTANT_CPU_TO_LE16(<a class="code" href="dwc__cfi__common_8h.html#4b0c4a003085148bef609d81fa3c1589">CFI_CORE_ID_OTG</a>),
+<a name="l00069"></a>00069         .wNumFeatures = DWC_CONSTANT_CPU_TO_LE16(9),
+<a name="l00070"></a>00070 };
+<a name="l00071"></a>00071 
+<a name="l00073"></a>00073 <span class="keyword">static</span> <a class="code" href="structcfi__feature__desc__header.html">cfi_feature_desc_header_t</a> prop_descs[] = {
+<a name="l00074"></a>00074 
+<a name="l00075"></a>00075         <span class="comment">/* FT_ID_DMA_MODE */</span>
+<a name="l00076"></a>00076         {
+<a name="l00077"></a>00077          .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(<a class="code" href="dwc__otg__cfi_8h.html#0e196868939f6bbf0d157868bfc90208">FT_ID_DMA_MODE</a>),
+<a name="l00078"></a>00078          .bmAttributes = <a class="code" href="dwc__cfi__common_8h.html#a4536fb9c1314c2f90a93cfcd082dbb9">CFI_FEATURE_ATTR_RW</a>,
+<a name="l00079"></a>00079          .wDataLength = DWC_CONSTANT_CPU_TO_LE16(1),
+<a name="l00080"></a>00080          },
+<a name="l00081"></a>00081 
+<a name="l00082"></a>00082         <span class="comment">/* FT_ID_DMA_BUFFER_SETUP */</span>
+<a name="l00083"></a>00083         {
+<a name="l00084"></a>00084          .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(<a class="code" href="dwc__otg__cfi_8h.html#98840b45640251bfafa3481260aef889">FT_ID_DMA_BUFFER_SETUP</a>),
+<a name="l00085"></a>00085          .bmAttributes = <a class="code" href="dwc__cfi__common_8h.html#a4536fb9c1314c2f90a93cfcd082dbb9">CFI_FEATURE_ATTR_RW</a>,
+<a name="l00086"></a>00086          .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6),
+<a name="l00087"></a>00087          },
+<a name="l00088"></a>00088 
+<a name="l00089"></a>00089         <span class="comment">/* FT_ID_DMA_BUFF_ALIGN */</span>
+<a name="l00090"></a>00090         {
+<a name="l00091"></a>00091          .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(<a class="code" href="dwc__otg__cfi_8h.html#9335284cd4dae01f4bc0da7cb89d5ef4">FT_ID_DMA_BUFF_ALIGN</a>),
+<a name="l00092"></a>00092          .bmAttributes = <a class="code" href="dwc__cfi__common_8h.html#a4536fb9c1314c2f90a93cfcd082dbb9">CFI_FEATURE_ATTR_RW</a>,
+<a name="l00093"></a>00093          .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
+<a name="l00094"></a>00094          },
+<a name="l00095"></a>00095 
+<a name="l00096"></a>00096         <span class="comment">/* FT_ID_DMA_CONCAT_SETUP */</span>
+<a name="l00097"></a>00097         {
+<a name="l00098"></a>00098          .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(<a class="code" href="dwc__otg__cfi_8h.html#779a11db5843dd058581d93c8232bd7c">FT_ID_DMA_CONCAT_SETUP</a>),
+<a name="l00099"></a>00099          .bmAttributes = <a class="code" href="dwc__cfi__common_8h.html#a4536fb9c1314c2f90a93cfcd082dbb9">CFI_FEATURE_ATTR_RW</a>,
+<a name="l00100"></a>00100          <span class="comment">//.wDataLength  = DWC_CONSTANT_CPU_TO_LE16(6),</span>
+<a name="l00101"></a>00101          },
+<a name="l00102"></a>00102 
+<a name="l00103"></a>00103         <span class="comment">/* FT_ID_DMA_CIRCULAR */</span>
+<a name="l00104"></a>00104         {
+<a name="l00105"></a>00105          .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(<a class="code" href="dwc__otg__cfi_8h.html#8db5bfce321e02d42b742e9deedfa665">FT_ID_DMA_CIRCULAR</a>),
+<a name="l00106"></a>00106          .bmAttributes = <a class="code" href="dwc__cfi__common_8h.html#a4536fb9c1314c2f90a93cfcd082dbb9">CFI_FEATURE_ATTR_RW</a>,
+<a name="l00107"></a>00107          .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6),
+<a name="l00108"></a>00108          },
+<a name="l00109"></a>00109 
+<a name="l00110"></a>00110         <span class="comment">/* FT_ID_THRESHOLD_SETUP */</span>
+<a name="l00111"></a>00111         {
+<a name="l00112"></a>00112          .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(<a class="code" href="dwc__otg__cfi_8h.html#bcc99a9e5a0b15b4212d88bd9c610647">FT_ID_THRESHOLD_SETUP</a>),
+<a name="l00113"></a>00113          .bmAttributes = <a class="code" href="dwc__cfi__common_8h.html#a4536fb9c1314c2f90a93cfcd082dbb9">CFI_FEATURE_ATTR_RW</a>,
+<a name="l00114"></a>00114          .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6),
+<a name="l00115"></a>00115          },
+<a name="l00116"></a>00116 
+<a name="l00117"></a>00117         <span class="comment">/* FT_ID_DFIFO_DEPTH */</span>
+<a name="l00118"></a>00118         {
+<a name="l00119"></a>00119          .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(<a class="code" href="dwc__otg__cfi_8h.html#54b879727edcb06acdd11968ec60d249">FT_ID_DFIFO_DEPTH</a>),
+<a name="l00120"></a>00120          .bmAttributes = <a class="code" href="dwc__cfi__common_8h.html#45ffc2183d956983ca297033f9e527af">CFI_FEATURE_ATTR_RO</a>,
+<a name="l00121"></a>00121          .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
+<a name="l00122"></a>00122          },
+<a name="l00123"></a>00123 
+<a name="l00124"></a>00124         <span class="comment">/* FT_ID_TX_FIFO_DEPTH */</span>
+<a name="l00125"></a>00125         {
+<a name="l00126"></a>00126          .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(<a class="code" href="dwc__otg__cfi_8h.html#a3a67b679a59c5279370bbf69f114cb6">FT_ID_TX_FIFO_DEPTH</a>),
+<a name="l00127"></a>00127          .bmAttributes = <a class="code" href="dwc__cfi__common_8h.html#a4536fb9c1314c2f90a93cfcd082dbb9">CFI_FEATURE_ATTR_RW</a>,
+<a name="l00128"></a>00128          .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
+<a name="l00129"></a>00129          },
+<a name="l00130"></a>00130 
+<a name="l00131"></a>00131         <span class="comment">/* FT_ID_RX_FIFO_DEPTH */</span>
+<a name="l00132"></a>00132         {
+<a name="l00133"></a>00133          .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(<a class="code" href="dwc__otg__cfi_8h.html#42b7c98c105de1f9399786a3419e7e20">FT_ID_RX_FIFO_DEPTH</a>),
+<a name="l00134"></a>00134          .bmAttributes = <a class="code" href="dwc__cfi__common_8h.html#a4536fb9c1314c2f90a93cfcd082dbb9">CFI_FEATURE_ATTR_RW</a>,
+<a name="l00135"></a>00135          .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
+<a name="l00136"></a>00136          }
+<a name="l00137"></a>00137 };
+<a name="l00138"></a>00138 
+<a name="l00140"></a>00140 <a class="code" href="structcfi__string.html">cfi_string_t</a> prop_name_table[] = {
+<a name="l00141"></a>00141         {<a class="code" href="dwc__otg__cfi_8h.html#0e196868939f6bbf0d157868bfc90208">FT_ID_DMA_MODE</a>, <span class="stringliteral">"dma_mode"</span>},
+<a name="l00142"></a>00142         {<a class="code" href="dwc__otg__cfi_8h.html#98840b45640251bfafa3481260aef889">FT_ID_DMA_BUFFER_SETUP</a>, <span class="stringliteral">"buffer_setup"</span>},
+<a name="l00143"></a>00143         {<a class="code" href="dwc__otg__cfi_8h.html#9335284cd4dae01f4bc0da7cb89d5ef4">FT_ID_DMA_BUFF_ALIGN</a>, <span class="stringliteral">"buffer_align"</span>},
+<a name="l00144"></a>00144         {<a class="code" href="dwc__otg__cfi_8h.html#779a11db5843dd058581d93c8232bd7c">FT_ID_DMA_CONCAT_SETUP</a>, <span class="stringliteral">"concat_setup"</span>},
+<a name="l00145"></a>00145         {<a class="code" href="dwc__otg__cfi_8h.html#8db5bfce321e02d42b742e9deedfa665">FT_ID_DMA_CIRCULAR</a>, <span class="stringliteral">"buffer_circular"</span>},
+<a name="l00146"></a>00146         {<a class="code" href="dwc__otg__cfi_8h.html#bcc99a9e5a0b15b4212d88bd9c610647">FT_ID_THRESHOLD_SETUP</a>, <span class="stringliteral">"threshold_setup"</span>},
+<a name="l00147"></a>00147         {<a class="code" href="dwc__otg__cfi_8h.html#54b879727edcb06acdd11968ec60d249">FT_ID_DFIFO_DEPTH</a>, <span class="stringliteral">"dfifo_depth"</span>},
+<a name="l00148"></a>00148         {<a class="code" href="dwc__otg__cfi_8h.html#a3a67b679a59c5279370bbf69f114cb6">FT_ID_TX_FIFO_DEPTH</a>, <span class="stringliteral">"txfifo_depth"</span>},
+<a name="l00149"></a>00149         {<a class="code" href="dwc__otg__cfi_8h.html#42b7c98c105de1f9399786a3419e7e20">FT_ID_RX_FIFO_DEPTH</a>, <span class="stringliteral">"rxfifo_depth"</span>},
+<a name="l00150"></a>00150         {}
+<a name="l00151"></a>00151 };
+<a name="l00152"></a>00152 
+<a name="l00153"></a>00153 <span class="comment">/************************************************************************/</span>
+<a name="l00154"></a>00154 
+<a name="l00160"></a>00160 <span class="keyword">const</span> uint8_t *get_prop_name(uint16_t prop_id, <span class="keywordtype">int</span> *len)
+<a name="l00161"></a>00161 {
+<a name="l00162"></a>00162         <a class="code" href="structcfi__string.html">cfi_string_t</a> *pstr;
+<a name="l00163"></a>00163         *len = 0;
+<a name="l00164"></a>00164 
+<a name="l00165"></a>00165         <span class="keywordflow">for</span> (pstr = prop_name_table; pstr &amp;&amp; pstr-&gt;<a class="code" href="structcfi__string.html#c852efd76029880787738fb474dd486e">s</a>; pstr++) {
+<a name="l00166"></a>00166                 <span class="keywordflow">if</span> (pstr-&gt;<a class="code" href="structcfi__string.html#dc88ed81d4ff35c7a1c837708659afea">id</a> == prop_id) {
+<a name="l00167"></a>00167                         *len = DWC_STRLEN(pstr-&gt;<a class="code" href="structcfi__string.html#c852efd76029880787738fb474dd486e">s</a>);
+<a name="l00168"></a>00168                         <span class="keywordflow">return</span> pstr-&gt;<a class="code" href="structcfi__string.html#c852efd76029880787738fb474dd486e">s</a>;
+<a name="l00169"></a>00169                 }
+<a name="l00170"></a>00170         }
+<a name="l00171"></a>00171         <span class="keywordflow">return</span> NULL;
+<a name="l00172"></a>00172 }
+<a name="l00173"></a>00173 
+<a name="l00179"></a>00179 <span class="keywordtype">int</span> cfi_setup(<span class="keyword">struct</span> <a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd</a> *pcd, <span class="keyword">struct</span> <a class="code" href="structcfi__usb__ctrlrequest.html">cfi_usb_ctrlrequest</a> *ctrl)
+<a name="l00180"></a>00180 {
+<a name="l00181"></a>00181         <span class="keywordtype">int</span> retval = 0;
+<a name="l00182"></a>00182         <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *ep = NULL;
+<a name="l00183"></a>00183         <a class="code" href="structcfiobject.html">cfiobject_t</a> *cfi = pcd-&gt;cfi;
+<a name="l00184"></a>00184         <span class="keyword">struct </span><a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if</a> *coreif = <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd);
+<a name="l00185"></a>00185         uint16_t wLen = DWC_LE16_TO_CPU(&amp;ctrl-&gt;<a class="code" href="structcfi__usb__ctrlrequest.html#60d71d1239e46e787f0b4c626de7c769">wLength</a>);
+<a name="l00186"></a>00186         uint16_t wValue = DWC_LE16_TO_CPU(&amp;ctrl-&gt;<a class="code" href="structcfi__usb__ctrlrequest.html#2f236bbf9450df1a3b5204c4570d883f">wValue</a>);
+<a name="l00187"></a>00187         uint16_t wIndex = DWC_LE16_TO_CPU(&amp;ctrl-&gt;<a class="code" href="structcfi__usb__ctrlrequest.html#984c95bd61e8d1120cd935bcbc5d7134">wIndex</a>);
+<a name="l00188"></a>00188         uint32_t regaddr = 0;
+<a name="l00189"></a>00189         uint32_t regval = 0;
+<a name="l00190"></a>00190 
+<a name="l00191"></a>00191         <span class="comment">/* Save this Control Request in the CFI object. </span>
+<a name="l00192"></a>00192 <span class="comment">         * The data field will be assigned in the data stage completion CB function.</span>
+<a name="l00193"></a>00193 <span class="comment">         */</span>
+<a name="l00194"></a>00194         cfi-&gt;<a class="code" href="structcfiobject.html#a86c33aef2a521a27ca515bb7397dd34">ctrl_req</a> = *ctrl;
+<a name="l00195"></a>00195         cfi-&gt;<a class="code" href="structcfiobject.html#a86c33aef2a521a27ca515bb7397dd34">ctrl_req</a>.<a class="code" href="structcfi__usb__ctrlrequest.html#5b3865e9cb2c0fcf373b1c862a63c180">data</a> = NULL;
+<a name="l00196"></a>00196 
+<a name="l00197"></a>00197         cfi-&gt;<a class="code" href="structcfiobject.html#f103d681f78c43dc92dd4a85cdbdc27c">need_gadget_att</a> = 0;
+<a name="l00198"></a>00198         cfi-&gt;<a class="code" href="structcfiobject.html#8d35a323dcd29a1c9d1a8568bd514c3b">need_status_in_complete</a> = 0;
+<a name="l00199"></a>00199 
+<a name="l00200"></a>00200         <span class="keywordflow">switch</span> (ctrl-&gt;<a class="code" href="structcfi__usb__ctrlrequest.html#b3083f525fa9bb97e41364418daee3fa">bRequest</a>) {
+<a name="l00201"></a>00201         <span class="keywordflow">case</span> <a class="code" href="dwc__cfi__common_8h.html#b206fe3fb25aa96547a4bc0e47a864c6">VEN_CORE_GET_FEATURES</a>:
+<a name="l00202"></a>00202                 retval = cfi_core_features_buf(cfi-&gt;<a class="code" href="structcfiobject.html#f6548b2b8fbab90656c22eb5ca857643">buf_in</a>.<a class="code" href="structcfi__dma__buff.html#474851b3123373b8b30fa3637eb81b5b">buf</a>, <a class="code" href="dwc__otg__cfi_8h.html#34582b9ef366f4c0e8ea24aa2388e829">CFI_IN_BUF_LEN</a>);
+<a name="l00203"></a>00203                 <span class="keywordflow">if</span> (retval &gt;= 0) {
+<a name="l00204"></a>00204                         <span class="comment">//dump_msg(cfi-&gt;buf_in.buf, retval);</span>
+<a name="l00205"></a>00205                         ep = &amp;pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a>;
+<a name="l00206"></a>00206 
+<a name="l00207"></a>00207                         retval = <a class="code" href="dwc__otg__cfi_8h.html#7c9949b9e692a8360832aedfa1843657">min</a>((uint16_t) retval, wLen);
+<a name="l00208"></a>00208                         <span class="comment">/* Transfer this buffer to the host through the EP0-IN EP */</span>
+<a name="l00209"></a>00209                         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#b40ce70422b6d105a855a8df4b33d45d">dma_addr</a> = cfi-&gt;<a class="code" href="structcfiobject.html#f6548b2b8fbab90656c22eb5ca857643">buf_in</a>.<a class="code" href="structcfi__dma__buff.html#549d40f7e33056fc5a99d51d00714d97">addr</a>;
+<a name="l00210"></a>00210                         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#d0cda8ded2e5142d9a1c9c17efc5812f">start_xfer_buff</a> = cfi-&gt;<a class="code" href="structcfiobject.html#f6548b2b8fbab90656c22eb5ca857643">buf_in</a>.<a class="code" href="structcfi__dma__buff.html#474851b3123373b8b30fa3637eb81b5b">buf</a>;
+<a name="l00211"></a>00211                         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#97fa9bf5c31ba734d54f70e6fe6ae8eb">xfer_buff</a> = cfi-&gt;<a class="code" href="structcfiobject.html#f6548b2b8fbab90656c22eb5ca857643">buf_in</a>.<a class="code" href="structcfi__dma__buff.html#474851b3123373b8b30fa3637eb81b5b">buf</a>;
+<a name="l00212"></a>00212                         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">xfer_len</a> = retval;
+<a name="l00213"></a>00213                         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#23d4871510b5bcb54fbf0674d8f122bd">xfer_count</a> = 0;
+<a name="l00214"></a>00214                         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#8c6340435beba0b8c025a4677602acab">sent_zlp</a> = 0;
+<a name="l00215"></a>00215                         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#5a218f200cff0491b735f43fed5176bf">total_len</a> = ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">xfer_len</a>;
+<a name="l00216"></a>00216 
+<a name="l00217"></a>00217                         pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#2c8be11c3b9c7cd02684348eb028aeb5">ep0_pending</a> = 1;
+<a name="l00218"></a>00218                         <a class="code" href="dwc__otg__cil_8c.html#ee4989b24826b2a6592535282853e556">dwc_otg_ep0_start_transfer</a>(coreif, &amp;ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>);
+<a name="l00219"></a>00219                 }
+<a name="l00220"></a>00220                 retval = 0;
+<a name="l00221"></a>00221                 <span class="keywordflow">break</span>;
+<a name="l00222"></a>00222 
+<a name="l00223"></a>00223         <span class="keywordflow">case</span> <a class="code" href="dwc__cfi__common_8h.html#22bf207e476d086391240b18aacc0314">VEN_CORE_GET_FEATURE</a>:
+<a name="l00224"></a>00224                 <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>(<span class="stringliteral">"VEN_CORE_GET_FEATURE\n"</span>);
+<a name="l00225"></a>00225                 retval = cfi_get_feature_value(cfi-&gt;<a class="code" href="structcfiobject.html#f6548b2b8fbab90656c22eb5ca857643">buf_in</a>.<a class="code" href="structcfi__dma__buff.html#474851b3123373b8b30fa3637eb81b5b">buf</a>, <a class="code" href="dwc__otg__cfi_8h.html#34582b9ef366f4c0e8ea24aa2388e829">CFI_IN_BUF_LEN</a>,
+<a name="l00226"></a>00226                                                pcd, ctrl);
+<a name="l00227"></a>00227                 <span class="keywordflow">if</span> (retval &gt;= 0) {
+<a name="l00228"></a>00228                         ep = &amp;pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a>;
+<a name="l00229"></a>00229 
+<a name="l00230"></a>00230                         retval = <a class="code" href="dwc__otg__cfi_8h.html#7c9949b9e692a8360832aedfa1843657">min</a>((uint16_t) retval, wLen);
+<a name="l00231"></a>00231                         <span class="comment">/* Transfer this buffer to the host through the EP0-IN EP */</span>
+<a name="l00232"></a>00232                         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#b40ce70422b6d105a855a8df4b33d45d">dma_addr</a> = cfi-&gt;<a class="code" href="structcfiobject.html#f6548b2b8fbab90656c22eb5ca857643">buf_in</a>.<a class="code" href="structcfi__dma__buff.html#549d40f7e33056fc5a99d51d00714d97">addr</a>;
+<a name="l00233"></a>00233                         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#d0cda8ded2e5142d9a1c9c17efc5812f">start_xfer_buff</a> = cfi-&gt;<a class="code" href="structcfiobject.html#f6548b2b8fbab90656c22eb5ca857643">buf_in</a>.<a class="code" href="structcfi__dma__buff.html#474851b3123373b8b30fa3637eb81b5b">buf</a>;
+<a name="l00234"></a>00234                         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#97fa9bf5c31ba734d54f70e6fe6ae8eb">xfer_buff</a> = cfi-&gt;<a class="code" href="structcfiobject.html#f6548b2b8fbab90656c22eb5ca857643">buf_in</a>.<a class="code" href="structcfi__dma__buff.html#474851b3123373b8b30fa3637eb81b5b">buf</a>;
+<a name="l00235"></a>00235                         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">xfer_len</a> = retval;
+<a name="l00236"></a>00236                         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#23d4871510b5bcb54fbf0674d8f122bd">xfer_count</a> = 0;
+<a name="l00237"></a>00237                         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#8c6340435beba0b8c025a4677602acab">sent_zlp</a> = 0;
+<a name="l00238"></a>00238                         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#5a218f200cff0491b735f43fed5176bf">total_len</a> = ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">xfer_len</a>;
+<a name="l00239"></a>00239 
+<a name="l00240"></a>00240                         pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#2c8be11c3b9c7cd02684348eb028aeb5">ep0_pending</a> = 1;
+<a name="l00241"></a>00241                         <a class="code" href="dwc__otg__cil_8c.html#ee4989b24826b2a6592535282853e556">dwc_otg_ep0_start_transfer</a>(coreif, &amp;ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>);
+<a name="l00242"></a>00242                 }
+<a name="l00243"></a>00243                 <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>(<span class="stringliteral">"VEN_CORE_GET_FEATURE=%d\n"</span>, retval);
+<a name="l00244"></a>00244                 <a class="code" href="dwc__otg__cfi_8h.html#8d8df6d136115ec977eb6bf20148547a">dump_msg</a>(cfi-&gt;<a class="code" href="structcfiobject.html#f6548b2b8fbab90656c22eb5ca857643">buf_in</a>.<a class="code" href="structcfi__dma__buff.html#474851b3123373b8b30fa3637eb81b5b">buf</a>, retval);
+<a name="l00245"></a>00245                 <span class="keywordflow">break</span>;
+<a name="l00246"></a>00246 
+<a name="l00247"></a>00247         <span class="keywordflow">case</span> <a class="code" href="dwc__cfi__common_8h.html#ee7fb610a7fb2437df3425e2330e9d39">VEN_CORE_SET_FEATURE</a>:
+<a name="l00248"></a>00248                 <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>(<span class="stringliteral">"VEN_CORE_SET_FEATURE\n"</span>);
+<a name="l00249"></a>00249                 <span class="comment">/* Set up an XFER to get the data stage of the control request,</span>
+<a name="l00250"></a>00250 <span class="comment">                 * which is the new value of the feature to be modified.</span>
+<a name="l00251"></a>00251 <span class="comment">                 */</span>
+<a name="l00252"></a>00252                 ep = &amp;pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a>;
+<a name="l00253"></a>00253                 ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#b882b6b7c857100ed20600e94ea37760">is_in</a> = 0;
+<a name="l00254"></a>00254                 ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#b40ce70422b6d105a855a8df4b33d45d">dma_addr</a> = cfi-&gt;<a class="code" href="structcfiobject.html#adaa1cd0f88e639251f8dfbd65da7935">buf_out</a>.<a class="code" href="structcfi__dma__buff.html#549d40f7e33056fc5a99d51d00714d97">addr</a>;
+<a name="l00255"></a>00255                 ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#d0cda8ded2e5142d9a1c9c17efc5812f">start_xfer_buff</a> = cfi-&gt;<a class="code" href="structcfiobject.html#adaa1cd0f88e639251f8dfbd65da7935">buf_out</a>.<a class="code" href="structcfi__dma__buff.html#474851b3123373b8b30fa3637eb81b5b">buf</a>;
+<a name="l00256"></a>00256                 ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#97fa9bf5c31ba734d54f70e6fe6ae8eb">xfer_buff</a> = cfi-&gt;<a class="code" href="structcfiobject.html#adaa1cd0f88e639251f8dfbd65da7935">buf_out</a>.<a class="code" href="structcfi__dma__buff.html#474851b3123373b8b30fa3637eb81b5b">buf</a>;
+<a name="l00257"></a>00257                 ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">xfer_len</a> = wLen;
+<a name="l00258"></a>00258                 ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#23d4871510b5bcb54fbf0674d8f122bd">xfer_count</a> = 0;
+<a name="l00259"></a>00259                 ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#8c6340435beba0b8c025a4677602acab">sent_zlp</a> = 0;
+<a name="l00260"></a>00260                 ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#5a218f200cff0491b735f43fed5176bf">total_len</a> = ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">xfer_len</a>;
+<a name="l00261"></a>00261 
+<a name="l00262"></a>00262                 pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#2c8be11c3b9c7cd02684348eb028aeb5">ep0_pending</a> = 1;
+<a name="l00263"></a>00263                 <span class="comment">/* Read the control write's data stage */</span>
+<a name="l00264"></a>00264                 <a class="code" href="dwc__otg__cil_8c.html#ee4989b24826b2a6592535282853e556">dwc_otg_ep0_start_transfer</a>(coreif, &amp;ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>);
+<a name="l00265"></a>00265                 retval = 0;
+<a name="l00266"></a>00266                 <span class="keywordflow">break</span>;
+<a name="l00267"></a>00267 
+<a name="l00268"></a>00268         <span class="keywordflow">case</span> <a class="code" href="dwc__cfi__common_8h.html#f7551c9e324871e8258dacc4f4467846">VEN_CORE_RESET_FEATURES</a>:
+<a name="l00269"></a>00269                 <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>(<span class="stringliteral">"VEN_CORE_RESET_FEATURES\n"</span>);
+<a name="l00270"></a>00270                 cfi-&gt;<a class="code" href="structcfiobject.html#f103d681f78c43dc92dd4a85cdbdc27c">need_gadget_att</a> = 1;
+<a name="l00271"></a>00271                 cfi-&gt;<a class="code" href="structcfiobject.html#8d35a323dcd29a1c9d1a8568bd514c3b">need_status_in_complete</a> = 1;
+<a name="l00272"></a>00272                 retval = cfi_preproc_reset(pcd, ctrl);
+<a name="l00273"></a>00273                 <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>(<span class="stringliteral">"VEN_CORE_RESET_FEATURES = (%d)\n"</span>, retval);
+<a name="l00274"></a>00274                 <span class="keywordflow">break</span>;
+<a name="l00275"></a>00275 
+<a name="l00276"></a>00276         <span class="keywordflow">case</span> <a class="code" href="dwc__cfi__common_8h.html#1d1302d0d167f7c9580878fbfff847d4">VEN_CORE_ACTIVATE_FEATURES</a>:
+<a name="l00277"></a>00277                 <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>(<span class="stringliteral">"VEN_CORE_ACTIVATE_FEATURES\n"</span>);
+<a name="l00278"></a>00278                 <span class="keywordflow">break</span>;
+<a name="l00279"></a>00279 
+<a name="l00280"></a>00280         <span class="keywordflow">case</span> <a class="code" href="dwc__cfi__common_8h.html#8d4bf92524d3e5fd4b4b060fc1269ec6">VEN_CORE_READ_REGISTER</a>:
+<a name="l00281"></a>00281                 <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>(<span class="stringliteral">"VEN_CORE_READ_REGISTER\n"</span>);
+<a name="l00282"></a>00282                 <span class="comment">/* wValue optionally contains the HI WORD of the register offset and</span>
+<a name="l00283"></a>00283 <span class="comment">                 * wIndex contains the LOW WORD of the register offset </span>
+<a name="l00284"></a>00284 <span class="comment">                 */</span>
+<a name="l00285"></a>00285                 <span class="keywordflow">if</span> (wValue == 0) {
+<a name="l00286"></a>00286                         <span class="comment">/* @TODO - MAS - fix the access to the base field */</span>
+<a name="l00287"></a>00287                         regaddr = 0;
+<a name="l00288"></a>00288                         <span class="comment">//regaddr = (uint32_t) pcd-&gt;otg_dev-&gt;base;</span>
+<a name="l00289"></a>00289                         <span class="comment">//GET_CORE_IF(pcd)-&gt;co</span>
+<a name="l00290"></a>00290                         regaddr |= wIndex;
+<a name="l00291"></a>00291                 } <span class="keywordflow">else</span> {
+<a name="l00292"></a>00292                         regaddr = (wValue &lt;&lt; 16) | wIndex;
+<a name="l00293"></a>00293                 }
+<a name="l00294"></a>00294 
+<a name="l00295"></a>00295                 <span class="comment">/* Read a 32-bit value of the memory at the regaddr */</span>
+<a name="l00296"></a>00296                 regval = dwc_read_reg32((uint32_t *) regaddr);
+<a name="l00297"></a>00297 
+<a name="l00298"></a>00298                 ep = &amp;pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a>;
+<a name="l00299"></a>00299                 dwc_memcpy(cfi-&gt;<a class="code" href="structcfiobject.html#f6548b2b8fbab90656c22eb5ca857643">buf_in</a>.<a class="code" href="structcfi__dma__buff.html#474851b3123373b8b30fa3637eb81b5b">buf</a>, &amp;regval, <span class="keyword">sizeof</span>(uint32_t));
+<a name="l00300"></a>00300                 ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#b882b6b7c857100ed20600e94ea37760">is_in</a> = 1;
+<a name="l00301"></a>00301                 ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#b40ce70422b6d105a855a8df4b33d45d">dma_addr</a> = cfi-&gt;<a class="code" href="structcfiobject.html#f6548b2b8fbab90656c22eb5ca857643">buf_in</a>.<a class="code" href="structcfi__dma__buff.html#549d40f7e33056fc5a99d51d00714d97">addr</a>;
+<a name="l00302"></a>00302                 ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#d0cda8ded2e5142d9a1c9c17efc5812f">start_xfer_buff</a> = cfi-&gt;<a class="code" href="structcfiobject.html#f6548b2b8fbab90656c22eb5ca857643">buf_in</a>.<a class="code" href="structcfi__dma__buff.html#474851b3123373b8b30fa3637eb81b5b">buf</a>;
+<a name="l00303"></a>00303                 ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#97fa9bf5c31ba734d54f70e6fe6ae8eb">xfer_buff</a> = cfi-&gt;<a class="code" href="structcfiobject.html#f6548b2b8fbab90656c22eb5ca857643">buf_in</a>.<a class="code" href="structcfi__dma__buff.html#474851b3123373b8b30fa3637eb81b5b">buf</a>;
+<a name="l00304"></a>00304                 ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">xfer_len</a> = wLen;
+<a name="l00305"></a>00305                 ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#23d4871510b5bcb54fbf0674d8f122bd">xfer_count</a> = 0;
+<a name="l00306"></a>00306                 ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#8c6340435beba0b8c025a4677602acab">sent_zlp</a> = 0;
+<a name="l00307"></a>00307                 ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#5a218f200cff0491b735f43fed5176bf">total_len</a> = ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">xfer_len</a>;
+<a name="l00308"></a>00308 
+<a name="l00309"></a>00309                 pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#2c8be11c3b9c7cd02684348eb028aeb5">ep0_pending</a> = 1;
+<a name="l00310"></a>00310                 <a class="code" href="dwc__otg__cil_8c.html#ee4989b24826b2a6592535282853e556">dwc_otg_ep0_start_transfer</a>(coreif, &amp;ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>);
+<a name="l00311"></a>00311                 cfi-&gt;<a class="code" href="structcfiobject.html#f103d681f78c43dc92dd4a85cdbdc27c">need_gadget_att</a> = 0;
+<a name="l00312"></a>00312                 retval = 0;
+<a name="l00313"></a>00313                 <span class="keywordflow">break</span>;
+<a name="l00314"></a>00314 
+<a name="l00315"></a>00315         <span class="keywordflow">case</span> <a class="code" href="dwc__cfi__common_8h.html#d132d545f74a408b62d44a34ba51426c">VEN_CORE_WRITE_REGISTER</a>:
+<a name="l00316"></a>00316                 <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>(<span class="stringliteral">"VEN_CORE_WRITE_REGISTER\n"</span>);
+<a name="l00317"></a>00317                 <span class="comment">/* Set up an XFER to get the data stage of the control request,</span>
+<a name="l00318"></a>00318 <span class="comment">                 * which is the new value of the register to be modified.</span>
+<a name="l00319"></a>00319 <span class="comment">                 */</span>
+<a name="l00320"></a>00320                 ep = &amp;pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a>;
+<a name="l00321"></a>00321                 ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#b882b6b7c857100ed20600e94ea37760">is_in</a> = 0;
+<a name="l00322"></a>00322                 ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#b40ce70422b6d105a855a8df4b33d45d">dma_addr</a> = cfi-&gt;<a class="code" href="structcfiobject.html#adaa1cd0f88e639251f8dfbd65da7935">buf_out</a>.<a class="code" href="structcfi__dma__buff.html#549d40f7e33056fc5a99d51d00714d97">addr</a>;
+<a name="l00323"></a>00323                 ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#d0cda8ded2e5142d9a1c9c17efc5812f">start_xfer_buff</a> = cfi-&gt;<a class="code" href="structcfiobject.html#adaa1cd0f88e639251f8dfbd65da7935">buf_out</a>.<a class="code" href="structcfi__dma__buff.html#474851b3123373b8b30fa3637eb81b5b">buf</a>;
+<a name="l00324"></a>00324                 ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#97fa9bf5c31ba734d54f70e6fe6ae8eb">xfer_buff</a> = cfi-&gt;<a class="code" href="structcfiobject.html#adaa1cd0f88e639251f8dfbd65da7935">buf_out</a>.<a class="code" href="structcfi__dma__buff.html#474851b3123373b8b30fa3637eb81b5b">buf</a>;
+<a name="l00325"></a>00325                 ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">xfer_len</a> = wLen;
+<a name="l00326"></a>00326                 ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#23d4871510b5bcb54fbf0674d8f122bd">xfer_count</a> = 0;
+<a name="l00327"></a>00327                 ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#8c6340435beba0b8c025a4677602acab">sent_zlp</a> = 0;
+<a name="l00328"></a>00328                 ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#5a218f200cff0491b735f43fed5176bf">total_len</a> = ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">xfer_len</a>;
+<a name="l00329"></a>00329 
+<a name="l00330"></a>00330                 pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#2c8be11c3b9c7cd02684348eb028aeb5">ep0_pending</a> = 1;
+<a name="l00331"></a>00331                 <span class="comment">/* Read the control write's data stage */</span>
+<a name="l00332"></a>00332                 <a class="code" href="dwc__otg__cil_8c.html#ee4989b24826b2a6592535282853e556">dwc_otg_ep0_start_transfer</a>(coreif, &amp;ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>);
+<a name="l00333"></a>00333                 retval = 0;
+<a name="l00334"></a>00334                 <span class="keywordflow">break</span>;
+<a name="l00335"></a>00335 
+<a name="l00336"></a>00336         <span class="keywordflow">default</span>:
+<a name="l00337"></a>00337                 retval = -DWC_E_NOT_SUPPORTED;
+<a name="l00338"></a>00338                 <span class="keywordflow">break</span>;
+<a name="l00339"></a>00339         }
+<a name="l00340"></a>00340 
+<a name="l00341"></a>00341         <span class="keywordflow">return</span> retval;
+<a name="l00342"></a>00342 }
+<a name="l00343"></a>00343 
+<a name="l00355"></a>00355 <span class="keyword">static</span> <span class="keywordtype">int</span> cfi_core_features_buf(uint8_t * buf, uint16_t buflen)
+<a name="l00356"></a>00356 {
+<a name="l00357"></a>00357         <a class="code" href="structcfi__feature__desc__header.html">cfi_feature_desc_header_t</a> *prop_hdr = prop_descs;
+<a name="l00358"></a>00358         <a class="code" href="structcfi__feature__desc__header.html">cfi_feature_desc_header_t</a> *prop;
+<a name="l00359"></a>00359         <a class="code" href="structcfi__all__features__header.html">cfi_all_features_header_t</a> *all_props_hdr = &amp;all_props_desc_header;
+<a name="l00360"></a>00360         <a class="code" href="structcfi__all__features__header.html">cfi_all_features_header_t</a> *tmp;
+<a name="l00361"></a>00361         uint8_t *tmpbuf = buf;
+<a name="l00362"></a>00362         <span class="keyword">const</span> uint8_t *pname = NULL;
+<a name="l00363"></a>00363         <span class="keywordtype">int</span> i, j, namelen = 0, totlen;
+<a name="l00364"></a>00364 
+<a name="l00365"></a>00365         <span class="comment">/* Prepare and copy the core features into the buffer */</span>
+<a name="l00366"></a>00366         <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>(<span class="stringliteral">"%s:\n"</span>, __func__);
+<a name="l00367"></a>00367 
+<a name="l00368"></a>00368         tmp = (<a class="code" href="structcfi__all__features__header.html">cfi_all_features_header_t</a> *) tmpbuf;
+<a name="l00369"></a>00369         *tmp = *all_props_hdr;
+<a name="l00370"></a>00370         tmpbuf += <a class="code" href="dwc__cfi__common_8h.html#b6c1d0a310ae1d0a89437b2cf92e57ba">CFI_ALL_FEATURES_HDR_LEN</a>;
+<a name="l00371"></a>00371 
+<a name="l00372"></a>00372         j = <span class="keyword">sizeof</span>(prop_descs) / <span class="keyword">sizeof</span>(<a class="code" href="structcfi__all__features__header.html">cfi_all_features_header_t</a>);
+<a name="l00373"></a>00373         <span class="keywordflow">for</span> (i = 0; i &lt; j; i++, prop_hdr++) {
+<a name="l00374"></a>00374                 pname = get_prop_name(prop_hdr-&gt;<a class="code" href="structcfi__feature__desc__header.html#f76e757383a5210368e599f872952170">wFeatureID</a>, &amp;namelen);
+<a name="l00375"></a>00375                 prop = (<a class="code" href="structcfi__feature__desc__header.html">cfi_feature_desc_header_t</a> *) tmpbuf;
+<a name="l00376"></a>00376                 *prop = *prop_hdr;
+<a name="l00377"></a>00377 
+<a name="l00378"></a>00378                 prop-&gt;<a class="code" href="structcfi__feature__desc__header.html#4e90b7a616a2efc24937fc6d5cff1347">bNameLen</a> = namelen;
+<a name="l00379"></a>00379                 prop-&gt;<a class="code" href="structcfi__feature__desc__header.html#77769436c06687bdbe98c5e75e7641df">wLength</a> =
+<a name="l00380"></a>00380                     DWC_CONSTANT_CPU_TO_LE16(<a class="code" href="dwc__cfi__common_8h.html#7ec5e43b7d52a39b553fdfa8fb17d889">CFI_FEATURE_DESC_HDR_LEN</a> +
+<a name="l00381"></a>00381                                              namelen);
+<a name="l00382"></a>00382 
+<a name="l00383"></a>00383                 tmpbuf += <a class="code" href="dwc__cfi__common_8h.html#7ec5e43b7d52a39b553fdfa8fb17d889">CFI_FEATURE_DESC_HDR_LEN</a>;
+<a name="l00384"></a>00384                 dwc_memcpy(tmpbuf, pname, namelen);
+<a name="l00385"></a>00385                 tmpbuf += namelen;
+<a name="l00386"></a>00386         }
+<a name="l00387"></a>00387 
+<a name="l00388"></a>00388         totlen = tmpbuf - buf;
+<a name="l00389"></a>00389 
+<a name="l00390"></a>00390         <span class="keywordflow">if</span> (totlen &gt; 0) {
+<a name="l00391"></a>00391                 tmp = (cfi_all_features_header_t *) buf;
+<a name="l00392"></a>00392                 tmp-&gt;<a class="code" href="structcfi__all__features__header.html#3973fa190311671de5bbd74a7b825f42">wTotalLen</a> = DWC_CONSTANT_CPU_TO_LE16(totlen);
+<a name="l00393"></a>00393         }
+<a name="l00394"></a>00394 
+<a name="l00395"></a>00395         <span class="keywordflow">return</span> totlen;
+<a name="l00396"></a>00396 }
+<a name="l00397"></a>00397 
+<a name="l00401"></a>00401 <span class="keyword">static</span> <span class="keywordtype">void</span> cfi_release(<a class="code" href="structcfiobject.html">cfiobject_t</a> * cfiobj)
+<a name="l00402"></a>00402 {
+<a name="l00403"></a>00403         <a class="code" href="structcfi__ep.html">cfi_ep_t</a> *cfiep;
+<a name="l00404"></a>00404         dwc_list_link_t *tmp;
+<a name="l00405"></a>00405 
+<a name="l00406"></a>00406         <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>(<span class="stringliteral">"%s\n"</span>, __func__);
+<a name="l00407"></a>00407 
+<a name="l00408"></a>00408         <span class="keywordflow">if</span> (cfiobj-&gt;<a class="code" href="structcfiobject.html#f6548b2b8fbab90656c22eb5ca857643">buf_in</a>.<a class="code" href="structcfi__dma__buff.html#474851b3123373b8b30fa3637eb81b5b">buf</a>) {
+<a name="l00409"></a>00409                 dwc_dma_free(<a class="code" href="dwc__otg__cfi_8h.html#34582b9ef366f4c0e8ea24aa2388e829">CFI_IN_BUF_LEN</a>, cfiobj-&gt;<a class="code" href="structcfiobject.html#f6548b2b8fbab90656c22eb5ca857643">buf_in</a>.<a class="code" href="structcfi__dma__buff.html#474851b3123373b8b30fa3637eb81b5b">buf</a>,
+<a name="l00410"></a>00410                              cfiobj-&gt;<a class="code" href="structcfiobject.html#f6548b2b8fbab90656c22eb5ca857643">buf_in</a>.<a class="code" href="structcfi__dma__buff.html#549d40f7e33056fc5a99d51d00714d97">addr</a>);
+<a name="l00411"></a>00411                 cfiobj-&gt;<a class="code" href="structcfiobject.html#f6548b2b8fbab90656c22eb5ca857643">buf_in</a>.<a class="code" href="structcfi__dma__buff.html#474851b3123373b8b30fa3637eb81b5b">buf</a> = NULL;
+<a name="l00412"></a>00412         }
+<a name="l00413"></a>00413 
+<a name="l00414"></a>00414         <span class="keywordflow">if</span> (cfiobj-&gt;<a class="code" href="structcfiobject.html#adaa1cd0f88e639251f8dfbd65da7935">buf_out</a>.<a class="code" href="structcfi__dma__buff.html#474851b3123373b8b30fa3637eb81b5b">buf</a>) {
+<a name="l00415"></a>00415                 dwc_dma_free(<a class="code" href="dwc__otg__cfi_8h.html#739556affb10ce8a44b362b8ffa41a40">CFI_OUT_BUF_LEN</a>, cfiobj-&gt;<a class="code" href="structcfiobject.html#adaa1cd0f88e639251f8dfbd65da7935">buf_out</a>.<a class="code" href="structcfi__dma__buff.html#474851b3123373b8b30fa3637eb81b5b">buf</a>,
+<a name="l00416"></a>00416                              cfiobj-&gt;<a class="code" href="structcfiobject.html#adaa1cd0f88e639251f8dfbd65da7935">buf_out</a>.<a class="code" href="structcfi__dma__buff.html#549d40f7e33056fc5a99d51d00714d97">addr</a>);
+<a name="l00417"></a>00417                 cfiobj-&gt;<a class="code" href="structcfiobject.html#adaa1cd0f88e639251f8dfbd65da7935">buf_out</a>.<a class="code" href="structcfi__dma__buff.html#474851b3123373b8b30fa3637eb81b5b">buf</a> = NULL;
+<a name="l00418"></a>00418         }
+<a name="l00419"></a>00419 
+<a name="l00420"></a>00420         <span class="comment">/* Free the Buffer Setup values for each EP */</span>
+<a name="l00421"></a>00421         <span class="comment">//list_for_each_entry(cfiep, &amp;cfiobj-&gt;active_eps, lh) {</span>
+<a name="l00422"></a>00422         DWC_LIST_FOREACH(tmp, &amp;cfiobj-&gt;<a class="code" href="structcfiobject.html#82805f011abf3deace7faa159729229a">active_eps</a>) {
+<a name="l00423"></a>00423                 cfiep = DWC_LIST_ENTRY(tmp, <span class="keyword">struct</span> <a class="code" href="structcfi__ep.html">cfi_ep</a>, lh);
+<a name="l00424"></a>00424                 cfi_free_ep_bs_dyn_data(cfiep);
+<a name="l00425"></a>00425         }
+<a name="l00426"></a>00426 }
+<a name="l00427"></a>00427 
+<a name="l00431"></a>00431 <span class="keyword">static</span> <span class="keywordtype">void</span> cfi_free_ep_bs_dyn_data(<a class="code" href="structcfi__ep.html">cfi_ep_t</a> * cfiep)
+<a name="l00432"></a>00432 {
+<a name="l00433"></a>00433         <span class="keywordflow">if</span> (cfiep-&gt;<a class="code" href="structcfi__ep.html#4010b0f12bf1cd37a2c0bf06b392570a">bm_sg</a>) {
+<a name="l00434"></a>00434                 dwc_free(cfiep-&gt;<a class="code" href="structcfi__ep.html#4010b0f12bf1cd37a2c0bf06b392570a">bm_sg</a>);
+<a name="l00435"></a>00435                 cfiep-&gt;<a class="code" href="structcfi__ep.html#4010b0f12bf1cd37a2c0bf06b392570a">bm_sg</a> = NULL;
+<a name="l00436"></a>00436         }
+<a name="l00437"></a>00437 
+<a name="l00438"></a>00438         <span class="keywordflow">if</span> (cfiep-&gt;<a class="code" href="structcfi__ep.html#bb544b7938d0c62857fc3726988310d2">bm_align</a>) {
+<a name="l00439"></a>00439                 dwc_free(cfiep-&gt;<a class="code" href="structcfi__ep.html#bb544b7938d0c62857fc3726988310d2">bm_align</a>);
+<a name="l00440"></a>00440                 cfiep-&gt;<a class="code" href="structcfi__ep.html#bb544b7938d0c62857fc3726988310d2">bm_align</a> = NULL;
+<a name="l00441"></a>00441         }
+<a name="l00442"></a>00442 
+<a name="l00443"></a>00443         <span class="keywordflow">if</span> (cfiep-&gt;<a class="code" href="structcfi__ep.html#4c83b9bb5a75e6b81fbfa86b51736164">bm_concat</a>) {
+<a name="l00444"></a>00444                 <span class="keywordflow">if</span> (NULL != cfiep-&gt;<a class="code" href="structcfi__ep.html#4c83b9bb5a75e6b81fbfa86b51736164">bm_concat</a>-&gt;<a class="code" href="struct__ddma__concat__buffer__setup.html#748241a5b55a514f4386498aceb1e505">wTxBytes</a>) {
+<a name="l00445"></a>00445                         dwc_free(cfiep-&gt;<a class="code" href="structcfi__ep.html#4c83b9bb5a75e6b81fbfa86b51736164">bm_concat</a>-&gt;<a class="code" href="struct__ddma__concat__buffer__setup.html#748241a5b55a514f4386498aceb1e505">wTxBytes</a>);
+<a name="l00446"></a>00446                         cfiep-&gt;<a class="code" href="structcfi__ep.html#4c83b9bb5a75e6b81fbfa86b51736164">bm_concat</a>-&gt;<a class="code" href="struct__ddma__concat__buffer__setup.html#748241a5b55a514f4386498aceb1e505">wTxBytes</a> = NULL;
+<a name="l00447"></a>00447                 }
+<a name="l00448"></a>00448                 dwc_free(cfiep-&gt;<a class="code" href="structcfi__ep.html#4c83b9bb5a75e6b81fbfa86b51736164">bm_concat</a>);
+<a name="l00449"></a>00449                 cfiep-&gt;<a class="code" href="structcfi__ep.html#4c83b9bb5a75e6b81fbfa86b51736164">bm_concat</a> = NULL;
+<a name="l00450"></a>00450         }
+<a name="l00451"></a>00451 }
+<a name="l00452"></a>00452 
+<a name="l00458"></a>00458 <span class="keyword">static</span> <span class="keywordtype">int</span> cfi_ep_init_defaults(<span class="keyword">struct</span> <a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd</a> *pcd, <a class="code" href="structcfi__ep.html">cfi_ep_t</a> * cfiep)
+<a name="l00459"></a>00459 {
+<a name="l00460"></a>00460         <span class="keywordtype">int</span> retval = 0;
+<a name="l00461"></a>00461 
+<a name="l00462"></a>00462         cfiep-&gt;<a class="code" href="structcfi__ep.html#4010b0f12bf1cd37a2c0bf06b392570a">bm_sg</a> = dwc_alloc(<span class="keyword">sizeof</span>(<a class="code" href="struct__ddma__sg__buffer__setup.html">ddma_sg_buffer_setup_t</a>));
+<a name="l00463"></a>00463         <span class="keywordflow">if</span> (NULL == cfiep-&gt;<a class="code" href="structcfi__ep.html#4010b0f12bf1cd37a2c0bf06b392570a">bm_sg</a>) {
+<a name="l00464"></a>00464                 <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>(<span class="stringliteral">"Failed to allocate memory for SG feature value\n"</span>);
+<a name="l00465"></a>00465                 <span class="keywordflow">return</span> -DWC_E_NO_MEMORY;
+<a name="l00466"></a>00466         }
+<a name="l00467"></a>00467         dwc_memset(cfiep-&gt;<a class="code" href="structcfi__ep.html#4010b0f12bf1cd37a2c0bf06b392570a">bm_sg</a>, 0, <span class="keyword">sizeof</span>(<a class="code" href="struct__ddma__sg__buffer__setup.html">ddma_sg_buffer_setup_t</a>));
+<a name="l00468"></a>00468 
+<a name="l00469"></a>00469         <span class="comment">/* For the Concatenation feature's default value we do not allocate</span>
+<a name="l00470"></a>00470 <span class="comment">         * memory for the wTxBytes field - it will be done in the set_feature_value</span>
+<a name="l00471"></a>00471 <span class="comment">         * request handler.</span>
+<a name="l00472"></a>00472 <span class="comment">         */</span>
+<a name="l00473"></a>00473         cfiep-&gt;<a class="code" href="structcfi__ep.html#4c83b9bb5a75e6b81fbfa86b51736164">bm_concat</a> = dwc_alloc(<span class="keyword">sizeof</span>(<a class="code" href="struct__ddma__concat__buffer__setup.html">ddma_concat_buffer_setup_t</a>));
+<a name="l00474"></a>00474         <span class="keywordflow">if</span> (NULL == cfiep-&gt;<a class="code" href="structcfi__ep.html#4c83b9bb5a75e6b81fbfa86b51736164">bm_concat</a>) {
+<a name="l00475"></a>00475                 <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>
+<a name="l00476"></a>00476                     (<span class="stringliteral">"Failed to allocate memory for CONCATENATION feature value\n"</span>);
+<a name="l00477"></a>00477                 dwc_free(cfiep-&gt;<a class="code" href="structcfi__ep.html#4010b0f12bf1cd37a2c0bf06b392570a">bm_sg</a>);
+<a name="l00478"></a>00478                 <span class="keywordflow">return</span> -DWC_E_NO_MEMORY;
+<a name="l00479"></a>00479         }
+<a name="l00480"></a>00480         dwc_memset(cfiep-&gt;<a class="code" href="structcfi__ep.html#4c83b9bb5a75e6b81fbfa86b51736164">bm_concat</a>, 0, <span class="keyword">sizeof</span>(<a class="code" href="struct__ddma__concat__buffer__setup.html">ddma_concat_buffer_setup_t</a>));
+<a name="l00481"></a>00481 
+<a name="l00482"></a>00482         cfiep-&gt;<a class="code" href="structcfi__ep.html#bb544b7938d0c62857fc3726988310d2">bm_align</a> = dwc_alloc(<span class="keyword">sizeof</span>(<a class="code" href="struct__ddma__align__buffer__setup.html">ddma_align_buffer_setup_t</a>));
+<a name="l00483"></a>00483         <span class="keywordflow">if</span> (NULL == cfiep-&gt;<a class="code" href="structcfi__ep.html#bb544b7938d0c62857fc3726988310d2">bm_align</a>) {
+<a name="l00484"></a>00484                 <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>
+<a name="l00485"></a>00485                     (<span class="stringliteral">"Failed to allocate memory for Alignment feature value\n"</span>);
+<a name="l00486"></a>00486                 dwc_free(cfiep-&gt;<a class="code" href="structcfi__ep.html#4010b0f12bf1cd37a2c0bf06b392570a">bm_sg</a>);
+<a name="l00487"></a>00487                 dwc_free(cfiep-&gt;<a class="code" href="structcfi__ep.html#4c83b9bb5a75e6b81fbfa86b51736164">bm_concat</a>);
+<a name="l00488"></a>00488                 <span class="keywordflow">return</span> -DWC_E_NO_MEMORY;
+<a name="l00489"></a>00489         }
+<a name="l00490"></a>00490         dwc_memset(cfiep-&gt;<a class="code" href="structcfi__ep.html#bb544b7938d0c62857fc3726988310d2">bm_align</a>, 0, <span class="keyword">sizeof</span>(<a class="code" href="struct__ddma__align__buffer__setup.html">ddma_align_buffer_setup_t</a>));
+<a name="l00491"></a>00491 
+<a name="l00492"></a>00492         <span class="keywordflow">return</span> retval;
+<a name="l00493"></a>00493 }
+<a name="l00494"></a>00494 
+<a name="l00506"></a>00506 <span class="keyword">static</span> <span class="keywordtype">int</span> cfi_ep_enable(<span class="keyword">struct</span> <a class="code" href="structcfiobject.html">cfiobject</a> *cfi, <span class="keyword">struct</span> <a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd</a> *pcd,
+<a name="l00507"></a>00507                          <span class="keyword">struct</span> <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep</a> *ep)
+<a name="l00508"></a>00508 {
+<a name="l00509"></a>00509         <a class="code" href="structcfi__ep.html">cfi_ep_t</a> *cfiep;
+<a name="l00510"></a>00510         <span class="keywordtype">int</span> retval = -DWC_E_NOT_SUPPORTED;
+<a name="l00511"></a>00511 
+<a name="l00512"></a>00512         <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>(<span class="stringliteral">"%s: epname=%s; epnum=0x%02x\n"</span>, __func__,
+<a name="l00513"></a>00513                  <span class="stringliteral">"EP_"</span> <span class="comment">/*ep-&gt;ep.name */</span> , ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#86e27843c439dd0b1d12d9bf2dc6516f">desc</a>-&gt;bEndpointAddress);
+<a name="l00514"></a>00514         <span class="comment">/* MAS - Check whether this endpoint already is in the list */</span>
+<a name="l00515"></a>00515         cfiep = <a class="code" href="dwc__otg__cfi_8h.html#c21284d5adf03032d094a36babf9b1e5">get_cfi_ep_by_pcd_ep</a>(cfi, ep);
+<a name="l00516"></a>00516 
+<a name="l00517"></a>00517         <span class="keywordflow">if</span> (NULL == cfiep) {
+<a name="l00518"></a>00518                 <span class="comment">/* Allocate a cfi_ep_t object */</span>
+<a name="l00519"></a>00519                 cfiep = dwc_alloc(<span class="keyword">sizeof</span>(<a class="code" href="structcfi__ep.html">cfi_ep_t</a>));
+<a name="l00520"></a>00520                 <span class="keywordflow">if</span> (NULL == cfiep) {
+<a name="l00521"></a>00521                         <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>
+<a name="l00522"></a>00522                             (<span class="stringliteral">"Unable to allocate memory for &lt;cfiep&gt; in function %s\n"</span>,
+<a name="l00523"></a>00523                              __func__);
+<a name="l00524"></a>00524                         <span class="keywordflow">return</span> -DWC_E_NO_MEMORY;
+<a name="l00525"></a>00525                 }
+<a name="l00526"></a>00526                 dwc_memset(cfiep, 0, <span class="keyword">sizeof</span>(<a class="code" href="structcfi__ep.html">cfi_ep_t</a>));
+<a name="l00527"></a>00527 
+<a name="l00528"></a>00528                 <span class="comment">/* Save the dwc_otg_pcd_ep pointer in the cfiep object */</span>
+<a name="l00529"></a>00529                 cfiep-&gt;<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a> = ep;
+<a name="l00530"></a>00530 
+<a name="l00531"></a>00531                 <span class="comment">/* Allocate the DMA Descriptors chain of MAX_DMA_DESCS_PER_EP count */</span>
+<a name="l00532"></a>00532                 ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.descs =
+<a name="l00533"></a>00533                     dwc_dma_alloc(MAX_DMA_DESCS_PER_EP *
+<a name="l00534"></a>00534                                   <span class="keyword">sizeof</span>(dwc_otg_dma_desc_t),
+<a name="l00535"></a>00535                                   &amp;ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.descs_dma_addr);
+<a name="l00536"></a>00536 
+<a name="l00537"></a>00537                 <span class="keywordflow">if</span> (NULL == ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.descs) {
+<a name="l00538"></a>00538                         dwc_free(cfiep);
+<a name="l00539"></a>00539                         <span class="keywordflow">return</span> -DWC_E_NO_MEMORY;
+<a name="l00540"></a>00540                 }
+<a name="l00541"></a>00541 
+<a name="l00542"></a>00542                 DWC_LIST_INIT(&amp;cfiep-&gt;<a class="code" href="structcfi__ep.html#18bff3370dc933cd374d458897dfbc2f">lh</a>);
+<a name="l00543"></a>00543 
+<a name="l00544"></a>00544                 <span class="comment">/* Set the buffer mode to BM_STANDARD. It will be modified </span>
+<a name="l00545"></a>00545 <span class="comment">                 * when building descriptors for a specific buffer mode */</span>
+<a name="l00546"></a>00546                 ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.buff_mode = BM_STANDARD;
+<a name="l00547"></a>00547 
+<a name="l00548"></a>00548                 <span class="comment">/* Create and initialize the default values for this EP's Buffer modes */</span>
+<a name="l00549"></a>00549                 <span class="keywordflow">if</span> ((retval = cfi_ep_init_defaults(pcd, cfiep)) &lt; 0)
+<a name="l00550"></a>00550                         <span class="keywordflow">return</span> retval;
+<a name="l00551"></a>00551 
+<a name="l00552"></a>00552                 <span class="comment">/* Add the cfi_ep_t object to the CFI object's list of active endpoints */</span>
+<a name="l00553"></a>00553                 DWC_LIST_INSERT_TAIL(&amp;cfi-&gt;<a class="code" href="structcfiobject.html#82805f011abf3deace7faa159729229a">active_eps</a>, &amp;cfiep-&gt;<a class="code" href="structcfi__ep.html#18bff3370dc933cd374d458897dfbc2f">lh</a>);
+<a name="l00554"></a>00554                 retval = 0;
+<a name="l00555"></a>00555         } <span class="keywordflow">else</span> {                <span class="comment">/* The sought EP already is in the list */</span>
+<a name="l00556"></a>00556                 <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>(<span class="stringliteral">"%s: The sought EP already is in the list\n"</span>,
+<a name="l00557"></a>00557                          __func__);
+<a name="l00558"></a>00558         }
+<a name="l00559"></a>00559 
+<a name="l00560"></a>00560         <span class="keywordflow">return</span> retval;
+<a name="l00561"></a>00561 }
+<a name="l00562"></a>00562 
+<a name="l00568"></a>00568 <span class="keyword">static</span> <span class="keywordtype">int</span> cfi_ctrl_write_complete(<span class="keyword">struct</span> <a class="code" href="structcfiobject.html">cfiobject</a> *cfi,
+<a name="l00569"></a>00569                                    <span class="keyword">struct</span> <a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd</a> *pcd)
+<a name="l00570"></a>00570 {
+<a name="l00571"></a>00571         uint32_t addr, reg_value;
+<a name="l00572"></a>00572         uint16_t wIndex, wValue;
+<a name="l00573"></a>00573         uint8_t bRequest;
+<a name="l00574"></a>00574         uint8_t *buf = cfi-&gt;<a class="code" href="structcfiobject.html#adaa1cd0f88e639251f8dfbd65da7935">buf_out</a>.<a class="code" href="structcfi__dma__buff.html#474851b3123373b8b30fa3637eb81b5b">buf</a>;
+<a name="l00575"></a>00575         <span class="comment">//struct usb_ctrlrequest *ctrl_req = &amp;cfi-&gt;ctrl_req_saved;</span>
+<a name="l00576"></a>00576         <span class="keyword">struct </span><a class="code" href="structcfi__usb__ctrlrequest.html">cfi_usb_ctrlrequest</a> *ctrl_req = &amp;cfi-&gt;<a class="code" href="structcfiobject.html#a86c33aef2a521a27ca515bb7397dd34">ctrl_req</a>;
+<a name="l00577"></a>00577         <span class="keywordtype">int</span> retval = -DWC_E_NOT_SUPPORTED;
+<a name="l00578"></a>00578 
+<a name="l00579"></a>00579         <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>(<span class="stringliteral">"%s\n"</span>, __func__);
+<a name="l00580"></a>00580 
+<a name="l00581"></a>00581         bRequest = ctrl_req-&gt;<a class="code" href="structcfi__usb__ctrlrequest.html#b3083f525fa9bb97e41364418daee3fa">bRequest</a>;
+<a name="l00582"></a>00582         wIndex = DWC_CONSTANT_CPU_TO_LE16(ctrl_req-&gt;<a class="code" href="structcfi__usb__ctrlrequest.html#984c95bd61e8d1120cd935bcbc5d7134">wIndex</a>);
+<a name="l00583"></a>00583         wValue = DWC_CONSTANT_CPU_TO_LE16(ctrl_req-&gt;<a class="code" href="structcfi__usb__ctrlrequest.html#2f236bbf9450df1a3b5204c4570d883f">wValue</a>);
+<a name="l00584"></a>00584 
+<a name="l00585"></a>00585         <span class="comment">/* </span>
+<a name="l00586"></a>00586 <span class="comment">         * Save the pointer to the data stage in the ctrl_req's &lt;data&gt; field.</span>
+<a name="l00587"></a>00587 <span class="comment">         * The request should be already saved in the command stage by now.</span>
+<a name="l00588"></a>00588 <span class="comment">         */</span>
+<a name="l00589"></a>00589         ctrl_req-&gt;<a class="code" href="structcfi__usb__ctrlrequest.html#5b3865e9cb2c0fcf373b1c862a63c180">data</a> = cfi-&gt;<a class="code" href="structcfiobject.html#adaa1cd0f88e639251f8dfbd65da7935">buf_out</a>.<a class="code" href="structcfi__dma__buff.html#474851b3123373b8b30fa3637eb81b5b">buf</a>;
+<a name="l00590"></a>00590         cfi-&gt;<a class="code" href="structcfiobject.html#8d35a323dcd29a1c9d1a8568bd514c3b">need_status_in_complete</a> = 0;
+<a name="l00591"></a>00591         cfi-&gt;<a class="code" href="structcfiobject.html#f103d681f78c43dc92dd4a85cdbdc27c">need_gadget_att</a> = 0;
+<a name="l00592"></a>00592 
+<a name="l00593"></a>00593         <span class="keywordflow">switch</span> (bRequest) {
+<a name="l00594"></a>00594         <span class="keywordflow">case</span> <a class="code" href="dwc__cfi__common_8h.html#d132d545f74a408b62d44a34ba51426c">VEN_CORE_WRITE_REGISTER</a>:
+<a name="l00595"></a>00595                 <span class="comment">/* The buffer contains raw data of the new value for the register */</span>
+<a name="l00596"></a>00596                 reg_value = *((uint32_t *) buf);
+<a name="l00597"></a>00597                 <span class="keywordflow">if</span> (wValue == 0) {
+<a name="l00598"></a>00598                         addr = 0;
+<a name="l00599"></a>00599                         <span class="comment">//addr = (uint32_t) pcd-&gt;otg_dev-&gt;base;</span>
+<a name="l00600"></a>00600                         addr += wIndex;
+<a name="l00601"></a>00601                 } <span class="keywordflow">else</span> {
+<a name="l00602"></a>00602                         addr = (wValue &lt;&lt; 16) | wIndex;
+<a name="l00603"></a>00603                 }
+<a name="l00604"></a>00604 
+<a name="l00605"></a>00605                 <span class="comment">//writel(reg_value, addr);</span>
+<a name="l00606"></a>00606 
+<a name="l00607"></a>00607                 retval = 0;
+<a name="l00608"></a>00608                 cfi-&gt;<a class="code" href="structcfiobject.html#8d35a323dcd29a1c9d1a8568bd514c3b">need_status_in_complete</a> = 1;
+<a name="l00609"></a>00609                 <span class="keywordflow">break</span>;
+<a name="l00610"></a>00610 
+<a name="l00611"></a>00611         <span class="keywordflow">case</span> <a class="code" href="dwc__cfi__common_8h.html#ee7fb610a7fb2437df3425e2330e9d39">VEN_CORE_SET_FEATURE</a>:
+<a name="l00612"></a>00612                 <span class="comment">/* The buffer contains raw data of the new value of the feature */</span>
+<a name="l00613"></a>00613                 retval = cfi_set_feature_value(pcd);
+<a name="l00614"></a>00614                 <span class="keywordflow">if</span> (retval &lt; 0)
+<a name="l00615"></a>00615                         <span class="keywordflow">return</span> retval;
+<a name="l00616"></a>00616 
+<a name="l00617"></a>00617                 cfi-&gt;<a class="code" href="structcfiobject.html#8d35a323dcd29a1c9d1a8568bd514c3b">need_status_in_complete</a> = 1;
+<a name="l00618"></a>00618                 <span class="keywordflow">break</span>;
+<a name="l00619"></a>00619 
+<a name="l00620"></a>00620         <span class="keywordflow">default</span>:
+<a name="l00621"></a>00621                 <span class="keywordflow">break</span>;
+<a name="l00622"></a>00622         }
+<a name="l00623"></a>00623 
+<a name="l00624"></a>00624         <span class="keywordflow">return</span> retval;
+<a name="l00625"></a>00625 }
+<a name="l00626"></a>00626 
+<a name="l00630"></a>00630 <span class="keyword">static</span> <span class="keywordtype">void</span> cfi_build_sg_descs(<span class="keyword">struct</span> <a class="code" href="structcfiobject.html">cfiobject</a> *cfi, <a class="code" href="structcfi__ep.html">cfi_ep_t</a> * cfiep,
+<a name="l00631"></a>00631                                <a class="code" href="structdwc__otg__pcd__request.html">dwc_otg_pcd_request_t</a> * req)
+<a name="l00632"></a>00632 {
+<a name="l00633"></a>00633         <span class="keyword">struct </span><a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep</a> *ep = cfiep-&gt;<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>;
+<a name="l00634"></a>00634         <a class="code" href="struct__ddma__sg__buffer__setup.html">ddma_sg_buffer_setup_t</a> *sgval = cfiep-&gt;<a class="code" href="structcfi__ep.html#4010b0f12bf1cd37a2c0bf06b392570a">bm_sg</a>;
+<a name="l00635"></a>00635         <span class="keyword">struct </span>dwc_otg_dma_desc *desc = cfiep-&gt;<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.descs;
+<a name="l00636"></a>00636         <span class="keyword">struct </span>dwc_otg_dma_desc *desc_last = cfiep-&gt;<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.descs;
+<a name="l00637"></a>00637         dma_addr_t buff_addr = req-&gt;<a class="code" href="structdwc__otg__pcd__request.html#df93c8905495816eb0327b192938a4a1">dma</a>;
+<a name="l00638"></a>00638         <span class="keywordtype">int</span> i;
+<a name="l00639"></a>00639         uint32_t txsize, off;
+<a name="l00640"></a>00640 
+<a name="l00641"></a>00641         txsize = sgval-&gt;<a class="code" href="struct__ddma__sg__buffer__setup.html#728db9bac2db62f7e7b2b9ccb0873546">wSize</a>;
+<a name="l00642"></a>00642         off = sgval-&gt;<a class="code" href="struct__ddma__sg__buffer__setup.html#5ab16a208d20dd6940ecfd3244e2b9c0">bOffset</a>;
+<a name="l00643"></a>00643 
+<a name="l00644"></a>00644 <span class="comment">//      CFI_INFO("%s: %s TXSIZE=0x%08x; OFFSET=0x%08x\n", </span>
+<a name="l00645"></a>00645 <span class="comment">//              __func__, cfiep-&gt;ep-&gt;ep.name, txsize, off);</span>
+<a name="l00646"></a>00646 
+<a name="l00647"></a>00647         <span class="keywordflow">for</span> (i = 0; i &lt; sgval-&gt;<a class="code" href="struct__ddma__sg__buffer__setup.html#6287daf5a964bf1d09e8ffca29b88748">bCount</a>; i++) {
+<a name="l00648"></a>00648                 desc-&gt;status.b.bs = <a class="code" href="dwc__otg__regs_8h.html#e6e96a79797557986256d1a1ff104ca1">BS_HOST_BUSY</a>;
+<a name="l00649"></a>00649                 desc-&gt;buf = buff_addr;
+<a name="l00650"></a>00650                 desc-&gt;status.b.l = 0;
+<a name="l00651"></a>00651                 desc-&gt;status.b.ioc = 0;
+<a name="l00652"></a>00652                 desc-&gt;status.b.sp = 0;
+<a name="l00653"></a>00653                 desc-&gt;status.b.bytes = txsize;
+<a name="l00654"></a>00654                 desc-&gt;status.b.bs = <a class="code" href="dwc__otg__regs_8h.html#c2cfc53da94087a90d21d3528b005bcf">BS_HOST_READY</a>;
+<a name="l00655"></a>00655 
+<a name="l00656"></a>00656                 <span class="comment">/* Set the next address of the buffer */</span>
+<a name="l00657"></a>00657                 buff_addr += txsize + off;
+<a name="l00658"></a>00658                 desc_last = desc;
+<a name="l00659"></a>00659                 desc++;
+<a name="l00660"></a>00660         }
+<a name="l00661"></a>00661 
+<a name="l00662"></a>00662         <span class="comment">/* Set the last, ioc and sp bits on the Last DMA Descriptor */</span>
+<a name="l00663"></a>00663         desc_last-&gt;status.b.l = 1;
+<a name="l00664"></a>00664         desc_last-&gt;status.b.ioc = 1;
+<a name="l00665"></a>00665         desc_last-&gt;status.b.sp = ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#8c6340435beba0b8c025a4677602acab">sent_zlp</a>;
+<a name="l00666"></a>00666         <span class="comment">/* Save the last DMA descriptor pointer */</span>
+<a name="l00667"></a>00667         cfiep-&gt;<a class="code" href="structcfi__ep.html#3f4e5c42f279663ee0065ffce4f44783">dma_desc_last</a> = desc_last;
+<a name="l00668"></a>00668         cfiep-&gt;<a class="code" href="structcfi__ep.html#73050a3011b918e8be6c2434db357514">desc_count</a> = sgval-&gt;<a class="code" href="struct__ddma__sg__buffer__setup.html#6287daf5a964bf1d09e8ffca29b88748">bCount</a>;
+<a name="l00669"></a>00669 }
+<a name="l00670"></a>00670 
+<a name="l00674"></a>00674 <span class="keyword">static</span> <span class="keywordtype">void</span> cfi_build_concat_descs(<span class="keyword">struct</span> <a class="code" href="structcfiobject.html">cfiobject</a> *cfi, <a class="code" href="structcfi__ep.html">cfi_ep_t</a> * cfiep,
+<a name="l00675"></a>00675                                    <a class="code" href="structdwc__otg__pcd__request.html">dwc_otg_pcd_request_t</a> * req)
+<a name="l00676"></a>00676 {
+<a name="l00677"></a>00677         <span class="keyword">struct </span><a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep</a> *ep = cfiep-&gt;<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>;
+<a name="l00678"></a>00678         <a class="code" href="struct__ddma__concat__buffer__setup.html">ddma_concat_buffer_setup_t</a> *concatval = cfiep-&gt;<a class="code" href="structcfi__ep.html#4c83b9bb5a75e6b81fbfa86b51736164">bm_concat</a>;
+<a name="l00679"></a>00679         <span class="keyword">struct </span>dwc_otg_dma_desc *desc = cfiep-&gt;<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.descs;
+<a name="l00680"></a>00680         <span class="keyword">struct </span>dwc_otg_dma_desc *desc_last = cfiep-&gt;<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.descs;
+<a name="l00681"></a>00681         dma_addr_t buff_addr = req-&gt;<a class="code" href="structdwc__otg__pcd__request.html#df93c8905495816eb0327b192938a4a1">dma</a>;
+<a name="l00682"></a>00682         <span class="keywordtype">int</span> i;
+<a name="l00683"></a>00683         uint16_t *txsize;
+<a name="l00684"></a>00684 
+<a name="l00685"></a>00685         txsize = concatval-&gt;<a class="code" href="struct__ddma__concat__buffer__setup.html#748241a5b55a514f4386498aceb1e505">wTxBytes</a>;
+<a name="l00686"></a>00686 
+<a name="l00687"></a>00687         <span class="keywordflow">for</span> (i = 0; i &lt; concatval-&gt;<a class="code" href="struct__ddma__concat__buffer__setup.html#512cdc8b5ef9053f514443b884ec4730">hdr</a>.<a class="code" href="struct__ddma__concat__buffer__setup__hdr.html#605becc1e8a681d6623343b28013b56a">bDescCount</a>; i++) {
+<a name="l00688"></a>00688                 desc-&gt;buf = buff_addr;
+<a name="l00689"></a>00689                 desc-&gt;status.b.bs = <a class="code" href="dwc__otg__regs_8h.html#e6e96a79797557986256d1a1ff104ca1">BS_HOST_BUSY</a>;
+<a name="l00690"></a>00690                 desc-&gt;status.b.l = 0;
+<a name="l00691"></a>00691                 desc-&gt;status.b.ioc = 0;
+<a name="l00692"></a>00692                 desc-&gt;status.b.sp = 0;
+<a name="l00693"></a>00693                 desc-&gt;status.b.bytes = *txsize;
+<a name="l00694"></a>00694                 desc-&gt;status.b.bs = <a class="code" href="dwc__otg__regs_8h.html#c2cfc53da94087a90d21d3528b005bcf">BS_HOST_READY</a>;
+<a name="l00695"></a>00695 
+<a name="l00696"></a>00696                 txsize++;
+<a name="l00697"></a>00697                 <span class="comment">/* Set the next address of the buffer */</span>
+<a name="l00698"></a>00698                 buff_addr += UGETW(ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#86e27843c439dd0b1d12d9bf2dc6516f">desc</a>-&gt;wMaxPacketSize);
+<a name="l00699"></a>00699                 desc_last = desc;
+<a name="l00700"></a>00700                 desc++;
+<a name="l00701"></a>00701         }
+<a name="l00702"></a>00702 
+<a name="l00703"></a>00703         <span class="comment">/* Set the last, ioc and sp bits on the Last DMA Descriptor */</span>
+<a name="l00704"></a>00704         desc_last-&gt;status.b.l = 1;
+<a name="l00705"></a>00705         desc_last-&gt;status.b.ioc = 1;
+<a name="l00706"></a>00706         desc_last-&gt;status.b.sp = ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#8c6340435beba0b8c025a4677602acab">sent_zlp</a>;
+<a name="l00707"></a>00707         cfiep-&gt;<a class="code" href="structcfi__ep.html#3f4e5c42f279663ee0065ffce4f44783">dma_desc_last</a> = desc_last;
+<a name="l00708"></a>00708         cfiep-&gt;<a class="code" href="structcfi__ep.html#73050a3011b918e8be6c2434db357514">desc_count</a> = concatval-&gt;<a class="code" href="struct__ddma__concat__buffer__setup.html#512cdc8b5ef9053f514443b884ec4730">hdr</a>.<a class="code" href="struct__ddma__concat__buffer__setup__hdr.html#605becc1e8a681d6623343b28013b56a">bDescCount</a>;
+<a name="l00709"></a>00709 }
+<a name="l00710"></a>00710 
+<a name="l00714"></a>00714 <span class="keyword">static</span> <span class="keywordtype">void</span> cfi_build_circ_descs(<span class="keyword">struct</span> <a class="code" href="structcfiobject.html">cfiobject</a> *cfi, <a class="code" href="structcfi__ep.html">cfi_ep_t</a> * cfiep,
+<a name="l00715"></a>00715                                  <a class="code" href="structdwc__otg__pcd__request.html">dwc_otg_pcd_request_t</a> * req)
+<a name="l00716"></a>00716 {
+<a name="l00717"></a>00717         <span class="comment">/* @todo: MAS - add implementation when this feature needs to be tested */</span>
+<a name="l00718"></a>00718 }
+<a name="l00719"></a>00719 
+<a name="l00723"></a>00723 <span class="keyword">static</span> <span class="keywordtype">void</span> cfi_build_align_descs(<span class="keyword">struct</span> <a class="code" href="structcfiobject.html">cfiobject</a> *cfi, <a class="code" href="structcfi__ep.html">cfi_ep_t</a> * cfiep,
+<a name="l00724"></a>00724                                   <a class="code" href="structdwc__otg__pcd__request.html">dwc_otg_pcd_request_t</a> * req)
+<a name="l00725"></a>00725 {
+<a name="l00726"></a>00726         <span class="keyword">struct </span><a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep</a> *ep = cfiep-&gt;<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>;
+<a name="l00727"></a>00727         <a class="code" href="struct__ddma__align__buffer__setup.html">ddma_align_buffer_setup_t</a> *alignval = cfiep-&gt;<a class="code" href="structcfi__ep.html#bb544b7938d0c62857fc3726988310d2">bm_align</a>;
+<a name="l00728"></a>00728         <span class="keyword">struct </span>dwc_otg_dma_desc *desc = cfiep-&gt;<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.descs;
+<a name="l00729"></a>00729         dma_addr_t buff_addr = req-&gt;<a class="code" href="structdwc__otg__pcd__request.html#df93c8905495816eb0327b192938a4a1">dma</a>;
+<a name="l00730"></a>00730 
+<a name="l00731"></a>00731         desc-&gt;status.b.bs = <a class="code" href="dwc__otg__regs_8h.html#e6e96a79797557986256d1a1ff104ca1">BS_HOST_BUSY</a>;
+<a name="l00732"></a>00732         desc-&gt;status.b.l = 1;
+<a name="l00733"></a>00733         desc-&gt;status.b.ioc = 1;
+<a name="l00734"></a>00734         desc-&gt;status.b.sp = ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#8c6340435beba0b8c025a4677602acab">sent_zlp</a>;
+<a name="l00735"></a>00735         desc-&gt;status.b.bytes = req-&gt;<a class="code" href="structdwc__otg__pcd__request.html#3dd3fcc889bf220b048023e8b05fab61">length</a>;
+<a name="l00736"></a>00736         <span class="comment">/* Adjust the buffer alignment */</span>
+<a name="l00737"></a>00737         desc-&gt;buf = (buff_addr + alignval-&gt;<a class="code" href="struct__ddma__align__buffer__setup.html#1cc0ba7e2c2a435cce1d502732ce07a1">bAlign</a>);
+<a name="l00738"></a>00738         desc-&gt;status.b.bs = <a class="code" href="dwc__otg__regs_8h.html#c2cfc53da94087a90d21d3528b005bcf">BS_HOST_READY</a>;
+<a name="l00739"></a>00739         cfiep-&gt;<a class="code" href="structcfi__ep.html#3f4e5c42f279663ee0065ffce4f44783">dma_desc_last</a> = desc;
+<a name="l00740"></a>00740         cfiep-&gt;<a class="code" href="structcfi__ep.html#73050a3011b918e8be6c2434db357514">desc_count</a> = 1;
+<a name="l00741"></a>00741 }
+<a name="l00742"></a>00742 
+<a name="l00747"></a>00747 <span class="keyword">static</span> <span class="keywordtype">void</span> cfi_build_descriptors(<span class="keyword">struct</span> <a class="code" href="structcfiobject.html">cfiobject</a> *cfi,
+<a name="l00748"></a>00748                                   <span class="keyword">struct</span> <a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd</a> *pcd,
+<a name="l00749"></a>00749                                   <span class="keyword">struct</span> <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep</a> *ep,
+<a name="l00750"></a>00750                                   <a class="code" href="structdwc__otg__pcd__request.html">dwc_otg_pcd_request_t</a> * req)
+<a name="l00751"></a>00751 {
+<a name="l00752"></a>00752         <a class="code" href="structcfi__ep.html">cfi_ep_t</a> *cfiep;
+<a name="l00753"></a>00753 
+<a name="l00754"></a>00754         <span class="comment">/* Get the cfiep by the dwc_otg_pcd_ep */</span>
+<a name="l00755"></a>00755         cfiep = <a class="code" href="dwc__otg__cfi_8h.html#c21284d5adf03032d094a36babf9b1e5">get_cfi_ep_by_pcd_ep</a>(cfi, ep);
+<a name="l00756"></a>00756         <span class="keywordflow">if</span> (NULL == cfiep) {
+<a name="l00757"></a>00757                 <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>(<span class="stringliteral">"%s: Unable to find a matching active endpoint\n"</span>,
+<a name="l00758"></a>00758                          __func__);
+<a name="l00759"></a>00759                 <span class="keywordflow">return</span>;
+<a name="l00760"></a>00760         }
+<a name="l00761"></a>00761 
+<a name="l00762"></a>00762         cfiep-&gt;<a class="code" href="structcfi__ep.html#f85903cb9e179124e42d98d557098011">xfer_len</a> = req-&gt;<a class="code" href="structdwc__otg__pcd__request.html#3dd3fcc889bf220b048023e8b05fab61">length</a>;
+<a name="l00763"></a>00763 
+<a name="l00764"></a>00764         <span class="comment">/* Iterate through all the DMA descriptors */</span>
+<a name="l00765"></a>00765         <span class="keywordflow">switch</span> (cfiep-&gt;<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.buff_mode) {
+<a name="l00766"></a>00766         <span class="keywordflow">case</span> BM_SG:
+<a name="l00767"></a>00767                 cfi_build_sg_descs(cfi, cfiep, req);
+<a name="l00768"></a>00768                 <span class="keywordflow">break</span>;
+<a name="l00769"></a>00769 
+<a name="l00770"></a>00770         <span class="keywordflow">case</span> BM_CONCAT:
+<a name="l00771"></a>00771                 cfi_build_concat_descs(cfi, cfiep, req);
+<a name="l00772"></a>00772                 <span class="keywordflow">break</span>;
+<a name="l00773"></a>00773 
+<a name="l00774"></a>00774         <span class="keywordflow">case</span> BM_CIRCULAR:
+<a name="l00775"></a>00775                 cfi_build_circ_descs(cfi, cfiep, req);
+<a name="l00776"></a>00776                 <span class="keywordflow">break</span>;
+<a name="l00777"></a>00777 
+<a name="l00778"></a>00778         <span class="keywordflow">case</span> BM_ALIGN:
+<a name="l00779"></a>00779                 cfi_build_align_descs(cfi, cfiep, req);
+<a name="l00780"></a>00780                 <span class="keywordflow">break</span>;
+<a name="l00781"></a>00781 
+<a name="l00782"></a>00782         <span class="keywordflow">default</span>:
+<a name="l00783"></a>00783                 <span class="keywordflow">break</span>;
+<a name="l00784"></a>00784         }
+<a name="l00785"></a>00785 }
+<a name="l00786"></a>00786 
+<a name="l00790"></a>00790 <span class="keyword">static</span> <span class="keywordtype">void</span> *cfi_ep_alloc_buf(<span class="keyword">struct</span> <a class="code" href="structcfiobject.html">cfiobject</a> *cfi, <span class="keyword">struct</span> <a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd</a> *pcd,
+<a name="l00791"></a>00791                               <span class="keyword">struct</span> <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep</a> *ep, dma_addr_t * dma,
+<a name="l00792"></a>00792                               <span class="keywordtype">unsigned</span> size, gfp_t flags)
+<a name="l00793"></a>00793 {
+<a name="l00794"></a>00794         <span class="keywordflow">return</span> dwc_dma_alloc(size, dma);
+<a name="l00795"></a>00795 }
+<a name="l00796"></a>00796 
+<a name="l00800"></a>00800 <span class="keywordtype">int</span> init_cfi(<a class="code" href="structcfiobject.html">cfiobject_t</a> * cfiobj)
+<a name="l00801"></a>00801 {
+<a name="l00802"></a>00802         <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>(<span class="stringliteral">"%s\n"</span>, __func__);
+<a name="l00803"></a>00803 
+<a name="l00804"></a>00804         <span class="comment">/* Allocate a buffer for IN XFERs */</span>
+<a name="l00805"></a>00805         cfiobj-&gt;<a class="code" href="structcfiobject.html#f6548b2b8fbab90656c22eb5ca857643">buf_in</a>.<a class="code" href="structcfi__dma__buff.html#474851b3123373b8b30fa3637eb81b5b">buf</a> =
+<a name="l00806"></a>00806             dwc_dma_alloc(<a class="code" href="dwc__otg__cfi_8h.html#34582b9ef366f4c0e8ea24aa2388e829">CFI_IN_BUF_LEN</a>, &amp;cfiobj-&gt;<a class="code" href="structcfiobject.html#f6548b2b8fbab90656c22eb5ca857643">buf_in</a>.<a class="code" href="structcfi__dma__buff.html#549d40f7e33056fc5a99d51d00714d97">addr</a>);
+<a name="l00807"></a>00807         <span class="keywordflow">if</span> (NULL == cfiobj-&gt;<a class="code" href="structcfiobject.html#f6548b2b8fbab90656c22eb5ca857643">buf_in</a>.<a class="code" href="structcfi__dma__buff.html#474851b3123373b8b30fa3637eb81b5b">buf</a>) {
+<a name="l00808"></a>00808                 <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>(<span class="stringliteral">"Unable to allocate buffer for INs\n"</span>);
+<a name="l00809"></a>00809                 <span class="keywordflow">return</span> -DWC_E_NO_MEMORY;
+<a name="l00810"></a>00810         }
+<a name="l00811"></a>00811 
+<a name="l00812"></a>00812         <span class="comment">/* Allocate a buffer for OUT XFERs */</span>
+<a name="l00813"></a>00813         cfiobj-&gt;<a class="code" href="structcfiobject.html#adaa1cd0f88e639251f8dfbd65da7935">buf_out</a>.<a class="code" href="structcfi__dma__buff.html#474851b3123373b8b30fa3637eb81b5b">buf</a> =
+<a name="l00814"></a>00814             dwc_dma_alloc(<a class="code" href="dwc__otg__cfi_8h.html#739556affb10ce8a44b362b8ffa41a40">CFI_OUT_BUF_LEN</a>, &amp;cfiobj-&gt;<a class="code" href="structcfiobject.html#adaa1cd0f88e639251f8dfbd65da7935">buf_out</a>.<a class="code" href="structcfi__dma__buff.html#549d40f7e33056fc5a99d51d00714d97">addr</a>);
+<a name="l00815"></a>00815         <span class="keywordflow">if</span> (NULL == cfiobj-&gt;<a class="code" href="structcfiobject.html#adaa1cd0f88e639251f8dfbd65da7935">buf_out</a>.<a class="code" href="structcfi__dma__buff.html#474851b3123373b8b30fa3637eb81b5b">buf</a>) {
+<a name="l00816"></a>00816                 <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>(<span class="stringliteral">"Unable to allocate buffer for OUT\n"</span>);
+<a name="l00817"></a>00817                 <span class="keywordflow">return</span> -DWC_E_NO_MEMORY;
+<a name="l00818"></a>00818         }
+<a name="l00819"></a>00819 
+<a name="l00820"></a>00820         <span class="comment">/* Initialize the callback function pointers */</span>
+<a name="l00821"></a>00821         cfiobj-&gt;<a class="code" href="structcfiobject.html#324b7481af9ba7a97233b162bbe8301a">ops</a>.<a class="code" href="structcfi__ops.html#132fd4871260083bbd9945e121dc1819">release</a> = cfi_release;
+<a name="l00822"></a>00822         cfiobj-&gt;<a class="code" href="structcfiobject.html#324b7481af9ba7a97233b162bbe8301a">ops</a>.<a class="code" href="structcfi__ops.html#1da60799de5a3a4ab53c63e1778e08af">ep_enable</a> = cfi_ep_enable;
+<a name="l00823"></a>00823         cfiobj-&gt;<a class="code" href="structcfiobject.html#324b7481af9ba7a97233b162bbe8301a">ops</a>.<a class="code" href="structcfi__ops.html#a46d61a3e78632ab9ca2787b1025fee7">ctrl_write_complete</a> = cfi_ctrl_write_complete;
+<a name="l00824"></a>00824         cfiobj-&gt;<a class="code" href="structcfiobject.html#324b7481af9ba7a97233b162bbe8301a">ops</a>.<a class="code" href="structcfi__ops.html#a3e763247b8fbedc46ddfa624408ab11">build_descriptors</a> = cfi_build_descriptors;
+<a name="l00825"></a>00825         cfiobj-&gt;<a class="code" href="structcfiobject.html#324b7481af9ba7a97233b162bbe8301a">ops</a>.<a class="code" href="structcfi__ops.html#0f57d061a80c9e04eeff9c960637595f">ep_alloc_buf</a> = cfi_ep_alloc_buf;
+<a name="l00826"></a>00826 
+<a name="l00827"></a>00827         <span class="comment">/* Initialize the list of active endpoints in the CFI object */</span>
+<a name="l00828"></a>00828         DWC_LIST_INIT(&amp;cfiobj-&gt;<a class="code" href="structcfiobject.html#82805f011abf3deace7faa159729229a">active_eps</a>);
+<a name="l00829"></a>00829 
+<a name="l00830"></a>00830         <span class="keywordflow">return</span> 0;
+<a name="l00831"></a>00831 }
+<a name="l00832"></a>00832 
+<a name="l00838"></a>00838 <span class="keyword">static</span> <span class="keywordtype">int</span> cfi_get_feature_value(uint8_t * buf, uint16_t buflen,
+<a name="l00839"></a>00839                                  <span class="keyword">struct</span> <a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd</a> *pcd,
+<a name="l00840"></a>00840                                  <span class="keyword">struct</span> <a class="code" href="structcfi__usb__ctrlrequest.html">cfi_usb_ctrlrequest</a> *ctrl_req)
+<a name="l00841"></a>00841 {
+<a name="l00842"></a>00842         <span class="keywordtype">int</span> retval = -DWC_E_NOT_SUPPORTED;
+<a name="l00843"></a>00843         <span class="keyword">struct </span><a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if</a> *coreif = <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd);
+<a name="l00844"></a>00844         uint16_t dfifo, rxfifo, txfifo;
+<a name="l00845"></a>00845 
+<a name="l00846"></a>00846         <span class="keywordflow">switch</span> (ctrl_req-&gt;<a class="code" href="structcfi__usb__ctrlrequest.html#984c95bd61e8d1120cd935bcbc5d7134">wIndex</a>) {
+<a name="l00847"></a>00847                 <span class="comment">/* Whether the DDMA is enabled or not */</span>
+<a name="l00848"></a>00848         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__cfi_8h.html#0e196868939f6bbf0d157868bfc90208">FT_ID_DMA_MODE</a>:
+<a name="l00849"></a>00849                 *buf = (coreif-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a> &amp;&amp; coreif-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a>) ? 1 : 0;
+<a name="l00850"></a>00850                 retval = 1;
+<a name="l00851"></a>00851                 <span class="keywordflow">break</span>;
+<a name="l00852"></a>00852 
+<a name="l00853"></a>00853         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__cfi_8h.html#98840b45640251bfafa3481260aef889">FT_ID_DMA_BUFFER_SETUP</a>:
+<a name="l00854"></a>00854                 retval = cfi_ep_get_sg_val(buf, pcd, ctrl_req);
+<a name="l00855"></a>00855                 <span class="keywordflow">break</span>;
+<a name="l00856"></a>00856 
+<a name="l00857"></a>00857         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__cfi_8h.html#9335284cd4dae01f4bc0da7cb89d5ef4">FT_ID_DMA_BUFF_ALIGN</a>:
+<a name="l00858"></a>00858                 retval = cfi_ep_get_align_val(buf, pcd, ctrl_req);
+<a name="l00859"></a>00859                 <span class="keywordflow">break</span>;
+<a name="l00860"></a>00860 
+<a name="l00861"></a>00861         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__cfi_8h.html#779a11db5843dd058581d93c8232bd7c">FT_ID_DMA_CONCAT_SETUP</a>:
+<a name="l00862"></a>00862                 retval = cfi_ep_get_concat_val(buf, pcd, ctrl_req);
+<a name="l00863"></a>00863                 <span class="keywordflow">break</span>;
+<a name="l00864"></a>00864 
+<a name="l00865"></a>00865         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__cfi_8h.html#8db5bfce321e02d42b742e9deedfa665">FT_ID_DMA_CIRCULAR</a>:
+<a name="l00866"></a>00866                 <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>(<span class="stringliteral">"GetFeature value (FT_ID_DMA_CIRCULAR)\n"</span>);
+<a name="l00867"></a>00867                 <span class="keywordflow">break</span>;
+<a name="l00868"></a>00868 
+<a name="l00869"></a>00869         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__cfi_8h.html#bcc99a9e5a0b15b4212d88bd9c610647">FT_ID_THRESHOLD_SETUP</a>:
+<a name="l00870"></a>00870                 <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>(<span class="stringliteral">"GetFeature value (FT_ID_THRESHOLD_SETUP)\n"</span>);
+<a name="l00871"></a>00871                 <span class="keywordflow">break</span>;
+<a name="l00872"></a>00872 
+<a name="l00873"></a>00873         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__cfi_8h.html#54b879727edcb06acdd11968ec60d249">FT_ID_DFIFO_DEPTH</a>:
+<a name="l00874"></a>00874                 dfifo = get_dfifo_size(coreif);
+<a name="l00875"></a>00875                 *((uint16_t *) buf) = dfifo;
+<a name="l00876"></a>00876                 retval = <span class="keyword">sizeof</span>(uint16_t);
+<a name="l00877"></a>00877                 <span class="keywordflow">break</span>;
+<a name="l00878"></a>00878 
+<a name="l00879"></a>00879         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__cfi_8h.html#a3a67b679a59c5279370bbf69f114cb6">FT_ID_TX_FIFO_DEPTH</a>:
+<a name="l00880"></a>00880                 retval = get_txfifo_size(pcd, ctrl_req-&gt;<a class="code" href="structcfi__usb__ctrlrequest.html#2f236bbf9450df1a3b5204c4570d883f">wValue</a>);
+<a name="l00881"></a>00881                 <span class="keywordflow">if</span> (retval &gt;= 0) {
+<a name="l00882"></a>00882                         txfifo = retval;
+<a name="l00883"></a>00883                         *((uint16_t *) buf) = txfifo;
+<a name="l00884"></a>00884                         retval = <span class="keyword">sizeof</span>(uint16_t);
+<a name="l00885"></a>00885                 }
+<a name="l00886"></a>00886                 <span class="keywordflow">break</span>;
+<a name="l00887"></a>00887 
+<a name="l00888"></a>00888         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__cfi_8h.html#42b7c98c105de1f9399786a3419e7e20">FT_ID_RX_FIFO_DEPTH</a>:
+<a name="l00889"></a>00889                 retval = get_rxfifo_size(coreif, ctrl_req-&gt;<a class="code" href="structcfi__usb__ctrlrequest.html#2f236bbf9450df1a3b5204c4570d883f">wValue</a>);
+<a name="l00890"></a>00890                 <span class="keywordflow">if</span> (retval &gt;= 0) {
+<a name="l00891"></a>00891                         rxfifo = retval;
+<a name="l00892"></a>00892                         *((uint16_t *) buf) = rxfifo;
+<a name="l00893"></a>00893                         retval = <span class="keyword">sizeof</span>(uint16_t);
+<a name="l00894"></a>00894                 }
+<a name="l00895"></a>00895                 <span class="keywordflow">break</span>;
+<a name="l00896"></a>00896         }
+<a name="l00897"></a>00897 
+<a name="l00898"></a>00898         <span class="keywordflow">return</span> retval;
+<a name="l00899"></a>00899 }
+<a name="l00900"></a>00900 
+<a name="l00904"></a>00904 <span class="keyword">static</span> <span class="keywordtype">int</span> cfi_reset_sg_val(<a class="code" href="structcfi__ep.html">cfi_ep_t</a> * cfiep)
+<a name="l00905"></a>00905 {
+<a name="l00906"></a>00906         dwc_memset(cfiep-&gt;<a class="code" href="structcfi__ep.html#4010b0f12bf1cd37a2c0bf06b392570a">bm_sg</a>, 0, <span class="keyword">sizeof</span>(<a class="code" href="struct__ddma__sg__buffer__setup.html">ddma_sg_buffer_setup_t</a>));
+<a name="l00907"></a>00907         <span class="keywordflow">return</span> 0;
+<a name="l00908"></a>00908 }
+<a name="l00909"></a>00909 
+<a name="l00913"></a>00913 <span class="keyword">static</span> <span class="keywordtype">int</span> cfi_reset_align_val(<a class="code" href="structcfi__ep.html">cfi_ep_t</a> * cfiep)
+<a name="l00914"></a>00914 {
+<a name="l00915"></a>00915         dwc_memset(cfiep-&gt;<a class="code" href="structcfi__ep.html#4010b0f12bf1cd37a2c0bf06b392570a">bm_sg</a>, 0, <span class="keyword">sizeof</span>(<a class="code" href="struct__ddma__sg__buffer__setup.html">ddma_sg_buffer_setup_t</a>));
+<a name="l00916"></a>00916         <span class="keywordflow">return</span> 0;
+<a name="l00917"></a>00917 }
+<a name="l00918"></a>00918 
+<a name="l00924"></a>00924 <span class="keyword">static</span> <span class="keywordtype">int</span> cfi_reset_concat_val(<a class="code" href="structcfi__ep.html">cfi_ep_t</a> * cfiep)
+<a name="l00925"></a>00925 {
+<a name="l00926"></a>00926         <span class="comment">/* First we need to free the wTxBytes field */</span>
+<a name="l00927"></a>00927         <span class="keywordflow">if</span> (cfiep-&gt;<a class="code" href="structcfi__ep.html#4c83b9bb5a75e6b81fbfa86b51736164">bm_concat</a>-&gt;<a class="code" href="struct__ddma__concat__buffer__setup.html#748241a5b55a514f4386498aceb1e505">wTxBytes</a>) {
+<a name="l00928"></a>00928                 dwc_free(cfiep-&gt;<a class="code" href="structcfi__ep.html#4c83b9bb5a75e6b81fbfa86b51736164">bm_concat</a>-&gt;<a class="code" href="struct__ddma__concat__buffer__setup.html#748241a5b55a514f4386498aceb1e505">wTxBytes</a>);
+<a name="l00929"></a>00929                 cfiep-&gt;<a class="code" href="structcfi__ep.html#4c83b9bb5a75e6b81fbfa86b51736164">bm_concat</a>-&gt;<a class="code" href="struct__ddma__concat__buffer__setup.html#748241a5b55a514f4386498aceb1e505">wTxBytes</a> = NULL;
+<a name="l00930"></a>00930         }
+<a name="l00931"></a>00931 
+<a name="l00932"></a>00932         dwc_memset(cfiep-&gt;<a class="code" href="structcfi__ep.html#4c83b9bb5a75e6b81fbfa86b51736164">bm_concat</a>, 0, <span class="keyword">sizeof</span>(<a class="code" href="struct__ddma__concat__buffer__setup.html">ddma_concat_buffer_setup_t</a>));
+<a name="l00933"></a>00933         <span class="keywordflow">return</span> 0;
+<a name="l00934"></a>00934 }
+<a name="l00935"></a>00935 
+<a name="l00939"></a>00939 <span class="keyword">static</span> <span class="keywordtype">int</span> cfi_ep_reset_all_setup_vals(<a class="code" href="structcfi__ep.html">cfi_ep_t</a> * cfiep)
+<a name="l00940"></a>00940 {
+<a name="l00941"></a>00941         cfi_reset_sg_val(cfiep);
+<a name="l00942"></a>00942         cfi_reset_align_val(cfiep);
+<a name="l00943"></a>00943         cfi_reset_concat_val(cfiep);
+<a name="l00944"></a>00944         <span class="keywordflow">return</span> 0;
+<a name="l00945"></a>00945 }
+<a name="l00946"></a>00946 
+<a name="l00947"></a>00947 <span class="keyword">static</span> <span class="keywordtype">int</span> cfi_handle_reset_fifo_val(<span class="keyword">struct</span> <a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd</a> *pcd, uint8_t ep_addr,
+<a name="l00948"></a>00948                                      uint8_t rx_rst, uint8_t tx_rst)
+<a name="l00949"></a>00949 {
+<a name="l00950"></a>00950         <span class="keywordtype">int</span> retval = -DWC_E_INVALID;
+<a name="l00951"></a>00951         uint16_t tx_siz[15];
+<a name="l00952"></a>00952         uint16_t rx_siz = 0;
+<a name="l00953"></a>00953         <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *ep = NULL;
+<a name="l00954"></a>00954         <a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if = <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd);
+<a name="l00955"></a>00955         <a class="code" href="structdwc__otg__core__params.html">dwc_otg_core_params_t</a> *params = <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;core_params;
+<a name="l00956"></a>00956 
+<a name="l00957"></a>00957         <span class="keywordflow">if</span> (rx_rst) {
+<a name="l00958"></a>00958                 rx_siz = params-&gt;<a class="code" href="structdwc__otg__core__params.html#24ea6f9329f64ac0ad2d31dafe0d1d8c">dev_rx_fifo_size</a>;
+<a name="l00959"></a>00959                 params-&gt;<a class="code" href="structdwc__otg__core__params.html#24ea6f9329f64ac0ad2d31dafe0d1d8c">dev_rx_fifo_size</a> = <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;init_rxfsiz;
+<a name="l00960"></a>00960         }
+<a name="l00961"></a>00961 
+<a name="l00962"></a>00962         <span class="keywordflow">if</span> (tx_rst) {
+<a name="l00963"></a>00963                 <span class="keywordflow">if</span> (ep_addr == 0) {
+<a name="l00964"></a>00964                         <span class="keywordtype">int</span> i;
+<a name="l00965"></a>00965 
+<a name="l00966"></a>00966                         <span class="keywordflow">for</span> (i = 0; i &lt; core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#9c1394f3c46adde2fa7be79bf0237f9b">hwcfg4</a>.<a class="code" href="unionhwcfg4__data.html#9fb9175668e2381c568c5adbf6e5225d">b</a>.<a class="code" href="unionhwcfg4__data.html#753b321350388c5e1307802ff968f9a8">num_in_eps</a>; i++) {
+<a name="l00967"></a>00967                                 tx_siz[i] =
+<a name="l00968"></a>00968                                     core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#6e0c5d06467fbf3458f11f7eb8153a8b">dev_tx_fifo_size</a>[i];
+<a name="l00969"></a>00969                                 core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#6e0c5d06467fbf3458f11f7eb8153a8b">dev_tx_fifo_size</a>[i] =
+<a name="l00970"></a>00970                                     core_if-&gt;init_txfsiz[i];
+<a name="l00971"></a>00971                         }
+<a name="l00972"></a>00972                 } <span class="keywordflow">else</span> {
+<a name="l00973"></a>00973 
+<a name="l00974"></a>00974                         ep = <a class="code" href="dwc__otg__pcd__intr_8c.html#3c351d7f51d6242296d6ea3bb1a9775c">get_ep_by_addr</a>(pcd, ep_addr);
+<a name="l00975"></a>00975 
+<a name="l00976"></a>00976                         <span class="keywordflow">if</span> (NULL == ep) {
+<a name="l00977"></a>00977                                 <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>
+<a name="l00978"></a>00978                                     (<span class="stringliteral">"%s: Unable to get the endpoint addr=0x%02x\n"</span>,
+<a name="l00979"></a>00979                                      __func__, ep_addr);
+<a name="l00980"></a>00980                                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l00981"></a>00981                         }
+<a name="l00982"></a>00982 
+<a name="l00983"></a>00983                         tx_siz[0] =
+<a name="l00984"></a>00984                             params-&gt;<a class="code" href="structdwc__otg__core__params.html#6e0c5d06467fbf3458f11f7eb8153a8b">dev_tx_fifo_size</a>[ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#ffa14f48094778143353b845b5d238cd">tx_fifo_num</a> -
+<a name="l00985"></a>00985                                                      1];
+<a name="l00986"></a>00986                         params-&gt;<a class="code" href="structdwc__otg__core__params.html#6e0c5d06467fbf3458f11f7eb8153a8b">dev_tx_fifo_size</a>[ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#ffa14f48094778143353b845b5d238cd">tx_fifo_num</a> - 1] =
+<a name="l00987"></a>00987                             <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;init_txfsiz[ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.
+<a name="l00988"></a>00988                                                           tx_fifo_num - 1];
+<a name="l00989"></a>00989                 }
+<a name="l00990"></a>00990         }
+<a name="l00991"></a>00991 
+<a name="l00992"></a>00992         <span class="keywordflow">if</span> (resize_fifos(<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd))) {
+<a name="l00993"></a>00993                 retval = 0;
+<a name="l00994"></a>00994         } <span class="keywordflow">else</span> {
+<a name="l00995"></a>00995                 <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>
+<a name="l00996"></a>00996                     (<span class="stringliteral">"%s: Error resetting the feature Reset All(FIFO size)\n"</span>,
+<a name="l00997"></a>00997                      __func__);
+<a name="l00998"></a>00998                 <span class="keywordflow">if</span> (rx_rst) {
+<a name="l00999"></a>00999                         params-&gt;<a class="code" href="structdwc__otg__core__params.html#24ea6f9329f64ac0ad2d31dafe0d1d8c">dev_rx_fifo_size</a> = rx_siz;
+<a name="l01000"></a>01000                 }
+<a name="l01001"></a>01001 
+<a name="l01002"></a>01002                 <span class="keywordflow">if</span> (tx_rst) {
+<a name="l01003"></a>01003                         <span class="keywordflow">if</span> (ep_addr == 0) {
+<a name="l01004"></a>01004                                 <span class="keywordtype">int</span> i;
+<a name="l01005"></a>01005                                 <span class="keywordflow">for</span> (i = 0; i &lt; core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#9c1394f3c46adde2fa7be79bf0237f9b">hwcfg4</a>.<a class="code" href="unionhwcfg4__data.html#9fb9175668e2381c568c5adbf6e5225d">b</a>.<a class="code" href="unionhwcfg4__data.html#753b321350388c5e1307802ff968f9a8">num_in_eps</a>;
+<a name="l01006"></a>01006                                      i++) {
+<a name="l01007"></a>01007                                         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;
+<a name="l01008"></a>01008                                             dev_tx_fifo_size[i] = tx_siz[i];
+<a name="l01009"></a>01009                                 }
+<a name="l01010"></a>01010                         } <span class="keywordflow">else</span> {
+<a name="l01011"></a>01011                                 params-&gt;<a class="code" href="structdwc__otg__core__params.html#6e0c5d06467fbf3458f11f7eb8153a8b">dev_tx_fifo_size</a>[ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.
+<a name="l01012"></a>01012                                                          tx_fifo_num - 1] =
+<a name="l01013"></a>01013                                     tx_siz[0];
+<a name="l01014"></a>01014                         }
+<a name="l01015"></a>01015                 }
+<a name="l01016"></a>01016                 retval = -DWC_E_INVALID;
+<a name="l01017"></a>01017         }
+<a name="l01018"></a>01018         <span class="keywordflow">return</span> retval;
+<a name="l01019"></a>01019 }
+<a name="l01020"></a>01020 
+<a name="l01021"></a>01021 <span class="keyword">static</span> <span class="keywordtype">int</span> cfi_handle_reset_all(<span class="keyword">struct</span> <a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd</a> *pcd, uint8_t addr)
+<a name="l01022"></a>01022 {
+<a name="l01023"></a>01023         <span class="keywordtype">int</span> retval = 0;
+<a name="l01024"></a>01024         <a class="code" href="structcfi__ep.html">cfi_ep_t</a> *cfiep;
+<a name="l01025"></a>01025         <a class="code" href="structcfiobject.html">cfiobject_t</a> *cfi = pcd-&gt;cfi;
+<a name="l01026"></a>01026         dwc_list_link_t *tmp;
+<a name="l01027"></a>01027 
+<a name="l01028"></a>01028         retval = cfi_handle_reset_fifo_val(pcd, addr, 1, 1);
+<a name="l01029"></a>01029         <span class="keywordflow">if</span> (retval &lt; 0) {
+<a name="l01030"></a>01030                 <span class="keywordflow">return</span> retval;
+<a name="l01031"></a>01031         }
+<a name="l01032"></a>01032 
+<a name="l01033"></a>01033         <span class="comment">/* If the EP address is known then reset the features for only that EP */</span>
+<a name="l01034"></a>01034         <span class="keywordflow">if</span> (addr) {
+<a name="l01035"></a>01035                 cfiep = <a class="code" href="dwc__otg__cfi_8h.html#5ece1e51b8534a5cc9a7dd5115bb01ca">get_cfi_ep_by_addr</a>(pcd-&gt;cfi, addr);
+<a name="l01036"></a>01036                 <span class="keywordflow">if</span> (NULL == cfiep) {
+<a name="l01037"></a>01037                         <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>(<span class="stringliteral">"%s: Error getting the EP address 0x%02x\n"</span>,
+<a name="l01038"></a>01038                                  __func__, addr);
+<a name="l01039"></a>01039                         <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l01040"></a>01040                 }
+<a name="l01041"></a>01041                 retval = cfi_ep_reset_all_setup_vals(cfiep);
+<a name="l01042"></a>01042                 cfiep-&gt;<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.buff_mode = BM_STANDARD;
+<a name="l01043"></a>01043         }
+<a name="l01044"></a>01044         <span class="comment">/* Otherwise (wValue == 0), reset all features of all EP's */</span>
+<a name="l01045"></a>01045         <span class="keywordflow">else</span> {
+<a name="l01046"></a>01046                 <span class="comment">/* Traverse all the active EP's and reset the feature(s) value(s) */</span>
+<a name="l01047"></a>01047                 <span class="comment">//list_for_each_entry(cfiep, &amp;cfi-&gt;active_eps, lh) {</span>
+<a name="l01048"></a>01048                 DWC_LIST_FOREACH(tmp, &amp;cfi-&gt;<a class="code" href="structcfiobject.html#82805f011abf3deace7faa159729229a">active_eps</a>) {
+<a name="l01049"></a>01049                         cfiep = DWC_LIST_ENTRY(tmp, <span class="keyword">struct</span> <a class="code" href="structcfi__ep.html">cfi_ep</a>, lh);
+<a name="l01050"></a>01050                         retval = cfi_ep_reset_all_setup_vals(cfiep);
+<a name="l01051"></a>01051                         cfiep-&gt;<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.buff_mode = BM_STANDARD;
+<a name="l01052"></a>01052                         <span class="keywordflow">if</span> (retval &lt; 0) {
+<a name="l01053"></a>01053                                 <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>
+<a name="l01054"></a>01054                                     (<span class="stringliteral">"%s: Error resetting the feature Reset All\n"</span>,
+<a name="l01055"></a>01055                                      __func__);
+<a name="l01056"></a>01056                                 <span class="keywordflow">return</span> retval;
+<a name="l01057"></a>01057                         }
+<a name="l01058"></a>01058                 }
+<a name="l01059"></a>01059         }
+<a name="l01060"></a>01060         <span class="keywordflow">return</span> retval;
+<a name="l01061"></a>01061 }
+<a name="l01062"></a>01062 
+<a name="l01063"></a>01063 <span class="keyword">static</span> <span class="keywordtype">int</span> cfi_handle_reset_dma_buff_setup(<span class="keyword">struct</span> <a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd</a> *pcd,
+<a name="l01064"></a>01064                                            uint8_t addr)
+<a name="l01065"></a>01065 {
+<a name="l01066"></a>01066         <span class="keywordtype">int</span> retval = 0;
+<a name="l01067"></a>01067         <a class="code" href="structcfi__ep.html">cfi_ep_t</a> *cfiep;
+<a name="l01068"></a>01068         <a class="code" href="structcfiobject.html">cfiobject_t</a> *cfi = pcd-&gt;cfi;
+<a name="l01069"></a>01069         dwc_list_link_t *tmp;
+<a name="l01070"></a>01070 
+<a name="l01071"></a>01071         <span class="comment">/* If the EP address is known then reset the features for only that EP */</span>
+<a name="l01072"></a>01072         <span class="keywordflow">if</span> (addr) {
+<a name="l01073"></a>01073                 cfiep = <a class="code" href="dwc__otg__cfi_8h.html#5ece1e51b8534a5cc9a7dd5115bb01ca">get_cfi_ep_by_addr</a>(pcd-&gt;cfi, addr);
+<a name="l01074"></a>01074                 <span class="keywordflow">if</span> (NULL == cfiep) {
+<a name="l01075"></a>01075                         <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>(<span class="stringliteral">"%s: Error getting the EP address 0x%02x\n"</span>,
+<a name="l01076"></a>01076                                  __func__, addr);
+<a name="l01077"></a>01077                         <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l01078"></a>01078                 }
+<a name="l01079"></a>01079                 retval = cfi_reset_sg_val(cfiep);
+<a name="l01080"></a>01080         }
+<a name="l01081"></a>01081         <span class="comment">/* Otherwise (wValue == 0), reset all features of all EP's */</span>
+<a name="l01082"></a>01082         <span class="keywordflow">else</span> {
+<a name="l01083"></a>01083                 <span class="comment">/* Traverse all the active EP's and reset the feature(s) value(s) */</span>
+<a name="l01084"></a>01084                 <span class="comment">//list_for_each_entry(cfiep, &amp;cfi-&gt;active_eps, lh) {</span>
+<a name="l01085"></a>01085                 DWC_LIST_FOREACH(tmp, &amp;cfi-&gt;<a class="code" href="structcfiobject.html#82805f011abf3deace7faa159729229a">active_eps</a>) {
+<a name="l01086"></a>01086                         cfiep = DWC_LIST_ENTRY(tmp, <span class="keyword">struct</span> <a class="code" href="structcfi__ep.html">cfi_ep</a>, lh);
+<a name="l01087"></a>01087                         retval = cfi_reset_sg_val(cfiep);
+<a name="l01088"></a>01088                         <span class="keywordflow">if</span> (retval &lt; 0) {
+<a name="l01089"></a>01089                                 <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>
+<a name="l01090"></a>01090                                     (<span class="stringliteral">"%s: Error resetting the feature Buffer Setup\n"</span>,
+<a name="l01091"></a>01091                                      __func__);
+<a name="l01092"></a>01092                                 <span class="keywordflow">return</span> retval;
+<a name="l01093"></a>01093                         }
+<a name="l01094"></a>01094                 }
+<a name="l01095"></a>01095         }
+<a name="l01096"></a>01096         <span class="keywordflow">return</span> retval;
+<a name="l01097"></a>01097 }
+<a name="l01098"></a>01098 
+<a name="l01099"></a>01099 <span class="keyword">static</span> <span class="keywordtype">int</span> cfi_handle_reset_concat_val(<span class="keyword">struct</span> <a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd</a> *pcd, uint8_t addr)
+<a name="l01100"></a>01100 {
+<a name="l01101"></a>01101         <span class="keywordtype">int</span> retval = 0;
+<a name="l01102"></a>01102         <a class="code" href="structcfi__ep.html">cfi_ep_t</a> *cfiep;
+<a name="l01103"></a>01103         <a class="code" href="structcfiobject.html">cfiobject_t</a> *cfi = pcd-&gt;cfi;
+<a name="l01104"></a>01104         dwc_list_link_t *tmp;
+<a name="l01105"></a>01105 
+<a name="l01106"></a>01106         <span class="comment">/* If the EP address is known then reset the features for only that EP */</span>
+<a name="l01107"></a>01107         <span class="keywordflow">if</span> (addr) {
+<a name="l01108"></a>01108                 cfiep = <a class="code" href="dwc__otg__cfi_8h.html#5ece1e51b8534a5cc9a7dd5115bb01ca">get_cfi_ep_by_addr</a>(pcd-&gt;cfi, addr);
+<a name="l01109"></a>01109                 <span class="keywordflow">if</span> (NULL == cfiep) {
+<a name="l01110"></a>01110                         <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>(<span class="stringliteral">"%s: Error getting the EP address 0x%02x\n"</span>,
+<a name="l01111"></a>01111                                  __func__, addr);
+<a name="l01112"></a>01112                         <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l01113"></a>01113                 }
+<a name="l01114"></a>01114                 retval = cfi_reset_concat_val(cfiep);
+<a name="l01115"></a>01115         }
+<a name="l01116"></a>01116         <span class="comment">/* Otherwise (wValue == 0), reset all features of all EP's */</span>
+<a name="l01117"></a>01117         <span class="keywordflow">else</span> {
+<a name="l01118"></a>01118                 <span class="comment">/* Traverse all the active EP's and reset the feature(s) value(s) */</span>
+<a name="l01119"></a>01119                 <span class="comment">//list_for_each_entry(cfiep, &amp;cfi-&gt;active_eps, lh) {</span>
+<a name="l01120"></a>01120                 DWC_LIST_FOREACH(tmp, &amp;cfi-&gt;<a class="code" href="structcfiobject.html#82805f011abf3deace7faa159729229a">active_eps</a>) {
+<a name="l01121"></a>01121                         cfiep = DWC_LIST_ENTRY(tmp, <span class="keyword">struct</span> <a class="code" href="structcfi__ep.html">cfi_ep</a>, lh);
+<a name="l01122"></a>01122                         retval = cfi_reset_concat_val(cfiep);
+<a name="l01123"></a>01123                         <span class="keywordflow">if</span> (retval &lt; 0) {
+<a name="l01124"></a>01124                                 <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>
+<a name="l01125"></a>01125                                     (<span class="stringliteral">"%s: Error resetting the feature Concatenation Value\n"</span>,
+<a name="l01126"></a>01126                                      __func__);
+<a name="l01127"></a>01127                                 <span class="keywordflow">return</span> retval;
+<a name="l01128"></a>01128                         }
+<a name="l01129"></a>01129                 }
+<a name="l01130"></a>01130         }
+<a name="l01131"></a>01131         <span class="keywordflow">return</span> retval;
+<a name="l01132"></a>01132 }
+<a name="l01133"></a>01133 
+<a name="l01134"></a>01134 <span class="keyword">static</span> <span class="keywordtype">int</span> cfi_handle_reset_align_val(<span class="keyword">struct</span> <a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd</a> *pcd, uint8_t addr)
+<a name="l01135"></a>01135 {
+<a name="l01136"></a>01136         <span class="keywordtype">int</span> retval = 0;
+<a name="l01137"></a>01137         <a class="code" href="structcfi__ep.html">cfi_ep_t</a> *cfiep;
+<a name="l01138"></a>01138         <a class="code" href="structcfiobject.html">cfiobject_t</a> *cfi = pcd-&gt;cfi;
+<a name="l01139"></a>01139         dwc_list_link_t *tmp;
+<a name="l01140"></a>01140 
+<a name="l01141"></a>01141         <span class="comment">/* If the EP address is known then reset the features for only that EP */</span>
+<a name="l01142"></a>01142         <span class="keywordflow">if</span> (addr) {
+<a name="l01143"></a>01143                 cfiep = <a class="code" href="dwc__otg__cfi_8h.html#5ece1e51b8534a5cc9a7dd5115bb01ca">get_cfi_ep_by_addr</a>(pcd-&gt;cfi, addr);
+<a name="l01144"></a>01144                 <span class="keywordflow">if</span> (NULL == cfiep) {
+<a name="l01145"></a>01145                         <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>(<span class="stringliteral">"%s: Error getting the EP address 0x%02x\n"</span>,
+<a name="l01146"></a>01146                                  __func__, addr);
+<a name="l01147"></a>01147                         <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l01148"></a>01148                 }
+<a name="l01149"></a>01149                 retval = cfi_reset_align_val(cfiep);
+<a name="l01150"></a>01150         }
+<a name="l01151"></a>01151         <span class="comment">/* Otherwise (wValue == 0), reset all features of all EP's */</span>
+<a name="l01152"></a>01152         <span class="keywordflow">else</span> {
+<a name="l01153"></a>01153                 <span class="comment">/* Traverse all the active EP's and reset the feature(s) value(s) */</span>
+<a name="l01154"></a>01154                 <span class="comment">//list_for_each_entry(cfiep, &amp;cfi-&gt;active_eps, lh) {</span>
+<a name="l01155"></a>01155                 DWC_LIST_FOREACH(tmp, &amp;cfi-&gt;<a class="code" href="structcfiobject.html#82805f011abf3deace7faa159729229a">active_eps</a>) {
+<a name="l01156"></a>01156                         cfiep = DWC_LIST_ENTRY(tmp, <span class="keyword">struct</span> <a class="code" href="structcfi__ep.html">cfi_ep</a>, lh);
+<a name="l01157"></a>01157                         retval = cfi_reset_align_val(cfiep);
+<a name="l01158"></a>01158                         <span class="keywordflow">if</span> (retval &lt; 0) {
+<a name="l01159"></a>01159                                 <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>
+<a name="l01160"></a>01160                                     (<span class="stringliteral">"%s: Error resetting the feature Aliignment Value\n"</span>,
+<a name="l01161"></a>01161                                      __func__);
+<a name="l01162"></a>01162                                 <span class="keywordflow">return</span> retval;
+<a name="l01163"></a>01163                         }
+<a name="l01164"></a>01164                 }
+<a name="l01165"></a>01165         }
+<a name="l01166"></a>01166         <span class="keywordflow">return</span> retval;
+<a name="l01167"></a>01167 
+<a name="l01168"></a>01168 }
+<a name="l01169"></a>01169 
+<a name="l01170"></a>01170 <span class="keyword">static</span> <span class="keywordtype">int</span> cfi_preproc_reset(<span class="keyword">struct</span> <a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd</a> *pcd,
+<a name="l01171"></a>01171                              <span class="keyword">struct</span> <a class="code" href="structcfi__usb__ctrlrequest.html">cfi_usb_ctrlrequest</a> *req)
+<a name="l01172"></a>01172 {
+<a name="l01173"></a>01173         <span class="keywordtype">int</span> retval = 0;
+<a name="l01174"></a>01174 
+<a name="l01175"></a>01175         <span class="keywordflow">switch</span> (req-&gt;<a class="code" href="structcfi__usb__ctrlrequest.html#984c95bd61e8d1120cd935bcbc5d7134">wIndex</a>) {
+<a name="l01176"></a>01176         <span class="keywordflow">case</span> 0:
+<a name="l01177"></a>01177                 <span class="comment">/* Reset all features */</span>
+<a name="l01178"></a>01178                 retval = cfi_handle_reset_all(pcd, req-&gt;<a class="code" href="structcfi__usb__ctrlrequest.html#2f236bbf9450df1a3b5204c4570d883f">wValue</a> &amp; 0xff);
+<a name="l01179"></a>01179                 <span class="keywordflow">break</span>;
+<a name="l01180"></a>01180 
+<a name="l01181"></a>01181         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__cfi_8h.html#98840b45640251bfafa3481260aef889">FT_ID_DMA_BUFFER_SETUP</a>:
+<a name="l01182"></a>01182                 <span class="comment">/* Reset the SG buffer setup */</span>
+<a name="l01183"></a>01183                 retval =
+<a name="l01184"></a>01184                     cfi_handle_reset_dma_buff_setup(pcd, req-&gt;<a class="code" href="structcfi__usb__ctrlrequest.html#2f236bbf9450df1a3b5204c4570d883f">wValue</a> &amp; 0xff);
+<a name="l01185"></a>01185                 <span class="keywordflow">break</span>;
+<a name="l01186"></a>01186 
+<a name="l01187"></a>01187         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__cfi_8h.html#779a11db5843dd058581d93c8232bd7c">FT_ID_DMA_CONCAT_SETUP</a>:
+<a name="l01188"></a>01188                 <span class="comment">/* Reset the Concatenation buffer setup */</span>
+<a name="l01189"></a>01189                 retval = cfi_handle_reset_concat_val(pcd, req-&gt;<a class="code" href="structcfi__usb__ctrlrequest.html#2f236bbf9450df1a3b5204c4570d883f">wValue</a> &amp; 0xff);
+<a name="l01190"></a>01190                 <span class="keywordflow">break</span>;
+<a name="l01191"></a>01191 
+<a name="l01192"></a>01192         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__cfi_8h.html#9335284cd4dae01f4bc0da7cb89d5ef4">FT_ID_DMA_BUFF_ALIGN</a>:
+<a name="l01193"></a>01193                 <span class="comment">/* Reset the Alignment buffer setup */</span>
+<a name="l01194"></a>01194                 retval = cfi_handle_reset_align_val(pcd, req-&gt;<a class="code" href="structcfi__usb__ctrlrequest.html#2f236bbf9450df1a3b5204c4570d883f">wValue</a> &amp; 0xff);
+<a name="l01195"></a>01195                 <span class="keywordflow">break</span>;
+<a name="l01196"></a>01196 
+<a name="l01197"></a>01197         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__cfi_8h.html#a3a67b679a59c5279370bbf69f114cb6">FT_ID_TX_FIFO_DEPTH</a>:
+<a name="l01198"></a>01198                 retval =
+<a name="l01199"></a>01199                     cfi_handle_reset_fifo_val(pcd, req-&gt;<a class="code" href="structcfi__usb__ctrlrequest.html#2f236bbf9450df1a3b5204c4570d883f">wValue</a> &amp; 0xff, 0, 1);
+<a name="l01200"></a>01200                 pcd-&gt;cfi-&gt;need_gadget_att = 0;
+<a name="l01201"></a>01201                 <span class="keywordflow">break</span>;
+<a name="l01202"></a>01202 
+<a name="l01203"></a>01203         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__cfi_8h.html#42b7c98c105de1f9399786a3419e7e20">FT_ID_RX_FIFO_DEPTH</a>:
+<a name="l01204"></a>01204                 retval = cfi_handle_reset_fifo_val(pcd, 0, 1, 0);
+<a name="l01205"></a>01205                 pcd-&gt;cfi-&gt;need_gadget_att = 0;
+<a name="l01206"></a>01206                 <span class="keywordflow">break</span>;
+<a name="l01207"></a>01207         <span class="keywordflow">default</span>:
+<a name="l01208"></a>01208                 <span class="keywordflow">break</span>;
+<a name="l01209"></a>01209         }
+<a name="l01210"></a>01210         <span class="keywordflow">return</span> retval;
+<a name="l01211"></a>01211 }
+<a name="l01212"></a>01212 
+<a name="l01216"></a>01216 <span class="keyword">static</span> <span class="keywordtype">int</span> cfi_ep_set_sg_val(uint8_t * buf, <span class="keyword">struct</span> <a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd</a> *pcd)
+<a name="l01217"></a>01217 {
+<a name="l01218"></a>01218         uint8_t inaddr, outaddr;
+<a name="l01219"></a>01219         <a class="code" href="structcfi__ep.html">cfi_ep_t</a> *epin, *epout;
+<a name="l01220"></a>01220         <a class="code" href="struct__ddma__sg__buffer__setup.html">ddma_sg_buffer_setup_t</a> *psgval;
+<a name="l01221"></a>01221         uint32_t desccount, size;
+<a name="l01222"></a>01222 
+<a name="l01223"></a>01223         <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>(<span class="stringliteral">"%s\n"</span>, __func__);
+<a name="l01224"></a>01224 
+<a name="l01225"></a>01225         psgval = (<a class="code" href="struct__ddma__sg__buffer__setup.html">ddma_sg_buffer_setup_t</a> *) buf;
+<a name="l01226"></a>01226         desccount = (uint32_t) psgval-&gt;<a class="code" href="struct__ddma__sg__buffer__setup.html#6287daf5a964bf1d09e8ffca29b88748">bCount</a>;
+<a name="l01227"></a>01227         size = (uint32_t) psgval-&gt;<a class="code" href="struct__ddma__sg__buffer__setup.html#728db9bac2db62f7e7b2b9ccb0873546">wSize</a>;
+<a name="l01228"></a>01228 
+<a name="l01229"></a>01229         <span class="comment">/* Check the DMA descriptor count */</span>
+<a name="l01230"></a>01230         <span class="keywordflow">if</span> ((desccount &gt; MAX_DMA_DESCS_PER_EP) || (desccount == 0)) {
+<a name="l01231"></a>01231                 <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>
+<a name="l01232"></a>01232                     (<span class="stringliteral">"%s: The count of DMA Descriptors should be between 1 and %d\n"</span>,
+<a name="l01233"></a>01233                      __func__, MAX_DMA_DESCS_PER_EP);
+<a name="l01234"></a>01234                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l01235"></a>01235         }
+<a name="l01236"></a>01236 
+<a name="l01237"></a>01237         <span class="comment">/* Check the DMA descriptor count */</span>
+<a name="l01238"></a>01238 
+<a name="l01239"></a>01239         <span class="keywordflow">if</span> (size == 0) {
+<a name="l01240"></a>01240 
+<a name="l01241"></a>01241                 <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>(<span class="stringliteral">"%s: The transfer size should be at least 1 byte\n"</span>,
+<a name="l01242"></a>01242                          __func__);
+<a name="l01243"></a>01243 
+<a name="l01244"></a>01244                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l01245"></a>01245 
+<a name="l01246"></a>01246         }
+<a name="l01247"></a>01247 
+<a name="l01248"></a>01248         inaddr = psgval-&gt;<a class="code" href="struct__ddma__sg__buffer__setup.html#bb435a2ac72bfd26384c9b5b1b0b35af">bInEndpointAddress</a>;
+<a name="l01249"></a>01249         outaddr = psgval-&gt;<a class="code" href="struct__ddma__sg__buffer__setup.html#b61eaff3e4857fd6223d9fc678814786">bOutEndpointAddress</a>;
+<a name="l01250"></a>01250 
+<a name="l01251"></a>01251         epin = <a class="code" href="dwc__otg__cfi_8h.html#5ece1e51b8534a5cc9a7dd5115bb01ca">get_cfi_ep_by_addr</a>(pcd-&gt;cfi, inaddr);
+<a name="l01252"></a>01252         epout = <a class="code" href="dwc__otg__cfi_8h.html#5ece1e51b8534a5cc9a7dd5115bb01ca">get_cfi_ep_by_addr</a>(pcd-&gt;cfi, outaddr);
+<a name="l01253"></a>01253 
+<a name="l01254"></a>01254         <span class="keywordflow">if</span> (NULL == epin || NULL == epout) {
+<a name="l01255"></a>01255                 <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>
+<a name="l01256"></a>01256                     (<span class="stringliteral">"%s: Unable to get the endpoints inaddr=0x%02x outaddr=0x%02x\n"</span>,
+<a name="l01257"></a>01257                      __func__, inaddr, outaddr);
+<a name="l01258"></a>01258                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l01259"></a>01259         }
+<a name="l01260"></a>01260 
+<a name="l01261"></a>01261         epin-&gt;<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.buff_mode = BM_SG;
+<a name="l01262"></a>01262         dwc_memcpy(epin-&gt;<a class="code" href="structcfi__ep.html#4010b0f12bf1cd37a2c0bf06b392570a">bm_sg</a>, psgval, <span class="keyword">sizeof</span>(<a class="code" href="struct__ddma__sg__buffer__setup.html">ddma_sg_buffer_setup_t</a>));
+<a name="l01263"></a>01263 
+<a name="l01264"></a>01264         epout-&gt;<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.buff_mode = BM_SG;
+<a name="l01265"></a>01265         dwc_memcpy(epout-&gt;<a class="code" href="structcfi__ep.html#4010b0f12bf1cd37a2c0bf06b392570a">bm_sg</a>, psgval, <span class="keyword">sizeof</span>(<a class="code" href="struct__ddma__sg__buffer__setup.html">ddma_sg_buffer_setup_t</a>));
+<a name="l01266"></a>01266 
+<a name="l01267"></a>01267         <span class="keywordflow">return</span> 0;
+<a name="l01268"></a>01268 }
+<a name="l01269"></a>01269 
+<a name="l01273"></a>01273 <span class="keyword">static</span> <span class="keywordtype">int</span> cfi_ep_set_alignment_val(uint8_t * buf, <span class="keyword">struct</span> <a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd</a> *pcd)
+<a name="l01274"></a>01274 {
+<a name="l01275"></a>01275         <a class="code" href="structcfi__ep.html">cfi_ep_t</a> *ep;
+<a name="l01276"></a>01276         uint8_t addr;
+<a name="l01277"></a>01277         <a class="code" href="struct__ddma__align__buffer__setup.html">ddma_align_buffer_setup_t</a> *palignval;
+<a name="l01278"></a>01278 
+<a name="l01279"></a>01279         palignval = (<a class="code" href="struct__ddma__align__buffer__setup.html">ddma_align_buffer_setup_t</a> *) buf;
+<a name="l01280"></a>01280         addr = palignval-&gt;<a class="code" href="struct__ddma__align__buffer__setup.html#28008cbe6479b7473aa21ac2d3ceaf67">bEndpointAddress</a>;
+<a name="l01281"></a>01281 
+<a name="l01282"></a>01282         ep = <a class="code" href="dwc__otg__cfi_8h.html#5ece1e51b8534a5cc9a7dd5115bb01ca">get_cfi_ep_by_addr</a>(pcd-&gt;cfi, addr);
+<a name="l01283"></a>01283 
+<a name="l01284"></a>01284         <span class="keywordflow">if</span> (NULL == ep) {
+<a name="l01285"></a>01285                 <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>(<span class="stringliteral">"%s: Unable to get the endpoint addr=0x%02x\n"</span>,
+<a name="l01286"></a>01286                          __func__, addr);
+<a name="l01287"></a>01287                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l01288"></a>01288         }
+<a name="l01289"></a>01289 
+<a name="l01290"></a>01290         ep-&gt;<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.buff_mode = BM_ALIGN;
+<a name="l01291"></a>01291         dwc_memcpy(ep-&gt;<a class="code" href="structcfi__ep.html#bb544b7938d0c62857fc3726988310d2">bm_align</a>, palignval, <span class="keyword">sizeof</span>(<a class="code" href="struct__ddma__align__buffer__setup.html">ddma_align_buffer_setup_t</a>));
+<a name="l01292"></a>01292 
+<a name="l01293"></a>01293         <span class="keywordflow">return</span> 0;
+<a name="l01294"></a>01294 }
+<a name="l01295"></a>01295 
+<a name="l01299"></a>01299 <span class="keyword">static</span> <span class="keywordtype">int</span> cfi_ep_set_concat_val(uint8_t * buf, <span class="keyword">struct</span> <a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd</a> *pcd)
+<a name="l01300"></a>01300 {
+<a name="l01301"></a>01301         uint8_t addr;
+<a name="l01302"></a>01302         <a class="code" href="structcfi__ep.html">cfi_ep_t</a> *ep;
+<a name="l01303"></a>01303         <span class="keyword">struct </span><a class="code" href="struct__ddma__concat__buffer__setup__hdr.html">_ddma_concat_buffer_setup_hdr</a> *pConcatValHdr;
+<a name="l01304"></a>01304         uint16_t *pVals;
+<a name="l01305"></a>01305         uint32_t desccount;
+<a name="l01306"></a>01306         <span class="keywordtype">int</span> i;
+<a name="l01307"></a>01307         uint16_t mps;
+<a name="l01308"></a>01308 
+<a name="l01309"></a>01309         pConcatValHdr = (<span class="keyword">struct </span><a class="code" href="struct__ddma__concat__buffer__setup__hdr.html">_ddma_concat_buffer_setup_hdr</a> *)buf;
+<a name="l01310"></a>01310         desccount = (uint32_t) pConcatValHdr-&gt;<a class="code" href="struct__ddma__concat__buffer__setup__hdr.html#605becc1e8a681d6623343b28013b56a">bDescCount</a>;
+<a name="l01311"></a>01311         pVals = (uint16_t *) (buf + <a class="code" href="dwc__otg__cfi_8h.html#c89955571b72df025126a1047bc53a00">BS_CONCAT_VAL_HDR_LEN</a>);
+<a name="l01312"></a>01312 
+<a name="l01313"></a>01313         <span class="comment">/* Check the DMA descriptor count */</span>
+<a name="l01314"></a>01314         <span class="keywordflow">if</span> (desccount &gt; MAX_DMA_DESCS_PER_EP) {
+<a name="l01315"></a>01315                 <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>(<span class="stringliteral">"%s: Maximum DMA Descriptor count should be %d\n"</span>,
+<a name="l01316"></a>01316                          __func__, MAX_DMA_DESCS_PER_EP);
+<a name="l01317"></a>01317                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l01318"></a>01318         }
+<a name="l01319"></a>01319 
+<a name="l01320"></a>01320         addr = pConcatValHdr-&gt;<a class="code" href="struct__ddma__concat__buffer__setup__hdr.html#b6e4aab1ee8884a314ba38326ea85f24">bEndpointAddress</a>;
+<a name="l01321"></a>01321         ep = <a class="code" href="dwc__otg__cfi_8h.html#5ece1e51b8534a5cc9a7dd5115bb01ca">get_cfi_ep_by_addr</a>(pcd-&gt;cfi, addr);
+<a name="l01322"></a>01322         <span class="keywordflow">if</span> (NULL == ep) {
+<a name="l01323"></a>01323                 <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>(<span class="stringliteral">"%s: Unable to get the endpoint addr=0x%02x\n"</span>,
+<a name="l01324"></a>01324                          __func__, addr);
+<a name="l01325"></a>01325                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l01326"></a>01326         }
+<a name="l01327"></a>01327 
+<a name="l01328"></a>01328         mps = UGETW(ep-&gt;<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#86e27843c439dd0b1d12d9bf2dc6516f">desc</a>-&gt;wMaxPacketSize);
+<a name="l01329"></a>01329 
+<a name="l01330"></a>01330 <span class="preprocessor">#if 0</span>
+<a name="l01331"></a>01331 <span class="preprocessor"></span>        <span class="keywordflow">for</span> (i = 0; i &lt; desccount; i++) {
+<a name="l01332"></a>01332                 <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>(<span class="stringliteral">"%s: wTxSize[%d]=0x%04x\n"</span>, __func__, i, pVals[i]);
+<a name="l01333"></a>01333         }
+<a name="l01334"></a>01334         <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>(<span class="stringliteral">"%s: epname=%s; mps=%d\n"</span>, __func__, ep-&gt;<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;ep.name, mps);
+<a name="l01335"></a>01335 <span class="preprocessor">#endif</span>
+<a name="l01336"></a>01336 <span class="preprocessor"></span>
+<a name="l01337"></a>01337         <span class="comment">/* Check the wTxSizes to be less than or equal to the mps */</span>
+<a name="l01338"></a>01338         <span class="keywordflow">for</span> (i = 0; i &lt; desccount; i++) {
+<a name="l01339"></a>01339                 <span class="keywordflow">if</span> (pVals[i] &gt; mps) {
+<a name="l01340"></a>01340                         <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>
+<a name="l01341"></a>01341                             (<span class="stringliteral">"%s: ERROR - the wTxSize[%d] should be &lt;= MPS (wTxSize=%d)\n"</span>,
+<a name="l01342"></a>01342                              __func__, i, pVals[i]);
+<a name="l01343"></a>01343                         <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l01344"></a>01344                 }
+<a name="l01345"></a>01345         }
+<a name="l01346"></a>01346 
+<a name="l01347"></a>01347         ep-&gt;<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.buff_mode = BM_CONCAT;
+<a name="l01348"></a>01348         dwc_memcpy(ep-&gt;<a class="code" href="structcfi__ep.html#4c83b9bb5a75e6b81fbfa86b51736164">bm_concat</a>, pConcatValHdr, <a class="code" href="dwc__otg__cfi_8h.html#c89955571b72df025126a1047bc53a00">BS_CONCAT_VAL_HDR_LEN</a>);
+<a name="l01349"></a>01349 
+<a name="l01350"></a>01350         <span class="comment">/* Free the previously allocated storage for the wTxBytes */</span>
+<a name="l01351"></a>01351         <span class="keywordflow">if</span> (ep-&gt;<a class="code" href="structcfi__ep.html#4c83b9bb5a75e6b81fbfa86b51736164">bm_concat</a>-&gt;<a class="code" href="struct__ddma__concat__buffer__setup.html#748241a5b55a514f4386498aceb1e505">wTxBytes</a>) {
+<a name="l01352"></a>01352                 dwc_free(ep-&gt;<a class="code" href="structcfi__ep.html#4c83b9bb5a75e6b81fbfa86b51736164">bm_concat</a>-&gt;<a class="code" href="struct__ddma__concat__buffer__setup.html#748241a5b55a514f4386498aceb1e505">wTxBytes</a>);
+<a name="l01353"></a>01353         }
+<a name="l01354"></a>01354 
+<a name="l01355"></a>01355         <span class="comment">/* Allocate a new storage for the wTxBytes field */</span>
+<a name="l01356"></a>01356         ep-&gt;<a class="code" href="structcfi__ep.html#4c83b9bb5a75e6b81fbfa86b51736164">bm_concat</a>-&gt;<a class="code" href="struct__ddma__concat__buffer__setup.html#748241a5b55a514f4386498aceb1e505">wTxBytes</a> =
+<a name="l01357"></a>01357             dwc_alloc(<span class="keyword">sizeof</span>(uint16_t) * pConcatValHdr-&gt;<a class="code" href="struct__ddma__concat__buffer__setup__hdr.html#605becc1e8a681d6623343b28013b56a">bDescCount</a>);
+<a name="l01358"></a>01358         <span class="keywordflow">if</span> (NULL == ep-&gt;<a class="code" href="structcfi__ep.html#4c83b9bb5a75e6b81fbfa86b51736164">bm_concat</a>-&gt;<a class="code" href="struct__ddma__concat__buffer__setup.html#748241a5b55a514f4386498aceb1e505">wTxBytes</a>) {
+<a name="l01359"></a>01359                 <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>(<span class="stringliteral">"%s: Unable to allocate memory\n"</span>, __func__);
+<a name="l01360"></a>01360                 <span class="keywordflow">return</span> -DWC_E_NO_MEMORY;
+<a name="l01361"></a>01361         }
+<a name="l01362"></a>01362 
+<a name="l01363"></a>01363         <span class="comment">/* Copy the new values into the wTxBytes filed */</span>
+<a name="l01364"></a>01364         dwc_memcpy(ep-&gt;<a class="code" href="structcfi__ep.html#4c83b9bb5a75e6b81fbfa86b51736164">bm_concat</a>-&gt;<a class="code" href="struct__ddma__concat__buffer__setup.html#748241a5b55a514f4386498aceb1e505">wTxBytes</a>, buf + <a class="code" href="dwc__otg__cfi_8h.html#c89955571b72df025126a1047bc53a00">BS_CONCAT_VAL_HDR_LEN</a>,
+<a name="l01365"></a>01365                    <span class="keyword">sizeof</span>(uint16_t) * pConcatValHdr-&gt;<a class="code" href="struct__ddma__concat__buffer__setup__hdr.html#605becc1e8a681d6623343b28013b56a">bDescCount</a>);
+<a name="l01366"></a>01366 
+<a name="l01367"></a>01367         <span class="keywordflow">return</span> 0;
+<a name="l01368"></a>01368 }
+<a name="l01369"></a>01369 
+<a name="l01378"></a>01378 <span class="keyword">static</span> uint16_t get_dfifo_size(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l01379"></a>01379 {
+<a name="l01380"></a>01380         <a class="code" href="structdwc__otg__core__params.html">dwc_otg_core_params_t</a> *params = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>;
+<a name="l01381"></a>01381         uint16_t dfifo_total = 0;
+<a name="l01382"></a>01382         <span class="keywordtype">int</span> i;
+<a name="l01383"></a>01383 
+<a name="l01384"></a>01384         <span class="comment">/* The shared RxFIFO size */</span>
+<a name="l01385"></a>01385         dfifo_total =
+<a name="l01386"></a>01386             params-&gt;<a class="code" href="structdwc__otg__core__params.html#24ea6f9329f64ac0ad2d31dafe0d1d8c">dev_rx_fifo_size</a> + params-&gt;<a class="code" href="structdwc__otg__core__params.html#d08d9aee1fb4e6508089415d6150176e">dev_nperio_tx_fifo_size</a>;
+<a name="l01387"></a>01387 
+<a name="l01388"></a>01388         <span class="comment">/* Add up each TxFIFO size to the total */</span>
+<a name="l01389"></a>01389         <span class="keywordflow">for</span> (i = 0; i &lt; core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#9c1394f3c46adde2fa7be79bf0237f9b">hwcfg4</a>.<a class="code" href="unionhwcfg4__data.html#9fb9175668e2381c568c5adbf6e5225d">b</a>.<a class="code" href="unionhwcfg4__data.html#753b321350388c5e1307802ff968f9a8">num_in_eps</a>; i++) {
+<a name="l01390"></a>01390                 dfifo_total += params-&gt;<a class="code" href="structdwc__otg__core__params.html#6e0c5d06467fbf3458f11f7eb8153a8b">dev_tx_fifo_size</a>[i];
+<a name="l01391"></a>01391         }
+<a name="l01392"></a>01392 
+<a name="l01393"></a>01393         <span class="keywordflow">return</span> dfifo_total;
+<a name="l01394"></a>01394 }
+<a name="l01395"></a>01395 
+<a name="l01404"></a>01404 <span class="keyword">static</span> int32_t get_rxfifo_size(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, uint16_t wValue)
+<a name="l01405"></a>01405 {
+<a name="l01406"></a>01406         <span class="keywordflow">switch</span> (wValue &gt;&gt; 8) {
+<a name="l01407"></a>01407         <span class="keywordflow">case</span> 0:
+<a name="l01408"></a>01408                 <span class="keywordflow">return</span> (core_if-&gt;pwron_rxfsiz &lt;
+<a name="l01409"></a>01409                         32768) ? core_if-&gt;pwron_rxfsiz : 32768;
+<a name="l01410"></a>01410                 <span class="keywordflow">break</span>;
+<a name="l01411"></a>01411         <span class="keywordflow">case</span> 1:
+<a name="l01412"></a>01412                 <span class="keywordflow">return</span> core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#24ea6f9329f64ac0ad2d31dafe0d1d8c">dev_rx_fifo_size</a>;
+<a name="l01413"></a>01413                 <span class="keywordflow">break</span>;
+<a name="l01414"></a>01414         <span class="keywordflow">default</span>:
+<a name="l01415"></a>01415                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l01416"></a>01416                 <span class="keywordflow">break</span>;
+<a name="l01417"></a>01417         }
+<a name="l01418"></a>01418 }
+<a name="l01419"></a>01419 
+<a name="l01428"></a>01428 <span class="keyword">static</span> int32_t get_txfifo_size(<span class="keyword">struct</span> <a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd</a> *pcd, uint16_t wValue)
+<a name="l01429"></a>01429 {
+<a name="l01430"></a>01430         <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *ep;
+<a name="l01431"></a>01431 
+<a name="l01432"></a>01432         ep = <a class="code" href="dwc__otg__pcd__intr_8c.html#3c351d7f51d6242296d6ea3bb1a9775c">get_ep_by_addr</a>(pcd, wValue &amp; 0xff);
+<a name="l01433"></a>01433 
+<a name="l01434"></a>01434         <span class="keywordflow">if</span> (NULL == ep) {
+<a name="l01435"></a>01435                 <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>(<span class="stringliteral">"%s: Unable to get the endpoint addr=0x%02x\n"</span>,
+<a name="l01436"></a>01436                          __func__, wValue &amp; 0xff);
+<a name="l01437"></a>01437                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l01438"></a>01438         }
+<a name="l01439"></a>01439 
+<a name="l01440"></a>01440         <span class="keywordflow">if</span> (!ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#b882b6b7c857100ed20600e94ea37760">is_in</a>) {
+<a name="l01441"></a>01441                 <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>
+<a name="l01442"></a>01442                     (<span class="stringliteral">"%s: No Tx FIFO assingned to the Out endpoint addr=0x%02x\n"</span>,
+<a name="l01443"></a>01443                      __func__, wValue &amp; 0xff);
+<a name="l01444"></a>01444                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l01445"></a>01445         }
+<a name="l01446"></a>01446 
+<a name="l01447"></a>01447         <span class="keywordflow">switch</span> (wValue &gt;&gt; 8) {
+<a name="l01448"></a>01448         <span class="keywordflow">case</span> 0:
+<a name="l01449"></a>01449                 <span class="keywordflow">return</span> (<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;
+<a name="l01450"></a>01450                         pwron_txfsiz[ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#ffa14f48094778143353b845b5d238cd">tx_fifo_num</a> - 1] &lt;
+<a name="l01451"></a>01451                         768) ? <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;pwron_txfsiz[ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.
+<a name="l01452"></a>01452                                                               tx_fifo_num -
+<a name="l01453"></a>01453                                                               1] : 32768;
+<a name="l01454"></a>01454                 <span class="keywordflow">break</span>;
+<a name="l01455"></a>01455         <span class="keywordflow">case</span> 1:
+<a name="l01456"></a>01456                 <span class="keywordflow">return</span> <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;core_params-&gt;dev_tx_fifo_size[ep-&gt;
+<a name="l01457"></a>01457                                                                        <a class="code" href="structdwc__ep.html">dwc_ep</a>.
+<a name="l01458"></a>01458                                                                        num - 1];
+<a name="l01459"></a>01459                 <span class="keywordflow">break</span>;
+<a name="l01460"></a>01460         <span class="keywordflow">default</span>:
+<a name="l01461"></a>01461                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l01462"></a>01462                 <span class="keywordflow">break</span>;
+<a name="l01463"></a>01463         }
+<a name="l01464"></a>01464 }
+<a name="l01465"></a>01465 
+<a name="l01475"></a>01475 <span class="keyword">static</span> uint8_t check_fifo_sizes(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l01476"></a>01476 {
+<a name="l01477"></a>01477         uint16_t dfifo_actual = 0;
+<a name="l01478"></a>01478         <a class="code" href="structdwc__otg__core__params.html">dwc_otg_core_params_t</a> *params = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>;
+<a name="l01479"></a>01479         uint16_t start_addr = 0;
+<a name="l01480"></a>01480         <span class="keywordtype">int</span> i;
+<a name="l01481"></a>01481 
+<a name="l01482"></a>01482         dfifo_actual =
+<a name="l01483"></a>01483             params-&gt;<a class="code" href="structdwc__otg__core__params.html#24ea6f9329f64ac0ad2d31dafe0d1d8c">dev_rx_fifo_size</a> + params-&gt;<a class="code" href="structdwc__otg__core__params.html#d08d9aee1fb4e6508089415d6150176e">dev_nperio_tx_fifo_size</a>;
+<a name="l01484"></a>01484 
+<a name="l01485"></a>01485         <span class="keywordflow">for</span> (i = 0; i &lt; core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#9c1394f3c46adde2fa7be79bf0237f9b">hwcfg4</a>.<a class="code" href="unionhwcfg4__data.html#9fb9175668e2381c568c5adbf6e5225d">b</a>.<a class="code" href="unionhwcfg4__data.html#753b321350388c5e1307802ff968f9a8">num_in_eps</a>; i++) {
+<a name="l01486"></a>01486                 dfifo_actual += params-&gt;<a class="code" href="structdwc__otg__core__params.html#6e0c5d06467fbf3458f11f7eb8153a8b">dev_tx_fifo_size</a>[i];
+<a name="l01487"></a>01487         }
+<a name="l01488"></a>01488 
+<a name="l01489"></a>01489         <span class="keywordflow">if</span> (dfifo_actual &gt; core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#cae59008a554cb7de24bd4f2afea7532">total_fifo_size</a>) {
+<a name="l01490"></a>01490                 <span class="keywordflow">return</span> 0;
+<a name="l01491"></a>01491         }
+<a name="l01492"></a>01492 
+<a name="l01493"></a>01493         <span class="keywordflow">if</span> (params-&gt;<a class="code" href="structdwc__otg__core__params.html#24ea6f9329f64ac0ad2d31dafe0d1d8c">dev_rx_fifo_size</a> &gt; 32768 || params-&gt;<a class="code" href="structdwc__otg__core__params.html#24ea6f9329f64ac0ad2d31dafe0d1d8c">dev_rx_fifo_size</a> &lt; 16)
+<a name="l01494"></a>01494                 <span class="keywordflow">return</span> 0;
+<a name="l01495"></a>01495 
+<a name="l01496"></a>01496         if (params-&gt;<a class="code" href="structdwc__otg__core__params.html#d08d9aee1fb4e6508089415d6150176e">dev_nperio_tx_fifo_size</a> &gt; 32768
+<a name="l01497"></a>01497             || params-&gt;<a class="code" href="structdwc__otg__core__params.html#d08d9aee1fb4e6508089415d6150176e">dev_nperio_tx_fifo_size</a> &lt; 16)
+<a name="l01498"></a>01498                 <span class="keywordflow">return</span> 0;
+<a name="l01499"></a>01499 
+<a name="l01500"></a>01500         for (i = 0; i &lt; core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#9c1394f3c46adde2fa7be79bf0237f9b">hwcfg4</a>.<a class="code" href="unionhwcfg4__data.html#9fb9175668e2381c568c5adbf6e5225d">b</a>.<a class="code" href="unionhwcfg4__data.html#753b321350388c5e1307802ff968f9a8">num_in_eps</a>; i++) {
+<a name="l01501"></a>01501 
+<a name="l01502"></a>01502                 <span class="keywordflow">if</span> (params-&gt;<a class="code" href="structdwc__otg__core__params.html#6e0c5d06467fbf3458f11f7eb8153a8b">dev_tx_fifo_size</a>[i] &gt; 768
+<a name="l01503"></a>01503                     || params-&gt;<a class="code" href="structdwc__otg__core__params.html#6e0c5d06467fbf3458f11f7eb8153a8b">dev_tx_fifo_size</a>[i] &lt; 4)
+<a name="l01504"></a>01504                         <span class="keywordflow">return</span> 0;
+<a name="l01505"></a>01505         }
+<a name="l01506"></a>01506 
+<a name="l01507"></a>01507         <span class="keywordflow">if</span> (params-&gt;<a class="code" href="structdwc__otg__core__params.html#24ea6f9329f64ac0ad2d31dafe0d1d8c">dev_rx_fifo_size</a> &gt; core_if-&gt;pwron_rxfsiz)
+<a name="l01508"></a>01508                 <span class="keywordflow">return</span> 0;
+<a name="l01509"></a>01509         start_addr = params-&gt;<a class="code" href="structdwc__otg__core__params.html#24ea6f9329f64ac0ad2d31dafe0d1d8c">dev_rx_fifo_size</a>;
+<a name="l01510"></a>01510 
+<a name="l01511"></a>01511         if (params-&gt;<a class="code" href="structdwc__otg__core__params.html#d08d9aee1fb4e6508089415d6150176e">dev_nperio_tx_fifo_size</a> &gt; core_if-&gt;pwron_gnptxfsiz)
+<a name="l01512"></a>01512                 <span class="keywordflow">return</span> 0;
+<a name="l01513"></a>01513         start_addr += params-&gt;<a class="code" href="structdwc__otg__core__params.html#d08d9aee1fb4e6508089415d6150176e">dev_nperio_tx_fifo_size</a>;
+<a name="l01514"></a>01514 
+<a name="l01515"></a>01515         for (i = 0; i &lt; core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#9c1394f3c46adde2fa7be79bf0237f9b">hwcfg4</a>.<a class="code" href="unionhwcfg4__data.html#9fb9175668e2381c568c5adbf6e5225d">b</a>.<a class="code" href="unionhwcfg4__data.html#753b321350388c5e1307802ff968f9a8">num_in_eps</a>; i++) {
+<a name="l01516"></a>01516 
+<a name="l01517"></a>01517                 <span class="keywordflow">if</span> (params-&gt;<a class="code" href="structdwc__otg__core__params.html#6e0c5d06467fbf3458f11f7eb8153a8b">dev_tx_fifo_size</a>[i] &gt; core_if-&gt;pwron_txfsiz[i])
+<a name="l01518"></a>01518                         <span class="keywordflow">return</span> 0;
+<a name="l01519"></a>01519                 start_addr += params-&gt;<a class="code" href="structdwc__otg__core__params.html#6e0c5d06467fbf3458f11f7eb8153a8b">dev_tx_fifo_size</a>[i];
+<a name="l01520"></a>01520         }
+<a name="l01521"></a>01521 
+<a name="l01522"></a>01522         <span class="keywordflow">return</span> 1;
+<a name="l01523"></a>01523 }
+<a name="l01524"></a>01524 
+<a name="l01533"></a>01533 <span class="keyword">static</span> uint8_t resize_fifos(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l01534"></a>01534 {
+<a name="l01535"></a>01535         <span class="keywordtype">int</span> i = 0;
+<a name="l01536"></a>01536         <a class="code" href="structdwc__otg__core__global__regs.html">dwc_otg_core_global_regs_t</a> *global_regs = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>;
+<a name="l01537"></a>01537         <a class="code" href="structdwc__otg__core__params.html">dwc_otg_core_params_t</a> *params = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>;
+<a name="l01538"></a>01538         uint32_t rx_fifo_size;
+<a name="l01539"></a>01539         <a class="code" href="unionfifosize__data.html">fifosize_data_t</a> nptxfifosize;
+<a name="l01540"></a>01540         <a class="code" href="unionfifosize__data.html">fifosize_data_t</a> txfifosize[15];
+<a name="l01541"></a>01541 
+<a name="l01542"></a>01542         uint32_t rx_fsz_bak;
+<a name="l01543"></a>01543         uint32_t nptxfsz_bak;
+<a name="l01544"></a>01544         uint32_t txfsz_bak[15];
+<a name="l01545"></a>01545 
+<a name="l01546"></a>01546         uint16_t start_address;
+<a name="l01547"></a>01547         uint8_t retval = 1;
+<a name="l01548"></a>01548 
+<a name="l01549"></a>01549         <span class="keywordflow">if</span> (!check_fifo_sizes(core_if)) {
+<a name="l01550"></a>01550                 <span class="keywordflow">return</span> 0;
+<a name="l01551"></a>01551         }
+<a name="l01552"></a>01552 
+<a name="l01553"></a>01553         <span class="comment">/* Configure data FIFO sizes */</span>
+<a name="l01554"></a>01554         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">hwcfg2</a>.<a class="code" href="unionhwcfg2__data.html#9dcc70e2dba617cbc6c12189be5c1d6a">b</a>.<a class="code" href="unionhwcfg2__data.html#b6bfbfe650352dec82a02d15677fe88d">dynamic_fifo</a> &amp;&amp; params-&gt;<a class="code" href="structdwc__otg__core__params.html#8c169633d4a6f28e964cef9f597c6e03">enable_dynamic_fifo</a>) {
+<a name="l01555"></a>01555                 rx_fsz_bak = dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#b1a8cc07a9541c9a73e864579602b79b">grxfsiz</a>);
+<a name="l01556"></a>01556                 rx_fifo_size = params-&gt;<a class="code" href="structdwc__otg__core__params.html#24ea6f9329f64ac0ad2d31dafe0d1d8c">dev_rx_fifo_size</a>;
+<a name="l01557"></a>01557                 dwc_write_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#b1a8cc07a9541c9a73e864579602b79b">grxfsiz</a>, rx_fifo_size);
+<a name="l01558"></a>01558 
+<a name="l01559"></a>01559                 <span class="comment">/*</span>
+<a name="l01560"></a>01560 <span class="comment">                 * Tx FIFOs These FIFOs are numbered from 1 to 15.</span>
+<a name="l01561"></a>01561 <span class="comment">                 * Indexes of the FIFO size module parameters in the</span>
+<a name="l01562"></a>01562 <span class="comment">                 * dev_tx_fifo_size array and the FIFO size registers in</span>
+<a name="l01563"></a>01563 <span class="comment">                 * the dptxfsiz_dieptxf array run from 0 to 14.</span>
+<a name="l01564"></a>01564 <span class="comment">                 */</span>
+<a name="l01565"></a>01565 
+<a name="l01566"></a>01566                 <span class="comment">/* Non-periodic Tx FIFO */</span>
+<a name="l01567"></a>01567                 nptxfsz_bak = dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#20fb70fe34a1a65d085b1d4e5f8d9106">gnptxfsiz</a>);
+<a name="l01568"></a>01568                 nptxfifosize.<a class="code" href="unionfifosize__data.html#4f0c71e88cc54c4efa4cd4ff43334c51">b</a>.<a class="code" href="unionfifosize__data.html#48c08d73da4d2d16d4320b93beb5ba8b">depth</a> = params-&gt;<a class="code" href="structdwc__otg__core__params.html#d08d9aee1fb4e6508089415d6150176e">dev_nperio_tx_fifo_size</a>;
+<a name="l01569"></a>01569                 start_address = params-&gt;<a class="code" href="structdwc__otg__core__params.html#24ea6f9329f64ac0ad2d31dafe0d1d8c">dev_rx_fifo_size</a>;
+<a name="l01570"></a>01570                 nptxfifosize.<a class="code" href="unionfifosize__data.html#4f0c71e88cc54c4efa4cd4ff43334c51">b</a>.<a class="code" href="unionfifosize__data.html#26d78332a532cf9c0337c89edbff5f1b">startaddr</a> = start_address;
+<a name="l01571"></a>01571 
+<a name="l01572"></a>01572                 dwc_write_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#20fb70fe34a1a65d085b1d4e5f8d9106">gnptxfsiz</a>, nptxfifosize.<a class="code" href="unionfifosize__data.html#937e01b91f0a60a5aa9f6a4eaf6ce661">d32</a>);
+<a name="l01573"></a>01573 
+<a name="l01574"></a>01574                 start_address += nptxfifosize.<a class="code" href="unionfifosize__data.html#4f0c71e88cc54c4efa4cd4ff43334c51">b</a>.<a class="code" href="unionfifosize__data.html#48c08d73da4d2d16d4320b93beb5ba8b">depth</a>;
+<a name="l01575"></a>01575 
+<a name="l01576"></a>01576                 <span class="keywordflow">for</span> (i = 0; i &lt; core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#9c1394f3c46adde2fa7be79bf0237f9b">hwcfg4</a>.<a class="code" href="unionhwcfg4__data.html#9fb9175668e2381c568c5adbf6e5225d">b</a>.<a class="code" href="unionhwcfg4__data.html#753b321350388c5e1307802ff968f9a8">num_in_eps</a>; i++) {
+<a name="l01577"></a>01577                         txfsz_bak[i] =
+<a name="l01578"></a>01578                             dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#efd9e780825f992dbc6cf46d2d72869e">dptxfsiz_dieptxf</a>[i]);
+<a name="l01579"></a>01579 
+<a name="l01580"></a>01580                         txfifosize[i].<a class="code" href="unionfifosize__data.html#4f0c71e88cc54c4efa4cd4ff43334c51">b</a>.<a class="code" href="unionfifosize__data.html#48c08d73da4d2d16d4320b93beb5ba8b">depth</a> = params-&gt;<a class="code" href="structdwc__otg__core__params.html#6e0c5d06467fbf3458f11f7eb8153a8b">dev_tx_fifo_size</a>[i];
+<a name="l01581"></a>01581                         txfifosize[i].<a class="code" href="unionfifosize__data.html#4f0c71e88cc54c4efa4cd4ff43334c51">b</a>.<a class="code" href="unionfifosize__data.html#26d78332a532cf9c0337c89edbff5f1b">startaddr</a> = start_address;
+<a name="l01582"></a>01582                         dwc_write_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#efd9e780825f992dbc6cf46d2d72869e">dptxfsiz_dieptxf</a>[i],
+<a name="l01583"></a>01583                                         txfifosize[i].<a class="code" href="unionfifosize__data.html#937e01b91f0a60a5aa9f6a4eaf6ce661">d32</a>);
+<a name="l01584"></a>01584 
+<a name="l01585"></a>01585                         start_address += txfifosize[i].<a class="code" href="unionfifosize__data.html#4f0c71e88cc54c4efa4cd4ff43334c51">b</a>.<a class="code" href="unionfifosize__data.html#48c08d73da4d2d16d4320b93beb5ba8b">depth</a>;
+<a name="l01586"></a>01586                 }
+<a name="l01587"></a>01587 
+<a name="l01589"></a>01589                 <span class="keywordflow">if</span> (rx_fifo_size != dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#b1a8cc07a9541c9a73e864579602b79b">grxfsiz</a>)) {
+<a name="l01590"></a>01590                         retval = 0;
+<a name="l01591"></a>01591                 }
+<a name="l01592"></a>01592 
+<a name="l01593"></a>01593                 <span class="keywordflow">if</span> (nptxfifosize.<a class="code" href="unionfifosize__data.html#937e01b91f0a60a5aa9f6a4eaf6ce661">d32</a> != dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#20fb70fe34a1a65d085b1d4e5f8d9106">gnptxfsiz</a>)) {
+<a name="l01594"></a>01594                         retval = 0;
+<a name="l01595"></a>01595                 }
+<a name="l01596"></a>01596 
+<a name="l01597"></a>01597                 <span class="keywordflow">for</span> (i = 0; i &lt; core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#9c1394f3c46adde2fa7be79bf0237f9b">hwcfg4</a>.<a class="code" href="unionhwcfg4__data.html#9fb9175668e2381c568c5adbf6e5225d">b</a>.<a class="code" href="unionhwcfg4__data.html#753b321350388c5e1307802ff968f9a8">num_in_eps</a>; i++) {
+<a name="l01598"></a>01598                         <span class="keywordflow">if</span> (txfifosize[i].d32 !=
+<a name="l01599"></a>01599                             dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#efd9e780825f992dbc6cf46d2d72869e">dptxfsiz_dieptxf</a>[i])) {
+<a name="l01600"></a>01600                                 retval = 0;
+<a name="l01601"></a>01601                         }
+<a name="l01602"></a>01602                 }
+<a name="l01603"></a>01603 
+<a name="l01605"></a>01605                 <span class="keywordflow">if</span> (retval == 0) {
+<a name="l01606"></a>01606                         dwc_write_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#b1a8cc07a9541c9a73e864579602b79b">grxfsiz</a>, rx_fsz_bak);
+<a name="l01607"></a>01607 
+<a name="l01608"></a>01608                         <span class="comment">/* Non-periodic Tx FIFO */</span>
+<a name="l01609"></a>01609                         dwc_write_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#20fb70fe34a1a65d085b1d4e5f8d9106">gnptxfsiz</a>, nptxfsz_bak);
+<a name="l01610"></a>01610 
+<a name="l01611"></a>01611                         for (i = 0; i &lt; core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#9c1394f3c46adde2fa7be79bf0237f9b">hwcfg4</a>.<a class="code" href="unionhwcfg4__data.html#9fb9175668e2381c568c5adbf6e5225d">b</a>.<a class="code" href="unionhwcfg4__data.html#753b321350388c5e1307802ff968f9a8">num_in_eps</a>; i++) {
+<a name="l01612"></a>01612                                 dwc_write_reg32(&amp;global_regs-&gt;
+<a name="l01613"></a>01613                                                 dptxfsiz_dieptxf[i],
+<a name="l01614"></a>01614                                                 txfsz_bak[i]);
+<a name="l01615"></a>01615                         }
+<a name="l01616"></a>01616                 }
+<a name="l01617"></a>01617         } <span class="keywordflow">else</span> {
+<a name="l01618"></a>01618                 <span class="keywordflow">return</span> 0;
+<a name="l01619"></a>01619         }
+<a name="l01620"></a>01620 
+<a name="l01621"></a>01621         <span class="comment">/* Flush the FIFOs */</span>
+<a name="l01622"></a>01622         <a class="code" href="dwc__otg__cil_8c.html#039e387cd0e0282727da3c5a36f4cdda">dwc_otg_flush_tx_fifo</a>(core_if, 0x10);   <span class="comment">/* all Tx FIFOs */</span>
+<a name="l01623"></a>01623         <a class="code" href="dwc__otg__cil_8c.html#fb275f0f9923cc30629fce5e3753025c">dwc_otg_flush_rx_fifo</a>(core_if);
+<a name="l01624"></a>01624 
+<a name="l01625"></a>01625         <span class="keywordflow">return</span> retval;
+<a name="l01626"></a>01626 }
+<a name="l01627"></a>01627 
+<a name="l01631"></a>01631 <span class="keyword">static</span> <span class="keywordtype">int</span> cfi_ep_set_tx_fifo_val(uint8_t * buf, <a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd)
+<a name="l01632"></a>01632 {
+<a name="l01633"></a>01633         <span class="keywordtype">int</span> retval;
+<a name="l01634"></a>01634         uint32_t fsiz;
+<a name="l01635"></a>01635         uint16_t size;
+<a name="l01636"></a>01636         uint16_t ep_addr;
+<a name="l01637"></a>01637         <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *ep;
+<a name="l01638"></a>01638         <a class="code" href="structdwc__otg__core__params.html">dwc_otg_core_params_t</a> *params = <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;core_params;
+<a name="l01639"></a>01639         <a class="code" href="struct__tx__fifo__size__setup.html">tx_fifo_size_setup_t</a> *ptxfifoval;
+<a name="l01640"></a>01640 
+<a name="l01641"></a>01641         ptxfifoval = (<a class="code" href="struct__tx__fifo__size__setup.html">tx_fifo_size_setup_t</a> *) buf;
+<a name="l01642"></a>01642         ep_addr = ptxfifoval-&gt;<a class="code" href="struct__tx__fifo__size__setup.html#c04a19a9c0c93d385f7ea42ed38ba0a6">bEndpointAddress</a>;
+<a name="l01643"></a>01643         size = ptxfifoval-&gt;<a class="code" href="struct__tx__fifo__size__setup.html#70fb102a57e335dd8ee56096f3a9f99d">wDepth</a>;
+<a name="l01644"></a>01644 
+<a name="l01645"></a>01645         ep = <a class="code" href="dwc__otg__pcd__intr_8c.html#3c351d7f51d6242296d6ea3bb1a9775c">get_ep_by_addr</a>(pcd, ep_addr);
+<a name="l01646"></a>01646 
+<a name="l01647"></a>01647         <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>
+<a name="l01648"></a>01648             (<span class="stringliteral">"%s: Set Tx FIFO size: endpoint addr=0x%02x, depth=%d, FIFO Num=%d\n"</span>,
+<a name="l01649"></a>01649              __func__, ep_addr, size, ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#ffa14f48094778143353b845b5d238cd">tx_fifo_num</a>);
+<a name="l01650"></a>01650 
+<a name="l01651"></a>01651         <span class="keywordflow">if</span> (NULL == ep) {
+<a name="l01652"></a>01652                 <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>(<span class="stringliteral">"%s: Unable to get the endpoint addr=0x%02x\n"</span>,
+<a name="l01653"></a>01653                          __func__, ep_addr);
+<a name="l01654"></a>01654                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l01655"></a>01655         }
+<a name="l01656"></a>01656 
+<a name="l01657"></a>01657         fsiz = params-&gt;<a class="code" href="structdwc__otg__core__params.html#6e0c5d06467fbf3458f11f7eb8153a8b">dev_tx_fifo_size</a>[ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#ffa14f48094778143353b845b5d238cd">tx_fifo_num</a> - 1];
+<a name="l01658"></a>01658         params-&gt;<a class="code" href="structdwc__otg__core__params.html#6e0c5d06467fbf3458f11f7eb8153a8b">dev_tx_fifo_size</a>[ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#ffa14f48094778143353b845b5d238cd">tx_fifo_num</a> - 1] = size;
+<a name="l01659"></a>01659 
+<a name="l01660"></a>01660         <span class="keywordflow">if</span> (resize_fifos(<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd))) {
+<a name="l01661"></a>01661                 retval = 0;
+<a name="l01662"></a>01662         } <span class="keywordflow">else</span> {
+<a name="l01663"></a>01663                 <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>
+<a name="l01664"></a>01664                     (<span class="stringliteral">"%s: Error setting the feature Tx FIFO Size for EP%d\n"</span>,
+<a name="l01665"></a>01665                      __func__, ep_addr);
+<a name="l01666"></a>01666                 params-&gt;<a class="code" href="structdwc__otg__core__params.html#6e0c5d06467fbf3458f11f7eb8153a8b">dev_tx_fifo_size</a>[ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#ffa14f48094778143353b845b5d238cd">tx_fifo_num</a> - 1] = fsiz;
+<a name="l01667"></a>01667                 retval = -DWC_E_INVALID;
+<a name="l01668"></a>01668         }
+<a name="l01669"></a>01669 
+<a name="l01670"></a>01670         <span class="keywordflow">return</span> retval;
+<a name="l01671"></a>01671 }
+<a name="l01672"></a>01672 
+<a name="l01676"></a>01676 <span class="keyword">static</span> <span class="keywordtype">int</span> cfi_set_rx_fifo_val(uint8_t * buf, <a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd)
+<a name="l01677"></a>01677 {
+<a name="l01678"></a>01678         <span class="keywordtype">int</span> retval;
+<a name="l01679"></a>01679         uint32_t fsiz;
+<a name="l01680"></a>01680         uint16_t size;
+<a name="l01681"></a>01681         <a class="code" href="structdwc__otg__core__params.html">dwc_otg_core_params_t</a> *params = <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;core_params;
+<a name="l01682"></a>01682         <a class="code" href="struct__rx__fifo__size__setup.html">rx_fifo_size_setup_t</a> *prxfifoval;
+<a name="l01683"></a>01683 
+<a name="l01684"></a>01684         prxfifoval = (<a class="code" href="struct__rx__fifo__size__setup.html">rx_fifo_size_setup_t</a> *) buf;
+<a name="l01685"></a>01685         size = prxfifoval-&gt;<a class="code" href="struct__rx__fifo__size__setup.html#a05d30e9417ac8c2ec0fd2c1ec49be71">wDepth</a>;
+<a name="l01686"></a>01686 
+<a name="l01687"></a>01687         fsiz = params-&gt;<a class="code" href="structdwc__otg__core__params.html#24ea6f9329f64ac0ad2d31dafe0d1d8c">dev_rx_fifo_size</a>;
+<a name="l01688"></a>01688         params-&gt;<a class="code" href="structdwc__otg__core__params.html#24ea6f9329f64ac0ad2d31dafe0d1d8c">dev_rx_fifo_size</a> = size;
+<a name="l01689"></a>01689 
+<a name="l01690"></a>01690         <span class="keywordflow">if</span> (resize_fifos(<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd))) {
+<a name="l01691"></a>01691                 retval = 0;
+<a name="l01692"></a>01692         } <span class="keywordflow">else</span> {
+<a name="l01693"></a>01693                 <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>(<span class="stringliteral">"%s: Error setting the feature Rx FIFO Size\n"</span>,
+<a name="l01694"></a>01694                          __func__);
+<a name="l01695"></a>01695                 params-&gt;<a class="code" href="structdwc__otg__core__params.html#24ea6f9329f64ac0ad2d31dafe0d1d8c">dev_rx_fifo_size</a> = fsiz;
+<a name="l01696"></a>01696                 retval = -DWC_E_INVALID;
+<a name="l01697"></a>01697         }
+<a name="l01698"></a>01698 
+<a name="l01699"></a>01699         <span class="keywordflow">return</span> retval;
+<a name="l01700"></a>01700 }
+<a name="l01701"></a>01701 
+<a name="l01705"></a>01705 <span class="keyword">static</span> <span class="keywordtype">int</span> cfi_ep_get_sg_val(uint8_t * buf, <span class="keyword">struct</span> <a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd</a> *pcd,
+<a name="l01706"></a>01706                              <span class="keyword">struct</span> <a class="code" href="structcfi__usb__ctrlrequest.html">cfi_usb_ctrlrequest</a> *req)
+<a name="l01707"></a>01707 {
+<a name="l01708"></a>01708         <span class="keywordtype">int</span> retval = -DWC_E_INVALID;
+<a name="l01709"></a>01709         uint8_t addr;
+<a name="l01710"></a>01710         <a class="code" href="structcfi__ep.html">cfi_ep_t</a> *ep;
+<a name="l01711"></a>01711 
+<a name="l01712"></a>01712         <span class="comment">/* The Low Byte of the wValue contains a non-zero address of the endpoint */</span>
+<a name="l01713"></a>01713         addr = req-&gt;<a class="code" href="structcfi__usb__ctrlrequest.html#2f236bbf9450df1a3b5204c4570d883f">wValue</a> &amp; 0xFF;
+<a name="l01714"></a>01714         <span class="keywordflow">if</span> (addr == 0)          <span class="comment">/* The address should be non-zero */</span>
+<a name="l01715"></a>01715                 <span class="keywordflow">return</span> retval;
+<a name="l01716"></a>01716 
+<a name="l01717"></a>01717         ep = <a class="code" href="dwc__otg__cfi_8h.html#5ece1e51b8534a5cc9a7dd5115bb01ca">get_cfi_ep_by_addr</a>(pcd-&gt;cfi, addr);
+<a name="l01718"></a>01718         <span class="keywordflow">if</span> (NULL == ep) {
+<a name="l01719"></a>01719                 <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>(<span class="stringliteral">"%s: Unable to get the endpoint address(0x%02x)\n"</span>,
+<a name="l01720"></a>01720                          __func__, addr);
+<a name="l01721"></a>01721                 <span class="keywordflow">return</span> retval;
+<a name="l01722"></a>01722         }
+<a name="l01723"></a>01723 
+<a name="l01724"></a>01724         dwc_memcpy(buf, ep-&gt;<a class="code" href="structcfi__ep.html#4010b0f12bf1cd37a2c0bf06b392570a">bm_sg</a>, <a class="code" href="dwc__otg__cfi_8h.html#2332c8839256e2bb1aa1e0e8a9185ce2">BS_SG_VAL_DESC_LEN</a>);
+<a name="l01725"></a>01725         retval = <a class="code" href="dwc__otg__cfi_8h.html#2332c8839256e2bb1aa1e0e8a9185ce2">BS_SG_VAL_DESC_LEN</a>;
+<a name="l01726"></a>01726         <span class="keywordflow">return</span> retval;
+<a name="l01727"></a>01727 }
+<a name="l01728"></a>01728 
+<a name="l01733"></a>01733 <span class="keyword">static</span> <span class="keywordtype">int</span> cfi_ep_get_concat_val(uint8_t * buf, <span class="keyword">struct</span> <a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd</a> *pcd,
+<a name="l01734"></a>01734                                  <span class="keyword">struct</span> <a class="code" href="structcfi__usb__ctrlrequest.html">cfi_usb_ctrlrequest</a> *req)
+<a name="l01735"></a>01735 {
+<a name="l01736"></a>01736         <span class="keywordtype">int</span> retval = -DWC_E_INVALID;
+<a name="l01737"></a>01737         uint8_t addr;
+<a name="l01738"></a>01738         <a class="code" href="structcfi__ep.html">cfi_ep_t</a> *ep;
+<a name="l01739"></a>01739         uint8_t desc_count;
+<a name="l01740"></a>01740 
+<a name="l01741"></a>01741         <span class="comment">/* The Low Byte of the wValue contains a non-zero address of the endpoint */</span>
+<a name="l01742"></a>01742         addr = req-&gt;<a class="code" href="structcfi__usb__ctrlrequest.html#2f236bbf9450df1a3b5204c4570d883f">wValue</a> &amp; 0xFF;
+<a name="l01743"></a>01743         <span class="keywordflow">if</span> (addr == 0)          <span class="comment">/* The address should be non-zero */</span>
+<a name="l01744"></a>01744                 <span class="keywordflow">return</span> retval;
+<a name="l01745"></a>01745 
+<a name="l01746"></a>01746         ep = <a class="code" href="dwc__otg__cfi_8h.html#5ece1e51b8534a5cc9a7dd5115bb01ca">get_cfi_ep_by_addr</a>(pcd-&gt;cfi, addr);
+<a name="l01747"></a>01747         <span class="keywordflow">if</span> (NULL == ep) {
+<a name="l01748"></a>01748                 <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>(<span class="stringliteral">"%s: Unable to get the endpoint address(0x%02x)\n"</span>,
+<a name="l01749"></a>01749                          __func__, addr);
+<a name="l01750"></a>01750                 <span class="keywordflow">return</span> retval;
+<a name="l01751"></a>01751         }
+<a name="l01752"></a>01752 
+<a name="l01753"></a>01753         <span class="comment">/* Copy the header to the buffer */</span>
+<a name="l01754"></a>01754         dwc_memcpy(buf, ep-&gt;<a class="code" href="structcfi__ep.html#4c83b9bb5a75e6b81fbfa86b51736164">bm_concat</a>, <a class="code" href="dwc__otg__cfi_8h.html#c89955571b72df025126a1047bc53a00">BS_CONCAT_VAL_HDR_LEN</a>);
+<a name="l01755"></a>01755         <span class="comment">/* Advance the buffer pointer by the header size */</span>
+<a name="l01756"></a>01756         buf += <a class="code" href="dwc__otg__cfi_8h.html#c89955571b72df025126a1047bc53a00">BS_CONCAT_VAL_HDR_LEN</a>;
+<a name="l01757"></a>01757 
+<a name="l01758"></a>01758         desc_count = ep-&gt;<a class="code" href="structcfi__ep.html#4c83b9bb5a75e6b81fbfa86b51736164">bm_concat</a>-&gt;<a class="code" href="struct__ddma__concat__buffer__setup.html#512cdc8b5ef9053f514443b884ec4730">hdr</a>.<a class="code" href="struct__ddma__concat__buffer__setup__hdr.html#605becc1e8a681d6623343b28013b56a">bDescCount</a>;
+<a name="l01759"></a>01759         <span class="comment">/* Copy alll the wTxBytes to the buffer */</span>
+<a name="l01760"></a>01760         dwc_memcpy(buf, ep-&gt;<a class="code" href="structcfi__ep.html#4c83b9bb5a75e6b81fbfa86b51736164">bm_concat</a>-&gt;<a class="code" href="struct__ddma__concat__buffer__setup.html#748241a5b55a514f4386498aceb1e505">wTxBytes</a>, <span class="keyword">sizeof</span>(uid16_t) * desc_count);
+<a name="l01761"></a>01761 
+<a name="l01762"></a>01762         retval = <a class="code" href="dwc__otg__cfi_8h.html#c89955571b72df025126a1047bc53a00">BS_CONCAT_VAL_HDR_LEN</a> + <span class="keyword">sizeof</span>(uid16_t) * desc_count;
+<a name="l01763"></a>01763         <span class="keywordflow">return</span> retval;
+<a name="l01764"></a>01764 }
+<a name="l01765"></a>01765 
+<a name="l01772"></a>01772 <span class="keyword">static</span> <span class="keywordtype">int</span> cfi_ep_get_align_val(uint8_t * buf, <span class="keyword">struct</span> <a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd</a> *pcd,
+<a name="l01773"></a>01773                                 <span class="keyword">struct</span> <a class="code" href="structcfi__usb__ctrlrequest.html">cfi_usb_ctrlrequest</a> *req)
+<a name="l01774"></a>01774 {
+<a name="l01775"></a>01775         <span class="keywordtype">int</span> retval = -DWC_E_INVALID;
+<a name="l01776"></a>01776         uint8_t addr;
+<a name="l01777"></a>01777         <a class="code" href="structcfi__ep.html">cfi_ep_t</a> *ep;
+<a name="l01778"></a>01778 
+<a name="l01779"></a>01779         <span class="comment">/* The Low Byte of the wValue contains a non-zero address of the endpoint */</span>
+<a name="l01780"></a>01780         addr = req-&gt;<a class="code" href="structcfi__usb__ctrlrequest.html#2f236bbf9450df1a3b5204c4570d883f">wValue</a> &amp; 0xFF;
+<a name="l01781"></a>01781         <span class="keywordflow">if</span> (addr == 0)          <span class="comment">/* The address should be non-zero */</span>
+<a name="l01782"></a>01782                 <span class="keywordflow">return</span> retval;
+<a name="l01783"></a>01783 
+<a name="l01784"></a>01784         ep = <a class="code" href="dwc__otg__cfi_8h.html#5ece1e51b8534a5cc9a7dd5115bb01ca">get_cfi_ep_by_addr</a>(pcd-&gt;cfi, addr);
+<a name="l01785"></a>01785         <span class="keywordflow">if</span> (NULL == ep) {
+<a name="l01786"></a>01786                 <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>(<span class="stringliteral">"%s: Unable to get the endpoint address(0x%02x)\n"</span>,
+<a name="l01787"></a>01787                          __func__, addr);
+<a name="l01788"></a>01788                 <span class="keywordflow">return</span> retval;
+<a name="l01789"></a>01789         }
+<a name="l01790"></a>01790 
+<a name="l01791"></a>01791         dwc_memcpy(buf, ep-&gt;<a class="code" href="structcfi__ep.html#bb544b7938d0c62857fc3726988310d2">bm_align</a>, <a class="code" href="dwc__otg__cfi_8h.html#5495ec473ea2d7c8f805567416c559f0">BS_ALIGN_VAL_HDR_LEN</a>);
+<a name="l01792"></a>01792         retval = <a class="code" href="dwc__otg__cfi_8h.html#5495ec473ea2d7c8f805567416c559f0">BS_ALIGN_VAL_HDR_LEN</a>;
+<a name="l01793"></a>01793 
+<a name="l01794"></a>01794         <span class="keywordflow">return</span> retval;
+<a name="l01795"></a>01795 }
+<a name="l01796"></a>01796 
+<a name="l01804"></a>01804 <span class="keyword">static</span> <span class="keywordtype">int</span> cfi_set_feature_value(<span class="keyword">struct</span> <a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd</a> *pcd)
+<a name="l01805"></a>01805 {
+<a name="l01806"></a>01806         <span class="keywordtype">int</span> retval = -DWC_E_NOT_SUPPORTED;
+<a name="l01807"></a>01807         uint16_t wIndex, wValue;
+<a name="l01808"></a>01808         uint8_t bRequest;
+<a name="l01809"></a>01809         <span class="keyword">struct </span><a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if</a> *coreif;
+<a name="l01810"></a>01810         <a class="code" href="structcfiobject.html">cfiobject_t</a> *cfi = pcd-&gt;cfi;
+<a name="l01811"></a>01811         <span class="keyword">struct </span><a class="code" href="structcfi__usb__ctrlrequest.html">cfi_usb_ctrlrequest</a> *ctrl_req;
+<a name="l01812"></a>01812         uint8_t *buf;
+<a name="l01813"></a>01813         ctrl_req = &amp;cfi-&gt;<a class="code" href="structcfiobject.html#a86c33aef2a521a27ca515bb7397dd34">ctrl_req</a>;
+<a name="l01814"></a>01814 
+<a name="l01815"></a>01815         buf = pcd-&gt;cfi-&gt;ctrl_req.data;
+<a name="l01816"></a>01816 
+<a name="l01817"></a>01817         coreif = <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd);
+<a name="l01818"></a>01818         bRequest = ctrl_req-&gt;<a class="code" href="structcfi__usb__ctrlrequest.html#b3083f525fa9bb97e41364418daee3fa">bRequest</a>;
+<a name="l01819"></a>01819         wIndex = DWC_CONSTANT_CPU_TO_LE16(ctrl_req-&gt;<a class="code" href="structcfi__usb__ctrlrequest.html#984c95bd61e8d1120cd935bcbc5d7134">wIndex</a>);
+<a name="l01820"></a>01820         wValue = DWC_CONSTANT_CPU_TO_LE16(ctrl_req-&gt;<a class="code" href="structcfi__usb__ctrlrequest.html#2f236bbf9450df1a3b5204c4570d883f">wValue</a>);
+<a name="l01821"></a>01821 
+<a name="l01822"></a>01822         <span class="comment">/* See which feature is to be modified */</span>
+<a name="l01823"></a>01823         <span class="keywordflow">switch</span> (wIndex) {
+<a name="l01824"></a>01824         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__cfi_8h.html#98840b45640251bfafa3481260aef889">FT_ID_DMA_BUFFER_SETUP</a>:
+<a name="l01825"></a>01825                 <span class="comment">/* Modify the feature */</span>
+<a name="l01826"></a>01826                 <span class="keywordflow">if</span> ((retval = cfi_ep_set_sg_val(buf, pcd)) &lt; 0)
+<a name="l01827"></a>01827                         <span class="keywordflow">return</span> retval;
+<a name="l01828"></a>01828 
+<a name="l01829"></a>01829                 <span class="comment">/* And send this request to the gadget */</span>
+<a name="l01830"></a>01830                 cfi-&gt;<a class="code" href="structcfiobject.html#f103d681f78c43dc92dd4a85cdbdc27c">need_gadget_att</a> = 1;
+<a name="l01831"></a>01831                 <span class="keywordflow">break</span>;
+<a name="l01832"></a>01832 
+<a name="l01833"></a>01833         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__cfi_8h.html#9335284cd4dae01f4bc0da7cb89d5ef4">FT_ID_DMA_BUFF_ALIGN</a>:
+<a name="l01834"></a>01834                 <span class="keywordflow">if</span> ((retval = cfi_ep_set_alignment_val(buf, pcd)) &lt; 0)
+<a name="l01835"></a>01835                         <span class="keywordflow">return</span> retval;
+<a name="l01836"></a>01836                 cfi-&gt;<a class="code" href="structcfiobject.html#f103d681f78c43dc92dd4a85cdbdc27c">need_gadget_att</a> = 1;
+<a name="l01837"></a>01837                 <span class="keywordflow">break</span>;
+<a name="l01838"></a>01838 
+<a name="l01839"></a>01839         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__cfi_8h.html#779a11db5843dd058581d93c8232bd7c">FT_ID_DMA_CONCAT_SETUP</a>:
+<a name="l01840"></a>01840                 <span class="comment">/* Modify the feature */</span>
+<a name="l01841"></a>01841                 <span class="keywordflow">if</span> ((retval = cfi_ep_set_concat_val(buf, pcd)) &lt; 0)
+<a name="l01842"></a>01842                         <span class="keywordflow">return</span> retval;
+<a name="l01843"></a>01843                 cfi-&gt;<a class="code" href="structcfiobject.html#f103d681f78c43dc92dd4a85cdbdc27c">need_gadget_att</a> = 1;
+<a name="l01844"></a>01844                 <span class="keywordflow">break</span>;
+<a name="l01845"></a>01845 
+<a name="l01846"></a>01846         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__cfi_8h.html#8db5bfce321e02d42b742e9deedfa665">FT_ID_DMA_CIRCULAR</a>:
+<a name="l01847"></a>01847                 <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>(<span class="stringliteral">"FT_ID_DMA_CIRCULAR\n"</span>);
+<a name="l01848"></a>01848                 <span class="keywordflow">break</span>;
+<a name="l01849"></a>01849 
+<a name="l01850"></a>01850         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__cfi_8h.html#bcc99a9e5a0b15b4212d88bd9c610647">FT_ID_THRESHOLD_SETUP</a>:
+<a name="l01851"></a>01851                 <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>(<span class="stringliteral">"FT_ID_THRESHOLD_SETUP\n"</span>);
+<a name="l01852"></a>01852                 <span class="keywordflow">break</span>;
+<a name="l01853"></a>01853 
+<a name="l01854"></a>01854         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__cfi_8h.html#54b879727edcb06acdd11968ec60d249">FT_ID_DFIFO_DEPTH</a>:
+<a name="l01855"></a>01855                 <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>(<span class="stringliteral">"FT_ID_DFIFO_DEPTH\n"</span>);
+<a name="l01856"></a>01856                 <span class="keywordflow">break</span>;
+<a name="l01857"></a>01857 
+<a name="l01858"></a>01858         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__cfi_8h.html#a3a67b679a59c5279370bbf69f114cb6">FT_ID_TX_FIFO_DEPTH</a>:
+<a name="l01859"></a>01859                 <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>(<span class="stringliteral">"FT_ID_TX_FIFO_DEPTH\n"</span>);
+<a name="l01860"></a>01860                 <span class="keywordflow">if</span> ((retval = cfi_ep_set_tx_fifo_val(buf, pcd)) &lt; 0)
+<a name="l01861"></a>01861                         <span class="keywordflow">return</span> retval;
+<a name="l01862"></a>01862                 cfi-&gt;<a class="code" href="structcfiobject.html#f103d681f78c43dc92dd4a85cdbdc27c">need_gadget_att</a> = 0;
+<a name="l01863"></a>01863                 <span class="keywordflow">break</span>;
+<a name="l01864"></a>01864 
+<a name="l01865"></a>01865         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__cfi_8h.html#42b7c98c105de1f9399786a3419e7e20">FT_ID_RX_FIFO_DEPTH</a>:
+<a name="l01866"></a>01866                 <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>(<span class="stringliteral">"FT_ID_RX_FIFO_DEPTH\n"</span>);
+<a name="l01867"></a>01867                 <span class="keywordflow">if</span> ((retval = cfi_set_rx_fifo_val(buf, pcd)) &lt; 0)
+<a name="l01868"></a>01868                         <span class="keywordflow">return</span> retval;
+<a name="l01869"></a>01869                 cfi-&gt;<a class="code" href="structcfiobject.html#f103d681f78c43dc92dd4a85cdbdc27c">need_gadget_att</a> = 0;
+<a name="l01870"></a>01870                 <span class="keywordflow">break</span>;
+<a name="l01871"></a>01871         }
+<a name="l01872"></a>01872 
+<a name="l01873"></a>01873         <span class="keywordflow">return</span> retval;
+<a name="l01874"></a>01874 }
+<a name="l01875"></a>01875 
+<a name="l01876"></a>01876 <span class="preprocessor">#endif                          //DWC_UTE_CFI</span>
+</pre></div><hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cfi_8c.html b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cfi_8c.html
new file mode 100644
index 000000000000..44402b4f174b
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cfi_8c.html
@@ -0,0 +1,36 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_cfi.c File Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<h1>dwc_otg_cfi.c File Reference</h1>This file contains the most of the CFI implementation for the OTG. <a href="#_details">More...</a>
+<p>
+
+<p>
+<a href="dwc__otg__cfi_8c-source.html">Go to the source code of this file.</a><table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This file contains the most of the CFI implementation for the OTG. 
+<p>
+
+<p>
+Definition in file <a class="el" href="dwc__otg__cfi_8c-source.html">dwc_otg_cfi.c</a>.<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cfi_8h-source.html b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cfi_8h-source.html
new file mode 100644
index 000000000000..28a9d364006a
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cfi_8h-source.html
@@ -0,0 +1,299 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_cfi.h Source File</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<h1>dwc_otg_cfi.h</h1><a href="dwc__otg__cfi_8h.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">/* ==========================================================================</span>
+<a name="l00002"></a>00002 <span class="comment"> * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,</span>
+<a name="l00003"></a>00003 <span class="comment"> * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless</span>
+<a name="l00004"></a>00004 <span class="comment"> * otherwise expressly agreed to in writing between Synopsys and you.</span>
+<a name="l00005"></a>00005 <span class="comment"> * </span>
+<a name="l00006"></a>00006 <span class="comment"> * The Software IS NOT an item of Licensed Software or Licensed Product under</span>
+<a name="l00007"></a>00007 <span class="comment"> * any End User Software License Agreement or Agreement for Licensed Product</span>
+<a name="l00008"></a>00008 <span class="comment"> * with Synopsys or any supplement thereto. You are permitted to use and</span>
+<a name="l00009"></a>00009 <span class="comment"> * redistribute this Software in source and binary forms, with or without</span>
+<a name="l00010"></a>00010 <span class="comment"> * modification, provided that redistributions of source code must retain this</span>
+<a name="l00011"></a>00011 <span class="comment"> * notice. You may not view, use, disclose, copy or distribute this file or</span>
+<a name="l00012"></a>00012 <span class="comment"> * any information contained herein except pursuant to this license grant from</span>
+<a name="l00013"></a>00013 <span class="comment"> * Synopsys. If you do not agree with this notice, including the disclaimer</span>
+<a name="l00014"></a>00014 <span class="comment"> * below, then you are not authorized to use the Software.</span>
+<a name="l00015"></a>00015 <span class="comment"> * </span>
+<a name="l00016"></a>00016 <span class="comment"> * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS</span>
+<a name="l00017"></a>00017 <span class="comment"> * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE</span>
+<a name="l00018"></a>00018 <span class="comment"> * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE</span>
+<a name="l00019"></a>00019 <span class="comment"> * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,</span>
+<a name="l00020"></a>00020 <span class="comment"> * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES</span>
+<a name="l00021"></a>00021 <span class="comment"> * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR</span>
+<a name="l00022"></a>00022 <span class="comment"> * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER</span>
+<a name="l00023"></a>00023 <span class="comment"> * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT</span>
+<a name="l00024"></a>00024 <span class="comment"> * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY</span>
+<a name="l00025"></a>00025 <span class="comment"> * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH</span>
+<a name="l00026"></a>00026 <span class="comment"> * DAMAGE.</span>
+<a name="l00027"></a>00027 <span class="comment"> * ========================================================================== */</span>
+<a name="l00028"></a>00028 
+<a name="l00029"></a>00029 <span class="preprocessor">#if !defined(__DWC_OTG_CFI_H__)</span>
+<a name="l00030"></a><a class="code" href="dwc__otg__cfi_8h.html#d4efa118a5f5c82587650944721a8dc1">00030</a> <span class="preprocessor"></span><span class="preprocessor">#define __DWC_OTG_CFI_H__</span>
+<a name="l00031"></a>00031 <span class="preprocessor"></span>
+<a name="l00032"></a>00032 <span class="preprocessor">#include "<a class="code" href="dwc__otg__pcd_8h.html">dwc_otg_pcd.h</a>"</span>
+<a name="l00033"></a>00033 <span class="preprocessor">#include "<a class="code" href="dwc__cfi__common_8h.html">dwc_cfi_common.h</a>"</span>
+<a name="l00034"></a>00034 
+<a name="l00043"></a>00043 <span class="keyword">struct </span><a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd</a>;
+<a name="l00044"></a>00044 <span class="keyword">struct </span><a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep</a>;
+<a name="l00045"></a>00045 
+<a name="l00048"></a><a class="code" href="dwc__otg__cfi_8h.html#0e196868939f6bbf0d157868bfc90208">00048</a> <span class="preprocessor">#define FT_ID_DMA_MODE                                  0x0001</span>
+<a name="l00049"></a><a class="code" href="dwc__otg__cfi_8h.html#98840b45640251bfafa3481260aef889">00049</a> <span class="preprocessor"></span><span class="preprocessor">#define FT_ID_DMA_BUFFER_SETUP                  0x0002</span>
+<a name="l00050"></a><a class="code" href="dwc__otg__cfi_8h.html#9335284cd4dae01f4bc0da7cb89d5ef4">00050</a> <span class="preprocessor"></span><span class="preprocessor">#define FT_ID_DMA_BUFF_ALIGN                    0x0003</span>
+<a name="l00051"></a><a class="code" href="dwc__otg__cfi_8h.html#779a11db5843dd058581d93c8232bd7c">00051</a> <span class="preprocessor"></span><span class="preprocessor">#define FT_ID_DMA_CONCAT_SETUP                  0x0004</span>
+<a name="l00052"></a><a class="code" href="dwc__otg__cfi_8h.html#8db5bfce321e02d42b742e9deedfa665">00052</a> <span class="preprocessor"></span><span class="preprocessor">#define FT_ID_DMA_CIRCULAR                              0x0005</span>
+<a name="l00053"></a><a class="code" href="dwc__otg__cfi_8h.html#bcc99a9e5a0b15b4212d88bd9c610647">00053</a> <span class="preprocessor"></span><span class="preprocessor">#define FT_ID_THRESHOLD_SETUP                   0x0006</span>
+<a name="l00054"></a><a class="code" href="dwc__otg__cfi_8h.html#54b879727edcb06acdd11968ec60d249">00054</a> <span class="preprocessor"></span><span class="preprocessor">#define FT_ID_DFIFO_DEPTH                               0x0007</span>
+<a name="l00055"></a><a class="code" href="dwc__otg__cfi_8h.html#a3a67b679a59c5279370bbf69f114cb6">00055</a> <span class="preprocessor"></span><span class="preprocessor">#define FT_ID_TX_FIFO_DEPTH                             0x0008</span>
+<a name="l00056"></a><a class="code" href="dwc__otg__cfi_8h.html#42b7c98c105de1f9399786a3419e7e20">00056</a> <span class="preprocessor"></span><span class="preprocessor">#define FT_ID_RX_FIFO_DEPTH                             0x0009</span>
+<a name="l00057"></a>00057 <span class="preprocessor"></span>
+<a name="l00058"></a>00058 <span class="comment">/**********************************************************/</span>
+<a name="l00059"></a><a class="code" href="dwc__otg__cfi_8h.html#7f62f8d1e9825c09b1f7d2badbe2527a">00059</a> <span class="preprocessor">#define CFI_INFO_DEF</span>
+<a name="l00060"></a>00060 <span class="preprocessor"></span>
+<a name="l00061"></a>00061 <span class="preprocessor">#ifdef CFI_INFO_DEF</span>
+<a name="l00062"></a><a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">00062</a> <span class="preprocessor"></span><span class="preprocessor">#define CFI_INFO(fmt...)        DWC_PRINTF("CFI: " fmt);</span>
+<a name="l00063"></a>00063 <span class="preprocessor"></span><span class="preprocessor">#else</span>
+<a name="l00064"></a>00064 <span class="preprocessor"></span><span class="preprocessor">#define CFI_INFO(fmt...)</span>
+<a name="l00065"></a>00065 <span class="preprocessor"></span><span class="preprocessor">#endif</span>
+<a name="l00066"></a>00066 <span class="preprocessor"></span>
+<a name="l00067"></a><a class="code" href="dwc__otg__cfi_8h.html#7c9949b9e692a8360832aedfa1843657">00067</a> <span class="preprocessor">#define min(x,y) ({ \</span>
+<a name="l00068"></a>00068 <span class="preprocessor">        x &lt; y ? x : y; })</span>
+<a name="l00069"></a>00069 <span class="preprocessor"></span>
+<a name="l00070"></a><a class="code" href="dwc__otg__cfi_8h.html#4755d18ce5205f644e5cd02db7f4ada5">00070</a> <span class="preprocessor">#define max(x,y) ({ \</span>
+<a name="l00071"></a>00071 <span class="preprocessor">        x &gt; y ? x : y; })</span>
+<a name="l00072"></a>00072 <span class="preprocessor"></span>
+<a name="l00077"></a><a class="code" href="struct__ddma__sg__buffer__setup.html">00077</a> <span class="keyword">struct </span><a class="code" href="struct__ddma__sg__buffer__setup.html">_ddma_sg_buffer_setup</a> {
+<a name="l00078"></a><a class="code" href="dwc__otg__cfi_8h.html#2332c8839256e2bb1aa1e0e8a9185ce2">00078</a> <span class="preprocessor">#define BS_SG_VAL_DESC_LEN      6</span>
+<a name="l00079"></a>00079 <span class="preprocessor"></span>        <span class="comment">/* The OUT EP address */</span>
+<a name="l00080"></a><a class="code" href="struct__ddma__sg__buffer__setup.html#b61eaff3e4857fd6223d9fc678814786">00080</a>         uint8_t <a class="code" href="struct__ddma__sg__buffer__setup.html#b61eaff3e4857fd6223d9fc678814786">bOutEndpointAddress</a>;
+<a name="l00081"></a>00081         <span class="comment">/* The IN EP address */</span>
+<a name="l00082"></a><a class="code" href="struct__ddma__sg__buffer__setup.html#bb435a2ac72bfd26384c9b5b1b0b35af">00082</a>         uint8_t <a class="code" href="struct__ddma__sg__buffer__setup.html#bb435a2ac72bfd26384c9b5b1b0b35af">bInEndpointAddress</a>;
+<a name="l00083"></a>00083         <span class="comment">/* Number of bytes to put between transfer segments (must be DWORD boundaries) */</span>
+<a name="l00084"></a><a class="code" href="struct__ddma__sg__buffer__setup.html#5ab16a208d20dd6940ecfd3244e2b9c0">00084</a>         uint8_t <a class="code" href="struct__ddma__sg__buffer__setup.html#5ab16a208d20dd6940ecfd3244e2b9c0">bOffset</a>;
+<a name="l00085"></a>00085         <span class="comment">/* The number of transfer segments (a DMA descriptors per each segment) */</span>
+<a name="l00086"></a><a class="code" href="struct__ddma__sg__buffer__setup.html#6287daf5a964bf1d09e8ffca29b88748">00086</a>         uint8_t <a class="code" href="struct__ddma__sg__buffer__setup.html#6287daf5a964bf1d09e8ffca29b88748">bCount</a>;
+<a name="l00087"></a>00087         <span class="comment">/* Size (in byte) of each transfer segment */</span>
+<a name="l00088"></a><a class="code" href="struct__ddma__sg__buffer__setup.html#728db9bac2db62f7e7b2b9ccb0873546">00088</a>         uint16_t <a class="code" href="struct__ddma__sg__buffer__setup.html#728db9bac2db62f7e7b2b9ccb0873546">wSize</a>;
+<a name="l00089"></a>00089 } __attribute__ ((<a class="code" href="dwc__otg__cfi_8h.html#1c517724be71d3c12952486ba172c0b6">packed</a>));
+<a name="l00090"></a><a class="code" href="dwc__otg__cfi_8h.html#1040b884c9adf08c1106ffdf9f191ad4">00090</a> <span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code" href="struct__ddma__sg__buffer__setup.html">_ddma_sg_buffer_setup</a> <a class="code" href="dwc__otg__cfi_8h.html#1040b884c9adf08c1106ffdf9f191ad4">ddma_sg_buffer_setup_t</a>;
+<a name="l00091"></a>00091 
+<a name="l00093"></a><a class="code" href="struct__ddma__concat__buffer__setup__hdr.html">00093</a> <span class="keyword">struct </span><a class="code" href="struct__ddma__concat__buffer__setup__hdr.html">_ddma_concat_buffer_setup_hdr</a> {
+<a name="l00094"></a><a class="code" href="dwc__otg__cfi_8h.html#c89955571b72df025126a1047bc53a00">00094</a> <span class="preprocessor">#define BS_CONCAT_VAL_HDR_LEN   4</span>
+<a name="l00095"></a>00095 <span class="preprocessor"></span>        <span class="comment">/* The endpoint for which the buffer is to be set up */</span>
+<a name="l00096"></a><a class="code" href="struct__ddma__concat__buffer__setup__hdr.html#b6e4aab1ee8884a314ba38326ea85f24">00096</a>         uint8_t <a class="code" href="struct__ddma__concat__buffer__setup__hdr.html#b6e4aab1ee8884a314ba38326ea85f24">bEndpointAddress</a>;
+<a name="l00097"></a>00097         <span class="comment">/* The count of descriptors to be used */</span>
+<a name="l00098"></a><a class="code" href="struct__ddma__concat__buffer__setup__hdr.html#605becc1e8a681d6623343b28013b56a">00098</a>         uint8_t <a class="code" href="struct__ddma__concat__buffer__setup__hdr.html#605becc1e8a681d6623343b28013b56a">bDescCount</a>;
+<a name="l00099"></a>00099         <span class="comment">/* The total size of the transfer */</span>
+<a name="l00100"></a><a class="code" href="struct__ddma__concat__buffer__setup__hdr.html#d59713609608ce8aab53c43332073ef7">00100</a>         uint16_t <a class="code" href="struct__ddma__concat__buffer__setup__hdr.html#d59713609608ce8aab53c43332073ef7">wSize</a>;
+<a name="l00101"></a>00101 } __attribute__ ((<a class="code" href="dwc__otg__cfi_8h.html#1c517724be71d3c12952486ba172c0b6">packed</a>));
+<a name="l00102"></a><a class="code" href="dwc__otg__cfi_8h.html#a6fccd9def2a83408bdb10eb7964a4d6">00102</a> <span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code" href="struct__ddma__concat__buffer__setup__hdr.html">_ddma_concat_buffer_setup_hdr</a> <a class="code" href="dwc__otg__cfi_8h.html#a6fccd9def2a83408bdb10eb7964a4d6">ddma_concat_buffer_setup_hdr_t</a>;
+<a name="l00103"></a>00103 
+<a name="l00105"></a><a class="code" href="struct__ddma__concat__buffer__setup.html">00105</a> <span class="keyword">struct </span><a class="code" href="struct__ddma__concat__buffer__setup.html">_ddma_concat_buffer_setup</a> {
+<a name="l00106"></a>00106         <span class="comment">/* The SG header */</span>
+<a name="l00107"></a><a class="code" href="struct__ddma__concat__buffer__setup.html#512cdc8b5ef9053f514443b884ec4730">00107</a>         <a class="code" href="dwc__otg__cfi_8h.html#a6fccd9def2a83408bdb10eb7964a4d6">ddma_concat_buffer_setup_hdr_t</a> <a class="code" href="struct__ddma__concat__buffer__setup.html#512cdc8b5ef9053f514443b884ec4730">hdr</a>;
+<a name="l00108"></a>00108 
+<a name="l00109"></a>00109         <span class="comment">/* The XFER sizes pointer (allocated dynamically) */</span>
+<a name="l00110"></a><a class="code" href="struct__ddma__concat__buffer__setup.html#748241a5b55a514f4386498aceb1e505">00110</a>         uint16_t *<a class="code" href="struct__ddma__concat__buffer__setup.html#748241a5b55a514f4386498aceb1e505">wTxBytes</a>;
+<a name="l00111"></a>00111 } __attribute__ ((<a class="code" href="dwc__otg__cfi_8h.html#1c517724be71d3c12952486ba172c0b6">packed</a>));
+<a name="l00112"></a><a class="code" href="dwc__otg__cfi_8h.html#083bc35d34ae5489588bb581fc45ae73">00112</a> <span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code" href="struct__ddma__concat__buffer__setup.html">_ddma_concat_buffer_setup</a> <a class="code" href="dwc__otg__cfi_8h.html#083bc35d34ae5489588bb581fc45ae73">ddma_concat_buffer_setup_t</a>;
+<a name="l00113"></a>00113 
+<a name="l00115"></a><a class="code" href="struct__ddma__align__buffer__setup.html">00115</a> <span class="keyword">struct </span><a class="code" href="struct__ddma__align__buffer__setup.html">_ddma_align_buffer_setup</a> {
+<a name="l00116"></a><a class="code" href="dwc__otg__cfi_8h.html#5495ec473ea2d7c8f805567416c559f0">00116</a> <span class="preprocessor">#define BS_ALIGN_VAL_HDR_LEN    2</span>
+<a name="l00117"></a><a class="code" href="struct__ddma__align__buffer__setup.html#28008cbe6479b7473aa21ac2d3ceaf67">00117</a> <span class="preprocessor"></span>        uint8_t <a class="code" href="struct__ddma__align__buffer__setup.html#28008cbe6479b7473aa21ac2d3ceaf67">bEndpointAddress</a>;
+<a name="l00118"></a><a class="code" href="struct__ddma__align__buffer__setup.html#1cc0ba7e2c2a435cce1d502732ce07a1">00118</a>         uint8_t <a class="code" href="struct__ddma__align__buffer__setup.html#1cc0ba7e2c2a435cce1d502732ce07a1">bAlign</a>;
+<a name="l00119"></a>00119 } __attribute__ ((<a class="code" href="dwc__otg__cfi_8h.html#1c517724be71d3c12952486ba172c0b6">packed</a>));
+<a name="l00120"></a><a class="code" href="dwc__otg__cfi_8h.html#f60b107e43f0edf8ac94f781803c8780">00120</a> <span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code" href="struct__ddma__align__buffer__setup.html">_ddma_align_buffer_setup</a> <a class="code" href="dwc__otg__cfi_8h.html#f60b107e43f0edf8ac94f781803c8780">ddma_align_buffer_setup_t</a>;
+<a name="l00121"></a>00121 
+<a name="l00123"></a><a class="code" href="struct__tx__fifo__size__setup.html">00123</a> <span class="keyword">struct </span><a class="code" href="struct__tx__fifo__size__setup.html">_tx_fifo_size_setup</a> {
+<a name="l00124"></a><a class="code" href="struct__tx__fifo__size__setup.html#c04a19a9c0c93d385f7ea42ed38ba0a6">00124</a>         uint8_t <a class="code" href="struct__tx__fifo__size__setup.html#c04a19a9c0c93d385f7ea42ed38ba0a6">bEndpointAddress</a>;
+<a name="l00125"></a><a class="code" href="struct__tx__fifo__size__setup.html#70fb102a57e335dd8ee56096f3a9f99d">00125</a>         uint16_t <a class="code" href="struct__tx__fifo__size__setup.html#70fb102a57e335dd8ee56096f3a9f99d">wDepth</a>;
+<a name="l00126"></a>00126 } __attribute__ ((<a class="code" href="dwc__otg__cfi_8h.html#1c517724be71d3c12952486ba172c0b6">packed</a>));
+<a name="l00127"></a><a class="code" href="dwc__otg__cfi_8h.html#9da70e9326ec40c9f1bd9c487aabe4c1">00127</a> <span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code" href="struct__tx__fifo__size__setup.html">_tx_fifo_size_setup</a> <a class="code" href="dwc__otg__cfi_8h.html#9da70e9326ec40c9f1bd9c487aabe4c1">tx_fifo_size_setup_t</a>;
+<a name="l00128"></a>00128 
+<a name="l00130"></a><a class="code" href="struct__rx__fifo__size__setup.html">00130</a> <span class="keyword">struct </span><a class="code" href="struct__rx__fifo__size__setup.html">_rx_fifo_size_setup</a> {
+<a name="l00131"></a><a class="code" href="struct__rx__fifo__size__setup.html#a05d30e9417ac8c2ec0fd2c1ec49be71">00131</a>         uint16_t <a class="code" href="struct__rx__fifo__size__setup.html#a05d30e9417ac8c2ec0fd2c1ec49be71">wDepth</a>;
+<a name="l00132"></a>00132 } __attribute__ ((<a class="code" href="dwc__otg__cfi_8h.html#1c517724be71d3c12952486ba172c0b6">packed</a>));
+<a name="l00133"></a><a class="code" href="dwc__otg__cfi_8h.html#0fbbd60333457c6667bd7757e4aac2f8">00133</a> <span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code" href="struct__rx__fifo__size__setup.html">_rx_fifo_size_setup</a> <a class="code" href="dwc__otg__cfi_8h.html#0fbbd60333457c6667bd7757e4aac2f8">rx_fifo_size_setup_t</a>;
+<a name="l00134"></a>00134 
+<a name="l00140"></a><a class="code" href="structcfi__usb__ctrlrequest.html">00140</a> <span class="keyword">struct </span><a class="code" href="structcfi__usb__ctrlrequest.html">cfi_usb_ctrlrequest</a> {
+<a name="l00141"></a><a class="code" href="structcfi__usb__ctrlrequest.html#6ba267845c2907b3908d3761c252b10c">00141</a>         uint8_t <a class="code" href="structcfi__usb__ctrlrequest.html#6ba267845c2907b3908d3761c252b10c">bRequestType</a>;
+<a name="l00142"></a><a class="code" href="structcfi__usb__ctrlrequest.html#b3083f525fa9bb97e41364418daee3fa">00142</a>         uint8_t <a class="code" href="structcfi__usb__ctrlrequest.html#b3083f525fa9bb97e41364418daee3fa">bRequest</a>;
+<a name="l00143"></a><a class="code" href="structcfi__usb__ctrlrequest.html#2f236bbf9450df1a3b5204c4570d883f">00143</a>         uint16_t <a class="code" href="structcfi__usb__ctrlrequest.html#2f236bbf9450df1a3b5204c4570d883f">wValue</a>;
+<a name="l00144"></a><a class="code" href="structcfi__usb__ctrlrequest.html#984c95bd61e8d1120cd935bcbc5d7134">00144</a>         uint16_t <a class="code" href="structcfi__usb__ctrlrequest.html#984c95bd61e8d1120cd935bcbc5d7134">wIndex</a>;
+<a name="l00145"></a><a class="code" href="structcfi__usb__ctrlrequest.html#60d71d1239e46e787f0b4c626de7c769">00145</a>         uint16_t <a class="code" href="structcfi__usb__ctrlrequest.html#60d71d1239e46e787f0b4c626de7c769">wLength</a>;
+<a name="l00146"></a><a class="code" href="structcfi__usb__ctrlrequest.html#5b3865e9cb2c0fcf373b1c862a63c180">00146</a>         uint8_t *<a class="code" href="structcfi__usb__ctrlrequest.html#5b3865e9cb2c0fcf373b1c862a63c180">data</a>;
+<a name="l00147"></a>00147 } <a class="code" href="dwc__cfi__common_8h.html#ec5d43311fa60a5ef0519797208df057">UPACKED</a>;
+<a name="l00148"></a>00148 
+<a name="l00149"></a>00149 <span class="comment">/*---------------------------------------------------------------------------*/</span>
+<a name="l00150"></a>00150 
+<a name="l00156"></a><a class="code" href="structcfi__ep.html">00156</a> <span class="keyword">struct </span><a class="code" href="structcfi__ep.html">cfi_ep</a> {
+<a name="l00157"></a>00157         <span class="comment">/* Entry for the list container */</span>
+<a name="l00158"></a><a class="code" href="structcfi__ep.html#18bff3370dc933cd374d458897dfbc2f">00158</a>         dwc_list_link_t <a class="code" href="structcfi__ep.html#18bff3370dc933cd374d458897dfbc2f">lh</a>;
+<a name="l00159"></a>00159         <span class="comment">/* Pointer to the active PCD endpoint structure */</span>
+<a name="l00160"></a><a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">00160</a>         <span class="keyword">struct </span><a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep</a> *<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>;
+<a name="l00161"></a>00161         <span class="comment">/* The last descriptor in the chain of DMA descriptors of the endpoint */</span>
+<a name="l00162"></a><a class="code" href="structcfi__ep.html#3f4e5c42f279663ee0065ffce4f44783">00162</a>         <span class="keyword">struct </span>dwc_otg_dma_desc *<a class="code" href="structcfi__ep.html#3f4e5c42f279663ee0065ffce4f44783">dma_desc_last</a>;
+<a name="l00163"></a>00163         <span class="comment">/* The SG feature value */</span>
+<a name="l00164"></a><a class="code" href="structcfi__ep.html#4010b0f12bf1cd37a2c0bf06b392570a">00164</a>         <a class="code" href="dwc__otg__cfi_8h.html#1040b884c9adf08c1106ffdf9f191ad4">ddma_sg_buffer_setup_t</a> *<a class="code" href="structcfi__ep.html#4010b0f12bf1cd37a2c0bf06b392570a">bm_sg</a>;
+<a name="l00165"></a>00165         <span class="comment">/* The Circular feature value */</span>
+<a name="l00166"></a><a class="code" href="structcfi__ep.html#3ab8ca6103c0483f2fefce0dc1684eaa">00166</a>         <a class="code" href="dwc__otg__cfi_8h.html#1040b884c9adf08c1106ffdf9f191ad4">ddma_sg_buffer_setup_t</a> *<a class="code" href="structcfi__ep.html#3ab8ca6103c0483f2fefce0dc1684eaa">bm_circ</a>;
+<a name="l00167"></a>00167         <span class="comment">/* The Concatenation feature value */</span>
+<a name="l00168"></a><a class="code" href="structcfi__ep.html#4c83b9bb5a75e6b81fbfa86b51736164">00168</a>         <a class="code" href="dwc__otg__cfi_8h.html#083bc35d34ae5489588bb581fc45ae73">ddma_concat_buffer_setup_t</a> *<a class="code" href="structcfi__ep.html#4c83b9bb5a75e6b81fbfa86b51736164">bm_concat</a>;
+<a name="l00169"></a>00169         <span class="comment">/* The Alignment feature value */</span>
+<a name="l00170"></a><a class="code" href="structcfi__ep.html#bb544b7938d0c62857fc3726988310d2">00170</a>         <a class="code" href="dwc__otg__cfi_8h.html#f60b107e43f0edf8ac94f781803c8780">ddma_align_buffer_setup_t</a> *<a class="code" href="structcfi__ep.html#bb544b7938d0c62857fc3726988310d2">bm_align</a>;
+<a name="l00171"></a>00171         <span class="comment">/* XFER length */</span>
+<a name="l00172"></a><a class="code" href="structcfi__ep.html#f85903cb9e179124e42d98d557098011">00172</a>         uint32_t <a class="code" href="structcfi__ep.html#f85903cb9e179124e42d98d557098011">xfer_len</a>;
+<a name="l00173"></a>00173         <span class="comment">/* </span>
+<a name="l00174"></a>00174 <span class="comment">         * Count of DMA descriptors currently used.</span>
+<a name="l00175"></a>00175 <span class="comment">         * The total should not exceed the MAX_DMA_DESCS_PER_EP value</span>
+<a name="l00176"></a>00176 <span class="comment">         * defined in the dwc_otg_cil.h</span>
+<a name="l00177"></a>00177 <span class="comment">         */</span>
+<a name="l00178"></a><a class="code" href="structcfi__ep.html#73050a3011b918e8be6c2434db357514">00178</a>         uint32_t <a class="code" href="structcfi__ep.html#73050a3011b918e8be6c2434db357514">desc_count</a>;
+<a name="l00179"></a>00179 };
+<a name="l00180"></a><a class="code" href="dwc__otg__cfi_8h.html#1c70b0d73323d138d4aac971e9998908">00180</a> <span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code" href="structcfi__ep.html">cfi_ep</a> <a class="code" href="dwc__otg__cfi_8h.html#1c70b0d73323d138d4aac971e9998908">cfi_ep_t</a>;
+<a name="l00181"></a>00181 
+<a name="l00182"></a><a class="code" href="structcfi__dma__buff.html">00182</a> <span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code" href="structcfi__dma__buff.html">cfi_dma_buff</a> {
+<a name="l00183"></a><a class="code" href="dwc__otg__cfi_8h.html#34582b9ef366f4c0e8ea24aa2388e829">00183</a> <span class="preprocessor">#define CFI_IN_BUF_LEN  1024</span>
+<a name="l00184"></a><a class="code" href="dwc__otg__cfi_8h.html#739556affb10ce8a44b362b8ffa41a40">00184</a> <span class="preprocessor"></span><span class="preprocessor">#define CFI_OUT_BUF_LEN 1024</span>
+<a name="l00185"></a><a class="code" href="structcfi__dma__buff.html#549d40f7e33056fc5a99d51d00714d97">00185</a> <span class="preprocessor"></span>        dma_addr_t <a class="code" href="structcfi__dma__buff.html#549d40f7e33056fc5a99d51d00714d97">addr</a>;
+<a name="l00186"></a><a class="code" href="structcfi__dma__buff.html#474851b3123373b8b30fa3637eb81b5b">00186</a>         uint8_t *<a class="code" href="structcfi__dma__buff.html#474851b3123373b8b30fa3637eb81b5b">buf</a>;
+<a name="l00187"></a>00187 } <a class="code" href="structcfi__dma__buff.html">cfi_dma_buff_t</a>;
+<a name="l00188"></a>00188 
+<a name="l00189"></a>00189 <span class="keyword">struct </span><a class="code" href="structcfiobject.html">cfiobject</a>;
+<a name="l00190"></a>00190 
+<a name="l00199"></a><a class="code" href="structcfi__ops.html">00199</a> <span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code" href="structcfi__ops.html">cfi_ops</a> {
+<a name="l00200"></a>00200         int (*ep_enable) (<span class="keyword">struct </span><a class="code" href="structcfiobject.html">cfiobject</a> * cfi, <span class="keyword">struct </span><a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd</a> * pcd,
+<a name="l00201"></a>00201                           <span class="keyword">struct </span><a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep</a> * ep);
+<a name="l00202"></a>00202         <span class="keywordtype">void</span> *(*ep_alloc_buf) (<span class="keyword">struct </span><a class="code" href="structcfiobject.html">cfiobject</a> * cfi, <span class="keyword">struct </span><a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd</a> * pcd,
+<a name="l00203"></a>00203                                <span class="keyword">struct </span><a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep</a> * ep, dma_addr_t * <a class="code" href="structdwc__otg__pcd__ep.html#314db0fbde1d5eb9eae0cbe4fdef47a4">dma</a>,
+<a name="l00204"></a>00204                                <span class="keywordtype">unsigned</span> size, gfp_t flags);
+<a name="l00205"></a>00205         void (*release) (<span class="keyword">struct </span><a class="code" href="structcfiobject.html">cfiobject</a> * cfi);
+<a name="l00206"></a>00206         int (*ctrl_write_complete) (<span class="keyword">struct </span><a class="code" href="structcfiobject.html">cfiobject</a> * cfi,
+<a name="l00207"></a>00207                                     <span class="keyword">struct </span><a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd</a> * pcd);
+<a name="l00208"></a>00208         void (*build_descriptors) (<span class="keyword">struct </span><a class="code" href="structcfiobject.html">cfiobject</a> * cfi,
+<a name="l00209"></a>00209                                    <span class="keyword">struct </span><a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd</a> * pcd,
+<a name="l00210"></a>00210                                    <span class="keyword">struct </span><a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep</a> * ep,
+<a name="l00211"></a>00211                                    <a class="code" href="structdwc__otg__pcd__request.html">dwc_otg_pcd_request_t</a> * req);
+<a name="l00212"></a>00212 } <a class="code" href="structcfi__ops.html">cfi_ops_t</a>;
+<a name="l00213"></a>00213 
+<a name="l00214"></a><a class="code" href="structcfiobject.html">00214</a> <span class="keyword">struct </span><a class="code" href="structcfiobject.html">cfiobject</a> {
+<a name="l00215"></a><a class="code" href="structcfiobject.html#324b7481af9ba7a97233b162bbe8301a">00215</a>         cfi_ops_t <a class="code" href="structcfiobject.html#324b7481af9ba7a97233b162bbe8301a">ops</a>;
+<a name="l00216"></a><a class="code" href="structcfiobject.html#bab38f9fb74c1332c70029000c7d3818">00216</a>         <span class="keyword">struct </span><a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd</a> *<a class="code" href="structcfiobject.html#bab38f9fb74c1332c70029000c7d3818">pcd</a>;
+<a name="l00217"></a><a class="code" href="structcfiobject.html#fcb2ec62bedb38bb1e6a596ac778d4e6">00217</a>         <span class="keyword">struct </span>usb_gadget *<a class="code" href="structcfiobject.html#fcb2ec62bedb38bb1e6a596ac778d4e6">gadget</a>;
+<a name="l00218"></a>00218 
+<a name="l00219"></a>00219         <span class="comment">/* Buffers used to send/receive CFI-related request data */</span>
+<a name="l00220"></a><a class="code" href="structcfiobject.html#f6548b2b8fbab90656c22eb5ca857643">00220</a>         <a class="code" href="structcfi__dma__buff.html">cfi_dma_buff_t</a> <a class="code" href="structcfiobject.html#f6548b2b8fbab90656c22eb5ca857643">buf_in</a>;
+<a name="l00221"></a><a class="code" href="structcfiobject.html#adaa1cd0f88e639251f8dfbd65da7935">00221</a>         <a class="code" href="structcfi__dma__buff.html">cfi_dma_buff_t</a> <a class="code" href="structcfiobject.html#adaa1cd0f88e639251f8dfbd65da7935">buf_out</a>;
+<a name="l00222"></a>00222 
+<a name="l00223"></a>00223         <span class="comment">/* CFI specific Control request wrapper */</span>
+<a name="l00224"></a><a class="code" href="structcfiobject.html#a86c33aef2a521a27ca515bb7397dd34">00224</a>         <span class="keyword">struct </span><a class="code" href="structcfi__usb__ctrlrequest.html">cfi_usb_ctrlrequest</a> <a class="code" href="structcfiobject.html#a86c33aef2a521a27ca515bb7397dd34">ctrl_req</a>;
+<a name="l00225"></a>00225 
+<a name="l00226"></a>00226         <span class="comment">/* The list of active EP's in the PCD of type cfi_ep_t */</span>
+<a name="l00227"></a><a class="code" href="structcfiobject.html#82805f011abf3deace7faa159729229a">00227</a>         dwc_list_link_t <a class="code" href="structcfiobject.html#82805f011abf3deace7faa159729229a">active_eps</a>;
+<a name="l00228"></a>00228 
+<a name="l00229"></a>00229         <span class="comment">/* This flag shall control the propagation of a specific request</span>
+<a name="l00230"></a>00230 <span class="comment">         * to the gadget's processing routines.</span>
+<a name="l00231"></a>00231 <span class="comment">         * 0 - no gadget handling</span>
+<a name="l00232"></a>00232 <span class="comment">         * 1 - the gadget needs to know about this request (w/o completing a status </span>
+<a name="l00233"></a>00233 <span class="comment">         * phase - just return a 0 to the _setup callback)</span>
+<a name="l00234"></a>00234 <span class="comment">         */</span>
+<a name="l00235"></a><a class="code" href="structcfiobject.html#f103d681f78c43dc92dd4a85cdbdc27c">00235</a>         uint8_t <a class="code" href="structcfiobject.html#f103d681f78c43dc92dd4a85cdbdc27c">need_gadget_att</a>;
+<a name="l00236"></a>00236 
+<a name="l00237"></a>00237         <span class="comment">/* Flag indicating whether the status IN phase needs to be </span>
+<a name="l00238"></a>00238 <span class="comment">         * completed by the PCD</span>
+<a name="l00239"></a>00239 <span class="comment">         */</span>
+<a name="l00240"></a><a class="code" href="structcfiobject.html#8d35a323dcd29a1c9d1a8568bd514c3b">00240</a>         uint8_t <a class="code" href="structcfiobject.html#8d35a323dcd29a1c9d1a8568bd514c3b">need_status_in_complete</a>;
+<a name="l00241"></a>00241 };
+<a name="l00242"></a><a class="code" href="dwc__otg__cfi_8h.html#4a1790f6f20555dd7cb9c8ae91c568a6">00242</a> <span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code" href="structcfiobject.html">cfiobject</a> <a class="code" href="dwc__otg__cfi_8h.html#4a1790f6f20555dd7cb9c8ae91c568a6">cfiobject_t</a>;
+<a name="l00243"></a>00243 
+<a name="l00244"></a><a class="code" href="dwc__otg__cfi_8h.html#63f942c5c80fd3a1d4d735ccbf082fcc">00244</a> <span class="preprocessor">#define DUMP_MSG</span>
+<a name="l00245"></a>00245 <span class="preprocessor"></span>
+<a name="l00246"></a>00246 <span class="preprocessor">#if defined(DUMP_MSG)</span>
+<a name="l00247"></a><a class="code" href="dwc__otg__cfi_8h.html#8d8df6d136115ec977eb6bf20148547a">00247</a> <span class="preprocessor"></span><span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cfi_8h.html#8d8df6d136115ec977eb6bf20148547a">dump_msg</a>(<span class="keyword">const</span> u8 * buf, <span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> length)
+<a name="l00248"></a>00248 {
+<a name="l00249"></a>00249         <span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> start, num, i;
+<a name="l00250"></a>00250         <span class="keywordtype">char</span> line[52], *p;
+<a name="l00251"></a>00251 
+<a name="l00252"></a>00252         <span class="keywordflow">if</span> (length &gt;= 512)
+<a name="l00253"></a>00253                 <span class="keywordflow">return</span>;
+<a name="l00254"></a>00254 
+<a name="l00255"></a>00255         start = 0;
+<a name="l00256"></a>00256         <span class="keywordflow">while</span> (length &gt; 0) {
+<a name="l00257"></a>00257                 num = <a class="code" href="dwc__otg__cfi_8h.html#7c9949b9e692a8360832aedfa1843657">min</a>(length, 16u);
+<a name="l00258"></a>00258                 p = line;
+<a name="l00259"></a>00259                 <span class="keywordflow">for</span> (i = 0; i &lt; num; ++i) {
+<a name="l00260"></a>00260                         <span class="keywordflow">if</span> (i == 8)
+<a name="l00261"></a>00261                                 *p++ = <span class="charliteral">' '</span>;
+<a name="l00262"></a>00262                         DWC_SPRINTF(p, <span class="stringliteral">" %02x"</span>, buf[i]);
+<a name="l00263"></a>00263                         p += 3;
+<a name="l00264"></a>00264                 }
+<a name="l00265"></a>00265                 *p = 0;
+<a name="l00266"></a>00266                 DWC_DEBUG(<span class="stringliteral">"%6x: %s\n"</span>, start, line);
+<a name="l00267"></a>00267                 buf += num;
+<a name="l00268"></a>00268                 start += num;
+<a name="l00269"></a>00269                 length -= num;
+<a name="l00270"></a>00270         }
+<a name="l00271"></a>00271 }
+<a name="l00272"></a>00272 <span class="preprocessor">#else</span>
+<a name="l00273"></a>00273 <span class="preprocessor"></span><span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cfi_8h.html#8d8df6d136115ec977eb6bf20148547a">dump_msg</a>(<span class="keyword">const</span> u8 * buf, <span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> length)
+<a name="l00274"></a>00274 {
+<a name="l00275"></a>00275 }
+<a name="l00276"></a>00276 <span class="preprocessor">#endif</span>
+<a name="l00277"></a>00277 <span class="preprocessor"></span>
+<a name="l00281"></a><a class="code" href="dwc__otg__cfi_8h.html#5ece1e51b8534a5cc9a7dd5115bb01ca">00281</a> <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keyword">struct </span><a class="code" href="structcfi__ep.html">cfi_ep</a> *<a class="code" href="dwc__otg__cfi_8h.html#5ece1e51b8534a5cc9a7dd5115bb01ca">get_cfi_ep_by_addr</a>(<span class="keyword">struct</span> <a class="code" href="structcfiobject.html">cfiobject</a> *cfi,
+<a name="l00282"></a>00282                                                 uint8_t addr)
+<a name="l00283"></a>00283 {
+<a name="l00284"></a>00284         <span class="keyword">struct </span><a class="code" href="structcfi__ep.html">cfi_ep</a> *pcfiep;
+<a name="l00285"></a>00285         dwc_list_link_t *tmp;
+<a name="l00286"></a>00286 
+<a name="l00287"></a>00287         DWC_LIST_FOREACH(tmp, &amp;cfi-&gt;<a class="code" href="structcfiobject.html#82805f011abf3deace7faa159729229a">active_eps</a>) {
+<a name="l00288"></a>00288                 pcfiep = DWC_LIST_ENTRY(tmp, <span class="keyword">struct</span> <a class="code" href="structcfi__ep.html">cfi_ep</a>, <a class="code" href="structcfi__ep.html#18bff3370dc933cd374d458897dfbc2f">lh</a>);
+<a name="l00289"></a>00289 
+<a name="l00290"></a>00290                 <span class="keywordflow">if</span> (pcfiep-&gt;<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#86e27843c439dd0b1d12d9bf2dc6516f">desc</a>-&gt;bEndpointAddress == addr) {
+<a name="l00291"></a>00291                         <span class="keywordflow">return</span> pcfiep;
+<a name="l00292"></a>00292                 }
+<a name="l00293"></a>00293         }
+<a name="l00294"></a>00294 
+<a name="l00295"></a>00295         <span class="keywordflow">return</span> NULL;
+<a name="l00296"></a>00296 }
+<a name="l00297"></a>00297 
+<a name="l00302"></a><a class="code" href="dwc__otg__cfi_8h.html#c21284d5adf03032d094a36babf9b1e5">00302</a> <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keyword">struct </span><a class="code" href="structcfi__ep.html">cfi_ep</a> *<a class="code" href="dwc__otg__cfi_8h.html#c21284d5adf03032d094a36babf9b1e5">get_cfi_ep_by_pcd_ep</a>(<span class="keyword">struct</span> <a class="code" href="structcfiobject.html">cfiobject</a> *cfi,
+<a name="l00303"></a>00303                                                   <span class="keyword">struct</span> <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep</a> *<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>)
+<a name="l00304"></a>00304 {
+<a name="l00305"></a>00305         <span class="keyword">struct </span><a class="code" href="structcfi__ep.html">cfi_ep</a> *pcfiep = NULL;
+<a name="l00306"></a>00306         dwc_list_link_t *tmp;
+<a name="l00307"></a>00307 
+<a name="l00308"></a>00308         DWC_LIST_FOREACH(tmp, &amp;cfi-&gt;<a class="code" href="structcfiobject.html#82805f011abf3deace7faa159729229a">active_eps</a>) {
+<a name="l00309"></a>00309                 pcfiep = DWC_LIST_ENTRY(tmp, <span class="keyword">struct</span> <a class="code" href="structcfi__ep.html">cfi_ep</a>, <a class="code" href="structcfi__ep.html#18bff3370dc933cd374d458897dfbc2f">lh</a>);
+<a name="l00310"></a>00310                 <span class="keywordflow">if</span> (pcfiep-&gt;<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a> == <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>) {
+<a name="l00311"></a>00311                         <span class="keywordflow">return</span> pcfiep;
+<a name="l00312"></a>00312                 }
+<a name="l00313"></a>00313         }
+<a name="l00314"></a>00314         <span class="keywordflow">return</span> NULL;
+<a name="l00315"></a>00315 }
+<a name="l00316"></a>00316 
+<a name="l00317"></a>00317 <span class="keywordtype">int</span> cfi_setup(<span class="keyword">struct</span> <a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd</a> *pcd, <span class="keyword">struct</span> <a class="code" href="structcfi__usb__ctrlrequest.html">cfi_usb_ctrlrequest</a> *ctrl);
+<a name="l00318"></a>00318 
+<a name="l00319"></a>00319 <span class="preprocessor">#endif                          </span><span class="comment">/* (__DWC_OTG_CFI_H__) */</span>
+</pre></div><hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cfi_8h.html b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cfi_8h.html
new file mode 100644
index 000000000000..f946f37a148c
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cfi_8h.html
@@ -0,0 +1,302 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_cfi.h File Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<h1>dwc_otg_cfi.h File Reference</h1>This file contains the CFI related OTG PCD specific common constants, interfaces (functions and macros) and data structures. <a href="#_details">More...</a>
+<p>
+<code>#include &quot;<a class="el" href="dwc__otg__pcd_8h-source.html">dwc_otg_pcd.h</a>&quot;</code><br>
+<code>#include &quot;<a class="el" href="dwc__cfi__common_8h-source.html">dwc_cfi_common.h</a>&quot;</code><br>
+
+<p>
+<a href="dwc__otg__cfi_8h-source.html">Go to the source code of this file.</a><table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Structures</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct__ddma__sg__buffer__setup.html">_ddma_sg_buffer_setup</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Descriptor DMA SG Buffer setup structure (SG buffer).  <a href="struct__ddma__sg__buffer__setup.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct__ddma__concat__buffer__setup__hdr.html">_ddma_concat_buffer_setup_hdr</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Descriptor DMA Concatenation Buffer setup structure.  <a href="struct__ddma__concat__buffer__setup__hdr.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct__ddma__concat__buffer__setup.html">_ddma_concat_buffer_setup</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Descriptor DMA Concatenation Buffer setup structure.  <a href="struct__ddma__concat__buffer__setup.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct__ddma__align__buffer__setup.html">_ddma_align_buffer_setup</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Descriptor DMA Alignment Buffer setup structure.  <a href="struct__ddma__align__buffer__setup.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct__tx__fifo__size__setup.html">_tx_fifo_size_setup</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Transmit FIFO Size setup structure.  <a href="struct__tx__fifo__size__setup.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct__rx__fifo__size__setup.html">_rx_fifo_size_setup</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Transmit FIFO Size setup structure.  <a href="struct__rx__fifo__size__setup.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcfi__usb__ctrlrequest.html">cfi_usb_ctrlrequest</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">struct <a class="el" href="structcfi__usb__ctrlrequest.html">cfi_usb_ctrlrequest</a> - the CFI implementation of the struct usb_ctrlrequest This structure encapsulates the standard usb_ctrlrequest and adds a pointer to the data returned in the data stage of a 3-stage Control Write requests.  <a href="structcfi__usb__ctrlrequest.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcfi__ep.html">cfi_ep</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">The CFI wrapper of the enabled and activated <a class="el" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep</a> structures.  <a href="structcfi__ep.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcfi__dma__buff.html">cfi_dma_buff</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcfi__ops.html">cfi_ops</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This is the interface for the CFI operations.  <a href="structcfi__ops.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcfiobject.html">cfiobject</a></td></tr>
+
+<tr><td colspan="2"><br><h2>Defines</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="d4efa118a5f5c82587650944721a8dc1"></a><!-- doxytag: member="dwc_otg_cfi.h::__DWC_OTG_CFI_H__" ref="d4efa118a5f5c82587650944721a8dc1" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cfi_8h.html#d4efa118a5f5c82587650944721a8dc1">__DWC_OTG_CFI_H__</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="0e196868939f6bbf0d157868bfc90208"></a><!-- doxytag: member="dwc_otg_cfi.h::FT_ID_DMA_MODE" ref="0e196868939f6bbf0d157868bfc90208" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cfi_8h.html#0e196868939f6bbf0d157868bfc90208">FT_ID_DMA_MODE</a>&nbsp;&nbsp;&nbsp;0x0001</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This is a request for all Core Features. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="98840b45640251bfafa3481260aef889"></a><!-- doxytag: member="dwc_otg_cfi.h::FT_ID_DMA_BUFFER_SETUP" ref="98840b45640251bfafa3481260aef889" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cfi_8h.html#98840b45640251bfafa3481260aef889">FT_ID_DMA_BUFFER_SETUP</a>&nbsp;&nbsp;&nbsp;0x0002</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="9335284cd4dae01f4bc0da7cb89d5ef4"></a><!-- doxytag: member="dwc_otg_cfi.h::FT_ID_DMA_BUFF_ALIGN" ref="9335284cd4dae01f4bc0da7cb89d5ef4" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cfi_8h.html#9335284cd4dae01f4bc0da7cb89d5ef4">FT_ID_DMA_BUFF_ALIGN</a>&nbsp;&nbsp;&nbsp;0x0003</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="779a11db5843dd058581d93c8232bd7c"></a><!-- doxytag: member="dwc_otg_cfi.h::FT_ID_DMA_CONCAT_SETUP" ref="779a11db5843dd058581d93c8232bd7c" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cfi_8h.html#779a11db5843dd058581d93c8232bd7c">FT_ID_DMA_CONCAT_SETUP</a>&nbsp;&nbsp;&nbsp;0x0004</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="8db5bfce321e02d42b742e9deedfa665"></a><!-- doxytag: member="dwc_otg_cfi.h::FT_ID_DMA_CIRCULAR" ref="8db5bfce321e02d42b742e9deedfa665" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cfi_8h.html#8db5bfce321e02d42b742e9deedfa665">FT_ID_DMA_CIRCULAR</a>&nbsp;&nbsp;&nbsp;0x0005</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="bcc99a9e5a0b15b4212d88bd9c610647"></a><!-- doxytag: member="dwc_otg_cfi.h::FT_ID_THRESHOLD_SETUP" ref="bcc99a9e5a0b15b4212d88bd9c610647" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cfi_8h.html#bcc99a9e5a0b15b4212d88bd9c610647">FT_ID_THRESHOLD_SETUP</a>&nbsp;&nbsp;&nbsp;0x0006</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="54b879727edcb06acdd11968ec60d249"></a><!-- doxytag: member="dwc_otg_cfi.h::FT_ID_DFIFO_DEPTH" ref="54b879727edcb06acdd11968ec60d249" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cfi_8h.html#54b879727edcb06acdd11968ec60d249">FT_ID_DFIFO_DEPTH</a>&nbsp;&nbsp;&nbsp;0x0007</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="a3a67b679a59c5279370bbf69f114cb6"></a><!-- doxytag: member="dwc_otg_cfi.h::FT_ID_TX_FIFO_DEPTH" ref="a3a67b679a59c5279370bbf69f114cb6" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cfi_8h.html#a3a67b679a59c5279370bbf69f114cb6">FT_ID_TX_FIFO_DEPTH</a>&nbsp;&nbsp;&nbsp;0x0008</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="42b7c98c105de1f9399786a3419e7e20"></a><!-- doxytag: member="dwc_otg_cfi.h::FT_ID_RX_FIFO_DEPTH" ref="42b7c98c105de1f9399786a3419e7e20" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cfi_8h.html#42b7c98c105de1f9399786a3419e7e20">FT_ID_RX_FIFO_DEPTH</a>&nbsp;&nbsp;&nbsp;0x0009</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7f62f8d1e9825c09b1f7d2badbe2527a"></a><!-- doxytag: member="dwc_otg_cfi.h::CFI_INFO_DEF" ref="7f62f8d1e9825c09b1f7d2badbe2527a" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cfi_8h.html#7f62f8d1e9825c09b1f7d2badbe2527a">CFI_INFO_DEF</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f121e7b686ae7277b695f7209c41135f"></a><!-- doxytag: member="dwc_otg_cfi.h::CFI_INFO" ref="f121e7b686ae7277b695f7209c41135f" args="(fmt...)" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>(fmt...)&nbsp;&nbsp;&nbsp;DWC_PRINTF(&quot;CFI: &quot; fmt);</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cfi_8h.html#7c9949b9e692a8360832aedfa1843657">min</a>(x, y)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cfi_8h.html#4755d18ce5205f644e5cd02db7f4ada5">max</a>(x, y)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="2332c8839256e2bb1aa1e0e8a9185ce2"></a><!-- doxytag: member="dwc_otg_cfi.h::BS_SG_VAL_DESC_LEN" ref="2332c8839256e2bb1aa1e0e8a9185ce2" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cfi_8h.html#2332c8839256e2bb1aa1e0e8a9185ce2">BS_SG_VAL_DESC_LEN</a>&nbsp;&nbsp;&nbsp;6</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c89955571b72df025126a1047bc53a00"></a><!-- doxytag: member="dwc_otg_cfi.h::BS_CONCAT_VAL_HDR_LEN" ref="c89955571b72df025126a1047bc53a00" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cfi_8h.html#c89955571b72df025126a1047bc53a00">BS_CONCAT_VAL_HDR_LEN</a>&nbsp;&nbsp;&nbsp;4</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="5495ec473ea2d7c8f805567416c559f0"></a><!-- doxytag: member="dwc_otg_cfi.h::BS_ALIGN_VAL_HDR_LEN" ref="5495ec473ea2d7c8f805567416c559f0" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cfi_8h.html#5495ec473ea2d7c8f805567416c559f0">BS_ALIGN_VAL_HDR_LEN</a>&nbsp;&nbsp;&nbsp;2</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="34582b9ef366f4c0e8ea24aa2388e829"></a><!-- doxytag: member="dwc_otg_cfi.h::CFI_IN_BUF_LEN" ref="34582b9ef366f4c0e8ea24aa2388e829" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cfi_8h.html#34582b9ef366f4c0e8ea24aa2388e829">CFI_IN_BUF_LEN</a>&nbsp;&nbsp;&nbsp;1024</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="739556affb10ce8a44b362b8ffa41a40"></a><!-- doxytag: member="dwc_otg_cfi.h::CFI_OUT_BUF_LEN" ref="739556affb10ce8a44b362b8ffa41a40" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cfi_8h.html#739556affb10ce8a44b362b8ffa41a40">CFI_OUT_BUF_LEN</a>&nbsp;&nbsp;&nbsp;1024</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="63f942c5c80fd3a1d4d735ccbf082fcc"></a><!-- doxytag: member="dwc_otg_cfi.h::DUMP_MSG" ref="63f942c5c80fd3a1d4d735ccbf082fcc" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cfi_8h.html#63f942c5c80fd3a1d4d735ccbf082fcc">DUMP_MSG</a></td></tr>
+
+<tr><td colspan="2"><br><h2>Typedefs</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="1040b884c9adf08c1106ffdf9f191ad4"></a><!-- doxytag: member="dwc_otg_cfi.h::ddma_sg_buffer_setup_t" ref="1040b884c9adf08c1106ffdf9f191ad4" args="" -->
+typedef <a class="el" href="struct__ddma__sg__buffer__setup.html">_ddma_sg_buffer_setup</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cfi_8h.html#1040b884c9adf08c1106ffdf9f191ad4">ddma_sg_buffer_setup_t</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="a6fccd9def2a83408bdb10eb7964a4d6"></a><!-- doxytag: member="dwc_otg_cfi.h::ddma_concat_buffer_setup_hdr_t" ref="a6fccd9def2a83408bdb10eb7964a4d6" args="" -->
+typedef <a class="el" href="struct__ddma__concat__buffer__setup__hdr.html">_ddma_concat_buffer_setup_hdr</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cfi_8h.html#a6fccd9def2a83408bdb10eb7964a4d6">ddma_concat_buffer_setup_hdr_t</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="083bc35d34ae5489588bb581fc45ae73"></a><!-- doxytag: member="dwc_otg_cfi.h::ddma_concat_buffer_setup_t" ref="083bc35d34ae5489588bb581fc45ae73" args="" -->
+typedef <a class="el" href="struct__ddma__concat__buffer__setup.html">_ddma_concat_buffer_setup</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cfi_8h.html#083bc35d34ae5489588bb581fc45ae73">ddma_concat_buffer_setup_t</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f60b107e43f0edf8ac94f781803c8780"></a><!-- doxytag: member="dwc_otg_cfi.h::ddma_align_buffer_setup_t" ref="f60b107e43f0edf8ac94f781803c8780" args="" -->
+typedef <a class="el" href="struct__ddma__align__buffer__setup.html">_ddma_align_buffer_setup</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cfi_8h.html#f60b107e43f0edf8ac94f781803c8780">ddma_align_buffer_setup_t</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="9da70e9326ec40c9f1bd9c487aabe4c1"></a><!-- doxytag: member="dwc_otg_cfi.h::tx_fifo_size_setup_t" ref="9da70e9326ec40c9f1bd9c487aabe4c1" args="" -->
+typedef <a class="el" href="struct__tx__fifo__size__setup.html">_tx_fifo_size_setup</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cfi_8h.html#9da70e9326ec40c9f1bd9c487aabe4c1">tx_fifo_size_setup_t</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="0fbbd60333457c6667bd7757e4aac2f8"></a><!-- doxytag: member="dwc_otg_cfi.h::rx_fifo_size_setup_t" ref="0fbbd60333457c6667bd7757e4aac2f8" args="" -->
+typedef <a class="el" href="struct__rx__fifo__size__setup.html">_rx_fifo_size_setup</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cfi_8h.html#0fbbd60333457c6667bd7757e4aac2f8">rx_fifo_size_setup_t</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="1c70b0d73323d138d4aac971e9998908"></a><!-- doxytag: member="dwc_otg_cfi.h::cfi_ep_t" ref="1c70b0d73323d138d4aac971e9998908" args="" -->
+typedef <a class="el" href="structcfi__ep.html">cfi_ep</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cfi_8h.html#1c70b0d73323d138d4aac971e9998908">cfi_ep_t</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="0af08d7cd547ec7ba9bf269967975f49"></a><!-- doxytag: member="dwc_otg_cfi.h::cfi_dma_buff_t" ref="0af08d7cd547ec7ba9bf269967975f49" args="" -->
+typedef <a class="el" href="structcfi__dma__buff.html">cfi_dma_buff</a>&nbsp;</td><td class="memItemRight" valign="bottom"><b>cfi_dma_buff_t</b></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef <a class="el" href="structcfi__ops.html">cfi_ops</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cfi_8h.html#226b99dcff1992adefa086b6c7773eff">cfi_ops_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This is the interface for the CFI operations.  <a href="#226b99dcff1992adefa086b6c7773eff"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="4a1790f6f20555dd7cb9c8ae91c568a6"></a><!-- doxytag: member="dwc_otg_cfi.h::cfiobject_t" ref="4a1790f6f20555dd7cb9c8ae91c568a6" args="" -->
+typedef <a class="el" href="structcfiobject.html">cfiobject</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cfi_8h.html#4a1790f6f20555dd7cb9c8ae91c568a6">cfiobject_t</a></td></tr>
+
+<tr><td colspan="2"><br><h2>Functions</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="8d8df6d136115ec977eb6bf20148547a"></a><!-- doxytag: member="dwc_otg_cfi.h::dump_msg" ref="8d8df6d136115ec977eb6bf20148547a" args="(const u8 *buf, unsigned int length)" -->
+static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cfi_8h.html#8d8df6d136115ec977eb6bf20148547a">dump_msg</a> (const u8 *buf, unsigned int length)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="5ece1e51b8534a5cc9a7dd5115bb01ca"></a><!-- doxytag: member="dwc_otg_cfi.h::get_cfi_ep_by_addr" ref="5ece1e51b8534a5cc9a7dd5115bb01ca" args="(struct cfiobject *cfi, uint8_t addr)" -->
+static struct <a class="el" href="structcfi__ep.html">cfi_ep</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cfi_8h.html#5ece1e51b8534a5cc9a7dd5115bb01ca">get_cfi_ep_by_addr</a> (struct <a class="el" href="structcfiobject.html">cfiobject</a> *cfi, uint8_t addr)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function returns a pointer to cfi_ep_t object with the addr address. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c21284d5adf03032d094a36babf9b1e5"></a><!-- doxytag: member="dwc_otg_cfi.h::get_cfi_ep_by_pcd_ep" ref="c21284d5adf03032d094a36babf9b1e5" args="(struct cfiobject *cfi, struct dwc_otg_pcd_ep *ep)" -->
+static struct <a class="el" href="structcfi__ep.html">cfi_ep</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cfi_8h.html#c21284d5adf03032d094a36babf9b1e5">get_cfi_ep_by_pcd_ep</a> (struct <a class="el" href="structcfiobject.html">cfiobject</a> *cfi, struct <a class="el" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep</a> *ep)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function returns a pointer to cfi_ep_t object that matches the <a class="el" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep</a> object. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="92f9f0271ce5b5a27f39ef94615ab521"></a><!-- doxytag: member="dwc_otg_cfi.h::cfi_setup" ref="92f9f0271ce5b5a27f39ef94615ab521" args="(struct dwc_otg_pcd *pcd, struct cfi_usb_ctrlrequest *ctrl)" -->
+int&nbsp;</td><td class="memItemRight" valign="bottom"><b>cfi_setup</b> (struct <a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd</a> *pcd, struct <a class="el" href="structcfi__usb__ctrlrequest.html">cfi_usb_ctrlrequest</a> *ctrl)</td></tr>
+
+<tr><td colspan="2"><br><h2>Variables</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="el" href="struct__ddma__sg__buffer__setup.html">_ddma_sg_buffer_setup</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cfi_8h.html#1c517724be71d3c12952486ba172c0b6">packed</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Descriptor DMA SG Buffer setup structure (SG buffer).  <a href="#1c517724be71d3c12952486ba172c0b6"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ac8e823df3e2c4089a32c5f1b4bc5c7c"></a><!-- doxytag: member="dwc_otg_cfi.h::packed" ref="ac8e823df3e2c4089a32c5f1b4bc5c7c" args="" -->
+<a class="el" href="struct__ddma__concat__buffer__setup__hdr.html">_ddma_concat_buffer_setup_hdr</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cfi_8h.html#ac8e823df3e2c4089a32c5f1b4bc5c7c">packed</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Descriptor DMA Concatenation Buffer setup structure. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="cccfe24f0404a0c12be7173b21fff9f3"></a><!-- doxytag: member="dwc_otg_cfi.h::packed" ref="cccfe24f0404a0c12be7173b21fff9f3" args="" -->
+<a class="el" href="struct__ddma__concat__buffer__setup.html">_ddma_concat_buffer_setup</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cfi_8h.html#cccfe24f0404a0c12be7173b21fff9f3">packed</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Descriptor DMA Concatenation Buffer setup structure. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="9d9da051973fc233a409c5e5f0c67d66"></a><!-- doxytag: member="dwc_otg_cfi.h::packed" ref="9d9da051973fc233a409c5e5f0c67d66" args="" -->
+<a class="el" href="struct__ddma__align__buffer__setup.html">_ddma_align_buffer_setup</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cfi_8h.html#9d9da051973fc233a409c5e5f0c67d66">packed</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Descriptor DMA Alignment Buffer setup structure. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="69a4b0318657fb107b2403c22c8d9dd9"></a><!-- doxytag: member="dwc_otg_cfi.h::packed" ref="69a4b0318657fb107b2403c22c8d9dd9" args="" -->
+<a class="el" href="struct__tx__fifo__size__setup.html">_tx_fifo_size_setup</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cfi_8h.html#69a4b0318657fb107b2403c22c8d9dd9">packed</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Transmit FIFO Size setup structure. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3e7b3a7aca62be5747bfe900e0a9e102"></a><!-- doxytag: member="dwc_otg_cfi.h::packed" ref="3e7b3a7aca62be5747bfe900e0a9e102" args="" -->
+<a class="el" href="struct__rx__fifo__size__setup.html">_rx_fifo_size_setup</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cfi_8h.html#3e7b3a7aca62be5747bfe900e0a9e102">packed</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Transmit FIFO Size setup structure. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="289004a802a0ba1d6ccaf6c6969f4e3f"></a><!-- doxytag: member="dwc_otg_cfi.h::UPACKED" ref="289004a802a0ba1d6ccaf6c6969f4e3f" args="" -->
+<a class="el" href="structcfi__usb__ctrlrequest.html">cfi_usb_ctrlrequest</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cfi_8h.html#289004a802a0ba1d6ccaf6c6969f4e3f">UPACKED</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">struct <a class="el" href="structcfi__usb__ctrlrequest.html">cfi_usb_ctrlrequest</a> - the CFI implementation of the struct usb_ctrlrequest This structure encapsulates the standard usb_ctrlrequest and adds a pointer to the data returned in the data stage of a 3-stage Control Write requests. <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This file contains the CFI related OTG PCD specific common constants, interfaces (functions and macros) and data structures. 
+<p>
+
+<p>
+Definition in file <a class="el" href="dwc__otg__cfi_8h-source.html">dwc_otg_cfi.h</a>.<hr><h2>Define Documentation</h2>
+<a class="anchor" name="7c9949b9e692a8360832aedfa1843657"></a><!-- doxytag: member="dwc_otg_cfi.h::min" ref="7c9949b9e692a8360832aedfa1843657" args="(x, y)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define min          </td>
+          <td>(</td>
+          <td class="paramtype">x,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">y&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment">({ \
+        x &lt; y ? x : y; })
+</pre></div>
+<p>
+Definition at line <a class="el" href="dwc__otg__cfi_8h-source.html#l00067">67</a> of file <a class="el" href="dwc__otg__cfi_8h-source.html">dwc_otg_cfi.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="4755d18ce5205f644e5cd02db7f4ada5"></a><!-- doxytag: member="dwc_otg_cfi.h::max" ref="4755d18ce5205f644e5cd02db7f4ada5" args="(x, y)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define max          </td>
+          <td>(</td>
+          <td class="paramtype">x,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">y&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment">({ \
+        x &gt; y ? x : y; })
+</pre></div>
+<p>
+Definition at line <a class="el" href="dwc__otg__cfi_8h-source.html#l00070">70</a> of file <a class="el" href="dwc__otg__cfi_8h-source.html">dwc_otg_cfi.h</a>.
+</div>
+</div><p>
+<hr><h2>Typedef Documentation</h2>
+<a class="anchor" name="226b99dcff1992adefa086b6c7773eff"></a><!-- doxytag: member="dwc_otg_cfi.h::cfi_ops_t" ref="226b99dcff1992adefa086b6c7773eff" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef struct <a class="el" href="structcfi__ops.html">cfi_ops</a>  <a class="el" href="structcfi__ops.html">cfi_ops_t</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This is the interface for the CFI operations. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>ep_enable</em>&nbsp;</td><td>Called when any endpoint is enabled and activated. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>release</em>&nbsp;</td><td>Called when the CFI object is released and it needs to correctly deallocate the dynamic memory </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ctrl_write_complete</em>&nbsp;</td><td>Called when the data stage of the request is complete </td></tr>
+  </table>
+</dl>
+
+</div>
+</div><p>
+<hr><h2>Variable Documentation</h2>
+<a class="anchor" name="1c517724be71d3c12952486ba172c0b6"></a><!-- doxytag: member="dwc_otg_cfi.h::packed" ref="1c517724be71d3c12952486ba172c0b6" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">struct <a class="el" href="struct__ddma__sg__buffer__setup.html">_ddma_sg_buffer_setup</a> <a class="el" href="dwc__otg__cfi_8h.html#3e7b3a7aca62be5747bfe900e0a9e102">packed</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Descriptor DMA SG Buffer setup structure (SG buffer). 
+<p>
+This structure is also used for setting up a buffer for Circular DDMA. 
+</div>
+</div><p>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil_8c-source.html b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil_8c-source.html
new file mode 100644
index 000000000000..f7684d695faf
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil_8c-source.html
@@ -0,0 +1,4922 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_cil.c Source File</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<h1>dwc_otg_cil.c</h1><a href="dwc__otg__cil_8c.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">/* ==========================================================================</span>
+<a name="l00002"></a>00002 <span class="comment"> * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.c $</span>
+<a name="l00003"></a>00003 <span class="comment"> * $Revision: #159 $</span>
+<a name="l00004"></a>00004 <span class="comment"> * $Date: 2009/04/21 $</span>
+<a name="l00005"></a>00005 <span class="comment"> * $Change: 1237465 $</span>
+<a name="l00006"></a>00006 <span class="comment"> *</span>
+<a name="l00007"></a>00007 <span class="comment"> * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,</span>
+<a name="l00008"></a>00008 <span class="comment"> * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless</span>
+<a name="l00009"></a>00009 <span class="comment"> * otherwise expressly agreed to in writing between Synopsys and you.</span>
+<a name="l00010"></a>00010 <span class="comment"> * </span>
+<a name="l00011"></a>00011 <span class="comment"> * The Software IS NOT an item of Licensed Software or Licensed Product under</span>
+<a name="l00012"></a>00012 <span class="comment"> * any End User Software License Agreement or Agreement for Licensed Product</span>
+<a name="l00013"></a>00013 <span class="comment"> * with Synopsys or any supplement thereto. You are permitted to use and</span>
+<a name="l00014"></a>00014 <span class="comment"> * redistribute this Software in source and binary forms, with or without</span>
+<a name="l00015"></a>00015 <span class="comment"> * modification, provided that redistributions of source code must retain this</span>
+<a name="l00016"></a>00016 <span class="comment"> * notice. You may not view, use, disclose, copy or distribute this file or</span>
+<a name="l00017"></a>00017 <span class="comment"> * any information contained herein except pursuant to this license grant from</span>
+<a name="l00018"></a>00018 <span class="comment"> * Synopsys. If you do not agree with this notice, including the disclaimer</span>
+<a name="l00019"></a>00019 <span class="comment"> * below, then you are not authorized to use the Software.</span>
+<a name="l00020"></a>00020 <span class="comment"> * </span>
+<a name="l00021"></a>00021 <span class="comment"> * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS</span>
+<a name="l00022"></a>00022 <span class="comment"> * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE</span>
+<a name="l00023"></a>00023 <span class="comment"> * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE</span>
+<a name="l00024"></a>00024 <span class="comment"> * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,</span>
+<a name="l00025"></a>00025 <span class="comment"> * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES</span>
+<a name="l00026"></a>00026 <span class="comment"> * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR</span>
+<a name="l00027"></a>00027 <span class="comment"> * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER</span>
+<a name="l00028"></a>00028 <span class="comment"> * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT</span>
+<a name="l00029"></a>00029 <span class="comment"> * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY</span>
+<a name="l00030"></a>00030 <span class="comment"> * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH</span>
+<a name="l00031"></a>00031 <span class="comment"> * DAMAGE.</span>
+<a name="l00032"></a>00032 <span class="comment"> * ========================================================================== */</span>
+<a name="l00033"></a>00033 
+<a name="l00060"></a>00060 <span class="preprocessor">#include "dwc_os.h"</span>
+<a name="l00061"></a>00061 <span class="preprocessor">#include "<a class="code" href="dwc__otg__regs_8h.html">dwc_otg_regs.h</a>"</span>
+<a name="l00062"></a>00062 <span class="preprocessor">#include "<a class="code" href="dwc__otg__cil_8h.html">dwc_otg_cil.h</a>"</span>
+<a name="l00063"></a>00063 
+<a name="l00064"></a>00064 <span class="keyword">static</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#2be12d7b5990c6eaac2f1a5fb688f2f8">dwc_otg_setup_params</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if);
+<a name="l00065"></a>00065 
+<a name="l00078"></a><a class="code" href="dwc__otg__core__if_8h.html#cd21205476fda6e8106730c3502f097b">00078</a> <a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *<a class="code" href="dwc__otg__cil_8c.html#2dc0a6c5541c1a8a014d66a8fce53f66">dwc_otg_cil_init</a>(<span class="keyword">const</span> uint32_t * reg_base_addr)
+<a name="l00079"></a>00079 {
+<a name="l00080"></a>00080         <a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if = 0;
+<a name="l00081"></a>00081         <a class="code" href="structdwc__otg__dev__if.html">dwc_otg_dev_if_t</a> *dev_if = 0;
+<a name="l00082"></a>00082         <a class="code" href="structdwc__otg__host__if.html">dwc_otg_host_if_t</a> *host_if = 0;
+<a name="l00083"></a>00083         uint8_t *reg_base = (uint8_t *) reg_base_addr;
+<a name="l00084"></a>00084         <span class="keywordtype">int</span> i = 0;
+<a name="l00085"></a>00085 
+<a name="l00086"></a>00086         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#daab8e158c0c530486656ef52e5b0bbe">DBG_CILV</a>, <span class="stringliteral">"%s(%p)\n"</span>, __func__, reg_base_addr);
+<a name="l00087"></a>00087 
+<a name="l00088"></a>00088         core_if = dwc_alloc(<span class="keyword">sizeof</span>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a>));
+<a name="l00089"></a>00089 
+<a name="l00090"></a>00090         <span class="keywordflow">if</span> (core_if == 0) {
+<a name="l00091"></a>00091                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">DBG_CIL</a>,
+<a name="l00092"></a>00092                             <span class="stringliteral">"Allocation of dwc_otg_core_if_t failed\n"</span>);
+<a name="l00093"></a>00093                 <span class="keywordflow">return</span> 0;
+<a name="l00094"></a>00094         }
+<a name="l00095"></a>00095         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a> = (<a class="code" href="structdwc__otg__core__global__regs.html">dwc_otg_core_global_regs_t</a> *) reg_base;
+<a name="l00096"></a>00096 
+<a name="l00097"></a>00097         <span class="comment">/*</span>
+<a name="l00098"></a>00098 <span class="comment">         * Allocate the Device Mode structures.</span>
+<a name="l00099"></a>00099 <span class="comment">         */</span>
+<a name="l00100"></a>00100         dev_if = dwc_alloc(<span class="keyword">sizeof</span>(<a class="code" href="structdwc__otg__dev__if.html">dwc_otg_dev_if_t</a>));
+<a name="l00101"></a>00101 
+<a name="l00102"></a>00102         <span class="keywordflow">if</span> (dev_if == 0) {
+<a name="l00103"></a>00103                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">DBG_CIL</a>, <span class="stringliteral">"Allocation of dwc_otg_dev_if_t failed\n"</span>);
+<a name="l00104"></a>00104                 dwc_free(core_if);
+<a name="l00105"></a>00105                 <span class="keywordflow">return</span> 0;
+<a name="l00106"></a>00106         }
+<a name="l00107"></a>00107 
+<a name="l00108"></a>00108         dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a> =
+<a name="l00109"></a>00109             (<a class="code" href="structdwc__otg__dev__global__regs.html">dwc_otg_device_global_regs_t</a> *) (reg_base +
+<a name="l00110"></a>00110                                               <a class="code" href="dwc__otg__regs_8h.html#4ea9445cbc89c8cc6bbf01c9dd7a9883">DWC_DEV_GLOBAL_REG_OFFSET</a>);
+<a name="l00111"></a>00111 
+<a name="l00112"></a>00112         <span class="keywordflow">for</span> (i = 0; i &lt; <a class="code" href="dwc__otg__core__if_8h.html#bfb88b45545f7685f668ac2f545674ec">MAX_EPS_CHANNELS</a>; i++) {
+<a name="l00113"></a>00113                 dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[i] = (<a class="code" href="structdwc__otg__dev__in__ep__regs.html">dwc_otg_dev_in_ep_regs_t</a> *)
+<a name="l00114"></a>00114                     (reg_base + <a class="code" href="dwc__otg__regs_8h.html#57eeaae2d9cf530fbae00d3f462cc7da">DWC_DEV_IN_EP_REG_OFFSET</a> +
+<a name="l00115"></a>00115                      (i * <a class="code" href="dwc__otg__regs_8h.html#c9c83030effbf067775d9111e4d90895">DWC_EP_REG_OFFSET</a>));
+<a name="l00116"></a>00116 
+<a name="l00117"></a>00117                 dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">out_ep_regs</a>[i] = (<a class="code" href="structdwc__otg__dev__out__ep__regs.html">dwc_otg_dev_out_ep_regs_t</a> *)
+<a name="l00118"></a>00118                     (reg_base + <a class="code" href="dwc__otg__regs_8h.html#7234e42a2bcd47aca0d67a414eb0598e">DWC_DEV_OUT_EP_REG_OFFSET</a> +
+<a name="l00119"></a>00119                      (i * DWC_EP_REG_OFFSET));
+<a name="l00120"></a>00120                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#daab8e158c0c530486656ef52e5b0bbe">DBG_CILV</a>, <span class="stringliteral">"in_ep_regs[%d]-&gt;diepctl=%p\n"</span>,
+<a name="l00121"></a>00121                             i, &amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[i]-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#53a5adb977e2aec66d4902c6ba293216">diepctl</a>);
+<a name="l00122"></a>00122                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(DBG_CILV, <span class="stringliteral">"out_ep_regs[%d]-&gt;doepctl=%p\n"</span>,
+<a name="l00123"></a>00123                             i, &amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">out_ep_regs</a>[i]-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#2a522b71fc97658c07debf3521f7d3e5">doepctl</a>);
+<a name="l00124"></a>00124         }
+<a name="l00125"></a>00125 
+<a name="l00126"></a>00126         dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#8a602da4cbdc4fc88c785471426ed63c">speed</a> = 0;      <span class="comment">// unknown</span>
+<a name="l00127"></a>00127 
+<a name="l00128"></a>00128         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a> = dev_if;
+<a name="l00129"></a>00129 
+<a name="l00130"></a>00130         <span class="comment">/*</span>
+<a name="l00131"></a>00131 <span class="comment">         * Allocate the Host Mode structures.</span>
+<a name="l00132"></a>00132 <span class="comment">         */</span>
+<a name="l00133"></a>00133         host_if = dwc_alloc(<span class="keyword">sizeof</span>(<a class="code" href="structdwc__otg__host__if.html">dwc_otg_host_if_t</a>));
+<a name="l00134"></a>00134 
+<a name="l00135"></a>00135         <span class="keywordflow">if</span> (host_if == 0) {
+<a name="l00136"></a>00136                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">DBG_CIL</a>,
+<a name="l00137"></a>00137                             <span class="stringliteral">"Allocation of dwc_otg_host_if_t failed\n"</span>);
+<a name="l00138"></a>00138                 dwc_free(dev_if);
+<a name="l00139"></a>00139                 dwc_free(core_if);
+<a name="l00140"></a>00140                 <span class="keywordflow">return</span> 0;
+<a name="l00141"></a>00141         }
+<a name="l00142"></a>00142 
+<a name="l00143"></a>00143         host_if-&gt;<a class="code" href="structdwc__otg__host__if.html#ff9692c2e10ca2bc7e24f981f25179c2">host_global_regs</a> = (<a class="code" href="structdwc__otg__host__global__regs.html">dwc_otg_host_global_regs_t</a> *)
+<a name="l00144"></a>00144             (reg_base + <a class="code" href="dwc__otg__regs_8h.html#b9ef775c8628a8f225e36729cf1be0c3">DWC_OTG_HOST_GLOBAL_REG_OFFSET</a>);
+<a name="l00145"></a>00145 
+<a name="l00146"></a>00146         host_if-&gt;<a class="code" href="structdwc__otg__host__if.html#dc8fe33e0bb3829cafa884d5fc603c4d">hprt0</a> =
+<a name="l00147"></a>00147             (uint32_t *) (reg_base + <a class="code" href="dwc__otg__regs_8h.html#d34097dedb09e076ae91cef4ab3b4b2a">DWC_OTG_HOST_PORT_REGS_OFFSET</a>);
+<a name="l00148"></a>00148 
+<a name="l00149"></a>00149         <span class="keywordflow">for</span> (i = 0; i &lt; MAX_EPS_CHANNELS; i++) {
+<a name="l00150"></a>00150                 host_if-&gt;<a class="code" href="structdwc__otg__host__if.html#7f7c107d4720641eb4141cd817211ac0">hc_regs</a>[i] = (<a class="code" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *)
+<a name="l00151"></a>00151                     (reg_base + <a class="code" href="dwc__otg__regs_8h.html#76dd0c82028245c6a217ad7ee366cf15">DWC_OTG_HOST_CHAN_REGS_OFFSET</a> +
+<a name="l00152"></a>00152                      (i * <a class="code" href="dwc__otg__regs_8h.html#850bdd3d5997cdf22bf69fe0a0df6be1">DWC_OTG_CHAN_REGS_OFFSET</a>));
+<a name="l00153"></a>00153                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#daab8e158c0c530486656ef52e5b0bbe">DBG_CILV</a>, <span class="stringliteral">"hc_reg[%d]-&gt;hcchar=%p\n"</span>,
+<a name="l00154"></a>00154                             i, &amp;host_if-&gt;<a class="code" href="structdwc__otg__host__if.html#7f7c107d4720641eb4141cd817211ac0">hc_regs</a>[i]-&gt;<a class="code" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">hcchar</a>);
+<a name="l00155"></a>00155         }
+<a name="l00156"></a>00156 
+<a name="l00157"></a>00157         host_if-&gt;<a class="code" href="structdwc__otg__host__if.html#a7b144c7f83d79fdafd7cd0c8c06102d">num_host_channels</a> = MAX_EPS_CHANNELS;
+<a name="l00158"></a>00158         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a> = host_if;
+<a name="l00159"></a>00159 
+<a name="l00160"></a>00160         <span class="keywordflow">for</span> (i = 0; i &lt; MAX_EPS_CHANNELS; i++) {
+<a name="l00161"></a>00161                 core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#f99c868784a8269073bc251f88d92ee4">data_fifo</a>[i] =
+<a name="l00162"></a>00162                     (uint32_t *) (reg_base + <a class="code" href="dwc__otg__cil_8h.html#921e7968f6c39c1d7c8d3b4b95a4f4eb">DWC_OTG_DATA_FIFO_OFFSET</a> +
+<a name="l00163"></a>00163                                   (i * <a class="code" href="dwc__otg__cil_8h.html#b7aa34c1f7efae9b69e2891fea7b615f">DWC_OTG_DATA_FIFO_SIZE</a>));
+<a name="l00164"></a>00164                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#daab8e158c0c530486656ef52e5b0bbe">DBG_CILV</a>, <span class="stringliteral">"data_fifo[%d]=0x%08x\n"</span>,
+<a name="l00165"></a>00165                             i, (<span class="keywordtype">unsigned</span>)core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#f99c868784a8269073bc251f88d92ee4">data_fifo</a>[i]);
+<a name="l00166"></a>00166         }
+<a name="l00167"></a>00167 
+<a name="l00168"></a>00168         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#348ed2c9aeae6fc608f1bb813978b3f9">pcgcctl</a> = (uint32_t *) (reg_base + <a class="code" href="dwc__otg__cil_8h.html#1e6c4a07594b33ba981e3664a2f3366c">DWC_OTG_PCGCCTL_OFFSET</a>);
+<a name="l00169"></a>00169 
+<a name="l00170"></a>00170         <span class="comment">/* Initiate lx_state to L3 disconnected state */</span>
+<a name="l00171"></a>00171         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#2b0701d814069ec69897e08374366c7b">lx_state</a> = <a class="code" href="dwc__otg__cil_8h.html#8442e49b7c783099ac17bda4f8b3bc3c86715d528a59b114b95aaafa8f2142f6">DWC_OTG_L3</a>;
+<a name="l00172"></a>00172         <span class="comment">/*</span>
+<a name="l00173"></a>00173 <span class="comment">         * Store the contents of the hardware configuration registers here for</span>
+<a name="l00174"></a>00174 <span class="comment">         * easy access later.</span>
+<a name="l00175"></a>00175 <span class="comment">         */</span>
+<a name="l00176"></a>00176         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#d7c6a00c6d7c157ff60a044a28ec8b95">hwcfg1</a>.<a class="code" href="unionhwcfg1__data.html#9ca836052f9bd01e0b70902862ed09a4">d32</a> =
+<a name="l00177"></a>00177             dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#56d2988ff8fedbbde479ffe8d4e84b75">ghwcfg1</a>);
+<a name="l00178"></a>00178         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">hwcfg2</a>.<a class="code" href="unionhwcfg2__data.html#2a2482b24bbfa8cdd589e376184d1e3b">d32</a> =
+<a name="l00179"></a>00179             dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#b0f241f53ca7b3be1c94bd684ed61f79">ghwcfg2</a>);
+<a name="l00180"></a>00180         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#91d0e0a5e8e048024c8846d12e00cecc">hwcfg3</a>.<a class="code" href="unionhwcfg3__data.html#9daf160f3fc0cc8e4e68c037f6c2f9d7">d32</a> =
+<a name="l00181"></a>00181             dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#57ddcc14f581f5d6276122f9747aff72">ghwcfg3</a>);
+<a name="l00182"></a>00182         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#9c1394f3c46adde2fa7be79bf0237f9b">hwcfg4</a>.<a class="code" href="unionhwcfg4__data.html#edcdf66b3add0e05ce0006b0b0de8dd0">d32</a> =
+<a name="l00183"></a>00183             dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#e1df73c776d3b31d5f0a501ccdeb1d2d">ghwcfg4</a>);
+<a name="l00184"></a>00184 
+<a name="l00185"></a>00185         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#daab8e158c0c530486656ef52e5b0bbe">DBG_CILV</a>, <span class="stringliteral">"hwcfg1=%08x\n"</span>, core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#d7c6a00c6d7c157ff60a044a28ec8b95">hwcfg1</a>.<a class="code" href="unionhwcfg1__data.html#9ca836052f9bd01e0b70902862ed09a4">d32</a>);
+<a name="l00186"></a>00186         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#daab8e158c0c530486656ef52e5b0bbe">DBG_CILV</a>, <span class="stringliteral">"hwcfg2=%08x\n"</span>, core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">hwcfg2</a>.<a class="code" href="unionhwcfg2__data.html#2a2482b24bbfa8cdd589e376184d1e3b">d32</a>);
+<a name="l00187"></a>00187         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#daab8e158c0c530486656ef52e5b0bbe">DBG_CILV</a>, <span class="stringliteral">"hwcfg3=%08x\n"</span>, core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#91d0e0a5e8e048024c8846d12e00cecc">hwcfg3</a>.<a class="code" href="unionhwcfg3__data.html#9daf160f3fc0cc8e4e68c037f6c2f9d7">d32</a>);
+<a name="l00188"></a>00188         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#daab8e158c0c530486656ef52e5b0bbe">DBG_CILV</a>, <span class="stringliteral">"hwcfg4=%08x\n"</span>, core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#9c1394f3c46adde2fa7be79bf0237f9b">hwcfg4</a>.<a class="code" href="unionhwcfg4__data.html#edcdf66b3add0e05ce0006b0b0de8dd0">d32</a>);
+<a name="l00189"></a>00189 
+<a name="l00190"></a>00190         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#447a626f22ad64a90c68a6f49e624eb8">hcfg</a>.<a class="code" href="unionhcfg__data.html#381a253b3a38a7f943dcbb42f7bf10be">d32</a> =
+<a name="l00191"></a>00191             dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#ff9692c2e10ca2bc7e24f981f25179c2">host_global_regs</a>-&gt;<a class="code" href="structdwc__otg__host__global__regs.html#fd7d93b5ffcb6c7c0a84ef656e6e68de">hcfg</a>);
+<a name="l00192"></a>00192         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#fcce854acc5b4afca80bd5667ecc4ef2">dcfg</a>.<a class="code" href="uniondcfg__data.html#efd84d3306db1b4370535a0e814612dc">d32</a> =
+<a name="l00193"></a>00193             dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#c0c24937bbd7184884f05343f56ef1da">dcfg</a>);
+<a name="l00194"></a>00194 
+<a name="l00195"></a>00195         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#daab8e158c0c530486656ef52e5b0bbe">DBG_CILV</a>, <span class="stringliteral">"hcfg=%08x\n"</span>, core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#447a626f22ad64a90c68a6f49e624eb8">hcfg</a>.<a class="code" href="unionhcfg__data.html#381a253b3a38a7f943dcbb42f7bf10be">d32</a>);
+<a name="l00196"></a>00196         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#daab8e158c0c530486656ef52e5b0bbe">DBG_CILV</a>, <span class="stringliteral">"dcfg=%08x\n"</span>, core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#fcce854acc5b4afca80bd5667ecc4ef2">dcfg</a>.<a class="code" href="uniondcfg__data.html#efd84d3306db1b4370535a0e814612dc">d32</a>);
+<a name="l00197"></a>00197 
+<a name="l00198"></a>00198         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#daab8e158c0c530486656ef52e5b0bbe">DBG_CILV</a>, <span class="stringliteral">"op_mode=%0x\n"</span>, core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">hwcfg2</a>.<a class="code" href="unionhwcfg2__data.html#9dcc70e2dba617cbc6c12189be5c1d6a">b</a>.<a class="code" href="unionhwcfg2__data.html#592df9b97ff9342b839d2ed76d54c652">op_mode</a>);
+<a name="l00199"></a>00199         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#daab8e158c0c530486656ef52e5b0bbe">DBG_CILV</a>, <span class="stringliteral">"arch=%0x\n"</span>, core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">hwcfg2</a>.<a class="code" href="unionhwcfg2__data.html#9dcc70e2dba617cbc6c12189be5c1d6a">b</a>.<a class="code" href="unionhwcfg2__data.html#e5000f58c6a0f09c75375b4c912af0eb">architecture</a>);
+<a name="l00200"></a>00200         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#daab8e158c0c530486656ef52e5b0bbe">DBG_CILV</a>, <span class="stringliteral">"num_dev_ep=%d\n"</span>, core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">hwcfg2</a>.<a class="code" href="unionhwcfg2__data.html#9dcc70e2dba617cbc6c12189be5c1d6a">b</a>.<a class="code" href="unionhwcfg2__data.html#9f827f334b58643849598ce1fa314c5a">num_dev_ep</a>);
+<a name="l00201"></a>00201         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#daab8e158c0c530486656ef52e5b0bbe">DBG_CILV</a>, <span class="stringliteral">"num_host_chan=%d\n"</span>,
+<a name="l00202"></a>00202                     core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">hwcfg2</a>.<a class="code" href="unionhwcfg2__data.html#9dcc70e2dba617cbc6c12189be5c1d6a">b</a>.<a class="code" href="unionhwcfg2__data.html#83708a4d45e8d019892367c5ae9f6fd0">num_host_chan</a>);
+<a name="l00203"></a>00203         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#daab8e158c0c530486656ef52e5b0bbe">DBG_CILV</a>, <span class="stringliteral">"nonperio_tx_q_depth=0x%0x\n"</span>,
+<a name="l00204"></a>00204                     core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">hwcfg2</a>.<a class="code" href="unionhwcfg2__data.html#9dcc70e2dba617cbc6c12189be5c1d6a">b</a>.<a class="code" href="unionhwcfg2__data.html#1369a191c7bd2f717cef2bce7a97ee67">nonperio_tx_q_depth</a>);
+<a name="l00205"></a>00205         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#daab8e158c0c530486656ef52e5b0bbe">DBG_CILV</a>, <span class="stringliteral">"host_perio_tx_q_depth=0x%0x\n"</span>,
+<a name="l00206"></a>00206                     core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">hwcfg2</a>.<a class="code" href="unionhwcfg2__data.html#9dcc70e2dba617cbc6c12189be5c1d6a">b</a>.<a class="code" href="unionhwcfg2__data.html#857bb59069e203a94ffd32538c60058f">host_perio_tx_q_depth</a>);
+<a name="l00207"></a>00207         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#daab8e158c0c530486656ef52e5b0bbe">DBG_CILV</a>, <span class="stringliteral">"dev_token_q_depth=0x%0x\n"</span>,
+<a name="l00208"></a>00208                     core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">hwcfg2</a>.<a class="code" href="unionhwcfg2__data.html#9dcc70e2dba617cbc6c12189be5c1d6a">b</a>.<a class="code" href="unionhwcfg2__data.html#ba242467585b60b4d3db9882e0f39b3f">dev_token_q_depth</a>);
+<a name="l00209"></a>00209 
+<a name="l00210"></a>00210         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#daab8e158c0c530486656ef52e5b0bbe">DBG_CILV</a>, <span class="stringliteral">"Total FIFO SZ=%d\n"</span>,
+<a name="l00211"></a>00211                     core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#91d0e0a5e8e048024c8846d12e00cecc">hwcfg3</a>.<a class="code" href="unionhwcfg3__data.html#928c5de42f8af177ce34712123b5093c">b</a>.<a class="code" href="unionhwcfg3__data.html#f885715ddb953dbe95acc08e49264706">dfifo_depth</a>);
+<a name="l00212"></a>00212         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#daab8e158c0c530486656ef52e5b0bbe">DBG_CILV</a>, <span class="stringliteral">"xfer_size_cntr_width=%0x\n"</span>,
+<a name="l00213"></a>00213                     core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#91d0e0a5e8e048024c8846d12e00cecc">hwcfg3</a>.<a class="code" href="unionhwcfg3__data.html#928c5de42f8af177ce34712123b5093c">b</a>.<a class="code" href="unionhwcfg3__data.html#66f311995decf2f11d620aa6a56fa26e">xfer_size_cntr_width</a>);
+<a name="l00214"></a>00214 
+<a name="l00215"></a>00215         <span class="comment">/*</span>
+<a name="l00216"></a>00216 <span class="comment">         * Set the SRP sucess bit for FS-I2c</span>
+<a name="l00217"></a>00217 <span class="comment">         */</span>
+<a name="l00218"></a>00218         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#c2bb1913ed3fcc082a06d70242e9768a">srp_success</a> = 0;
+<a name="l00219"></a>00219         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#749cdeef193b7590b036a9b1d1442b73">srp_timer_started</a> = 0;
+<a name="l00220"></a>00220 
+<a name="l00221"></a>00221         <span class="comment">/*</span>
+<a name="l00222"></a>00222 <span class="comment">         * Create new workqueue and init works</span>
+<a name="l00223"></a>00223 <span class="comment">         */</span>
+<a name="l00224"></a>00224         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3716f6d6bc6f956a45efbe6e308386">wq_otg</a> = DWC_WORKQ_ALLOC(<span class="stringliteral">"dwc_otg"</span>);
+<a name="l00225"></a>00225         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3716f6d6bc6f956a45efbe6e308386">wq_otg</a> == 0) {
+<a name="l00226"></a>00226                 DWC_WARN(<span class="stringliteral">"DWC_WORKQ_ALLOC failed\n"</span>);
+<a name="l00227"></a>00227                 dwc_free(host_if);
+<a name="l00228"></a>00228                 dwc_free(dev_if);
+<a name="l00229"></a>00229                 dwc_free(core_if);
+<a name="l00230"></a>00230                 <span class="keywordflow">return</span> 0;
+<a name="l00231"></a>00231         }
+<a name="l00232"></a>00232 
+<a name="l00233"></a>00233         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#afc495591efa54c74c1dd50278b57ffe">snpsid</a> = dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#30798436df220217c3960ac4a46710dc">gsnpsid</a>);
+<a name="l00234"></a>00234 
+<a name="l00235"></a>00235         DWC_PRINTF(<span class="stringliteral">"Core Release: %x.%x%x%x\n"</span>,
+<a name="l00236"></a>00236                    (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#afc495591efa54c74c1dd50278b57ffe">snpsid</a> &gt;&gt; 12 &amp; 0xF),
+<a name="l00237"></a>00237                    (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#afc495591efa54c74c1dd50278b57ffe">snpsid</a> &gt;&gt; 8 &amp; 0xF),
+<a name="l00238"></a>00238                    (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#afc495591efa54c74c1dd50278b57ffe">snpsid</a> &gt;&gt; 4 &amp; 0xF), (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#afc495591efa54c74c1dd50278b57ffe">snpsid</a> &amp; 0xF));
+<a name="l00239"></a>00239 
+<a name="l00240"></a>00240         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#c914461f460deacd426bea7a05ebb204">wkp_timer</a> = DWC_TIMER_ALLOC(<span class="stringliteral">"Wake Up Timer"</span>,
+<a name="l00241"></a>00241                                              <a class="code" href="dwc__otg__cil_8h.html#07f0b189448c71e7ea4c7b121320fb89">w_wakeup_detected</a>, core_if);
+<a name="l00242"></a>00242         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#c914461f460deacd426bea7a05ebb204">wkp_timer</a> == 0) {
+<a name="l00243"></a>00243                 DWC_WARN(<span class="stringliteral">"DWC_TIMER_ALLOC failed\n"</span>);
+<a name="l00244"></a>00244                 dwc_free(host_if);
+<a name="l00245"></a>00245                 dwc_free(dev_if);
+<a name="l00246"></a>00246                 DWC_WORKQ_FREE(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3716f6d6bc6f956a45efbe6e308386">wq_otg</a>);
+<a name="l00247"></a>00247                 dwc_free(core_if);
+<a name="l00248"></a>00248                 <span class="keywordflow">return</span> 0;
+<a name="l00249"></a>00249         }
+<a name="l00250"></a>00250 
+<a name="l00251"></a>00251         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#2be12d7b5990c6eaac2f1a5fb688f2f8">dwc_otg_setup_params</a>(core_if)) {
+<a name="l00252"></a>00252                 DWC_WARN(<span class="stringliteral">"Error while setting core params\n"</span>);
+<a name="l00253"></a>00253         }
+<a name="l00254"></a>00254 
+<a name="l00255"></a>00255         <span class="keywordflow">return</span> core_if;
+<a name="l00256"></a>00256 }
+<a name="l00257"></a>00257 
+<a name="l00265"></a><a class="code" href="dwc__otg__core__if_8h.html#c942f856a93287803eba8c84846730ac">00265</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#cc4a08b278c7afe0484b595cacf80c04">dwc_otg_cil_remove</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l00266"></a>00266 {
+<a name="l00267"></a>00267         <span class="comment">/* Disable all interrupts */</span>
+<a name="l00268"></a>00268         dwc_modify_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#537c95e57269fabf29c6b36ad8e1ed45">gahbcfg</a>, 1, 0);
+<a name="l00269"></a>00269         dwc_write_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#48827c76da2c6b18f369e2f2483cc4b6">gintmsk</a>, 0);
+<a name="l00270"></a>00270 
+<a name="l00271"></a>00271         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3716f6d6bc6f956a45efbe6e308386">wq_otg</a>) {
+<a name="l00272"></a>00272                 DWC_WORKQ_WAIT_WORK_DONE(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3716f6d6bc6f956a45efbe6e308386">wq_otg</a>, 500);
+<a name="l00273"></a>00273                 DWC_WORKQ_FREE(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3716f6d6bc6f956a45efbe6e308386">wq_otg</a>);
+<a name="l00274"></a>00274         }
+<a name="l00275"></a>00275         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>) {
+<a name="l00276"></a>00276                 dwc_free(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>);
+<a name="l00277"></a>00277         }
+<a name="l00278"></a>00278         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>) {
+<a name="l00279"></a>00279                 dwc_free(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>);
+<a name="l00280"></a>00280         }
+<a name="l00281"></a>00281         dwc_free(core_if);
+<a name="l00282"></a>00282         DWC_TIMER_FREE(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#c914461f460deacd426bea7a05ebb204">wkp_timer</a>);
+<a name="l00283"></a>00283         DWC_FREE(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>);
+<a name="l00284"></a>00284 }
+<a name="l00285"></a>00285 
+<a name="l00292"></a><a class="code" href="dwc__otg__core__if_8h.html#90b4321b4979bcfdb71fb41aa66a6ce2">00292</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#8b0b841d69298089b7d03b07ade8eda6">dwc_otg_enable_global_interrupts</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l00293"></a>00293 {
+<a name="l00294"></a>00294         <a class="code" href="uniongahbcfg__data.html">gahbcfg_data_t</a> ahbcfg = {.d32 = 0 };
+<a name="l00295"></a>00295         ahbcfg.<a class="code" href="uniongahbcfg__data.html#aa9726048597c5bb54ea38eda976e1a4">b</a>.<a class="code" href="uniongahbcfg__data.html#f75957f35be7ecd70616f5d0bcfb1e51">glblintrmsk</a> = 1;       <span class="comment">/* Enable interrupts */</span>
+<a name="l00296"></a>00296         dwc_modify_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#537c95e57269fabf29c6b36ad8e1ed45">gahbcfg</a>, 0, ahbcfg.<a class="code" href="uniongahbcfg__data.html#2532b75f838946009af8806c924f0c08">d32</a>);
+<a name="l00297"></a>00297 }
+<a name="l00298"></a>00298 
+<a name="l00305"></a><a class="code" href="dwc__otg__core__if_8h.html#fe39ea4a5daa6dd32e12a42a82b3a463">00305</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#9f673c38ca761d8ab7b3333b506bcbfc">dwc_otg_disable_global_interrupts</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l00306"></a>00306 {
+<a name="l00307"></a>00307         <a class="code" href="uniongahbcfg__data.html">gahbcfg_data_t</a> ahbcfg = {.d32 = 0 };
+<a name="l00308"></a>00308         ahbcfg.<a class="code" href="uniongahbcfg__data.html#aa9726048597c5bb54ea38eda976e1a4">b</a>.<a class="code" href="uniongahbcfg__data.html#f75957f35be7ecd70616f5d0bcfb1e51">glblintrmsk</a> = 1;       <span class="comment">/* Enable interrupts */</span>
+<a name="l00309"></a>00309         dwc_modify_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#537c95e57269fabf29c6b36ad8e1ed45">gahbcfg</a>, ahbcfg.<a class="code" href="uniongahbcfg__data.html#2532b75f838946009af8806c924f0c08">d32</a>, 0);
+<a name="l00310"></a>00310 }
+<a name="l00311"></a>00311 
+<a name="l00319"></a><a class="code" href="dwc__otg__cil_8c.html#1761ac95e17bad3fa304413cc81c51de">00319</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#1761ac95e17bad3fa304413cc81c51de">dwc_otg_enable_common_interrupts</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l00320"></a>00320 {
+<a name="l00321"></a>00321         <a class="code" href="structdwc__otg__core__global__regs.html">dwc_otg_core_global_regs_t</a> *global_regs = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>;
+<a name="l00322"></a>00322         <a class="code" href="uniongintmsk__data.html">gintmsk_data_t</a> intr_mask = {.d32 = 0 };
+<a name="l00323"></a>00323 
+<a name="l00324"></a>00324         <span class="comment">/* Clear any pending OTG Interrupts */</span>
+<a name="l00325"></a>00325         dwc_write_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#69cc290cfdfe6900890f7a5a16b3137c">gotgint</a>, 0xFFFFFFFF);
+<a name="l00326"></a>00326 
+<a name="l00327"></a>00327         <span class="comment">/* Clear any pending interrupts */</span>
+<a name="l00328"></a>00328         dwc_write_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>, 0xFFFFFFFF);
+<a name="l00329"></a>00329 
+<a name="l00330"></a>00330         <span class="comment">/* </span>
+<a name="l00331"></a>00331 <span class="comment">         * Enable the interrupts in the GINTMSK. </span>
+<a name="l00332"></a>00332 <span class="comment">         */</span>
+<a name="l00333"></a>00333         intr_mask.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#f62315fe9de8bb3bc371cb0a51927496">modemismatch</a> = 1;
+<a name="l00334"></a>00334         intr_mask.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#6c9d578034af4f2ca08447fdac22ff88">otgintr</a> = 1;
+<a name="l00335"></a>00335 
+<a name="l00336"></a>00336         <span class="keywordflow">if</span> (!core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a>) {
+<a name="l00337"></a>00337                 intr_mask.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#83db45f92a3a692d79199e1a850c2a62">rxstsqlvl</a> = 1;
+<a name="l00338"></a>00338         }
+<a name="l00339"></a>00339 
+<a name="l00340"></a>00340         intr_mask.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#ade723f4f136cfa884e5bf536d913f14">conidstschng</a> = 1;
+<a name="l00341"></a>00341         intr_mask.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#d3cde0fd62a006ec3f5db615f1e62da5">wkupintr</a> = 1;
+<a name="l00342"></a>00342         intr_mask.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#0ff313bfc712a2f3d71bc1a5f1a17ce2">disconnect</a> = 1;
+<a name="l00343"></a>00343         intr_mask.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#3b93f1ae00dcd1dcc4d6d19547f26b56">usbsuspend</a> = 1;
+<a name="l00344"></a>00344         intr_mask.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#aabb586a72e2a76982bfaa780e482212">sessreqintr</a> = 1;
+<a name="l00345"></a>00345 <span class="preprocessor">#ifdef CONFIG_USB_DWC_OTG_LPM</span>
+<a name="l00346"></a>00346 <span class="preprocessor"></span>        <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#8b906ba765a10dd9fcfa1c02dbc0184e">lpm_enable</a>) {
+<a name="l00347"></a>00347                 intr_mask.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#24f9f89b33866c5dc7b16588bc94e103">lpmtranrcvd</a> = 1;
+<a name="l00348"></a>00348         }
+<a name="l00349"></a>00349 <span class="preprocessor">#endif</span>
+<a name="l00350"></a>00350 <span class="preprocessor"></span>        dwc_write_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#48827c76da2c6b18f369e2f2483cc4b6">gintmsk</a>, intr_mask.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a>);
+<a name="l00351"></a>00351 }
+<a name="l00352"></a>00352 
+<a name="l00357"></a><a class="code" href="dwc__otg__cil_8c.html#4550564b18dcd56bd2c4ec1ba91c6e13">00357</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#4550564b18dcd56bd2c4ec1ba91c6e13">init_fslspclksel</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l00358"></a>00358 {
+<a name="l00359"></a>00359         uint32_t val;
+<a name="l00360"></a>00360         <a class="code" href="unionhcfg__data.html">hcfg_data_t</a> hcfg;
+<a name="l00361"></a>00361 
+<a name="l00362"></a>00362         <span class="keywordflow">if</span> (((core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">hwcfg2</a>.<a class="code" href="unionhwcfg2__data.html#9dcc70e2dba617cbc6c12189be5c1d6a">b</a>.<a class="code" href="unionhwcfg2__data.html#a248a2502e3c440d7b6e4ad61d396f4e">hs_phy_type</a> == 2) &amp;&amp;
+<a name="l00363"></a>00363              (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">hwcfg2</a>.<a class="code" href="unionhwcfg2__data.html#9dcc70e2dba617cbc6c12189be5c1d6a">b</a>.<a class="code" href="unionhwcfg2__data.html#e75417d7e2d1843abf6e48f67851326e">fs_phy_type</a> == 1) &amp;&amp;
+<a name="l00364"></a>00364              (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#3d7cfc3c416010102b2c671dfaa828d5">ulpi_fs_ls</a>)) ||
+<a name="l00365"></a>00365             (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#8b5d4e0c98c46d0d4e80b6faf66daf72">phy_type</a> == <a class="code" href="dwc__otg__core__if_8h.html#f7395410ea596c4c660f61ff41cb38b8">DWC_PHY_TYPE_PARAM_FS</a>)) {
+<a name="l00366"></a>00366                 <span class="comment">/* Full speed PHY */</span>
+<a name="l00367"></a>00367                 val = <a class="code" href="dwc__otg__regs_8h.html#556ba73fd9346d666a7c0a28fcf993a7">DWC_HCFG_48_MHZ</a>;
+<a name="l00368"></a>00368         } <span class="keywordflow">else</span> {
+<a name="l00369"></a>00369                 <span class="comment">/* High speed PHY running at full speed or high speed */</span>
+<a name="l00370"></a>00370                 val = <a class="code" href="dwc__otg__regs_8h.html#398b117902d7a5594388a5086bb2de21">DWC_HCFG_30_60_MHZ</a>;
+<a name="l00371"></a>00371         }
+<a name="l00372"></a>00372 
+<a name="l00373"></a>00373         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">DBG_CIL</a>, <span class="stringliteral">"Initializing HCFG.FSLSPClkSel to 0x%1x\n"</span>, val);
+<a name="l00374"></a>00374         hcfg.<a class="code" href="unionhcfg__data.html#381a253b3a38a7f943dcbb42f7bf10be">d32</a> = dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#ff9692c2e10ca2bc7e24f981f25179c2">host_global_regs</a>-&gt;<a class="code" href="structdwc__otg__host__global__regs.html#fd7d93b5ffcb6c7c0a84ef656e6e68de">hcfg</a>);
+<a name="l00375"></a>00375         hcfg.<a class="code" href="unionhcfg__data.html#45bbb24387d58961dd2b8f2f65689bd7">b</a>.<a class="code" href="unionhcfg__data.html#e048ad3775c6794c3ee07af86079fadf">fslspclksel</a> = val;
+<a name="l00376"></a>00376         dwc_write_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#ff9692c2e10ca2bc7e24f981f25179c2">host_global_regs</a>-&gt;<a class="code" href="structdwc__otg__host__global__regs.html#fd7d93b5ffcb6c7c0a84ef656e6e68de">hcfg</a>, hcfg.<a class="code" href="unionhcfg__data.html#381a253b3a38a7f943dcbb42f7bf10be">d32</a>);
+<a name="l00377"></a>00377 }
+<a name="l00378"></a>00378 
+<a name="l00383"></a><a class="code" href="dwc__otg__cil_8c.html#6ef971c486eacd419d20e1bc545f9238">00383</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#6ef971c486eacd419d20e1bc545f9238">init_devspd</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l00384"></a>00384 {
+<a name="l00385"></a>00385         uint32_t val;
+<a name="l00386"></a>00386         <a class="code" href="uniondcfg__data.html">dcfg_data_t</a> dcfg;
+<a name="l00387"></a>00387 
+<a name="l00388"></a>00388         <span class="keywordflow">if</span> (((core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">hwcfg2</a>.<a class="code" href="unionhwcfg2__data.html#9dcc70e2dba617cbc6c12189be5c1d6a">b</a>.<a class="code" href="unionhwcfg2__data.html#a248a2502e3c440d7b6e4ad61d396f4e">hs_phy_type</a> == 2) &amp;&amp;
+<a name="l00389"></a>00389              (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">hwcfg2</a>.<a class="code" href="unionhwcfg2__data.html#9dcc70e2dba617cbc6c12189be5c1d6a">b</a>.<a class="code" href="unionhwcfg2__data.html#e75417d7e2d1843abf6e48f67851326e">fs_phy_type</a> == 1) &amp;&amp;
+<a name="l00390"></a>00390              (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#3d7cfc3c416010102b2c671dfaa828d5">ulpi_fs_ls</a>)) ||
+<a name="l00391"></a>00391             (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#8b5d4e0c98c46d0d4e80b6faf66daf72">phy_type</a> == <a class="code" href="dwc__otg__core__if_8h.html#f7395410ea596c4c660f61ff41cb38b8">DWC_PHY_TYPE_PARAM_FS</a>)) {
+<a name="l00392"></a>00392                 <span class="comment">/* Full speed PHY */</span>
+<a name="l00393"></a>00393                 val = 0x3;
+<a name="l00394"></a>00394         } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#d2c4f622f1c14f68c6e60e2603acd09d">speed</a> == <a class="code" href="dwc__otg__core__if_8h.html#353c64bfe6bbc9da8406528ad8220166">DWC_SPEED_PARAM_FULL</a>) {
+<a name="l00395"></a>00395                 <span class="comment">/* High speed PHY running at full speed */</span>
+<a name="l00396"></a>00396                 val = 0x1;
+<a name="l00397"></a>00397         } <span class="keywordflow">else</span> {
+<a name="l00398"></a>00398                 <span class="comment">/* High speed PHY running at high speed */</span>
+<a name="l00399"></a>00399                 val = 0x0;
+<a name="l00400"></a>00400         }
+<a name="l00401"></a>00401 
+<a name="l00402"></a>00402         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">DBG_CIL</a>, <span class="stringliteral">"Initializing DCFG.DevSpd to 0x%1x\n"</span>, val);
+<a name="l00403"></a>00403 
+<a name="l00404"></a>00404         dcfg.<a class="code" href="uniondcfg__data.html#efd84d3306db1b4370535a0e814612dc">d32</a> = dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#c0c24937bbd7184884f05343f56ef1da">dcfg</a>);
+<a name="l00405"></a>00405         dcfg.<a class="code" href="uniondcfg__data.html#242c1b463f445de3fc265e8c20fde50b">b</a>.<a class="code" href="uniondcfg__data.html#28ffb9fb43686fe553fbe80f1ead62a4">devspd</a> = val;
+<a name="l00406"></a>00406         dwc_write_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#c0c24937bbd7184884f05343f56ef1da">dcfg</a>, dcfg.<a class="code" href="uniondcfg__data.html#efd84d3306db1b4370535a0e814612dc">d32</a>);
+<a name="l00407"></a>00407 }
+<a name="l00408"></a>00408 
+<a name="l00415"></a><a class="code" href="dwc__otg__cil_8c.html#1cdde3ab3e53e93c5a42feed628aaf7d">00415</a> <span class="keyword">static</span> uint32_t <a class="code" href="dwc__otg__cil_8c.html#1cdde3ab3e53e93c5a42feed628aaf7d">calc_num_in_eps</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l00416"></a>00416 {
+<a name="l00417"></a>00417         uint32_t num_in_eps = 0;
+<a name="l00418"></a>00418         uint32_t num_eps = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">hwcfg2</a>.<a class="code" href="unionhwcfg2__data.html#9dcc70e2dba617cbc6c12189be5c1d6a">b</a>.<a class="code" href="unionhwcfg2__data.html#9f827f334b58643849598ce1fa314c5a">num_dev_ep</a>;
+<a name="l00419"></a>00419         uint32_t hwcfg1 = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#d7c6a00c6d7c157ff60a044a28ec8b95">hwcfg1</a>.<a class="code" href="unionhwcfg1__data.html#9ca836052f9bd01e0b70902862ed09a4">d32</a> &gt;&gt; 3;
+<a name="l00420"></a>00420         uint32_t num_tx_fifos = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#9c1394f3c46adde2fa7be79bf0237f9b">hwcfg4</a>.<a class="code" href="unionhwcfg4__data.html#9fb9175668e2381c568c5adbf6e5225d">b</a>.<a class="code" href="unionhwcfg4__data.html#753b321350388c5e1307802ff968f9a8">num_in_eps</a>;
+<a name="l00421"></a>00421         <span class="keywordtype">int</span> i;
+<a name="l00422"></a>00422 
+<a name="l00423"></a>00423         <span class="keywordflow">for</span> (i = 0; i &lt; num_eps; ++i) {
+<a name="l00424"></a>00424                 <span class="keywordflow">if</span> (!(hwcfg1 &amp; 0x1))
+<a name="l00425"></a>00425                         num_in_eps++;
+<a name="l00426"></a>00426 
+<a name="l00427"></a>00427                 hwcfg1 &gt;&gt;= 2;
+<a name="l00428"></a>00428         }
+<a name="l00429"></a>00429 
+<a name="l00430"></a>00430         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#9c1394f3c46adde2fa7be79bf0237f9b">hwcfg4</a>.<a class="code" href="unionhwcfg4__data.html#9fb9175668e2381c568c5adbf6e5225d">b</a>.<a class="code" href="unionhwcfg4__data.html#175e8897d6e3c8ef4026413943de503b">ded_fifo_en</a>) {
+<a name="l00431"></a>00431                 num_in_eps =
+<a name="l00432"></a>00432                     (num_in_eps &gt; num_tx_fifos) ? num_tx_fifos : num_in_eps;
+<a name="l00433"></a>00433         }
+<a name="l00434"></a>00434 
+<a name="l00435"></a>00435         <span class="keywordflow">return</span> num_in_eps;
+<a name="l00436"></a>00436 }
+<a name="l00437"></a>00437 
+<a name="l00444"></a><a class="code" href="dwc__otg__cil_8c.html#e923d8ecfaf2957ef7d0a1379e0b5101">00444</a> <span class="keyword">static</span> uint32_t <a class="code" href="dwc__otg__cil_8c.html#e923d8ecfaf2957ef7d0a1379e0b5101">calc_num_out_eps</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l00445"></a>00445 {
+<a name="l00446"></a>00446         uint32_t num_out_eps = 0;
+<a name="l00447"></a>00447         uint32_t num_eps = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">hwcfg2</a>.<a class="code" href="unionhwcfg2__data.html#9dcc70e2dba617cbc6c12189be5c1d6a">b</a>.<a class="code" href="unionhwcfg2__data.html#9f827f334b58643849598ce1fa314c5a">num_dev_ep</a>;
+<a name="l00448"></a>00448         uint32_t hwcfg1 = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#d7c6a00c6d7c157ff60a044a28ec8b95">hwcfg1</a>.<a class="code" href="unionhwcfg1__data.html#9ca836052f9bd01e0b70902862ed09a4">d32</a> &gt;&gt; 2;
+<a name="l00449"></a>00449         <span class="keywordtype">int</span> i;
+<a name="l00450"></a>00450 
+<a name="l00451"></a>00451         <span class="keywordflow">for</span> (i = 0; i &lt; num_eps; ++i) {
+<a name="l00452"></a>00452                 <span class="keywordflow">if</span> (!(hwcfg1 &amp; 0x1))
+<a name="l00453"></a>00453                         num_out_eps++;
+<a name="l00454"></a>00454 
+<a name="l00455"></a>00455                 hwcfg1 &gt;&gt;= 2;
+<a name="l00456"></a>00456         }
+<a name="l00457"></a>00457         <span class="keywordflow">return</span> num_out_eps;
+<a name="l00458"></a>00458 }
+<a name="l00459"></a>00459 
+<a name="l00467"></a><a class="code" href="dwc__otg__core__if_8h.html#bb49c254dfc70ec4cfe1bcb072cad5d8">00467</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#ce48d4f2d172600c325a82d793473d0f">dwc_otg_core_init</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l00468"></a>00468 {
+<a name="l00469"></a>00469         <span class="keywordtype">int</span> i = 0;
+<a name="l00470"></a>00470         <a class="code" href="structdwc__otg__core__global__regs.html">dwc_otg_core_global_regs_t</a> *global_regs = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>;
+<a name="l00471"></a>00471         <a class="code" href="structdwc__otg__dev__if.html">dwc_otg_dev_if_t</a> *dev_if = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>;
+<a name="l00472"></a>00472         <a class="code" href="uniongahbcfg__data.html">gahbcfg_data_t</a> ahbcfg = {.d32 = 0 };
+<a name="l00473"></a>00473         <a class="code" href="uniongusbcfg__data.html">gusbcfg_data_t</a> usbcfg = {.d32 = 0 };
+<a name="l00474"></a>00474         <a class="code" href="uniongi2cctl__data.html">gi2cctl_data_t</a> i2cctl = {.d32 = 0 };
+<a name="l00475"></a>00475 
+<a name="l00476"></a>00476         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#daab8e158c0c530486656ef52e5b0bbe">DBG_CILV</a>, <span class="stringliteral">"dwc_otg_core_init(%p)\n"</span>, core_if);
+<a name="l00477"></a>00477 
+<a name="l00478"></a>00478         <span class="comment">/* Common Initialization */</span>
+<a name="l00479"></a>00479 
+<a name="l00480"></a>00480         usbcfg.<a class="code" href="uniongusbcfg__data.html#c3d8f2d95fd61a172eb108cb72a85b47">d32</a> = dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#ef39e181e246447df47c56aa4e37cc42">gusbcfg</a>);
+<a name="l00481"></a>00481 
+<a name="l00482"></a>00482         <span class="comment">/* Program the ULPI External VBUS bit if needed */</span>
+<a name="l00483"></a>00483         usbcfg.<a class="code" href="uniongusbcfg__data.html#1dab81bf7260b1e23f97298c34abea06">b</a>.<a class="code" href="uniongusbcfg__data.html#f4784a3028f221e2aed6138ecef53048">ulpi_ext_vbus_drv</a> =
+<a name="l00484"></a>00484             (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#3b6fa0a7fe7d7f87326894fdbe0aa375">phy_ulpi_ext_vbus</a> ==
+<a name="l00485"></a>00485              <a class="code" href="dwc__otg__core__if_8h.html#4e318fec85faf7169df368ee4f7b5176">DWC_PHY_ULPI_EXTERNAL_VBUS</a>) ? 1 : 0;
+<a name="l00486"></a>00486 
+<a name="l00487"></a>00487         <span class="comment">/* Set external TS Dline pulsing */</span>
+<a name="l00488"></a>00488         usbcfg.<a class="code" href="uniongusbcfg__data.html#1dab81bf7260b1e23f97298c34abea06">b</a>.<a class="code" href="uniongusbcfg__data.html#d075f50f1d962c57ff491291f66f1778">term_sel_dl_pulse</a> =
+<a name="l00489"></a>00489             (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#879afefd6e13233a78d74ee71d3ee75e">ts_dline</a> == 1) ? 1 : 0;
+<a name="l00490"></a>00490         dwc_write_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#ef39e181e246447df47c56aa4e37cc42">gusbcfg</a>, usbcfg.<a class="code" href="uniongusbcfg__data.html#c3d8f2d95fd61a172eb108cb72a85b47">d32</a>);
+<a name="l00491"></a>00491 
+<a name="l00492"></a>00492         <span class="comment">/* Reset the Controller */</span>
+<a name="l00493"></a>00493         <a class="code" href="dwc__otg__cil_8c.html#1edfc5634dd76db76e30f20affc10f0c">dwc_otg_core_reset</a>(core_if);
+<a name="l00494"></a>00494 
+<a name="l00495"></a>00495         <span class="comment">/* Initialize parameters from Hardware configuration registers. */</span>
+<a name="l00496"></a>00496         dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#4fae9bc1293bf2e58966c38fa5b98822">num_in_eps</a> = <a class="code" href="dwc__otg__cil_8c.html#1cdde3ab3e53e93c5a42feed628aaf7d">calc_num_in_eps</a>(core_if);
+<a name="l00497"></a>00497         dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#2f0e01cdc605623f591963fc83c8dc73">num_out_eps</a> = <a class="code" href="dwc__otg__cil_8c.html#e923d8ecfaf2957ef7d0a1379e0b5101">calc_num_out_eps</a>(core_if);
+<a name="l00498"></a>00498 
+<a name="l00499"></a>00499         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">DBG_CIL</a>, <span class="stringliteral">"num_dev_perio_in_ep=%d\n"</span>,
+<a name="l00500"></a>00500                     core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#9c1394f3c46adde2fa7be79bf0237f9b">hwcfg4</a>.<a class="code" href="unionhwcfg4__data.html#9fb9175668e2381c568c5adbf6e5225d">b</a>.<a class="code" href="unionhwcfg4__data.html#aee60fb196cf53b610df556744e4d317">num_dev_perio_in_ep</a>);
+<a name="l00501"></a>00501 
+<a name="l00502"></a>00502         <span class="keywordflow">for</span> (i = 0; i &lt; core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#9c1394f3c46adde2fa7be79bf0237f9b">hwcfg4</a>.<a class="code" href="unionhwcfg4__data.html#9fb9175668e2381c568c5adbf6e5225d">b</a>.<a class="code" href="unionhwcfg4__data.html#aee60fb196cf53b610df556744e4d317">num_dev_perio_in_ep</a>; i++) {
+<a name="l00503"></a>00503                 dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#817a953b04c45cf346d7a7d6fc274150">perio_tx_fifo_size</a>[i] =
+<a name="l00504"></a>00504                     dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#efd9e780825f992dbc6cf46d2d72869e">dptxfsiz_dieptxf</a>[i]) &gt;&gt; 16;
+<a name="l00505"></a>00505                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">DBG_CIL</a>, <span class="stringliteral">"Periodic Tx FIFO SZ #%d=0x%0x\n"</span>,
+<a name="l00506"></a>00506                             i, dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#817a953b04c45cf346d7a7d6fc274150">perio_tx_fifo_size</a>[i]);
+<a name="l00507"></a>00507         }
+<a name="l00508"></a>00508 
+<a name="l00509"></a>00509         <span class="keywordflow">for</span> (i = 0; i &lt; core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#9c1394f3c46adde2fa7be79bf0237f9b">hwcfg4</a>.<a class="code" href="unionhwcfg4__data.html#9fb9175668e2381c568c5adbf6e5225d">b</a>.<a class="code" href="unionhwcfg4__data.html#753b321350388c5e1307802ff968f9a8">num_in_eps</a>; i++) {
+<a name="l00510"></a>00510                 dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#ea32a81a3c0a752e6d6274f8fd6faef9">tx_fifo_size</a>[i] =
+<a name="l00511"></a>00511                     dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#efd9e780825f992dbc6cf46d2d72869e">dptxfsiz_dieptxf</a>[i]) &gt;&gt; 16;
+<a name="l00512"></a>00512                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">DBG_CIL</a>, <span class="stringliteral">"Tx FIFO SZ #%d=0x%0x\n"</span>,
+<a name="l00513"></a>00513                             i, dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#817a953b04c45cf346d7a7d6fc274150">perio_tx_fifo_size</a>[i]);
+<a name="l00514"></a>00514         }
+<a name="l00515"></a>00515 
+<a name="l00516"></a>00516         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#cae59008a554cb7de24bd4f2afea7532">total_fifo_size</a> = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#91d0e0a5e8e048024c8846d12e00cecc">hwcfg3</a>.<a class="code" href="unionhwcfg3__data.html#928c5de42f8af177ce34712123b5093c">b</a>.<a class="code" href="unionhwcfg3__data.html#f885715ddb953dbe95acc08e49264706">dfifo_depth</a>;
+<a name="l00517"></a>00517         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#50bbb76c3818ada9ed2ea5527edabcd4">rx_fifo_size</a> = dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#b1a8cc07a9541c9a73e864579602b79b">grxfsiz</a>);
+<a name="l00518"></a>00518         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#fb77b09f04a5687d2087726edd8dece6">nperio_tx_fifo_size</a> =
+<a name="l00519"></a>00519             dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#20fb70fe34a1a65d085b1d4e5f8d9106">gnptxfsiz</a>) &gt;&gt; 16;
+<a name="l00520"></a>00520 
+<a name="l00521"></a>00521         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">DBG_CIL</a>, <span class="stringliteral">"Total FIFO SZ=%d\n"</span>, core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#cae59008a554cb7de24bd4f2afea7532">total_fifo_size</a>);
+<a name="l00522"></a>00522         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">DBG_CIL</a>, <span class="stringliteral">"Rx FIFO SZ=%d\n"</span>, core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#50bbb76c3818ada9ed2ea5527edabcd4">rx_fifo_size</a>);
+<a name="l00523"></a>00523         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">DBG_CIL</a>, <span class="stringliteral">"NP Tx FIFO SZ=%d\n"</span>,
+<a name="l00524"></a>00524                     core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#fb77b09f04a5687d2087726edd8dece6">nperio_tx_fifo_size</a>);
+<a name="l00525"></a>00525 
+<a name="l00526"></a>00526         <span class="comment">/* This programming sequence needs to happen in FS mode before any other</span>
+<a name="l00527"></a>00527 <span class="comment">         * programming occurs */</span>
+<a name="l00528"></a>00528         <span class="keywordflow">if</span> ((core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#d2c4f622f1c14f68c6e60e2603acd09d">speed</a> == <a class="code" href="dwc__otg__core__if_8h.html#353c64bfe6bbc9da8406528ad8220166">DWC_SPEED_PARAM_FULL</a>) &amp;&amp;
+<a name="l00529"></a>00529             (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#8b5d4e0c98c46d0d4e80b6faf66daf72">phy_type</a> == <a class="code" href="dwc__otg__core__if_8h.html#f7395410ea596c4c660f61ff41cb38b8">DWC_PHY_TYPE_PARAM_FS</a>)) {
+<a name="l00530"></a>00530                 <span class="comment">/* If FS mode with FS PHY */</span>
+<a name="l00531"></a>00531 
+<a name="l00532"></a>00532                 <span class="comment">/* core_init() is now called on every switch so only call the</span>
+<a name="l00533"></a>00533 <span class="comment">                 * following for the first time through. */</span>
+<a name="l00534"></a>00534                 <span class="keywordflow">if</span> (!core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#24dd9dec510e5edac930538b81004b74">phy_init_done</a>) {
+<a name="l00535"></a>00535                         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#24dd9dec510e5edac930538b81004b74">phy_init_done</a> = 1;
+<a name="l00536"></a>00536                         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">DBG_CIL</a>, <span class="stringliteral">"FS_PHY detected\n"</span>);
+<a name="l00537"></a>00537                         usbcfg.<a class="code" href="uniongusbcfg__data.html#c3d8f2d95fd61a172eb108cb72a85b47">d32</a> = dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#ef39e181e246447df47c56aa4e37cc42">gusbcfg</a>);
+<a name="l00538"></a>00538                         usbcfg.<a class="code" href="uniongusbcfg__data.html#1dab81bf7260b1e23f97298c34abea06">b</a>.<a class="code" href="uniongusbcfg__data.html#6680455bce7433ccec13377a20912e04">physel</a> = 1;
+<a name="l00539"></a>00539                         dwc_write_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#ef39e181e246447df47c56aa4e37cc42">gusbcfg</a>, usbcfg.<a class="code" href="uniongusbcfg__data.html#c3d8f2d95fd61a172eb108cb72a85b47">d32</a>);
+<a name="l00540"></a>00540 
+<a name="l00541"></a>00541                         <span class="comment">/* Reset after a PHY select */</span>
+<a name="l00542"></a>00542                         <a class="code" href="dwc__otg__cil_8c.html#1edfc5634dd76db76e30f20affc10f0c">dwc_otg_core_reset</a>(core_if);
+<a name="l00543"></a>00543                 }
+<a name="l00544"></a>00544 
+<a name="l00545"></a>00545                 <span class="comment">/* Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.      Also</span>
+<a name="l00546"></a>00546 <span class="comment">                 * do this on HNP Dev/Host mode switches (done in dev_init and</span>
+<a name="l00547"></a>00547 <span class="comment">                 * host_init). */</span>
+<a name="l00548"></a>00548                 <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#f0bfe5f933e21a94ea06c96ffc086e72">dwc_otg_is_host_mode</a>(core_if)) {
+<a name="l00549"></a>00549                         <a class="code" href="dwc__otg__cil_8c.html#4550564b18dcd56bd2c4ec1ba91c6e13">init_fslspclksel</a>(core_if);
+<a name="l00550"></a>00550                 } <span class="keywordflow">else</span> {
+<a name="l00551"></a>00551                         <a class="code" href="dwc__otg__cil_8c.html#6ef971c486eacd419d20e1bc545f9238">init_devspd</a>(core_if);
+<a name="l00552"></a>00552                 }
+<a name="l00553"></a>00553 
+<a name="l00554"></a>00554                 <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#6b0a0ab15284a541ae079beecaf3e617">i2c_enable</a>) {
+<a name="l00555"></a>00555                         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">DBG_CIL</a>, <span class="stringliteral">"FS_PHY Enabling I2c\n"</span>);
+<a name="l00556"></a>00556                         <span class="comment">/* Program GUSBCFG.OtgUtmifsSel to I2C */</span>
+<a name="l00557"></a>00557                         usbcfg.<a class="code" href="uniongusbcfg__data.html#c3d8f2d95fd61a172eb108cb72a85b47">d32</a> = dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#ef39e181e246447df47c56aa4e37cc42">gusbcfg</a>);
+<a name="l00558"></a>00558                         usbcfg.<a class="code" href="uniongusbcfg__data.html#1dab81bf7260b1e23f97298c34abea06">b</a>.<a class="code" href="uniongusbcfg__data.html#ef6e00f543156d1af19662c3ee86830d">otgutmifssel</a> = 1;
+<a name="l00559"></a>00559                         dwc_write_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#ef39e181e246447df47c56aa4e37cc42">gusbcfg</a>, usbcfg.<a class="code" href="uniongusbcfg__data.html#c3d8f2d95fd61a172eb108cb72a85b47">d32</a>);
+<a name="l00560"></a>00560 
+<a name="l00561"></a>00561                         <span class="comment">/* Program GI2CCTL.I2CEn */</span>
+<a name="l00562"></a>00562                         i2cctl.<a class="code" href="uniongi2cctl__data.html#97e9ae4e52d9bd9370027b5da5f65787">d32</a> = dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#8ecf68262dbcdb6901f3011cfe35a144">gi2cctl</a>);
+<a name="l00563"></a>00563                         i2cctl.<a class="code" href="uniongi2cctl__data.html#5cd3b77fc770fc81b9cf9330cac214a8">b</a>.<a class="code" href="uniongi2cctl__data.html#78d1a33a0a81bbca4e89e2f578b27ca2">i2cdevaddr</a> = 1;
+<a name="l00564"></a>00564                         i2cctl.<a class="code" href="uniongi2cctl__data.html#5cd3b77fc770fc81b9cf9330cac214a8">b</a>.<a class="code" href="uniongi2cctl__data.html#6a14bacfd6c36d22071a79cb0fb53e77">i2cen</a> = 0;
+<a name="l00565"></a>00565                         dwc_write_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#8ecf68262dbcdb6901f3011cfe35a144">gi2cctl</a>, i2cctl.<a class="code" href="uniongi2cctl__data.html#97e9ae4e52d9bd9370027b5da5f65787">d32</a>);
+<a name="l00566"></a>00566                         i2cctl.<a class="code" href="uniongi2cctl__data.html#5cd3b77fc770fc81b9cf9330cac214a8">b</a>.<a class="code" href="uniongi2cctl__data.html#6a14bacfd6c36d22071a79cb0fb53e77">i2cen</a> = 1;
+<a name="l00567"></a>00567                         dwc_write_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#8ecf68262dbcdb6901f3011cfe35a144">gi2cctl</a>, i2cctl.<a class="code" href="uniongi2cctl__data.html#97e9ae4e52d9bd9370027b5da5f65787">d32</a>);
+<a name="l00568"></a>00568                 }
+<a name="l00569"></a>00569 
+<a name="l00570"></a>00570         } <span class="comment">/* endif speed == DWC_SPEED_PARAM_FULL */</span>
+<a name="l00571"></a>00571         <span class="keywordflow">else</span> {
+<a name="l00572"></a>00572                 <span class="comment">/* High speed PHY. */</span>
+<a name="l00573"></a>00573                 <span class="keywordflow">if</span> (!core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#24dd9dec510e5edac930538b81004b74">phy_init_done</a>) {
+<a name="l00574"></a>00574                         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#24dd9dec510e5edac930538b81004b74">phy_init_done</a> = 1;
+<a name="l00575"></a>00575                         <span class="comment">/* HS PHY parameters.  These parameters are preserved</span>
+<a name="l00576"></a>00576 <span class="comment">                         * during soft reset so only program the first time.  Do</span>
+<a name="l00577"></a>00577 <span class="comment">                         * a soft reset immediately after setting phyif.  */</span>
+<a name="l00578"></a>00578                         usbcfg.<a class="code" href="uniongusbcfg__data.html#1dab81bf7260b1e23f97298c34abea06">b</a>.<a class="code" href="uniongusbcfg__data.html#f86631568e6d3682cdba6482608bdcfe">ulpi_utmi_sel</a> = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#8b5d4e0c98c46d0d4e80b6faf66daf72">phy_type</a>;
+<a name="l00579"></a>00579                         <span class="keywordflow">if</span> (usbcfg.<a class="code" href="uniongusbcfg__data.html#1dab81bf7260b1e23f97298c34abea06">b</a>.<a class="code" href="uniongusbcfg__data.html#f86631568e6d3682cdba6482608bdcfe">ulpi_utmi_sel</a> == 1) {
+<a name="l00580"></a>00580                                 <span class="comment">/* ULPI interface */</span>
+<a name="l00581"></a>00581                                 usbcfg.<a class="code" href="uniongusbcfg__data.html#1dab81bf7260b1e23f97298c34abea06">b</a>.<a class="code" href="uniongusbcfg__data.html#f5e1a41cbdf6ae4b30a929ff3de8c99c">phyif</a> = 0;
+<a name="l00582"></a>00582                                 usbcfg.<a class="code" href="uniongusbcfg__data.html#1dab81bf7260b1e23f97298c34abea06">b</a>.<a class="code" href="uniongusbcfg__data.html#e6dc05942f880adfaee600bc9e0ba33b">ddrsel</a> =
+<a name="l00583"></a>00583                                     core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#6fc9a3fbe3c36cbbc231f1642ee96cfe">phy_ulpi_ddr</a>;
+<a name="l00584"></a>00584                         } <span class="keywordflow">else</span> {
+<a name="l00585"></a>00585                                 <span class="comment">/* UTMI+ interface */</span>
+<a name="l00586"></a>00586                                 <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#41f5a03ab1b68564b240e03f33a09dde">phy_utmi_width</a> == 16) {
+<a name="l00587"></a>00587                                         usbcfg.<a class="code" href="uniongusbcfg__data.html#1dab81bf7260b1e23f97298c34abea06">b</a>.<a class="code" href="uniongusbcfg__data.html#f5e1a41cbdf6ae4b30a929ff3de8c99c">phyif</a> = 1;
+<a name="l00588"></a>00588 
+<a name="l00589"></a>00589                                 } <span class="keywordflow">else</span> {
+<a name="l00590"></a>00590                                         usbcfg.<a class="code" href="uniongusbcfg__data.html#1dab81bf7260b1e23f97298c34abea06">b</a>.<a class="code" href="uniongusbcfg__data.html#f5e1a41cbdf6ae4b30a929ff3de8c99c">phyif</a> = 0;
+<a name="l00591"></a>00591                                 }
+<a name="l00592"></a>00592 
+<a name="l00593"></a>00593                         }
+<a name="l00594"></a>00594 
+<a name="l00595"></a>00595                         dwc_write_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#ef39e181e246447df47c56aa4e37cc42">gusbcfg</a>, usbcfg.<a class="code" href="uniongusbcfg__data.html#c3d8f2d95fd61a172eb108cb72a85b47">d32</a>);
+<a name="l00596"></a>00596                         <span class="comment">/* Reset after setting the PHY parameters */</span>
+<a name="l00597"></a>00597                         <a class="code" href="dwc__otg__cil_8c.html#1edfc5634dd76db76e30f20affc10f0c">dwc_otg_core_reset</a>(core_if);
+<a name="l00598"></a>00598                 }
+<a name="l00599"></a>00599         }
+<a name="l00600"></a>00600 
+<a name="l00601"></a>00601         <span class="keywordflow">if</span> ((core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">hwcfg2</a>.<a class="code" href="unionhwcfg2__data.html#9dcc70e2dba617cbc6c12189be5c1d6a">b</a>.<a class="code" href="unionhwcfg2__data.html#a248a2502e3c440d7b6e4ad61d396f4e">hs_phy_type</a> == 2) &amp;&amp;
+<a name="l00602"></a>00602             (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">hwcfg2</a>.<a class="code" href="unionhwcfg2__data.html#9dcc70e2dba617cbc6c12189be5c1d6a">b</a>.<a class="code" href="unionhwcfg2__data.html#e75417d7e2d1843abf6e48f67851326e">fs_phy_type</a> == 1) &amp;&amp;
+<a name="l00603"></a>00603             (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#3d7cfc3c416010102b2c671dfaa828d5">ulpi_fs_ls</a>)) {
+<a name="l00604"></a>00604                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">DBG_CIL</a>, <span class="stringliteral">"Setting ULPI FSLS\n"</span>);
+<a name="l00605"></a>00605                 usbcfg.<a class="code" href="uniongusbcfg__data.html#c3d8f2d95fd61a172eb108cb72a85b47">d32</a> = dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#ef39e181e246447df47c56aa4e37cc42">gusbcfg</a>);
+<a name="l00606"></a>00606                 usbcfg.<a class="code" href="uniongusbcfg__data.html#1dab81bf7260b1e23f97298c34abea06">b</a>.<a class="code" href="uniongusbcfg__data.html#de6d061bf2d0d8c909e6f7d701977b73">ulpi_fsls</a> = 1;
+<a name="l00607"></a>00607                 usbcfg.<a class="code" href="uniongusbcfg__data.html#1dab81bf7260b1e23f97298c34abea06">b</a>.<a class="code" href="uniongusbcfg__data.html#017fa2eb1df13d0917ffc6b243e5064c">ulpi_clk_sus_m</a> = 1;
+<a name="l00608"></a>00608                 dwc_write_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#ef39e181e246447df47c56aa4e37cc42">gusbcfg</a>, usbcfg.<a class="code" href="uniongusbcfg__data.html#c3d8f2d95fd61a172eb108cb72a85b47">d32</a>);
+<a name="l00609"></a>00609         } <span class="keywordflow">else</span> {
+<a name="l00610"></a>00610                 usbcfg.<a class="code" href="uniongusbcfg__data.html#c3d8f2d95fd61a172eb108cb72a85b47">d32</a> = dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#ef39e181e246447df47c56aa4e37cc42">gusbcfg</a>);
+<a name="l00611"></a>00611                 usbcfg.<a class="code" href="uniongusbcfg__data.html#1dab81bf7260b1e23f97298c34abea06">b</a>.<a class="code" href="uniongusbcfg__data.html#de6d061bf2d0d8c909e6f7d701977b73">ulpi_fsls</a> = 0;
+<a name="l00612"></a>00612                 usbcfg.<a class="code" href="uniongusbcfg__data.html#1dab81bf7260b1e23f97298c34abea06">b</a>.<a class="code" href="uniongusbcfg__data.html#017fa2eb1df13d0917ffc6b243e5064c">ulpi_clk_sus_m</a> = 0;
+<a name="l00613"></a>00613                 dwc_write_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#ef39e181e246447df47c56aa4e37cc42">gusbcfg</a>, usbcfg.<a class="code" href="uniongusbcfg__data.html#c3d8f2d95fd61a172eb108cb72a85b47">d32</a>);
+<a name="l00614"></a>00614         }
+<a name="l00615"></a>00615 
+<a name="l00616"></a>00616         <span class="comment">/* Program the GAHBCFG Register. */</span>
+<a name="l00617"></a>00617         <span class="keywordflow">switch</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">hwcfg2</a>.<a class="code" href="unionhwcfg2__data.html#9dcc70e2dba617cbc6c12189be5c1d6a">b</a>.<a class="code" href="unionhwcfg2__data.html#e5000f58c6a0f09c75375b4c912af0eb">architecture</a>) {
+<a name="l00618"></a>00618 
+<a name="l00619"></a>00619         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__regs_8h.html#b06d547ae50b58fd46847daa34578122">DWC_SLAVE_ONLY_ARCH</a>:
+<a name="l00620"></a>00620                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">DBG_CIL</a>, <span class="stringliteral">"Slave Only Mode\n"</span>);
+<a name="l00621"></a>00621                 ahbcfg.<a class="code" href="uniongahbcfg__data.html#aa9726048597c5bb54ea38eda976e1a4">b</a>.<a class="code" href="uniongahbcfg__data.html#00758ec639d12cc80fd98b1a6526c454">nptxfemplvl_txfemplvl</a> =
+<a name="l00622"></a>00622                     <a class="code" href="dwc__otg__regs_8h.html#0ec8d38e3f85707561b300ae1b339b71">DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY</a>;
+<a name="l00623"></a>00623                 ahbcfg.<a class="code" href="uniongahbcfg__data.html#aa9726048597c5bb54ea38eda976e1a4">b</a>.<a class="code" href="uniongahbcfg__data.html#e45b68a6e6e681e58d70fd8e70f9542f">ptxfemplvl</a> = <a class="code" href="dwc__otg__regs_8h.html#0ec8d38e3f85707561b300ae1b339b71">DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY</a>;
+<a name="l00624"></a>00624                 core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a> = 0;
+<a name="l00625"></a>00625                 core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a> = 0;
+<a name="l00626"></a>00626                 <span class="keywordflow">break</span>;
+<a name="l00627"></a>00627 
+<a name="l00628"></a>00628         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__regs_8h.html#bc493e89caf2ae15aa2b306099b8a927">DWC_EXT_DMA_ARCH</a>:
+<a name="l00629"></a>00629                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">DBG_CIL</a>, <span class="stringliteral">"External DMA Mode\n"</span>);
+<a name="l00630"></a>00630                 {
+<a name="l00631"></a>00631                         uint8_t brst_sz = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#f9d2a8cd9b36d24de89121d19f693ccb">dma_burst_size</a>;
+<a name="l00632"></a>00632                         ahbcfg.<a class="code" href="uniongahbcfg__data.html#aa9726048597c5bb54ea38eda976e1a4">b</a>.<a class="code" href="uniongahbcfg__data.html#b8f9a94aa77eb5abc379c438bf68f3d0">hburstlen</a> = 0;
+<a name="l00633"></a>00633                         <span class="keywordflow">while</span> (brst_sz &gt; 1) {
+<a name="l00634"></a>00634                                 ahbcfg.<a class="code" href="uniongahbcfg__data.html#aa9726048597c5bb54ea38eda976e1a4">b</a>.<a class="code" href="uniongahbcfg__data.html#b8f9a94aa77eb5abc379c438bf68f3d0">hburstlen</a>++;
+<a name="l00635"></a>00635                                 brst_sz &gt;&gt;= 1;
+<a name="l00636"></a>00636                         }
+<a name="l00637"></a>00637                 }
+<a name="l00638"></a>00638                 core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a> = (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#3c791cb4898379d156acc47c5b9a84fc">dma_enable</a> != 0);
+<a name="l00639"></a>00639                 core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a> =
+<a name="l00640"></a>00640                     (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#36c5bcf00d0f776b5c9e84e5d8ae408d">dma_desc_enable</a> != 0);
+<a name="l00641"></a>00641                 <span class="keywordflow">break</span>;
+<a name="l00642"></a>00642 
+<a name="l00643"></a>00643         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__regs_8h.html#f91a3e3ec200595566b8df5e40485fda">DWC_INT_DMA_ARCH</a>:
+<a name="l00644"></a>00644                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">DBG_CIL</a>, <span class="stringliteral">"Internal DMA Mode\n"</span>);
+<a name="l00645"></a>00645                 ahbcfg.<a class="code" href="uniongahbcfg__data.html#aa9726048597c5bb54ea38eda976e1a4">b</a>.<a class="code" href="uniongahbcfg__data.html#b8f9a94aa77eb5abc379c438bf68f3d0">hburstlen</a> = <a class="code" href="dwc__otg__regs_8h.html#e817b2bec10af4c5e95f10a78e031bcc">DWC_GAHBCFG_INT_DMA_BURST_INCR</a>;
+<a name="l00646"></a>00646                 core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a> = (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#3c791cb4898379d156acc47c5b9a84fc">dma_enable</a> != 0);
+<a name="l00647"></a>00647                 core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a> =
+<a name="l00648"></a>00648                     (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#36c5bcf00d0f776b5c9e84e5d8ae408d">dma_desc_enable</a> != 0);
+<a name="l00649"></a>00649                 <span class="keywordflow">break</span>;
+<a name="l00650"></a>00650 
+<a name="l00651"></a>00651         }
+<a name="l00652"></a>00652         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a>) {
+<a name="l00653"></a>00653                 <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a>) {
+<a name="l00654"></a>00654                         DWC_PRINTF(<span class="stringliteral">"Using Descriptor DMA mode\n"</span>);
+<a name="l00655"></a>00655                 } <span class="keywordflow">else</span> {
+<a name="l00656"></a>00656                         DWC_PRINTF(<span class="stringliteral">"Using Buffer DMA mode\n"</span>);
+<a name="l00657"></a>00657 
+<a name="l00658"></a>00658                 }
+<a name="l00659"></a>00659         } <span class="keywordflow">else</span> {
+<a name="l00660"></a>00660                 DWC_PRINTF(<span class="stringliteral">"Using Slave mode\n"</span>);
+<a name="l00661"></a>00661                 core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a> = 0;
+<a name="l00662"></a>00662         }
+<a name="l00663"></a>00663         
+<a name="l00664"></a>00664         ahbcfg.<a class="code" href="uniongahbcfg__data.html#aa9726048597c5bb54ea38eda976e1a4">b</a>.<a class="code" href="uniongahbcfg__data.html#f39c07c45326af38a267b0e308496b5c">dmaenable</a> = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a>;
+<a name="l00665"></a>00665         dwc_write_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#537c95e57269fabf29c6b36ad8e1ed45">gahbcfg</a>, ahbcfg.<a class="code" href="uniongahbcfg__data.html#2532b75f838946009af8806c924f0c08">d32</a>);
+<a name="l00666"></a>00666 
+<a name="l00667"></a>00667         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#31d08d1ebcd290b05139b0fcd24048ec">en_multiple_tx_fifo</a> = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#9c1394f3c46adde2fa7be79bf0237f9b">hwcfg4</a>.<a class="code" href="unionhwcfg4__data.html#9fb9175668e2381c568c5adbf6e5225d">b</a>.<a class="code" href="unionhwcfg4__data.html#175e8897d6e3c8ef4026413943de503b">ded_fifo_en</a>;
+<a name="l00668"></a>00668 
+<a name="l00669"></a>00669         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#34540b79e9a14bfa234a52ac132c5cd1">pti_enh_enable</a> = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#b601fde03b371b74deab1205e1329a7d">pti_enable</a> != 0;
+<a name="l00670"></a>00670         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5675c8d8dd7df746fda9157dc39ba5c2">multiproc_int_enable</a> = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#740e50199a75b3877b7db630d49c36aa">mpi_enable</a>;
+<a name="l00671"></a>00671         DWC_PRINTF(<span class="stringliteral">"Periodic Transfer Interrupt Enhancement - %s\n"</span>,
+<a name="l00672"></a>00672                    ((core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#34540b79e9a14bfa234a52ac132c5cd1">pti_enh_enable</a>) ? <span class="stringliteral">"enabled"</span> : <span class="stringliteral">"disabled"</span>));
+<a name="l00673"></a>00673         DWC_PRINTF(<span class="stringliteral">"Multiprocessor Interrupt Enhancement - %s\n"</span>,
+<a name="l00674"></a>00674                    ((core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5675c8d8dd7df746fda9157dc39ba5c2">multiproc_int_enable</a>) ? <span class="stringliteral">"enabled"</span> : <span class="stringliteral">"disabled"</span>));
+<a name="l00675"></a>00675 
+<a name="l00676"></a>00676         <span class="comment">/* </span>
+<a name="l00677"></a>00677 <span class="comment">         * Program the GUSBCFG register. </span>
+<a name="l00678"></a>00678 <span class="comment">         */</span>
+<a name="l00679"></a>00679         usbcfg.<a class="code" href="uniongusbcfg__data.html#c3d8f2d95fd61a172eb108cb72a85b47">d32</a> = dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#ef39e181e246447df47c56aa4e37cc42">gusbcfg</a>);
+<a name="l00680"></a>00680 
+<a name="l00681"></a>00681         <span class="keywordflow">switch</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">hwcfg2</a>.<a class="code" href="unionhwcfg2__data.html#9dcc70e2dba617cbc6c12189be5c1d6a">b</a>.<a class="code" href="unionhwcfg2__data.html#592df9b97ff9342b839d2ed76d54c652">op_mode</a>) {
+<a name="l00682"></a>00682         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__regs_8h.html#8d3140b85bae33e2d7955693c61fd490">DWC_MODE_HNP_SRP_CAPABLE</a>:
+<a name="l00683"></a>00683                 usbcfg.<a class="code" href="uniongusbcfg__data.html#1dab81bf7260b1e23f97298c34abea06">b</a>.<a class="code" href="uniongusbcfg__data.html#71b6330c5ccf1d21ebf79a0a829612b5">hnpcap</a> = (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#b6960c28e9c7d82dca37645726c8f7ce">otg_cap</a> ==
+<a name="l00684"></a>00684                                    <a class="code" href="dwc__otg__core__if_8h.html#83c71a480363001711ff07e03834c49f">DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE</a>);
+<a name="l00685"></a>00685                 usbcfg.<a class="code" href="uniongusbcfg__data.html#1dab81bf7260b1e23f97298c34abea06">b</a>.<a class="code" href="uniongusbcfg__data.html#44485a787b8a386fadae801869ce7810">srpcap</a> = (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#b6960c28e9c7d82dca37645726c8f7ce">otg_cap</a> !=
+<a name="l00686"></a>00686                                    <a class="code" href="dwc__otg__core__if_8h.html#42ff7d87b7b3d3a47cf1749f02ce516c">DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE</a>);
+<a name="l00687"></a>00687                 <span class="keywordflow">break</span>;
+<a name="l00688"></a>00688 
+<a name="l00689"></a>00689         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__regs_8h.html#ecd675d5698ebf873bad50c6d2241296">DWC_MODE_SRP_ONLY_CAPABLE</a>:
+<a name="l00690"></a>00690                 usbcfg.<a class="code" href="uniongusbcfg__data.html#1dab81bf7260b1e23f97298c34abea06">b</a>.<a class="code" href="uniongusbcfg__data.html#71b6330c5ccf1d21ebf79a0a829612b5">hnpcap</a> = 0;
+<a name="l00691"></a>00691                 usbcfg.<a class="code" href="uniongusbcfg__data.html#1dab81bf7260b1e23f97298c34abea06">b</a>.<a class="code" href="uniongusbcfg__data.html#44485a787b8a386fadae801869ce7810">srpcap</a> = (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#b6960c28e9c7d82dca37645726c8f7ce">otg_cap</a> !=
+<a name="l00692"></a>00692                                    <a class="code" href="dwc__otg__core__if_8h.html#42ff7d87b7b3d3a47cf1749f02ce516c">DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE</a>);
+<a name="l00693"></a>00693                 <span class="keywordflow">break</span>;
+<a name="l00694"></a>00694 
+<a name="l00695"></a>00695         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__regs_8h.html#42740812c78415753c76ea58e2dd6a50">DWC_MODE_NO_HNP_SRP_CAPABLE</a>:
+<a name="l00696"></a>00696                 usbcfg.<a class="code" href="uniongusbcfg__data.html#1dab81bf7260b1e23f97298c34abea06">b</a>.<a class="code" href="uniongusbcfg__data.html#71b6330c5ccf1d21ebf79a0a829612b5">hnpcap</a> = 0;
+<a name="l00697"></a>00697                 usbcfg.<a class="code" href="uniongusbcfg__data.html#1dab81bf7260b1e23f97298c34abea06">b</a>.<a class="code" href="uniongusbcfg__data.html#44485a787b8a386fadae801869ce7810">srpcap</a> = 0;
+<a name="l00698"></a>00698                 <span class="keywordflow">break</span>;
+<a name="l00699"></a>00699 
+<a name="l00700"></a>00700         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__regs_8h.html#0e5bc465c451f7ce8402ce94c355398e">DWC_MODE_SRP_CAPABLE_DEVICE</a>:
+<a name="l00701"></a>00701                 usbcfg.<a class="code" href="uniongusbcfg__data.html#1dab81bf7260b1e23f97298c34abea06">b</a>.<a class="code" href="uniongusbcfg__data.html#71b6330c5ccf1d21ebf79a0a829612b5">hnpcap</a> = 0;
+<a name="l00702"></a>00702                 usbcfg.<a class="code" href="uniongusbcfg__data.html#1dab81bf7260b1e23f97298c34abea06">b</a>.<a class="code" href="uniongusbcfg__data.html#44485a787b8a386fadae801869ce7810">srpcap</a> = (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#b6960c28e9c7d82dca37645726c8f7ce">otg_cap</a> !=
+<a name="l00703"></a>00703                                    <a class="code" href="dwc__otg__core__if_8h.html#42ff7d87b7b3d3a47cf1749f02ce516c">DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE</a>);
+<a name="l00704"></a>00704                 <span class="keywordflow">break</span>;
+<a name="l00705"></a>00705 
+<a name="l00706"></a>00706         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__regs_8h.html#74152fd1bf534e043a53efd98a982bb6">DWC_MODE_NO_SRP_CAPABLE_DEVICE</a>:
+<a name="l00707"></a>00707                 usbcfg.<a class="code" href="uniongusbcfg__data.html#1dab81bf7260b1e23f97298c34abea06">b</a>.<a class="code" href="uniongusbcfg__data.html#71b6330c5ccf1d21ebf79a0a829612b5">hnpcap</a> = 0;
+<a name="l00708"></a>00708                 usbcfg.<a class="code" href="uniongusbcfg__data.html#1dab81bf7260b1e23f97298c34abea06">b</a>.<a class="code" href="uniongusbcfg__data.html#44485a787b8a386fadae801869ce7810">srpcap</a> = 0;
+<a name="l00709"></a>00709                 <span class="keywordflow">break</span>;
+<a name="l00710"></a>00710 
+<a name="l00711"></a>00711         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__regs_8h.html#bbca30221d8415bad1c254e5cb240eaa">DWC_MODE_SRP_CAPABLE_HOST</a>:
+<a name="l00712"></a>00712                 usbcfg.<a class="code" href="uniongusbcfg__data.html#1dab81bf7260b1e23f97298c34abea06">b</a>.<a class="code" href="uniongusbcfg__data.html#71b6330c5ccf1d21ebf79a0a829612b5">hnpcap</a> = 0;
+<a name="l00713"></a>00713                 usbcfg.<a class="code" href="uniongusbcfg__data.html#1dab81bf7260b1e23f97298c34abea06">b</a>.<a class="code" href="uniongusbcfg__data.html#44485a787b8a386fadae801869ce7810">srpcap</a> = (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#b6960c28e9c7d82dca37645726c8f7ce">otg_cap</a> !=
+<a name="l00714"></a>00714                                    <a class="code" href="dwc__otg__core__if_8h.html#42ff7d87b7b3d3a47cf1749f02ce516c">DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE</a>);
+<a name="l00715"></a>00715                 <span class="keywordflow">break</span>;
+<a name="l00716"></a>00716 
+<a name="l00717"></a>00717         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__regs_8h.html#91a7255e685d172cfa7b6be0eaab5102">DWC_MODE_NO_SRP_CAPABLE_HOST</a>:
+<a name="l00718"></a>00718                 usbcfg.<a class="code" href="uniongusbcfg__data.html#1dab81bf7260b1e23f97298c34abea06">b</a>.<a class="code" href="uniongusbcfg__data.html#71b6330c5ccf1d21ebf79a0a829612b5">hnpcap</a> = 0;
+<a name="l00719"></a>00719                 usbcfg.<a class="code" href="uniongusbcfg__data.html#1dab81bf7260b1e23f97298c34abea06">b</a>.<a class="code" href="uniongusbcfg__data.html#44485a787b8a386fadae801869ce7810">srpcap</a> = 0;
+<a name="l00720"></a>00720                 <span class="keywordflow">break</span>;
+<a name="l00721"></a>00721         }
+<a name="l00722"></a>00722 
+<a name="l00723"></a>00723         dwc_write_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#ef39e181e246447df47c56aa4e37cc42">gusbcfg</a>, usbcfg.<a class="code" href="uniongusbcfg__data.html#c3d8f2d95fd61a172eb108cb72a85b47">d32</a>);
+<a name="l00724"></a>00724 
+<a name="l00725"></a>00725 <span class="preprocessor">#ifdef CONFIG_USB_DWC_OTG_LPM</span>
+<a name="l00726"></a>00726 <span class="preprocessor"></span>        <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#8b906ba765a10dd9fcfa1c02dbc0184e">lpm_enable</a>) {
+<a name="l00727"></a>00727                 <a class="code" href="unionglpmctl__data.html">glpmcfg_data_t</a> lpmcfg = {.d32 = 0 };
+<a name="l00728"></a>00728 
+<a name="l00729"></a>00729                 <span class="comment">/* To enable LPM support set lpm_cap_en bit */</span>
+<a name="l00730"></a>00730                 lpmcfg.<a class="code" href="unionglpmctl__data.html#bd3cc34c338226ff1cd89448f7590ff1">b</a>.<a class="code" href="unionglpmctl__data.html#cf0a4cfcd158e41eb3811048e723890f">lpm_cap_en</a> = 1;
+<a name="l00731"></a>00731 
+<a name="l00732"></a>00732                 <span class="comment">/* Make AppL1Res ACK */</span>
+<a name="l00733"></a>00733                 lpmcfg.<a class="code" href="unionglpmctl__data.html#bd3cc34c338226ff1cd89448f7590ff1">b</a>.<a class="code" href="unionglpmctl__data.html#1898203022af680f08036de89e86e4b0">appl_resp</a> = 1;
+<a name="l00734"></a>00734 
+<a name="l00735"></a>00735                 <span class="comment">/* Retry 3 times */</span>
+<a name="l00736"></a>00736                 lpmcfg.<a class="code" href="unionglpmctl__data.html#bd3cc34c338226ff1cd89448f7590ff1">b</a>.<a class="code" href="unionglpmctl__data.html#be75ed525bcfe231cd9bda6a1b8594f6">retry_count</a> = 3;
+<a name="l00737"></a>00737 
+<a name="l00738"></a>00738                 dwc_modify_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#843cfb38ba366a9a46ad07ed11eb8396">glpmcfg</a>,
+<a name="l00739"></a>00739                                  0, lpmcfg.<a class="code" href="unionglpmctl__data.html#cd41461734ff898209bfb64057ef2eb8">d32</a>);
+<a name="l00740"></a>00740 
+<a name="l00741"></a>00741         }
+<a name="l00742"></a>00742 <span class="preprocessor">#endif</span>
+<a name="l00743"></a>00743 <span class="preprocessor"></span>        <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#359a3cb3a7b4800a0c32750005c9fd1b">ic_usb_cap</a>) {
+<a name="l00744"></a>00744                 <a class="code" href="uniongusbcfg__data.html">gusbcfg_data_t</a> gusbcfg = {.d32 = 0 };
+<a name="l00745"></a>00745                 gusbcfg.<a class="code" href="uniongusbcfg__data.html#1dab81bf7260b1e23f97298c34abea06">b</a>.<a class="code" href="uniongusbcfg__data.html#b729e853539aafb4bab1e4e9ac57916a">ic_usb_cap</a> = 1;
+<a name="l00746"></a>00746                 dwc_modify_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#ef39e181e246447df47c56aa4e37cc42">gusbcfg</a>,
+<a name="l00747"></a>00747                                  0, gusbcfg.<a class="code" href="uniongusbcfg__data.html#c3d8f2d95fd61a172eb108cb72a85b47">d32</a>);
+<a name="l00748"></a>00748         }
+<a name="l00749"></a>00749 
+<a name="l00750"></a>00750         <span class="comment">/* Enable common interrupts */</span>
+<a name="l00751"></a>00751         <a class="code" href="dwc__otg__cil_8c.html#1761ac95e17bad3fa304413cc81c51de">dwc_otg_enable_common_interrupts</a>(core_if);
+<a name="l00752"></a>00752 
+<a name="l00753"></a>00753         <span class="comment">/* Do device or host intialization based on mode during PCD</span>
+<a name="l00754"></a>00754 <span class="comment">         * and HCD initialization  */</span>
+<a name="l00755"></a>00755         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#f0bfe5f933e21a94ea06c96ffc086e72">dwc_otg_is_host_mode</a>(core_if)) {
+<a name="l00756"></a>00756                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#2bf62a567355d1ea38814714bd7b57ec">DBG_ANY</a>, <span class="stringliteral">"Host Mode\n"</span>);
+<a name="l00757"></a>00757                 core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5a5c5c1cf8d870101cc1fffac56d88c0">op_state</a> = <a class="code" href="dwc__otg__cil_8h.html#a0732b344b6571a4554968e4ee2214dd">A_HOST</a>;
+<a name="l00758"></a>00758         } <span class="keywordflow">else</span> {
+<a name="l00759"></a>00759                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#2bf62a567355d1ea38814714bd7b57ec">DBG_ANY</a>, <span class="stringliteral">"Device Mode\n"</span>);
+<a name="l00760"></a>00760                 core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5a5c5c1cf8d870101cc1fffac56d88c0">op_state</a> = <a class="code" href="dwc__otg__cil_8h.html#622c3b95c9a587f518a787c05c50ffb7">B_PERIPHERAL</a>;
+<a name="l00761"></a>00761 <span class="preprocessor">#ifdef DWC_DEVICE_ONLY</span>
+<a name="l00762"></a>00762 <span class="preprocessor"></span>                <a class="code" href="dwc__otg__cil_8c.html#f79b0f3b5b96b0535e33627ee3a66eba">dwc_otg_core_dev_init</a>(core_if);
+<a name="l00763"></a>00763 <span class="preprocessor">#endif</span>
+<a name="l00764"></a>00764 <span class="preprocessor"></span>        }
+<a name="l00765"></a>00765 }
+<a name="l00766"></a>00766 
+<a name="l00772"></a><a class="code" href="dwc__otg__cil_8h.html#ea31a3abac0bdb1ede29a9d65c402553">00772</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#3d60e58f32be881047ac61bc852f60f7">dwc_otg_enable_device_interrupts</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l00773"></a>00773 {
+<a name="l00774"></a>00774         <a class="code" href="uniongintmsk__data.html">gintmsk_data_t</a> intr_mask = {.d32 = 0 };
+<a name="l00775"></a>00775         <a class="code" href="structdwc__otg__core__global__regs.html">dwc_otg_core_global_regs_t</a> *global_regs = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>;
+<a name="l00776"></a>00776 
+<a name="l00777"></a>00777         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">DBG_CIL</a>, <span class="stringliteral">"%s()\n"</span>, __func__);
+<a name="l00778"></a>00778 
+<a name="l00779"></a>00779         <span class="comment">/* Disable all interrupts. */</span>
+<a name="l00780"></a>00780         dwc_write_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#48827c76da2c6b18f369e2f2483cc4b6">gintmsk</a>, 0);
+<a name="l00781"></a>00781 
+<a name="l00782"></a>00782         <span class="comment">/* Clear any pending interrupts */</span>
+<a name="l00783"></a>00783         dwc_write_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>, 0xFFFFFFFF);
+<a name="l00784"></a>00784 
+<a name="l00785"></a>00785         <span class="comment">/* Enable the common interrupts */</span>
+<a name="l00786"></a>00786         <a class="code" href="dwc__otg__cil_8c.html#1761ac95e17bad3fa304413cc81c51de">dwc_otg_enable_common_interrupts</a>(core_if);
+<a name="l00787"></a>00787 
+<a name="l00788"></a>00788         <span class="comment">/* Enable interrupts */</span>
+<a name="l00789"></a>00789         intr_mask.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#de79426e6a5436e34cf4b1ac42a72ee6">usbreset</a> = 1;
+<a name="l00790"></a>00790         intr_mask.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#895f1c1537debec62da4fd248249859c">enumdone</a> = 1;
+<a name="l00791"></a>00791 
+<a name="l00792"></a>00792         <span class="keywordflow">if</span> (!core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5675c8d8dd7df746fda9157dc39ba5c2">multiproc_int_enable</a>) {
+<a name="l00793"></a>00793                 intr_mask.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#bcae4c9dd3d0f153b379dfbc6c830fc5">inepintr</a> = 1;
+<a name="l00794"></a>00794                 intr_mask.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#d48fe24e3e91bc1bcbc1c790c1b67f96">outepintr</a> = 1;
+<a name="l00795"></a>00795         }
+<a name="l00796"></a>00796 
+<a name="l00797"></a>00797         intr_mask.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#0c455b6461081720584a8acc4e0e18a5">erlysuspend</a> = 1;
+<a name="l00798"></a>00798 
+<a name="l00799"></a>00799         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#31d08d1ebcd290b05139b0fcd24048ec">en_multiple_tx_fifo</a> == 0) {
+<a name="l00800"></a>00800                 intr_mask.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#3a21d0006e144647b43ef910b9183da9">epmismatch</a> = 1;
+<a name="l00801"></a>00801         }
+<a name="l00802"></a>00802 <span class="preprocessor">#ifdef DWC_EN_ISOC</span>
+<a name="l00803"></a>00803 <span class="preprocessor"></span>        <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a>) {
+<a name="l00804"></a>00804                 <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a> == 0) {
+<a name="l00805"></a>00805                         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#34540b79e9a14bfa234a52ac132c5cd1">pti_enh_enable</a>) {
+<a name="l00806"></a>00806                                 <a class="code" href="uniondctl__data.html">dctl_data_t</a> dctl = {.d32 = 0 };
+<a name="l00807"></a>00807                                 dctl.<a class="code" href="uniondctl__data.html#a3abfa6d609d9864f1f65712b409d4d3">b</a>.<a class="code" href="uniondctl__data.html#a817a529df5c5fc57135560014b90dcc">ifrmnum</a> = 1;
+<a name="l00808"></a>00808                                 dwc_modify_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;
+<a name="l00809"></a>00809                                                  dev_global_regs-&gt;dctl, 0,
+<a name="l00810"></a>00810                                                  dctl.<a class="code" href="uniondctl__data.html#f49aadfd7ad95b570115b3c245b1729e">d32</a>);
+<a name="l00811"></a>00811                         } <span class="keywordflow">else</span> {
+<a name="l00812"></a>00812                                 intr_mask.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#3f9eeb4c73291b7943b7187ba34c90f4">incomplisoin</a> = 1;
+<a name="l00813"></a>00813                                 intr_mask.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#c63c107070bd7623766e39cd06ec7c97">incomplisoout</a> = 1;
+<a name="l00814"></a>00814                         }
+<a name="l00815"></a>00815                 }
+<a name="l00816"></a>00816         } <span class="keywordflow">else</span> {
+<a name="l00817"></a>00817                 intr_mask.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#3f9eeb4c73291b7943b7187ba34c90f4">incomplisoin</a> = 1;
+<a name="l00818"></a>00818                 intr_mask.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#c63c107070bd7623766e39cd06ec7c97">incomplisoout</a> = 1;
+<a name="l00819"></a>00819         }
+<a name="l00820"></a>00820 <span class="preprocessor">#endif                          </span><span class="comment">/* DWC_EN_ISOC */</span>
+<a name="l00821"></a>00821 
+<a name="l00823"></a>00823 <span class="preprocessor">#ifdef USE_PERIODIC_EP</span>
+<a name="l00824"></a>00824 <span class="preprocessor"></span>        intr_mask.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#3a0a75b129ccdaed6d98d1982b374d52">isooutdrop</a> = 1;
+<a name="l00825"></a>00825         intr_mask.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#aeb61a24f3c50caacfb8fe523c85768a">eopframe</a> = 1;
+<a name="l00826"></a>00826         intr_mask.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#3f9eeb4c73291b7943b7187ba34c90f4">incomplisoin</a> = 1;
+<a name="l00827"></a>00827         intr_mask.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#c63c107070bd7623766e39cd06ec7c97">incomplisoout</a> = 1;
+<a name="l00828"></a>00828 <span class="preprocessor">#endif</span>
+<a name="l00829"></a>00829 <span class="preprocessor"></span>
+<a name="l00830"></a>00830         dwc_modify_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#48827c76da2c6b18f369e2f2483cc4b6">gintmsk</a>, intr_mask.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a>, intr_mask.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a>);
+<a name="l00831"></a>00831 
+<a name="l00832"></a>00832         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">DBG_CIL</a>, <span class="stringliteral">"%s() gintmsk=%0x\n"</span>, __func__,
+<a name="l00833"></a>00833                     dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#48827c76da2c6b18f369e2f2483cc4b6">gintmsk</a>));
+<a name="l00834"></a>00834 }
+<a name="l00835"></a>00835 
+<a name="l00843"></a><a class="code" href="dwc__otg__cil_8h.html#16b147d5ce40708fe305d65c869edad8">00843</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#f79b0f3b5b96b0535e33627ee3a66eba">dwc_otg_core_dev_init</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l00844"></a>00844 {
+<a name="l00845"></a>00845         <span class="keywordtype">int</span> i;
+<a name="l00846"></a>00846         <a class="code" href="structdwc__otg__core__global__regs.html">dwc_otg_core_global_regs_t</a> *global_regs = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>;
+<a name="l00847"></a>00847         <a class="code" href="structdwc__otg__dev__if.html">dwc_otg_dev_if_t</a> *dev_if = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>;
+<a name="l00848"></a>00848         <a class="code" href="structdwc__otg__core__params.html">dwc_otg_core_params_t</a> *params = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>;
+<a name="l00849"></a>00849         <a class="code" href="uniondcfg__data.html">dcfg_data_t</a> dcfg = {.d32 = 0 };
+<a name="l00850"></a>00850         <a class="code" href="uniongrstctl__data.html">grstctl_t</a> resetctl = {.d32 = 0 };
+<a name="l00851"></a>00851         uint32_t rx_fifo_size;
+<a name="l00852"></a>00852         <a class="code" href="unionfifosize__data.html">fifosize_data_t</a> nptxfifosize;
+<a name="l00853"></a>00853         <a class="code" href="unionfifosize__data.html">fifosize_data_t</a> txfifosize;
+<a name="l00854"></a>00854         <a class="code" href="uniondthrctl__data.html">dthrctl_data_t</a> dthrctl;
+<a name="l00855"></a>00855         <a class="code" href="unionfifosize__data.html">fifosize_data_t</a> ptxfifosize;
+<a name="l00856"></a>00856 
+<a name="l00857"></a>00857         <span class="comment">/* Restart the Phy Clock */</span>
+<a name="l00858"></a>00858         dwc_write_reg32(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#348ed2c9aeae6fc608f1bb813978b3f9">pcgcctl</a>, 0);
+<a name="l00859"></a>00859 
+<a name="l00860"></a>00860         <span class="comment">/* Device configuration register */</span>
+<a name="l00861"></a>00861         <a class="code" href="dwc__otg__cil_8c.html#6ef971c486eacd419d20e1bc545f9238">init_devspd</a>(core_if);
+<a name="l00862"></a>00862         dcfg.<a class="code" href="uniondcfg__data.html#efd84d3306db1b4370535a0e814612dc">d32</a> = dwc_read_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#c0c24937bbd7184884f05343f56ef1da">dcfg</a>);
+<a name="l00863"></a>00863         dcfg.<a class="code" href="uniondcfg__data.html#242c1b463f445de3fc265e8c20fde50b">b</a>.<a class="code" href="uniondcfg__data.html#d83666dcf5675453a387915ce1653d54">descdma</a> = (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a>) ? 1 : 0;
+<a name="l00864"></a>00864         dcfg.<a class="code" href="uniondcfg__data.html#242c1b463f445de3fc265e8c20fde50b">b</a>.<a class="code" href="uniondcfg__data.html#f4ed8f15f1716ff0f9366badac18fbb4">perfrint</a> = <a class="code" href="dwc__otg__regs_8h.html#d5b5378a658017c4f9cbdd8e4462d4fc">DWC_DCFG_FRAME_INTERVAL_80</a>;
+<a name="l00865"></a>00865 
+<a name="l00866"></a>00866         dwc_write_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#c0c24937bbd7184884f05343f56ef1da">dcfg</a>, dcfg.<a class="code" href="uniondcfg__data.html#efd84d3306db1b4370535a0e814612dc">d32</a>);
+<a name="l00867"></a>00867 
+<a name="l00868"></a>00868         <span class="comment">/* Configure data FIFO sizes */</span>
+<a name="l00869"></a>00869         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">hwcfg2</a>.<a class="code" href="unionhwcfg2__data.html#9dcc70e2dba617cbc6c12189be5c1d6a">b</a>.<a class="code" href="unionhwcfg2__data.html#b6bfbfe650352dec82a02d15677fe88d">dynamic_fifo</a> &amp;&amp; params-&gt;<a class="code" href="structdwc__otg__core__params.html#8c169633d4a6f28e964cef9f597c6e03">enable_dynamic_fifo</a>) {
+<a name="l00870"></a>00870                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">DBG_CIL</a>, <span class="stringliteral">"Total FIFO Size=%d\n"</span>,
+<a name="l00871"></a>00871                             core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#cae59008a554cb7de24bd4f2afea7532">total_fifo_size</a>);
+<a name="l00872"></a>00872                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">DBG_CIL</a>, <span class="stringliteral">"Rx FIFO Size=%d\n"</span>,
+<a name="l00873"></a>00873                             params-&gt;<a class="code" href="structdwc__otg__core__params.html#24ea6f9329f64ac0ad2d31dafe0d1d8c">dev_rx_fifo_size</a>);
+<a name="l00874"></a>00874                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">DBG_CIL</a>, <span class="stringliteral">"NP Tx FIFO Size=%d\n"</span>,
+<a name="l00875"></a>00875                             params-&gt;<a class="code" href="structdwc__otg__core__params.html#d08d9aee1fb4e6508089415d6150176e">dev_nperio_tx_fifo_size</a>);
+<a name="l00876"></a>00876 
+<a name="l00877"></a>00877                 <span class="comment">/* Rx FIFO */</span>
+<a name="l00878"></a>00878                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">DBG_CIL</a>, <span class="stringliteral">"initial grxfsiz=%08x\n"</span>,
+<a name="l00879"></a>00879                             dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#b1a8cc07a9541c9a73e864579602b79b">grxfsiz</a>));
+<a name="l00880"></a>00880 
+<a name="l00881"></a>00881 <span class="preprocessor">#ifdef DWC_UTE_CFI</span>
+<a name="l00882"></a>00882 <span class="preprocessor"></span>                core_if-&gt;pwron_rxfsiz = dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#b1a8cc07a9541c9a73e864579602b79b">grxfsiz</a>);
+<a name="l00883"></a>00883                 core_if-&gt;init_rxfsiz = params-&gt;<a class="code" href="structdwc__otg__core__params.html#24ea6f9329f64ac0ad2d31dafe0d1d8c">dev_rx_fifo_size</a>;
+<a name="l00884"></a>00884 <span class="preprocessor">#endif</span>
+<a name="l00885"></a>00885 <span class="preprocessor"></span>                rx_fifo_size = params-&gt;<a class="code" href="structdwc__otg__core__params.html#24ea6f9329f64ac0ad2d31dafe0d1d8c">dev_rx_fifo_size</a>;
+<a name="l00886"></a>00886                 dwc_write_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#b1a8cc07a9541c9a73e864579602b79b">grxfsiz</a>, rx_fifo_size);
+<a name="l00887"></a>00887 
+<a name="l00888"></a>00888                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">DBG_CIL</a>, <span class="stringliteral">"new grxfsiz=%08x\n"</span>,
+<a name="l00889"></a>00889                             dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#b1a8cc07a9541c9a73e864579602b79b">grxfsiz</a>));
+<a name="l00890"></a>00890 
+<a name="l00892"></a>00892                 core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#0683b28ebf5247a60247d27a1a714d27">p_tx_msk</a> = 0;
+<a name="l00893"></a>00893 
+<a name="l00895"></a>00895                 core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#b558bae74403677f08e45c692a88d4e2">tx_msk</a> = 0;
+<a name="l00896"></a>00896 
+<a name="l00897"></a>00897                 <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#31d08d1ebcd290b05139b0fcd24048ec">en_multiple_tx_fifo</a> == 0) {
+<a name="l00898"></a>00898                         <span class="comment">/* Non-periodic Tx FIFO */</span>
+<a name="l00899"></a>00899                         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">DBG_CIL</a>, <span class="stringliteral">"initial gnptxfsiz=%08x\n"</span>,
+<a name="l00900"></a>00900                                     dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#20fb70fe34a1a65d085b1d4e5f8d9106">gnptxfsiz</a>));
+<a name="l00901"></a>00901 
+<a name="l00902"></a>00902                         nptxfifosize.<a class="code" href="unionfifosize__data.html#4f0c71e88cc54c4efa4cd4ff43334c51">b</a>.<a class="code" href="unionfifosize__data.html#48c08d73da4d2d16d4320b93beb5ba8b">depth</a> = params-&gt;<a class="code" href="structdwc__otg__core__params.html#d08d9aee1fb4e6508089415d6150176e">dev_nperio_tx_fifo_size</a>;
+<a name="l00903"></a>00903                         nptxfifosize.<a class="code" href="unionfifosize__data.html#4f0c71e88cc54c4efa4cd4ff43334c51">b</a>.<a class="code" href="unionfifosize__data.html#26d78332a532cf9c0337c89edbff5f1b">startaddr</a> = params-&gt;<a class="code" href="structdwc__otg__core__params.html#24ea6f9329f64ac0ad2d31dafe0d1d8c">dev_rx_fifo_size</a>;
+<a name="l00904"></a>00904 
+<a name="l00905"></a>00905                         dwc_write_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#20fb70fe34a1a65d085b1d4e5f8d9106">gnptxfsiz</a>,
+<a name="l00906"></a>00906                                         nptxfifosize.<a class="code" href="unionfifosize__data.html#937e01b91f0a60a5aa9f6a4eaf6ce661">d32</a>);
+<a name="l00907"></a>00907 
+<a name="l00908"></a>00908                         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">DBG_CIL</a>, <span class="stringliteral">"new gnptxfsiz=%08x\n"</span>,
+<a name="l00909"></a>00909                                     dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#20fb70fe34a1a65d085b1d4e5f8d9106">gnptxfsiz</a>));
+<a name="l00910"></a>00910 
+<a name="l00912"></a>00912                         <span class="comment">/*</span>
+<a name="l00913"></a>00913 <span class="comment">                         * Periodic Tx FIFOs These FIFOs are numbered from 1 to 15.</span>
+<a name="l00914"></a>00914 <span class="comment">                         * Indexes of the FIFO size module parameters in the</span>
+<a name="l00915"></a>00915 <span class="comment">                         * dev_perio_tx_fifo_size array and the FIFO size registers in</span>
+<a name="l00916"></a>00916 <span class="comment">                         * the dptxfsiz array run from 0 to 14.</span>
+<a name="l00917"></a>00917 <span class="comment">                         */</span>
+<a name="l00919"></a>00919                         ptxfifosize.<a class="code" href="unionfifosize__data.html#4f0c71e88cc54c4efa4cd4ff43334c51">b</a>.<a class="code" href="unionfifosize__data.html#26d78332a532cf9c0337c89edbff5f1b">startaddr</a> =
+<a name="l00920"></a>00920                             nptxfifosize.<a class="code" href="unionfifosize__data.html#4f0c71e88cc54c4efa4cd4ff43334c51">b</a>.<a class="code" href="unionfifosize__data.html#26d78332a532cf9c0337c89edbff5f1b">startaddr</a> + nptxfifosize.<a class="code" href="unionfifosize__data.html#4f0c71e88cc54c4efa4cd4ff43334c51">b</a>.<a class="code" href="unionfifosize__data.html#48c08d73da4d2d16d4320b93beb5ba8b">depth</a>;
+<a name="l00921"></a>00921                         <span class="keywordflow">for</span> (i = 0; i &lt; core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#9c1394f3c46adde2fa7be79bf0237f9b">hwcfg4</a>.<a class="code" href="unionhwcfg4__data.html#9fb9175668e2381c568c5adbf6e5225d">b</a>.<a class="code" href="unionhwcfg4__data.html#aee60fb196cf53b610df556744e4d317">num_dev_perio_in_ep</a>;
+<a name="l00922"></a>00922                              i++) {
+<a name="l00923"></a>00923                                 ptxfifosize.<a class="code" href="unionfifosize__data.html#4f0c71e88cc54c4efa4cd4ff43334c51">b</a>.<a class="code" href="unionfifosize__data.html#48c08d73da4d2d16d4320b93beb5ba8b">depth</a> =
+<a name="l00924"></a>00924                                     params-&gt;<a class="code" href="structdwc__otg__core__params.html#2958d325289f4a77b6435cda729e5f6e">dev_perio_tx_fifo_size</a>[i];
+<a name="l00925"></a>00925                                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">DBG_CIL</a>,
+<a name="l00926"></a>00926                                             <span class="stringliteral">"initial dptxfsiz_dieptxf[%d]=%08x\n"</span>,
+<a name="l00927"></a>00927                                             i,
+<a name="l00928"></a>00928                                             dwc_read_reg32(&amp;global_regs-&gt;
+<a name="l00929"></a>00929                                                            dptxfsiz_dieptxf
+<a name="l00930"></a>00930                                                            [i]));
+<a name="l00931"></a>00931                                 dwc_write_reg32(&amp;global_regs-&gt;
+<a name="l00932"></a>00932                                                 dptxfsiz_dieptxf[i],
+<a name="l00933"></a>00933                                                 ptxfifosize.<a class="code" href="unionfifosize__data.html#937e01b91f0a60a5aa9f6a4eaf6ce661">d32</a>);
+<a name="l00934"></a>00934                                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(DBG_CIL,
+<a name="l00935"></a>00935                                             <span class="stringliteral">"new dptxfsiz_dieptxf[%d]=%08x\n"</span>,
+<a name="l00936"></a>00936                                             i,
+<a name="l00937"></a>00937                                             dwc_read_reg32(&amp;global_regs-&gt;
+<a name="l00938"></a>00938                                                            dptxfsiz_dieptxf
+<a name="l00939"></a>00939                                                            [i]));
+<a name="l00940"></a>00940                                 ptxfifosize.<a class="code" href="unionfifosize__data.html#4f0c71e88cc54c4efa4cd4ff43334c51">b</a>.<a class="code" href="unionfifosize__data.html#26d78332a532cf9c0337c89edbff5f1b">startaddr</a> += ptxfifosize.<a class="code" href="unionfifosize__data.html#4f0c71e88cc54c4efa4cd4ff43334c51">b</a>.<a class="code" href="unionfifosize__data.html#48c08d73da4d2d16d4320b93beb5ba8b">depth</a>;
+<a name="l00941"></a>00941                         }
+<a name="l00942"></a>00942                 } <span class="keywordflow">else</span> {
+<a name="l00943"></a>00943                         <span class="comment">/*</span>
+<a name="l00944"></a>00944 <span class="comment">                         * Tx FIFOs These FIFOs are numbered from 1 to 15.</span>
+<a name="l00945"></a>00945 <span class="comment">                         * Indexes of the FIFO size module parameters in the</span>
+<a name="l00946"></a>00946 <span class="comment">                         * dev_tx_fifo_size array and the FIFO size registers in</span>
+<a name="l00947"></a>00947 <span class="comment">                         * the dptxfsiz_dieptxf array run from 0 to 14.</span>
+<a name="l00948"></a>00948 <span class="comment">                         */</span>
+<a name="l00949"></a>00949 
+<a name="l00950"></a>00950                         <span class="comment">/* Non-periodic Tx FIFO */</span>
+<a name="l00951"></a>00951                         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">DBG_CIL</a>, <span class="stringliteral">"initial gnptxfsiz=%08x\n"</span>,
+<a name="l00952"></a>00952                                     dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#20fb70fe34a1a65d085b1d4e5f8d9106">gnptxfsiz</a>));
+<a name="l00953"></a>00953 
+<a name="l00954"></a>00954 <span class="preprocessor">#ifdef DWC_UTE_CFI</span>
+<a name="l00955"></a>00955 <span class="preprocessor"></span>                        core_if-&gt;pwron_gnptxfsiz =
+<a name="l00956"></a>00956                             (dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#20fb70fe34a1a65d085b1d4e5f8d9106">gnptxfsiz</a>) &gt;&gt; 16);
+<a name="l00957"></a>00957                         core_if-&gt;init_gnptxfsiz =
+<a name="l00958"></a>00958                             params-&gt;<a class="code" href="structdwc__otg__core__params.html#d08d9aee1fb4e6508089415d6150176e">dev_nperio_tx_fifo_size</a>;
+<a name="l00959"></a>00959 <span class="preprocessor">#endif</span>
+<a name="l00960"></a>00960 <span class="preprocessor"></span>                        nptxfifosize.<a class="code" href="unionfifosize__data.html#4f0c71e88cc54c4efa4cd4ff43334c51">b</a>.<a class="code" href="unionfifosize__data.html#48c08d73da4d2d16d4320b93beb5ba8b">depth</a> = params-&gt;<a class="code" href="structdwc__otg__core__params.html#d08d9aee1fb4e6508089415d6150176e">dev_nperio_tx_fifo_size</a>;
+<a name="l00961"></a>00961                         nptxfifosize.<a class="code" href="unionfifosize__data.html#4f0c71e88cc54c4efa4cd4ff43334c51">b</a>.<a class="code" href="unionfifosize__data.html#26d78332a532cf9c0337c89edbff5f1b">startaddr</a> = params-&gt;<a class="code" href="structdwc__otg__core__params.html#24ea6f9329f64ac0ad2d31dafe0d1d8c">dev_rx_fifo_size</a>;
+<a name="l00962"></a>00962 
+<a name="l00963"></a>00963                         dwc_write_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#20fb70fe34a1a65d085b1d4e5f8d9106">gnptxfsiz</a>,
+<a name="l00964"></a>00964                                         nptxfifosize.<a class="code" href="unionfifosize__data.html#937e01b91f0a60a5aa9f6a4eaf6ce661">d32</a>);
+<a name="l00965"></a>00965 
+<a name="l00966"></a>00966                         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">DBG_CIL</a>, <span class="stringliteral">"new gnptxfsiz=%08x\n"</span>,
+<a name="l00967"></a>00967                                     dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#20fb70fe34a1a65d085b1d4e5f8d9106">gnptxfsiz</a>));
+<a name="l00968"></a>00968 
+<a name="l00969"></a>00969                         txfifosize.<a class="code" href="unionfifosize__data.html#4f0c71e88cc54c4efa4cd4ff43334c51">b</a>.<a class="code" href="unionfifosize__data.html#26d78332a532cf9c0337c89edbff5f1b">startaddr</a> =
+<a name="l00970"></a>00970                             nptxfifosize.<a class="code" href="unionfifosize__data.html#4f0c71e88cc54c4efa4cd4ff43334c51">b</a>.<a class="code" href="unionfifosize__data.html#26d78332a532cf9c0337c89edbff5f1b">startaddr</a> + nptxfifosize.<a class="code" href="unionfifosize__data.html#4f0c71e88cc54c4efa4cd4ff43334c51">b</a>.<a class="code" href="unionfifosize__data.html#48c08d73da4d2d16d4320b93beb5ba8b">depth</a>;
+<a name="l00971"></a>00971 
+<a name="l00972"></a>00972                         <span class="keywordflow">for</span> (i = 0; i &lt; core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#9c1394f3c46adde2fa7be79bf0237f9b">hwcfg4</a>.<a class="code" href="unionhwcfg4__data.html#9fb9175668e2381c568c5adbf6e5225d">b</a>.<a class="code" href="unionhwcfg4__data.html#753b321350388c5e1307802ff968f9a8">num_in_eps</a>; i++) {
+<a name="l00973"></a>00973 
+<a name="l00974"></a>00974                                 txfifosize.<a class="code" href="unionfifosize__data.html#4f0c71e88cc54c4efa4cd4ff43334c51">b</a>.<a class="code" href="unionfifosize__data.html#48c08d73da4d2d16d4320b93beb5ba8b">depth</a> =
+<a name="l00975"></a>00975                                     params-&gt;<a class="code" href="structdwc__otg__core__params.html#6e0c5d06467fbf3458f11f7eb8153a8b">dev_tx_fifo_size</a>[i];
+<a name="l00976"></a>00976 
+<a name="l00977"></a>00977                                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">DBG_CIL</a>,
+<a name="l00978"></a>00978                                             <span class="stringliteral">"initial dptxfsiz_dieptxf[%d]=%08x\n"</span>,
+<a name="l00979"></a>00979                                             i,
+<a name="l00980"></a>00980                                             dwc_read_reg32(&amp;global_regs-&gt;
+<a name="l00981"></a>00981                                                            dptxfsiz_dieptxf
+<a name="l00982"></a>00982                                                            [i]));
+<a name="l00983"></a>00983 
+<a name="l00984"></a>00984 #ifdef DWC_UTE_CFI
+<a name="l00985"></a>00985                                 core_if-&gt;pwron_txfsiz[i] =
+<a name="l00986"></a>00986                                     (dwc_read_reg32
+<a name="l00987"></a>00987                                      (&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#efd9e780825f992dbc6cf46d2d72869e">dptxfsiz_dieptxf</a>[i]) &gt;&gt; 16);
+<a name="l00988"></a>00988                                 core_if-&gt;init_txfsiz[i] =
+<a name="l00989"></a>00989                                     params-&gt;<a class="code" href="structdwc__otg__core__params.html#6e0c5d06467fbf3458f11f7eb8153a8b">dev_tx_fifo_size</a>[i];
+<a name="l00990"></a>00990 #endif
+<a name="l00991"></a>00991                                 dwc_write_reg32(&amp;global_regs-&gt;
+<a name="l00992"></a>00992                                                 dptxfsiz_dieptxf[i],
+<a name="l00993"></a>00993                                                 txfifosize.<a class="code" href="unionfifosize__data.html#937e01b91f0a60a5aa9f6a4eaf6ce661">d32</a>);
+<a name="l00994"></a>00994 
+<a name="l00995"></a>00995                                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(DBG_CIL,
+<a name="l00996"></a>00996                                             <span class="stringliteral">"new dptxfsiz_dieptxf[%d]=%08x\n"</span>,
+<a name="l00997"></a>00997                                             i,
+<a name="l00998"></a>00998                                             dwc_read_reg32(&amp;global_regs-&gt;
+<a name="l00999"></a>00999                                                            dptxfsiz_dieptxf
+<a name="l01000"></a>01000                                                            [i]));
+<a name="l01001"></a>01001 
+<a name="l01002"></a>01002                                 txfifosize.<a class="code" href="unionfifosize__data.html#4f0c71e88cc54c4efa4cd4ff43334c51">b</a>.<a class="code" href="unionfifosize__data.html#26d78332a532cf9c0337c89edbff5f1b">startaddr</a> += txfifosize.<a class="code" href="unionfifosize__data.html#4f0c71e88cc54c4efa4cd4ff43334c51">b</a>.<a class="code" href="unionfifosize__data.html#48c08d73da4d2d16d4320b93beb5ba8b">depth</a>;
+<a name="l01003"></a>01003                         }
+<a name="l01004"></a>01004                 }
+<a name="l01005"></a>01005         }
+<a name="l01006"></a>01006         <span class="comment">/* Flush the FIFOs */</span>
+<a name="l01007"></a>01007         <a class="code" href="dwc__otg__cil_8c.html#039e387cd0e0282727da3c5a36f4cdda">dwc_otg_flush_tx_fifo</a>(core_if, 0x10);   <span class="comment">/* all Tx FIFOs */</span>
+<a name="l01008"></a>01008         <a class="code" href="dwc__otg__cil_8c.html#fb275f0f9923cc30629fce5e3753025c">dwc_otg_flush_rx_fifo</a>(core_if);
+<a name="l01009"></a>01009 
+<a name="l01010"></a>01010         <span class="comment">/* Flush the Learning Queue. */</span>
+<a name="l01011"></a>01011         resetctl.<a class="code" href="uniongrstctl__data.html#7907ac8831a2f72dec59592a093871e3">b</a>.<a class="code" href="uniongrstctl__data.html#259049fa7991ecad9ca1595763b636f9">intknqflsh</a> = 1;
+<a name="l01012"></a>01012         dwc_write_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#49d307957dbe53f20aa8f7a5409ee8ad">grstctl</a>, resetctl.<a class="code" href="uniongrstctl__data.html#d89d99c95bd5177fbd879d38963d3e62">d32</a>);
+<a name="l01013"></a>01013 
+<a name="l01014"></a>01014         <span class="comment">/* Clear all pending Device Interrupts */</span>
+<a name="l01018"></a>01018         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5675c8d8dd7df746fda9157dc39ba5c2">multiproc_int_enable</a>) {
+<a name="l01019"></a>01019                 <span class="keywordflow">for</span> (i = 0; i &lt; core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#4fae9bc1293bf2e58966c38fa5b98822">num_in_eps</a>; ++i) {
+<a name="l01020"></a>01020                         dwc_write_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;
+<a name="l01021"></a>01021                                         diepeachintmsk[i], 0);
+<a name="l01022"></a>01022                 }
+<a name="l01023"></a>01023 
+<a name="l01024"></a>01024                 <span class="keywordflow">for</span> (i = 0; i &lt; core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#2f0e01cdc605623f591963fc83c8dc73">num_out_eps</a>; ++i) {
+<a name="l01025"></a>01025                         dwc_write_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;
+<a name="l01026"></a>01026                                         doepeachintmsk[i], 0);
+<a name="l01027"></a>01027                 }
+<a name="l01028"></a>01028 
+<a name="l01029"></a>01029                 dwc_write_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#4795bc8eab569241a3f8e6aad5d99ac7">deachint</a>, 0xFFFFFFFF);
+<a name="l01030"></a>01030                 dwc_write_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#e64a153683f0e0cda14b56a163651825">deachintmsk</a>, 0);
+<a name="l01031"></a>01031         } <span class="keywordflow">else</span> {
+<a name="l01032"></a>01032                 dwc_write_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#02e44cb182548d78c5b7d27929ca5f11">diepmsk</a>, 0);
+<a name="l01033"></a>01033                 dwc_write_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#d6947be9d84a1d87156f81a10ebb036b">doepmsk</a>, 0);
+<a name="l01034"></a>01034                 dwc_write_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#2e25df2fbec9d398742709524056cbd5">daint</a>, 0xFFFFFFFF);
+<a name="l01035"></a>01035                 dwc_write_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#5def6c3850c041928b9a662422ee0679">daintmsk</a>, 0);
+<a name="l01036"></a>01036         }
+<a name="l01037"></a>01037 
+<a name="l01038"></a>01038         <span class="keywordflow">for</span> (i = 0; i &lt;= dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#4fae9bc1293bf2e58966c38fa5b98822">num_in_eps</a>; i++) {
+<a name="l01039"></a>01039                 <a class="code" href="uniondepctl__data.html">depctl_data_t</a> depctl;
+<a name="l01040"></a>01040                 depctl.d32 = dwc_read_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[i]-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#53a5adb977e2aec66d4902c6ba293216">diepctl</a>);
+<a name="l01041"></a>01041                 <span class="keywordflow">if</span> (depctl.b.epena) {
+<a name="l01042"></a>01042                         depctl.d32 = 0;
+<a name="l01043"></a>01043                         depctl.b.epdis = 1;
+<a name="l01044"></a>01044                         depctl.b.snak = 1;
+<a name="l01045"></a>01045                 } <span class="keywordflow">else</span> {
+<a name="l01046"></a>01046                         depctl.d32 = 0;
+<a name="l01047"></a>01047                 }
+<a name="l01048"></a>01048 
+<a name="l01049"></a>01049                 dwc_write_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[i]-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#53a5adb977e2aec66d4902c6ba293216">diepctl</a>, depctl.d32);
+<a name="l01050"></a>01050 
+<a name="l01051"></a>01051                 dwc_write_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[i]-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#88f637b5a4e8a0c6bc87d157072255dd">dieptsiz</a>, 0);
+<a name="l01052"></a>01052                 dwc_write_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[i]-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#5f013840a15e0a310b8722646880a420">diepdma</a>, 0);
+<a name="l01053"></a>01053                 dwc_write_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[i]-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#4d6d6309ef5e09ad9048655ced6a2769">diepint</a>, 0xFF);
+<a name="l01054"></a>01054         }
+<a name="l01055"></a>01055 
+<a name="l01056"></a>01056         <span class="keywordflow">for</span> (i = 0; i &lt;= dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#2f0e01cdc605623f591963fc83c8dc73">num_out_eps</a>; i++) {
+<a name="l01057"></a>01057                 <a class="code" href="uniondepctl__data.html">depctl_data_t</a> depctl;
+<a name="l01058"></a>01058                 depctl.d32 = dwc_read_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">out_ep_regs</a>[i]-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#2a522b71fc97658c07debf3521f7d3e5">doepctl</a>);
+<a name="l01059"></a>01059                 <span class="keywordflow">if</span> (depctl.b.epena) {
+<a name="l01060"></a>01060                         depctl.d32 = 0;
+<a name="l01061"></a>01061                         depctl.b.epdis = 1;
+<a name="l01062"></a>01062                         depctl.b.snak = 1;
+<a name="l01063"></a>01063                 } <span class="keywordflow">else</span> {
+<a name="l01064"></a>01064                         depctl.d32 = 0;
+<a name="l01065"></a>01065                 }
+<a name="l01066"></a>01066 
+<a name="l01067"></a>01067                 dwc_write_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">out_ep_regs</a>[i]-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#2a522b71fc97658c07debf3521f7d3e5">doepctl</a>, depctl.d32);
+<a name="l01068"></a>01068 
+<a name="l01069"></a>01069                 dwc_write_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">out_ep_regs</a>[i]-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#e756ec48787099f0a4e2ce353fce4f91">doeptsiz</a>, 0);
+<a name="l01070"></a>01070                 dwc_write_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">out_ep_regs</a>[i]-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#006071bf54bfa1c1f5e25cf4c9f65cb1">doepdma</a>, 0);
+<a name="l01071"></a>01071                 dwc_write_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">out_ep_regs</a>[i]-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#81d837c801dcfa30f17b567419a86f62">doepint</a>, 0xFF);
+<a name="l01072"></a>01072         }
+<a name="l01073"></a>01073 
+<a name="l01074"></a>01074         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#31d08d1ebcd290b05139b0fcd24048ec">en_multiple_tx_fifo</a> &amp;&amp; core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a>) {
+<a name="l01075"></a>01075                 dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#c4c1cdbb40f37e3403d62ae00b4819eb">non_iso_tx_thr_en</a> = params-&gt;<a class="code" href="structdwc__otg__core__params.html#1610a4b28bea581c46f251d995bf4a51">thr_ctl</a> &amp; 0x1;
+<a name="l01076"></a>01076                 dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#76af117a05ad95e5e5c534a1afcdae22">iso_tx_thr_en</a> = (params-&gt;<a class="code" href="structdwc__otg__core__params.html#1610a4b28bea581c46f251d995bf4a51">thr_ctl</a> &gt;&gt; 1) &amp; 0x1;
+<a name="l01077"></a>01077                 dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#839ada1cbeff50af91f5db00f4b36ec4">rx_thr_en</a> = (params-&gt;<a class="code" href="structdwc__otg__core__params.html#1610a4b28bea581c46f251d995bf4a51">thr_ctl</a> &gt;&gt; 2) &amp; 0x1;
+<a name="l01078"></a>01078 
+<a name="l01079"></a>01079                 dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#e1ec98fc03446d7e172572a973107d62">rx_thr_length</a> = params-&gt;<a class="code" href="structdwc__otg__core__params.html#2cb1f83013e357828fbf55ac91971d44">rx_thr_length</a>;
+<a name="l01080"></a>01080                 dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#55206f9ce7b0c2614e2c534d01acd6c4">tx_thr_length</a> = params-&gt;<a class="code" href="structdwc__otg__core__params.html#c92fc907d503f9b8bb3600164c520b0e">tx_thr_length</a>;
+<a name="l01081"></a>01081 
+<a name="l01082"></a>01082                 dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#dd45f3935b2ebb171de8da70cddd6935">setup_desc_index</a> = 0;
+<a name="l01083"></a>01083 
+<a name="l01084"></a>01084                 dthrctl.<a class="code" href="uniondthrctl__data.html#f66c52fe9278bb6ed52c811ddbed16a5">d32</a> = 0;
+<a name="l01085"></a>01085                 dthrctl.<a class="code" href="uniondthrctl__data.html#298be6991ca44e5e1ca558471789d33f">b</a>.<a class="code" href="uniondthrctl__data.html#9b9e309f454fb10621cbaeafe068af47">non_iso_thr_en</a> = dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#c4c1cdbb40f37e3403d62ae00b4819eb">non_iso_tx_thr_en</a>;
+<a name="l01086"></a>01086                 dthrctl.<a class="code" href="uniondthrctl__data.html#298be6991ca44e5e1ca558471789d33f">b</a>.<a class="code" href="uniondthrctl__data.html#f69727f09d4443c01038ba7b163814f8">iso_thr_en</a> = dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#76af117a05ad95e5e5c534a1afcdae22">iso_tx_thr_en</a>;
+<a name="l01087"></a>01087                 dthrctl.<a class="code" href="uniondthrctl__data.html#298be6991ca44e5e1ca558471789d33f">b</a>.<a class="code" href="uniondthrctl__data.html#75959c97b938bf99faa602c933938340">tx_thr_len</a> = dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#55206f9ce7b0c2614e2c534d01acd6c4">tx_thr_length</a>;
+<a name="l01088"></a>01088                 dthrctl.<a class="code" href="uniondthrctl__data.html#298be6991ca44e5e1ca558471789d33f">b</a>.<a class="code" href="uniondthrctl__data.html#0a73132b4e481b250e1b5f533b807bcb">rx_thr_en</a> = dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#839ada1cbeff50af91f5db00f4b36ec4">rx_thr_en</a>;
+<a name="l01089"></a>01089                 dthrctl.<a class="code" href="uniondthrctl__data.html#298be6991ca44e5e1ca558471789d33f">b</a>.<a class="code" href="uniondthrctl__data.html#210370ba2134a296e1c1dcc8b2f05461">rx_thr_len</a> = dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#e1ec98fc03446d7e172572a973107d62">rx_thr_length</a>;
+<a name="l01090"></a>01090                 dthrctl.<a class="code" href="uniondthrctl__data.html#298be6991ca44e5e1ca558471789d33f">b</a>.<a class="code" href="uniondthrctl__data.html#00bbf39ee16616cc14410549c1e97c45">ahb_thr_ratio</a> = params-&gt;<a class="code" href="structdwc__otg__core__params.html#8787af52f8d70a9100ab1fa2b0f69bfb">ahb_thr_ratio</a>;
+<a name="l01091"></a>01091 
+<a name="l01092"></a>01092                 dwc_write_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#c263c55a0bb752f8939731aa2f8f6cb8">dtknqr3_dthrctl</a>,
+<a name="l01093"></a>01093                                 dthrctl.<a class="code" href="uniondthrctl__data.html#f66c52fe9278bb6ed52c811ddbed16a5">d32</a>);
+<a name="l01094"></a>01094 
+<a name="l01095"></a>01095                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">DBG_CIL</a>,
+<a name="l01096"></a>01096                             <span class="stringliteral">"Non ISO Tx Thr - %d\nISO Tx Thr - %d\nRx Thr - %d\nTx Thr Len - %d\nRx Thr Len - %d\n"</span>,
+<a name="l01097"></a>01097                             dthrctl.<a class="code" href="uniondthrctl__data.html#298be6991ca44e5e1ca558471789d33f">b</a>.<a class="code" href="uniondthrctl__data.html#9b9e309f454fb10621cbaeafe068af47">non_iso_thr_en</a>, dthrctl.<a class="code" href="uniondthrctl__data.html#298be6991ca44e5e1ca558471789d33f">b</a>.<a class="code" href="uniondthrctl__data.html#f69727f09d4443c01038ba7b163814f8">iso_thr_en</a>,
+<a name="l01098"></a>01098                             dthrctl.<a class="code" href="uniondthrctl__data.html#298be6991ca44e5e1ca558471789d33f">b</a>.<a class="code" href="uniondthrctl__data.html#0a73132b4e481b250e1b5f533b807bcb">rx_thr_en</a>, dthrctl.<a class="code" href="uniondthrctl__data.html#298be6991ca44e5e1ca558471789d33f">b</a>.<a class="code" href="uniondthrctl__data.html#75959c97b938bf99faa602c933938340">tx_thr_len</a>,
+<a name="l01099"></a>01099                             dthrctl.<a class="code" href="uniondthrctl__data.html#298be6991ca44e5e1ca558471789d33f">b</a>.<a class="code" href="uniondthrctl__data.html#210370ba2134a296e1c1dcc8b2f05461">rx_thr_len</a>);
+<a name="l01100"></a>01100 
+<a name="l01101"></a>01101         }
+<a name="l01102"></a>01102 
+<a name="l01103"></a>01103         <a class="code" href="dwc__otg__cil_8c.html#3d60e58f32be881047ac61bc852f60f7">dwc_otg_enable_device_interrupts</a>(core_if);
+<a name="l01104"></a>01104 
+<a name="l01105"></a>01105         {
+<a name="l01106"></a>01106                 <a class="code" href="uniondiepint__data.html">diepmsk_data_t</a> msk = {.d32 = 0 };
+<a name="l01107"></a>01107                 msk.<a class="code" href="uniondiepint__data.html#48d2a745e0ec983a47b35b0428b0437d">b</a>.<a class="code" href="uniondiepint__data.html#90d0e6a99275eccd4a50f62644de9152">txfifoundrn</a> = 1;
+<a name="l01108"></a>01108                 <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5675c8d8dd7df746fda9157dc39ba5c2">multiproc_int_enable</a>) {
+<a name="l01109"></a>01109                         dwc_modify_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;
+<a name="l01110"></a>01110                                          diepeachintmsk[0], msk.<a class="code" href="uniondiepint__data.html#7d2c24507663bf96c280c57fbf544ef7">d32</a>, msk.<a class="code" href="uniondiepint__data.html#7d2c24507663bf96c280c57fbf544ef7">d32</a>);
+<a name="l01111"></a>01111                 } <span class="keywordflow">else</span> {
+<a name="l01112"></a>01112                         dwc_modify_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#02e44cb182548d78c5b7d27929ca5f11">diepmsk</a>,
+<a name="l01113"></a>01113                                          msk.<a class="code" href="uniondiepint__data.html#7d2c24507663bf96c280c57fbf544ef7">d32</a>, msk.<a class="code" href="uniondiepint__data.html#7d2c24507663bf96c280c57fbf544ef7">d32</a>);
+<a name="l01114"></a>01114                 }
+<a name="l01115"></a>01115         }
+<a name="l01116"></a>01116 
+<a name="l01117"></a>01117         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5675c8d8dd7df746fda9157dc39ba5c2">multiproc_int_enable</a>) {
+<a name="l01118"></a>01118                 <span class="comment">/* Set NAK on Babble */</span>
+<a name="l01119"></a>01119                 <a class="code" href="uniondctl__data.html">dctl_data_t</a> dctl = {.d32 = 0 };
+<a name="l01120"></a>01120                 dctl.<a class="code" href="uniondctl__data.html#a3abfa6d609d9864f1f65712b409d4d3">b</a>.<a class="code" href="uniondctl__data.html#422c27727aa788391b807b62011bd464">nakonbble</a> = 1;
+<a name="l01121"></a>01121                 dwc_modify_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#3779c2fc508920a831a59e696a8fa785">dctl</a>, 0, dctl.<a class="code" href="uniondctl__data.html#f49aadfd7ad95b570115b3c245b1729e">d32</a>);
+<a name="l01122"></a>01122         }
+<a name="l01123"></a>01123 }
+<a name="l01124"></a>01124 
+<a name="l01130"></a><a class="code" href="dwc__otg__cil_8h.html#99a7497537db075b95c72816e766acf8">01130</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#373701240c023fda03eed98cf093df74">dwc_otg_enable_host_interrupts</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l01131"></a>01131 {
+<a name="l01132"></a>01132         <a class="code" href="structdwc__otg__core__global__regs.html">dwc_otg_core_global_regs_t</a> *global_regs = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>;
+<a name="l01133"></a>01133         <a class="code" href="uniongintmsk__data.html">gintmsk_data_t</a> intr_mask = {.d32 = 0 };
+<a name="l01134"></a>01134 
+<a name="l01135"></a>01135         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">DBG_CIL</a>, <span class="stringliteral">"%s()\n"</span>, __func__);
+<a name="l01136"></a>01136 
+<a name="l01137"></a>01137         <span class="comment">/* Disable all interrupts. */</span>
+<a name="l01138"></a>01138         dwc_write_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#48827c76da2c6b18f369e2f2483cc4b6">gintmsk</a>, 0);
+<a name="l01139"></a>01139 
+<a name="l01140"></a>01140         <span class="comment">/* Clear any pending interrupts. */</span>
+<a name="l01141"></a>01141         dwc_write_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>, 0xFFFFFFFF);
+<a name="l01142"></a>01142 
+<a name="l01143"></a>01143         <span class="comment">/* Enable the common interrupts */</span>
+<a name="l01144"></a>01144         <a class="code" href="dwc__otg__cil_8c.html#1761ac95e17bad3fa304413cc81c51de">dwc_otg_enable_common_interrupts</a>(core_if);
+<a name="l01145"></a>01145 
+<a name="l01146"></a>01146         <span class="comment">/*</span>
+<a name="l01147"></a>01147 <span class="comment">         * Enable host mode interrupts without disturbing common</span>
+<a name="l01148"></a>01148 <span class="comment">         * interrupts.</span>
+<a name="l01149"></a>01149 <span class="comment">         */</span>
+<a name="l01150"></a>01150          
+<a name="l01151"></a>01151         <span class="comment">/* Do not need sof interrupt for Descriptor DMA*/</span> 
+<a name="l01152"></a>01152         <span class="keywordflow">if</span> (!core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a>) 
+<a name="l01153"></a>01153         intr_mask.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#d9cb28e92090a5da3c00d35768d90c82">sofintr</a> = 1;
+<a name="l01154"></a>01154         intr_mask.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#c907c60cbc7b157e730b053b40f4a2b3">portintr</a> = 1;
+<a name="l01155"></a>01155         intr_mask.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#3a4c193d8ff48291809dcd3ccb7c0585">hcintr</a> = 1;
+<a name="l01156"></a>01156 
+<a name="l01157"></a>01157         dwc_modify_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#48827c76da2c6b18f369e2f2483cc4b6">gintmsk</a>, intr_mask.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a>, intr_mask.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a>);
+<a name="l01158"></a>01158 }
+<a name="l01159"></a>01159 
+<a name="l01165"></a><a class="code" href="dwc__otg__cil_8h.html#6f3cf40d961167bf8c5888bcf577c15b">01165</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#4dd4a30dd75a819e9da38d6410cbb0a4">dwc_otg_disable_host_interrupts</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l01166"></a>01166 {
+<a name="l01167"></a>01167         <a class="code" href="structdwc__otg__core__global__regs.html">dwc_otg_core_global_regs_t</a> *global_regs = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>;
+<a name="l01168"></a>01168         <a class="code" href="uniongintmsk__data.html">gintmsk_data_t</a> intr_mask = {.d32 = 0 };
+<a name="l01169"></a>01169 
+<a name="l01170"></a>01170         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#daab8e158c0c530486656ef52e5b0bbe">DBG_CILV</a>, <span class="stringliteral">"%s()\n"</span>, __func__);
+<a name="l01171"></a>01171 
+<a name="l01172"></a>01172         <span class="comment">/*</span>
+<a name="l01173"></a>01173 <span class="comment">         * Disable host mode interrupts without disturbing common</span>
+<a name="l01174"></a>01174 <span class="comment">         * interrupts.</span>
+<a name="l01175"></a>01175 <span class="comment">         */</span>
+<a name="l01176"></a>01176         intr_mask.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#d9cb28e92090a5da3c00d35768d90c82">sofintr</a> = 1;
+<a name="l01177"></a>01177         intr_mask.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#c907c60cbc7b157e730b053b40f4a2b3">portintr</a> = 1;
+<a name="l01178"></a>01178         intr_mask.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#3a4c193d8ff48291809dcd3ccb7c0585">hcintr</a> = 1;
+<a name="l01179"></a>01179         intr_mask.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#3b52444894e041c660c146af2178272f">ptxfempty</a> = 1;
+<a name="l01180"></a>01180         intr_mask.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#2c395e7bef31a4d9b2d1a3257c601be4">nptxfempty</a> = 1;
+<a name="l01181"></a>01181 
+<a name="l01182"></a>01182         dwc_modify_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#48827c76da2c6b18f369e2f2483cc4b6">gintmsk</a>, intr_mask.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a>, 0);
+<a name="l01183"></a>01183 }
+<a name="l01184"></a>01184 
+<a name="l01196"></a><a class="code" href="dwc__otg__cil_8h.html#9389236ccea6cb2710628143ab771004">01196</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#04ad276f20faad71333f6293c952744e">dwc_otg_core_host_init</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l01197"></a>01197 {
+<a name="l01198"></a>01198         <a class="code" href="structdwc__otg__core__global__regs.html">dwc_otg_core_global_regs_t</a> *global_regs = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>;
+<a name="l01199"></a>01199         <a class="code" href="structdwc__otg__host__if.html">dwc_otg_host_if_t</a> *host_if = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>;
+<a name="l01200"></a>01200         <a class="code" href="structdwc__otg__core__params.html">dwc_otg_core_params_t</a> *params = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>;
+<a name="l01201"></a>01201         <a class="code" href="unionhprt0__data.html">hprt0_data_t</a> hprt0 = {.d32 = 0 };
+<a name="l01202"></a>01202         <a class="code" href="unionfifosize__data.html">fifosize_data_t</a> nptxfifosize;
+<a name="l01203"></a>01203         <a class="code" href="unionfifosize__data.html">fifosize_data_t</a> ptxfifosize;
+<a name="l01204"></a>01204         <span class="keywordtype">int</span> i;
+<a name="l01205"></a>01205         <a class="code" href="unionhcchar__data.html">hcchar_data_t</a> hcchar;
+<a name="l01206"></a>01206         <a class="code" href="unionhcfg__data.html">hcfg_data_t</a> hcfg;
+<a name="l01207"></a>01207         <a class="code" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *hc_regs;
+<a name="l01208"></a>01208         <span class="keywordtype">int</span> num_channels;
+<a name="l01209"></a>01209         <a class="code" href="uniongotgctl__data.html">gotgctl_data_t</a> gotgctl = {.d32 = 0 };
+<a name="l01210"></a>01210 
+<a name="l01211"></a>01211         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#daab8e158c0c530486656ef52e5b0bbe">DBG_CILV</a>, <span class="stringliteral">"%s(%p)\n"</span>, __func__, core_if);
+<a name="l01212"></a>01212 
+<a name="l01213"></a>01213         <span class="comment">/* Restart the Phy Clock */</span>
+<a name="l01214"></a>01214         dwc_write_reg32(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#348ed2c9aeae6fc608f1bb813978b3f9">pcgcctl</a>, 0);
+<a name="l01215"></a>01215 
+<a name="l01216"></a>01216         <span class="comment">/* Initialize Host Configuration Register */</span>
+<a name="l01217"></a>01217         <a class="code" href="dwc__otg__cil_8c.html#4550564b18dcd56bd2c4ec1ba91c6e13">init_fslspclksel</a>(core_if);
+<a name="l01218"></a>01218         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#d2c4f622f1c14f68c6e60e2603acd09d">speed</a> == <a class="code" href="dwc__otg__core__if_8h.html#353c64bfe6bbc9da8406528ad8220166">DWC_SPEED_PARAM_FULL</a>) {
+<a name="l01219"></a>01219                 hcfg.<a class="code" href="unionhcfg__data.html#381a253b3a38a7f943dcbb42f7bf10be">d32</a> = dwc_read_reg32(&amp;host_if-&gt;<a class="code" href="structdwc__otg__host__if.html#ff9692c2e10ca2bc7e24f981f25179c2">host_global_regs</a>-&gt;<a class="code" href="structdwc__otg__host__global__regs.html#fd7d93b5ffcb6c7c0a84ef656e6e68de">hcfg</a>);
+<a name="l01220"></a>01220                 hcfg.<a class="code" href="unionhcfg__data.html#45bbb24387d58961dd2b8f2f65689bd7">b</a>.<a class="code" href="unionhcfg__data.html#c047f55e398b8a94aef27a66ed78f2de">fslssupp</a> = 1;
+<a name="l01221"></a>01221                 dwc_write_reg32(&amp;host_if-&gt;<a class="code" href="structdwc__otg__host__if.html#ff9692c2e10ca2bc7e24f981f25179c2">host_global_regs</a>-&gt;<a class="code" href="structdwc__otg__host__global__regs.html#fd7d93b5ffcb6c7c0a84ef656e6e68de">hcfg</a>, hcfg.<a class="code" href="unionhcfg__data.html#381a253b3a38a7f943dcbb42f7bf10be">d32</a>);
+<a name="l01222"></a>01222                 
+<a name="l01223"></a>01223         }
+<a name="l01224"></a>01224 
+<a name="l01225"></a>01225         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#36c5bcf00d0f776b5c9e84e5d8ae408d">dma_desc_enable</a>) {
+<a name="l01226"></a>01226                 uint8_t op_mode = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">hwcfg2</a>.<a class="code" href="unionhwcfg2__data.html#9dcc70e2dba617cbc6c12189be5c1d6a">b</a>.<a class="code" href="unionhwcfg2__data.html#592df9b97ff9342b839d2ed76d54c652">op_mode</a>;    
+<a name="l01227"></a>01227                 <span class="keywordflow">if</span> (!(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#9c1394f3c46adde2fa7be79bf0237f9b">hwcfg4</a>.<a class="code" href="unionhwcfg4__data.html#9fb9175668e2381c568c5adbf6e5225d">b</a>.<a class="code" href="unionhwcfg4__data.html#988888a48e9088d0e9f889818eb63509">desc_dma</a> &amp;&amp; (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#afc495591efa54c74c1dd50278b57ffe">snpsid</a> &gt;= <a class="code" href="dwc__otg__cil_8h.html#c2f4aa7b1cfc164330925404c5029724">OTG_CORE_REV_2_90a</a>) &amp;&amp;
+<a name="l01228"></a>01228                                 ((op_mode == <a class="code" href="dwc__otg__regs_8h.html#8af3c99831b24f4f12a6d5c8d738b5c1">DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG</a>) ||
+<a name="l01229"></a>01229                                 (op_mode == <a class="code" href="dwc__otg__regs_8h.html#184dedc2208935e427ec8d70f63acc03">DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG</a>) || 
+<a name="l01230"></a>01230                                 (op_mode == <a class="code" href="dwc__otg__regs_8h.html#9f259c90ff1115e85ad4ffc7dab0186b">DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG</a>) ||
+<a name="l01231"></a>01231                                 (op_mode == <a class="code" href="dwc__otg__regs_8h.html#77eccf27fae160a4ad7f72b1b43864c3">DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST</a>) ||
+<a name="l01232"></a>01232                                 (op_mode == <a class="code" href="dwc__otg__regs_8h.html#dc5c9ee91aa1e0070aa05fd7d958ab8f">DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST</a>)))) {
+<a name="l01233"></a>01233                                 
+<a name="l01234"></a>01234                                 DWC_ERROR(<span class="stringliteral">"Host can't operate in Descriptor DMA mode.\n"</span>
+<a name="l01235"></a>01235                                           <span class="stringliteral">"Either core version is below 2.90a or "</span>
+<a name="l01236"></a>01236                                           <span class="stringliteral">"GHWCFG2, GHWCFG4 registers' values do not allow Descriptor DMA in host mode.\n"</span>
+<a name="l01237"></a>01237                                           <span class="stringliteral">"To run the driver in Buffer DMA host mode set dma_desc_enable "</span>
+<a name="l01238"></a>01238                                           <span class="stringliteral">"module parameter to 0.\n"</span>);
+<a name="l01239"></a>01239                                 <span class="keywordflow">return</span>;
+<a name="l01240"></a>01240                 }               
+<a name="l01241"></a>01241                 hcfg.<a class="code" href="unionhcfg__data.html#381a253b3a38a7f943dcbb42f7bf10be">d32</a> = dwc_read_reg32(&amp;host_if-&gt;<a class="code" href="structdwc__otg__host__if.html#ff9692c2e10ca2bc7e24f981f25179c2">host_global_regs</a>-&gt;<a class="code" href="structdwc__otg__host__global__regs.html#fd7d93b5ffcb6c7c0a84ef656e6e68de">hcfg</a>);
+<a name="l01242"></a>01242                 hcfg.<a class="code" href="unionhcfg__data.html#45bbb24387d58961dd2b8f2f65689bd7">b</a>.<a class="code" href="unionhcfg__data.html#7ec04d77b1c0d3cc25165e77e9bce5f4">descdma</a> = 1;
+<a name="l01243"></a>01243                 dwc_write_reg32(&amp;host_if-&gt;<a class="code" href="structdwc__otg__host__if.html#ff9692c2e10ca2bc7e24f981f25179c2">host_global_regs</a>-&gt;<a class="code" href="structdwc__otg__host__global__regs.html#fd7d93b5ffcb6c7c0a84ef656e6e68de">hcfg</a>, hcfg.<a class="code" href="unionhcfg__data.html#381a253b3a38a7f943dcbb42f7bf10be">d32</a>);
+<a name="l01244"></a>01244         }
+<a name="l01245"></a>01245         
+<a name="l01246"></a>01246         <span class="comment">/* Configure data FIFO sizes */</span>
+<a name="l01247"></a>01247         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">hwcfg2</a>.<a class="code" href="unionhwcfg2__data.html#9dcc70e2dba617cbc6c12189be5c1d6a">b</a>.<a class="code" href="unionhwcfg2__data.html#b6bfbfe650352dec82a02d15677fe88d">dynamic_fifo</a> &amp;&amp; params-&gt;<a class="code" href="structdwc__otg__core__params.html#8c169633d4a6f28e964cef9f597c6e03">enable_dynamic_fifo</a>) {
+<a name="l01248"></a>01248                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">DBG_CIL</a>, <span class="stringliteral">"Total FIFO Size=%d\n"</span>,
+<a name="l01249"></a>01249                             core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#cae59008a554cb7de24bd4f2afea7532">total_fifo_size</a>);
+<a name="l01250"></a>01250                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">DBG_CIL</a>, <span class="stringliteral">"Rx FIFO Size=%d\n"</span>,
+<a name="l01251"></a>01251                             params-&gt;<a class="code" href="structdwc__otg__core__params.html#2b2ab9c2fe16db70b136515b2e981f6b">host_rx_fifo_size</a>);
+<a name="l01252"></a>01252                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">DBG_CIL</a>, <span class="stringliteral">"NP Tx FIFO Size=%d\n"</span>,
+<a name="l01253"></a>01253                             params-&gt;<a class="code" href="structdwc__otg__core__params.html#6ff00857d99f72c0cfd6198cbcfab9a7">host_nperio_tx_fifo_size</a>);
+<a name="l01254"></a>01254                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">DBG_CIL</a>, <span class="stringliteral">"P Tx FIFO Size=%d\n"</span>,
+<a name="l01255"></a>01255                             params-&gt;<a class="code" href="structdwc__otg__core__params.html#5bc3cac5c81fd8d6fd291ca4b7de3e28">host_perio_tx_fifo_size</a>);
+<a name="l01256"></a>01256 
+<a name="l01257"></a>01257                 <span class="comment">/* Rx FIFO */</span>
+<a name="l01258"></a>01258                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">DBG_CIL</a>, <span class="stringliteral">"initial grxfsiz=%08x\n"</span>,
+<a name="l01259"></a>01259                             dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#b1a8cc07a9541c9a73e864579602b79b">grxfsiz</a>));
+<a name="l01260"></a>01260                 dwc_write_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#b1a8cc07a9541c9a73e864579602b79b">grxfsiz</a>,
+<a name="l01261"></a>01261                                 params-&gt;<a class="code" href="structdwc__otg__core__params.html#2b2ab9c2fe16db70b136515b2e981f6b">host_rx_fifo_size</a>);
+<a name="l01262"></a>01262                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">DBG_CIL</a>, <span class="stringliteral">"new grxfsiz=%08x\n"</span>,
+<a name="l01263"></a>01263                             dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#b1a8cc07a9541c9a73e864579602b79b">grxfsiz</a>));
+<a name="l01264"></a>01264 
+<a name="l01265"></a>01265                 <span class="comment">/* Non-periodic Tx FIFO */</span>
+<a name="l01266"></a>01266                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">DBG_CIL</a>, <span class="stringliteral">"initial gnptxfsiz=%08x\n"</span>,
+<a name="l01267"></a>01267                             dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#20fb70fe34a1a65d085b1d4e5f8d9106">gnptxfsiz</a>));
+<a name="l01268"></a>01268                 nptxfifosize.<a class="code" href="unionfifosize__data.html#4f0c71e88cc54c4efa4cd4ff43334c51">b</a>.<a class="code" href="unionfifosize__data.html#48c08d73da4d2d16d4320b93beb5ba8b">depth</a> = params-&gt;<a class="code" href="structdwc__otg__core__params.html#6ff00857d99f72c0cfd6198cbcfab9a7">host_nperio_tx_fifo_size</a>;
+<a name="l01269"></a>01269                 nptxfifosize.<a class="code" href="unionfifosize__data.html#4f0c71e88cc54c4efa4cd4ff43334c51">b</a>.<a class="code" href="unionfifosize__data.html#26d78332a532cf9c0337c89edbff5f1b">startaddr</a> = params-&gt;<a class="code" href="structdwc__otg__core__params.html#2b2ab9c2fe16db70b136515b2e981f6b">host_rx_fifo_size</a>;
+<a name="l01270"></a>01270                 dwc_write_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#20fb70fe34a1a65d085b1d4e5f8d9106">gnptxfsiz</a>, nptxfifosize.<a class="code" href="unionfifosize__data.html#937e01b91f0a60a5aa9f6a4eaf6ce661">d32</a>);
+<a name="l01271"></a>01271                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">DBG_CIL</a>, <span class="stringliteral">"new gnptxfsiz=%08x\n"</span>,
+<a name="l01272"></a>01272                             dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#20fb70fe34a1a65d085b1d4e5f8d9106">gnptxfsiz</a>));
+<a name="l01273"></a>01273 
+<a name="l01274"></a>01274                 <span class="comment">/* Periodic Tx FIFO */</span>
+<a name="l01275"></a>01275                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">DBG_CIL</a>, <span class="stringliteral">"initial hptxfsiz=%08x\n"</span>,
+<a name="l01276"></a>01276                             dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#94ae41f04d5a4244a8ebc23e51187e96">hptxfsiz</a>));
+<a name="l01277"></a>01277                 ptxfifosize.<a class="code" href="unionfifosize__data.html#4f0c71e88cc54c4efa4cd4ff43334c51">b</a>.<a class="code" href="unionfifosize__data.html#48c08d73da4d2d16d4320b93beb5ba8b">depth</a> = params-&gt;<a class="code" href="structdwc__otg__core__params.html#5bc3cac5c81fd8d6fd291ca4b7de3e28">host_perio_tx_fifo_size</a>;
+<a name="l01278"></a>01278                 ptxfifosize.<a class="code" href="unionfifosize__data.html#4f0c71e88cc54c4efa4cd4ff43334c51">b</a>.<a class="code" href="unionfifosize__data.html#26d78332a532cf9c0337c89edbff5f1b">startaddr</a> =
+<a name="l01279"></a>01279                     nptxfifosize.<a class="code" href="unionfifosize__data.html#4f0c71e88cc54c4efa4cd4ff43334c51">b</a>.<a class="code" href="unionfifosize__data.html#26d78332a532cf9c0337c89edbff5f1b">startaddr</a> + nptxfifosize.<a class="code" href="unionfifosize__data.html#4f0c71e88cc54c4efa4cd4ff43334c51">b</a>.<a class="code" href="unionfifosize__data.html#48c08d73da4d2d16d4320b93beb5ba8b">depth</a>;
+<a name="l01280"></a>01280                 dwc_write_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#94ae41f04d5a4244a8ebc23e51187e96">hptxfsiz</a>, ptxfifosize.<a class="code" href="unionfifosize__data.html#937e01b91f0a60a5aa9f6a4eaf6ce661">d32</a>);
+<a name="l01281"></a>01281                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">DBG_CIL</a>, <span class="stringliteral">"new hptxfsiz=%08x\n"</span>,
+<a name="l01282"></a>01282                             dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#94ae41f04d5a4244a8ebc23e51187e96">hptxfsiz</a>));
+<a name="l01283"></a>01283         }
+<a name="l01284"></a>01284 
+<a name="l01285"></a>01285         <span class="comment">/* Clear Host Set HNP Enable in the OTG Control Register */</span>
+<a name="l01286"></a>01286         gotgctl.<a class="code" href="uniongotgctl__data.html#212c81366266e906a188f4dbfadb6dd3">b</a>.<a class="code" href="uniongotgctl__data.html#7d45791d3622a59ff43ab248bbb1b2c1">hstsethnpen</a> = 1;
+<a name="l01287"></a>01287         dwc_modify_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#54034d00bb6b47ada4e0c0baa87cbd8a">gotgctl</a>, gotgctl.<a class="code" href="uniongotgctl__data.html#ebb591ab40ff41f0e06f03a795647d33">d32</a>, 0);
+<a name="l01288"></a>01288 
+<a name="l01289"></a>01289         <span class="comment">/* Make sure the FIFOs are flushed. */</span>
+<a name="l01290"></a>01290         <a class="code" href="dwc__otg__cil_8c.html#039e387cd0e0282727da3c5a36f4cdda">dwc_otg_flush_tx_fifo</a>(core_if, 0x10 <span class="comment">/* all Tx FIFOs */</span> );
+<a name="l01291"></a>01291         <a class="code" href="dwc__otg__cil_8c.html#fb275f0f9923cc30629fce5e3753025c">dwc_otg_flush_rx_fifo</a>(core_if);
+<a name="l01292"></a>01292 
+<a name="l01293"></a>01293         <span class="keywordflow">if</span>(!core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#36c5bcf00d0f776b5c9e84e5d8ae408d">dma_desc_enable</a>) {
+<a name="l01294"></a>01294                 <span class="comment">/* Flush out any leftover queued requests. */</span>
+<a name="l01295"></a>01295                 num_channels = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#c1b433c6965aa7d48f6ca6818c592039">host_channels</a>;
+<a name="l01296"></a>01296         
+<a name="l01297"></a>01297                 <span class="keywordflow">for</span> (i = 0; i &lt; num_channels; i++) {
+<a name="l01298"></a>01298                         hc_regs = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#7f7c107d4720641eb4141cd817211ac0">hc_regs</a>[i];
+<a name="l01299"></a>01299                         hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">hcchar</a>);
+<a name="l01300"></a>01300                         hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#994a5305780edb0c4fe159b6cc7b14ae">chen</a> = 0;
+<a name="l01301"></a>01301                         hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#73c9f7f3cc4036c72ef341d1d1d9c388">chdis</a> = 1;
+<a name="l01302"></a>01302                         hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#11f1b16e50f90806f90953bb979d4e77">epdir</a> = 0;
+<a name="l01303"></a>01303                         dwc_write_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">hcchar</a>, hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a>);
+<a name="l01304"></a>01304                 }
+<a name="l01305"></a>01305 
+<a name="l01306"></a>01306                 <span class="comment">/* Halt all channels to put them into a known state. */</span>
+<a name="l01307"></a>01307                 <span class="keywordflow">for</span> (i = 0; i &lt; num_channels; i++) {
+<a name="l01308"></a>01308                         <span class="keywordtype">int</span> count = 0;
+<a name="l01309"></a>01309                         hc_regs = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#7f7c107d4720641eb4141cd817211ac0">hc_regs</a>[i];
+<a name="l01310"></a>01310                         hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">hcchar</a>);
+<a name="l01311"></a>01311                         hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#994a5305780edb0c4fe159b6cc7b14ae">chen</a> = 1;
+<a name="l01312"></a>01312                         hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#73c9f7f3cc4036c72ef341d1d1d9c388">chdis</a> = 1;
+<a name="l01313"></a>01313                         hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#11f1b16e50f90806f90953bb979d4e77">epdir</a> = 0;
+<a name="l01314"></a>01314                         dwc_write_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">hcchar</a>, hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a>);
+<a name="l01315"></a>01315                         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"%s: Halt channel %d\n"</span>, __func__, i);
+<a name="l01316"></a>01316                         <span class="keywordflow">do</span> {
+<a name="l01317"></a>01317                                 hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">hcchar</a>);
+<a name="l01318"></a>01318                                 <span class="keywordflow">if</span> (++count &gt; 1000) {
+<a name="l01319"></a>01319                                         DWC_ERROR
+<a name="l01320"></a>01320                                             (<span class="stringliteral">"%s: Unable to clear halt on channel %d\n"</span>,
+<a name="l01321"></a>01321                                              __func__, i);
+<a name="l01322"></a>01322                                         <span class="keywordflow">break</span>;
+<a name="l01323"></a>01323                                 }
+<a name="l01324"></a>01324                                 dwc_udelay(1);
+<a name="l01325"></a>01325                         } <span class="keywordflow">while</span> (hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#994a5305780edb0c4fe159b6cc7b14ae">chen</a>);
+<a name="l01326"></a>01326                 }
+<a name="l01327"></a>01327         }
+<a name="l01328"></a>01328         
+<a name="l01329"></a>01329         <span class="comment">/* Turn on the vbus power. */</span>
+<a name="l01330"></a>01330         DWC_PRINTF(<span class="stringliteral">"Init: Port Power? op_state=%d\n"</span>, core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5a5c5c1cf8d870101cc1fffac56d88c0">op_state</a>);
+<a name="l01331"></a>01331         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5a5c5c1cf8d870101cc1fffac56d88c0">op_state</a> == <a class="code" href="dwc__otg__cil_8h.html#a0732b344b6571a4554968e4ee2214dd">A_HOST</a>) {
+<a name="l01332"></a>01332                 hprt0.<a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a> = <a class="code" href="dwc__otg__cil_8h.html#ce67da6af4023cffd25333d20992438e">dwc_otg_read_hprt0</a>(core_if);
+<a name="l01333"></a>01333                 DWC_PRINTF(<span class="stringliteral">"Init: Power Port (%d)\n"</span>, hprt0.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#010bd8fb208ef4eeaa288b28f8f8c3a4">prtpwr</a>);
+<a name="l01334"></a>01334                 <span class="keywordflow">if</span> (hprt0.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#010bd8fb208ef4eeaa288b28f8f8c3a4">prtpwr</a> == 0) {
+<a name="l01335"></a>01335                         hprt0.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#010bd8fb208ef4eeaa288b28f8f8c3a4">prtpwr</a> = 1;
+<a name="l01336"></a>01336                         dwc_write_reg32(host_if-&gt;<a class="code" href="structdwc__otg__host__if.html#dc8fe33e0bb3829cafa884d5fc603c4d">hprt0</a>, hprt0.<a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a>);
+<a name="l01337"></a>01337                 }
+<a name="l01338"></a>01338         }
+<a name="l01339"></a>01339 
+<a name="l01340"></a>01340         <a class="code" href="dwc__otg__cil_8c.html#373701240c023fda03eed98cf093df74">dwc_otg_enable_host_interrupts</a>(core_if);
+<a name="l01341"></a>01341 }
+<a name="l01342"></a>01342 
+<a name="l01352"></a><a class="code" href="dwc__otg__cil_8h.html#f2f5f8703a3292608f1cb756d0d5c4ea">01352</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#7b04d5b3b31c79c73d577cfbb231998c">dwc_otg_hc_init</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, <a class="code" href="structdwc__hc.html">dwc_hc_t</a> * hc)
+<a name="l01353"></a>01353 {
+<a name="l01354"></a>01354         uint32_t intr_enable;
+<a name="l01355"></a>01355         <a class="code" href="unionhcintmsk__data.html">hcintmsk_data_t</a> hc_intr_mask;
+<a name="l01356"></a>01356         <a class="code" href="uniongintmsk__data.html">gintmsk_data_t</a> gintmsk = {.d32 = 0 };
+<a name="l01357"></a>01357         <a class="code" href="unionhcchar__data.html">hcchar_data_t</a> hcchar;
+<a name="l01358"></a>01358         <a class="code" href="unionhcsplt__data.html">hcsplt_data_t</a> hcsplt;
+<a name="l01359"></a>01359 
+<a name="l01360"></a>01360         uint8_t hc_num = hc-&gt;<a class="code" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">hc_num</a>;
+<a name="l01361"></a>01361         <a class="code" href="structdwc__otg__host__if.html">dwc_otg_host_if_t</a> *host_if = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>;
+<a name="l01362"></a>01362         <a class="code" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *hc_regs = host_if-&gt;<a class="code" href="structdwc__otg__host__if.html#7f7c107d4720641eb4141cd817211ac0">hc_regs</a>[hc_num];
+<a name="l01363"></a>01363 
+<a name="l01364"></a>01364         <span class="comment">/* Clear old interrupt conditions for this host channel. */</span>
+<a name="l01365"></a>01365         hc_intr_mask.<a class="code" href="unionhcintmsk__data.html#8868299fcc762e005b7f0bf67e5fbe30">d32</a> = 0xFFFFFFFF;
+<a name="l01366"></a>01366         hc_intr_mask.<a class="code" href="unionhcintmsk__data.html#6835f55069c94947b580c8f01f64a075">b</a>.<a class="code" href="unionhcintmsk__data.html#dcb3b9df0efa5f60db95dd09a7e4a083">reserved14_31</a> = 0;
+<a name="l01367"></a>01367         dwc_write_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#0dfd5bae537d58e13788508dc719480d">hcint</a>, hc_intr_mask.<a class="code" href="unionhcintmsk__data.html#8868299fcc762e005b7f0bf67e5fbe30">d32</a>);
+<a name="l01368"></a>01368 
+<a name="l01369"></a>01369         <span class="comment">/* Enable channel interrupts required for this transfer. */</span>
+<a name="l01370"></a>01370         hc_intr_mask.<a class="code" href="unionhcintmsk__data.html#8868299fcc762e005b7f0bf67e5fbe30">d32</a> = 0;
+<a name="l01371"></a>01371         hc_intr_mask.<a class="code" href="unionhcintmsk__data.html#6835f55069c94947b580c8f01f64a075">b</a>.<a class="code" href="unionhcintmsk__data.html#2549a84a06f4f6a7ad6fed50fcf7b068">chhltd</a> = 1;
+<a name="l01372"></a>01372         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a>) {
+<a name="l01373"></a>01373                 <span class="comment">/* For Descriptor DMA mode core halts the channel on AHB error. Interrupt is not required */</span>
+<a name="l01374"></a>01374                 <span class="keywordflow">if</span> (!core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a>)
+<a name="l01375"></a>01375                         hc_intr_mask.<a class="code" href="unionhcintmsk__data.html#6835f55069c94947b580c8f01f64a075">b</a>.<a class="code" href="unionhcintmsk__data.html#bd9e228b6cb8e60cdbefd4bb57bdcc33">ahberr</a> = 1;
+<a name="l01376"></a>01376                 <span class="keywordflow">else</span> {
+<a name="l01377"></a>01377                         <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#e6169fbc92e4d79686097742ad646f5c">ep_type</a> == <a class="code" href="dwc__otg__cil_8h.html#152a3a5e1433bd2197672f0b5105e7a4">DWC_OTG_EP_TYPE_ISOC</a>) 
+<a name="l01378"></a>01378                                 hc_intr_mask.<a class="code" href="unionhcintmsk__data.html#6835f55069c94947b580c8f01f64a075">b</a>.<a class="code" href="unionhcintmsk__data.html#4983a78156d96d9a0c16ca8ea2b09106">xfercompl</a> = 1;
+<a name="l01379"></a>01379                 }
+<a name="l01380"></a>01380                 
+<a name="l01381"></a>01381                 <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#ab0855754930fdc74978fa71772982ed">error_state</a> &amp;&amp; !hc-&gt;<a class="code" href="structdwc__hc.html#4365ef67d517a621a626ac5392545c6d">do_split</a> &amp;&amp;
+<a name="l01382"></a>01382                     hc-&gt;<a class="code" href="structdwc__hc.html#e6169fbc92e4d79686097742ad646f5c">ep_type</a> != <a class="code" href="dwc__otg__cil_8h.html#152a3a5e1433bd2197672f0b5105e7a4">DWC_OTG_EP_TYPE_ISOC</a>) {
+<a name="l01383"></a>01383                         hc_intr_mask.<a class="code" href="unionhcintmsk__data.html#6835f55069c94947b580c8f01f64a075">b</a>.<a class="code" href="unionhcintmsk__data.html#8d3388818a6dc098a1e1c64147d1ced9">ack</a> = 1;
+<a name="l01384"></a>01384                         <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#c5088d431f5efc382121f201f5d571aa">ep_is_in</a>) {
+<a name="l01385"></a>01385                                 hc_intr_mask.<a class="code" href="unionhcintmsk__data.html#6835f55069c94947b580c8f01f64a075">b</a>.<a class="code" href="unionhcintmsk__data.html#60bbf3878314aad41055137e348cc01d">datatglerr</a> = 1;
+<a name="l01386"></a>01386                                 <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#e6169fbc92e4d79686097742ad646f5c">ep_type</a> != <a class="code" href="dwc__otg__cil_8h.html#1401d1264f88530232cf51ab31cc5347">DWC_OTG_EP_TYPE_INTR</a>) {
+<a name="l01387"></a>01387                                         hc_intr_mask.<a class="code" href="unionhcintmsk__data.html#6835f55069c94947b580c8f01f64a075">b</a>.<a class="code" href="unionhcintmsk__data.html#32ae7d92d0eb93ced42ac3773ddc3a2f">nak</a> = 1;
+<a name="l01388"></a>01388                                 }
+<a name="l01389"></a>01389                         }
+<a name="l01390"></a>01390                 }
+<a name="l01391"></a>01391         } <span class="keywordflow">else</span> {
+<a name="l01392"></a>01392                 <span class="keywordflow">switch</span> (hc-&gt;<a class="code" href="structdwc__hc.html#e6169fbc92e4d79686097742ad646f5c">ep_type</a>) {
+<a name="l01393"></a>01393                 <span class="keywordflow">case</span> <a class="code" href="dwc__otg__cil_8h.html#64e5cd756330f5adab79b25cc8067bdc">DWC_OTG_EP_TYPE_CONTROL</a>:
+<a name="l01394"></a>01394                 <span class="keywordflow">case</span> <a class="code" href="dwc__otg__cil_8h.html#9b079858cda0b917316ad9161b3881e0">DWC_OTG_EP_TYPE_BULK</a>:
+<a name="l01395"></a>01395                         hc_intr_mask.<a class="code" href="unionhcintmsk__data.html#6835f55069c94947b580c8f01f64a075">b</a>.<a class="code" href="unionhcintmsk__data.html#4983a78156d96d9a0c16ca8ea2b09106">xfercompl</a> = 1;
+<a name="l01396"></a>01396                         hc_intr_mask.<a class="code" href="unionhcintmsk__data.html#6835f55069c94947b580c8f01f64a075">b</a>.<a class="code" href="unionhcintmsk__data.html#94dc82e231d28d16d21238809cb88f78">stall</a> = 1;
+<a name="l01397"></a>01397                         hc_intr_mask.<a class="code" href="unionhcintmsk__data.html#6835f55069c94947b580c8f01f64a075">b</a>.<a class="code" href="unionhcintmsk__data.html#29686b2c0b9502932327915d690a45d5">xacterr</a> = 1;
+<a name="l01398"></a>01398                         hc_intr_mask.<a class="code" href="unionhcintmsk__data.html#6835f55069c94947b580c8f01f64a075">b</a>.<a class="code" href="unionhcintmsk__data.html#60bbf3878314aad41055137e348cc01d">datatglerr</a> = 1;
+<a name="l01399"></a>01399                         <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#c5088d431f5efc382121f201f5d571aa">ep_is_in</a>) {
+<a name="l01400"></a>01400                                 hc_intr_mask.<a class="code" href="unionhcintmsk__data.html#6835f55069c94947b580c8f01f64a075">b</a>.<a class="code" href="unionhcintmsk__data.html#5052c8737755083ee10105f36e839590">bblerr</a> = 1;
+<a name="l01401"></a>01401                         } <span class="keywordflow">else</span> {
+<a name="l01402"></a>01402                                 hc_intr_mask.<a class="code" href="unionhcintmsk__data.html#6835f55069c94947b580c8f01f64a075">b</a>.<a class="code" href="unionhcintmsk__data.html#32ae7d92d0eb93ced42ac3773ddc3a2f">nak</a> = 1;
+<a name="l01403"></a>01403                                 hc_intr_mask.<a class="code" href="unionhcintmsk__data.html#6835f55069c94947b580c8f01f64a075">b</a>.<a class="code" href="unionhcintmsk__data.html#4274f9b730db0e390e5f3be4247ee45c">nyet</a> = 1;
+<a name="l01404"></a>01404                                 <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#ae7184275dbb23b3a5d2af20ed224920">do_ping</a>) {
+<a name="l01405"></a>01405                                         hc_intr_mask.<a class="code" href="unionhcintmsk__data.html#6835f55069c94947b580c8f01f64a075">b</a>.<a class="code" href="unionhcintmsk__data.html#8d3388818a6dc098a1e1c64147d1ced9">ack</a> = 1;
+<a name="l01406"></a>01406                                 }
+<a name="l01407"></a>01407                         }
+<a name="l01408"></a>01408 
+<a name="l01409"></a>01409                         <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#4365ef67d517a621a626ac5392545c6d">do_split</a>) {
+<a name="l01410"></a>01410                                 hc_intr_mask.<a class="code" href="unionhcintmsk__data.html#6835f55069c94947b580c8f01f64a075">b</a>.<a class="code" href="unionhcintmsk__data.html#32ae7d92d0eb93ced42ac3773ddc3a2f">nak</a> = 1;
+<a name="l01411"></a>01411                                 <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#21e00df6fb9a555975879526118d599e">complete_split</a>) {
+<a name="l01412"></a>01412                                         hc_intr_mask.<a class="code" href="unionhcintmsk__data.html#6835f55069c94947b580c8f01f64a075">b</a>.<a class="code" href="unionhcintmsk__data.html#4274f9b730db0e390e5f3be4247ee45c">nyet</a> = 1;
+<a name="l01413"></a>01413                                 } <span class="keywordflow">else</span> {
+<a name="l01414"></a>01414                                         hc_intr_mask.<a class="code" href="unionhcintmsk__data.html#6835f55069c94947b580c8f01f64a075">b</a>.<a class="code" href="unionhcintmsk__data.html#8d3388818a6dc098a1e1c64147d1ced9">ack</a> = 1;
+<a name="l01415"></a>01415                                 }
+<a name="l01416"></a>01416                         }
+<a name="l01417"></a>01417 
+<a name="l01418"></a>01418                         <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#ab0855754930fdc74978fa71772982ed">error_state</a>) {
+<a name="l01419"></a>01419                                 hc_intr_mask.<a class="code" href="unionhcintmsk__data.html#6835f55069c94947b580c8f01f64a075">b</a>.<a class="code" href="unionhcintmsk__data.html#8d3388818a6dc098a1e1c64147d1ced9">ack</a> = 1;
+<a name="l01420"></a>01420                         }
+<a name="l01421"></a>01421                         <span class="keywordflow">break</span>;
+<a name="l01422"></a>01422                 <span class="keywordflow">case</span> <a class="code" href="dwc__otg__cil_8h.html#1401d1264f88530232cf51ab31cc5347">DWC_OTG_EP_TYPE_INTR</a>:
+<a name="l01423"></a>01423                         hc_intr_mask.<a class="code" href="unionhcintmsk__data.html#6835f55069c94947b580c8f01f64a075">b</a>.<a class="code" href="unionhcintmsk__data.html#4983a78156d96d9a0c16ca8ea2b09106">xfercompl</a> = 1;
+<a name="l01424"></a>01424                         hc_intr_mask.<a class="code" href="unionhcintmsk__data.html#6835f55069c94947b580c8f01f64a075">b</a>.<a class="code" href="unionhcintmsk__data.html#32ae7d92d0eb93ced42ac3773ddc3a2f">nak</a> = 1;
+<a name="l01425"></a>01425                         hc_intr_mask.<a class="code" href="unionhcintmsk__data.html#6835f55069c94947b580c8f01f64a075">b</a>.<a class="code" href="unionhcintmsk__data.html#94dc82e231d28d16d21238809cb88f78">stall</a> = 1;
+<a name="l01426"></a>01426                         hc_intr_mask.<a class="code" href="unionhcintmsk__data.html#6835f55069c94947b580c8f01f64a075">b</a>.<a class="code" href="unionhcintmsk__data.html#29686b2c0b9502932327915d690a45d5">xacterr</a> = 1;
+<a name="l01427"></a>01427                         hc_intr_mask.<a class="code" href="unionhcintmsk__data.html#6835f55069c94947b580c8f01f64a075">b</a>.<a class="code" href="unionhcintmsk__data.html#60bbf3878314aad41055137e348cc01d">datatglerr</a> = 1;
+<a name="l01428"></a>01428                         hc_intr_mask.<a class="code" href="unionhcintmsk__data.html#6835f55069c94947b580c8f01f64a075">b</a>.<a class="code" href="unionhcintmsk__data.html#2ba9f8dc5e946b28ac4169f75364e182">frmovrun</a> = 1;
+<a name="l01429"></a>01429 
+<a name="l01430"></a>01430                         <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#c5088d431f5efc382121f201f5d571aa">ep_is_in</a>) {
+<a name="l01431"></a>01431                                 hc_intr_mask.<a class="code" href="unionhcintmsk__data.html#6835f55069c94947b580c8f01f64a075">b</a>.<a class="code" href="unionhcintmsk__data.html#5052c8737755083ee10105f36e839590">bblerr</a> = 1;
+<a name="l01432"></a>01432                         }
+<a name="l01433"></a>01433                         <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#ab0855754930fdc74978fa71772982ed">error_state</a>) {
+<a name="l01434"></a>01434                                 hc_intr_mask.<a class="code" href="unionhcintmsk__data.html#6835f55069c94947b580c8f01f64a075">b</a>.<a class="code" href="unionhcintmsk__data.html#8d3388818a6dc098a1e1c64147d1ced9">ack</a> = 1;
+<a name="l01435"></a>01435                         }
+<a name="l01436"></a>01436                         <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#4365ef67d517a621a626ac5392545c6d">do_split</a>) {
+<a name="l01437"></a>01437                                 <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#21e00df6fb9a555975879526118d599e">complete_split</a>) {
+<a name="l01438"></a>01438                                         hc_intr_mask.<a class="code" href="unionhcintmsk__data.html#6835f55069c94947b580c8f01f64a075">b</a>.<a class="code" href="unionhcintmsk__data.html#4274f9b730db0e390e5f3be4247ee45c">nyet</a> = 1;
+<a name="l01439"></a>01439                                 } <span class="keywordflow">else</span> {
+<a name="l01440"></a>01440                                         hc_intr_mask.<a class="code" href="unionhcintmsk__data.html#6835f55069c94947b580c8f01f64a075">b</a>.<a class="code" href="unionhcintmsk__data.html#8d3388818a6dc098a1e1c64147d1ced9">ack</a> = 1;
+<a name="l01441"></a>01441                                 }
+<a name="l01442"></a>01442                         }
+<a name="l01443"></a>01443                         <span class="keywordflow">break</span>;
+<a name="l01444"></a>01444                 <span class="keywordflow">case</span> <a class="code" href="dwc__otg__cil_8h.html#152a3a5e1433bd2197672f0b5105e7a4">DWC_OTG_EP_TYPE_ISOC</a>:
+<a name="l01445"></a>01445                         hc_intr_mask.<a class="code" href="unionhcintmsk__data.html#6835f55069c94947b580c8f01f64a075">b</a>.<a class="code" href="unionhcintmsk__data.html#4983a78156d96d9a0c16ca8ea2b09106">xfercompl</a> = 1;
+<a name="l01446"></a>01446                         hc_intr_mask.<a class="code" href="unionhcintmsk__data.html#6835f55069c94947b580c8f01f64a075">b</a>.<a class="code" href="unionhcintmsk__data.html#2ba9f8dc5e946b28ac4169f75364e182">frmovrun</a> = 1;
+<a name="l01447"></a>01447                         hc_intr_mask.<a class="code" href="unionhcintmsk__data.html#6835f55069c94947b580c8f01f64a075">b</a>.<a class="code" href="unionhcintmsk__data.html#8d3388818a6dc098a1e1c64147d1ced9">ack</a> = 1;
+<a name="l01448"></a>01448 
+<a name="l01449"></a>01449                         <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#c5088d431f5efc382121f201f5d571aa">ep_is_in</a>) {
+<a name="l01450"></a>01450                                 hc_intr_mask.<a class="code" href="unionhcintmsk__data.html#6835f55069c94947b580c8f01f64a075">b</a>.<a class="code" href="unionhcintmsk__data.html#29686b2c0b9502932327915d690a45d5">xacterr</a> = 1;
+<a name="l01451"></a>01451                                 hc_intr_mask.<a class="code" href="unionhcintmsk__data.html#6835f55069c94947b580c8f01f64a075">b</a>.<a class="code" href="unionhcintmsk__data.html#5052c8737755083ee10105f36e839590">bblerr</a> = 1;
+<a name="l01452"></a>01452                         }
+<a name="l01453"></a>01453                         <span class="keywordflow">break</span>;
+<a name="l01454"></a>01454                 }
+<a name="l01455"></a>01455         }
+<a name="l01456"></a>01456         dwc_write_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#830aa61c1d4326823662168ea7359205">hcintmsk</a>, hc_intr_mask.<a class="code" href="unionhcintmsk__data.html#8868299fcc762e005b7f0bf67e5fbe30">d32</a>);
+<a name="l01457"></a>01457 
+<a name="l01458"></a>01458         <span class="comment">/* Enable the top level host channel interrupt. */</span>
+<a name="l01459"></a>01459         intr_enable = (1 &lt;&lt; hc_num);
+<a name="l01460"></a>01460         dwc_modify_reg32(&amp;host_if-&gt;<a class="code" href="structdwc__otg__host__if.html#ff9692c2e10ca2bc7e24f981f25179c2">host_global_regs</a>-&gt;<a class="code" href="structdwc__otg__host__global__regs.html#317f5059d4c2dc91da041f5c0a4819fc">haintmsk</a>, 0, intr_enable);
+<a name="l01461"></a>01461 
+<a name="l01462"></a>01462         <span class="comment">/* Make sure host channel interrupts are enabled. */</span>
+<a name="l01463"></a>01463         gintmsk.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#3a4c193d8ff48291809dcd3ccb7c0585">hcintr</a> = 1;
+<a name="l01464"></a>01464         dwc_modify_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#48827c76da2c6b18f369e2f2483cc4b6">gintmsk</a>, 0, gintmsk.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a>);
+<a name="l01465"></a>01465 
+<a name="l01466"></a>01466         <span class="comment">/*</span>
+<a name="l01467"></a>01467 <span class="comment">         * Program the HCCHARn register with the endpoint characteristics for</span>
+<a name="l01468"></a>01468 <span class="comment">         * the current transfer.</span>
+<a name="l01469"></a>01469 <span class="comment">         */</span>
+<a name="l01470"></a>01470         hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a> = 0;
+<a name="l01471"></a>01471         hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#19326a679cb3507cf294d229834252a1">devaddr</a> = hc-&gt;<a class="code" href="structdwc__hc.html#b2c7e8baff70104375f4916e9b76cef7">dev_addr</a>;
+<a name="l01472"></a>01472         hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#1597f36b85006e643aaf6f4d503bebc9">epnum</a> = hc-&gt;<a class="code" href="structdwc__hc.html#70b755f76a00b81679aeb1e0db8b2e60">ep_num</a>;
+<a name="l01473"></a>01473         hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#11f1b16e50f90806f90953bb979d4e77">epdir</a> = hc-&gt;<a class="code" href="structdwc__hc.html#c5088d431f5efc382121f201f5d571aa">ep_is_in</a>;
+<a name="l01474"></a>01474         hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#ca469c8bda88761c4d9ef74b811d71f4">lspddev</a> = (hc-&gt;<a class="code" href="structdwc__hc.html#570b78178975193edb921af1ef36d37b">speed</a> == <a class="code" href="dwc__otg__cil_8h.html#1a25260b2e1a06850c26f7b7e5128f31">DWC_OTG_EP_SPEED_LOW</a>);
+<a name="l01475"></a>01475         hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#df4deee52d932ab29e5d077cde77cbfc">eptype</a> = hc-&gt;<a class="code" href="structdwc__hc.html#e6169fbc92e4d79686097742ad646f5c">ep_type</a>;
+<a name="l01476"></a>01476         hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#47d11a5e62f69534d8ac0606aa7ffe7d">mps</a> = hc-&gt;<a class="code" href="structdwc__hc.html#bd88f02eb286ba01d8d1b049e8975ccb">max_packet</a>;
+<a name="l01477"></a>01477 
+<a name="l01478"></a>01478         dwc_write_reg32(&amp;host_if-&gt;<a class="code" href="structdwc__otg__host__if.html#7f7c107d4720641eb4141cd817211ac0">hc_regs</a>[hc_num]-&gt;<a class="code" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">hcchar</a>, hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a>);
+<a name="l01479"></a>01479 
+<a name="l01480"></a>01480         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"%s: Channel %d\n"</span>, __func__, hc-&gt;<a class="code" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">hc_num</a>);
+<a name="l01481"></a>01481         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"  Dev Addr: %d\n"</span>, hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#19326a679cb3507cf294d229834252a1">devaddr</a>);
+<a name="l01482"></a>01482         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"  Ep Num: %d\n"</span>, hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#1597f36b85006e643aaf6f4d503bebc9">epnum</a>);
+<a name="l01483"></a>01483         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"  Is In: %d\n"</span>, hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#11f1b16e50f90806f90953bb979d4e77">epdir</a>);
+<a name="l01484"></a>01484         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"  Is Low Speed: %d\n"</span>, hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#ca469c8bda88761c4d9ef74b811d71f4">lspddev</a>);
+<a name="l01485"></a>01485         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"  Ep Type: %d\n"</span>, hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#df4deee52d932ab29e5d077cde77cbfc">eptype</a>);
+<a name="l01486"></a>01486         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"  Max Pkt: %d\n"</span>, hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#47d11a5e62f69534d8ac0606aa7ffe7d">mps</a>);
+<a name="l01487"></a>01487         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"  Multi Cnt: %d\n"</span>, hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#9c0f515663251779e4960ec5613ce6fe">multicnt</a>);
+<a name="l01488"></a>01488 
+<a name="l01489"></a>01489         <span class="comment">/*</span>
+<a name="l01490"></a>01490 <span class="comment">         * Program the HCSPLIT register for SPLITs</span>
+<a name="l01491"></a>01491 <span class="comment">         */</span>
+<a name="l01492"></a>01492         hcsplt.<a class="code" href="unionhcsplt__data.html#0cd235b445ff681b846f5dccf24fd644">d32</a> = 0;
+<a name="l01493"></a>01493         <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#4365ef67d517a621a626ac5392545c6d">do_split</a>) {
+<a name="l01494"></a>01494                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"Programming HC %d with split --&gt; %s\n"</span>,
+<a name="l01495"></a>01495                             hc-&gt;<a class="code" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">hc_num</a>,
+<a name="l01496"></a>01496                             hc-&gt;<a class="code" href="structdwc__hc.html#21e00df6fb9a555975879526118d599e">complete_split</a> ? <span class="stringliteral">"CSPLIT"</span> : <span class="stringliteral">"SSPLIT"</span>);
+<a name="l01497"></a>01497                 hcsplt.<a class="code" href="unionhcsplt__data.html#b8bafe40eee4a9f598659d254be836e1">b</a>.<a class="code" href="unionhcsplt__data.html#0a4855eb44ec93ec47dcc218a8703e94">compsplt</a> = hc-&gt;<a class="code" href="structdwc__hc.html#21e00df6fb9a555975879526118d599e">complete_split</a>;
+<a name="l01498"></a>01498                 hcsplt.<a class="code" href="unionhcsplt__data.html#b8bafe40eee4a9f598659d254be836e1">b</a>.<a class="code" href="unionhcsplt__data.html#68e7b96ce2ca96c96f40b4f95c679a11">xactpos</a> = hc-&gt;<a class="code" href="structdwc__hc.html#3cde49a724756e16eb11a027360b2d4b">xact_pos</a>;
+<a name="l01499"></a>01499                 hcsplt.<a class="code" href="unionhcsplt__data.html#b8bafe40eee4a9f598659d254be836e1">b</a>.<a class="code" href="unionhcsplt__data.html#2843e0a36458a9a4c2d5ed6da3027b36">hubaddr</a> = hc-&gt;<a class="code" href="structdwc__hc.html#19d0302b6e3769eada2466b8e5e0dd91">hub_addr</a>;
+<a name="l01500"></a>01500                 hcsplt.<a class="code" href="unionhcsplt__data.html#b8bafe40eee4a9f598659d254be836e1">b</a>.<a class="code" href="unionhcsplt__data.html#e1c0812d6f655ea9915a6152c9f16cd6">prtaddr</a> = hc-&gt;<a class="code" href="structdwc__hc.html#9f597e05c37d7292f4c0d965c67ee3dd">port_addr</a>;
+<a name="l01501"></a>01501                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"   comp split %d\n"</span>, hc-&gt;<a class="code" href="structdwc__hc.html#21e00df6fb9a555975879526118d599e">complete_split</a>);
+<a name="l01502"></a>01502                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"   xact pos %d\n"</span>, hc-&gt;<a class="code" href="structdwc__hc.html#3cde49a724756e16eb11a027360b2d4b">xact_pos</a>);
+<a name="l01503"></a>01503                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"   hub addr %d\n"</span>, hc-&gt;<a class="code" href="structdwc__hc.html#19d0302b6e3769eada2466b8e5e0dd91">hub_addr</a>);
+<a name="l01504"></a>01504                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"   port addr %d\n"</span>, hc-&gt;<a class="code" href="structdwc__hc.html#9f597e05c37d7292f4c0d965c67ee3dd">port_addr</a>);
+<a name="l01505"></a>01505                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"   is_in %d\n"</span>, hc-&gt;<a class="code" href="structdwc__hc.html#c5088d431f5efc382121f201f5d571aa">ep_is_in</a>);
+<a name="l01506"></a>01506                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"   Max Pkt: %d\n"</span>, hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#47d11a5e62f69534d8ac0606aa7ffe7d">mps</a>);
+<a name="l01507"></a>01507                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"   xferlen: %d\n"</span>, hc-&gt;<a class="code" href="structdwc__hc.html#ce32fe93214f1686896e924fbf61cac7">xfer_len</a>);
+<a name="l01508"></a>01508         }
+<a name="l01509"></a>01509         dwc_write_reg32(&amp;host_if-&gt;<a class="code" href="structdwc__otg__host__if.html#7f7c107d4720641eb4141cd817211ac0">hc_regs</a>[hc_num]-&gt;<a class="code" href="structdwc__otg__hc__regs.html#149053001a9ee21b692afde531a814de">hcsplt</a>, hcsplt.<a class="code" href="unionhcsplt__data.html#0cd235b445ff681b846f5dccf24fd644">d32</a>);
+<a name="l01510"></a>01510 
+<a name="l01511"></a>01511 }
+<a name="l01512"></a>01512 
+<a name="l01540"></a><a class="code" href="dwc__otg__cil_8h.html#ec2bad3cbf8baa9b4932d84719e952e1">01540</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#de044bf6b96c1bac92259a447ae85c0f">dwc_otg_hc_halt</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if,
+<a name="l01541"></a>01541                      <a class="code" href="structdwc__hc.html">dwc_hc_t</a> * hc, dwc_otg_halt_status_e halt_status)
+<a name="l01542"></a>01542 {
+<a name="l01543"></a>01543         <a class="code" href="uniongnptxsts__data.html">gnptxsts_data_t</a> nptxsts;
+<a name="l01544"></a>01544         <a class="code" href="unionhptxsts__data.html">hptxsts_data_t</a> hptxsts;
+<a name="l01545"></a>01545         <a class="code" href="unionhcchar__data.html">hcchar_data_t</a> hcchar;
+<a name="l01546"></a>01546         <a class="code" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *hc_regs;
+<a name="l01547"></a>01547         <a class="code" href="structdwc__otg__core__global__regs.html">dwc_otg_core_global_regs_t</a> *global_regs;
+<a name="l01548"></a>01548         <a class="code" href="structdwc__otg__host__global__regs.html">dwc_otg_host_global_regs_t</a> *host_global_regs;
+<a name="l01549"></a>01549 
+<a name="l01550"></a>01550         hc_regs = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#7f7c107d4720641eb4141cd817211ac0">hc_regs</a>[hc-&gt;<a class="code" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">hc_num</a>];
+<a name="l01551"></a>01551         global_regs = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>;
+<a name="l01552"></a>01552         host_global_regs = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#ff9692c2e10ca2bc7e24f981f25179c2">host_global_regs</a>;
+<a name="l01553"></a>01553 
+<a name="l01554"></a>01554         DWC_ASSERT(!(halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS),
+<a name="l01555"></a>01555                    <span class="stringliteral">"halt_status = %d\n"</span>, halt_status);
+<a name="l01556"></a>01556 
+<a name="l01557"></a>01557         <span class="keywordflow">if</span> (halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
+<a name="l01558"></a>01558             halt_status == DWC_OTG_HC_XFER_AHB_ERR) {
+<a name="l01559"></a>01559                 <span class="comment">/*</span>
+<a name="l01560"></a>01560 <span class="comment">                 * Disable all channel interrupts except Ch Halted. The QTD</span>
+<a name="l01561"></a>01561 <span class="comment">                 * and QH state associated with this transfer has been cleared</span>
+<a name="l01562"></a>01562 <span class="comment">                 * (in the case of URB_DEQUEUE), so the channel needs to be</span>
+<a name="l01563"></a>01563 <span class="comment">                 * shut down carefully to prevent crashes.</span>
+<a name="l01564"></a>01564 <span class="comment">                 */</span>
+<a name="l01565"></a>01565                 <a class="code" href="unionhcintmsk__data.html">hcintmsk_data_t</a> hcintmsk;
+<a name="l01566"></a>01566                 hcintmsk.<a class="code" href="unionhcintmsk__data.html#8868299fcc762e005b7f0bf67e5fbe30">d32</a> = 0;
+<a name="l01567"></a>01567                 hcintmsk.<a class="code" href="unionhcintmsk__data.html#6835f55069c94947b580c8f01f64a075">b</a>.<a class="code" href="unionhcintmsk__data.html#2549a84a06f4f6a7ad6fed50fcf7b068">chhltd</a> = 1;
+<a name="l01568"></a>01568                 dwc_write_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#830aa61c1d4326823662168ea7359205">hcintmsk</a>, hcintmsk.<a class="code" href="unionhcintmsk__data.html#8868299fcc762e005b7f0bf67e5fbe30">d32</a>);
+<a name="l01569"></a>01569 
+<a name="l01570"></a>01570                 <span class="comment">/*</span>
+<a name="l01571"></a>01571 <span class="comment">                 * Make sure no other interrupts besides halt are currently</span>
+<a name="l01572"></a>01572 <span class="comment">                 * pending. Handling another interrupt could cause a crash due</span>
+<a name="l01573"></a>01573 <span class="comment">                 * to the QTD and QH state.</span>
+<a name="l01574"></a>01574 <span class="comment">                 */</span>
+<a name="l01575"></a>01575                 dwc_write_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#0dfd5bae537d58e13788508dc719480d">hcint</a>, ~hcintmsk.<a class="code" href="unionhcintmsk__data.html#8868299fcc762e005b7f0bf67e5fbe30">d32</a>);
+<a name="l01576"></a>01576 
+<a name="l01577"></a>01577                 <span class="comment">/*</span>
+<a name="l01578"></a>01578 <span class="comment">                 * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR</span>
+<a name="l01579"></a>01579 <span class="comment">                 * even if the channel was already halted for some other</span>
+<a name="l01580"></a>01580 <span class="comment">                 * reason.</span>
+<a name="l01581"></a>01581 <span class="comment">                 */</span>
+<a name="l01582"></a>01582                 hc-&gt;<a class="code" href="structdwc__hc.html#07eca0fa02105ddaa1719387f5558b23">halt_status</a> = halt_status;
+<a name="l01583"></a>01583 
+<a name="l01584"></a>01584                 hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">hcchar</a>);
+<a name="l01585"></a>01585                 <span class="keywordflow">if</span> (hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#994a5305780edb0c4fe159b6cc7b14ae">chen</a> == 0) {
+<a name="l01586"></a>01586                         <span class="comment">/*</span>
+<a name="l01587"></a>01587 <span class="comment">                         * The channel is either already halted or it hasn't</span>
+<a name="l01588"></a>01588 <span class="comment">                         * started yet. In DMA mode, the transfer may halt if</span>
+<a name="l01589"></a>01589 <span class="comment">                         * it finishes normally or a condition occurs that</span>
+<a name="l01590"></a>01590 <span class="comment">                         * requires driver intervention. Don't want to halt</span>
+<a name="l01591"></a>01591 <span class="comment">                         * the channel again. In either Slave or DMA mode,</span>
+<a name="l01592"></a>01592 <span class="comment">                         * it's possible that the transfer has been assigned</span>
+<a name="l01593"></a>01593 <span class="comment">                         * to a channel, but not started yet when an URB is</span>
+<a name="l01594"></a>01594 <span class="comment">                         * dequeued. Don't want to halt a channel that hasn't</span>
+<a name="l01595"></a>01595 <span class="comment">                         * started yet.</span>
+<a name="l01596"></a>01596 <span class="comment">                         */</span>
+<a name="l01597"></a>01597                         <span class="keywordflow">return</span>;
+<a name="l01598"></a>01598                 }
+<a name="l01599"></a>01599         }
+<a name="l01600"></a>01600         <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#2177dcde6dbb17b6bc7d0fb34e8ec95a">halt_pending</a>) {
+<a name="l01601"></a>01601                 <span class="comment">/*</span>
+<a name="l01602"></a>01602 <span class="comment">                 * A halt has already been issued for this channel. This might</span>
+<a name="l01603"></a>01603 <span class="comment">                 * happen when a transfer is aborted by a higher level in</span>
+<a name="l01604"></a>01604 <span class="comment">                 * the stack.</span>
+<a name="l01605"></a>01605 <span class="comment">                 */</span>
+<a name="l01606"></a>01606 <span class="preprocessor">#ifdef DEBUG</span>
+<a name="l01607"></a>01607 <span class="preprocessor"></span>                DWC_PRINTF
+<a name="l01608"></a>01608                     (<span class="stringliteral">"*** %s: Channel %d, _hc-&gt;halt_pending already set ***\n"</span>,
+<a name="l01609"></a>01609                      __func__, hc-&gt;<a class="code" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">hc_num</a>);
+<a name="l01610"></a>01610 
+<a name="l01611"></a>01611 <span class="preprocessor">#endif</span>
+<a name="l01612"></a>01612 <span class="preprocessor"></span>                <span class="keywordflow">return</span>;
+<a name="l01613"></a>01613         }
+<a name="l01614"></a>01614 
+<a name="l01615"></a>01615         hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">hcchar</a>);
+<a name="l01616"></a>01616         
+<a name="l01617"></a>01617         <span class="comment">/* No need to set the bit in DDMA for disabling the channel */</span>
+<a name="l01618"></a>01618         <span class="comment">//TODO check it everywhere channel is disabled          </span>
+<a name="l01619"></a>01619         <span class="keywordflow">if</span>(!core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#36c5bcf00d0f776b5c9e84e5d8ae408d">dma_desc_enable</a>)
+<a name="l01620"></a>01620                 hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#994a5305780edb0c4fe159b6cc7b14ae">chen</a> = 1;
+<a name="l01621"></a>01621         hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#73c9f7f3cc4036c72ef341d1d1d9c388">chdis</a> = 1;
+<a name="l01622"></a>01622         
+<a name="l01623"></a>01623         <span class="keywordflow">if</span> (!core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a>) {
+<a name="l01624"></a>01624                 <span class="comment">/* Check for space in the request queue to issue the halt. */</span>
+<a name="l01625"></a>01625                 <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#e6169fbc92e4d79686097742ad646f5c">ep_type</a> == <a class="code" href="dwc__otg__cil_8h.html#64e5cd756330f5adab79b25cc8067bdc">DWC_OTG_EP_TYPE_CONTROL</a> ||
+<a name="l01626"></a>01626                     hc-&gt;<a class="code" href="structdwc__hc.html#e6169fbc92e4d79686097742ad646f5c">ep_type</a> == <a class="code" href="dwc__otg__cil_8h.html#9b079858cda0b917316ad9161b3881e0">DWC_OTG_EP_TYPE_BULK</a>) {
+<a name="l01627"></a>01627                         nptxsts.<a class="code" href="uniongnptxsts__data.html#a58b5adbe6bd0344c4f585ef6aba4672">d32</a> = dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#57dabea6f6e0bf9e1ee8e94f55b9e465">gnptxsts</a>);
+<a name="l01628"></a>01628                         <span class="keywordflow">if</span> (nptxsts.<a class="code" href="uniongnptxsts__data.html#be1d1adf7b827616ebbbf6bf564c0738">b</a>.<a class="code" href="uniongnptxsts__data.html#634ffd5e84bc422ddef043574d8f0957">nptxqspcavail</a> == 0) {
+<a name="l01629"></a>01629                                 hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#994a5305780edb0c4fe159b6cc7b14ae">chen</a> = 0;
+<a name="l01630"></a>01630                         }
+<a name="l01631"></a>01631                 } <span class="keywordflow">else</span> {
+<a name="l01632"></a>01632                         hptxsts.<a class="code" href="unionhptxsts__data.html#b48d41d449d8f71c0b184b38029c26bc">d32</a> =
+<a name="l01633"></a>01633                             dwc_read_reg32(&amp;host_global_regs-&gt;<a class="code" href="structdwc__otg__host__global__regs.html#bf1a1528a2e479d86318d49ecd52ee40">hptxsts</a>);
+<a name="l01634"></a>01634                         <span class="keywordflow">if</span> ((hptxsts.<a class="code" href="unionhptxsts__data.html#a6839185cc4aeabf771f04f1b2a97ec3">b</a>.<a class="code" href="unionhptxsts__data.html#8139e6eafb7b0bbb3cbafa125d5cd28f">ptxqspcavail</a> == 0)
+<a name="l01635"></a>01635                             || (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5a6a90b40bc80e71d40f107b68f1e84c">queuing_high_bandwidth</a>)) {
+<a name="l01636"></a>01636                                 hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#994a5305780edb0c4fe159b6cc7b14ae">chen</a> = 0;
+<a name="l01637"></a>01637                         }
+<a name="l01638"></a>01638                 }
+<a name="l01639"></a>01639         }
+<a name="l01640"></a>01640         dwc_write_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">hcchar</a>, hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a>);
+<a name="l01641"></a>01641 
+<a name="l01642"></a>01642         hc-&gt;<a class="code" href="structdwc__hc.html#07eca0fa02105ddaa1719387f5558b23">halt_status</a> = halt_status;
+<a name="l01643"></a>01643 
+<a name="l01644"></a>01644         <span class="keywordflow">if</span> (hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#994a5305780edb0c4fe159b6cc7b14ae">chen</a>) {
+<a name="l01645"></a>01645                 hc-&gt;<a class="code" href="structdwc__hc.html#2177dcde6dbb17b6bc7d0fb34e8ec95a">halt_pending</a> = 1;
+<a name="l01646"></a>01646                 hc-&gt;<a class="code" href="structdwc__hc.html#c3b27b33fae73aff43a9834a1ed585da">halt_on_queue</a> = 0;
+<a name="l01647"></a>01647         } <span class="keywordflow">else</span> {
+<a name="l01648"></a>01648                 hc-&gt;<a class="code" href="structdwc__hc.html#c3b27b33fae73aff43a9834a1ed585da">halt_on_queue</a> = 1;
+<a name="l01649"></a>01649         }
+<a name="l01650"></a>01650 
+<a name="l01651"></a>01651         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"%s: Channel %d\n"</span>, __func__, hc-&gt;<a class="code" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">hc_num</a>);
+<a name="l01652"></a>01652         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"  hcchar: 0x%08x\n"</span>, hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a>);
+<a name="l01653"></a>01653         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"  halt_pending: %d\n"</span>, hc-&gt;<a class="code" href="structdwc__hc.html#2177dcde6dbb17b6bc7d0fb34e8ec95a">halt_pending</a>);
+<a name="l01654"></a>01654         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"  halt_on_queue: %d\n"</span>, hc-&gt;<a class="code" href="structdwc__hc.html#c3b27b33fae73aff43a9834a1ed585da">halt_on_queue</a>);
+<a name="l01655"></a>01655         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"  halt_status: %d\n"</span>, hc-&gt;<a class="code" href="structdwc__hc.html#07eca0fa02105ddaa1719387f5558b23">halt_status</a>);
+<a name="l01656"></a>01656 
+<a name="l01657"></a>01657         <span class="keywordflow">return</span>;
+<a name="l01658"></a>01658 }
+<a name="l01659"></a>01659 
+<a name="l01667"></a><a class="code" href="dwc__otg__cil_8h.html#99d4028c98b445a925ea5068b399d319">01667</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#f05341f811fba7f6183db66faf50a867">dwc_otg_hc_cleanup</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, <a class="code" href="structdwc__hc.html">dwc_hc_t</a> * hc)
+<a name="l01668"></a>01668 {
+<a name="l01669"></a>01669         <a class="code" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *hc_regs;
+<a name="l01670"></a>01670 
+<a name="l01671"></a>01671         hc-&gt;<a class="code" href="structdwc__hc.html#78a1cf134604b24bfdedb4f4df9f2c1f">xfer_started</a> = 0;
+<a name="l01672"></a>01672 
+<a name="l01673"></a>01673         <span class="comment">/*</span>
+<a name="l01674"></a>01674 <span class="comment">         * Clear channel interrupt enables and any unhandled channel interrupt</span>
+<a name="l01675"></a>01675 <span class="comment">         * conditions.</span>
+<a name="l01676"></a>01676 <span class="comment">         */</span>
+<a name="l01677"></a>01677         hc_regs = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#7f7c107d4720641eb4141cd817211ac0">hc_regs</a>[hc-&gt;<a class="code" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">hc_num</a>];
+<a name="l01678"></a>01678         dwc_write_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#830aa61c1d4326823662168ea7359205">hcintmsk</a>, 0);
+<a name="l01679"></a>01679         dwc_write_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#0dfd5bae537d58e13788508dc719480d">hcint</a>, 0xFFFFFFFF);
+<a name="l01680"></a>01680 <span class="preprocessor">#ifdef DEBUG</span>
+<a name="l01681"></a>01681 <span class="preprocessor"></span>        DWC_TIMER_CANCEL(core_if-&gt;hc_xfer_timer[hc-&gt;<a class="code" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">hc_num</a>]);
+<a name="l01682"></a>01682 <span class="preprocessor">#endif</span>
+<a name="l01683"></a>01683 <span class="preprocessor"></span>}
+<a name="l01684"></a>01684 
+<a name="l01695"></a><a class="code" href="dwc__otg__cil_8c.html#b2669551136671d3e4b6ad56bd947222">01695</a> <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#b2669551136671d3e4b6ad56bd947222">hc_set_even_odd_frame</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if,
+<a name="l01696"></a>01696                                          <a class="code" href="structdwc__hc.html">dwc_hc_t</a> * hc, <a class="code" href="unionhcchar__data.html">hcchar_data_t</a> * hcchar)
+<a name="l01697"></a>01697 {
+<a name="l01698"></a>01698         <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#e6169fbc92e4d79686097742ad646f5c">ep_type</a> == <a class="code" href="dwc__otg__cil_8h.html#1401d1264f88530232cf51ab31cc5347">DWC_OTG_EP_TYPE_INTR</a> ||
+<a name="l01699"></a>01699             hc-&gt;<a class="code" href="structdwc__hc.html#e6169fbc92e4d79686097742ad646f5c">ep_type</a> == <a class="code" href="dwc__otg__cil_8h.html#152a3a5e1433bd2197672f0b5105e7a4">DWC_OTG_EP_TYPE_ISOC</a>) {
+<a name="l01700"></a>01700                 <a class="code" href="unionhfnum__data.html">hfnum_data_t</a> hfnum;
+<a name="l01701"></a>01701                 hfnum.<a class="code" href="unionhfnum__data.html#e5ccbed3af86ac88577ded328e6c9932">d32</a> =
+<a name="l01702"></a>01702                     dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#ff9692c2e10ca2bc7e24f981f25179c2">host_global_regs</a>-&gt;<a class="code" href="structdwc__otg__host__global__regs.html#cebb0d86d0776473ef30eeac61e8692c">hfnum</a>);
+<a name="l01703"></a>01703 
+<a name="l01704"></a>01704                 <span class="comment">/* 1 if _next_ frame is odd, 0 if it's even */</span>
+<a name="l01705"></a>01705                 hcchar-&gt;<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#1eae01428cc22feed785eedff05c86da">oddfrm</a> = (hfnum.<a class="code" href="unionhfnum__data.html#81df6fbd20a454665803eb5790855c66">b</a>.<a class="code" href="unionhfnum__data.html#a64e8b6c4a1cd262dbc30e158f3cb8bc">frnum</a> &amp; 0x1) ? 0 : 1;
+<a name="l01706"></a>01706 <span class="preprocessor">#ifdef DEBUG</span>
+<a name="l01707"></a>01707 <span class="preprocessor"></span>                <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#e6169fbc92e4d79686097742ad646f5c">ep_type</a> == <a class="code" href="dwc__otg__cil_8h.html#1401d1264f88530232cf51ab31cc5347">DWC_OTG_EP_TYPE_INTR</a> &amp;&amp; hc-&gt;<a class="code" href="structdwc__hc.html#4365ef67d517a621a626ac5392545c6d">do_split</a>
+<a name="l01708"></a>01708                     &amp;&amp; !hc-&gt;<a class="code" href="structdwc__hc.html#21e00df6fb9a555975879526118d599e">complete_split</a>) {
+<a name="l01709"></a>01709                         <span class="keywordflow">switch</span> (hfnum.<a class="code" href="unionhfnum__data.html#81df6fbd20a454665803eb5790855c66">b</a>.<a class="code" href="unionhfnum__data.html#a64e8b6c4a1cd262dbc30e158f3cb8bc">frnum</a> &amp; 0x7) {
+<a name="l01710"></a>01710                         <span class="keywordflow">case</span> 7:
+<a name="l01711"></a>01711                                 core_if-&gt;hfnum_7_samples++;
+<a name="l01712"></a>01712                                 core_if-&gt;hfnum_7_frrem_accum += hfnum.<a class="code" href="unionhfnum__data.html#81df6fbd20a454665803eb5790855c66">b</a>.<a class="code" href="unionhfnum__data.html#2a2ce50ebd4c4da5347a2d93c4bbc996">frrem</a>;
+<a name="l01713"></a>01713                                 <span class="keywordflow">break</span>;
+<a name="l01714"></a>01714                         <span class="keywordflow">case</span> 0:
+<a name="l01715"></a>01715                                 core_if-&gt;hfnum_0_samples++;
+<a name="l01716"></a>01716                                 core_if-&gt;hfnum_0_frrem_accum += hfnum.<a class="code" href="unionhfnum__data.html#81df6fbd20a454665803eb5790855c66">b</a>.<a class="code" href="unionhfnum__data.html#2a2ce50ebd4c4da5347a2d93c4bbc996">frrem</a>;
+<a name="l01717"></a>01717                                 <span class="keywordflow">break</span>;
+<a name="l01718"></a>01718                         <span class="keywordflow">default</span>:
+<a name="l01719"></a>01719                                 core_if-&gt;hfnum_other_samples++;
+<a name="l01720"></a>01720                                 core_if-&gt;hfnum_other_frrem_accum +=
+<a name="l01721"></a>01721                                     hfnum.<a class="code" href="unionhfnum__data.html#81df6fbd20a454665803eb5790855c66">b</a>.<a class="code" href="unionhfnum__data.html#2a2ce50ebd4c4da5347a2d93c4bbc996">frrem</a>;
+<a name="l01722"></a>01722                                 <span class="keywordflow">break</span>;
+<a name="l01723"></a>01723                         }
+<a name="l01724"></a>01724                 }
+<a name="l01725"></a>01725 <span class="preprocessor">#endif</span>
+<a name="l01726"></a>01726 <span class="preprocessor"></span>        }
+<a name="l01727"></a>01727 }
+<a name="l01728"></a>01728 
+<a name="l01729"></a>01729 <span class="preprocessor">#ifdef DEBUG</span>
+<a name="l01730"></a>01730 <span class="preprocessor"></span><span class="keywordtype">void</span> hc_xfer_timeout(<span class="keywordtype">void</span> *ptr)
+<a name="l01731"></a>01731 {
+<a name="l01732"></a>01732         hc_xfer_info_t *xfer_info = (hc_xfer_info_t *) ptr;
+<a name="l01733"></a>01733         <span class="keywordtype">int</span> hc_num = xfer_info-&gt;hc-&gt;hc_num;
+<a name="l01734"></a>01734         DWC_WARN(<span class="stringliteral">"%s: timeout on channel %d\n"</span>, __func__, hc_num);
+<a name="l01735"></a>01735         DWC_WARN(<span class="stringliteral">"      start_hcchar_val 0x%08x\n"</span>,
+<a name="l01736"></a>01736                  xfer_info-&gt;core_if-&gt;start_hcchar_val[hc_num]);
+<a name="l01737"></a>01737 }
+<a name="l01738"></a>01738 <span class="preprocessor">#endif</span>
+<a name="l01739"></a>01739 <span class="preprocessor"></span>
+<a name="l01740"></a><a class="code" href="dwc__otg__cil_8c.html#bf1f2e3a039a78f9cc51c8223c40d8e1">01740</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#bf1f2e3a039a78f9cc51c8223c40d8e1">set_pid_isoc</a>(<a class="code" href="structdwc__hc.html">dwc_hc_t</a> * hc)
+<a name="l01741"></a>01741 {
+<a name="l01742"></a>01742         <span class="comment">/* Set up the initial PID for the transfer. */</span>
+<a name="l01743"></a>01743         <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#570b78178975193edb921af1ef36d37b">speed</a> == <a class="code" href="dwc__otg__cil_8h.html#b9dc03c6bc3c1113a935a73cf7021fbe">DWC_OTG_EP_SPEED_HIGH</a>) {
+<a name="l01744"></a>01744                 <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#c5088d431f5efc382121f201f5d571aa">ep_is_in</a>) {
+<a name="l01745"></a>01745                         <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#9a01b904f7ccc7178cdb80c20e8a9b0c">multi_count</a> == 1) {
+<a name="l01746"></a>01746                                 hc-&gt;<a class="code" href="structdwc__hc.html#513427c5e8c4603ba344d4e7f9191064">data_pid_start</a> =
+<a name="l01747"></a>01747                                     <a class="code" href="dwc__otg__cil_8h.html#0e843d08e80c29e82962ce9170a02a52">DWC_OTG_HC_PID_DATA0</a>;
+<a name="l01748"></a>01748                         } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#9a01b904f7ccc7178cdb80c20e8a9b0c">multi_count</a> == 2) {
+<a name="l01749"></a>01749                                 hc-&gt;<a class="code" href="structdwc__hc.html#513427c5e8c4603ba344d4e7f9191064">data_pid_start</a> =
+<a name="l01750"></a>01750                                     <a class="code" href="dwc__otg__cil_8h.html#e623eb446c55928b324e9636111315e1">DWC_OTG_HC_PID_DATA1</a>;
+<a name="l01751"></a>01751                         } <span class="keywordflow">else</span> {
+<a name="l01752"></a>01752                                 hc-&gt;<a class="code" href="structdwc__hc.html#513427c5e8c4603ba344d4e7f9191064">data_pid_start</a> =
+<a name="l01753"></a>01753                                     <a class="code" href="dwc__otg__cil_8h.html#5a78ac2f42a7e583d849903fa4570fb8">DWC_OTG_HC_PID_DATA2</a>;
+<a name="l01754"></a>01754                         }
+<a name="l01755"></a>01755                 } <span class="keywordflow">else</span> {
+<a name="l01756"></a>01756                         <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#9a01b904f7ccc7178cdb80c20e8a9b0c">multi_count</a> == 1) {
+<a name="l01757"></a>01757                                 hc-&gt;<a class="code" href="structdwc__hc.html#513427c5e8c4603ba344d4e7f9191064">data_pid_start</a> =
+<a name="l01758"></a>01758                                     <a class="code" href="dwc__otg__cil_8h.html#0e843d08e80c29e82962ce9170a02a52">DWC_OTG_HC_PID_DATA0</a>;
+<a name="l01759"></a>01759                         } <span class="keywordflow">else</span> {
+<a name="l01760"></a>01760                                 hc-&gt;<a class="code" href="structdwc__hc.html#513427c5e8c4603ba344d4e7f9191064">data_pid_start</a> =
+<a name="l01761"></a>01761                                     <a class="code" href="dwc__otg__cil_8h.html#3cea7ef8aa1cfeb50060f07e08fa6aff">DWC_OTG_HC_PID_MDATA</a>;
+<a name="l01762"></a>01762                         }
+<a name="l01763"></a>01763                 }
+<a name="l01764"></a>01764         } <span class="keywordflow">else</span> {
+<a name="l01765"></a>01765                 hc-&gt;<a class="code" href="structdwc__hc.html#513427c5e8c4603ba344d4e7f9191064">data_pid_start</a> = <a class="code" href="dwc__otg__cil_8h.html#0e843d08e80c29e82962ce9170a02a52">DWC_OTG_HC_PID_DATA0</a>;
+<a name="l01766"></a>01766         }
+<a name="l01767"></a>01767 }
+<a name="l01768"></a>01768 
+<a name="l01800"></a><a class="code" href="dwc__otg__cil_8h.html#0e66d54f3126186b0548743eb4641ad6">01800</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#025af79d6a2255dba4578588be510444">dwc_otg_hc_start_transfer</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, <a class="code" href="structdwc__hc.html">dwc_hc_t</a> * hc)
+<a name="l01801"></a>01801 {
+<a name="l01802"></a>01802         <a class="code" href="unionhcchar__data.html">hcchar_data_t</a> hcchar;
+<a name="l01803"></a>01803         <a class="code" href="unionhctsiz__data.html">hctsiz_data_t</a> hctsiz;
+<a name="l01804"></a>01804         uint16_t num_packets;
+<a name="l01805"></a>01805         uint32_t max_hc_xfer_size = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#e614d1d2ee740cd972ca76ed0dffec74">max_transfer_size</a>;
+<a name="l01806"></a>01806         uint16_t max_hc_pkt_count = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#e17230afa013a15beda38565d19fa933">max_packet_count</a>;
+<a name="l01807"></a>01807         <a class="code" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *hc_regs = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#7f7c107d4720641eb4141cd817211ac0">hc_regs</a>[hc-&gt;<a class="code" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">hc_num</a>];
+<a name="l01808"></a>01808 
+<a name="l01809"></a>01809         hctsiz.<a class="code" href="unionhctsiz__data.html#fb41950555c60c6015294bdefe9cd39d">d32</a> = 0;
+<a name="l01810"></a>01810 
+<a name="l01811"></a>01811         <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#ae7184275dbb23b3a5d2af20ed224920">do_ping</a>) {
+<a name="l01812"></a>01812                 <span class="keywordflow">if</span> (!core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a>) {
+<a name="l01813"></a>01813                         <a class="code" href="dwc__otg__cil_8c.html#4185d0b9bb4a49d28894f957c2e41117">dwc_otg_hc_do_ping</a>(core_if, hc);
+<a name="l01814"></a>01814                         hc-&gt;<a class="code" href="structdwc__hc.html#78a1cf134604b24bfdedb4f4df9f2c1f">xfer_started</a> = 1;
+<a name="l01815"></a>01815                         <span class="keywordflow">return</span>;
+<a name="l01816"></a>01816                 } <span class="keywordflow">else</span> {
+<a name="l01817"></a>01817                         hctsiz.<a class="code" href="unionhctsiz__data.html#8967fa90c651bce44a3cbe90c44cf638">b</a>.<a class="code" href="unionhctsiz__data.html#68625ebdd11afc0a026f41c94aedc161">dopng</a> = 1;
+<a name="l01818"></a>01818                 }
+<a name="l01819"></a>01819         }
+<a name="l01820"></a>01820 
+<a name="l01821"></a>01821         <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#4365ef67d517a621a626ac5392545c6d">do_split</a>) {
+<a name="l01822"></a>01822                 num_packets = 1;
+<a name="l01823"></a>01823 
+<a name="l01824"></a>01824                 <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#21e00df6fb9a555975879526118d599e">complete_split</a> &amp;&amp; !hc-&gt;<a class="code" href="structdwc__hc.html#c5088d431f5efc382121f201f5d571aa">ep_is_in</a>) {
+<a name="l01825"></a>01825                         <span class="comment">/* For CSPLIT OUT Transfer, set the size to 0 so the</span>
+<a name="l01826"></a>01826 <span class="comment">                         * core doesn't expect any data written to the FIFO */</span>
+<a name="l01827"></a>01827                         hc-&gt;<a class="code" href="structdwc__hc.html#ce32fe93214f1686896e924fbf61cac7">xfer_len</a> = 0;
+<a name="l01828"></a>01828                 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#c5088d431f5efc382121f201f5d571aa">ep_is_in</a> || (hc-&gt;<a class="code" href="structdwc__hc.html#ce32fe93214f1686896e924fbf61cac7">xfer_len</a> &gt; hc-&gt;<a class="code" href="structdwc__hc.html#bd88f02eb286ba01d8d1b049e8975ccb">max_packet</a>)) {
+<a name="l01829"></a>01829                         hc-&gt;<a class="code" href="structdwc__hc.html#ce32fe93214f1686896e924fbf61cac7">xfer_len</a> = hc-&gt;<a class="code" href="structdwc__hc.html#bd88f02eb286ba01d8d1b049e8975ccb">max_packet</a>;
+<a name="l01830"></a>01830                 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (!hc-&gt;<a class="code" href="structdwc__hc.html#c5088d431f5efc382121f201f5d571aa">ep_is_in</a> &amp;&amp; (hc-&gt;<a class="code" href="structdwc__hc.html#ce32fe93214f1686896e924fbf61cac7">xfer_len</a> &gt; 188)) {
+<a name="l01831"></a>01831                         hc-&gt;<a class="code" href="structdwc__hc.html#ce32fe93214f1686896e924fbf61cac7">xfer_len</a> = 188;
+<a name="l01832"></a>01832                 }
+<a name="l01833"></a>01833 
+<a name="l01834"></a>01834                 hctsiz.<a class="code" href="unionhctsiz__data.html#8967fa90c651bce44a3cbe90c44cf638">b</a>.<a class="code" href="unionhctsiz__data.html#6ad01d874d77aa4382f71fa68eaec12d">xfersize</a> = hc-&gt;<a class="code" href="structdwc__hc.html#ce32fe93214f1686896e924fbf61cac7">xfer_len</a>;
+<a name="l01835"></a>01835         } <span class="keywordflow">else</span> {
+<a name="l01836"></a>01836                 <span class="comment">/*</span>
+<a name="l01837"></a>01837 <span class="comment">                 * Ensure that the transfer length and packet count will fit</span>
+<a name="l01838"></a>01838 <span class="comment">                 * in the widths allocated for them in the HCTSIZn register.</span>
+<a name="l01839"></a>01839 <span class="comment">                 */</span>
+<a name="l01840"></a>01840                 <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#e6169fbc92e4d79686097742ad646f5c">ep_type</a> == <a class="code" href="dwc__otg__cil_8h.html#1401d1264f88530232cf51ab31cc5347">DWC_OTG_EP_TYPE_INTR</a> ||
+<a name="l01841"></a>01841                     hc-&gt;<a class="code" href="structdwc__hc.html#e6169fbc92e4d79686097742ad646f5c">ep_type</a> == <a class="code" href="dwc__otg__cil_8h.html#152a3a5e1433bd2197672f0b5105e7a4">DWC_OTG_EP_TYPE_ISOC</a>) {
+<a name="l01842"></a>01842                         <span class="comment">/*</span>
+<a name="l01843"></a>01843 <span class="comment">                         * Make sure the transfer size is no larger than one</span>
+<a name="l01844"></a>01844 <span class="comment">                         * (micro)frame's worth of data. (A check was done</span>
+<a name="l01845"></a>01845 <span class="comment">                         * when the periodic transfer was accepted to ensure</span>
+<a name="l01846"></a>01846 <span class="comment">                         * that a (micro)frame's worth of data can be</span>
+<a name="l01847"></a>01847 <span class="comment">                         * programmed into a channel.)</span>
+<a name="l01848"></a>01848 <span class="comment">                         */</span>
+<a name="l01849"></a>01849                         uint32_t max_periodic_len =
+<a name="l01850"></a>01850                             hc-&gt;<a class="code" href="structdwc__hc.html#9a01b904f7ccc7178cdb80c20e8a9b0c">multi_count</a> * hc-&gt;<a class="code" href="structdwc__hc.html#bd88f02eb286ba01d8d1b049e8975ccb">max_packet</a>;
+<a name="l01851"></a>01851                         <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#ce32fe93214f1686896e924fbf61cac7">xfer_len</a> &gt; max_periodic_len) {
+<a name="l01852"></a>01852                                 hc-&gt;<a class="code" href="structdwc__hc.html#ce32fe93214f1686896e924fbf61cac7">xfer_len</a> = max_periodic_len;
+<a name="l01853"></a>01853                         } <span class="keywordflow">else</span> {
+<a name="l01854"></a>01854                         }
+<a name="l01855"></a>01855                 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#ce32fe93214f1686896e924fbf61cac7">xfer_len</a> &gt; max_hc_xfer_size) {
+<a name="l01856"></a>01856                         <span class="comment">/* Make sure that xfer_len is a multiple of max packet size. */</span>
+<a name="l01857"></a>01857                         hc-&gt;<a class="code" href="structdwc__hc.html#ce32fe93214f1686896e924fbf61cac7">xfer_len</a> = max_hc_xfer_size - hc-&gt;<a class="code" href="structdwc__hc.html#bd88f02eb286ba01d8d1b049e8975ccb">max_packet</a> + 1;
+<a name="l01858"></a>01858                 }
+<a name="l01859"></a>01859 
+<a name="l01860"></a>01860                 <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#ce32fe93214f1686896e924fbf61cac7">xfer_len</a> &gt; 0) {
+<a name="l01861"></a>01861                         num_packets =
+<a name="l01862"></a>01862                             (hc-&gt;<a class="code" href="structdwc__hc.html#ce32fe93214f1686896e924fbf61cac7">xfer_len</a> + hc-&gt;<a class="code" href="structdwc__hc.html#bd88f02eb286ba01d8d1b049e8975ccb">max_packet</a> -
+<a name="l01863"></a>01863                              1) / hc-&gt;<a class="code" href="structdwc__hc.html#bd88f02eb286ba01d8d1b049e8975ccb">max_packet</a>;
+<a name="l01864"></a>01864                         if (num_packets &gt; max_hc_pkt_count) {
+<a name="l01865"></a>01865                                 num_packets = max_hc_pkt_count;
+<a name="l01866"></a>01866                                 hc-&gt;<a class="code" href="structdwc__hc.html#ce32fe93214f1686896e924fbf61cac7">xfer_len</a> = num_packets * hc-&gt;<a class="code" href="structdwc__hc.html#bd88f02eb286ba01d8d1b049e8975ccb">max_packet</a>;
+<a name="l01867"></a>01867                         }
+<a name="l01868"></a>01868                 } <span class="keywordflow">else</span> {
+<a name="l01869"></a>01869                         <span class="comment">/* Need 1 packet for transfer length of 0. */</span>
+<a name="l01870"></a>01870                         num_packets = 1;
+<a name="l01871"></a>01871                 }
+<a name="l01872"></a>01872 
+<a name="l01873"></a>01873                 <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#c5088d431f5efc382121f201f5d571aa">ep_is_in</a>) {
+<a name="l01874"></a>01874                         <span class="comment">/* Always program an integral # of max packets for IN transfers. */</span>
+<a name="l01875"></a>01875                         hc-&gt;<a class="code" href="structdwc__hc.html#ce32fe93214f1686896e924fbf61cac7">xfer_len</a> = num_packets * hc-&gt;<a class="code" href="structdwc__hc.html#bd88f02eb286ba01d8d1b049e8975ccb">max_packet</a>;
+<a name="l01876"></a>01876                 }
+<a name="l01877"></a>01877 
+<a name="l01878"></a>01878                 <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#e6169fbc92e4d79686097742ad646f5c">ep_type</a> == <a class="code" href="dwc__otg__cil_8h.html#1401d1264f88530232cf51ab31cc5347">DWC_OTG_EP_TYPE_INTR</a> ||
+<a name="l01879"></a>01879                     hc-&gt;<a class="code" href="structdwc__hc.html#e6169fbc92e4d79686097742ad646f5c">ep_type</a> == <a class="code" href="dwc__otg__cil_8h.html#152a3a5e1433bd2197672f0b5105e7a4">DWC_OTG_EP_TYPE_ISOC</a>) {
+<a name="l01880"></a>01880                         <span class="comment">/*</span>
+<a name="l01881"></a>01881 <span class="comment">                         * Make sure that the multi_count field matches the</span>
+<a name="l01882"></a>01882 <span class="comment">                         * actual transfer length.</span>
+<a name="l01883"></a>01883 <span class="comment">                         */</span>
+<a name="l01884"></a>01884                         hc-&gt;<a class="code" href="structdwc__hc.html#9a01b904f7ccc7178cdb80c20e8a9b0c">multi_count</a> = num_packets;
+<a name="l01885"></a>01885                 }
+<a name="l01886"></a>01886 
+<a name="l01887"></a>01887                 <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#e6169fbc92e4d79686097742ad646f5c">ep_type</a> == <a class="code" href="dwc__otg__cil_8h.html#152a3a5e1433bd2197672f0b5105e7a4">DWC_OTG_EP_TYPE_ISOC</a>)
+<a name="l01888"></a>01888                         <a class="code" href="dwc__otg__cil_8c.html#bf1f2e3a039a78f9cc51c8223c40d8e1">set_pid_isoc</a>(hc);
+<a name="l01889"></a>01889 
+<a name="l01890"></a>01890                 hctsiz.<a class="code" href="unionhctsiz__data.html#8967fa90c651bce44a3cbe90c44cf638">b</a>.<a class="code" href="unionhctsiz__data.html#6ad01d874d77aa4382f71fa68eaec12d">xfersize</a> = hc-&gt;xfer_len;
+<a name="l01891"></a>01891         }
+<a name="l01892"></a>01892 
+<a name="l01893"></a>01893         hc-&gt;<a class="code" href="structdwc__hc.html#6c030bc725f43025d3046d17b4fbee4e">start_pkt_count</a> = num_packets;
+<a name="l01894"></a>01894         hctsiz.<a class="code" href="unionhctsiz__data.html#8967fa90c651bce44a3cbe90c44cf638">b</a>.<a class="code" href="unionhctsiz__data.html#3ea18df5a98d33a6f8fa786252a0205b">pktcnt</a> = num_packets;
+<a name="l01895"></a>01895         hctsiz.<a class="code" href="unionhctsiz__data.html#8967fa90c651bce44a3cbe90c44cf638">b</a>.<a class="code" href="unionhctsiz__data.html#d8b17af02c244e47ca0c38f933a6b3f0">pid</a> = hc-&gt;<a class="code" href="structdwc__hc.html#513427c5e8c4603ba344d4e7f9191064">data_pid_start</a>;
+<a name="l01896"></a>01896         dwc_write_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#c6173f823ba754d9f9549422b6380ca2">hctsiz</a>, hctsiz.<a class="code" href="unionhctsiz__data.html#fb41950555c60c6015294bdefe9cd39d">d32</a>);
+<a name="l01897"></a>01897 
+<a name="l01898"></a>01898         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"%s: Channel %d\n"</span>, __func__, hc-&gt;<a class="code" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">hc_num</a>);
+<a name="l01899"></a>01899         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"  Xfer Size: %d\n"</span>, hctsiz.<a class="code" href="unionhctsiz__data.html#8967fa90c651bce44a3cbe90c44cf638">b</a>.<a class="code" href="unionhctsiz__data.html#6ad01d874d77aa4382f71fa68eaec12d">xfersize</a>);
+<a name="l01900"></a>01900         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"  Num Pkts: %d\n"</span>, hctsiz.<a class="code" href="unionhctsiz__data.html#8967fa90c651bce44a3cbe90c44cf638">b</a>.<a class="code" href="unionhctsiz__data.html#3ea18df5a98d33a6f8fa786252a0205b">pktcnt</a>);
+<a name="l01901"></a>01901         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"  Start PID: %d\n"</span>, hctsiz.<a class="code" href="unionhctsiz__data.html#8967fa90c651bce44a3cbe90c44cf638">b</a>.<a class="code" href="unionhctsiz__data.html#d8b17af02c244e47ca0c38f933a6b3f0">pid</a>);
+<a name="l01902"></a>01902 
+<a name="l01903"></a>01903         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a>) {
+<a name="l01904"></a>01904                 dwc_dma_t dma_addr;
+<a name="l01905"></a>01905                 <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#e0c3ba51a04b36656baa4e70fc63cf77">align_buff</a>) {
+<a name="l01906"></a>01906                         dma_addr = hc-&gt;<a class="code" href="structdwc__hc.html#e0c3ba51a04b36656baa4e70fc63cf77">align_buff</a>;
+<a name="l01907"></a>01907                 } <span class="keywordflow">else</span> {
+<a name="l01908"></a>01908                         dma_addr = (uint32_t)hc-&gt;<a class="code" href="structdwc__hc.html#9dc781cb9e4bc639765beee37ce76673">xfer_buff</a>;
+<a name="l01909"></a>01909                 }
+<a name="l01910"></a>01910                 dwc_write_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#ab2148d4b5f1bf3a2ad438e497a8b4a3">hcdma</a>, dma_addr);
+<a name="l01911"></a>01911         }
+<a name="l01912"></a>01912 
+<a name="l01913"></a>01913         <span class="comment">/* Start the split */</span>
+<a name="l01914"></a>01914         <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#4365ef67d517a621a626ac5392545c6d">do_split</a>) {
+<a name="l01915"></a>01915                 <a class="code" href="unionhcsplt__data.html">hcsplt_data_t</a> hcsplt;
+<a name="l01916"></a>01916                 hcsplt.<a class="code" href="unionhcsplt__data.html#0cd235b445ff681b846f5dccf24fd644">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#149053001a9ee21b692afde531a814de">hcsplt</a>);
+<a name="l01917"></a>01917                 hcsplt.<a class="code" href="unionhcsplt__data.html#b8bafe40eee4a9f598659d254be836e1">b</a>.<a class="code" href="unionhcsplt__data.html#8b174930345ac0e5a8a6bd16794836d7">spltena</a> = 1;
+<a name="l01918"></a>01918                 dwc_write_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#149053001a9ee21b692afde531a814de">hcsplt</a>, hcsplt.<a class="code" href="unionhcsplt__data.html#0cd235b445ff681b846f5dccf24fd644">d32</a>);
+<a name="l01919"></a>01919         }
+<a name="l01920"></a>01920 
+<a name="l01921"></a>01921         hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">hcchar</a>);
+<a name="l01922"></a>01922         hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#9c0f515663251779e4960ec5613ce6fe">multicnt</a> = hc-&gt;<a class="code" href="structdwc__hc.html#9a01b904f7ccc7178cdb80c20e8a9b0c">multi_count</a>;
+<a name="l01923"></a>01923         <a class="code" href="dwc__otg__cil_8c.html#b2669551136671d3e4b6ad56bd947222">hc_set_even_odd_frame</a>(core_if, hc, &amp;hcchar);
+<a name="l01924"></a>01924 <span class="preprocessor">#ifdef DEBUG</span>
+<a name="l01925"></a>01925 <span class="preprocessor"></span>        core_if-&gt;start_hcchar_val[hc-&gt;<a class="code" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">hc_num</a>] = hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a>;
+<a name="l01926"></a>01926         <span class="keywordflow">if</span> (hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#73c9f7f3cc4036c72ef341d1d1d9c388">chdis</a>) {
+<a name="l01927"></a>01927                 DWC_WARN(<span class="stringliteral">"%s: chdis set, channel %d, hcchar 0x%08x\n"</span>,
+<a name="l01928"></a>01928                          __func__, hc-&gt;<a class="code" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">hc_num</a>, hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a>);
+<a name="l01929"></a>01929         }
+<a name="l01930"></a>01930 <span class="preprocessor">#endif</span>
+<a name="l01931"></a>01931 <span class="preprocessor"></span>
+<a name="l01932"></a>01932         <span class="comment">/* Set host channel enable after all other setup is complete. */</span>
+<a name="l01933"></a>01933         hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#994a5305780edb0c4fe159b6cc7b14ae">chen</a> = 1;
+<a name="l01934"></a>01934         hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#73c9f7f3cc4036c72ef341d1d1d9c388">chdis</a> = 0;
+<a name="l01935"></a>01935         dwc_write_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">hcchar</a>, hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a>);
+<a name="l01936"></a>01936 
+<a name="l01937"></a>01937         hc-&gt;<a class="code" href="structdwc__hc.html#78a1cf134604b24bfdedb4f4df9f2c1f">xfer_started</a> = 1;
+<a name="l01938"></a>01938         hc-&gt;<a class="code" href="structdwc__hc.html#961e8eae7a18c503e370c4bc513d3e55">requests</a>++;
+<a name="l01939"></a>01939 
+<a name="l01940"></a>01940         <span class="keywordflow">if</span> (!core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a> &amp;&amp; !hc-&gt;<a class="code" href="structdwc__hc.html#c5088d431f5efc382121f201f5d571aa">ep_is_in</a> &amp;&amp; hc-&gt;<a class="code" href="structdwc__hc.html#ce32fe93214f1686896e924fbf61cac7">xfer_len</a> &gt; 0) {
+<a name="l01941"></a>01941                 <span class="comment">/* Load OUT packet into the appropriate Tx FIFO. */</span>
+<a name="l01942"></a>01942                 <a class="code" href="dwc__otg__cil_8c.html#c4ccce95ab4067e03c089519c1b54a94">dwc_otg_hc_write_packet</a>(core_if, hc);
+<a name="l01943"></a>01943         }
+<a name="l01944"></a>01944 <span class="preprocessor">#ifdef DEBUG</span>
+<a name="l01945"></a>01945 <span class="preprocessor"></span>        <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#e6169fbc92e4d79686097742ad646f5c">ep_type</a> != <a class="code" href="dwc__otg__cil_8h.html#1401d1264f88530232cf51ab31cc5347">DWC_OTG_EP_TYPE_INTR</a>) {
+<a name="l01946"></a>01946                 core_if-&gt;hc_xfer_info[hc-&gt;<a class="code" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">hc_num</a>].core_if = core_if;
+<a name="l01947"></a>01947                 core_if-&gt;hc_xfer_info[hc-&gt;<a class="code" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">hc_num</a>].hc = hc;
+<a name="l01948"></a>01948                 <span class="comment">/* Start a timer for this transfer. */</span>
+<a name="l01949"></a>01949                 DWC_TIMER_SCHEDULE(core_if-&gt;hc_xfer_timer[hc-&gt;<a class="code" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">hc_num</a>], 10000);
+<a name="l01950"></a>01950         }
+<a name="l01951"></a>01951 <span class="preprocessor">#endif</span>
+<a name="l01952"></a>01952 <span class="preprocessor"></span>}
+<a name="l01953"></a>01953 
+<a name="l01968"></a><a class="code" href="dwc__otg__cil_8h.html#dbc20e9f9cadbdf4df65db3f82bbb820">01968</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#dbc20e9f9cadbdf4df65db3f82bbb820">dwc_otg_hc_start_transfer_ddma</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, <a class="code" href="structdwc__hc.html">dwc_hc_t</a> * hc)
+<a name="l01969"></a>01969 {
+<a name="l01970"></a>01970         <a class="code" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *hc_regs = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#7f7c107d4720641eb4141cd817211ac0">hc_regs</a>[hc-&gt;<a class="code" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">hc_num</a>];     
+<a name="l01971"></a>01971         <a class="code" href="unionhcchar__data.html">hcchar_data_t</a> hcchar;
+<a name="l01972"></a>01972         <a class="code" href="unionhctsiz__data.html">hctsiz_data_t</a> hctsiz;
+<a name="l01973"></a>01973         <a class="code" href="unionhcdma__data.html">hcdma_data_t</a>  hcdma;
+<a name="l01974"></a>01974         
+<a name="l01975"></a>01975         hctsiz.<a class="code" href="unionhctsiz__data.html#fb41950555c60c6015294bdefe9cd39d">d32</a> = 0;
+<a name="l01976"></a>01976 
+<a name="l01977"></a>01977         <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#ae7184275dbb23b3a5d2af20ed224920">do_ping</a> &amp;&amp; !hc-&gt;<a class="code" href="structdwc__hc.html#c5088d431f5efc382121f201f5d571aa">ep_is_in</a>)
+<a name="l01978"></a>01978                 hctsiz.<a class="code" href="unionhctsiz__data.html#6cc80c630201f29e4a43e0cd7030786b">b_ddma</a>.<a class="code" href="unionhctsiz__data.html#68625ebdd11afc0a026f41c94aedc161">dopng</a> = 1;
+<a name="l01979"></a>01979 
+<a name="l01980"></a>01980         <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#e6169fbc92e4d79686097742ad646f5c">ep_type</a> == <a class="code" href="dwc__otg__cil_8h.html#152a3a5e1433bd2197672f0b5105e7a4">DWC_OTG_EP_TYPE_ISOC</a>)
+<a name="l01981"></a>01981                 <a class="code" href="dwc__otg__cil_8c.html#bf1f2e3a039a78f9cc51c8223c40d8e1">set_pid_isoc</a>(hc);
+<a name="l01982"></a>01982         
+<a name="l01983"></a>01983         <span class="comment">/* Packet Count and Xfer Size are not used in Descriptor DMA mode */</span>
+<a name="l01984"></a>01984         hctsiz.<a class="code" href="unionhctsiz__data.html#6cc80c630201f29e4a43e0cd7030786b">b_ddma</a>.<a class="code" href="unionhctsiz__data.html#d8b17af02c244e47ca0c38f933a6b3f0">pid</a> = hc-&gt;data_pid_start;
+<a name="l01985"></a>01985         hctsiz.<a class="code" href="unionhctsiz__data.html#6cc80c630201f29e4a43e0cd7030786b">b_ddma</a>.<a class="code" href="unionhctsiz__data.html#ac1addd68951e1a6a25312d49be9895d">ntd</a> = hc-&gt;ntd - 1; <span class="comment">/* 0 - 1 descriptor, 1 - 2 descriptors, etc. */</span>
+<a name="l01986"></a>01986         hctsiz.<a class="code" href="unionhctsiz__data.html#6cc80c630201f29e4a43e0cd7030786b">b_ddma</a>.<a class="code" href="unionhctsiz__data.html#0d1f05f3b24da2caa3acc1c3864bc29b">schinfo</a> = hc-&gt;schinfo; <span class="comment">/* Non-zero only for high-speed interrupt endpoints */</span>
+<a name="l01987"></a>01987         
+<a name="l01988"></a>01988         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"%s: Channel %d\n"</span>, __func__, hc-&gt;hc_num);
+<a name="l01989"></a>01989         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"  Start PID: %d\n"</span>, hctsiz.<a class="code" href="unionhctsiz__data.html#8967fa90c651bce44a3cbe90c44cf638">b</a>.<a class="code" href="unionhctsiz__data.html#d8b17af02c244e47ca0c38f933a6b3f0">pid</a>);
+<a name="l01990"></a>01990         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"  NTD: %d\n"</span>, hctsiz.<a class="code" href="unionhctsiz__data.html#6cc80c630201f29e4a43e0cd7030786b">b_ddma</a>.<a class="code" href="unionhctsiz__data.html#ac1addd68951e1a6a25312d49be9895d">ntd</a>);        
+<a name="l01991"></a>01991 
+<a name="l01992"></a>01992         dwc_write_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#c6173f823ba754d9f9549422b6380ca2">hctsiz</a>, hctsiz.<a class="code" href="unionhctsiz__data.html#fb41950555c60c6015294bdefe9cd39d">d32</a>);
+<a name="l01993"></a>01993 
+<a name="l01994"></a>01994         hcdma.<a class="code" href="unionhcdma__data.html#27b804015f09ea7eb25f602cc6dbdda9">d32</a> = 0;
+<a name="l01995"></a>01995         hcdma.<a class="code" href="unionhcdma__data.html#61ea7b926fcef1d4fe1a6c8a1a1be41a">b</a>.<a class="code" href="unionhcdma__data.html#8324b2ba8d18c5ecb1cbcb23874393db">dma_addr</a> = ((uint32_t)hc-&gt;desc_list_addr) &gt;&gt; 11;
+<a name="l01996"></a>01996                 
+<a name="l01997"></a>01997         <span class="comment">/* Always start from first descriptor. */</span>
+<a name="l01998"></a>01998         hcdma.<a class="code" href="unionhcdma__data.html#61ea7b926fcef1d4fe1a6c8a1a1be41a">b</a>.<a class="code" href="unionhcdma__data.html#d1238e3a2f81540362765b3e6a29d7de">ctd</a> = 0;
+<a name="l01999"></a>01999         dwc_write_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#ab2148d4b5f1bf3a2ad438e497a8b4a3">hcdma</a>, hcdma.<a class="code" href="unionhcdma__data.html#27b804015f09ea7eb25f602cc6dbdda9">d32</a>);
+<a name="l02000"></a>02000 
+<a name="l02001"></a>02001         hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">hcchar</a>);
+<a name="l02002"></a>02002         hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#9c0f515663251779e4960ec5613ce6fe">multicnt</a> = hc-&gt;multi_count;
+<a name="l02003"></a>02003         
+<a name="l02004"></a>02004 <span class="preprocessor">#ifdef DEBUG</span>
+<a name="l02005"></a>02005 <span class="preprocessor"></span>        core_if-&gt;start_hcchar_val[hc-&gt;hc_num] = hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a>;
+<a name="l02006"></a>02006         <span class="keywordflow">if</span> (hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#73c9f7f3cc4036c72ef341d1d1d9c388">chdis</a>) {
+<a name="l02007"></a>02007                 DWC_WARN(<span class="stringliteral">"%s: chdis set, channel %d, hcchar 0x%08x\n"</span>,
+<a name="l02008"></a>02008                          __func__, hc-&gt;hc_num, hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a>);
+<a name="l02009"></a>02009         }
+<a name="l02010"></a>02010 <span class="preprocessor">#endif</span>
+<a name="l02011"></a>02011 <span class="preprocessor"></span>
+<a name="l02012"></a>02012         <span class="comment">/* Set host channel enable after all other setup is complete. */</span>
+<a name="l02013"></a>02013         hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#994a5305780edb0c4fe159b6cc7b14ae">chen</a> = 1;
+<a name="l02014"></a>02014         hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#73c9f7f3cc4036c72ef341d1d1d9c388">chdis</a> = 0;
+<a name="l02015"></a>02015         
+<a name="l02016"></a>02016         dwc_write_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">hcchar</a>, hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a>);
+<a name="l02017"></a>02017 
+<a name="l02018"></a>02018         hc-&gt;xfer_started = 1;
+<a name="l02019"></a>02019         hc-&gt;requests++;
+<a name="l02020"></a>02020         
+<a name="l02021"></a>02021 <span class="preprocessor">#ifdef DEBUG</span>
+<a name="l02022"></a>02022 <span class="preprocessor"></span>        <span class="keywordflow">if</span> ((hc-&gt;ep_type != <a class="code" href="dwc__otg__cil_8h.html#1401d1264f88530232cf51ab31cc5347">DWC_OTG_EP_TYPE_INTR</a>) &amp;&amp; (hc-&gt;ep_type != <a class="code" href="dwc__otg__cil_8h.html#152a3a5e1433bd2197672f0b5105e7a4">DWC_OTG_EP_TYPE_ISOC</a>)) {
+<a name="l02023"></a>02023                 core_if-&gt;hc_xfer_info[hc-&gt;hc_num].core_if = core_if;
+<a name="l02024"></a>02024                 core_if-&gt;hc_xfer_info[hc-&gt;hc_num].hc = hc;
+<a name="l02025"></a>02025                 <span class="comment">/* Start a timer for this transfer. */</span>
+<a name="l02026"></a>02026                 DWC_TIMER_SCHEDULE(core_if-&gt;hc_xfer_timer[hc-&gt;hc_num], 10000);
+<a name="l02027"></a>02027         }
+<a name="l02028"></a>02028 
+<a name="l02029"></a>02029 <span class="preprocessor">#endif</span>
+<a name="l02030"></a>02030 <span class="preprocessor"></span>        
+<a name="l02031"></a>02031 }
+<a name="l02032"></a>02032         
+<a name="l02048"></a><a class="code" href="dwc__otg__cil_8h.html#1677ed41bf5cf0c64cdcec47265a4052">02048</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#d848c41cdd739edd9271e1e207af9c9c">dwc_otg_hc_continue_transfer</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, <a class="code" href="structdwc__hc.html">dwc_hc_t</a> * hc)
+<a name="l02049"></a>02049 {
+<a name="l02050"></a>02050         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"%s: Channel %d\n"</span>, __func__, hc-&gt;<a class="code" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">hc_num</a>);
+<a name="l02051"></a>02051 
+<a name="l02052"></a>02052         <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#4365ef67d517a621a626ac5392545c6d">do_split</a>) {
+<a name="l02053"></a>02053                 <span class="comment">/* SPLITs always queue just once per channel */</span>
+<a name="l02054"></a>02054                 <span class="keywordflow">return</span> 0;
+<a name="l02055"></a>02055         } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#513427c5e8c4603ba344d4e7f9191064">data_pid_start</a> == <a class="code" href="dwc__otg__cil_8h.html#8d329f92a5ff6f9a72fc755b6b1a4e17">DWC_OTG_HC_PID_SETUP</a>) {
+<a name="l02056"></a>02056                 <span class="comment">/* SETUPs are queued only once since they can't be NAKed. */</span>
+<a name="l02057"></a>02057                 <span class="keywordflow">return</span> 0;
+<a name="l02058"></a>02058         } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#c5088d431f5efc382121f201f5d571aa">ep_is_in</a>) {
+<a name="l02059"></a>02059                 <span class="comment">/*</span>
+<a name="l02060"></a>02060 <span class="comment">                 * Always queue another request for other IN transfers. If</span>
+<a name="l02061"></a>02061 <span class="comment">                 * back-to-back INs are issued and NAKs are received for both,</span>
+<a name="l02062"></a>02062 <span class="comment">                 * the driver may still be processing the first NAK when the</span>
+<a name="l02063"></a>02063 <span class="comment">                 * second NAK is received. When the interrupt handler clears</span>
+<a name="l02064"></a>02064 <span class="comment">                 * the NAK interrupt for the first NAK, the second NAK will</span>
+<a name="l02065"></a>02065 <span class="comment">                 * not be seen. So we can't depend on the NAK interrupt</span>
+<a name="l02066"></a>02066 <span class="comment">                 * handler to requeue a NAKed request. Instead, IN requests</span>
+<a name="l02067"></a>02067 <span class="comment">                 * are issued each time this function is called. When the</span>
+<a name="l02068"></a>02068 <span class="comment">                 * transfer completes, the extra requests for the channel will</span>
+<a name="l02069"></a>02069 <span class="comment">                 * be flushed.</span>
+<a name="l02070"></a>02070 <span class="comment">                 */</span>
+<a name="l02071"></a>02071                 <a class="code" href="unionhcchar__data.html">hcchar_data_t</a> hcchar;
+<a name="l02072"></a>02072                 <a class="code" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *hc_regs =
+<a name="l02073"></a>02073                     core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#7f7c107d4720641eb4141cd817211ac0">hc_regs</a>[hc-&gt;<a class="code" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">hc_num</a>];
+<a name="l02074"></a>02074 
+<a name="l02075"></a>02075                 hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">hcchar</a>);
+<a name="l02076"></a>02076                 <a class="code" href="dwc__otg__cil_8c.html#b2669551136671d3e4b6ad56bd947222">hc_set_even_odd_frame</a>(core_if, hc, &amp;hcchar);
+<a name="l02077"></a>02077                 hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#994a5305780edb0c4fe159b6cc7b14ae">chen</a> = 1;
+<a name="l02078"></a>02078                 hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#73c9f7f3cc4036c72ef341d1d1d9c388">chdis</a> = 0;
+<a name="l02079"></a>02079                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"  IN xfer: hcchar = 0x%08x\n"</span>,
+<a name="l02080"></a>02080                             hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a>);
+<a name="l02081"></a>02081                 dwc_write_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">hcchar</a>, hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a>);
+<a name="l02082"></a>02082                 hc-&gt;<a class="code" href="structdwc__hc.html#961e8eae7a18c503e370c4bc513d3e55">requests</a>++;
+<a name="l02083"></a>02083                 <span class="keywordflow">return</span> 1;
+<a name="l02084"></a>02084         } <span class="keywordflow">else</span> {
+<a name="l02085"></a>02085                 <span class="comment">/* OUT transfers. */</span>
+<a name="l02086"></a>02086                 <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#6199aaeab2d64954311c410b30270293">xfer_count</a> &lt; hc-&gt;<a class="code" href="structdwc__hc.html#ce32fe93214f1686896e924fbf61cac7">xfer_len</a>) {
+<a name="l02087"></a>02087                         <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#e6169fbc92e4d79686097742ad646f5c">ep_type</a> == <a class="code" href="dwc__otg__cil_8h.html#1401d1264f88530232cf51ab31cc5347">DWC_OTG_EP_TYPE_INTR</a> ||
+<a name="l02088"></a>02088                             hc-&gt;<a class="code" href="structdwc__hc.html#e6169fbc92e4d79686097742ad646f5c">ep_type</a> == <a class="code" href="dwc__otg__cil_8h.html#152a3a5e1433bd2197672f0b5105e7a4">DWC_OTG_EP_TYPE_ISOC</a>) {
+<a name="l02089"></a>02089                                 <a class="code" href="unionhcchar__data.html">hcchar_data_t</a> hcchar;
+<a name="l02090"></a>02090                                 <a class="code" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *hc_regs;
+<a name="l02091"></a>02091                                 hc_regs = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#7f7c107d4720641eb4141cd817211ac0">hc_regs</a>[hc-&gt;<a class="code" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">hc_num</a>];
+<a name="l02092"></a>02092                                 hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">hcchar</a>);
+<a name="l02093"></a>02093                                 <a class="code" href="dwc__otg__cil_8c.html#b2669551136671d3e4b6ad56bd947222">hc_set_even_odd_frame</a>(core_if, hc, &amp;hcchar);
+<a name="l02094"></a>02094                         }
+<a name="l02095"></a>02095 
+<a name="l02096"></a>02096                         <span class="comment">/* Load OUT packet into the appropriate Tx FIFO. */</span>
+<a name="l02097"></a>02097                         <a class="code" href="dwc__otg__cil_8c.html#c4ccce95ab4067e03c089519c1b54a94">dwc_otg_hc_write_packet</a>(core_if, hc);
+<a name="l02098"></a>02098                         hc-&gt;<a class="code" href="structdwc__hc.html#961e8eae7a18c503e370c4bc513d3e55">requests</a>++;
+<a name="l02099"></a>02099                         <span class="keywordflow">return</span> 1;
+<a name="l02100"></a>02100                 } <span class="keywordflow">else</span> {
+<a name="l02101"></a>02101                         <span class="keywordflow">return</span> 0;
+<a name="l02102"></a>02102                 }
+<a name="l02103"></a>02103         }
+<a name="l02104"></a>02104 }
+<a name="l02105"></a>02105 
+<a name="l02110"></a><a class="code" href="dwc__otg__cil_8h.html#ca1e0ad294962a68562280543947446e">02110</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#4185d0b9bb4a49d28894f957c2e41117">dwc_otg_hc_do_ping</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, <a class="code" href="structdwc__hc.html">dwc_hc_t</a> * hc)
+<a name="l02111"></a>02111 {
+<a name="l02112"></a>02112         <a class="code" href="unionhcchar__data.html">hcchar_data_t</a> hcchar;
+<a name="l02113"></a>02113         <a class="code" href="unionhctsiz__data.html">hctsiz_data_t</a> hctsiz;
+<a name="l02114"></a>02114         <a class="code" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *hc_regs = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#7f7c107d4720641eb4141cd817211ac0">hc_regs</a>[hc-&gt;<a class="code" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">hc_num</a>];
+<a name="l02115"></a>02115 
+<a name="l02116"></a>02116         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"%s: Channel %d\n"</span>, __func__, hc-&gt;<a class="code" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">hc_num</a>);
+<a name="l02117"></a>02117 
+<a name="l02118"></a>02118         hctsiz.<a class="code" href="unionhctsiz__data.html#fb41950555c60c6015294bdefe9cd39d">d32</a> = 0;
+<a name="l02119"></a>02119         hctsiz.<a class="code" href="unionhctsiz__data.html#8967fa90c651bce44a3cbe90c44cf638">b</a>.<a class="code" href="unionhctsiz__data.html#68625ebdd11afc0a026f41c94aedc161">dopng</a> = 1;
+<a name="l02120"></a>02120         hctsiz.<a class="code" href="unionhctsiz__data.html#8967fa90c651bce44a3cbe90c44cf638">b</a>.<a class="code" href="unionhctsiz__data.html#3ea18df5a98d33a6f8fa786252a0205b">pktcnt</a> = 1;
+<a name="l02121"></a>02121         dwc_write_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#c6173f823ba754d9f9549422b6380ca2">hctsiz</a>, hctsiz.<a class="code" href="unionhctsiz__data.html#fb41950555c60c6015294bdefe9cd39d">d32</a>);
+<a name="l02122"></a>02122 
+<a name="l02123"></a>02123         hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">hcchar</a>);
+<a name="l02124"></a>02124         hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#994a5305780edb0c4fe159b6cc7b14ae">chen</a> = 1;
+<a name="l02125"></a>02125         hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#73c9f7f3cc4036c72ef341d1d1d9c388">chdis</a> = 0;
+<a name="l02126"></a>02126         dwc_write_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">hcchar</a>, hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a>);
+<a name="l02127"></a>02127 }
+<a name="l02128"></a>02128 
+<a name="l02129"></a>02129 <span class="comment">/*</span>
+<a name="l02130"></a>02130 <span class="comment"> * This function writes a packet into the Tx FIFO associated with the Host</span>
+<a name="l02131"></a>02131 <span class="comment"> * Channel. For a channel associated with a non-periodic EP, the non-periodic</span>
+<a name="l02132"></a>02132 <span class="comment"> * Tx FIFO is written. For a channel associated with a periodic EP, the</span>
+<a name="l02133"></a>02133 <span class="comment"> * periodic Tx FIFO is written. This function should only be called in Slave</span>
+<a name="l02134"></a>02134 <span class="comment"> * mode.</span>
+<a name="l02135"></a>02135 <span class="comment"> *</span>
+<a name="l02136"></a>02136 <span class="comment"> * Upon return the xfer_buff and xfer_count fields in _hc are incremented by</span>
+<a name="l02137"></a>02137 <span class="comment"> * then number of bytes written to the Tx FIFO.</span>
+<a name="l02138"></a>02138 <span class="comment"> */</span>
+<a name="l02139"></a><a class="code" href="dwc__otg__cil_8h.html#5cc27afc02b8f7199e3cf5f02ddbdeee">02139</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#c4ccce95ab4067e03c089519c1b54a94">dwc_otg_hc_write_packet</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, <a class="code" href="structdwc__hc.html">dwc_hc_t</a> * hc)
+<a name="l02140"></a>02140 {
+<a name="l02141"></a>02141         uint32_t i;
+<a name="l02142"></a>02142         uint32_t remaining_count;
+<a name="l02143"></a>02143         uint32_t byte_count;
+<a name="l02144"></a>02144         uint32_t dword_count;
+<a name="l02145"></a>02145 
+<a name="l02146"></a>02146         uint32_t *data_buff = (uint32_t *) (hc-&gt;<a class="code" href="structdwc__hc.html#9dc781cb9e4bc639765beee37ce76673">xfer_buff</a>);
+<a name="l02147"></a>02147         uint32_t *data_fifo = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#f99c868784a8269073bc251f88d92ee4">data_fifo</a>[hc-&gt;<a class="code" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">hc_num</a>];
+<a name="l02148"></a>02148 
+<a name="l02149"></a>02149         remaining_count = hc-&gt;<a class="code" href="structdwc__hc.html#ce32fe93214f1686896e924fbf61cac7">xfer_len</a> - hc-&gt;<a class="code" href="structdwc__hc.html#6199aaeab2d64954311c410b30270293">xfer_count</a>;
+<a name="l02150"></a>02150         <span class="keywordflow">if</span> (remaining_count &gt; hc-&gt;<a class="code" href="structdwc__hc.html#bd88f02eb286ba01d8d1b049e8975ccb">max_packet</a>) {
+<a name="l02151"></a>02151                 byte_count = hc-&gt;<a class="code" href="structdwc__hc.html#bd88f02eb286ba01d8d1b049e8975ccb">max_packet</a>;
+<a name="l02152"></a>02152         } <span class="keywordflow">else</span> {
+<a name="l02153"></a>02153                 byte_count = remaining_count;
+<a name="l02154"></a>02154         }
+<a name="l02155"></a>02155 
+<a name="l02156"></a>02156         dword_count = (byte_count + 3) / 4;
+<a name="l02157"></a>02157 
+<a name="l02158"></a>02158         <span class="keywordflow">if</span> ((((<span class="keywordtype">unsigned</span> <span class="keywordtype">long</span>)data_buff) &amp; 0x3) == 0) {
+<a name="l02159"></a>02159                 <span class="comment">/* xfer_buff is DWORD aligned. */</span>
+<a name="l02160"></a>02160                 <span class="keywordflow">for</span> (i = 0; i &lt; dword_count; i++, data_buff++) {
+<a name="l02161"></a>02161                         dwc_write_reg32(data_fifo, *data_buff);
+<a name="l02162"></a>02162                 }
+<a name="l02163"></a>02163         } <span class="keywordflow">else</span> {
+<a name="l02164"></a>02164                 <span class="comment">/* xfer_buff is not DWORD aligned. */</span>
+<a name="l02165"></a>02165                 <span class="keywordflow">for</span> (i = 0; i &lt; dword_count; i++, data_buff++) {
+<a name="l02166"></a>02166                         uint32_t data;
+<a name="l02167"></a>02167                         data =
+<a name="l02168"></a>02168                             (data_buff[0] | data_buff[1] &lt;&lt; 8 | data_buff[2] &lt;&lt;
+<a name="l02169"></a>02169                              16 | data_buff[3] &lt;&lt; 24);
+<a name="l02170"></a>02170                         dwc_write_reg32(data_fifo, data);
+<a name="l02171"></a>02171                 }
+<a name="l02172"></a>02172         }
+<a name="l02173"></a>02173 
+<a name="l02174"></a>02174         hc-&gt;<a class="code" href="structdwc__hc.html#6199aaeab2d64954311c410b30270293">xfer_count</a> += byte_count;
+<a name="l02175"></a>02175         hc-&gt;<a class="code" href="structdwc__hc.html#9dc781cb9e4bc639765beee37ce76673">xfer_buff</a> += byte_count;
+<a name="l02176"></a>02176 }
+<a name="l02177"></a>02177 
+<a name="l02182"></a><a class="code" href="dwc__otg__cil_8h.html#9e8d3f050dc72eeaad2541bfd9796879">02182</a> uint32_t <a class="code" href="dwc__otg__cil_8c.html#78f20f3acf6245b189abde83d9ce78f2">dwc_otg_get_frame_number</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l02183"></a>02183 {
+<a name="l02184"></a>02184         <a class="code" href="uniondsts__data.html">dsts_data_t</a> dsts;
+<a name="l02185"></a>02185         dsts.<a class="code" href="uniondsts__data.html#0f126daef735b142b06dbc4cdbe13814">d32</a> = dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#1ed00edd20ce5db7d07666804101ec05">dsts</a>);
+<a name="l02186"></a>02186 
+<a name="l02187"></a>02187         <span class="comment">/* read current frame/microframe number from DSTS register */</span>
+<a name="l02188"></a>02188         <span class="keywordflow">return</span> dsts.<a class="code" href="uniondsts__data.html#4066fcedb7ac9a88e47aa1b2df0e89ee">b</a>.<a class="code" href="uniondsts__data.html#5a81ac4848c859cbf7d494dc345a0ce8">soffn</a>;
+<a name="l02189"></a>02189 }
+<a name="l02190"></a>02190 
+<a name="l02199"></a><a class="code" href="dwc__otg__cil_8h.html#674adeecada7af04f0d43aa819469b71">02199</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#b56e0d90c67bbf2829e630cafd630f17">dwc_otg_read_setup_packet</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, uint32_t * dest)
+<a name="l02200"></a>02200 {
+<a name="l02201"></a>02201         <span class="comment">/* Get the 8 bytes of a setup transaction data */</span>
+<a name="l02202"></a>02202 
+<a name="l02203"></a>02203         <span class="comment">/* Pop 2 DWORDS off the receive data FIFO into memory */</span>
+<a name="l02204"></a>02204         dest[0] = dwc_read_reg32(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#f99c868784a8269073bc251f88d92ee4">data_fifo</a>[0]);
+<a name="l02205"></a>02205         dest[1] = dwc_read_reg32(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#f99c868784a8269073bc251f88d92ee4">data_fifo</a>[0]);
+<a name="l02206"></a>02206 }
+<a name="l02207"></a>02207 
+<a name="l02216"></a><a class="code" href="dwc__otg__cil_8h.html#382592a5e686a82ece47d7634800aae3">02216</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#8ebf5023c783a2ec48a18a5b9aef4a87">dwc_otg_ep0_activate</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, <a class="code" href="structdwc__ep.html">dwc_ep_t</a> * <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>)
+<a name="l02217"></a>02217 {
+<a name="l02218"></a>02218         <a class="code" href="structdwc__otg__dev__if.html">dwc_otg_dev_if_t</a> *dev_if = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>;
+<a name="l02219"></a>02219         <a class="code" href="uniondsts__data.html">dsts_data_t</a> dsts;
+<a name="l02220"></a>02220         <a class="code" href="uniondepctl__data.html">depctl_data_t</a> diepctl;
+<a name="l02221"></a>02221         <a class="code" href="uniondepctl__data.html">depctl_data_t</a> doepctl;
+<a name="l02222"></a>02222         <a class="code" href="uniondctl__data.html">dctl_data_t</a> dctl = {.d32 = 0 };
+<a name="l02223"></a>02223 
+<a name="l02224"></a>02224         <span class="comment">/* Read the Device Status and Endpoint 0 Control registers */</span>
+<a name="l02225"></a>02225         dsts.<a class="code" href="uniondsts__data.html#0f126daef735b142b06dbc4cdbe13814">d32</a> = dwc_read_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#1ed00edd20ce5db7d07666804101ec05">dsts</a>);
+<a name="l02226"></a>02226         diepctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a> = dwc_read_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[0]-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#53a5adb977e2aec66d4902c6ba293216">diepctl</a>);
+<a name="l02227"></a>02227         doepctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a> = dwc_read_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">out_ep_regs</a>[0]-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#2a522b71fc97658c07debf3521f7d3e5">doepctl</a>);
+<a name="l02228"></a>02228 
+<a name="l02229"></a>02229         <span class="comment">/* Set the MPS of the IN EP based on the enumeration speed */</span>
+<a name="l02230"></a>02230         <span class="keywordflow">switch</span> (dsts.<a class="code" href="uniondsts__data.html#4066fcedb7ac9a88e47aa1b2df0e89ee">b</a>.<a class="code" href="uniondsts__data.html#f918f3d04b026687af3e1953f5c79fea">enumspd</a>) {
+<a name="l02231"></a>02231         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__regs_8h.html#2c41cb64f1ba728146bece30a622044c">DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ</a>:
+<a name="l02232"></a>02232         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__regs_8h.html#373742ad0a97af406169cc3ada63ca04">DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ</a>:
+<a name="l02233"></a>02233         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__regs_8h.html#81dafef32b78df31eb2eeac36fd0694a">DWC_DSTS_ENUMSPD_FS_PHY_48MHZ</a>:
+<a name="l02234"></a>02234                 diepctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#5899d20333186341271c2d0b7781b98c">mps</a> = <a class="code" href="dwc__otg__regs_8h.html#8ed30be9c5fc70ceb62f8e974ef5d58f">DWC_DEP0CTL_MPS_64</a>;
+<a name="l02235"></a>02235                 <span class="keywordflow">break</span>;
+<a name="l02236"></a>02236         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__regs_8h.html#7df682e9f37924c859657ff26fee5cbc">DWC_DSTS_ENUMSPD_LS_PHY_6MHZ</a>:
+<a name="l02237"></a>02237                 diepctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#5899d20333186341271c2d0b7781b98c">mps</a> = <a class="code" href="dwc__otg__regs_8h.html#3207e5140ff0395b34f637942ab5b191">DWC_DEP0CTL_MPS_8</a>;
+<a name="l02238"></a>02238                 <span class="keywordflow">break</span>;
+<a name="l02239"></a>02239         }
+<a name="l02240"></a>02240 
+<a name="l02241"></a>02241         dwc_write_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[0]-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#53a5adb977e2aec66d4902c6ba293216">diepctl</a>, diepctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a>);
+<a name="l02242"></a>02242 
+<a name="l02243"></a>02243         <span class="comment">/* Enable OUT EP for receive */</span>
+<a name="l02244"></a>02244         doepctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#337ceb41a9e0735e144e684b1f9e5368">epena</a> = 1;
+<a name="l02245"></a>02245         dwc_write_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">out_ep_regs</a>[0]-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#2a522b71fc97658c07debf3521f7d3e5">doepctl</a>, doepctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a>);
+<a name="l02246"></a>02246 
+<a name="l02247"></a>02247 <span class="preprocessor">#ifdef VERBOSE</span>
+<a name="l02248"></a>02248 <span class="preprocessor"></span>        <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"doepctl0=%0x\n"</span>,
+<a name="l02249"></a>02249                     dwc_read_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">out_ep_regs</a>[0]-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#2a522b71fc97658c07debf3521f7d3e5">doepctl</a>));
+<a name="l02250"></a>02250         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"diepctl0=%0x\n"</span>,
+<a name="l02251"></a>02251                     dwc_read_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[0]-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#53a5adb977e2aec66d4902c6ba293216">diepctl</a>));
+<a name="l02252"></a>02252 <span class="preprocessor">#endif</span>
+<a name="l02253"></a>02253 <span class="preprocessor"></span>        dctl.<a class="code" href="uniondctl__data.html#a3abfa6d609d9864f1f65712b409d4d3">b</a>.<a class="code" href="uniondctl__data.html#6feecf1184cd67b8b8ede2e2030a5dba">cgnpinnak</a> = 1;
+<a name="l02254"></a>02254 
+<a name="l02255"></a>02255         dwc_modify_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#3779c2fc508920a831a59e696a8fa785">dctl</a>, dctl.<a class="code" href="uniondctl__data.html#f49aadfd7ad95b570115b3c245b1729e">d32</a>, dctl.<a class="code" href="uniondctl__data.html#f49aadfd7ad95b570115b3c245b1729e">d32</a>);
+<a name="l02256"></a>02256         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"dctl=%0x\n"</span>,
+<a name="l02257"></a>02257                     dwc_read_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#3779c2fc508920a831a59e696a8fa785">dctl</a>));
+<a name="l02258"></a>02258 }
+<a name="l02259"></a>02259 
+<a name="l02268"></a><a class="code" href="dwc__otg__cil_8h.html#ceb07d2056baad0974dedf55cf9cab80">02268</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#5e5a1fb1ff70d5c42d8cf4a1c5d12b7f">dwc_otg_ep_activate</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, <a class="code" href="structdwc__ep.html">dwc_ep_t</a> * <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>)
+<a name="l02269"></a>02269 {
+<a name="l02270"></a>02270         <a class="code" href="structdwc__otg__dev__if.html">dwc_otg_dev_if_t</a> *dev_if = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>;
+<a name="l02271"></a>02271         <a class="code" href="uniondepctl__data.html">depctl_data_t</a> depctl;
+<a name="l02272"></a>02272         <span class="keyword">volatile</span> uint32_t *addr;
+<a name="l02273"></a>02273         <a class="code" href="uniondaint__data.html">daint_data_t</a> daintmsk = {.d32 = 0 };
+<a name="l02274"></a>02274 
+<a name="l02275"></a>02275         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"%s() EP%d-%s\n"</span>, __func__, <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;num,
+<a name="l02276"></a>02276                     (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;is_in ? <span class="stringliteral">"IN"</span> : <span class="stringliteral">"OUT"</span>));
+<a name="l02277"></a>02277 
+<a name="l02278"></a>02278         <span class="comment">/* Read DEPCTLn register */</span>
+<a name="l02279"></a>02279         <span class="keywordflow">if</span> (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;is_in == 1) {
+<a name="l02280"></a>02280                 addr = &amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;num]-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#53a5adb977e2aec66d4902c6ba293216">diepctl</a>;
+<a name="l02281"></a>02281                 daintmsk.<a class="code" href="uniondaint__data.html#5d048f0d5695317b05317d3c5ec4f79d">ep</a>.<a class="code" href="uniondaint__data.html#dbc4f689d070e6cbc112ec910f8bc36a">in</a> = 1 &lt;&lt; <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;num;
+<a name="l02282"></a>02282         } <span class="keywordflow">else</span> {
+<a name="l02283"></a>02283                 addr = &amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">out_ep_regs</a>[<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;num]-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#2a522b71fc97658c07debf3521f7d3e5">doepctl</a>;
+<a name="l02284"></a>02284                 daintmsk.<a class="code" href="uniondaint__data.html#5d048f0d5695317b05317d3c5ec4f79d">ep</a>.<a class="code" href="uniondaint__data.html#8462ad2dc1692f1253b769445382e2d4">out</a> = 1 &lt;&lt; <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;num;
+<a name="l02285"></a>02285         }
+<a name="l02286"></a>02286 
+<a name="l02287"></a>02287         <span class="comment">/* If the EP is already active don't change the EP Control</span>
+<a name="l02288"></a>02288 <span class="comment">         * register. */</span>
+<a name="l02289"></a>02289         depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a> = dwc_read_reg32(addr);
+<a name="l02290"></a>02290         <span class="keywordflow">if</span> (!depctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#2ddb1e68ac29dfc383dacd94f76b4710">usbactep</a>) {
+<a name="l02291"></a>02291                 depctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#5899d20333186341271c2d0b7781b98c">mps</a> = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;maxpacket;
+<a name="l02292"></a>02292                 depctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#f119782e7db731a3d4bf6c500b4ba5d2">eptype</a> = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;type;
+<a name="l02293"></a>02293                 depctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#89fd2f9f2183a32181e9a04bf3251c43">txfnum</a> = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;tx_fifo_num;
+<a name="l02294"></a>02294 
+<a name="l02295"></a>02295                 <span class="keywordflow">if</span> (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;type == <a class="code" href="dwc__otg__cil_8h.html#152a3a5e1433bd2197672f0b5105e7a4">DWC_OTG_EP_TYPE_ISOC</a>) {
+<a name="l02296"></a>02296                         depctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#90d89b642aafd60a6c62db5bf8396de9">setd0pid</a> = 1;  <span class="comment">// ??? </span>
+<a name="l02297"></a>02297                 } <span class="keywordflow">else</span> {
+<a name="l02298"></a>02298                         depctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#90d89b642aafd60a6c62db5bf8396de9">setd0pid</a> = 1;
+<a name="l02299"></a>02299                 }
+<a name="l02300"></a>02300                 depctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#2ddb1e68ac29dfc383dacd94f76b4710">usbactep</a> = 1;
+<a name="l02301"></a>02301 
+<a name="l02302"></a>02302                 dwc_write_reg32(addr, depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a>);
+<a name="l02303"></a>02303                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"DEPCTL=%08x\n"</span>, dwc_read_reg32(addr));
+<a name="l02304"></a>02304         }
+<a name="l02305"></a>02305 
+<a name="l02306"></a>02306         <span class="comment">/* Enable the Interrupt for this EP */</span>
+<a name="l02307"></a>02307         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5675c8d8dd7df746fda9157dc39ba5c2">multiproc_int_enable</a>) {
+<a name="l02308"></a>02308                 <span class="keywordflow">if</span> (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;is_in == 1) {
+<a name="l02309"></a>02309                         <a class="code" href="uniondiepint__data.html">diepmsk_data_t</a> diepmsk = {.d32 = 0 };
+<a name="l02310"></a>02310                         diepmsk.<a class="code" href="uniondiepint__data.html#48d2a745e0ec983a47b35b0428b0437d">b</a>.<a class="code" href="uniondiepint__data.html#56e1252841323973e0ada12cc89059c9">xfercompl</a> = 1;
+<a name="l02311"></a>02311                         diepmsk.<a class="code" href="uniondiepint__data.html#48d2a745e0ec983a47b35b0428b0437d">b</a>.<a class="code" href="uniondiepint__data.html#2513e8eef259c711e9a139cb2631b142">timeout</a> = 1;
+<a name="l02312"></a>02312                         diepmsk.<a class="code" href="uniondiepint__data.html#48d2a745e0ec983a47b35b0428b0437d">b</a>.<a class="code" href="uniondiepint__data.html#3a649b75195fb5b26135d75b03cf561d">epdisabled</a> = 1;
+<a name="l02313"></a>02313                         diepmsk.<a class="code" href="uniondiepint__data.html#48d2a745e0ec983a47b35b0428b0437d">b</a>.<a class="code" href="uniondiepint__data.html#6d57fa84f687bc4f05013c1e1a7edf29">ahberr</a> = 1;
+<a name="l02314"></a>02314                         diepmsk.<a class="code" href="uniondiepint__data.html#48d2a745e0ec983a47b35b0428b0437d">b</a>.<a class="code" href="uniondiepint__data.html#103fb29d954cf12d33f7ebe6009f9a46">intknepmis</a> = 1;
+<a name="l02315"></a>02315                         diepmsk.<a class="code" href="uniondiepint__data.html#48d2a745e0ec983a47b35b0428b0437d">b</a>.<a class="code" href="uniondiepint__data.html#90d0e6a99275eccd4a50f62644de9152">txfifoundrn</a> = 1;      <span class="comment">//?????</span>
+<a name="l02316"></a>02316 
+<a name="l02317"></a>02317                         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a>) {
+<a name="l02318"></a>02318                                 diepmsk.<a class="code" href="uniondiepint__data.html#48d2a745e0ec983a47b35b0428b0437d">b</a>.<a class="code" href="uniondiepint__data.html#2530c984ae3ebda73405d98080d8a57b">bna</a> = 1;
+<a name="l02319"></a>02319                         }
+<a name="l02320"></a>02320 <span class="comment">/*                      </span>
+<a name="l02321"></a>02321 <span class="comment">                        if(core_if-&gt;dma_enable) {</span>
+<a name="l02322"></a>02322 <span class="comment">                                doepmsk.b.nak = 1;</span>
+<a name="l02323"></a>02323 <span class="comment">                        }</span>
+<a name="l02324"></a>02324 <span class="comment">*/</span>
+<a name="l02325"></a>02325                         dwc_write_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;
+<a name="l02326"></a>02326                                         diepeachintmsk[<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;num], diepmsk.<a class="code" href="uniondiepint__data.html#7d2c24507663bf96c280c57fbf544ef7">d32</a>);
+<a name="l02327"></a>02327 
+<a name="l02328"></a>02328                 } <span class="keywordflow">else</span> {
+<a name="l02329"></a>02329                         <a class="code" href="uniondoepint__data.html">doepmsk_data_t</a> doepmsk = {.d32 = 0 };
+<a name="l02330"></a>02330                         doepmsk.<a class="code" href="uniondoepint__data.html#9e966d9f85589f278dc2c0d0c7833856">b</a>.<a class="code" href="uniondoepint__data.html#341f7ffa5a9da7f6b1e09e9f4cc516a3">xfercompl</a> = 1;
+<a name="l02331"></a>02331                         doepmsk.<a class="code" href="uniondoepint__data.html#9e966d9f85589f278dc2c0d0c7833856">b</a>.<a class="code" href="uniondoepint__data.html#cdfedbad6643d94271e91e135485a68d">ahberr</a> = 1;
+<a name="l02332"></a>02332                         doepmsk.<a class="code" href="uniondoepint__data.html#9e966d9f85589f278dc2c0d0c7833856">b</a>.<a class="code" href="uniondoepint__data.html#8a263ddc3ab9080b8c2e02ccead0c983">epdisabled</a> = 1;
+<a name="l02333"></a>02333 
+<a name="l02334"></a>02334                         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a>) {
+<a name="l02335"></a>02335                                 doepmsk.<a class="code" href="uniondoepint__data.html#9e966d9f85589f278dc2c0d0c7833856">b</a>.<a class="code" href="uniondoepint__data.html#e68e77d553158195b16a790012f9627d">bna</a> = 1;
+<a name="l02336"></a>02336                         }
+<a name="l02337"></a>02337 <span class="comment">/*                      </span>
+<a name="l02338"></a>02338 <span class="comment">                        doepmsk.b.babble = 1;</span>
+<a name="l02339"></a>02339 <span class="comment">                        doepmsk.b.nyet = 1;</span>
+<a name="l02340"></a>02340 <span class="comment">                        doepmsk.b.nak = 1;</span>
+<a name="l02341"></a>02341 <span class="comment">*/</span>
+<a name="l02342"></a>02342                         dwc_write_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;
+<a name="l02343"></a>02343                                         doepeachintmsk[<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;num], doepmsk.<a class="code" href="uniondoepint__data.html#94f8c8fc116b430565f9322e3621b3a5">d32</a>);
+<a name="l02344"></a>02344                 }
+<a name="l02345"></a>02345                 dwc_modify_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#e64a153683f0e0cda14b56a163651825">deachintmsk</a>,
+<a name="l02346"></a>02346                                  0, daintmsk.<a class="code" href="uniondaint__data.html#cf05e79bf751384bef904448a231bc41">d32</a>);
+<a name="l02347"></a>02347         } <span class="keywordflow">else</span> {
+<a name="l02348"></a>02348                 dwc_modify_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#5def6c3850c041928b9a662422ee0679">daintmsk</a>,
+<a name="l02349"></a>02349                                  0, daintmsk.<a class="code" href="uniondaint__data.html#cf05e79bf751384bef904448a231bc41">d32</a>);
+<a name="l02350"></a>02350         }
+<a name="l02351"></a>02351 
+<a name="l02352"></a>02352         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"DAINTMSK=%0x\n"</span>,
+<a name="l02353"></a>02353                     dwc_read_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#5def6c3850c041928b9a662422ee0679">daintmsk</a>));
+<a name="l02354"></a>02354 
+<a name="l02355"></a>02355         <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;stall_clear_flag = 0;
+<a name="l02356"></a>02356         <span class="keywordflow">return</span>;
+<a name="l02357"></a>02357 }
+<a name="l02358"></a>02358 
+<a name="l02367"></a><a class="code" href="dwc__otg__cil_8h.html#e813a4a71aab8a37f63790d3450367ec">02367</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#94789f2d72adb5daf65c99eadced66b3">dwc_otg_ep_deactivate</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, <a class="code" href="structdwc__ep.html">dwc_ep_t</a> * <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>)
+<a name="l02368"></a>02368 {
+<a name="l02369"></a>02369         <a class="code" href="uniondepctl__data.html">depctl_data_t</a> depctl = {.d32 = 0 };
+<a name="l02370"></a>02370         <span class="keyword">volatile</span> uint32_t *addr;
+<a name="l02371"></a>02371         <a class="code" href="uniondaint__data.html">daint_data_t</a> daintmsk = {.d32 = 0 };
+<a name="l02372"></a>02372 
+<a name="l02373"></a>02373         <span class="comment">/* Read DEPCTLn register */</span>
+<a name="l02374"></a>02374         <span class="keywordflow">if</span> (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;is_in == 1) {
+<a name="l02375"></a>02375                 addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;num]-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#53a5adb977e2aec66d4902c6ba293216">diepctl</a>;
+<a name="l02376"></a>02376                 daintmsk.<a class="code" href="uniondaint__data.html#5d048f0d5695317b05317d3c5ec4f79d">ep</a>.<a class="code" href="uniondaint__data.html#dbc4f689d070e6cbc112ec910f8bc36a">in</a> = 1 &lt;&lt; <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;num;
+<a name="l02377"></a>02377         } <span class="keywordflow">else</span> {
+<a name="l02378"></a>02378                 addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">out_ep_regs</a>[<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;num]-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#2a522b71fc97658c07debf3521f7d3e5">doepctl</a>;
+<a name="l02379"></a>02379                 daintmsk.<a class="code" href="uniondaint__data.html#5d048f0d5695317b05317d3c5ec4f79d">ep</a>.<a class="code" href="uniondaint__data.html#8462ad2dc1692f1253b769445382e2d4">out</a> = 1 &lt;&lt; <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;num;
+<a name="l02380"></a>02380         }
+<a name="l02381"></a>02381 
+<a name="l02382"></a>02382         depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a> = dwc_read_reg32(addr);
+<a name="l02383"></a>02383 
+<a name="l02384"></a>02384         depctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#2ddb1e68ac29dfc383dacd94f76b4710">usbactep</a> = 0;
+<a name="l02385"></a>02385 
+<a name="l02386"></a>02386         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a>)
+<a name="l02387"></a>02387                 depctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#4d76ba4ebd506d3175ec5cdc0d811654">epdis</a> = 1;
+<a name="l02388"></a>02388 
+<a name="l02389"></a>02389         dwc_write_reg32(addr, depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a>);
+<a name="l02390"></a>02390 
+<a name="l02391"></a>02391         <span class="comment">/* Disable the Interrupt for this EP */</span>
+<a name="l02392"></a>02392         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5675c8d8dd7df746fda9157dc39ba5c2">multiproc_int_enable</a>) {
+<a name="l02393"></a>02393                 dwc_modify_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#e64a153683f0e0cda14b56a163651825">deachintmsk</a>,
+<a name="l02394"></a>02394                                  daintmsk.<a class="code" href="uniondaint__data.html#cf05e79bf751384bef904448a231bc41">d32</a>, 0);
+<a name="l02395"></a>02395 
+<a name="l02396"></a>02396                 <span class="keywordflow">if</span> (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;is_in == 1) {
+<a name="l02397"></a>02397                         dwc_write_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;
+<a name="l02398"></a>02398                                         diepeachintmsk[<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;num], 0);
+<a name="l02399"></a>02399                 } <span class="keywordflow">else</span> {
+<a name="l02400"></a>02400                         dwc_write_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;
+<a name="l02401"></a>02401                                         doepeachintmsk[<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;num], 0);
+<a name="l02402"></a>02402                 }
+<a name="l02403"></a>02403         } <span class="keywordflow">else</span> {
+<a name="l02404"></a>02404                 dwc_modify_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#5def6c3850c041928b9a662422ee0679">daintmsk</a>,
+<a name="l02405"></a>02405                                  daintmsk.<a class="code" href="uniondaint__data.html#cf05e79bf751384bef904448a231bc41">d32</a>, 0);
+<a name="l02406"></a>02406         }
+<a name="l02407"></a>02407 }
+<a name="l02408"></a>02408 
+<a name="l02415"></a><a class="code" href="dwc__otg__cil_8c.html#50a39773d3477ca76a71787e27400d7a">02415</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#50a39773d3477ca76a71787e27400d7a">init_dma_desc_chain</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, <a class="code" href="structdwc__ep.html">dwc_ep_t</a> * <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>)
+<a name="l02416"></a>02416 {
+<a name="l02417"></a>02417         <a class="code" href="structdwc__otg__dev__dma__desc.html">dwc_otg_dev_dma_desc_t</a> *dma_desc;
+<a name="l02418"></a>02418         uint32_t offset;
+<a name="l02419"></a>02419         uint32_t xfer_est;
+<a name="l02420"></a>02420         <span class="keywordtype">int</span> i;
+<a name="l02421"></a>02421 
+<a name="l02422"></a>02422         <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;desc_cnt = (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;total_len / <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;maxxfer) +
+<a name="l02423"></a>02423             ((<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;total_len % <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;maxxfer) ? 1 : 0);
+<a name="l02424"></a>02424         <span class="keywordflow">if</span> (!<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;desc_cnt)
+<a name="l02425"></a>02425                 <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;desc_cnt = 1;
+<a name="l02426"></a>02426 
+<a name="l02427"></a>02427         dma_desc = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;desc_addr;
+<a name="l02428"></a>02428         xfer_est = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;total_len;
+<a name="l02429"></a>02429         offset = 0;
+<a name="l02430"></a>02430         <span class="keywordflow">for</span> (i = 0; i &lt; <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;desc_cnt; ++i) {
+<a name="l02432"></a>02432                 <span class="keywordflow">if</span> (xfer_est &gt; <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;maxxfer) {
+<a name="l02433"></a>02433                         dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#1876c32496f0067948f6282b7583aeab">b</a>.<a class="code" href="uniondev__dma__desc__sts.html#05d1c1d8f6c5a1967c51c5d0e2e04261">bs</a> = <a class="code" href="dwc__otg__regs_8h.html#e6e96a79797557986256d1a1ff104ca1">BS_HOST_BUSY</a>;
+<a name="l02434"></a>02434                         dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#1876c32496f0067948f6282b7583aeab">b</a>.<a class="code" href="uniondev__dma__desc__sts.html#b728a79d6a86a0d1b6426a1b2627f2c2">l</a> = 0;
+<a name="l02435"></a>02435                         dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#1876c32496f0067948f6282b7583aeab">b</a>.<a class="code" href="uniondev__dma__desc__sts.html#02c8be72ef6258c25094478c7cac0b12">ioc</a> = 0;
+<a name="l02436"></a>02436                         dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#1876c32496f0067948f6282b7583aeab">b</a>.<a class="code" href="uniondev__dma__desc__sts.html#a850ddfa13601227c05e0ae43a538a9d">sp</a> = 0;
+<a name="l02437"></a>02437                         dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#1876c32496f0067948f6282b7583aeab">b</a>.<a class="code" href="uniondev__dma__desc__sts.html#9b6181d78984cb4d853945774f300ef0">bytes</a> = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;maxxfer;
+<a name="l02438"></a>02438                         dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#0454dad420ef536fe5eb7c38ef764430">buf</a> = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;dma_addr + offset;
+<a name="l02439"></a>02439                         dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#1876c32496f0067948f6282b7583aeab">b</a>.<a class="code" href="uniondev__dma__desc__sts.html#05d1c1d8f6c5a1967c51c5d0e2e04261">bs</a> = <a class="code" href="dwc__otg__regs_8h.html#c2cfc53da94087a90d21d3528b005bcf">BS_HOST_READY</a>;
+<a name="l02440"></a>02440 
+<a name="l02441"></a>02441                         xfer_est -= <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;maxxfer;
+<a name="l02442"></a>02442                         offset += <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;maxxfer;
+<a name="l02443"></a>02443                 } <span class="keywordflow">else</span> {
+<a name="l02444"></a>02444                         dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#1876c32496f0067948f6282b7583aeab">b</a>.<a class="code" href="uniondev__dma__desc__sts.html#05d1c1d8f6c5a1967c51c5d0e2e04261">bs</a> = <a class="code" href="dwc__otg__regs_8h.html#e6e96a79797557986256d1a1ff104ca1">BS_HOST_BUSY</a>;
+<a name="l02445"></a>02445                         dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#1876c32496f0067948f6282b7583aeab">b</a>.<a class="code" href="uniondev__dma__desc__sts.html#b728a79d6a86a0d1b6426a1b2627f2c2">l</a> = 1;
+<a name="l02446"></a>02446                         dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#1876c32496f0067948f6282b7583aeab">b</a>.<a class="code" href="uniondev__dma__desc__sts.html#02c8be72ef6258c25094478c7cac0b12">ioc</a> = 1;
+<a name="l02447"></a>02447                         <span class="keywordflow">if</span> (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;is_in) {
+<a name="l02448"></a>02448                                 dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#1876c32496f0067948f6282b7583aeab">b</a>.<a class="code" href="uniondev__dma__desc__sts.html#a850ddfa13601227c05e0ae43a538a9d">sp</a> =
+<a name="l02449"></a>02449                                     (xfer_est %
+<a name="l02450"></a>02450                                      <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;maxpacket) ? 1 : ((<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;
+<a name="l02451"></a>02451                                                             sent_zlp) ? 1 : 0);
+<a name="l02452"></a>02452                                 dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#1876c32496f0067948f6282b7583aeab">b</a>.<a class="code" href="uniondev__dma__desc__sts.html#9b6181d78984cb4d853945774f300ef0">bytes</a> = xfer_est;
+<a name="l02453"></a>02453                         } <span class="keywordflow">else</span> {
+<a name="l02454"></a>02454                                 dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#1876c32496f0067948f6282b7583aeab">b</a>.<a class="code" href="uniondev__dma__desc__sts.html#9b6181d78984cb4d853945774f300ef0">bytes</a> =
+<a name="l02455"></a>02455                                     xfer_est + ((4 - (xfer_est &amp; 0x3)) &amp; 0x3);
+<a name="l02456"></a>02456                         }
+<a name="l02457"></a>02457 
+<a name="l02458"></a>02458                         dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#0454dad420ef536fe5eb7c38ef764430">buf</a> = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;dma_addr + offset;
+<a name="l02459"></a>02459                         dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#1876c32496f0067948f6282b7583aeab">b</a>.<a class="code" href="uniondev__dma__desc__sts.html#05d1c1d8f6c5a1967c51c5d0e2e04261">bs</a> = <a class="code" href="dwc__otg__regs_8h.html#c2cfc53da94087a90d21d3528b005bcf">BS_HOST_READY</a>;
+<a name="l02460"></a>02460                 }
+<a name="l02461"></a>02461                 dma_desc++;
+<a name="l02462"></a>02462         }
+<a name="l02463"></a>02463 }
+<a name="l02464"></a>02464 
+<a name="l02475"></a><a class="code" href="dwc__otg__cil_8h.html#aa731bad72017df1111f0f31bcbc7f33">02475</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#1278f6d58a4a2bc780e90e0b6c9b9a68">dwc_otg_ep_start_transfer</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, <a class="code" href="structdwc__ep.html">dwc_ep_t</a> * <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>)
+<a name="l02476"></a>02476 {
+<a name="l02477"></a>02477         <a class="code" href="uniondepctl__data.html">depctl_data_t</a> depctl;
+<a name="l02478"></a>02478         <a class="code" href="uniondeptsiz__data.html">deptsiz_data_t</a> deptsiz;
+<a name="l02479"></a>02479         <a class="code" href="uniongintmsk__data.html">gintmsk_data_t</a> intr_mask = {.d32 = 0 };
+<a name="l02480"></a>02480 
+<a name="l02481"></a>02481         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>((<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a> | <a class="code" href="dwc__otg__dbg_8h.html#daab8e158c0c530486656ef52e5b0bbe">DBG_CILV</a>), <span class="stringliteral">"%s()\n"</span>, __func__);
+<a name="l02482"></a>02482         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"ep%d-%s xfer_len=%d xfer_cnt=%d "</span>
+<a name="l02483"></a>02483                     <span class="stringliteral">"xfer_buff=%p start_xfer_buff=%p, total_len = %d\n"</span>,
+<a name="l02484"></a>02484                     <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;num, (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;is_in ? <span class="stringliteral">"IN"</span> : <span class="stringliteral">"OUT"</span>), <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_len,
+<a name="l02485"></a>02485                     <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_count, <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_buff, <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;start_xfer_buff,
+<a name="l02486"></a>02486                     <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;total_len);
+<a name="l02487"></a>02487         <span class="comment">/* IN endpoint */</span>
+<a name="l02488"></a>02488         <span class="keywordflow">if</span> (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;is_in == 1) {
+<a name="l02489"></a>02489                 <a class="code" href="structdwc__otg__dev__in__ep__regs.html">dwc_otg_dev_in_ep_regs_t</a> *in_regs =
+<a name="l02490"></a>02490                     core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;num];
+<a name="l02491"></a>02491 
+<a name="l02492"></a>02492                 <a class="code" href="uniongnptxsts__data.html">gnptxsts_data_t</a> gtxstatus;
+<a name="l02493"></a>02493 
+<a name="l02494"></a>02494                 gtxstatus.<a class="code" href="uniongnptxsts__data.html#a58b5adbe6bd0344c4f585ef6aba4672">d32</a> =
+<a name="l02495"></a>02495                     dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#57dabea6f6e0bf9e1ee8e94f55b9e465">gnptxsts</a>);
+<a name="l02496"></a>02496 
+<a name="l02497"></a>02497                 <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#31d08d1ebcd290b05139b0fcd24048ec">en_multiple_tx_fifo</a> == 0
+<a name="l02498"></a>02498                     &amp;&amp; gtxstatus.<a class="code" href="uniongnptxsts__data.html#be1d1adf7b827616ebbbf6bf564c0738">b</a>.<a class="code" href="uniongnptxsts__data.html#634ffd5e84bc422ddef043574d8f0957">nptxqspcavail</a> == 0) {
+<a name="l02499"></a>02499 <span class="preprocessor">#ifdef DEBUG</span>
+<a name="l02500"></a>02500 <span class="preprocessor"></span>                        DWC_PRINTF(<span class="stringliteral">"TX Queue Full (0x%0x)\n"</span>, gtxstatus.<a class="code" href="uniongnptxsts__data.html#a58b5adbe6bd0344c4f585ef6aba4672">d32</a>);
+<a name="l02501"></a>02501 <span class="preprocessor">#endif</span>
+<a name="l02502"></a>02502 <span class="preprocessor"></span>                        <span class="keywordflow">return</span>;
+<a name="l02503"></a>02503                 }
+<a name="l02504"></a>02504 
+<a name="l02505"></a>02505                 depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a> = dwc_read_reg32(&amp;(in_regs-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#53a5adb977e2aec66d4902c6ba293216">diepctl</a>));
+<a name="l02506"></a>02506                 deptsiz.<a class="code" href="uniondeptsiz__data.html#10c2b2ba8b419b0a766430a59befbbe0">d32</a> = dwc_read_reg32(&amp;(in_regs-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#88f637b5a4e8a0c6bc87d157072255dd">dieptsiz</a>));
+<a name="l02507"></a>02507 
+<a name="l02508"></a>02508                 <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_len += (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;maxxfer &lt; (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;total_len - <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_len)) ?
+<a name="l02509"></a>02509                     <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;maxxfer : (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;total_len - <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_len);
+<a name="l02510"></a>02510 
+<a name="l02511"></a>02511                 <span class="comment">/* Zero Length Packet? */</span>
+<a name="l02512"></a>02512                 <span class="keywordflow">if</span> ((<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_len - <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_count) == 0) {
+<a name="l02513"></a>02513                         deptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#cf06327d851e7cfe5c442b29bf2d6fa4">xfersize</a> = 0;
+<a name="l02514"></a>02514                         deptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#bbd89e812371e5b555bb82373f3643d9">pktcnt</a> = 1;
+<a name="l02515"></a>02515                 } <span class="keywordflow">else</span> {
+<a name="l02516"></a>02516                         <span class="comment">/* Program the transfer size and packet count</span>
+<a name="l02517"></a>02517 <span class="comment">                         *      as follows: xfersize = N * maxpacket +</span>
+<a name="l02518"></a>02518 <span class="comment">                         *      short_packet pktcnt = N + (short_packet</span>
+<a name="l02519"></a>02519 <span class="comment">                         *      exist ? 1 : 0)  </span>
+<a name="l02520"></a>02520 <span class="comment">                         */</span>
+<a name="l02521"></a>02521                         deptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#cf06327d851e7cfe5c442b29bf2d6fa4">xfersize</a> = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_len - <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_count;
+<a name="l02522"></a>02522                         deptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#bbd89e812371e5b555bb82373f3643d9">pktcnt</a> =
+<a name="l02523"></a>02523                             (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_len - <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_count - 1 +
+<a name="l02524"></a>02524                              <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;maxpacket) / <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;maxpacket;
+<a name="l02525"></a>02525                 }
+<a name="l02526"></a>02526 
+<a name="l02527"></a>02527                 <span class="comment">/* Write the DMA register */</span>
+<a name="l02528"></a>02528                 <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a>) {
+<a name="l02529"></a>02529                         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a> == 0) {
+<a name="l02530"></a>02530                                 dwc_write_reg32(&amp;in_regs-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#88f637b5a4e8a0c6bc87d157072255dd">dieptsiz</a>,
+<a name="l02531"></a>02531                                                 deptsiz.<a class="code" href="uniondeptsiz__data.html#10c2b2ba8b419b0a766430a59befbbe0">d32</a>);
+<a name="l02532"></a>02532                                 dwc_write_reg32(&amp;(in_regs-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#5f013840a15e0a310b8722646880a420">diepdma</a>),
+<a name="l02533"></a>02533                                                 (uint32_t) <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;dma_addr);
+<a name="l02534"></a>02534                         } <span class="keywordflow">else</span> {
+<a name="l02535"></a>02535 <span class="preprocessor">#ifdef DWC_UTE_CFI</span>
+<a name="l02536"></a>02536 <span class="preprocessor"></span>                                <span class="comment">/* The descriptor chain should be already initialized by now */</span>
+<a name="l02537"></a>02537                                 <span class="keywordflow">if</span> (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;buff_mode != BM_STANDARD) {
+<a name="l02538"></a>02538                                         dwc_write_reg32(&amp;in_regs-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#5f013840a15e0a310b8722646880a420">diepdma</a>,
+<a name="l02539"></a>02539                                                         <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;descs_dma_addr);
+<a name="l02540"></a>02540                                 } <span class="keywordflow">else</span> {
+<a name="l02541"></a>02541 <span class="preprocessor">#endif</span>
+<a name="l02542"></a>02542 <span class="preprocessor"></span>                                <a class="code" href="dwc__otg__cil_8c.html#50a39773d3477ca76a71787e27400d7a">init_dma_desc_chain</a>(core_if, <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>);
+<a name="l02544"></a>02544                                 dwc_write_reg32(&amp;in_regs-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#5f013840a15e0a310b8722646880a420">diepdma</a>,
+<a name="l02545"></a>02545                                                 <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;dma_desc_addr);
+<a name="l02546"></a>02546 <span class="preprocessor">#ifdef DWC_UTE_CFI</span>
+<a name="l02547"></a>02547 <span class="preprocessor"></span>                        }
+<a name="l02548"></a>02548 <span class="preprocessor">#endif</span>
+<a name="l02549"></a>02549 <span class="preprocessor"></span>                        }
+<a name="l02550"></a>02550                 } <span class="keywordflow">else</span> {
+<a name="l02551"></a>02551                         dwc_write_reg32(&amp;in_regs-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#88f637b5a4e8a0c6bc87d157072255dd">dieptsiz</a>, deptsiz.<a class="code" href="uniondeptsiz__data.html#10c2b2ba8b419b0a766430a59befbbe0">d32</a>);
+<a name="l02552"></a>02552                         <span class="keywordflow">if</span> (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;type != <a class="code" href="dwc__otg__cil_8h.html#152a3a5e1433bd2197672f0b5105e7a4">DWC_OTG_EP_TYPE_ISOC</a>) {
+<a name="l02558"></a>02558                                 <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#31d08d1ebcd290b05139b0fcd24048ec">en_multiple_tx_fifo</a> == 0) {
+<a name="l02559"></a>02559                                         intr_mask.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#2c395e7bef31a4d9b2d1a3257c601be4">nptxfempty</a> = 1;
+<a name="l02560"></a>02560                                         dwc_modify_reg32(&amp;core_if-&gt;
+<a name="l02561"></a>02561                                                          core_global_regs-&gt;
+<a name="l02562"></a>02562                                                          gintmsk, intr_mask.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a>,
+<a name="l02563"></a>02563                                                          intr_mask.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a>);
+<a name="l02564"></a>02564                                 } <span class="keywordflow">else</span> {
+<a name="l02565"></a>02565                                         <span class="comment">/* Enable the Tx FIFO Empty Interrupt for this EP */</span>
+<a name="l02566"></a>02566                                         <span class="keywordflow">if</span> (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_len &gt; 0) {
+<a name="l02567"></a>02567                                                 uint32_t fifoemptymsk = 0;
+<a name="l02568"></a>02568                                                 fifoemptymsk = 1 &lt;&lt; <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;num;
+<a name="l02569"></a>02569                                                 dwc_modify_reg32(&amp;core_if-&gt;
+<a name="l02570"></a>02570                                                                  dev_if-&gt;
+<a name="l02571"></a>02571                                                                  dev_global_regs-&gt;
+<a name="l02572"></a>02572                                                                  dtknqr4_fifoemptymsk,
+<a name="l02573"></a>02573                                                                  0,
+<a name="l02574"></a>02574                                                                  fifoemptymsk);
+<a name="l02575"></a>02575 
+<a name="l02576"></a>02576                                         }
+<a name="l02577"></a>02577                                 }
+<a name="l02578"></a>02578                         }
+<a name="l02579"></a>02579                 }
+<a name="l02580"></a>02580 
+<a name="l02581"></a>02581                 <span class="comment">/* EP enable, IN data in FIFO */</span>
+<a name="l02582"></a>02582                 depctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#0b87d0914ceee7a20ffd2d7510b6a72e">cnak</a> = 1;
+<a name="l02583"></a>02583                 depctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#337ceb41a9e0735e144e684b1f9e5368">epena</a> = 1;
+<a name="l02584"></a>02584                 dwc_write_reg32(&amp;in_regs-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#53a5adb977e2aec66d4902c6ba293216">diepctl</a>, depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a>);
+<a name="l02585"></a>02585 
+<a name="l02586"></a>02586                 depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a> =
+<a name="l02587"></a>02587                     dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[0]-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#53a5adb977e2aec66d4902c6ba293216">diepctl</a>);
+<a name="l02588"></a>02588                 depctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#3bdea97ec728985cbc4b9305f3ed8e96">nextep</a> = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;num;
+<a name="l02589"></a>02589                 dwc_write_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[0]-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#53a5adb977e2aec66d4902c6ba293216">diepctl</a>,
+<a name="l02590"></a>02590                                 depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a>);
+<a name="l02591"></a>02591 
+<a name="l02592"></a>02592         } <span class="keywordflow">else</span> {
+<a name="l02593"></a>02593                 <span class="comment">/* OUT endpoint */</span>
+<a name="l02594"></a>02594                 <a class="code" href="structdwc__otg__dev__out__ep__regs.html">dwc_otg_dev_out_ep_regs_t</a> *out_regs =
+<a name="l02595"></a>02595                     core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">out_ep_regs</a>[<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;num];
+<a name="l02596"></a>02596 
+<a name="l02597"></a>02597                 depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a> = dwc_read_reg32(&amp;(out_regs-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#2a522b71fc97658c07debf3521f7d3e5">doepctl</a>));
+<a name="l02598"></a>02598                 deptsiz.<a class="code" href="uniondeptsiz__data.html#10c2b2ba8b419b0a766430a59befbbe0">d32</a> = dwc_read_reg32(&amp;(out_regs-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#e756ec48787099f0a4e2ce353fce4f91">doeptsiz</a>));
+<a name="l02599"></a>02599 
+<a name="l02600"></a>02600                 <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_len += (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;maxxfer &lt; (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;total_len - <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_len)) ?
+<a name="l02601"></a>02601                     <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;maxxfer : (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;total_len - <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_len);
+<a name="l02602"></a>02602 
+<a name="l02603"></a>02603                 <span class="comment">/* Program the transfer size and packet count as follows:</span>
+<a name="l02604"></a>02604 <span class="comment">                 * </span>
+<a name="l02605"></a>02605 <span class="comment">                 *      pktcnt = N                                                                                 </span>
+<a name="l02606"></a>02606 <span class="comment">                 *      xfersize = N * maxpacket</span>
+<a name="l02607"></a>02607 <span class="comment">                 */</span>
+<a name="l02608"></a>02608                 <span class="keywordflow">if</span> ((<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_len - <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_count) == 0) {
+<a name="l02609"></a>02609                         <span class="comment">/* Zero Length Packet */</span>
+<a name="l02610"></a>02610                         deptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#cf06327d851e7cfe5c442b29bf2d6fa4">xfersize</a> = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;maxpacket;
+<a name="l02611"></a>02611                         deptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#bbd89e812371e5b555bb82373f3643d9">pktcnt</a> = 1;
+<a name="l02612"></a>02612                 } <span class="keywordflow">else</span> {
+<a name="l02613"></a>02613                         deptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#bbd89e812371e5b555bb82373f3643d9">pktcnt</a> =
+<a name="l02614"></a>02614                             (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_len - <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_count +
+<a name="l02615"></a>02615                              (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;maxpacket - 1)) / <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;maxpacket;
+<a name="l02616"></a>02616                         <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_len =
+<a name="l02617"></a>02617                             deptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#bbd89e812371e5b555bb82373f3643d9">pktcnt</a> * <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;maxpacket + <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_count;
+<a name="l02618"></a>02618                         deptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#cf06327d851e7cfe5c442b29bf2d6fa4">xfersize</a> = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_len - <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_count;
+<a name="l02619"></a>02619                 }
+<a name="l02620"></a>02620 
+<a name="l02621"></a>02621                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"ep%d xfersize=%d pktcnt=%d\n"</span>,
+<a name="l02622"></a>02622                             <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;num, deptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#cf06327d851e7cfe5c442b29bf2d6fa4">xfersize</a>, deptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#bbd89e812371e5b555bb82373f3643d9">pktcnt</a>);
+<a name="l02623"></a>02623 
+<a name="l02624"></a>02624                 <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a>) {
+<a name="l02625"></a>02625                         <span class="keywordflow">if</span> (!core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a>) {
+<a name="l02626"></a>02626                                 dwc_write_reg32(&amp;out_regs-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#e756ec48787099f0a4e2ce353fce4f91">doeptsiz</a>,
+<a name="l02627"></a>02627                                                 deptsiz.<a class="code" href="uniondeptsiz__data.html#10c2b2ba8b419b0a766430a59befbbe0">d32</a>);
+<a name="l02628"></a>02628 
+<a name="l02629"></a>02629                                 dwc_write_reg32(&amp;(out_regs-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#006071bf54bfa1c1f5e25cf4c9f65cb1">doepdma</a>),
+<a name="l02630"></a>02630                                                 (uint32_t) <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;dma_addr);
+<a name="l02631"></a>02631                         } <span class="keywordflow">else</span> {
+<a name="l02632"></a>02632 <span class="preprocessor">#ifdef DWC_UTE_CFI</span>
+<a name="l02633"></a>02633 <span class="preprocessor"></span>                                <span class="comment">/* The descriptor chain should be already initialized by now */</span>
+<a name="l02634"></a>02634                                 <span class="keywordflow">if</span> (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;buff_mode != BM_STANDARD) {
+<a name="l02635"></a>02635                                         dwc_write_reg32(&amp;out_regs-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#006071bf54bfa1c1f5e25cf4c9f65cb1">doepdma</a>,
+<a name="l02636"></a>02636                                                         <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;descs_dma_addr);
+<a name="l02637"></a>02637                                 } <span class="keywordflow">else</span> {
+<a name="l02638"></a>02638 <span class="preprocessor">#endif</span>
+<a name="l02639"></a>02639 <span class="preprocessor"></span>
+<a name="l02640"></a>02640                                 <a class="code" href="dwc__otg__cil_8c.html#50a39773d3477ca76a71787e27400d7a">init_dma_desc_chain</a>(core_if, <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>);
+<a name="l02641"></a>02641 
+<a name="l02643"></a>02643                                 dwc_write_reg32(&amp;out_regs-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#006071bf54bfa1c1f5e25cf4c9f65cb1">doepdma</a>,
+<a name="l02644"></a>02644                                                 <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;dma_desc_addr);
+<a name="l02645"></a>02645 <span class="preprocessor">#ifdef DWC_UTE_CFI</span>
+<a name="l02646"></a>02646 <span class="preprocessor"></span>                                }
+<a name="l02647"></a>02647 <span class="preprocessor">#endif</span>
+<a name="l02648"></a>02648 <span class="preprocessor"></span>                        }
+<a name="l02649"></a>02649                 } <span class="keywordflow">else</span> {
+<a name="l02650"></a>02650                         dwc_write_reg32(&amp;out_regs-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#e756ec48787099f0a4e2ce353fce4f91">doeptsiz</a>, deptsiz.<a class="code" href="uniondeptsiz__data.html#10c2b2ba8b419b0a766430a59befbbe0">d32</a>);
+<a name="l02651"></a>02651                 }
+<a name="l02652"></a>02652 
+<a name="l02653"></a>02653                 <span class="comment">/* EP enable */</span>
+<a name="l02654"></a>02654                 depctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#0b87d0914ceee7a20ffd2d7510b6a72e">cnak</a> = 1;
+<a name="l02655"></a>02655                 depctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#337ceb41a9e0735e144e684b1f9e5368">epena</a> = 1;
+<a name="l02656"></a>02656 
+<a name="l02657"></a>02657                 dwc_write_reg32(&amp;out_regs-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#2a522b71fc97658c07debf3521f7d3e5">doepctl</a>, depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a>);
+<a name="l02658"></a>02658 
+<a name="l02659"></a>02659                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"DOEPCTL=%08x DOEPTSIZ=%08x\n"</span>,
+<a name="l02660"></a>02660                             dwc_read_reg32(&amp;out_regs-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#2a522b71fc97658c07debf3521f7d3e5">doepctl</a>),
+<a name="l02661"></a>02661                             dwc_read_reg32(&amp;out_regs-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#e756ec48787099f0a4e2ce353fce4f91">doeptsiz</a>));
+<a name="l02662"></a>02662                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"DAINTMSK=%08x GINTMSK=%08x\n"</span>,
+<a name="l02663"></a>02663                             dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;
+<a name="l02664"></a>02664                                            daintmsk),
+<a name="l02665"></a>02665                             dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;
+<a name="l02666"></a>02666                                            gintmsk));
+<a name="l02667"></a>02667         }
+<a name="l02668"></a>02668 }
+<a name="l02669"></a>02669 
+<a name="l02678"></a><a class="code" href="dwc__otg__cil_8h.html#fc1d9180b7d4e894214afddde1f4397e">02678</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#fcc9f9b12c040c3649f0b8273a24ddf7">dwc_otg_ep_start_zl_transfer</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, <a class="code" href="structdwc__ep.html">dwc_ep_t</a> * <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>)
+<a name="l02679"></a>02679 {
+<a name="l02680"></a>02680 
+<a name="l02681"></a>02681         <a class="code" href="uniondepctl__data.html">depctl_data_t</a> depctl;
+<a name="l02682"></a>02682         <a class="code" href="uniondeptsiz__data.html">deptsiz_data_t</a> deptsiz;
+<a name="l02683"></a>02683         <a class="code" href="uniongintmsk__data.html">gintmsk_data_t</a> intr_mask = {.d32 = 0 };
+<a name="l02684"></a>02684 
+<a name="l02685"></a>02685         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>((<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a> | <a class="code" href="dwc__otg__dbg_8h.html#daab8e158c0c530486656ef52e5b0bbe">DBG_CILV</a>), <span class="stringliteral">"%s()\n"</span>, __func__);
+<a name="l02686"></a>02686         DWC_PRINTF(<span class="stringliteral">"zero length transfer is called\n"</span>);
+<a name="l02687"></a>02687 
+<a name="l02688"></a>02688         <span class="comment">/* IN endpoint */</span>
+<a name="l02689"></a>02689         <span class="keywordflow">if</span> (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;is_in == 1) {
+<a name="l02690"></a>02690                 <a class="code" href="structdwc__otg__dev__in__ep__regs.html">dwc_otg_dev_in_ep_regs_t</a> *in_regs =
+<a name="l02691"></a>02691                     core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;num];
+<a name="l02692"></a>02692 
+<a name="l02693"></a>02693                 depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a> = dwc_read_reg32(&amp;(in_regs-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#53a5adb977e2aec66d4902c6ba293216">diepctl</a>));
+<a name="l02694"></a>02694                 deptsiz.<a class="code" href="uniondeptsiz__data.html#10c2b2ba8b419b0a766430a59befbbe0">d32</a> = dwc_read_reg32(&amp;(in_regs-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#88f637b5a4e8a0c6bc87d157072255dd">dieptsiz</a>));
+<a name="l02695"></a>02695 
+<a name="l02696"></a>02696                 deptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#cf06327d851e7cfe5c442b29bf2d6fa4">xfersize</a> = 0;
+<a name="l02697"></a>02697                 deptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#bbd89e812371e5b555bb82373f3643d9">pktcnt</a> = 1;
+<a name="l02698"></a>02698 
+<a name="l02699"></a>02699                 <span class="comment">/* Write the DMA register */</span>
+<a name="l02700"></a>02700                 <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a>) {
+<a name="l02701"></a>02701                         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a> == 0) {
+<a name="l02702"></a>02702                                 dwc_write_reg32(&amp;in_regs-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#88f637b5a4e8a0c6bc87d157072255dd">dieptsiz</a>,
+<a name="l02703"></a>02703                                                 deptsiz.<a class="code" href="uniondeptsiz__data.html#10c2b2ba8b419b0a766430a59befbbe0">d32</a>);
+<a name="l02704"></a>02704                                 dwc_write_reg32(&amp;(in_regs-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#5f013840a15e0a310b8722646880a420">diepdma</a>),
+<a name="l02705"></a>02705                                                 (uint32_t) <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;dma_addr);
+<a name="l02706"></a>02706                         }
+<a name="l02707"></a>02707                 } <span class="keywordflow">else</span> {
+<a name="l02708"></a>02708                         dwc_write_reg32(&amp;in_regs-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#88f637b5a4e8a0c6bc87d157072255dd">dieptsiz</a>, deptsiz.<a class="code" href="uniondeptsiz__data.html#10c2b2ba8b419b0a766430a59befbbe0">d32</a>);
+<a name="l02714"></a>02714                         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#31d08d1ebcd290b05139b0fcd24048ec">en_multiple_tx_fifo</a> == 0) {
+<a name="l02715"></a>02715                                 intr_mask.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#2c395e7bef31a4d9b2d1a3257c601be4">nptxfempty</a> = 1;
+<a name="l02716"></a>02716                                 dwc_modify_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;
+<a name="l02717"></a>02717                                                  gintmsk, intr_mask.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a>,
+<a name="l02718"></a>02718                                                  intr_mask.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a>);
+<a name="l02719"></a>02719                         } <span class="keywordflow">else</span> {
+<a name="l02720"></a>02720                                 <span class="comment">/* Enable the Tx FIFO Empty Interrupt for this EP */</span>
+<a name="l02721"></a>02721                                 <span class="keywordflow">if</span> (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_len &gt; 0) {
+<a name="l02722"></a>02722                                         uint32_t fifoemptymsk = 0;
+<a name="l02723"></a>02723                                         fifoemptymsk = 1 &lt;&lt; <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;num;
+<a name="l02724"></a>02724                                         dwc_modify_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;
+<a name="l02725"></a>02725                                                          dev_global_regs-&gt;
+<a name="l02726"></a>02726                                                          dtknqr4_fifoemptymsk,
+<a name="l02727"></a>02727                                                          0, fifoemptymsk);
+<a name="l02728"></a>02728                                 }
+<a name="l02729"></a>02729                         }
+<a name="l02730"></a>02730                 }
+<a name="l02731"></a>02731 
+<a name="l02732"></a>02732                 <span class="comment">/* EP enable, IN data in FIFO */</span>
+<a name="l02733"></a>02733                 depctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#0b87d0914ceee7a20ffd2d7510b6a72e">cnak</a> = 1;
+<a name="l02734"></a>02734                 depctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#337ceb41a9e0735e144e684b1f9e5368">epena</a> = 1;
+<a name="l02735"></a>02735                 dwc_write_reg32(&amp;in_regs-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#53a5adb977e2aec66d4902c6ba293216">diepctl</a>, depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a>);
+<a name="l02736"></a>02736 
+<a name="l02737"></a>02737                 depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a> =
+<a name="l02738"></a>02738                     dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[0]-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#53a5adb977e2aec66d4902c6ba293216">diepctl</a>);
+<a name="l02739"></a>02739                 depctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#3bdea97ec728985cbc4b9305f3ed8e96">nextep</a> = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;num;
+<a name="l02740"></a>02740                 dwc_write_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[0]-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#53a5adb977e2aec66d4902c6ba293216">diepctl</a>,
+<a name="l02741"></a>02741                                 depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a>);
+<a name="l02742"></a>02742 
+<a name="l02743"></a>02743         } <span class="keywordflow">else</span> {
+<a name="l02744"></a>02744                 <span class="comment">/* OUT endpoint */</span>
+<a name="l02745"></a>02745                 <a class="code" href="structdwc__otg__dev__out__ep__regs.html">dwc_otg_dev_out_ep_regs_t</a> *out_regs =
+<a name="l02746"></a>02746                     core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">out_ep_regs</a>[<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;num];
+<a name="l02747"></a>02747 
+<a name="l02748"></a>02748                 depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a> = dwc_read_reg32(&amp;(out_regs-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#2a522b71fc97658c07debf3521f7d3e5">doepctl</a>));
+<a name="l02749"></a>02749                 deptsiz.<a class="code" href="uniondeptsiz__data.html#10c2b2ba8b419b0a766430a59befbbe0">d32</a> = dwc_read_reg32(&amp;(out_regs-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#e756ec48787099f0a4e2ce353fce4f91">doeptsiz</a>));
+<a name="l02750"></a>02750 
+<a name="l02751"></a>02751                 <span class="comment">/* Zero Length Packet */</span>
+<a name="l02752"></a>02752                 deptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#cf06327d851e7cfe5c442b29bf2d6fa4">xfersize</a> = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;maxpacket;
+<a name="l02753"></a>02753                 deptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#bbd89e812371e5b555bb82373f3643d9">pktcnt</a> = 1;
+<a name="l02754"></a>02754 
+<a name="l02755"></a>02755                 <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a>) {
+<a name="l02756"></a>02756                         <span class="keywordflow">if</span> (!core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a>) {
+<a name="l02757"></a>02757                                 dwc_write_reg32(&amp;out_regs-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#e756ec48787099f0a4e2ce353fce4f91">doeptsiz</a>,
+<a name="l02758"></a>02758                                                 deptsiz.<a class="code" href="uniondeptsiz__data.html#10c2b2ba8b419b0a766430a59befbbe0">d32</a>);
+<a name="l02759"></a>02759 
+<a name="l02760"></a>02760                                 dwc_write_reg32(&amp;(out_regs-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#006071bf54bfa1c1f5e25cf4c9f65cb1">doepdma</a>),
+<a name="l02761"></a>02761                                                 (uint32_t) <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;dma_addr);
+<a name="l02762"></a>02762                         }
+<a name="l02763"></a>02763                 } <span class="keywordflow">else</span> {
+<a name="l02764"></a>02764                         dwc_write_reg32(&amp;out_regs-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#e756ec48787099f0a4e2ce353fce4f91">doeptsiz</a>, deptsiz.<a class="code" href="uniondeptsiz__data.html#10c2b2ba8b419b0a766430a59befbbe0">d32</a>);
+<a name="l02765"></a>02765                 }
+<a name="l02766"></a>02766 
+<a name="l02767"></a>02767                 <span class="comment">/* EP enable */</span>
+<a name="l02768"></a>02768                 depctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#0b87d0914ceee7a20ffd2d7510b6a72e">cnak</a> = 1;
+<a name="l02769"></a>02769                 depctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#337ceb41a9e0735e144e684b1f9e5368">epena</a> = 1;
+<a name="l02770"></a>02770 
+<a name="l02771"></a>02771                 dwc_write_reg32(&amp;out_regs-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#2a522b71fc97658c07debf3521f7d3e5">doepctl</a>, depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a>);
+<a name="l02772"></a>02772 
+<a name="l02773"></a>02773         }
+<a name="l02774"></a>02774 }
+<a name="l02775"></a>02775 
+<a name="l02785"></a><a class="code" href="dwc__otg__cil_8h.html#d4a111ecd96bec3afd3b7c0421af9652">02785</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#ee4989b24826b2a6592535282853e556">dwc_otg_ep0_start_transfer</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, <a class="code" href="structdwc__ep.html">dwc_ep_t</a> * <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>)
+<a name="l02786"></a>02786 {
+<a name="l02787"></a>02787         <a class="code" href="uniondepctl__data.html">depctl_data_t</a> depctl;
+<a name="l02788"></a>02788         <a class="code" href="uniondeptsiz0__data.html">deptsiz0_data_t</a> deptsiz;
+<a name="l02789"></a>02789         <a class="code" href="uniongintmsk__data.html">gintmsk_data_t</a> intr_mask = {.d32 = 0 };
+<a name="l02790"></a>02790         <a class="code" href="structdwc__otg__dev__dma__desc.html">dwc_otg_dev_dma_desc_t</a> *dma_desc;
+<a name="l02791"></a>02791 
+<a name="l02792"></a>02792         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"ep%d-%s xfer_len=%d xfer_cnt=%d "</span>
+<a name="l02793"></a>02793                     <span class="stringliteral">"xfer_buff=%p start_xfer_buff=%p \n"</span>,
+<a name="l02794"></a>02794                     <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;num, (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;is_in ? <span class="stringliteral">"IN"</span> : <span class="stringliteral">"OUT"</span>), <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_len,
+<a name="l02795"></a>02795                     <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_count, <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_buff, <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;start_xfer_buff);
+<a name="l02796"></a>02796 
+<a name="l02797"></a>02797         <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;total_len = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_len;
+<a name="l02798"></a>02798 
+<a name="l02799"></a>02799         <span class="comment">/* IN endpoint */</span>
+<a name="l02800"></a>02800         <span class="keywordflow">if</span> (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;is_in == 1) {
+<a name="l02801"></a>02801                 <a class="code" href="structdwc__otg__dev__in__ep__regs.html">dwc_otg_dev_in_ep_regs_t</a> *in_regs =
+<a name="l02802"></a>02802                     core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[0];
+<a name="l02803"></a>02803 
+<a name="l02804"></a>02804                 <a class="code" href="uniongnptxsts__data.html">gnptxsts_data_t</a> gtxstatus;
+<a name="l02805"></a>02805 
+<a name="l02806"></a>02806                 gtxstatus.<a class="code" href="uniongnptxsts__data.html#a58b5adbe6bd0344c4f585ef6aba4672">d32</a> =
+<a name="l02807"></a>02807                     dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#57dabea6f6e0bf9e1ee8e94f55b9e465">gnptxsts</a>);
+<a name="l02808"></a>02808 
+<a name="l02809"></a>02809                 <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#31d08d1ebcd290b05139b0fcd24048ec">en_multiple_tx_fifo</a> == 0
+<a name="l02810"></a>02810                     &amp;&amp; gtxstatus.<a class="code" href="uniongnptxsts__data.html#be1d1adf7b827616ebbbf6bf564c0738">b</a>.<a class="code" href="uniongnptxsts__data.html#634ffd5e84bc422ddef043574d8f0957">nptxqspcavail</a> == 0) {
+<a name="l02811"></a>02811 <span class="preprocessor">#ifdef DEBUG</span>
+<a name="l02812"></a>02812 <span class="preprocessor"></span>                        deptsiz.<a class="code" href="uniondeptsiz0__data.html#a06fa9b1dcaee47fba9cf869027ed6f1">d32</a> = dwc_read_reg32(&amp;in_regs-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#88f637b5a4e8a0c6bc87d157072255dd">dieptsiz</a>);
+<a name="l02813"></a>02813                         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"DIEPCTL0=%0x\n"</span>,
+<a name="l02814"></a>02814                                     dwc_read_reg32(&amp;in_regs-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#53a5adb977e2aec66d4902c6ba293216">diepctl</a>));
+<a name="l02815"></a>02815                         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"DIEPTSIZ0=%0x (sz=%d, pcnt=%d)\n"</span>,
+<a name="l02816"></a>02816                                     deptsiz.<a class="code" href="uniondeptsiz0__data.html#a06fa9b1dcaee47fba9cf869027ed6f1">d32</a>,
+<a name="l02817"></a>02817                                     deptsiz.<a class="code" href="uniondeptsiz0__data.html#8e50594573fd774fc3e27404d8b1f59c">b</a>.<a class="code" href="uniondeptsiz0__data.html#1792e672dde70ead19bd0f5e7642af03">xfersize</a>, deptsiz.<a class="code" href="uniondeptsiz0__data.html#8e50594573fd774fc3e27404d8b1f59c">b</a>.<a class="code" href="uniondeptsiz0__data.html#debb8f273e4480cde57bef7677697bd0">pktcnt</a>);
+<a name="l02818"></a>02818                         DWC_PRINTF(<span class="stringliteral">"TX Queue or FIFO Full (0x%0x)\n"</span>,
+<a name="l02819"></a>02819                                    gtxstatus.<a class="code" href="uniongnptxsts__data.html#a58b5adbe6bd0344c4f585ef6aba4672">d32</a>);
+<a name="l02820"></a>02820 <span class="preprocessor">#endif</span>
+<a name="l02821"></a>02821 <span class="preprocessor"></span>                        <span class="keywordflow">return</span>;
+<a name="l02822"></a>02822                 }
+<a name="l02823"></a>02823 
+<a name="l02824"></a>02824                 depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a> = dwc_read_reg32(&amp;in_regs-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#53a5adb977e2aec66d4902c6ba293216">diepctl</a>);
+<a name="l02825"></a>02825                 deptsiz.<a class="code" href="uniondeptsiz0__data.html#a06fa9b1dcaee47fba9cf869027ed6f1">d32</a> = dwc_read_reg32(&amp;in_regs-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#88f637b5a4e8a0c6bc87d157072255dd">dieptsiz</a>);
+<a name="l02826"></a>02826 
+<a name="l02827"></a>02827                 <span class="comment">/* Zero Length Packet? */</span>
+<a name="l02828"></a>02828                 <span class="keywordflow">if</span> (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_len == 0) {
+<a name="l02829"></a>02829                         deptsiz.<a class="code" href="uniondeptsiz0__data.html#8e50594573fd774fc3e27404d8b1f59c">b</a>.<a class="code" href="uniondeptsiz0__data.html#1792e672dde70ead19bd0f5e7642af03">xfersize</a> = 0;
+<a name="l02830"></a>02830                         deptsiz.<a class="code" href="uniondeptsiz0__data.html#8e50594573fd774fc3e27404d8b1f59c">b</a>.<a class="code" href="uniondeptsiz0__data.html#debb8f273e4480cde57bef7677697bd0">pktcnt</a> = 1;
+<a name="l02831"></a>02831                 } <span class="keywordflow">else</span> {
+<a name="l02832"></a>02832                         <span class="comment">/* Program the transfer size and packet count</span>
+<a name="l02833"></a>02833 <span class="comment">                         *      as follows: xfersize = N * maxpacket +</span>
+<a name="l02834"></a>02834 <span class="comment">                         *      short_packet pktcnt = N + (short_packet</span>
+<a name="l02835"></a>02835 <span class="comment">                         *      exist ? 1 : 0)  </span>
+<a name="l02836"></a>02836 <span class="comment">                         */</span>
+<a name="l02837"></a>02837                         <span class="keywordflow">if</span> (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_len &gt; <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;maxpacket) {
+<a name="l02838"></a>02838                                 <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_len = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;maxpacket;
+<a name="l02839"></a>02839                                 deptsiz.<a class="code" href="uniondeptsiz0__data.html#8e50594573fd774fc3e27404d8b1f59c">b</a>.<a class="code" href="uniondeptsiz0__data.html#1792e672dde70ead19bd0f5e7642af03">xfersize</a> = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;maxpacket;
+<a name="l02840"></a>02840                         } <span class="keywordflow">else</span> {
+<a name="l02841"></a>02841                                 deptsiz.<a class="code" href="uniondeptsiz0__data.html#8e50594573fd774fc3e27404d8b1f59c">b</a>.<a class="code" href="uniondeptsiz0__data.html#1792e672dde70ead19bd0f5e7642af03">xfersize</a> = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_len;
+<a name="l02842"></a>02842                         }
+<a name="l02843"></a>02843                         deptsiz.<a class="code" href="uniondeptsiz0__data.html#8e50594573fd774fc3e27404d8b1f59c">b</a>.<a class="code" href="uniondeptsiz0__data.html#debb8f273e4480cde57bef7677697bd0">pktcnt</a> = 1;
+<a name="l02844"></a>02844 
+<a name="l02845"></a>02845                 }
+<a name="l02846"></a>02846                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>,
+<a name="l02847"></a>02847                             <span class="stringliteral">"IN len=%d  xfersize=%d pktcnt=%d [%08x]\n"</span>,
+<a name="l02848"></a>02848                             <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_len, deptsiz.<a class="code" href="uniondeptsiz0__data.html#8e50594573fd774fc3e27404d8b1f59c">b</a>.<a class="code" href="uniondeptsiz0__data.html#1792e672dde70ead19bd0f5e7642af03">xfersize</a>, deptsiz.<a class="code" href="uniondeptsiz0__data.html#8e50594573fd774fc3e27404d8b1f59c">b</a>.<a class="code" href="uniondeptsiz0__data.html#debb8f273e4480cde57bef7677697bd0">pktcnt</a>,
+<a name="l02849"></a>02849                             deptsiz.<a class="code" href="uniondeptsiz0__data.html#a06fa9b1dcaee47fba9cf869027ed6f1">d32</a>);
+<a name="l02850"></a>02850 
+<a name="l02851"></a>02851                 <span class="comment">/* Write the DMA register */</span>
+<a name="l02852"></a>02852                 <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a>) {
+<a name="l02853"></a>02853                         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a> == 0) {
+<a name="l02854"></a>02854                                 dwc_write_reg32(&amp;in_regs-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#88f637b5a4e8a0c6bc87d157072255dd">dieptsiz</a>,
+<a name="l02855"></a>02855                                                 deptsiz.<a class="code" href="uniondeptsiz0__data.html#a06fa9b1dcaee47fba9cf869027ed6f1">d32</a>);
+<a name="l02856"></a>02856 
+<a name="l02857"></a>02857                                 dwc_write_reg32(&amp;(in_regs-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#5f013840a15e0a310b8722646880a420">diepdma</a>),
+<a name="l02858"></a>02858                                                 (uint32_t) <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;dma_addr);
+<a name="l02859"></a>02859                         } <span class="keywordflow">else</span> {
+<a name="l02860"></a>02860                                 dma_desc = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#99f44e328bbb4401aabd8e2708853238">in_desc_addr</a>;
+<a name="l02861"></a>02861 
+<a name="l02863"></a>02863                                 dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#1876c32496f0067948f6282b7583aeab">b</a>.<a class="code" href="uniondev__dma__desc__sts.html#05d1c1d8f6c5a1967c51c5d0e2e04261">bs</a> = <a class="code" href="dwc__otg__regs_8h.html#e6e96a79797557986256d1a1ff104ca1">BS_HOST_BUSY</a>;
+<a name="l02864"></a>02864                                 dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#1876c32496f0067948f6282b7583aeab">b</a>.<a class="code" href="uniondev__dma__desc__sts.html#b728a79d6a86a0d1b6426a1b2627f2c2">l</a> = 1;
+<a name="l02865"></a>02865                                 dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#1876c32496f0067948f6282b7583aeab">b</a>.<a class="code" href="uniondev__dma__desc__sts.html#02c8be72ef6258c25094478c7cac0b12">ioc</a> = 1;
+<a name="l02866"></a>02866                                 dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#1876c32496f0067948f6282b7583aeab">b</a>.<a class="code" href="uniondev__dma__desc__sts.html#a850ddfa13601227c05e0ae43a538a9d">sp</a> =
+<a name="l02867"></a>02867                                     (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_len == <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;maxpacket) ? 0 : 1;
+<a name="l02868"></a>02868                                 dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#1876c32496f0067948f6282b7583aeab">b</a>.<a class="code" href="uniondev__dma__desc__sts.html#9b6181d78984cb4d853945774f300ef0">bytes</a> = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_len;
+<a name="l02869"></a>02869                                 dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#0454dad420ef536fe5eb7c38ef764430">buf</a> = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;dma_addr;
+<a name="l02870"></a>02870                                 dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#1876c32496f0067948f6282b7583aeab">b</a>.<a class="code" href="uniondev__dma__desc__sts.html#05d1c1d8f6c5a1967c51c5d0e2e04261">bs</a> = <a class="code" href="dwc__otg__regs_8h.html#c2cfc53da94087a90d21d3528b005bcf">BS_HOST_READY</a>;
+<a name="l02871"></a>02871 
+<a name="l02873"></a>02873                                 dwc_write_reg32(&amp;in_regs-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#5f013840a15e0a310b8722646880a420">diepdma</a>,
+<a name="l02874"></a>02874                                                 core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;
+<a name="l02875"></a>02875                                                 dma_in_desc_addr);
+<a name="l02876"></a>02876                         }
+<a name="l02877"></a>02877                 } <span class="keywordflow">else</span> {
+<a name="l02878"></a>02878                         dwc_write_reg32(&amp;in_regs-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#88f637b5a4e8a0c6bc87d157072255dd">dieptsiz</a>, deptsiz.<a class="code" href="uniondeptsiz0__data.html#a06fa9b1dcaee47fba9cf869027ed6f1">d32</a>);
+<a name="l02879"></a>02879                 }
+<a name="l02880"></a>02880 
+<a name="l02881"></a>02881                 <span class="comment">/* EP enable, IN data in FIFO */</span>
+<a name="l02882"></a>02882                 depctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#0b87d0914ceee7a20ffd2d7510b6a72e">cnak</a> = 1;
+<a name="l02883"></a>02883                 depctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#337ceb41a9e0735e144e684b1f9e5368">epena</a> = 1;
+<a name="l02884"></a>02884                 dwc_write_reg32(&amp;in_regs-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#53a5adb977e2aec66d4902c6ba293216">diepctl</a>, depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a>);
+<a name="l02885"></a>02885 
+<a name="l02890"></a>02890                 <span class="keywordflow">if</span> (!core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a>) {
+<a name="l02891"></a>02891                         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#31d08d1ebcd290b05139b0fcd24048ec">en_multiple_tx_fifo</a> == 0) {
+<a name="l02892"></a>02892                                 intr_mask.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#2c395e7bef31a4d9b2d1a3257c601be4">nptxfempty</a> = 1;
+<a name="l02893"></a>02893                                 dwc_modify_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;
+<a name="l02894"></a>02894                                                  gintmsk, intr_mask.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a>,
+<a name="l02895"></a>02895                                                  intr_mask.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a>);
+<a name="l02896"></a>02896                         } <span class="keywordflow">else</span> {
+<a name="l02897"></a>02897                                 <span class="comment">/* Enable the Tx FIFO Empty Interrupt for this EP */</span>
+<a name="l02898"></a>02898                                 <span class="keywordflow">if</span> (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_len &gt; 0) {
+<a name="l02899"></a>02899                                         uint32_t fifoemptymsk = 0;
+<a name="l02900"></a>02900                                         fifoemptymsk |= 1 &lt;&lt; <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;num;
+<a name="l02901"></a>02901                                         dwc_modify_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;
+<a name="l02902"></a>02902                                                          dev_global_regs-&gt;
+<a name="l02903"></a>02903                                                          dtknqr4_fifoemptymsk,
+<a name="l02904"></a>02904                                                          0, fifoemptymsk);
+<a name="l02905"></a>02905                                 }
+<a name="l02906"></a>02906                         }
+<a name="l02907"></a>02907                 }
+<a name="l02908"></a>02908         } <span class="keywordflow">else</span> {
+<a name="l02909"></a>02909                 <span class="comment">/* OUT endpoint */</span>
+<a name="l02910"></a>02910                 <a class="code" href="structdwc__otg__dev__out__ep__regs.html">dwc_otg_dev_out_ep_regs_t</a> *out_regs =
+<a name="l02911"></a>02911                     core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">out_ep_regs</a>[0];
+<a name="l02912"></a>02912 
+<a name="l02913"></a>02913                 depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a> = dwc_read_reg32(&amp;out_regs-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#2a522b71fc97658c07debf3521f7d3e5">doepctl</a>);
+<a name="l02914"></a>02914                 deptsiz.<a class="code" href="uniondeptsiz0__data.html#a06fa9b1dcaee47fba9cf869027ed6f1">d32</a> = dwc_read_reg32(&amp;out_regs-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#e756ec48787099f0a4e2ce353fce4f91">doeptsiz</a>);
+<a name="l02915"></a>02915 
+<a name="l02916"></a>02916                 <span class="comment">/* Program the transfer size and packet count as follows:</span>
+<a name="l02917"></a>02917 <span class="comment">                 *      xfersize = N * (maxpacket + 4 - (maxpacket % 4))</span>
+<a name="l02918"></a>02918 <span class="comment">                 *      pktcnt = N                                                                                      */</span>
+<a name="l02919"></a>02919                 <span class="comment">/* Zero Length Packet */</span>
+<a name="l02920"></a>02920                 deptsiz.<a class="code" href="uniondeptsiz0__data.html#8e50594573fd774fc3e27404d8b1f59c">b</a>.<a class="code" href="uniondeptsiz0__data.html#1792e672dde70ead19bd0f5e7642af03">xfersize</a> = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;maxpacket;
+<a name="l02921"></a>02921                 deptsiz.<a class="code" href="uniondeptsiz0__data.html#8e50594573fd774fc3e27404d8b1f59c">b</a>.<a class="code" href="uniondeptsiz0__data.html#debb8f273e4480cde57bef7677697bd0">pktcnt</a> = 1;
+<a name="l02922"></a>02922 
+<a name="l02923"></a>02923                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"len=%d  xfersize=%d pktcnt=%d\n"</span>,
+<a name="l02924"></a>02924                             <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_len, deptsiz.<a class="code" href="uniondeptsiz0__data.html#8e50594573fd774fc3e27404d8b1f59c">b</a>.<a class="code" href="uniondeptsiz0__data.html#1792e672dde70ead19bd0f5e7642af03">xfersize</a>, deptsiz.<a class="code" href="uniondeptsiz0__data.html#8e50594573fd774fc3e27404d8b1f59c">b</a>.<a class="code" href="uniondeptsiz0__data.html#debb8f273e4480cde57bef7677697bd0">pktcnt</a>);
+<a name="l02925"></a>02925 
+<a name="l02926"></a>02926                 <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a>) {
+<a name="l02927"></a>02927                         <span class="keywordflow">if</span> (!core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a>) {
+<a name="l02928"></a>02928                                 dwc_write_reg32(&amp;out_regs-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#e756ec48787099f0a4e2ce353fce4f91">doeptsiz</a>,
+<a name="l02929"></a>02929                                                 deptsiz.<a class="code" href="uniondeptsiz0__data.html#a06fa9b1dcaee47fba9cf869027ed6f1">d32</a>);
+<a name="l02930"></a>02930 
+<a name="l02931"></a>02931                                 dwc_write_reg32(&amp;(out_regs-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#006071bf54bfa1c1f5e25cf4c9f65cb1">doepdma</a>),
+<a name="l02932"></a>02932                                                 (uint32_t) <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;dma_addr);
+<a name="l02933"></a>02933                         } <span class="keywordflow">else</span> {
+<a name="l02934"></a>02934                                 dma_desc = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#8cc9be8ccaba2ef93b02b34ba7b26bad">out_desc_addr</a>;
+<a name="l02935"></a>02935 
+<a name="l02937"></a>02937                                 dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#1876c32496f0067948f6282b7583aeab">b</a>.<a class="code" href="uniondev__dma__desc__sts.html#05d1c1d8f6c5a1967c51c5d0e2e04261">bs</a> = <a class="code" href="dwc__otg__regs_8h.html#e6e96a79797557986256d1a1ff104ca1">BS_HOST_BUSY</a>;
+<a name="l02938"></a>02938                                 dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#1876c32496f0067948f6282b7583aeab">b</a>.<a class="code" href="uniondev__dma__desc__sts.html#b728a79d6a86a0d1b6426a1b2627f2c2">l</a> = 1;
+<a name="l02939"></a>02939                                 dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#1876c32496f0067948f6282b7583aeab">b</a>.<a class="code" href="uniondev__dma__desc__sts.html#02c8be72ef6258c25094478c7cac0b12">ioc</a> = 1;
+<a name="l02940"></a>02940                                 dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#1876c32496f0067948f6282b7583aeab">b</a>.<a class="code" href="uniondev__dma__desc__sts.html#9b6181d78984cb4d853945774f300ef0">bytes</a> = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;maxpacket;
+<a name="l02941"></a>02941                                 dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#0454dad420ef536fe5eb7c38ef764430">buf</a> = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;dma_addr;
+<a name="l02942"></a>02942                                 dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#1876c32496f0067948f6282b7583aeab">b</a>.<a class="code" href="uniondev__dma__desc__sts.html#05d1c1d8f6c5a1967c51c5d0e2e04261">bs</a> = <a class="code" href="dwc__otg__regs_8h.html#c2cfc53da94087a90d21d3528b005bcf">BS_HOST_READY</a>;
+<a name="l02943"></a>02943 
+<a name="l02945"></a>02945                                 dwc_write_reg32(&amp;out_regs-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#006071bf54bfa1c1f5e25cf4c9f65cb1">doepdma</a>,
+<a name="l02946"></a>02946                                                 core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;
+<a name="l02947"></a>02947                                                 dma_out_desc_addr);
+<a name="l02948"></a>02948                         }
+<a name="l02949"></a>02949                 } <span class="keywordflow">else</span> {
+<a name="l02950"></a>02950                         dwc_write_reg32(&amp;out_regs-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#e756ec48787099f0a4e2ce353fce4f91">doeptsiz</a>, deptsiz.<a class="code" href="uniondeptsiz0__data.html#a06fa9b1dcaee47fba9cf869027ed6f1">d32</a>);
+<a name="l02951"></a>02951                 }
+<a name="l02952"></a>02952 
+<a name="l02953"></a>02953                 <span class="comment">/* EP enable */</span>
+<a name="l02954"></a>02954                 depctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#0b87d0914ceee7a20ffd2d7510b6a72e">cnak</a> = 1;
+<a name="l02955"></a>02955                 depctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#337ceb41a9e0735e144e684b1f9e5368">epena</a> = 1;
+<a name="l02956"></a>02956                 dwc_write_reg32(&amp;(out_regs-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#2a522b71fc97658c07debf3521f7d3e5">doepctl</a>), depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a>);
+<a name="l02957"></a>02957         }
+<a name="l02958"></a>02958 }
+<a name="l02959"></a>02959 
+<a name="l02969"></a><a class="code" href="dwc__otg__cil_8h.html#e52e9ca5ecba4797f51be5e30f1c6fbc">02969</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#d8c1e6f7860c482df84db003b52c369c">dwc_otg_ep0_continue_transfer</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, <a class="code" href="structdwc__ep.html">dwc_ep_t</a> * <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>)
+<a name="l02970"></a>02970 {
+<a name="l02971"></a>02971         <a class="code" href="uniondepctl__data.html">depctl_data_t</a> depctl;
+<a name="l02972"></a>02972         <a class="code" href="uniondeptsiz0__data.html">deptsiz0_data_t</a> deptsiz;
+<a name="l02973"></a>02973         <a class="code" href="uniongintmsk__data.html">gintmsk_data_t</a> intr_mask = {.d32 = 0 };
+<a name="l02974"></a>02974         <a class="code" href="structdwc__otg__dev__dma__desc.html">dwc_otg_dev_dma_desc_t</a> *dma_desc;
+<a name="l02975"></a>02975 
+<a name="l02976"></a>02976         <span class="keywordflow">if</span> (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;is_in == 1) {
+<a name="l02977"></a>02977                 <a class="code" href="structdwc__otg__dev__in__ep__regs.html">dwc_otg_dev_in_ep_regs_t</a> *in_regs =
+<a name="l02978"></a>02978                     core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[0];
+<a name="l02979"></a>02979                 <a class="code" href="uniongnptxsts__data.html">gnptxsts_data_t</a> tx_status = {.d32 = 0 };
+<a name="l02980"></a>02980 
+<a name="l02981"></a>02981                 tx_status.<a class="code" href="uniongnptxsts__data.html#a58b5adbe6bd0344c4f585ef6aba4672">d32</a> =
+<a name="l02982"></a>02982                     dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#57dabea6f6e0bf9e1ee8e94f55b9e465">gnptxsts</a>);
+<a name="l02986"></a>02986                 depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a> = dwc_read_reg32(&amp;in_regs-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#53a5adb977e2aec66d4902c6ba293216">diepctl</a>);
+<a name="l02987"></a>02987                 deptsiz.<a class="code" href="uniondeptsiz0__data.html#a06fa9b1dcaee47fba9cf869027ed6f1">d32</a> = dwc_read_reg32(&amp;in_regs-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#88f637b5a4e8a0c6bc87d157072255dd">dieptsiz</a>);
+<a name="l02988"></a>02988 
+<a name="l02989"></a>02989                 <span class="comment">/* Program the transfer size and packet count</span>
+<a name="l02990"></a>02990 <span class="comment">                 *      as follows: xfersize = N * maxpacket +</span>
+<a name="l02991"></a>02991 <span class="comment">                 *      short_packet pktcnt = N + (short_packet</span>
+<a name="l02992"></a>02992 <span class="comment">                 *      exist ? 1 : 0)  </span>
+<a name="l02993"></a>02993 <span class="comment">                 */</span>
+<a name="l02994"></a>02994 
+<a name="l02995"></a>02995                 <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a> == 0) {
+<a name="l02996"></a>02996                         deptsiz.<a class="code" href="uniondeptsiz0__data.html#8e50594573fd774fc3e27404d8b1f59c">b</a>.<a class="code" href="uniondeptsiz0__data.html#1792e672dde70ead19bd0f5e7642af03">xfersize</a> =
+<a name="l02997"></a>02997                             (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;total_len - <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_count) &gt;
+<a name="l02998"></a>02998                             <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;maxpacket ? <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;maxpacket : (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;total_len -
+<a name="l02999"></a>02999                                                              <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_count);
+<a name="l03000"></a>03000                         deptsiz.<a class="code" href="uniondeptsiz0__data.html#8e50594573fd774fc3e27404d8b1f59c">b</a>.<a class="code" href="uniondeptsiz0__data.html#debb8f273e4480cde57bef7677697bd0">pktcnt</a> = 1;
+<a name="l03001"></a>03001                         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a> == 0) {
+<a name="l03002"></a>03002                                 <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_len += deptsiz.<a class="code" href="uniondeptsiz0__data.html#8e50594573fd774fc3e27404d8b1f59c">b</a>.<a class="code" href="uniondeptsiz0__data.html#1792e672dde70ead19bd0f5e7642af03">xfersize</a>;
+<a name="l03003"></a>03003                         } <span class="keywordflow">else</span> {
+<a name="l03004"></a>03004                                 <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_len = deptsiz.<a class="code" href="uniondeptsiz0__data.html#8e50594573fd774fc3e27404d8b1f59c">b</a>.<a class="code" href="uniondeptsiz0__data.html#1792e672dde70ead19bd0f5e7642af03">xfersize</a>;
+<a name="l03005"></a>03005                         }
+<a name="l03006"></a>03006                         dwc_write_reg32(&amp;in_regs-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#88f637b5a4e8a0c6bc87d157072255dd">dieptsiz</a>, deptsiz.<a class="code" href="uniondeptsiz0__data.html#a06fa9b1dcaee47fba9cf869027ed6f1">d32</a>);
+<a name="l03007"></a>03007                 } <span class="keywordflow">else</span> {
+<a name="l03008"></a>03008                         <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_len =
+<a name="l03009"></a>03009                             (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;total_len - <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_count) &gt;
+<a name="l03010"></a>03010                             <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;maxpacket ? <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;maxpacket : (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;total_len -
+<a name="l03011"></a>03011                                                              <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_count);
+<a name="l03012"></a>03012 
+<a name="l03013"></a>03013                         dma_desc = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#99f44e328bbb4401aabd8e2708853238">in_desc_addr</a>;
+<a name="l03014"></a>03014 
+<a name="l03016"></a>03016                         dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#1876c32496f0067948f6282b7583aeab">b</a>.<a class="code" href="uniondev__dma__desc__sts.html#05d1c1d8f6c5a1967c51c5d0e2e04261">bs</a> = <a class="code" href="dwc__otg__regs_8h.html#e6e96a79797557986256d1a1ff104ca1">BS_HOST_BUSY</a>;
+<a name="l03017"></a>03017                         dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#1876c32496f0067948f6282b7583aeab">b</a>.<a class="code" href="uniondev__dma__desc__sts.html#b728a79d6a86a0d1b6426a1b2627f2c2">l</a> = 1;
+<a name="l03018"></a>03018                         dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#1876c32496f0067948f6282b7583aeab">b</a>.<a class="code" href="uniondev__dma__desc__sts.html#02c8be72ef6258c25094478c7cac0b12">ioc</a> = 1;
+<a name="l03019"></a>03019                         dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#1876c32496f0067948f6282b7583aeab">b</a>.<a class="code" href="uniondev__dma__desc__sts.html#a850ddfa13601227c05e0ae43a538a9d">sp</a> =
+<a name="l03020"></a>03020                             (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_len == <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;maxpacket) ? 0 : 1;
+<a name="l03021"></a>03021                         dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#1876c32496f0067948f6282b7583aeab">b</a>.<a class="code" href="uniondev__dma__desc__sts.html#9b6181d78984cb4d853945774f300ef0">bytes</a> = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_len;
+<a name="l03022"></a>03022                         dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#0454dad420ef536fe5eb7c38ef764430">buf</a> = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;dma_addr;
+<a name="l03023"></a>03023                         dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#1876c32496f0067948f6282b7583aeab">b</a>.<a class="code" href="uniondev__dma__desc__sts.html#05d1c1d8f6c5a1967c51c5d0e2e04261">bs</a> = <a class="code" href="dwc__otg__regs_8h.html#c2cfc53da94087a90d21d3528b005bcf">BS_HOST_READY</a>;
+<a name="l03024"></a>03024 
+<a name="l03026"></a>03026                         dwc_write_reg32(&amp;in_regs-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#5f013840a15e0a310b8722646880a420">diepdma</a>,
+<a name="l03027"></a>03027                                         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#ba2f5eede8b3deaaec8882baeea6a35b">dma_in_desc_addr</a>);
+<a name="l03028"></a>03028                 }
+<a name="l03029"></a>03029 
+<a name="l03030"></a>03030                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>,
+<a name="l03031"></a>03031                             <span class="stringliteral">"IN len=%d  xfersize=%d pktcnt=%d [%08x]\n"</span>,
+<a name="l03032"></a>03032                             <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_len, deptsiz.<a class="code" href="uniondeptsiz0__data.html#8e50594573fd774fc3e27404d8b1f59c">b</a>.<a class="code" href="uniondeptsiz0__data.html#1792e672dde70ead19bd0f5e7642af03">xfersize</a>, deptsiz.<a class="code" href="uniondeptsiz0__data.html#8e50594573fd774fc3e27404d8b1f59c">b</a>.<a class="code" href="uniondeptsiz0__data.html#debb8f273e4480cde57bef7677697bd0">pktcnt</a>,
+<a name="l03033"></a>03033                             deptsiz.<a class="code" href="uniondeptsiz0__data.html#a06fa9b1dcaee47fba9cf869027ed6f1">d32</a>);
+<a name="l03034"></a>03034 
+<a name="l03035"></a>03035                 <span class="comment">/* Write the DMA register */</span>
+<a name="l03036"></a>03036                 <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">hwcfg2</a>.<a class="code" href="unionhwcfg2__data.html#9dcc70e2dba617cbc6c12189be5c1d6a">b</a>.<a class="code" href="unionhwcfg2__data.html#e5000f58c6a0f09c75375b4c912af0eb">architecture</a> == <a class="code" href="dwc__otg__regs_8h.html#f91a3e3ec200595566b8df5e40485fda">DWC_INT_DMA_ARCH</a>) {
+<a name="l03037"></a>03037                         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a> == 0)
+<a name="l03038"></a>03038                                 dwc_write_reg32(&amp;(in_regs-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#5f013840a15e0a310b8722646880a420">diepdma</a>),
+<a name="l03039"></a>03039                                                 (uint32_t) <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;dma_addr);
+<a name="l03040"></a>03040                 }
+<a name="l03041"></a>03041 
+<a name="l03042"></a>03042                 <span class="comment">/* EP enable, IN data in FIFO */</span>
+<a name="l03043"></a>03043                 depctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#0b87d0914ceee7a20ffd2d7510b6a72e">cnak</a> = 1;
+<a name="l03044"></a>03044                 depctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#337ceb41a9e0735e144e684b1f9e5368">epena</a> = 1;
+<a name="l03045"></a>03045                 dwc_write_reg32(&amp;in_regs-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#53a5adb977e2aec66d4902c6ba293216">diepctl</a>, depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a>);
+<a name="l03046"></a>03046 
+<a name="l03051"></a>03051                 <span class="keywordflow">if</span> (!core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a>) {
+<a name="l03052"></a>03052                         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#31d08d1ebcd290b05139b0fcd24048ec">en_multiple_tx_fifo</a> == 0) {
+<a name="l03053"></a>03053                                 <span class="comment">/* First clear it from GINTSTS */</span>
+<a name="l03054"></a>03054                                 intr_mask.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#2c395e7bef31a4d9b2d1a3257c601be4">nptxfempty</a> = 1;
+<a name="l03055"></a>03055                                 dwc_modify_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;
+<a name="l03056"></a>03056                                                  gintmsk, intr_mask.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a>,
+<a name="l03057"></a>03057                                                  intr_mask.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a>);
+<a name="l03058"></a>03058 
+<a name="l03059"></a>03059                         } <span class="keywordflow">else</span> {
+<a name="l03060"></a>03060                                 <span class="comment">/* Enable the Tx FIFO Empty Interrupt for this EP */</span>
+<a name="l03061"></a>03061                                 <span class="keywordflow">if</span> (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_len &gt; 0) {
+<a name="l03062"></a>03062                                         uint32_t fifoemptymsk = 0;
+<a name="l03063"></a>03063                                         fifoemptymsk |= 1 &lt;&lt; <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;num;
+<a name="l03064"></a>03064                                         dwc_modify_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;
+<a name="l03065"></a>03065                                                          dev_global_regs-&gt;
+<a name="l03066"></a>03066                                                          dtknqr4_fifoemptymsk,
+<a name="l03067"></a>03067                                                          0, fifoemptymsk);
+<a name="l03068"></a>03068                                 }
+<a name="l03069"></a>03069                         }
+<a name="l03070"></a>03070                 }
+<a name="l03071"></a>03071         } <span class="keywordflow">else</span> {
+<a name="l03072"></a>03072                 <a class="code" href="structdwc__otg__dev__out__ep__regs.html">dwc_otg_dev_out_ep_regs_t</a> *out_regs =
+<a name="l03073"></a>03073                     core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">out_ep_regs</a>[0];
+<a name="l03074"></a>03074 
+<a name="l03075"></a>03075                 depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a> = dwc_read_reg32(&amp;out_regs-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#2a522b71fc97658c07debf3521f7d3e5">doepctl</a>);
+<a name="l03076"></a>03076                 deptsiz.<a class="code" href="uniondeptsiz0__data.html#a06fa9b1dcaee47fba9cf869027ed6f1">d32</a> = dwc_read_reg32(&amp;out_regs-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#e756ec48787099f0a4e2ce353fce4f91">doeptsiz</a>);
+<a name="l03077"></a>03077 
+<a name="l03078"></a>03078                 <span class="comment">/* Program the transfer size and packet count</span>
+<a name="l03079"></a>03079 <span class="comment">                 *      as follows: xfersize = N * maxpacket +</span>
+<a name="l03080"></a>03080 <span class="comment">                 *      short_packet pktcnt = N + (short_packet</span>
+<a name="l03081"></a>03081 <span class="comment">                 *      exist ? 1 : 0)  </span>
+<a name="l03082"></a>03082 <span class="comment">                 */</span>
+<a name="l03083"></a>03083                 deptsiz.<a class="code" href="uniondeptsiz0__data.html#8e50594573fd774fc3e27404d8b1f59c">b</a>.<a class="code" href="uniondeptsiz0__data.html#1792e672dde70ead19bd0f5e7642af03">xfersize</a> = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;maxpacket;
+<a name="l03084"></a>03084                 deptsiz.<a class="code" href="uniondeptsiz0__data.html#8e50594573fd774fc3e27404d8b1f59c">b</a>.<a class="code" href="uniondeptsiz0__data.html#debb8f273e4480cde57bef7677697bd0">pktcnt</a> = 1;
+<a name="l03085"></a>03085 
+<a name="l03086"></a>03086                 <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a> == 0) {
+<a name="l03087"></a>03087                         dwc_write_reg32(&amp;out_regs-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#e756ec48787099f0a4e2ce353fce4f91">doeptsiz</a>, deptsiz.<a class="code" href="uniondeptsiz0__data.html#a06fa9b1dcaee47fba9cf869027ed6f1">d32</a>);
+<a name="l03088"></a>03088                 } <span class="keywordflow">else</span> {
+<a name="l03089"></a>03089                         dma_desc = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#8cc9be8ccaba2ef93b02b34ba7b26bad">out_desc_addr</a>;
+<a name="l03090"></a>03090 
+<a name="l03092"></a>03092                         dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#1876c32496f0067948f6282b7583aeab">b</a>.<a class="code" href="uniondev__dma__desc__sts.html#05d1c1d8f6c5a1967c51c5d0e2e04261">bs</a> = <a class="code" href="dwc__otg__regs_8h.html#e6e96a79797557986256d1a1ff104ca1">BS_HOST_BUSY</a>;
+<a name="l03093"></a>03093                         dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#1876c32496f0067948f6282b7583aeab">b</a>.<a class="code" href="uniondev__dma__desc__sts.html#b728a79d6a86a0d1b6426a1b2627f2c2">l</a> = 1;
+<a name="l03094"></a>03094                         dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#1876c32496f0067948f6282b7583aeab">b</a>.<a class="code" href="uniondev__dma__desc__sts.html#02c8be72ef6258c25094478c7cac0b12">ioc</a> = 1;
+<a name="l03095"></a>03095                         dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#1876c32496f0067948f6282b7583aeab">b</a>.<a class="code" href="uniondev__dma__desc__sts.html#9b6181d78984cb4d853945774f300ef0">bytes</a> = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;maxpacket;
+<a name="l03096"></a>03096                         dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#0454dad420ef536fe5eb7c38ef764430">buf</a> = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;dma_addr;
+<a name="l03097"></a>03097                         dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#1876c32496f0067948f6282b7583aeab">b</a>.<a class="code" href="uniondev__dma__desc__sts.html#05d1c1d8f6c5a1967c51c5d0e2e04261">bs</a> = <a class="code" href="dwc__otg__regs_8h.html#c2cfc53da94087a90d21d3528b005bcf">BS_HOST_READY</a>;
+<a name="l03098"></a>03098 
+<a name="l03100"></a>03100                         dwc_write_reg32(&amp;out_regs-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#006071bf54bfa1c1f5e25cf4c9f65cb1">doepdma</a>,
+<a name="l03101"></a>03101                                         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#3829a415bbaf0f5c3e29b1a9f3cf546b">dma_out_desc_addr</a>);
+<a name="l03102"></a>03102                 }
+<a name="l03103"></a>03103 
+<a name="l03104"></a>03104                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>,
+<a name="l03105"></a>03105                             <span class="stringliteral">"IN len=%d  xfersize=%d pktcnt=%d [%08x]\n"</span>,
+<a name="l03106"></a>03106                             <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_len, deptsiz.<a class="code" href="uniondeptsiz0__data.html#8e50594573fd774fc3e27404d8b1f59c">b</a>.<a class="code" href="uniondeptsiz0__data.html#1792e672dde70ead19bd0f5e7642af03">xfersize</a>, deptsiz.<a class="code" href="uniondeptsiz0__data.html#8e50594573fd774fc3e27404d8b1f59c">b</a>.<a class="code" href="uniondeptsiz0__data.html#debb8f273e4480cde57bef7677697bd0">pktcnt</a>,
+<a name="l03107"></a>03107                             deptsiz.<a class="code" href="uniondeptsiz0__data.html#a06fa9b1dcaee47fba9cf869027ed6f1">d32</a>);
+<a name="l03108"></a>03108 
+<a name="l03109"></a>03109                 <span class="comment">/* Write the DMA register */</span>
+<a name="l03110"></a>03110                 <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">hwcfg2</a>.<a class="code" href="unionhwcfg2__data.html#9dcc70e2dba617cbc6c12189be5c1d6a">b</a>.<a class="code" href="unionhwcfg2__data.html#e5000f58c6a0f09c75375b4c912af0eb">architecture</a> == <a class="code" href="dwc__otg__regs_8h.html#f91a3e3ec200595566b8df5e40485fda">DWC_INT_DMA_ARCH</a>) {
+<a name="l03111"></a>03111                         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a> == 0)
+<a name="l03112"></a>03112                                 dwc_write_reg32(&amp;(out_regs-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#006071bf54bfa1c1f5e25cf4c9f65cb1">doepdma</a>),
+<a name="l03113"></a>03113                                                 (uint32_t) <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;dma_addr);
+<a name="l03114"></a>03114                 }
+<a name="l03115"></a>03115 
+<a name="l03116"></a>03116                 <span class="comment">/* EP enable, IN data in FIFO */</span>
+<a name="l03117"></a>03117                 depctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#0b87d0914ceee7a20ffd2d7510b6a72e">cnak</a> = 1;
+<a name="l03118"></a>03118                 depctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#337ceb41a9e0735e144e684b1f9e5368">epena</a> = 1;
+<a name="l03119"></a>03119                 dwc_write_reg32(&amp;out_regs-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#2a522b71fc97658c07debf3521f7d3e5">doepctl</a>, depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a>);
+<a name="l03120"></a>03120 
+<a name="l03121"></a>03121         }
+<a name="l03122"></a>03122 }
+<a name="l03123"></a>03123 
+<a name="l03124"></a>03124 <span class="preprocessor">#ifdef DEBUG</span>
+<a name="l03125"></a>03125 <span class="preprocessor"></span><span class="keywordtype">void</span> <a class="code" href="dwc__otg__cfi_8h.html#8d8df6d136115ec977eb6bf20148547a">dump_msg</a>(<span class="keyword">const</span> u8 * buf, <span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> length)
+<a name="l03126"></a>03126 {
+<a name="l03127"></a>03127         <span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> start, num, i;
+<a name="l03128"></a>03128         <span class="keywordtype">char</span> line[52], *p;
+<a name="l03129"></a>03129 
+<a name="l03130"></a>03130         <span class="keywordflow">if</span> (length &gt;= 512)
+<a name="l03131"></a>03131                 <span class="keywordflow">return</span>;
+<a name="l03132"></a>03132         start = 0;
+<a name="l03133"></a>03133         <span class="keywordflow">while</span> (length &gt; 0) {
+<a name="l03134"></a>03134                 num = length &lt; 16u ? length : 16u;
+<a name="l03135"></a>03135                 p = line;
+<a name="l03136"></a>03136                 <span class="keywordflow">for</span> (i = 0; i &lt; num; ++i) {
+<a name="l03137"></a>03137                         <span class="keywordflow">if</span> (i == 8)
+<a name="l03138"></a>03138                                 *p++ = <span class="charliteral">' '</span>;
+<a name="l03139"></a>03139                         DWC_SPRINTF(p, <span class="stringliteral">" %02x"</span>, buf[i]);
+<a name="l03140"></a>03140                         p += 3;
+<a name="l03141"></a>03141                 }
+<a name="l03142"></a>03142                 *p = 0;
+<a name="l03143"></a>03143                 DWC_PRINTF(<span class="stringliteral">"%6x: %s\n"</span>, start, line);
+<a name="l03144"></a>03144                 buf += num;
+<a name="l03145"></a>03145                 start += num;
+<a name="l03146"></a>03146                 length -= num;
+<a name="l03147"></a>03147         }
+<a name="l03148"></a>03148 }
+<a name="l03149"></a>03149 <span class="preprocessor">#else</span>
+<a name="l03150"></a><a class="code" href="dwc__otg__cil_8c.html#8d8df6d136115ec977eb6bf20148547a">03150</a> <span class="preprocessor"></span><span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cfi_8h.html#8d8df6d136115ec977eb6bf20148547a">dump_msg</a>(<span class="keyword">const</span> u8 * buf, <span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> length)
+<a name="l03151"></a>03151 {
+<a name="l03152"></a>03152 }
+<a name="l03153"></a>03153 <span class="preprocessor">#endif</span>
+<a name="l03154"></a>03154 <span class="preprocessor"></span>
+<a name="l03165"></a><a class="code" href="dwc__otg__cil_8h.html#42cba51a650375f6a18f4136cb4dba92">03165</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#97a11808b8b12a365a91f02b6d686d0c">dwc_otg_ep_write_packet</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, <a class="code" href="structdwc__ep.html">dwc_ep_t</a> * <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>,
+<a name="l03166"></a>03166                              <span class="keywordtype">int</span> dma)
+<a name="l03167"></a>03167 {
+<a name="l03183"></a>03183         uint32_t i;
+<a name="l03184"></a>03184         uint32_t byte_count;
+<a name="l03185"></a>03185         uint32_t dword_count;
+<a name="l03186"></a>03186         uint32_t *fifo;
+<a name="l03187"></a>03187         uint32_t *data_buff = (uint32_t *) <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_buff;
+<a name="l03188"></a>03188 
+<a name="l03189"></a>03189         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>((<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a> | <a class="code" href="dwc__otg__dbg_8h.html#daab8e158c0c530486656ef52e5b0bbe">DBG_CILV</a>), <span class="stringliteral">"%s(%p,%p)\n"</span>, __func__, core_if,
+<a name="l03190"></a>03190                     <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>);
+<a name="l03191"></a>03191         <span class="keywordflow">if</span> (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_count &gt;= <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_len) {
+<a name="l03192"></a>03192                 DWC_WARN(<span class="stringliteral">"%s() No data for EP%d!!!\n"</span>, __func__, <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;num);
+<a name="l03193"></a>03193                 <span class="keywordflow">return</span>;
+<a name="l03194"></a>03194         }
+<a name="l03195"></a>03195 
+<a name="l03196"></a>03196         <span class="comment">/* Find the byte length of the packet either short packet or MPS */</span>
+<a name="l03197"></a>03197         <span class="keywordflow">if</span> ((<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_len - <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_count) &lt; <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;maxpacket) {
+<a name="l03198"></a>03198                 byte_count = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_len - <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_count;
+<a name="l03199"></a>03199         } <span class="keywordflow">else</span> {
+<a name="l03200"></a>03200                 byte_count = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;maxpacket;
+<a name="l03201"></a>03201         }
+<a name="l03202"></a>03202 
+<a name="l03203"></a>03203         <span class="comment">/* Find the DWORD length, padded by extra bytes as neccessary if MPS</span>
+<a name="l03204"></a>03204 <span class="comment">         * is not a multiple of DWORD */</span>
+<a name="l03205"></a>03205         dword_count = (byte_count + 3) / 4;
+<a name="l03206"></a>03206 
+<a name="l03207"></a>03207 <span class="preprocessor">#ifdef VERBOSE</span>
+<a name="l03208"></a>03208 <span class="preprocessor"></span>        <a class="code" href="dwc__otg__cfi_8h.html#8d8df6d136115ec977eb6bf20148547a">dump_msg</a>(<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_buff, byte_count);
+<a name="l03209"></a>03209 <span class="preprocessor">#endif</span>
+<a name="l03210"></a>03210 <span class="preprocessor"></span>
+<a name="l03214"></a>03214         fifo = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#f99c868784a8269073bc251f88d92ee4">data_fifo</a>[<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;num];
+<a name="l03215"></a>03215 
+<a name="l03216"></a>03216         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>((<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a> | <a class="code" href="dwc__otg__dbg_8h.html#daab8e158c0c530486656ef52e5b0bbe">DBG_CILV</a>), <span class="stringliteral">"fifo=%p buff=%p *p=%08x bc=%d\n"</span>,
+<a name="l03217"></a>03217                     fifo, data_buff, *data_buff, byte_count);
+<a name="l03218"></a>03218 
+<a name="l03219"></a>03219         <span class="keywordflow">if</span> (!dma) {
+<a name="l03220"></a>03220                 <span class="keywordflow">for</span> (i = 0; i &lt; dword_count; i++, data_buff++) {
+<a name="l03221"></a>03221                         dwc_write_reg32(fifo, *data_buff);
+<a name="l03222"></a>03222                 }
+<a name="l03223"></a>03223         }
+<a name="l03224"></a>03224 
+<a name="l03225"></a>03225         <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_count += byte_count;
+<a name="l03226"></a>03226         <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_buff += byte_count;
+<a name="l03227"></a>03227         <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;dma_addr += byte_count;
+<a name="l03228"></a>03228 }
+<a name="l03229"></a>03229 
+<a name="l03236"></a><a class="code" href="dwc__otg__cil_8h.html#e1490c2dd3586403cf3fe12c716b41b2">03236</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#5edca13178261136209ed51360c850b4">dwc_otg_ep_set_stall</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, <a class="code" href="structdwc__ep.html">dwc_ep_t</a> * <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>)
+<a name="l03237"></a>03237 {
+<a name="l03238"></a>03238         <a class="code" href="uniondepctl__data.html">depctl_data_t</a> depctl;
+<a name="l03239"></a>03239         <span class="keyword">volatile</span> uint32_t *depctl_addr;
+<a name="l03240"></a>03240 
+<a name="l03241"></a>03241         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"%s ep%d-%s\n"</span>, __func__, <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;num,
+<a name="l03242"></a>03242                     (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;is_in ? <span class="stringliteral">"IN"</span> : <span class="stringliteral">"OUT"</span>));
+<a name="l03243"></a>03243 
+<a name="l03244"></a>03244         <span class="keywordflow">if</span> (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;is_in == 1) {
+<a name="l03245"></a>03245                 depctl_addr = &amp;(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;num]-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#53a5adb977e2aec66d4902c6ba293216">diepctl</a>);
+<a name="l03246"></a>03246                 depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a> = dwc_read_reg32(depctl_addr);
+<a name="l03247"></a>03247 
+<a name="l03248"></a>03248                 <span class="comment">/* set the disable and stall bits */</span>
+<a name="l03249"></a>03249                 <span class="keywordflow">if</span> (depctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#337ceb41a9e0735e144e684b1f9e5368">epena</a>) {
+<a name="l03250"></a>03250                         depctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#4d76ba4ebd506d3175ec5cdc0d811654">epdis</a> = 1;
+<a name="l03251"></a>03251                 }
+<a name="l03252"></a>03252                 depctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#f7ad1bcf91d28b8a4aa8d3a343dd83e4">stall</a> = 1;
+<a name="l03253"></a>03253                 dwc_write_reg32(depctl_addr, depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a>);
+<a name="l03254"></a>03254         } <span class="keywordflow">else</span> {
+<a name="l03255"></a>03255                 depctl_addr = &amp;(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">out_ep_regs</a>[<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;num]-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#2a522b71fc97658c07debf3521f7d3e5">doepctl</a>);
+<a name="l03256"></a>03256                 depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a> = dwc_read_reg32(depctl_addr);
+<a name="l03257"></a>03257 
+<a name="l03258"></a>03258                 <span class="comment">/* set the stall bit */</span>
+<a name="l03259"></a>03259                 depctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#f7ad1bcf91d28b8a4aa8d3a343dd83e4">stall</a> = 1;
+<a name="l03260"></a>03260                 dwc_write_reg32(depctl_addr, depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a>);
+<a name="l03261"></a>03261         }
+<a name="l03262"></a>03262 
+<a name="l03263"></a>03263         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"DEPCTL=%0x\n"</span>, dwc_read_reg32(depctl_addr));
+<a name="l03264"></a>03264 
+<a name="l03265"></a>03265         <span class="keywordflow">return</span>;
+<a name="l03266"></a>03266 }
+<a name="l03267"></a>03267 
+<a name="l03274"></a><a class="code" href="dwc__otg__cil_8h.html#45d65850c250067079f80c3ba87ef077">03274</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#a5f77318fb1c589406927a606844007f">dwc_otg_ep_clear_stall</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, <a class="code" href="structdwc__ep.html">dwc_ep_t</a> * <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>)
+<a name="l03275"></a>03275 {
+<a name="l03276"></a>03276         <a class="code" href="uniondepctl__data.html">depctl_data_t</a> depctl;
+<a name="l03277"></a>03277         <span class="keyword">volatile</span> uint32_t *depctl_addr;
+<a name="l03278"></a>03278 
+<a name="l03279"></a>03279         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"%s ep%d-%s\n"</span>, __func__, <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;num,
+<a name="l03280"></a>03280                     (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;is_in ? <span class="stringliteral">"IN"</span> : <span class="stringliteral">"OUT"</span>));
+<a name="l03281"></a>03281 
+<a name="l03282"></a>03282         <span class="keywordflow">if</span> (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;is_in == 1) {
+<a name="l03283"></a>03283                 depctl_addr = &amp;(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;num]-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#53a5adb977e2aec66d4902c6ba293216">diepctl</a>);
+<a name="l03284"></a>03284         } <span class="keywordflow">else</span> {
+<a name="l03285"></a>03285                 depctl_addr = &amp;(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">out_ep_regs</a>[<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;num]-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#2a522b71fc97658c07debf3521f7d3e5">doepctl</a>);
+<a name="l03286"></a>03286         }
+<a name="l03287"></a>03287 
+<a name="l03288"></a>03288         depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a> = dwc_read_reg32(depctl_addr);
+<a name="l03289"></a>03289 
+<a name="l03290"></a>03290         <span class="comment">/* clear the stall bits */</span>
+<a name="l03291"></a>03291         depctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#f7ad1bcf91d28b8a4aa8d3a343dd83e4">stall</a> = 0;
+<a name="l03292"></a>03292 
+<a name="l03293"></a>03293         <span class="comment">/* </span>
+<a name="l03294"></a>03294 <span class="comment">         * USB Spec 9.4.5: For endpoints using data toggle, regardless</span>
+<a name="l03295"></a>03295 <span class="comment">         * of whether an endpoint has the Halt feature set, a</span>
+<a name="l03296"></a>03296 <span class="comment">         * ClearFeature(ENDPOINT_HALT) request always results in the</span>
+<a name="l03297"></a>03297 <span class="comment">         * data toggle being reinitialized to DATA0.</span>
+<a name="l03298"></a>03298 <span class="comment">         */</span>
+<a name="l03299"></a>03299         <span class="keywordflow">if</span> (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;type == <a class="code" href="dwc__otg__cil_8h.html#1401d1264f88530232cf51ab31cc5347">DWC_OTG_EP_TYPE_INTR</a> ||
+<a name="l03300"></a>03300             <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;type == <a class="code" href="dwc__otg__cil_8h.html#9b079858cda0b917316ad9161b3881e0">DWC_OTG_EP_TYPE_BULK</a>) {
+<a name="l03301"></a>03301                 depctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#90d89b642aafd60a6c62db5bf8396de9">setd0pid</a> = 1;  <span class="comment">/* DATA0 */</span>
+<a name="l03302"></a>03302         }
+<a name="l03303"></a>03303 
+<a name="l03304"></a>03304         dwc_write_reg32(depctl_addr, depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a>);
+<a name="l03305"></a>03305         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"DEPCTL=%0x\n"</span>, dwc_read_reg32(depctl_addr));
+<a name="l03306"></a>03306         <span class="keywordflow">return</span>;
+<a name="l03307"></a>03307 }
+<a name="l03308"></a>03308 
+<a name="l03317"></a><a class="code" href="dwc__otg__cil_8h.html#68f59dd23ccfffa9aa1dc590e99b7668">03317</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#68f59dd23ccfffa9aa1dc590e99b7668">dwc_otg_read_packet</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if,
+<a name="l03318"></a>03318                          uint8_t * dest, uint16_t bytes)
+<a name="l03319"></a>03319 {
+<a name="l03320"></a>03320         <span class="keywordtype">int</span> i;
+<a name="l03321"></a>03321         <span class="keywordtype">int</span> word_count = (bytes + 3) / 4;
+<a name="l03322"></a>03322 
+<a name="l03323"></a>03323         <span class="keyword">volatile</span> uint32_t *fifo = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#f99c868784a8269073bc251f88d92ee4">data_fifo</a>[0];
+<a name="l03324"></a>03324         uint32_t *data_buff = (uint32_t *) dest;
+<a name="l03325"></a>03325 
+<a name="l03332"></a>03332         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>((<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a> | <a class="code" href="dwc__otg__dbg_8h.html#daab8e158c0c530486656ef52e5b0bbe">DBG_CILV</a>), <span class="stringliteral">"%s(%p,%p,%d)\n"</span>, __func__,
+<a name="l03333"></a>03333                     core_if, dest, bytes);
+<a name="l03334"></a>03334 
+<a name="l03335"></a>03335         <span class="keywordflow">for</span> (i = 0; i &lt; word_count; i++, data_buff++) {
+<a name="l03336"></a>03336                 *data_buff = dwc_read_reg32(fifo);
+<a name="l03337"></a>03337         }
+<a name="l03338"></a>03338 
+<a name="l03339"></a>03339         <span class="keywordflow">return</span>;
+<a name="l03340"></a>03340 }
+<a name="l03341"></a>03341 
+<a name="l03347"></a><a class="code" href="dwc__otg__core__if_8h.html#f4a8cc5126f81ceb361294c7734737aa">03347</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#ea3bce6af9d0bd9b2fb6de94f1c7a133">dwc_otg_dump_dev_registers</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l03348"></a>03348 {
+<a name="l03349"></a>03349         <span class="keywordtype">int</span> i;
+<a name="l03350"></a>03350         <span class="keyword">volatile</span> uint32_t *addr;
+<a name="l03351"></a>03351 
+<a name="l03352"></a>03352         DWC_PRINTF(<span class="stringliteral">"Device Global Registers\n"</span>);
+<a name="l03353"></a>03353         addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#c0c24937bbd7184884f05343f56ef1da">dcfg</a>;
+<a name="l03354"></a>03354         DWC_PRINTF(<span class="stringliteral">"DCFG                 @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03355"></a>03355                    dwc_read_reg32(addr));
+<a name="l03356"></a>03356         addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#3779c2fc508920a831a59e696a8fa785">dctl</a>;
+<a name="l03357"></a>03357         DWC_PRINTF(<span class="stringliteral">"DCTL                 @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03358"></a>03358                    dwc_read_reg32(addr));
+<a name="l03359"></a>03359         addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#1ed00edd20ce5db7d07666804101ec05">dsts</a>;
+<a name="l03360"></a>03360         DWC_PRINTF(<span class="stringliteral">"DSTS                 @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03361"></a>03361                    dwc_read_reg32(addr));
+<a name="l03362"></a>03362         addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#02e44cb182548d78c5b7d27929ca5f11">diepmsk</a>;
+<a name="l03363"></a>03363         DWC_PRINTF(<span class="stringliteral">"DIEPMSK      @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03364"></a>03364                    dwc_read_reg32(addr));
+<a name="l03365"></a>03365         addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#d6947be9d84a1d87156f81a10ebb036b">doepmsk</a>;
+<a name="l03366"></a>03366         DWC_PRINTF(<span class="stringliteral">"DOEPMSK      @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03367"></a>03367                    dwc_read_reg32(addr));
+<a name="l03368"></a>03368         addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#2e25df2fbec9d398742709524056cbd5">daint</a>;
+<a name="l03369"></a>03369         DWC_PRINTF(<span class="stringliteral">"DAINT        @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03370"></a>03370                    dwc_read_reg32(addr));
+<a name="l03371"></a>03371         addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#5def6c3850c041928b9a662422ee0679">daintmsk</a>;
+<a name="l03372"></a>03372         DWC_PRINTF(<span class="stringliteral">"DAINTMSK     @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03373"></a>03373                    dwc_read_reg32(addr));
+<a name="l03374"></a>03374         addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#b130a76736e0e81d5a020651109352de">dtknqr1</a>;
+<a name="l03375"></a>03375         DWC_PRINTF(<span class="stringliteral">"DTKNQR1      @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03376"></a>03376                    dwc_read_reg32(addr));
+<a name="l03377"></a>03377         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">hwcfg2</a>.<a class="code" href="unionhwcfg2__data.html#9dcc70e2dba617cbc6c12189be5c1d6a">b</a>.<a class="code" href="unionhwcfg2__data.html#ba242467585b60b4d3db9882e0f39b3f">dev_token_q_depth</a> &gt; 6) {
+<a name="l03378"></a>03378                 addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#27968db886161264e7820bcf4a746e5d">dtknqr2</a>;
+<a name="l03379"></a>03379                 DWC_PRINTF(<span class="stringliteral">"DTKNQR2      @0x%08X : 0x%08X\n"</span>,
+<a name="l03380"></a>03380                            (uint32_t) addr, dwc_read_reg32(addr));
+<a name="l03381"></a>03381         }
+<a name="l03382"></a>03382 
+<a name="l03383"></a>03383         addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#95088e182c3ff164d1b331bb196eb95d">dvbusdis</a>;
+<a name="l03384"></a>03384         DWC_PRINTF(<span class="stringliteral">"DVBUSID      @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03385"></a>03385                    dwc_read_reg32(addr));
+<a name="l03386"></a>03386 
+<a name="l03387"></a>03387         addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#8747dbe01b5a4cbd2c980bf39fdb4737">dvbuspulse</a>;
+<a name="l03388"></a>03388         DWC_PRINTF(<span class="stringliteral">"DVBUSPULSE  @0x%08X : 0x%08X\n"</span>,
+<a name="l03389"></a>03389                    (uint32_t) addr, dwc_read_reg32(addr));
+<a name="l03390"></a>03390 
+<a name="l03391"></a>03391                 addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#c263c55a0bb752f8939731aa2f8f6cb8">dtknqr3_dthrctl</a>;
+<a name="l03392"></a>03392                 DWC_PRINTF(<span class="stringliteral">"DTKNQR3_DTHRCTL      @0x%08X : 0x%08X\n"</span>,
+<a name="l03393"></a>03393                            (uint32_t) addr, dwc_read_reg32(addr));
+<a name="l03394"></a>03394 
+<a name="l03395"></a>03395         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">hwcfg2</a>.<a class="code" href="unionhwcfg2__data.html#9dcc70e2dba617cbc6c12189be5c1d6a">b</a>.<a class="code" href="unionhwcfg2__data.html#ba242467585b60b4d3db9882e0f39b3f">dev_token_q_depth</a> &gt; 22) {
+<a name="l03396"></a>03396                 addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#fbc2b776c2150842813e4681dd43bedc">dtknqr4_fifoemptymsk</a>;
+<a name="l03397"></a>03397                 DWC_PRINTF(<span class="stringliteral">"DTKNQR4      @0x%08X : 0x%08X\n"</span>,
+<a name="l03398"></a>03398                            (uint32_t) addr, dwc_read_reg32(addr));
+<a name="l03399"></a>03399         }
+<a name="l03400"></a>03400 
+<a name="l03401"></a>03401         addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#fbc2b776c2150842813e4681dd43bedc">dtknqr4_fifoemptymsk</a>;
+<a name="l03402"></a>03402         DWC_PRINTF(<span class="stringliteral">"FIFOEMPMSK   @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03403"></a>03403                    dwc_read_reg32(addr));
+<a name="l03404"></a>03404 
+<a name="l03405"></a>03405         addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#4795bc8eab569241a3f8e6aad5d99ac7">deachint</a>;
+<a name="l03406"></a>03406         DWC_PRINTF(<span class="stringliteral">"DEACHINT     @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03407"></a>03407                    dwc_read_reg32(addr));
+<a name="l03408"></a>03408         addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#e64a153683f0e0cda14b56a163651825">deachintmsk</a>;
+<a name="l03409"></a>03409         DWC_PRINTF(<span class="stringliteral">"DEACHINTMSK  @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03410"></a>03410                    dwc_read_reg32(addr));
+<a name="l03411"></a>03411 
+<a name="l03412"></a>03412         <span class="keywordflow">for</span> (i = 0; i &lt;= core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#4fae9bc1293bf2e58966c38fa5b98822">num_in_eps</a>; i++) {
+<a name="l03413"></a>03413                 addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#aaf2a5c6be4130d558c291f6aaeeca4f">diepeachintmsk</a>[i];
+<a name="l03414"></a>03414                 DWC_PRINTF(<span class="stringliteral">"DIEPEACHINTMSK[%d]   @0x%08X : 0x%08X\n"</span>, i,
+<a name="l03415"></a>03415                            (uint32_t) addr, dwc_read_reg32(addr));
+<a name="l03416"></a>03416         }
+<a name="l03417"></a>03417 
+<a name="l03418"></a>03418         <span class="keywordflow">for</span> (i = 0; i &lt;= core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#2f0e01cdc605623f591963fc83c8dc73">num_out_eps</a>; i++) {
+<a name="l03419"></a>03419                 addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#304e089ed2d36d9076228b8d7e1cc515">doepeachintmsk</a>[i];
+<a name="l03420"></a>03420                 DWC_PRINTF(<span class="stringliteral">"DOEPEACHINTMSK[%d]   @0x%08X : 0x%08X\n"</span>, i,
+<a name="l03421"></a>03421                            (uint32_t) addr, dwc_read_reg32(addr));
+<a name="l03422"></a>03422         }
+<a name="l03423"></a>03423 
+<a name="l03424"></a>03424         <span class="keywordflow">for</span> (i = 0; i &lt;= core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#4fae9bc1293bf2e58966c38fa5b98822">num_in_eps</a>; i++) {
+<a name="l03425"></a>03425                 DWC_PRINTF(<span class="stringliteral">"Device IN EP %d Registers\n"</span>, i);
+<a name="l03426"></a>03426                 addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[i]-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#53a5adb977e2aec66d4902c6ba293216">diepctl</a>;
+<a name="l03427"></a>03427                 DWC_PRINTF(<span class="stringliteral">"DIEPCTL      @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03428"></a>03428                            dwc_read_reg32(addr));
+<a name="l03429"></a>03429                 addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[i]-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#4d6d6309ef5e09ad9048655ced6a2769">diepint</a>;
+<a name="l03430"></a>03430                 DWC_PRINTF(<span class="stringliteral">"DIEPINT      @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03431"></a>03431                            dwc_read_reg32(addr));
+<a name="l03432"></a>03432                 addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[i]-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#88f637b5a4e8a0c6bc87d157072255dd">dieptsiz</a>;
+<a name="l03433"></a>03433                 DWC_PRINTF(<span class="stringliteral">"DIETSIZ      @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03434"></a>03434                            dwc_read_reg32(addr));
+<a name="l03435"></a>03435                 addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[i]-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#5f013840a15e0a310b8722646880a420">diepdma</a>;
+<a name="l03436"></a>03436                 DWC_PRINTF(<span class="stringliteral">"DIEPDMA      @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03437"></a>03437                            dwc_read_reg32(addr));
+<a name="l03438"></a>03438                 addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[i]-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#90db7d3ed2dd087e0a55a1465deb21c9">dtxfsts</a>;
+<a name="l03439"></a>03439                 DWC_PRINTF(<span class="stringliteral">"DTXFSTS      @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03440"></a>03440                            dwc_read_reg32(addr));
+<a name="l03441"></a>03441                 addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[i]-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#aa24ec8b19877c7f2f20802afc6f9cef">diepdmab</a>;
+<a name="l03442"></a>03442                 DWC_PRINTF(<span class="stringliteral">"DIEPDMAB     @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03443"></a>03443                            0 <span class="comment">/*dwc_read_reg32(addr) */</span> );
+<a name="l03444"></a>03444         }
+<a name="l03445"></a>03445 
+<a name="l03446"></a>03446         <span class="keywordflow">for</span> (i = 0; i &lt;= core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#2f0e01cdc605623f591963fc83c8dc73">num_out_eps</a>; i++) {
+<a name="l03447"></a>03447                 DWC_PRINTF(<span class="stringliteral">"Device OUT EP %d Registers\n"</span>, i);
+<a name="l03448"></a>03448                 addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">out_ep_regs</a>[i]-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#2a522b71fc97658c07debf3521f7d3e5">doepctl</a>;
+<a name="l03449"></a>03449                 DWC_PRINTF(<span class="stringliteral">"DOEPCTL      @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03450"></a>03450                            dwc_read_reg32(addr));
+<a name="l03451"></a>03451                 addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">out_ep_regs</a>[i]-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#f23e8e9750d99b1c4b5ac0c674e8733e">doepfn</a>;
+<a name="l03452"></a>03452                 DWC_PRINTF(<span class="stringliteral">"DOEPFN       @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03453"></a>03453                            dwc_read_reg32(addr));
+<a name="l03454"></a>03454                 addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">out_ep_regs</a>[i]-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#81d837c801dcfa30f17b567419a86f62">doepint</a>;
+<a name="l03455"></a>03455                 DWC_PRINTF(<span class="stringliteral">"DOEPINT      @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03456"></a>03456                            dwc_read_reg32(addr));
+<a name="l03457"></a>03457                 addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">out_ep_regs</a>[i]-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#e756ec48787099f0a4e2ce353fce4f91">doeptsiz</a>;
+<a name="l03458"></a>03458                 DWC_PRINTF(<span class="stringliteral">"DOETSIZ      @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03459"></a>03459                            dwc_read_reg32(addr));
+<a name="l03460"></a>03460                 addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">out_ep_regs</a>[i]-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#006071bf54bfa1c1f5e25cf4c9f65cb1">doepdma</a>;
+<a name="l03461"></a>03461                 DWC_PRINTF(<span class="stringliteral">"DOEPDMA      @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03462"></a>03462                            dwc_read_reg32(addr));
+<a name="l03463"></a>03463                 <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a>) {      <span class="comment">/* Don't access this register in SLAVE mode */</span>
+<a name="l03464"></a>03464                         addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">out_ep_regs</a>[i]-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#baff3c1aea7aed57a42fa0015f15e0fa">doepdmab</a>;
+<a name="l03465"></a>03465                         DWC_PRINTF(<span class="stringliteral">"DOEPDMAB     @0x%08X : 0x%08X\n"</span>,
+<a name="l03466"></a>03466                                    (uint32_t) addr, dwc_read_reg32(addr));
+<a name="l03467"></a>03467                 }
+<a name="l03468"></a>03468 
+<a name="l03469"></a>03469         }
+<a name="l03470"></a>03470 }
+<a name="l03471"></a>03471 
+<a name="l03477"></a><a class="code" href="dwc__otg__core__if_8h.html#5b28e869ddc5a4c44d8669b6423b414e">03477</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#393e65ddcbaed38935ea06fb7451167b">dwc_otg_dump_spram</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l03478"></a>03478 {
+<a name="l03479"></a>03479         <span class="keyword">volatile</span> uint8_t *addr, *start_addr, *end_addr;
+<a name="l03480"></a>03480 
+<a name="l03481"></a>03481         DWC_PRINTF(<span class="stringliteral">"SPRAM Data:\n"</span>);
+<a name="l03482"></a>03482         start_addr = (<span class="keywordtype">void</span> *)core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>;
+<a name="l03483"></a>03483         DWC_PRINTF(<span class="stringliteral">"Base Address: 0x%8X\n"</span>, (uint32_t) start_addr);
+<a name="l03484"></a>03484         start_addr += 0x00028000;
+<a name="l03485"></a>03485         end_addr = (<span class="keywordtype">void</span> *)core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>;
+<a name="l03486"></a>03486         end_addr += 0x000280e0;
+<a name="l03487"></a>03487 
+<a name="l03488"></a>03488         for (addr = start_addr; addr &lt; end_addr; addr += 16) {
+<a name="l03489"></a>03489                 DWC_PRINTF
+<a name="l03490"></a>03490                     (<span class="stringliteral">"0x%8X:\t%2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X\n"</span>,
+<a name="l03491"></a>03491                      (uint32_t) addr, addr[0], addr[1], addr[2], addr[3],
+<a name="l03492"></a>03492                      addr[4], addr[5], addr[6], addr[7], addr[8], addr[9],
+<a name="l03493"></a>03493                      addr[10], addr[11], addr[12], addr[13], addr[14], addr[15]
+<a name="l03494"></a>03494                     );
+<a name="l03495"></a>03495         }
+<a name="l03496"></a>03496 
+<a name="l03497"></a>03497         <span class="keywordflow">return</span>;
+<a name="l03498"></a>03498 }
+<a name="l03499"></a>03499 
+<a name="l03505"></a><a class="code" href="dwc__otg__core__if_8h.html#a4c7a094e7c6eb2d28103e787ff09934">03505</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#e85d3d04799b17226fcb00ea2074ca63">dwc_otg_dump_host_registers</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l03506"></a>03506 {
+<a name="l03507"></a>03507         <span class="keywordtype">int</span> i;
+<a name="l03508"></a>03508         <span class="keyword">volatile</span> uint32_t *addr;
+<a name="l03509"></a>03509 
+<a name="l03510"></a>03510         DWC_PRINTF(<span class="stringliteral">"Host Global Registers\n"</span>);
+<a name="l03511"></a>03511         addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#ff9692c2e10ca2bc7e24f981f25179c2">host_global_regs</a>-&gt;<a class="code" href="structdwc__otg__host__global__regs.html#fd7d93b5ffcb6c7c0a84ef656e6e68de">hcfg</a>;
+<a name="l03512"></a>03512         DWC_PRINTF(<span class="stringliteral">"HCFG                 @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03513"></a>03513                    dwc_read_reg32(addr));
+<a name="l03514"></a>03514         addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#ff9692c2e10ca2bc7e24f981f25179c2">host_global_regs</a>-&gt;<a class="code" href="structdwc__otg__host__global__regs.html#d5ad893315e7b0dde27a3c5867dc56d0">hfir</a>;
+<a name="l03515"></a>03515         DWC_PRINTF(<span class="stringliteral">"HFIR                 @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03516"></a>03516                    dwc_read_reg32(addr));
+<a name="l03517"></a>03517         addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#ff9692c2e10ca2bc7e24f981f25179c2">host_global_regs</a>-&gt;<a class="code" href="structdwc__otg__host__global__regs.html#cebb0d86d0776473ef30eeac61e8692c">hfnum</a>;
+<a name="l03518"></a>03518         DWC_PRINTF(<span class="stringliteral">"HFNUM        @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03519"></a>03519                    dwc_read_reg32(addr));
+<a name="l03520"></a>03520         addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#ff9692c2e10ca2bc7e24f981f25179c2">host_global_regs</a>-&gt;<a class="code" href="structdwc__otg__host__global__regs.html#bf1a1528a2e479d86318d49ecd52ee40">hptxsts</a>;
+<a name="l03521"></a>03521         DWC_PRINTF(<span class="stringliteral">"HPTXSTS      @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03522"></a>03522                    dwc_read_reg32(addr));
+<a name="l03523"></a>03523         addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#ff9692c2e10ca2bc7e24f981f25179c2">host_global_regs</a>-&gt;<a class="code" href="structdwc__otg__host__global__regs.html#7c41808b0a69ed7d2125eb3afbbf6c14">haint</a>;
+<a name="l03524"></a>03524         DWC_PRINTF(<span class="stringliteral">"HAINT        @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03525"></a>03525                    dwc_read_reg32(addr));
+<a name="l03526"></a>03526         addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#ff9692c2e10ca2bc7e24f981f25179c2">host_global_regs</a>-&gt;<a class="code" href="structdwc__otg__host__global__regs.html#317f5059d4c2dc91da041f5c0a4819fc">haintmsk</a>;
+<a name="l03527"></a>03527         DWC_PRINTF(<span class="stringliteral">"HAINTMSK     @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03528"></a>03528                    dwc_read_reg32(addr));
+<a name="l03529"></a>03529         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a>) {
+<a name="l03530"></a>03530                 addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#ff9692c2e10ca2bc7e24f981f25179c2">host_global_regs</a>-&gt;<a class="code" href="structdwc__otg__host__global__regs.html#9a6af0a2c19d7b6228c7a40c9078907b">hflbaddr</a>;
+<a name="l03531"></a>03531                 DWC_PRINTF(<span class="stringliteral">"HFLBADDR     @0x%08X : 0x%08X\n"</span>,(uint32_t) addr,
+<a name="l03532"></a>03532                            dwc_read_reg32(addr));
+<a name="l03533"></a>03533         }
+<a name="l03534"></a>03534         
+<a name="l03535"></a>03535         addr = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#dc8fe33e0bb3829cafa884d5fc603c4d">hprt0</a>;
+<a name="l03536"></a>03536         DWC_PRINTF(<span class="stringliteral">"HPRT0        @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03537"></a>03537                    dwc_read_reg32(addr));
+<a name="l03538"></a>03538 
+<a name="l03539"></a>03539         <span class="keywordflow">for</span> (i = 0; i &lt; core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#c1b433c6965aa7d48f6ca6818c592039">host_channels</a>; i++) {
+<a name="l03540"></a>03540                 DWC_PRINTF(<span class="stringliteral">"Host Channel %d Specific Registers\n"</span>, i);
+<a name="l03541"></a>03541                 addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#7f7c107d4720641eb4141cd817211ac0">hc_regs</a>[i]-&gt;<a class="code" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">hcchar</a>;
+<a name="l03542"></a>03542                 DWC_PRINTF(<span class="stringliteral">"HCCHAR       @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03543"></a>03543                            dwc_read_reg32(addr));
+<a name="l03544"></a>03544                 addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#7f7c107d4720641eb4141cd817211ac0">hc_regs</a>[i]-&gt;<a class="code" href="structdwc__otg__hc__regs.html#149053001a9ee21b692afde531a814de">hcsplt</a>;
+<a name="l03545"></a>03545                 DWC_PRINTF(<span class="stringliteral">"HCSPLT       @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03546"></a>03546                            dwc_read_reg32(addr));
+<a name="l03547"></a>03547                 addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#7f7c107d4720641eb4141cd817211ac0">hc_regs</a>[i]-&gt;<a class="code" href="structdwc__otg__hc__regs.html#0dfd5bae537d58e13788508dc719480d">hcint</a>;
+<a name="l03548"></a>03548                 DWC_PRINTF(<span class="stringliteral">"HCINT        @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03549"></a>03549                            dwc_read_reg32(addr));
+<a name="l03550"></a>03550                 addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#7f7c107d4720641eb4141cd817211ac0">hc_regs</a>[i]-&gt;<a class="code" href="structdwc__otg__hc__regs.html#830aa61c1d4326823662168ea7359205">hcintmsk</a>;
+<a name="l03551"></a>03551                 DWC_PRINTF(<span class="stringliteral">"HCINTMSK     @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03552"></a>03552                            dwc_read_reg32(addr));
+<a name="l03553"></a>03553                 addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#7f7c107d4720641eb4141cd817211ac0">hc_regs</a>[i]-&gt;<a class="code" href="structdwc__otg__hc__regs.html#c6173f823ba754d9f9549422b6380ca2">hctsiz</a>;
+<a name="l03554"></a>03554                 DWC_PRINTF(<span class="stringliteral">"HCTSIZ       @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03555"></a>03555                            dwc_read_reg32(addr));
+<a name="l03556"></a>03556                 addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#7f7c107d4720641eb4141cd817211ac0">hc_regs</a>[i]-&gt;<a class="code" href="structdwc__otg__hc__regs.html#ab2148d4b5f1bf3a2ad438e497a8b4a3">hcdma</a>;
+<a name="l03557"></a>03557                 DWC_PRINTF(<span class="stringliteral">"HCDMA        @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03558"></a>03558                            dwc_read_reg32(addr));
+<a name="l03559"></a>03559                 <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a>) {
+<a name="l03560"></a>03560                         addr=&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#7f7c107d4720641eb4141cd817211ac0">hc_regs</a>[i]-&gt;<a class="code" href="structdwc__otg__hc__regs.html#602f4c6eceb8e9d4fa61f35d4149f355">hcdmab</a>;
+<a name="l03561"></a>03561                         DWC_PRINTF(<span class="stringliteral">"HCDMAB       @0x%08X : 0x%08X\n"</span>,(uint32_t) addr, dwc_read_reg32(addr));
+<a name="l03562"></a>03562         }
+<a name="l03563"></a>03563 
+<a name="l03564"></a>03564         }
+<a name="l03565"></a>03565         <span class="keywordflow">return</span>;
+<a name="l03566"></a>03566 }
+<a name="l03567"></a>03567 
+<a name="l03573"></a><a class="code" href="dwc__otg__core__if_8h.html#814be5b2f30d8321f7152fe897799224">03573</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#118ecda931e2b745f76fde129ff707c2">dwc_otg_dump_global_registers</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l03574"></a>03574 {
+<a name="l03575"></a>03575         <span class="keywordtype">int</span> i;
+<a name="l03576"></a>03576         <span class="keyword">volatile</span> uint32_t *addr;
+<a name="l03577"></a>03577 
+<a name="l03578"></a>03578         DWC_PRINTF(<span class="stringliteral">"Core Global Registers\n"</span>);
+<a name="l03579"></a>03579         addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#54034d00bb6b47ada4e0c0baa87cbd8a">gotgctl</a>;
+<a name="l03580"></a>03580         DWC_PRINTF(<span class="stringliteral">"GOTGCTL      @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03581"></a>03581                    dwc_read_reg32(addr));
+<a name="l03582"></a>03582         addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#69cc290cfdfe6900890f7a5a16b3137c">gotgint</a>;
+<a name="l03583"></a>03583         DWC_PRINTF(<span class="stringliteral">"GOTGINT      @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03584"></a>03584                    dwc_read_reg32(addr));
+<a name="l03585"></a>03585         addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#537c95e57269fabf29c6b36ad8e1ed45">gahbcfg</a>;
+<a name="l03586"></a>03586         DWC_PRINTF(<span class="stringliteral">"GAHBCFG      @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03587"></a>03587                    dwc_read_reg32(addr));
+<a name="l03588"></a>03588         addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#ef39e181e246447df47c56aa4e37cc42">gusbcfg</a>;
+<a name="l03589"></a>03589         DWC_PRINTF(<span class="stringliteral">"GUSBCFG      @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03590"></a>03590                    dwc_read_reg32(addr));
+<a name="l03591"></a>03591         addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#49d307957dbe53f20aa8f7a5409ee8ad">grstctl</a>;
+<a name="l03592"></a>03592         DWC_PRINTF(<span class="stringliteral">"GRSTCTL      @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03593"></a>03593                    dwc_read_reg32(addr));
+<a name="l03594"></a>03594         addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>;
+<a name="l03595"></a>03595         DWC_PRINTF(<span class="stringliteral">"GINTSTS      @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03596"></a>03596                    dwc_read_reg32(addr));
+<a name="l03597"></a>03597         addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#48827c76da2c6b18f369e2f2483cc4b6">gintmsk</a>;
+<a name="l03598"></a>03598         DWC_PRINTF(<span class="stringliteral">"GINTMSK      @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03599"></a>03599                    dwc_read_reg32(addr));
+<a name="l03600"></a>03600         addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#5e688c41f25ba8081f34cb1b2b052dbc">grxstsr</a>;
+<a name="l03601"></a>03601         DWC_PRINTF(<span class="stringliteral">"GRXSTSR      @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03602"></a>03602                    dwc_read_reg32(addr));
+<a name="l03603"></a>03603         addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#b1a8cc07a9541c9a73e864579602b79b">grxfsiz</a>;
+<a name="l03604"></a>03604         DWC_PRINTF(<span class="stringliteral">"GRXFSIZ      @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03605"></a>03605                    dwc_read_reg32(addr));
+<a name="l03606"></a>03606         addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#20fb70fe34a1a65d085b1d4e5f8d9106">gnptxfsiz</a>;
+<a name="l03607"></a>03607         DWC_PRINTF(<span class="stringliteral">"GNPTXFSIZ @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03608"></a>03608                    dwc_read_reg32(addr));
+<a name="l03609"></a>03609         addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#57dabea6f6e0bf9e1ee8e94f55b9e465">gnptxsts</a>;
+<a name="l03610"></a>03610         DWC_PRINTF(<span class="stringliteral">"GNPTXSTS     @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03611"></a>03611                    dwc_read_reg32(addr));
+<a name="l03612"></a>03612         addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#8ecf68262dbcdb6901f3011cfe35a144">gi2cctl</a>;
+<a name="l03613"></a>03613         DWC_PRINTF(<span class="stringliteral">"GI2CCTL      @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03614"></a>03614                    dwc_read_reg32(addr));
+<a name="l03615"></a>03615         addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#a12db668367caef8386d2ba20289e437">gpvndctl</a>;
+<a name="l03616"></a>03616         DWC_PRINTF(<span class="stringliteral">"GPVNDCTL     @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03617"></a>03617                    dwc_read_reg32(addr));
+<a name="l03618"></a>03618         addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#694546400c443d41b449772c8573f3e8">ggpio</a>;
+<a name="l03619"></a>03619         DWC_PRINTF(<span class="stringliteral">"GGPIO        @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03620"></a>03620                    dwc_read_reg32(addr));
+<a name="l03621"></a>03621         addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#8735ca2e93c1e984ac2d5bcf0cda96d7">guid</a>;
+<a name="l03622"></a>03622         DWC_PRINTF(<span class="stringliteral">"GUID                 @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03623"></a>03623                    dwc_read_reg32(addr));
+<a name="l03624"></a>03624         addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#30798436df220217c3960ac4a46710dc">gsnpsid</a>;
+<a name="l03625"></a>03625         DWC_PRINTF(<span class="stringliteral">"GSNPSID      @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03626"></a>03626                    dwc_read_reg32(addr));
+<a name="l03627"></a>03627         addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#56d2988ff8fedbbde479ffe8d4e84b75">ghwcfg1</a>;
+<a name="l03628"></a>03628         DWC_PRINTF(<span class="stringliteral">"GHWCFG1      @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03629"></a>03629                    dwc_read_reg32(addr));
+<a name="l03630"></a>03630         addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#b0f241f53ca7b3be1c94bd684ed61f79">ghwcfg2</a>;
+<a name="l03631"></a>03631         DWC_PRINTF(<span class="stringliteral">"GHWCFG2      @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03632"></a>03632                    dwc_read_reg32(addr));
+<a name="l03633"></a>03633         addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#57ddcc14f581f5d6276122f9747aff72">ghwcfg3</a>;
+<a name="l03634"></a>03634         DWC_PRINTF(<span class="stringliteral">"GHWCFG3      @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03635"></a>03635                    dwc_read_reg32(addr));
+<a name="l03636"></a>03636         addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#e1df73c776d3b31d5f0a501ccdeb1d2d">ghwcfg4</a>;
+<a name="l03637"></a>03637         DWC_PRINTF(<span class="stringliteral">"GHWCFG4      @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03638"></a>03638                    dwc_read_reg32(addr));
+<a name="l03639"></a>03639         addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#843cfb38ba366a9a46ad07ed11eb8396">glpmcfg</a>;
+<a name="l03640"></a>03640         DWC_PRINTF(<span class="stringliteral">"GLPMCFG      @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03641"></a>03641                    dwc_read_reg32(addr));
+<a name="l03642"></a>03642         addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#94ae41f04d5a4244a8ebc23e51187e96">hptxfsiz</a>;
+<a name="l03643"></a>03643         DWC_PRINTF(<span class="stringliteral">"HPTXFSIZ     @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03644"></a>03644                    dwc_read_reg32(addr));
+<a name="l03645"></a>03645 
+<a name="l03646"></a>03646         <span class="keywordflow">for</span> (i = 0; i &lt; core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#9c1394f3c46adde2fa7be79bf0237f9b">hwcfg4</a>.<a class="code" href="unionhwcfg4__data.html#9fb9175668e2381c568c5adbf6e5225d">b</a>.<a class="code" href="unionhwcfg4__data.html#aee60fb196cf53b610df556744e4d317">num_dev_perio_in_ep</a>; i++) {
+<a name="l03647"></a>03647                 addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#efd9e780825f992dbc6cf46d2d72869e">dptxfsiz_dieptxf</a>[i];
+<a name="l03648"></a>03648                 DWC_PRINTF(<span class="stringliteral">"DPTXFSIZ[%d] @0x%08X : 0x%08X\n"</span>, i,
+<a name="l03649"></a>03649                            (uint32_t) addr, dwc_read_reg32(addr));
+<a name="l03650"></a>03650         }
+<a name="l03651"></a>03651         addr = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#348ed2c9aeae6fc608f1bb813978b3f9">pcgcctl</a>;
+<a name="l03652"></a>03652         DWC_PRINTF(<span class="stringliteral">"PCGCCTL      @0x%08X : 0x%08X\n"</span>, (uint32_t) addr,
+<a name="l03653"></a>03653                    dwc_read_reg32(addr));
+<a name="l03654"></a>03654 }
+<a name="l03655"></a>03655 
+<a name="l03662"></a><a class="code" href="dwc__otg__cil_8h.html#f92d866287dce46d9e150c48901086bf">03662</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#039e387cd0e0282727da3c5a36f4cdda">dwc_otg_flush_tx_fifo</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, <span class="keyword">const</span> <span class="keywordtype">int</span> num)
+<a name="l03663"></a>03663 {
+<a name="l03664"></a>03664         <a class="code" href="structdwc__otg__core__global__regs.html">dwc_otg_core_global_regs_t</a> *global_regs = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>;
+<a name="l03665"></a>03665         <span class="keyword">volatile</span> <a class="code" href="uniongrstctl__data.html">grstctl_t</a> greset = {.d32 = 0 };
+<a name="l03666"></a>03666         <span class="keywordtype">int</span> count = 0;
+<a name="l03667"></a>03667 
+<a name="l03668"></a>03668         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>((<a class="code" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">DBG_CIL</a> | <a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>), <span class="stringliteral">"Flush Tx FIFO %d\n"</span>, num);
+<a name="l03669"></a>03669 
+<a name="l03670"></a>03670         greset.<a class="code" href="uniongrstctl__data.html#7907ac8831a2f72dec59592a093871e3">b</a>.<a class="code" href="uniongrstctl__data.html#8a5fcfc953bd0ba61beb36739c70b0ef">txfflsh</a> = 1;
+<a name="l03671"></a>03671         greset.<a class="code" href="uniongrstctl__data.html#7907ac8831a2f72dec59592a093871e3">b</a>.<a class="code" href="uniongrstctl__data.html#d074ddfa3331eeb6d088e35f4f627481">txfnum</a> = num;
+<a name="l03672"></a>03672         dwc_write_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#49d307957dbe53f20aa8f7a5409ee8ad">grstctl</a>, greset.<a class="code" href="uniongrstctl__data.html#d89d99c95bd5177fbd879d38963d3e62">d32</a>);
+<a name="l03673"></a>03673 
+<a name="l03674"></a>03674         <span class="keywordflow">do</span> {
+<a name="l03675"></a>03675                 greset.<a class="code" href="uniongrstctl__data.html#d89d99c95bd5177fbd879d38963d3e62">d32</a> = dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#49d307957dbe53f20aa8f7a5409ee8ad">grstctl</a>);
+<a name="l03676"></a>03676                 <span class="keywordflow">if</span> (++count &gt; 10000) {
+<a name="l03677"></a>03677                         DWC_WARN(<span class="stringliteral">"%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n"</span>,
+<a name="l03678"></a>03678                                  __func__, greset.<a class="code" href="uniongrstctl__data.html#d89d99c95bd5177fbd879d38963d3e62">d32</a>,
+<a name="l03679"></a>03679                                  dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#57dabea6f6e0bf9e1ee8e94f55b9e465">gnptxsts</a>));
+<a name="l03680"></a>03680                         <span class="keywordflow">break</span>;
+<a name="l03681"></a>03681                 }
+<a name="l03682"></a>03682                 dwc_udelay(1);
+<a name="l03683"></a>03683         } <span class="keywordflow">while</span> (greset.<a class="code" href="uniongrstctl__data.html#7907ac8831a2f72dec59592a093871e3">b</a>.<a class="code" href="uniongrstctl__data.html#8a5fcfc953bd0ba61beb36739c70b0ef">txfflsh</a> == 1);
+<a name="l03684"></a>03684 
+<a name="l03685"></a>03685         <span class="comment">/* Wait for 3 PHY Clocks */</span>
+<a name="l03686"></a>03686         dwc_udelay(1);
+<a name="l03687"></a>03687 }
+<a name="l03688"></a>03688 
+<a name="l03694"></a><a class="code" href="dwc__otg__cil_8h.html#07661371177fec53ba6d020320f2bae8">03694</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#fb275f0f9923cc30629fce5e3753025c">dwc_otg_flush_rx_fifo</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l03695"></a>03695 {
+<a name="l03696"></a>03696         <a class="code" href="structdwc__otg__core__global__regs.html">dwc_otg_core_global_regs_t</a> *global_regs = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>;
+<a name="l03697"></a>03697         <span class="keyword">volatile</span> <a class="code" href="uniongrstctl__data.html">grstctl_t</a> greset = {.d32 = 0 };
+<a name="l03698"></a>03698         <span class="keywordtype">int</span> count = 0;
+<a name="l03699"></a>03699 
+<a name="l03700"></a>03700         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>((<a class="code" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">DBG_CIL</a> | <a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>), <span class="stringliteral">"%s\n"</span>, __func__);
+<a name="l03701"></a>03701         <span class="comment">/*</span>
+<a name="l03702"></a>03702 <span class="comment">         * </span>
+<a name="l03703"></a>03703 <span class="comment">         */</span>
+<a name="l03704"></a>03704         greset.<a class="code" href="uniongrstctl__data.html#7907ac8831a2f72dec59592a093871e3">b</a>.<a class="code" href="uniongrstctl__data.html#88467c1f0580f4837d229d85b35c97a7">rxfflsh</a> = 1;
+<a name="l03705"></a>03705         dwc_write_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#49d307957dbe53f20aa8f7a5409ee8ad">grstctl</a>, greset.<a class="code" href="uniongrstctl__data.html#d89d99c95bd5177fbd879d38963d3e62">d32</a>);
+<a name="l03706"></a>03706 
+<a name="l03707"></a>03707         <span class="keywordflow">do</span> {
+<a name="l03708"></a>03708                 greset.<a class="code" href="uniongrstctl__data.html#d89d99c95bd5177fbd879d38963d3e62">d32</a> = dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#49d307957dbe53f20aa8f7a5409ee8ad">grstctl</a>);
+<a name="l03709"></a>03709                 <span class="keywordflow">if</span> (++count &gt; 10000) {
+<a name="l03710"></a>03710                         DWC_WARN(<span class="stringliteral">"%s() HANG! GRSTCTL=%0x\n"</span>, __func__,
+<a name="l03711"></a>03711                                  greset.<a class="code" href="uniongrstctl__data.html#d89d99c95bd5177fbd879d38963d3e62">d32</a>);
+<a name="l03712"></a>03712                         <span class="keywordflow">break</span>;
+<a name="l03713"></a>03713                 }
+<a name="l03714"></a>03714                 dwc_udelay(1);
+<a name="l03715"></a>03715         } <span class="keywordflow">while</span> (greset.<a class="code" href="uniongrstctl__data.html#7907ac8831a2f72dec59592a093871e3">b</a>.<a class="code" href="uniongrstctl__data.html#88467c1f0580f4837d229d85b35c97a7">rxfflsh</a> == 1);
+<a name="l03716"></a>03716 
+<a name="l03717"></a>03717         <span class="comment">/* Wait for 3 PHY Clocks */</span>
+<a name="l03718"></a>03718         dwc_udelay(1);
+<a name="l03719"></a>03719 }
+<a name="l03720"></a>03720 
+<a name="l03725"></a><a class="code" href="dwc__otg__cil_8h.html#c8466c3cd6229625268ec423c4b44aa4">03725</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#1edfc5634dd76db76e30f20affc10f0c">dwc_otg_core_reset</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l03726"></a>03726 {
+<a name="l03727"></a>03727         <a class="code" href="structdwc__otg__core__global__regs.html">dwc_otg_core_global_regs_t</a> *global_regs = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>;
+<a name="l03728"></a>03728         <span class="keyword">volatile</span> <a class="code" href="uniongrstctl__data.html">grstctl_t</a> greset = {.d32 = 0 };
+<a name="l03729"></a>03729         <span class="keywordtype">int</span> count = 0;
+<a name="l03730"></a>03730 
+<a name="l03731"></a>03731         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#daab8e158c0c530486656ef52e5b0bbe">DBG_CILV</a>, <span class="stringliteral">"%s\n"</span>, __func__);
+<a name="l03732"></a>03732         <span class="comment">/* Wait for AHB master IDLE state. */</span>
+<a name="l03733"></a>03733         <span class="keywordflow">do</span> {
+<a name="l03734"></a>03734                 dwc_udelay(10);
+<a name="l03735"></a>03735                 greset.<a class="code" href="uniongrstctl__data.html#d89d99c95bd5177fbd879d38963d3e62">d32</a> = dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#49d307957dbe53f20aa8f7a5409ee8ad">grstctl</a>);
+<a name="l03736"></a>03736                 <span class="keywordflow">if</span> (++count &gt; 100000) {
+<a name="l03737"></a>03737                         DWC_WARN(<span class="stringliteral">"%s() HANG! AHB Idle GRSTCTL=%0x\n"</span>, __func__,
+<a name="l03738"></a>03738                                  greset.<a class="code" href="uniongrstctl__data.html#d89d99c95bd5177fbd879d38963d3e62">d32</a>);
+<a name="l03739"></a>03739                         <span class="keywordflow">return</span>;
+<a name="l03740"></a>03740                 }
+<a name="l03741"></a>03741         }
+<a name="l03742"></a>03742         <span class="keywordflow">while</span> (greset.<a class="code" href="uniongrstctl__data.html#7907ac8831a2f72dec59592a093871e3">b</a>.<a class="code" href="uniongrstctl__data.html#587c5ec6713e2626db517105ab9aea3e">ahbidle</a> == 0);
+<a name="l03743"></a>03743 
+<a name="l03744"></a>03744         <span class="comment">/* Core Soft Reset */</span>
+<a name="l03745"></a>03745         count = 0;
+<a name="l03746"></a>03746         greset.<a class="code" href="uniongrstctl__data.html#7907ac8831a2f72dec59592a093871e3">b</a>.<a class="code" href="uniongrstctl__data.html#82df3462742f67d18b2964fafc0d9c02">csftrst</a> = 1;
+<a name="l03747"></a>03747         dwc_write_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#49d307957dbe53f20aa8f7a5409ee8ad">grstctl</a>, greset.<a class="code" href="uniongrstctl__data.html#d89d99c95bd5177fbd879d38963d3e62">d32</a>);
+<a name="l03748"></a>03748         <span class="keywordflow">do</span> {
+<a name="l03749"></a>03749                 greset.<a class="code" href="uniongrstctl__data.html#d89d99c95bd5177fbd879d38963d3e62">d32</a> = dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#49d307957dbe53f20aa8f7a5409ee8ad">grstctl</a>);
+<a name="l03750"></a>03750                 <span class="keywordflow">if</span> (++count &gt; 10000) {
+<a name="l03751"></a>03751                         DWC_WARN(<span class="stringliteral">"%s() HANG! Soft Reset GRSTCTL=%0x\n"</span>,
+<a name="l03752"></a>03752                                  __func__, greset.<a class="code" href="uniongrstctl__data.html#d89d99c95bd5177fbd879d38963d3e62">d32</a>);
+<a name="l03753"></a>03753                         <span class="keywordflow">break</span>;
+<a name="l03754"></a>03754                 }
+<a name="l03755"></a>03755                 dwc_udelay(1);
+<a name="l03756"></a>03756         }
+<a name="l03757"></a>03757         <span class="keywordflow">while</span> (greset.<a class="code" href="uniongrstctl__data.html#7907ac8831a2f72dec59592a093871e3">b</a>.<a class="code" href="uniongrstctl__data.html#82df3462742f67d18b2964fafc0d9c02">csftrst</a> == 1);
+<a name="l03758"></a>03758 
+<a name="l03759"></a>03759         <span class="comment">/* Wait for 3 PHY Clocks */</span>
+<a name="l03760"></a>03760         dwc_mdelay(100);
+<a name="l03761"></a>03761 }
+<a name="l03762"></a>03762 
+<a name="l03763"></a><a class="code" href="dwc__otg__core__if_8h.html#e83fb22890bc54c6b06cedb751430e77">03763</a> uint8_t <a class="code" href="dwc__otg__cil_8c.html#e83fb22890bc54c6b06cedb751430e77">dwc_otg_is_device_mode</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * _core_if)
+<a name="l03764"></a>03764 {
+<a name="l03765"></a>03765         <span class="keywordflow">return</span> (<a class="code" href="dwc__otg__cil_8h.html#de0ac73b05fc306b04614f73b890a364">dwc_otg_mode</a>(_core_if) != <a class="code" href="dwc__otg__regs_8h.html#dc3fa334f676024ecd75f63f885d4ec3">DWC_HOST_MODE</a>);
+<a name="l03766"></a>03766 }
+<a name="l03767"></a>03767 
+<a name="l03768"></a><a class="code" href="dwc__otg__core__if_8h.html#f0bfe5f933e21a94ea06c96ffc086e72">03768</a> uint8_t <a class="code" href="dwc__otg__cil_8c.html#f0bfe5f933e21a94ea06c96ffc086e72">dwc_otg_is_host_mode</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * _core_if)
+<a name="l03769"></a>03769 {
+<a name="l03770"></a>03770         <span class="keywordflow">return</span> (<a class="code" href="dwc__otg__cil_8h.html#de0ac73b05fc306b04614f73b890a364">dwc_otg_mode</a>(_core_if) == <a class="code" href="dwc__otg__regs_8h.html#dc3fa334f676024ecd75f63f885d4ec3">DWC_HOST_MODE</a>);
+<a name="l03771"></a>03771 }
+<a name="l03772"></a>03772 
+<a name="l03781"></a><a class="code" href="dwc__otg__cil_8h.html#b8a0bb1f2b02714a0186656c4e315ef6">03781</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#97c9b9d68211477e486848203def0d0f">dwc_otg_cil_register_hcd_callbacks</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if,
+<a name="l03782"></a>03782                                         <a class="code" href="structdwc__otg__cil__callbacks.html">dwc_otg_cil_callbacks_t</a> * cb, <span class="keywordtype">void</span> *p)
+<a name="l03783"></a>03783 {
+<a name="l03784"></a>03784         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#9a8568a762af68c9b0d97e0278cc26ba">hcd_cb</a> = cb;
+<a name="l03785"></a>03785         cb-&gt;<a class="code" href="structdwc__otg__cil__callbacks.html#a486473d73fb104dc3a37e963a8ef8e5">p</a> = p;
+<a name="l03786"></a>03786 }
+<a name="l03787"></a>03787 
+<a name="l03796"></a><a class="code" href="dwc__otg__cil_8h.html#0ffb9dfee005bc3da77eb52f96a87fc8">03796</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#d2a92003214f444d7ec35dd0c4bb4bc0">dwc_otg_cil_register_pcd_callbacks</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if,
+<a name="l03797"></a>03797                                         <a class="code" href="structdwc__otg__cil__callbacks.html">dwc_otg_cil_callbacks_t</a> * cb, <span class="keywordtype">void</span> *p)
+<a name="l03798"></a>03798 {
+<a name="l03799"></a>03799         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#83bca1e02fafc4bbfa9c1f2eeb19b245">pcd_cb</a> = cb;
+<a name="l03800"></a>03800         cb-&gt;<a class="code" href="structdwc__otg__cil__callbacks.html#a486473d73fb104dc3a37e963a8ef8e5">p</a> = p;
+<a name="l03801"></a>03801 }
+<a name="l03802"></a>03802 
+<a name="l03803"></a>03803 <span class="preprocessor">#ifdef DWC_EN_ISOC</span>
+<a name="l03804"></a>03804 <span class="preprocessor"></span>
+<a name="l03812"></a><a class="code" href="dwc__otg__cil_8c.html#e39d47d3aee9efcd525c13ce6a1f5f6a">03812</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#e39d47d3aee9efcd525c13ce6a1f5f6a">write_isoc_frame_data</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, <a class="code" href="structdwc__ep.html">dwc_ep_t</a> * <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>)
+<a name="l03813"></a>03813 {
+<a name="l03814"></a>03814         <a class="code" href="structdwc__otg__dev__in__ep__regs.html">dwc_otg_dev_in_ep_regs_t</a> *ep_regs;
+<a name="l03815"></a>03815         <a class="code" href="uniondtxfsts__data.html">dtxfsts_data_t</a> txstatus = {.d32 = 0 };
+<a name="l03816"></a>03816         uint32_t len = 0;
+<a name="l03817"></a>03817         uint32_t dwords;
+<a name="l03818"></a>03818 
+<a name="l03819"></a>03819         <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_len = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;data_per_frame;
+<a name="l03820"></a>03820         <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_count = 0;
+<a name="l03821"></a>03821 
+<a name="l03822"></a>03822         ep_regs = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;num];
+<a name="l03823"></a>03823 
+<a name="l03824"></a>03824         len = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_len - <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_count;
+<a name="l03825"></a>03825 
+<a name="l03826"></a>03826         <span class="keywordflow">if</span> (len &gt; <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;maxpacket) {
+<a name="l03827"></a>03827                 len = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;maxpacket;
+<a name="l03828"></a>03828         }
+<a name="l03829"></a>03829 
+<a name="l03830"></a>03830         dwords = (len + 3) / 4;
+<a name="l03831"></a>03831 
+<a name="l03832"></a>03832         <span class="comment">/* While there is space in the queue and space in the FIFO and</span>
+<a name="l03833"></a>03833 <span class="comment">         * More data to tranfer, Write packets to the Tx FIFO */</span>
+<a name="l03834"></a>03834         txstatus.<a class="code" href="uniondtxfsts__data.html#684b8a9ccf83a5807e9bb3491c662c39">d32</a> =
+<a name="l03835"></a>03835             dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;num]-&gt;dtxfsts);
+<a name="l03836"></a>03836         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"b4 dtxfsts[%d]=0x%08x\n"</span>, <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;num, txstatus.<a class="code" href="uniondtxfsts__data.html#684b8a9ccf83a5807e9bb3491c662c39">d32</a>);
+<a name="l03837"></a>03837 
+<a name="l03838"></a>03838         <span class="keywordflow">while</span> (txstatus.<a class="code" href="uniondtxfsts__data.html#168f673549aad11d0d9fdc06ee6c5480">b</a>.<a class="code" href="uniondtxfsts__data.html#83db0e2dbe071694f549a383b7037b3b">txfspcavail</a> &gt; dwords &amp;&amp;
+<a name="l03839"></a>03839                <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_count &lt; <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_len &amp;&amp; <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_len != 0) {
+<a name="l03840"></a>03840                 <span class="comment">/* Write the FIFO */</span>
+<a name="l03841"></a>03841                 <a class="code" href="dwc__otg__cil_8c.html#97a11808b8b12a365a91f02b6d686d0c">dwc_otg_ep_write_packet</a>(core_if, <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>, 0);
+<a name="l03842"></a>03842 
+<a name="l03843"></a>03843                 len = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_len - <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_count;
+<a name="l03844"></a>03844                 <span class="keywordflow">if</span> (len &gt; <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;maxpacket) {
+<a name="l03845"></a>03845                         len = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;maxpacket;
+<a name="l03846"></a>03846                 }
+<a name="l03847"></a>03847 
+<a name="l03848"></a>03848                 dwords = (len + 3) / 4;
+<a name="l03849"></a>03849                 txstatus.<a class="code" href="uniondtxfsts__data.html#684b8a9ccf83a5807e9bb3491c662c39">d32</a> =
+<a name="l03850"></a>03850                     dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;num]-&gt;
+<a name="l03851"></a>03851                                    dtxfsts);
+<a name="l03852"></a>03852                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"dtxfsts[%d]=0x%08x\n"</span>, <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;num,
+<a name="l03853"></a>03853                             txstatus.<a class="code" href="uniondtxfsts__data.html#684b8a9ccf83a5807e9bb3491c662c39">d32</a>);
+<a name="l03854"></a>03854         }
+<a name="l03855"></a>03855 }
+<a name="l03856"></a>03856 
+<a name="l03864"></a><a class="code" href="dwc__otg__cil_8h.html#0f0894ae9890260e1da839aa10af35cc">03864</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#0f0894ae9890260e1da839aa10af35cc">dwc_otg_iso_ep_start_frm_transfer</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if,
+<a name="l03865"></a>03865                                        <a class="code" href="structdwc__ep.html">dwc_ep_t</a> * <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>)
+<a name="l03866"></a>03866 {
+<a name="l03867"></a>03867         <a class="code" href="uniondeptsiz__data.html">deptsiz_data_t</a> deptsiz = {.d32 = 0 };
+<a name="l03868"></a>03868         <a class="code" href="uniondepctl__data.html">depctl_data_t</a> depctl = {.d32 = 0 };
+<a name="l03869"></a>03869         <a class="code" href="uniondsts__data.html">dsts_data_t</a> dsts = {.d32 = 0 };
+<a name="l03870"></a>03870         <span class="keyword">volatile</span> uint32_t *addr;
+<a name="l03871"></a>03871 
+<a name="l03872"></a>03872         <span class="keywordflow">if</span> (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;is_in) {
+<a name="l03873"></a>03873                 addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;num]-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#53a5adb977e2aec66d4902c6ba293216">diepctl</a>;
+<a name="l03874"></a>03874         } <span class="keywordflow">else</span> {
+<a name="l03875"></a>03875                 addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">out_ep_regs</a>[<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;num]-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#2a522b71fc97658c07debf3521f7d3e5">doepctl</a>;
+<a name="l03876"></a>03876         }
+<a name="l03877"></a>03877 
+<a name="l03878"></a>03878         <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_len = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;data_per_frame;
+<a name="l03879"></a>03879         <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_count = 0;
+<a name="l03880"></a>03880         <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_buff = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;cur_pkt_addr;
+<a name="l03881"></a>03881         <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;dma_addr = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;cur_pkt_dma_addr;
+<a name="l03882"></a>03882 
+<a name="l03883"></a>03883         <span class="keywordflow">if</span> (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;is_in) {
+<a name="l03884"></a>03884                 <span class="comment">/* Program the transfer size and packet count</span>
+<a name="l03885"></a>03885 <span class="comment">                 *      as follows: xfersize = N * maxpacket +</span>
+<a name="l03886"></a>03886 <span class="comment">                 *      short_packet pktcnt = N + (short_packet</span>
+<a name="l03887"></a>03887 <span class="comment">                 *      exist ? 1 : 0)  </span>
+<a name="l03888"></a>03888 <span class="comment">                 */</span>
+<a name="l03889"></a>03889                 deptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#cf06327d851e7cfe5c442b29bf2d6fa4">xfersize</a> = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_len;
+<a name="l03890"></a>03890                 deptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#bbd89e812371e5b555bb82373f3643d9">pktcnt</a> =
+<a name="l03891"></a>03891                     (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_len - 1 + <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;maxpacket) / <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;maxpacket;
+<a name="l03892"></a>03892                 deptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#45a97381fba9a7d9c3bde425334a60a5">mc</a> = deptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#bbd89e812371e5b555bb82373f3643d9">pktcnt</a>;
+<a name="l03893"></a>03893                 dwc_write_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;num]-&gt;dieptsiz,
+<a name="l03894"></a>03894                                 deptsiz.<a class="code" href="uniondeptsiz__data.html#10c2b2ba8b419b0a766430a59befbbe0">d32</a>);
+<a name="l03895"></a>03895 
+<a name="l03896"></a>03896                 <span class="comment">/* Write the DMA register */</span>
+<a name="l03897"></a>03897                 <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a>) {
+<a name="l03898"></a>03898                         dwc_write_reg32(&amp;
+<a name="l03899"></a>03899                                         (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;num]-&gt;
+<a name="l03900"></a>03900                                          diepdma), (uint32_t) <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;dma_addr);
+<a name="l03901"></a>03901                 }
+<a name="l03902"></a>03902         } <span class="keywordflow">else</span> {
+<a name="l03903"></a>03903                 deptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#bbd89e812371e5b555bb82373f3643d9">pktcnt</a> =
+<a name="l03904"></a>03904                     (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;xfer_len + (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;maxpacket - 1)) / <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;maxpacket;
+<a name="l03905"></a>03905                 deptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#cf06327d851e7cfe5c442b29bf2d6fa4">xfersize</a> = deptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#bbd89e812371e5b555bb82373f3643d9">pktcnt</a> * <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;maxpacket;
+<a name="l03906"></a>03906 
+<a name="l03907"></a>03907                 dwc_write_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">out_ep_regs</a>[<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;num]-&gt;
+<a name="l03908"></a>03908                                 doeptsiz, deptsiz.<a class="code" href="uniondeptsiz__data.html#10c2b2ba8b419b0a766430a59befbbe0">d32</a>);
+<a name="l03909"></a>03909 
+<a name="l03910"></a>03910                 <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a>) {
+<a name="l03911"></a>03911                         dwc_write_reg32(&amp;
+<a name="l03912"></a>03912                                         (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">out_ep_regs</a>[<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;num]-&gt;
+<a name="l03913"></a>03913                                          doepdma), (uint32_t) <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;dma_addr);
+<a name="l03914"></a>03914                 }
+<a name="l03915"></a>03915         }
+<a name="l03916"></a>03916 
+<a name="l03919"></a>03919         depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a> = 0;
+<a name="l03920"></a>03920         <span class="keywordflow">if</span> (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;bInterval == 1) {
+<a name="l03921"></a>03921                 dsts.<a class="code" href="uniondsts__data.html#0f126daef735b142b06dbc4cdbe13814">d32</a> =
+<a name="l03922"></a>03922                     dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#1ed00edd20ce5db7d07666804101ec05">dsts</a>);
+<a name="l03923"></a>03923                 <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;next_frame = dsts.<a class="code" href="uniondsts__data.html#4066fcedb7ac9a88e47aa1b2df0e89ee">b</a>.<a class="code" href="uniondsts__data.html#5a81ac4848c859cbf7d494dc345a0ce8">soffn</a> + <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;bInterval;
+<a name="l03924"></a>03924 
+<a name="l03925"></a>03925                 <span class="keywordflow">if</span> (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;next_frame &amp; 0x1) {
+<a name="l03926"></a>03926                         depctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#9c0962acc0c23fe46a7738ad36634c25">setd1pid</a> = 1;
+<a name="l03927"></a>03927                 } <span class="keywordflow">else</span> {
+<a name="l03928"></a>03928                         depctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#90d89b642aafd60a6c62db5bf8396de9">setd0pid</a> = 1;
+<a name="l03929"></a>03929                 }
+<a name="l03930"></a>03930         } <span class="keywordflow">else</span> {
+<a name="l03931"></a>03931                 <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;next_frame += <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;bInterval;
+<a name="l03932"></a>03932 
+<a name="l03933"></a>03933                 <span class="keywordflow">if</span> (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;next_frame &amp; 0x1) {
+<a name="l03934"></a>03934                         depctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#9c0962acc0c23fe46a7738ad36634c25">setd1pid</a> = 1;
+<a name="l03935"></a>03935                 } <span class="keywordflow">else</span> {
+<a name="l03936"></a>03936                         depctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#90d89b642aafd60a6c62db5bf8396de9">setd0pid</a> = 1;
+<a name="l03937"></a>03937                 }
+<a name="l03938"></a>03938         }
+<a name="l03939"></a>03939         depctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#337ceb41a9e0735e144e684b1f9e5368">epena</a> = 1;
+<a name="l03940"></a>03940         depctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#0b87d0914ceee7a20ffd2d7510b6a72e">cnak</a> = 1;
+<a name="l03941"></a>03941 
+<a name="l03942"></a>03942         dwc_modify_reg32(addr, 0, depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a>);
+<a name="l03943"></a>03943         depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a> = dwc_read_reg32(addr);
+<a name="l03944"></a>03944 
+<a name="l03945"></a>03945         <span class="keywordflow">if</span> (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;is_in &amp;&amp; core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a> == 0) {
+<a name="l03946"></a>03946                 <a class="code" href="dwc__otg__cil_8c.html#e39d47d3aee9efcd525c13ce6a1f5f6a">write_isoc_frame_data</a>(core_if, <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>);
+<a name="l03947"></a>03947         }
+<a name="l03948"></a>03948 
+<a name="l03949"></a>03949 }
+<a name="l03950"></a>03950 <span class="preprocessor">#endif                          </span><span class="comment">/* DWC_EN_ISOC */</span>
+<a name="l03951"></a>03951 
+<a name="l03952"></a><a class="code" href="dwc__otg__cil_8c.html#322ac38f3a85f48410ed6e91adce3955">03952</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#322ac38f3a85f48410ed6e91adce3955">dwc_otg_set_uninitialized</a>(int32_t * p, <span class="keywordtype">int</span> size)
+<a name="l03953"></a>03953 {
+<a name="l03954"></a>03954         <span class="keywordtype">int</span> i;
+<a name="l03955"></a>03955         <span class="keywordflow">for</span> (i = 0; i &lt; size; i++) {
+<a name="l03956"></a>03956                 p[i] = -1;
+<a name="l03957"></a>03957         }
+<a name="l03958"></a>03958 }
+<a name="l03959"></a>03959 
+<a name="l03960"></a><a class="code" href="dwc__otg__cil_8c.html#d3dd61d5d48c2fc06bf4b2d37e848c93">03960</a> <span class="keyword">static</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#d3dd61d5d48c2fc06bf4b2d37e848c93">dwc_otg_param_initialized</a>(int32_t val)
+<a name="l03961"></a>03961 {
+<a name="l03962"></a>03962         <span class="keywordflow">return</span> val != -1;
+<a name="l03963"></a>03963 }
+<a name="l03964"></a>03964 
+<a name="l03965"></a><a class="code" href="dwc__otg__cil_8c.html#2be12d7b5990c6eaac2f1a5fb688f2f8">03965</a> <span class="keyword">static</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#2be12d7b5990c6eaac2f1a5fb688f2f8">dwc_otg_setup_params</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l03966"></a>03966 {
+<a name="l03967"></a>03967         <span class="keywordtype">int</span> i;
+<a name="l03968"></a>03968         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a> = DWC_ALLOC(<span class="keyword">sizeof</span>(*core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>));
+<a name="l03969"></a>03969         <span class="keywordflow">if</span> (!core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>) {
+<a name="l03970"></a>03970                 <span class="keywordflow">return</span> -DWC_E_NO_MEMORY;
+<a name="l03971"></a>03971         }
+<a name="l03972"></a>03972         <a class="code" href="dwc__otg__cil_8c.html#322ac38f3a85f48410ed6e91adce3955">dwc_otg_set_uninitialized</a>((int32_t *) core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>,
+<a name="l03973"></a>03973                                   <span class="keyword">sizeof</span>(*core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>) /
+<a name="l03974"></a>03974                                   <span class="keyword">sizeof</span>(int32_t));
+<a name="l03975"></a>03975         DWC_PRINTF(<span class="stringliteral">"Setting default values for core params\n"</span>);
+<a name="l03976"></a>03976         <a class="code" href="dwc__otg__cil_8c.html#878cc478f43c58991c446bd78f50f8f0">dwc_otg_set_param_otg_cap</a>(core_if, <a class="code" href="dwc__otg__core__if_8h.html#64e4ebd3b09e2ed667ab4c1438424e92">dwc_param_otg_cap_default</a>);
+<a name="l03977"></a>03977         <a class="code" href="dwc__otg__cil_8c.html#b4fbe11281b8200b70202d4e0048a9d7">dwc_otg_set_param_dma_enable</a>(core_if, <a class="code" href="dwc__otg__core__if_8h.html#2d5fa78eb125e55111bb7a61c5cc13de">dwc_param_dma_enable_default</a>);
+<a name="l03978"></a>03978         <a class="code" href="dwc__otg__cil_8c.html#7eae744525314774d3b390f116db126c">dwc_otg_set_param_dma_desc_enable</a>(core_if,
+<a name="l03979"></a>03979                                           <a class="code" href="dwc__otg__core__if_8h.html#a3a57c75cfc0c2e2178d8db079c8185e">dwc_param_dma_desc_enable_default</a>);
+<a name="l03980"></a>03980         <a class="code" href="dwc__otg__cil_8c.html#d0603b00a0ff87007ded1c06613d6b87">dwc_otg_set_param_opt</a>(core_if, <a class="code" href="dwc__otg__core__if_8h.html#a38a6bfa4913d2832ec3d7fc5d7b54a1">dwc_param_opt_default</a>);
+<a name="l03981"></a>03981         <a class="code" href="dwc__otg__cil_8c.html#920035c6082dcdfec11a20e8535e9fe9">dwc_otg_set_param_dma_burst_size</a>(core_if,
+<a name="l03982"></a>03982                                          <a class="code" href="dwc__otg__core__if_8h.html#627cfe039c4f743e12ca8d37f787a6c8">dwc_param_dma_burst_size_default</a>);
+<a name="l03983"></a>03983         <a class="code" href="dwc__otg__cil_8c.html#8bd669637630521655c455c03d470e10">dwc_otg_set_param_host_support_fs_ls_low_power</a>(core_if,
+<a name="l03984"></a>03984                                                        <a class="code" href="dwc__otg__core__if_8h.html#3df14e916b2c9c2172240d6103d0df98">dwc_param_host_support_fs_ls_low_power_default</a>);
+<a name="l03985"></a>03985         <a class="code" href="dwc__otg__cil_8c.html#61bb728cc80220e5173d5e3126dd4fd1">dwc_otg_set_param_enable_dynamic_fifo</a>(core_if,
+<a name="l03986"></a>03986                                               <a class="code" href="dwc__otg__core__if_8h.html#8b88b4426126f04a71603df7401b19df">dwc_param_enable_dynamic_fifo_default</a>);
+<a name="l03987"></a>03987         <a class="code" href="dwc__otg__cil_8c.html#69d52c46eb236816b20675ecb57975ae">dwc_otg_set_param_data_fifo_size</a>(core_if,
+<a name="l03988"></a>03988                                          <a class="code" href="dwc__otg__core__if_8h.html#f115dcb7c077b31659173f7f33edefff">dwc_param_data_fifo_size_default</a>);
+<a name="l03989"></a>03989         <a class="code" href="dwc__otg__cil_8c.html#0fa4db196053869ac19832c03c62913f">dwc_otg_set_param_dev_rx_fifo_size</a>(core_if,
+<a name="l03990"></a>03990                                            <a class="code" href="dwc__otg__core__if_8h.html#cd0a0b07970f53d4cc9c4ec689d6f29d">dwc_param_dev_rx_fifo_size_default</a>);
+<a name="l03991"></a>03991         <a class="code" href="dwc__otg__cil_8c.html#4f7059cecabbf8cfe5014112ba9a3d42">dwc_otg_set_param_dev_nperio_tx_fifo_size</a>(core_if,
+<a name="l03992"></a>03992                                                   <a class="code" href="dwc__otg__core__if_8h.html#d068247cd8a85a6f3e7b12911082c0a1">dwc_param_dev_nperio_tx_fifo_size_default</a>);
+<a name="l03993"></a>03993         <a class="code" href="dwc__otg__cil_8c.html#254c1e97cf22fe34b7383165e30071eb">dwc_otg_set_param_host_rx_fifo_size</a>(core_if,
+<a name="l03994"></a>03994                                             <a class="code" href="dwc__otg__core__if_8h.html#90093ab1ac67472188e46fe171e7edc1">dwc_param_host_rx_fifo_size_default</a>);
+<a name="l03995"></a>03995         <a class="code" href="dwc__otg__cil_8c.html#a66ca9f9345a13606148b050f8690a56">dwc_otg_set_param_host_nperio_tx_fifo_size</a>(core_if,
+<a name="l03996"></a>03996                                                    <a class="code" href="dwc__otg__core__if_8h.html#a0ef15f080c34d1ca47159d6aec1d691">dwc_param_host_nperio_tx_fifo_size_default</a>);
+<a name="l03997"></a>03997         <a class="code" href="dwc__otg__cil_8c.html#e4ce399208d8a85dcb9dedd1fb8cd8ce">dwc_otg_set_param_host_perio_tx_fifo_size</a>(core_if,
+<a name="l03998"></a>03998                                                   <a class="code" href="dwc__otg__core__if_8h.html#b2540fa14f8256322fe99931f5d74025">dwc_param_host_perio_tx_fifo_size_default</a>);
+<a name="l03999"></a>03999         <a class="code" href="dwc__otg__cil_8c.html#2eee676071d6bb4eba53b413e80b045f">dwc_otg_set_param_max_transfer_size</a>(core_if,
+<a name="l04000"></a>04000                                             <a class="code" href="dwc__otg__core__if_8h.html#dafcc111c37c08300b380509e8b60b84">dwc_param_max_transfer_size_default</a>);
+<a name="l04001"></a>04001         <a class="code" href="dwc__otg__cil_8c.html#a1c52f0740f7d0b72c980b38cc4314d1">dwc_otg_set_param_max_packet_count</a>(core_if,
+<a name="l04002"></a>04002                                            <a class="code" href="dwc__otg__core__if_8h.html#157ed6a26b1bb4b14008edc2e17b5645">dwc_param_max_packet_count_default</a>);
+<a name="l04003"></a>04003         <a class="code" href="dwc__otg__cil_8c.html#f802acfc49b3fbb86159036f8f317f76">dwc_otg_set_param_host_channels</a>(core_if,
+<a name="l04004"></a>04004                                         <a class="code" href="dwc__otg__core__if_8h.html#84c89a21c7e8319b996bbad29cf486ca">dwc_param_host_channels_default</a>);
+<a name="l04005"></a>04005         <a class="code" href="dwc__otg__cil_8c.html#75d3b409824c0ca52631277398ba8367">dwc_otg_set_param_dev_endpoints</a>(core_if,
+<a name="l04006"></a>04006                                         <a class="code" href="dwc__otg__core__if_8h.html#6c0b373c7d629c87007fe125fa029aa4">dwc_param_dev_endpoints_default</a>);
+<a name="l04007"></a>04007         <a class="code" href="dwc__otg__cil_8c.html#2b7087c85c0ea1520ec2e091b80bf36b">dwc_otg_set_param_phy_type</a>(core_if, <a class="code" href="dwc__otg__core__if_8h.html#e9ecfde05af7206a4fe15f18d12fc47e">dwc_param_phy_type_default</a>);
+<a name="l04008"></a>04008         <a class="code" href="dwc__otg__cil_8c.html#7acd153b5577a3db825fa08d243ae856">dwc_otg_set_param_speed</a>(core_if, <a class="code" href="dwc__otg__core__if_8h.html#43d7e266ea8e39002a96578e9ab5e70d">dwc_param_speed_default</a>);
+<a name="l04009"></a>04009         <a class="code" href="dwc__otg__cil_8c.html#354ce49f65334e829c2694811c4f2016">dwc_otg_set_param_host_ls_low_power_phy_clk</a>(core_if,
+<a name="l04010"></a>04010                                                     <a class="code" href="dwc__otg__core__if_8h.html#ff8cfea2259a0d456576ef255b60bbb9">dwc_param_host_ls_low_power_phy_clk_default</a>);
+<a name="l04011"></a>04011         <a class="code" href="dwc__otg__cil_8c.html#5dab15db053bd02c6bc9619e189a6a14">dwc_otg_set_param_phy_ulpi_ddr</a>(core_if, <a class="code" href="dwc__otg__core__if_8h.html#e500bb317e047963e0bff06de78a8835">dwc_param_phy_ulpi_ddr_default</a>);
+<a name="l04012"></a>04012         <a class="code" href="dwc__otg__cil_8c.html#a12296bcb04a3b0f6f80037590e97bec">dwc_otg_set_param_phy_ulpi_ext_vbus</a>(core_if,
+<a name="l04013"></a>04013                                             <a class="code" href="dwc__otg__core__if_8h.html#c1530e5f28eabbaa1d25267a5435de87">dwc_param_phy_ulpi_ext_vbus_default</a>);
+<a name="l04014"></a>04014         <a class="code" href="dwc__otg__cil_8c.html#1eacecc96e1ab100cbf129ad6aa5f6c8">dwc_otg_set_param_phy_utmi_width</a>(core_if,
+<a name="l04015"></a>04015                                          <a class="code" href="dwc__otg__core__if_8h.html#628748b25af7b09c91c9b40a801fd1c2">dwc_param_phy_utmi_width_default</a>);
+<a name="l04016"></a>04016         <a class="code" href="dwc__otg__cil_8c.html#b05c92754c0ebc3d58ea0c090b9659de">dwc_otg_set_param_ts_dline</a>(core_if, <a class="code" href="dwc__otg__core__if_8h.html#f65e86f5f54b329161081f4016162ec0">dwc_param_ts_dline_default</a>);
+<a name="l04017"></a>04017         <a class="code" href="dwc__otg__cil_8c.html#65d7407ed24c82e158a38ab2a60120c4">dwc_otg_set_param_i2c_enable</a>(core_if, <a class="code" href="dwc__otg__core__if_8h.html#5f6376ff90b4206f1411ad3454e32690">dwc_param_i2c_enable_default</a>);
+<a name="l04018"></a>04018         <a class="code" href="dwc__otg__cil_8c.html#f235e9c7b844b899d759a073a84f782f">dwc_otg_set_param_ulpi_fs_ls</a>(core_if, <a class="code" href="dwc__otg__core__if_8h.html#7db2560bca75c28869d6fdf302dd3cae">dwc_param_ulpi_fs_ls_default</a>);
+<a name="l04019"></a>04019         <a class="code" href="dwc__otg__cil_8c.html#2eefd02d72c79200072d54b4eb13e5cd">dwc_otg_set_param_en_multiple_tx_fifo</a>(core_if,
+<a name="l04020"></a>04020                                               <a class="code" href="dwc__otg__core__if_8h.html#ea0a79ef09fcf9078c2c0779e7a36801">dwc_param_en_multiple_tx_fifo_default</a>);
+<a name="l04021"></a>04021         <span class="keywordflow">for</span> (i = 0; i &lt; 15; i++) {
+<a name="l04022"></a>04022                 <a class="code" href="dwc__otg__cil_8c.html#2119a493582bea4004b5fdeba15f1609">dwc_otg_set_param_dev_perio_tx_fifo_size</a>(core_if,
+<a name="l04023"></a>04023                                                          <a class="code" href="dwc__otg__core__if_8h.html#83815074ba10fec73bb108e1c6a739fd">dwc_param_dev_perio_tx_fifo_size_default</a>,
+<a name="l04024"></a>04024                                                          i);
+<a name="l04025"></a>04025         }
+<a name="l04026"></a>04026 
+<a name="l04027"></a>04027         <span class="keywordflow">for</span> (i = 0; i &lt; 15; i++) {
+<a name="l04028"></a>04028                 <a class="code" href="dwc__otg__cil_8c.html#44bf6b41f0892f480ea6c03a2ac1e73f">dwc_otg_set_param_dev_tx_fifo_size</a>(core_if,
+<a name="l04029"></a>04029                                                    <a class="code" href="dwc__otg__core__if_8h.html#a6ad2334d1d977070a24e671db3b8f3a">dwc_param_dev_tx_fifo_size_default</a>,
+<a name="l04030"></a>04030                                                    i);
+<a name="l04031"></a>04031         }
+<a name="l04032"></a>04032         <a class="code" href="dwc__otg__cil_8c.html#6095d6a93f901f32522d4b950c99a8e1">dwc_otg_set_param_thr_ctl</a>(core_if, <a class="code" href="dwc__otg__core__if_8h.html#11b1ee2892d3645ce27d46d2198dc241">dwc_param_thr_ctl_default</a>);
+<a name="l04033"></a>04033         <a class="code" href="dwc__otg__cil_8c.html#7ba10fdfd2ce9f3ef4b0a2bef555a7c1">dwc_otg_set_param_mpi_enable</a>(core_if, <a class="code" href="dwc__otg__core__if_8h.html#891784dcf9e045a78c14fe75c0bb0c31">dwc_param_mpi_enable_default</a>);
+<a name="l04034"></a>04034         <a class="code" href="dwc__otg__cil_8c.html#63c0b4bfcf3b1c6c90c5572258439e1f">dwc_otg_set_param_pti_enable</a>(core_if, <a class="code" href="dwc__otg__core__if_8h.html#9dc50d52206e9c2bf9b3cf184fa9a912">dwc_param_pti_enable_default</a>);
+<a name="l04035"></a>04035         <a class="code" href="dwc__otg__cil_8c.html#e3a62b66e19a302a55046830f5eecf0c">dwc_otg_set_param_lpm_enable</a>(core_if, <a class="code" href="dwc__otg__core__if_8h.html#12ae395ada45a106bdc4e6ff3006ffd7">dwc_param_lpm_enable_default</a>);
+<a name="l04036"></a>04036         <a class="code" href="dwc__otg__cil_8c.html#93036faefc8179eef11c8ca0b18993a8">dwc_otg_set_param_ic_usb_cap</a>(core_if, <a class="code" href="dwc__otg__core__if_8h.html#00e03f82db17880c007a150623471327">dwc_param_ic_usb_cap_default</a>);
+<a name="l04037"></a>04037         <a class="code" href="dwc__otg__cil_8c.html#1ed19fed8939a352f91fe1403574135e">dwc_otg_set_param_tx_thr_length</a>(core_if,
+<a name="l04038"></a>04038                                         <a class="code" href="dwc__otg__core__if_8h.html#35f8a2bd23274ef01afe6b7471603c5c">dwc_param_tx_thr_length_default</a>);
+<a name="l04039"></a>04039         <a class="code" href="dwc__otg__cil_8c.html#20d005470a65927cb243b37619f6c6bf">dwc_otg_set_param_rx_thr_length</a>(core_if,
+<a name="l04040"></a>04040                                         <a class="code" href="dwc__otg__core__if_8h.html#5ef7eee81a06fcee9a038264fcf79626">dwc_param_rx_thr_length_default</a>);
+<a name="l04041"></a>04041         <a class="code" href="dwc__otg__cil_8c.html#9bf87dcaa6dcea51eb3d8c30439a2138">dwc_otg_set_param_ahb_thr_ratio</a>(core_if, <a class="code" href="dwc__otg__core__if_8h.html#5a5f06f045acf28eca0992898545ae03">dwc_param_ahb_thr_ratio_default</a>);
+<a name="l04042"></a>04042         <span class="keywordflow">return</span> 0;
+<a name="l04043"></a>04043 }
+<a name="l04044"></a>04044 
+<a name="l04045"></a><a class="code" href="dwc__otg__core__if_8h.html#f4f060a2decd6434bbd96703a4d1fc66">04045</a> uint8_t <a class="code" href="dwc__otg__cil_8c.html#f4f060a2decd6434bbd96703a4d1fc66">dwc_otg_is_dma_enable</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l04046"></a>04046 {
+<a name="l04047"></a>04047         <span class="keywordflow">return</span> core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a>;
+<a name="l04048"></a>04048 }
+<a name="l04049"></a>04049 
+<a name="l04050"></a>04050 <span class="comment">/* Checks if the parameter is outside of its valid range of values */</span>
+<a name="l04051"></a><a class="code" href="dwc__otg__cil_8c.html#c4138a87302505f6ef79dc3bfb4951c0">04051</a> <span class="preprocessor">#define DWC_OTG_PARAM_TEST(_param_, _low_, _high_) \</span>
+<a name="l04052"></a>04052 <span class="preprocessor">                (((_param_) &lt; (_low_)) || \</span>
+<a name="l04053"></a>04053 <span class="preprocessor">                ((_param_) &gt; (_high_)))</span>
+<a name="l04054"></a>04054 <span class="preprocessor"></span>
+<a name="l04055"></a>04055 <span class="comment">/* Parameter access functions */</span>
+<a name="l04056"></a><a class="code" href="dwc__otg__core__if_8h.html#878cc478f43c58991c446bd78f50f8f0">04056</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#878cc478f43c58991c446bd78f50f8f0">dwc_otg_set_param_otg_cap</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, int32_t val)
+<a name="l04057"></a>04057 {
+<a name="l04058"></a>04058         <span class="keywordtype">int</span> valid;
+<a name="l04059"></a>04059         <span class="keywordtype">int</span> retval = 0;
+<a name="l04060"></a>04060         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#c4138a87302505f6ef79dc3bfb4951c0">DWC_OTG_PARAM_TEST</a>(val, 0, 2)) {
+<a name="l04061"></a>04061                 DWC_WARN(<span class="stringliteral">"Wrong value for otg_cap parameter\n"</span>);
+<a name="l04062"></a>04062                 DWC_WARN(<span class="stringliteral">"otg_cap parameter must be 0,1 or 2\n"</span>);
+<a name="l04063"></a>04063                 retval = -DWC_E_INVALID;
+<a name="l04064"></a>04064                 <span class="keywordflow">goto</span> out;
+<a name="l04065"></a>04065         }
+<a name="l04066"></a>04066 
+<a name="l04067"></a>04067         valid = 1;
+<a name="l04068"></a>04068         <span class="keywordflow">switch</span> (val) {
+<a name="l04069"></a>04069         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__core__if_8h.html#83c71a480363001711ff07e03834c49f">DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE</a>:
+<a name="l04070"></a>04070                 <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">hwcfg2</a>.<a class="code" href="unionhwcfg2__data.html#9dcc70e2dba617cbc6c12189be5c1d6a">b</a>.<a class="code" href="unionhwcfg2__data.html#592df9b97ff9342b839d2ed76d54c652">op_mode</a> !=
+<a name="l04071"></a>04071                     <a class="code" href="dwc__otg__regs_8h.html#8af3c99831b24f4f12a6d5c8d738b5c1">DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG</a>)
+<a name="l04072"></a>04072                         valid = 0;
+<a name="l04073"></a>04073                 <span class="keywordflow">break</span>;
+<a name="l04074"></a>04074         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__core__if_8h.html#f398fce430aa9b84d2429bad1f419d3e">DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE</a>:
+<a name="l04075"></a>04075                 <span class="keywordflow">if</span> ((core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">hwcfg2</a>.<a class="code" href="unionhwcfg2__data.html#9dcc70e2dba617cbc6c12189be5c1d6a">b</a>.<a class="code" href="unionhwcfg2__data.html#592df9b97ff9342b839d2ed76d54c652">op_mode</a> !=
+<a name="l04076"></a>04076                      <a class="code" href="dwc__otg__regs_8h.html#8af3c99831b24f4f12a6d5c8d738b5c1">DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG</a>)
+<a name="l04077"></a>04077                     &amp;&amp; (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">hwcfg2</a>.<a class="code" href="unionhwcfg2__data.html#9dcc70e2dba617cbc6c12189be5c1d6a">b</a>.<a class="code" href="unionhwcfg2__data.html#592df9b97ff9342b839d2ed76d54c652">op_mode</a> !=
+<a name="l04078"></a>04078                         <a class="code" href="dwc__otg__regs_8h.html#184dedc2208935e427ec8d70f63acc03">DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG</a>)
+<a name="l04079"></a>04079                     &amp;&amp; (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">hwcfg2</a>.<a class="code" href="unionhwcfg2__data.html#9dcc70e2dba617cbc6c12189be5c1d6a">b</a>.<a class="code" href="unionhwcfg2__data.html#592df9b97ff9342b839d2ed76d54c652">op_mode</a> !=
+<a name="l04080"></a>04080                         <a class="code" href="dwc__otg__regs_8h.html#1f8de01acf1cfba7684a6b541cdacc72">DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE</a>)
+<a name="l04081"></a>04081                     &amp;&amp; (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">hwcfg2</a>.<a class="code" href="unionhwcfg2__data.html#9dcc70e2dba617cbc6c12189be5c1d6a">b</a>.<a class="code" href="unionhwcfg2__data.html#592df9b97ff9342b839d2ed76d54c652">op_mode</a> !=
+<a name="l04082"></a>04082                       <a class="code" href="dwc__otg__regs_8h.html#77eccf27fae160a4ad7f72b1b43864c3">DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST</a>)) {
+<a name="l04083"></a>04083                         valid = 0;
+<a name="l04084"></a>04084                 }
+<a name="l04085"></a>04085                 <span class="keywordflow">break</span>;
+<a name="l04086"></a>04086         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__core__if_8h.html#42ff7d87b7b3d3a47cf1749f02ce516c">DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE</a>:
+<a name="l04087"></a>04087                 <span class="comment">/* always valid */</span>
+<a name="l04088"></a>04088                 <span class="keywordflow">break</span>;
+<a name="l04089"></a>04089         }
+<a name="l04090"></a>04090         <span class="keywordflow">if</span> (!valid) {
+<a name="l04091"></a>04091                 <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#d3dd61d5d48c2fc06bf4b2d37e848c93">dwc_otg_param_initialized</a>(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#b6960c28e9c7d82dca37645726c8f7ce">otg_cap</a>)) {
+<a name="l04092"></a>04092                         DWC_ERROR
+<a name="l04093"></a>04093                             (<span class="stringliteral">"%d invalid for otg_cap paremter. Check HW configuration.\n"</span>,
+<a name="l04094"></a>04094                              val);
+<a name="l04095"></a>04095                 }
+<a name="l04096"></a>04096                 val =
+<a name="l04097"></a>04097                     (((core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">hwcfg2</a>.<a class="code" href="unionhwcfg2__data.html#9dcc70e2dba617cbc6c12189be5c1d6a">b</a>.<a class="code" href="unionhwcfg2__data.html#592df9b97ff9342b839d2ed76d54c652">op_mode</a> ==
+<a name="l04098"></a>04098                        <a class="code" href="dwc__otg__regs_8h.html#8af3c99831b24f4f12a6d5c8d738b5c1">DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG</a>)
+<a name="l04099"></a>04099                       || (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">hwcfg2</a>.<a class="code" href="unionhwcfg2__data.html#9dcc70e2dba617cbc6c12189be5c1d6a">b</a>.<a class="code" href="unionhwcfg2__data.html#592df9b97ff9342b839d2ed76d54c652">op_mode</a> ==
+<a name="l04100"></a>04100                           <a class="code" href="dwc__otg__regs_8h.html#184dedc2208935e427ec8d70f63acc03">DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG</a>)
+<a name="l04101"></a>04101                       || (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">hwcfg2</a>.<a class="code" href="unionhwcfg2__data.html#9dcc70e2dba617cbc6c12189be5c1d6a">b</a>.<a class="code" href="unionhwcfg2__data.html#592df9b97ff9342b839d2ed76d54c652">op_mode</a> ==
+<a name="l04102"></a>04102                           <a class="code" href="dwc__otg__regs_8h.html#1f8de01acf1cfba7684a6b541cdacc72">DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE</a>)
+<a name="l04103"></a>04103                       || (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">hwcfg2</a>.<a class="code" href="unionhwcfg2__data.html#9dcc70e2dba617cbc6c12189be5c1d6a">b</a>.<a class="code" href="unionhwcfg2__data.html#592df9b97ff9342b839d2ed76d54c652">op_mode</a> ==
+<a name="l04104"></a>04104                           <a class="code" href="dwc__otg__regs_8h.html#77eccf27fae160a4ad7f72b1b43864c3">DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST</a>)) ?
+<a name="l04105"></a>04105                      <a class="code" href="dwc__otg__core__if_8h.html#f398fce430aa9b84d2429bad1f419d3e">DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE</a> :
+<a name="l04106"></a>04106                      <a class="code" href="dwc__otg__core__if_8h.html#42ff7d87b7b3d3a47cf1749f02ce516c">DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE</a>);
+<a name="l04107"></a>04107                 retval = -DWC_E_INVALID;
+<a name="l04108"></a>04108         }
+<a name="l04109"></a>04109 
+<a name="l04110"></a>04110         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#b6960c28e9c7d82dca37645726c8f7ce">otg_cap</a> = val;
+<a name="l04111"></a>04111       out:
+<a name="l04112"></a>04112         <span class="keywordflow">return</span> retval;
+<a name="l04113"></a>04113 }
+<a name="l04114"></a>04114 
+<a name="l04115"></a><a class="code" href="dwc__otg__core__if_8h.html#0896106921e87788480f078c86de274a">04115</a> int32_t <a class="code" href="dwc__otg__cil_8c.html#0896106921e87788480f078c86de274a">dwc_otg_get_param_otg_cap</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l04116"></a>04116 {
+<a name="l04117"></a>04117         <span class="keywordflow">return</span> core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#b6960c28e9c7d82dca37645726c8f7ce">otg_cap</a>;
+<a name="l04118"></a>04118 }
+<a name="l04119"></a>04119 
+<a name="l04120"></a><a class="code" href="dwc__otg__core__if_8h.html#d0603b00a0ff87007ded1c06613d6b87">04120</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#d0603b00a0ff87007ded1c06613d6b87">dwc_otg_set_param_opt</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, int32_t val)
+<a name="l04121"></a>04121 {
+<a name="l04122"></a>04122         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#c4138a87302505f6ef79dc3bfb4951c0">DWC_OTG_PARAM_TEST</a>(val, 0, 1)) {
+<a name="l04123"></a>04123                 DWC_WARN(<span class="stringliteral">"Wrong value for opt parameter\n"</span>);
+<a name="l04124"></a>04124                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l04125"></a>04125         }
+<a name="l04126"></a>04126         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#6d67db1b1152d788bf2fc7fdc6363f78">opt</a> = val;
+<a name="l04127"></a>04127         <span class="keywordflow">return</span> 0;
+<a name="l04128"></a>04128 }
+<a name="l04129"></a>04129 
+<a name="l04130"></a><a class="code" href="dwc__otg__core__if_8h.html#1b57cc827b21df14faa0eec1cbab1742">04130</a> int32_t <a class="code" href="dwc__otg__cil_8c.html#1b57cc827b21df14faa0eec1cbab1742">dwc_otg_get_param_opt</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l04131"></a>04131 {
+<a name="l04132"></a>04132         <span class="keywordflow">return</span> core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#6d67db1b1152d788bf2fc7fdc6363f78">opt</a>;
+<a name="l04133"></a>04133 }
+<a name="l04134"></a>04134 
+<a name="l04135"></a><a class="code" href="dwc__otg__core__if_8h.html#b4fbe11281b8200b70202d4e0048a9d7">04135</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#b4fbe11281b8200b70202d4e0048a9d7">dwc_otg_set_param_dma_enable</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, int32_t val)
+<a name="l04136"></a>04136 {
+<a name="l04137"></a>04137         <span class="keywordtype">int</span> retval = 0;
+<a name="l04138"></a>04138         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#c4138a87302505f6ef79dc3bfb4951c0">DWC_OTG_PARAM_TEST</a>(val, 0, 1)) {
+<a name="l04139"></a>04139                 DWC_WARN(<span class="stringliteral">"Wrong value for dma enable\n"</span>);
+<a name="l04140"></a>04140                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l04141"></a>04141         }
+<a name="l04142"></a>04142 
+<a name="l04143"></a>04143         <span class="keywordflow">if</span> ((val == 1) &amp;&amp; (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">hwcfg2</a>.<a class="code" href="unionhwcfg2__data.html#9dcc70e2dba617cbc6c12189be5c1d6a">b</a>.<a class="code" href="unionhwcfg2__data.html#e5000f58c6a0f09c75375b4c912af0eb">architecture</a> == 0)) {
+<a name="l04144"></a>04144                 <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#d3dd61d5d48c2fc06bf4b2d37e848c93">dwc_otg_param_initialized</a>(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#3c791cb4898379d156acc47c5b9a84fc">dma_enable</a>)) {
+<a name="l04145"></a>04145                         DWC_ERROR
+<a name="l04146"></a>04146                             (<span class="stringliteral">"%d invalid for dma_enable paremter. Check HW configuration.\n"</span>,
+<a name="l04147"></a>04147                              val);
+<a name="l04148"></a>04148                 }
+<a name="l04149"></a>04149                 val = 0;
+<a name="l04150"></a>04150                 retval = -DWC_E_INVALID;
+<a name="l04151"></a>04151         }
+<a name="l04152"></a>04152 
+<a name="l04153"></a>04153         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#3c791cb4898379d156acc47c5b9a84fc">dma_enable</a> = val;
+<a name="l04154"></a>04154         <span class="keywordflow">if</span> (val == 0) {
+<a name="l04155"></a>04155                 <a class="code" href="dwc__otg__cil_8c.html#7eae744525314774d3b390f116db126c">dwc_otg_set_param_dma_desc_enable</a>(core_if, 0);
+<a name="l04156"></a>04156         }
+<a name="l04157"></a>04157         <span class="keywordflow">return</span> retval;
+<a name="l04158"></a>04158 }
+<a name="l04159"></a>04159 
+<a name="l04160"></a><a class="code" href="dwc__otg__core__if_8h.html#0c78da7b7e7b59b31bd99a07d926a298">04160</a> int32_t <a class="code" href="dwc__otg__cil_8c.html#0c78da7b7e7b59b31bd99a07d926a298">dwc_otg_get_param_dma_enable</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l04161"></a>04161 {
+<a name="l04162"></a>04162         <span class="keywordflow">return</span> core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#3c791cb4898379d156acc47c5b9a84fc">dma_enable</a>;
+<a name="l04163"></a>04163 }
+<a name="l04164"></a>04164 
+<a name="l04165"></a><a class="code" href="dwc__otg__core__if_8h.html#7eae744525314774d3b390f116db126c">04165</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#7eae744525314774d3b390f116db126c">dwc_otg_set_param_dma_desc_enable</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, int32_t val)
+<a name="l04166"></a>04166 {
+<a name="l04167"></a>04167         <span class="keywordtype">int</span> retval = 0;
+<a name="l04168"></a>04168         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#c4138a87302505f6ef79dc3bfb4951c0">DWC_OTG_PARAM_TEST</a>(val, 0, 1)) {
+<a name="l04169"></a>04169                 DWC_WARN(<span class="stringliteral">"Wrong value for dma_enable\n"</span>);
+<a name="l04170"></a>04170                 DWC_WARN(<span class="stringliteral">"dma_desc_enable must be 0 or 1\n"</span>);
+<a name="l04171"></a>04171                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l04172"></a>04172         }
+<a name="l04173"></a>04173 
+<a name="l04174"></a>04174         <span class="keywordflow">if</span> ((val == 1)
+<a name="l04175"></a>04175             &amp;&amp; ((<a class="code" href="dwc__otg__cil_8c.html#0c78da7b7e7b59b31bd99a07d926a298">dwc_otg_get_param_dma_enable</a>(core_if) == 0)
+<a name="l04176"></a>04176                 || (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#9c1394f3c46adde2fa7be79bf0237f9b">hwcfg4</a>.<a class="code" href="unionhwcfg4__data.html#9fb9175668e2381c568c5adbf6e5225d">b</a>.<a class="code" href="unionhwcfg4__data.html#988888a48e9088d0e9f889818eb63509">desc_dma</a> == 0))) {
+<a name="l04177"></a>04177                 <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#d3dd61d5d48c2fc06bf4b2d37e848c93">dwc_otg_param_initialized</a>
+<a name="l04178"></a>04178                     (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#36c5bcf00d0f776b5c9e84e5d8ae408d">dma_desc_enable</a>)) {
+<a name="l04179"></a>04179                         DWC_ERROR
+<a name="l04180"></a>04180                             (<span class="stringliteral">"%d invalid for dma_desc_enable paremter. Check HW configuration.\n"</span>,
+<a name="l04181"></a>04181                              val);
+<a name="l04182"></a>04182                 }
+<a name="l04183"></a>04183                 val = 0;
+<a name="l04184"></a>04184                 retval = -DWC_E_INVALID;
+<a name="l04185"></a>04185         }
+<a name="l04186"></a>04186         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#36c5bcf00d0f776b5c9e84e5d8ae408d">dma_desc_enable</a> = val;
+<a name="l04187"></a>04187         <span class="keywordflow">return</span> retval;
+<a name="l04188"></a>04188 }
+<a name="l04189"></a>04189 
+<a name="l04190"></a><a class="code" href="dwc__otg__core__if_8h.html#5cac7b3770cefa9db25bb46193134c5a">04190</a> int32_t <a class="code" href="dwc__otg__cil_8c.html#5cac7b3770cefa9db25bb46193134c5a">dwc_otg_get_param_dma_desc_enable</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l04191"></a>04191 {
+<a name="l04192"></a>04192         <span class="keywordflow">return</span> core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#36c5bcf00d0f776b5c9e84e5d8ae408d">dma_desc_enable</a>;
+<a name="l04193"></a>04193 }
+<a name="l04194"></a>04194 
+<a name="l04195"></a><a class="code" href="dwc__otg__core__if_8h.html#8bd669637630521655c455c03d470e10">04195</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#8bd669637630521655c455c03d470e10">dwc_otg_set_param_host_support_fs_ls_low_power</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if,
+<a name="l04196"></a>04196                                                    int32_t val)
+<a name="l04197"></a>04197 {
+<a name="l04198"></a>04198         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#c4138a87302505f6ef79dc3bfb4951c0">DWC_OTG_PARAM_TEST</a>(val, 0, 1)) {
+<a name="l04199"></a>04199                 DWC_WARN(<span class="stringliteral">"Wrong value for host_support_fs_low_power\n"</span>);
+<a name="l04200"></a>04200                 DWC_WARN(<span class="stringliteral">"host_support_fs_low_power must be 0 or 1\n"</span>);
+<a name="l04201"></a>04201                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l04202"></a>04202         }
+<a name="l04203"></a>04203         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#85cad588a450b8497347af9cf166bfde">host_support_fs_ls_low_power</a> = val;
+<a name="l04204"></a>04204         <span class="keywordflow">return</span> 0;
+<a name="l04205"></a>04205 }
+<a name="l04206"></a>04206 
+<a name="l04207"></a><a class="code" href="dwc__otg__core__if_8h.html#ce7a69af8ef1970a640d0a23c7c8f12a">04207</a> int32_t <a class="code" href="dwc__otg__cil_8c.html#ce7a69af8ef1970a640d0a23c7c8f12a">dwc_otg_get_param_host_support_fs_ls_low_power</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *
+<a name="l04208"></a>04208                                                        core_if)
+<a name="l04209"></a>04209 {
+<a name="l04210"></a>04210         <span class="keywordflow">return</span> core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#85cad588a450b8497347af9cf166bfde">host_support_fs_ls_low_power</a>;
+<a name="l04211"></a>04211 }
+<a name="l04212"></a>04212 
+<a name="l04213"></a><a class="code" href="dwc__otg__core__if_8h.html#61bb728cc80220e5173d5e3126dd4fd1">04213</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#61bb728cc80220e5173d5e3126dd4fd1">dwc_otg_set_param_enable_dynamic_fifo</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if,
+<a name="l04214"></a>04214                                           int32_t val)
+<a name="l04215"></a>04215 {
+<a name="l04216"></a>04216         <span class="keywordtype">int</span> retval = 0;
+<a name="l04217"></a>04217         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#c4138a87302505f6ef79dc3bfb4951c0">DWC_OTG_PARAM_TEST</a>(val, 0, 1)) {
+<a name="l04218"></a>04218                 DWC_WARN(<span class="stringliteral">"Wrong value for enable_dynamic_fifo\n"</span>);
+<a name="l04219"></a>04219                 DWC_WARN(<span class="stringliteral">"enable_dynamic_fifo must be 0 or 1\n"</span>);
+<a name="l04220"></a>04220                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l04221"></a>04221         }
+<a name="l04222"></a>04222 
+<a name="l04223"></a>04223         <span class="keywordflow">if</span> ((val == 1) &amp;&amp; (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">hwcfg2</a>.<a class="code" href="unionhwcfg2__data.html#9dcc70e2dba617cbc6c12189be5c1d6a">b</a>.<a class="code" href="unionhwcfg2__data.html#b6bfbfe650352dec82a02d15677fe88d">dynamic_fifo</a> == 0)) {
+<a name="l04224"></a>04224                 <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#d3dd61d5d48c2fc06bf4b2d37e848c93">dwc_otg_param_initialized</a>
+<a name="l04225"></a>04225                     (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#8c169633d4a6f28e964cef9f597c6e03">enable_dynamic_fifo</a>)) {
+<a name="l04226"></a>04226                         DWC_ERROR
+<a name="l04227"></a>04227                             (<span class="stringliteral">"%d invalid for enable_dynamic_fifo paremter. Check HW configuration.\n"</span>,
+<a name="l04228"></a>04228                              val);
+<a name="l04229"></a>04229                 }
+<a name="l04230"></a>04230                 val = 0;
+<a name="l04231"></a>04231                 retval = -DWC_E_INVALID;
+<a name="l04232"></a>04232         }
+<a name="l04233"></a>04233         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#8c169633d4a6f28e964cef9f597c6e03">enable_dynamic_fifo</a> = val;
+<a name="l04234"></a>04234         <span class="keywordflow">return</span> retval;
+<a name="l04235"></a>04235 }
+<a name="l04236"></a>04236 
+<a name="l04237"></a><a class="code" href="dwc__otg__core__if_8h.html#3bc5fc1c94b4bb1a5b5dcca6fa71584e">04237</a> int32_t <a class="code" href="dwc__otg__cil_8c.html#3bc5fc1c94b4bb1a5b5dcca6fa71584e">dwc_otg_get_param_enable_dynamic_fifo</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l04238"></a>04238 {
+<a name="l04239"></a>04239         <span class="keywordflow">return</span> core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#8c169633d4a6f28e964cef9f597c6e03">enable_dynamic_fifo</a>;
+<a name="l04240"></a>04240 }
+<a name="l04241"></a>04241 
+<a name="l04242"></a><a class="code" href="dwc__otg__core__if_8h.html#69d52c46eb236816b20675ecb57975ae">04242</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#69d52c46eb236816b20675ecb57975ae">dwc_otg_set_param_data_fifo_size</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, int32_t val)
+<a name="l04243"></a>04243 {
+<a name="l04244"></a>04244         <span class="keywordtype">int</span> retval = 0;
+<a name="l04245"></a>04245         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#c4138a87302505f6ef79dc3bfb4951c0">DWC_OTG_PARAM_TEST</a>(val, 32, 32768)) {
+<a name="l04246"></a>04246                 DWC_WARN(<span class="stringliteral">"Wrong value for data_fifo_size\n"</span>);
+<a name="l04247"></a>04247                 DWC_WARN(<span class="stringliteral">"data_fifo_size must be 32-32768\n"</span>);
+<a name="l04248"></a>04248                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l04249"></a>04249         }
+<a name="l04250"></a>04250 
+<a name="l04251"></a>04251         <span class="keywordflow">if</span> (val &gt; core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#91d0e0a5e8e048024c8846d12e00cecc">hwcfg3</a>.<a class="code" href="unionhwcfg3__data.html#928c5de42f8af177ce34712123b5093c">b</a>.<a class="code" href="unionhwcfg3__data.html#f885715ddb953dbe95acc08e49264706">dfifo_depth</a>) {
+<a name="l04252"></a>04252                 <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#d3dd61d5d48c2fc06bf4b2d37e848c93">dwc_otg_param_initialized</a>
+<a name="l04253"></a>04253                     (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#3d8dc206f54165f52c7f8599731d0f95">data_fifo_size</a>)) {
+<a name="l04254"></a>04254                         DWC_ERROR
+<a name="l04255"></a>04255                             (<span class="stringliteral">"%d invalid for data_fifo_size parameter. Check HW configuration.\n"</span>,
+<a name="l04256"></a>04256                              val);
+<a name="l04257"></a>04257                 }
+<a name="l04258"></a>04258                 val = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#91d0e0a5e8e048024c8846d12e00cecc">hwcfg3</a>.<a class="code" href="unionhwcfg3__data.html#928c5de42f8af177ce34712123b5093c">b</a>.<a class="code" href="unionhwcfg3__data.html#f885715ddb953dbe95acc08e49264706">dfifo_depth</a>;
+<a name="l04259"></a>04259                 retval = -DWC_E_INVALID;
+<a name="l04260"></a>04260         }
+<a name="l04261"></a>04261 
+<a name="l04262"></a>04262         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#3d8dc206f54165f52c7f8599731d0f95">data_fifo_size</a> = val;
+<a name="l04263"></a>04263         <span class="keywordflow">return</span> retval;
+<a name="l04264"></a>04264 }
+<a name="l04265"></a>04265 
+<a name="l04266"></a><a class="code" href="dwc__otg__core__if_8h.html#3695ec355114fb8da2f57b7f5c2159b7">04266</a> int32_t <a class="code" href="dwc__otg__cil_8c.html#3695ec355114fb8da2f57b7f5c2159b7">dwc_otg_get_param_data_fifo_size</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l04267"></a>04267 {
+<a name="l04268"></a>04268         <span class="keywordflow">return</span> core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#3d8dc206f54165f52c7f8599731d0f95">data_fifo_size</a>;
+<a name="l04269"></a>04269 }
+<a name="l04270"></a>04270 
+<a name="l04271"></a><a class="code" href="dwc__otg__core__if_8h.html#0fa4db196053869ac19832c03c62913f">04271</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#0fa4db196053869ac19832c03c62913f">dwc_otg_set_param_dev_rx_fifo_size</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, int32_t val)
+<a name="l04272"></a>04272 {
+<a name="l04273"></a>04273         <span class="keywordtype">int</span> retval = 0;
+<a name="l04274"></a>04274         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#c4138a87302505f6ef79dc3bfb4951c0">DWC_OTG_PARAM_TEST</a>(val, 16, 32768)) {
+<a name="l04275"></a>04275                 DWC_WARN(<span class="stringliteral">"Wrong value for dev_rx_fifo_size\n"</span>);
+<a name="l04276"></a>04276                 DWC_WARN(<span class="stringliteral">"dev_rx_fifo_size must be 16-32768\n"</span>);
+<a name="l04277"></a>04277                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l04278"></a>04278         }
+<a name="l04279"></a>04279 
+<a name="l04280"></a>04280         <span class="keywordflow">if</span> (val &gt; dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#b1a8cc07a9541c9a73e864579602b79b">grxfsiz</a>)) {
+<a name="l04281"></a>04281                 <span class="keywordflow">if</span>(<a class="code" href="dwc__otg__cil_8c.html#d3dd61d5d48c2fc06bf4b2d37e848c93">dwc_otg_param_initialized</a>(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#24ea6f9329f64ac0ad2d31dafe0d1d8c">dev_rx_fifo_size</a>)) {
+<a name="l04282"></a>04282                 DWC_WARN(<span class="stringliteral">"%d invalid for dev_rx_fifo_size parameter\n"</span>, val);
+<a name="l04283"></a>04283                 }
+<a name="l04284"></a>04284                 val = dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#b1a8cc07a9541c9a73e864579602b79b">grxfsiz</a>);
+<a name="l04285"></a>04285                 retval = -DWC_E_INVALID;
+<a name="l04286"></a>04286         }
+<a name="l04287"></a>04287 
+<a name="l04288"></a>04288         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#24ea6f9329f64ac0ad2d31dafe0d1d8c">dev_rx_fifo_size</a> = val;
+<a name="l04289"></a>04289         <span class="keywordflow">return</span> retval;
+<a name="l04290"></a>04290 }
+<a name="l04291"></a>04291 
+<a name="l04292"></a><a class="code" href="dwc__otg__core__if_8h.html#56781e1cc653e948147afab10c19b72a">04292</a> int32_t <a class="code" href="dwc__otg__cil_8c.html#56781e1cc653e948147afab10c19b72a">dwc_otg_get_param_dev_rx_fifo_size</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l04293"></a>04293 {
+<a name="l04294"></a>04294         <span class="keywordflow">return</span> core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#24ea6f9329f64ac0ad2d31dafe0d1d8c">dev_rx_fifo_size</a>;
+<a name="l04295"></a>04295 }
+<a name="l04296"></a>04296 
+<a name="l04297"></a><a class="code" href="dwc__otg__core__if_8h.html#4f7059cecabbf8cfe5014112ba9a3d42">04297</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#4f7059cecabbf8cfe5014112ba9a3d42">dwc_otg_set_param_dev_nperio_tx_fifo_size</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if,
+<a name="l04298"></a>04298                                               int32_t val)
+<a name="l04299"></a>04299 {
+<a name="l04300"></a>04300         <span class="keywordtype">int</span> retval = 0;
+<a name="l04301"></a>04301 
+<a name="l04302"></a>04302         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#c4138a87302505f6ef79dc3bfb4951c0">DWC_OTG_PARAM_TEST</a>(val, 16, 32768)) {
+<a name="l04303"></a>04303                 DWC_WARN(<span class="stringliteral">"Wrong value for dev_nperio_tx_fifo\n"</span>);
+<a name="l04304"></a>04304                 DWC_WARN(<span class="stringliteral">"dev_nperio_tx_fifo must be 16-32768\n"</span>);
+<a name="l04305"></a>04305                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l04306"></a>04306         }
+<a name="l04307"></a>04307 
+<a name="l04308"></a>04308         <span class="keywordflow">if</span> (val &gt; (dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#20fb70fe34a1a65d085b1d4e5f8d9106">gnptxfsiz</a>) &gt;&gt; 16)) {
+<a name="l04309"></a>04309                 <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#d3dd61d5d48c2fc06bf4b2d37e848c93">dwc_otg_param_initialized</a>
+<a name="l04310"></a>04310                     (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#d08d9aee1fb4e6508089415d6150176e">dev_nperio_tx_fifo_size</a>)) {
+<a name="l04311"></a>04311                         DWC_ERROR
+<a name="l04312"></a>04312                             (<span class="stringliteral">"%d invalid for dev_nperio_tx_fifo_size. Check HW configuration.\n"</span>,
+<a name="l04313"></a>04313                              val);
+<a name="l04314"></a>04314                 }
+<a name="l04315"></a>04315                 val =
+<a name="l04316"></a>04316                     (dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#20fb70fe34a1a65d085b1d4e5f8d9106">gnptxfsiz</a>) &gt;&gt;
+<a name="l04317"></a>04317                      16);
+<a name="l04318"></a>04318                 retval = -DWC_E_INVALID;
+<a name="l04319"></a>04319         }
+<a name="l04320"></a>04320 
+<a name="l04321"></a>04321         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#d08d9aee1fb4e6508089415d6150176e">dev_nperio_tx_fifo_size</a> = val;
+<a name="l04322"></a>04322         <span class="keywordflow">return</span> retval;
+<a name="l04323"></a>04323 }
+<a name="l04324"></a>04324 
+<a name="l04325"></a><a class="code" href="dwc__otg__core__if_8h.html#bb61fc259fe1dc0aee41a3c8b4e99b88">04325</a> int32_t <a class="code" href="dwc__otg__cil_8c.html#bb61fc259fe1dc0aee41a3c8b4e99b88">dwc_otg_get_param_dev_nperio_tx_fifo_size</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l04326"></a>04326 {
+<a name="l04327"></a>04327         <span class="keywordflow">return</span> core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#d08d9aee1fb4e6508089415d6150176e">dev_nperio_tx_fifo_size</a>;
+<a name="l04328"></a>04328 }
+<a name="l04329"></a>04329 
+<a name="l04330"></a><a class="code" href="dwc__otg__core__if_8h.html#254c1e97cf22fe34b7383165e30071eb">04330</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#254c1e97cf22fe34b7383165e30071eb">dwc_otg_set_param_host_rx_fifo_size</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if,
+<a name="l04331"></a>04331                                         int32_t val)
+<a name="l04332"></a>04332 {
+<a name="l04333"></a>04333         <span class="keywordtype">int</span> retval = 0;
+<a name="l04334"></a>04334 
+<a name="l04335"></a>04335         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#c4138a87302505f6ef79dc3bfb4951c0">DWC_OTG_PARAM_TEST</a>(val, 16, 32768)) {
+<a name="l04336"></a>04336                 DWC_WARN(<span class="stringliteral">"Wrong value for host_rx_fifo_size\n"</span>);
+<a name="l04337"></a>04337                 DWC_WARN(<span class="stringliteral">"host_rx_fifo_size must be 16-32768\n"</span>);
+<a name="l04338"></a>04338                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l04339"></a>04339         }
+<a name="l04340"></a>04340 
+<a name="l04341"></a>04341         <span class="keywordflow">if</span> (val &gt; dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#b1a8cc07a9541c9a73e864579602b79b">grxfsiz</a>)) {
+<a name="l04342"></a>04342                 <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#d3dd61d5d48c2fc06bf4b2d37e848c93">dwc_otg_param_initialized</a>
+<a name="l04343"></a>04343                     (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#2b2ab9c2fe16db70b136515b2e981f6b">host_rx_fifo_size</a>)) {
+<a name="l04344"></a>04344                         DWC_ERROR
+<a name="l04345"></a>04345                             (<span class="stringliteral">"%d invalid for host_rx_fifo_size. Check HW configuration.\n"</span>,
+<a name="l04346"></a>04346                              val);
+<a name="l04347"></a>04347                 }
+<a name="l04348"></a>04348                 val = dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#b1a8cc07a9541c9a73e864579602b79b">grxfsiz</a>);
+<a name="l04349"></a>04349                 retval = -DWC_E_INVALID;
+<a name="l04350"></a>04350         }
+<a name="l04351"></a>04351 
+<a name="l04352"></a>04352         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#2b2ab9c2fe16db70b136515b2e981f6b">host_rx_fifo_size</a> = val;
+<a name="l04353"></a>04353         <span class="keywordflow">return</span> retval;
+<a name="l04354"></a>04354 
+<a name="l04355"></a>04355 }
+<a name="l04356"></a>04356 
+<a name="l04357"></a><a class="code" href="dwc__otg__core__if_8h.html#7b964a905858d04ce43159bbfca20f34">04357</a> int32_t <a class="code" href="dwc__otg__cil_8c.html#7b964a905858d04ce43159bbfca20f34">dwc_otg_get_param_host_rx_fifo_size</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l04358"></a>04358 {
+<a name="l04359"></a>04359         <span class="keywordflow">return</span> core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#2b2ab9c2fe16db70b136515b2e981f6b">host_rx_fifo_size</a>;
+<a name="l04360"></a>04360 }
+<a name="l04361"></a>04361 
+<a name="l04362"></a><a class="code" href="dwc__otg__core__if_8h.html#a66ca9f9345a13606148b050f8690a56">04362</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#a66ca9f9345a13606148b050f8690a56">dwc_otg_set_param_host_nperio_tx_fifo_size</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if,
+<a name="l04363"></a>04363                                                int32_t val)
+<a name="l04364"></a>04364 {
+<a name="l04365"></a>04365         <span class="keywordtype">int</span> retval = 0;
+<a name="l04366"></a>04366 
+<a name="l04367"></a>04367         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#c4138a87302505f6ef79dc3bfb4951c0">DWC_OTG_PARAM_TEST</a>(val, 16, 32768)) {
+<a name="l04368"></a>04368                 DWC_WARN(<span class="stringliteral">"Wrong value for host_nperio_tx_fifo_size\n"</span>);
+<a name="l04369"></a>04369                 DWC_WARN(<span class="stringliteral">"host_nperio_tx_fifo_size must be 16-32768\n"</span>);
+<a name="l04370"></a>04370                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l04371"></a>04371         }
+<a name="l04372"></a>04372 
+<a name="l04373"></a>04373         <span class="keywordflow">if</span> (val &gt; (dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#20fb70fe34a1a65d085b1d4e5f8d9106">gnptxfsiz</a>) &gt;&gt; 16)) {
+<a name="l04374"></a>04374                 <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#d3dd61d5d48c2fc06bf4b2d37e848c93">dwc_otg_param_initialized</a>
+<a name="l04375"></a>04375                     (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#6ff00857d99f72c0cfd6198cbcfab9a7">host_nperio_tx_fifo_size</a>)) {
+<a name="l04376"></a>04376                         DWC_ERROR
+<a name="l04377"></a>04377                             (<span class="stringliteral">"%d invalid for host_nperio_tx_fifo_size. Check HW configuration.\n"</span>,
+<a name="l04378"></a>04378                              val);
+<a name="l04379"></a>04379                 }
+<a name="l04380"></a>04380                 val =
+<a name="l04381"></a>04381                     (dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#20fb70fe34a1a65d085b1d4e5f8d9106">gnptxfsiz</a>) &gt;&gt;
+<a name="l04382"></a>04382                      16);
+<a name="l04383"></a>04383                 retval = -DWC_E_INVALID;
+<a name="l04384"></a>04384         }
+<a name="l04385"></a>04385 
+<a name="l04386"></a>04386         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#6ff00857d99f72c0cfd6198cbcfab9a7">host_nperio_tx_fifo_size</a> = val;
+<a name="l04387"></a>04387         <span class="keywordflow">return</span> retval;
+<a name="l04388"></a>04388 }
+<a name="l04389"></a>04389 
+<a name="l04390"></a><a class="code" href="dwc__otg__core__if_8h.html#e53a7fddb0a2689e463cbd9c441ee004">04390</a> int32_t <a class="code" href="dwc__otg__cil_8c.html#e53a7fddb0a2689e463cbd9c441ee004">dwc_otg_get_param_host_nperio_tx_fifo_size</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l04391"></a>04391 {
+<a name="l04392"></a>04392         <span class="keywordflow">return</span> core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#6ff00857d99f72c0cfd6198cbcfab9a7">host_nperio_tx_fifo_size</a>;
+<a name="l04393"></a>04393 }
+<a name="l04394"></a>04394 
+<a name="l04395"></a><a class="code" href="dwc__otg__core__if_8h.html#e4ce399208d8a85dcb9dedd1fb8cd8ce">04395</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#e4ce399208d8a85dcb9dedd1fb8cd8ce">dwc_otg_set_param_host_perio_tx_fifo_size</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if,
+<a name="l04396"></a>04396                                               int32_t val)
+<a name="l04397"></a>04397 {
+<a name="l04398"></a>04398         <span class="keywordtype">int</span> retval = 0;
+<a name="l04399"></a>04399         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#c4138a87302505f6ef79dc3bfb4951c0">DWC_OTG_PARAM_TEST</a>(val, 16, 32768)) {
+<a name="l04400"></a>04400                 DWC_WARN(<span class="stringliteral">"Wrong value for host_perio_tx_fifo_size\n"</span>);
+<a name="l04401"></a>04401                 DWC_WARN(<span class="stringliteral">"host_perio_tx_fifo_size must be 16-32768\n"</span>);
+<a name="l04402"></a>04402                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l04403"></a>04403         }
+<a name="l04404"></a>04404 
+<a name="l04405"></a>04405         <span class="keywordflow">if</span> (val &gt;
+<a name="l04406"></a>04406             ((dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#94ae41f04d5a4244a8ebc23e51187e96">hptxfsiz</a>) &gt;&gt; 16))) {
+<a name="l04407"></a>04407                 <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#d3dd61d5d48c2fc06bf4b2d37e848c93">dwc_otg_param_initialized</a>
+<a name="l04408"></a>04408                     (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#5bc3cac5c81fd8d6fd291ca4b7de3e28">host_perio_tx_fifo_size</a>)) {
+<a name="l04409"></a>04409                         DWC_ERROR
+<a name="l04410"></a>04410                             (<span class="stringliteral">"%d invalid for host_perio_tx_fifo_size. Check HW configuration.\n"</span>,
+<a name="l04411"></a>04411                              val);
+<a name="l04412"></a>04412                 }
+<a name="l04413"></a>04413                 val =
+<a name="l04414"></a>04414                     (dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#94ae41f04d5a4244a8ebc23e51187e96">hptxfsiz</a>) &gt;&gt;
+<a name="l04415"></a>04415                      16);
+<a name="l04416"></a>04416                 retval = -DWC_E_INVALID;
+<a name="l04417"></a>04417         }
+<a name="l04418"></a>04418 
+<a name="l04419"></a>04419         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#5bc3cac5c81fd8d6fd291ca4b7de3e28">host_perio_tx_fifo_size</a> = val;
+<a name="l04420"></a>04420         <span class="keywordflow">return</span> retval;
+<a name="l04421"></a>04421 }
+<a name="l04422"></a>04422 
+<a name="l04423"></a><a class="code" href="dwc__otg__core__if_8h.html#9b2de0caea0d9ee86258ac4bbe63acd5">04423</a> int32_t <a class="code" href="dwc__otg__cil_8c.html#9b2de0caea0d9ee86258ac4bbe63acd5">dwc_otg_get_param_host_perio_tx_fifo_size</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l04424"></a>04424 {
+<a name="l04425"></a>04425         <span class="keywordflow">return</span> core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#5bc3cac5c81fd8d6fd291ca4b7de3e28">host_perio_tx_fifo_size</a>;
+<a name="l04426"></a>04426 }
+<a name="l04427"></a>04427 
+<a name="l04428"></a><a class="code" href="dwc__otg__core__if_8h.html#2eee676071d6bb4eba53b413e80b045f">04428</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#2eee676071d6bb4eba53b413e80b045f">dwc_otg_set_param_max_transfer_size</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if,
+<a name="l04429"></a>04429                                         int32_t val)
+<a name="l04430"></a>04430 {
+<a name="l04431"></a>04431         <span class="keywordtype">int</span> retval = 0;
+<a name="l04432"></a>04432 
+<a name="l04433"></a>04433         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#c4138a87302505f6ef79dc3bfb4951c0">DWC_OTG_PARAM_TEST</a>(val, 2047, 524288)) {
+<a name="l04434"></a>04434                 DWC_WARN(<span class="stringliteral">"Wrong value for max_transfer_size\n"</span>);
+<a name="l04435"></a>04435                 DWC_WARN(<span class="stringliteral">"max_transfer_size must be 2047-524288\n"</span>);
+<a name="l04436"></a>04436                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l04437"></a>04437         }
+<a name="l04438"></a>04438 
+<a name="l04439"></a>04439         <span class="keywordflow">if</span> (val &gt;= (1 &lt;&lt; (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#91d0e0a5e8e048024c8846d12e00cecc">hwcfg3</a>.<a class="code" href="unionhwcfg3__data.html#928c5de42f8af177ce34712123b5093c">b</a>.<a class="code" href="unionhwcfg3__data.html#66f311995decf2f11d620aa6a56fa26e">xfer_size_cntr_width</a> + 11))) {
+<a name="l04440"></a>04440                 <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#d3dd61d5d48c2fc06bf4b2d37e848c93">dwc_otg_param_initialized</a>
+<a name="l04441"></a>04441                     (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#e614d1d2ee740cd972ca76ed0dffec74">max_transfer_size</a>)) {
+<a name="l04442"></a>04442                         DWC_ERROR
+<a name="l04443"></a>04443                             (<span class="stringliteral">"%d invalid for max_transfer_size. Check HW configuration.\n"</span>,
+<a name="l04444"></a>04444                              val);
+<a name="l04445"></a>04445                 }
+<a name="l04446"></a>04446                 val =
+<a name="l04447"></a>04447                     ((1 &lt;&lt; (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#91d0e0a5e8e048024c8846d12e00cecc">hwcfg3</a>.<a class="code" href="unionhwcfg3__data.html#928c5de42f8af177ce34712123b5093c">b</a>.<a class="code" href="unionhwcfg3__data.html#a397ea503f5155d8e3a66cc82d7937f2">packet_size_cntr_width</a> + 11)) -
+<a name="l04448"></a>04448                      1);
+<a name="l04449"></a>04449                 retval = -DWC_E_INVALID;
+<a name="l04450"></a>04450         }
+<a name="l04451"></a>04451 
+<a name="l04452"></a>04452         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#e614d1d2ee740cd972ca76ed0dffec74">max_transfer_size</a> = val;
+<a name="l04453"></a>04453         <span class="keywordflow">return</span> retval;
+<a name="l04454"></a>04454 }
+<a name="l04455"></a>04455 
+<a name="l04456"></a><a class="code" href="dwc__otg__core__if_8h.html#307c59e350a8ea67ef5d1c02f79de17b">04456</a> int32_t <a class="code" href="dwc__otg__cil_8c.html#307c59e350a8ea67ef5d1c02f79de17b">dwc_otg_get_param_max_transfer_size</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l04457"></a>04457 {
+<a name="l04458"></a>04458         <span class="keywordflow">return</span> core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#e614d1d2ee740cd972ca76ed0dffec74">max_transfer_size</a>;
+<a name="l04459"></a>04459 }
+<a name="l04460"></a>04460 
+<a name="l04461"></a><a class="code" href="dwc__otg__core__if_8h.html#a1c52f0740f7d0b72c980b38cc4314d1">04461</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#a1c52f0740f7d0b72c980b38cc4314d1">dwc_otg_set_param_max_packet_count</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, int32_t val)
+<a name="l04462"></a>04462 {
+<a name="l04463"></a>04463         <span class="keywordtype">int</span> retval = 0;
+<a name="l04464"></a>04464 
+<a name="l04465"></a>04465         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#c4138a87302505f6ef79dc3bfb4951c0">DWC_OTG_PARAM_TEST</a>(val, 15, 511)) {
+<a name="l04466"></a>04466                 DWC_WARN(<span class="stringliteral">"Wrong value for max_packet_count\n"</span>);
+<a name="l04467"></a>04467                 DWC_WARN(<span class="stringliteral">"max_packet_count must be 15-511\n"</span>);
+<a name="l04468"></a>04468                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l04469"></a>04469         }
+<a name="l04470"></a>04470 
+<a name="l04471"></a>04471         <span class="keywordflow">if</span> (val &gt; (1 &lt;&lt; (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#91d0e0a5e8e048024c8846d12e00cecc">hwcfg3</a>.<a class="code" href="unionhwcfg3__data.html#928c5de42f8af177ce34712123b5093c">b</a>.<a class="code" href="unionhwcfg3__data.html#a397ea503f5155d8e3a66cc82d7937f2">packet_size_cntr_width</a> + 4))) {
+<a name="l04472"></a>04472                 <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#d3dd61d5d48c2fc06bf4b2d37e848c93">dwc_otg_param_initialized</a>
+<a name="l04473"></a>04473                     (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#e17230afa013a15beda38565d19fa933">max_packet_count</a>)) {
+<a name="l04474"></a>04474                         DWC_ERROR
+<a name="l04475"></a>04475                             (<span class="stringliteral">"%d invalid for max_packet_count. Check HW configuration.\n"</span>,
+<a name="l04476"></a>04476                              val);
+<a name="l04477"></a>04477                 }
+<a name="l04478"></a>04478                 val =
+<a name="l04479"></a>04479                     ((1 &lt;&lt; (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#91d0e0a5e8e048024c8846d12e00cecc">hwcfg3</a>.<a class="code" href="unionhwcfg3__data.html#928c5de42f8af177ce34712123b5093c">b</a>.<a class="code" href="unionhwcfg3__data.html#a397ea503f5155d8e3a66cc82d7937f2">packet_size_cntr_width</a> + 4)) - 1);
+<a name="l04480"></a>04480                 retval = -DWC_E_INVALID;
+<a name="l04481"></a>04481         }
+<a name="l04482"></a>04482 
+<a name="l04483"></a>04483         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#e17230afa013a15beda38565d19fa933">max_packet_count</a> = val;
+<a name="l04484"></a>04484         <span class="keywordflow">return</span> retval;
+<a name="l04485"></a>04485 }
+<a name="l04486"></a>04486 
+<a name="l04487"></a><a class="code" href="dwc__otg__core__if_8h.html#765e82d04dc91bdc93c129d9ba7c5161">04487</a> int32_t <a class="code" href="dwc__otg__cil_8c.html#765e82d04dc91bdc93c129d9ba7c5161">dwc_otg_get_param_max_packet_count</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l04488"></a>04488 {
+<a name="l04489"></a>04489         <span class="keywordflow">return</span> core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#e17230afa013a15beda38565d19fa933">max_packet_count</a>;
+<a name="l04490"></a>04490 }
+<a name="l04491"></a>04491 
+<a name="l04492"></a><a class="code" href="dwc__otg__core__if_8h.html#f802acfc49b3fbb86159036f8f317f76">04492</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#f802acfc49b3fbb86159036f8f317f76">dwc_otg_set_param_host_channels</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, int32_t val)
+<a name="l04493"></a>04493 {
+<a name="l04494"></a>04494         <span class="keywordtype">int</span> retval = 0;
+<a name="l04495"></a>04495 
+<a name="l04496"></a>04496         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#c4138a87302505f6ef79dc3bfb4951c0">DWC_OTG_PARAM_TEST</a>(val, 1, 16)) {
+<a name="l04497"></a>04497                 DWC_WARN(<span class="stringliteral">"Wrong value for host_channels\n"</span>);
+<a name="l04498"></a>04498                 DWC_WARN(<span class="stringliteral">"host_channels must be 1-16\n"</span>);
+<a name="l04499"></a>04499                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l04500"></a>04500         }
+<a name="l04501"></a>04501 
+<a name="l04502"></a>04502         <span class="keywordflow">if</span> (val &gt; (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">hwcfg2</a>.<a class="code" href="unionhwcfg2__data.html#9dcc70e2dba617cbc6c12189be5c1d6a">b</a>.<a class="code" href="unionhwcfg2__data.html#83708a4d45e8d019892367c5ae9f6fd0">num_host_chan</a> + 1)) {
+<a name="l04503"></a>04503                 <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#d3dd61d5d48c2fc06bf4b2d37e848c93">dwc_otg_param_initialized</a>
+<a name="l04504"></a>04504                     (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#c1b433c6965aa7d48f6ca6818c592039">host_channels</a>)) {
+<a name="l04505"></a>04505                         DWC_ERROR
+<a name="l04506"></a>04506                             (<span class="stringliteral">"%d invalid for host_channels. Check HW configurations.\n"</span>,
+<a name="l04507"></a>04507                              val);
+<a name="l04508"></a>04508                 }
+<a name="l04509"></a>04509                 val = (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">hwcfg2</a>.<a class="code" href="unionhwcfg2__data.html#9dcc70e2dba617cbc6c12189be5c1d6a">b</a>.<a class="code" href="unionhwcfg2__data.html#83708a4d45e8d019892367c5ae9f6fd0">num_host_chan</a> + 1);
+<a name="l04510"></a>04510                 retval = -DWC_E_INVALID;
+<a name="l04511"></a>04511         }
+<a name="l04512"></a>04512 
+<a name="l04513"></a>04513         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#c1b433c6965aa7d48f6ca6818c592039">host_channels</a> = val;
+<a name="l04514"></a>04514         <span class="keywordflow">return</span> retval;
+<a name="l04515"></a>04515 }
+<a name="l04516"></a>04516 
+<a name="l04517"></a><a class="code" href="dwc__otg__core__if_8h.html#e1235c11a6a3e8d0e78df59d86d4d287">04517</a> int32_t <a class="code" href="dwc__otg__cil_8c.html#e1235c11a6a3e8d0e78df59d86d4d287">dwc_otg_get_param_host_channels</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l04518"></a>04518 {
+<a name="l04519"></a>04519         <span class="keywordflow">return</span> core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#c1b433c6965aa7d48f6ca6818c592039">host_channels</a>;
+<a name="l04520"></a>04520 }
+<a name="l04521"></a>04521 
+<a name="l04522"></a><a class="code" href="dwc__otg__core__if_8h.html#75d3b409824c0ca52631277398ba8367">04522</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#75d3b409824c0ca52631277398ba8367">dwc_otg_set_param_dev_endpoints</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, int32_t val)
+<a name="l04523"></a>04523 {
+<a name="l04524"></a>04524         <span class="keywordtype">int</span> retval = 0;
+<a name="l04525"></a>04525 
+<a name="l04526"></a>04526         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#c4138a87302505f6ef79dc3bfb4951c0">DWC_OTG_PARAM_TEST</a>(val, 1, 15)) {
+<a name="l04527"></a>04527                 DWC_WARN(<span class="stringliteral">"Wrong value for dev_endpoints\n"</span>);
+<a name="l04528"></a>04528                 DWC_WARN(<span class="stringliteral">"dev_endpoints must be 1-15\n"</span>);
+<a name="l04529"></a>04529                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l04530"></a>04530         }
+<a name="l04531"></a>04531 
+<a name="l04532"></a>04532         <span class="keywordflow">if</span> (val &gt; (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">hwcfg2</a>.<a class="code" href="unionhwcfg2__data.html#9dcc70e2dba617cbc6c12189be5c1d6a">b</a>.<a class="code" href="unionhwcfg2__data.html#9f827f334b58643849598ce1fa314c5a">num_dev_ep</a>)) {
+<a name="l04533"></a>04533                 <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#d3dd61d5d48c2fc06bf4b2d37e848c93">dwc_otg_param_initialized</a>
+<a name="l04534"></a>04534                     (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#17d0dda7fe2cd51726cd1dd34c57b94a">dev_endpoints</a>)) {
+<a name="l04535"></a>04535                         DWC_ERROR
+<a name="l04536"></a>04536                             (<span class="stringliteral">"%d invalid for dev_endpoints. Check HW configurations.\n"</span>,
+<a name="l04537"></a>04537                              val);
+<a name="l04538"></a>04538                 }
+<a name="l04539"></a>04539                 val = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">hwcfg2</a>.<a class="code" href="unionhwcfg2__data.html#9dcc70e2dba617cbc6c12189be5c1d6a">b</a>.<a class="code" href="unionhwcfg2__data.html#9f827f334b58643849598ce1fa314c5a">num_dev_ep</a>;
+<a name="l04540"></a>04540                 retval = -DWC_E_INVALID;
+<a name="l04541"></a>04541         }
+<a name="l04542"></a>04542 
+<a name="l04543"></a>04543         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#17d0dda7fe2cd51726cd1dd34c57b94a">dev_endpoints</a> = val;
+<a name="l04544"></a>04544         <span class="keywordflow">return</span> retval;
+<a name="l04545"></a>04545 }
+<a name="l04546"></a>04546 
+<a name="l04547"></a><a class="code" href="dwc__otg__core__if_8h.html#27447ccef5d5a1c3e5c93ed3b352e152">04547</a> int32_t <a class="code" href="dwc__otg__cil_8c.html#27447ccef5d5a1c3e5c93ed3b352e152">dwc_otg_get_param_dev_endpoints</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l04548"></a>04548 {
+<a name="l04549"></a>04549         <span class="keywordflow">return</span> core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#17d0dda7fe2cd51726cd1dd34c57b94a">dev_endpoints</a>;
+<a name="l04550"></a>04550 }
+<a name="l04551"></a>04551 
+<a name="l04552"></a><a class="code" href="dwc__otg__core__if_8h.html#2b7087c85c0ea1520ec2e091b80bf36b">04552</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#2b7087c85c0ea1520ec2e091b80bf36b">dwc_otg_set_param_phy_type</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, int32_t val)
+<a name="l04553"></a>04553 {
+<a name="l04554"></a>04554         <span class="keywordtype">int</span> retval = 0;
+<a name="l04555"></a>04555         <span class="keywordtype">int</span> valid = 0;
+<a name="l04556"></a>04556 
+<a name="l04557"></a>04557         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#c4138a87302505f6ef79dc3bfb4951c0">DWC_OTG_PARAM_TEST</a>(val, 0, 2)) {
+<a name="l04558"></a>04558                 DWC_WARN(<span class="stringliteral">"Wrong value for phy_type\n"</span>);
+<a name="l04559"></a>04559                 DWC_WARN(<span class="stringliteral">"phy_type must be 0,1 or 2\n"</span>);
+<a name="l04560"></a>04560                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l04561"></a>04561         }
+<a name="l04562"></a>04562 <span class="preprocessor">#ifndef NO_FS_PHY_HW_CHECKS</span>
+<a name="l04563"></a>04563 <span class="preprocessor"></span>        <span class="keywordflow">if</span> ((val == <a class="code" href="dwc__otg__core__if_8h.html#825a1595a3b15dc34adb88984b8b027e">DWC_PHY_TYPE_PARAM_UTMI</a>) &amp;&amp;
+<a name="l04564"></a>04564             ((core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">hwcfg2</a>.<a class="code" href="unionhwcfg2__data.html#9dcc70e2dba617cbc6c12189be5c1d6a">b</a>.<a class="code" href="unionhwcfg2__data.html#a248a2502e3c440d7b6e4ad61d396f4e">hs_phy_type</a> == 1) ||
+<a name="l04565"></a>04565              (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">hwcfg2</a>.<a class="code" href="unionhwcfg2__data.html#9dcc70e2dba617cbc6c12189be5c1d6a">b</a>.<a class="code" href="unionhwcfg2__data.html#a248a2502e3c440d7b6e4ad61d396f4e">hs_phy_type</a> == 3))) {
+<a name="l04566"></a>04566                 valid = 1;
+<a name="l04567"></a>04567         } <span class="keywordflow">else</span> <span class="keywordflow">if</span> ((val == <a class="code" href="dwc__otg__core__if_8h.html#1951e77698d1cecdac00c786428146bf">DWC_PHY_TYPE_PARAM_ULPI</a>) &amp;&amp;
+<a name="l04568"></a>04568                    ((core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">hwcfg2</a>.<a class="code" href="unionhwcfg2__data.html#9dcc70e2dba617cbc6c12189be5c1d6a">b</a>.<a class="code" href="unionhwcfg2__data.html#a248a2502e3c440d7b6e4ad61d396f4e">hs_phy_type</a> == 2) ||
+<a name="l04569"></a>04569                     (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">hwcfg2</a>.<a class="code" href="unionhwcfg2__data.html#9dcc70e2dba617cbc6c12189be5c1d6a">b</a>.<a class="code" href="unionhwcfg2__data.html#a248a2502e3c440d7b6e4ad61d396f4e">hs_phy_type</a> == 3))) {
+<a name="l04570"></a>04570                 valid = 1;
+<a name="l04571"></a>04571         } <span class="keywordflow">else</span> <span class="keywordflow">if</span> ((val == <a class="code" href="dwc__otg__core__if_8h.html#f7395410ea596c4c660f61ff41cb38b8">DWC_PHY_TYPE_PARAM_FS</a>) &amp;&amp;
+<a name="l04572"></a>04572                    (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">hwcfg2</a>.<a class="code" href="unionhwcfg2__data.html#9dcc70e2dba617cbc6c12189be5c1d6a">b</a>.<a class="code" href="unionhwcfg2__data.html#e75417d7e2d1843abf6e48f67851326e">fs_phy_type</a> == 1)) {
+<a name="l04573"></a>04573                 valid = 1;
+<a name="l04574"></a>04574         }
+<a name="l04575"></a>04575         <span class="keywordflow">if</span> (!valid) {
+<a name="l04576"></a>04576                 <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#d3dd61d5d48c2fc06bf4b2d37e848c93">dwc_otg_param_initialized</a>(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#8b5d4e0c98c46d0d4e80b6faf66daf72">phy_type</a>)) {
+<a name="l04577"></a>04577                         DWC_ERROR
+<a name="l04578"></a>04578                             (<span class="stringliteral">"%d invalid for phy_type. Check HW configurations.\n"</span>,
+<a name="l04579"></a>04579                              val);
+<a name="l04580"></a>04580                 }
+<a name="l04581"></a>04581                 <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">hwcfg2</a>.<a class="code" href="unionhwcfg2__data.html#9dcc70e2dba617cbc6c12189be5c1d6a">b</a>.<a class="code" href="unionhwcfg2__data.html#a248a2502e3c440d7b6e4ad61d396f4e">hs_phy_type</a>) {
+<a name="l04582"></a>04582                         <span class="keywordflow">if</span> ((core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">hwcfg2</a>.<a class="code" href="unionhwcfg2__data.html#9dcc70e2dba617cbc6c12189be5c1d6a">b</a>.<a class="code" href="unionhwcfg2__data.html#a248a2502e3c440d7b6e4ad61d396f4e">hs_phy_type</a> == 3) ||
+<a name="l04583"></a>04583                             (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">hwcfg2</a>.<a class="code" href="unionhwcfg2__data.html#9dcc70e2dba617cbc6c12189be5c1d6a">b</a>.<a class="code" href="unionhwcfg2__data.html#a248a2502e3c440d7b6e4ad61d396f4e">hs_phy_type</a> == 1)) {
+<a name="l04584"></a>04584                                 val = <a class="code" href="dwc__otg__core__if_8h.html#825a1595a3b15dc34adb88984b8b027e">DWC_PHY_TYPE_PARAM_UTMI</a>;
+<a name="l04585"></a>04585                         } <span class="keywordflow">else</span> {
+<a name="l04586"></a>04586                                 val = <a class="code" href="dwc__otg__core__if_8h.html#1951e77698d1cecdac00c786428146bf">DWC_PHY_TYPE_PARAM_ULPI</a>;
+<a name="l04587"></a>04587                         }
+<a name="l04588"></a>04588                 }
+<a name="l04589"></a>04589                 retval = -DWC_E_INVALID;
+<a name="l04590"></a>04590         }
+<a name="l04591"></a>04591 <span class="preprocessor">#endif</span>
+<a name="l04592"></a>04592 <span class="preprocessor"></span>        core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#8b5d4e0c98c46d0d4e80b6faf66daf72">phy_type</a> = val;
+<a name="l04593"></a>04593         <span class="keywordflow">return</span> retval;
+<a name="l04594"></a>04594 }
+<a name="l04595"></a>04595 
+<a name="l04596"></a><a class="code" href="dwc__otg__core__if_8h.html#e49dd633ec87aa71335ef6ef312283a3">04596</a> int32_t <a class="code" href="dwc__otg__cil_8c.html#e49dd633ec87aa71335ef6ef312283a3">dwc_otg_get_param_phy_type</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l04597"></a>04597 {
+<a name="l04598"></a>04598         <span class="keywordflow">return</span> core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#8b5d4e0c98c46d0d4e80b6faf66daf72">phy_type</a>;
+<a name="l04599"></a>04599 }
+<a name="l04600"></a>04600 
+<a name="l04601"></a><a class="code" href="dwc__otg__core__if_8h.html#7acd153b5577a3db825fa08d243ae856">04601</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#7acd153b5577a3db825fa08d243ae856">dwc_otg_set_param_speed</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, int32_t val)
+<a name="l04602"></a>04602 {
+<a name="l04603"></a>04603         <span class="keywordtype">int</span> retval = 0;
+<a name="l04604"></a>04604         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#c4138a87302505f6ef79dc3bfb4951c0">DWC_OTG_PARAM_TEST</a>(val, 0, 1)) {
+<a name="l04605"></a>04605                 DWC_WARN(<span class="stringliteral">"Wrong value for speed parameter\n"</span>);
+<a name="l04606"></a>04606                 DWC_WARN(<span class="stringliteral">"max_speed parameter must be 0 or 1\n"</span>);
+<a name="l04607"></a>04607                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l04608"></a>04608         }
+<a name="l04609"></a>04609         <span class="keywordflow">if</span> ((val == 0)
+<a name="l04610"></a>04610             &amp;&amp; <a class="code" href="dwc__otg__cil_8c.html#e49dd633ec87aa71335ef6ef312283a3">dwc_otg_get_param_phy_type</a>(core_if) == <a class="code" href="dwc__otg__core__if_8h.html#f7395410ea596c4c660f61ff41cb38b8">DWC_PHY_TYPE_PARAM_FS</a>) {
+<a name="l04611"></a>04611                 <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#d3dd61d5d48c2fc06bf4b2d37e848c93">dwc_otg_param_initialized</a>(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#d2c4f622f1c14f68c6e60e2603acd09d">speed</a>)) {
+<a name="l04612"></a>04612                         DWC_ERROR
+<a name="l04613"></a>04613                             (<span class="stringliteral">"%d invalid for speed paremter. Check HW configuration.\n"</span>,
+<a name="l04614"></a>04614                              val);
+<a name="l04615"></a>04615                 }
+<a name="l04616"></a>04616                 val =
+<a name="l04617"></a>04617                     (<a class="code" href="dwc__otg__cil_8c.html#e49dd633ec87aa71335ef6ef312283a3">dwc_otg_get_param_phy_type</a>(core_if) ==
+<a name="l04618"></a>04618                      <a class="code" href="dwc__otg__core__if_8h.html#f7395410ea596c4c660f61ff41cb38b8">DWC_PHY_TYPE_PARAM_FS</a> ? 1 : 0);
+<a name="l04619"></a>04619                 retval = -DWC_E_INVALID;
+<a name="l04620"></a>04620         }
+<a name="l04621"></a>04621         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#d2c4f622f1c14f68c6e60e2603acd09d">speed</a> = val;
+<a name="l04622"></a>04622         <span class="keywordflow">return</span> retval;
+<a name="l04623"></a>04623 }
+<a name="l04624"></a>04624 
+<a name="l04625"></a><a class="code" href="dwc__otg__core__if_8h.html#f18994b0fe09d9d3031ef8290945c1ea">04625</a> int32_t <a class="code" href="dwc__otg__cil_8c.html#f18994b0fe09d9d3031ef8290945c1ea">dwc_otg_get_param_speed</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l04626"></a>04626 {
+<a name="l04627"></a>04627         <span class="keywordflow">return</span> core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#d2c4f622f1c14f68c6e60e2603acd09d">speed</a>;
+<a name="l04628"></a>04628 }
+<a name="l04629"></a>04629 
+<a name="l04630"></a><a class="code" href="dwc__otg__core__if_8h.html#354ce49f65334e829c2694811c4f2016">04630</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#354ce49f65334e829c2694811c4f2016">dwc_otg_set_param_host_ls_low_power_phy_clk</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if,
+<a name="l04631"></a>04631                                                 int32_t val)
+<a name="l04632"></a>04632 {
+<a name="l04633"></a>04633         <span class="keywordtype">int</span> retval = 0;
+<a name="l04634"></a>04634 
+<a name="l04635"></a>04635         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#c4138a87302505f6ef79dc3bfb4951c0">DWC_OTG_PARAM_TEST</a>(val, 0, 1)) {
+<a name="l04636"></a>04636                 DWC_WARN
+<a name="l04637"></a>04637                     (<span class="stringliteral">"Wrong value for host_ls_low_power_phy_clk parameter\n"</span>);
+<a name="l04638"></a>04638                 DWC_WARN(<span class="stringliteral">"host_ls_low_power_phy_clk must be 0 or 1\n"</span>);
+<a name="l04639"></a>04639                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l04640"></a>04640         }
+<a name="l04641"></a>04641 
+<a name="l04642"></a>04642         <span class="keywordflow">if</span> ((val == <a class="code" href="dwc__otg__core__if_8h.html#3d57c56290d6cd9252eb8ccacb028f46">DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ</a>)
+<a name="l04643"></a>04643             &amp;&amp; (<a class="code" href="dwc__otg__cil_8c.html#e49dd633ec87aa71335ef6ef312283a3">dwc_otg_get_param_phy_type</a>(core_if) == <a class="code" href="dwc__otg__core__if_8h.html#f7395410ea596c4c660f61ff41cb38b8">DWC_PHY_TYPE_PARAM_FS</a>)) {
+<a name="l04644"></a>04644                 <span class="keywordflow">if</span>(<a class="code" href="dwc__otg__cil_8c.html#d3dd61d5d48c2fc06bf4b2d37e848c93">dwc_otg_param_initialized</a>(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#98f413798f20dc40036a2ec527935a7d">host_ls_low_power_phy_clk</a>)) {
+<a name="l04645"></a>04645                         DWC_ERROR(<span class="stringliteral">"%d invalid for host_ls_low_power_phy_clk. Check HW configuration.\n"</span>,
+<a name="l04646"></a>04646                      val);
+<a name="l04647"></a>04647                 }
+<a name="l04648"></a>04648                 val =
+<a name="l04649"></a>04649                     (<a class="code" href="dwc__otg__cil_8c.html#e49dd633ec87aa71335ef6ef312283a3">dwc_otg_get_param_phy_type</a>(core_if) ==
+<a name="l04650"></a>04650                      <a class="code" href="dwc__otg__core__if_8h.html#f7395410ea596c4c660f61ff41cb38b8">DWC_PHY_TYPE_PARAM_FS</a>) ?
+<a name="l04651"></a>04651                     <a class="code" href="dwc__otg__core__if_8h.html#5037c1f130bf6b40970dbf9a498fb918">DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ</a> :
+<a name="l04652"></a>04652                     <a class="code" href="dwc__otg__core__if_8h.html#3d57c56290d6cd9252eb8ccacb028f46">DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ</a>;
+<a name="l04653"></a>04653                 retval = -DWC_E_INVALID;
+<a name="l04654"></a>04654         }
+<a name="l04655"></a>04655 
+<a name="l04656"></a>04656         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#98f413798f20dc40036a2ec527935a7d">host_ls_low_power_phy_clk</a> = val;
+<a name="l04657"></a>04657         <span class="keywordflow">return</span> retval;
+<a name="l04658"></a>04658 }
+<a name="l04659"></a>04659 
+<a name="l04660"></a><a class="code" href="dwc__otg__core__if_8h.html#02ea6a179d92658c4cf4e5b513cb2414">04660</a> int32_t <a class="code" href="dwc__otg__cil_8c.html#02ea6a179d92658c4cf4e5b513cb2414">dwc_otg_get_param_host_ls_low_power_phy_clk</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l04661"></a>04661 {
+<a name="l04662"></a>04662         <span class="keywordflow">return</span> core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#98f413798f20dc40036a2ec527935a7d">host_ls_low_power_phy_clk</a>;
+<a name="l04663"></a>04663 }
+<a name="l04664"></a>04664 
+<a name="l04665"></a><a class="code" href="dwc__otg__core__if_8h.html#5dab15db053bd02c6bc9619e189a6a14">04665</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#5dab15db053bd02c6bc9619e189a6a14">dwc_otg_set_param_phy_ulpi_ddr</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, int32_t val)
+<a name="l04666"></a>04666 {
+<a name="l04667"></a>04667         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#c4138a87302505f6ef79dc3bfb4951c0">DWC_OTG_PARAM_TEST</a>(val, 0, 1)) {
+<a name="l04668"></a>04668                 DWC_WARN(<span class="stringliteral">"Wrong value for phy_ulpi_ddr\n"</span>);
+<a name="l04669"></a>04669                 DWC_WARN(<span class="stringliteral">"phy_upli_ddr must be 0 or 1\n"</span>);
+<a name="l04670"></a>04670                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l04671"></a>04671         }
+<a name="l04672"></a>04672 
+<a name="l04673"></a>04673         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#6fc9a3fbe3c36cbbc231f1642ee96cfe">phy_ulpi_ddr</a> = val;
+<a name="l04674"></a>04674         <span class="keywordflow">return</span> 0;
+<a name="l04675"></a>04675 }
+<a name="l04676"></a>04676 
+<a name="l04677"></a><a class="code" href="dwc__otg__core__if_8h.html#95655db9d2dce391da40361fe310599c">04677</a> int32_t <a class="code" href="dwc__otg__cil_8c.html#95655db9d2dce391da40361fe310599c">dwc_otg_get_param_phy_ulpi_ddr</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l04678"></a>04678 {
+<a name="l04679"></a>04679         <span class="keywordflow">return</span> core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#6fc9a3fbe3c36cbbc231f1642ee96cfe">phy_ulpi_ddr</a>;
+<a name="l04680"></a>04680 }
+<a name="l04681"></a>04681 
+<a name="l04682"></a><a class="code" href="dwc__otg__core__if_8h.html#a12296bcb04a3b0f6f80037590e97bec">04682</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#a12296bcb04a3b0f6f80037590e97bec">dwc_otg_set_param_phy_ulpi_ext_vbus</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if,
+<a name="l04683"></a>04683                                         int32_t val)
+<a name="l04684"></a>04684 {
+<a name="l04685"></a>04685         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#c4138a87302505f6ef79dc3bfb4951c0">DWC_OTG_PARAM_TEST</a>(val, 0, 1)) {
+<a name="l04686"></a>04686                 DWC_WARN(<span class="stringliteral">"Wrong valaue for phy_ulpi_ext_vbus\n"</span>);
+<a name="l04687"></a>04687                 DWC_WARN(<span class="stringliteral">"phy_ulpi_ext_vbus must be 0 or 1\n"</span>);
+<a name="l04688"></a>04688                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l04689"></a>04689         }
+<a name="l04690"></a>04690 
+<a name="l04691"></a>04691         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#3b6fa0a7fe7d7f87326894fdbe0aa375">phy_ulpi_ext_vbus</a> = val;
+<a name="l04692"></a>04692         <span class="keywordflow">return</span> 0;
+<a name="l04693"></a>04693 }
+<a name="l04694"></a>04694 
+<a name="l04695"></a><a class="code" href="dwc__otg__core__if_8h.html#b0604fadb0b685a106507eacd18e12a6">04695</a> int32_t <a class="code" href="dwc__otg__cil_8c.html#b0604fadb0b685a106507eacd18e12a6">dwc_otg_get_param_phy_ulpi_ext_vbus</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l04696"></a>04696 {
+<a name="l04697"></a>04697         <span class="keywordflow">return</span> core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#3b6fa0a7fe7d7f87326894fdbe0aa375">phy_ulpi_ext_vbus</a>;
+<a name="l04698"></a>04698 }
+<a name="l04699"></a>04699 
+<a name="l04700"></a><a class="code" href="dwc__otg__core__if_8h.html#1eacecc96e1ab100cbf129ad6aa5f6c8">04700</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#1eacecc96e1ab100cbf129ad6aa5f6c8">dwc_otg_set_param_phy_utmi_width</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, int32_t val)
+<a name="l04701"></a>04701 {
+<a name="l04702"></a>04702         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#c4138a87302505f6ef79dc3bfb4951c0">DWC_OTG_PARAM_TEST</a>(val, 8, 8) &amp;&amp; <a class="code" href="dwc__otg__cil_8c.html#c4138a87302505f6ef79dc3bfb4951c0">DWC_OTG_PARAM_TEST</a>(val, 16, 16)) {
+<a name="l04703"></a>04703                 DWC_WARN(<span class="stringliteral">"Wrong valaue for phy_utmi_width\n"</span>);
+<a name="l04704"></a>04704                 DWC_WARN(<span class="stringliteral">"phy_utmi_width must be 8 or 16\n"</span>);
+<a name="l04705"></a>04705                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l04706"></a>04706         }
+<a name="l04707"></a>04707 
+<a name="l04708"></a>04708         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#41f5a03ab1b68564b240e03f33a09dde">phy_utmi_width</a> = val;
+<a name="l04709"></a>04709         <span class="keywordflow">return</span> 0;
+<a name="l04710"></a>04710 }
+<a name="l04711"></a>04711 
+<a name="l04712"></a><a class="code" href="dwc__otg__core__if_8h.html#9dfa6a24c38b5ba13c08abe22d532a1d">04712</a> int32_t <a class="code" href="dwc__otg__cil_8c.html#9dfa6a24c38b5ba13c08abe22d532a1d">dwc_otg_get_param_phy_utmi_width</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l04713"></a>04713 {
+<a name="l04714"></a>04714         <span class="keywordflow">return</span> core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#41f5a03ab1b68564b240e03f33a09dde">phy_utmi_width</a>;
+<a name="l04715"></a>04715 }
+<a name="l04716"></a>04716 
+<a name="l04717"></a><a class="code" href="dwc__otg__core__if_8h.html#f235e9c7b844b899d759a073a84f782f">04717</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#f235e9c7b844b899d759a073a84f782f">dwc_otg_set_param_ulpi_fs_ls</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, int32_t val)
+<a name="l04718"></a>04718 {
+<a name="l04719"></a>04719         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#c4138a87302505f6ef79dc3bfb4951c0">DWC_OTG_PARAM_TEST</a>(val, 0, 1)) {
+<a name="l04720"></a>04720                 DWC_WARN(<span class="stringliteral">"Wrong valaue for ulpi_fs_ls\n"</span>);
+<a name="l04721"></a>04721                 DWC_WARN(<span class="stringliteral">"ulpi_fs_ls must be 0 or 1\n"</span>);
+<a name="l04722"></a>04722                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l04723"></a>04723         }
+<a name="l04724"></a>04724 
+<a name="l04725"></a>04725         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#3d7cfc3c416010102b2c671dfaa828d5">ulpi_fs_ls</a> = val;
+<a name="l04726"></a>04726         <span class="keywordflow">return</span> 0;
+<a name="l04727"></a>04727 }
+<a name="l04728"></a>04728 
+<a name="l04729"></a><a class="code" href="dwc__otg__core__if_8h.html#0ee03a3468e74cd2e38da1617b88313b">04729</a> int32_t <a class="code" href="dwc__otg__cil_8c.html#0ee03a3468e74cd2e38da1617b88313b">dwc_otg_get_param_ulpi_fs_ls</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l04730"></a>04730 {
+<a name="l04731"></a>04731         <span class="keywordflow">return</span> core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#3d7cfc3c416010102b2c671dfaa828d5">ulpi_fs_ls</a>;
+<a name="l04732"></a>04732 }
+<a name="l04733"></a>04733 
+<a name="l04734"></a><a class="code" href="dwc__otg__core__if_8h.html#b05c92754c0ebc3d58ea0c090b9659de">04734</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#b05c92754c0ebc3d58ea0c090b9659de">dwc_otg_set_param_ts_dline</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, int32_t val)
+<a name="l04735"></a>04735 {
+<a name="l04736"></a>04736         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#c4138a87302505f6ef79dc3bfb4951c0">DWC_OTG_PARAM_TEST</a>(val, 0, 1)) {
+<a name="l04737"></a>04737                 DWC_WARN(<span class="stringliteral">"Wrong valaue for ts_dline\n"</span>);
+<a name="l04738"></a>04738                 DWC_WARN(<span class="stringliteral">"ts_dline must be 0 or 1\n"</span>);
+<a name="l04739"></a>04739                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l04740"></a>04740         }
+<a name="l04741"></a>04741 
+<a name="l04742"></a>04742         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#879afefd6e13233a78d74ee71d3ee75e">ts_dline</a> = val;
+<a name="l04743"></a>04743         <span class="keywordflow">return</span> 0;
+<a name="l04744"></a>04744 }
+<a name="l04745"></a>04745 
+<a name="l04746"></a><a class="code" href="dwc__otg__core__if_8h.html#025a93aef8cabae431033cb4fdc7772f">04746</a> int32_t <a class="code" href="dwc__otg__cil_8c.html#025a93aef8cabae431033cb4fdc7772f">dwc_otg_get_param_ts_dline</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l04747"></a>04747 {
+<a name="l04748"></a>04748         <span class="keywordflow">return</span> core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#879afefd6e13233a78d74ee71d3ee75e">ts_dline</a>;
+<a name="l04749"></a>04749 }
+<a name="l04750"></a>04750 
+<a name="l04751"></a><a class="code" href="dwc__otg__core__if_8h.html#65d7407ed24c82e158a38ab2a60120c4">04751</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#65d7407ed24c82e158a38ab2a60120c4">dwc_otg_set_param_i2c_enable</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, int32_t val)
+<a name="l04752"></a>04752 {
+<a name="l04753"></a>04753         <span class="keywordtype">int</span> retval = 0;
+<a name="l04754"></a>04754         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#c4138a87302505f6ef79dc3bfb4951c0">DWC_OTG_PARAM_TEST</a>(val, 0, 1)) {
+<a name="l04755"></a>04755                 DWC_WARN(<span class="stringliteral">"Wrong valaue for i2c_enable\n"</span>);
+<a name="l04756"></a>04756                 DWC_WARN(<span class="stringliteral">"i2c_enable must be 0 or 1\n"</span>);
+<a name="l04757"></a>04757                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l04758"></a>04758         }
+<a name="l04759"></a>04759 <span class="preprocessor">#ifndef NO_FS_PHY_HW_CHECK</span>
+<a name="l04760"></a>04760 <span class="preprocessor"></span>        <span class="keywordflow">if</span> (val == 1 &amp;&amp; core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#91d0e0a5e8e048024c8846d12e00cecc">hwcfg3</a>.<a class="code" href="unionhwcfg3__data.html#928c5de42f8af177ce34712123b5093c">b</a>.<a class="code" href="unionhwcfg3__data.html#dd2115f4a4bfa47b2c9c9a7b5f42e203">i2c</a> == 0) {
+<a name="l04761"></a>04761                 <span class="keywordflow">if</span>(<a class="code" href="dwc__otg__cil_8c.html#d3dd61d5d48c2fc06bf4b2d37e848c93">dwc_otg_param_initialized</a>(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#6b0a0ab15284a541ae079beecaf3e617">i2c_enable</a>)) {
+<a name="l04762"></a>04762                         DWC_ERROR(<span class="stringliteral">"%d invalid for i2c_enable. Check HW configuration.\n"</span>,
+<a name="l04763"></a>04763                      val);
+<a name="l04764"></a>04764                 }
+<a name="l04765"></a>04765                 val = 0;
+<a name="l04766"></a>04766                 retval = -DWC_E_INVALID;
+<a name="l04767"></a>04767         }
+<a name="l04768"></a>04768 <span class="preprocessor">#endif</span>
+<a name="l04769"></a>04769 <span class="preprocessor"></span>
+<a name="l04770"></a>04770         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#6b0a0ab15284a541ae079beecaf3e617">i2c_enable</a> = val;
+<a name="l04771"></a>04771         <span class="keywordflow">return</span> retval;
+<a name="l04772"></a>04772 }
+<a name="l04773"></a>04773 
+<a name="l04774"></a><a class="code" href="dwc__otg__core__if_8h.html#80cf1905c95391fa1acaa2237182ddf8">04774</a> int32_t <a class="code" href="dwc__otg__cil_8c.html#80cf1905c95391fa1acaa2237182ddf8">dwc_otg_get_param_i2c_enable</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l04775"></a>04775 {
+<a name="l04776"></a>04776         <span class="keywordflow">return</span> core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#6b0a0ab15284a541ae079beecaf3e617">i2c_enable</a>;
+<a name="l04777"></a>04777 }
+<a name="l04778"></a>04778 
+<a name="l04779"></a><a class="code" href="dwc__otg__core__if_8h.html#2119a493582bea4004b5fdeba15f1609">04779</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#2119a493582bea4004b5fdeba15f1609">dwc_otg_set_param_dev_perio_tx_fifo_size</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if,
+<a name="l04780"></a>04780                                              int32_t val, <span class="keywordtype">int</span> fifo_num)
+<a name="l04781"></a>04781 {
+<a name="l04782"></a>04782         <span class="keywordtype">int</span> retval = 0;
+<a name="l04783"></a>04783 
+<a name="l04784"></a>04784         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#c4138a87302505f6ef79dc3bfb4951c0">DWC_OTG_PARAM_TEST</a>(val, 4, 768)) {
+<a name="l04785"></a>04785                 DWC_WARN(<span class="stringliteral">"Wrong value for dev_perio_tx_fifo_size\n"</span>);
+<a name="l04786"></a>04786                 DWC_WARN(<span class="stringliteral">"dev_perio_tx_fifo_size must be 4-768\n"</span>);
+<a name="l04787"></a>04787                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l04788"></a>04788         }
+<a name="l04789"></a>04789 
+<a name="l04790"></a>04790         <span class="keywordflow">if</span> (val &gt; (dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#efd9e780825f992dbc6cf46d2d72869e">dptxfsiz_dieptxf</a>[fifo_num]))) {
+<a name="l04791"></a>04791                 <span class="keywordflow">if</span>(<a class="code" href="dwc__otg__cil_8c.html#d3dd61d5d48c2fc06bf4b2d37e848c93">dwc_otg_param_initialized</a>(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#2958d325289f4a77b6435cda729e5f6e">dev_perio_tx_fifo_size</a>[fifo_num])) {
+<a name="l04792"></a>04792                         DWC_ERROR(<span class="stringliteral">"`%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n"</span>,
+<a name="l04793"></a>04793                      val, fifo_num);
+<a name="l04794"></a>04794                 }
+<a name="l04795"></a>04795                 val = (dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#efd9e780825f992dbc6cf46d2d72869e">dptxfsiz_dieptxf</a>[fifo_num]));
+<a name="l04796"></a>04796                 retval = -DWC_E_INVALID;
+<a name="l04797"></a>04797         }
+<a name="l04798"></a>04798 
+<a name="l04799"></a>04799         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#2958d325289f4a77b6435cda729e5f6e">dev_perio_tx_fifo_size</a>[fifo_num] = val;
+<a name="l04800"></a>04800         <span class="keywordflow">return</span> retval;
+<a name="l04801"></a>04801 }
+<a name="l04802"></a>04802 
+<a name="l04803"></a><a class="code" href="dwc__otg__core__if_8h.html#d9bf0270a9b9617f0d196dd566a1c610">04803</a> int32_t <a class="code" href="dwc__otg__cil_8c.html#d9bf0270a9b9617f0d196dd566a1c610">dwc_otg_get_param_dev_perio_tx_fifo_size</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if,
+<a name="l04804"></a>04804                                                  <span class="keywordtype">int</span> fifo_num)
+<a name="l04805"></a>04805 {
+<a name="l04806"></a>04806         <span class="keywordflow">return</span> core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#2958d325289f4a77b6435cda729e5f6e">dev_perio_tx_fifo_size</a>[fifo_num];
+<a name="l04807"></a>04807 }
+<a name="l04808"></a>04808 
+<a name="l04809"></a><a class="code" href="dwc__otg__core__if_8h.html#2eefd02d72c79200072d54b4eb13e5cd">04809</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#2eefd02d72c79200072d54b4eb13e5cd">dwc_otg_set_param_en_multiple_tx_fifo</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if,
+<a name="l04810"></a>04810                                           int32_t val)
+<a name="l04811"></a>04811 {
+<a name="l04812"></a>04812         <span class="keywordtype">int</span> retval = 0;
+<a name="l04813"></a>04813         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#c4138a87302505f6ef79dc3bfb4951c0">DWC_OTG_PARAM_TEST</a>(val, 0, 1)) {
+<a name="l04814"></a>04814                 DWC_WARN(<span class="stringliteral">"Wrong valaue for en_multiple_tx_fifo,\n"</span>);
+<a name="l04815"></a>04815                 DWC_WARN(<span class="stringliteral">"en_multiple_tx_fifo must be 0 or 1\n"</span>);
+<a name="l04816"></a>04816                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l04817"></a>04817         }
+<a name="l04818"></a>04818 
+<a name="l04819"></a>04819         <span class="keywordflow">if</span> (val == 1 &amp;&amp; core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#9c1394f3c46adde2fa7be79bf0237f9b">hwcfg4</a>.<a class="code" href="unionhwcfg4__data.html#9fb9175668e2381c568c5adbf6e5225d">b</a>.<a class="code" href="unionhwcfg4__data.html#175e8897d6e3c8ef4026413943de503b">ded_fifo_en</a> == 0) {
+<a name="l04820"></a>04820                 <span class="keywordflow">if</span>(<a class="code" href="dwc__otg__cil_8c.html#d3dd61d5d48c2fc06bf4b2d37e848c93">dwc_otg_param_initialized</a>(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#d61279dcea66973b2915e335efb07fe3">en_multiple_tx_fifo</a>)) {
+<a name="l04821"></a>04821                         DWC_ERROR(<span class="stringliteral">"%d invalid for parameter en_multiple_tx_fifo. Check HW configuration.\n"</span>,
+<a name="l04822"></a>04822                      val);
+<a name="l04823"></a>04823                 }
+<a name="l04824"></a>04824                 val = 0;
+<a name="l04825"></a>04825                 retval = -DWC_E_INVALID;
+<a name="l04826"></a>04826         }
+<a name="l04827"></a>04827 
+<a name="l04828"></a>04828         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#d61279dcea66973b2915e335efb07fe3">en_multiple_tx_fifo</a> = val;
+<a name="l04829"></a>04829         <span class="keywordflow">return</span> retval;
+<a name="l04830"></a>04830 }
+<a name="l04831"></a>04831 
+<a name="l04832"></a><a class="code" href="dwc__otg__core__if_8h.html#bc8e0312a565efb2d5117984219b4460">04832</a> int32_t <a class="code" href="dwc__otg__cil_8c.html#bc8e0312a565efb2d5117984219b4460">dwc_otg_get_param_en_multiple_tx_fifo</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l04833"></a>04833 {
+<a name="l04834"></a>04834         <span class="keywordflow">return</span> core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#d61279dcea66973b2915e335efb07fe3">en_multiple_tx_fifo</a>;
+<a name="l04835"></a>04835 }
+<a name="l04836"></a>04836 
+<a name="l04837"></a><a class="code" href="dwc__otg__cil_8c.html#44bf6b41f0892f480ea6c03a2ac1e73f">04837</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#44bf6b41f0892f480ea6c03a2ac1e73f">dwc_otg_set_param_dev_tx_fifo_size</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, int32_t val,
+<a name="l04838"></a>04838                                        <span class="keywordtype">int</span> fifo_num)
+<a name="l04839"></a>04839 {
+<a name="l04840"></a>04840         <span class="keywordtype">int</span> retval = 0;
+<a name="l04841"></a>04841 
+<a name="l04842"></a>04842         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#c4138a87302505f6ef79dc3bfb4951c0">DWC_OTG_PARAM_TEST</a>(val, 4, 768)) {
+<a name="l04843"></a>04843                 DWC_WARN(<span class="stringliteral">"Wrong value for dev_tx_fifo_size\n"</span>);
+<a name="l04844"></a>04844                 DWC_WARN(<span class="stringliteral">"dev_tx_fifo_size must be 4-768\n"</span>);
+<a name="l04845"></a>04845                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l04846"></a>04846         }
+<a name="l04847"></a>04847 
+<a name="l04848"></a>04848         <span class="keywordflow">if</span> (val &gt; (dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#efd9e780825f992dbc6cf46d2d72869e">dptxfsiz_dieptxf</a>[fifo_num]))) {
+<a name="l04849"></a>04849                 <span class="keywordflow">if</span>(<a class="code" href="dwc__otg__cil_8c.html#d3dd61d5d48c2fc06bf4b2d37e848c93">dwc_otg_param_initialized</a>(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#6e0c5d06467fbf3458f11f7eb8153a8b">dev_tx_fifo_size</a>[fifo_num])) {
+<a name="l04850"></a>04850                         DWC_ERROR(<span class="stringliteral">"`%d' invalid for parameter `dev_tx_fifo_size_%d'. Check HW configuration.\n"</span>,
+<a name="l04851"></a>04851                      val, fifo_num);
+<a name="l04852"></a>04852                 }
+<a name="l04853"></a>04853                 val = (dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#efd9e780825f992dbc6cf46d2d72869e">dptxfsiz_dieptxf</a>[fifo_num]));
+<a name="l04854"></a>04854                 retval = -DWC_E_INVALID;
+<a name="l04855"></a>04855         }
+<a name="l04856"></a>04856 
+<a name="l04857"></a>04857         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#6e0c5d06467fbf3458f11f7eb8153a8b">dev_tx_fifo_size</a>[fifo_num] = val;
+<a name="l04858"></a>04858         <span class="keywordflow">return</span> retval;
+<a name="l04859"></a>04859 }
+<a name="l04860"></a>04860 
+<a name="l04861"></a><a class="code" href="dwc__otg__core__if_8h.html#99a491c648b6066077426c9cdc374aa8">04861</a> int32_t <a class="code" href="dwc__otg__cil_8c.html#99a491c648b6066077426c9cdc374aa8">dwc_otg_get_param_dev_tx_fifo_size</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if,
+<a name="l04862"></a>04862                                            <span class="keywordtype">int</span> fifo_num)
+<a name="l04863"></a>04863 {
+<a name="l04864"></a>04864         <span class="keywordflow">return</span> core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#6e0c5d06467fbf3458f11f7eb8153a8b">dev_tx_fifo_size</a>[fifo_num];
+<a name="l04865"></a>04865 }
+<a name="l04866"></a>04866 
+<a name="l04867"></a><a class="code" href="dwc__otg__core__if_8h.html#6095d6a93f901f32522d4b950c99a8e1">04867</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#6095d6a93f901f32522d4b950c99a8e1">dwc_otg_set_param_thr_ctl</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, int32_t val)
+<a name="l04868"></a>04868 {
+<a name="l04869"></a>04869         <span class="keywordtype">int</span> retval = 0;
+<a name="l04870"></a>04870 
+<a name="l04871"></a>04871         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#c4138a87302505f6ef79dc3bfb4951c0">DWC_OTG_PARAM_TEST</a>(val, 0, 7)) {
+<a name="l04872"></a>04872                 DWC_WARN(<span class="stringliteral">"Wrong value for thr_ctl\n"</span>);
+<a name="l04873"></a>04873                 DWC_WARN(<span class="stringliteral">"thr_ctl must be 0-7\n"</span>);
+<a name="l04874"></a>04874                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l04875"></a>04875         }
+<a name="l04876"></a>04876 
+<a name="l04877"></a>04877         <span class="keywordflow">if</span> ((val != 0) &amp;&amp;
+<a name="l04878"></a>04878             (!<a class="code" href="dwc__otg__cil_8c.html#0c78da7b7e7b59b31bd99a07d926a298">dwc_otg_get_param_dma_enable</a>(core_if) ||
+<a name="l04879"></a>04879              !core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#9c1394f3c46adde2fa7be79bf0237f9b">hwcfg4</a>.<a class="code" href="unionhwcfg4__data.html#9fb9175668e2381c568c5adbf6e5225d">b</a>.<a class="code" href="unionhwcfg4__data.html#175e8897d6e3c8ef4026413943de503b">ded_fifo_en</a>)) {
+<a name="l04880"></a>04880                 <span class="keywordflow">if</span>(<a class="code" href="dwc__otg__cil_8c.html#d3dd61d5d48c2fc06bf4b2d37e848c93">dwc_otg_param_initialized</a>(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#1610a4b28bea581c46f251d995bf4a51">thr_ctl</a>)) {
+<a name="l04881"></a>04881                         DWC_ERROR(<span class="stringliteral">"%d invalid for parameter thr_ctl. Check HW configuration.\n"</span>,
+<a name="l04882"></a>04882                      val);
+<a name="l04883"></a>04883                 }
+<a name="l04884"></a>04884                 val = 0;
+<a name="l04885"></a>04885                 retval = -DWC_E_INVALID;
+<a name="l04886"></a>04886         }
+<a name="l04887"></a>04887 
+<a name="l04888"></a>04888         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#1610a4b28bea581c46f251d995bf4a51">thr_ctl</a> = val;
+<a name="l04889"></a>04889         <span class="keywordflow">return</span> retval;
+<a name="l04890"></a>04890 }
+<a name="l04891"></a>04891 
+<a name="l04892"></a><a class="code" href="dwc__otg__cil_8c.html#99787b8e86a8d37e1a5be93d52487a3a">04892</a> int32_t <a class="code" href="dwc__otg__cil_8c.html#99787b8e86a8d37e1a5be93d52487a3a">dwc_otg_get_param_thr_ctl</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l04893"></a>04893 {
+<a name="l04894"></a>04894         <span class="keywordflow">return</span> core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#1610a4b28bea581c46f251d995bf4a51">thr_ctl</a>;
+<a name="l04895"></a>04895 }
+<a name="l04896"></a>04896 
+<a name="l04897"></a><a class="code" href="dwc__otg__core__if_8h.html#e3a62b66e19a302a55046830f5eecf0c">04897</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#e3a62b66e19a302a55046830f5eecf0c">dwc_otg_set_param_lpm_enable</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, int32_t val)
+<a name="l04898"></a>04898 {
+<a name="l04899"></a>04899         <span class="keywordtype">int</span> retval = 0;
+<a name="l04900"></a>04900 
+<a name="l04901"></a>04901         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#c4138a87302505f6ef79dc3bfb4951c0">DWC_OTG_PARAM_TEST</a>(val, 0, 1)) {
+<a name="l04902"></a>04902                 DWC_WARN(<span class="stringliteral">"Wrong value for lpm_enable\n"</span>);
+<a name="l04903"></a>04903                 DWC_WARN(<span class="stringliteral">"lpm_enable must be 0 or 1\n"</span>);
+<a name="l04904"></a>04904                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l04905"></a>04905         }
+<a name="l04906"></a>04906 
+<a name="l04907"></a>04907         <span class="keywordflow">if</span> (val &amp;&amp; !core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#91d0e0a5e8e048024c8846d12e00cecc">hwcfg3</a>.<a class="code" href="unionhwcfg3__data.html#928c5de42f8af177ce34712123b5093c">b</a>.<a class="code" href="unionhwcfg3__data.html#2b9c39a4ce021bfd039729ccf2c2c503">otg_lpm_en</a>) {
+<a name="l04908"></a>04908                 <span class="keywordflow">if</span>(<a class="code" href="dwc__otg__cil_8c.html#d3dd61d5d48c2fc06bf4b2d37e848c93">dwc_otg_param_initialized</a>(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#8b906ba765a10dd9fcfa1c02dbc0184e">lpm_enable</a>)) {
+<a name="l04909"></a>04909                         DWC_ERROR(<span class="stringliteral">"%d invalid for parameter lpm_enable. Check HW configuration.\n"</span>,
+<a name="l04910"></a>04910                      val);
+<a name="l04911"></a>04911                 }
+<a name="l04912"></a>04912                 val = 0;
+<a name="l04913"></a>04913                 retval = -DWC_E_INVALID;
+<a name="l04914"></a>04914         }
+<a name="l04915"></a>04915 
+<a name="l04916"></a>04916         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#8b906ba765a10dd9fcfa1c02dbc0184e">lpm_enable</a> = val;
+<a name="l04917"></a>04917         <span class="keywordflow">return</span> retval;
+<a name="l04918"></a>04918 }
+<a name="l04919"></a>04919 
+<a name="l04920"></a><a class="code" href="dwc__otg__core__if_8h.html#0e0eb29733595730396da3ddf3d0ded5">04920</a> int32_t <a class="code" href="dwc__otg__cil_8c.html#0e0eb29733595730396da3ddf3d0ded5">dwc_otg_get_param_lpm_enable</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l04921"></a>04921 {
+<a name="l04922"></a>04922         <span class="keywordflow">return</span> core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#8b906ba765a10dd9fcfa1c02dbc0184e">lpm_enable</a>;
+<a name="l04923"></a>04923 }
+<a name="l04924"></a>04924 
+<a name="l04925"></a><a class="code" href="dwc__otg__core__if_8h.html#1ed19fed8939a352f91fe1403574135e">04925</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#1ed19fed8939a352f91fe1403574135e">dwc_otg_set_param_tx_thr_length</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, int32_t val)
+<a name="l04926"></a>04926 {
+<a name="l04927"></a>04927         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#c4138a87302505f6ef79dc3bfb4951c0">DWC_OTG_PARAM_TEST</a>(val, 8, 128)) {
+<a name="l04928"></a>04928                 DWC_WARN(<span class="stringliteral">"Wrong valaue for tx_thr_length\n"</span>);
+<a name="l04929"></a>04929                 DWC_WARN(<span class="stringliteral">"tx_thr_length must be 8 - 128\n"</span>);
+<a name="l04930"></a>04930                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l04931"></a>04931         }
+<a name="l04932"></a>04932 
+<a name="l04933"></a>04933         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#c92fc907d503f9b8bb3600164c520b0e">tx_thr_length</a> = val;
+<a name="l04934"></a>04934         <span class="keywordflow">return</span> 0;
+<a name="l04935"></a>04935 }
+<a name="l04936"></a>04936 
+<a name="l04937"></a><a class="code" href="dwc__otg__cil_8c.html#e3499cd5ce6ab45640be2a5040ad4f1c">04937</a> int32_t <a class="code" href="dwc__otg__cil_8c.html#e3499cd5ce6ab45640be2a5040ad4f1c">dwc_otg_get_param_tx_thr_length</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l04938"></a>04938 {
+<a name="l04939"></a>04939         <span class="keywordflow">return</span> core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#c92fc907d503f9b8bb3600164c520b0e">tx_thr_length</a>;
+<a name="l04940"></a>04940 }
+<a name="l04941"></a>04941 
+<a name="l04942"></a><a class="code" href="dwc__otg__core__if_8h.html#20d005470a65927cb243b37619f6c6bf">04942</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#20d005470a65927cb243b37619f6c6bf">dwc_otg_set_param_rx_thr_length</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, int32_t val)
+<a name="l04943"></a>04943 {
+<a name="l04944"></a>04944         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#c4138a87302505f6ef79dc3bfb4951c0">DWC_OTG_PARAM_TEST</a>(val, 8, 128)) {
+<a name="l04945"></a>04945                 DWC_WARN(<span class="stringliteral">"Wrong valaue for rx_thr_length\n"</span>);
+<a name="l04946"></a>04946                 DWC_WARN(<span class="stringliteral">"rx_thr_length must be 8 - 128\n"</span>);
+<a name="l04947"></a>04947                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l04948"></a>04948         }
+<a name="l04949"></a>04949 
+<a name="l04950"></a>04950         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#2cb1f83013e357828fbf55ac91971d44">rx_thr_length</a> = val;
+<a name="l04951"></a>04951         <span class="keywordflow">return</span> 0;
+<a name="l04952"></a>04952 }
+<a name="l04953"></a>04953 
+<a name="l04954"></a><a class="code" href="dwc__otg__cil_8c.html#c0cd2e32622903a2c1707bf8fe9c3dba">04954</a> int32_t <a class="code" href="dwc__otg__cil_8c.html#c0cd2e32622903a2c1707bf8fe9c3dba">dwc_otg_get_param_rx_thr_length</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l04955"></a>04955 {
+<a name="l04956"></a>04956         <span class="keywordflow">return</span> core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#2cb1f83013e357828fbf55ac91971d44">rx_thr_length</a>;
+<a name="l04957"></a>04957 }
+<a name="l04958"></a>04958 
+<a name="l04959"></a><a class="code" href="dwc__otg__core__if_8h.html#920035c6082dcdfec11a20e8535e9fe9">04959</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#920035c6082dcdfec11a20e8535e9fe9">dwc_otg_set_param_dma_burst_size</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, int32_t val)
+<a name="l04960"></a>04960 {
+<a name="l04961"></a>04961         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#c4138a87302505f6ef79dc3bfb4951c0">DWC_OTG_PARAM_TEST</a>(val, 1, 1) &amp;&amp;
+<a name="l04962"></a>04962             <a class="code" href="dwc__otg__cil_8c.html#c4138a87302505f6ef79dc3bfb4951c0">DWC_OTG_PARAM_TEST</a>(val, 4, 4) &amp;&amp;
+<a name="l04963"></a>04963             <a class="code" href="dwc__otg__cil_8c.html#c4138a87302505f6ef79dc3bfb4951c0">DWC_OTG_PARAM_TEST</a>(val, 8, 8) &amp;&amp;
+<a name="l04964"></a>04964             <a class="code" href="dwc__otg__cil_8c.html#c4138a87302505f6ef79dc3bfb4951c0">DWC_OTG_PARAM_TEST</a>(val, 16, 16) &amp;&amp;
+<a name="l04965"></a>04965             <a class="code" href="dwc__otg__cil_8c.html#c4138a87302505f6ef79dc3bfb4951c0">DWC_OTG_PARAM_TEST</a>(val, 32, 32) &amp;&amp;
+<a name="l04966"></a>04966             <a class="code" href="dwc__otg__cil_8c.html#c4138a87302505f6ef79dc3bfb4951c0">DWC_OTG_PARAM_TEST</a>(val, 64, 64) &amp;&amp;
+<a name="l04967"></a>04967             <a class="code" href="dwc__otg__cil_8c.html#c4138a87302505f6ef79dc3bfb4951c0">DWC_OTG_PARAM_TEST</a>(val, 128, 128) &amp;&amp;
+<a name="l04968"></a>04968             <a class="code" href="dwc__otg__cil_8c.html#c4138a87302505f6ef79dc3bfb4951c0">DWC_OTG_PARAM_TEST</a>(val, 256, 256)) {
+<a name="l04969"></a>04969                 DWC_WARN(<span class="stringliteral">"`%d' invalid for parameter `dma_burst_size'\n"</span>, val);
+<a name="l04970"></a>04970                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l04971"></a>04971         }
+<a name="l04972"></a>04972         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#f9d2a8cd9b36d24de89121d19f693ccb">dma_burst_size</a> = val;
+<a name="l04973"></a>04973         <span class="keywordflow">return</span> 0;
+<a name="l04974"></a>04974 }
+<a name="l04975"></a>04975 
+<a name="l04976"></a><a class="code" href="dwc__otg__core__if_8h.html#7450ef9275974e46f41f12fdc6da7901">04976</a> int32_t <a class="code" href="dwc__otg__cil_8c.html#7450ef9275974e46f41f12fdc6da7901">dwc_otg_get_param_dma_burst_size</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l04977"></a>04977 {
+<a name="l04978"></a>04978         <span class="keywordflow">return</span> core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#f9d2a8cd9b36d24de89121d19f693ccb">dma_burst_size</a>;
+<a name="l04979"></a>04979 }
+<a name="l04980"></a>04980 
+<a name="l04981"></a><a class="code" href="dwc__otg__core__if_8h.html#63c0b4bfcf3b1c6c90c5572258439e1f">04981</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#63c0b4bfcf3b1c6c90c5572258439e1f">dwc_otg_set_param_pti_enable</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, int32_t val)
+<a name="l04982"></a>04982 {
+<a name="l04983"></a>04983         <span class="keywordtype">int</span> retval = 0;
+<a name="l04984"></a>04984         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#c4138a87302505f6ef79dc3bfb4951c0">DWC_OTG_PARAM_TEST</a>(val, 0, 1)) {
+<a name="l04985"></a>04985                 DWC_WARN(<span class="stringliteral">"`%d' invalid for parameter `pti_enable'\n"</span>, val);
+<a name="l04986"></a>04986                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l04987"></a>04987         }
+<a name="l04988"></a>04988         <span class="keywordflow">if</span> (val &amp;&amp; (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#afc495591efa54c74c1dd50278b57ffe">snpsid</a> &lt; <a class="code" href="dwc__otg__cil_8h.html#3d25615a19f95042bcc3512b4855cebe">OTG_CORE_REV_2_72a</a>)) {
+<a name="l04989"></a>04989                 <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#d3dd61d5d48c2fc06bf4b2d37e848c93">dwc_otg_param_initialized</a>(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#b601fde03b371b74deab1205e1329a7d">pti_enable</a>)) {
+<a name="l04990"></a>04990                         DWC_ERROR(<span class="stringliteral">"%d invalid for parameter pti_enable. Check HW configuration.\n"</span>,
+<a name="l04991"></a>04991                              val);
+<a name="l04992"></a>04992                 }
+<a name="l04993"></a>04993                 retval = -DWC_E_INVALID;
+<a name="l04994"></a>04994                 val = 0;
+<a name="l04995"></a>04995         }
+<a name="l04996"></a>04996         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#b601fde03b371b74deab1205e1329a7d">pti_enable</a> = val;
+<a name="l04997"></a>04997         <span class="keywordflow">return</span> retval;
+<a name="l04998"></a>04998 }
+<a name="l04999"></a>04999 
+<a name="l05000"></a><a class="code" href="dwc__otg__core__if_8h.html#9d729a393133a8111b68d4b5ec9fdd30">05000</a> int32_t <a class="code" href="dwc__otg__cil_8c.html#9d729a393133a8111b68d4b5ec9fdd30">dwc_otg_get_param_pti_enable</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l05001"></a>05001 {
+<a name="l05002"></a>05002         <span class="keywordflow">return</span> core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#b601fde03b371b74deab1205e1329a7d">pti_enable</a>;
+<a name="l05003"></a>05003 }
+<a name="l05004"></a>05004 
+<a name="l05005"></a><a class="code" href="dwc__otg__core__if_8h.html#7ba10fdfd2ce9f3ef4b0a2bef555a7c1">05005</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#7ba10fdfd2ce9f3ef4b0a2bef555a7c1">dwc_otg_set_param_mpi_enable</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, int32_t val)
+<a name="l05006"></a>05006 {
+<a name="l05007"></a>05007         <span class="keywordtype">int</span> retval = 0;
+<a name="l05008"></a>05008         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#c4138a87302505f6ef79dc3bfb4951c0">DWC_OTG_PARAM_TEST</a>(val, 0, 1)) {
+<a name="l05009"></a>05009                 DWC_WARN(<span class="stringliteral">"`%d' invalid for parameter `mpi_enable'\n"</span>, val);
+<a name="l05010"></a>05010                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l05011"></a>05011         }
+<a name="l05012"></a>05012         <span class="keywordflow">if</span> (val &amp;&amp; (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">hwcfg2</a>.<a class="code" href="unionhwcfg2__data.html#9dcc70e2dba617cbc6c12189be5c1d6a">b</a>.<a class="code" href="unionhwcfg2__data.html#53c36944e5bd45e6f3ecbe933d7246eb">multi_proc_int</a> == 0)) {
+<a name="l05013"></a>05013                 <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#d3dd61d5d48c2fc06bf4b2d37e848c93">dwc_otg_param_initialized</a>(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#740e50199a75b3877b7db630d49c36aa">mpi_enable</a>)) {
+<a name="l05014"></a>05014                         DWC_ERROR(<span class="stringliteral">"%d invalid for parameter mpi_enable. Check HW configuration.\n"</span>,
+<a name="l05015"></a>05015                              val);
+<a name="l05016"></a>05016                 }
+<a name="l05017"></a>05017                 retval = -DWC_E_INVALID;
+<a name="l05018"></a>05018                 val = 0;
+<a name="l05019"></a>05019         }
+<a name="l05020"></a>05020         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#740e50199a75b3877b7db630d49c36aa">mpi_enable</a> = val;
+<a name="l05021"></a>05021         <span class="keywordflow">return</span> retval;
+<a name="l05022"></a>05022 }
+<a name="l05023"></a>05023 
+<a name="l05024"></a><a class="code" href="dwc__otg__core__if_8h.html#7b9e3bced8a43e810fca322e36946f31">05024</a> int32_t <a class="code" href="dwc__otg__cil_8c.html#7b9e3bced8a43e810fca322e36946f31">dwc_otg_get_param_mpi_enable</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l05025"></a>05025 {
+<a name="l05026"></a>05026         <span class="keywordflow">return</span> core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#740e50199a75b3877b7db630d49c36aa">mpi_enable</a>;
+<a name="l05027"></a>05027 }
+<a name="l05028"></a>05028 
+<a name="l05029"></a><a class="code" href="dwc__otg__core__if_8h.html#93036faefc8179eef11c8ca0b18993a8">05029</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#93036faefc8179eef11c8ca0b18993a8">dwc_otg_set_param_ic_usb_cap</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if,
+<a name="l05030"></a>05030                                         int32_t val)
+<a name="l05031"></a>05031 {
+<a name="l05032"></a>05032         <span class="keywordtype">int</span> retval = 0;
+<a name="l05033"></a>05033         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#c4138a87302505f6ef79dc3bfb4951c0">DWC_OTG_PARAM_TEST</a>(val, 0, 1)) {
+<a name="l05034"></a>05034                 DWC_WARN(<span class="stringliteral">"`%d' invalid for parameter `ic_usb_cap'\n"</span>, val);
+<a name="l05035"></a>05035                 DWC_WARN(<span class="stringliteral">"ic_usb_cap must be 0 or 1\n"</span>);
+<a name="l05036"></a>05036                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l05037"></a>05037         }
+<a name="l05038"></a>05038 
+<a name="l05039"></a>05039         <span class="keywordflow">if</span> (val &amp;&amp; (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#91d0e0a5e8e048024c8846d12e00cecc">hwcfg3</a>.<a class="code" href="unionhwcfg3__data.html#928c5de42f8af177ce34712123b5093c">b</a>.<a class="code" href="unionhwcfg3__data.html#a01a48361a21cb9dfbbd555823b8531b">otg_enable_ic_usb</a> == 0)) {
+<a name="l05040"></a>05040                 <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#d3dd61d5d48c2fc06bf4b2d37e848c93">dwc_otg_param_initialized</a>(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#359a3cb3a7b4800a0c32750005c9fd1b">ic_usb_cap</a>)) {
+<a name="l05041"></a>05041                         DWC_ERROR(<span class="stringliteral">"%d invalid for parameter ic_usb_cap. Check HW configuration.\n"</span>,
+<a name="l05042"></a>05042                              val);
+<a name="l05043"></a>05043                 }
+<a name="l05044"></a>05044                 retval = -DWC_E_INVALID;
+<a name="l05045"></a>05045                 val = 0;
+<a name="l05046"></a>05046         }
+<a name="l05047"></a>05047         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#359a3cb3a7b4800a0c32750005c9fd1b">ic_usb_cap</a> = val;
+<a name="l05048"></a>05048         <span class="keywordflow">return</span> retval;
+<a name="l05049"></a>05049 }
+<a name="l05050"></a><a class="code" href="dwc__otg__core__if_8h.html#1ccaddc86262ff99dad6c1e44f5ff965">05050</a> int32_t <a class="code" href="dwc__otg__cil_8c.html#1ccaddc86262ff99dad6c1e44f5ff965">dwc_otg_get_param_ic_usb_cap</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l05051"></a>05051 {
+<a name="l05052"></a>05052         <span class="keywordflow">return</span> core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#359a3cb3a7b4800a0c32750005c9fd1b">ic_usb_cap</a>;
+<a name="l05053"></a>05053 }
+<a name="l05054"></a>05054 
+<a name="l05055"></a><a class="code" href="dwc__otg__core__if_8h.html#9bf87dcaa6dcea51eb3d8c30439a2138">05055</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#9bf87dcaa6dcea51eb3d8c30439a2138">dwc_otg_set_param_ahb_thr_ratio</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, int32_t val)
+<a name="l05056"></a>05056 {
+<a name="l05057"></a>05057         <span class="keywordtype">int</span> retval = 0;
+<a name="l05058"></a>05058         <span class="keywordtype">int</span> valid = 1;
+<a name="l05059"></a>05059 
+<a name="l05060"></a>05060         <span class="keywordflow">if</span>(<a class="code" href="dwc__otg__cil_8c.html#c4138a87302505f6ef79dc3bfb4951c0">DWC_OTG_PARAM_TEST</a>(val, 0, 3)) {
+<a name="l05061"></a>05061                 DWC_WARN(<span class="stringliteral">"`%d' invalid for parameter `ahb_thr_ratio'\n"</span>, val);
+<a name="l05062"></a>05062                 DWC_WARN(<span class="stringliteral">"ahb_thr_ratio must be 0 - 3\n"</span>);
+<a name="l05063"></a>05063                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l05064"></a>05064         }
+<a name="l05065"></a>05065 
+<a name="l05066"></a>05066         <span class="keywordflow">if</span>(val &amp;&amp; (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#afc495591efa54c74c1dd50278b57ffe">snpsid</a> &lt; <a class="code" href="dwc__otg__cil_8h.html#ceb592db3a34e7435e6bd9fc4cf5627c">OTG_CORE_REV_2_81a</a> || !<a class="code" href="dwc__otg__cil_8c.html#99787b8e86a8d37e1a5be93d52487a3a">dwc_otg_get_param_thr_ctl</a>(core_if))) {
+<a name="l05067"></a>05067                 valid = 0;
+<a name="l05068"></a>05068         } <span class="keywordflow">else</span> <span class="keywordflow">if</span>(val &amp;&amp; ((<a class="code" href="dwc__otg__cil_8c.html#e3499cd5ce6ab45640be2a5040ad4f1c">dwc_otg_get_param_tx_thr_length</a>(core_if) / (1 &lt;&lt; val)) &lt; 4)) {
+<a name="l05069"></a>05069                 valid = 0;
+<a name="l05070"></a>05070         }
+<a name="l05071"></a>05071         <span class="keywordflow">if</span>(valid == 0) {
+<a name="l05072"></a>05072                 <span class="keywordflow">if</span>(<a class="code" href="dwc__otg__cil_8c.html#d3dd61d5d48c2fc06bf4b2d37e848c93">dwc_otg_param_initialized</a>(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#8787af52f8d70a9100ab1fa2b0f69bfb">ahb_thr_ratio</a>)) {
+<a name="l05073"></a>05073                         DWC_ERROR(<span class="stringliteral">"%d invalid for parameter ahb_thr_ratio. Chack HW configuration.\n"</span>, val);
+<a name="l05074"></a>05074                 }
+<a name="l05075"></a>05075                 retval = -DWC_E_INVALID;
+<a name="l05076"></a>05076                 val = 0;
+<a name="l05077"></a>05077         }
+<a name="l05078"></a>05078 
+<a name="l05079"></a>05079         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#8787af52f8d70a9100ab1fa2b0f69bfb">ahb_thr_ratio</a> = val;
+<a name="l05080"></a>05080         <span class="keywordflow">return</span> retval;
+<a name="l05081"></a>05081 }
+<a name="l05082"></a><a class="code" href="dwc__otg__core__if_8h.html#275fab9bf16bd3cb148901c578fbcbd0">05082</a> int32_t <a class="code" href="dwc__otg__cil_8c.html#275fab9bf16bd3cb148901c578fbcbd0">dwc_otg_get_param_ahb_thr_ratio</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l05083"></a>05083 {
+<a name="l05084"></a>05084         <span class="keywordflow">return</span> core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#8787af52f8d70a9100ab1fa2b0f69bfb">ahb_thr_ratio</a>;
+<a name="l05085"></a>05085 }
+<a name="l05086"></a>05086 
+<a name="l05087"></a>05087 
+<a name="l05088"></a><a class="code" href="dwc__otg__core__if_8h.html#df391379aafa69a8683bb1f88c413675">05088</a> uint32_t <a class="code" href="dwc__otg__cil_8c.html#df391379aafa69a8683bb1f88c413675">dwc_otg_get_hnpstatus</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l05089"></a>05089 {
+<a name="l05090"></a>05090         <a class="code" href="uniongotgctl__data.html">gotgctl_data_t</a> otgctl;
+<a name="l05091"></a>05091         otgctl.<a class="code" href="uniongotgctl__data.html#ebb591ab40ff41f0e06f03a795647d33">d32</a> = dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#54034d00bb6b47ada4e0c0baa87cbd8a">gotgctl</a>);
+<a name="l05092"></a>05092         <span class="keywordflow">return</span> otgctl.<a class="code" href="uniongotgctl__data.html#212c81366266e906a188f4dbfadb6dd3">b</a>.<a class="code" href="uniongotgctl__data.html#20b17868fc09a12b163732d5bbc84d8d">hstnegscs</a>;
+<a name="l05093"></a>05093 }
+<a name="l05094"></a>05094 
+<a name="l05095"></a><a class="code" href="dwc__otg__core__if_8h.html#b13eac2758aace478587df0f043e80f8">05095</a> uint32_t <a class="code" href="dwc__otg__cil_8c.html#b13eac2758aace478587df0f043e80f8">dwc_otg_get_srpstatus</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l05096"></a>05096 {
+<a name="l05097"></a>05097         <a class="code" href="uniongotgctl__data.html">gotgctl_data_t</a> otgctl;
+<a name="l05098"></a>05098         otgctl.<a class="code" href="uniongotgctl__data.html#ebb591ab40ff41f0e06f03a795647d33">d32</a> = dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#54034d00bb6b47ada4e0c0baa87cbd8a">gotgctl</a>);
+<a name="l05099"></a>05099         <span class="keywordflow">return</span> otgctl.<a class="code" href="uniongotgctl__data.html#212c81366266e906a188f4dbfadb6dd3">b</a>.<a class="code" href="uniongotgctl__data.html#5239dbbb4b31210a35a7104abb688801">sesreqscs</a>;
+<a name="l05100"></a>05100 }
+<a name="l05101"></a>05101 
+<a name="l05102"></a><a class="code" href="dwc__otg__core__if_8h.html#5cab27b65ed5a6a1e31c0e4df1650f0e">05102</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#5cab27b65ed5a6a1e31c0e4df1650f0e">dwc_otg_set_hnpreq</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, uint32_t val)
+<a name="l05103"></a>05103 {
+<a name="l05104"></a>05104         <a class="code" href="uniongotgctl__data.html">gotgctl_data_t</a> otgctl;
+<a name="l05105"></a>05105         otgctl.<a class="code" href="uniongotgctl__data.html#ebb591ab40ff41f0e06f03a795647d33">d32</a> = dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#54034d00bb6b47ada4e0c0baa87cbd8a">gotgctl</a>);
+<a name="l05106"></a>05106         otgctl.<a class="code" href="uniongotgctl__data.html#212c81366266e906a188f4dbfadb6dd3">b</a>.<a class="code" href="uniongotgctl__data.html#08487ecb0860252b73815ee6e0f8eaa3">hnpreq</a> = val;
+<a name="l05107"></a>05107         dwc_write_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#54034d00bb6b47ada4e0c0baa87cbd8a">gotgctl</a>, otgctl.<a class="code" href="uniongotgctl__data.html#ebb591ab40ff41f0e06f03a795647d33">d32</a>);
+<a name="l05108"></a>05108 }
+<a name="l05109"></a>05109 
+<a name="l05110"></a><a class="code" href="dwc__otg__core__if_8h.html#c505c47a08029706f60ab8f3d67b70d3">05110</a> uint32_t <a class="code" href="dwc__otg__cil_8c.html#c505c47a08029706f60ab8f3d67b70d3">dwc_otg_get_gsnpsid</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l05111"></a>05111 {
+<a name="l05112"></a>05112         <span class="keywordflow">return</span> core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#afc495591efa54c74c1dd50278b57ffe">snpsid</a>;
+<a name="l05113"></a>05113 }
+<a name="l05114"></a>05114 
+<a name="l05115"></a><a class="code" href="dwc__otg__core__if_8h.html#788149caf9d915abbe5e289793684b1e">05115</a> uint32_t <a class="code" href="dwc__otg__cil_8c.html#788149caf9d915abbe5e289793684b1e">dwc_otg_get_mode</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l05116"></a>05116 {
+<a name="l05117"></a>05117         <a class="code" href="uniongotgctl__data.html">gotgctl_data_t</a> otgctl;
+<a name="l05118"></a>05118         otgctl.<a class="code" href="uniongotgctl__data.html#ebb591ab40ff41f0e06f03a795647d33">d32</a> = dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#54034d00bb6b47ada4e0c0baa87cbd8a">gotgctl</a>);
+<a name="l05119"></a>05119         <span class="keywordflow">return</span> otgctl.<a class="code" href="uniongotgctl__data.html#212c81366266e906a188f4dbfadb6dd3">b</a>.<a class="code" href="uniongotgctl__data.html#540a9022e5ff38c2a656b8ebd59070cb">currmod</a>;
+<a name="l05120"></a>05120 }
+<a name="l05121"></a>05121 
+<a name="l05122"></a><a class="code" href="dwc__otg__core__if_8h.html#d222e3bdaba5ea8fa0df22ff9cee2f5e">05122</a> uint32_t <a class="code" href="dwc__otg__cil_8c.html#d222e3bdaba5ea8fa0df22ff9cee2f5e">dwc_otg_get_hnpcapable</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l05123"></a>05123 {
+<a name="l05124"></a>05124         <a class="code" href="uniongusbcfg__data.html">gusbcfg_data_t</a> usbcfg;
+<a name="l05125"></a>05125         usbcfg.<a class="code" href="uniongusbcfg__data.html#c3d8f2d95fd61a172eb108cb72a85b47">d32</a> = dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#ef39e181e246447df47c56aa4e37cc42">gusbcfg</a>);
+<a name="l05126"></a>05126         <span class="keywordflow">return</span> usbcfg.<a class="code" href="uniongusbcfg__data.html#1dab81bf7260b1e23f97298c34abea06">b</a>.<a class="code" href="uniongusbcfg__data.html#71b6330c5ccf1d21ebf79a0a829612b5">hnpcap</a>;
+<a name="l05127"></a>05127 }
+<a name="l05128"></a>05128 
+<a name="l05129"></a><a class="code" href="dwc__otg__core__if_8h.html#b9ab6ff4d50ea35738853f831f480c3e">05129</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#b9ab6ff4d50ea35738853f831f480c3e">dwc_otg_set_hnpcapable</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, uint32_t val)
+<a name="l05130"></a>05130 {
+<a name="l05131"></a>05131         <a class="code" href="uniongusbcfg__data.html">gusbcfg_data_t</a> usbcfg;
+<a name="l05132"></a>05132         usbcfg.<a class="code" href="uniongusbcfg__data.html#c3d8f2d95fd61a172eb108cb72a85b47">d32</a> = dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#ef39e181e246447df47c56aa4e37cc42">gusbcfg</a>);
+<a name="l05133"></a>05133         usbcfg.<a class="code" href="uniongusbcfg__data.html#1dab81bf7260b1e23f97298c34abea06">b</a>.<a class="code" href="uniongusbcfg__data.html#71b6330c5ccf1d21ebf79a0a829612b5">hnpcap</a> = val;
+<a name="l05134"></a>05134         dwc_write_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#ef39e181e246447df47c56aa4e37cc42">gusbcfg</a>, usbcfg.<a class="code" href="uniongusbcfg__data.html#c3d8f2d95fd61a172eb108cb72a85b47">d32</a>);
+<a name="l05135"></a>05135 }
+<a name="l05136"></a>05136 
+<a name="l05137"></a><a class="code" href="dwc__otg__core__if_8h.html#2bba47b0255cfbc9b19661e9ddd2f497">05137</a> uint32_t <a class="code" href="dwc__otg__cil_8c.html#2bba47b0255cfbc9b19661e9ddd2f497">dwc_otg_get_srpcapable</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l05138"></a>05138 {
+<a name="l05139"></a>05139         <a class="code" href="uniongusbcfg__data.html">gusbcfg_data_t</a> usbcfg;
+<a name="l05140"></a>05140         usbcfg.<a class="code" href="uniongusbcfg__data.html#c3d8f2d95fd61a172eb108cb72a85b47">d32</a> = dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#ef39e181e246447df47c56aa4e37cc42">gusbcfg</a>);
+<a name="l05141"></a>05141         <span class="keywordflow">return</span> usbcfg.<a class="code" href="uniongusbcfg__data.html#1dab81bf7260b1e23f97298c34abea06">b</a>.<a class="code" href="uniongusbcfg__data.html#44485a787b8a386fadae801869ce7810">srpcap</a>;
+<a name="l05142"></a>05142 }
+<a name="l05143"></a>05143 
+<a name="l05144"></a><a class="code" href="dwc__otg__core__if_8h.html#e75a4faa49ac70c19e9bc8a039d6e37f">05144</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#e75a4faa49ac70c19e9bc8a039d6e37f">dwc_otg_set_srpcapable</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, uint32_t val)
+<a name="l05145"></a>05145 {
+<a name="l05146"></a>05146         <a class="code" href="uniongusbcfg__data.html">gusbcfg_data_t</a> usbcfg;
+<a name="l05147"></a>05147         usbcfg.<a class="code" href="uniongusbcfg__data.html#c3d8f2d95fd61a172eb108cb72a85b47">d32</a> = dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#ef39e181e246447df47c56aa4e37cc42">gusbcfg</a>);
+<a name="l05148"></a>05148         usbcfg.<a class="code" href="uniongusbcfg__data.html#1dab81bf7260b1e23f97298c34abea06">b</a>.<a class="code" href="uniongusbcfg__data.html#44485a787b8a386fadae801869ce7810">srpcap</a> = val;
+<a name="l05149"></a>05149         dwc_write_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#ef39e181e246447df47c56aa4e37cc42">gusbcfg</a>, usbcfg.<a class="code" href="uniongusbcfg__data.html#c3d8f2d95fd61a172eb108cb72a85b47">d32</a>);
+<a name="l05150"></a>05150 }
+<a name="l05151"></a>05151 
+<a name="l05152"></a><a class="code" href="dwc__otg__core__if_8h.html#d69afedd204a41974de582224479569e">05152</a> uint32_t <a class="code" href="dwc__otg__cil_8c.html#d69afedd204a41974de582224479569e">dwc_otg_get_devspeed</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l05153"></a>05153 {
+<a name="l05154"></a>05154         <a class="code" href="uniondcfg__data.html">dcfg_data_t</a> dcfg;
+<a name="l05155"></a>05155         dcfg.<a class="code" href="uniondcfg__data.html#efd84d3306db1b4370535a0e814612dc">d32</a> = dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#c0c24937bbd7184884f05343f56ef1da">dcfg</a>);
+<a name="l05156"></a>05156         <span class="keywordflow">return</span> dcfg.<a class="code" href="uniondcfg__data.html#242c1b463f445de3fc265e8c20fde50b">b</a>.<a class="code" href="uniondcfg__data.html#28ffb9fb43686fe553fbe80f1ead62a4">devspd</a>;
+<a name="l05157"></a>05157 }
+<a name="l05158"></a>05158 
+<a name="l05159"></a><a class="code" href="dwc__otg__core__if_8h.html#ead8dea166cbefca04dc5c543c96fba0">05159</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#ead8dea166cbefca04dc5c543c96fba0">dwc_otg_set_devspeed</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, uint32_t val)
+<a name="l05160"></a>05160 {
+<a name="l05161"></a>05161         <a class="code" href="uniondcfg__data.html">dcfg_data_t</a> dcfg;
+<a name="l05162"></a>05162         dcfg.<a class="code" href="uniondcfg__data.html#efd84d3306db1b4370535a0e814612dc">d32</a> = dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#c0c24937bbd7184884f05343f56ef1da">dcfg</a>);
+<a name="l05163"></a>05163         dcfg.<a class="code" href="uniondcfg__data.html#242c1b463f445de3fc265e8c20fde50b">b</a>.<a class="code" href="uniondcfg__data.html#28ffb9fb43686fe553fbe80f1ead62a4">devspd</a> = val;
+<a name="l05164"></a>05164         dwc_write_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#c0c24937bbd7184884f05343f56ef1da">dcfg</a>, dcfg.<a class="code" href="uniondcfg__data.html#efd84d3306db1b4370535a0e814612dc">d32</a>);
+<a name="l05165"></a>05165 }
+<a name="l05166"></a>05166 
+<a name="l05167"></a><a class="code" href="dwc__otg__core__if_8h.html#07354b164566c5c1c34446d5b0c4036f">05167</a> uint32_t <a class="code" href="dwc__otg__cil_8c.html#07354b164566c5c1c34446d5b0c4036f">dwc_otg_get_busconnected</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l05168"></a>05168 {
+<a name="l05169"></a>05169         <a class="code" href="unionhprt0__data.html">hprt0_data_t</a> hprt0;
+<a name="l05170"></a>05170         hprt0.<a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a> = dwc_read_reg32(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#dc8fe33e0bb3829cafa884d5fc603c4d">hprt0</a>);
+<a name="l05171"></a>05171         <span class="keywordflow">return</span> hprt0.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#39b2dee944be8ec96857a3b43d203390">prtconnsts</a>;
+<a name="l05172"></a>05172 }
+<a name="l05173"></a>05173 
+<a name="l05174"></a><a class="code" href="dwc__otg__core__if_8h.html#520bf6b5f5ec69e5dcbdad6254c3cede">05174</a> uint32_t <a class="code" href="dwc__otg__cil_8c.html#520bf6b5f5ec69e5dcbdad6254c3cede">dwc_otg_get_enumspeed</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l05175"></a>05175 {
+<a name="l05176"></a>05176         <a class="code" href="uniondsts__data.html">dsts_data_t</a> dsts;
+<a name="l05177"></a>05177         dsts.<a class="code" href="uniondsts__data.html#0f126daef735b142b06dbc4cdbe13814">d32</a> = dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#1ed00edd20ce5db7d07666804101ec05">dsts</a>);
+<a name="l05178"></a>05178         <span class="keywordflow">return</span> dsts.<a class="code" href="uniondsts__data.html#4066fcedb7ac9a88e47aa1b2df0e89ee">b</a>.<a class="code" href="uniondsts__data.html#f918f3d04b026687af3e1953f5c79fea">enumspd</a>;
+<a name="l05179"></a>05179 }
+<a name="l05180"></a>05180 
+<a name="l05181"></a><a class="code" href="dwc__otg__core__if_8h.html#83a11dae1c9563aee56baea469cd6064">05181</a> uint32_t <a class="code" href="dwc__otg__cil_8c.html#83a11dae1c9563aee56baea469cd6064">dwc_otg_get_prtpower</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l05182"></a>05182 {
+<a name="l05183"></a>05183         <a class="code" href="unionhprt0__data.html">hprt0_data_t</a> hprt0;
+<a name="l05184"></a>05184         hprt0.<a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a> = dwc_read_reg32(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#dc8fe33e0bb3829cafa884d5fc603c4d">hprt0</a>);
+<a name="l05185"></a>05185         <span class="keywordflow">return</span> hprt0.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#010bd8fb208ef4eeaa288b28f8f8c3a4">prtpwr</a>;
+<a name="l05186"></a>05186 
+<a name="l05187"></a>05187 }
+<a name="l05188"></a>05188 
+<a name="l05189"></a><a class="code" href="dwc__otg__core__if_8h.html#63c880f915b4705a5c118b276e6e9567">05189</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#63c880f915b4705a5c118b276e6e9567">dwc_otg_set_prtpower</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, uint32_t val)
+<a name="l05190"></a>05190 {
+<a name="l05191"></a>05191         <a class="code" href="unionhprt0__data.html">hprt0_data_t</a> hprt0;
+<a name="l05192"></a>05192         hprt0.<a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a> = dwc_read_reg32(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#dc8fe33e0bb3829cafa884d5fc603c4d">hprt0</a>);
+<a name="l05193"></a>05193         hprt0.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#010bd8fb208ef4eeaa288b28f8f8c3a4">prtpwr</a> = val;
+<a name="l05194"></a>05194         dwc_write_reg32(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#dc8fe33e0bb3829cafa884d5fc603c4d">hprt0</a>, val);
+<a name="l05195"></a>05195 }
+<a name="l05196"></a>05196 
+<a name="l05197"></a><a class="code" href="dwc__otg__core__if_8h.html#65b0861f7d5d604fb97e599adac62642">05197</a> uint32_t <a class="code" href="dwc__otg__cil_8c.html#65b0861f7d5d604fb97e599adac62642">dwc_otg_get_prtsuspend</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l05198"></a>05198 {
+<a name="l05199"></a>05199         <a class="code" href="unionhprt0__data.html">hprt0_data_t</a> hprt0;
+<a name="l05200"></a>05200         hprt0.<a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a> = dwc_read_reg32(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#dc8fe33e0bb3829cafa884d5fc603c4d">hprt0</a>);
+<a name="l05201"></a>05201         <span class="keywordflow">return</span> hprt0.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#e7fe71d6c465ae002211c24a6ba359d2">prtsusp</a>;
+<a name="l05202"></a>05202 
+<a name="l05203"></a>05203 }
+<a name="l05204"></a>05204 
+<a name="l05205"></a><a class="code" href="dwc__otg__core__if_8h.html#c072cef5b7d3c5566ad3be010c6d49ed">05205</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#c072cef5b7d3c5566ad3be010c6d49ed">dwc_otg_set_prtsuspend</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, uint32_t val)
+<a name="l05206"></a>05206 {
+<a name="l05207"></a>05207         <a class="code" href="unionhprt0__data.html">hprt0_data_t</a> hprt0;
+<a name="l05208"></a>05208         hprt0.<a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a> = dwc_read_reg32(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#dc8fe33e0bb3829cafa884d5fc603c4d">hprt0</a>);
+<a name="l05209"></a>05209         hprt0.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#e7fe71d6c465ae002211c24a6ba359d2">prtsusp</a> = val;
+<a name="l05210"></a>05210         dwc_write_reg32(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#dc8fe33e0bb3829cafa884d5fc603c4d">hprt0</a>, val);
+<a name="l05211"></a>05211 }
+<a name="l05212"></a>05212 
+<a name="l05213"></a><a class="code" href="dwc__otg__core__if_8h.html#b6d6b18934ba5cd4ce2cf9e68be338f5">05213</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#b6d6b18934ba5cd4ce2cf9e68be338f5">dwc_otg_set_prtresume</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, uint32_t val)
+<a name="l05214"></a>05214 {
+<a name="l05215"></a>05215         <a class="code" href="unionhprt0__data.html">hprt0_data_t</a> hprt0;
+<a name="l05216"></a>05216         hprt0.<a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a> = dwc_read_reg32(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#dc8fe33e0bb3829cafa884d5fc603c4d">hprt0</a>);
+<a name="l05217"></a>05217         hprt0.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#3f5961529636a3891a4ca9421dd535fa">prtres</a> = val;
+<a name="l05218"></a>05218         dwc_write_reg32(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#dc8fe33e0bb3829cafa884d5fc603c4d">hprt0</a>, val);
+<a name="l05219"></a>05219 }
+<a name="l05220"></a>05220 
+<a name="l05221"></a><a class="code" href="dwc__otg__core__if_8h.html#285696198299e317222544aa912b2c35">05221</a> uint32_t <a class="code" href="dwc__otg__cil_8c.html#285696198299e317222544aa912b2c35">dwc_otg_get_remotewakesig</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l05222"></a>05222 {
+<a name="l05223"></a>05223         <a class="code" href="uniondctl__data.html">dctl_data_t</a> dctl;
+<a name="l05224"></a>05224         dctl.<a class="code" href="uniondctl__data.html#f49aadfd7ad95b570115b3c245b1729e">d32</a> = dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#3779c2fc508920a831a59e696a8fa785">dctl</a>);
+<a name="l05225"></a>05225         <span class="keywordflow">return</span> dctl.<a class="code" href="uniondctl__data.html#a3abfa6d609d9864f1f65712b409d4d3">b</a>.<a class="code" href="uniondctl__data.html#dcae5af28dc159cd7ba85a9a2b8be51a">rmtwkupsig</a>;
+<a name="l05226"></a>05226 }
+<a name="l05227"></a>05227 
+<a name="l05228"></a><a class="code" href="dwc__otg__core__if_8h.html#87d643973839554bac437d283a462e00">05228</a> uint32_t <a class="code" href="dwc__otg__cil_8c.html#87d643973839554bac437d283a462e00">dwc_otg_get_lpm_portsleepstatus</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l05229"></a>05229 {
+<a name="l05230"></a>05230         <a class="code" href="unionglpmctl__data.html">glpmcfg_data_t</a> lpmcfg;
+<a name="l05231"></a>05231         lpmcfg.<a class="code" href="unionglpmctl__data.html#cd41461734ff898209bfb64057ef2eb8">d32</a> = dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#843cfb38ba366a9a46ad07ed11eb8396">glpmcfg</a>);
+<a name="l05232"></a>05232 
+<a name="l05233"></a>05233         DWC_ASSERT(!
+<a name="l05234"></a>05234                    ((core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#2b0701d814069ec69897e08374366c7b">lx_state</a> == <a class="code" href="dwc__otg__cil_8h.html#8442e49b7c783099ac17bda4f8b3bc3cf5b112742a8103f3489107ad26c0ff58">DWC_OTG_L1</a>) ^ lpmcfg.<a class="code" href="unionglpmctl__data.html#bd3cc34c338226ff1cd89448f7590ff1">b</a>.<a class="code" href="unionglpmctl__data.html#241ff25a215f16ac29b3bb6d9f4943ed">prt_sleep_sts</a>),
+<a name="l05235"></a>05235                    <span class="stringliteral">"lx_state = %d, lmpcfg.prt_sleep_sts = %d\n"</span>,
+<a name="l05236"></a>05236                    core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#2b0701d814069ec69897e08374366c7b">lx_state</a>, lpmcfg.<a class="code" href="unionglpmctl__data.html#bd3cc34c338226ff1cd89448f7590ff1">b</a>.<a class="code" href="unionglpmctl__data.html#241ff25a215f16ac29b3bb6d9f4943ed">prt_sleep_sts</a>);
+<a name="l05237"></a>05237 
+<a name="l05238"></a>05238         <span class="keywordflow">return</span> lpmcfg.<a class="code" href="unionglpmctl__data.html#bd3cc34c338226ff1cd89448f7590ff1">b</a>.<a class="code" href="unionglpmctl__data.html#241ff25a215f16ac29b3bb6d9f4943ed">prt_sleep_sts</a>;
+<a name="l05239"></a>05239 }
+<a name="l05240"></a>05240 
+<a name="l05241"></a><a class="code" href="dwc__otg__core__if_8h.html#91d2a6b57c7216fd5c6dc981a5f0e1ae">05241</a> uint32_t <a class="code" href="dwc__otg__cil_8c.html#91d2a6b57c7216fd5c6dc981a5f0e1ae">dwc_otg_get_lpm_remotewakeenabled</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l05242"></a>05242 {
+<a name="l05243"></a>05243         <a class="code" href="unionglpmctl__data.html">glpmcfg_data_t</a> lpmcfg;
+<a name="l05244"></a>05244         lpmcfg.<a class="code" href="unionglpmctl__data.html#cd41461734ff898209bfb64057ef2eb8">d32</a> = dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#843cfb38ba366a9a46ad07ed11eb8396">glpmcfg</a>);
+<a name="l05245"></a>05245         <span class="keywordflow">return</span> lpmcfg.<a class="code" href="unionglpmctl__data.html#bd3cc34c338226ff1cd89448f7590ff1">b</a>.<a class="code" href="unionglpmctl__data.html#60a9c2e233e3ee15a80ae80b27d09f8b">rem_wkup_en</a>;
+<a name="l05246"></a>05246 }
+<a name="l05247"></a>05247 
+<a name="l05248"></a><a class="code" href="dwc__otg__core__if_8h.html#86d921a91b7e2b143a305283282ce36d">05248</a> uint32_t <a class="code" href="dwc__otg__cil_8c.html#86d921a91b7e2b143a305283282ce36d">dwc_otg_get_lpmresponse</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l05249"></a>05249 {
+<a name="l05250"></a>05250         <a class="code" href="unionglpmctl__data.html">glpmcfg_data_t</a> lpmcfg;
+<a name="l05251"></a>05251         lpmcfg.<a class="code" href="unionglpmctl__data.html#cd41461734ff898209bfb64057ef2eb8">d32</a> = dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#843cfb38ba366a9a46ad07ed11eb8396">glpmcfg</a>);
+<a name="l05252"></a>05252         <span class="keywordflow">return</span> lpmcfg.<a class="code" href="unionglpmctl__data.html#bd3cc34c338226ff1cd89448f7590ff1">b</a>.<a class="code" href="unionglpmctl__data.html#1898203022af680f08036de89e86e4b0">appl_resp</a>;
+<a name="l05253"></a>05253 }
+<a name="l05254"></a>05254 
+<a name="l05255"></a><a class="code" href="dwc__otg__core__if_8h.html#b19565bc2a8dbb258c3c2cb8c52240b8">05255</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#b19565bc2a8dbb258c3c2cb8c52240b8">dwc_otg_set_lpmresponse</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, uint32_t val)
+<a name="l05256"></a>05256 {
+<a name="l05257"></a>05257         <a class="code" href="unionglpmctl__data.html">glpmcfg_data_t</a> lpmcfg;
+<a name="l05258"></a>05258         lpmcfg.<a class="code" href="unionglpmctl__data.html#cd41461734ff898209bfb64057ef2eb8">d32</a> = dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#843cfb38ba366a9a46ad07ed11eb8396">glpmcfg</a>);
+<a name="l05259"></a>05259         lpmcfg.<a class="code" href="unionglpmctl__data.html#bd3cc34c338226ff1cd89448f7590ff1">b</a>.<a class="code" href="unionglpmctl__data.html#1898203022af680f08036de89e86e4b0">appl_resp</a> = val;
+<a name="l05260"></a>05260         dwc_write_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#843cfb38ba366a9a46ad07ed11eb8396">glpmcfg</a>, lpmcfg.<a class="code" href="unionglpmctl__data.html#cd41461734ff898209bfb64057ef2eb8">d32</a>);
+<a name="l05261"></a>05261 }
+<a name="l05262"></a>05262 
+<a name="l05263"></a><a class="code" href="dwc__otg__core__if_8h.html#0fb8a2b51041b2f5476abc8ffbcc46cb">05263</a> uint32_t <a class="code" href="dwc__otg__cil_8c.html#0fb8a2b51041b2f5476abc8ffbcc46cb">dwc_otg_get_hsic_connect</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l05264"></a>05264 {
+<a name="l05265"></a>05265         <a class="code" href="unionglpmctl__data.html">glpmcfg_data_t</a> lpmcfg;
+<a name="l05266"></a>05266         lpmcfg.<a class="code" href="unionglpmctl__data.html#cd41461734ff898209bfb64057ef2eb8">d32</a> = dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#843cfb38ba366a9a46ad07ed11eb8396">glpmcfg</a>);
+<a name="l05267"></a>05267         <span class="keywordflow">return</span> lpmcfg.<a class="code" href="unionglpmctl__data.html#bd3cc34c338226ff1cd89448f7590ff1">b</a>.<a class="code" href="unionglpmctl__data.html#76c64ead46647c39aa76edebf2f63444">hsic_connect</a>;
+<a name="l05268"></a>05268 }
+<a name="l05269"></a>05269 
+<a name="l05270"></a><a class="code" href="dwc__otg__core__if_8h.html#6625bea93daab21b2a97004f743203f9">05270</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#6625bea93daab21b2a97004f743203f9">dwc_otg_set_hsic_connect</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, uint32_t val)
+<a name="l05271"></a>05271 {
+<a name="l05272"></a>05272         <a class="code" href="unionglpmctl__data.html">glpmcfg_data_t</a> lpmcfg;
+<a name="l05273"></a>05273         lpmcfg.<a class="code" href="unionglpmctl__data.html#cd41461734ff898209bfb64057ef2eb8">d32</a> = dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#843cfb38ba366a9a46ad07ed11eb8396">glpmcfg</a>);
+<a name="l05274"></a>05274         lpmcfg.<a class="code" href="unionglpmctl__data.html#bd3cc34c338226ff1cd89448f7590ff1">b</a>.<a class="code" href="unionglpmctl__data.html#76c64ead46647c39aa76edebf2f63444">hsic_connect</a> = val;
+<a name="l05275"></a>05275         dwc_write_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#843cfb38ba366a9a46ad07ed11eb8396">glpmcfg</a>, lpmcfg.<a class="code" href="unionglpmctl__data.html#cd41461734ff898209bfb64057ef2eb8">d32</a>);
+<a name="l05276"></a>05276 }
+<a name="l05277"></a>05277 
+<a name="l05278"></a><a class="code" href="dwc__otg__core__if_8h.html#a3399019a62013ccc6ce213e8f241d7a">05278</a> uint32_t <a class="code" href="dwc__otg__cil_8c.html#a3399019a62013ccc6ce213e8f241d7a">dwc_otg_get_inv_sel_hsic</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l05279"></a>05279 {
+<a name="l05280"></a>05280         <a class="code" href="unionglpmctl__data.html">glpmcfg_data_t</a> lpmcfg;
+<a name="l05281"></a>05281         lpmcfg.<a class="code" href="unionglpmctl__data.html#cd41461734ff898209bfb64057ef2eb8">d32</a> = dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#843cfb38ba366a9a46ad07ed11eb8396">glpmcfg</a>);
+<a name="l05282"></a>05282         <span class="keywordflow">return</span> lpmcfg.<a class="code" href="unionglpmctl__data.html#bd3cc34c338226ff1cd89448f7590ff1">b</a>.<a class="code" href="unionglpmctl__data.html#f664636955d9476647937d13d48f068e">inv_sel_hsic</a>;
+<a name="l05283"></a>05283 
+<a name="l05284"></a>05284 }
+<a name="l05285"></a>05285 
+<a name="l05286"></a><a class="code" href="dwc__otg__core__if_8h.html#ef8b7bbc803e779480aa06779a44e4f0">05286</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#ef8b7bbc803e779480aa06779a44e4f0">dwc_otg_set_inv_sel_hsic</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, uint32_t val)
+<a name="l05287"></a>05287 {
+<a name="l05288"></a>05288         <a class="code" href="unionglpmctl__data.html">glpmcfg_data_t</a> lpmcfg;
+<a name="l05289"></a>05289         lpmcfg.<a class="code" href="unionglpmctl__data.html#cd41461734ff898209bfb64057ef2eb8">d32</a> = dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#843cfb38ba366a9a46ad07ed11eb8396">glpmcfg</a>);
+<a name="l05290"></a>05290         lpmcfg.<a class="code" href="unionglpmctl__data.html#bd3cc34c338226ff1cd89448f7590ff1">b</a>.<a class="code" href="unionglpmctl__data.html#f664636955d9476647937d13d48f068e">inv_sel_hsic</a> = val;
+<a name="l05291"></a>05291         dwc_write_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#843cfb38ba366a9a46ad07ed11eb8396">glpmcfg</a>, lpmcfg.<a class="code" href="unionglpmctl__data.html#cd41461734ff898209bfb64057ef2eb8">d32</a>);
+<a name="l05292"></a>05292 }
+<a name="l05293"></a>05293 
+<a name="l05294"></a><a class="code" href="dwc__otg__core__if_8h.html#a450da19279ae7246c89ede2949189fe">05294</a> uint32_t <a class="code" href="dwc__otg__cil_8c.html#a450da19279ae7246c89ede2949189fe">dwc_otg_get_gotgctl</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l05295"></a>05295 {
+<a name="l05296"></a>05296         <span class="keywordflow">return</span> dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#54034d00bb6b47ada4e0c0baa87cbd8a">gotgctl</a>);
+<a name="l05297"></a>05297 }
+<a name="l05298"></a>05298 
+<a name="l05299"></a><a class="code" href="dwc__otg__core__if_8h.html#be44aee1ee301bdcbf7174cc1c729032">05299</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#be44aee1ee301bdcbf7174cc1c729032">dwc_otg_set_gotgctl</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, uint32_t val)
+<a name="l05300"></a>05300 {
+<a name="l05301"></a>05301         dwc_write_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#54034d00bb6b47ada4e0c0baa87cbd8a">gotgctl</a>, val);
+<a name="l05302"></a>05302 }
+<a name="l05303"></a>05303 
+<a name="l05304"></a><a class="code" href="dwc__otg__core__if_8h.html#eb5b1512f29fa951f2875dc52d368085">05304</a> uint32_t <a class="code" href="dwc__otg__cil_8c.html#eb5b1512f29fa951f2875dc52d368085">dwc_otg_get_gusbcfg</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l05305"></a>05305 {
+<a name="l05306"></a>05306         <span class="keywordflow">return</span> dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#ef39e181e246447df47c56aa4e37cc42">gusbcfg</a>);
+<a name="l05307"></a>05307 }
+<a name="l05308"></a>05308 
+<a name="l05309"></a><a class="code" href="dwc__otg__core__if_8h.html#74d5e1045c70fd5efc35a39ca4311baa">05309</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#74d5e1045c70fd5efc35a39ca4311baa">dwc_otg_set_gusbcfg</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, uint32_t val)
+<a name="l05310"></a>05310 {
+<a name="l05311"></a>05311         dwc_write_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#ef39e181e246447df47c56aa4e37cc42">gusbcfg</a>, val);
+<a name="l05312"></a>05312 }
+<a name="l05313"></a>05313 
+<a name="l05314"></a><a class="code" href="dwc__otg__core__if_8h.html#ce6ba769b9c0abd15c8f0b118d74c8e4">05314</a> uint32_t <a class="code" href="dwc__otg__cil_8c.html#ce6ba769b9c0abd15c8f0b118d74c8e4">dwc_otg_get_grxfsiz</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l05315"></a>05315 {
+<a name="l05316"></a>05316         <span class="keywordflow">return</span> dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#b1a8cc07a9541c9a73e864579602b79b">grxfsiz</a>);
+<a name="l05317"></a>05317 }
+<a name="l05318"></a>05318 
+<a name="l05319"></a><a class="code" href="dwc__otg__core__if_8h.html#3e251d5b9273ae2e2b3f5714694974a5">05319</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#3e251d5b9273ae2e2b3f5714694974a5">dwc_otg_set_grxfsiz</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, uint32_t val)
+<a name="l05320"></a>05320 {
+<a name="l05321"></a>05321         dwc_write_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#b1a8cc07a9541c9a73e864579602b79b">grxfsiz</a>, val);
+<a name="l05322"></a>05322 }
+<a name="l05323"></a>05323 
+<a name="l05324"></a><a class="code" href="dwc__otg__core__if_8h.html#3110e552598b04bbe6b30bcddadda98b">05324</a> uint32_t <a class="code" href="dwc__otg__cil_8c.html#3110e552598b04bbe6b30bcddadda98b">dwc_otg_get_gnptxfsiz</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l05325"></a>05325 {
+<a name="l05326"></a>05326         <span class="keywordflow">return</span> dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#20fb70fe34a1a65d085b1d4e5f8d9106">gnptxfsiz</a>);
+<a name="l05327"></a>05327 }
+<a name="l05328"></a>05328 
+<a name="l05329"></a><a class="code" href="dwc__otg__core__if_8h.html#48c625d569671523aac60af8e2d60d7a">05329</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#48c625d569671523aac60af8e2d60d7a">dwc_otg_set_gnptxfsiz</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, uint32_t val)
+<a name="l05330"></a>05330 {
+<a name="l05331"></a>05331         dwc_write_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#20fb70fe34a1a65d085b1d4e5f8d9106">gnptxfsiz</a>, val);
+<a name="l05332"></a>05332 }
+<a name="l05333"></a>05333 
+<a name="l05334"></a><a class="code" href="dwc__otg__core__if_8h.html#c8fcf302be26cad07b9ba36082e0ed5c">05334</a> uint32_t <a class="code" href="dwc__otg__cil_8c.html#c8fcf302be26cad07b9ba36082e0ed5c">dwc_otg_get_gpvndctl</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l05335"></a>05335 {
+<a name="l05336"></a>05336         <span class="keywordflow">return</span> dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#a12db668367caef8386d2ba20289e437">gpvndctl</a>);
+<a name="l05337"></a>05337 }
+<a name="l05338"></a>05338 
+<a name="l05339"></a><a class="code" href="dwc__otg__core__if_8h.html#4c700540a6c1061eb2491c78670bb26f">05339</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#4c700540a6c1061eb2491c78670bb26f">dwc_otg_set_gpvndctl</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, uint32_t val)
+<a name="l05340"></a>05340 {
+<a name="l05341"></a>05341         dwc_write_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#a12db668367caef8386d2ba20289e437">gpvndctl</a>, val);
+<a name="l05342"></a>05342 }
+<a name="l05343"></a>05343 
+<a name="l05344"></a><a class="code" href="dwc__otg__core__if_8h.html#5b3367179e8c0c6ccb5041db26f8e0cc">05344</a> uint32_t <a class="code" href="dwc__otg__cil_8c.html#5b3367179e8c0c6ccb5041db26f8e0cc">dwc_otg_get_ggpio</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l05345"></a>05345 {
+<a name="l05346"></a>05346         <span class="keywordflow">return</span> dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#694546400c443d41b449772c8573f3e8">ggpio</a>);
+<a name="l05347"></a>05347 }
+<a name="l05348"></a>05348 
+<a name="l05349"></a><a class="code" href="dwc__otg__core__if_8h.html#4b6bd4ddf333b856631cd561eb747882">05349</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#4b6bd4ddf333b856631cd561eb747882">dwc_otg_set_ggpio</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, uint32_t val)
+<a name="l05350"></a>05350 {
+<a name="l05351"></a>05351         dwc_write_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#694546400c443d41b449772c8573f3e8">ggpio</a>, val);
+<a name="l05352"></a>05352 }
+<a name="l05353"></a>05353 
+<a name="l05354"></a><a class="code" href="dwc__otg__core__if_8h.html#6345490821a039a5eff6ec8e5c0e8c0b">05354</a> uint32_t <a class="code" href="dwc__otg__cil_8c.html#6345490821a039a5eff6ec8e5c0e8c0b">dwc_otg_get_hprt0</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l05355"></a>05355 {
+<a name="l05356"></a>05356         <span class="keywordflow">return</span> dwc_read_reg32(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#dc8fe33e0bb3829cafa884d5fc603c4d">hprt0</a>);
+<a name="l05357"></a>05357 
+<a name="l05358"></a>05358 }
+<a name="l05359"></a>05359 
+<a name="l05360"></a><a class="code" href="dwc__otg__core__if_8h.html#c2ec55794abeeb14f5b4d00613122bb7">05360</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#c2ec55794abeeb14f5b4d00613122bb7">dwc_otg_set_hprt0</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, uint32_t val)
+<a name="l05361"></a>05361 {
+<a name="l05362"></a>05362         dwc_write_reg32(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#dc8fe33e0bb3829cafa884d5fc603c4d">hprt0</a>, val);
+<a name="l05363"></a>05363 }
+<a name="l05364"></a>05364 
+<a name="l05365"></a><a class="code" href="dwc__otg__core__if_8h.html#c308abdec734a3d2f183d2085271d285">05365</a> uint32_t <a class="code" href="dwc__otg__cil_8c.html#c308abdec734a3d2f183d2085271d285">dwc_otg_get_guid</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l05366"></a>05366 {
+<a name="l05367"></a>05367         <span class="keywordflow">return</span> dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#8735ca2e93c1e984ac2d5bcf0cda96d7">guid</a>);
+<a name="l05368"></a>05368 }
+<a name="l05369"></a>05369 
+<a name="l05370"></a><a class="code" href="dwc__otg__core__if_8h.html#edf22163b21a9ab3539976e19338f1e9">05370</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#edf22163b21a9ab3539976e19338f1e9">dwc_otg_set_guid</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, uint32_t val)
+<a name="l05371"></a>05371 {
+<a name="l05372"></a>05372         dwc_write_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#8735ca2e93c1e984ac2d5bcf0cda96d7">guid</a>, val);
+<a name="l05373"></a>05373 }
+<a name="l05374"></a>05374 
+<a name="l05375"></a><a class="code" href="dwc__otg__core__if_8h.html#6180fa187cfbeef487a71fb4f72a6381">05375</a> uint32_t <a class="code" href="dwc__otg__cil_8c.html#6180fa187cfbeef487a71fb4f72a6381">dwc_otg_get_hptxfsiz</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l05376"></a>05376 {
+<a name="l05377"></a>05377         <span class="keywordflow">return</span> dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#94ae41f04d5a4244a8ebc23e51187e96">hptxfsiz</a>);
+<a name="l05378"></a>05378 }
+</pre></div><hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil_8c.html b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil_8c.html
new file mode 100644
index 000000000000..38aba4b62294
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil_8c.html
@@ -0,0 +1,3103 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_cil.c File Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<h1>dwc_otg_cil.c File Reference</h1>The Core Interface Layer provides basic services for accessing and managing the DWC_otg hardware. <a href="#_details">More...</a>
+<p>
+<code>#include &quot;dwc_os.h&quot;</code><br>
+<code>#include &quot;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&quot;</code><br>
+<code>#include &quot;<a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a>&quot;</code><br>
+
+<p>
+<a href="dwc__otg__cil_8c-source.html">Go to the source code of this file.</a><table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Defines</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#c4138a87302505f6ef79dc3bfb4951c0">DWC_OTG_PARAM_TEST</a>(_param_, _low_, _high_)</td></tr>
+
+<tr><td colspan="2"><br><h2>Functions</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="2be12d7b5990c6eaac2f1a5fb688f2f8"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_setup_params" ref="2be12d7b5990c6eaac2f1a5fb688f2f8" args="(dwc_otg_core_if_t *core_if)" -->
+static int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#2be12d7b5990c6eaac2f1a5fb688f2f8">dwc_otg_setup_params</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#2dc0a6c5541c1a8a014d66a8fce53f66">dwc_otg_cil_init</a> (const uint32_t *reg_base_addr)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function is called to initialize the DWC_otg CSR data structures.  <a href="#2dc0a6c5541c1a8a014d66a8fce53f66"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#cc4a08b278c7afe0484b595cacf80c04">dwc_otg_cil_remove</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function frees the structures allocated by <a class="el" href="dwc__otg__cil_8c.html#2dc0a6c5541c1a8a014d66a8fce53f66">dwc_otg_cil_init()</a>.  <a href="#cc4a08b278c7afe0484b595cacf80c04"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#8b0b841d69298089b7d03b07ade8eda6">dwc_otg_enable_global_interrupts</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function enables the controller's Global Interrupt in the AHB Config register.  <a href="#8b0b841d69298089b7d03b07ade8eda6"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#9f673c38ca761d8ab7b3333b506bcbfc">dwc_otg_disable_global_interrupts</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function disables the controller's Global Interrupt in the AHB Config register.  <a href="#9f673c38ca761d8ab7b3333b506bcbfc"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#1761ac95e17bad3fa304413cc81c51de">dwc_otg_enable_common_interrupts</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function initializes the commmon interrupts, used in both device and host modes.  <a href="#1761ac95e17bad3fa304413cc81c51de"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="4550564b18dcd56bd2c4ec1ba91c6e13"></a><!-- doxytag: member="dwc_otg_cil.c::init_fslspclksel" ref="4550564b18dcd56bd2c4ec1ba91c6e13" args="(dwc_otg_core_if_t *core_if)" -->
+static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#4550564b18dcd56bd2c4ec1ba91c6e13">init_fslspclksel</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Initializes the FSLSPClkSel field of the HCFG register depending on the PHY type. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="6ef971c486eacd419d20e1bc545f9238"></a><!-- doxytag: member="dwc_otg_cil.c::init_devspd" ref="6ef971c486eacd419d20e1bc545f9238" args="(dwc_otg_core_if_t *core_if)" -->
+static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#6ef971c486eacd419d20e1bc545f9238">init_devspd</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Initializes the DevSpd field of the DCFG register depending on the PHY type and the enumeration speed of the device. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#1cdde3ab3e53e93c5a42feed628aaf7d">calc_num_in_eps</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function calculates the number of IN EPS using GHWCFG1 and GHWCFG2 registers values.  <a href="#1cdde3ab3e53e93c5a42feed628aaf7d"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#e923d8ecfaf2957ef7d0a1379e0b5101">calc_num_out_eps</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function calculates the number of OUT EPS using GHWCFG1 and GHWCFG2 registers values.  <a href="#e923d8ecfaf2957ef7d0a1379e0b5101"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#ce48d4f2d172600c325a82d793473d0f">dwc_otg_core_init</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function initializes the DWC_otg controller registers and prepares the core for device mode or host mode operation.  <a href="#ce48d4f2d172600c325a82d793473d0f"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#3d60e58f32be881047ac61bc852f60f7">dwc_otg_enable_device_interrupts</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function enables the Device mode interrupts.  <a href="#3d60e58f32be881047ac61bc852f60f7"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#f79b0f3b5b96b0535e33627ee3a66eba">dwc_otg_core_dev_init</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function initializes the DWC_otg controller registers for device mode.  <a href="#f79b0f3b5b96b0535e33627ee3a66eba"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#373701240c023fda03eed98cf093df74">dwc_otg_enable_host_interrupts</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function enables the Host mode interrupts.  <a href="#373701240c023fda03eed98cf093df74"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#4dd4a30dd75a819e9da38d6410cbb0a4">dwc_otg_disable_host_interrupts</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function disables the Host Mode interrupts.  <a href="#4dd4a30dd75a819e9da38d6410cbb0a4"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#04ad276f20faad71333f6293c952744e">dwc_otg_core_host_init</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function initializes the DWC_otg controller registers for host mode.  <a href="#04ad276f20faad71333f6293c952744e"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#7b04d5b3b31c79c73d577cfbb231998c">dwc_otg_hc_init</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, <a class="el" href="structdwc__hc.html">dwc_hc_t</a> *hc)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Prepares a host channel for transferring packets to/from a specific endpoint.  <a href="#7b04d5b3b31c79c73d577cfbb231998c"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#de044bf6b96c1bac92259a447ae85c0f">dwc_otg_hc_halt</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, <a class="el" href="structdwc__hc.html">dwc_hc_t</a> *hc, dwc_otg_halt_status_e halt_status)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Attempts to halt a host channel.  <a href="#de044bf6b96c1bac92259a447ae85c0f"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#f05341f811fba7f6183db66faf50a867">dwc_otg_hc_cleanup</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, <a class="el" href="structdwc__hc.html">dwc_hc_t</a> *hc)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Clears the transfer state for a host channel.  <a href="#f05341f811fba7f6183db66faf50a867"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#b2669551136671d3e4b6ad56bd947222">hc_set_even_odd_frame</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, <a class="el" href="structdwc__hc.html">dwc_hc_t</a> *hc, <a class="el" href="unionhcchar__data.html">hcchar_data_t</a> *hcchar)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Sets the channel property that indicates in which frame a periodic transfer should occur.  <a href="#b2669551136671d3e4b6ad56bd947222"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="bf1f2e3a039a78f9cc51c8223c40d8e1"></a><!-- doxytag: member="dwc_otg_cil.c::set_pid_isoc" ref="bf1f2e3a039a78f9cc51c8223c40d8e1" args="(dwc_hc_t *hc)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#bf1f2e3a039a78f9cc51c8223c40d8e1">set_pid_isoc</a> (<a class="el" href="structdwc__hc.html">dwc_hc_t</a> *hc)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#025af79d6a2255dba4578588be510444">dwc_otg_hc_start_transfer</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, <a class="el" href="structdwc__hc.html">dwc_hc_t</a> *hc)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function does the setup for a data transfer for a host channel and starts the transfer.  <a href="#025af79d6a2255dba4578588be510444"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#dbc20e9f9cadbdf4df65db3f82bbb820">dwc_otg_hc_start_transfer_ddma</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, <a class="el" href="structdwc__hc.html">dwc_hc_t</a> *hc)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function does the setup for a data transfer for a host channel and starts the transfer in Descriptor DMA mode.  <a href="#dbc20e9f9cadbdf4df65db3f82bbb820"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#d848c41cdd739edd9271e1e207af9c9c">dwc_otg_hc_continue_transfer</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, <a class="el" href="structdwc__hc.html">dwc_hc_t</a> *hc)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function continues a data transfer that was started by previous call to <code>dwc_otg_hc_start_transfer</code>.  <a href="#d848c41cdd739edd9271e1e207af9c9c"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#4185d0b9bb4a49d28894f957c2e41117">dwc_otg_hc_do_ping</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, <a class="el" href="structdwc__hc.html">dwc_hc_t</a> *hc)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Starts a PING transfer.  <a href="#4185d0b9bb4a49d28894f957c2e41117"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c4ccce95ab4067e03c089519c1b54a94"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_hc_write_packet" ref="c4ccce95ab4067e03c089519c1b54a94" args="(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#c4ccce95ab4067e03c089519c1b54a94">dwc_otg_hc_write_packet</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, <a class="el" href="structdwc__hc.html">dwc_hc_t</a> *hc)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#78f20f3acf6245b189abde83d9ce78f2">dwc_otg_get_frame_number</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Gets the current USB frame number.  <a href="#78f20f3acf6245b189abde83d9ce78f2"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#b56e0d90c67bbf2829e630cafd630f17">dwc_otg_read_setup_packet</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, uint32_t *dest)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function reads a setup packet from the Rx FIFO into the destination buffer.  <a href="#b56e0d90c67bbf2829e630cafd630f17"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#8ebf5023c783a2ec48a18a5b9aef4a87">dwc_otg_ep0_activate</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, <a class="el" href="structdwc__ep.html">dwc_ep_t</a> *ep)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function enables EP0 OUT to receive SETUP packets and configures EP0 IN for transmitting packets.  <a href="#8ebf5023c783a2ec48a18a5b9aef4a87"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#5e5a1fb1ff70d5c42d8cf4a1c5d12b7f">dwc_otg_ep_activate</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, <a class="el" href="structdwc__ep.html">dwc_ep_t</a> *ep)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function activates an EP.  <a href="#5e5a1fb1ff70d5c42d8cf4a1c5d12b7f"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#94789f2d72adb5daf65c99eadced66b3">dwc_otg_ep_deactivate</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, <a class="el" href="structdwc__ep.html">dwc_ep_t</a> *ep)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function deactivates an EP.  <a href="#94789f2d72adb5daf65c99eadced66b3"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#50a39773d3477ca76a71787e27400d7a">init_dma_desc_chain</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, <a class="el" href="structdwc__ep.html">dwc_ep_t</a> *ep)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function initializes dma descriptor chain.  <a href="#50a39773d3477ca76a71787e27400d7a"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#1278f6d58a4a2bc780e90e0b6c9b9a68">dwc_otg_ep_start_transfer</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, <a class="el" href="structdwc__ep.html">dwc_ep_t</a> *ep)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function does the setup for a data transfer for an EP and starts the transfer.  <a href="#1278f6d58a4a2bc780e90e0b6c9b9a68"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#fcc9f9b12c040c3649f0b8273a24ddf7">dwc_otg_ep_start_zl_transfer</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, <a class="el" href="structdwc__ep.html">dwc_ep_t</a> *ep)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function setup a zero length transfer in Buffer DMA and Slave modes for usb requests with zero field set.  <a href="#fcc9f9b12c040c3649f0b8273a24ddf7"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#ee4989b24826b2a6592535282853e556">dwc_otg_ep0_start_transfer</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, <a class="el" href="structdwc__ep.html">dwc_ep_t</a> *ep)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function does the setup for a data transfer for EP0 and starts the transfer.  <a href="#ee4989b24826b2a6592535282853e556"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#d8c1e6f7860c482df84db003b52c369c">dwc_otg_ep0_continue_transfer</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, <a class="el" href="structdwc__ep.html">dwc_ep_t</a> *ep)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function continues control IN transfers started by dwc_otg_ep0_start_transfer, when the transfer does not fit in a single packet.  <a href="#d8c1e6f7860c482df84db003b52c369c"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="8d8df6d136115ec977eb6bf20148547a"></a><!-- doxytag: member="dwc_otg_cil.c::dump_msg" ref="8d8df6d136115ec977eb6bf20148547a" args="(const u8 *buf, unsigned int length)" -->
+static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#8d8df6d136115ec977eb6bf20148547a">dump_msg</a> (const u8 *buf, unsigned int length)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#97a11808b8b12a365a91f02b6d686d0c">dwc_otg_ep_write_packet</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, <a class="el" href="structdwc__ep.html">dwc_ep_t</a> *ep, int dma)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function writes a packet into the Tx FIFO associated with the EP.  <a href="#97a11808b8b12a365a91f02b6d686d0c"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#5edca13178261136209ed51360c850b4">dwc_otg_ep_set_stall</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, <a class="el" href="structdwc__ep.html">dwc_ep_t</a> *ep)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Set the EP STALL.  <a href="#5edca13178261136209ed51360c850b4"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#a5f77318fb1c589406927a606844007f">dwc_otg_ep_clear_stall</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, <a class="el" href="structdwc__ep.html">dwc_ep_t</a> *ep)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Clear the EP STALL.  <a href="#a5f77318fb1c589406927a606844007f"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#68f59dd23ccfffa9aa1dc590e99b7668">dwc_otg_read_packet</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, uint8_t *dest, uint16_t bytes)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function reads a packet from the Rx FIFO into the destination buffer.  <a href="#68f59dd23ccfffa9aa1dc590e99b7668"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#ea3bce6af9d0bd9b2fb6de94f1c7a133">dwc_otg_dump_dev_registers</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Dump core registers and SPRAM.  <a href="#ea3bce6af9d0bd9b2fb6de94f1c7a133"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#393e65ddcbaed38935ea06fb7451167b">dwc_otg_dump_spram</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This functions reads the SPRAM and prints its content.  <a href="#393e65ddcbaed38935ea06fb7451167b"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#e85d3d04799b17226fcb00ea2074ca63">dwc_otg_dump_host_registers</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function reads the host registers and prints them.  <a href="#e85d3d04799b17226fcb00ea2074ca63"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#118ecda931e2b745f76fde129ff707c2">dwc_otg_dump_global_registers</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function reads the core global registers and prints them.  <a href="#118ecda931e2b745f76fde129ff707c2"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#039e387cd0e0282727da3c5a36f4cdda">dwc_otg_flush_tx_fifo</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, const int num)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Flush a Tx FIFO.  <a href="#039e387cd0e0282727da3c5a36f4cdda"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#fb275f0f9923cc30629fce5e3753025c">dwc_otg_flush_rx_fifo</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Flush Rx FIFO.  <a href="#fb275f0f9923cc30629fce5e3753025c"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#1edfc5634dd76db76e30f20affc10f0c">dwc_otg_core_reset</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Do core a soft reset of the core.  <a href="#1edfc5634dd76db76e30f20affc10f0c"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e83fb22890bc54c6b06cedb751430e77"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_is_device_mode" ref="e83fb22890bc54c6b06cedb751430e77" args="(dwc_otg_core_if_t *_core_if)" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#e83fb22890bc54c6b06cedb751430e77">dwc_otg_is_device_mode</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *_core_if)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f0bfe5f933e21a94ea06c96ffc086e72"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_is_host_mode" ref="f0bfe5f933e21a94ea06c96ffc086e72" args="(dwc_otg_core_if_t *_core_if)" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#f0bfe5f933e21a94ea06c96ffc086e72">dwc_otg_is_host_mode</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *_core_if)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#97c9b9d68211477e486848203def0d0f">dwc_otg_cil_register_hcd_callbacks</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, <a class="el" href="structdwc__otg__cil__callbacks.html">dwc_otg_cil_callbacks_t</a> *cb, void *p)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Register HCD callbacks.  <a href="#97c9b9d68211477e486848203def0d0f"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#d2a92003214f444d7ec35dd0c4bb4bc0">dwc_otg_cil_register_pcd_callbacks</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, <a class="el" href="structdwc__otg__cil__callbacks.html">dwc_otg_cil_callbacks_t</a> *cb, void *p)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Register PCD callbacks.  <a href="#d2a92003214f444d7ec35dd0c4bb4bc0"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#e39d47d3aee9efcd525c13ce6a1f5f6a">write_isoc_frame_data</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, <a class="el" href="structdwc__ep.html">dwc_ep_t</a> *ep)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function writes isoc data per 1 (micro)frame into tx fifo.  <a href="#e39d47d3aee9efcd525c13ce6a1f5f6a"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#0f0894ae9890260e1da839aa10af35cc">dwc_otg_iso_ep_start_frm_transfer</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, <a class="el" href="structdwc__ep.html">dwc_ep_t</a> *ep)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function initializes a descriptor chain for Isochronous transfer.  <a href="#0f0894ae9890260e1da839aa10af35cc"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="322ac38f3a85f48410ed6e91adce3955"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_set_uninitialized" ref="322ac38f3a85f48410ed6e91adce3955" args="(int32_t *p, int size)" -->
+static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#322ac38f3a85f48410ed6e91adce3955">dwc_otg_set_uninitialized</a> (int32_t *p, int size)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="d3dd61d5d48c2fc06bf4b2d37e848c93"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_param_initialized" ref="d3dd61d5d48c2fc06bf4b2d37e848c93" args="(int32_t val)" -->
+static int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#d3dd61d5d48c2fc06bf4b2d37e848c93">dwc_otg_param_initialized</a> (int32_t val)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f4f060a2decd6434bbd96703a4d1fc66"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_is_dma_enable" ref="f4f060a2decd6434bbd96703a4d1fc66" args="(dwc_otg_core_if_t *core_if)" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#f4f060a2decd6434bbd96703a4d1fc66">dwc_otg_is_dma_enable</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#878cc478f43c58991c446bd78f50f8f0">dwc_otg_set_param_otg_cap</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Specifies the OTG capabilities.  <a href="#878cc478f43c58991c446bd78f50f8f0"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="0896106921e87788480f078c86de274a"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_param_otg_cap" ref="0896106921e87788480f078c86de274a" args="(dwc_otg_core_if_t *core_if)" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#0896106921e87788480f078c86de274a">dwc_otg_get_param_otg_cap</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="d0603b00a0ff87007ded1c06613d6b87"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_set_param_opt" ref="d0603b00a0ff87007ded1c06613d6b87" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#d0603b00a0ff87007ded1c06613d6b87">dwc_otg_set_param_opt</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="1b57cc827b21df14faa0eec1cbab1742"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_param_opt" ref="1b57cc827b21df14faa0eec1cbab1742" args="(dwc_otg_core_if_t *core_if)" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#1b57cc827b21df14faa0eec1cbab1742">dwc_otg_get_param_opt</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#b4fbe11281b8200b70202d4e0048a9d7">dwc_otg_set_param_dma_enable</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Specifies whether to use slave or DMA mode for accessing the data FIFOs.  <a href="#b4fbe11281b8200b70202d4e0048a9d7"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="0c78da7b7e7b59b31bd99a07d926a298"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_param_dma_enable" ref="0c78da7b7e7b59b31bd99a07d926a298" args="(dwc_otg_core_if_t *core_if)" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#0c78da7b7e7b59b31bd99a07d926a298">dwc_otg_get_param_dma_enable</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#7eae744525314774d3b390f116db126c">dwc_otg_set_param_dma_desc_enable</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">When DMA mode is enabled specifies whether to use address DMA or DMA Descritor mode for accessing the data FIFOs in device mode.  <a href="#7eae744525314774d3b390f116db126c"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="5cac7b3770cefa9db25bb46193134c5a"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_param_dma_desc_enable" ref="5cac7b3770cefa9db25bb46193134c5a" args="(dwc_otg_core_if_t *core_if)" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#5cac7b3770cefa9db25bb46193134c5a">dwc_otg_get_param_dma_desc_enable</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#8bd669637630521655c455c03d470e10">dwc_otg_set_param_host_support_fs_ls_low_power</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Specifies whether low power mode is supported when attached to a Full Speed or Low Speed device in host mode.  <a href="#8bd669637630521655c455c03d470e10"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ce7a69af8ef1970a640d0a23c7c8f12a"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_param_host_support_fs_ls_low_power" ref="ce7a69af8ef1970a640d0a23c7c8f12a" args="(dwc_otg_core_if_t *core_if)" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#ce7a69af8ef1970a640d0a23c7c8f12a">dwc_otg_get_param_host_support_fs_ls_low_power</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="61bb728cc80220e5173d5e3126dd4fd1"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_set_param_enable_dynamic_fifo" ref="61bb728cc80220e5173d5e3126dd4fd1" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#61bb728cc80220e5173d5e3126dd4fd1">dwc_otg_set_param_enable_dynamic_fifo</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">0 - Use cC FIFO size parameters 1 - Allow dynamic FIFO sizing (default) <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3bc5fc1c94b4bb1a5b5dcca6fa71584e"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_param_enable_dynamic_fifo" ref="3bc5fc1c94b4bb1a5b5dcca6fa71584e" args="(dwc_otg_core_if_t *core_if)" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#3bc5fc1c94b4bb1a5b5dcca6fa71584e">dwc_otg_get_param_enable_dynamic_fifo</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#69d52c46eb236816b20675ecb57975ae">dwc_otg_set_param_data_fifo_size</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Total number of 4-byte words in the data FIFO memory.  <a href="#69d52c46eb236816b20675ecb57975ae"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3695ec355114fb8da2f57b7f5c2159b7"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_param_data_fifo_size" ref="3695ec355114fb8da2f57b7f5c2159b7" args="(dwc_otg_core_if_t *core_if)" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#3695ec355114fb8da2f57b7f5c2159b7">dwc_otg_get_param_data_fifo_size</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#0fa4db196053869ac19832c03c62913f">dwc_otg_set_param_dev_rx_fifo_size</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Number of 4-byte words in the Rx FIFO in device mode when dynamic FIFO sizing is enabled.  <a href="#0fa4db196053869ac19832c03c62913f"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="56781e1cc653e948147afab10c19b72a"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_param_dev_rx_fifo_size" ref="56781e1cc653e948147afab10c19b72a" args="(dwc_otg_core_if_t *core_if)" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#56781e1cc653e948147afab10c19b72a">dwc_otg_get_param_dev_rx_fifo_size</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#4f7059cecabbf8cfe5014112ba9a3d42">dwc_otg_set_param_dev_nperio_tx_fifo_size</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Number of 4-byte words in the non-periodic Tx FIFO in device mode when dynamic FIFO sizing is enabled.  <a href="#4f7059cecabbf8cfe5014112ba9a3d42"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="bb61fc259fe1dc0aee41a3c8b4e99b88"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_param_dev_nperio_tx_fifo_size" ref="bb61fc259fe1dc0aee41a3c8b4e99b88" args="(dwc_otg_core_if_t *core_if)" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#bb61fc259fe1dc0aee41a3c8b4e99b88">dwc_otg_get_param_dev_nperio_tx_fifo_size</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#254c1e97cf22fe34b7383165e30071eb">dwc_otg_set_param_host_rx_fifo_size</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO sizing is enabled.  <a href="#254c1e97cf22fe34b7383165e30071eb"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7b964a905858d04ce43159bbfca20f34"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_param_host_rx_fifo_size" ref="7b964a905858d04ce43159bbfca20f34" args="(dwc_otg_core_if_t *core_if)" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#7b964a905858d04ce43159bbfca20f34">dwc_otg_get_param_host_rx_fifo_size</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#a66ca9f9345a13606148b050f8690a56">dwc_otg_set_param_host_nperio_tx_fifo_size</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Number of 4-byte words in the non-periodic Tx FIFO in host mode when Dynamic FIFO sizing is enabled in the core.  <a href="#a66ca9f9345a13606148b050f8690a56"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e53a7fddb0a2689e463cbd9c441ee004"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_param_host_nperio_tx_fifo_size" ref="e53a7fddb0a2689e463cbd9c441ee004" args="(dwc_otg_core_if_t *core_if)" -->
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+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#e4ce399208d8a85dcb9dedd1fb8cd8ce">dwc_otg_set_param_host_perio_tx_fifo_size</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO sizing is enabled.  <a href="#e4ce399208d8a85dcb9dedd1fb8cd8ce"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="9b2de0caea0d9ee86258ac4bbe63acd5"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_param_host_perio_tx_fifo_size" ref="9b2de0caea0d9ee86258ac4bbe63acd5" args="(dwc_otg_core_if_t *core_if)" -->
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+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#2eee676071d6bb4eba53b413e80b045f">dwc_otg_set_param_max_transfer_size</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">The maximum transfer size supported in bytes.  <a href="#2eee676071d6bb4eba53b413e80b045f"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="307c59e350a8ea67ef5d1c02f79de17b"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_param_max_transfer_size" ref="307c59e350a8ea67ef5d1c02f79de17b" args="(dwc_otg_core_if_t *core_if)" -->
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+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#a1c52f0740f7d0b72c980b38cc4314d1">dwc_otg_set_param_max_packet_count</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">The maximum number of packets in a transfer.  <a href="#a1c52f0740f7d0b72c980b38cc4314d1"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="765e82d04dc91bdc93c129d9ba7c5161"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_param_max_packet_count" ref="765e82d04dc91bdc93c129d9ba7c5161" args="(dwc_otg_core_if_t *core_if)" -->
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+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#f802acfc49b3fbb86159036f8f317f76">dwc_otg_set_param_host_channels</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">The number of host channel registers to use.  <a href="#f802acfc49b3fbb86159036f8f317f76"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e1235c11a6a3e8d0e78df59d86d4d287"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_param_host_channels" ref="e1235c11a6a3e8d0e78df59d86d4d287" args="(dwc_otg_core_if_t *core_if)" -->
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+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#75d3b409824c0ca52631277398ba8367">dwc_otg_set_param_dev_endpoints</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">The number of endpoints in addition to EP0 available for device mode operations.  <a href="#75d3b409824c0ca52631277398ba8367"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="27447ccef5d5a1c3e5c93ed3b352e152"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_param_dev_endpoints" ref="27447ccef5d5a1c3e5c93ed3b352e152" args="(dwc_otg_core_if_t *core_if)" -->
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+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#2b7087c85c0ea1520ec2e091b80bf36b">dwc_otg_set_param_phy_type</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Specifies the type of PHY interface to use.  <a href="#2b7087c85c0ea1520ec2e091b80bf36b"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e49dd633ec87aa71335ef6ef312283a3"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_param_phy_type" ref="e49dd633ec87aa71335ef6ef312283a3" args="(dwc_otg_core_if_t *core_if)" -->
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+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#7acd153b5577a3db825fa08d243ae856">dwc_otg_set_param_speed</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Specifies the maximum speed of operation in host and device mode.  <a href="#7acd153b5577a3db825fa08d243ae856"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f18994b0fe09d9d3031ef8290945c1ea"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_param_speed" ref="f18994b0fe09d9d3031ef8290945c1ea" args="(dwc_otg_core_if_t *core_if)" -->
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+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#354ce49f65334e829c2694811c4f2016">dwc_otg_set_param_host_ls_low_power_phy_clk</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Specifies the PHY clock rate in low power mode when connected to a Low Speed device in host mode.  <a href="#354ce49f65334e829c2694811c4f2016"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="02ea6a179d92658c4cf4e5b513cb2414"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_param_host_ls_low_power_phy_clk" ref="02ea6a179d92658c4cf4e5b513cb2414" args="(dwc_otg_core_if_t *core_if)" -->
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+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#5dab15db053bd02c6bc9619e189a6a14">dwc_otg_set_param_phy_ulpi_ddr</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Specifies whether the ULPI operates at double or single data rate.  <a href="#5dab15db053bd02c6bc9619e189a6a14"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="95655db9d2dce391da40361fe310599c"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_param_phy_ulpi_ddr" ref="95655db9d2dce391da40361fe310599c" args="(dwc_otg_core_if_t *core_if)" -->
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+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Specifies whether to use the internal or external supply to drive the vbus with a ULPI phy. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b0604fadb0b685a106507eacd18e12a6"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_param_phy_ulpi_ext_vbus" ref="b0604fadb0b685a106507eacd18e12a6" args="(dwc_otg_core_if_t *core_if)" -->
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+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#1eacecc96e1ab100cbf129ad6aa5f6c8">dwc_otg_set_param_phy_utmi_width</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Specifies the UTMI+ Data Width.  <a href="#1eacecc96e1ab100cbf129ad6aa5f6c8"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="9dfa6a24c38b5ba13c08abe22d532a1d"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_param_phy_utmi_width" ref="9dfa6a24c38b5ba13c08abe22d532a1d" args="(dwc_otg_core_if_t *core_if)" -->
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+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#65d7407ed24c82e158a38ab2a60120c4">dwc_otg_set_param_i2c_enable</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Specifies whether to use the I2Cinterface for full speed PHY.  <a href="#65d7407ed24c82e158a38ab2a60120c4"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="80cf1905c95391fa1acaa2237182ddf8"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_param_i2c_enable" ref="80cf1905c95391fa1acaa2237182ddf8" args="(dwc_otg_core_if_t *core_if)" -->
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+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#2119a493582bea4004b5fdeba15f1609">dwc_otg_set_param_dev_perio_tx_fifo_size</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val, int fifo_num)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Number of 4-byte words in each of the periodic Tx FIFOs in device mode when dynamic FIFO sizing is enabled.  <a href="#2119a493582bea4004b5fdeba15f1609"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="d9bf0270a9b9617f0d196dd566a1c610"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_param_dev_perio_tx_fifo_size" ref="d9bf0270a9b9617f0d196dd566a1c610" args="(dwc_otg_core_if_t *core_if, int fifo_num)" -->
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+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="2eefd02d72c79200072d54b4eb13e5cd"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_set_param_en_multiple_tx_fifo" ref="2eefd02d72c79200072d54b4eb13e5cd" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
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+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Specifies whether dedicated transmit FIFOs are enabled for non periodic IN endpoints in device mode 0 - No 1 - Yes. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="bc8e0312a565efb2d5117984219b4460"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_param_en_multiple_tx_fifo" ref="bc8e0312a565efb2d5117984219b4460" args="(dwc_otg_core_if_t *core_if)" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#bc8e0312a565efb2d5117984219b4460">dwc_otg_get_param_en_multiple_tx_fifo</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="44bf6b41f0892f480ea6c03a2ac1e73f"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_set_param_dev_tx_fifo_size" ref="44bf6b41f0892f480ea6c03a2ac1e73f" args="(dwc_otg_core_if_t *core_if, int32_t val, int fifo_num)" -->
+int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#44bf6b41f0892f480ea6c03a2ac1e73f">dwc_otg_set_param_dev_tx_fifo_size</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val, int fifo_num)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="99a491c648b6066077426c9cdc374aa8"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_param_dev_tx_fifo_size" ref="99a491c648b6066077426c9cdc374aa8" args="(dwc_otg_core_if_t *core_if, int fifo_num)" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#99a491c648b6066077426c9cdc374aa8">dwc_otg_get_param_dev_tx_fifo_size</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int fifo_num)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="6095d6a93f901f32522d4b950c99a8e1"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_set_param_thr_ctl" ref="6095d6a93f901f32522d4b950c99a8e1" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#6095d6a93f901f32522d4b950c99a8e1">dwc_otg_set_param_thr_ctl</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Thresholding enable flag- bit 0 - enable non-ISO Tx thresholding bit 1 - enable ISO Tx thresholding bit 2 - enable Rx thresholding. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="99787b8e86a8d37e1a5be93d52487a3a"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_param_thr_ctl" ref="99787b8e86a8d37e1a5be93d52487a3a" args="(dwc_otg_core_if_t *core_if)" -->
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+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e3a62b66e19a302a55046830f5eecf0c"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_set_param_lpm_enable" ref="e3a62b66e19a302a55046830f5eecf0c" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
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+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Specifies whether LPM (Link Power Management) support is enabled. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="0e0eb29733595730396da3ddf3d0ded5"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_param_lpm_enable" ref="0e0eb29733595730396da3ddf3d0ded5" args="(dwc_otg_core_if_t *core_if)" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#0e0eb29733595730396da3ddf3d0ded5">dwc_otg_get_param_lpm_enable</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="1ed19fed8939a352f91fe1403574135e"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_set_param_tx_thr_length" ref="1ed19fed8939a352f91fe1403574135e" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#1ed19fed8939a352f91fe1403574135e">dwc_otg_set_param_tx_thr_length</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Thresholding length for Tx FIFOs in 32 bit DWORDs. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e3499cd5ce6ab45640be2a5040ad4f1c"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_param_tx_thr_length" ref="e3499cd5ce6ab45640be2a5040ad4f1c" args="(dwc_otg_core_if_t *core_if)" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#e3499cd5ce6ab45640be2a5040ad4f1c">dwc_otg_get_param_tx_thr_length</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="20d005470a65927cb243b37619f6c6bf"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_set_param_rx_thr_length" ref="20d005470a65927cb243b37619f6c6bf" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#20d005470a65927cb243b37619f6c6bf">dwc_otg_set_param_rx_thr_length</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Thresholding length for Rx FIFOs in 32 bit DWORDs. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c0cd2e32622903a2c1707bf8fe9c3dba"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_param_rx_thr_length" ref="c0cd2e32622903a2c1707bf8fe9c3dba" args="(dwc_otg_core_if_t *core_if)" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#c0cd2e32622903a2c1707bf8fe9c3dba">dwc_otg_get_param_rx_thr_length</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#920035c6082dcdfec11a20e8535e9fe9">dwc_otg_set_param_dma_burst_size</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">The DMA Burst size (applicable only for External DMA Mode).  <a href="#920035c6082dcdfec11a20e8535e9fe9"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7450ef9275974e46f41f12fdc6da7901"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_param_dma_burst_size" ref="7450ef9275974e46f41f12fdc6da7901" args="(dwc_otg_core_if_t *core_if)" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#7450ef9275974e46f41f12fdc6da7901">dwc_otg_get_param_dma_burst_size</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="63c0b4bfcf3b1c6c90c5572258439e1f"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_set_param_pti_enable" ref="63c0b4bfcf3b1c6c90c5572258439e1f" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#63c0b4bfcf3b1c6c90c5572258439e1f">dwc_otg_set_param_pti_enable</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Specifies whether PTI enhancement is enabled. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="9d729a393133a8111b68d4b5ec9fdd30"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_param_pti_enable" ref="9d729a393133a8111b68d4b5ec9fdd30" args="(dwc_otg_core_if_t *core_if)" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#9d729a393133a8111b68d4b5ec9fdd30">dwc_otg_get_param_pti_enable</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7ba10fdfd2ce9f3ef4b0a2bef555a7c1"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_set_param_mpi_enable" ref="7ba10fdfd2ce9f3ef4b0a2bef555a7c1" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#7ba10fdfd2ce9f3ef4b0a2bef555a7c1">dwc_otg_set_param_mpi_enable</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Specifies whether MPI enhancement is enabled. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7b9e3bced8a43e810fca322e36946f31"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_param_mpi_enable" ref="7b9e3bced8a43e810fca322e36946f31" args="(dwc_otg_core_if_t *core_if)" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#7b9e3bced8a43e810fca322e36946f31">dwc_otg_get_param_mpi_enable</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="93036faefc8179eef11c8ca0b18993a8"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_set_param_ic_usb_cap" ref="93036faefc8179eef11c8ca0b18993a8" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#93036faefc8179eef11c8ca0b18993a8">dwc_otg_set_param_ic_usb_cap</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Specifies whether IC_USB capability is enabled. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="1ccaddc86262ff99dad6c1e44f5ff965"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_param_ic_usb_cap" ref="1ccaddc86262ff99dad6c1e44f5ff965" args="(dwc_otg_core_if_t *core_if)" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#1ccaddc86262ff99dad6c1e44f5ff965">dwc_otg_get_param_ic_usb_cap</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="9bf87dcaa6dcea51eb3d8c30439a2138"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_set_param_ahb_thr_ratio" ref="9bf87dcaa6dcea51eb3d8c30439a2138" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#9bf87dcaa6dcea51eb3d8c30439a2138">dwc_otg_set_param_ahb_thr_ratio</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="275fab9bf16bd3cb148901c578fbcbd0"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_param_ahb_thr_ratio" ref="275fab9bf16bd3cb148901c578fbcbd0" args="(dwc_otg_core_if_t *core_if)" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#275fab9bf16bd3cb148901c578fbcbd0">dwc_otg_get_param_ahb_thr_ratio</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="df391379aafa69a8683bb1f88c413675"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_hnpstatus" ref="df391379aafa69a8683bb1f88c413675" args="(dwc_otg_core_if_t *core_if)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#df391379aafa69a8683bb1f88c413675">dwc_otg_get_hnpstatus</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get host negotiation status. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b13eac2758aace478587df0f043e80f8"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_srpstatus" ref="b13eac2758aace478587df0f043e80f8" args="(dwc_otg_core_if_t *core_if)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#b13eac2758aace478587df0f043e80f8">dwc_otg_get_srpstatus</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get srp status. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="5cab27b65ed5a6a1e31c0e4df1650f0e"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_set_hnpreq" ref="5cab27b65ed5a6a1e31c0e4df1650f0e" args="(dwc_otg_core_if_t *core_if, uint32_t val)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#5cab27b65ed5a6a1e31c0e4df1650f0e">dwc_otg_set_hnpreq</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, uint32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Set hnpreq bit in the GOTGCTL register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c505c47a08029706f60ab8f3d67b70d3"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_gsnpsid" ref="c505c47a08029706f60ab8f3d67b70d3" args="(dwc_otg_core_if_t *core_if)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#c505c47a08029706f60ab8f3d67b70d3">dwc_otg_get_gsnpsid</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get Content of SNPSID register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#788149caf9d915abbe5e289793684b1e">dwc_otg_get_mode</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get current mode.  <a href="#788149caf9d915abbe5e289793684b1e"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="d222e3bdaba5ea8fa0df22ff9cee2f5e"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_hnpcapable" ref="d222e3bdaba5ea8fa0df22ff9cee2f5e" args="(dwc_otg_core_if_t *core_if)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#d222e3bdaba5ea8fa0df22ff9cee2f5e">dwc_otg_get_hnpcapable</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get value of hnpcapable field in the GUSBCFG register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b9ab6ff4d50ea35738853f831f480c3e"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_set_hnpcapable" ref="b9ab6ff4d50ea35738853f831f480c3e" args="(dwc_otg_core_if_t *core_if, uint32_t val)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#b9ab6ff4d50ea35738853f831f480c3e">dwc_otg_set_hnpcapable</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, uint32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Set value of hnpcapable field in the GUSBCFG register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="2bba47b0255cfbc9b19661e9ddd2f497"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_srpcapable" ref="2bba47b0255cfbc9b19661e9ddd2f497" args="(dwc_otg_core_if_t *core_if)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#2bba47b0255cfbc9b19661e9ddd2f497">dwc_otg_get_srpcapable</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get value of srpcapable field in the GUSBCFG register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e75a4faa49ac70c19e9bc8a039d6e37f"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_set_srpcapable" ref="e75a4faa49ac70c19e9bc8a039d6e37f" args="(dwc_otg_core_if_t *core_if, uint32_t val)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#e75a4faa49ac70c19e9bc8a039d6e37f">dwc_otg_set_srpcapable</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, uint32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Set value of srpcapable field in the GUSBCFG register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="d69afedd204a41974de582224479569e"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_devspeed" ref="d69afedd204a41974de582224479569e" args="(dwc_otg_core_if_t *core_if)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#d69afedd204a41974de582224479569e">dwc_otg_get_devspeed</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get value of devspeed field in the DCFG register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ead8dea166cbefca04dc5c543c96fba0"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_set_devspeed" ref="ead8dea166cbefca04dc5c543c96fba0" args="(dwc_otg_core_if_t *core_if, uint32_t val)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#ead8dea166cbefca04dc5c543c96fba0">dwc_otg_set_devspeed</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, uint32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Set value of devspeed field in the DCFG register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="07354b164566c5c1c34446d5b0c4036f"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_busconnected" ref="07354b164566c5c1c34446d5b0c4036f" args="(dwc_otg_core_if_t *core_if)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#07354b164566c5c1c34446d5b0c4036f">dwc_otg_get_busconnected</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get the value of busconnected field from the HPRT0 register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="520bf6b5f5ec69e5dcbdad6254c3cede"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_enumspeed" ref="520bf6b5f5ec69e5dcbdad6254c3cede" args="(dwc_otg_core_if_t *core_if)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#520bf6b5f5ec69e5dcbdad6254c3cede">dwc_otg_get_enumspeed</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Gets the device enumeration Speed. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="83a11dae1c9563aee56baea469cd6064"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_prtpower" ref="83a11dae1c9563aee56baea469cd6064" args="(dwc_otg_core_if_t *core_if)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#83a11dae1c9563aee56baea469cd6064">dwc_otg_get_prtpower</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get value of prtpwr field from the HPRT0 register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="63c880f915b4705a5c118b276e6e9567"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_set_prtpower" ref="63c880f915b4705a5c118b276e6e9567" args="(dwc_otg_core_if_t *core_if, uint32_t val)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#63c880f915b4705a5c118b276e6e9567">dwc_otg_set_prtpower</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, uint32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Set value of prtpwr field from the HPRT0 register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="65b0861f7d5d604fb97e599adac62642"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_prtsuspend" ref="65b0861f7d5d604fb97e599adac62642" args="(dwc_otg_core_if_t *core_if)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#65b0861f7d5d604fb97e599adac62642">dwc_otg_get_prtsuspend</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get value of prtsusp field from the HPRT0 regsiter. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c072cef5b7d3c5566ad3be010c6d49ed"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_set_prtsuspend" ref="c072cef5b7d3c5566ad3be010c6d49ed" args="(dwc_otg_core_if_t *core_if, uint32_t val)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#c072cef5b7d3c5566ad3be010c6d49ed">dwc_otg_set_prtsuspend</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, uint32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Set value of prtpwr field from the HPRT0 register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b6d6b18934ba5cd4ce2cf9e68be338f5"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_set_prtresume" ref="b6d6b18934ba5cd4ce2cf9e68be338f5" args="(dwc_otg_core_if_t *core_if, uint32_t val)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#b6d6b18934ba5cd4ce2cf9e68be338f5">dwc_otg_set_prtresume</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, uint32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Set value of prtres field from the HPRT0 register FIXME Remove? <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="285696198299e317222544aa912b2c35"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_remotewakesig" ref="285696198299e317222544aa912b2c35" args="(dwc_otg_core_if_t *core_if)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#285696198299e317222544aa912b2c35">dwc_otg_get_remotewakesig</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get value of rmtwkupsig bit in DCTL register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="87d643973839554bac437d283a462e00"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_lpm_portsleepstatus" ref="87d643973839554bac437d283a462e00" args="(dwc_otg_core_if_t *core_if)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#87d643973839554bac437d283a462e00">dwc_otg_get_lpm_portsleepstatus</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get value of prt_sleep_sts field from the GLPMCFG register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="91d2a6b57c7216fd5c6dc981a5f0e1ae"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_lpm_remotewakeenabled" ref="91d2a6b57c7216fd5c6dc981a5f0e1ae" args="(dwc_otg_core_if_t *core_if)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#91d2a6b57c7216fd5c6dc981a5f0e1ae">dwc_otg_get_lpm_remotewakeenabled</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get value of rem_wkup_en field from the GLPMCFG register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="86d921a91b7e2b143a305283282ce36d"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_lpmresponse" ref="86d921a91b7e2b143a305283282ce36d" args="(dwc_otg_core_if_t *core_if)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#86d921a91b7e2b143a305283282ce36d">dwc_otg_get_lpmresponse</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get value of appl_resp field from the GLPMCFG register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b19565bc2a8dbb258c3c2cb8c52240b8"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_set_lpmresponse" ref="b19565bc2a8dbb258c3c2cb8c52240b8" args="(dwc_otg_core_if_t *core_if, uint32_t val)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#b19565bc2a8dbb258c3c2cb8c52240b8">dwc_otg_set_lpmresponse</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, uint32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Set value of appl_resp field from the GLPMCFG register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="0fb8a2b51041b2f5476abc8ffbcc46cb"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_hsic_connect" ref="0fb8a2b51041b2f5476abc8ffbcc46cb" args="(dwc_otg_core_if_t *core_if)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#0fb8a2b51041b2f5476abc8ffbcc46cb">dwc_otg_get_hsic_connect</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get value of hsic_connect field from the GLPMCFG register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="6625bea93daab21b2a97004f743203f9"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_set_hsic_connect" ref="6625bea93daab21b2a97004f743203f9" args="(dwc_otg_core_if_t *core_if, uint32_t val)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#6625bea93daab21b2a97004f743203f9">dwc_otg_set_hsic_connect</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, uint32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Set value of hsic_connect field from the GLPMCFG register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="a3399019a62013ccc6ce213e8f241d7a"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_inv_sel_hsic" ref="a3399019a62013ccc6ce213e8f241d7a" args="(dwc_otg_core_if_t *core_if)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#a3399019a62013ccc6ce213e8f241d7a">dwc_otg_get_inv_sel_hsic</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get value of inv_sel_hsic field from the GLPMCFG register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ef8b7bbc803e779480aa06779a44e4f0"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_set_inv_sel_hsic" ref="ef8b7bbc803e779480aa06779a44e4f0" args="(dwc_otg_core_if_t *core_if, uint32_t val)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#ef8b7bbc803e779480aa06779a44e4f0">dwc_otg_set_inv_sel_hsic</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, uint32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Set value of inv_sel_hsic field from the GLPMFG register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="a450da19279ae7246c89ede2949189fe"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_gotgctl" ref="a450da19279ae7246c89ede2949189fe" args="(dwc_otg_core_if_t *core_if)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#a450da19279ae7246c89ede2949189fe">dwc_otg_get_gotgctl</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">GOTGCTL register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="be44aee1ee301bdcbf7174cc1c729032"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_set_gotgctl" ref="be44aee1ee301bdcbf7174cc1c729032" args="(dwc_otg_core_if_t *core_if, uint32_t val)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#be44aee1ee301bdcbf7174cc1c729032">dwc_otg_set_gotgctl</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, uint32_t val)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="eb5b1512f29fa951f2875dc52d368085"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_gusbcfg" ref="eb5b1512f29fa951f2875dc52d368085" args="(dwc_otg_core_if_t *core_if)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#eb5b1512f29fa951f2875dc52d368085">dwc_otg_get_gusbcfg</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">GUSBCFG register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="74d5e1045c70fd5efc35a39ca4311baa"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_set_gusbcfg" ref="74d5e1045c70fd5efc35a39ca4311baa" args="(dwc_otg_core_if_t *core_if, uint32_t val)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#74d5e1045c70fd5efc35a39ca4311baa">dwc_otg_set_gusbcfg</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, uint32_t val)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ce6ba769b9c0abd15c8f0b118d74c8e4"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_grxfsiz" ref="ce6ba769b9c0abd15c8f0b118d74c8e4" args="(dwc_otg_core_if_t *core_if)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#ce6ba769b9c0abd15c8f0b118d74c8e4">dwc_otg_get_grxfsiz</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">GRXFSIZ register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3e251d5b9273ae2e2b3f5714694974a5"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_set_grxfsiz" ref="3e251d5b9273ae2e2b3f5714694974a5" args="(dwc_otg_core_if_t *core_if, uint32_t val)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#3e251d5b9273ae2e2b3f5714694974a5">dwc_otg_set_grxfsiz</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, uint32_t val)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3110e552598b04bbe6b30bcddadda98b"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_gnptxfsiz" ref="3110e552598b04bbe6b30bcddadda98b" args="(dwc_otg_core_if_t *core_if)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#3110e552598b04bbe6b30bcddadda98b">dwc_otg_get_gnptxfsiz</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">GNPTXFSIZ register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="48c625d569671523aac60af8e2d60d7a"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_set_gnptxfsiz" ref="48c625d569671523aac60af8e2d60d7a" args="(dwc_otg_core_if_t *core_if, uint32_t val)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#48c625d569671523aac60af8e2d60d7a">dwc_otg_set_gnptxfsiz</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, uint32_t val)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c8fcf302be26cad07b9ba36082e0ed5c"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_gpvndctl" ref="c8fcf302be26cad07b9ba36082e0ed5c" args="(dwc_otg_core_if_t *core_if)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#c8fcf302be26cad07b9ba36082e0ed5c">dwc_otg_get_gpvndctl</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="4c700540a6c1061eb2491c78670bb26f"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_set_gpvndctl" ref="4c700540a6c1061eb2491c78670bb26f" args="(dwc_otg_core_if_t *core_if, uint32_t val)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#4c700540a6c1061eb2491c78670bb26f">dwc_otg_set_gpvndctl</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, uint32_t val)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="5b3367179e8c0c6ccb5041db26f8e0cc"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_ggpio" ref="5b3367179e8c0c6ccb5041db26f8e0cc" args="(dwc_otg_core_if_t *core_if)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#5b3367179e8c0c6ccb5041db26f8e0cc">dwc_otg_get_ggpio</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">GGPIO register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="4b6bd4ddf333b856631cd561eb747882"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_set_ggpio" ref="4b6bd4ddf333b856631cd561eb747882" args="(dwc_otg_core_if_t *core_if, uint32_t val)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#4b6bd4ddf333b856631cd561eb747882">dwc_otg_set_ggpio</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, uint32_t val)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="6345490821a039a5eff6ec8e5c0e8c0b"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_hprt0" ref="6345490821a039a5eff6ec8e5c0e8c0b" args="(dwc_otg_core_if_t *core_if)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#6345490821a039a5eff6ec8e5c0e8c0b">dwc_otg_get_hprt0</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">HPRT0 register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c2ec55794abeeb14f5b4d00613122bb7"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_set_hprt0" ref="c2ec55794abeeb14f5b4d00613122bb7" args="(dwc_otg_core_if_t *core_if, uint32_t val)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#c2ec55794abeeb14f5b4d00613122bb7">dwc_otg_set_hprt0</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, uint32_t val)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c308abdec734a3d2f183d2085271d285"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_guid" ref="c308abdec734a3d2f183d2085271d285" args="(dwc_otg_core_if_t *core_if)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#c308abdec734a3d2f183d2085271d285">dwc_otg_get_guid</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">GUID register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="edf22163b21a9ab3539976e19338f1e9"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_set_guid" ref="edf22163b21a9ab3539976e19338f1e9" args="(dwc_otg_core_if_t *core_if, uint32_t val)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#edf22163b21a9ab3539976e19338f1e9">dwc_otg_set_guid</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, uint32_t val)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="6180fa187cfbeef487a71fb4f72a6381"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_hptxfsiz" ref="6180fa187cfbeef487a71fb4f72a6381" args="(dwc_otg_core_if_t *core_if)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8c.html#6180fa187cfbeef487a71fb4f72a6381">dwc_otg_get_hptxfsiz</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">GHPTXFSIZE. <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+The Core Interface Layer provides basic services for accessing and managing the DWC_otg hardware. 
+<p>
+These services are used by both the Host Controller Driver and the Peripheral Controller Driver.<p>
+The CIL manages the memory map for the core so that the HCD and PCD don't have to do this separately. It also handles basic tasks like reading/writing the registers and data FIFOs in the controller. Some of the data access functions provide encapsulation of several operations required to perform a task, such as writing multiple registers to start a transfer. Finally, the CIL performs basic services that are not specific to either the host or device modes of operation. These services include management of the OTG Host Negotiation Protocol (HNP) and Session Request Protocol (SRP). A Diagnostic API is also provided to allow testing of the controller hardware.<p>
+The Core Interface Layer has the following requirements:<ul>
+<li>Provides basic controller operations.</li><li>Minimal use of OS services.</li><li>The OS services used will be abstracted by using inline functions or macros. </li></ul>
+
+<p>
+Definition in file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.<hr><h2>Define Documentation</h2>
+<a class="anchor" name="c4138a87302505f6ef79dc3bfb4951c0"></a><!-- doxytag: member="dwc_otg_cil.c::DWC_OTG_PARAM_TEST" ref="c4138a87302505f6ef79dc3bfb4951c0" args="(_param_, _low_, _high_)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_OTG_PARAM_TEST          </td>
+          <td>(</td>
+          <td class="paramtype">_param_,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">_low_,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">_high_&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment">(((_param_) &lt; (_low_)) || \
+                ((_param_) &gt; (_high_)))
+</pre></div>
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l04051">4051</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<hr><h2>Function Documentation</h2>
+<a class="anchor" name="2dc0a6c5541c1a8a014d66a8fce53f66"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_cil_init" ref="2dc0a6c5541c1a8a014d66a8fce53f66" args="(const uint32_t *reg_base_addr)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a>* dwc_otg_cil_init           </td>
+          <td>(</td>
+          <td class="paramtype">const uint32_t *&nbsp;</td>
+          <td class="paramname"> <em>reg_base_addr</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function is called to initialize the DWC_otg CSR data structures. 
+<p>
+The register addresses in the device and host structures are initialized from the base address supplied by the caller. The calling function must make the OS calls to get the base address of the DWC_otg controller registers. The core_params argument holds the parameters that specify how the core should be configured.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>reg_base_addr</em>&nbsp;</td><td>Base address of DWC_otg core registers </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l00078">78</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="cc4a08b278c7afe0484b595cacf80c04"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_cil_remove" ref="cc4a08b278c7afe0484b595cacf80c04" args="(dwc_otg_core_if_t *core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_cil_remove           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function frees the structures allocated by <a class="el" href="dwc__otg__cil_8c.html#2dc0a6c5541c1a8a014d66a8fce53f66">dwc_otg_cil_init()</a>. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>The core interface pointer returned from <a class="el" href="dwc__otg__cil_8c.html#2dc0a6c5541c1a8a014d66a8fce53f66">dwc_otg_cil_init()</a>. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l00265">265</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="8b0b841d69298089b7d03b07ade8eda6"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_enable_global_interrupts" ref="8b0b841d69298089b7d03b07ade8eda6" args="(dwc_otg_core_if_t *core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_enable_global_interrupts           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function enables the controller's Global Interrupt in the AHB Config register. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l00292">292</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="9f673c38ca761d8ab7b3333b506bcbfc"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_disable_global_interrupts" ref="9f673c38ca761d8ab7b3333b506bcbfc" args="(dwc_otg_core_if_t *core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_disable_global_interrupts           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function disables the controller's Global Interrupt in the AHB Config register. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l00305">305</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="1761ac95e17bad3fa304413cc81c51de"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_enable_common_interrupts" ref="1761ac95e17bad3fa304413cc81c51de" args="(dwc_otg_core_if_t *core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static void dwc_otg_enable_common_interrupts           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function initializes the commmon interrupts, used in both device and host modes. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of the DWC_otg controller </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l00319">319</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="1cdde3ab3e53e93c5a42feed628aaf7d"></a><!-- doxytag: member="dwc_otg_cil.c::calc_num_in_eps" ref="1cdde3ab3e53e93c5a42feed628aaf7d" args="(dwc_otg_core_if_t *core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static uint32_t calc_num_in_eps           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function calculates the number of IN EPS using GHWCFG1 and GHWCFG2 registers values. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of the DWC_otg controller </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l00415">415</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="e923d8ecfaf2957ef7d0a1379e0b5101"></a><!-- doxytag: member="dwc_otg_cil.c::calc_num_out_eps" ref="e923d8ecfaf2957ef7d0a1379e0b5101" args="(dwc_otg_core_if_t *core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static uint32_t calc_num_out_eps           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function calculates the number of OUT EPS using GHWCFG1 and GHWCFG2 registers values. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of the DWC_otg controller </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l00444">444</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="ce48d4f2d172600c325a82d793473d0f"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_core_init" ref="ce48d4f2d172600c325a82d793473d0f" args="(dwc_otg_core_if_t *core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_core_init           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function initializes the DWC_otg controller registers and prepares the core for device mode or host mode operation. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of the DWC_otg controller </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l00467">467</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="3d60e58f32be881047ac61bc852f60f7"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_enable_device_interrupts" ref="3d60e58f32be881047ac61bc852f60f7" args="(dwc_otg_core_if_t *core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_enable_device_interrupts           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function enables the Device mode interrupts. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller </td></tr>
+  </table>
+</dl>
+
+<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000005">Todo:</a></b></dt><dd>NGS: Should this be a module parameter? </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l00772">772</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="f79b0f3b5b96b0535e33627ee3a66eba"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_core_dev_init" ref="f79b0f3b5b96b0535e33627ee3a66eba" args="(dwc_otg_core_if_t *core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_core_dev_init           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function initializes the DWC_otg controller registers for device mode. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller </td></tr>
+  </table>
+</dl>
+
+<p>
+Set Periodic Tx FIFO Mask all bits 0<p>
+Set Tx FIFO Mask all bits 0<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000006">Todo:</a></b></dt><dd>NGS: Fix Periodic FIFO Sizing! </dd></dl>
+<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000006">Todo:</a></b></dt><dd>Finish debug of this </dd></dl>
+<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000006">Todo:</a></b></dt><dd><ul>
+<li>if the condition needed to be checked or in any case all pending interrutps should be cleared? </li></ul>
+</dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l00843">843</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="373701240c023fda03eed98cf093df74"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_enable_host_interrupts" ref="373701240c023fda03eed98cf093df74" args="(dwc_otg_core_if_t *core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_enable_host_interrupts           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function enables the Host mode interrupts. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l01130">1130</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="4dd4a30dd75a819e9da38d6410cbb0a4"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_disable_host_interrupts" ref="4dd4a30dd75a819e9da38d6410cbb0a4" args="(dwc_otg_core_if_t *core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_disable_host_interrupts           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function disables the Host Mode interrupts. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l01165">1165</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="04ad276f20faad71333f6293c952744e"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_core_host_init" ref="04ad276f20faad71333f6293c952744e" args="(dwc_otg_core_if_t *core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_core_host_init           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function initializes the DWC_otg controller registers for host mode. 
+<p>
+This function flushes the Tx and Rx FIFOs and it flushes any entries in the request queues. Host channels are reset to ensure that they are ready for performing transfers.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l01196">1196</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="7b04d5b3b31c79c73d577cfbb231998c"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_hc_init" ref="7b04d5b3b31c79c73d577cfbb231998c" args="(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_hc_init           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__hc.html">dwc_hc_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Prepares a host channel for transferring packets to/from a specific endpoint. 
+<p>
+The HCCHARn register is set up with the characteristics specified in _hc. Host channel interrupts that may need to be serviced while this transfer is in progress are enabled.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>hc</em>&nbsp;</td><td>Information needed to initialize the host channel </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l01352">1352</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="de044bf6b96c1bac92259a447ae85c0f"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_hc_halt" ref="de044bf6b96c1bac92259a447ae85c0f" args="(dwc_otg_core_if_t *core_if, dwc_hc_t *hc, dwc_otg_halt_status_e halt_status)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_hc_halt           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__hc.html">dwc_hc_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">dwc_otg_halt_status_e&nbsp;</td>
+          <td class="paramname"> <em>halt_status</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Attempts to halt a host channel. 
+<p>
+This function should only be called in Slave mode or to abort a transfer in either Slave mode or DMA mode. Under normal circumstances in DMA mode, the controller halts the channel when the transfer is complete or a condition occurs that requires application intervention.<p>
+In slave mode, checks for a free request queue entry, then sets the Channel Enable and Channel Disable bits of the Host Channel Characteristics register of the specified channel to intiate the halt. If there is no free request queue entry, sets only the Channel Disable bit of the HCCHARn register to flush requests for this channel. In the latter case, sets a flag to indicate that the host channel needs to be halted when a request queue slot is open.<p>
+In DMA mode, always sets the Channel Enable and Channel Disable bits of the HCCHARn register. The controller ensures there is space in the request queue before submitting the halt request.<p>
+Some time may elapse before the core flushes any posted requests for this host channel and halts. The Channel Halted interrupt handler completes the deactivation of the host channel.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Controller register interface. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>hc</em>&nbsp;</td><td>Host channel to halt. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>halt_status</em>&nbsp;</td><td>Reason for halting the channel. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l01540">1540</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="f05341f811fba7f6183db66faf50a867"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_hc_cleanup" ref="f05341f811fba7f6183db66faf50a867" args="(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_hc_cleanup           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__hc.html">dwc_hc_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Clears the transfer state for a host channel. 
+<p>
+This function is normally called after a transfer is done and the host channel is being released.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>hc</em>&nbsp;</td><td>Identifies the host channel to clean up. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l01667">1667</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="b2669551136671d3e4b6ad56bd947222"></a><!-- doxytag: member="dwc_otg_cil.c::hc_set_even_odd_frame" ref="b2669551136671d3e4b6ad56bd947222" args="(dwc_otg_core_if_t *core_if, dwc_hc_t *hc, hcchar_data_t *hcchar)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static void hc_set_even_odd_frame           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__hc.html">dwc_hc_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="unionhcchar__data.html">hcchar_data_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcchar</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [inline, static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Sets the channel property that indicates in which frame a periodic transfer should occur. 
+<p>
+This is always set to the _next_ frame. This function has no effect on non-periodic transfers.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>hc</em>&nbsp;</td><td>Identifies the host channel to set up and its properties. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>hcchar</em>&nbsp;</td><td>Current value of the HCCHAR register for the specified host channel. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l01695">1695</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="025af79d6a2255dba4578588be510444"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_hc_start_transfer" ref="025af79d6a2255dba4578588be510444" args="(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_hc_start_transfer           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__hc.html">dwc_hc_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function does the setup for a data transfer for a host channel and starts the transfer. 
+<p>
+May be called in either Slave mode or DMA mode. In Slave mode, the caller must ensure that there is sufficient space in the request queue and Tx Data FIFO.<p>
+For an OUT transfer in Slave mode, it loads a data packet into the appropriate FIFO. If necessary, additional data packets will be loaded in the Host ISR.<p>
+For an IN transfer in Slave mode, a data packet is requested. The data packets are unloaded from the Rx FIFO in the Host ISR. If necessary, additional data packets are requested in the Host ISR.<p>
+For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ register along with a packet count of 1 and the channel is enabled. This causes a single PING transaction to occur. Other fields in HCTSIZ are simply set to 0 since no data transfer occurs in this case.<p>
+For a PING transfer in DMA mode, the HCTSIZ register is initialized with all the information required to perform the subsequent data transfer. In addition, the Do Ping bit is set in the HCTSIZ register. In this case, the controller performs the entire PING protocol, then starts the data transfer.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>hc</em>&nbsp;</td><td>Information needed to initialize the host channel. The xfer_len value may be reduced to accommodate the max widths of the XferSize and PktCnt fields in the HCTSIZn register. The multi_count value may be changed to reflect the final xfer_len value. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l01800">1800</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="dbc20e9f9cadbdf4df65db3f82bbb820"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_hc_start_transfer_ddma" ref="dbc20e9f9cadbdf4df65db3f82bbb820" args="(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_hc_start_transfer_ddma           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__hc.html">dwc_hc_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function does the setup for a data transfer for a host channel and starts the transfer in Descriptor DMA mode. 
+<p>
+Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set. Sets PID and NTD values. For periodic transfers initializes SCHED_INFO field with micro-frame bitmap.<p>
+Initializes HCDMA register with descriptor list address and CTD value then starts the transfer via enabling the channel.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>hc</em>&nbsp;</td><td>Information needed to initialize the host channel. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l01968">1968</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="d848c41cdd739edd9271e1e207af9c9c"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_hc_continue_transfer" ref="d848c41cdd739edd9271e1e207af9c9c" args="(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_hc_continue_transfer           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__hc.html">dwc_hc_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function continues a data transfer that was started by previous call to <code>dwc_otg_hc_start_transfer</code>. 
+<p>
+The caller must ensure there is sufficient space in the request queue and Tx Data FIFO. This function should only be called in Slave mode. In DMA mode, the controller acts autonomously to complete transfers programmed to a host channel.<p>
+For an OUT transfer, a new data packet is loaded into the appropriate FIFO if there is any data remaining to be queued. For an IN transfer, another data packet is always requested. For the SETUP phase of a control transfer, this function does nothing.<p>
+<dl compact><dt><b>Returns:</b></dt><dd>1 if a new request is queued, 0 if no more requests are required for this transfer. </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l02048">2048</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="4185d0b9bb4a49d28894f957c2e41117"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_hc_do_ping" ref="4185d0b9bb4a49d28894f957c2e41117" args="(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_hc_do_ping           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__hc.html">dwc_hc_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Starts a PING transfer. 
+<p>
+This function should only be called in Slave mode. The Do Ping bit is set in the HCTSIZ register, then the channel is enabled. 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l02110">2110</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="78f20f3acf6245b189abde83d9ce78f2"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_frame_number" ref="78f20f3acf6245b189abde83d9ce78f2" args="(dwc_otg_core_if_t *core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t dwc_otg_get_frame_number           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Gets the current USB frame number. 
+<p>
+This is the frame number from the last SOF packet. 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l02182">2182</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="b56e0d90c67bbf2829e630cafd630f17"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_read_setup_packet" ref="b56e0d90c67bbf2829e630cafd630f17" args="(dwc_otg_core_if_t *core_if, uint32_t *dest)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_read_setup_packet           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint32_t *&nbsp;</td>
+          <td class="paramname"> <em>dest</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function reads a setup packet from the Rx FIFO into the destination buffer. 
+<p>
+This function is called from the Rx Status Queue Level (RxStsQLvl) Interrupt routine when a SETUP packet has been received in Slave mode.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>dest</em>&nbsp;</td><td>Destination buffer for packet data. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l02199">2199</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="8ebf5023c783a2ec48a18a5b9aef4a87"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_ep0_activate" ref="8ebf5023c783a2ec48a18a5b9aef4a87" args="(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_ep0_activate           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__ep.html">dwc_ep_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>ep</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function enables EP0 OUT to receive SETUP packets and configures EP0 IN for transmitting packets. 
+<p>
+It is normally called when the "Enumeration Done" interrupt occurs.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep</em>&nbsp;</td><td>The EP0 data. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l02216">2216</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="5e5a1fb1ff70d5c42d8cf4a1c5d12b7f"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_ep_activate" ref="5e5a1fb1ff70d5c42d8cf4a1c5d12b7f" args="(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_ep_activate           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__ep.html">dwc_ep_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>ep</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function activates an EP. 
+<p>
+The Device EP control register for the EP is configured as defined in the ep structure. Note: This function is not used for EP0.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep</em>&nbsp;</td><td>The EP to activate. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l02268">2268</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="94789f2d72adb5daf65c99eadced66b3"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_ep_deactivate" ref="94789f2d72adb5daf65c99eadced66b3" args="(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_ep_deactivate           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__ep.html">dwc_ep_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>ep</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function deactivates an EP. 
+<p>
+This is done by clearing the USB Active EP bit in the Device EP control register. Note: This function is not used for EP0. EP0 cannot be deactivated.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep</em>&nbsp;</td><td>The EP to deactivate. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l02367">2367</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="50a39773d3477ca76a71787e27400d7a"></a><!-- doxytag: member="dwc_otg_cil.c::init_dma_desc_chain" ref="50a39773d3477ca76a71787e27400d7a" args="(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static void init_dma_desc_chain           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__ep.html">dwc_ep_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>ep</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function initializes dma descriptor chain. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep</em>&nbsp;</td><td>The EP to start the transfer on. </td></tr>
+  </table>
+</dl>
+
+<p>
+DMA Descriptor Setup 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l02415">2415</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="1278f6d58a4a2bc780e90e0b6c9b9a68"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_ep_start_transfer" ref="1278f6d58a4a2bc780e90e0b6c9b9a68" args="(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_ep_start_transfer           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__ep.html">dwc_ep_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>ep</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function does the setup for a data transfer for an EP and starts the transfer. 
+<p>
+For an IN transfer, the packets will be loaded into the appropriate Tx FIFO in the ISR. For OUT transfers, the packets are unloaded from the Rx FIFO in the ISR. the ISR.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep</em>&nbsp;</td><td>The EP to start the transfer on. </td></tr>
+  </table>
+</dl>
+
+<p>
+DIEPDMAn Register write<p>
+Enable the Non-Periodic Tx FIFO empty interrupt, or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode, the data will be written into the fifo by the ISR.<p>
+DOEPDMAn Register write 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l02475">2475</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="fcc9f9b12c040c3649f0b8273a24ddf7"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_ep_start_zl_transfer" ref="fcc9f9b12c040c3649f0b8273a24ddf7" args="(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_ep_start_zl_transfer           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__ep.html">dwc_ep_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>ep</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function setup a zero length transfer in Buffer DMA and Slave modes for usb requests with zero field set. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep</em>&nbsp;</td><td>The EP to start the transfer on. </td></tr>
+  </table>
+</dl>
+
+<p>
+Enable the Non-Periodic Tx FIFO empty interrupt, or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode, the data will be written into the fifo by the ISR. 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l02678">2678</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="ee4989b24826b2a6592535282853e556"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_ep0_start_transfer" ref="ee4989b24826b2a6592535282853e556" args="(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_ep0_start_transfer           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__ep.html">dwc_ep_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>ep</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function does the setup for a data transfer for EP0 and starts the transfer. 
+<p>
+For an IN transfer, the packets will be loaded into the appropriate Tx FIFO in the ISR. For OUT transfers, the packets are unloaded from the Rx FIFO in the ISR.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep</em>&nbsp;</td><td>The EP0 data. </td></tr>
+  </table>
+</dl>
+
+<p>
+DMA Descriptor Setup<p>
+DIEPDMA0 Register write<p>
+Enable the Non-Periodic Tx FIFO empty interrupt, the data will be written into the fifo by the ISR.<p>
+DMA Descriptor Setup<p>
+DOEPDMA0 Register write 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l02785">2785</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="d8c1e6f7860c482df84db003b52c369c"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_ep0_continue_transfer" ref="d8c1e6f7860c482df84db003b52c369c" args="(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_ep0_continue_transfer           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__ep.html">dwc_ep_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>ep</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function continues control IN transfers started by dwc_otg_ep0_start_transfer, when the transfer does not fit in a single packet. 
+<p>
+NOTE: The DIEPCTL0/DOEPCTL0 registers only have one bit for the packet count.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep</em>&nbsp;</td><td>The EP0 data. </td></tr>
+  </table>
+</dl>
+
+<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000009">Todo:</a></b></dt><dd>Should there be check for room in the Tx Status Queue. If not remove the code above this comment. </dd></dl>
+<p>
+DMA Descriptor Setup<p>
+DIEPDMA0 Register write<p>
+Enable the Non-Periodic Tx FIFO empty interrupt, the data will be written into the fifo by the ISR.<p>
+DMA Descriptor Setup<p>
+DOEPDMA0 Register write 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l02969">2969</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="97a11808b8b12a365a91f02b6d686d0c"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_ep_write_packet" ref="97a11808b8b12a365a91f02b6d686d0c" args="(dwc_otg_core_if_t *core_if, dwc_ep_t *ep, int dma)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_ep_write_packet           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__ep.html">dwc_ep_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>ep</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>dma</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function writes a packet into the Tx FIFO associated with the EP. 
+<p>
+For non-periodic EPs the non-periodic Tx FIFO is written. For periodic EPs the periodic Tx FIFO associated with the EP is written with all packets for the next micro-frame.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep</em>&nbsp;</td><td>The EP to write packet for. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>dma</em>&nbsp;</td><td>Indicates if DMA is being used. </td></tr>
+  </table>
+</dl>
+
+<p>
+The buffer is padded to DWORD on a per packet basis in slave/dma mode if the MPS is not DWORD aligned. The last packet, if short, is also padded to a multiple of DWORD.<p>
+ep-&gt;xfer_buff always starts DWORD aligned in memory and is a multiple of DWORD in length<p>
+ep-&gt;xfer_len can be any number of bytes<p>
+ep-&gt;xfer_count is a multiple of ep-&gt;maxpacket until the last packet<p>
+FIFO access is DWORD<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000010">Todo:</a></b></dt><dd>NGS Where are the Periodic Tx FIFO addresses intialized? What should this be? </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l03165">3165</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="5edca13178261136209ed51360c850b4"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_ep_set_stall" ref="5edca13178261136209ed51360c850b4" args="(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_ep_set_stall           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__ep.html">dwc_ep_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>ep</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Set the EP STALL. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep</em>&nbsp;</td><td>The EP to set the stall on. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l03236">3236</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="a5f77318fb1c589406927a606844007f"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_ep_clear_stall" ref="a5f77318fb1c589406927a606844007f" args="(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_ep_clear_stall           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__ep.html">dwc_ep_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>ep</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Clear the EP STALL. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep</em>&nbsp;</td><td>The EP to clear stall from. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l03274">3274</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="68f59dd23ccfffa9aa1dc590e99b7668"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_read_packet" ref="68f59dd23ccfffa9aa1dc590e99b7668" args="(dwc_otg_core_if_t *core_if, uint8_t *dest, uint16_t bytes)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_read_packet           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>dest</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint16_t&nbsp;</td>
+          <td class="paramname"> <em>bytes</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function reads a packet from the Rx FIFO into the destination buffer. 
+<p>
+To read SETUP data use dwc_otg_read_setup_packet.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>dest</em>&nbsp;</td><td>Destination buffer for the packet. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>bytes</em>&nbsp;</td><td>Number of bytes to copy to the destination. </td></tr>
+  </table>
+</dl>
+
+<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000011">Todo:</a></b></dt><dd>Account for the case where _dest is not dword aligned. This requires reading data from the FIFO into a uint32_t temp buffer, then moving it into the data buffer. </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l03317">3317</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="ea3bce6af9d0bd9b2fb6de94f1c7a133"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_dump_dev_registers" ref="ea3bce6af9d0bd9b2fb6de94f1c7a133" args="(dwc_otg_core_if_t *core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_dump_dev_registers           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Dump core registers and SPRAM. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l03347">3347</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="393e65ddcbaed38935ea06fb7451167b"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_dump_spram" ref="393e65ddcbaed38935ea06fb7451167b" args="(dwc_otg_core_if_t *core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_dump_spram           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This functions reads the SPRAM and prints its content. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l03477">3477</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="e85d3d04799b17226fcb00ea2074ca63"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_dump_host_registers" ref="e85d3d04799b17226fcb00ea2074ca63" args="(dwc_otg_core_if_t *core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_dump_host_registers           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function reads the host registers and prints them. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l03505">3505</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="118ecda931e2b745f76fde129ff707c2"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_dump_global_registers" ref="118ecda931e2b745f76fde129ff707c2" args="(dwc_otg_core_if_t *core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_dump_global_registers           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function reads the core global registers and prints them. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l03573">3573</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="039e387cd0e0282727da3c5a36f4cdda"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_flush_tx_fifo" ref="039e387cd0e0282727da3c5a36f4cdda" args="(dwc_otg_core_if_t *core_if, const int num)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_flush_tx_fifo           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">const int&nbsp;</td>
+          <td class="paramname"> <em>num</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Flush a Tx FIFO. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>num</em>&nbsp;</td><td>Tx FIFO to flush. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l03662">3662</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="fb275f0f9923cc30629fce5e3753025c"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_flush_rx_fifo" ref="fb275f0f9923cc30629fce5e3753025c" args="(dwc_otg_core_if_t *core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_flush_rx_fifo           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Flush Rx FIFO. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l03694">3694</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="1edfc5634dd76db76e30f20affc10f0c"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_core_reset" ref="1edfc5634dd76db76e30f20affc10f0c" args="(dwc_otg_core_if_t *core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_core_reset           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Do core a soft reset of the core. 
+<p>
+Be careful with this because it resets all the internal state machines of the core. 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l03725">3725</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="97c9b9d68211477e486848203def0d0f"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_cil_register_hcd_callbacks" ref="97c9b9d68211477e486848203def0d0f" args="(dwc_otg_core_if_t *core_if, dwc_otg_cil_callbacks_t *cb, void *p)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_cil_register_hcd_callbacks           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__cil__callbacks.html">dwc_otg_cil_callbacks_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>cb</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>p</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Register HCD callbacks. 
+<p>
+The callbacks are used to start and stop the HCD for interrupt processing.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>cb</em>&nbsp;</td><td>the HCD callback structure. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>p</em>&nbsp;</td><td>pointer to be passed to callback function (usb_hcd*). </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l03781">3781</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="d2a92003214f444d7ec35dd0c4bb4bc0"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_cil_register_pcd_callbacks" ref="d2a92003214f444d7ec35dd0c4bb4bc0" args="(dwc_otg_core_if_t *core_if, dwc_otg_cil_callbacks_t *cb, void *p)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_cil_register_pcd_callbacks           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__cil__callbacks.html">dwc_otg_cil_callbacks_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>cb</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>p</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Register PCD callbacks. 
+<p>
+The callbacks are used to start and stop the PCD for interrupt processing.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>cb</em>&nbsp;</td><td>the PCD callback structure. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>p</em>&nbsp;</td><td>pointer to be passed to callback function (pcd*). </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l03796">3796</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="e39d47d3aee9efcd525c13ce6a1f5f6a"></a><!-- doxytag: member="dwc_otg_cil.c::write_isoc_frame_data" ref="e39d47d3aee9efcd525c13ce6a1f5f6a" args="(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void write_isoc_frame_data           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__ep.html">dwc_ep_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>ep</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function writes isoc data per 1 (micro)frame into tx fifo. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep</em>&nbsp;</td><td>The EP to start the transfer on. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l03812">3812</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="0f0894ae9890260e1da839aa10af35cc"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_iso_ep_start_frm_transfer" ref="0f0894ae9890260e1da839aa10af35cc" args="(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_iso_ep_start_frm_transfer           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__ep.html">dwc_ep_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>ep</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function initializes a descriptor chain for Isochronous transfer. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep</em>&nbsp;</td><td>The EP to start the transfer on. </td></tr>
+  </table>
+</dl>
+
+<p>
+Enable endpoint, clear nak 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l03864">3864</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="878cc478f43c58991c446bd78f50f8f0"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_set_param_otg_cap" ref="878cc478f43c58991c446bd78f50f8f0" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_set_param_otg_cap           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&nbsp;</td>
+          <td class="paramname"> <em>val</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Specifies the OTG capabilities. 
+<p>
+The driver will automatically detect the value for this parameter if none is specified. 0 - HNP and SRP capable (default) 1 - SRP Only capable 2 - No HNP/SRP capable 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l04056">4056</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="b4fbe11281b8200b70202d4e0048a9d7"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_set_param_dma_enable" ref="b4fbe11281b8200b70202d4e0048a9d7" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_set_param_dma_enable           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&nbsp;</td>
+          <td class="paramname"> <em>val</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Specifies whether to use slave or DMA mode for accessing the data FIFOs. 
+<p>
+The driver will automatically detect the value for this parameter if none is specified. 0 - Slave 1 - DMA (default, if available) 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l04135">4135</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="7eae744525314774d3b390f116db126c"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_set_param_dma_desc_enable" ref="7eae744525314774d3b390f116db126c" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_set_param_dma_desc_enable           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&nbsp;</td>
+          <td class="paramname"> <em>val</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+When DMA mode is enabled specifies whether to use address DMA or DMA Descritor mode for accessing the data FIFOs in device mode. 
+<p>
+The driver will automatically detect the value for this parameter if none is specified. 0 - address DMA 1 - DMA Descriptor(default, if available) 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l04165">4165</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="8bd669637630521655c455c03d470e10"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_set_param_host_support_fs_ls_low_power" ref="8bd669637630521655c455c03d470e10" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_set_param_host_support_fs_ls_low_power           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&nbsp;</td>
+          <td class="paramname"> <em>val</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Specifies whether low power mode is supported when attached to a Full Speed or Low Speed device in host mode. 
+<p>
+0 - Don't support low power mode (default) 1 - Support low power mode 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l04195">4195</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="69d52c46eb236816b20675ecb57975ae"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_set_param_data_fifo_size" ref="69d52c46eb236816b20675ecb57975ae" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_set_param_data_fifo_size           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&nbsp;</td>
+          <td class="paramname"> <em>val</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Total number of 4-byte words in the data FIFO memory. 
+<p>
+This memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs. 32 to 32768 (default 8192) Note: The total FIFO memory depth in the FPGA configuration is 8192. 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l04242">4242</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="0fa4db196053869ac19832c03c62913f"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_set_param_dev_rx_fifo_size" ref="0fa4db196053869ac19832c03c62913f" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_set_param_dev_rx_fifo_size           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&nbsp;</td>
+          <td class="paramname"> <em>val</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Number of 4-byte words in the Rx FIFO in device mode when dynamic FIFO sizing is enabled. 
+<p>
+16 to 32768 (default 1064) 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l04271">4271</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="4f7059cecabbf8cfe5014112ba9a3d42"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_set_param_dev_nperio_tx_fifo_size" ref="4f7059cecabbf8cfe5014112ba9a3d42" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_set_param_dev_nperio_tx_fifo_size           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&nbsp;</td>
+          <td class="paramname"> <em>val</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Number of 4-byte words in the non-periodic Tx FIFO in device mode when dynamic FIFO sizing is enabled. 
+<p>
+16 to 32768 (default 1024) 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l04297">4297</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="254c1e97cf22fe34b7383165e30071eb"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_set_param_host_rx_fifo_size" ref="254c1e97cf22fe34b7383165e30071eb" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_set_param_host_rx_fifo_size           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&nbsp;</td>
+          <td class="paramname"> <em>val</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO sizing is enabled. 
+<p>
+16 to 32768 (default 1024) 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l04330">4330</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="a66ca9f9345a13606148b050f8690a56"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_set_param_host_nperio_tx_fifo_size" ref="a66ca9f9345a13606148b050f8690a56" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_set_param_host_nperio_tx_fifo_size           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&nbsp;</td>
+          <td class="paramname"> <em>val</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Number of 4-byte words in the non-periodic Tx FIFO in host mode when Dynamic FIFO sizing is enabled in the core. 
+<p>
+16 to 32768 (default 1024) 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l04362">4362</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="e4ce399208d8a85dcb9dedd1fb8cd8ce"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_set_param_host_perio_tx_fifo_size" ref="e4ce399208d8a85dcb9dedd1fb8cd8ce" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_set_param_host_perio_tx_fifo_size           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&nbsp;</td>
+          <td class="paramname"> <em>val</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO sizing is enabled. 
+<p>
+16 to 32768 (default 1024) 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l04395">4395</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="2eee676071d6bb4eba53b413e80b045f"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_set_param_max_transfer_size" ref="2eee676071d6bb4eba53b413e80b045f" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_set_param_max_transfer_size           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&nbsp;</td>
+          <td class="paramname"> <em>val</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+The maximum transfer size supported in bytes. 
+<p>
+2047 to 65,535 (default 65,535) 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l04428">4428</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="a1c52f0740f7d0b72c980b38cc4314d1"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_set_param_max_packet_count" ref="a1c52f0740f7d0b72c980b38cc4314d1" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_set_param_max_packet_count           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&nbsp;</td>
+          <td class="paramname"> <em>val</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+The maximum number of packets in a transfer. 
+<p>
+15 to 511 (default 511) 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l04461">4461</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="f802acfc49b3fbb86159036f8f317f76"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_set_param_host_channels" ref="f802acfc49b3fbb86159036f8f317f76" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_set_param_host_channels           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&nbsp;</td>
+          <td class="paramname"> <em>val</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+The number of host channel registers to use. 
+<p>
+1 to 16 (default 12) Note: The FPGA configuration supports a maximum of 12 host channels. 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l04492">4492</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="75d3b409824c0ca52631277398ba8367"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_set_param_dev_endpoints" ref="75d3b409824c0ca52631277398ba8367" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_set_param_dev_endpoints           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&nbsp;</td>
+          <td class="paramname"> <em>val</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+The number of endpoints in addition to EP0 available for device mode operations. 
+<p>
+1 to 15 (default 6 IN and OUT) Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in addition to EP0. 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l04522">4522</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="2b7087c85c0ea1520ec2e091b80bf36b"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_set_param_phy_type" ref="2b7087c85c0ea1520ec2e091b80bf36b" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_set_param_phy_type           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&nbsp;</td>
+          <td class="paramname"> <em>val</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Specifies the type of PHY interface to use. 
+<p>
+By default, the driver will automatically detect the phy_type.<p>
+0 - Full Speed PHY 1 - UTMI+ (default) 2 - ULPI 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l04552">4552</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="7acd153b5577a3db825fa08d243ae856"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_set_param_speed" ref="7acd153b5577a3db825fa08d243ae856" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_set_param_speed           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&nbsp;</td>
+          <td class="paramname"> <em>val</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Specifies the maximum speed of operation in host and device mode. 
+<p>
+The actual speed depends on the speed of the attached device and the value of phy_type. The actual speed depends on the speed of the attached device. 0 - High Speed (default) 1 - Full Speed 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l04601">4601</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="354ce49f65334e829c2694811c4f2016"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_set_param_host_ls_low_power_phy_clk" ref="354ce49f65334e829c2694811c4f2016" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_set_param_host_ls_low_power_phy_clk           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&nbsp;</td>
+          <td class="paramname"> <em>val</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Specifies the PHY clock rate in low power mode when connected to a Low Speed device in host mode. 
+<p>
+This parameter is applicable only if HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS then defaults to 6 MHZ otherwise 48 MHZ.<p>
+0 - 48 MHz 1 - 6 MHz 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l04630">4630</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="5dab15db053bd02c6bc9619e189a6a14"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_set_param_phy_ulpi_ddr" ref="5dab15db053bd02c6bc9619e189a6a14" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_set_param_phy_ulpi_ddr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&nbsp;</td>
+          <td class="paramname"> <em>val</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Specifies whether the ULPI operates at double or single data rate. 
+<p>
+This parameter is only applicable if PHY_TYPE is ULPI.<p>
+0 - single data rate ULPI interface with 8 bit wide data bus (default) 1 - double data rate ULPI interface with 4 bit wide data bus 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l04665">4665</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="1eacecc96e1ab100cbf129ad6aa5f6c8"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_set_param_phy_utmi_width" ref="1eacecc96e1ab100cbf129ad6aa5f6c8" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_set_param_phy_utmi_width           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&nbsp;</td>
+          <td class="paramname"> <em>val</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Specifies the UTMI+ Data Width. 
+<p>
+This parameter is applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI PHY_TYPE, this parameter indicates the data width between the MAC and the ULPI Wrapper.) Also, this parameter is applicable only if the OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the core has been configured to work at either data path width.<p>
+8 or 16 bits (default 16) 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l04700">4700</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="65d7407ed24c82e158a38ab2a60120c4"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_set_param_i2c_enable" ref="65d7407ed24c82e158a38ab2a60120c4" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_set_param_i2c_enable           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&nbsp;</td>
+          <td class="paramname"> <em>val</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Specifies whether to use the I2Cinterface for full speed PHY. 
+<p>
+This parameter is only applicable if PHY_TYPE is FS. 0 - No (default) 1 - Yes 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l04751">4751</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="2119a493582bea4004b5fdeba15f1609"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_set_param_dev_perio_tx_fifo_size" ref="2119a493582bea4004b5fdeba15f1609" args="(dwc_otg_core_if_t *core_if, int32_t val, int fifo_num)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_set_param_dev_perio_tx_fifo_size           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&nbsp;</td>
+          <td class="paramname"> <em>val</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>fifo_num</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Number of 4-byte words in each of the periodic Tx FIFOs in device mode when dynamic FIFO sizing is enabled. 
+<p>
+4 to 768 (default 256) 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l04779">4779</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="920035c6082dcdfec11a20e8535e9fe9"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_set_param_dma_burst_size" ref="920035c6082dcdfec11a20e8535e9fe9" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_set_param_dma_burst_size           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&nbsp;</td>
+          <td class="paramname"> <em>val</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+The DMA Burst size (applicable only for External DMA Mode). 
+<p>
+1, 4, 8 16, 32, 64, 128, 256 (default 32) 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l04959">4959</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="788149caf9d915abbe5e289793684b1e"></a><!-- doxytag: member="dwc_otg_cil.c::dwc_otg_get_mode" ref="788149caf9d915abbe5e289793684b1e" args="(dwc_otg_core_if_t *core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t dwc_otg_get_mode           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Get current mode. 
+<p>
+Returns 0 if in device mode, and 1 if in host mode. 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l05115">5115</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil_8h-source.html b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil_8h-source.html
new file mode 100644
index 000000000000..bfe829d972e0
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil_8h-source.html
@@ -0,0 +1,709 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_cil.h Source File</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<h1>dwc_otg_cil.h</h1><a href="dwc__otg__cil_8h.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">/* ==========================================================================</span>
+<a name="l00002"></a>00002 <span class="comment"> * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.h $</span>
+<a name="l00003"></a>00003 <span class="comment"> * $Revision: #99 $</span>
+<a name="l00004"></a>00004 <span class="comment"> * $Date: 2009/04/21 $</span>
+<a name="l00005"></a>00005 <span class="comment"> * $Change: 1237466 $</span>
+<a name="l00006"></a>00006 <span class="comment"> *</span>
+<a name="l00007"></a>00007 <span class="comment"> * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,</span>
+<a name="l00008"></a>00008 <span class="comment"> * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless</span>
+<a name="l00009"></a>00009 <span class="comment"> * otherwise expressly agreed to in writing between Synopsys and you.</span>
+<a name="l00010"></a>00010 <span class="comment"> * </span>
+<a name="l00011"></a>00011 <span class="comment"> * The Software IS NOT an item of Licensed Software or Licensed Product under</span>
+<a name="l00012"></a>00012 <span class="comment"> * any End User Software License Agreement or Agreement for Licensed Product</span>
+<a name="l00013"></a>00013 <span class="comment"> * with Synopsys or any supplement thereto. You are permitted to use and</span>
+<a name="l00014"></a>00014 <span class="comment"> * redistribute this Software in source and binary forms, with or without</span>
+<a name="l00015"></a>00015 <span class="comment"> * modification, provided that redistributions of source code must retain this</span>
+<a name="l00016"></a>00016 <span class="comment"> * notice. You may not view, use, disclose, copy or distribute this file or</span>
+<a name="l00017"></a>00017 <span class="comment"> * any information contained herein except pursuant to this license grant from</span>
+<a name="l00018"></a>00018 <span class="comment"> * Synopsys. If you do not agree with this notice, including the disclaimer</span>
+<a name="l00019"></a>00019 <span class="comment"> * below, then you are not authorized to use the Software.</span>
+<a name="l00020"></a>00020 <span class="comment"> * </span>
+<a name="l00021"></a>00021 <span class="comment"> * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS</span>
+<a name="l00022"></a>00022 <span class="comment"> * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE</span>
+<a name="l00023"></a>00023 <span class="comment"> * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE</span>
+<a name="l00024"></a>00024 <span class="comment"> * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,</span>
+<a name="l00025"></a>00025 <span class="comment"> * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES</span>
+<a name="l00026"></a>00026 <span class="comment"> * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR</span>
+<a name="l00027"></a>00027 <span class="comment"> * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER</span>
+<a name="l00028"></a>00028 <span class="comment"> * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT</span>
+<a name="l00029"></a>00029 <span class="comment"> * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY</span>
+<a name="l00030"></a>00030 <span class="comment"> * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH</span>
+<a name="l00031"></a>00031 <span class="comment"> * DAMAGE.</span>
+<a name="l00032"></a>00032 <span class="comment"> * ========================================================================== */</span>
+<a name="l00033"></a>00033 
+<a name="l00034"></a>00034 <span class="preprocessor">#if !defined(__DWC_CIL_H__)</span>
+<a name="l00035"></a><a class="code" href="dwc__otg__cil_8h.html#c9555551bb7f2d0a51be23d54463f2ec">00035</a> <span class="preprocessor"></span><span class="preprocessor">#define __DWC_CIL_H__</span>
+<a name="l00036"></a>00036 <span class="preprocessor"></span>
+<a name="l00037"></a>00037 <span class="preprocessor">#include "dwc_os.h"</span>
+<a name="l00038"></a>00038 <span class="preprocessor">#include "dwc_list.h"</span>
+<a name="l00039"></a>00039 <span class="preprocessor">#include "<a class="code" href="dwc__otg__dbg_8h.html">dwc_otg_dbg.h</a>"</span>
+<a name="l00040"></a>00040 <span class="preprocessor">#include "<a class="code" href="dwc__otg__regs_8h.html">dwc_otg_regs.h</a>"</span>
+<a name="l00041"></a>00041 
+<a name="l00042"></a>00042 <span class="preprocessor">#include "<a class="code" href="dwc__otg__core__if_8h.html">dwc_otg_core_if.h</a>"</span>
+<a name="l00043"></a>00043 
+<a name="l00049"></a>00049 <span class="preprocessor">#ifdef DWC_UTE_CFI</span>
+<a name="l00050"></a>00050 <span class="preprocessor"></span>
+<a name="l00051"></a>00051 <span class="preprocessor">#define MAX_DMA_DESCS_PER_EP    256</span>
+<a name="l00052"></a>00052 <span class="preprocessor"></span>
+<a name="l00056"></a>00056 <span class="keyword">typedef</span> <span class="keyword">enum</span> _data_buffer_mode {
+<a name="l00057"></a>00057         BM_STANDARD = 0,        <span class="comment">/* data buffer is in normal mode */</span>
+<a name="l00058"></a>00058         BM_SG = 1,              <span class="comment">/* data buffer uses the scatter/gather mode */</span>
+<a name="l00059"></a>00059         BM_CONCAT = 2,          <span class="comment">/* data buffer uses the concatenation mode */</span>
+<a name="l00060"></a>00060         BM_CIRCULAR = 3,        <span class="comment">/* data buffer uses the circular DMA mode */</span>
+<a name="l00061"></a>00061         BM_ALIGN = 4            <span class="comment">/* data buffer is in buffer alignment mode */</span>
+<a name="l00062"></a>00062 } data_buffer_mode_e;
+<a name="l00063"></a>00063 <span class="preprocessor">#endif                          //DWC_UTE_CFI</span>
+<a name="l00064"></a>00064 <span class="preprocessor"></span>
+<a name="l00067"></a><a class="code" href="dwc__otg__cil_8h.html#51536e4844fe9022b60531eebca32a26">00067</a> <span class="preprocessor">#define OTG_CORE_REV_2_60a      0x4F54260A</span>
+<a name="l00068"></a><a class="code" href="dwc__otg__cil_8h.html#aac1e3cc465029aa0a2965b7c6d9fc50">00068</a> <span class="preprocessor"></span><span class="preprocessor">#define OTG_CORE_REV_2_71a      0x4F54271A</span>
+<a name="l00069"></a><a class="code" href="dwc__otg__cil_8h.html#3d25615a19f95042bcc3512b4855cebe">00069</a> <span class="preprocessor"></span><span class="preprocessor">#define OTG_CORE_REV_2_72a      0x4F54272A</span>
+<a name="l00070"></a><a class="code" href="dwc__otg__cil_8h.html#02c75ff58b0b88ae59c89063478648dd">00070</a> <span class="preprocessor"></span><span class="preprocessor">#define OTG_CORE_REV_2_80a      0x4F54280A</span>
+<a name="l00071"></a><a class="code" href="dwc__otg__cil_8h.html#ceb592db3a34e7435e6bd9fc4cf5627c">00071</a> <span class="preprocessor"></span><span class="preprocessor">#define OTG_CORE_REV_2_81a      0x4F54281A</span>
+<a name="l00072"></a><a class="code" href="dwc__otg__cil_8h.html#c2f4aa7b1cfc164330925404c5029724">00072</a> <span class="preprocessor"></span><span class="preprocessor">#define OTG_CORE_REV_2_90a      0x4F54290A              </span>
+<a name="l00073"></a>00073 <span class="preprocessor"></span>
+<a name="l00077"></a><a class="code" href="structiso__pkt__info.html">00077</a> <span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code" href="structiso__pkt__info.html">iso_pkt_info</a> {
+<a name="l00078"></a><a class="code" href="structiso__pkt__info.html#0c72a0585ccc93555da4db7e168f75f8">00078</a>         uint32_t <a class="code" href="structiso__pkt__info.html#0c72a0585ccc93555da4db7e168f75f8">offset</a>;
+<a name="l00079"></a><a class="code" href="structiso__pkt__info.html#ced82142e81778345016841e15020eb8">00079</a>         uint32_t <a class="code" href="structiso__pkt__info.html#ced82142e81778345016841e15020eb8">length</a>;
+<a name="l00080"></a><a class="code" href="structiso__pkt__info.html#1317c3b425c0ef55dbde153b04c28dd4">00080</a>         int32_t <a class="code" href="structiso__pkt__info.html#1317c3b425c0ef55dbde153b04c28dd4">status</a>;
+<a name="l00081"></a>00081 } <a class="code" href="structiso__pkt__info.html">iso_pkt_info_t</a>;
+<a name="l00082"></a>00082 
+<a name="l00088"></a><a class="code" href="structdwc__ep.html">00088</a> <span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code" href="structdwc__ep.html">dwc_ep</a> {
+<a name="l00090"></a><a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">00090</a>         uint8_t <a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a>;
+<a name="l00092"></a><a class="code" href="structdwc__ep.html#b882b6b7c857100ed20600e94ea37760">00092</a>         <span class="keywordtype">unsigned</span> <a class="code" href="structdwc__ep.html#b882b6b7c857100ed20600e94ea37760">is_in</a>:1;
+<a name="l00094"></a><a class="code" href="structdwc__ep.html#63b7a1a3ee32df393ff10d8bfc5c8648">00094</a>         <span class="keywordtype">unsigned</span> <a class="code" href="structdwc__ep.html#63b7a1a3ee32df393ff10d8bfc5c8648">active</a>:1;
+<a name="l00095"></a>00095 
+<a name="l00098"></a><a class="code" href="structdwc__ep.html#ffa14f48094778143353b845b5d238cd">00098</a>         <span class="keywordtype">unsigned</span> <a class="code" href="structdwc__ep.html#ffa14f48094778143353b845b5d238cd">tx_fifo_num</a>:4;
+<a name="l00100"></a><a class="code" href="structdwc__ep.html#17b10677bd9b0a1d612dd4ce2fb0eb0f">00100</a>         <span class="keywordtype">unsigned</span> <a class="code" href="structdwc__ep.html#17b10677bd9b0a1d612dd4ce2fb0eb0f">type</a>:2;
+<a name="l00101"></a><a class="code" href="dwc__otg__cil_8h.html#64e5cd756330f5adab79b25cc8067bdc">00101</a> <span class="preprocessor">#define DWC_OTG_EP_TYPE_CONTROL    0</span>
+<a name="l00102"></a><a class="code" href="dwc__otg__cil_8h.html#152a3a5e1433bd2197672f0b5105e7a4">00102</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_OTG_EP_TYPE_ISOC       1</span>
+<a name="l00103"></a><a class="code" href="dwc__otg__cil_8h.html#9b079858cda0b917316ad9161b3881e0">00103</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_OTG_EP_TYPE_BULK       2</span>
+<a name="l00104"></a><a class="code" href="dwc__otg__cil_8h.html#1401d1264f88530232cf51ab31cc5347">00104</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_OTG_EP_TYPE_INTR       3</span>
+<a name="l00105"></a>00105 <span class="preprocessor"></span>
+<a name="l00107"></a><a class="code" href="structdwc__ep.html#4ceafa9e067ba462ab38c20ffcf8d597">00107</a>         <span class="keywordtype">unsigned</span> <a class="code" href="structdwc__ep.html#4ceafa9e067ba462ab38c20ffcf8d597">data_pid_start</a>:1;
+<a name="l00109"></a><a class="code" href="structdwc__ep.html#0692ad9970f4ff48b4210577a6bf86ee">00109</a>         <span class="keywordtype">unsigned</span> <a class="code" href="structdwc__ep.html#0692ad9970f4ff48b4210577a6bf86ee">even_odd_frame</a>:1;
+<a name="l00111"></a><a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">00111</a>         <span class="keywordtype">unsigned</span> <a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a>:11;
+<a name="l00112"></a>00112 
+<a name="l00114"></a><a class="code" href="structdwc__ep.html#f60095e5ebedf7f98f3bfea77ce9a755">00114</a>         uint32_t <a class="code" href="structdwc__ep.html#f60095e5ebedf7f98f3bfea77ce9a755">maxxfer</a>;
+<a name="l00115"></a>00115 
+<a name="l00124"></a><a class="code" href="structdwc__ep.html#b40ce70422b6d105a855a8df4b33d45d">00124</a>         dwc_dma_t <a class="code" href="structdwc__ep.html#b40ce70422b6d105a855a8df4b33d45d">dma_addr</a>;
+<a name="l00125"></a>00125 
+<a name="l00126"></a><a class="code" href="structdwc__ep.html#1a43e464429530e874472092e0e1af09">00126</a>         dwc_dma_t <a class="code" href="structdwc__ep.html#1a43e464429530e874472092e0e1af09">dma_desc_addr</a>;
+<a name="l00127"></a><a class="code" href="structdwc__ep.html#57e934b26e76939912eaa76321075a0d">00127</a>         <a class="code" href="structdwc__otg__dev__dma__desc.html">dwc_otg_dev_dma_desc_t</a> *<a class="code" href="structdwc__ep.html#57e934b26e76939912eaa76321075a0d">desc_addr</a>;
+<a name="l00128"></a>00128 
+<a name="l00129"></a><a class="code" href="structdwc__ep.html#d0cda8ded2e5142d9a1c9c17efc5812f">00129</a>         uint8_t *<a class="code" href="structdwc__ep.html#d0cda8ded2e5142d9a1c9c17efc5812f">start_xfer_buff</a>;
+<a name="l00131"></a><a class="code" href="structdwc__ep.html#97fa9bf5c31ba734d54f70e6fe6ae8eb">00131</a>         uint8_t *<a class="code" href="structdwc__ep.html#97fa9bf5c31ba734d54f70e6fe6ae8eb">xfer_buff</a>;
+<a name="l00133"></a><a class="code" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">00133</a>         <span class="keywordtype">unsigned</span> <a class="code" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">xfer_len</a>:19;
+<a name="l00135"></a><a class="code" href="structdwc__ep.html#23d4871510b5bcb54fbf0674d8f122bd">00135</a>         <span class="keywordtype">unsigned</span> <a class="code" href="structdwc__ep.html#23d4871510b5bcb54fbf0674d8f122bd">xfer_count</a>:19;
+<a name="l00137"></a><a class="code" href="structdwc__ep.html#8c6340435beba0b8c025a4677602acab">00137</a>         <span class="keywordtype">unsigned</span> <a class="code" href="structdwc__ep.html#8c6340435beba0b8c025a4677602acab">sent_zlp</a>:1;
+<a name="l00139"></a><a class="code" href="structdwc__ep.html#5a218f200cff0491b735f43fed5176bf">00139</a>         <span class="keywordtype">unsigned</span> <a class="code" href="structdwc__ep.html#5a218f200cff0491b735f43fed5176bf">total_len</a>:19;
+<a name="l00140"></a>00140 
+<a name="l00142"></a><a class="code" href="structdwc__ep.html#0d30d306e370810fc819f6ef735c7e67">00142</a>         <span class="keywordtype">unsigned</span> <a class="code" href="structdwc__ep.html#0d30d306e370810fc819f6ef735c7e67">stall_clear_flag</a>:1;
+<a name="l00143"></a>00143 
+<a name="l00144"></a>00144 <span class="preprocessor">#ifdef DWC_UTE_CFI</span>
+<a name="l00145"></a>00145 <span class="preprocessor"></span>        <span class="comment">/* The buffer mode */</span>
+<a name="l00146"></a>00146         data_buffer_mode_e buff_mode;
+<a name="l00147"></a>00147 
+<a name="l00148"></a>00148         <span class="comment">/* The chain of DMA descriptors.</span>
+<a name="l00149"></a>00149 <span class="comment">         * MAX_DMA_DESCS_PER_EP will be allocated for each active EP.</span>
+<a name="l00150"></a>00150 <span class="comment">         */</span>
+<a name="l00151"></a>00151         dwc_otg_dma_desc_t *descs;
+<a name="l00152"></a>00152 
+<a name="l00153"></a>00153         <span class="comment">/* The DMA address of the descriptors chain start */</span>
+<a name="l00154"></a>00154         dma_addr_t descs_dma_addr;
+<a name="l00156"></a>00156         uint32_t cfi_req_len;
+<a name="l00157"></a>00157 <span class="preprocessor">#endif                          //DWC_UTE_CFI</span>
+<a name="l00158"></a>00158 <span class="preprocessor"></span>
+<a name="l00160"></a><a class="code" href="structdwc__ep.html#5e5bfcc93d41670bc0d29ad5f0f35871">00160</a>         uint32_t <a class="code" href="structdwc__ep.html#5e5bfcc93d41670bc0d29ad5f0f35871">desc_cnt</a>;
+<a name="l00161"></a>00161 
+<a name="l00162"></a>00162 <span class="preprocessor">#ifdef DWC_EN_ISOC</span>
+<a name="l00163"></a>00163 <span class="preprocessor"></span>
+<a name="l00168"></a><a class="code" href="structdwc__ep.html#553936d1d003413d00a24330274887f9">00168</a>         dwc_dma_t <a class="code" href="structdwc__ep.html#553936d1d003413d00a24330274887f9">dma_addr0</a>;
+<a name="l00169"></a><a class="code" href="structdwc__ep.html#02dc1be77d505b19f14651fe9805c97f">00169</a>         dwc_dma_t <a class="code" href="structdwc__ep.html#02dc1be77d505b19f14651fe9805c97f">dma_addr1</a>;
+<a name="l00170"></a>00170 
+<a name="l00171"></a><a class="code" href="structdwc__ep.html#d571f49545171ea167193edac7984173">00171</a>         dwc_dma_t <a class="code" href="structdwc__ep.html#d571f49545171ea167193edac7984173">iso_dma_desc_addr</a>;
+<a name="l00172"></a><a class="code" href="structdwc__ep.html#a4e11d12099ad64dd5048a3a210fc9f6">00172</a>         <a class="code" href="structdwc__otg__dev__dma__desc.html">dwc_otg_dev_dma_desc_t</a> *<a class="code" href="structdwc__ep.html#a4e11d12099ad64dd5048a3a210fc9f6">iso_desc_addr</a>;
+<a name="l00173"></a>00173 
+<a name="l00175"></a><a class="code" href="structdwc__ep.html#b6d727e366ac589d304256c758d2d44a">00175</a>         uint8_t *<a class="code" href="structdwc__ep.html#b6d727e366ac589d304256c758d2d44a">xfer_buff0</a>;
+<a name="l00176"></a><a class="code" href="structdwc__ep.html#36ff87362a0da5bce95eaf85522d49ff">00176</a>         uint8_t *<a class="code" href="structdwc__ep.html#36ff87362a0da5bce95eaf85522d49ff">xfer_buff1</a>;
+<a name="l00177"></a>00177 
+<a name="l00179"></a><a class="code" href="structdwc__ep.html#53033f174854701986545f05502e1cad">00179</a>         uint32_t <a class="code" href="structdwc__ep.html#53033f174854701986545f05502e1cad">proc_buf_num</a>;
+<a name="l00181"></a><a class="code" href="structdwc__ep.html#4638b25387e59a5a4721a503b5279dfc">00181</a>         uint32_t <a class="code" href="structdwc__ep.html#4638b25387e59a5a4721a503b5279dfc">buf_proc_intrvl</a>;
+<a name="l00183"></a><a class="code" href="structdwc__ep.html#4672369f4724db642856d72d5048213e">00183</a>         uint32_t <a class="code" href="structdwc__ep.html#4672369f4724db642856d72d5048213e">data_per_frame</a>;
+<a name="l00184"></a>00184 
+<a name="l00185"></a>00185         <span class="comment">/* todo - pattern data support is to be implemented in the future */</span>
+<a name="l00187"></a><a class="code" href="structdwc__ep.html#c505483882bd67a7b0076851f693f2cc">00187</a>         uint32_t <a class="code" href="structdwc__ep.html#c505483882bd67a7b0076851f693f2cc">data_pattern_frame</a>;
+<a name="l00189"></a><a class="code" href="structdwc__ep.html#1b9094ddfba3cddf397fd308cdbf4c81">00189</a>         uint32_t <a class="code" href="structdwc__ep.html#1b9094ddfba3cddf397fd308cdbf4c81">sync_frame</a>;
+<a name="l00190"></a>00190 
+<a name="l00192"></a><a class="code" href="structdwc__ep.html#d9e9ffe348764ababc3165ed04f9ec6c">00192</a>         uint32_t <a class="code" href="structdwc__ep.html#d9e9ffe348764ababc3165ed04f9ec6c">bInterval</a>;
+<a name="l00194"></a><a class="code" href="structdwc__ep.html#fe51420474de8a9d74fc9c4adc811c4b">00194</a>         uint32_t <a class="code" href="structdwc__ep.html#fe51420474de8a9d74fc9c4adc811c4b">pkt_per_frm</a>;
+<a name="l00196"></a><a class="code" href="structdwc__ep.html#1e9f4d08454c973c17acb3e52a2c3689">00196</a>         uint32_t <a class="code" href="structdwc__ep.html#1e9f4d08454c973c17acb3e52a2c3689">next_frame</a>;
+<a name="l00198"></a><a class="code" href="structdwc__ep.html#46349fb0608d8c6849ced211b0628c15">00198</a>         uint32_t <a class="code" href="structdwc__ep.html#46349fb0608d8c6849ced211b0628c15">pkt_cnt</a>;
+<a name="l00200"></a><a class="code" href="structdwc__ep.html#a8ed15a24123a2dad6861da7d61dfb48">00200</a>         <a class="code" href="structiso__pkt__info.html">iso_pkt_info_t</a> *<a class="code" href="structdwc__ep.html#a8ed15a24123a2dad6861da7d61dfb48">pkt_info</a>;
+<a name="l00202"></a><a class="code" href="structdwc__ep.html#d4e63c7d944c2b48260b4a75c2b58925">00202</a>         uint32_t <a class="code" href="structdwc__ep.html#d4e63c7d944c2b48260b4a75c2b58925">cur_pkt</a>;
+<a name="l00204"></a><a class="code" href="structdwc__ep.html#d3bc23598a77d3cca52c70a28afc6b5e">00204</a>         uint8_t *<a class="code" href="structdwc__ep.html#d3bc23598a77d3cca52c70a28afc6b5e">cur_pkt_addr</a>;
+<a name="l00206"></a><a class="code" href="structdwc__ep.html#ed4594c9f6c2bcbcf6f1bbe9e9c64061">00206</a>         uint32_t <a class="code" href="structdwc__ep.html#ed4594c9f6c2bcbcf6f1bbe9e9c64061">cur_pkt_dma_addr</a>;
+<a name="l00207"></a>00207 <span class="preprocessor">#endif                          </span><span class="comment">/* DWC_EN_ISOC */</span>
+<a name="l00208"></a>00208 
+<a name="l00210"></a>00210 } <a class="code" href="structdwc__ep.html">dwc_ep_t</a>;
+<a name="l00211"></a>00211 
+<a name="l00212"></a>00212 <span class="comment">/*</span>
+<a name="l00213"></a>00213 <span class="comment"> * Reasons for halting a host channel.</span>
+<a name="l00214"></a>00214 <span class="comment"> */</span>
+<a name="l00215"></a><a class="code" href="dwc__otg__cil_8h.html#5535f5641e4293d3ecca5c863863d60d">00215</a> <span class="keyword">typedef</span> <span class="keyword">enum</span> <a class="code" href="dwc__otg__cil_8h.html#5535f5641e4293d3ecca5c863863d60d">dwc_otg_halt_status</a> {
+<a name="l00216"></a>00216         DWC_OTG_HC_XFER_NO_HALT_STATUS,
+<a name="l00217"></a>00217         DWC_OTG_HC_XFER_COMPLETE,
+<a name="l00218"></a>00218         DWC_OTG_HC_XFER_URB_COMPLETE,
+<a name="l00219"></a>00219         DWC_OTG_HC_XFER_ACK,
+<a name="l00220"></a>00220         DWC_OTG_HC_XFER_NAK,
+<a name="l00221"></a>00221         DWC_OTG_HC_XFER_NYET,
+<a name="l00222"></a>00222         DWC_OTG_HC_XFER_STALL,
+<a name="l00223"></a>00223         DWC_OTG_HC_XFER_XACT_ERR,
+<a name="l00224"></a>00224         DWC_OTG_HC_XFER_FRAME_OVERRUN,
+<a name="l00225"></a>00225         DWC_OTG_HC_XFER_BABBLE_ERR,
+<a name="l00226"></a>00226         DWC_OTG_HC_XFER_DATA_TOGGLE_ERR,
+<a name="l00227"></a>00227         DWC_OTG_HC_XFER_AHB_ERR,
+<a name="l00228"></a>00228         DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE,
+<a name="l00229"></a>00229         DWC_OTG_HC_XFER_URB_DEQUEUE
+<a name="l00230"></a>00230 } dwc_otg_halt_status_e;
+<a name="l00231"></a>00231 
+<a name="l00237"></a><a class="code" href="structdwc__hc.html">00237</a> <span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code" href="structdwc__hc.html">dwc_hc</a> {
+<a name="l00239"></a><a class="code" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">00239</a>         uint8_t <a class="code" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">hc_num</a>;
+<a name="l00240"></a>00240 
+<a name="l00242"></a><a class="code" href="structdwc__hc.html#b2c7e8baff70104375f4916e9b76cef7">00242</a>         <span class="keywordtype">unsigned</span> <a class="code" href="structdwc__hc.html#b2c7e8baff70104375f4916e9b76cef7">dev_addr</a>:7;
+<a name="l00243"></a>00243 
+<a name="l00245"></a><a class="code" href="structdwc__hc.html#70b755f76a00b81679aeb1e0db8b2e60">00245</a>         <span class="keywordtype">unsigned</span> <a class="code" href="structdwc__hc.html#70b755f76a00b81679aeb1e0db8b2e60">ep_num</a>:4;
+<a name="l00246"></a>00246 
+<a name="l00248"></a><a class="code" href="structdwc__hc.html#c5088d431f5efc382121f201f5d571aa">00248</a>         <span class="keywordtype">unsigned</span> <a class="code" href="structdwc__hc.html#c5088d431f5efc382121f201f5d571aa">ep_is_in</a>:1;
+<a name="l00249"></a>00249 
+<a name="l00257"></a><a class="code" href="structdwc__hc.html#570b78178975193edb921af1ef36d37b">00257</a>         <span class="keywordtype">unsigned</span> <a class="code" href="structdwc__hc.html#570b78178975193edb921af1ef36d37b">speed</a>:2;
+<a name="l00258"></a><a class="code" href="dwc__otg__cil_8h.html#1a25260b2e1a06850c26f7b7e5128f31">00258</a> <span class="preprocessor">#define DWC_OTG_EP_SPEED_LOW    0</span>
+<a name="l00259"></a><a class="code" href="dwc__otg__cil_8h.html#2ec9a7665a34074eedf1f40681d124ef">00259</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_OTG_EP_SPEED_FULL   1</span>
+<a name="l00260"></a><a class="code" href="dwc__otg__cil_8h.html#b9dc03c6bc3c1113a935a73cf7021fbe">00260</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_OTG_EP_SPEED_HIGH   2</span>
+<a name="l00261"></a>00261 <span class="preprocessor"></span>
+<a name="l00270"></a><a class="code" href="structdwc__hc.html#e6169fbc92e4d79686097742ad646f5c">00270</a>         <span class="keywordtype">unsigned</span> <a class="code" href="structdwc__hc.html#e6169fbc92e4d79686097742ad646f5c">ep_type</a>:2;
+<a name="l00271"></a>00271 
+<a name="l00273"></a><a class="code" href="structdwc__hc.html#bd88f02eb286ba01d8d1b049e8975ccb">00273</a>         <span class="keywordtype">unsigned</span> <a class="code" href="structdwc__hc.html#bd88f02eb286ba01d8d1b049e8975ccb">max_packet</a>:11;
+<a name="l00274"></a>00274 
+<a name="l00283"></a><a class="code" href="structdwc__hc.html#513427c5e8c4603ba344d4e7f9191064">00283</a>         <span class="keywordtype">unsigned</span> <a class="code" href="structdwc__hc.html#513427c5e8c4603ba344d4e7f9191064">data_pid_start</a>:2;
+<a name="l00284"></a><a class="code" href="dwc__otg__cil_8h.html#0e843d08e80c29e82962ce9170a02a52">00284</a> <span class="preprocessor">#define DWC_OTG_HC_PID_DATA0 0</span>
+<a name="l00285"></a><a class="code" href="dwc__otg__cil_8h.html#5a78ac2f42a7e583d849903fa4570fb8">00285</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_OTG_HC_PID_DATA2 1</span>
+<a name="l00286"></a><a class="code" href="dwc__otg__cil_8h.html#e623eb446c55928b324e9636111315e1">00286</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_OTG_HC_PID_DATA1 2</span>
+<a name="l00287"></a><a class="code" href="dwc__otg__cil_8h.html#3cea7ef8aa1cfeb50060f07e08fa6aff">00287</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_OTG_HC_PID_MDATA 3</span>
+<a name="l00288"></a><a class="code" href="dwc__otg__cil_8h.html#8d329f92a5ff6f9a72fc755b6b1a4e17">00288</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_OTG_HC_PID_SETUP 3</span>
+<a name="l00289"></a>00289 <span class="preprocessor"></span>
+<a name="l00291"></a><a class="code" href="structdwc__hc.html#9a01b904f7ccc7178cdb80c20e8a9b0c">00291</a>         <span class="keywordtype">unsigned</span> <a class="code" href="structdwc__hc.html#9a01b904f7ccc7178cdb80c20e8a9b0c">multi_count</a>:2;
+<a name="l00292"></a>00292 
+<a name="l00297"></a><a class="code" href="structdwc__hc.html#9dc781cb9e4bc639765beee37ce76673">00297</a>         uint8_t *<a class="code" href="structdwc__hc.html#9dc781cb9e4bc639765beee37ce76673">xfer_buff</a>;
+<a name="l00302"></a><a class="code" href="structdwc__hc.html#e0c3ba51a04b36656baa4e70fc63cf77">00302</a>         dwc_dma_t <a class="code" href="structdwc__hc.html#e0c3ba51a04b36656baa4e70fc63cf77">align_buff</a>;
+<a name="l00304"></a><a class="code" href="structdwc__hc.html#ce32fe93214f1686896e924fbf61cac7">00304</a>         uint32_t <a class="code" href="structdwc__hc.html#ce32fe93214f1686896e924fbf61cac7">xfer_len</a>;
+<a name="l00306"></a><a class="code" href="structdwc__hc.html#6199aaeab2d64954311c410b30270293">00306</a>         uint32_t <a class="code" href="structdwc__hc.html#6199aaeab2d64954311c410b30270293">xfer_count</a>;
+<a name="l00308"></a><a class="code" href="structdwc__hc.html#6c030bc725f43025d3046d17b4fbee4e">00308</a>         uint16_t <a class="code" href="structdwc__hc.html#6c030bc725f43025d3046d17b4fbee4e">start_pkt_count</a>;
+<a name="l00309"></a>00309 
+<a name="l00314"></a><a class="code" href="structdwc__hc.html#78a1cf134604b24bfdedb4f4df9f2c1f">00314</a>         uint8_t <a class="code" href="structdwc__hc.html#78a1cf134604b24bfdedb4f4df9f2c1f">xfer_started</a>;
+<a name="l00315"></a>00315 
+<a name="l00320"></a><a class="code" href="structdwc__hc.html#ae7184275dbb23b3a5d2af20ed224920">00320</a>         uint8_t <a class="code" href="structdwc__hc.html#ae7184275dbb23b3a5d2af20ed224920">do_ping</a>;
+<a name="l00321"></a>00321 
+<a name="l00326"></a><a class="code" href="structdwc__hc.html#ab0855754930fdc74978fa71772982ed">00326</a>         uint8_t <a class="code" href="structdwc__hc.html#ab0855754930fdc74978fa71772982ed">error_state</a>;
+<a name="l00327"></a>00327 
+<a name="l00334"></a><a class="code" href="structdwc__hc.html#c3b27b33fae73aff43a9834a1ed585da">00334</a>         uint8_t <a class="code" href="structdwc__hc.html#c3b27b33fae73aff43a9834a1ed585da">halt_on_queue</a>;
+<a name="l00335"></a>00335 
+<a name="l00340"></a><a class="code" href="structdwc__hc.html#2177dcde6dbb17b6bc7d0fb34e8ec95a">00340</a>         uint8_t <a class="code" href="structdwc__hc.html#2177dcde6dbb17b6bc7d0fb34e8ec95a">halt_pending</a>;
+<a name="l00341"></a>00341 
+<a name="l00345"></a><a class="code" href="structdwc__hc.html#07eca0fa02105ddaa1719387f5558b23">00345</a>         dwc_otg_halt_status_e <a class="code" href="structdwc__hc.html#07eca0fa02105ddaa1719387f5558b23">halt_status</a>;
+<a name="l00346"></a>00346 
+<a name="l00347"></a>00347         <span class="comment">/*</span>
+<a name="l00348"></a>00348 <span class="comment">         * Split settings for the host channel</span>
+<a name="l00349"></a>00349 <span class="comment">         */</span>
+<a name="l00350"></a><a class="code" href="structdwc__hc.html#4365ef67d517a621a626ac5392545c6d">00350</a>         uint8_t <a class="code" href="structdwc__hc.html#4365ef67d517a621a626ac5392545c6d">do_split</a>;                  
+<a name="l00351"></a><a class="code" href="structdwc__hc.html#21e00df6fb9a555975879526118d599e">00351</a>         uint8_t <a class="code" href="structdwc__hc.html#21e00df6fb9a555975879526118d599e">complete_split</a>;    
+<a name="l00352"></a><a class="code" href="structdwc__hc.html#19d0302b6e3769eada2466b8e5e0dd91">00352</a>         uint8_t <a class="code" href="structdwc__hc.html#19d0302b6e3769eada2466b8e5e0dd91">hub_addr</a>;                  
+<a name="l00354"></a><a class="code" href="structdwc__hc.html#9f597e05c37d7292f4c0d965c67ee3dd">00354</a>         uint8_t <a class="code" href="structdwc__hc.html#9f597e05c37d7292f4c0d965c67ee3dd">port_addr</a>;                 
+<a name="l00361"></a><a class="code" href="structdwc__hc.html#3cde49a724756e16eb11a027360b2d4b">00361</a>         uint8_t <a class="code" href="structdwc__hc.html#3cde49a724756e16eb11a027360b2d4b">xact_pos</a>;
+<a name="l00362"></a>00362 
+<a name="l00364"></a><a class="code" href="structdwc__hc.html#83e9a3cc9075b1fe21a6fa5190fa78c1">00364</a>         uint8_t <a class="code" href="structdwc__hc.html#83e9a3cc9075b1fe21a6fa5190fa78c1">short_read</a>;
+<a name="l00365"></a>00365 
+<a name="l00370"></a><a class="code" href="structdwc__hc.html#961e8eae7a18c503e370c4bc513d3e55">00370</a>         uint8_t <a class="code" href="structdwc__hc.html#961e8eae7a18c503e370c4bc513d3e55">requests</a>;
+<a name="l00371"></a>00371 
+<a name="l00375"></a><a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">00375</a>         <span class="keyword">struct </span><a class="code" href="structdwc__otg__qh.html">dwc_otg_qh</a> *<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>;
+<a name="l00376"></a>00376 
+<a name="l00380"></a>00380          <a class="code" href="structdwc__hc.html#bf81e1a0c0ae06faf445a61b950e24f5">DWC_CIRCLEQ_ENTRY</a>(<a class="code" href="structdwc__hc.html">dwc_hc</a>) hc_list_entry;
+<a name="l00381"></a>00381         
+<a name="l00386"></a><a class="code" href="structdwc__hc.html#9a3a483b9c4e45d1ec5f475beb6a10a3">00386</a>         uint16_t <a class="code" href="structdwc__hc.html#9a3a483b9c4e45d1ec5f475beb6a10a3">ntd</a>;
+<a name="l00387"></a>00387         
+<a name="l00389"></a><a class="code" href="structdwc__hc.html#f3001addf65df4d3c6a5c685d7637efd">00389</a>         dwc_dma_t <a class="code" href="structdwc__hc.html#f3001addf65df4d3c6a5c685d7637efd">desc_list_addr</a>;
+<a name="l00390"></a>00390         
+<a name="l00392"></a><a class="code" href="structdwc__hc.html#42c5f7b0264ee050df79dc1fe57464b7">00392</a>         uint8_t <a class="code" href="structdwc__hc.html#42c5f7b0264ee050df79dc1fe57464b7">schinfo</a>;
+<a name="l00393"></a>00393         
+<a name="l00395"></a>00395 } <a class="code" href="structdwc__hc.html">dwc_hc_t</a>;
+<a name="l00396"></a>00396 
+<a name="l00401"></a><a class="code" href="structdwc__otg__core__params.html">00401</a> typedef struct <a class="code" href="structdwc__otg__core__params.html">dwc_otg_core_params</a> {
+<a name="l00402"></a><a class="code" href="structdwc__otg__core__params.html#6d67db1b1152d788bf2fc7fdc6363f78">00402</a>         int32_t opt;
+<a name="l00403"></a>00403 
+<a name="l00411"></a><a class="code" href="structdwc__otg__core__params.html#b6960c28e9c7d82dca37645726c8f7ce">00411</a>         int32_t otg_cap;
+<a name="l00412"></a>00412 
+<a name="l00420"></a><a class="code" href="structdwc__otg__core__params.html#3c791cb4898379d156acc47c5b9a84fc">00420</a>         int32_t dma_enable;
+<a name="l00421"></a>00421 
+<a name="l00429"></a><a class="code" href="structdwc__otg__core__params.html#36c5bcf00d0f776b5c9e84e5d8ae408d">00429</a>         int32_t dma_desc_enable;
+<a name="l00433"></a><a class="code" href="structdwc__otg__core__params.html#f9d2a8cd9b36d24de89121d19f693ccb">00433</a>         int32_t dma_burst_size; <span class="comment">/* Translate this to GAHBCFG values */</span>
+<a name="l00434"></a>00434 
+<a name="l00443"></a><a class="code" href="structdwc__otg__core__params.html#d2c4f622f1c14f68c6e60e2603acd09d">00443</a>         int32_t <a class="code" href="structdwc__hc.html#570b78178975193edb921af1ef36d37b">speed</a>;
+<a name="l00449"></a><a class="code" href="structdwc__otg__core__params.html#85cad588a450b8497347af9cf166bfde">00449</a>         int32_t host_support_fs_ls_low_power;
+<a name="l00450"></a>00450 
+<a name="l00459"></a><a class="code" href="structdwc__otg__core__params.html#98f413798f20dc40036a2ec527935a7d">00459</a>         int32_t host_ls_low_power_phy_clk;
+<a name="l00460"></a>00460 
+<a name="l00465"></a><a class="code" href="structdwc__otg__core__params.html#8c169633d4a6f28e964cef9f597c6e03">00465</a>         int32_t enable_dynamic_fifo;
+<a name="l00466"></a>00466 
+<a name="l00473"></a><a class="code" href="structdwc__otg__core__params.html#3d8dc206f54165f52c7f8599731d0f95">00473</a>         int32_t data_fifo_size;
+<a name="l00474"></a>00474 
+<a name="l00479"></a><a class="code" href="structdwc__otg__core__params.html#24ea6f9329f64ac0ad2d31dafe0d1d8c">00479</a>         int32_t dev_rx_fifo_size;
+<a name="l00480"></a>00480 
+<a name="l00485"></a><a class="code" href="structdwc__otg__core__params.html#d08d9aee1fb4e6508089415d6150176e">00485</a>         int32_t dev_nperio_tx_fifo_size;
+<a name="l00486"></a>00486 
+<a name="l00491"></a><a class="code" href="structdwc__otg__core__params.html#2958d325289f4a77b6435cda729e5f6e">00491</a>         uint32_t dev_perio_tx_fifo_size[<a class="code" href="dwc__otg__core__if_8h.html#13bb22067644d357537c2905fe5ffb8c">MAX_PERIO_FIFOS</a>];
+<a name="l00492"></a>00492 
+<a name="l00497"></a><a class="code" href="structdwc__otg__core__params.html#2b2ab9c2fe16db70b136515b2e981f6b">00497</a>         int32_t host_rx_fifo_size;
+<a name="l00498"></a>00498 
+<a name="l00503"></a><a class="code" href="structdwc__otg__core__params.html#6ff00857d99f72c0cfd6198cbcfab9a7">00503</a>         int32_t host_nperio_tx_fifo_size;
+<a name="l00504"></a>00504 
+<a name="l00509"></a><a class="code" href="structdwc__otg__core__params.html#5bc3cac5c81fd8d6fd291ca4b7de3e28">00509</a>         int32_t host_perio_tx_fifo_size;
+<a name="l00510"></a>00510 
+<a name="l00514"></a><a class="code" href="structdwc__otg__core__params.html#e614d1d2ee740cd972ca76ed0dffec74">00514</a>         int32_t max_transfer_size;
+<a name="l00515"></a>00515 
+<a name="l00519"></a><a class="code" href="structdwc__otg__core__params.html#e17230afa013a15beda38565d19fa933">00519</a>         int32_t max_packet_count;
+<a name="l00520"></a>00520 
+<a name="l00525"></a><a class="code" href="structdwc__otg__core__params.html#c1b433c6965aa7d48f6ca6818c592039">00525</a>         int32_t host_channels;
+<a name="l00526"></a>00526 
+<a name="l00533"></a><a class="code" href="structdwc__otg__core__params.html#17d0dda7fe2cd51726cd1dd34c57b94a">00533</a>         int32_t dev_endpoints;
+<a name="l00534"></a>00534 
+<a name="l00543"></a><a class="code" href="structdwc__otg__core__params.html#8b5d4e0c98c46d0d4e80b6faf66daf72">00543</a>         int32_t phy_type;
+<a name="l00544"></a>00544 
+<a name="l00556"></a><a class="code" href="structdwc__otg__core__params.html#41f5a03ab1b68564b240e03f33a09dde">00556</a>         int32_t phy_utmi_width;
+<a name="l00557"></a>00557 
+<a name="l00568"></a><a class="code" href="structdwc__otg__core__params.html#6fc9a3fbe3c36cbbc231f1642ee96cfe">00568</a>         int32_t phy_ulpi_ddr;
+<a name="l00569"></a>00569 
+<a name="l00574"></a><a class="code" href="structdwc__otg__core__params.html#3b6fa0a7fe7d7f87326894fdbe0aa375">00574</a>         int32_t phy_ulpi_ext_vbus;
+<a name="l00575"></a>00575 
+<a name="l00582"></a><a class="code" href="structdwc__otg__core__params.html#6b0a0ab15284a541ae079beecaf3e617">00582</a>         int32_t i2c_enable;
+<a name="l00583"></a>00583 
+<a name="l00584"></a><a class="code" href="structdwc__otg__core__params.html#3d7cfc3c416010102b2c671dfaa828d5">00584</a>         int32_t ulpi_fs_ls;
+<a name="l00585"></a>00585 
+<a name="l00586"></a><a class="code" href="structdwc__otg__core__params.html#879afefd6e13233a78d74ee71d3ee75e">00586</a>         int32_t ts_dline;
+<a name="l00587"></a>00587 
+<a name="l00594"></a><a class="code" href="structdwc__otg__core__params.html#d61279dcea66973b2915e335efb07fe3">00594</a>         int32_t en_multiple_tx_fifo;
+<a name="l00595"></a>00595 
+<a name="l00600"></a><a class="code" href="structdwc__otg__core__params.html#6e0c5d06467fbf3458f11f7eb8153a8b">00600</a>         uint32_t dev_tx_fifo_size[<a class="code" href="dwc__otg__core__if_8h.html#050db6129005b993e573311dc42bc1a8">MAX_TX_FIFOS</a>];
+<a name="l00601"></a>00601 
+<a name="l00607"></a><a class="code" href="structdwc__otg__core__params.html#1610a4b28bea581c46f251d995bf4a51">00607</a>         uint32_t thr_ctl;
+<a name="l00608"></a>00608 
+<a name="l00612"></a><a class="code" href="structdwc__otg__core__params.html#c92fc907d503f9b8bb3600164c520b0e">00612</a>         uint32_t tx_thr_length;
+<a name="l00613"></a>00613 
+<a name="l00617"></a><a class="code" href="structdwc__otg__core__params.html#2cb1f83013e357828fbf55ac91971d44">00617</a>         uint32_t rx_thr_length;
+<a name="l00618"></a>00618 
+<a name="l00622"></a><a class="code" href="structdwc__otg__core__params.html#8b906ba765a10dd9fcfa1c02dbc0184e">00622</a>         int32_t lpm_enable;
+<a name="l00623"></a>00623 
+<a name="l00629"></a><a class="code" href="structdwc__otg__core__params.html#b601fde03b371b74deab1205e1329a7d">00629</a>         int32_t pti_enable;
+<a name="l00630"></a>00630 
+<a name="l00636"></a><a class="code" href="structdwc__otg__core__params.html#740e50199a75b3877b7db630d49c36aa">00636</a>         int32_t mpi_enable;
+<a name="l00637"></a>00637 
+<a name="l00642"></a><a class="code" href="structdwc__otg__core__params.html#359a3cb3a7b4800a0c32750005c9fd1b">00642</a>         int32_t ic_usb_cap;
+<a name="l00643"></a>00643 
+<a name="l00650"></a><a class="code" href="structdwc__otg__core__params.html#8787af52f8d70a9100ab1fa2b0f69bfb">00650</a>         int32_t ahb_thr_ratio;
+<a name="l00651"></a>00651 
+<a name="l00652"></a>00652 } <a class="code" href="structdwc__otg__core__params.html">dwc_otg_core_params_t</a>;
+<a name="l00653"></a>00653 
+<a name="l00654"></a>00654 <span class="preprocessor">#ifdef DEBUG</span>
+<a name="l00655"></a>00655 <span class="preprocessor"></span><span class="keyword">struct </span><a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if</a>;
+<a name="l00656"></a>00656 <span class="keyword">typedef</span> <span class="keyword">struct </span>hc_xfer_info {
+<a name="l00657"></a>00657         <span class="keyword">struct </span><a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if</a> *core_if;
+<a name="l00658"></a>00658         <a class="code" href="structdwc__hc.html">dwc_hc_t</a> *hc;
+<a name="l00659"></a>00659 } hc_xfer_info_t;
+<a name="l00660"></a>00660 <span class="preprocessor">#endif</span>
+<a name="l00661"></a>00661 <span class="preprocessor"></span><span class="comment">/*</span>
+<a name="l00662"></a>00662 <span class="comment"> * Device States</span>
+<a name="l00663"></a>00663 <span class="comment"> */</span>
+<a name="l00664"></a><a class="code" href="dwc__otg__cil_8h.html#8442e49b7c783099ac17bda4f8b3bc3c">00664</a> <span class="keyword">typedef</span> <span class="keyword">enum</span> <a class="code" href="dwc__otg__cil_8h.html#8442e49b7c783099ac17bda4f8b3bc3c">dwc_otg_lx_state</a> {
+<a name="l00666"></a>00666         <a class="code" href="dwc__otg__cil_8h.html#8442e49b7c783099ac17bda4f8b3bc3c9743a36d9b0b8c66a11a0714fdd27fb5">DWC_OTG_L0</a>,
+<a name="l00668"></a>00668         <a class="code" href="dwc__otg__cil_8h.html#8442e49b7c783099ac17bda4f8b3bc3cf5b112742a8103f3489107ad26c0ff58">DWC_OTG_L1</a>,
+<a name="l00670"></a>00670         <a class="code" href="dwc__otg__cil_8h.html#8442e49b7c783099ac17bda4f8b3bc3cd1fadb6fa31de73e8176316a0e0ba905">DWC_OTG_L2</a>,
+<a name="l00672"></a>00672         <a class="code" href="dwc__otg__cil_8h.html#8442e49b7c783099ac17bda4f8b3bc3c86715d528a59b114b95aaafa8f2142f6">DWC_OTG_L3</a>
+<a name="l00673"></a>00673 } dwc_otg_lx_state_e;
+<a name="l00674"></a>00674 
+<a name="l00680"></a><a class="code" href="structdwc__otg__core__if.html">00680</a> <span class="keyword">struct </span><a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if</a> {
+<a name="l00682"></a><a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">00682</a>         <a class="code" href="structdwc__otg__core__params.html">dwc_otg_core_params_t</a> *core_params;
+<a name="l00683"></a>00683 
+<a name="l00685"></a><a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">00685</a>         <a class="code" href="structdwc__otg__core__global__regs.html">dwc_otg_core_global_regs_t</a> *core_global_regs;
+<a name="l00686"></a>00686 
+<a name="l00688"></a><a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">00688</a>         <a class="code" href="structdwc__otg__dev__if.html">dwc_otg_dev_if_t</a> *dev_if;
+<a name="l00690"></a><a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">00690</a>         <a class="code" href="structdwc__otg__host__if.html">dwc_otg_host_if_t</a> *host_if;
+<a name="l00691"></a>00691 
+<a name="l00693"></a><a class="code" href="structdwc__otg__core__if.html#afc495591efa54c74c1dd50278b57ffe">00693</a>         uint32_t snpsid;
+<a name="l00694"></a>00694 
+<a name="l00695"></a>00695         <span class="comment">/*</span>
+<a name="l00696"></a>00696 <span class="comment">         * Set to 1 if the core PHY interface bits in USBCFG have been</span>
+<a name="l00697"></a>00697 <span class="comment">         * initialized.</span>
+<a name="l00698"></a>00698 <span class="comment">         */</span>
+<a name="l00699"></a><a class="code" href="structdwc__otg__core__if.html#24dd9dec510e5edac930538b81004b74">00699</a>         uint8_t phy_init_done;
+<a name="l00700"></a>00700 
+<a name="l00701"></a>00701         <span class="comment">/*</span>
+<a name="l00702"></a>00702 <span class="comment">         * SRP Success flag, set by srp success interrupt in FS I2C mode</span>
+<a name="l00703"></a>00703 <span class="comment">         */</span>
+<a name="l00704"></a><a class="code" href="structdwc__otg__core__if.html#c2bb1913ed3fcc082a06d70242e9768a">00704</a>         uint8_t srp_success;
+<a name="l00705"></a><a class="code" href="structdwc__otg__core__if.html#749cdeef193b7590b036a9b1d1442b73">00705</a>         uint8_t srp_timer_started;
+<a name="l00706"></a>00706 
+<a name="l00707"></a>00707         <span class="comment">/* Common configuration information */</span>
+<a name="l00709"></a><a class="code" href="structdwc__otg__core__if.html#348ed2c9aeae6fc608f1bb813978b3f9">00709</a>         <span class="keyword">volatile</span> uint32_t *pcgcctl;
+<a name="l00710"></a><a class="code" href="dwc__otg__cil_8h.html#1e6c4a07594b33ba981e3664a2f3366c">00710</a> <span class="preprocessor">#define DWC_OTG_PCGCCTL_OFFSET 0xE00</span>
+<a name="l00711"></a>00711 <span class="preprocessor"></span>
+<a name="l00713"></a><a class="code" href="structdwc__otg__core__if.html#f99c868784a8269073bc251f88d92ee4">00713</a>         uint32_t *data_fifo[<a class="code" href="dwc__otg__core__if_8h.html#bfb88b45545f7685f668ac2f545674ec">MAX_EPS_CHANNELS</a>];
+<a name="l00714"></a><a class="code" href="dwc__otg__cil_8h.html#921e7968f6c39c1d7c8d3b4b95a4f4eb">00714</a> <span class="preprocessor">#define DWC_OTG_DATA_FIFO_OFFSET 0x1000</span>
+<a name="l00715"></a><a class="code" href="dwc__otg__cil_8h.html#b7aa34c1f7efae9b69e2891fea7b615f">00715</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_OTG_DATA_FIFO_SIZE 0x1000</span>
+<a name="l00716"></a>00716 <span class="preprocessor"></span>
+<a name="l00718"></a><a class="code" href="structdwc__otg__core__if.html#cae59008a554cb7de24bd4f2afea7532">00718</a>         uint16_t total_fifo_size;
+<a name="l00720"></a><a class="code" href="structdwc__otg__core__if.html#50bbb76c3818ada9ed2ea5527edabcd4">00720</a>         uint16_t rx_fifo_size;
+<a name="l00722"></a><a class="code" href="structdwc__otg__core__if.html#fb77b09f04a5687d2087726edd8dece6">00722</a>         uint16_t nperio_tx_fifo_size;
+<a name="l00723"></a>00723 
+<a name="l00725"></a><a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">00725</a>         uint8_t dma_enable;
+<a name="l00726"></a>00726 
+<a name="l00728"></a><a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">00728</a>         uint8_t dma_desc_enable;
+<a name="l00729"></a>00729 
+<a name="l00731"></a><a class="code" href="structdwc__otg__core__if.html#34540b79e9a14bfa234a52ac132c5cd1">00731</a>         uint8_t pti_enh_enable;
+<a name="l00732"></a>00732 
+<a name="l00734"></a><a class="code" href="structdwc__otg__core__if.html#5675c8d8dd7df746fda9157dc39ba5c2">00734</a>         uint8_t multiproc_int_enable;
+<a name="l00735"></a>00735 
+<a name="l00737"></a><a class="code" href="structdwc__otg__core__if.html#31d08d1ebcd290b05139b0fcd24048ec">00737</a>         uint8_t en_multiple_tx_fifo;
+<a name="l00738"></a>00738 
+<a name="l00741"></a><a class="code" href="structdwc__otg__core__if.html#5a6a90b40bc80e71d40f107b68f1e84c">00741</a>         uint8_t queuing_high_bandwidth;
+<a name="l00742"></a>00742 
+<a name="l00744"></a><a class="code" href="structdwc__otg__core__if.html#d7c6a00c6d7c157ff60a044a28ec8b95">00744</a>         <a class="code" href="unionhwcfg1__data.html">hwcfg1_data_t</a> hwcfg1;
+<a name="l00745"></a><a class="code" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">00745</a>         <a class="code" href="unionhwcfg2__data.html">hwcfg2_data_t</a> hwcfg2;
+<a name="l00746"></a><a class="code" href="structdwc__otg__core__if.html#91d0e0a5e8e048024c8846d12e00cecc">00746</a>         <a class="code" href="unionhwcfg3__data.html">hwcfg3_data_t</a> hwcfg3;
+<a name="l00747"></a><a class="code" href="structdwc__otg__core__if.html#9c1394f3c46adde2fa7be79bf0237f9b">00747</a>         <a class="code" href="unionhwcfg4__data.html">hwcfg4_data_t</a> hwcfg4;
+<a name="l00748"></a>00748 
+<a name="l00750"></a><a class="code" href="structdwc__otg__core__if.html#447a626f22ad64a90c68a6f49e624eb8">00750</a>         <a class="code" href="unionhcfg__data.html">hcfg_data_t</a> hcfg;
+<a name="l00751"></a><a class="code" href="structdwc__otg__core__if.html#fcce854acc5b4afca80bd5667ecc4ef2">00751</a>         <a class="code" href="uniondcfg__data.html">dcfg_data_t</a> dcfg;
+<a name="l00752"></a>00752 
+<a name="l00758"></a><a class="code" href="structdwc__otg__core__if.html#5a5c5c1cf8d870101cc1fffac56d88c0">00758</a>         uint8_t op_state;
+<a name="l00759"></a>00759 
+<a name="l00765"></a><a class="code" href="structdwc__otg__core__if.html#05b4c81b19338fc64090cf22d635517a">00765</a>         uint8_t restart_hcd_on_session_req;
+<a name="l00766"></a>00766 
+<a name="l00769"></a><a class="code" href="dwc__otg__cil_8h.html#a0732b344b6571a4554968e4ee2214dd">00769</a> <span class="preprocessor">#define A_HOST          (1)</span>
+<a name="l00770"></a>00770 <span class="preprocessor"></span>
+<a name="l00771"></a><a class="code" href="dwc__otg__cil_8h.html#da9f5eb506da71435e8976ceb38bc14d">00771</a> <span class="preprocessor">#define A_SUSPEND       (2)</span>
+<a name="l00772"></a>00772 <span class="preprocessor"></span>
+<a name="l00773"></a><a class="code" href="dwc__otg__cil_8h.html#7528970c03451cfc85e86ab92bbaf554">00773</a> <span class="preprocessor">#define A_PERIPHERAL    (3)</span>
+<a name="l00774"></a>00774 <span class="preprocessor"></span>
+<a name="l00775"></a><a class="code" href="dwc__otg__cil_8h.html#622c3b95c9a587f518a787c05c50ffb7">00775</a> <span class="preprocessor">#define B_PERIPHERAL    (4)</span>
+<a name="l00776"></a>00776 <span class="preprocessor"></span>
+<a name="l00777"></a><a class="code" href="dwc__otg__cil_8h.html#02d6d4d9a0fdcc4fc8c5cf8e6c8577aa">00777</a> <span class="preprocessor">#define B_HOST          (5)</span>
+<a name="l00778"></a>00778 <span class="preprocessor"></span>
+<a name="l00780"></a><a class="code" href="structdwc__otg__core__if.html#9a8568a762af68c9b0d97e0278cc26ba">00780</a>         <span class="keyword">struct </span><a class="code" href="structdwc__otg__cil__callbacks.html">dwc_otg_cil_callbacks</a> *hcd_cb;
+<a name="l00782"></a><a class="code" href="structdwc__otg__core__if.html#83bca1e02fafc4bbfa9c1f2eeb19b245">00782</a>         <span class="keyword">struct </span><a class="code" href="structdwc__otg__cil__callbacks.html">dwc_otg_cil_callbacks</a> *pcd_cb;
+<a name="l00783"></a>00783 
+<a name="l00785"></a><a class="code" href="structdwc__otg__core__if.html#0683b28ebf5247a60247d27a1a714d27">00785</a>         uint32_t p_tx_msk;
+<a name="l00787"></a><a class="code" href="structdwc__otg__core__if.html#b558bae74403677f08e45c692a88d4e2">00787</a>         uint32_t tx_msk;
+<a name="l00788"></a>00788 
+<a name="l00790"></a><a class="code" href="structdwc__otg__core__if.html#7e3716f6d6bc6f956a45efbe6e308386">00790</a>         dwc_workq_t *wq_otg;
+<a name="l00791"></a>00791 
+<a name="l00793"></a><a class="code" href="structdwc__otg__core__if.html#c914461f460deacd426bea7a05ebb204">00793</a>         dwc_timer_t *wkp_timer;
+<a name="l00794"></a>00794 
+<a name="l00795"></a>00795 <span class="preprocessor">#ifdef DEBUG</span>
+<a name="l00796"></a>00796 <span class="preprocessor"></span>        uint32_t start_hcchar_val[<a class="code" href="dwc__otg__core__if_8h.html#bfb88b45545f7685f668ac2f545674ec">MAX_EPS_CHANNELS</a>];
+<a name="l00797"></a>00797 
+<a name="l00798"></a>00798         hc_xfer_info_t hc_xfer_info[<a class="code" href="dwc__otg__core__if_8h.html#bfb88b45545f7685f668ac2f545674ec">MAX_EPS_CHANNELS</a>];
+<a name="l00799"></a>00799         dwc_timer_t *hc_xfer_timer[<a class="code" href="dwc__otg__core__if_8h.html#bfb88b45545f7685f668ac2f545674ec">MAX_EPS_CHANNELS</a>];
+<a name="l00800"></a>00800 
+<a name="l00801"></a>00801         uint32_t hfnum_7_samples;
+<a name="l00802"></a>00802         uint64_t hfnum_7_frrem_accum;
+<a name="l00803"></a>00803         uint32_t hfnum_0_samples;
+<a name="l00804"></a>00804         uint64_t hfnum_0_frrem_accum;
+<a name="l00805"></a>00805         uint32_t hfnum_other_samples;
+<a name="l00806"></a>00806         uint64_t hfnum_other_frrem_accum;
+<a name="l00807"></a>00807 <span class="preprocessor">#endif</span>
+<a name="l00808"></a>00808 <span class="preprocessor"></span>
+<a name="l00809"></a>00809 <span class="preprocessor">#ifdef DWC_UTE_CFI</span>
+<a name="l00810"></a>00810 <span class="preprocessor"></span>        uint16_t pwron_rxfsiz;
+<a name="l00811"></a>00811         uint16_t pwron_gnptxfsiz;
+<a name="l00812"></a>00812         uint16_t pwron_txfsiz[15];
+<a name="l00813"></a>00813 
+<a name="l00814"></a>00814         uint16_t init_rxfsiz;
+<a name="l00815"></a>00815         uint16_t init_gnptxfsiz;
+<a name="l00816"></a>00816         uint16_t init_txfsiz[15];
+<a name="l00817"></a>00817 <span class="preprocessor">#endif</span>
+<a name="l00818"></a>00818 <span class="preprocessor"></span>
+<a name="l00820"></a><a class="code" href="structdwc__otg__core__if.html#2b0701d814069ec69897e08374366c7b">00820</a>         dwc_otg_lx_state_e lx_state;
+<a name="l00821"></a>00821 
+<a name="l00822"></a>00822 };
+<a name="l00823"></a>00823 
+<a name="l00824"></a>00824 <span class="preprocessor">#ifdef DEBUG</span>
+<a name="l00825"></a>00825 <span class="preprocessor"></span><span class="comment">/*</span>
+<a name="l00826"></a>00826 <span class="comment"> * This function is called when transfer is timed out.</span>
+<a name="l00827"></a>00827 <span class="comment"> */</span>
+<a name="l00828"></a>00828 <span class="keyword">extern</span> <span class="keywordtype">void</span> hc_xfer_timeout(<span class="keywordtype">void</span> *ptr);
+<a name="l00829"></a>00829 <span class="preprocessor">#endif</span>
+<a name="l00830"></a>00830 <span class="preprocessor"></span>
+<a name="l00831"></a>00831 <span class="comment">/*</span>
+<a name="l00832"></a>00832 <span class="comment"> * The following functions are functions for works </span>
+<a name="l00833"></a>00833 <span class="comment"> * using during handling some interrupts</span>
+<a name="l00834"></a>00834 <span class="comment"> */</span>
+<a name="l00835"></a>00835 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8h.html#9ef061e0e79210e6c2a2c2b9cc45bd45">w_conn_id_status_change</a>(<span class="keywordtype">void</span> *<a class="code" href="structdwc__otg__cil__callbacks.html#a486473d73fb104dc3a37e963a8ef8e5">p</a>);
+<a name="l00836"></a>00836 
+<a name="l00837"></a>00837 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8h.html#07f0b189448c71e7ea4c7b121320fb89">w_wakeup_detected</a>(<span class="keywordtype">void</span> *<a class="code" href="structdwc__otg__cil__callbacks.html#a486473d73fb104dc3a37e963a8ef8e5">p</a>);
+<a name="l00838"></a>00838 
+<a name="l00839"></a>00839 <span class="comment">/*</span>
+<a name="l00840"></a>00840 <span class="comment"> * The following functions support initialization of the CIL driver component</span>
+<a name="l00841"></a>00841 <span class="comment"> * and the DWC_otg controller.</span>
+<a name="l00842"></a>00842 <span class="comment"> */</span>
+<a name="l00843"></a>00843 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#04ad276f20faad71333f6293c952744e">dwc_otg_core_host_init</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * _core_if);
+<a name="l00844"></a>00844 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#f79b0f3b5b96b0535e33627ee3a66eba">dwc_otg_core_dev_init</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * _core_if);
+<a name="l00845"></a>00845 
+<a name="l00851"></a>00851 <span class="keyword">extern</span> <span class="keywordtype">void</span> dwc_otg_wakeup(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * _core_if);
+<a name="l00852"></a>00852 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#b56e0d90c67bbf2829e630cafd630f17">dwc_otg_read_setup_packet</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * _core_if,
+<a name="l00853"></a>00853                                       uint32_t * _dest);
+<a name="l00854"></a>00854 <span class="keyword">extern</span> uint32_t <a class="code" href="dwc__otg__cil_8c.html#78f20f3acf6245b189abde83d9ce78f2">dwc_otg_get_frame_number</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * _core_if);
+<a name="l00855"></a>00855 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#8ebf5023c783a2ec48a18a5b9aef4a87">dwc_otg_ep0_activate</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * _core_if, <a class="code" href="structdwc__ep.html">dwc_ep_t</a> * _ep);
+<a name="l00856"></a>00856 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#5e5a1fb1ff70d5c42d8cf4a1c5d12b7f">dwc_otg_ep_activate</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * _core_if, <a class="code" href="structdwc__ep.html">dwc_ep_t</a> * _ep);
+<a name="l00857"></a>00857 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#94789f2d72adb5daf65c99eadced66b3">dwc_otg_ep_deactivate</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * _core_if, <a class="code" href="structdwc__ep.html">dwc_ep_t</a> * _ep);
+<a name="l00858"></a>00858 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#1278f6d58a4a2bc780e90e0b6c9b9a68">dwc_otg_ep_start_transfer</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * _core_if,
+<a name="l00859"></a>00859                                       <a class="code" href="structdwc__ep.html">dwc_ep_t</a> * _ep);
+<a name="l00860"></a>00860 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#fcc9f9b12c040c3649f0b8273a24ddf7">dwc_otg_ep_start_zl_transfer</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * _core_if,
+<a name="l00861"></a>00861                                          <a class="code" href="structdwc__ep.html">dwc_ep_t</a> * _ep);
+<a name="l00862"></a>00862 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#ee4989b24826b2a6592535282853e556">dwc_otg_ep0_start_transfer</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * _core_if,
+<a name="l00863"></a>00863                                        <a class="code" href="structdwc__ep.html">dwc_ep_t</a> * _ep);
+<a name="l00864"></a>00864 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#d8c1e6f7860c482df84db003b52c369c">dwc_otg_ep0_continue_transfer</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * _core_if,
+<a name="l00865"></a>00865                                           <a class="code" href="structdwc__ep.html">dwc_ep_t</a> * _ep);
+<a name="l00866"></a>00866 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#97a11808b8b12a365a91f02b6d686d0c">dwc_otg_ep_write_packet</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * _core_if,
+<a name="l00867"></a>00867                                     <a class="code" href="structdwc__ep.html">dwc_ep_t</a> * _ep, <span class="keywordtype">int</span> _dma);
+<a name="l00868"></a>00868 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#5edca13178261136209ed51360c850b4">dwc_otg_ep_set_stall</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * _core_if, <a class="code" href="structdwc__ep.html">dwc_ep_t</a> * _ep);
+<a name="l00869"></a>00869 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#a5f77318fb1c589406927a606844007f">dwc_otg_ep_clear_stall</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * _core_if,
+<a name="l00870"></a>00870                                    <a class="code" href="structdwc__ep.html">dwc_ep_t</a> * _ep);
+<a name="l00871"></a>00871 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#3d60e58f32be881047ac61bc852f60f7">dwc_otg_enable_device_interrupts</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * _core_if);
+<a name="l00872"></a>00872 
+<a name="l00873"></a>00873 <span class="preprocessor">#ifdef DWC_EN_ISOC</span>
+<a name="l00874"></a>00874 <span class="preprocessor"></span><span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#0f0894ae9890260e1da839aa10af35cc">dwc_otg_iso_ep_start_frm_transfer</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if,
+<a name="l00875"></a>00875                                               <a class="code" href="structdwc__ep.html">dwc_ep_t</a> * ep);
+<a name="l00876"></a>00876 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8h.html#0b13a31a7ddc82b53862cd06cfed6393">dwc_otg_iso_ep_start_buf_transfer</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if,
+<a name="l00877"></a>00877                                               <a class="code" href="structdwc__ep.html">dwc_ep_t</a> * ep);
+<a name="l00878"></a>00878 <span class="preprocessor">#endif                          </span><span class="comment">/* DWC_EN_ISOC */</span>
+<a name="l00879"></a>00879 
+<a name="l00886"></a>00886 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#7b04d5b3b31c79c73d577cfbb231998c">dwc_otg_hc_init</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * _core_if, <a class="code" href="structdwc__hc.html">dwc_hc_t</a> * _hc);
+<a name="l00887"></a>00887 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#de044bf6b96c1bac92259a447ae85c0f">dwc_otg_hc_halt</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * _core_if,
+<a name="l00888"></a>00888                             <a class="code" href="structdwc__hc.html">dwc_hc_t</a> * _hc, dwc_otg_halt_status_e _halt_status);
+<a name="l00889"></a>00889 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#f05341f811fba7f6183db66faf50a867">dwc_otg_hc_cleanup</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * _core_if, <a class="code" href="structdwc__hc.html">dwc_hc_t</a> * _hc);
+<a name="l00890"></a>00890 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#025af79d6a2255dba4578588be510444">dwc_otg_hc_start_transfer</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * _core_if,
+<a name="l00891"></a>00891                                       <a class="code" href="structdwc__hc.html">dwc_hc_t</a> * _hc);
+<a name="l00892"></a>00892 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#d848c41cdd739edd9271e1e207af9c9c">dwc_otg_hc_continue_transfer</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * _core_if,
+<a name="l00893"></a>00893                                         <a class="code" href="structdwc__hc.html">dwc_hc_t</a> * _hc);
+<a name="l00894"></a>00894 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#4185d0b9bb4a49d28894f957c2e41117">dwc_otg_hc_do_ping</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * _core_if, <a class="code" href="structdwc__hc.html">dwc_hc_t</a> * _hc);
+<a name="l00895"></a>00895 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#c4ccce95ab4067e03c089519c1b54a94">dwc_otg_hc_write_packet</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * _core_if,
+<a name="l00896"></a>00896                                     <a class="code" href="structdwc__hc.html">dwc_hc_t</a> * _hc);
+<a name="l00897"></a>00897 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#373701240c023fda03eed98cf093df74">dwc_otg_enable_host_interrupts</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * _core_if);
+<a name="l00898"></a>00898 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#4dd4a30dd75a819e9da38d6410cbb0a4">dwc_otg_disable_host_interrupts</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * _core_if);
+<a name="l00899"></a>00899 
+<a name="l00900"></a>00900 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#dbc20e9f9cadbdf4df65db3f82bbb820">dwc_otg_hc_start_transfer_ddma</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, <a class="code" href="structdwc__hc.html">dwc_hc_t</a> * hc);
+<a name="l00901"></a>00901 
+<a name="l00902"></a>00902 <span class="comment">/* Macro used to clear one channel interrupt */</span>
+<a name="l00903"></a><a class="code" href="dwc__otg__cil_8h.html#071cb1f3f29f9a52775e9fff270b1c7c">00903</a> <span class="preprocessor">#define clear_hc_int(_hc_regs_, _intr_) \</span>
+<a name="l00904"></a>00904 <span class="preprocessor">do { \</span>
+<a name="l00905"></a>00905 <span class="preprocessor">        hcint_data_t hcint_clear = {.d32 = 0}; \</span>
+<a name="l00906"></a>00906 <span class="preprocessor">        hcint_clear.b._intr_ = 1; \</span>
+<a name="l00907"></a>00907 <span class="preprocessor">        dwc_write_reg32(&amp;(_hc_regs_)-&gt;hcint, hcint_clear.d32); \</span>
+<a name="l00908"></a>00908 <span class="preprocessor">} while (0)</span>
+<a name="l00909"></a>00909 <span class="preprocessor"></span>
+<a name="l00910"></a>00910 <span class="comment">/*</span>
+<a name="l00911"></a>00911 <span class="comment"> * Macro used to disable one channel interrupt. Channel interrupts are</span>
+<a name="l00912"></a>00912 <span class="comment"> * disabled when the channel is halted or released by the interrupt handler.</span>
+<a name="l00913"></a>00913 <span class="comment"> * There is no need to handle further interrupts of that type until the</span>
+<a name="l00914"></a>00914 <span class="comment"> * channel is re-assigned. In fact, subsequent handling may cause crashes</span>
+<a name="l00915"></a>00915 <span class="comment"> * because the channel structures are cleaned up when the channel is released.</span>
+<a name="l00916"></a>00916 <span class="comment"> */</span>
+<a name="l00917"></a><a class="code" href="dwc__otg__cil_8h.html#e530fa4a6ed31f67cad65969355651ef">00917</a> <span class="preprocessor">#define disable_hc_int(_hc_regs_, _intr_) \</span>
+<a name="l00918"></a>00918 <span class="preprocessor">do { \</span>
+<a name="l00919"></a>00919 <span class="preprocessor">        hcintmsk_data_t hcintmsk = {.d32 = 0}; \</span>
+<a name="l00920"></a>00920 <span class="preprocessor">        hcintmsk.b._intr_ = 1; \</span>
+<a name="l00921"></a>00921 <span class="preprocessor">        dwc_modify_reg32(&amp;(_hc_regs_)-&gt;hcintmsk, hcintmsk.d32, 0); \</span>
+<a name="l00922"></a>00922 <span class="preprocessor">} while (0)</span>
+<a name="l00923"></a>00923 <span class="preprocessor"></span>                
+<a name="l00929"></a><a class="code" href="dwc__otg__cil_8h.html#ce67da6af4023cffd25333d20992438e">00929</a> <span class="keyword">static</span> <span class="keyword">inline</span> uint32_t <a class="code" href="dwc__otg__cil_8h.html#ce67da6af4023cffd25333d20992438e">dwc_otg_read_hprt0</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * _core_if)
+<a name="l00930"></a>00930 {
+<a name="l00931"></a>00931         <a class="code" href="unionhprt0__data.html">hprt0_data_t</a> hprt0;
+<a name="l00932"></a>00932         hprt0.<a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a> = dwc_read_reg32(_core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#dc8fe33e0bb3829cafa884d5fc603c4d">hprt0</a>);
+<a name="l00933"></a>00933         hprt0.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#a964274b5d22e89ca4490f66dff3c763">prtena</a> = 0;
+<a name="l00934"></a>00934         hprt0.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#5124a40eeafd92c9632c91a2c3132937">prtconndet</a> = 0;
+<a name="l00935"></a>00935         hprt0.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#75eae10eb537e49cc1ae2dc01c18aa47">prtenchng</a> = 0;
+<a name="l00936"></a>00936         hprt0.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#cc51da1d52cb824d419ef3feb6ba70b6">prtovrcurrchng</a> = 0;
+<a name="l00937"></a>00937         <span class="keywordflow">return</span> hprt0.<a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a>;
+<a name="l00938"></a>00938 }
+<a name="l00939"></a>00939 
+<a name="l00948"></a>00948 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#68f59dd23ccfffa9aa1dc590e99b7668">dwc_otg_read_packet</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if,
+<a name="l00949"></a>00949                                 uint8_t * dest, uint16_t bytes);
+<a name="l00950"></a>00950 
+<a name="l00951"></a>00951 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#039e387cd0e0282727da3c5a36f4cdda">dwc_otg_flush_tx_fifo</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * _core_if, <span class="keyword">const</span> <span class="keywordtype">int</span> _num);
+<a name="l00952"></a>00952 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#fb275f0f9923cc30629fce5e3753025c">dwc_otg_flush_rx_fifo</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * _core_if);
+<a name="l00953"></a>00953 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#1edfc5634dd76db76e30f20affc10f0c">dwc_otg_core_reset</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * _core_if);
+<a name="l00954"></a>00954 
+<a name="l00958"></a><a class="code" href="dwc__otg__cil_8h.html#639809e3c27026b8f956c2a133b1d433">00958</a> <span class="keyword">static</span> <span class="keyword">inline</span> uint32_t <a class="code" href="dwc__otg__cil_8h.html#639809e3c27026b8f956c2a133b1d433">dwc_otg_read_core_intr</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l00959"></a>00959 {
+<a name="l00960"></a>00960         <span class="keywordflow">return</span> (dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>) &amp;
+<a name="l00961"></a>00961                 dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#48827c76da2c6b18f369e2f2483cc4b6">gintmsk</a>));
+<a name="l00962"></a>00962 }
+<a name="l00963"></a>00963 
+<a name="l00967"></a><a class="code" href="dwc__otg__cil_8h.html#6f5d7863a0e519c8e2e331da3029b579">00967</a> <span class="keyword">static</span> <span class="keyword">inline</span> uint32_t <a class="code" href="dwc__otg__cil_8h.html#6f5d7863a0e519c8e2e331da3029b579">dwc_otg_read_otg_intr</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l00968"></a>00968 {
+<a name="l00969"></a>00969         <span class="keywordflow">return</span> (dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#69cc290cfdfe6900890f7a5a16b3137c">gotgint</a>));
+<a name="l00970"></a>00970 }
+<a name="l00971"></a>00971 
+<a name="l00976"></a><a class="code" href="dwc__otg__cil_8h.html#574c9a2a3f7fa76d93e735daf2c64e2f">00976</a> <span class="keyword">static</span> <span class="keyword">inline</span> uint32_t <a class="code" href="dwc__otg__cil_8h.html#574c9a2a3f7fa76d93e735daf2c64e2f">dwc_otg_read_dev_all_in_ep_intr</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *
+<a name="l00977"></a>00977                                                        core_if)
+<a name="l00978"></a>00978 {
+<a name="l00979"></a>00979 
+<a name="l00980"></a>00980         uint32_t v;
+<a name="l00981"></a>00981 
+<a name="l00982"></a>00982         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5675c8d8dd7df746fda9157dc39ba5c2">multiproc_int_enable</a>) {
+<a name="l00983"></a>00983                 v = dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;
+<a name="l00984"></a>00984                                    deachint) &amp; dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;
+<a name="l00985"></a>00985                                                               dev_global_regs-&gt;
+<a name="l00986"></a>00986                                                               deachintmsk);
+<a name="l00987"></a>00987         } <span class="keywordflow">else</span> {
+<a name="l00988"></a>00988                 v = dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#2e25df2fbec9d398742709524056cbd5">daint</a>) &amp;
+<a name="l00989"></a>00989                     dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#5def6c3850c041928b9a662422ee0679">daintmsk</a>);
+<a name="l00990"></a>00990         }
+<a name="l00991"></a>00991         <span class="keywordflow">return</span> (v &amp; 0xffff);
+<a name="l00992"></a>00992 }
+<a name="l00993"></a>00993 
+<a name="l00998"></a><a class="code" href="dwc__otg__cil_8h.html#43d4fc3ed87fc91c58c0299a9f3e82fe">00998</a> <span class="keyword">static</span> <span class="keyword">inline</span> uint32_t <a class="code" href="dwc__otg__cil_8h.html#43d4fc3ed87fc91c58c0299a9f3e82fe">dwc_otg_read_dev_all_out_ep_intr</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *
+<a name="l00999"></a>00999                                                         core_if)
+<a name="l01000"></a>01000 {
+<a name="l01001"></a>01001         uint32_t v;
+<a name="l01002"></a>01002 
+<a name="l01003"></a>01003         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5675c8d8dd7df746fda9157dc39ba5c2">multiproc_int_enable</a>) {
+<a name="l01004"></a>01004                 v = dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;
+<a name="l01005"></a>01005                                    deachint) &amp; dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;
+<a name="l01006"></a>01006                                                               dev_global_regs-&gt;
+<a name="l01007"></a>01007                                                               deachintmsk);
+<a name="l01008"></a>01008         } <span class="keywordflow">else</span> {
+<a name="l01009"></a>01009                 v = dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#2e25df2fbec9d398742709524056cbd5">daint</a>) &amp;
+<a name="l01010"></a>01010                     dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#5def6c3850c041928b9a662422ee0679">daintmsk</a>);
+<a name="l01011"></a>01011         }
+<a name="l01012"></a>01012 
+<a name="l01013"></a>01013         <span class="keywordflow">return</span> ((v &amp; 0xffff0000) &gt;&gt; 16);
+<a name="l01014"></a>01014 }
+<a name="l01015"></a>01015 
+<a name="l01019"></a><a class="code" href="dwc__otg__cil_8h.html#d14e93e73613cfa13336db4da4ee2f20">01019</a> <span class="keyword">static</span> <span class="keyword">inline</span> uint32_t <a class="code" href="dwc__otg__cil_8h.html#d14e93e73613cfa13336db4da4ee2f20">dwc_otg_read_dev_in_ep_intr</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if,
+<a name="l01020"></a>01020                                                    <a class="code" href="structdwc__ep.html">dwc_ep_t</a> * ep)
+<a name="l01021"></a>01021 {
+<a name="l01022"></a>01022         <a class="code" href="structdwc__otg__dev__if.html">dwc_otg_dev_if_t</a> *dev_if = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>;
+<a name="l01023"></a>01023         uint32_t v, msk, emp;
+<a name="l01024"></a>01024 
+<a name="l01025"></a>01025         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5675c8d8dd7df746fda9157dc39ba5c2">multiproc_int_enable</a>) {
+<a name="l01026"></a>01026                 msk =
+<a name="l01027"></a>01027                     dwc_read_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;
+<a name="l01028"></a>01028                                    diepeachintmsk[ep-&gt;<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a>]);
+<a name="l01029"></a>01029                 emp =
+<a name="l01030"></a>01030                     dwc_read_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;
+<a name="l01031"></a>01031                                    dtknqr4_fifoemptymsk);
+<a name="l01032"></a>01032                 msk |= ((emp &gt;&gt; ep-&gt;<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a>) &amp; 0x1) &lt;&lt; 7;
+<a name="l01033"></a>01033                 v = dwc_read_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[ep-&gt;<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a>]-&gt;diepint) &amp; msk;
+<a name="l01034"></a>01034         } <span class="keywordflow">else</span> {
+<a name="l01035"></a>01035                 msk = dwc_read_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#02e44cb182548d78c5b7d27929ca5f11">diepmsk</a>);
+<a name="l01036"></a>01036                 emp =
+<a name="l01037"></a>01037                     dwc_read_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;
+<a name="l01038"></a>01038                                    dtknqr4_fifoemptymsk);
+<a name="l01039"></a>01039                 msk |= ((emp &gt;&gt; ep-&gt;<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a>) &amp; 0x1) &lt;&lt; 7;
+<a name="l01040"></a>01040                 v = dwc_read_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[ep-&gt;<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a>]-&gt;diepint) &amp; msk;
+<a name="l01041"></a>01041         }
+<a name="l01042"></a>01042 
+<a name="l01043"></a>01043         <span class="keywordflow">return</span> v;
+<a name="l01044"></a>01044 }
+<a name="l01045"></a>01045 
+<a name="l01049"></a><a class="code" href="dwc__otg__cil_8h.html#01199eaadd2a7b875c1841d13ee3728b">01049</a> <span class="keyword">static</span> <span class="keyword">inline</span> uint32_t <a class="code" href="dwc__otg__cil_8h.html#01199eaadd2a7b875c1841d13ee3728b">dwc_otg_read_dev_out_ep_intr</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *
+<a name="l01050"></a>01050                                                     _core_if, <a class="code" href="structdwc__ep.html">dwc_ep_t</a> * _ep)
+<a name="l01051"></a>01051 {
+<a name="l01052"></a>01052         <a class="code" href="structdwc__otg__dev__if.html">dwc_otg_dev_if_t</a> *dev_if = _core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>;
+<a name="l01053"></a>01053         uint32_t v;
+<a name="l01054"></a>01054         <a class="code" href="uniondoepint__data.html">doepmsk_data_t</a> msk = {.d32 = 0 };
+<a name="l01055"></a>01055 
+<a name="l01056"></a>01056         <span class="keywordflow">if</span> (_core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5675c8d8dd7df746fda9157dc39ba5c2">multiproc_int_enable</a>) {
+<a name="l01057"></a>01057                 msk.<a class="code" href="uniondoepint__data.html#94f8c8fc116b430565f9322e3621b3a5">d32</a> =
+<a name="l01058"></a>01058                     dwc_read_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;
+<a name="l01059"></a>01059                                    doepeachintmsk[_ep-&gt;<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a>]);
+<a name="l01060"></a>01060                 <span class="keywordflow">if</span> (_core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#34540b79e9a14bfa234a52ac132c5cd1">pti_enh_enable</a>) {
+<a name="l01061"></a>01061                         msk.<a class="code" href="uniondoepint__data.html#9e966d9f85589f278dc2c0d0c7833856">b</a>.<a class="code" href="uniondoepint__data.html#0c8fc4f5245a9874c0c3b61d1c6f719d">pktdrpsts</a> = 1;
+<a name="l01062"></a>01062                 }
+<a name="l01063"></a>01063                 v = dwc_read_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">out_ep_regs</a>[_ep-&gt;<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a>]-&gt;
+<a name="l01064"></a>01064                                    doepint) &amp; msk.<a class="code" href="uniondoepint__data.html#94f8c8fc116b430565f9322e3621b3a5">d32</a>;
+<a name="l01065"></a>01065         } <span class="keywordflow">else</span> {
+<a name="l01066"></a>01066                 msk.<a class="code" href="uniondoepint__data.html#94f8c8fc116b430565f9322e3621b3a5">d32</a> = dwc_read_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#d6947be9d84a1d87156f81a10ebb036b">doepmsk</a>);
+<a name="l01067"></a>01067                 <span class="keywordflow">if</span> (_core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#34540b79e9a14bfa234a52ac132c5cd1">pti_enh_enable</a>) {
+<a name="l01068"></a>01068                         msk.<a class="code" href="uniondoepint__data.html#9e966d9f85589f278dc2c0d0c7833856">b</a>.<a class="code" href="uniondoepint__data.html#0c8fc4f5245a9874c0c3b61d1c6f719d">pktdrpsts</a> = 1;
+<a name="l01069"></a>01069                 }
+<a name="l01070"></a>01070                 v = dwc_read_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">out_ep_regs</a>[_ep-&gt;<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a>]-&gt;
+<a name="l01071"></a>01071                                    doepint) &amp; msk.<a class="code" href="uniondoepint__data.html#94f8c8fc116b430565f9322e3621b3a5">d32</a>;
+<a name="l01072"></a>01072         }
+<a name="l01073"></a>01073         <span class="keywordflow">return</span> v;
+<a name="l01074"></a>01074 }
+<a name="l01075"></a>01075 
+<a name="l01079"></a><a class="code" href="dwc__otg__cil_8h.html#ddc68d442228b5b0600e7ee26c641700">01079</a> <span class="keyword">static</span> <span class="keyword">inline</span> uint32_t <a class="code" href="dwc__otg__cil_8h.html#ddc68d442228b5b0600e7ee26c641700">dwc_otg_read_host_all_channels_intr</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *
+<a name="l01080"></a>01080                                                            _core_if)
+<a name="l01081"></a>01081 {
+<a name="l01082"></a>01082         <span class="keywordflow">return</span> (dwc_read_reg32(&amp;_core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#ff9692c2e10ca2bc7e24f981f25179c2">host_global_regs</a>-&gt;<a class="code" href="structdwc__otg__host__global__regs.html#7c41808b0a69ed7d2125eb3afbbf6c14">haint</a>));
+<a name="l01083"></a>01083 }
+<a name="l01084"></a>01084 
+<a name="l01085"></a><a class="code" href="dwc__otg__cil_8h.html#65dda5b1d8f94672a6123536574448c4">01085</a> <span class="keyword">static</span> <span class="keyword">inline</span> uint32_t <a class="code" href="dwc__otg__cil_8h.html#65dda5b1d8f94672a6123536574448c4">dwc_otg_read_host_channel_intr</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *
+<a name="l01086"></a>01086                                                       _core_if, <a class="code" href="structdwc__hc.html">dwc_hc_t</a> * _hc)
+<a name="l01087"></a>01087 {
+<a name="l01088"></a>01088         <span class="keywordflow">return</span> (dwc_read_reg32
+<a name="l01089"></a>01089                 (&amp;_core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#7f7c107d4720641eb4141cd817211ac0">hc_regs</a>[_hc-&gt;<a class="code" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">hc_num</a>]-&gt;hcint));
+<a name="l01090"></a>01090 }
+<a name="l01091"></a>01091 
+<a name="l01097"></a><a class="code" href="dwc__otg__cil_8h.html#de0ac73b05fc306b04614f73b890a364">01097</a> <span class="keyword">static</span> <span class="keyword">inline</span> uint32_t <a class="code" href="dwc__otg__cil_8h.html#de0ac73b05fc306b04614f73b890a364">dwc_otg_mode</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * _core_if)
+<a name="l01098"></a>01098 {
+<a name="l01099"></a>01099         <span class="keywordflow">return</span> (dwc_read_reg32(&amp;_core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>) &amp; 0x1);
+<a name="l01100"></a>01100 }
+<a name="l01101"></a>01101 
+<a name="l01109"></a><a class="code" href="structdwc__otg__cil__callbacks.html">01109</a> <span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code" href="structdwc__otg__cil__callbacks.html">dwc_otg_cil_callbacks</a> {
+<a name="l01111"></a>01111         int (*start) (<span class="keywordtype">void</span> *_p);
+<a name="l01113"></a>01113         int (*stop) (<span class="keywordtype">void</span> *_p);
+<a name="l01115"></a>01115         int (*disconnect) (<span class="keywordtype">void</span> *_p);
+<a name="l01117"></a>01117         int (*resume_wakeup) (<span class="keywordtype">void</span> *_p);
+<a name="l01119"></a>01119         int (*suspend) (<span class="keywordtype">void</span> *_p);
+<a name="l01121"></a>01121         int (*session_start) (<span class="keywordtype">void</span> *_p);
+<a name="l01122"></a>01122 <span class="preprocessor">#ifdef CONFIG_USB_DWC_OTG_LPM</span>
+<a name="l01123"></a>01123 <span class="preprocessor"></span>
+<a name="l01124"></a>01124         int (*sleep) (<span class="keywordtype">void</span> *_p);
+<a name="l01125"></a>01125 <span class="preprocessor">#endif</span>
+<a name="l01126"></a>01126 <span class="preprocessor"></span>
+<a name="l01127"></a><a class="code" href="structdwc__otg__cil__callbacks.html#a486473d73fb104dc3a37e963a8ef8e5">01127</a>         <span class="keywordtype">void</span> *p;
+<a name="l01128"></a>01128 } <a class="code" href="structdwc__otg__cil__callbacks.html">dwc_otg_cil_callbacks_t</a>;
+<a name="l01129"></a>01129 
+<a name="l01130"></a>01130 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#d2a92003214f444d7ec35dd0c4bb4bc0">dwc_otg_cil_register_pcd_callbacks</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * _core_if,
+<a name="l01131"></a>01131                                                <a class="code" href="structdwc__otg__cil__callbacks.html">dwc_otg_cil_callbacks_t</a> * _cb,
+<a name="l01132"></a>01132                                                <span class="keywordtype">void</span> *_p);
+<a name="l01133"></a>01133 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#97c9b9d68211477e486848203def0d0f">dwc_otg_cil_register_hcd_callbacks</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * _core_if,
+<a name="l01134"></a>01134                                                <a class="code" href="structdwc__otg__cil__callbacks.html">dwc_otg_cil_callbacks_t</a> * _cb,
+<a name="l01135"></a>01135                                                <span class="keywordtype">void</span> *_p);
+<a name="l01136"></a>01136 
+<a name="l01137"></a>01137 <span class="preprocessor">#endif</span>
+</pre></div><hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil_8h.html b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil_8h.html
new file mode 100644
index 000000000000..708233e04595
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil_8h.html
@@ -0,0 +1,1844 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_cil.h File Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<h1>dwc_otg_cil.h File Reference</h1>This file contains the interface to the Core Interface Layer. <a href="#_details">More...</a>
+<p>
+<code>#include &quot;dwc_os.h&quot;</code><br>
+<code>#include &quot;dwc_list.h&quot;</code><br>
+<code>#include &quot;<a class="el" href="dwc__otg__dbg_8h-source.html">dwc_otg_dbg.h</a>&quot;</code><br>
+<code>#include &quot;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&quot;</code><br>
+<code>#include &quot;<a class="el" href="dwc__otg__core__if_8h-source.html">dwc_otg_core_if.h</a>&quot;</code><br>
+
+<p>
+<a href="dwc__otg__cil_8h-source.html">Go to the source code of this file.</a><table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Structures</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structiso__pkt__info.html">iso_pkt_info</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Information for each ISOC packet.  <a href="structiso__pkt__info.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__ep.html">dwc_ep</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">The <code><a class="el" href="structdwc__ep.html">dwc_ep</a></code> structure represents the state of a single endpoint when acting in device mode.  <a href="structdwc__ep.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__hc.html">dwc_hc</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Host channel descriptor.  <a href="structdwc__hc.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__params.html">dwc_otg_core_params</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">The following parameters may be specified when starting the module.  <a href="structdwc__otg__core__params.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">The <code><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if</a></code> structure contains information needed to manage the DWC_otg controller acting in either host or device mode.  <a href="structdwc__otg__core__if.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__cil__callbacks.html">dwc_otg_cil_callbacks</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">DWC_otg CIL callback structure.  <a href="structdwc__otg__cil__callbacks.html#_details">More...</a><br></td></tr>
+<tr><td colspan="2"><br><h2>Host CIL Functions</h2></td></tr>
+<tr><td colspan="2">The following functions support managing the DWC_otg controller in host mode. <br><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#071cb1f3f29f9a52775e9fff270b1c7c">clear_hc_int</a>(_hc_regs_, _intr_)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#e530fa4a6ed31f67cad65969355651ef">disable_hc_int</a>(_hc_regs_, _intr_)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#f2f5f8703a3292608f1cb756d0d5c4ea">dwc_otg_hc_init</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *_core_if, <a class="el" href="structdwc__hc.html">dwc_hc_t</a> *_hc)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Prepares a host channel for transferring packets to/from a specific endpoint.  <a href="#f2f5f8703a3292608f1cb756d0d5c4ea"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#ec2bad3cbf8baa9b4932d84719e952e1">dwc_otg_hc_halt</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *_core_if, <a class="el" href="structdwc__hc.html">dwc_hc_t</a> *_hc, dwc_otg_halt_status_e _halt_status)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Attempts to halt a host channel.  <a href="#ec2bad3cbf8baa9b4932d84719e952e1"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#99d4028c98b445a925ea5068b399d319">dwc_otg_hc_cleanup</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *_core_if, <a class="el" href="structdwc__hc.html">dwc_hc_t</a> *_hc)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Clears the transfer state for a host channel.  <a href="#99d4028c98b445a925ea5068b399d319"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#0e66d54f3126186b0548743eb4641ad6">dwc_otg_hc_start_transfer</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *_core_if, <a class="el" href="structdwc__hc.html">dwc_hc_t</a> *_hc)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function does the setup for a data transfer for a host channel and starts the transfer.  <a href="#0e66d54f3126186b0548743eb4641ad6"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#1677ed41bf5cf0c64cdcec47265a4052">dwc_otg_hc_continue_transfer</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *_core_if, <a class="el" href="structdwc__hc.html">dwc_hc_t</a> *_hc)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function continues a data transfer that was started by previous call to <code>dwc_otg_hc_start_transfer</code>.  <a href="#1677ed41bf5cf0c64cdcec47265a4052"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#ca1e0ad294962a68562280543947446e">dwc_otg_hc_do_ping</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *_core_if, <a class="el" href="structdwc__hc.html">dwc_hc_t</a> *_hc)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Starts a PING transfer.  <a href="#ca1e0ad294962a68562280543947446e"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="5cc27afc02b8f7199e3cf5f02ddbdeee"></a><!-- doxytag: member="dwc_otg_cil.h::dwc_otg_hc_write_packet" ref="5cc27afc02b8f7199e3cf5f02ddbdeee" args="(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#5cc27afc02b8f7199e3cf5f02ddbdeee">dwc_otg_hc_write_packet</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *_core_if, <a class="el" href="structdwc__hc.html">dwc_hc_t</a> *_hc)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#99a7497537db075b95c72816e766acf8">dwc_otg_enable_host_interrupts</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *_core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function enables the Host mode interrupts.  <a href="#99a7497537db075b95c72816e766acf8"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#6f3cf40d961167bf8c5888bcf577c15b">dwc_otg_disable_host_interrupts</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *_core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function disables the Host Mode interrupts.  <a href="#6f3cf40d961167bf8c5888bcf577c15b"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#dbc20e9f9cadbdf4df65db3f82bbb820">dwc_otg_hc_start_transfer_ddma</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, <a class="el" href="structdwc__hc.html">dwc_hc_t</a> *hc)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function does the setup for a data transfer for a host channel and starts the transfer in Descriptor DMA mode.  <a href="#dbc20e9f9cadbdf4df65db3f82bbb820"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#ce67da6af4023cffd25333d20992438e">dwc_otg_read_hprt0</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *_core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function Reads HPRT0 in preparation to modify.  <a href="#ce67da6af4023cffd25333d20992438e"></a><br></td></tr>
+<tr><td colspan="2"><br><h2>Device CIL Functions</h2></td></tr>
+<tr><td colspan="2">The following functions support managing the DWC_otg controller in device mode. <br><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="88a31fe802a64ad8f866e3d362d3a74e"></a><!-- doxytag: member="dwc_otg_cil.h::dwc_otg_wakeup" ref="88a31fe802a64ad8f866e3d362d3a74e" args="(dwc_otg_core_if_t *_core_if)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_otg_wakeup</b> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *_core_if)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#674adeecada7af04f0d43aa819469b71">dwc_otg_read_setup_packet</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *_core_if, uint32_t *_dest)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function reads a setup packet from the Rx FIFO into the destination buffer.  <a href="#674adeecada7af04f0d43aa819469b71"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#9e8d3f050dc72eeaad2541bfd9796879">dwc_otg_get_frame_number</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *_core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Gets the current USB frame number.  <a href="#9e8d3f050dc72eeaad2541bfd9796879"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#382592a5e686a82ece47d7634800aae3">dwc_otg_ep0_activate</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *_core_if, <a class="el" href="structdwc__ep.html">dwc_ep_t</a> *_ep)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function enables EP0 OUT to receive SETUP packets and configures EP0 IN for transmitting packets.  <a href="#382592a5e686a82ece47d7634800aae3"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#ceb07d2056baad0974dedf55cf9cab80">dwc_otg_ep_activate</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *_core_if, <a class="el" href="structdwc__ep.html">dwc_ep_t</a> *_ep)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function activates an EP.  <a href="#ceb07d2056baad0974dedf55cf9cab80"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#e813a4a71aab8a37f63790d3450367ec">dwc_otg_ep_deactivate</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *_core_if, <a class="el" href="structdwc__ep.html">dwc_ep_t</a> *_ep)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function deactivates an EP.  <a href="#e813a4a71aab8a37f63790d3450367ec"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#aa731bad72017df1111f0f31bcbc7f33">dwc_otg_ep_start_transfer</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *_core_if, <a class="el" href="structdwc__ep.html">dwc_ep_t</a> *_ep)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function does the setup for a data transfer for an EP and starts the transfer.  <a href="#aa731bad72017df1111f0f31bcbc7f33"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#fc1d9180b7d4e894214afddde1f4397e">dwc_otg_ep_start_zl_transfer</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *_core_if, <a class="el" href="structdwc__ep.html">dwc_ep_t</a> *_ep)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function setup a zero length transfer in Buffer DMA and Slave modes for usb requests with zero field set.  <a href="#fc1d9180b7d4e894214afddde1f4397e"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#d4a111ecd96bec3afd3b7c0421af9652">dwc_otg_ep0_start_transfer</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *_core_if, <a class="el" href="structdwc__ep.html">dwc_ep_t</a> *_ep)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function does the setup for a data transfer for EP0 and starts the transfer.  <a href="#d4a111ecd96bec3afd3b7c0421af9652"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#e52e9ca5ecba4797f51be5e30f1c6fbc">dwc_otg_ep0_continue_transfer</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *_core_if, <a class="el" href="structdwc__ep.html">dwc_ep_t</a> *_ep)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function continues control IN transfers started by dwc_otg_ep0_start_transfer, when the transfer does not fit in a single packet.  <a href="#e52e9ca5ecba4797f51be5e30f1c6fbc"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#42cba51a650375f6a18f4136cb4dba92">dwc_otg_ep_write_packet</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *_core_if, <a class="el" href="structdwc__ep.html">dwc_ep_t</a> *_ep, int _dma)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function writes a packet into the Tx FIFO associated with the EP.  <a href="#42cba51a650375f6a18f4136cb4dba92"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#e1490c2dd3586403cf3fe12c716b41b2">dwc_otg_ep_set_stall</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *_core_if, <a class="el" href="structdwc__ep.html">dwc_ep_t</a> *_ep)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Set the EP STALL.  <a href="#e1490c2dd3586403cf3fe12c716b41b2"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#45d65850c250067079f80c3ba87ef077">dwc_otg_ep_clear_stall</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *_core_if, <a class="el" href="structdwc__ep.html">dwc_ep_t</a> *_ep)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Clear the EP STALL.  <a href="#45d65850c250067079f80c3ba87ef077"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#ea31a3abac0bdb1ede29a9d65c402553">dwc_otg_enable_device_interrupts</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *_core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function enables the Device mode interrupts.  <a href="#ea31a3abac0bdb1ede29a9d65c402553"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#0f0894ae9890260e1da839aa10af35cc">dwc_otg_iso_ep_start_frm_transfer</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, <a class="el" href="structdwc__ep.html">dwc_ep_t</a> *ep)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function initializes a descriptor chain for Isochronous transfer.  <a href="#0f0894ae9890260e1da839aa10af35cc"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#0b13a31a7ddc82b53862cd06cfed6393">dwc_otg_iso_ep_start_buf_transfer</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, <a class="el" href="structdwc__ep.html">dwc_ep_t</a> *ep)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function initializes a descriptor chain for Isochronous transfer.  <a href="#0b13a31a7ddc82b53862cd06cfed6393"></a><br></td></tr>
+<tr><td colspan="2"><br><h2>Common CIL Functions</h2></td></tr>
+<tr><td colspan="2">The following functions support managing the DWC_otg controller in either device or host mode. <br><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#68f59dd23ccfffa9aa1dc590e99b7668">dwc_otg_read_packet</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, uint8_t *dest, uint16_t bytes)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function reads a packet from the Rx FIFO into the destination buffer.  <a href="#68f59dd23ccfffa9aa1dc590e99b7668"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#f92d866287dce46d9e150c48901086bf">dwc_otg_flush_tx_fifo</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *_core_if, const int _num)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Flush a Tx FIFO.  <a href="#f92d866287dce46d9e150c48901086bf"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#07661371177fec53ba6d020320f2bae8">dwc_otg_flush_rx_fifo</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *_core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Flush Rx FIFO.  <a href="#07661371177fec53ba6d020320f2bae8"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#c8466c3cd6229625268ec423c4b44aa4">dwc_otg_core_reset</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *_core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Do core a soft reset of the core.  <a href="#c8466c3cd6229625268ec423c4b44aa4"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="639809e3c27026b8f956c2a133b1d433"></a><!-- doxytag: member="dwc_otg_cil.h::dwc_otg_read_core_intr" ref="639809e3c27026b8f956c2a133b1d433" args="(dwc_otg_core_if_t *core_if)" -->
+static uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#639809e3c27026b8f956c2a133b1d433">dwc_otg_read_core_intr</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function returns the Core Interrupt register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="6f5d7863a0e519c8e2e331da3029b579"></a><!-- doxytag: member="dwc_otg_cil.h::dwc_otg_read_otg_intr" ref="6f5d7863a0e519c8e2e331da3029b579" args="(dwc_otg_core_if_t *core_if)" -->
+static uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#6f5d7863a0e519c8e2e331da3029b579">dwc_otg_read_otg_intr</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function returns the OTG Interrupt register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="574c9a2a3f7fa76d93e735daf2c64e2f"></a><!-- doxytag: member="dwc_otg_cil.h::dwc_otg_read_dev_all_in_ep_intr" ref="574c9a2a3f7fa76d93e735daf2c64e2f" args="(dwc_otg_core_if_t *core_if)" -->
+static uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#574c9a2a3f7fa76d93e735daf2c64e2f">dwc_otg_read_dev_all_in_ep_intr</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function reads the Device All Endpoints Interrupt register and returns the IN endpoint interrupt bits. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="43d4fc3ed87fc91c58c0299a9f3e82fe"></a><!-- doxytag: member="dwc_otg_cil.h::dwc_otg_read_dev_all_out_ep_intr" ref="43d4fc3ed87fc91c58c0299a9f3e82fe" args="(dwc_otg_core_if_t *core_if)" -->
+static uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#43d4fc3ed87fc91c58c0299a9f3e82fe">dwc_otg_read_dev_all_out_ep_intr</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function reads the Device All Endpoints Interrupt register and returns the OUT endpoint interrupt bits. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="d14e93e73613cfa13336db4da4ee2f20"></a><!-- doxytag: member="dwc_otg_cil.h::dwc_otg_read_dev_in_ep_intr" ref="d14e93e73613cfa13336db4da4ee2f20" args="(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)" -->
+static uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#d14e93e73613cfa13336db4da4ee2f20">dwc_otg_read_dev_in_ep_intr</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, <a class="el" href="structdwc__ep.html">dwc_ep_t</a> *ep)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function returns the Device IN EP Interrupt register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="01199eaadd2a7b875c1841d13ee3728b"></a><!-- doxytag: member="dwc_otg_cil.h::dwc_otg_read_dev_out_ep_intr" ref="01199eaadd2a7b875c1841d13ee3728b" args="(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)" -->
+static uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#01199eaadd2a7b875c1841d13ee3728b">dwc_otg_read_dev_out_ep_intr</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *_core_if, <a class="el" href="structdwc__ep.html">dwc_ep_t</a> *_ep)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function returns the Device OUT EP Interrupt register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ddc68d442228b5b0600e7ee26c641700"></a><!-- doxytag: member="dwc_otg_cil.h::dwc_otg_read_host_all_channels_intr" ref="ddc68d442228b5b0600e7ee26c641700" args="(dwc_otg_core_if_t *_core_if)" -->
+static uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#ddc68d442228b5b0600e7ee26c641700">dwc_otg_read_host_all_channels_intr</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *_core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function returns the Host All Channel Interrupt register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="65dda5b1d8f94672a6123536574448c4"></a><!-- doxytag: member="dwc_otg_cil.h::dwc_otg_read_host_channel_intr" ref="65dda5b1d8f94672a6123536574448c4" args="(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)" -->
+static uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#65dda5b1d8f94672a6123536574448c4">dwc_otg_read_host_channel_intr</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *_core_if, <a class="el" href="structdwc__hc.html">dwc_hc_t</a> *_hc)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#de0ac73b05fc306b04614f73b890a364">dwc_otg_mode</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *_core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function returns the mode of the operation, host or device.  <a href="#de0ac73b05fc306b04614f73b890a364"></a><br></td></tr>
+<tr><td colspan="2"><br><h2>Defines</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c9555551bb7f2d0a51be23d54463f2ec"></a><!-- doxytag: member="dwc_otg_cil.h::__DWC_CIL_H__" ref="c9555551bb7f2d0a51be23d54463f2ec" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#c9555551bb7f2d0a51be23d54463f2ec">__DWC_CIL_H__</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="51536e4844fe9022b60531eebca32a26"></a><!-- doxytag: member="dwc_otg_cil.h::OTG_CORE_REV_2_60a" ref="51536e4844fe9022b60531eebca32a26" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#51536e4844fe9022b60531eebca32a26">OTG_CORE_REV_2_60a</a>&nbsp;&nbsp;&nbsp;0x4F54260A</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Macros defined for DWC OTG HW Release verison. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="aac1e3cc465029aa0a2965b7c6d9fc50"></a><!-- doxytag: member="dwc_otg_cil.h::OTG_CORE_REV_2_71a" ref="aac1e3cc465029aa0a2965b7c6d9fc50" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#aac1e3cc465029aa0a2965b7c6d9fc50">OTG_CORE_REV_2_71a</a>&nbsp;&nbsp;&nbsp;0x4F54271A</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3d25615a19f95042bcc3512b4855cebe"></a><!-- doxytag: member="dwc_otg_cil.h::OTG_CORE_REV_2_72a" ref="3d25615a19f95042bcc3512b4855cebe" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#3d25615a19f95042bcc3512b4855cebe">OTG_CORE_REV_2_72a</a>&nbsp;&nbsp;&nbsp;0x4F54272A</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="02c75ff58b0b88ae59c89063478648dd"></a><!-- doxytag: member="dwc_otg_cil.h::OTG_CORE_REV_2_80a" ref="02c75ff58b0b88ae59c89063478648dd" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#02c75ff58b0b88ae59c89063478648dd">OTG_CORE_REV_2_80a</a>&nbsp;&nbsp;&nbsp;0x4F54280A</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ceb592db3a34e7435e6bd9fc4cf5627c"></a><!-- doxytag: member="dwc_otg_cil.h::OTG_CORE_REV_2_81a" ref="ceb592db3a34e7435e6bd9fc4cf5627c" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#ceb592db3a34e7435e6bd9fc4cf5627c">OTG_CORE_REV_2_81a</a>&nbsp;&nbsp;&nbsp;0x4F54281A</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c2f4aa7b1cfc164330925404c5029724"></a><!-- doxytag: member="dwc_otg_cil.h::OTG_CORE_REV_2_90a" ref="c2f4aa7b1cfc164330925404c5029724" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#c2f4aa7b1cfc164330925404c5029724">OTG_CORE_REV_2_90a</a>&nbsp;&nbsp;&nbsp;0x4F54290A</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="64e5cd756330f5adab79b25cc8067bdc"></a><!-- doxytag: member="dwc_otg_cil.h::DWC_OTG_EP_TYPE_CONTROL" ref="64e5cd756330f5adab79b25cc8067bdc" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#64e5cd756330f5adab79b25cc8067bdc">DWC_OTG_EP_TYPE_CONTROL</a>&nbsp;&nbsp;&nbsp;0</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="152a3a5e1433bd2197672f0b5105e7a4"></a><!-- doxytag: member="dwc_otg_cil.h::DWC_OTG_EP_TYPE_ISOC" ref="152a3a5e1433bd2197672f0b5105e7a4" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#152a3a5e1433bd2197672f0b5105e7a4">DWC_OTG_EP_TYPE_ISOC</a>&nbsp;&nbsp;&nbsp;1</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="9b079858cda0b917316ad9161b3881e0"></a><!-- doxytag: member="dwc_otg_cil.h::DWC_OTG_EP_TYPE_BULK" ref="9b079858cda0b917316ad9161b3881e0" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#9b079858cda0b917316ad9161b3881e0">DWC_OTG_EP_TYPE_BULK</a>&nbsp;&nbsp;&nbsp;2</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="1401d1264f88530232cf51ab31cc5347"></a><!-- doxytag: member="dwc_otg_cil.h::DWC_OTG_EP_TYPE_INTR" ref="1401d1264f88530232cf51ab31cc5347" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#1401d1264f88530232cf51ab31cc5347">DWC_OTG_EP_TYPE_INTR</a>&nbsp;&nbsp;&nbsp;3</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="1a25260b2e1a06850c26f7b7e5128f31"></a><!-- doxytag: member="dwc_otg_cil.h::DWC_OTG_EP_SPEED_LOW" ref="1a25260b2e1a06850c26f7b7e5128f31" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#1a25260b2e1a06850c26f7b7e5128f31">DWC_OTG_EP_SPEED_LOW</a>&nbsp;&nbsp;&nbsp;0</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="2ec9a7665a34074eedf1f40681d124ef"></a><!-- doxytag: member="dwc_otg_cil.h::DWC_OTG_EP_SPEED_FULL" ref="2ec9a7665a34074eedf1f40681d124ef" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#2ec9a7665a34074eedf1f40681d124ef">DWC_OTG_EP_SPEED_FULL</a>&nbsp;&nbsp;&nbsp;1</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b9dc03c6bc3c1113a935a73cf7021fbe"></a><!-- doxytag: member="dwc_otg_cil.h::DWC_OTG_EP_SPEED_HIGH" ref="b9dc03c6bc3c1113a935a73cf7021fbe" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#b9dc03c6bc3c1113a935a73cf7021fbe">DWC_OTG_EP_SPEED_HIGH</a>&nbsp;&nbsp;&nbsp;2</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="0e843d08e80c29e82962ce9170a02a52"></a><!-- doxytag: member="dwc_otg_cil.h::DWC_OTG_HC_PID_DATA0" ref="0e843d08e80c29e82962ce9170a02a52" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#0e843d08e80c29e82962ce9170a02a52">DWC_OTG_HC_PID_DATA0</a>&nbsp;&nbsp;&nbsp;0</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="5a78ac2f42a7e583d849903fa4570fb8"></a><!-- doxytag: member="dwc_otg_cil.h::DWC_OTG_HC_PID_DATA2" ref="5a78ac2f42a7e583d849903fa4570fb8" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#5a78ac2f42a7e583d849903fa4570fb8">DWC_OTG_HC_PID_DATA2</a>&nbsp;&nbsp;&nbsp;1</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e623eb446c55928b324e9636111315e1"></a><!-- doxytag: member="dwc_otg_cil.h::DWC_OTG_HC_PID_DATA1" ref="e623eb446c55928b324e9636111315e1" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#e623eb446c55928b324e9636111315e1">DWC_OTG_HC_PID_DATA1</a>&nbsp;&nbsp;&nbsp;2</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3cea7ef8aa1cfeb50060f07e08fa6aff"></a><!-- doxytag: member="dwc_otg_cil.h::DWC_OTG_HC_PID_MDATA" ref="3cea7ef8aa1cfeb50060f07e08fa6aff" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#3cea7ef8aa1cfeb50060f07e08fa6aff">DWC_OTG_HC_PID_MDATA</a>&nbsp;&nbsp;&nbsp;3</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="8d329f92a5ff6f9a72fc755b6b1a4e17"></a><!-- doxytag: member="dwc_otg_cil.h::DWC_OTG_HC_PID_SETUP" ref="8d329f92a5ff6f9a72fc755b6b1a4e17" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#8d329f92a5ff6f9a72fc755b6b1a4e17">DWC_OTG_HC_PID_SETUP</a>&nbsp;&nbsp;&nbsp;3</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="1e6c4a07594b33ba981e3664a2f3366c"></a><!-- doxytag: member="dwc_otg_cil.h::DWC_OTG_PCGCCTL_OFFSET" ref="1e6c4a07594b33ba981e3664a2f3366c" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#1e6c4a07594b33ba981e3664a2f3366c">DWC_OTG_PCGCCTL_OFFSET</a>&nbsp;&nbsp;&nbsp;0xE00</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="921e7968f6c39c1d7c8d3b4b95a4f4eb"></a><!-- doxytag: member="dwc_otg_cil.h::DWC_OTG_DATA_FIFO_OFFSET" ref="921e7968f6c39c1d7c8d3b4b95a4f4eb" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#921e7968f6c39c1d7c8d3b4b95a4f4eb">DWC_OTG_DATA_FIFO_OFFSET</a>&nbsp;&nbsp;&nbsp;0x1000</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b7aa34c1f7efae9b69e2891fea7b615f"></a><!-- doxytag: member="dwc_otg_cil.h::DWC_OTG_DATA_FIFO_SIZE" ref="b7aa34c1f7efae9b69e2891fea7b615f" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#b7aa34c1f7efae9b69e2891fea7b615f">DWC_OTG_DATA_FIFO_SIZE</a>&nbsp;&nbsp;&nbsp;0x1000</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="a0732b344b6571a4554968e4ee2214dd"></a><!-- doxytag: member="dwc_otg_cil.h::A_HOST" ref="a0732b344b6571a4554968e4ee2214dd" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#a0732b344b6571a4554968e4ee2214dd">A_HOST</a>&nbsp;&nbsp;&nbsp;(1)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">A-Device is a_host. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="da9f5eb506da71435e8976ceb38bc14d"></a><!-- doxytag: member="dwc_otg_cil.h::A_SUSPEND" ref="da9f5eb506da71435e8976ceb38bc14d" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#da9f5eb506da71435e8976ceb38bc14d">A_SUSPEND</a>&nbsp;&nbsp;&nbsp;(2)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">A-Device is a_suspend. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7528970c03451cfc85e86ab92bbaf554"></a><!-- doxytag: member="dwc_otg_cil.h::A_PERIPHERAL" ref="7528970c03451cfc85e86ab92bbaf554" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#7528970c03451cfc85e86ab92bbaf554">A_PERIPHERAL</a>&nbsp;&nbsp;&nbsp;(3)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">A-Device is a_peripherial. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="622c3b95c9a587f518a787c05c50ffb7"></a><!-- doxytag: member="dwc_otg_cil.h::B_PERIPHERAL" ref="622c3b95c9a587f518a787c05c50ffb7" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#622c3b95c9a587f518a787c05c50ffb7">B_PERIPHERAL</a>&nbsp;&nbsp;&nbsp;(4)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">B-Device is operating as a Peripheral. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="02d6d4d9a0fdcc4fc8c5cf8e6c8577aa"></a><!-- doxytag: member="dwc_otg_cil.h::B_HOST" ref="02d6d4d9a0fdcc4fc8c5cf8e6c8577aa" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#02d6d4d9a0fdcc4fc8c5cf8e6c8577aa">B_HOST</a>&nbsp;&nbsp;&nbsp;(5)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">B-Device is operating as a Host. <br></td></tr>
+<tr><td colspan="2"><br><h2>Typedefs</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ef7ad72528599bd12fe954ce1899576e"></a><!-- doxytag: member="dwc_otg_cil.h::iso_pkt_info_t" ref="ef7ad72528599bd12fe954ce1899576e" args="" -->
+typedef <a class="el" href="structiso__pkt__info.html">iso_pkt_info</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#ef7ad72528599bd12fe954ce1899576e">iso_pkt_info_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Information for each ISOC packet. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef <a class="el" href="structdwc__ep.html">dwc_ep</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#974bc77a560995de85c414ac44799443">dwc_ep_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">The <code><a class="el" href="structdwc__ep.html">dwc_ep</a></code> structure represents the state of a single endpoint when acting in device mode.  <a href="#974bc77a560995de85c414ac44799443"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="346dc8786819502ccd295958eaf89c00"></a><!-- doxytag: member="dwc_otg_cil.h::dwc_otg_halt_status_e" ref="346dc8786819502ccd295958eaf89c00" args="" -->
+typedef enum <a class="el" href="dwc__otg__cil_8h.html#5535f5641e4293d3ecca5c863863d60d">dwc_otg_halt_status</a>&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_otg_halt_status_e</b></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef <a class="el" href="structdwc__hc.html">dwc_hc</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#fc0170955f6bcf84c1b8d02ec94a5826">dwc_hc_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Host channel descriptor.  <a href="#fc0170955f6bcf84c1b8d02ec94a5826"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef <a class="el" href="structdwc__otg__core__params.html">dwc_otg_core_params</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#b277e9a981ab1d2769a32f6610a52f51">dwc_otg_core_params_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">The following parameters may be specified when starting the module.  <a href="#b277e9a981ab1d2769a32f6610a52f51"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="eb81bb79f5836aa8c6a647ca4d928887"></a><!-- doxytag: member="dwc_otg_cil.h::dwc_otg_lx_state_e" ref="eb81bb79f5836aa8c6a647ca4d928887" args="" -->
+typedef enum <a class="el" href="dwc__otg__cil_8h.html#8442e49b7c783099ac17bda4f8b3bc3c">dwc_otg_lx_state</a>&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_otg_lx_state_e</b></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef <a class="el" href="structdwc__otg__cil__callbacks.html">dwc_otg_cil_callbacks</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#b54889e4f4d9fd42235411c317645280">dwc_otg_cil_callbacks_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">DWC_otg CIL callback structure.  <a href="#b54889e4f4d9fd42235411c317645280"></a><br></td></tr>
+<tr><td colspan="2"><br><h2>Enumerations</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">enum &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#5535f5641e4293d3ecca5c863863d60d">dwc_otg_halt_status</a> { <br>
+&nbsp;&nbsp;<b>DWC_OTG_HC_XFER_NO_HALT_STATUS</b>, 
+<b>DWC_OTG_HC_XFER_COMPLETE</b>, 
+<b>DWC_OTG_HC_XFER_URB_COMPLETE</b>, 
+<b>DWC_OTG_HC_XFER_ACK</b>, 
+<br>
+&nbsp;&nbsp;<b>DWC_OTG_HC_XFER_NAK</b>, 
+<b>DWC_OTG_HC_XFER_NYET</b>, 
+<b>DWC_OTG_HC_XFER_STALL</b>, 
+<b>DWC_OTG_HC_XFER_XACT_ERR</b>, 
+<br>
+&nbsp;&nbsp;<b>DWC_OTG_HC_XFER_FRAME_OVERRUN</b>, 
+<b>DWC_OTG_HC_XFER_BABBLE_ERR</b>, 
+<b>DWC_OTG_HC_XFER_DATA_TOGGLE_ERR</b>, 
+<b>DWC_OTG_HC_XFER_AHB_ERR</b>, 
+<br>
+&nbsp;&nbsp;<b>DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE</b>, 
+<b>DWC_OTG_HC_XFER_URB_DEQUEUE</b>
+<br>
+ }</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">enum &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#8442e49b7c783099ac17bda4f8b3bc3c">dwc_otg_lx_state</a> { <a class="el" href="dwc__otg__cil_8h.html#8442e49b7c783099ac17bda4f8b3bc3c9743a36d9b0b8c66a11a0714fdd27fb5">DWC_OTG_L0</a>, 
+<a class="el" href="dwc__otg__cil_8h.html#8442e49b7c783099ac17bda4f8b3bc3cf5b112742a8103f3489107ad26c0ff58">DWC_OTG_L1</a>, 
+<a class="el" href="dwc__otg__cil_8h.html#8442e49b7c783099ac17bda4f8b3bc3cd1fadb6fa31de73e8176316a0e0ba905">DWC_OTG_L2</a>, 
+<a class="el" href="dwc__otg__cil_8h.html#8442e49b7c783099ac17bda4f8b3bc3c86715d528a59b114b95aaafa8f2142f6">DWC_OTG_L3</a>
+ }</td></tr>
+
+<tr><td colspan="2"><br><h2>Functions</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="9ef061e0e79210e6c2a2c2b9cc45bd45"></a><!-- doxytag: member="dwc_otg_cil.h::w_conn_id_status_change" ref="9ef061e0e79210e6c2a2c2b9cc45bd45" args="(void *p)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#9ef061e0e79210e6c2a2c2b9cc45bd45">w_conn_id_status_change</a> (void *p)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#07f0b189448c71e7ea4c7b121320fb89">w_wakeup_detected</a> (void *p)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#9389236ccea6cb2710628143ab771004">dwc_otg_core_host_init</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *_core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function initializes the DWC_otg controller registers for host mode.  <a href="#9389236ccea6cb2710628143ab771004"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#16b147d5ce40708fe305d65c869edad8">dwc_otg_core_dev_init</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *_core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function initializes the DWC_otg controller registers for device mode.  <a href="#16b147d5ce40708fe305d65c869edad8"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#0ffb9dfee005bc3da77eb52f96a87fc8">dwc_otg_cil_register_pcd_callbacks</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *_core_if, <a class="el" href="structdwc__otg__cil__callbacks.html">dwc_otg_cil_callbacks_t</a> *_cb, void *_p)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Register PCD callbacks.  <a href="#0ffb9dfee005bc3da77eb52f96a87fc8"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil_8h.html#b8a0bb1f2b02714a0186656c4e315ef6">dwc_otg_cil_register_hcd_callbacks</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *_core_if, <a class="el" href="structdwc__otg__cil__callbacks.html">dwc_otg_cil_callbacks_t</a> *_cb, void *_p)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Register HCD callbacks.  <a href="#b8a0bb1f2b02714a0186656c4e315ef6"></a><br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This file contains the interface to the Core Interface Layer. 
+<p>
+
+<p>
+Definition in file <a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a>.<hr><h2>Define Documentation</h2>
+<a class="anchor" name="071cb1f3f29f9a52775e9fff270b1c7c"></a><!-- doxytag: member="dwc_otg_cil.h::clear_hc_int" ref="071cb1f3f29f9a52775e9fff270b1c7c" args="(_hc_regs_, _intr_)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define clear_hc_int          </td>
+          <td>(</td>
+          <td class="paramtype">_hc_regs_,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">_intr_&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keywordflow">do</span> { \
+        <a class="code" href="unionhcint__data.html">hcint_data_t</a> hcint_clear = {.d32 = 0}; \
+        hcint_clear.<a class="code" href="unionhcint__data.html#3ab6af507f45d91a7898dd711f4368ee">b</a>._intr_ = 1; \
+        dwc_write_reg32(&amp;(_hc_regs_)-&gt;hcint, hcint_clear.<a class="code" href="unionhcint__data.html#05a82fa7693f875622db744716d7f73e">d32</a>); \
+} <span class="keywordflow">while</span> (0)
+</pre></div>
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8h-source.html#l00903">903</a> of file <a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="e530fa4a6ed31f67cad65969355651ef"></a><!-- doxytag: member="dwc_otg_cil.h::disable_hc_int" ref="e530fa4a6ed31f67cad65969355651ef" args="(_hc_regs_, _intr_)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define disable_hc_int          </td>
+          <td>(</td>
+          <td class="paramtype">_hc_regs_,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">_intr_&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keywordflow">do</span> { \
+        <a class="code" href="unionhcintmsk__data.html">hcintmsk_data_t</a> hcintmsk = {.d32 = 0}; \
+        hcintmsk.<a class="code" href="unionhcintmsk__data.html#6835f55069c94947b580c8f01f64a075">b</a>._intr_ = 1; \
+        dwc_modify_reg32(&amp;(_hc_regs_)-&gt;hcintmsk, hcintmsk.<a class="code" href="unionhcintmsk__data.html#8868299fcc762e005b7f0bf67e5fbe30">d32</a>, 0); \
+} <span class="keywordflow">while</span> (0)
+</pre></div>
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8h-source.html#l00917">917</a> of file <a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a>.
+</div>
+</div><p>
+<hr><h2>Typedef Documentation</h2>
+<a class="anchor" name="974bc77a560995de85c414ac44799443"></a><!-- doxytag: member="dwc_otg_cil.h::dwc_ep_t" ref="974bc77a560995de85c414ac44799443" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef struct <a class="el" href="structdwc__ep.html">dwc_ep</a>  <a class="el" href="structdwc__ep.html">dwc_ep_t</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+The <code><a class="el" href="structdwc__ep.html">dwc_ep</a></code> structure represents the state of a single endpoint when acting in device mode. 
+<p>
+It contains the data items needed for an endpoint to be activated and transfer packets. 
+</div>
+</div><p>
+<a class="anchor" name="fc0170955f6bcf84c1b8d02ec94a5826"></a><!-- doxytag: member="dwc_otg_cil.h::dwc_hc_t" ref="fc0170955f6bcf84c1b8d02ec94a5826" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef struct <a class="el" href="structdwc__hc.html">dwc_hc</a>  <a class="el" href="structdwc__hc.html">dwc_hc_t</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Host channel descriptor. 
+<p>
+This structure represents the state of a single host channel when acting in host mode. It contains the data items needed to transfer packets to an endpoint via a host channel. 
+</div>
+</div><p>
+<a class="anchor" name="b277e9a981ab1d2769a32f6610a52f51"></a><!-- doxytag: member="dwc_otg_cil.h::dwc_otg_core_params_t" ref="b277e9a981ab1d2769a32f6610a52f51" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef struct <a class="el" href="structdwc__otg__core__params.html">dwc_otg_core_params</a>  <a class="el" href="structdwc__otg__core__params.html">dwc_otg_core_params_t</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+The following parameters may be specified when starting the module. 
+<p>
+These parameters define how the DWC_otg controller should be configured. 
+</div>
+</div><p>
+<a class="anchor" name="b54889e4f4d9fd42235411c317645280"></a><!-- doxytag: member="dwc_otg_cil.h::dwc_otg_cil_callbacks_t" ref="b54889e4f4d9fd42235411c317645280" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef struct <a class="el" href="structdwc__otg__cil__callbacks.html">dwc_otg_cil_callbacks</a>  <a class="el" href="structdwc__otg__cil__callbacks.html">dwc_otg_cil_callbacks_t</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+DWC_otg CIL callback structure. 
+<p>
+This structure allows the HCD and PCD to register functions used for starting and stopping the PCD and HCD for role change on for a DRD. 
+</div>
+</div><p>
+<hr><h2>Enumeration Type Documentation</h2>
+<a class="anchor" name="8442e49b7c783099ac17bda4f8b3bc3c"></a><!-- doxytag: member="dwc_otg_cil.h::dwc_otg_lx_state" ref="8442e49b7c783099ac17bda4f8b3bc3c" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">enum <a class="el" href="dwc__otg__cil_8h.html#8442e49b7c783099ac17bda4f8b3bc3c">dwc_otg_lx_state</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<dl compact><dt><b>Enumerator: </b></dt><dd>
+<table border="0" cellspacing="2" cellpadding="0">
+<tr><td valign="top"><em><a class="anchor" name="8442e49b7c783099ac17bda4f8b3bc3c9743a36d9b0b8c66a11a0714fdd27fb5"></a><!-- doxytag: member="DWC_OTG_L0" ref="8442e49b7c783099ac17bda4f8b3bc3c9743a36d9b0b8c66a11a0714fdd27fb5" args="" -->DWC_OTG_L0</em>&nbsp;</td><td>
+On state. </td></tr>
+<tr><td valign="top"><em><a class="anchor" name="8442e49b7c783099ac17bda4f8b3bc3cf5b112742a8103f3489107ad26c0ff58"></a><!-- doxytag: member="DWC_OTG_L1" ref="8442e49b7c783099ac17bda4f8b3bc3cf5b112742a8103f3489107ad26c0ff58" args="" -->DWC_OTG_L1</em>&nbsp;</td><td>
+LPM sleep state. </td></tr>
+<tr><td valign="top"><em><a class="anchor" name="8442e49b7c783099ac17bda4f8b3bc3cd1fadb6fa31de73e8176316a0e0ba905"></a><!-- doxytag: member="DWC_OTG_L2" ref="8442e49b7c783099ac17bda4f8b3bc3cd1fadb6fa31de73e8176316a0e0ba905" args="" -->DWC_OTG_L2</em>&nbsp;</td><td>
+USB suspend state. </td></tr>
+<tr><td valign="top"><em><a class="anchor" name="8442e49b7c783099ac17bda4f8b3bc3c86715d528a59b114b95aaafa8f2142f6"></a><!-- doxytag: member="DWC_OTG_L3" ref="8442e49b7c783099ac17bda4f8b3bc3c86715d528a59b114b95aaafa8f2142f6" args="" -->DWC_OTG_L3</em>&nbsp;</td><td>
+Off state. </td></tr>
+</table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8h-source.html#l00664">664</a> of file <a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a>.
+</div>
+</div><p>
+<hr><h2>Function Documentation</h2>
+<a class="anchor" name="07f0b189448c71e7ea4c7b121320fb89"></a><!-- doxytag: member="dwc_otg_cil.h::w_wakeup_detected" ref="07f0b189448c71e7ea4c7b121320fb89" args="(void *p)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void w_wakeup_detected           </td>
+          <td>(</td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>p</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil__intr_8c-source.html#l00473">473</a> of file <a class="el" href="dwc__otg__cil__intr_8c-source.html">dwc_otg_cil_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="9389236ccea6cb2710628143ab771004"></a><!-- doxytag: member="dwc_otg_cil.h::dwc_otg_core_host_init" ref="9389236ccea6cb2710628143ab771004" args="(dwc_otg_core_if_t *_core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_core_host_init           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function initializes the DWC_otg controller registers for host mode. 
+<p>
+This function flushes the Tx and Rx FIFOs and it flushes any entries in the request queues. Host channels are reset to ensure that they are ready for performing transfers.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l01196">1196</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="16b147d5ce40708fe305d65c869edad8"></a><!-- doxytag: member="dwc_otg_cil.h::dwc_otg_core_dev_init" ref="16b147d5ce40708fe305d65c869edad8" args="(dwc_otg_core_if_t *_core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_core_dev_init           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function initializes the DWC_otg controller registers for device mode. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller </td></tr>
+  </table>
+</dl>
+
+<p>
+Set Periodic Tx FIFO Mask all bits 0<p>
+Set Tx FIFO Mask all bits 0<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000006">Todo:</a></b></dt><dd>NGS: Fix Periodic FIFO Sizing! </dd></dl>
+<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000006">Todo:</a></b></dt><dd>Finish debug of this </dd></dl>
+<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000006">Todo:</a></b></dt><dd><ul>
+<li>if the condition needed to be checked or in any case all pending interrutps should be cleared? </li></ul>
+</dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l00843">843</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="674adeecada7af04f0d43aa819469b71"></a><!-- doxytag: member="dwc_otg_cil.h::dwc_otg_read_setup_packet" ref="674adeecada7af04f0d43aa819469b71" args="(dwc_otg_core_if_t *_core_if, uint32_t *_dest)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_read_setup_packet           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint32_t *&nbsp;</td>
+          <td class="paramname"> <em>dest</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function reads a setup packet from the Rx FIFO into the destination buffer. 
+<p>
+This function is called from the Rx Status Queue Level (RxStsQLvl) Interrupt routine when a SETUP packet has been received in Slave mode.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>dest</em>&nbsp;</td><td>Destination buffer for packet data. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l02199">2199</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="9e8d3f050dc72eeaad2541bfd9796879"></a><!-- doxytag: member="dwc_otg_cil.h::dwc_otg_get_frame_number" ref="9e8d3f050dc72eeaad2541bfd9796879" args="(dwc_otg_core_if_t *_core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t dwc_otg_get_frame_number           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Gets the current USB frame number. 
+<p>
+This is the frame number from the last SOF packet. 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l02182">2182</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="382592a5e686a82ece47d7634800aae3"></a><!-- doxytag: member="dwc_otg_cil.h::dwc_otg_ep0_activate" ref="382592a5e686a82ece47d7634800aae3" args="(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_ep0_activate           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__ep.html">dwc_ep_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>ep</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function enables EP0 OUT to receive SETUP packets and configures EP0 IN for transmitting packets. 
+<p>
+It is normally called when the "Enumeration Done" interrupt occurs.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep</em>&nbsp;</td><td>The EP0 data. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l02216">2216</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="ceb07d2056baad0974dedf55cf9cab80"></a><!-- doxytag: member="dwc_otg_cil.h::dwc_otg_ep_activate" ref="ceb07d2056baad0974dedf55cf9cab80" args="(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_ep_activate           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__ep.html">dwc_ep_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>ep</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function activates an EP. 
+<p>
+The Device EP control register for the EP is configured as defined in the ep structure. Note: This function is not used for EP0.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep</em>&nbsp;</td><td>The EP to activate. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l02268">2268</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="e813a4a71aab8a37f63790d3450367ec"></a><!-- doxytag: member="dwc_otg_cil.h::dwc_otg_ep_deactivate" ref="e813a4a71aab8a37f63790d3450367ec" args="(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_ep_deactivate           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__ep.html">dwc_ep_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>ep</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function deactivates an EP. 
+<p>
+This is done by clearing the USB Active EP bit in the Device EP control register. Note: This function is not used for EP0. EP0 cannot be deactivated.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep</em>&nbsp;</td><td>The EP to deactivate. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l02367">2367</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="aa731bad72017df1111f0f31bcbc7f33"></a><!-- doxytag: member="dwc_otg_cil.h::dwc_otg_ep_start_transfer" ref="aa731bad72017df1111f0f31bcbc7f33" args="(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_ep_start_transfer           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__ep.html">dwc_ep_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>ep</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function does the setup for a data transfer for an EP and starts the transfer. 
+<p>
+For an IN transfer, the packets will be loaded into the appropriate Tx FIFO in the ISR. For OUT transfers, the packets are unloaded from the Rx FIFO in the ISR. the ISR.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep</em>&nbsp;</td><td>The EP to start the transfer on. </td></tr>
+  </table>
+</dl>
+
+<p>
+DIEPDMAn Register write<p>
+Enable the Non-Periodic Tx FIFO empty interrupt, or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode, the data will be written into the fifo by the ISR.<p>
+DOEPDMAn Register write 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l02475">2475</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="fc1d9180b7d4e894214afddde1f4397e"></a><!-- doxytag: member="dwc_otg_cil.h::dwc_otg_ep_start_zl_transfer" ref="fc1d9180b7d4e894214afddde1f4397e" args="(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_ep_start_zl_transfer           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__ep.html">dwc_ep_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>ep</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function setup a zero length transfer in Buffer DMA and Slave modes for usb requests with zero field set. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep</em>&nbsp;</td><td>The EP to start the transfer on. </td></tr>
+  </table>
+</dl>
+
+<p>
+Enable the Non-Periodic Tx FIFO empty interrupt, or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode, the data will be written into the fifo by the ISR. 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l02678">2678</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="d4a111ecd96bec3afd3b7c0421af9652"></a><!-- doxytag: member="dwc_otg_cil.h::dwc_otg_ep0_start_transfer" ref="d4a111ecd96bec3afd3b7c0421af9652" args="(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_ep0_start_transfer           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__ep.html">dwc_ep_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>ep</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function does the setup for a data transfer for EP0 and starts the transfer. 
+<p>
+For an IN transfer, the packets will be loaded into the appropriate Tx FIFO in the ISR. For OUT transfers, the packets are unloaded from the Rx FIFO in the ISR.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep</em>&nbsp;</td><td>The EP0 data. </td></tr>
+  </table>
+</dl>
+
+<p>
+DMA Descriptor Setup<p>
+DIEPDMA0 Register write<p>
+Enable the Non-Periodic Tx FIFO empty interrupt, the data will be written into the fifo by the ISR.<p>
+DMA Descriptor Setup<p>
+DOEPDMA0 Register write 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l02785">2785</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="e52e9ca5ecba4797f51be5e30f1c6fbc"></a><!-- doxytag: member="dwc_otg_cil.h::dwc_otg_ep0_continue_transfer" ref="e52e9ca5ecba4797f51be5e30f1c6fbc" args="(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_ep0_continue_transfer           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__ep.html">dwc_ep_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>ep</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function continues control IN transfers started by dwc_otg_ep0_start_transfer, when the transfer does not fit in a single packet. 
+<p>
+NOTE: The DIEPCTL0/DOEPCTL0 registers only have one bit for the packet count.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep</em>&nbsp;</td><td>The EP0 data. </td></tr>
+  </table>
+</dl>
+
+<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000009">Todo:</a></b></dt><dd>Should there be check for room in the Tx Status Queue. If not remove the code above this comment. </dd></dl>
+<p>
+DMA Descriptor Setup<p>
+DIEPDMA0 Register write<p>
+Enable the Non-Periodic Tx FIFO empty interrupt, the data will be written into the fifo by the ISR.<p>
+DMA Descriptor Setup<p>
+DOEPDMA0 Register write 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l02969">2969</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="42cba51a650375f6a18f4136cb4dba92"></a><!-- doxytag: member="dwc_otg_cil.h::dwc_otg_ep_write_packet" ref="42cba51a650375f6a18f4136cb4dba92" args="(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep, int _dma)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_ep_write_packet           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__ep.html">dwc_ep_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>ep</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>dma</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function writes a packet into the Tx FIFO associated with the EP. 
+<p>
+For non-periodic EPs the non-periodic Tx FIFO is written. For periodic EPs the periodic Tx FIFO associated with the EP is written with all packets for the next micro-frame.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep</em>&nbsp;</td><td>The EP to write packet for. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>dma</em>&nbsp;</td><td>Indicates if DMA is being used. </td></tr>
+  </table>
+</dl>
+
+<p>
+The buffer is padded to DWORD on a per packet basis in slave/dma mode if the MPS is not DWORD aligned. The last packet, if short, is also padded to a multiple of DWORD.<p>
+ep-&gt;xfer_buff always starts DWORD aligned in memory and is a multiple of DWORD in length<p>
+ep-&gt;xfer_len can be any number of bytes<p>
+ep-&gt;xfer_count is a multiple of ep-&gt;maxpacket until the last packet<p>
+FIFO access is DWORD<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000010">Todo:</a></b></dt><dd>NGS Where are the Periodic Tx FIFO addresses intialized? What should this be? </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l03165">3165</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="e1490c2dd3586403cf3fe12c716b41b2"></a><!-- doxytag: member="dwc_otg_cil.h::dwc_otg_ep_set_stall" ref="e1490c2dd3586403cf3fe12c716b41b2" args="(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_ep_set_stall           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__ep.html">dwc_ep_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>ep</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Set the EP STALL. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep</em>&nbsp;</td><td>The EP to set the stall on. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l03236">3236</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="45d65850c250067079f80c3ba87ef077"></a><!-- doxytag: member="dwc_otg_cil.h::dwc_otg_ep_clear_stall" ref="45d65850c250067079f80c3ba87ef077" args="(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_ep_clear_stall           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__ep.html">dwc_ep_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>ep</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Clear the EP STALL. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep</em>&nbsp;</td><td>The EP to clear stall from. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l03274">3274</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="ea31a3abac0bdb1ede29a9d65c402553"></a><!-- doxytag: member="dwc_otg_cil.h::dwc_otg_enable_device_interrupts" ref="ea31a3abac0bdb1ede29a9d65c402553" args="(dwc_otg_core_if_t *_core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_enable_device_interrupts           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function enables the Device mode interrupts. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller </td></tr>
+  </table>
+</dl>
+
+<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000005">Todo:</a></b></dt><dd>NGS: Should this be a module parameter? </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l00772">772</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="0f0894ae9890260e1da839aa10af35cc"></a><!-- doxytag: member="dwc_otg_cil.h::dwc_otg_iso_ep_start_frm_transfer" ref="0f0894ae9890260e1da839aa10af35cc" args="(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_iso_ep_start_frm_transfer           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__ep.html">dwc_ep_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>ep</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function initializes a descriptor chain for Isochronous transfer. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep</em>&nbsp;</td><td>The EP to start the transfer on. </td></tr>
+  </table>
+</dl>
+
+<p>
+Enable endpoint, clear nak 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l03864">3864</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="0b13a31a7ddc82b53862cd06cfed6393"></a><!-- doxytag: member="dwc_otg_cil.h::dwc_otg_iso_ep_start_buf_transfer" ref="0b13a31a7ddc82b53862cd06cfed6393" args="(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_iso_ep_start_buf_transfer           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__ep.html">dwc_ep_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>ep</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function initializes a descriptor chain for Isochronous transfer. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep</em>&nbsp;</td><td>The EP to start the transfer on. </td></tr>
+  </table>
+</dl>
+
+<p>
+Enable endpoint, clear nak 
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd_8c-source.html#l00517">517</a> of file <a class="el" href="dwc__otg__pcd_8c-source.html">dwc_otg_pcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="f2f5f8703a3292608f1cb756d0d5c4ea"></a><!-- doxytag: member="dwc_otg_cil.h::dwc_otg_hc_init" ref="f2f5f8703a3292608f1cb756d0d5c4ea" args="(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_hc_init           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__hc.html">dwc_hc_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Prepares a host channel for transferring packets to/from a specific endpoint. 
+<p>
+The HCCHARn register is set up with the characteristics specified in _hc. Host channel interrupts that may need to be serviced while this transfer is in progress are enabled.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>hc</em>&nbsp;</td><td>Information needed to initialize the host channel </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l01352">1352</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="ec2bad3cbf8baa9b4932d84719e952e1"></a><!-- doxytag: member="dwc_otg_cil.h::dwc_otg_hc_halt" ref="ec2bad3cbf8baa9b4932d84719e952e1" args="(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc, dwc_otg_halt_status_e _halt_status)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_hc_halt           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__hc.html">dwc_hc_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">dwc_otg_halt_status_e&nbsp;</td>
+          <td class="paramname"> <em>halt_status</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Attempts to halt a host channel. 
+<p>
+This function should only be called in Slave mode or to abort a transfer in either Slave mode or DMA mode. Under normal circumstances in DMA mode, the controller halts the channel when the transfer is complete or a condition occurs that requires application intervention.<p>
+In slave mode, checks for a free request queue entry, then sets the Channel Enable and Channel Disable bits of the Host Channel Characteristics register of the specified channel to intiate the halt. If there is no free request queue entry, sets only the Channel Disable bit of the HCCHARn register to flush requests for this channel. In the latter case, sets a flag to indicate that the host channel needs to be halted when a request queue slot is open.<p>
+In DMA mode, always sets the Channel Enable and Channel Disable bits of the HCCHARn register. The controller ensures there is space in the request queue before submitting the halt request.<p>
+Some time may elapse before the core flushes any posted requests for this host channel and halts. The Channel Halted interrupt handler completes the deactivation of the host channel.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Controller register interface. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>hc</em>&nbsp;</td><td>Host channel to halt. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>halt_status</em>&nbsp;</td><td>Reason for halting the channel. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l01540">1540</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="99d4028c98b445a925ea5068b399d319"></a><!-- doxytag: member="dwc_otg_cil.h::dwc_otg_hc_cleanup" ref="99d4028c98b445a925ea5068b399d319" args="(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_hc_cleanup           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__hc.html">dwc_hc_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Clears the transfer state for a host channel. 
+<p>
+This function is normally called after a transfer is done and the host channel is being released.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>hc</em>&nbsp;</td><td>Identifies the host channel to clean up. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l01667">1667</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="0e66d54f3126186b0548743eb4641ad6"></a><!-- doxytag: member="dwc_otg_cil.h::dwc_otg_hc_start_transfer" ref="0e66d54f3126186b0548743eb4641ad6" args="(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_hc_start_transfer           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__hc.html">dwc_hc_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function does the setup for a data transfer for a host channel and starts the transfer. 
+<p>
+May be called in either Slave mode or DMA mode. In Slave mode, the caller must ensure that there is sufficient space in the request queue and Tx Data FIFO.<p>
+For an OUT transfer in Slave mode, it loads a data packet into the appropriate FIFO. If necessary, additional data packets will be loaded in the Host ISR.<p>
+For an IN transfer in Slave mode, a data packet is requested. The data packets are unloaded from the Rx FIFO in the Host ISR. If necessary, additional data packets are requested in the Host ISR.<p>
+For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ register along with a packet count of 1 and the channel is enabled. This causes a single PING transaction to occur. Other fields in HCTSIZ are simply set to 0 since no data transfer occurs in this case.<p>
+For a PING transfer in DMA mode, the HCTSIZ register is initialized with all the information required to perform the subsequent data transfer. In addition, the Do Ping bit is set in the HCTSIZ register. In this case, the controller performs the entire PING protocol, then starts the data transfer.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>hc</em>&nbsp;</td><td>Information needed to initialize the host channel. The xfer_len value may be reduced to accommodate the max widths of the XferSize and PktCnt fields in the HCTSIZn register. The multi_count value may be changed to reflect the final xfer_len value. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l01800">1800</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="1677ed41bf5cf0c64cdcec47265a4052"></a><!-- doxytag: member="dwc_otg_cil.h::dwc_otg_hc_continue_transfer" ref="1677ed41bf5cf0c64cdcec47265a4052" args="(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_hc_continue_transfer           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__hc.html">dwc_hc_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function continues a data transfer that was started by previous call to <code>dwc_otg_hc_start_transfer</code>. 
+<p>
+The caller must ensure there is sufficient space in the request queue and Tx Data FIFO. This function should only be called in Slave mode. In DMA mode, the controller acts autonomously to complete transfers programmed to a host channel.<p>
+For an OUT transfer, a new data packet is loaded into the appropriate FIFO if there is any data remaining to be queued. For an IN transfer, another data packet is always requested. For the SETUP phase of a control transfer, this function does nothing.<p>
+<dl compact><dt><b>Returns:</b></dt><dd>1 if a new request is queued, 0 if no more requests are required for this transfer. </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l02048">2048</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="ca1e0ad294962a68562280543947446e"></a><!-- doxytag: member="dwc_otg_cil.h::dwc_otg_hc_do_ping" ref="ca1e0ad294962a68562280543947446e" args="(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_hc_do_ping           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__hc.html">dwc_hc_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Starts a PING transfer. 
+<p>
+This function should only be called in Slave mode. The Do Ping bit is set in the HCTSIZ register, then the channel is enabled. 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l02110">2110</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="99a7497537db075b95c72816e766acf8"></a><!-- doxytag: member="dwc_otg_cil.h::dwc_otg_enable_host_interrupts" ref="99a7497537db075b95c72816e766acf8" args="(dwc_otg_core_if_t *_core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_enable_host_interrupts           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function enables the Host mode interrupts. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l01130">1130</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="6f3cf40d961167bf8c5888bcf577c15b"></a><!-- doxytag: member="dwc_otg_cil.h::dwc_otg_disable_host_interrupts" ref="6f3cf40d961167bf8c5888bcf577c15b" args="(dwc_otg_core_if_t *_core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_disable_host_interrupts           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function disables the Host Mode interrupts. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l01165">1165</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="dbc20e9f9cadbdf4df65db3f82bbb820"></a><!-- doxytag: member="dwc_otg_cil.h::dwc_otg_hc_start_transfer_ddma" ref="dbc20e9f9cadbdf4df65db3f82bbb820" args="(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_hc_start_transfer_ddma           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__hc.html">dwc_hc_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function does the setup for a data transfer for a host channel and starts the transfer in Descriptor DMA mode. 
+<p>
+Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set. Sets PID and NTD values. For periodic transfers initializes SCHED_INFO field with micro-frame bitmap.<p>
+Initializes HCDMA register with descriptor list address and CTD value then starts the transfer via enabling the channel.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>hc</em>&nbsp;</td><td>Information needed to initialize the host channel. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l01968">1968</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="ce67da6af4023cffd25333d20992438e"></a><!-- doxytag: member="dwc_otg_cil.h::dwc_otg_read_hprt0" ref="ce67da6af4023cffd25333d20992438e" args="(dwc_otg_core_if_t *_core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static uint32_t dwc_otg_read_hprt0           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>_core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [inline, static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function Reads HPRT0 in preparation to modify. 
+<p>
+It keeps the WC bits 0 so that if they are read as 1, they won't clear when you write it back 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8h-source.html#l00929">929</a> of file <a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="68f59dd23ccfffa9aa1dc590e99b7668"></a><!-- doxytag: member="dwc_otg_cil.h::dwc_otg_read_packet" ref="68f59dd23ccfffa9aa1dc590e99b7668" args="(dwc_otg_core_if_t *core_if, uint8_t *dest, uint16_t bytes)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_read_packet           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>dest</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint16_t&nbsp;</td>
+          <td class="paramname"> <em>bytes</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function reads a packet from the Rx FIFO into the destination buffer. 
+<p>
+To read SETUP data use dwc_otg_read_setup_packet.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>dest</em>&nbsp;</td><td>Destination buffer for the packet. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>bytes</em>&nbsp;</td><td>Number of bytes to copy to the destination. </td></tr>
+  </table>
+</dl>
+
+<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000011">Todo:</a></b></dt><dd>Account for the case where _dest is not dword aligned. This requires reading data from the FIFO into a uint32_t temp buffer, then moving it into the data buffer. </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l03317">3317</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="f92d866287dce46d9e150c48901086bf"></a><!-- doxytag: member="dwc_otg_cil.h::dwc_otg_flush_tx_fifo" ref="f92d866287dce46d9e150c48901086bf" args="(dwc_otg_core_if_t *_core_if, const int _num)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_flush_tx_fifo           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">const int&nbsp;</td>
+          <td class="paramname"> <em>num</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Flush a Tx FIFO. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>num</em>&nbsp;</td><td>Tx FIFO to flush. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l03662">3662</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="07661371177fec53ba6d020320f2bae8"></a><!-- doxytag: member="dwc_otg_cil.h::dwc_otg_flush_rx_fifo" ref="07661371177fec53ba6d020320f2bae8" args="(dwc_otg_core_if_t *_core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_flush_rx_fifo           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Flush Rx FIFO. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l03694">3694</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="c8466c3cd6229625268ec423c4b44aa4"></a><!-- doxytag: member="dwc_otg_cil.h::dwc_otg_core_reset" ref="c8466c3cd6229625268ec423c4b44aa4" args="(dwc_otg_core_if_t *_core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_core_reset           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Do core a soft reset of the core. 
+<p>
+Be careful with this because it resets all the internal state machines of the core. 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l03725">3725</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="de0ac73b05fc306b04614f73b890a364"></a><!-- doxytag: member="dwc_otg_cil.h::dwc_otg_mode" ref="de0ac73b05fc306b04614f73b890a364" args="(dwc_otg_core_if_t *_core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static uint32_t dwc_otg_mode           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>_core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [inline, static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function returns the mode of the operation, host or device. 
+<p>
+<dl compact><dt><b>Returns:</b></dt><dd>0 - Device Mode, 1 - Host Mode </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8h-source.html#l01097">1097</a> of file <a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="0ffb9dfee005bc3da77eb52f96a87fc8"></a><!-- doxytag: member="dwc_otg_cil.h::dwc_otg_cil_register_pcd_callbacks" ref="0ffb9dfee005bc3da77eb52f96a87fc8" args="(dwc_otg_core_if_t *_core_if, dwc_otg_cil_callbacks_t *_cb, void *_p)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_cil_register_pcd_callbacks           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__cil__callbacks.html">dwc_otg_cil_callbacks_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>cb</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>p</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Register PCD callbacks. 
+<p>
+The callbacks are used to start and stop the PCD for interrupt processing.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>cb</em>&nbsp;</td><td>the PCD callback structure. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>p</em>&nbsp;</td><td>pointer to be passed to callback function (pcd*). </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l03796">3796</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="b8a0bb1f2b02714a0186656c4e315ef6"></a><!-- doxytag: member="dwc_otg_cil.h::dwc_otg_cil_register_hcd_callbacks" ref="b8a0bb1f2b02714a0186656c4e315ef6" args="(dwc_otg_core_if_t *_core_if, dwc_otg_cil_callbacks_t *_cb, void *_p)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_cil_register_hcd_callbacks           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__cil__callbacks.html">dwc_otg_cil_callbacks_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>cb</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>p</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Register HCD callbacks. 
+<p>
+The callbacks are used to start and stop the HCD for interrupt processing.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>cb</em>&nbsp;</td><td>the HCD callback structure. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>p</em>&nbsp;</td><td>pointer to be passed to callback function (usb_hcd*). </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l03781">3781</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil__intr_8c-source.html b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil__intr_8c-source.html
new file mode 100644
index 000000000000..e4b698882176
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil__intr_8c-source.html
@@ -0,0 +1,742 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_cil_intr.c Source File</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<h1>dwc_otg_cil_intr.c</h1><a href="dwc__otg__cil__intr_8c.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">/* ==========================================================================</span>
+<a name="l00002"></a>00002 <span class="comment"> * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil_intr.c $</span>
+<a name="l00003"></a>00003 <span class="comment"> * $Revision: #15 $</span>
+<a name="l00004"></a>00004 <span class="comment"> * $Date: 2009/04/15 $</span>
+<a name="l00005"></a>00005 <span class="comment"> * $Change: 1234129 $</span>
+<a name="l00006"></a>00006 <span class="comment"> *</span>
+<a name="l00007"></a>00007 <span class="comment"> * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,</span>
+<a name="l00008"></a>00008 <span class="comment"> * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless</span>
+<a name="l00009"></a>00009 <span class="comment"> * otherwise expressly agreed to in writing between Synopsys and you.</span>
+<a name="l00010"></a>00010 <span class="comment"> *</span>
+<a name="l00011"></a>00011 <span class="comment"> * The Software IS NOT an item of Licensed Software or Licensed Product under</span>
+<a name="l00012"></a>00012 <span class="comment"> * any End User Software License Agreement or Agreement for Licensed Product</span>
+<a name="l00013"></a>00013 <span class="comment"> * with Synopsys or any supplement thereto. You are permitted to use and</span>
+<a name="l00014"></a>00014 <span class="comment"> * redistribute this Software in source and binary forms, with or without</span>
+<a name="l00015"></a>00015 <span class="comment"> * modification, provided that redistributions of source code must retain this</span>
+<a name="l00016"></a>00016 <span class="comment"> * notice. You may not view, use, disclose, copy or distribute this file or</span>
+<a name="l00017"></a>00017 <span class="comment"> * any information contained herein except pursuant to this license grant from</span>
+<a name="l00018"></a>00018 <span class="comment"> * Synopsys. If you do not agree with this notice, including the disclaimer</span>
+<a name="l00019"></a>00019 <span class="comment"> * below, then you are not authorized to use the Software.</span>
+<a name="l00020"></a>00020 <span class="comment"> *</span>
+<a name="l00021"></a>00021 <span class="comment"> * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS</span>
+<a name="l00022"></a>00022 <span class="comment"> * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE</span>
+<a name="l00023"></a>00023 <span class="comment"> * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE</span>
+<a name="l00024"></a>00024 <span class="comment"> * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,</span>
+<a name="l00025"></a>00025 <span class="comment"> * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES</span>
+<a name="l00026"></a>00026 <span class="comment"> * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR</span>
+<a name="l00027"></a>00027 <span class="comment"> * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER</span>
+<a name="l00028"></a>00028 <span class="comment"> * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT</span>
+<a name="l00029"></a>00029 <span class="comment"> * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY</span>
+<a name="l00030"></a>00030 <span class="comment"> * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH</span>
+<a name="l00031"></a>00031 <span class="comment"> * DAMAGE.</span>
+<a name="l00032"></a>00032 <span class="comment"> * ========================================================================== */</span>
+<a name="l00033"></a>00033 
+<a name="l00042"></a>00042 <span class="preprocessor">#include "dwc_os.h"</span>
+<a name="l00043"></a>00043 <span class="preprocessor">#include "<a class="code" href="dwc__otg__regs_8h.html">dwc_otg_regs.h</a>"</span>
+<a name="l00044"></a>00044 <span class="preprocessor">#include "<a class="code" href="dwc__otg__cil_8h.html">dwc_otg_cil.h</a>"</span>
+<a name="l00045"></a>00045 
+<a name="l00046"></a>00046 <span class="preprocessor">#ifdef DEBUG</span>
+<a name="l00047"></a>00047 <span class="preprocessor"></span><span class="keyword">inline</span> <span class="keyword">const</span> <span class="keywordtype">char</span> *op_state_str(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l00048"></a>00048 {
+<a name="l00049"></a>00049         <span class="keywordflow">return</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5a5c5c1cf8d870101cc1fffac56d88c0">op_state</a> == <a class="code" href="dwc__otg__cil_8h.html#a0732b344b6571a4554968e4ee2214dd">A_HOST</a> ? <span class="stringliteral">"a_host"</span> :
+<a name="l00050"></a>00050                 (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5a5c5c1cf8d870101cc1fffac56d88c0">op_state</a> == <a class="code" href="dwc__otg__cil_8h.html#da9f5eb506da71435e8976ceb38bc14d">A_SUSPEND</a> ? <span class="stringliteral">"a_suspend"</span> :
+<a name="l00051"></a>00051                  (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5a5c5c1cf8d870101cc1fffac56d88c0">op_state</a> == <a class="code" href="dwc__otg__cil_8h.html#7528970c03451cfc85e86ab92bbaf554">A_PERIPHERAL</a> ? <span class="stringliteral">"a_peripheral"</span> :
+<a name="l00052"></a>00052                   (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5a5c5c1cf8d870101cc1fffac56d88c0">op_state</a> == <a class="code" href="dwc__otg__cil_8h.html#622c3b95c9a587f518a787c05c50ffb7">B_PERIPHERAL</a> ? <span class="stringliteral">"b_peripheral"</span> :
+<a name="l00053"></a>00053                    (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5a5c5c1cf8d870101cc1fffac56d88c0">op_state</a> == <a class="code" href="dwc__otg__cil_8h.html#02d6d4d9a0fdcc4fc8c5cf8e6c8577aa">B_HOST</a> ? <span class="stringliteral">"b_host"</span> : <span class="stringliteral">"unknown"</span>)))));
+<a name="l00054"></a>00054 }
+<a name="l00055"></a>00055 <span class="preprocessor">#endif</span>
+<a name="l00056"></a>00056 <span class="preprocessor"></span>
+<a name="l00061"></a><a class="code" href="dwc__otg__cil__intr_8c.html#934ada5611b9fac2645fa286fbc12cf0">00061</a> int32_t <a class="code" href="dwc__otg__cil__intr_8c.html#934ada5611b9fac2645fa286fbc12cf0">dwc_otg_handle_mode_mismatch_intr</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l00062"></a>00062 {
+<a name="l00063"></a>00063         <a class="code" href="uniongintsts__data.html">gintsts_data_t</a> gintsts;
+<a name="l00064"></a>00064         DWC_WARN(<span class="stringliteral">"Mode Mismatch Interrupt: currently in %s mode\n"</span>,
+<a name="l00065"></a>00065                  <a class="code" href="dwc__otg__cil_8h.html#de0ac73b05fc306b04614f73b890a364">dwc_otg_mode</a>(core_if) ? <span class="stringliteral">"Host"</span> : <span class="stringliteral">"Device"</span>);
+<a name="l00066"></a>00066 
+<a name="l00067"></a>00067         <span class="comment">/* Clear interrupt */</span>
+<a name="l00068"></a>00068         gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a> = 0;
+<a name="l00069"></a>00069         gintsts.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#5fda463a80eb6927b2b875d64e8a0753">modemismatch</a> = 1;
+<a name="l00070"></a>00070         dwc_write_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>, gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a>);
+<a name="l00071"></a>00071         <span class="keywordflow">return</span> 1;
+<a name="l00072"></a>00072 }
+<a name="l00073"></a>00073 
+<a name="l00078"></a><a class="code" href="dwc__otg__cil__intr_8c.html#fc2d933cd662b3d060747004c79203a1">00078</a> <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil__intr_8c.html#fc2d933cd662b3d060747004c79203a1">hcd_start</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l00079"></a>00079 {
+<a name="l00080"></a>00080         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#9a8568a762af68c9b0d97e0278cc26ba">hcd_cb</a> &amp;&amp; core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#9a8568a762af68c9b0d97e0278cc26ba">hcd_cb</a>-&gt;<a class="code" href="structdwc__otg__cil__callbacks.html#ebb662b2e0b4d187648b7f91b9d00713">start</a>) {
+<a name="l00081"></a>00081                 core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#9a8568a762af68c9b0d97e0278cc26ba">hcd_cb</a>-&gt;<a class="code" href="structdwc__otg__cil__callbacks.html#ebb662b2e0b4d187648b7f91b9d00713">start</a>(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#9a8568a762af68c9b0d97e0278cc26ba">hcd_cb</a>-&gt;<a class="code" href="structdwc__otg__cil__callbacks.html#a486473d73fb104dc3a37e963a8ef8e5">p</a>);
+<a name="l00082"></a>00082         }
+<a name="l00083"></a>00083 }
+<a name="l00084"></a>00084 
+<a name="l00089"></a><a class="code" href="dwc__otg__cil__intr_8c.html#b2721d01cc389181470095955b4e0994">00089</a> <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil__intr_8c.html#b2721d01cc389181470095955b4e0994">hcd_stop</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l00090"></a>00090 {
+<a name="l00091"></a>00091         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#9a8568a762af68c9b0d97e0278cc26ba">hcd_cb</a> &amp;&amp; core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#9a8568a762af68c9b0d97e0278cc26ba">hcd_cb</a>-&gt;<a class="code" href="structdwc__otg__cil__callbacks.html#cd604365bc84ceda780e10c2344870e4">stop</a>) {
+<a name="l00092"></a>00092                 core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#9a8568a762af68c9b0d97e0278cc26ba">hcd_cb</a>-&gt;<a class="code" href="structdwc__otg__cil__callbacks.html#cd604365bc84ceda780e10c2344870e4">stop</a>(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#9a8568a762af68c9b0d97e0278cc26ba">hcd_cb</a>-&gt;<a class="code" href="structdwc__otg__cil__callbacks.html#a486473d73fb104dc3a37e963a8ef8e5">p</a>);
+<a name="l00093"></a>00093         }
+<a name="l00094"></a>00094 }
+<a name="l00095"></a>00095 
+<a name="l00100"></a><a class="code" href="dwc__otg__cil__intr_8c.html#b208bc4537e7b26658edc642e407894b">00100</a> <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil__intr_8c.html#b208bc4537e7b26658edc642e407894b">hcd_disconnect</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l00101"></a>00101 {
+<a name="l00102"></a>00102         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#9a8568a762af68c9b0d97e0278cc26ba">hcd_cb</a> &amp;&amp; core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#9a8568a762af68c9b0d97e0278cc26ba">hcd_cb</a>-&gt;<a class="code" href="structdwc__otg__cil__callbacks.html#1a8ccad34a04f3e8b085aa5720bbcc70">disconnect</a>) {
+<a name="l00103"></a>00103                 core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#9a8568a762af68c9b0d97e0278cc26ba">hcd_cb</a>-&gt;<a class="code" href="structdwc__otg__cil__callbacks.html#1a8ccad34a04f3e8b085aa5720bbcc70">disconnect</a>(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#9a8568a762af68c9b0d97e0278cc26ba">hcd_cb</a>-&gt;<a class="code" href="structdwc__otg__cil__callbacks.html#a486473d73fb104dc3a37e963a8ef8e5">p</a>);
+<a name="l00104"></a>00104         }
+<a name="l00105"></a>00105 }
+<a name="l00106"></a>00106 
+<a name="l00112"></a><a class="code" href="dwc__otg__cil__intr_8c.html#2ccec1f0c44ae8129f3012a519ecd5eb">00112</a> <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil__intr_8c.html#2ccec1f0c44ae8129f3012a519ecd5eb">hcd_session_start</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l00113"></a>00113 {
+<a name="l00114"></a>00114         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#9a8568a762af68c9b0d97e0278cc26ba">hcd_cb</a> &amp;&amp; core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#9a8568a762af68c9b0d97e0278cc26ba">hcd_cb</a>-&gt;<a class="code" href="structdwc__otg__cil__callbacks.html#d4235cc3ff7705538ccafa408950d759">session_start</a>) {
+<a name="l00115"></a>00115                 core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#9a8568a762af68c9b0d97e0278cc26ba">hcd_cb</a>-&gt;<a class="code" href="structdwc__otg__cil__callbacks.html#d4235cc3ff7705538ccafa408950d759">session_start</a>(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#9a8568a762af68c9b0d97e0278cc26ba">hcd_cb</a>-&gt;<a class="code" href="structdwc__otg__cil__callbacks.html#a486473d73fb104dc3a37e963a8ef8e5">p</a>);
+<a name="l00116"></a>00116         }
+<a name="l00117"></a>00117 }
+<a name="l00118"></a>00118 
+<a name="l00119"></a>00119 <span class="preprocessor">#ifdef CONFIG_USB_DWC_OTG_LPM</span>
+<a name="l00120"></a>00120 <span class="preprocessor"></span>
+<a name="l00126"></a>00126 <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">void</span> hcd_sleep(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l00127"></a>00127 {
+<a name="l00128"></a>00128         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#9a8568a762af68c9b0d97e0278cc26ba">hcd_cb</a> &amp;&amp; core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#9a8568a762af68c9b0d97e0278cc26ba">hcd_cb</a>-&gt;sleep) {
+<a name="l00129"></a>00129                 core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#9a8568a762af68c9b0d97e0278cc26ba">hcd_cb</a>-&gt;sleep(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#9a8568a762af68c9b0d97e0278cc26ba">hcd_cb</a>-&gt;<a class="code" href="structdwc__otg__cil__callbacks.html#a486473d73fb104dc3a37e963a8ef8e5">p</a>);
+<a name="l00130"></a>00130         }
+<a name="l00131"></a>00131 }
+<a name="l00132"></a>00132 <span class="preprocessor">#endif</span>
+<a name="l00133"></a>00133 <span class="preprocessor"></span>
+<a name="l00138"></a><a class="code" href="dwc__otg__cil__intr_8c.html#681e193a107c04b5005500ff35c59cd5">00138</a> <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil__intr_8c.html#681e193a107c04b5005500ff35c59cd5">hcd_resume</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l00139"></a>00139 {
+<a name="l00140"></a>00140         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#9a8568a762af68c9b0d97e0278cc26ba">hcd_cb</a> &amp;&amp; core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#9a8568a762af68c9b0d97e0278cc26ba">hcd_cb</a>-&gt;<a class="code" href="structdwc__otg__cil__callbacks.html#ad1895ddf4ad83622a514a725b4129d6">resume_wakeup</a>) {
+<a name="l00141"></a>00141                 core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#9a8568a762af68c9b0d97e0278cc26ba">hcd_cb</a>-&gt;<a class="code" href="structdwc__otg__cil__callbacks.html#ad1895ddf4ad83622a514a725b4129d6">resume_wakeup</a>(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#9a8568a762af68c9b0d97e0278cc26ba">hcd_cb</a>-&gt;<a class="code" href="structdwc__otg__cil__callbacks.html#a486473d73fb104dc3a37e963a8ef8e5">p</a>);
+<a name="l00142"></a>00142         }
+<a name="l00143"></a>00143 }
+<a name="l00144"></a>00144 
+<a name="l00149"></a><a class="code" href="dwc__otg__cil__intr_8c.html#a1de88a9a54457a0b828a8a2845a210c">00149</a> <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil__intr_8c.html#a1de88a9a54457a0b828a8a2845a210c">pcd_start</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l00150"></a>00150 {
+<a name="l00151"></a>00151         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#83bca1e02fafc4bbfa9c1f2eeb19b245">pcd_cb</a> &amp;&amp; core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#83bca1e02fafc4bbfa9c1f2eeb19b245">pcd_cb</a>-&gt;<a class="code" href="structdwc__otg__cil__callbacks.html#ebb662b2e0b4d187648b7f91b9d00713">start</a>) {
+<a name="l00152"></a>00152                 core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#83bca1e02fafc4bbfa9c1f2eeb19b245">pcd_cb</a>-&gt;<a class="code" href="structdwc__otg__cil__callbacks.html#ebb662b2e0b4d187648b7f91b9d00713">start</a>(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#83bca1e02fafc4bbfa9c1f2eeb19b245">pcd_cb</a>-&gt;<a class="code" href="structdwc__otg__cil__callbacks.html#a486473d73fb104dc3a37e963a8ef8e5">p</a>);
+<a name="l00153"></a>00153         }
+<a name="l00154"></a>00154 }
+<a name="l00155"></a>00155 
+<a name="l00160"></a><a class="code" href="dwc__otg__cil__intr_8c.html#d8eff82b37ea044fd7621faedcb36570">00160</a> <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil__intr_8c.html#d8eff82b37ea044fd7621faedcb36570">pcd_stop</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l00161"></a>00161 {
+<a name="l00162"></a>00162         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#83bca1e02fafc4bbfa9c1f2eeb19b245">pcd_cb</a> &amp;&amp; core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#83bca1e02fafc4bbfa9c1f2eeb19b245">pcd_cb</a>-&gt;<a class="code" href="structdwc__otg__cil__callbacks.html#cd604365bc84ceda780e10c2344870e4">stop</a>) {
+<a name="l00163"></a>00163                 core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#83bca1e02fafc4bbfa9c1f2eeb19b245">pcd_cb</a>-&gt;<a class="code" href="structdwc__otg__cil__callbacks.html#cd604365bc84ceda780e10c2344870e4">stop</a>(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#83bca1e02fafc4bbfa9c1f2eeb19b245">pcd_cb</a>-&gt;<a class="code" href="structdwc__otg__cil__callbacks.html#a486473d73fb104dc3a37e963a8ef8e5">p</a>);
+<a name="l00164"></a>00164         }
+<a name="l00165"></a>00165 }
+<a name="l00166"></a>00166 
+<a name="l00171"></a><a class="code" href="dwc__otg__cil__intr_8c.html#d9ac0577152f65fe83a76cbbca4ea795">00171</a> <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil__intr_8c.html#d9ac0577152f65fe83a76cbbca4ea795">pcd_suspend</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l00172"></a>00172 {
+<a name="l00173"></a>00173         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#83bca1e02fafc4bbfa9c1f2eeb19b245">pcd_cb</a> &amp;&amp; core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#83bca1e02fafc4bbfa9c1f2eeb19b245">pcd_cb</a>-&gt;<a class="code" href="structdwc__otg__cil__callbacks.html#a9e06ccc347fa446e2b131532e203d94">suspend</a>) {
+<a name="l00174"></a>00174                 core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#83bca1e02fafc4bbfa9c1f2eeb19b245">pcd_cb</a>-&gt;<a class="code" href="structdwc__otg__cil__callbacks.html#a9e06ccc347fa446e2b131532e203d94">suspend</a>(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#83bca1e02fafc4bbfa9c1f2eeb19b245">pcd_cb</a>-&gt;<a class="code" href="structdwc__otg__cil__callbacks.html#a486473d73fb104dc3a37e963a8ef8e5">p</a>);
+<a name="l00175"></a>00175         }
+<a name="l00176"></a>00176 }
+<a name="l00177"></a>00177 
+<a name="l00182"></a><a class="code" href="dwc__otg__cil__intr_8c.html#7d70de843b2e147969d32f7a9b2aa9e3">00182</a> <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil__intr_8c.html#7d70de843b2e147969d32f7a9b2aa9e3">pcd_resume</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l00183"></a>00183 {
+<a name="l00184"></a>00184         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#83bca1e02fafc4bbfa9c1f2eeb19b245">pcd_cb</a> &amp;&amp; core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#83bca1e02fafc4bbfa9c1f2eeb19b245">pcd_cb</a>-&gt;<a class="code" href="structdwc__otg__cil__callbacks.html#ad1895ddf4ad83622a514a725b4129d6">resume_wakeup</a>) {
+<a name="l00185"></a>00185                 core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#83bca1e02fafc4bbfa9c1f2eeb19b245">pcd_cb</a>-&gt;<a class="code" href="structdwc__otg__cil__callbacks.html#ad1895ddf4ad83622a514a725b4129d6">resume_wakeup</a>(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#83bca1e02fafc4bbfa9c1f2eeb19b245">pcd_cb</a>-&gt;<a class="code" href="structdwc__otg__cil__callbacks.html#a486473d73fb104dc3a37e963a8ef8e5">p</a>);
+<a name="l00186"></a>00186         }
+<a name="l00187"></a>00187 }
+<a name="l00188"></a>00188 
+<a name="l00196"></a><a class="code" href="dwc__otg__cil__intr_8c.html#420006ca946698a9eb123ad352df8870">00196</a> int32_t <a class="code" href="dwc__otg__cil__intr_8c.html#420006ca946698a9eb123ad352df8870">dwc_otg_handle_otg_intr</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l00197"></a>00197 {
+<a name="l00198"></a>00198         <a class="code" href="structdwc__otg__core__global__regs.html">dwc_otg_core_global_regs_t</a> *global_regs = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>;
+<a name="l00199"></a>00199         <a class="code" href="uniongotgint__data.html">gotgint_data_t</a> gotgint;
+<a name="l00200"></a>00200         <a class="code" href="uniongotgctl__data.html">gotgctl_data_t</a> gotgctl;
+<a name="l00201"></a>00201         <a class="code" href="uniongintmsk__data.html">gintmsk_data_t</a> gintmsk;
+<a name="l00202"></a>00202 
+<a name="l00203"></a>00203         gotgint.<a class="code" href="uniongotgint__data.html#8a343df4fc4e68b802be7629864308e2">d32</a> = dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#69cc290cfdfe6900890f7a5a16b3137c">gotgint</a>);
+<a name="l00204"></a>00204         gotgctl.<a class="code" href="uniongotgctl__data.html#ebb591ab40ff41f0e06f03a795647d33">d32</a> = dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#54034d00bb6b47ada4e0c0baa87cbd8a">gotgctl</a>);
+<a name="l00205"></a>00205         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">DBG_CIL</a>, <span class="stringliteral">"++OTG Interrupt gotgint=%0x [%s]\n"</span>, gotgint.<a class="code" href="uniongotgint__data.html#8a343df4fc4e68b802be7629864308e2">d32</a>,
+<a name="l00206"></a>00206                     op_state_str(core_if));
+<a name="l00207"></a>00207 
+<a name="l00208"></a>00208         <span class="keywordflow">if</span> (gotgint.<a class="code" href="uniongotgint__data.html#e48c5633608687c8895da201199c2a7c">b</a>.<a class="code" href="uniongotgint__data.html#58a04bef67e26229efe95f12938d18e8">sesenddet</a>) {
+<a name="l00209"></a>00209                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#2bf62a567355d1ea38814714bd7b57ec">DBG_ANY</a>, <span class="stringliteral">" ++OTG Interrupt: "</span>
+<a name="l00210"></a>00210                             <span class="stringliteral">"Session End Detected++ (%s)\n"</span>,
+<a name="l00211"></a>00211                             op_state_str(core_if));
+<a name="l00212"></a>00212                 gotgctl.<a class="code" href="uniongotgctl__data.html#ebb591ab40ff41f0e06f03a795647d33">d32</a> = dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#54034d00bb6b47ada4e0c0baa87cbd8a">gotgctl</a>);
+<a name="l00213"></a>00213 
+<a name="l00214"></a>00214                 <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5a5c5c1cf8d870101cc1fffac56d88c0">op_state</a> == <a class="code" href="dwc__otg__cil_8h.html#02d6d4d9a0fdcc4fc8c5cf8e6c8577aa">B_HOST</a>) {
+<a name="l00215"></a>00215                         <a class="code" href="dwc__otg__cil__intr_8c.html#a1de88a9a54457a0b828a8a2845a210c">pcd_start</a>(core_if);
+<a name="l00216"></a>00216                         core_if-&gt;op_state = <a class="code" href="dwc__otg__cil_8h.html#622c3b95c9a587f518a787c05c50ffb7">B_PERIPHERAL</a>;
+<a name="l00217"></a>00217                 } <span class="keywordflow">else</span> {
+<a name="l00218"></a>00218                         <span class="comment">/* If not B_HOST and Device HNP still set. HNP</span>
+<a name="l00219"></a>00219 <span class="comment">                         * Did not succeed!*/</span>
+<a name="l00220"></a>00220                         <span class="keywordflow">if</span> (gotgctl.<a class="code" href="uniongotgctl__data.html#212c81366266e906a188f4dbfadb6dd3">b</a>.<a class="code" href="uniongotgctl__data.html#0058cbee8b53336c28746116301ea796">devhnpen</a>) {
+<a name="l00221"></a>00221                                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#2bf62a567355d1ea38814714bd7b57ec">DBG_ANY</a>, <span class="stringliteral">"Session End Detected\n"</span>);
+<a name="l00222"></a>00222                                 __DWC_ERROR(<span class="stringliteral">"Device Not Connected/Responding!\n"</span>);
+<a name="l00223"></a>00223                         }
+<a name="l00224"></a>00224 
+<a name="l00225"></a>00225                         <span class="comment">/* If Session End Detected the B-Cable has</span>
+<a name="l00226"></a>00226 <span class="comment">                         * been disconnected. */</span>
+<a name="l00227"></a>00227                         <span class="comment">/* Reset PCD and Gadget driver to a</span>
+<a name="l00228"></a>00228 <span class="comment">                         * clean state. */</span>
+<a name="l00229"></a>00229                         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#2b0701d814069ec69897e08374366c7b">lx_state</a> = <a class="code" href="dwc__otg__cil_8h.html#8442e49b7c783099ac17bda4f8b3bc3c9743a36d9b0b8c66a11a0714fdd27fb5">DWC_OTG_L0</a>;
+<a name="l00230"></a>00230                         <a class="code" href="dwc__otg__cil__intr_8c.html#d8eff82b37ea044fd7621faedcb36570">pcd_stop</a>(core_if);
+<a name="l00231"></a>00231                 }
+<a name="l00232"></a>00232                 gotgctl.<a class="code" href="uniongotgctl__data.html#ebb591ab40ff41f0e06f03a795647d33">d32</a> = 0;
+<a name="l00233"></a>00233                 gotgctl.<a class="code" href="uniongotgctl__data.html#212c81366266e906a188f4dbfadb6dd3">b</a>.<a class="code" href="uniongotgctl__data.html#0058cbee8b53336c28746116301ea796">devhnpen</a> = 1;
+<a name="l00234"></a>00234                 dwc_modify_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#54034d00bb6b47ada4e0c0baa87cbd8a">gotgctl</a>, gotgctl.<a class="code" href="uniongotgctl__data.html#ebb591ab40ff41f0e06f03a795647d33">d32</a>, 0);
+<a name="l00235"></a>00235         }
+<a name="l00236"></a>00236         <span class="keywordflow">if</span> (gotgint.<a class="code" href="uniongotgint__data.html#e48c5633608687c8895da201199c2a7c">b</a>.<a class="code" href="uniongotgint__data.html#99a56305c7cc48086ef34c15bbc40ca6">sesreqsucstschng</a>) {
+<a name="l00237"></a>00237                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#2bf62a567355d1ea38814714bd7b57ec">DBG_ANY</a>, <span class="stringliteral">" ++OTG Interrupt: "</span>
+<a name="l00238"></a>00238                             <span class="stringliteral">"Session Reqeust Success Status Change++\n"</span>);
+<a name="l00239"></a>00239                 gotgctl.<a class="code" href="uniongotgctl__data.html#ebb591ab40ff41f0e06f03a795647d33">d32</a> = dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#54034d00bb6b47ada4e0c0baa87cbd8a">gotgctl</a>);
+<a name="l00240"></a>00240                 <span class="keywordflow">if</span> (gotgctl.<a class="code" href="uniongotgctl__data.html#212c81366266e906a188f4dbfadb6dd3">b</a>.<a class="code" href="uniongotgctl__data.html#5239dbbb4b31210a35a7104abb688801">sesreqscs</a>) {
+<a name="l00241"></a>00241                         <span class="keywordflow">if</span> ((core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#8b5d4e0c98c46d0d4e80b6faf66daf72">phy_type</a> ==
+<a name="l00242"></a>00242                              <a class="code" href="dwc__otg__core__if_8h.html#f7395410ea596c4c660f61ff41cb38b8">DWC_PHY_TYPE_PARAM_FS</a>) &amp;&amp; (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#6b0a0ab15284a541ae079beecaf3e617">i2c_enable</a>)) {
+<a name="l00243"></a>00243                                 core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#c2bb1913ed3fcc082a06d70242e9768a">srp_success</a> = 1;
+<a name="l00244"></a>00244                         } <span class="keywordflow">else</span> {
+<a name="l00245"></a>00245                                 <a class="code" href="dwc__otg__cil__intr_8c.html#7d70de843b2e147969d32f7a9b2aa9e3">pcd_resume</a>(core_if);
+<a name="l00246"></a>00246                                 <span class="comment">/* Clear Session Request */</span>
+<a name="l00247"></a>00247                                 gotgctl.<a class="code" href="uniongotgctl__data.html#ebb591ab40ff41f0e06f03a795647d33">d32</a> = 0;
+<a name="l00248"></a>00248                                 gotgctl.<a class="code" href="uniongotgctl__data.html#212c81366266e906a188f4dbfadb6dd3">b</a>.<a class="code" href="uniongotgctl__data.html#c6b0b35d4366f74cf6fe268eda781f06">sesreq</a> = 1;
+<a name="l00249"></a>00249                                 dwc_modify_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#54034d00bb6b47ada4e0c0baa87cbd8a">gotgctl</a>,
+<a name="l00250"></a>00250                                                  gotgctl.<a class="code" href="uniongotgctl__data.html#ebb591ab40ff41f0e06f03a795647d33">d32</a>, 0);
+<a name="l00251"></a>00251                         }
+<a name="l00252"></a>00252                 }
+<a name="l00253"></a>00253         }
+<a name="l00254"></a>00254         <span class="keywordflow">if</span> (gotgint.<a class="code" href="uniongotgint__data.html#e48c5633608687c8895da201199c2a7c">b</a>.<a class="code" href="uniongotgint__data.html#e41c62fee3da6113b23594cec6fb0c67">hstnegsucstschng</a>) {
+<a name="l00255"></a>00255                 <span class="comment">/* Print statements during the HNP interrupt handling</span>
+<a name="l00256"></a>00256 <span class="comment">                 * can cause it to fail.*/</span>
+<a name="l00257"></a>00257                 gotgctl.<a class="code" href="uniongotgctl__data.html#ebb591ab40ff41f0e06f03a795647d33">d32</a> = dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#54034d00bb6b47ada4e0c0baa87cbd8a">gotgctl</a>);
+<a name="l00258"></a>00258                 <span class="keywordflow">if</span> (gotgctl.<a class="code" href="uniongotgctl__data.html#212c81366266e906a188f4dbfadb6dd3">b</a>.<a class="code" href="uniongotgctl__data.html#20b17868fc09a12b163732d5bbc84d8d">hstnegscs</a>) {
+<a name="l00259"></a>00259                         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#f0bfe5f933e21a94ea06c96ffc086e72">dwc_otg_is_host_mode</a>(core_if)) {
+<a name="l00260"></a>00260                                 core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5a5c5c1cf8d870101cc1fffac56d88c0">op_state</a> = <a class="code" href="dwc__otg__cil_8h.html#02d6d4d9a0fdcc4fc8c5cf8e6c8577aa">B_HOST</a>;
+<a name="l00261"></a>00261                                 <span class="comment">/*</span>
+<a name="l00262"></a>00262 <span class="comment">                                 * Need to disable SOF interrupt immediately.</span>
+<a name="l00263"></a>00263 <span class="comment">                                 * When switching from device to host, the PCD</span>
+<a name="l00264"></a>00264 <span class="comment">                                 * interrupt handler won't handle the</span>
+<a name="l00265"></a>00265 <span class="comment">                                 * interrupt if host mode is already set. The</span>
+<a name="l00266"></a>00266 <span class="comment">                                 * HCD interrupt handler won't get called if</span>
+<a name="l00267"></a>00267 <span class="comment">                                 * the HCD state is HALT. This means that the</span>
+<a name="l00268"></a>00268 <span class="comment">                                 * interrupt does not get handled and Linux</span>
+<a name="l00269"></a>00269 <span class="comment">                                 * complains loudly.</span>
+<a name="l00270"></a>00270 <span class="comment">                                 */</span>
+<a name="l00271"></a>00271                                 gintmsk.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a> = 0;
+<a name="l00272"></a>00272                                 gintmsk.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#d9cb28e92090a5da3c00d35768d90c82">sofintr</a> = 1;
+<a name="l00273"></a>00273                                 dwc_modify_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#48827c76da2c6b18f369e2f2483cc4b6">gintmsk</a>,
+<a name="l00274"></a>00274                                                  gintmsk.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a>, 0);
+<a name="l00275"></a>00275                                 <a class="code" href="dwc__otg__cil__intr_8c.html#d8eff82b37ea044fd7621faedcb36570">pcd_stop</a>(core_if);
+<a name="l00276"></a>00276                                 <span class="comment">/*</span>
+<a name="l00277"></a>00277 <span class="comment">                                 * Initialize the Core for Host mode.</span>
+<a name="l00278"></a>00278 <span class="comment">                                 */</span>
+<a name="l00279"></a>00279                                 <a class="code" href="dwc__otg__cil__intr_8c.html#fc2d933cd662b3d060747004c79203a1">hcd_start</a>(core_if);
+<a name="l00280"></a>00280                                 core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5a5c5c1cf8d870101cc1fffac56d88c0">op_state</a> = <a class="code" href="dwc__otg__cil_8h.html#02d6d4d9a0fdcc4fc8c5cf8e6c8577aa">B_HOST</a>;
+<a name="l00281"></a>00281                         }
+<a name="l00282"></a>00282                 } <span class="keywordflow">else</span> {
+<a name="l00283"></a>00283                         gotgctl.<a class="code" href="uniongotgctl__data.html#ebb591ab40ff41f0e06f03a795647d33">d32</a> = 0;
+<a name="l00284"></a>00284                         gotgctl.<a class="code" href="uniongotgctl__data.html#212c81366266e906a188f4dbfadb6dd3">b</a>.<a class="code" href="uniongotgctl__data.html#08487ecb0860252b73815ee6e0f8eaa3">hnpreq</a> = 1;
+<a name="l00285"></a>00285                         gotgctl.<a class="code" href="uniongotgctl__data.html#212c81366266e906a188f4dbfadb6dd3">b</a>.<a class="code" href="uniongotgctl__data.html#0058cbee8b53336c28746116301ea796">devhnpen</a> = 1;
+<a name="l00286"></a>00286                         dwc_modify_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#54034d00bb6b47ada4e0c0baa87cbd8a">gotgctl</a>, gotgctl.<a class="code" href="uniongotgctl__data.html#ebb591ab40ff41f0e06f03a795647d33">d32</a>, 0);
+<a name="l00287"></a>00287                         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#2bf62a567355d1ea38814714bd7b57ec">DBG_ANY</a>, <span class="stringliteral">"HNP Failed\n"</span>);
+<a name="l00288"></a>00288                         __DWC_ERROR(<span class="stringliteral">"Device Not Connected/Responding\n"</span>);
+<a name="l00289"></a>00289                 }
+<a name="l00290"></a>00290         }
+<a name="l00291"></a>00291         <span class="keywordflow">if</span> (gotgint.<a class="code" href="uniongotgint__data.html#e48c5633608687c8895da201199c2a7c">b</a>.<a class="code" href="uniongotgint__data.html#7cd2a34cef45f168eb3ee197c101d164">hstnegdet</a>) {
+<a name="l00292"></a>00292                 <span class="comment">/* The disconnect interrupt is set at the same time as</span>
+<a name="l00293"></a>00293 <span class="comment">                 * Host Negotiation Detected.  During the mode</span>
+<a name="l00294"></a>00294 <span class="comment">                 * switch all interrupts are cleared so the disconnect</span>
+<a name="l00295"></a>00295 <span class="comment">                 * interrupt handler will not get executed.</span>
+<a name="l00296"></a>00296 <span class="comment">                 */</span>
+<a name="l00297"></a>00297                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#2bf62a567355d1ea38814714bd7b57ec">DBG_ANY</a>, <span class="stringliteral">" ++OTG Interrupt: "</span>
+<a name="l00298"></a>00298                             <span class="stringliteral">"Host Negotiation Detected++ (%s)\n"</span>,
+<a name="l00299"></a>00299                             (<a class="code" href="dwc__otg__cil_8c.html#f0bfe5f933e21a94ea06c96ffc086e72">dwc_otg_is_host_mode</a>(core_if) ? <span class="stringliteral">"Host"</span> :
+<a name="l00300"></a>00300                              <span class="stringliteral">"Device"</span>));
+<a name="l00301"></a>00301                 <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#e83fb22890bc54c6b06cedb751430e77">dwc_otg_is_device_mode</a>(core_if)) {
+<a name="l00302"></a>00302                         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#2bf62a567355d1ea38814714bd7b57ec">DBG_ANY</a>, <span class="stringliteral">"a_suspend-&gt;a_peripheral (%d)\n"</span>,
+<a name="l00303"></a>00303                                     core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5a5c5c1cf8d870101cc1fffac56d88c0">op_state</a>);
+<a name="l00304"></a>00304                         <a class="code" href="dwc__otg__cil__intr_8c.html#b208bc4537e7b26658edc642e407894b">hcd_disconnect</a>(core_if);
+<a name="l00305"></a>00305                         <a class="code" href="dwc__otg__cil__intr_8c.html#a1de88a9a54457a0b828a8a2845a210c">pcd_start</a>(core_if);
+<a name="l00306"></a>00306                         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5a5c5c1cf8d870101cc1fffac56d88c0">op_state</a> = <a class="code" href="dwc__otg__cil_8h.html#7528970c03451cfc85e86ab92bbaf554">A_PERIPHERAL</a>;
+<a name="l00307"></a>00307                 } <span class="keywordflow">else</span> {
+<a name="l00308"></a>00308                         <span class="comment">/*</span>
+<a name="l00309"></a>00309 <span class="comment">                         * Need to disable SOF interrupt immediately. When</span>
+<a name="l00310"></a>00310 <span class="comment">                         * switching from device to host, the PCD interrupt</span>
+<a name="l00311"></a>00311 <span class="comment">                         * handler won't handle the interrupt if host mode is</span>
+<a name="l00312"></a>00312 <span class="comment">                         * already set. The HCD interrupt handler won't get</span>
+<a name="l00313"></a>00313 <span class="comment">                         * called if the HCD state is HALT. This means that</span>
+<a name="l00314"></a>00314 <span class="comment">                         * the interrupt does not get handled and Linux</span>
+<a name="l00315"></a>00315 <span class="comment">                         * complains loudly.</span>
+<a name="l00316"></a>00316 <span class="comment">                         */</span>
+<a name="l00317"></a>00317                         gintmsk.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a> = 0;
+<a name="l00318"></a>00318                         gintmsk.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#d9cb28e92090a5da3c00d35768d90c82">sofintr</a> = 1;
+<a name="l00319"></a>00319                         dwc_modify_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#48827c76da2c6b18f369e2f2483cc4b6">gintmsk</a>, gintmsk.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a>, 0);
+<a name="l00320"></a>00320                         <a class="code" href="dwc__otg__cil__intr_8c.html#d8eff82b37ea044fd7621faedcb36570">pcd_stop</a>(core_if);
+<a name="l00321"></a>00321                         <a class="code" href="dwc__otg__cil__intr_8c.html#fc2d933cd662b3d060747004c79203a1">hcd_start</a>(core_if);
+<a name="l00322"></a>00322                         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5a5c5c1cf8d870101cc1fffac56d88c0">op_state</a> = <a class="code" href="dwc__otg__cil_8h.html#a0732b344b6571a4554968e4ee2214dd">A_HOST</a>;
+<a name="l00323"></a>00323                 }
+<a name="l00324"></a>00324         }
+<a name="l00325"></a>00325         <span class="keywordflow">if</span> (gotgint.<a class="code" href="uniongotgint__data.html#e48c5633608687c8895da201199c2a7c">b</a>.<a class="code" href="uniongotgint__data.html#f216cb4939e1a348fbffaff87fc42772">adevtoutchng</a>) {
+<a name="l00326"></a>00326                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#2bf62a567355d1ea38814714bd7b57ec">DBG_ANY</a>, <span class="stringliteral">" ++OTG Interrupt: "</span>
+<a name="l00327"></a>00327                             <span class="stringliteral">"A-Device Timeout Change++\n"</span>);
+<a name="l00328"></a>00328         }
+<a name="l00329"></a>00329         <span class="keywordflow">if</span> (gotgint.<a class="code" href="uniongotgint__data.html#e48c5633608687c8895da201199c2a7c">b</a>.<a class="code" href="uniongotgint__data.html#7bac6821d07d401731213dc0e94852ca">debdone</a>) {
+<a name="l00330"></a>00330                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#2bf62a567355d1ea38814714bd7b57ec">DBG_ANY</a>, <span class="stringliteral">" ++OTG Interrupt: "</span> <span class="stringliteral">"Debounce Done++\n"</span>);
+<a name="l00331"></a>00331         }
+<a name="l00332"></a>00332 
+<a name="l00333"></a>00333         <span class="comment">/* Clear GOTGINT */</span>
+<a name="l00334"></a>00334         dwc_write_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#69cc290cfdfe6900890f7a5a16b3137c">gotgint</a>, gotgint.<a class="code" href="uniongotgint__data.html#8a343df4fc4e68b802be7629864308e2">d32</a>);
+<a name="l00335"></a>00335 
+<a name="l00336"></a>00336         <span class="keywordflow">return</span> 1;
+<a name="l00337"></a>00337 }
+<a name="l00338"></a>00338 
+<a name="l00339"></a><a class="code" href="dwc__otg__cil__intr_8c.html#9ef061e0e79210e6c2a2c2b9cc45bd45">00339</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8h.html#9ef061e0e79210e6c2a2c2b9cc45bd45">w_conn_id_status_change</a>(<span class="keywordtype">void</span> *p)
+<a name="l00340"></a>00340 {
+<a name="l00341"></a>00341         <a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if = p;
+<a name="l00342"></a>00342         uint32_t count = 0;
+<a name="l00343"></a>00343         <a class="code" href="uniongotgctl__data.html">gotgctl_data_t</a> gotgctl = {.d32 = 0 };
+<a name="l00344"></a>00344 
+<a name="l00345"></a>00345         gotgctl.<a class="code" href="uniongotgctl__data.html#ebb591ab40ff41f0e06f03a795647d33">d32</a> = dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#54034d00bb6b47ada4e0c0baa87cbd8a">gotgctl</a>);
+<a name="l00346"></a>00346         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">DBG_CIL</a>, <span class="stringliteral">"gotgctl=%0x\n"</span>, gotgctl.<a class="code" href="uniongotgctl__data.html#ebb591ab40ff41f0e06f03a795647d33">d32</a>);
+<a name="l00347"></a>00347         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">DBG_CIL</a>, <span class="stringliteral">"gotgctl.b.conidsts=%d\n"</span>, gotgctl.<a class="code" href="uniongotgctl__data.html#212c81366266e906a188f4dbfadb6dd3">b</a>.<a class="code" href="uniongotgctl__data.html#777151f3c8c1b3117493aee2cd7a2e5c">conidsts</a>);
+<a name="l00348"></a>00348 
+<a name="l00349"></a>00349         <span class="comment">/* B-Device connector (Device Mode) */</span>
+<a name="l00350"></a>00350         <span class="keywordflow">if</span> (gotgctl.<a class="code" href="uniongotgctl__data.html#212c81366266e906a188f4dbfadb6dd3">b</a>.<a class="code" href="uniongotgctl__data.html#777151f3c8c1b3117493aee2cd7a2e5c">conidsts</a>) {
+<a name="l00351"></a>00351                 <span class="comment">/* Wait for switch to device mode. */</span>
+<a name="l00352"></a>00352                 <span class="keywordflow">while</span> (!<a class="code" href="dwc__otg__cil_8c.html#e83fb22890bc54c6b06cedb751430e77">dwc_otg_is_device_mode</a>(core_if)) {
+<a name="l00353"></a>00353                         DWC_PRINTF(<span class="stringliteral">"Waiting for Peripheral Mode, Mode=%s\n"</span>,
+<a name="l00354"></a>00354                                    (<a class="code" href="dwc__otg__cil_8c.html#f0bfe5f933e21a94ea06c96ffc086e72">dwc_otg_is_host_mode</a>(core_if) ? <span class="stringliteral">"Host"</span> :
+<a name="l00355"></a>00355                                     <span class="stringliteral">"Peripheral"</span>));
+<a name="l00356"></a>00356                         dwc_mdelay(100);
+<a name="l00357"></a>00357                         <span class="keywordflow">if</span> (++count &gt; 10000)
+<a name="l00358"></a>00358                                 <span class="keywordflow">break</span>;
+<a name="l00359"></a>00359                 }
+<a name="l00360"></a>00360                 DWC_ASSERT(++count &lt; 10000,
+<a name="l00361"></a>00361                            <span class="stringliteral">"Connection id status change timed out"</span>);
+<a name="l00362"></a>00362                 core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5a5c5c1cf8d870101cc1fffac56d88c0">op_state</a> = <a class="code" href="dwc__otg__cil_8h.html#622c3b95c9a587f518a787c05c50ffb7">B_PERIPHERAL</a>;
+<a name="l00363"></a>00363                 <a class="code" href="dwc__otg__cil_8c.html#ce48d4f2d172600c325a82d793473d0f">dwc_otg_core_init</a>(core_if);
+<a name="l00364"></a>00364                 <a class="code" href="dwc__otg__cil_8c.html#8b0b841d69298089b7d03b07ade8eda6">dwc_otg_enable_global_interrupts</a>(core_if);
+<a name="l00365"></a>00365                 <a class="code" href="dwc__otg__cil__intr_8c.html#a1de88a9a54457a0b828a8a2845a210c">pcd_start</a>(core_if);
+<a name="l00366"></a>00366         } <span class="keywordflow">else</span> {
+<a name="l00367"></a>00367                 <span class="comment">/* A-Device connector (Host Mode) */</span>
+<a name="l00368"></a>00368                 <span class="keywordflow">while</span> (!<a class="code" href="dwc__otg__cil_8c.html#f0bfe5f933e21a94ea06c96ffc086e72">dwc_otg_is_host_mode</a>(core_if)) {
+<a name="l00369"></a>00369                         DWC_PRINTF(<span class="stringliteral">"Waiting for Host Mode, Mode=%s\n"</span>,
+<a name="l00370"></a>00370                                    (<a class="code" href="dwc__otg__cil_8c.html#f0bfe5f933e21a94ea06c96ffc086e72">dwc_otg_is_host_mode</a>(core_if) ? <span class="stringliteral">"Host"</span> :
+<a name="l00371"></a>00371                                     <span class="stringliteral">"Peripheral"</span>));
+<a name="l00372"></a>00372                         dwc_mdelay(100);
+<a name="l00373"></a>00373                         <span class="keywordflow">if</span> (++count &gt; 10000)
+<a name="l00374"></a>00374                                 <span class="keywordflow">break</span>;
+<a name="l00375"></a>00375                 }
+<a name="l00376"></a>00376                 DWC_ASSERT(++count &lt; 10000,
+<a name="l00377"></a>00377                            <span class="stringliteral">"Connection id status change timed out"</span>);
+<a name="l00378"></a>00378                 core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5a5c5c1cf8d870101cc1fffac56d88c0">op_state</a> = <a class="code" href="dwc__otg__cil_8h.html#a0732b344b6571a4554968e4ee2214dd">A_HOST</a>;
+<a name="l00379"></a>00379                 <span class="comment">/*</span>
+<a name="l00380"></a>00380 <span class="comment">                 * Initialize the Core for Host mode.</span>
+<a name="l00381"></a>00381 <span class="comment">                 */</span>
+<a name="l00382"></a>00382                 <a class="code" href="dwc__otg__cil_8c.html#ce48d4f2d172600c325a82d793473d0f">dwc_otg_core_init</a>(core_if);
+<a name="l00383"></a>00383                 <a class="code" href="dwc__otg__cil_8c.html#8b0b841d69298089b7d03b07ade8eda6">dwc_otg_enable_global_interrupts</a>(core_if);
+<a name="l00384"></a>00384                 <a class="code" href="dwc__otg__cil__intr_8c.html#fc2d933cd662b3d060747004c79203a1">hcd_start</a>(core_if);
+<a name="l00385"></a>00385         }
+<a name="l00386"></a>00386 }
+<a name="l00387"></a>00387 
+<a name="l00399"></a><a class="code" href="dwc__otg__cil__intr_8c.html#edfd5ea8fead031a866ea017c3181c50">00399</a> int32_t <a class="code" href="dwc__otg__cil__intr_8c.html#edfd5ea8fead031a866ea017c3181c50">dwc_otg_handle_conn_id_status_change_intr</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l00400"></a>00400 {
+<a name="l00401"></a>00401 
+<a name="l00402"></a>00402         <span class="comment">/*</span>
+<a name="l00403"></a>00403 <span class="comment">         * Need to disable SOF interrupt immediately. If switching from device</span>
+<a name="l00404"></a>00404 <span class="comment">         * to host, the PCD interrupt handler won't handle the interrupt if</span>
+<a name="l00405"></a>00405 <span class="comment">         * host mode is already set. The HCD interrupt handler won't get</span>
+<a name="l00406"></a>00406 <span class="comment">         * called if the HCD state is HALT. This means that the interrupt does</span>
+<a name="l00407"></a>00407 <span class="comment">         * not get handled and Linux complains loudly.</span>
+<a name="l00408"></a>00408 <span class="comment">         */</span>
+<a name="l00409"></a>00409         <a class="code" href="uniongintmsk__data.html">gintmsk_data_t</a> gintmsk = {.d32 = 0 };
+<a name="l00410"></a>00410         <a class="code" href="uniongintsts__data.html">gintsts_data_t</a> gintsts = {.d32 = 0 };
+<a name="l00411"></a>00411 
+<a name="l00412"></a>00412         gintmsk.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#d9cb28e92090a5da3c00d35768d90c82">sofintr</a> = 1;
+<a name="l00413"></a>00413         dwc_modify_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#48827c76da2c6b18f369e2f2483cc4b6">gintmsk</a>, gintmsk.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a>, 0);
+<a name="l00414"></a>00414 
+<a name="l00415"></a>00415         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">DBG_CIL</a>,
+<a name="l00416"></a>00416                     <span class="stringliteral">" ++Connector ID Status Change Interrupt++  (%s)\n"</span>,
+<a name="l00417"></a>00417                     (<a class="code" href="dwc__otg__cil_8c.html#f0bfe5f933e21a94ea06c96ffc086e72">dwc_otg_is_host_mode</a>(core_if) ? <span class="stringliteral">"Host"</span> : <span class="stringliteral">"Device"</span>));
+<a name="l00418"></a>00418 
+<a name="l00419"></a>00419         <span class="comment">/*</span>
+<a name="l00420"></a>00420 <span class="comment">         * Need to schedule a work, as there are possible DELAY function calls</span>
+<a name="l00421"></a>00421 <span class="comment">         */</span>
+<a name="l00422"></a>00422         DWC_WORKQ_SCHEDULE(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3716f6d6bc6f956a45efbe6e308386">wq_otg</a>, <a class="code" href="dwc__otg__cil_8h.html#9ef061e0e79210e6c2a2c2b9cc45bd45">w_conn_id_status_change</a>,
+<a name="l00423"></a>00423                            core_if, <span class="stringliteral">"connection id status change"</span>);
+<a name="l00424"></a>00424 
+<a name="l00425"></a>00425         <span class="comment">/* Set flag and clear interrupt */</span>
+<a name="l00426"></a>00426         gintsts.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#86b8b53e53486db96a8faf6307c248df">conidstschng</a> = 1;
+<a name="l00427"></a>00427         dwc_write_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>, gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a>);
+<a name="l00428"></a>00428 
+<a name="l00429"></a>00429         <span class="keywordflow">return</span> 1;
+<a name="l00430"></a>00430 }
+<a name="l00431"></a>00431 
+<a name="l00441"></a><a class="code" href="dwc__otg__cil__intr_8c.html#c38ce60f07652dd841d000a3c56a1f9f">00441</a> int32_t <a class="code" href="dwc__otg__cil__intr_8c.html#c38ce60f07652dd841d000a3c56a1f9f">dwc_otg_handle_session_req_intr</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l00442"></a>00442 {
+<a name="l00443"></a>00443         <a class="code" href="unionhprt0__data.html">hprt0_data_t</a> hprt0;
+<a name="l00444"></a>00444         <a class="code" href="uniongintsts__data.html">gintsts_data_t</a> gintsts;
+<a name="l00445"></a>00445 
+<a name="l00446"></a>00446 <span class="preprocessor">#ifndef DWC_HOST_ONLY</span>
+<a name="l00447"></a>00447 <span class="preprocessor"></span>        <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#2bf62a567355d1ea38814714bd7b57ec">DBG_ANY</a>, <span class="stringliteral">"++Session Request Interrupt++\n"</span>);
+<a name="l00448"></a>00448 
+<a name="l00449"></a>00449         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#e83fb22890bc54c6b06cedb751430e77">dwc_otg_is_device_mode</a>(core_if)) {
+<a name="l00450"></a>00450                 DWC_PRINTF(<span class="stringliteral">"SRP: Device mode\n"</span>);
+<a name="l00451"></a>00451         } <span class="keywordflow">else</span> {
+<a name="l00452"></a>00452                 DWC_PRINTF(<span class="stringliteral">"SRP: Host mode\n"</span>);
+<a name="l00453"></a>00453 
+<a name="l00454"></a>00454                 <span class="comment">/* Turn on the port power bit. */</span>
+<a name="l00455"></a>00455                 hprt0.<a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a> = <a class="code" href="dwc__otg__cil_8h.html#ce67da6af4023cffd25333d20992438e">dwc_otg_read_hprt0</a>(core_if);
+<a name="l00456"></a>00456                 hprt0.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#010bd8fb208ef4eeaa288b28f8f8c3a4">prtpwr</a> = 1;
+<a name="l00457"></a>00457                 dwc_write_reg32(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#dc8fe33e0bb3829cafa884d5fc603c4d">hprt0</a>, hprt0.<a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a>);
+<a name="l00458"></a>00458 
+<a name="l00459"></a>00459                 <span class="comment">/* Start the Connection timer. So a message can be displayed</span>
+<a name="l00460"></a>00460 <span class="comment">                 * if connect does not occur within 10 seconds. */</span>
+<a name="l00461"></a>00461                 <a class="code" href="dwc__otg__cil__intr_8c.html#2ccec1f0c44ae8129f3012a519ecd5eb">hcd_session_start</a>(core_if);
+<a name="l00462"></a>00462         }
+<a name="l00463"></a>00463 <span class="preprocessor">#endif</span>
+<a name="l00464"></a>00464 <span class="preprocessor"></span>
+<a name="l00465"></a>00465         <span class="comment">/* Clear interrupt */</span>
+<a name="l00466"></a>00466         gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a> = 0;
+<a name="l00467"></a>00467         gintsts.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#c8b14c042daab677d0c4ae691d573995">sessreqintr</a> = 1;
+<a name="l00468"></a>00468         dwc_write_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>, gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a>);
+<a name="l00469"></a>00469 
+<a name="l00470"></a>00470         <span class="keywordflow">return</span> 1;
+<a name="l00471"></a>00471 }
+<a name="l00472"></a>00472 
+<a name="l00473"></a><a class="code" href="dwc__otg__cil__intr_8c.html#07f0b189448c71e7ea4c7b121320fb89">00473</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8h.html#07f0b189448c71e7ea4c7b121320fb89">w_wakeup_detected</a>(<span class="keywordtype">void</span> *p)
+<a name="l00474"></a>00474 {
+<a name="l00475"></a>00475         <a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if = (<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *) p;
+<a name="l00476"></a>00476         <span class="comment">/*</span>
+<a name="l00477"></a>00477 <span class="comment">         * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms</span>
+<a name="l00478"></a>00478 <span class="comment">         * so that OPT tests pass with all PHYs).</span>
+<a name="l00479"></a>00479 <span class="comment">         */</span>
+<a name="l00480"></a>00480         <a class="code" href="unionhprt0__data.html">hprt0_data_t</a> hprt0 = {.d32 = 0 };
+<a name="l00481"></a>00481 <span class="preprocessor">#if 0</span>
+<a name="l00482"></a>00482 <span class="preprocessor"></span>        <a class="code" href="unionpcgcctl__data.html">pcgcctl_data_t</a> pcgcctl = {.d32 = 0 };
+<a name="l00483"></a>00483         <span class="comment">/* Restart the Phy Clock */</span>
+<a name="l00484"></a>00484         pcgcctl.<a class="code" href="unionpcgcctl__data.html#f2bb76709d0ab9d08280eafb78a36279">b</a>.<a class="code" href="unionpcgcctl__data.html#bf40184845ef70be8e59b2672cb0bedf">stoppclk</a> = 1;
+<a name="l00485"></a>00485         dwc_modify_reg32(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#348ed2c9aeae6fc608f1bb813978b3f9">pcgcctl</a>, pcgcctl.<a class="code" href="unionpcgcctl__data.html#abe048ee884143501929b27d94c52db7">d32</a>, 0);
+<a name="l00486"></a>00486         dwc_udelay(10);
+<a name="l00487"></a>00487 <span class="preprocessor">#endif                          //0</span>
+<a name="l00488"></a>00488 <span class="preprocessor"></span>        hprt0.<a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a> = <a class="code" href="dwc__otg__cil_8h.html#ce67da6af4023cffd25333d20992438e">dwc_otg_read_hprt0</a>(core_if);
+<a name="l00489"></a>00489         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#2bf62a567355d1ea38814714bd7b57ec">DBG_ANY</a>, <span class="stringliteral">"Resume: HPRT0=%0x\n"</span>, hprt0.<a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a>);
+<a name="l00490"></a>00490 <span class="comment">//      dwc_mdelay(70);</span>
+<a name="l00491"></a>00491         hprt0.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#3f5961529636a3891a4ca9421dd535fa">prtres</a> = 0;     <span class="comment">/* Resume */</span>
+<a name="l00492"></a>00492         dwc_write_reg32(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#dc8fe33e0bb3829cafa884d5fc603c4d">hprt0</a>, hprt0.<a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a>);
+<a name="l00493"></a>00493         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#2bf62a567355d1ea38814714bd7b57ec">DBG_ANY</a>, <span class="stringliteral">"Clear Resume: HPRT0=%0x\n"</span>,
+<a name="l00494"></a>00494                     dwc_read_reg32(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#dc8fe33e0bb3829cafa884d5fc603c4d">hprt0</a>));
+<a name="l00495"></a>00495 
+<a name="l00496"></a>00496         <a class="code" href="dwc__otg__cil__intr_8c.html#681e193a107c04b5005500ff35c59cd5">hcd_resume</a>(core_if);
+<a name="l00497"></a>00497 
+<a name="l00499"></a>00499         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#2b0701d814069ec69897e08374366c7b">lx_state</a> = <a class="code" href="dwc__otg__cil_8h.html#8442e49b7c783099ac17bda4f8b3bc3c9743a36d9b0b8c66a11a0714fdd27fb5">DWC_OTG_L0</a>;
+<a name="l00500"></a>00500 
+<a name="l00501"></a>00501 }
+<a name="l00502"></a>00502 
+<a name="l00510"></a><a class="code" href="dwc__otg__cil__intr_8c.html#775343dba810fff0c4f17f8616d82f62">00510</a> int32_t <a class="code" href="dwc__otg__cil__intr_8c.html#775343dba810fff0c4f17f8616d82f62">dwc_otg_handle_wakeup_detected_intr</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l00511"></a>00511 {
+<a name="l00512"></a>00512         <a class="code" href="uniongintsts__data.html">gintsts_data_t</a> gintsts;
+<a name="l00513"></a>00513 
+<a name="l00514"></a>00514         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#2bf62a567355d1ea38814714bd7b57ec">DBG_ANY</a>,
+<a name="l00515"></a>00515                     <span class="stringliteral">"++Resume and Remote Wakeup Detected Interrupt++\n"</span>);
+<a name="l00516"></a>00516 
+<a name="l00517"></a>00517         DWC_PRINTF(<span class="stringliteral">"%s lxstate = %d\n"</span>, __func__, core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#2b0701d814069ec69897e08374366c7b">lx_state</a>);
+<a name="l00518"></a>00518 
+<a name="l00519"></a>00519         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#e83fb22890bc54c6b06cedb751430e77">dwc_otg_is_device_mode</a>(core_if)) {
+<a name="l00520"></a>00520                 <a class="code" href="uniondctl__data.html">dctl_data_t</a> dctl = {.d32 = 0 };
+<a name="l00521"></a>00521                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"DSTS=0x%0x\n"</span>,
+<a name="l00522"></a>00522                             dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;
+<a name="l00523"></a>00523                                            dsts));
+<a name="l00524"></a>00524                 <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#2b0701d814069ec69897e08374366c7b">lx_state</a> == <a class="code" href="dwc__otg__cil_8h.html#8442e49b7c783099ac17bda4f8b3bc3cd1fadb6fa31de73e8176316a0e0ba905">DWC_OTG_L2</a>) {
+<a name="l00525"></a>00525 <span class="preprocessor">#ifdef PARTIAL_POWER_DOWN</span>
+<a name="l00526"></a>00526 <span class="preprocessor"></span>                        <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#9c1394f3c46adde2fa7be79bf0237f9b">hwcfg4</a>.<a class="code" href="unionhwcfg4__data.html#9fb9175668e2381c568c5adbf6e5225d">b</a>.<a class="code" href="unionhwcfg4__data.html#3227ec0129191d0d099f0dce7f18c546">power_optimiz</a>) {
+<a name="l00527"></a>00527                                 <a class="code" href="unionpcgcctl__data.html">pcgcctl_data_t</a> power = {.d32 = 0 };
+<a name="l00528"></a>00528 
+<a name="l00529"></a>00529                                 power.<a class="code" href="unionpcgcctl__data.html#abe048ee884143501929b27d94c52db7">d32</a> = dwc_read_reg32(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#348ed2c9aeae6fc608f1bb813978b3f9">pcgcctl</a>);
+<a name="l00530"></a>00530                                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">DBG_CIL</a>, <span class="stringliteral">"PCGCCTL=%0x\n"</span>,
+<a name="l00531"></a>00531                                             power.<a class="code" href="unionpcgcctl__data.html#abe048ee884143501929b27d94c52db7">d32</a>);
+<a name="l00532"></a>00532 
+<a name="l00533"></a>00533                                 power.<a class="code" href="unionpcgcctl__data.html#f2bb76709d0ab9d08280eafb78a36279">b</a>.<a class="code" href="unionpcgcctl__data.html#bf40184845ef70be8e59b2672cb0bedf">stoppclk</a> = 0;
+<a name="l00534"></a>00534                                 dwc_write_reg32(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#348ed2c9aeae6fc608f1bb813978b3f9">pcgcctl</a>, power.<a class="code" href="unionpcgcctl__data.html#abe048ee884143501929b27d94c52db7">d32</a>);
+<a name="l00535"></a>00535 
+<a name="l00536"></a>00536                                 power.<a class="code" href="unionpcgcctl__data.html#f2bb76709d0ab9d08280eafb78a36279">b</a>.<a class="code" href="unionpcgcctl__data.html#02d7dff0f26c3ac50ad4b876f1853c17">pwrclmp</a> = 0;
+<a name="l00537"></a>00537                                 dwc_write_reg32(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#348ed2c9aeae6fc608f1bb813978b3f9">pcgcctl</a>, power.<a class="code" href="unionpcgcctl__data.html#abe048ee884143501929b27d94c52db7">d32</a>);
+<a name="l00538"></a>00538 
+<a name="l00539"></a>00539                                 power.<a class="code" href="unionpcgcctl__data.html#f2bb76709d0ab9d08280eafb78a36279">b</a>.<a class="code" href="unionpcgcctl__data.html#9708a50a6e42cd2372d65555edf5cf28">rstpdwnmodule</a> = 0;
+<a name="l00540"></a>00540                                 dwc_write_reg32(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#348ed2c9aeae6fc608f1bb813978b3f9">pcgcctl</a>, power.<a class="code" href="unionpcgcctl__data.html#abe048ee884143501929b27d94c52db7">d32</a>);
+<a name="l00541"></a>00541                         }
+<a name="l00542"></a>00542 <span class="preprocessor">#endif</span>
+<a name="l00543"></a>00543 <span class="preprocessor"></span>                        <span class="comment">/* Clear the Remote Wakeup Signalling */</span>
+<a name="l00544"></a>00544                         dctl.<a class="code" href="uniondctl__data.html#a3abfa6d609d9864f1f65712b409d4d3">b</a>.<a class="code" href="uniondctl__data.html#dcae5af28dc159cd7ba85a9a2b8be51a">rmtwkupsig</a> = 1;
+<a name="l00545"></a>00545                         dwc_modify_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;
+<a name="l00546"></a>00546                                          dctl, dctl.<a class="code" href="uniondctl__data.html#f49aadfd7ad95b570115b3c245b1729e">d32</a>, 0);
+<a name="l00547"></a>00547 
+<a name="l00548"></a>00548                         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#83bca1e02fafc4bbfa9c1f2eeb19b245">pcd_cb</a> &amp;&amp; core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#83bca1e02fafc4bbfa9c1f2eeb19b245">pcd_cb</a>-&gt;<a class="code" href="structdwc__otg__cil__callbacks.html#ad1895ddf4ad83622a514a725b4129d6">resume_wakeup</a>) {
+<a name="l00549"></a>00549                                 core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#83bca1e02fafc4bbfa9c1f2eeb19b245">pcd_cb</a>-&gt;<a class="code" href="structdwc__otg__cil__callbacks.html#ad1895ddf4ad83622a514a725b4129d6">resume_wakeup</a>(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#83bca1e02fafc4bbfa9c1f2eeb19b245">pcd_cb</a>-&gt;
+<a name="l00550"></a>00550                                                                p);
+<a name="l00551"></a>00551                         }
+<a name="l00552"></a>00552                 } <span class="keywordflow">else</span> {
+<a name="l00553"></a>00553                         <a class="code" href="unionglpmctl__data.html">glpmcfg_data_t</a> lpmcfg;
+<a name="l00554"></a>00554                         lpmcfg.<a class="code" href="unionglpmctl__data.html#cd41461734ff898209bfb64057ef2eb8">d32</a> =
+<a name="l00555"></a>00555                             dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#843cfb38ba366a9a46ad07ed11eb8396">glpmcfg</a>);
+<a name="l00556"></a>00556                         lpmcfg.<a class="code" href="unionglpmctl__data.html#bd3cc34c338226ff1cd89448f7590ff1">b</a>.<a class="code" href="unionglpmctl__data.html#e2ceea4bfe468c7b3c800235d7ffd5d2">hird_thres</a> &amp;= (~(1 &lt;&lt; 4));
+<a name="l00557"></a>00557                         dwc_write_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#843cfb38ba366a9a46ad07ed11eb8396">glpmcfg</a>,
+<a name="l00558"></a>00558                                         lpmcfg.<a class="code" href="unionglpmctl__data.html#cd41461734ff898209bfb64057ef2eb8">d32</a>);
+<a name="l00559"></a>00559                 }
+<a name="l00561"></a>00561                 core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#2b0701d814069ec69897e08374366c7b">lx_state</a> = <a class="code" href="dwc__otg__cil_8h.html#8442e49b7c783099ac17bda4f8b3bc3c9743a36d9b0b8c66a11a0714fdd27fb5">DWC_OTG_L0</a>;
+<a name="l00562"></a>00562         } <span class="keywordflow">else</span> {
+<a name="l00563"></a>00563                 <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#2b0701d814069ec69897e08374366c7b">lx_state</a> != <a class="code" href="dwc__otg__cil_8h.html#8442e49b7c783099ac17bda4f8b3bc3cf5b112742a8103f3489107ad26c0ff58">DWC_OTG_L1</a>) {
+<a name="l00564"></a>00564                         <a class="code" href="unionpcgcctl__data.html">pcgcctl_data_t</a> pcgcctl = {.d32 = 0 };
+<a name="l00565"></a>00565 
+<a name="l00566"></a>00566                         <span class="comment">/* Restart the Phy Clock */</span>
+<a name="l00567"></a>00567                         pcgcctl.<a class="code" href="unionpcgcctl__data.html#f2bb76709d0ab9d08280eafb78a36279">b</a>.<a class="code" href="unionpcgcctl__data.html#bf40184845ef70be8e59b2672cb0bedf">stoppclk</a> = 1;
+<a name="l00568"></a>00568                         dwc_modify_reg32(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#348ed2c9aeae6fc608f1bb813978b3f9">pcgcctl</a>, pcgcctl.<a class="code" href="unionpcgcctl__data.html#abe048ee884143501929b27d94c52db7">d32</a>, 0);
+<a name="l00569"></a>00569 
+<a name="l00570"></a>00570                         DWC_TIMER_SCHEDULE(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#c914461f460deacd426bea7a05ebb204">wkp_timer</a>, 71);
+<a name="l00571"></a>00571                 } <span class="keywordflow">else</span> {
+<a name="l00573"></a>00573                         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#2b0701d814069ec69897e08374366c7b">lx_state</a> = <a class="code" href="dwc__otg__cil_8h.html#8442e49b7c783099ac17bda4f8b3bc3c9743a36d9b0b8c66a11a0714fdd27fb5">DWC_OTG_L0</a>;
+<a name="l00574"></a>00574                 }
+<a name="l00575"></a>00575         }
+<a name="l00576"></a>00576 
+<a name="l00577"></a>00577         <span class="comment">/* Clear interrupt */</span>
+<a name="l00578"></a>00578         gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a> = 0;
+<a name="l00579"></a>00579         gintsts.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#d2e845fd68f2e8abe6b7445dbde9d2a4">wkupintr</a> = 1;
+<a name="l00580"></a>00580         dwc_write_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>, gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a>);
+<a name="l00581"></a>00581 
+<a name="l00582"></a>00582         <span class="keywordflow">return</span> 1;
+<a name="l00583"></a>00583 }
+<a name="l00584"></a>00584 
+<a name="l00589"></a><a class="code" href="dwc__otg__cil__intr_8c.html#93001a1a9717b7e0491f5a2548fce1b6">00589</a> int32_t <a class="code" href="dwc__otg__cil__intr_8c.html#93001a1a9717b7e0491f5a2548fce1b6">dwc_otg_handle_disconnect_intr</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l00590"></a>00590 {
+<a name="l00591"></a>00591         <a class="code" href="uniongintsts__data.html">gintsts_data_t</a> gintsts;
+<a name="l00592"></a>00592 
+<a name="l00593"></a>00593         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#2bf62a567355d1ea38814714bd7b57ec">DBG_ANY</a>, <span class="stringliteral">"++Disconnect Detected Interrupt++ (%s) %s\n"</span>,
+<a name="l00594"></a>00594                     (<a class="code" href="dwc__otg__cil_8c.html#f0bfe5f933e21a94ea06c96ffc086e72">dwc_otg_is_host_mode</a>(core_if) ? <span class="stringliteral">"Host"</span> : <span class="stringliteral">"Device"</span>),
+<a name="l00595"></a>00595                     op_state_str(core_if));
+<a name="l00596"></a>00596 
+<a name="l00598"></a>00598 <span class="preprocessor">#ifndef DWC_HOST_ONLY</span>
+<a name="l00599"></a>00599 <span class="preprocessor"></span>        <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5a5c5c1cf8d870101cc1fffac56d88c0">op_state</a> == <a class="code" href="dwc__otg__cil_8h.html#02d6d4d9a0fdcc4fc8c5cf8e6c8577aa">B_HOST</a>) {
+<a name="l00600"></a>00600                 <span class="comment">/* If in device mode Disconnect and stop the HCD, then</span>
+<a name="l00601"></a>00601 <span class="comment">                 * start the PCD. */</span>
+<a name="l00602"></a>00602                 <a class="code" href="dwc__otg__cil__intr_8c.html#b208bc4537e7b26658edc642e407894b">hcd_disconnect</a>(core_if);
+<a name="l00603"></a>00603                 <a class="code" href="dwc__otg__cil__intr_8c.html#a1de88a9a54457a0b828a8a2845a210c">pcd_start</a>(core_if);
+<a name="l00604"></a>00604                 core_if-&gt;op_state = <a class="code" href="dwc__otg__cil_8h.html#622c3b95c9a587f518a787c05c50ffb7">B_PERIPHERAL</a>;
+<a name="l00605"></a>00605         } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#e83fb22890bc54c6b06cedb751430e77">dwc_otg_is_device_mode</a>(core_if)) {
+<a name="l00606"></a>00606                 <a class="code" href="uniongotgctl__data.html">gotgctl_data_t</a> gotgctl = {.d32 = 0 };
+<a name="l00607"></a>00607                 gotgctl.<a class="code" href="uniongotgctl__data.html#ebb591ab40ff41f0e06f03a795647d33">d32</a> =
+<a name="l00608"></a>00608                     dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#54034d00bb6b47ada4e0c0baa87cbd8a">gotgctl</a>);
+<a name="l00609"></a>00609                 <span class="keywordflow">if</span> (gotgctl.<a class="code" href="uniongotgctl__data.html#212c81366266e906a188f4dbfadb6dd3">b</a>.<a class="code" href="uniongotgctl__data.html#7d45791d3622a59ff43ab248bbb1b2c1">hstsethnpen</a> == 1) {
+<a name="l00610"></a>00610                         <span class="comment">/* Do nothing, if HNP in process the OTG</span>
+<a name="l00611"></a>00611 <span class="comment">                         * interrupt "Host Negotiation Detected"</span>
+<a name="l00612"></a>00612 <span class="comment">                         * interrupt will do the mode switch.</span>
+<a name="l00613"></a>00613 <span class="comment">                         */</span>
+<a name="l00614"></a>00614                 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (gotgctl.<a class="code" href="uniongotgctl__data.html#212c81366266e906a188f4dbfadb6dd3">b</a>.<a class="code" href="uniongotgctl__data.html#0058cbee8b53336c28746116301ea796">devhnpen</a> == 0) {
+<a name="l00615"></a>00615                         <span class="comment">/* If in device mode Disconnect and stop the HCD, then</span>
+<a name="l00616"></a>00616 <span class="comment">                         * start the PCD. */</span>
+<a name="l00617"></a>00617                         <a class="code" href="dwc__otg__cil__intr_8c.html#b208bc4537e7b26658edc642e407894b">hcd_disconnect</a>(core_if);
+<a name="l00618"></a>00618                         <a class="code" href="dwc__otg__cil__intr_8c.html#a1de88a9a54457a0b828a8a2845a210c">pcd_start</a>(core_if);
+<a name="l00619"></a>00619                         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5a5c5c1cf8d870101cc1fffac56d88c0">op_state</a> = <a class="code" href="dwc__otg__cil_8h.html#622c3b95c9a587f518a787c05c50ffb7">B_PERIPHERAL</a>;
+<a name="l00620"></a>00620                 } <span class="keywordflow">else</span> {
+<a name="l00621"></a>00621                         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#2bf62a567355d1ea38814714bd7b57ec">DBG_ANY</a>, <span class="stringliteral">"!a_peripheral &amp;&amp; !devhnpen\n"</span>);
+<a name="l00622"></a>00622                 }
+<a name="l00623"></a>00623         } <span class="keywordflow">else</span> {
+<a name="l00624"></a>00624                 <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5a5c5c1cf8d870101cc1fffac56d88c0">op_state</a> == <a class="code" href="dwc__otg__cil_8h.html#a0732b344b6571a4554968e4ee2214dd">A_HOST</a>) {
+<a name="l00625"></a>00625                         <span class="comment">/* A-Cable still connected but device disconnected. */</span>
+<a name="l00626"></a>00626                         <a class="code" href="dwc__otg__cil__intr_8c.html#b208bc4537e7b26658edc642e407894b">hcd_disconnect</a>(core_if);
+<a name="l00627"></a>00627                 }
+<a name="l00628"></a>00628         }
+<a name="l00629"></a>00629 <span class="preprocessor">#endif</span>
+<a name="l00630"></a>00630 <span class="preprocessor"></span>        <span class="comment">/* Change to L3(OFF) state */</span>
+<a name="l00631"></a>00631         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#2b0701d814069ec69897e08374366c7b">lx_state</a> = <a class="code" href="dwc__otg__cil_8h.html#8442e49b7c783099ac17bda4f8b3bc3c86715d528a59b114b95aaafa8f2142f6">DWC_OTG_L3</a>;
+<a name="l00632"></a>00632 
+<a name="l00633"></a>00633         gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a> = 0;
+<a name="l00634"></a>00634         gintsts.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#45d8d681263dcfc7c2b6cf30ee689f28">disconnect</a> = 1;
+<a name="l00635"></a>00635         dwc_write_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>, gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a>);
+<a name="l00636"></a>00636         <span class="keywordflow">return</span> 1;
+<a name="l00637"></a>00637 }
+<a name="l00638"></a>00638 
+<a name="l00649"></a><a class="code" href="dwc__otg__cil__intr_8c.html#c7e246ec77f0b751abe95c6e5d09b2fe">00649</a> int32_t <a class="code" href="dwc__otg__cil__intr_8c.html#c7e246ec77f0b751abe95c6e5d09b2fe">dwc_otg_handle_usb_suspend_intr</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l00650"></a>00650 {
+<a name="l00651"></a>00651         <a class="code" href="uniondsts__data.html">dsts_data_t</a> dsts;
+<a name="l00652"></a>00652         <a class="code" href="uniongintsts__data.html">gintsts_data_t</a> gintsts;
+<a name="l00653"></a>00653 
+<a name="l00654"></a>00654         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#2bf62a567355d1ea38814714bd7b57ec">DBG_ANY</a>, <span class="stringliteral">"USB SUSPEND\n"</span>);
+<a name="l00655"></a>00655 
+<a name="l00656"></a>00656         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#e83fb22890bc54c6b06cedb751430e77">dwc_otg_is_device_mode</a>(core_if)) {
+<a name="l00657"></a>00657                 <span class="comment">/* Check the Device status register to determine if the Suspend</span>
+<a name="l00658"></a>00658 <span class="comment">                 * state is active. */</span>
+<a name="l00659"></a>00659                 dsts.<a class="code" href="uniondsts__data.html#0f126daef735b142b06dbc4cdbe13814">d32</a> =
+<a name="l00660"></a>00660                     dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#1ed00edd20ce5db7d07666804101ec05">dsts</a>);
+<a name="l00661"></a>00661                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"DSTS=0x%0x\n"</span>, dsts.<a class="code" href="uniondsts__data.html#0f126daef735b142b06dbc4cdbe13814">d32</a>);
+<a name="l00662"></a>00662                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"DSTS.Suspend Status=%d "</span>
+<a name="l00663"></a>00663                             <span class="stringliteral">"HWCFG4.power Optimize=%d\n"</span>,
+<a name="l00664"></a>00664                             dsts.<a class="code" href="uniondsts__data.html#4066fcedb7ac9a88e47aa1b2df0e89ee">b</a>.<a class="code" href="uniondsts__data.html#4c7cd8ee3877701268846b0b02ac3d97">suspsts</a>, core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#9c1394f3c46adde2fa7be79bf0237f9b">hwcfg4</a>.<a class="code" href="unionhwcfg4__data.html#9fb9175668e2381c568c5adbf6e5225d">b</a>.<a class="code" href="unionhwcfg4__data.html#3227ec0129191d0d099f0dce7f18c546">power_optimiz</a>);
+<a name="l00665"></a>00665 
+<a name="l00666"></a>00666 <span class="preprocessor">#ifdef PARTIAL_POWER_DOWN</span>
+<a name="l00667"></a>00667 <span class="preprocessor"></span>
+<a name="l00669"></a>00669                 <span class="keywordflow">if</span> (dsts.<a class="code" href="uniondsts__data.html#4066fcedb7ac9a88e47aa1b2df0e89ee">b</a>.<a class="code" href="uniondsts__data.html#4c7cd8ee3877701268846b0b02ac3d97">suspsts</a> &amp;&amp; core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#9c1394f3c46adde2fa7be79bf0237f9b">hwcfg4</a>.<a class="code" href="unionhwcfg4__data.html#9fb9175668e2381c568c5adbf6e5225d">b</a>.<a class="code" href="unionhwcfg4__data.html#3227ec0129191d0d099f0dce7f18c546">power_optimiz</a>) {
+<a name="l00670"></a>00670                         <a class="code" href="unionpcgcctl__data.html">pcgcctl_data_t</a> power = {.d32 = 0 };
+<a name="l00671"></a>00671                         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">DBG_CIL</a>, <span class="stringliteral">"suspend\n"</span>);
+<a name="l00672"></a>00672 
+<a name="l00673"></a>00673                         power.<a class="code" href="unionpcgcctl__data.html#f2bb76709d0ab9d08280eafb78a36279">b</a>.<a class="code" href="unionpcgcctl__data.html#02d7dff0f26c3ac50ad4b876f1853c17">pwrclmp</a> = 1;
+<a name="l00674"></a>00674                         dwc_write_reg32(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#348ed2c9aeae6fc608f1bb813978b3f9">pcgcctl</a>, power.<a class="code" href="unionpcgcctl__data.html#abe048ee884143501929b27d94c52db7">d32</a>);
+<a name="l00675"></a>00675 
+<a name="l00676"></a>00676                         power.<a class="code" href="unionpcgcctl__data.html#f2bb76709d0ab9d08280eafb78a36279">b</a>.<a class="code" href="unionpcgcctl__data.html#9708a50a6e42cd2372d65555edf5cf28">rstpdwnmodule</a> = 1;
+<a name="l00677"></a>00677                         dwc_modify_reg32(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#348ed2c9aeae6fc608f1bb813978b3f9">pcgcctl</a>, 0, power.<a class="code" href="unionpcgcctl__data.html#abe048ee884143501929b27d94c52db7">d32</a>);
+<a name="l00678"></a>00678 
+<a name="l00679"></a>00679                         power.<a class="code" href="unionpcgcctl__data.html#f2bb76709d0ab9d08280eafb78a36279">b</a>.<a class="code" href="unionpcgcctl__data.html#bf40184845ef70be8e59b2672cb0bedf">stoppclk</a> = 1;
+<a name="l00680"></a>00680                         dwc_modify_reg32(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#348ed2c9aeae6fc608f1bb813978b3f9">pcgcctl</a>, 0, power.<a class="code" href="unionpcgcctl__data.html#abe048ee884143501929b27d94c52db7">d32</a>);
+<a name="l00681"></a>00681 
+<a name="l00682"></a>00682                 } <span class="keywordflow">else</span> {
+<a name="l00683"></a>00683                         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#2bf62a567355d1ea38814714bd7b57ec">DBG_ANY</a>, <span class="stringliteral">"disconnect?\n"</span>);
+<a name="l00684"></a>00684                 }
+<a name="l00685"></a>00685 <span class="preprocessor">#endif</span>
+<a name="l00686"></a>00686 <span class="preprocessor"></span>                <span class="comment">/* PCD callback for suspend. */</span>
+<a name="l00687"></a>00687                 <a class="code" href="dwc__otg__cil__intr_8c.html#d9ac0577152f65fe83a76cbbca4ea795">pcd_suspend</a>(core_if);
+<a name="l00688"></a>00688         } <span class="keywordflow">else</span> {
+<a name="l00689"></a>00689                 <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5a5c5c1cf8d870101cc1fffac56d88c0">op_state</a> == <a class="code" href="dwc__otg__cil_8h.html#7528970c03451cfc85e86ab92bbaf554">A_PERIPHERAL</a>) {
+<a name="l00690"></a>00690                         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#2bf62a567355d1ea38814714bd7b57ec">DBG_ANY</a>, <span class="stringliteral">"a_peripheral-&gt;a_host\n"</span>);
+<a name="l00691"></a>00691                         <span class="comment">/* Clear the a_peripheral flag, back to a_host. */</span>
+<a name="l00692"></a>00692                         <a class="code" href="dwc__otg__cil__intr_8c.html#d8eff82b37ea044fd7621faedcb36570">pcd_stop</a>(core_if);
+<a name="l00693"></a>00693                         <a class="code" href="dwc__otg__cil__intr_8c.html#fc2d933cd662b3d060747004c79203a1">hcd_start</a>(core_if);
+<a name="l00694"></a>00694                         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5a5c5c1cf8d870101cc1fffac56d88c0">op_state</a> = <a class="code" href="dwc__otg__cil_8h.html#a0732b344b6571a4554968e4ee2214dd">A_HOST</a>;
+<a name="l00695"></a>00695                 }
+<a name="l00696"></a>00696         }
+<a name="l00697"></a>00697 
+<a name="l00698"></a>00698         <span class="comment">/* Change to L2(suspend) state */</span>
+<a name="l00699"></a>00699         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#2b0701d814069ec69897e08374366c7b">lx_state</a> = <a class="code" href="dwc__otg__cil_8h.html#8442e49b7c783099ac17bda4f8b3bc3cd1fadb6fa31de73e8176316a0e0ba905">DWC_OTG_L2</a>;
+<a name="l00700"></a>00700 
+<a name="l00701"></a>00701         <span class="comment">/* Clear interrupt */</span>
+<a name="l00702"></a>00702         gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a> = 0;
+<a name="l00703"></a>00703         gintsts.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#de67a7536cdb9305e24f05d771708bce">usbsuspend</a> = 1;
+<a name="l00704"></a>00704         dwc_write_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>, gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a>);
+<a name="l00705"></a>00705 
+<a name="l00706"></a>00706         <span class="keywordflow">return</span> 1;
+<a name="l00707"></a>00707 }
+<a name="l00708"></a>00708 
+<a name="l00709"></a>00709 <span class="preprocessor">#ifdef CONFIG_USB_DWC_OTG_LPM</span>
+<a name="l00710"></a>00710 <span class="preprocessor"></span>
+<a name="l00713"></a>00713 <span class="keyword">static</span> int32_t dwc_otg_handle_lpm_intr(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l00714"></a>00714 {
+<a name="l00715"></a>00715         <a class="code" href="unionglpmctl__data.html">glpmcfg_data_t</a> lpmcfg;
+<a name="l00716"></a>00716         <a class="code" href="uniongintsts__data.html">gintsts_data_t</a> gintsts;
+<a name="l00717"></a>00717 
+<a name="l00718"></a>00718         <span class="keywordflow">if</span> (!core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#8b906ba765a10dd9fcfa1c02dbc0184e">lpm_enable</a>) {
+<a name="l00719"></a>00719                 DWC_PRINTF(<span class="stringliteral">"Unexpected LPM interrupt\n"</span>);
+<a name="l00720"></a>00720         }
+<a name="l00721"></a>00721 
+<a name="l00722"></a>00722         lpmcfg.<a class="code" href="unionglpmctl__data.html#cd41461734ff898209bfb64057ef2eb8">d32</a> = dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#843cfb38ba366a9a46ad07ed11eb8396">glpmcfg</a>);
+<a name="l00723"></a>00723         DWC_PRINTF(<span class="stringliteral">"LPM config register = 0x%08x\n"</span>, lpmcfg.<a class="code" href="unionglpmctl__data.html#cd41461734ff898209bfb64057ef2eb8">d32</a>);
+<a name="l00724"></a>00724 
+<a name="l00725"></a>00725         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#f0bfe5f933e21a94ea06c96ffc086e72">dwc_otg_is_host_mode</a>(core_if)) {
+<a name="l00726"></a>00726                 hcd_sleep(core_if);
+<a name="l00727"></a>00727         } <span class="keywordflow">else</span> {
+<a name="l00728"></a>00728                 lpmcfg.<a class="code" href="unionglpmctl__data.html#bd3cc34c338226ff1cd89448f7590ff1">b</a>.<a class="code" href="unionglpmctl__data.html#e2ceea4bfe468c7b3c800235d7ffd5d2">hird_thres</a> |= (1 &lt;&lt; 4);
+<a name="l00729"></a>00729                 dwc_write_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#843cfb38ba366a9a46ad07ed11eb8396">glpmcfg</a>,
+<a name="l00730"></a>00730                                 lpmcfg.<a class="code" href="unionglpmctl__data.html#cd41461734ff898209bfb64057ef2eb8">d32</a>);
+<a name="l00731"></a>00731         }
+<a name="l00732"></a>00732 
+<a name="l00733"></a>00733         <span class="comment">/* Examine prt_sleep_sts after TL1TokenTetry period max (10 us) */</span>      
+<a name="l00734"></a>00734         dwc_udelay(10);
+<a name="l00735"></a>00735         lpmcfg.<a class="code" href="unionglpmctl__data.html#cd41461734ff898209bfb64057ef2eb8">d32</a> = dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#843cfb38ba366a9a46ad07ed11eb8396">glpmcfg</a>);
+<a name="l00736"></a>00736         <span class="keywordflow">if</span> (lpmcfg.<a class="code" href="unionglpmctl__data.html#bd3cc34c338226ff1cd89448f7590ff1">b</a>.<a class="code" href="unionglpmctl__data.html#241ff25a215f16ac29b3bb6d9f4943ed">prt_sleep_sts</a>) {
+<a name="l00737"></a>00737                 <span class="comment">/* Save the current state */</span>
+<a name="l00738"></a>00738                 core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#2b0701d814069ec69897e08374366c7b">lx_state</a> = <a class="code" href="dwc__otg__cil_8h.html#8442e49b7c783099ac17bda4f8b3bc3cf5b112742a8103f3489107ad26c0ff58">DWC_OTG_L1</a>;
+<a name="l00739"></a>00739         }
+<a name="l00740"></a>00740 
+<a name="l00741"></a>00741         <span class="comment">/* Clear interrupt  */</span>
+<a name="l00742"></a>00742         gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a> = 0;
+<a name="l00743"></a>00743         gintsts.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#50e73e91df681c835de50f8276058829">lpmtranrcvd</a> = 1;
+<a name="l00744"></a>00744         dwc_write_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>, gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a>);
+<a name="l00745"></a>00745         <span class="keywordflow">return</span> 1;
+<a name="l00746"></a>00746 }
+<a name="l00747"></a>00747 <span class="preprocessor">#endif                          </span><span class="comment">/* CONFIG_USB_DWC_OTG_LPM */</span>
+<a name="l00748"></a>00748 
+<a name="l00752"></a><a class="code" href="dwc__otg__cil__intr_8c.html#b86f8c4806bdc1f78ea438263c9f6c67">00752</a> <span class="keyword">static</span> <span class="keyword">inline</span> uint32_t <a class="code" href="dwc__otg__cil__intr_8c.html#b86f8c4806bdc1f78ea438263c9f6c67">dwc_otg_read_common_intr</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l00753"></a>00753 {
+<a name="l00754"></a>00754         <a class="code" href="uniongintsts__data.html">gintsts_data_t</a> gintsts;
+<a name="l00755"></a>00755         <a class="code" href="uniongintmsk__data.html">gintmsk_data_t</a> gintmsk;
+<a name="l00756"></a>00756         <a class="code" href="uniongintmsk__data.html">gintmsk_data_t</a> gintmsk_common = {.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a> = 0 };
+<a name="l00757"></a>00757         gintmsk_common.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#d3cde0fd62a006ec3f5db615f1e62da5">wkupintr</a> = 1;
+<a name="l00758"></a>00758         gintmsk_common.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#aabb586a72e2a76982bfaa780e482212">sessreqintr</a> = 1;
+<a name="l00759"></a>00759         gintmsk_common.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#ade723f4f136cfa884e5bf536d913f14">conidstschng</a> = 1;
+<a name="l00760"></a>00760         gintmsk_common.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#6c9d578034af4f2ca08447fdac22ff88">otgintr</a> = 1;
+<a name="l00761"></a>00761         gintmsk_common.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#f62315fe9de8bb3bc371cb0a51927496">modemismatch</a> = 1;
+<a name="l00762"></a>00762         gintmsk_common.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#0ff313bfc712a2f3d71bc1a5f1a17ce2">disconnect</a> = 1;
+<a name="l00763"></a>00763         gintmsk_common.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#3b93f1ae00dcd1dcc4d6d19547f26b56">usbsuspend</a> = 1;
+<a name="l00764"></a>00764 <span class="preprocessor">#ifdef CONFIG_USB_DWC_OTG_LPM</span>
+<a name="l00765"></a>00765 <span class="preprocessor"></span>        gintmsk_common.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#24f9f89b33866c5dc7b16588bc94e103">lpmtranrcvd</a> = 1;
+<a name="l00766"></a>00766 <span class="preprocessor">#endif</span>
+<a name="l00767"></a>00767 <span class="preprocessor"></span>
+<a name="l00770"></a>00770         gintmsk_common.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#c907c60cbc7b157e730b053b40f4a2b3">portintr</a> = 1;
+<a name="l00771"></a>00771 
+<a name="l00772"></a>00772         gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a> = dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>);
+<a name="l00773"></a>00773         gintmsk.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a> = dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#48827c76da2c6b18f369e2f2483cc4b6">gintmsk</a>);
+<a name="l00774"></a>00774 <span class="preprocessor">#ifdef DEBUG</span>
+<a name="l00775"></a>00775 <span class="preprocessor"></span>        <span class="comment">/* if any common interrupts set */</span>
+<a name="l00776"></a>00776         <span class="keywordflow">if</span> (gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a> &amp; gintmsk_common.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a>) {
+<a name="l00777"></a>00777                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#2bf62a567355d1ea38814714bd7b57ec">DBG_ANY</a>, <span class="stringliteral">"gintsts=%08x  gintmsk=%08x\n"</span>,
+<a name="l00778"></a>00778                             gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a>, gintmsk.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a>);
+<a name="l00779"></a>00779         }
+<a name="l00780"></a>00780 <span class="preprocessor">#endif</span>
+<a name="l00781"></a>00781 <span class="preprocessor"></span>
+<a name="l00782"></a>00782         <span class="keywordflow">return</span> ((gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a> &amp; gintmsk.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a>) &amp; gintmsk_common.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a>);
+<a name="l00783"></a>00783 
+<a name="l00784"></a>00784 }
+<a name="l00785"></a>00785 
+<a name="l00800"></a><a class="code" href="dwc__otg__core__if_8h.html#f13810eb319c429745b8f5cb9870dc2b">00800</a> int32_t <a class="code" href="dwc__otg__cil__intr_8c.html#1fad5cb7f68bc87c628bc4cb5db922b8">dwc_otg_handle_common_intr</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l00801"></a>00801 {
+<a name="l00802"></a>00802         <span class="keywordtype">int</span> retval = 0;
+<a name="l00803"></a>00803         <a class="code" href="uniongintsts__data.html">gintsts_data_t</a> gintsts;
+<a name="l00804"></a>00804 
+<a name="l00805"></a>00805         gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a> = <a class="code" href="dwc__otg__cil__intr_8c.html#b86f8c4806bdc1f78ea438263c9f6c67">dwc_otg_read_common_intr</a>(core_if);
+<a name="l00806"></a>00806 
+<a name="l00807"></a>00807         <span class="keywordflow">if</span> (gintsts.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#5fda463a80eb6927b2b875d64e8a0753">modemismatch</a>) {
+<a name="l00808"></a>00808                 retval |= <a class="code" href="dwc__otg__cil__intr_8c.html#934ada5611b9fac2645fa286fbc12cf0">dwc_otg_handle_mode_mismatch_intr</a>(core_if);
+<a name="l00809"></a>00809         }
+<a name="l00810"></a>00810         <span class="keywordflow">if</span> (gintsts.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#7934c11c40b0b60137edbdaa2be45542">otgintr</a>) {
+<a name="l00811"></a>00811                 retval |= <a class="code" href="dwc__otg__cil__intr_8c.html#420006ca946698a9eb123ad352df8870">dwc_otg_handle_otg_intr</a>(core_if);
+<a name="l00812"></a>00812         }
+<a name="l00813"></a>00813         <span class="keywordflow">if</span> (gintsts.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#86b8b53e53486db96a8faf6307c248df">conidstschng</a>) {
+<a name="l00814"></a>00814                 retval |= <a class="code" href="dwc__otg__cil__intr_8c.html#edfd5ea8fead031a866ea017c3181c50">dwc_otg_handle_conn_id_status_change_intr</a>(core_if);
+<a name="l00815"></a>00815         }
+<a name="l00816"></a>00816         <span class="keywordflow">if</span> (gintsts.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#45d8d681263dcfc7c2b6cf30ee689f28">disconnect</a>) {
+<a name="l00817"></a>00817                 retval |= <a class="code" href="dwc__otg__cil__intr_8c.html#93001a1a9717b7e0491f5a2548fce1b6">dwc_otg_handle_disconnect_intr</a>(core_if);
+<a name="l00818"></a>00818         }
+<a name="l00819"></a>00819         <span class="keywordflow">if</span> (gintsts.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#c8b14c042daab677d0c4ae691d573995">sessreqintr</a>) {
+<a name="l00820"></a>00820                 retval |= <a class="code" href="dwc__otg__cil__intr_8c.html#c38ce60f07652dd841d000a3c56a1f9f">dwc_otg_handle_session_req_intr</a>(core_if);
+<a name="l00821"></a>00821         }
+<a name="l00822"></a>00822         <span class="keywordflow">if</span> (gintsts.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#d2e845fd68f2e8abe6b7445dbde9d2a4">wkupintr</a>) {
+<a name="l00823"></a>00823                 retval |= <a class="code" href="dwc__otg__cil__intr_8c.html#775343dba810fff0c4f17f8616d82f62">dwc_otg_handle_wakeup_detected_intr</a>(core_if);
+<a name="l00824"></a>00824         }
+<a name="l00825"></a>00825         <span class="keywordflow">if</span> (gintsts.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#de67a7536cdb9305e24f05d771708bce">usbsuspend</a>) {
+<a name="l00826"></a>00826                 retval |= <a class="code" href="dwc__otg__cil__intr_8c.html#c7e246ec77f0b751abe95c6e5d09b2fe">dwc_otg_handle_usb_suspend_intr</a>(core_if);
+<a name="l00827"></a>00827         }
+<a name="l00828"></a>00828 <span class="preprocessor">#ifdef CONFIG_USB_DWC_OTG_LPM</span>
+<a name="l00829"></a>00829 <span class="preprocessor"></span>        <span class="keywordflow">if</span> (gintsts.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#50e73e91df681c835de50f8276058829">lpmtranrcvd</a>) {
+<a name="l00830"></a>00830                 retval |= dwc_otg_handle_lpm_intr(core_if);
+<a name="l00831"></a>00831         }
+<a name="l00832"></a>00832 <span class="preprocessor">#endif</span>
+<a name="l00833"></a>00833 <span class="preprocessor"></span>
+<a name="l00834"></a>00834         <span class="keywordflow">if</span> (gintsts.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#7490e48c2c93d20c182f00161f18b8e5">portintr</a> &amp;&amp; <a class="code" href="dwc__otg__cil_8c.html#e83fb22890bc54c6b06cedb751430e77">dwc_otg_is_device_mode</a>(core_if)) {
+<a name="l00835"></a>00835                 <span class="comment">/* The port interrupt occurs while in device mode with HPRT0</span>
+<a name="l00836"></a>00836 <span class="comment">                 * Port Enable/Disable.</span>
+<a name="l00837"></a>00837 <span class="comment">                 */</span>
+<a name="l00838"></a>00838                 gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a> = 0;
+<a name="l00839"></a>00839                 gintsts.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#7490e48c2c93d20c182f00161f18b8e5">portintr</a> = 1;
+<a name="l00840"></a>00840                 dwc_write_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>,
+<a name="l00841"></a>00841                                 gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a>);
+<a name="l00842"></a>00842                 retval |= 1;
+<a name="l00843"></a>00843 
+<a name="l00844"></a>00844         }
+<a name="l00845"></a>00845         <span class="keywordflow">return</span> retval;
+<a name="l00846"></a>00846 }
+</pre></div><hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil__intr_8c.html b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil__intr_8c.html
new file mode 100644
index 000000000000..24c66e38dee7
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil__intr_8c.html
@@ -0,0 +1,645 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_cil_intr.c File Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<h1>dwc_otg_cil_intr.c File Reference</h1>The Core Interface Layer provides basic services for accessing and managing the DWC_otg hardware. <a href="#_details">More...</a>
+<p>
+<code>#include &quot;dwc_os.h&quot;</code><br>
+<code>#include &quot;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&quot;</code><br>
+<code>#include &quot;<a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a>&quot;</code><br>
+
+<p>
+<a href="dwc__otg__cil__intr_8c-source.html">Go to the source code of this file.</a><table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Functions</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil__intr_8c.html#934ada5611b9fac2645fa286fbc12cf0">dwc_otg_handle_mode_mismatch_intr</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function will log a debug message.  <a href="#934ada5611b9fac2645fa286fbc12cf0"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil__intr_8c.html#fc2d933cd662b3d060747004c79203a1">hcd_start</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Start the HCD.  <a href="#fc2d933cd662b3d060747004c79203a1"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil__intr_8c.html#b2721d01cc389181470095955b4e0994">hcd_stop</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Stop the HCD.  <a href="#b2721d01cc389181470095955b4e0994"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil__intr_8c.html#b208bc4537e7b26658edc642e407894b">hcd_disconnect</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Disconnect the HCD.  <a href="#b208bc4537e7b26658edc642e407894b"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil__intr_8c.html#2ccec1f0c44ae8129f3012a519ecd5eb">hcd_session_start</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Inform the HCD the a New Session has begun.  <a href="#2ccec1f0c44ae8129f3012a519ecd5eb"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil__intr_8c.html#681e193a107c04b5005500ff35c59cd5">hcd_resume</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Resume the HCD.  <a href="#681e193a107c04b5005500ff35c59cd5"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil__intr_8c.html#a1de88a9a54457a0b828a8a2845a210c">pcd_start</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Start the PCD.  <a href="#a1de88a9a54457a0b828a8a2845a210c"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil__intr_8c.html#d8eff82b37ea044fd7621faedcb36570">pcd_stop</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Stop the PCD.  <a href="#d8eff82b37ea044fd7621faedcb36570"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil__intr_8c.html#d9ac0577152f65fe83a76cbbca4ea795">pcd_suspend</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Suspend the PCD.  <a href="#d9ac0577152f65fe83a76cbbca4ea795"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil__intr_8c.html#7d70de843b2e147969d32f7a9b2aa9e3">pcd_resume</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Resume the PCD.  <a href="#7d70de843b2e147969d32f7a9b2aa9e3"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil__intr_8c.html#420006ca946698a9eb123ad352df8870">dwc_otg_handle_otg_intr</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function handles the OTG Interrupts.  <a href="#420006ca946698a9eb123ad352df8870"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="9ef061e0e79210e6c2a2c2b9cc45bd45"></a><!-- doxytag: member="dwc_otg_cil_intr.c::w_conn_id_status_change" ref="9ef061e0e79210e6c2a2c2b9cc45bd45" args="(void *p)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil__intr_8c.html#9ef061e0e79210e6c2a2c2b9cc45bd45">w_conn_id_status_change</a> (void *p)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil__intr_8c.html#edfd5ea8fead031a866ea017c3181c50">dwc_otg_handle_conn_id_status_change_intr</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function handles the Connector ID Status Change Interrupt.  <a href="#edfd5ea8fead031a866ea017c3181c50"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil__intr_8c.html#c38ce60f07652dd841d000a3c56a1f9f">dwc_otg_handle_session_req_intr</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This interrupt indicates that a device is initiating the Session Request Protocol to request the host to turn on bus power so a new session can begin.  <a href="#c38ce60f07652dd841d000a3c56a1f9f"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil__intr_8c.html#07f0b189448c71e7ea4c7b121320fb89">w_wakeup_detected</a> (void *p)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil__intr_8c.html#775343dba810fff0c4f17f8616d82f62">dwc_otg_handle_wakeup_detected_intr</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This interrupt indicates that the DWC_otg controller has detected a resume or remote wakeup sequence.  <a href="#775343dba810fff0c4f17f8616d82f62"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil__intr_8c.html#93001a1a9717b7e0491f5a2548fce1b6">dwc_otg_handle_disconnect_intr</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This interrupt indicates that a device has been disconnected from the root port.  <a href="#93001a1a9717b7e0491f5a2548fce1b6"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil__intr_8c.html#c7e246ec77f0b751abe95c6e5d09b2fe">dwc_otg_handle_usb_suspend_intr</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This interrupt indicates that SUSPEND state has been detected on the USB.  <a href="#c7e246ec77f0b751abe95c6e5d09b2fe"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil__intr_8c.html#b86f8c4806bdc1f78ea438263c9f6c67">dwc_otg_read_common_intr</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function returns the Core Interrupt register.  <a href="#b86f8c4806bdc1f78ea438263c9f6c67"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__cil__intr_8c.html#1fad5cb7f68bc87c628bc4cb5db922b8">dwc_otg_handle_common_intr</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function should be called on every hardware interrupt.  <a href="#1fad5cb7f68bc87c628bc4cb5db922b8"></a><br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+The Core Interface Layer provides basic services for accessing and managing the DWC_otg hardware. 
+<p>
+These services are used by both the Host Controller Driver and the Peripheral Controller Driver.<p>
+This file contains the Common Interrupt handlers. 
+<p>
+Definition in file <a class="el" href="dwc__otg__cil__intr_8c-source.html">dwc_otg_cil_intr.c</a>.<hr><h2>Function Documentation</h2>
+<a class="anchor" name="934ada5611b9fac2645fa286fbc12cf0"></a><!-- doxytag: member="dwc_otg_cil_intr.c::dwc_otg_handle_mode_mismatch_intr" ref="934ada5611b9fac2645fa286fbc12cf0" args="(dwc_otg_core_if_t *core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t dwc_otg_handle_mode_mismatch_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function will log a debug message. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil__intr_8c-source.html#l00061">61</a> of file <a class="el" href="dwc__otg__cil__intr_8c-source.html">dwc_otg_cil_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="fc2d933cd662b3d060747004c79203a1"></a><!-- doxytag: member="dwc_otg_cil_intr.c::hcd_start" ref="fc2d933cd662b3d060747004c79203a1" args="(dwc_otg_core_if_t *core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static void hcd_start           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [inline, static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Start the HCD. 
+<p>
+Helper function for using the HCD callbacks.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil__intr_8c-source.html#l00078">78</a> of file <a class="el" href="dwc__otg__cil__intr_8c-source.html">dwc_otg_cil_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="b2721d01cc389181470095955b4e0994"></a><!-- doxytag: member="dwc_otg_cil_intr.c::hcd_stop" ref="b2721d01cc389181470095955b4e0994" args="(dwc_otg_core_if_t *core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static void hcd_stop           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [inline, static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Stop the HCD. 
+<p>
+Helper function for using the HCD callbacks.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil__intr_8c-source.html#l00089">89</a> of file <a class="el" href="dwc__otg__cil__intr_8c-source.html">dwc_otg_cil_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="b208bc4537e7b26658edc642e407894b"></a><!-- doxytag: member="dwc_otg_cil_intr.c::hcd_disconnect" ref="b208bc4537e7b26658edc642e407894b" args="(dwc_otg_core_if_t *core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static void hcd_disconnect           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [inline, static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Disconnect the HCD. 
+<p>
+Helper function for using the HCD callbacks.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil__intr_8c-source.html#l00100">100</a> of file <a class="el" href="dwc__otg__cil__intr_8c-source.html">dwc_otg_cil_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="2ccec1f0c44ae8129f3012a519ecd5eb"></a><!-- doxytag: member="dwc_otg_cil_intr.c::hcd_session_start" ref="2ccec1f0c44ae8129f3012a519ecd5eb" args="(dwc_otg_core_if_t *core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static void hcd_session_start           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [inline, static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Inform the HCD the a New Session has begun. 
+<p>
+Helper function for using the HCD callbacks.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil__intr_8c-source.html#l00112">112</a> of file <a class="el" href="dwc__otg__cil__intr_8c-source.html">dwc_otg_cil_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="681e193a107c04b5005500ff35c59cd5"></a><!-- doxytag: member="dwc_otg_cil_intr.c::hcd_resume" ref="681e193a107c04b5005500ff35c59cd5" args="(dwc_otg_core_if_t *core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static void hcd_resume           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [inline, static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Resume the HCD. 
+<p>
+Helper function for using the HCD callbacks.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil__intr_8c-source.html#l00138">138</a> of file <a class="el" href="dwc__otg__cil__intr_8c-source.html">dwc_otg_cil_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="a1de88a9a54457a0b828a8a2845a210c"></a><!-- doxytag: member="dwc_otg_cil_intr.c::pcd_start" ref="a1de88a9a54457a0b828a8a2845a210c" args="(dwc_otg_core_if_t *core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static void pcd_start           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [inline, static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Start the PCD. 
+<p>
+Helper function for using the PCD callbacks.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil__intr_8c-source.html#l00149">149</a> of file <a class="el" href="dwc__otg__cil__intr_8c-source.html">dwc_otg_cil_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="d8eff82b37ea044fd7621faedcb36570"></a><!-- doxytag: member="dwc_otg_cil_intr.c::pcd_stop" ref="d8eff82b37ea044fd7621faedcb36570" args="(dwc_otg_core_if_t *core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static void pcd_stop           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [inline, static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Stop the PCD. 
+<p>
+Helper function for using the PCD callbacks.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil__intr_8c-source.html#l00160">160</a> of file <a class="el" href="dwc__otg__cil__intr_8c-source.html">dwc_otg_cil_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="d9ac0577152f65fe83a76cbbca4ea795"></a><!-- doxytag: member="dwc_otg_cil_intr.c::pcd_suspend" ref="d9ac0577152f65fe83a76cbbca4ea795" args="(dwc_otg_core_if_t *core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static void pcd_suspend           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [inline, static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Suspend the PCD. 
+<p>
+Helper function for using the PCD callbacks.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil__intr_8c-source.html#l00171">171</a> of file <a class="el" href="dwc__otg__cil__intr_8c-source.html">dwc_otg_cil_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="7d70de843b2e147969d32f7a9b2aa9e3"></a><!-- doxytag: member="dwc_otg_cil_intr.c::pcd_resume" ref="7d70de843b2e147969d32f7a9b2aa9e3" args="(dwc_otg_core_if_t *core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static void pcd_resume           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [inline, static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Resume the PCD. 
+<p>
+Helper function for using the PCD callbacks.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil__intr_8c-source.html#l00182">182</a> of file <a class="el" href="dwc__otg__cil__intr_8c-source.html">dwc_otg_cil_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="420006ca946698a9eb123ad352df8870"></a><!-- doxytag: member="dwc_otg_cil_intr.c::dwc_otg_handle_otg_intr" ref="420006ca946698a9eb123ad352df8870" args="(dwc_otg_core_if_t *core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t dwc_otg_handle_otg_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function handles the OTG Interrupts. 
+<p>
+It reads the OTG Interrupt Register (GOTGINT) to determine what interrupt has occurred.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil__intr_8c-source.html#l00196">196</a> of file <a class="el" href="dwc__otg__cil__intr_8c-source.html">dwc_otg_cil_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="edfd5ea8fead031a866ea017c3181c50"></a><!-- doxytag: member="dwc_otg_cil_intr.c::dwc_otg_handle_conn_id_status_change_intr" ref="edfd5ea8fead031a866ea017c3181c50" args="(dwc_otg_core_if_t *core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t dwc_otg_handle_conn_id_status_change_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function handles the Connector ID Status Change Interrupt. 
+<p>
+It reads the OTG Interrupt Register (GOTCTL) to determine whether this is a Device to Host Mode transition or a Host Mode to Device Transition.<p>
+This only occurs when the cable is connected/removed from the PHY connector.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil__intr_8c-source.html#l00399">399</a> of file <a class="el" href="dwc__otg__cil__intr_8c-source.html">dwc_otg_cil_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="c38ce60f07652dd841d000a3c56a1f9f"></a><!-- doxytag: member="dwc_otg_cil_intr.c::dwc_otg_handle_session_req_intr" ref="c38ce60f07652dd841d000a3c56a1f9f" args="(dwc_otg_core_if_t *core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t dwc_otg_handle_session_req_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This interrupt indicates that a device is initiating the Session Request Protocol to request the host to turn on bus power so a new session can begin. 
+<p>
+The handler responds by turning on bus power. If the DWC_otg controller is in low power mode, the handler brings the controller out of low power mode before turning on bus power.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil__intr_8c-source.html#l00441">441</a> of file <a class="el" href="dwc__otg__cil__intr_8c-source.html">dwc_otg_cil_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="07f0b189448c71e7ea4c7b121320fb89"></a><!-- doxytag: member="dwc_otg_cil_intr.c::w_wakeup_detected" ref="07f0b189448c71e7ea4c7b121320fb89" args="(void *p)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void w_wakeup_detected           </td>
+          <td>(</td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>p</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil__intr_8c-source.html#l00473">473</a> of file <a class="el" href="dwc__otg__cil__intr_8c-source.html">dwc_otg_cil_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="775343dba810fff0c4f17f8616d82f62"></a><!-- doxytag: member="dwc_otg_cil_intr.c::dwc_otg_handle_wakeup_detected_intr" ref="775343dba810fff0c4f17f8616d82f62" args="(dwc_otg_core_if_t *core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t dwc_otg_handle_wakeup_detected_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This interrupt indicates that the DWC_otg controller has detected a resume or remote wakeup sequence. 
+<p>
+If the DWC_otg controller is in low power mode, the handler must brings the controller out of low power mode. The controller automatically begins resume signaling. The handler schedules a time to stop resume signaling. 
+<p>
+Change to L0 state<p>
+Change to L0 state 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil__intr_8c-source.html#l00510">510</a> of file <a class="el" href="dwc__otg__cil__intr_8c-source.html">dwc_otg_cil_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="93001a1a9717b7e0491f5a2548fce1b6"></a><!-- doxytag: member="dwc_otg_cil_intr.c::dwc_otg_handle_disconnect_intr" ref="93001a1a9717b7e0491f5a2548fce1b6" args="(dwc_otg_core_if_t *core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t dwc_otg_handle_disconnect_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This interrupt indicates that a device has been disconnected from the root port. 
+<p>
+
+<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000012">Todo:</a></b></dt><dd>Consolidate this if statement. </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil__intr_8c-source.html#l00589">589</a> of file <a class="el" href="dwc__otg__cil__intr_8c-source.html">dwc_otg_cil_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="c7e246ec77f0b751abe95c6e5d09b2fe"></a><!-- doxytag: member="dwc_otg_cil_intr.c::dwc_otg_handle_usb_suspend_intr" ref="c7e246ec77f0b751abe95c6e5d09b2fe" args="(dwc_otg_core_if_t *core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t dwc_otg_handle_usb_suspend_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This interrupt indicates that SUSPEND state has been detected on the USB. 
+<p>
+For HNP the USB Suspend interrupt signals the change from "a_peripheral" to "a_host".<p>
+When power management is enabled the core will be put in low power mode. 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil__intr_8c-source.html#l00649">649</a> of file <a class="el" href="dwc__otg__cil__intr_8c-source.html">dwc_otg_cil_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="b86f8c4806bdc1f78ea438263c9f6c67"></a><!-- doxytag: member="dwc_otg_cil_intr.c::dwc_otg_read_common_intr" ref="b86f8c4806bdc1f78ea438263c9f6c67" args="(dwc_otg_core_if_t *core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static uint32_t dwc_otg_read_common_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [inline, static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function returns the Core Interrupt register. 
+<p>
+
+<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000013">Todo:</a></b></dt><dd>: The port interrupt occurs while in device mode. Added code to CIL to clear the interrupt for now! </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil__intr_8c-source.html#l00752">752</a> of file <a class="el" href="dwc__otg__cil__intr_8c-source.html">dwc_otg_cil_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="1fad5cb7f68bc87c628bc4cb5db922b8"></a><!-- doxytag: member="dwc_otg_cil_intr.c::dwc_otg_handle_common_intr" ref="1fad5cb7f68bc87c628bc4cb5db922b8" args="(dwc_otg_core_if_t *core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t dwc_otg_handle_common_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function should be called on every hardware interrupt. 
+<p>
+The common interrupts are those that occur in both Host and Device mode. This handler handles the following interrupts:<ul>
+<li>Mode Mismatch Interrupt</li><li>Disconnect Interrupt</li><li>OTG Interrupt</li><li>Connector ID Status Change Interrupt</li><li>Session Request Interrupt.</li><li>Resume / Remote Wakeup Detected Interrupt.</li><li>LPM Transaction Received Interrutp </li></ul>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil__intr_8c-source.html#l00800">800</a> of file <a class="el" href="dwc__otg__cil__intr_8c-source.html">dwc_otg_cil_intr.c</a>.
+</div>
+</div><p>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/dwc__otg__core__if_8h-source.html b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__core__if_8h-source.html
new file mode 100644
index 000000000000..76294c2bf173
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__core__if_8h-source.html
@@ -0,0 +1,365 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_core_if.h Source File</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<h1>dwc_otg_core_if.h</h1><a href="dwc__otg__core__if_8h.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">/* ==========================================================================</span>
+<a name="l00002"></a>00002 <span class="comment"> * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_core_if.h $</span>
+<a name="l00003"></a>00003 <span class="comment"> * $Revision: #4 $</span>
+<a name="l00004"></a>00004 <span class="comment"> * $Date: 2008/12/18 $</span>
+<a name="l00005"></a>00005 <span class="comment"> * $Change: 1155299 $</span>
+<a name="l00006"></a>00006 <span class="comment"> *</span>
+<a name="l00007"></a>00007 <span class="comment"> * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,</span>
+<a name="l00008"></a>00008 <span class="comment"> * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless</span>
+<a name="l00009"></a>00009 <span class="comment"> * otherwise expressly agreed to in writing between Synopsys and you.</span>
+<a name="l00010"></a>00010 <span class="comment"> *</span>
+<a name="l00011"></a>00011 <span class="comment"> * The Software IS NOT an item of Licensed Software or Licensed Product under</span>
+<a name="l00012"></a>00012 <span class="comment"> * any End User Software License Agreement or Agreement for Licensed Product</span>
+<a name="l00013"></a>00013 <span class="comment"> * with Synopsys or any supplement thereto. You are permitted to use and</span>
+<a name="l00014"></a>00014 <span class="comment"> * redistribute this Software in source and binary forms, with or without</span>
+<a name="l00015"></a>00015 <span class="comment"> * modification, provided that redistributions of source code must retain this</span>
+<a name="l00016"></a>00016 <span class="comment"> * notice. You may not view, use, disclose, copy or distribute this file or</span>
+<a name="l00017"></a>00017 <span class="comment"> * any information contained herein except pursuant to this license grant from</span>
+<a name="l00018"></a>00018 <span class="comment"> * Synopsys. If you do not agree with this notice, including the disclaimer</span>
+<a name="l00019"></a>00019 <span class="comment"> * below, then you are not authorized to use the Software.</span>
+<a name="l00020"></a>00020 <span class="comment"> *</span>
+<a name="l00021"></a>00021 <span class="comment"> * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS</span>
+<a name="l00022"></a>00022 <span class="comment"> * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE</span>
+<a name="l00023"></a>00023 <span class="comment"> * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE</span>
+<a name="l00024"></a>00024 <span class="comment"> * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,</span>
+<a name="l00025"></a>00025 <span class="comment"> * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES</span>
+<a name="l00026"></a>00026 <span class="comment"> * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR</span>
+<a name="l00027"></a>00027 <span class="comment"> * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER</span>
+<a name="l00028"></a>00028 <span class="comment"> * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT</span>
+<a name="l00029"></a>00029 <span class="comment"> * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY</span>
+<a name="l00030"></a>00030 <span class="comment"> * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH</span>
+<a name="l00031"></a>00031 <span class="comment"> * DAMAGE.</span>
+<a name="l00032"></a>00032 <span class="comment"> * ========================================================================== */</span>
+<a name="l00033"></a>00033 <span class="preprocessor">#if !defined(__DWC_CORE_IF_H__)</span>
+<a name="l00034"></a><a class="code" href="dwc__otg__core__if_8h.html#5bae757850823a08f21d3c2156dcdb19">00034</a> <span class="preprocessor"></span><span class="preprocessor">#define __DWC_CORE_IF_H__</span>
+<a name="l00035"></a>00035 <span class="preprocessor"></span>
+<a name="l00036"></a>00036 <span class="preprocessor">#include "dwc_os.h"</span>
+<a name="l00037"></a>00037 
+<a name="l00042"></a>00042 <span class="keyword">struct </span><a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if</a>;
+<a name="l00043"></a><a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">00043</a> <span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if</a> <a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a>;
+<a name="l00044"></a>00044 
+<a name="l00046"></a><a class="code" href="dwc__otg__core__if_8h.html#13bb22067644d357537c2905fe5ffb8c">00046</a> <span class="preprocessor">#define MAX_PERIO_FIFOS 15</span>
+<a name="l00047"></a>00047 <span class="preprocessor"></span>
+<a name="l00048"></a><a class="code" href="dwc__otg__core__if_8h.html#050db6129005b993e573311dc42bc1a8">00048</a> <span class="preprocessor">#define MAX_TX_FIFOS 15</span>
+<a name="l00049"></a>00049 <span class="preprocessor"></span>
+<a name="l00051"></a><a class="code" href="dwc__otg__core__if_8h.html#bfb88b45545f7685f668ac2f545674ec">00051</a> <span class="preprocessor">#define MAX_EPS_CHANNELS 16</span>
+<a name="l00052"></a>00052 <span class="preprocessor"></span>
+<a name="l00053"></a>00053 <span class="keyword">extern</span> <a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> *<a class="code" href="dwc__otg__cil_8c.html#2dc0a6c5541c1a8a014d66a8fce53f66">dwc_otg_cil_init</a>(<span class="keyword">const</span> uint32_t * _reg_base_addr);
+<a name="l00054"></a>00054 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#ce48d4f2d172600c325a82d793473d0f">dwc_otg_core_init</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * _core_if);
+<a name="l00055"></a>00055 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#cc4a08b278c7afe0484b595cacf80c04">dwc_otg_cil_remove</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * _core_if);
+<a name="l00056"></a>00056 
+<a name="l00057"></a>00057 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#8b0b841d69298089b7d03b07ade8eda6">dwc_otg_enable_global_interrupts</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * _core_if);
+<a name="l00058"></a>00058 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#9f673c38ca761d8ab7b3333b506bcbfc">dwc_otg_disable_global_interrupts</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * _core_if);
+<a name="l00059"></a>00059 
+<a name="l00060"></a>00060 <span class="keyword">extern</span> uint8_t <a class="code" href="dwc__otg__cil_8c.html#e83fb22890bc54c6b06cedb751430e77">dwc_otg_is_device_mode</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * _core_if);
+<a name="l00061"></a>00061 <span class="keyword">extern</span> uint8_t <a class="code" href="dwc__otg__cil_8c.html#f0bfe5f933e21a94ea06c96ffc086e72">dwc_otg_is_host_mode</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * _core_if);
+<a name="l00062"></a>00062 
+<a name="l00063"></a>00063 <span class="keyword">extern</span> uint8_t <a class="code" href="dwc__otg__cil_8c.html#f4f060a2decd6434bbd96703a4d1fc66">dwc_otg_is_dma_enable</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if);
+<a name="l00064"></a>00064 
+<a name="l00066"></a>00066 <span class="keyword">extern</span> int32_t <a class="code" href="dwc__otg__cil__intr_8c.html#1fad5cb7f68bc87c628bc4cb5db922b8">dwc_otg_handle_common_intr</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * _core_if);
+<a name="l00067"></a>00067 
+<a name="l00078"></a>00078 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#878cc478f43c58991c446bd78f50f8f0">dwc_otg_set_param_otg_cap</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if, int32_t val);
+<a name="l00079"></a>00079 <span class="keyword">extern</span> int32_t <a class="code" href="dwc__otg__cil_8c.html#0896106921e87788480f078c86de274a">dwc_otg_get_param_otg_cap</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if);
+<a name="l00080"></a><a class="code" href="dwc__otg__core__if_8h.html#83c71a480363001711ff07e03834c49f">00080</a> <span class="preprocessor">#define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE 0</span>
+<a name="l00081"></a><a class="code" href="dwc__otg__core__if_8h.html#f398fce430aa9b84d2429bad1f419d3e">00081</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE 1</span>
+<a name="l00082"></a><a class="code" href="dwc__otg__core__if_8h.html#42ff7d87b7b3d3a47cf1749f02ce516c">00082</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE 2</span>
+<a name="l00083"></a><a class="code" href="dwc__otg__core__if_8h.html#64e4ebd3b09e2ed667ab4c1438424e92">00083</a> <span class="preprocessor"></span><span class="preprocessor">#define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE</span>
+<a name="l00084"></a>00084 <span class="preprocessor"></span>
+<a name="l00085"></a>00085 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#d0603b00a0ff87007ded1c06613d6b87">dwc_otg_set_param_opt</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if, int32_t val);
+<a name="l00086"></a>00086 <span class="keyword">extern</span> int32_t <a class="code" href="dwc__otg__cil_8c.html#1b57cc827b21df14faa0eec1cbab1742">dwc_otg_get_param_opt</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if);
+<a name="l00087"></a><a class="code" href="dwc__otg__core__if_8h.html#a38a6bfa4913d2832ec3d7fc5d7b54a1">00087</a> <span class="preprocessor">#define dwc_param_opt_default 1</span>
+<a name="l00088"></a>00088 <span class="preprocessor"></span>
+<a name="l00096"></a>00096 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#b4fbe11281b8200b70202d4e0048a9d7">dwc_otg_set_param_dma_enable</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if,
+<a name="l00097"></a>00097                                         int32_t val);
+<a name="l00098"></a>00098 <span class="keyword">extern</span> int32_t <a class="code" href="dwc__otg__cil_8c.html#0c78da7b7e7b59b31bd99a07d926a298">dwc_otg_get_param_dma_enable</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if);
+<a name="l00099"></a><a class="code" href="dwc__otg__core__if_8h.html#2d5fa78eb125e55111bb7a61c5cc13de">00099</a> <span class="preprocessor">#define dwc_param_dma_enable_default 1</span>
+<a name="l00100"></a>00100 <span class="preprocessor"></span>
+<a name="l00109"></a>00109 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#7eae744525314774d3b390f116db126c">dwc_otg_set_param_dma_desc_enable</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if,
+<a name="l00110"></a>00110                                              int32_t val);
+<a name="l00111"></a>00111 <span class="keyword">extern</span> int32_t <a class="code" href="dwc__otg__cil_8c.html#5cac7b3770cefa9db25bb46193134c5a">dwc_otg_get_param_dma_desc_enable</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if);
+<a name="l00112"></a><a class="code" href="dwc__otg__core__if_8h.html#a3a57c75cfc0c2e2178d8db079c8185e">00112</a> <span class="preprocessor">#define dwc_param_dma_desc_enable_default 1</span>
+<a name="l00113"></a>00113 <span class="preprocessor"></span>
+<a name="l00117"></a>00117 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#920035c6082dcdfec11a20e8535e9fe9">dwc_otg_set_param_dma_burst_size</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if,
+<a name="l00118"></a>00118                                             int32_t val);
+<a name="l00119"></a>00119 <span class="keyword">extern</span> int32_t <a class="code" href="dwc__otg__cil_8c.html#7450ef9275974e46f41f12fdc6da7901">dwc_otg_get_param_dma_burst_size</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if);
+<a name="l00120"></a><a class="code" href="dwc__otg__core__if_8h.html#627cfe039c4f743e12ca8d37f787a6c8">00120</a> <span class="preprocessor">#define dwc_param_dma_burst_size_default 32</span>
+<a name="l00121"></a>00121 <span class="preprocessor"></span>
+<a name="l00130"></a>00130 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#7acd153b5577a3db825fa08d243ae856">dwc_otg_set_param_speed</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if, int32_t val);
+<a name="l00131"></a>00131 <span class="keyword">extern</span> int32_t <a class="code" href="dwc__otg__cil_8c.html#f18994b0fe09d9d3031ef8290945c1ea">dwc_otg_get_param_speed</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if);
+<a name="l00132"></a><a class="code" href="dwc__otg__core__if_8h.html#43d7e266ea8e39002a96578e9ab5e70d">00132</a> <span class="preprocessor">#define dwc_param_speed_default 0</span>
+<a name="l00133"></a><a class="code" href="dwc__otg__core__if_8h.html#43c6bf01342fe06704016619c8d35fa7">00133</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_SPEED_PARAM_HIGH 0</span>
+<a name="l00134"></a><a class="code" href="dwc__otg__core__if_8h.html#353c64bfe6bbc9da8406528ad8220166">00134</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_SPEED_PARAM_FULL 1</span>
+<a name="l00135"></a>00135 <span class="preprocessor"></span>
+<a name="l00141"></a>00141 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#8bd669637630521655c455c03d470e10">dwc_otg_set_param_host_support_fs_ls_low_power</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> *
+<a name="l00142"></a>00142                                                           core_if, int32_t val);
+<a name="l00143"></a>00143 <span class="keyword">extern</span> int32_t <a class="code" href="dwc__otg__cil_8c.html#ce7a69af8ef1970a640d0a23c7c8f12a">dwc_otg_get_param_host_support_fs_ls_low_power</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a>
+<a name="l00144"></a>00144                                                               * core_if);
+<a name="l00145"></a><a class="code" href="dwc__otg__core__if_8h.html#3df14e916b2c9c2172240d6103d0df98">00145</a> <span class="preprocessor">#define dwc_param_host_support_fs_ls_low_power_default 0</span>
+<a name="l00146"></a>00146 <span class="preprocessor"></span>
+<a name="l00155"></a>00155 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#354ce49f65334e829c2694811c4f2016">dwc_otg_set_param_host_ls_low_power_phy_clk</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> *
+<a name="l00156"></a>00156                                                        core_if, int32_t val);
+<a name="l00157"></a>00157 <span class="keyword">extern</span> int32_t <a class="code" href="dwc__otg__cil_8c.html#02ea6a179d92658c4cf4e5b513cb2414">dwc_otg_get_param_host_ls_low_power_phy_clk</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> *
+<a name="l00158"></a>00158                                                            core_if);
+<a name="l00159"></a><a class="code" href="dwc__otg__core__if_8h.html#ff8cfea2259a0d456576ef255b60bbb9">00159</a> <span class="preprocessor">#define dwc_param_host_ls_low_power_phy_clk_default 0</span>
+<a name="l00160"></a><a class="code" href="dwc__otg__core__if_8h.html#3d57c56290d6cd9252eb8ccacb028f46">00160</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0</span>
+<a name="l00161"></a><a class="code" href="dwc__otg__core__if_8h.html#5037c1f130bf6b40970dbf9a498fb918">00161</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1</span>
+<a name="l00162"></a>00162 <span class="preprocessor"></span>
+<a name="l00167"></a>00167 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#61bb728cc80220e5173d5e3126dd4fd1">dwc_otg_set_param_enable_dynamic_fifo</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if,
+<a name="l00168"></a>00168                                                  int32_t val);
+<a name="l00169"></a>00169 <span class="keyword">extern</span> int32_t <a class="code" href="dwc__otg__cil_8c.html#3bc5fc1c94b4bb1a5b5dcca6fa71584e">dwc_otg_get_param_enable_dynamic_fifo</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> *
+<a name="l00170"></a>00170                                                      core_if);
+<a name="l00171"></a><a class="code" href="dwc__otg__core__if_8h.html#8b88b4426126f04a71603df7401b19df">00171</a> <span class="preprocessor">#define dwc_param_enable_dynamic_fifo_default 1</span>
+<a name="l00172"></a>00172 <span class="preprocessor"></span>
+<a name="l00179"></a>00179 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#69d52c46eb236816b20675ecb57975ae">dwc_otg_set_param_data_fifo_size</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if,
+<a name="l00180"></a>00180                                             int32_t val);
+<a name="l00181"></a>00181 <span class="keyword">extern</span> int32_t <a class="code" href="dwc__otg__cil_8c.html#3695ec355114fb8da2f57b7f5c2159b7">dwc_otg_get_param_data_fifo_size</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if);
+<a name="l00182"></a><a class="code" href="dwc__otg__core__if_8h.html#f115dcb7c077b31659173f7f33edefff">00182</a> <span class="preprocessor">#define dwc_param_data_fifo_size_default 8192</span>
+<a name="l00183"></a>00183 <span class="preprocessor"></span>
+<a name="l00188"></a>00188 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#0fa4db196053869ac19832c03c62913f">dwc_otg_set_param_dev_rx_fifo_size</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if,
+<a name="l00189"></a>00189                                               int32_t val);
+<a name="l00190"></a>00190 <span class="keyword">extern</span> int32_t <a class="code" href="dwc__otg__cil_8c.html#56781e1cc653e948147afab10c19b72a">dwc_otg_get_param_dev_rx_fifo_size</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if);
+<a name="l00191"></a><a class="code" href="dwc__otg__core__if_8h.html#cd0a0b07970f53d4cc9c4ec689d6f29d">00191</a> <span class="preprocessor">#define dwc_param_dev_rx_fifo_size_default 1064</span>
+<a name="l00192"></a>00192 <span class="preprocessor"></span>
+<a name="l00197"></a>00197 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#4f7059cecabbf8cfe5014112ba9a3d42">dwc_otg_set_param_dev_nperio_tx_fifo_size</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> *
+<a name="l00198"></a>00198                                                      core_if, int32_t val);
+<a name="l00199"></a>00199 <span class="keyword">extern</span> int32_t <a class="code" href="dwc__otg__cil_8c.html#bb61fc259fe1dc0aee41a3c8b4e99b88">dwc_otg_get_param_dev_nperio_tx_fifo_size</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> *
+<a name="l00200"></a>00200                                                          core_if);
+<a name="l00201"></a><a class="code" href="dwc__otg__core__if_8h.html#d068247cd8a85a6f3e7b12911082c0a1">00201</a> <span class="preprocessor">#define dwc_param_dev_nperio_tx_fifo_size_default 1024</span>
+<a name="l00202"></a>00202 <span class="preprocessor"></span>
+<a name="l00207"></a>00207 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#2119a493582bea4004b5fdeba15f1609">dwc_otg_set_param_dev_perio_tx_fifo_size</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if,
+<a name="l00208"></a>00208                                                     int32_t val, <span class="keywordtype">int</span> fifo_num);
+<a name="l00209"></a>00209 <span class="keyword">extern</span> int32_t <a class="code" href="dwc__otg__cil_8c.html#d9bf0270a9b9617f0d196dd566a1c610">dwc_otg_get_param_dev_perio_tx_fifo_size</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> *
+<a name="l00210"></a>00210                                                         core_if, <span class="keywordtype">int</span> fifo_num);
+<a name="l00211"></a><a class="code" href="dwc__otg__core__if_8h.html#83815074ba10fec73bb108e1c6a739fd">00211</a> <span class="preprocessor">#define dwc_param_dev_perio_tx_fifo_size_default 256</span>
+<a name="l00212"></a>00212 <span class="preprocessor"></span>
+<a name="l00217"></a>00217 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#254c1e97cf22fe34b7383165e30071eb">dwc_otg_set_param_host_rx_fifo_size</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if,
+<a name="l00218"></a>00218                                                int32_t val);
+<a name="l00219"></a>00219 <span class="keyword">extern</span> int32_t <a class="code" href="dwc__otg__cil_8c.html#7b964a905858d04ce43159bbfca20f34">dwc_otg_get_param_host_rx_fifo_size</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if);
+<a name="l00220"></a><a class="code" href="dwc__otg__core__if_8h.html#90093ab1ac67472188e46fe171e7edc1">00220</a> <span class="preprocessor">#define dwc_param_host_rx_fifo_size_default 1024</span>
+<a name="l00221"></a>00221 <span class="preprocessor"></span>
+<a name="l00226"></a>00226 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#a66ca9f9345a13606148b050f8690a56">dwc_otg_set_param_host_nperio_tx_fifo_size</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> *
+<a name="l00227"></a>00227                                                       core_if, int32_t val);
+<a name="l00228"></a>00228 <span class="keyword">extern</span> int32_t <a class="code" href="dwc__otg__cil_8c.html#e53a7fddb0a2689e463cbd9c441ee004">dwc_otg_get_param_host_nperio_tx_fifo_size</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> *
+<a name="l00229"></a>00229                                                           core_if);
+<a name="l00230"></a><a class="code" href="dwc__otg__core__if_8h.html#a0ef15f080c34d1ca47159d6aec1d691">00230</a> <span class="preprocessor">#define dwc_param_host_nperio_tx_fifo_size_default 1024</span>
+<a name="l00231"></a>00231 <span class="preprocessor"></span>
+<a name="l00236"></a>00236 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#e4ce399208d8a85dcb9dedd1fb8cd8ce">dwc_otg_set_param_host_perio_tx_fifo_size</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> *
+<a name="l00237"></a>00237                                                      core_if, int32_t val);
+<a name="l00238"></a>00238 <span class="keyword">extern</span> int32_t <a class="code" href="dwc__otg__cil_8c.html#9b2de0caea0d9ee86258ac4bbe63acd5">dwc_otg_get_param_host_perio_tx_fifo_size</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> *
+<a name="l00239"></a>00239                                                          core_if);
+<a name="l00240"></a><a class="code" href="dwc__otg__core__if_8h.html#b2540fa14f8256322fe99931f5d74025">00240</a> <span class="preprocessor">#define dwc_param_host_perio_tx_fifo_size_default 1024</span>
+<a name="l00241"></a>00241 <span class="preprocessor"></span>
+<a name="l00245"></a>00245 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#2eee676071d6bb4eba53b413e80b045f">dwc_otg_set_param_max_transfer_size</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if,
+<a name="l00246"></a>00246                                                int32_t val);
+<a name="l00247"></a>00247 <span class="keyword">extern</span> int32_t <a class="code" href="dwc__otg__cil_8c.html#307c59e350a8ea67ef5d1c02f79de17b">dwc_otg_get_param_max_transfer_size</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if);
+<a name="l00248"></a><a class="code" href="dwc__otg__core__if_8h.html#dafcc111c37c08300b380509e8b60b84">00248</a> <span class="preprocessor">#define dwc_param_max_transfer_size_default 65535</span>
+<a name="l00249"></a>00249 <span class="preprocessor"></span>
+<a name="l00253"></a>00253 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#a1c52f0740f7d0b72c980b38cc4314d1">dwc_otg_set_param_max_packet_count</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if,
+<a name="l00254"></a>00254                                               int32_t val);
+<a name="l00255"></a>00255 <span class="keyword">extern</span> int32_t <a class="code" href="dwc__otg__cil_8c.html#765e82d04dc91bdc93c129d9ba7c5161">dwc_otg_get_param_max_packet_count</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if);
+<a name="l00256"></a><a class="code" href="dwc__otg__core__if_8h.html#157ed6a26b1bb4b14008edc2e17b5645">00256</a> <span class="preprocessor">#define dwc_param_max_packet_count_default 511</span>
+<a name="l00257"></a>00257 <span class="preprocessor"></span>
+<a name="l00262"></a>00262 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#f802acfc49b3fbb86159036f8f317f76">dwc_otg_set_param_host_channels</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if,
+<a name="l00263"></a>00263                                            int32_t val);
+<a name="l00264"></a>00264 <span class="keyword">extern</span> int32_t <a class="code" href="dwc__otg__cil_8c.html#e1235c11a6a3e8d0e78df59d86d4d287">dwc_otg_get_param_host_channels</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if);
+<a name="l00265"></a><a class="code" href="dwc__otg__core__if_8h.html#84c89a21c7e8319b996bbad29cf486ca">00265</a> <span class="preprocessor">#define dwc_param_host_channels_default 12</span>
+<a name="l00266"></a>00266 <span class="preprocessor"></span>
+<a name="l00273"></a>00273 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#75d3b409824c0ca52631277398ba8367">dwc_otg_set_param_dev_endpoints</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if,
+<a name="l00274"></a>00274                                            int32_t val);
+<a name="l00275"></a>00275 <span class="keyword">extern</span> int32_t <a class="code" href="dwc__otg__cil_8c.html#27447ccef5d5a1c3e5c93ed3b352e152">dwc_otg_get_param_dev_endpoints</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if);
+<a name="l00276"></a><a class="code" href="dwc__otg__core__if_8h.html#6c0b373c7d629c87007fe125fa029aa4">00276</a> <span class="preprocessor">#define dwc_param_dev_endpoints_default 6</span>
+<a name="l00277"></a>00277 <span class="preprocessor"></span>
+<a name="l00286"></a>00286 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#2b7087c85c0ea1520ec2e091b80bf36b">dwc_otg_set_param_phy_type</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if, int32_t val);
+<a name="l00287"></a>00287 <span class="keyword">extern</span> int32_t <a class="code" href="dwc__otg__cil_8c.html#e49dd633ec87aa71335ef6ef312283a3">dwc_otg_get_param_phy_type</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if);
+<a name="l00288"></a><a class="code" href="dwc__otg__core__if_8h.html#f7395410ea596c4c660f61ff41cb38b8">00288</a> <span class="preprocessor">#define DWC_PHY_TYPE_PARAM_FS 0</span>
+<a name="l00289"></a><a class="code" href="dwc__otg__core__if_8h.html#825a1595a3b15dc34adb88984b8b027e">00289</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_PHY_TYPE_PARAM_UTMI 1</span>
+<a name="l00290"></a><a class="code" href="dwc__otg__core__if_8h.html#1951e77698d1cecdac00c786428146bf">00290</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_PHY_TYPE_PARAM_ULPI 2</span>
+<a name="l00291"></a><a class="code" href="dwc__otg__core__if_8h.html#e9ecfde05af7206a4fe15f18d12fc47e">00291</a> <span class="preprocessor"></span><span class="preprocessor">#define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI</span>
+<a name="l00292"></a>00292 <span class="preprocessor"></span>
+<a name="l00304"></a>00304 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#1eacecc96e1ab100cbf129ad6aa5f6c8">dwc_otg_set_param_phy_utmi_width</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if,
+<a name="l00305"></a>00305                                             int32_t val);
+<a name="l00306"></a>00306 <span class="keyword">extern</span> int32_t <a class="code" href="dwc__otg__cil_8c.html#9dfa6a24c38b5ba13c08abe22d532a1d">dwc_otg_get_param_phy_utmi_width</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if);
+<a name="l00307"></a><a class="code" href="dwc__otg__core__if_8h.html#628748b25af7b09c91c9b40a801fd1c2">00307</a> <span class="preprocessor">#define dwc_param_phy_utmi_width_default 16</span>
+<a name="l00308"></a>00308 <span class="preprocessor"></span>
+<a name="l00319"></a>00319 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#5dab15db053bd02c6bc9619e189a6a14">dwc_otg_set_param_phy_ulpi_ddr</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if,
+<a name="l00320"></a>00320                                           int32_t val);
+<a name="l00321"></a>00321 <span class="keyword">extern</span> int32_t <a class="code" href="dwc__otg__cil_8c.html#95655db9d2dce391da40361fe310599c">dwc_otg_get_param_phy_ulpi_ddr</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if);
+<a name="l00322"></a><a class="code" href="dwc__otg__core__if_8h.html#e500bb317e047963e0bff06de78a8835">00322</a> <span class="preprocessor">#define dwc_param_phy_ulpi_ddr_default 0</span>
+<a name="l00323"></a>00323 <span class="preprocessor"></span>
+<a name="l00328"></a>00328 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#a12296bcb04a3b0f6f80037590e97bec">dwc_otg_set_param_phy_ulpi_ext_vbus</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if,
+<a name="l00329"></a>00329                                                int32_t val);
+<a name="l00330"></a>00330 <span class="keyword">extern</span> int32_t <a class="code" href="dwc__otg__cil_8c.html#b0604fadb0b685a106507eacd18e12a6">dwc_otg_get_param_phy_ulpi_ext_vbus</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if);
+<a name="l00331"></a><a class="code" href="dwc__otg__core__if_8h.html#06e120a40de7fe3a8a8c02ec981307c8">00331</a> <span class="preprocessor">#define DWC_PHY_ULPI_INTERNAL_VBUS 0</span>
+<a name="l00332"></a><a class="code" href="dwc__otg__core__if_8h.html#4e318fec85faf7169df368ee4f7b5176">00332</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_PHY_ULPI_EXTERNAL_VBUS 1</span>
+<a name="l00333"></a><a class="code" href="dwc__otg__core__if_8h.html#c1530e5f28eabbaa1d25267a5435de87">00333</a> <span class="preprocessor"></span><span class="preprocessor">#define dwc_param_phy_ulpi_ext_vbus_default DWC_PHY_ULPI_INTERNAL_VBUS</span>
+<a name="l00334"></a>00334 <span class="preprocessor"></span>
+<a name="l00341"></a>00341 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#65d7407ed24c82e158a38ab2a60120c4">dwc_otg_set_param_i2c_enable</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if,
+<a name="l00342"></a>00342                                         int32_t val);
+<a name="l00343"></a>00343 <span class="keyword">extern</span> int32_t <a class="code" href="dwc__otg__cil_8c.html#80cf1905c95391fa1acaa2237182ddf8">dwc_otg_get_param_i2c_enable</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if);
+<a name="l00344"></a><a class="code" href="dwc__otg__core__if_8h.html#5f6376ff90b4206f1411ad3454e32690">00344</a> <span class="preprocessor">#define dwc_param_i2c_enable_default 0</span>
+<a name="l00345"></a>00345 <span class="preprocessor"></span>
+<a name="l00346"></a>00346 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#f235e9c7b844b899d759a073a84f782f">dwc_otg_set_param_ulpi_fs_ls</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if,
+<a name="l00347"></a>00347                                         int32_t val);
+<a name="l00348"></a>00348 <span class="keyword">extern</span> int32_t <a class="code" href="dwc__otg__cil_8c.html#0ee03a3468e74cd2e38da1617b88313b">dwc_otg_get_param_ulpi_fs_ls</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if);
+<a name="l00349"></a><a class="code" href="dwc__otg__core__if_8h.html#7db2560bca75c28869d6fdf302dd3cae">00349</a> <span class="preprocessor">#define dwc_param_ulpi_fs_ls_default 0</span>
+<a name="l00350"></a>00350 <span class="preprocessor"></span>
+<a name="l00351"></a>00351 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#b05c92754c0ebc3d58ea0c090b9659de">dwc_otg_set_param_ts_dline</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if, int32_t val);
+<a name="l00352"></a>00352 <span class="keyword">extern</span> int32_t <a class="code" href="dwc__otg__cil_8c.html#025a93aef8cabae431033cb4fdc7772f">dwc_otg_get_param_ts_dline</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if);
+<a name="l00353"></a><a class="code" href="dwc__otg__core__if_8h.html#f65e86f5f54b329161081f4016162ec0">00353</a> <span class="preprocessor">#define dwc_param_ts_dline_default 0</span>
+<a name="l00354"></a>00354 <span class="preprocessor"></span>
+<a name="l00361"></a>00361 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#2eefd02d72c79200072d54b4eb13e5cd">dwc_otg_set_param_en_multiple_tx_fifo</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if,
+<a name="l00362"></a>00362                                                  int32_t val);
+<a name="l00363"></a>00363 <span class="keyword">extern</span> int32_t <a class="code" href="dwc__otg__cil_8c.html#bc8e0312a565efb2d5117984219b4460">dwc_otg_get_param_en_multiple_tx_fifo</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> *
+<a name="l00364"></a>00364                                                      core_if);
+<a name="l00365"></a><a class="code" href="dwc__otg__core__if_8h.html#ea0a79ef09fcf9078c2c0779e7a36801">00365</a> <span class="preprocessor">#define dwc_param_en_multiple_tx_fifo_default 1</span>
+<a name="l00366"></a>00366 <span class="preprocessor"></span>
+<a name="l00371"></a>00371 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#44bf6b41f0892f480ea6c03a2ac1e73f">dwc_otg_set_param_dev_tx_fifo_size</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if,
+<a name="l00372"></a>00372                                               <span class="keywordtype">int</span> fifo_num, int32_t val);
+<a name="l00373"></a>00373 <span class="keyword">extern</span> int32_t <a class="code" href="dwc__otg__cil_8c.html#99a491c648b6066077426c9cdc374aa8">dwc_otg_get_param_dev_tx_fifo_size</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if,
+<a name="l00374"></a>00374                                                   <span class="keywordtype">int</span> fifo_num);
+<a name="l00375"></a><a class="code" href="dwc__otg__core__if_8h.html#a6ad2334d1d977070a24e671db3b8f3a">00375</a> <span class="preprocessor">#define dwc_param_dev_tx_fifo_size_default 256</span>
+<a name="l00376"></a>00376 <span class="preprocessor"></span>
+<a name="l00382"></a>00382 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#6095d6a93f901f32522d4b950c99a8e1">dwc_otg_set_param_thr_ctl</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if, int32_t val);
+<a name="l00383"></a>00383 <span class="keyword">extern</span> int32_t dwc_otg_get_thr_ctl(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if, <span class="keywordtype">int</span> fifo_num);
+<a name="l00384"></a><a class="code" href="dwc__otg__core__if_8h.html#11b1ee2892d3645ce27d46d2198dc241">00384</a> <span class="preprocessor">#define dwc_param_thr_ctl_default 0</span>
+<a name="l00385"></a>00385 <span class="preprocessor"></span>
+<a name="l00389"></a>00389 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#1ed19fed8939a352f91fe1403574135e">dwc_otg_set_param_tx_thr_length</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if,
+<a name="l00390"></a>00390                                            int32_t val);
+<a name="l00391"></a>00391 <span class="keyword">extern</span> int32_t dwc_otg_get_tx_thr_length(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if);
+<a name="l00392"></a><a class="code" href="dwc__otg__core__if_8h.html#35f8a2bd23274ef01afe6b7471603c5c">00392</a> <span class="preprocessor">#define dwc_param_tx_thr_length_default 64</span>
+<a name="l00393"></a>00393 <span class="preprocessor"></span>
+<a name="l00397"></a>00397 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#20d005470a65927cb243b37619f6c6bf">dwc_otg_set_param_rx_thr_length</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if,
+<a name="l00398"></a>00398                                            int32_t val);
+<a name="l00399"></a>00399 <span class="keyword">extern</span> int32_t dwc_otg_get_rx_thr_length(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if);
+<a name="l00400"></a><a class="code" href="dwc__otg__core__if_8h.html#5ef7eee81a06fcee9a038264fcf79626">00400</a> <span class="preprocessor">#define dwc_param_rx_thr_length_default 64</span>
+<a name="l00401"></a>00401 <span class="preprocessor"></span>
+<a name="l00405"></a>00405 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#e3a62b66e19a302a55046830f5eecf0c">dwc_otg_set_param_lpm_enable</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if,
+<a name="l00406"></a>00406                                         int32_t val);
+<a name="l00407"></a>00407 <span class="keyword">extern</span> int32_t <a class="code" href="dwc__otg__cil_8c.html#0e0eb29733595730396da3ddf3d0ded5">dwc_otg_get_param_lpm_enable</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if);
+<a name="l00408"></a><a class="code" href="dwc__otg__core__if_8h.html#12ae395ada45a106bdc4e6ff3006ffd7">00408</a> <span class="preprocessor">#define dwc_param_lpm_enable_default 1</span>
+<a name="l00409"></a>00409 <span class="preprocessor"></span>
+<a name="l00413"></a>00413 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#63c0b4bfcf3b1c6c90c5572258439e1f">dwc_otg_set_param_pti_enable</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if,
+<a name="l00414"></a>00414                                         int32_t val);
+<a name="l00415"></a>00415 <span class="keyword">extern</span> int32_t <a class="code" href="dwc__otg__cil_8c.html#9d729a393133a8111b68d4b5ec9fdd30">dwc_otg_get_param_pti_enable</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if);
+<a name="l00416"></a><a class="code" href="dwc__otg__core__if_8h.html#9dc50d52206e9c2bf9b3cf184fa9a912">00416</a> <span class="preprocessor">#define dwc_param_pti_enable_default 0</span>
+<a name="l00417"></a>00417 <span class="preprocessor"></span>
+<a name="l00421"></a>00421 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#7ba10fdfd2ce9f3ef4b0a2bef555a7c1">dwc_otg_set_param_mpi_enable</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if,
+<a name="l00422"></a>00422                                         int32_t val);
+<a name="l00423"></a>00423 <span class="keyword">extern</span> int32_t <a class="code" href="dwc__otg__cil_8c.html#7b9e3bced8a43e810fca322e36946f31">dwc_otg_get_param_mpi_enable</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if);
+<a name="l00424"></a><a class="code" href="dwc__otg__core__if_8h.html#891784dcf9e045a78c14fe75c0bb0c31">00424</a> <span class="preprocessor">#define dwc_param_mpi_enable_default 0</span>
+<a name="l00425"></a>00425 <span class="preprocessor"></span>
+<a name="l00429"></a>00429 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#93036faefc8179eef11c8ca0b18993a8">dwc_otg_set_param_ic_usb_cap</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if,
+<a name="l00430"></a>00430                                         int32_t val);
+<a name="l00431"></a>00431 <span class="keyword">extern</span> int32_t <a class="code" href="dwc__otg__cil_8c.html#1ccaddc86262ff99dad6c1e44f5ff965">dwc_otg_get_param_ic_usb_cap</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if);
+<a name="l00432"></a><a class="code" href="dwc__otg__core__if_8h.html#00e03f82db17880c007a150623471327">00432</a> <span class="preprocessor">#define dwc_param_ic_usb_cap_default 0</span>
+<a name="l00433"></a>00433 <span class="preprocessor"></span>
+<a name="l00434"></a>00434 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil_8c.html#9bf87dcaa6dcea51eb3d8c30439a2138">dwc_otg_set_param_ahb_thr_ratio</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if, int32_t val);
+<a name="l00435"></a>00435 <span class="keyword">extern</span> int32_t <a class="code" href="dwc__otg__cil_8c.html#275fab9bf16bd3cb148901c578fbcbd0">dwc_otg_get_param_ahb_thr_ratio</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if);
+<a name="l00436"></a><a class="code" href="dwc__otg__core__if_8h.html#5a5f06f045acf28eca0992898545ae03">00436</a> <span class="preprocessor">#define dwc_param_ahb_thr_ratio_default 0</span>
+<a name="l00437"></a>00437 <span class="preprocessor"></span>
+<a name="l00445"></a>00445 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#ea3bce6af9d0bd9b2fb6de94f1c7a133">dwc_otg_dump_dev_registers</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * _core_if);
+<a name="l00446"></a>00446 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#393e65ddcbaed38935ea06fb7451167b">dwc_otg_dump_spram</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * _core_if);
+<a name="l00447"></a>00447 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#e85d3d04799b17226fcb00ea2074ca63">dwc_otg_dump_host_registers</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * _core_if);
+<a name="l00448"></a>00448 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#118ecda931e2b745f76fde129ff707c2">dwc_otg_dump_global_registers</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * _core_if);
+<a name="l00449"></a>00449 
+<a name="l00453"></a>00453 <span class="keyword">extern</span> uint32_t <a class="code" href="dwc__otg__cil_8c.html#df391379aafa69a8683bb1f88c413675">dwc_otg_get_hnpstatus</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if);
+<a name="l00454"></a>00454 
+<a name="l00458"></a>00458 <span class="keyword">extern</span> uint32_t <a class="code" href="dwc__otg__cil_8c.html#b13eac2758aace478587df0f043e80f8">dwc_otg_get_srpstatus</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if);
+<a name="l00459"></a>00459 
+<a name="l00463"></a>00463 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#5cab27b65ed5a6a1e31c0e4df1650f0e">dwc_otg_set_hnpreq</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if, uint32_t val);
+<a name="l00464"></a>00464 
+<a name="l00468"></a>00468 <span class="keyword">extern</span> uint32_t <a class="code" href="dwc__otg__cil_8c.html#c505c47a08029706f60ab8f3d67b70d3">dwc_otg_get_gsnpsid</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if);
+<a name="l00469"></a>00469 
+<a name="l00474"></a>00474 <span class="keyword">extern</span> uint32_t <a class="code" href="dwc__otg__cil_8c.html#788149caf9d915abbe5e289793684b1e">dwc_otg_get_mode</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if);
+<a name="l00475"></a>00475 
+<a name="l00479"></a>00479 <span class="keyword">extern</span> uint32_t <a class="code" href="dwc__otg__cil_8c.html#d222e3bdaba5ea8fa0df22ff9cee2f5e">dwc_otg_get_hnpcapable</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if);
+<a name="l00483"></a>00483 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#b9ab6ff4d50ea35738853f831f480c3e">dwc_otg_set_hnpcapable</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if, uint32_t val);
+<a name="l00484"></a>00484 
+<a name="l00488"></a>00488 <span class="keyword">extern</span> uint32_t <a class="code" href="dwc__otg__cil_8c.html#2bba47b0255cfbc9b19661e9ddd2f497">dwc_otg_get_srpcapable</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if);
+<a name="l00492"></a>00492 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#e75a4faa49ac70c19e9bc8a039d6e37f">dwc_otg_set_srpcapable</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if, uint32_t val);
+<a name="l00493"></a>00493 
+<a name="l00497"></a>00497 <span class="keyword">extern</span> uint32_t <a class="code" href="dwc__otg__cil_8c.html#d69afedd204a41974de582224479569e">dwc_otg_get_devspeed</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if);
+<a name="l00501"></a>00501 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#ead8dea166cbefca04dc5c543c96fba0">dwc_otg_set_devspeed</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if, uint32_t val);
+<a name="l00502"></a>00502 
+<a name="l00506"></a>00506 <span class="keyword">extern</span> uint32_t <a class="code" href="dwc__otg__cil_8c.html#07354b164566c5c1c34446d5b0c4036f">dwc_otg_get_busconnected</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if);
+<a name="l00507"></a>00507 
+<a name="l00511"></a>00511 <span class="keyword">extern</span> uint32_t <a class="code" href="dwc__otg__cil_8c.html#520bf6b5f5ec69e5dcbdad6254c3cede">dwc_otg_get_enumspeed</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if);
+<a name="l00512"></a>00512 
+<a name="l00516"></a>00516 <span class="keyword">extern</span> uint32_t <a class="code" href="dwc__otg__cil_8c.html#83a11dae1c9563aee56baea469cd6064">dwc_otg_get_prtpower</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if);
+<a name="l00520"></a>00520 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#63c880f915b4705a5c118b276e6e9567">dwc_otg_set_prtpower</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if, uint32_t val);
+<a name="l00521"></a>00521 
+<a name="l00525"></a>00525 <span class="keyword">extern</span> uint32_t <a class="code" href="dwc__otg__cil_8c.html#65b0861f7d5d604fb97e599adac62642">dwc_otg_get_prtsuspend</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if);
+<a name="l00529"></a>00529 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#c072cef5b7d3c5566ad3be010c6d49ed">dwc_otg_set_prtsuspend</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if, uint32_t val);
+<a name="l00530"></a>00530 
+<a name="l00535"></a>00535 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#b6d6b18934ba5cd4ce2cf9e68be338f5">dwc_otg_set_prtresume</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if, uint32_t val);
+<a name="l00536"></a>00536 
+<a name="l00540"></a>00540 <span class="keyword">extern</span> uint32_t <a class="code" href="dwc__otg__cil_8c.html#285696198299e317222544aa912b2c35">dwc_otg_get_remotewakesig</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if);
+<a name="l00541"></a>00541 
+<a name="l00545"></a>00545 <span class="keyword">extern</span> uint32_t <a class="code" href="dwc__otg__cil_8c.html#87d643973839554bac437d283a462e00">dwc_otg_get_lpm_portsleepstatus</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if);
+<a name="l00546"></a>00546 
+<a name="l00550"></a>00550 <span class="keyword">extern</span> uint32_t <a class="code" href="dwc__otg__cil_8c.html#91d2a6b57c7216fd5c6dc981a5f0e1ae">dwc_otg_get_lpm_remotewakeenabled</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if);
+<a name="l00551"></a>00551 
+<a name="l00555"></a>00555 <span class="keyword">extern</span> uint32_t <a class="code" href="dwc__otg__cil_8c.html#86d921a91b7e2b143a305283282ce36d">dwc_otg_get_lpmresponse</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if);
+<a name="l00559"></a>00559 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#b19565bc2a8dbb258c3c2cb8c52240b8">dwc_otg_set_lpmresponse</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if, uint32_t val);
+<a name="l00560"></a>00560 
+<a name="l00564"></a>00564 <span class="keyword">extern</span> uint32_t <a class="code" href="dwc__otg__cil_8c.html#0fb8a2b51041b2f5476abc8ffbcc46cb">dwc_otg_get_hsic_connect</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if);
+<a name="l00568"></a>00568 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#6625bea93daab21b2a97004f743203f9">dwc_otg_set_hsic_connect</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if, uint32_t val);
+<a name="l00569"></a>00569 
+<a name="l00573"></a>00573 <span class="keyword">extern</span> uint32_t <a class="code" href="dwc__otg__cil_8c.html#a3399019a62013ccc6ce213e8f241d7a">dwc_otg_get_inv_sel_hsic</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if);
+<a name="l00577"></a>00577 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#ef8b7bbc803e779480aa06779a44e4f0">dwc_otg_set_inv_sel_hsic</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if, uint32_t val);
+<a name="l00578"></a>00578 
+<a name="l00579"></a>00579 <span class="comment">/*</span>
+<a name="l00580"></a>00580 <span class="comment"> * Some functions for accessing registers</span>
+<a name="l00581"></a>00581 <span class="comment"> */</span>
+<a name="l00582"></a>00582 
+<a name="l00586"></a>00586 <span class="keyword">extern</span> uint32_t <a class="code" href="dwc__otg__cil_8c.html#a450da19279ae7246c89ede2949189fe">dwc_otg_get_gotgctl</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if);
+<a name="l00587"></a>00587 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#be44aee1ee301bdcbf7174cc1c729032">dwc_otg_set_gotgctl</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if, uint32_t val);
+<a name="l00588"></a>00588 
+<a name="l00592"></a>00592 <span class="keyword">extern</span> uint32_t <a class="code" href="dwc__otg__cil_8c.html#eb5b1512f29fa951f2875dc52d368085">dwc_otg_get_gusbcfg</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if);
+<a name="l00593"></a>00593 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#74d5e1045c70fd5efc35a39ca4311baa">dwc_otg_set_gusbcfg</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if, uint32_t val);
+<a name="l00594"></a>00594 
+<a name="l00598"></a>00598 <span class="keyword">extern</span> uint32_t <a class="code" href="dwc__otg__cil_8c.html#ce6ba769b9c0abd15c8f0b118d74c8e4">dwc_otg_get_grxfsiz</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if);
+<a name="l00599"></a>00599 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#3e251d5b9273ae2e2b3f5714694974a5">dwc_otg_set_grxfsiz</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if, uint32_t val);
+<a name="l00600"></a>00600 
+<a name="l00604"></a>00604 <span class="keyword">extern</span> uint32_t <a class="code" href="dwc__otg__cil_8c.html#3110e552598b04bbe6b30bcddadda98b">dwc_otg_get_gnptxfsiz</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if);
+<a name="l00605"></a>00605 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#48c625d569671523aac60af8e2d60d7a">dwc_otg_set_gnptxfsiz</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if, uint32_t val);
+<a name="l00606"></a>00606 
+<a name="l00607"></a>00607 <span class="keyword">extern</span> uint32_t <a class="code" href="dwc__otg__cil_8c.html#c8fcf302be26cad07b9ba36082e0ed5c">dwc_otg_get_gpvndctl</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if);
+<a name="l00608"></a>00608 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#4c700540a6c1061eb2491c78670bb26f">dwc_otg_set_gpvndctl</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if, uint32_t val);
+<a name="l00609"></a>00609 
+<a name="l00613"></a>00613 <span class="keyword">extern</span> uint32_t <a class="code" href="dwc__otg__cil_8c.html#5b3367179e8c0c6ccb5041db26f8e0cc">dwc_otg_get_ggpio</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if);
+<a name="l00614"></a>00614 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#4b6bd4ddf333b856631cd561eb747882">dwc_otg_set_ggpio</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if, uint32_t val);
+<a name="l00615"></a>00615 
+<a name="l00619"></a>00619 <span class="keyword">extern</span> uint32_t <a class="code" href="dwc__otg__cil_8c.html#c308abdec734a3d2f183d2085271d285">dwc_otg_get_guid</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if);
+<a name="l00620"></a>00620 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#edf22163b21a9ab3539976e19338f1e9">dwc_otg_set_guid</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if, uint32_t val);
+<a name="l00621"></a>00621 
+<a name="l00625"></a>00625 <span class="keyword">extern</span> uint32_t <a class="code" href="dwc__otg__cil_8c.html#6345490821a039a5eff6ec8e5c0e8c0b">dwc_otg_get_hprt0</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if);
+<a name="l00626"></a>00626 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8c.html#c2ec55794abeeb14f5b4d00613122bb7">dwc_otg_set_hprt0</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if, uint32_t val);
+<a name="l00627"></a>00627 
+<a name="l00631"></a>00631 <span class="keyword">extern</span> uint32_t <a class="code" href="dwc__otg__cil_8c.html#6180fa187cfbeef487a71fb4f72a6381">dwc_otg_get_hptxfsiz</a>(<a class="code" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a> * core_if);
+<a name="l00632"></a>00632 
+<a name="l00635"></a>00635 <span class="preprocessor">#endif                          </span><span class="comment">/* __DWC_CORE_IF_H__ */</span>
+</pre></div><hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/dwc__otg__core__if_8h.html b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__core__if_8h.html
new file mode 100644
index 000000000000..2aef00fc08be
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__core__if_8h.html
@@ -0,0 +1,1730 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_core_if.h File Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<h1>dwc_otg_core_if.h File Reference</h1>This file defines DWC_OTG Core API. <a href="#_details">More...</a>
+<p>
+<code>#include &quot;dwc_os.h&quot;</code><br>
+
+<p>
+<a href="dwc__otg__core__if_8h-source.html">Go to the source code of this file.</a><table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>OTG Core Parameters</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="83c71a480363001711ff07e03834c49f"></a><!-- doxytag: member="dwc_otg_core_if.h::DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE" ref="83c71a480363001711ff07e03834c49f" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#83c71a480363001711ff07e03834c49f">DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE</a>&nbsp;&nbsp;&nbsp;0</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f398fce430aa9b84d2429bad1f419d3e"></a><!-- doxytag: member="dwc_otg_core_if.h::DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE" ref="f398fce430aa9b84d2429bad1f419d3e" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#f398fce430aa9b84d2429bad1f419d3e">DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE</a>&nbsp;&nbsp;&nbsp;1</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="42ff7d87b7b3d3a47cf1749f02ce516c"></a><!-- doxytag: member="dwc_otg_core_if.h::DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE" ref="42ff7d87b7b3d3a47cf1749f02ce516c" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#42ff7d87b7b3d3a47cf1749f02ce516c">DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE</a>&nbsp;&nbsp;&nbsp;2</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="64e4ebd3b09e2ed667ab4c1438424e92"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_param_otg_cap_default" ref="64e4ebd3b09e2ed667ab4c1438424e92" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#64e4ebd3b09e2ed667ab4c1438424e92">dwc_param_otg_cap_default</a>&nbsp;&nbsp;&nbsp;DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="a38a6bfa4913d2832ec3d7fc5d7b54a1"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_param_opt_default" ref="a38a6bfa4913d2832ec3d7fc5d7b54a1" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#a38a6bfa4913d2832ec3d7fc5d7b54a1">dwc_param_opt_default</a>&nbsp;&nbsp;&nbsp;1</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="2d5fa78eb125e55111bb7a61c5cc13de"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_param_dma_enable_default" ref="2d5fa78eb125e55111bb7a61c5cc13de" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#2d5fa78eb125e55111bb7a61c5cc13de">dwc_param_dma_enable_default</a>&nbsp;&nbsp;&nbsp;1</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="a3a57c75cfc0c2e2178d8db079c8185e"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_param_dma_desc_enable_default" ref="a3a57c75cfc0c2e2178d8db079c8185e" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#a3a57c75cfc0c2e2178d8db079c8185e">dwc_param_dma_desc_enable_default</a>&nbsp;&nbsp;&nbsp;1</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="627cfe039c4f743e12ca8d37f787a6c8"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_param_dma_burst_size_default" ref="627cfe039c4f743e12ca8d37f787a6c8" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#627cfe039c4f743e12ca8d37f787a6c8">dwc_param_dma_burst_size_default</a>&nbsp;&nbsp;&nbsp;32</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="43d7e266ea8e39002a96578e9ab5e70d"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_param_speed_default" ref="43d7e266ea8e39002a96578e9ab5e70d" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#43d7e266ea8e39002a96578e9ab5e70d">dwc_param_speed_default</a>&nbsp;&nbsp;&nbsp;0</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="43c6bf01342fe06704016619c8d35fa7"></a><!-- doxytag: member="dwc_otg_core_if.h::DWC_SPEED_PARAM_HIGH" ref="43c6bf01342fe06704016619c8d35fa7" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#43c6bf01342fe06704016619c8d35fa7">DWC_SPEED_PARAM_HIGH</a>&nbsp;&nbsp;&nbsp;0</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="353c64bfe6bbc9da8406528ad8220166"></a><!-- doxytag: member="dwc_otg_core_if.h::DWC_SPEED_PARAM_FULL" ref="353c64bfe6bbc9da8406528ad8220166" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#353c64bfe6bbc9da8406528ad8220166">DWC_SPEED_PARAM_FULL</a>&nbsp;&nbsp;&nbsp;1</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3df14e916b2c9c2172240d6103d0df98"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_param_host_support_fs_ls_low_power_default" ref="3df14e916b2c9c2172240d6103d0df98" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#3df14e916b2c9c2172240d6103d0df98">dwc_param_host_support_fs_ls_low_power_default</a>&nbsp;&nbsp;&nbsp;0</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ff8cfea2259a0d456576ef255b60bbb9"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_param_host_ls_low_power_phy_clk_default" ref="ff8cfea2259a0d456576ef255b60bbb9" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#ff8cfea2259a0d456576ef255b60bbb9">dwc_param_host_ls_low_power_phy_clk_default</a>&nbsp;&nbsp;&nbsp;0</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3d57c56290d6cd9252eb8ccacb028f46"></a><!-- doxytag: member="dwc_otg_core_if.h::DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ" ref="3d57c56290d6cd9252eb8ccacb028f46" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#3d57c56290d6cd9252eb8ccacb028f46">DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ</a>&nbsp;&nbsp;&nbsp;0</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="5037c1f130bf6b40970dbf9a498fb918"></a><!-- doxytag: member="dwc_otg_core_if.h::DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ" ref="5037c1f130bf6b40970dbf9a498fb918" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#5037c1f130bf6b40970dbf9a498fb918">DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ</a>&nbsp;&nbsp;&nbsp;1</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="8b88b4426126f04a71603df7401b19df"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_param_enable_dynamic_fifo_default" ref="8b88b4426126f04a71603df7401b19df" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#8b88b4426126f04a71603df7401b19df">dwc_param_enable_dynamic_fifo_default</a>&nbsp;&nbsp;&nbsp;1</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f115dcb7c077b31659173f7f33edefff"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_param_data_fifo_size_default" ref="f115dcb7c077b31659173f7f33edefff" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#f115dcb7c077b31659173f7f33edefff">dwc_param_data_fifo_size_default</a>&nbsp;&nbsp;&nbsp;8192</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="cd0a0b07970f53d4cc9c4ec689d6f29d"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_param_dev_rx_fifo_size_default" ref="cd0a0b07970f53d4cc9c4ec689d6f29d" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#cd0a0b07970f53d4cc9c4ec689d6f29d">dwc_param_dev_rx_fifo_size_default</a>&nbsp;&nbsp;&nbsp;1064</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="d068247cd8a85a6f3e7b12911082c0a1"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_param_dev_nperio_tx_fifo_size_default" ref="d068247cd8a85a6f3e7b12911082c0a1" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#d068247cd8a85a6f3e7b12911082c0a1">dwc_param_dev_nperio_tx_fifo_size_default</a>&nbsp;&nbsp;&nbsp;1024</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="83815074ba10fec73bb108e1c6a739fd"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_param_dev_perio_tx_fifo_size_default" ref="83815074ba10fec73bb108e1c6a739fd" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#83815074ba10fec73bb108e1c6a739fd">dwc_param_dev_perio_tx_fifo_size_default</a>&nbsp;&nbsp;&nbsp;256</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="90093ab1ac67472188e46fe171e7edc1"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_param_host_rx_fifo_size_default" ref="90093ab1ac67472188e46fe171e7edc1" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#90093ab1ac67472188e46fe171e7edc1">dwc_param_host_rx_fifo_size_default</a>&nbsp;&nbsp;&nbsp;1024</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="a0ef15f080c34d1ca47159d6aec1d691"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_param_host_nperio_tx_fifo_size_default" ref="a0ef15f080c34d1ca47159d6aec1d691" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#a0ef15f080c34d1ca47159d6aec1d691">dwc_param_host_nperio_tx_fifo_size_default</a>&nbsp;&nbsp;&nbsp;1024</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b2540fa14f8256322fe99931f5d74025"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_param_host_perio_tx_fifo_size_default" ref="b2540fa14f8256322fe99931f5d74025" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#b2540fa14f8256322fe99931f5d74025">dwc_param_host_perio_tx_fifo_size_default</a>&nbsp;&nbsp;&nbsp;1024</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="dafcc111c37c08300b380509e8b60b84"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_param_max_transfer_size_default" ref="dafcc111c37c08300b380509e8b60b84" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#dafcc111c37c08300b380509e8b60b84">dwc_param_max_transfer_size_default</a>&nbsp;&nbsp;&nbsp;65535</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="157ed6a26b1bb4b14008edc2e17b5645"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_param_max_packet_count_default" ref="157ed6a26b1bb4b14008edc2e17b5645" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#157ed6a26b1bb4b14008edc2e17b5645">dwc_param_max_packet_count_default</a>&nbsp;&nbsp;&nbsp;511</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="84c89a21c7e8319b996bbad29cf486ca"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_param_host_channels_default" ref="84c89a21c7e8319b996bbad29cf486ca" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#84c89a21c7e8319b996bbad29cf486ca">dwc_param_host_channels_default</a>&nbsp;&nbsp;&nbsp;12</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="6c0b373c7d629c87007fe125fa029aa4"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_param_dev_endpoints_default" ref="6c0b373c7d629c87007fe125fa029aa4" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#6c0b373c7d629c87007fe125fa029aa4">dwc_param_dev_endpoints_default</a>&nbsp;&nbsp;&nbsp;6</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f7395410ea596c4c660f61ff41cb38b8"></a><!-- doxytag: member="dwc_otg_core_if.h::DWC_PHY_TYPE_PARAM_FS" ref="f7395410ea596c4c660f61ff41cb38b8" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#f7395410ea596c4c660f61ff41cb38b8">DWC_PHY_TYPE_PARAM_FS</a>&nbsp;&nbsp;&nbsp;0</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="825a1595a3b15dc34adb88984b8b027e"></a><!-- doxytag: member="dwc_otg_core_if.h::DWC_PHY_TYPE_PARAM_UTMI" ref="825a1595a3b15dc34adb88984b8b027e" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#825a1595a3b15dc34adb88984b8b027e">DWC_PHY_TYPE_PARAM_UTMI</a>&nbsp;&nbsp;&nbsp;1</td></tr>
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+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="1951e77698d1cecdac00c786428146bf"></a><!-- doxytag: member="dwc_otg_core_if.h::DWC_PHY_TYPE_PARAM_ULPI" ref="1951e77698d1cecdac00c786428146bf" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#1951e77698d1cecdac00c786428146bf">DWC_PHY_TYPE_PARAM_ULPI</a>&nbsp;&nbsp;&nbsp;2</td></tr>
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+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e9ecfde05af7206a4fe15f18d12fc47e"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_param_phy_type_default" ref="e9ecfde05af7206a4fe15f18d12fc47e" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#e9ecfde05af7206a4fe15f18d12fc47e">dwc_param_phy_type_default</a>&nbsp;&nbsp;&nbsp;DWC_PHY_TYPE_PARAM_UTMI</td></tr>
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+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="628748b25af7b09c91c9b40a801fd1c2"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_param_phy_utmi_width_default" ref="628748b25af7b09c91c9b40a801fd1c2" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#628748b25af7b09c91c9b40a801fd1c2">dwc_param_phy_utmi_width_default</a>&nbsp;&nbsp;&nbsp;16</td></tr>
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+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e500bb317e047963e0bff06de78a8835"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_param_phy_ulpi_ddr_default" ref="e500bb317e047963e0bff06de78a8835" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#e500bb317e047963e0bff06de78a8835">dwc_param_phy_ulpi_ddr_default</a>&nbsp;&nbsp;&nbsp;0</td></tr>
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+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="06e120a40de7fe3a8a8c02ec981307c8"></a><!-- doxytag: member="dwc_otg_core_if.h::DWC_PHY_ULPI_INTERNAL_VBUS" ref="06e120a40de7fe3a8a8c02ec981307c8" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#06e120a40de7fe3a8a8c02ec981307c8">DWC_PHY_ULPI_INTERNAL_VBUS</a>&nbsp;&nbsp;&nbsp;0</td></tr>
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+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="4e318fec85faf7169df368ee4f7b5176"></a><!-- doxytag: member="dwc_otg_core_if.h::DWC_PHY_ULPI_EXTERNAL_VBUS" ref="4e318fec85faf7169df368ee4f7b5176" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#4e318fec85faf7169df368ee4f7b5176">DWC_PHY_ULPI_EXTERNAL_VBUS</a>&nbsp;&nbsp;&nbsp;1</td></tr>
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+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c1530e5f28eabbaa1d25267a5435de87"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_param_phy_ulpi_ext_vbus_default" ref="c1530e5f28eabbaa1d25267a5435de87" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#c1530e5f28eabbaa1d25267a5435de87">dwc_param_phy_ulpi_ext_vbus_default</a>&nbsp;&nbsp;&nbsp;DWC_PHY_ULPI_INTERNAL_VBUS</td></tr>
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+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="5f6376ff90b4206f1411ad3454e32690"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_param_i2c_enable_default" ref="5f6376ff90b4206f1411ad3454e32690" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#5f6376ff90b4206f1411ad3454e32690">dwc_param_i2c_enable_default</a>&nbsp;&nbsp;&nbsp;0</td></tr>
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+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7db2560bca75c28869d6fdf302dd3cae"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_param_ulpi_fs_ls_default" ref="7db2560bca75c28869d6fdf302dd3cae" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#7db2560bca75c28869d6fdf302dd3cae">dwc_param_ulpi_fs_ls_default</a>&nbsp;&nbsp;&nbsp;0</td></tr>
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+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#f65e86f5f54b329161081f4016162ec0">dwc_param_ts_dline_default</a>&nbsp;&nbsp;&nbsp;0</td></tr>
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+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ea0a79ef09fcf9078c2c0779e7a36801"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_param_en_multiple_tx_fifo_default" ref="ea0a79ef09fcf9078c2c0779e7a36801" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#ea0a79ef09fcf9078c2c0779e7a36801">dwc_param_en_multiple_tx_fifo_default</a>&nbsp;&nbsp;&nbsp;1</td></tr>
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+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="a6ad2334d1d977070a24e671db3b8f3a"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_param_dev_tx_fifo_size_default" ref="a6ad2334d1d977070a24e671db3b8f3a" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#a6ad2334d1d977070a24e671db3b8f3a">dwc_param_dev_tx_fifo_size_default</a>&nbsp;&nbsp;&nbsp;256</td></tr>
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+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="11b1ee2892d3645ce27d46d2198dc241"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_param_thr_ctl_default" ref="11b1ee2892d3645ce27d46d2198dc241" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#11b1ee2892d3645ce27d46d2198dc241">dwc_param_thr_ctl_default</a>&nbsp;&nbsp;&nbsp;0</td></tr>
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+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="35f8a2bd23274ef01afe6b7471603c5c"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_param_tx_thr_length_default" ref="35f8a2bd23274ef01afe6b7471603c5c" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#35f8a2bd23274ef01afe6b7471603c5c">dwc_param_tx_thr_length_default</a>&nbsp;&nbsp;&nbsp;64</td></tr>
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+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="5ef7eee81a06fcee9a038264fcf79626"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_param_rx_thr_length_default" ref="5ef7eee81a06fcee9a038264fcf79626" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#5ef7eee81a06fcee9a038264fcf79626">dwc_param_rx_thr_length_default</a>&nbsp;&nbsp;&nbsp;64</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="12ae395ada45a106bdc4e6ff3006ffd7"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_param_lpm_enable_default" ref="12ae395ada45a106bdc4e6ff3006ffd7" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#12ae395ada45a106bdc4e6ff3006ffd7">dwc_param_lpm_enable_default</a>&nbsp;&nbsp;&nbsp;1</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="9dc50d52206e9c2bf9b3cf184fa9a912"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_param_pti_enable_default" ref="9dc50d52206e9c2bf9b3cf184fa9a912" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#9dc50d52206e9c2bf9b3cf184fa9a912">dwc_param_pti_enable_default</a>&nbsp;&nbsp;&nbsp;0</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="891784dcf9e045a78c14fe75c0bb0c31"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_param_mpi_enable_default" ref="891784dcf9e045a78c14fe75c0bb0c31" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#891784dcf9e045a78c14fe75c0bb0c31">dwc_param_mpi_enable_default</a>&nbsp;&nbsp;&nbsp;0</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="00e03f82db17880c007a150623471327"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_param_ic_usb_cap_default" ref="00e03f82db17880c007a150623471327" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#00e03f82db17880c007a150623471327">dwc_param_ic_usb_cap_default</a>&nbsp;&nbsp;&nbsp;0</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="5a5f06f045acf28eca0992898545ae03"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_param_ahb_thr_ratio_default" ref="5a5f06f045acf28eca0992898545ae03" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#5a5f06f045acf28eca0992898545ae03">dwc_param_ahb_thr_ratio_default</a>&nbsp;&nbsp;&nbsp;0</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#878cc478f43c58991c446bd78f50f8f0">dwc_otg_set_param_otg_cap</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Specifies the OTG capabilities.  <a href="#878cc478f43c58991c446bd78f50f8f0"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="0896106921e87788480f078c86de274a"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_param_otg_cap" ref="0896106921e87788480f078c86de274a" args="(dwc_otg_core_if_t *core_if)" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#0896106921e87788480f078c86de274a">dwc_otg_get_param_otg_cap</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="d0603b00a0ff87007ded1c06613d6b87"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_set_param_opt" ref="d0603b00a0ff87007ded1c06613d6b87" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#d0603b00a0ff87007ded1c06613d6b87">dwc_otg_set_param_opt</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="1b57cc827b21df14faa0eec1cbab1742"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_param_opt" ref="1b57cc827b21df14faa0eec1cbab1742" args="(dwc_otg_core_if_t *core_if)" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#1b57cc827b21df14faa0eec1cbab1742">dwc_otg_get_param_opt</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#b4fbe11281b8200b70202d4e0048a9d7">dwc_otg_set_param_dma_enable</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Specifies whether to use slave or DMA mode for accessing the data FIFOs.  <a href="#b4fbe11281b8200b70202d4e0048a9d7"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="0c78da7b7e7b59b31bd99a07d926a298"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_param_dma_enable" ref="0c78da7b7e7b59b31bd99a07d926a298" args="(dwc_otg_core_if_t *core_if)" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#0c78da7b7e7b59b31bd99a07d926a298">dwc_otg_get_param_dma_enable</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#7eae744525314774d3b390f116db126c">dwc_otg_set_param_dma_desc_enable</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">When DMA mode is enabled specifies whether to use address DMA or DMA Descritor mode for accessing the data FIFOs in device mode.  <a href="#7eae744525314774d3b390f116db126c"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="5cac7b3770cefa9db25bb46193134c5a"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_param_dma_desc_enable" ref="5cac7b3770cefa9db25bb46193134c5a" args="(dwc_otg_core_if_t *core_if)" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#5cac7b3770cefa9db25bb46193134c5a">dwc_otg_get_param_dma_desc_enable</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#920035c6082dcdfec11a20e8535e9fe9">dwc_otg_set_param_dma_burst_size</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">The DMA Burst size (applicable only for External DMA Mode).  <a href="#920035c6082dcdfec11a20e8535e9fe9"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7450ef9275974e46f41f12fdc6da7901"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_param_dma_burst_size" ref="7450ef9275974e46f41f12fdc6da7901" args="(dwc_otg_core_if_t *core_if)" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#7450ef9275974e46f41f12fdc6da7901">dwc_otg_get_param_dma_burst_size</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#7acd153b5577a3db825fa08d243ae856">dwc_otg_set_param_speed</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Specifies the maximum speed of operation in host and device mode.  <a href="#7acd153b5577a3db825fa08d243ae856"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f18994b0fe09d9d3031ef8290945c1ea"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_param_speed" ref="f18994b0fe09d9d3031ef8290945c1ea" args="(dwc_otg_core_if_t *core_if)" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#f18994b0fe09d9d3031ef8290945c1ea">dwc_otg_get_param_speed</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#8bd669637630521655c455c03d470e10">dwc_otg_set_param_host_support_fs_ls_low_power</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Specifies whether low power mode is supported when attached to a Full Speed or Low Speed device in host mode.  <a href="#8bd669637630521655c455c03d470e10"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ce7a69af8ef1970a640d0a23c7c8f12a"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_param_host_support_fs_ls_low_power" ref="ce7a69af8ef1970a640d0a23c7c8f12a" args="(dwc_otg_core_if_t *core_if)" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#ce7a69af8ef1970a640d0a23c7c8f12a">dwc_otg_get_param_host_support_fs_ls_low_power</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#354ce49f65334e829c2694811c4f2016">dwc_otg_set_param_host_ls_low_power_phy_clk</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Specifies the PHY clock rate in low power mode when connected to a Low Speed device in host mode.  <a href="#354ce49f65334e829c2694811c4f2016"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="02ea6a179d92658c4cf4e5b513cb2414"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_param_host_ls_low_power_phy_clk" ref="02ea6a179d92658c4cf4e5b513cb2414" args="(dwc_otg_core_if_t *core_if)" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#02ea6a179d92658c4cf4e5b513cb2414">dwc_otg_get_param_host_ls_low_power_phy_clk</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="61bb728cc80220e5173d5e3126dd4fd1"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_set_param_enable_dynamic_fifo" ref="61bb728cc80220e5173d5e3126dd4fd1" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#61bb728cc80220e5173d5e3126dd4fd1">dwc_otg_set_param_enable_dynamic_fifo</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">0 - Use cC FIFO size parameters 1 - Allow dynamic FIFO sizing (default) <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3bc5fc1c94b4bb1a5b5dcca6fa71584e"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_param_enable_dynamic_fifo" ref="3bc5fc1c94b4bb1a5b5dcca6fa71584e" args="(dwc_otg_core_if_t *core_if)" -->
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+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#69d52c46eb236816b20675ecb57975ae">dwc_otg_set_param_data_fifo_size</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Total number of 4-byte words in the data FIFO memory.  <a href="#69d52c46eb236816b20675ecb57975ae"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3695ec355114fb8da2f57b7f5c2159b7"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_param_data_fifo_size" ref="3695ec355114fb8da2f57b7f5c2159b7" args="(dwc_otg_core_if_t *core_if)" -->
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+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#0fa4db196053869ac19832c03c62913f">dwc_otg_set_param_dev_rx_fifo_size</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Number of 4-byte words in the Rx FIFO in device mode when dynamic FIFO sizing is enabled.  <a href="#0fa4db196053869ac19832c03c62913f"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="56781e1cc653e948147afab10c19b72a"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_param_dev_rx_fifo_size" ref="56781e1cc653e948147afab10c19b72a" args="(dwc_otg_core_if_t *core_if)" -->
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+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#4f7059cecabbf8cfe5014112ba9a3d42">dwc_otg_set_param_dev_nperio_tx_fifo_size</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Number of 4-byte words in the non-periodic Tx FIFO in device mode when dynamic FIFO sizing is enabled.  <a href="#4f7059cecabbf8cfe5014112ba9a3d42"></a><br></td></tr>
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+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#2119a493582bea4004b5fdeba15f1609">dwc_otg_set_param_dev_perio_tx_fifo_size</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val, int fifo_num)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Number of 4-byte words in each of the periodic Tx FIFOs in device mode when dynamic FIFO sizing is enabled.  <a href="#2119a493582bea4004b5fdeba15f1609"></a><br></td></tr>
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+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#254c1e97cf22fe34b7383165e30071eb">dwc_otg_set_param_host_rx_fifo_size</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO sizing is enabled.  <a href="#254c1e97cf22fe34b7383165e30071eb"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7b964a905858d04ce43159bbfca20f34"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_param_host_rx_fifo_size" ref="7b964a905858d04ce43159bbfca20f34" args="(dwc_otg_core_if_t *core_if)" -->
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+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#a66ca9f9345a13606148b050f8690a56">dwc_otg_set_param_host_nperio_tx_fifo_size</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Number of 4-byte words in the non-periodic Tx FIFO in host mode when Dynamic FIFO sizing is enabled in the core.  <a href="#a66ca9f9345a13606148b050f8690a56"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e53a7fddb0a2689e463cbd9c441ee004"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_param_host_nperio_tx_fifo_size" ref="e53a7fddb0a2689e463cbd9c441ee004" args="(dwc_otg_core_if_t *core_if)" -->
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+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#e4ce399208d8a85dcb9dedd1fb8cd8ce">dwc_otg_set_param_host_perio_tx_fifo_size</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO sizing is enabled.  <a href="#e4ce399208d8a85dcb9dedd1fb8cd8ce"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="9b2de0caea0d9ee86258ac4bbe63acd5"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_param_host_perio_tx_fifo_size" ref="9b2de0caea0d9ee86258ac4bbe63acd5" args="(dwc_otg_core_if_t *core_if)" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#9b2de0caea0d9ee86258ac4bbe63acd5">dwc_otg_get_param_host_perio_tx_fifo_size</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#2eee676071d6bb4eba53b413e80b045f">dwc_otg_set_param_max_transfer_size</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">The maximum transfer size supported in bytes.  <a href="#2eee676071d6bb4eba53b413e80b045f"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="307c59e350a8ea67ef5d1c02f79de17b"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_param_max_transfer_size" ref="307c59e350a8ea67ef5d1c02f79de17b" args="(dwc_otg_core_if_t *core_if)" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#307c59e350a8ea67ef5d1c02f79de17b">dwc_otg_get_param_max_transfer_size</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#a1c52f0740f7d0b72c980b38cc4314d1">dwc_otg_set_param_max_packet_count</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">The maximum number of packets in a transfer.  <a href="#a1c52f0740f7d0b72c980b38cc4314d1"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="765e82d04dc91bdc93c129d9ba7c5161"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_param_max_packet_count" ref="765e82d04dc91bdc93c129d9ba7c5161" args="(dwc_otg_core_if_t *core_if)" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#765e82d04dc91bdc93c129d9ba7c5161">dwc_otg_get_param_max_packet_count</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#f802acfc49b3fbb86159036f8f317f76">dwc_otg_set_param_host_channels</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">The number of host channel registers to use.  <a href="#f802acfc49b3fbb86159036f8f317f76"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e1235c11a6a3e8d0e78df59d86d4d287"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_param_host_channels" ref="e1235c11a6a3e8d0e78df59d86d4d287" args="(dwc_otg_core_if_t *core_if)" -->
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+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#75d3b409824c0ca52631277398ba8367">dwc_otg_set_param_dev_endpoints</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">The number of endpoints in addition to EP0 available for device mode operations.  <a href="#75d3b409824c0ca52631277398ba8367"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="27447ccef5d5a1c3e5c93ed3b352e152"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_param_dev_endpoints" ref="27447ccef5d5a1c3e5c93ed3b352e152" args="(dwc_otg_core_if_t *core_if)" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#27447ccef5d5a1c3e5c93ed3b352e152">dwc_otg_get_param_dev_endpoints</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#2b7087c85c0ea1520ec2e091b80bf36b">dwc_otg_set_param_phy_type</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Specifies the type of PHY interface to use.  <a href="#2b7087c85c0ea1520ec2e091b80bf36b"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e49dd633ec87aa71335ef6ef312283a3"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_param_phy_type" ref="e49dd633ec87aa71335ef6ef312283a3" args="(dwc_otg_core_if_t *core_if)" -->
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+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#1eacecc96e1ab100cbf129ad6aa5f6c8">dwc_otg_set_param_phy_utmi_width</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Specifies the UTMI+ Data Width.  <a href="#1eacecc96e1ab100cbf129ad6aa5f6c8"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="9dfa6a24c38b5ba13c08abe22d532a1d"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_param_phy_utmi_width" ref="9dfa6a24c38b5ba13c08abe22d532a1d" args="(dwc_otg_core_if_t *core_if)" -->
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+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#5dab15db053bd02c6bc9619e189a6a14">dwc_otg_set_param_phy_ulpi_ddr</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Specifies whether the ULPI operates at double or single data rate.  <a href="#5dab15db053bd02c6bc9619e189a6a14"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="95655db9d2dce391da40361fe310599c"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_param_phy_ulpi_ddr" ref="95655db9d2dce391da40361fe310599c" args="(dwc_otg_core_if_t *core_if)" -->
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+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="a12296bcb04a3b0f6f80037590e97bec"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_set_param_phy_ulpi_ext_vbus" ref="a12296bcb04a3b0f6f80037590e97bec" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
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+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Specifies whether to use the internal or external supply to drive the vbus with a ULPI phy. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b0604fadb0b685a106507eacd18e12a6"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_param_phy_ulpi_ext_vbus" ref="b0604fadb0b685a106507eacd18e12a6" args="(dwc_otg_core_if_t *core_if)" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#b0604fadb0b685a106507eacd18e12a6">dwc_otg_get_param_phy_ulpi_ext_vbus</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#65d7407ed24c82e158a38ab2a60120c4">dwc_otg_set_param_i2c_enable</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Specifies whether to use the I2Cinterface for full speed PHY.  <a href="#65d7407ed24c82e158a38ab2a60120c4"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="80cf1905c95391fa1acaa2237182ddf8"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_param_i2c_enable" ref="80cf1905c95391fa1acaa2237182ddf8" args="(dwc_otg_core_if_t *core_if)" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#80cf1905c95391fa1acaa2237182ddf8">dwc_otg_get_param_i2c_enable</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f235e9c7b844b899d759a073a84f782f"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_set_param_ulpi_fs_ls" ref="f235e9c7b844b899d759a073a84f782f" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#f235e9c7b844b899d759a073a84f782f">dwc_otg_set_param_ulpi_fs_ls</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="0ee03a3468e74cd2e38da1617b88313b"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_param_ulpi_fs_ls" ref="0ee03a3468e74cd2e38da1617b88313b" args="(dwc_otg_core_if_t *core_if)" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#0ee03a3468e74cd2e38da1617b88313b">dwc_otg_get_param_ulpi_fs_ls</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b05c92754c0ebc3d58ea0c090b9659de"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_set_param_ts_dline" ref="b05c92754c0ebc3d58ea0c090b9659de" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#b05c92754c0ebc3d58ea0c090b9659de">dwc_otg_set_param_ts_dline</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="025a93aef8cabae431033cb4fdc7772f"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_param_ts_dline" ref="025a93aef8cabae431033cb4fdc7772f" args="(dwc_otg_core_if_t *core_if)" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#025a93aef8cabae431033cb4fdc7772f">dwc_otg_get_param_ts_dline</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="2eefd02d72c79200072d54b4eb13e5cd"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_set_param_en_multiple_tx_fifo" ref="2eefd02d72c79200072d54b4eb13e5cd" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#2eefd02d72c79200072d54b4eb13e5cd">dwc_otg_set_param_en_multiple_tx_fifo</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Specifies whether dedicated transmit FIFOs are enabled for non periodic IN endpoints in device mode 0 - No 1 - Yes. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="bc8e0312a565efb2d5117984219b4460"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_param_en_multiple_tx_fifo" ref="bc8e0312a565efb2d5117984219b4460" args="(dwc_otg_core_if_t *core_if)" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#bc8e0312a565efb2d5117984219b4460">dwc_otg_get_param_en_multiple_tx_fifo</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#16eec7b52e6a95825f91b7f60d58db50">dwc_otg_set_param_dev_tx_fifo_size</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int fifo_num, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Number of 4-byte words in each of the Tx FIFOs in device mode when dynamic FIFO sizing is enabled.  <a href="#16eec7b52e6a95825f91b7f60d58db50"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="99a491c648b6066077426c9cdc374aa8"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_param_dev_tx_fifo_size" ref="99a491c648b6066077426c9cdc374aa8" args="(dwc_otg_core_if_t *core_if, int fifo_num)" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#99a491c648b6066077426c9cdc374aa8">dwc_otg_get_param_dev_tx_fifo_size</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int fifo_num)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="6095d6a93f901f32522d4b950c99a8e1"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_set_param_thr_ctl" ref="6095d6a93f901f32522d4b950c99a8e1" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#6095d6a93f901f32522d4b950c99a8e1">dwc_otg_set_param_thr_ctl</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Thresholding enable flag- bit 0 - enable non-ISO Tx thresholding bit 1 - enable ISO Tx thresholding bit 2 - enable Rx thresholding. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="1558e84fae6a8ee8f711245ceccd2cd8"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_thr_ctl" ref="1558e84fae6a8ee8f711245ceccd2cd8" args="(dwc_otg_core_if_t *core_if, int fifo_num)" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_otg_get_thr_ctl</b> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int fifo_num)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="1ed19fed8939a352f91fe1403574135e"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_set_param_tx_thr_length" ref="1ed19fed8939a352f91fe1403574135e" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#1ed19fed8939a352f91fe1403574135e">dwc_otg_set_param_tx_thr_length</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Thresholding length for Tx FIFOs in 32 bit DWORDs. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="dc01d00c85660cb5334b9e68c1ec7da2"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_tx_thr_length" ref="dc01d00c85660cb5334b9e68c1ec7da2" args="(dwc_otg_core_if_t *core_if)" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_otg_get_tx_thr_length</b> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="20d005470a65927cb243b37619f6c6bf"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_set_param_rx_thr_length" ref="20d005470a65927cb243b37619f6c6bf" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#20d005470a65927cb243b37619f6c6bf">dwc_otg_set_param_rx_thr_length</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Thresholding length for Rx FIFOs in 32 bit DWORDs. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ed17dde438e96fb98a4a4bad173a704b"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_rx_thr_length" ref="ed17dde438e96fb98a4a4bad173a704b" args="(dwc_otg_core_if_t *core_if)" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_otg_get_rx_thr_length</b> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e3a62b66e19a302a55046830f5eecf0c"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_set_param_lpm_enable" ref="e3a62b66e19a302a55046830f5eecf0c" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#e3a62b66e19a302a55046830f5eecf0c">dwc_otg_set_param_lpm_enable</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Specifies whether LPM (Link Power Management) support is enabled. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="0e0eb29733595730396da3ddf3d0ded5"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_param_lpm_enable" ref="0e0eb29733595730396da3ddf3d0ded5" args="(dwc_otg_core_if_t *core_if)" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#0e0eb29733595730396da3ddf3d0ded5">dwc_otg_get_param_lpm_enable</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="63c0b4bfcf3b1c6c90c5572258439e1f"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_set_param_pti_enable" ref="63c0b4bfcf3b1c6c90c5572258439e1f" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#63c0b4bfcf3b1c6c90c5572258439e1f">dwc_otg_set_param_pti_enable</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Specifies whether PTI enhancement is enabled. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="9d729a393133a8111b68d4b5ec9fdd30"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_param_pti_enable" ref="9d729a393133a8111b68d4b5ec9fdd30" args="(dwc_otg_core_if_t *core_if)" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#9d729a393133a8111b68d4b5ec9fdd30">dwc_otg_get_param_pti_enable</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7ba10fdfd2ce9f3ef4b0a2bef555a7c1"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_set_param_mpi_enable" ref="7ba10fdfd2ce9f3ef4b0a2bef555a7c1" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#7ba10fdfd2ce9f3ef4b0a2bef555a7c1">dwc_otg_set_param_mpi_enable</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Specifies whether MPI enhancement is enabled. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7b9e3bced8a43e810fca322e36946f31"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_param_mpi_enable" ref="7b9e3bced8a43e810fca322e36946f31" args="(dwc_otg_core_if_t *core_if)" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#7b9e3bced8a43e810fca322e36946f31">dwc_otg_get_param_mpi_enable</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="93036faefc8179eef11c8ca0b18993a8"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_set_param_ic_usb_cap" ref="93036faefc8179eef11c8ca0b18993a8" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#93036faefc8179eef11c8ca0b18993a8">dwc_otg_set_param_ic_usb_cap</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Specifies whether IC_USB capability is enabled. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="1ccaddc86262ff99dad6c1e44f5ff965"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_param_ic_usb_cap" ref="1ccaddc86262ff99dad6c1e44f5ff965" args="(dwc_otg_core_if_t *core_if)" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#1ccaddc86262ff99dad6c1e44f5ff965">dwc_otg_get_param_ic_usb_cap</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="9bf87dcaa6dcea51eb3d8c30439a2138"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_set_param_ahb_thr_ratio" ref="9bf87dcaa6dcea51eb3d8c30439a2138" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#9bf87dcaa6dcea51eb3d8c30439a2138">dwc_otg_set_param_ahb_thr_ratio</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, int32_t val)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="275fab9bf16bd3cb148901c578fbcbd0"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_param_ahb_thr_ratio" ref="275fab9bf16bd3cb148901c578fbcbd0" args="(dwc_otg_core_if_t *core_if)" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#275fab9bf16bd3cb148901c578fbcbd0">dwc_otg_get_param_ahb_thr_ratio</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td colspan="2"><br><h2>Access to registers and bit-fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#f4a8cc5126f81ceb361294c7734737aa">dwc_otg_dump_dev_registers</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *_core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Dump core registers and SPRAM.  <a href="#f4a8cc5126f81ceb361294c7734737aa"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#5b28e869ddc5a4c44d8669b6423b414e">dwc_otg_dump_spram</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *_core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This functions reads the SPRAM and prints its content.  <a href="#5b28e869ddc5a4c44d8669b6423b414e"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#a4c7a094e7c6eb2d28103e787ff09934">dwc_otg_dump_host_registers</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *_core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function reads the host registers and prints them.  <a href="#a4c7a094e7c6eb2d28103e787ff09934"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#814be5b2f30d8321f7152fe897799224">dwc_otg_dump_global_registers</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *_core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function reads the core global registers and prints them.  <a href="#814be5b2f30d8321f7152fe897799224"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="df391379aafa69a8683bb1f88c413675"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_hnpstatus" ref="df391379aafa69a8683bb1f88c413675" args="(dwc_otg_core_if_t *core_if)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#df391379aafa69a8683bb1f88c413675">dwc_otg_get_hnpstatus</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get host negotiation status. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b13eac2758aace478587df0f043e80f8"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_srpstatus" ref="b13eac2758aace478587df0f043e80f8" args="(dwc_otg_core_if_t *core_if)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#b13eac2758aace478587df0f043e80f8">dwc_otg_get_srpstatus</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get srp status. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="5cab27b65ed5a6a1e31c0e4df1650f0e"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_set_hnpreq" ref="5cab27b65ed5a6a1e31c0e4df1650f0e" args="(dwc_otg_core_if_t *core_if, uint32_t val)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#5cab27b65ed5a6a1e31c0e4df1650f0e">dwc_otg_set_hnpreq</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, uint32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Set hnpreq bit in the GOTGCTL register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c505c47a08029706f60ab8f3d67b70d3"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_gsnpsid" ref="c505c47a08029706f60ab8f3d67b70d3" args="(dwc_otg_core_if_t *core_if)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#c505c47a08029706f60ab8f3d67b70d3">dwc_otg_get_gsnpsid</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get Content of SNPSID register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#788149caf9d915abbe5e289793684b1e">dwc_otg_get_mode</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get current mode.  <a href="#788149caf9d915abbe5e289793684b1e"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="d222e3bdaba5ea8fa0df22ff9cee2f5e"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_hnpcapable" ref="d222e3bdaba5ea8fa0df22ff9cee2f5e" args="(dwc_otg_core_if_t *core_if)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#d222e3bdaba5ea8fa0df22ff9cee2f5e">dwc_otg_get_hnpcapable</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get value of hnpcapable field in the GUSBCFG register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b9ab6ff4d50ea35738853f831f480c3e"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_set_hnpcapable" ref="b9ab6ff4d50ea35738853f831f480c3e" args="(dwc_otg_core_if_t *core_if, uint32_t val)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#b9ab6ff4d50ea35738853f831f480c3e">dwc_otg_set_hnpcapable</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, uint32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Set value of hnpcapable field in the GUSBCFG register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="2bba47b0255cfbc9b19661e9ddd2f497"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_srpcapable" ref="2bba47b0255cfbc9b19661e9ddd2f497" args="(dwc_otg_core_if_t *core_if)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#2bba47b0255cfbc9b19661e9ddd2f497">dwc_otg_get_srpcapable</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get value of srpcapable field in the GUSBCFG register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e75a4faa49ac70c19e9bc8a039d6e37f"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_set_srpcapable" ref="e75a4faa49ac70c19e9bc8a039d6e37f" args="(dwc_otg_core_if_t *core_if, uint32_t val)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#e75a4faa49ac70c19e9bc8a039d6e37f">dwc_otg_set_srpcapable</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, uint32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Set value of srpcapable field in the GUSBCFG register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="d69afedd204a41974de582224479569e"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_devspeed" ref="d69afedd204a41974de582224479569e" args="(dwc_otg_core_if_t *core_if)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#d69afedd204a41974de582224479569e">dwc_otg_get_devspeed</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get value of devspeed field in the DCFG register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ead8dea166cbefca04dc5c543c96fba0"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_set_devspeed" ref="ead8dea166cbefca04dc5c543c96fba0" args="(dwc_otg_core_if_t *core_if, uint32_t val)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#ead8dea166cbefca04dc5c543c96fba0">dwc_otg_set_devspeed</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, uint32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Set value of devspeed field in the DCFG register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="07354b164566c5c1c34446d5b0c4036f"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_busconnected" ref="07354b164566c5c1c34446d5b0c4036f" args="(dwc_otg_core_if_t *core_if)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#07354b164566c5c1c34446d5b0c4036f">dwc_otg_get_busconnected</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get the value of busconnected field from the HPRT0 register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="520bf6b5f5ec69e5dcbdad6254c3cede"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_enumspeed" ref="520bf6b5f5ec69e5dcbdad6254c3cede" args="(dwc_otg_core_if_t *core_if)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#520bf6b5f5ec69e5dcbdad6254c3cede">dwc_otg_get_enumspeed</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Gets the device enumeration Speed. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="83a11dae1c9563aee56baea469cd6064"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_prtpower" ref="83a11dae1c9563aee56baea469cd6064" args="(dwc_otg_core_if_t *core_if)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#83a11dae1c9563aee56baea469cd6064">dwc_otg_get_prtpower</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get value of prtpwr field from the HPRT0 register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="63c880f915b4705a5c118b276e6e9567"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_set_prtpower" ref="63c880f915b4705a5c118b276e6e9567" args="(dwc_otg_core_if_t *core_if, uint32_t val)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#63c880f915b4705a5c118b276e6e9567">dwc_otg_set_prtpower</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, uint32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Set value of prtpwr field from the HPRT0 register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="65b0861f7d5d604fb97e599adac62642"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_prtsuspend" ref="65b0861f7d5d604fb97e599adac62642" args="(dwc_otg_core_if_t *core_if)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#65b0861f7d5d604fb97e599adac62642">dwc_otg_get_prtsuspend</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get value of prtsusp field from the HPRT0 regsiter. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c072cef5b7d3c5566ad3be010c6d49ed"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_set_prtsuspend" ref="c072cef5b7d3c5566ad3be010c6d49ed" args="(dwc_otg_core_if_t *core_if, uint32_t val)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#c072cef5b7d3c5566ad3be010c6d49ed">dwc_otg_set_prtsuspend</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, uint32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Set value of prtpwr field from the HPRT0 register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b6d6b18934ba5cd4ce2cf9e68be338f5"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_set_prtresume" ref="b6d6b18934ba5cd4ce2cf9e68be338f5" args="(dwc_otg_core_if_t *core_if, uint32_t val)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#b6d6b18934ba5cd4ce2cf9e68be338f5">dwc_otg_set_prtresume</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, uint32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Set value of prtres field from the HPRT0 register FIXME Remove? <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="285696198299e317222544aa912b2c35"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_remotewakesig" ref="285696198299e317222544aa912b2c35" args="(dwc_otg_core_if_t *core_if)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#285696198299e317222544aa912b2c35">dwc_otg_get_remotewakesig</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get value of rmtwkupsig bit in DCTL register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="87d643973839554bac437d283a462e00"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_lpm_portsleepstatus" ref="87d643973839554bac437d283a462e00" args="(dwc_otg_core_if_t *core_if)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#87d643973839554bac437d283a462e00">dwc_otg_get_lpm_portsleepstatus</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get value of prt_sleep_sts field from the GLPMCFG register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="91d2a6b57c7216fd5c6dc981a5f0e1ae"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_lpm_remotewakeenabled" ref="91d2a6b57c7216fd5c6dc981a5f0e1ae" args="(dwc_otg_core_if_t *core_if)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#91d2a6b57c7216fd5c6dc981a5f0e1ae">dwc_otg_get_lpm_remotewakeenabled</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get value of rem_wkup_en field from the GLPMCFG register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="86d921a91b7e2b143a305283282ce36d"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_lpmresponse" ref="86d921a91b7e2b143a305283282ce36d" args="(dwc_otg_core_if_t *core_if)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#86d921a91b7e2b143a305283282ce36d">dwc_otg_get_lpmresponse</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get value of appl_resp field from the GLPMCFG register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b19565bc2a8dbb258c3c2cb8c52240b8"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_set_lpmresponse" ref="b19565bc2a8dbb258c3c2cb8c52240b8" args="(dwc_otg_core_if_t *core_if, uint32_t val)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#b19565bc2a8dbb258c3c2cb8c52240b8">dwc_otg_set_lpmresponse</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, uint32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Set value of appl_resp field from the GLPMCFG register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="0fb8a2b51041b2f5476abc8ffbcc46cb"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_hsic_connect" ref="0fb8a2b51041b2f5476abc8ffbcc46cb" args="(dwc_otg_core_if_t *core_if)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#0fb8a2b51041b2f5476abc8ffbcc46cb">dwc_otg_get_hsic_connect</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get value of hsic_connect field from the GLPMCFG register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="6625bea93daab21b2a97004f743203f9"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_set_hsic_connect" ref="6625bea93daab21b2a97004f743203f9" args="(dwc_otg_core_if_t *core_if, uint32_t val)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#6625bea93daab21b2a97004f743203f9">dwc_otg_set_hsic_connect</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, uint32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Set value of hsic_connect field from the GLPMCFG register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="a3399019a62013ccc6ce213e8f241d7a"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_inv_sel_hsic" ref="a3399019a62013ccc6ce213e8f241d7a" args="(dwc_otg_core_if_t *core_if)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#a3399019a62013ccc6ce213e8f241d7a">dwc_otg_get_inv_sel_hsic</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get value of inv_sel_hsic field from the GLPMCFG register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ef8b7bbc803e779480aa06779a44e4f0"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_set_inv_sel_hsic" ref="ef8b7bbc803e779480aa06779a44e4f0" args="(dwc_otg_core_if_t *core_if, uint32_t val)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#ef8b7bbc803e779480aa06779a44e4f0">dwc_otg_set_inv_sel_hsic</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, uint32_t val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Set value of inv_sel_hsic field from the GLPMFG register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="a450da19279ae7246c89ede2949189fe"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_gotgctl" ref="a450da19279ae7246c89ede2949189fe" args="(dwc_otg_core_if_t *core_if)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#a450da19279ae7246c89ede2949189fe">dwc_otg_get_gotgctl</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">GOTGCTL register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="be44aee1ee301bdcbf7174cc1c729032"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_set_gotgctl" ref="be44aee1ee301bdcbf7174cc1c729032" args="(dwc_otg_core_if_t *core_if, uint32_t val)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#be44aee1ee301bdcbf7174cc1c729032">dwc_otg_set_gotgctl</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, uint32_t val)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="eb5b1512f29fa951f2875dc52d368085"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_gusbcfg" ref="eb5b1512f29fa951f2875dc52d368085" args="(dwc_otg_core_if_t *core_if)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#eb5b1512f29fa951f2875dc52d368085">dwc_otg_get_gusbcfg</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">GUSBCFG register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="74d5e1045c70fd5efc35a39ca4311baa"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_set_gusbcfg" ref="74d5e1045c70fd5efc35a39ca4311baa" args="(dwc_otg_core_if_t *core_if, uint32_t val)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#74d5e1045c70fd5efc35a39ca4311baa">dwc_otg_set_gusbcfg</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, uint32_t val)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ce6ba769b9c0abd15c8f0b118d74c8e4"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_grxfsiz" ref="ce6ba769b9c0abd15c8f0b118d74c8e4" args="(dwc_otg_core_if_t *core_if)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#ce6ba769b9c0abd15c8f0b118d74c8e4">dwc_otg_get_grxfsiz</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">GRXFSIZ register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3e251d5b9273ae2e2b3f5714694974a5"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_set_grxfsiz" ref="3e251d5b9273ae2e2b3f5714694974a5" args="(dwc_otg_core_if_t *core_if, uint32_t val)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#3e251d5b9273ae2e2b3f5714694974a5">dwc_otg_set_grxfsiz</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, uint32_t val)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3110e552598b04bbe6b30bcddadda98b"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_gnptxfsiz" ref="3110e552598b04bbe6b30bcddadda98b" args="(dwc_otg_core_if_t *core_if)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#3110e552598b04bbe6b30bcddadda98b">dwc_otg_get_gnptxfsiz</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">GNPTXFSIZ register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="48c625d569671523aac60af8e2d60d7a"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_set_gnptxfsiz" ref="48c625d569671523aac60af8e2d60d7a" args="(dwc_otg_core_if_t *core_if, uint32_t val)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#48c625d569671523aac60af8e2d60d7a">dwc_otg_set_gnptxfsiz</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, uint32_t val)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c8fcf302be26cad07b9ba36082e0ed5c"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_gpvndctl" ref="c8fcf302be26cad07b9ba36082e0ed5c" args="(dwc_otg_core_if_t *core_if)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#c8fcf302be26cad07b9ba36082e0ed5c">dwc_otg_get_gpvndctl</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="4c700540a6c1061eb2491c78670bb26f"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_set_gpvndctl" ref="4c700540a6c1061eb2491c78670bb26f" args="(dwc_otg_core_if_t *core_if, uint32_t val)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#4c700540a6c1061eb2491c78670bb26f">dwc_otg_set_gpvndctl</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, uint32_t val)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="5b3367179e8c0c6ccb5041db26f8e0cc"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_ggpio" ref="5b3367179e8c0c6ccb5041db26f8e0cc" args="(dwc_otg_core_if_t *core_if)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#5b3367179e8c0c6ccb5041db26f8e0cc">dwc_otg_get_ggpio</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">GGPIO register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="4b6bd4ddf333b856631cd561eb747882"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_set_ggpio" ref="4b6bd4ddf333b856631cd561eb747882" args="(dwc_otg_core_if_t *core_if, uint32_t val)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#4b6bd4ddf333b856631cd561eb747882">dwc_otg_set_ggpio</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, uint32_t val)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c308abdec734a3d2f183d2085271d285"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_guid" ref="c308abdec734a3d2f183d2085271d285" args="(dwc_otg_core_if_t *core_if)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#c308abdec734a3d2f183d2085271d285">dwc_otg_get_guid</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">GUID register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="edf22163b21a9ab3539976e19338f1e9"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_set_guid" ref="edf22163b21a9ab3539976e19338f1e9" args="(dwc_otg_core_if_t *core_if, uint32_t val)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#edf22163b21a9ab3539976e19338f1e9">dwc_otg_set_guid</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, uint32_t val)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="6345490821a039a5eff6ec8e5c0e8c0b"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_hprt0" ref="6345490821a039a5eff6ec8e5c0e8c0b" args="(dwc_otg_core_if_t *core_if)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#6345490821a039a5eff6ec8e5c0e8c0b">dwc_otg_get_hprt0</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">HPRT0 register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c2ec55794abeeb14f5b4d00613122bb7"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_set_hprt0" ref="c2ec55794abeeb14f5b4d00613122bb7" args="(dwc_otg_core_if_t *core_if, uint32_t val)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#c2ec55794abeeb14f5b4d00613122bb7">dwc_otg_set_hprt0</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, uint32_t val)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="6180fa187cfbeef487a71fb4f72a6381"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_hptxfsiz" ref="6180fa187cfbeef487a71fb4f72a6381" args="(dwc_otg_core_if_t *core_if)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#6180fa187cfbeef487a71fb4f72a6381">dwc_otg_get_hptxfsiz</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">GHPTXFSIZE. <br></td></tr>
+<tr><td colspan="2"><br><h2>Defines</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="5bae757850823a08f21d3c2156dcdb19"></a><!-- doxytag: member="dwc_otg_core_if.h::__DWC_CORE_IF_H__" ref="5bae757850823a08f21d3c2156dcdb19" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#5bae757850823a08f21d3c2156dcdb19">__DWC_CORE_IF_H__</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="13bb22067644d357537c2905fe5ffb8c"></a><!-- doxytag: member="dwc_otg_core_if.h::MAX_PERIO_FIFOS" ref="13bb22067644d357537c2905fe5ffb8c" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#13bb22067644d357537c2905fe5ffb8c">MAX_PERIO_FIFOS</a>&nbsp;&nbsp;&nbsp;15</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Maximum number of Periodic FIFOs. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="050db6129005b993e573311dc42bc1a8"></a><!-- doxytag: member="dwc_otg_core_if.h::MAX_TX_FIFOS" ref="050db6129005b993e573311dc42bc1a8" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#050db6129005b993e573311dc42bc1a8">MAX_TX_FIFOS</a>&nbsp;&nbsp;&nbsp;15</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Maximum number of Periodic FIFOs. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="bfb88b45545f7685f668ac2f545674ec"></a><!-- doxytag: member="dwc_otg_core_if.h::MAX_EPS_CHANNELS" ref="bfb88b45545f7685f668ac2f545674ec" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#bfb88b45545f7685f668ac2f545674ec">MAX_EPS_CHANNELS</a>&nbsp;&nbsp;&nbsp;16</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Maximum number of Endpoints/HostChannels. <br></td></tr>
+<tr><td colspan="2"><br><h2>Typedefs</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="645ef0682256d1b3dbd576fe9dfaf487"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_core_if_t" ref="645ef0682256d1b3dbd576fe9dfaf487" args="" -->
+typedef <a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if_t</a></td></tr>
+
+<tr><td colspan="2"><br><h2>Functions</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#cd21205476fda6e8106730c3502f097b">dwc_otg_cil_init</a> (const uint32_t *_reg_base_addr)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function is called to initialize the DWC_otg CSR data structures.  <a href="#cd21205476fda6e8106730c3502f097b"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#bb49c254dfc70ec4cfe1bcb072cad5d8">dwc_otg_core_init</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *_core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function initializes the DWC_otg controller registers and prepares the core for device mode or host mode operation.  <a href="#bb49c254dfc70ec4cfe1bcb072cad5d8"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#c942f856a93287803eba8c84846730ac">dwc_otg_cil_remove</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *_core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function frees the structures allocated by <a class="el" href="dwc__otg__cil_8c.html#2dc0a6c5541c1a8a014d66a8fce53f66">dwc_otg_cil_init()</a>.  <a href="#c942f856a93287803eba8c84846730ac"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#90b4321b4979bcfdb71fb41aa66a6ce2">dwc_otg_enable_global_interrupts</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *_core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function enables the controller's Global Interrupt in the AHB Config register.  <a href="#90b4321b4979bcfdb71fb41aa66a6ce2"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#fe39ea4a5daa6dd32e12a42a82b3a463">dwc_otg_disable_global_interrupts</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *_core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function disables the controller's Global Interrupt in the AHB Config register.  <a href="#fe39ea4a5daa6dd32e12a42a82b3a463"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e83fb22890bc54c6b06cedb751430e77"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_is_device_mode" ref="e83fb22890bc54c6b06cedb751430e77" args="(dwc_otg_core_if_t *_core_if)" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#e83fb22890bc54c6b06cedb751430e77">dwc_otg_is_device_mode</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *_core_if)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f0bfe5f933e21a94ea06c96ffc086e72"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_is_host_mode" ref="f0bfe5f933e21a94ea06c96ffc086e72" args="(dwc_otg_core_if_t *_core_if)" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#f0bfe5f933e21a94ea06c96ffc086e72">dwc_otg_is_host_mode</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *_core_if)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f4f060a2decd6434bbd96703a4d1fc66"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_is_dma_enable" ref="f4f060a2decd6434bbd96703a4d1fc66" args="(dwc_otg_core_if_t *core_if)" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#f4f060a2decd6434bbd96703a4d1fc66">dwc_otg_is_dma_enable</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__core__if_8h.html#f13810eb319c429745b8f5cb9870dc2b">dwc_otg_handle_common_intr</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *_core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function should be called on every hardware interrupt.  <a href="#f13810eb319c429745b8f5cb9870dc2b"></a><br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This file defines DWC_OTG Core API. 
+<p>
+
+<p>
+Definition in file <a class="el" href="dwc__otg__core__if_8h-source.html">dwc_otg_core_if.h</a>.<hr><h2>Function Documentation</h2>
+<a class="anchor" name="cd21205476fda6e8106730c3502f097b"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_cil_init" ref="cd21205476fda6e8106730c3502f097b" args="(const uint32_t *_reg_base_addr)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a>* dwc_otg_cil_init           </td>
+          <td>(</td>
+          <td class="paramtype">const uint32_t *&nbsp;</td>
+          <td class="paramname"> <em>reg_base_addr</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function is called to initialize the DWC_otg CSR data structures. 
+<p>
+The register addresses in the device and host structures are initialized from the base address supplied by the caller. The calling function must make the OS calls to get the base address of the DWC_otg controller registers. The core_params argument holds the parameters that specify how the core should be configured.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>reg_base_addr</em>&nbsp;</td><td>Base address of DWC_otg core registers </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l00078">78</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="bb49c254dfc70ec4cfe1bcb072cad5d8"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_core_init" ref="bb49c254dfc70ec4cfe1bcb072cad5d8" args="(dwc_otg_core_if_t *_core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_core_init           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function initializes the DWC_otg controller registers and prepares the core for device mode or host mode operation. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of the DWC_otg controller </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l00467">467</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="c942f856a93287803eba8c84846730ac"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_cil_remove" ref="c942f856a93287803eba8c84846730ac" args="(dwc_otg_core_if_t *_core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_cil_remove           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function frees the structures allocated by <a class="el" href="dwc__otg__cil_8c.html#2dc0a6c5541c1a8a014d66a8fce53f66">dwc_otg_cil_init()</a>. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>The core interface pointer returned from <a class="el" href="dwc__otg__cil_8c.html#2dc0a6c5541c1a8a014d66a8fce53f66">dwc_otg_cil_init()</a>. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l00265">265</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="90b4321b4979bcfdb71fb41aa66a6ce2"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_enable_global_interrupts" ref="90b4321b4979bcfdb71fb41aa66a6ce2" args="(dwc_otg_core_if_t *_core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_enable_global_interrupts           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function enables the controller's Global Interrupt in the AHB Config register. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l00292">292</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="fe39ea4a5daa6dd32e12a42a82b3a463"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_disable_global_interrupts" ref="fe39ea4a5daa6dd32e12a42a82b3a463" args="(dwc_otg_core_if_t *_core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_disable_global_interrupts           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function disables the controller's Global Interrupt in the AHB Config register. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l00305">305</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="f13810eb319c429745b8f5cb9870dc2b"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_handle_common_intr" ref="f13810eb319c429745b8f5cb9870dc2b" args="(dwc_otg_core_if_t *_core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t dwc_otg_handle_common_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function should be called on every hardware interrupt. 
+<p>
+The common interrupts are those that occur in both Host and Device mode. This handler handles the following interrupts:<ul>
+<li>Mode Mismatch Interrupt</li><li>Disconnect Interrupt</li><li>OTG Interrupt</li><li>Connector ID Status Change Interrupt</li><li>Session Request Interrupt.</li><li>Resume / Remote Wakeup Detected Interrupt.</li><li>LPM Transaction Received Interrutp </li></ul>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil__intr_8c-source.html#l00800">800</a> of file <a class="el" href="dwc__otg__cil__intr_8c-source.html">dwc_otg_cil_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="878cc478f43c58991c446bd78f50f8f0"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_set_param_otg_cap" ref="878cc478f43c58991c446bd78f50f8f0" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_set_param_otg_cap           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&nbsp;</td>
+          <td class="paramname"> <em>val</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Specifies the OTG capabilities. 
+<p>
+The driver will automatically detect the value for this parameter if none is specified. 0 - HNP and SRP capable (default) 1 - SRP Only capable 2 - No HNP/SRP capable 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l04056">4056</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="b4fbe11281b8200b70202d4e0048a9d7"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_set_param_dma_enable" ref="b4fbe11281b8200b70202d4e0048a9d7" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_set_param_dma_enable           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&nbsp;</td>
+          <td class="paramname"> <em>val</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Specifies whether to use slave or DMA mode for accessing the data FIFOs. 
+<p>
+The driver will automatically detect the value for this parameter if none is specified. 0 - Slave 1 - DMA (default, if available) 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l04135">4135</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="7eae744525314774d3b390f116db126c"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_set_param_dma_desc_enable" ref="7eae744525314774d3b390f116db126c" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_set_param_dma_desc_enable           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&nbsp;</td>
+          <td class="paramname"> <em>val</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+When DMA mode is enabled specifies whether to use address DMA or DMA Descritor mode for accessing the data FIFOs in device mode. 
+<p>
+The driver will automatically detect the value for this parameter if none is specified. 0 - address DMA 1 - DMA Descriptor(default, if available) 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l04165">4165</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="920035c6082dcdfec11a20e8535e9fe9"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_set_param_dma_burst_size" ref="920035c6082dcdfec11a20e8535e9fe9" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_set_param_dma_burst_size           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&nbsp;</td>
+          <td class="paramname"> <em>val</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+The DMA Burst size (applicable only for External DMA Mode). 
+<p>
+1, 4, 8 16, 32, 64, 128, 256 (default 32) 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l04959">4959</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="7acd153b5577a3db825fa08d243ae856"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_set_param_speed" ref="7acd153b5577a3db825fa08d243ae856" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_set_param_speed           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&nbsp;</td>
+          <td class="paramname"> <em>val</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Specifies the maximum speed of operation in host and device mode. 
+<p>
+The actual speed depends on the speed of the attached device and the value of phy_type. The actual speed depends on the speed of the attached device. 0 - High Speed (default) 1 - Full Speed 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l04601">4601</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="8bd669637630521655c455c03d470e10"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_set_param_host_support_fs_ls_low_power" ref="8bd669637630521655c455c03d470e10" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_set_param_host_support_fs_ls_low_power           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&nbsp;</td>
+          <td class="paramname"> <em>val</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Specifies whether low power mode is supported when attached to a Full Speed or Low Speed device in host mode. 
+<p>
+0 - Don't support low power mode (default) 1 - Support low power mode 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l04195">4195</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="354ce49f65334e829c2694811c4f2016"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_set_param_host_ls_low_power_phy_clk" ref="354ce49f65334e829c2694811c4f2016" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_set_param_host_ls_low_power_phy_clk           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&nbsp;</td>
+          <td class="paramname"> <em>val</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Specifies the PHY clock rate in low power mode when connected to a Low Speed device in host mode. 
+<p>
+This parameter is applicable only if HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS then defaults to 6 MHZ otherwise 48 MHZ.<p>
+0 - 48 MHz 1 - 6 MHz 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l04630">4630</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="69d52c46eb236816b20675ecb57975ae"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_set_param_data_fifo_size" ref="69d52c46eb236816b20675ecb57975ae" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_set_param_data_fifo_size           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&nbsp;</td>
+          <td class="paramname"> <em>val</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Total number of 4-byte words in the data FIFO memory. 
+<p>
+This memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs. 32 to 32768 (default 8192) Note: The total FIFO memory depth in the FPGA configuration is 8192. 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l04242">4242</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="0fa4db196053869ac19832c03c62913f"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_set_param_dev_rx_fifo_size" ref="0fa4db196053869ac19832c03c62913f" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_set_param_dev_rx_fifo_size           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&nbsp;</td>
+          <td class="paramname"> <em>val</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Number of 4-byte words in the Rx FIFO in device mode when dynamic FIFO sizing is enabled. 
+<p>
+16 to 32768 (default 1064) 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l04271">4271</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="4f7059cecabbf8cfe5014112ba9a3d42"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_set_param_dev_nperio_tx_fifo_size" ref="4f7059cecabbf8cfe5014112ba9a3d42" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_set_param_dev_nperio_tx_fifo_size           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&nbsp;</td>
+          <td class="paramname"> <em>val</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Number of 4-byte words in the non-periodic Tx FIFO in device mode when dynamic FIFO sizing is enabled. 
+<p>
+16 to 32768 (default 1024) 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l04297">4297</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="2119a493582bea4004b5fdeba15f1609"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_set_param_dev_perio_tx_fifo_size" ref="2119a493582bea4004b5fdeba15f1609" args="(dwc_otg_core_if_t *core_if, int32_t val, int fifo_num)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_set_param_dev_perio_tx_fifo_size           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&nbsp;</td>
+          <td class="paramname"> <em>val</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>fifo_num</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Number of 4-byte words in each of the periodic Tx FIFOs in device mode when dynamic FIFO sizing is enabled. 
+<p>
+4 to 768 (default 256) 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l04779">4779</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="254c1e97cf22fe34b7383165e30071eb"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_set_param_host_rx_fifo_size" ref="254c1e97cf22fe34b7383165e30071eb" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_set_param_host_rx_fifo_size           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&nbsp;</td>
+          <td class="paramname"> <em>val</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO sizing is enabled. 
+<p>
+16 to 32768 (default 1024) 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l04330">4330</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="a66ca9f9345a13606148b050f8690a56"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_set_param_host_nperio_tx_fifo_size" ref="a66ca9f9345a13606148b050f8690a56" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_set_param_host_nperio_tx_fifo_size           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&nbsp;</td>
+          <td class="paramname"> <em>val</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Number of 4-byte words in the non-periodic Tx FIFO in host mode when Dynamic FIFO sizing is enabled in the core. 
+<p>
+16 to 32768 (default 1024) 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l04362">4362</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="e4ce399208d8a85dcb9dedd1fb8cd8ce"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_set_param_host_perio_tx_fifo_size" ref="e4ce399208d8a85dcb9dedd1fb8cd8ce" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_set_param_host_perio_tx_fifo_size           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&nbsp;</td>
+          <td class="paramname"> <em>val</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO sizing is enabled. 
+<p>
+16 to 32768 (default 1024) 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l04395">4395</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="2eee676071d6bb4eba53b413e80b045f"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_set_param_max_transfer_size" ref="2eee676071d6bb4eba53b413e80b045f" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_set_param_max_transfer_size           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&nbsp;</td>
+          <td class="paramname"> <em>val</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+The maximum transfer size supported in bytes. 
+<p>
+2047 to 65,535 (default 65,535) 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l04428">4428</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="a1c52f0740f7d0b72c980b38cc4314d1"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_set_param_max_packet_count" ref="a1c52f0740f7d0b72c980b38cc4314d1" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_set_param_max_packet_count           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&nbsp;</td>
+          <td class="paramname"> <em>val</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+The maximum number of packets in a transfer. 
+<p>
+15 to 511 (default 511) 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l04461">4461</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="f802acfc49b3fbb86159036f8f317f76"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_set_param_host_channels" ref="f802acfc49b3fbb86159036f8f317f76" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_set_param_host_channels           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&nbsp;</td>
+          <td class="paramname"> <em>val</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+The number of host channel registers to use. 
+<p>
+1 to 16 (default 12) Note: The FPGA configuration supports a maximum of 12 host channels. 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l04492">4492</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="75d3b409824c0ca52631277398ba8367"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_set_param_dev_endpoints" ref="75d3b409824c0ca52631277398ba8367" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_set_param_dev_endpoints           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&nbsp;</td>
+          <td class="paramname"> <em>val</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+The number of endpoints in addition to EP0 available for device mode operations. 
+<p>
+1 to 15 (default 6 IN and OUT) Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in addition to EP0. 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l04522">4522</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="2b7087c85c0ea1520ec2e091b80bf36b"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_set_param_phy_type" ref="2b7087c85c0ea1520ec2e091b80bf36b" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_set_param_phy_type           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&nbsp;</td>
+          <td class="paramname"> <em>val</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Specifies the type of PHY interface to use. 
+<p>
+By default, the driver will automatically detect the phy_type.<p>
+0 - Full Speed PHY 1 - UTMI+ (default) 2 - ULPI 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l04552">4552</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="1eacecc96e1ab100cbf129ad6aa5f6c8"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_set_param_phy_utmi_width" ref="1eacecc96e1ab100cbf129ad6aa5f6c8" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_set_param_phy_utmi_width           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&nbsp;</td>
+          <td class="paramname"> <em>val</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Specifies the UTMI+ Data Width. 
+<p>
+This parameter is applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI PHY_TYPE, this parameter indicates the data width between the MAC and the ULPI Wrapper.) Also, this parameter is applicable only if the OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the core has been configured to work at either data path width.<p>
+8 or 16 bits (default 16) 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l04700">4700</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="5dab15db053bd02c6bc9619e189a6a14"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_set_param_phy_ulpi_ddr" ref="5dab15db053bd02c6bc9619e189a6a14" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_set_param_phy_ulpi_ddr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&nbsp;</td>
+          <td class="paramname"> <em>val</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Specifies whether the ULPI operates at double or single data rate. 
+<p>
+This parameter is only applicable if PHY_TYPE is ULPI.<p>
+0 - single data rate ULPI interface with 8 bit wide data bus (default) 1 - double data rate ULPI interface with 4 bit wide data bus 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l04665">4665</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="65d7407ed24c82e158a38ab2a60120c4"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_set_param_i2c_enable" ref="65d7407ed24c82e158a38ab2a60120c4" args="(dwc_otg_core_if_t *core_if, int32_t val)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_set_param_i2c_enable           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&nbsp;</td>
+          <td class="paramname"> <em>val</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Specifies whether to use the I2Cinterface for full speed PHY. 
+<p>
+This parameter is only applicable if PHY_TYPE is FS. 0 - No (default) 1 - Yes 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l04751">4751</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="16eec7b52e6a95825f91b7f60d58db50"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_set_param_dev_tx_fifo_size" ref="16eec7b52e6a95825f91b7f60d58db50" args="(dwc_otg_core_if_t *core_if, int fifo_num, int32_t val)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_set_param_dev_tx_fifo_size           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>fifo_num</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&nbsp;</td>
+          <td class="paramname"> <em>val</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Number of 4-byte words in each of the Tx FIFOs in device mode when dynamic FIFO sizing is enabled. 
+<p>
+4 to 768 (default 256) 
+</div>
+</div><p>
+<a class="anchor" name="f4a8cc5126f81ceb361294c7734737aa"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_dump_dev_registers" ref="f4a8cc5126f81ceb361294c7734737aa" args="(dwc_otg_core_if_t *_core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_dump_dev_registers           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Dump core registers and SPRAM. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l03347">3347</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="5b28e869ddc5a4c44d8669b6423b414e"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_dump_spram" ref="5b28e869ddc5a4c44d8669b6423b414e" args="(dwc_otg_core_if_t *_core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_dump_spram           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This functions reads the SPRAM and prints its content. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l03477">3477</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="a4c7a094e7c6eb2d28103e787ff09934"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_dump_host_registers" ref="a4c7a094e7c6eb2d28103e787ff09934" args="(dwc_otg_core_if_t *_core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_dump_host_registers           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function reads the host registers and prints them. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l03505">3505</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="814be5b2f30d8321f7152fe897799224"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_dump_global_registers" ref="814be5b2f30d8321f7152fe897799224" args="(dwc_otg_core_if_t *_core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_dump_global_registers           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function reads the core global registers and prints them. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l03573">3573</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="788149caf9d915abbe5e289793684b1e"></a><!-- doxytag: member="dwc_otg_core_if.h::dwc_otg_get_mode" ref="788149caf9d915abbe5e289793684b1e" args="(dwc_otg_core_if_t *core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t dwc_otg_get_mode           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Get current mode. 
+<p>
+Returns 0 if in device mode, and 1 if in host mode. 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8c-source.html#l05115">5115</a> of file <a class="el" href="dwc__otg__cil_8c-source.html">dwc_otg_cil.c</a>.
+</div>
+</div><p>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/dwc__otg__dbg_8h-source.html b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__dbg_8h-source.html
new file mode 100644
index 000000000000..824e31765117
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__dbg_8h-source.html
@@ -0,0 +1,100 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_dbg.h Source File</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<h1>dwc_otg_dbg.h</h1><a href="dwc__otg__dbg_8h.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">/* ==========================================================================</span>
+<a name="l00002"></a>00002 <span class="comment"> *</span>
+<a name="l00003"></a>00003 <span class="comment"> * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,</span>
+<a name="l00004"></a>00004 <span class="comment"> * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless</span>
+<a name="l00005"></a>00005 <span class="comment"> * otherwise expressly agreed to in writing between Synopsys and you.</span>
+<a name="l00006"></a>00006 <span class="comment"> * </span>
+<a name="l00007"></a>00007 <span class="comment"> * The Software IS NOT an item of Licensed Software or Licensed Product under</span>
+<a name="l00008"></a>00008 <span class="comment"> * any End User Software License Agreement or Agreement for Licensed Product</span>
+<a name="l00009"></a>00009 <span class="comment"> * with Synopsys or any supplement thereto. You are permitted to use and</span>
+<a name="l00010"></a>00010 <span class="comment"> * redistribute this Software in source and binary forms, with or without</span>
+<a name="l00011"></a>00011 <span class="comment"> * modification, provided that redistributions of source code must retain this</span>
+<a name="l00012"></a>00012 <span class="comment"> * notice. You may not view, use, disclose, copy or distribute this file or</span>
+<a name="l00013"></a>00013 <span class="comment"> * any information contained herein except pursuant to this license grant from</span>
+<a name="l00014"></a>00014 <span class="comment"> * Synopsys. If you do not agree with this notice, including the disclaimer</span>
+<a name="l00015"></a>00015 <span class="comment"> * below, then you are not authorized to use the Software.</span>
+<a name="l00016"></a>00016 <span class="comment"> * </span>
+<a name="l00017"></a>00017 <span class="comment"> * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS</span>
+<a name="l00018"></a>00018 <span class="comment"> * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE</span>
+<a name="l00019"></a>00019 <span class="comment"> * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE</span>
+<a name="l00020"></a>00020 <span class="comment"> * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,</span>
+<a name="l00021"></a>00021 <span class="comment"> * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES</span>
+<a name="l00022"></a>00022 <span class="comment"> * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR</span>
+<a name="l00023"></a>00023 <span class="comment"> * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER</span>
+<a name="l00024"></a>00024 <span class="comment"> * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT</span>
+<a name="l00025"></a>00025 <span class="comment"> * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY</span>
+<a name="l00026"></a>00026 <span class="comment"> * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH</span>
+<a name="l00027"></a>00027 <span class="comment"> * DAMAGE.</span>
+<a name="l00028"></a>00028 <span class="comment"> * ========================================================================== */</span>
+<a name="l00029"></a>00029 
+<a name="l00030"></a>00030 <span class="preprocessor">#ifndef __DWC_OTG_DBG_H__</span>
+<a name="l00031"></a>00031 <span class="preprocessor"></span><span class="preprocessor">#define __DWC_OTG_DBG_H__</span>
+<a name="l00032"></a>00032 <span class="preprocessor"></span>
+<a name="l00041"></a>00041 <span class="keyword">extern</span> uint32_t <a class="code" href="dwc__otg__dbg_8h.html#7ef4ada2ebb5f1aadf3be4d7fbf8ce62">g_dbg_lvl</a>;
+<a name="l00045"></a><a class="code" href="dwc__otg__dbg_8h.html#68eadfdf7a6a3f2eed00492119b00bae">00045</a> <span class="keyword">static</span> <span class="keyword">inline</span> uint32_t <a class="code" href="dwc__otg__dbg_8h.html#68eadfdf7a6a3f2eed00492119b00bae">SET_DEBUG_LEVEL</a>(<span class="keyword">const</span> uint32_t <span class="keyword">new</span>)
+<a name="l00046"></a>00046 {
+<a name="l00047"></a>00047         uint32_t old = <a class="code" href="dwc__otg__dbg_8h.html#7ef4ada2ebb5f1aadf3be4d7fbf8ce62">g_dbg_lvl</a>;
+<a name="l00048"></a>00048         <a class="code" href="dwc__otg__dbg_8h.html#7ef4ada2ebb5f1aadf3be4d7fbf8ce62">g_dbg_lvl</a> = <span class="keyword">new</span>;
+<a name="l00049"></a>00049         <span class="keywordflow">return</span> old;
+<a name="l00050"></a>00050 }
+<a name="l00051"></a>00051 
+<a name="l00053"></a><a class="code" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">00053</a> <span class="preprocessor">#define DBG_CIL         (0x2)</span>
+<a name="l00054"></a>00054 <span class="preprocessor"></span>
+<a name="l00056"></a><a class="code" href="dwc__otg__dbg_8h.html#daab8e158c0c530486656ef52e5b0bbe">00056</a> <span class="preprocessor">#define DBG_CILV        (0x20)</span>
+<a name="l00057"></a>00057 <span class="preprocessor"></span>
+<a name="l00059"></a><a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">00059</a> <span class="preprocessor">#define DBG_PCD         (0x4)</span>
+<a name="l00060"></a>00060 <span class="preprocessor"></span>
+<a name="l00062"></a><a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">00062</a> <span class="preprocessor">#define DBG_PCDV        (0x40)</span>
+<a name="l00063"></a>00063 <span class="preprocessor"></span>
+<a name="l00064"></a><a class="code" href="dwc__otg__dbg_8h.html#e4a050e176c1c4f556da2b276a8c2b37">00064</a> <span class="preprocessor">#define DBG_HCD         (0x8)</span>
+<a name="l00065"></a>00065 <span class="preprocessor"></span>
+<a name="l00067"></a><a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">00067</a> <span class="preprocessor">#define DBG_HCDV        (0x80)</span>
+<a name="l00068"></a>00068 <span class="preprocessor"></span>
+<a name="l00070"></a><a class="code" href="dwc__otg__dbg_8h.html#737e22e02729647d12db8e3059ad06c9">00070</a> <span class="preprocessor">#define DBG_HCD_URB     (0x800)</span>
+<a name="l00071"></a>00071 <span class="preprocessor"></span>
+<a name="l00073"></a><a class="code" href="dwc__otg__dbg_8h.html#2bf62a567355d1ea38814714bd7b57ec">00073</a> <span class="preprocessor">#define DBG_ANY         (0xFF)</span>
+<a name="l00074"></a>00074 <span class="preprocessor"></span>
+<a name="l00076"></a><a class="code" href="dwc__otg__dbg_8h.html#7d413cde1d2543d2c3447e890868f800">00076</a> <span class="preprocessor">#define DBG_OFF         0</span>
+<a name="l00077"></a>00077 <span class="preprocessor"></span>
+<a name="l00079"></a><a class="code" href="dwc__otg__dbg_8h.html#c1cdef6b622b17c7bb2d2574c6b66e0c">00079</a> <span class="preprocessor">#define USB_DWC "DWC_otg: "</span>
+<a name="l00080"></a>00080 <span class="preprocessor"></span>
+<a name="l00098"></a>00098 <span class="preprocessor">#ifdef DEBUG</span>
+<a name="l00099"></a>00099 <span class="preprocessor"></span>
+<a name="l00100"></a>00100 <span class="preprocessor"># define DWC_DEBUGPL(lvl, x...) do{ if ((lvl)&amp;g_dbg_lvl)__DWC_DEBUG(USB_DWC x ); }while(0)</span>
+<a name="l00101"></a>00101 <span class="preprocessor"></span><span class="preprocessor"># define DWC_DEBUGP(x...)       DWC_DEBUGPL(DBG_ANY, x )</span>
+<a name="l00102"></a>00102 <span class="preprocessor"></span>
+<a name="l00103"></a>00103 <span class="preprocessor"># define CHK_DEBUG_LEVEL(level) ((level) &amp; g_dbg_lvl)</span>
+<a name="l00104"></a>00104 <span class="preprocessor"></span>
+<a name="l00105"></a>00105 <span class="preprocessor">#else</span>
+<a name="l00106"></a>00106 <span class="preprocessor"></span>
+<a name="l00107"></a><a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">00107</a> <span class="preprocessor"># define DWC_DEBUGPL(lvl, x...) do{}while(0)</span>
+<a name="l00108"></a><a class="code" href="dwc__otg__dbg_8h.html#73c0407e149f78df1c16ef88afa1aa62">00108</a> <span class="preprocessor"></span><span class="preprocessor"># define DWC_DEBUGP(x...)</span>
+<a name="l00109"></a>00109 <span class="preprocessor"></span>
+<a name="l00110"></a><a class="code" href="dwc__otg__dbg_8h.html#7a96217c88a4d786f6cb3d4df09dee04">00110</a> <span class="preprocessor"># define CHK_DEBUG_LEVEL(level) (0)</span>
+<a name="l00111"></a>00111 <span class="preprocessor"></span>
+<a name="l00112"></a>00112 <span class="preprocessor">#endif </span><span class="comment">/*DEBUG*/</span>
+<a name="l00113"></a>00113 <span class="preprocessor">#endif</span>
+</pre></div><hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/dwc__otg__dbg_8h.html b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__dbg_8h.html
new file mode 100644
index 000000000000..7fef85df6f7b
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__dbg_8h.html
@@ -0,0 +1,133 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_dbg.h File Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<h1>dwc_otg_dbg.h File Reference</h1>This file defines debug levels. <a href="#_details">More...</a>
+<p>
+
+<p>
+<a href="dwc__otg__dbg_8h-source.html">Go to the source code of this file.</a><table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Defines</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="57840e6b35e0e469296fd2db46227b13"></a><!-- doxytag: member="dwc_otg_dbg.h::DBG_CIL" ref="57840e6b35e0e469296fd2db46227b13" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">DBG_CIL</a>&nbsp;&nbsp;&nbsp;(0x2)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">When debug level has the DBG_CIL bit set, display CIL Debug messages. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="daab8e158c0c530486656ef52e5b0bbe"></a><!-- doxytag: member="dwc_otg_dbg.h::DBG_CILV" ref="daab8e158c0c530486656ef52e5b0bbe" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__dbg_8h.html#daab8e158c0c530486656ef52e5b0bbe">DBG_CILV</a>&nbsp;&nbsp;&nbsp;(0x20)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">When debug level has the DBG_CILV bit set, display CIL Verbose debug messages. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b39e7fe4805812e8f65962134b45f48a"></a><!-- doxytag: member="dwc_otg_dbg.h::DBG_PCD" ref="b39e7fe4805812e8f65962134b45f48a" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>&nbsp;&nbsp;&nbsp;(0x4)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">When debug level has the DBG_PCD bit set, display PCD (Device) debug messages. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="fe60e047aac272899de8f63b43df80e7"></a><!-- doxytag: member="dwc_otg_dbg.h::DBG_PCDV" ref="fe60e047aac272899de8f63b43df80e7" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>&nbsp;&nbsp;&nbsp;(0x40)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">When debug level has the DBG_PCDV set, display PCD (Device) Verbose debug messages. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e4a050e176c1c4f556da2b276a8c2b37"></a><!-- doxytag: member="dwc_otg_dbg.h::DBG_HCD" ref="e4a050e176c1c4f556da2b276a8c2b37" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__dbg_8h.html#e4a050e176c1c4f556da2b276a8c2b37">DBG_HCD</a>&nbsp;&nbsp;&nbsp;(0x8)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">When debug level has the DBG_HCD bit set, display Host debug messages. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="39931d908ba215b3d5d590e42d8408b5"></a><!-- doxytag: member="dwc_otg_dbg.h::DBG_HCDV" ref="39931d908ba215b3d5d590e42d8408b5" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>&nbsp;&nbsp;&nbsp;(0x80)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">When debug level has the DBG_HCDV bit set, display Verbose Host debug messages. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="737e22e02729647d12db8e3059ad06c9"></a><!-- doxytag: member="dwc_otg_dbg.h::DBG_HCD_URB" ref="737e22e02729647d12db8e3059ad06c9" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__dbg_8h.html#737e22e02729647d12db8e3059ad06c9">DBG_HCD_URB</a>&nbsp;&nbsp;&nbsp;(0x800)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">When debug level has the DBG_HCD_URB bit set, display enqueued URBs in host mode. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="2bf62a567355d1ea38814714bd7b57ec"></a><!-- doxytag: member="dwc_otg_dbg.h::DBG_ANY" ref="2bf62a567355d1ea38814714bd7b57ec" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__dbg_8h.html#2bf62a567355d1ea38814714bd7b57ec">DBG_ANY</a>&nbsp;&nbsp;&nbsp;(0xFF)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">When debug level has any bit set, display debug messages. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7d413cde1d2543d2c3447e890868f800"></a><!-- doxytag: member="dwc_otg_dbg.h::DBG_OFF" ref="7d413cde1d2543d2c3447e890868f800" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__dbg_8h.html#7d413cde1d2543d2c3447e890868f800">DBG_OFF</a>&nbsp;&nbsp;&nbsp;0</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">All debug messages off. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c1cdef6b622b17c7bb2d2574c6b66e0c"></a><!-- doxytag: member="dwc_otg_dbg.h::USB_DWC" ref="c1cdef6b622b17c7bb2d2574c6b66e0c" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__dbg_8h.html#c1cdef6b622b17c7bb2d2574c6b66e0c">USB_DWC</a>&nbsp;&nbsp;&nbsp;&quot;DWC_otg: &quot;</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Prefix string for DWC_DEBUG print macros. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(lvl, x...)&nbsp;&nbsp;&nbsp;do{}while(0)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Print a debug message when the Global debug level variable contains the bit defined in <code>lvl</code>.  <a href="#ed38f5a57cb756e97a17c0926cc9a10e"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="73c0407e149f78df1c16ef88afa1aa62"></a><!-- doxytag: member="dwc_otg_dbg.h::DWC_DEBUGP" ref="73c0407e149f78df1c16ef88afa1aa62" args="(x...)" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__dbg_8h.html#73c0407e149f78df1c16ef88afa1aa62">DWC_DEBUGP</a>(x...)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7a96217c88a4d786f6cb3d4df09dee04"></a><!-- doxytag: member="dwc_otg_dbg.h::CHK_DEBUG_LEVEL" ref="7a96217c88a4d786f6cb3d4df09dee04" args="(level)" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__dbg_8h.html#7a96217c88a4d786f6cb3d4df09dee04">CHK_DEBUG_LEVEL</a>(level)&nbsp;&nbsp;&nbsp;(0)</td></tr>
+
+<tr><td colspan="2"><br><h2>Functions</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="68eadfdf7a6a3f2eed00492119b00bae"></a><!-- doxytag: member="dwc_otg_dbg.h::SET_DEBUG_LEVEL" ref="68eadfdf7a6a3f2eed00492119b00bae" args="(const uint32_t new)" -->
+static uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__dbg_8h.html#68eadfdf7a6a3f2eed00492119b00bae">SET_DEBUG_LEVEL</a> (const uint32_t new)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Set the Debug Level variable. <br></td></tr>
+<tr><td colspan="2"><br><h2>Variables</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7ef4ada2ebb5f1aadf3be4d7fbf8ce62"></a><!-- doxytag: member="dwc_otg_dbg.h::g_dbg_lvl" ref="7ef4ada2ebb5f1aadf3be4d7fbf8ce62" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__dbg_8h.html#7ef4ada2ebb5f1aadf3be4d7fbf8ce62">g_dbg_lvl</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">The Debug Level bit-mask variable. <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This file defines debug levels. 
+<p>
+Debugging support vanishes in non-debug builds. 
+<p>
+Definition in file <a class="el" href="dwc__otg__dbg_8h-source.html">dwc_otg_dbg.h</a>.<hr><h2>Define Documentation</h2>
+<a class="anchor" name="ed38f5a57cb756e97a17c0926cc9a10e"></a><!-- doxytag: member="dwc_otg_dbg.h::DWC_DEBUGPL" ref="ed38f5a57cb756e97a17c0926cc9a10e" args="(lvl, x...)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define DWC_DEBUGPL          </td>
+          <td>(</td>
+          <td class="paramtype">lvl,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">x...&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%">&nbsp;&nbsp;&nbsp;do{}while(0)</td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Print a debug message when the Global debug level variable contains the bit defined in <code>lvl</code>. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"><tt>[in]</tt>&nbsp;</td><td valign="top"><em>lvl</em>&nbsp;</td><td>- Debug level, use one of the DBG_ constants above. </td></tr>
+    <tr><td valign="top"><tt>[in]</tt>&nbsp;</td><td valign="top"><em>x</em>&nbsp;</td><td>- like printf</td></tr>
+  </table>
+</dl>
+Example:<p>
+<code> DWC_DEBUGPL( DBG_ANY, "%s(%p)\n", __func__, _reg_base_addr); </code> <br>
+ results in:<br>
+ <code> usb-DWC_otg: dwc_otg_cil_init(ca867000) </code> 
+<p>
+Definition at line <a class="el" href="dwc__otg__dbg_8h-source.html#l00107">107</a> of file <a class="el" href="dwc__otg__dbg_8h-source.html">dwc_otg_dbg.h</a>.
+</div>
+</div><p>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/dwc__otg__driver_8c-source.html b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__driver_8c-source.html
new file mode 100644
index 000000000000..850bcb593382
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__driver_8c-source.html
@@ -0,0 +1,1079 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_driver.c Source File</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<h1>dwc_otg_driver.c</h1><a href="dwc__otg__driver_8c.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">/* ==========================================================================</span>
+<a name="l00002"></a>00002 <span class="comment"> * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.c $</span>
+<a name="l00003"></a>00003 <span class="comment"> * $Revision: #76 $</span>
+<a name="l00004"></a>00004 <span class="comment"> * $Date: 2009/05/03 $</span>
+<a name="l00005"></a>00005 <span class="comment"> * $Change: 1245589 $</span>
+<a name="l00006"></a>00006 <span class="comment"> *</span>
+<a name="l00007"></a>00007 <span class="comment"> * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,</span>
+<a name="l00008"></a>00008 <span class="comment"> * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless</span>
+<a name="l00009"></a>00009 <span class="comment"> * otherwise expressly agreed to in writing between Synopsys and you.</span>
+<a name="l00010"></a>00010 <span class="comment"> *</span>
+<a name="l00011"></a>00011 <span class="comment"> * The Software IS NOT an item of Licensed Software or Licensed Product under</span>
+<a name="l00012"></a>00012 <span class="comment"> * any End User Software License Agreement or Agreement for Licensed Product</span>
+<a name="l00013"></a>00013 <span class="comment"> * with Synopsys or any supplement thereto. You are permitted to use and</span>
+<a name="l00014"></a>00014 <span class="comment"> * redistribute this Software in source and binary forms, with or without</span>
+<a name="l00015"></a>00015 <span class="comment"> * modification, provided that redistributions of source code must retain this</span>
+<a name="l00016"></a>00016 <span class="comment"> * notice. You may not view, use, disclose, copy or distribute this file or</span>
+<a name="l00017"></a>00017 <span class="comment"> * any information contained herein except pursuant to this license grant from</span>
+<a name="l00018"></a>00018 <span class="comment"> * Synopsys. If you do not agree with this notice, including the disclaimer</span>
+<a name="l00019"></a>00019 <span class="comment"> * below, then you are not authorized to use the Software.</span>
+<a name="l00020"></a>00020 <span class="comment"> *</span>
+<a name="l00021"></a>00021 <span class="comment"> * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS</span>
+<a name="l00022"></a>00022 <span class="comment"> * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE</span>
+<a name="l00023"></a>00023 <span class="comment"> * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE</span>
+<a name="l00024"></a>00024 <span class="comment"> * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,</span>
+<a name="l00025"></a>00025 <span class="comment"> * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES</span>
+<a name="l00026"></a>00026 <span class="comment"> * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR</span>
+<a name="l00027"></a>00027 <span class="comment"> * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER</span>
+<a name="l00028"></a>00028 <span class="comment"> * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT</span>
+<a name="l00029"></a>00029 <span class="comment"> * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY</span>
+<a name="l00030"></a>00030 <span class="comment"> * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH</span>
+<a name="l00031"></a>00031 <span class="comment"> * DAMAGE.</span>
+<a name="l00032"></a>00032 <span class="comment"> * ========================================================================== */</span>
+<a name="l00033"></a>00033 
+<a name="l00051"></a>00051 <span class="preprocessor">#include &lt;linux/kernel.h&gt;</span>
+<a name="l00052"></a>00052 <span class="preprocessor">#include &lt;linux/module.h&gt;</span>
+<a name="l00053"></a>00053 <span class="preprocessor">#include &lt;linux/moduleparam.h&gt;</span>
+<a name="l00054"></a>00054 <span class="preprocessor">#include &lt;linux/init.h&gt;</span>
+<a name="l00055"></a>00055 <span class="preprocessor">#include &lt;linux/device.h&gt;</span>
+<a name="l00056"></a>00056 <span class="preprocessor">#include &lt;linux/errno.h&gt;</span>
+<a name="l00057"></a>00057 <span class="preprocessor">#include &lt;linux/types.h&gt;</span>
+<a name="l00058"></a>00058 <span class="preprocessor">#include &lt;linux/stat.h&gt;</span>         <span class="comment">/* permission constants */</span>
+<a name="l00059"></a>00059 <span class="preprocessor">#include &lt;linux/version.h&gt;</span>
+<a name="l00060"></a>00060 <span class="preprocessor">#include &lt;linux/interrupt.h&gt;</span>
+<a name="l00061"></a>00061 
+<a name="l00062"></a>00062 <span class="preprocessor">#ifdef LM_INTERFACE</span>
+<a name="l00063"></a>00063 <span class="preprocessor"></span><span class="preprocessor">#include &lt;asm/arch/regs-irq.h&gt;</span>
+<a name="l00064"></a>00064 <span class="preprocessor">#include &lt;asm/arch/lm.h&gt;</span>
+<a name="l00065"></a>00065 <span class="preprocessor">#include &lt;asm/sizes.h&gt;</span>
+<a name="l00066"></a>00066 <span class="preprocessor">#endif</span>
+<a name="l00067"></a>00067 <span class="preprocessor"></span>
+<a name="l00068"></a>00068 <span class="preprocessor"># include &lt;linux/irq.h&gt;</span>
+<a name="l00069"></a>00069 
+<a name="l00070"></a>00070 <span class="preprocessor">#include &lt;asm/io.h&gt;</span>
+<a name="l00071"></a>00071 
+<a name="l00072"></a>00072 
+<a name="l00073"></a>00073 <span class="preprocessor">#include "dwc_os.h"</span>
+<a name="l00074"></a>00074 <span class="preprocessor">#include "<a class="code" href="dwc__otg__dbg_8h.html">dwc_otg_dbg.h</a>"</span>
+<a name="l00075"></a>00075 <span class="preprocessor">#include "<a class="code" href="dwc__otg__driver_8h.html">dwc_otg_driver.h</a>"</span>
+<a name="l00076"></a>00076 <span class="preprocessor">#include "<a class="code" href="dwc__otg__attr_8h.html">dwc_otg_attr.h</a>"</span>
+<a name="l00077"></a>00077 <span class="preprocessor">#include "<a class="code" href="dwc__otg__core__if_8h.html">dwc_otg_core_if.h</a>"</span>
+<a name="l00078"></a>00078 <span class="preprocessor">#include "<a class="code" href="dwc__otg__pcd__if_8h.html">dwc_otg_pcd_if.h</a>"</span>
+<a name="l00079"></a>00079 <span class="preprocessor">#include "<a class="code" href="dwc__otg__hcd__if_8h.html">dwc_otg_hcd_if.h</a>"</span>
+<a name="l00080"></a>00080 
+<a name="l00081"></a><a class="code" href="dwc__otg__driver_8c.html#7fb7b6d344624c19c1d920239458999a">00081</a> <span class="preprocessor">#define DWC_DRIVER_VERSION      "2.90a 23-APR-2009"</span>
+<a name="l00082"></a><a class="code" href="dwc__otg__driver_8c.html#d78dec8459bcb2092d84be524494378b">00082</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_DRIVER_DESC         "HS OTG USB Controller driver"</span>
+<a name="l00083"></a>00083 <span class="preprocessor"></span>
+<a name="l00084"></a><a class="code" href="dwc__otg__driver_8c.html#3f7932dcd77bb7b05f92f759e6569fe2">00084</a> <span class="keyword">static</span> <span class="keyword">const</span> <span class="keywordtype">char</span> <a class="code" href="dwc__otg__driver_8c.html#3f7932dcd77bb7b05f92f759e6569fe2">dwc_driver_name</a>[] = <span class="stringliteral">"dwc_otg"</span>;
+<a name="l00085"></a>00085 
+<a name="l00086"></a>00086 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__driver_8c.html#9dbc565a7942db0adbf1ec341db22901">pcd_init</a>(
+<a name="l00087"></a>00087 #ifdef LM_INTERFACE
+<a name="l00088"></a>00088         <span class="keyword">struct</span> lm_device *_dev
+<a name="l00089"></a>00089 #elif  PCI_INTERFACE
+<a name="l00090"></a>00090         <span class="keyword">struct</span> pci_dev *_dev
+<a name="l00091"></a>00091 #endif
+<a name="l00092"></a>00092         );
+<a name="l00093"></a>00093 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__driver_8c.html#ab12cdf65bf4ed68545a6c17cc31269f">hcd_init</a>(
+<a name="l00094"></a>00094 #ifdef LM_INTERFACE
+<a name="l00095"></a>00095         <span class="keyword">struct</span> lm_device *_dev
+<a name="l00096"></a>00096 #elif  PCI_INTERFACE
+<a name="l00097"></a>00097         <span class="keyword">struct</span> pci_dev *_dev
+<a name="l00098"></a>00098 #endif
+<a name="l00099"></a>00099         );
+<a name="l00100"></a>00100 
+<a name="l00101"></a>00101 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__driver_8c.html#7960b8e2c02d9ab89b65cb01ba08658b">pcd_remove</a>(
+<a name="l00102"></a>00102 #ifdef LM_INTERFACE
+<a name="l00103"></a>00103         <span class="keyword">struct</span> lm_device *_dev
+<a name="l00104"></a>00104 #elif  PCI_INTERFACE
+<a name="l00105"></a>00105         <span class="keyword">struct</span> pci_dev *_dev
+<a name="l00106"></a>00106 #endif
+<a name="l00107"></a>00107         );
+<a name="l00108"></a>00108 
+<a name="l00109"></a>00109 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__driver_8c.html#f36193b3ff33c0473956c8a15eee4f5b">hcd_remove</a>(
+<a name="l00110"></a>00110 #ifdef LM_INTERFACE
+<a name="l00111"></a>00111         <span class="keyword">struct</span> lm_device *_dev
+<a name="l00112"></a>00112 #elif  PCI_INTERFACE
+<a name="l00113"></a>00113         <span class="keyword">struct</span> pci_dev *_dev
+<a name="l00114"></a>00114 #endif
+<a name="l00115"></a>00115         );
+<a name="l00116"></a>00116 
+<a name="l00117"></a>00117 <span class="comment">/*-------------------------------------------------------------------------*/</span>
+<a name="l00118"></a>00118 <span class="comment">/* Encapsulate the module parameter settings */</span>
+<a name="l00119"></a>00119 
+<a name="l00120"></a><a class="code" href="structdwc__otg__driver__module__params.html">00120</a> <span class="keyword">struct </span><a class="code" href="structdwc__otg__driver__module__params.html">dwc_otg_driver_module_params</a> {
+<a name="l00121"></a><a class="code" href="structdwc__otg__driver__module__params.html#bccaf8d2ce8da6d5ef0d1c81caf9e518">00121</a>         int32_t <a class="code" href="structdwc__otg__driver__module__params.html#bccaf8d2ce8da6d5ef0d1c81caf9e518">opt</a>;
+<a name="l00122"></a><a class="code" href="structdwc__otg__driver__module__params.html#985f1849ab70919e756c86280a8f7ef0">00122</a>         int32_t <a class="code" href="structdwc__otg__driver__module__params.html#985f1849ab70919e756c86280a8f7ef0">otg_cap</a>;
+<a name="l00123"></a><a class="code" href="structdwc__otg__driver__module__params.html#fe4469605ca0460a3e309603d7c23e86">00123</a>         int32_t <a class="code" href="structdwc__otg__driver__module__params.html#fe4469605ca0460a3e309603d7c23e86">dma_enable</a>;
+<a name="l00124"></a><a class="code" href="structdwc__otg__driver__module__params.html#cdceee2a19bb233c12893751f443c40d">00124</a>         int32_t <a class="code" href="structdwc__otg__driver__module__params.html#cdceee2a19bb233c12893751f443c40d">dma_desc_enable</a>;
+<a name="l00125"></a><a class="code" href="structdwc__otg__driver__module__params.html#19c1567261677aa53120cfae53b90f8d">00125</a>         int32_t <a class="code" href="structdwc__otg__driver__module__params.html#19c1567261677aa53120cfae53b90f8d">dma_burst_size</a>;
+<a name="l00126"></a><a class="code" href="structdwc__otg__driver__module__params.html#e0002437cefb2b64dc92f40fd69ef29f">00126</a>         int32_t <a class="code" href="structdwc__otg__driver__module__params.html#e0002437cefb2b64dc92f40fd69ef29f">speed</a>;
+<a name="l00127"></a><a class="code" href="structdwc__otg__driver__module__params.html#6f3a0a2bf5c82d296fec31fec7b765ca">00127</a>         int32_t <a class="code" href="structdwc__otg__driver__module__params.html#6f3a0a2bf5c82d296fec31fec7b765ca">host_support_fs_ls_low_power</a>;
+<a name="l00128"></a><a class="code" href="structdwc__otg__driver__module__params.html#91c46e96e070e983e3f91c756dd4aa64">00128</a>         int32_t <a class="code" href="structdwc__otg__driver__module__params.html#91c46e96e070e983e3f91c756dd4aa64">host_ls_low_power_phy_clk</a>;
+<a name="l00129"></a><a class="code" href="structdwc__otg__driver__module__params.html#f448f6de6dcafca027bd2873b714b916">00129</a>         int32_t <a class="code" href="structdwc__otg__driver__module__params.html#f448f6de6dcafca027bd2873b714b916">enable_dynamic_fifo</a>;
+<a name="l00130"></a><a class="code" href="structdwc__otg__driver__module__params.html#a9ae5039d88c52fab455235bf4f8696b">00130</a>         int32_t <a class="code" href="structdwc__otg__driver__module__params.html#a9ae5039d88c52fab455235bf4f8696b">data_fifo_size</a>;
+<a name="l00131"></a><a class="code" href="structdwc__otg__driver__module__params.html#707eedd2d7794728c5188e5d5056316e">00131</a>         int32_t <a class="code" href="structdwc__otg__driver__module__params.html#707eedd2d7794728c5188e5d5056316e">dev_rx_fifo_size</a>;
+<a name="l00132"></a><a class="code" href="structdwc__otg__driver__module__params.html#3172175dc8f08e96b63c7a8c162201f5">00132</a>         int32_t <a class="code" href="structdwc__otg__driver__module__params.html#3172175dc8f08e96b63c7a8c162201f5">dev_nperio_tx_fifo_size</a>;
+<a name="l00133"></a><a class="code" href="structdwc__otg__driver__module__params.html#aada52f0668d5d52b8ac6281c8736283">00133</a>         uint32_t <a class="code" href="structdwc__otg__driver__module__params.html#aada52f0668d5d52b8ac6281c8736283">dev_perio_tx_fifo_size</a>[<a class="code" href="dwc__otg__core__if_8h.html#13bb22067644d357537c2905fe5ffb8c">MAX_PERIO_FIFOS</a>];
+<a name="l00134"></a><a class="code" href="structdwc__otg__driver__module__params.html#1f490daab4c4e08d2773f46d51f1f5f7">00134</a>         int32_t <a class="code" href="structdwc__otg__driver__module__params.html#1f490daab4c4e08d2773f46d51f1f5f7">host_rx_fifo_size</a>;
+<a name="l00135"></a><a class="code" href="structdwc__otg__driver__module__params.html#edf2038417f58acd8dab202a8ca19d2a">00135</a>         int32_t <a class="code" href="structdwc__otg__driver__module__params.html#edf2038417f58acd8dab202a8ca19d2a">host_nperio_tx_fifo_size</a>;
+<a name="l00136"></a><a class="code" href="structdwc__otg__driver__module__params.html#bdc820350ca3b6aec5ac435c9712ccd5">00136</a>         int32_t <a class="code" href="structdwc__otg__driver__module__params.html#bdc820350ca3b6aec5ac435c9712ccd5">host_perio_tx_fifo_size</a>;
+<a name="l00137"></a><a class="code" href="structdwc__otg__driver__module__params.html#16cc5351ae1dfbcd81d56a7ec16e1748">00137</a>         int32_t <a class="code" href="structdwc__otg__driver__module__params.html#16cc5351ae1dfbcd81d56a7ec16e1748">max_transfer_size</a>;
+<a name="l00138"></a><a class="code" href="structdwc__otg__driver__module__params.html#bb7904edc790fce40ac04ed68a64217e">00138</a>         int32_t <a class="code" href="structdwc__otg__driver__module__params.html#bb7904edc790fce40ac04ed68a64217e">max_packet_count</a>;
+<a name="l00139"></a><a class="code" href="structdwc__otg__driver__module__params.html#4727585082d86c52396adfde0cfffa17">00139</a>         int32_t <a class="code" href="structdwc__otg__driver__module__params.html#4727585082d86c52396adfde0cfffa17">host_channels</a>;
+<a name="l00140"></a><a class="code" href="structdwc__otg__driver__module__params.html#c1c36daec6af25fb425c85a696c445e4">00140</a>         int32_t <a class="code" href="structdwc__otg__driver__module__params.html#c1c36daec6af25fb425c85a696c445e4">dev_endpoints</a>;
+<a name="l00141"></a><a class="code" href="structdwc__otg__driver__module__params.html#77d1c10524440ed2e5189624157526ac">00141</a>         int32_t <a class="code" href="structdwc__otg__driver__module__params.html#77d1c10524440ed2e5189624157526ac">phy_type</a>;
+<a name="l00142"></a><a class="code" href="structdwc__otg__driver__module__params.html#f6284c33f13fe2f02491fa1a0c479b25">00142</a>         int32_t <a class="code" href="structdwc__otg__driver__module__params.html#f6284c33f13fe2f02491fa1a0c479b25">phy_utmi_width</a>;
+<a name="l00143"></a><a class="code" href="structdwc__otg__driver__module__params.html#6a2b8c0c6298a7b1da23d5dd5abc4da8">00143</a>         int32_t <a class="code" href="structdwc__otg__driver__module__params.html#6a2b8c0c6298a7b1da23d5dd5abc4da8">phy_ulpi_ddr</a>;
+<a name="l00144"></a><a class="code" href="structdwc__otg__driver__module__params.html#8402de29e6ec24baa5881cb7d74914c2">00144</a>         int32_t <a class="code" href="structdwc__otg__driver__module__params.html#8402de29e6ec24baa5881cb7d74914c2">phy_ulpi_ext_vbus</a>;
+<a name="l00145"></a><a class="code" href="structdwc__otg__driver__module__params.html#4e1d822cfcc6332fcaa0471bb1ca0d54">00145</a>         int32_t <a class="code" href="structdwc__otg__driver__module__params.html#4e1d822cfcc6332fcaa0471bb1ca0d54">i2c_enable</a>;
+<a name="l00146"></a><a class="code" href="structdwc__otg__driver__module__params.html#33489751a5cef9e462d26e92caae3031">00146</a>         int32_t <a class="code" href="structdwc__otg__driver__module__params.html#33489751a5cef9e462d26e92caae3031">ulpi_fs_ls</a>;
+<a name="l00147"></a><a class="code" href="structdwc__otg__driver__module__params.html#25f8f9c3558aa01fecf8bcd1527ee6cc">00147</a>         int32_t <a class="code" href="structdwc__otg__driver__module__params.html#25f8f9c3558aa01fecf8bcd1527ee6cc">ts_dline</a>;
+<a name="l00148"></a><a class="code" href="structdwc__otg__driver__module__params.html#13860bb2c8d23e40088703289e6ae835">00148</a>         int32_t <a class="code" href="structdwc__otg__driver__module__params.html#13860bb2c8d23e40088703289e6ae835">en_multiple_tx_fifo</a>;
+<a name="l00149"></a><a class="code" href="structdwc__otg__driver__module__params.html#d1c3fbc5325b13e1191388b76795b848">00149</a>         uint32_t <a class="code" href="structdwc__otg__driver__module__params.html#d1c3fbc5325b13e1191388b76795b848">dev_tx_fifo_size</a>[<a class="code" href="dwc__otg__core__if_8h.html#050db6129005b993e573311dc42bc1a8">MAX_TX_FIFOS</a>];
+<a name="l00150"></a><a class="code" href="structdwc__otg__driver__module__params.html#7fe5c7ff692926fb5cbe3b10d4123594">00150</a>         uint32_t <a class="code" href="structdwc__otg__driver__module__params.html#7fe5c7ff692926fb5cbe3b10d4123594">thr_ctl</a>;
+<a name="l00151"></a><a class="code" href="structdwc__otg__driver__module__params.html#04d15f44d06c291acfeef82812bd1c65">00151</a>         uint32_t <a class="code" href="structdwc__otg__driver__module__params.html#04d15f44d06c291acfeef82812bd1c65">tx_thr_length</a>;
+<a name="l00152"></a><a class="code" href="structdwc__otg__driver__module__params.html#eecdc71dde5ce0543a04d541a90f79bc">00152</a>         uint32_t <a class="code" href="structdwc__otg__driver__module__params.html#eecdc71dde5ce0543a04d541a90f79bc">rx_thr_length</a>;
+<a name="l00153"></a><a class="code" href="structdwc__otg__driver__module__params.html#2e17f84d9b07732a7fdf37b13832c54a">00153</a>         int32_t <a class="code" href="structdwc__otg__driver__module__params.html#2e17f84d9b07732a7fdf37b13832c54a">pti_enable</a>;
+<a name="l00154"></a><a class="code" href="structdwc__otg__driver__module__params.html#484412984c814a6298b05b58d94bd730">00154</a>         int32_t <a class="code" href="structdwc__otg__driver__module__params.html#484412984c814a6298b05b58d94bd730">mpi_enable</a>;
+<a name="l00155"></a><a class="code" href="structdwc__otg__driver__module__params.html#bb4e33c533d53de007814f0e5a70dd8a">00155</a>         int32_t <a class="code" href="structdwc__otg__driver__module__params.html#bb4e33c533d53de007814f0e5a70dd8a">lpm_enable</a>;
+<a name="l00156"></a><a class="code" href="structdwc__otg__driver__module__params.html#ed3802eea4e62cd79ef7d8701d45b506">00156</a>         int32_t <a class="code" href="structdwc__otg__driver__module__params.html#ed3802eea4e62cd79ef7d8701d45b506">ic_usb_cap</a>;
+<a name="l00157"></a><a class="code" href="structdwc__otg__driver__module__params.html#b450246efcbc087eb36b0979040162ca">00157</a>         int32_t <a class="code" href="structdwc__otg__driver__module__params.html#b450246efcbc087eb36b0979040162ca">ahb_thr_ratio</a>;
+<a name="l00158"></a>00158 };
+<a name="l00159"></a>00159 
+<a name="l00160"></a><a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">00160</a> <span class="keyword">static</span> <span class="keyword">struct </span><a class="code" href="structdwc__otg__driver__module__params.html">dwc_otg_driver_module_params</a> <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a> = {
+<a name="l00161"></a>00161         .<a class="code" href="structdwc__otg__driver__module__params.html#bccaf8d2ce8da6d5ef0d1c81caf9e518">opt</a> = -1,
+<a name="l00162"></a>00162         .otg_cap = -1,
+<a name="l00163"></a>00163         .dma_enable = -1,
+<a name="l00164"></a>00164         .dma_desc_enable = -1,
+<a name="l00165"></a>00165         .dma_burst_size = -1,
+<a name="l00166"></a>00166         .speed = -1,
+<a name="l00167"></a>00167         .host_support_fs_ls_low_power = -1,
+<a name="l00168"></a>00168         .host_ls_low_power_phy_clk = -1,
+<a name="l00169"></a>00169         .enable_dynamic_fifo = -1,
+<a name="l00170"></a>00170         .data_fifo_size = -1,
+<a name="l00171"></a>00171         .dev_rx_fifo_size = -1,
+<a name="l00172"></a>00172         .dev_nperio_tx_fifo_size = -1,
+<a name="l00173"></a>00173         .dev_perio_tx_fifo_size = {
+<a name="l00174"></a>00174                                    <span class="comment">/* dev_perio_tx_fifo_size_1 */</span>
+<a name="l00175"></a>00175                                    -1,
+<a name="l00176"></a>00176                                    -1,
+<a name="l00177"></a>00177                                    -1,
+<a name="l00178"></a>00178                                    -1,
+<a name="l00179"></a>00179                                    -1,
+<a name="l00180"></a>00180                                    -1,
+<a name="l00181"></a>00181                                    -1,
+<a name="l00182"></a>00182                                    -1,
+<a name="l00183"></a>00183                                    -1,
+<a name="l00184"></a>00184                                    -1,
+<a name="l00185"></a>00185                                    -1,
+<a name="l00186"></a>00186                                    -1,
+<a name="l00187"></a>00187                                    -1,
+<a name="l00188"></a>00188                                    -1,
+<a name="l00189"></a>00189                                    -1
+<a name="l00190"></a>00190                                    <span class="comment">/* 15 */</span>
+<a name="l00191"></a>00191                                    },
+<a name="l00192"></a>00192         .host_rx_fifo_size = -1,
+<a name="l00193"></a>00193         .host_nperio_tx_fifo_size = -1,
+<a name="l00194"></a>00194         .host_perio_tx_fifo_size = -1,
+<a name="l00195"></a>00195         .max_transfer_size = -1,
+<a name="l00196"></a>00196         .max_packet_count = -1,
+<a name="l00197"></a>00197         .host_channels = -1,
+<a name="l00198"></a>00198         .dev_endpoints = -1,
+<a name="l00199"></a>00199         .phy_type = -1,
+<a name="l00200"></a>00200         .phy_utmi_width = -1,
+<a name="l00201"></a>00201         .phy_ulpi_ddr = -1,
+<a name="l00202"></a>00202         .phy_ulpi_ext_vbus = -1,
+<a name="l00203"></a>00203         .i2c_enable = -1,
+<a name="l00204"></a>00204         .ulpi_fs_ls = -1,
+<a name="l00205"></a>00205         .ts_dline = -1,
+<a name="l00206"></a>00206         .en_multiple_tx_fifo = -1,
+<a name="l00207"></a>00207         .dev_tx_fifo_size = {
+<a name="l00208"></a>00208                              <span class="comment">/* dev_tx_fifo_size */</span>
+<a name="l00209"></a>00209                              -1,
+<a name="l00210"></a>00210                              -1,
+<a name="l00211"></a>00211                              -1,
+<a name="l00212"></a>00212                              -1,
+<a name="l00213"></a>00213                              -1,
+<a name="l00214"></a>00214                              -1,
+<a name="l00215"></a>00215                              -1,
+<a name="l00216"></a>00216                              -1,
+<a name="l00217"></a>00217                              -1,
+<a name="l00218"></a>00218                              -1,
+<a name="l00219"></a>00219                              -1,
+<a name="l00220"></a>00220                              -1,
+<a name="l00221"></a>00221                              -1,
+<a name="l00222"></a>00222                              -1,
+<a name="l00223"></a>00223                              -1
+<a name="l00224"></a>00224                              <span class="comment">/* 15 */</span>
+<a name="l00225"></a>00225                              },
+<a name="l00226"></a>00226         .thr_ctl = -1,
+<a name="l00227"></a>00227         .tx_thr_length = -1,
+<a name="l00228"></a>00228         .rx_thr_length = -1,
+<a name="l00229"></a>00229         .pti_enable = -1,
+<a name="l00230"></a>00230         .mpi_enable = -1,
+<a name="l00231"></a>00231         .lpm_enable = -1,
+<a name="l00232"></a>00232         .ic_usb_cap = -1,
+<a name="l00233"></a>00233         .ahb_thr_ratio = -1,
+<a name="l00234"></a>00234 };
+<a name="l00235"></a>00235 
+<a name="l00239"></a><a class="code" href="dwc__otg__driver_8c.html#6eaf4dedcf1df7eb80c48f1872212012">00239</a> <span class="keyword">static</span> ssize_t <a class="code" href="dwc__otg__driver_8c.html#6eaf4dedcf1df7eb80c48f1872212012">version_show</a>(<span class="keyword">struct</span> device_driver *dev, <span class="keywordtype">char</span> *buf)
+<a name="l00240"></a>00240 {
+<a name="l00241"></a>00241         <span class="keywordflow">return</span> snprintf(buf, <span class="keyword">sizeof</span>(<a class="code" href="dwc__otg__driver_8c.html#7fb7b6d344624c19c1d920239458999a">DWC_DRIVER_VERSION</a>) + 2, <span class="stringliteral">"%s\n"</span>,
+<a name="l00242"></a>00242                         DWC_DRIVER_VERSION);
+<a name="l00243"></a>00243 }
+<a name="l00244"></a>00244 
+<a name="l00245"></a>00245 <span class="keyword">static</span> DRIVER_ATTR(version, S_IRUGO, <a class="code" href="dwc__otg__driver_8c.html#6eaf4dedcf1df7eb80c48f1872212012">version_show</a>, NULL);
+<a name="l00246"></a>00246 
+<a name="l00250"></a><a class="code" href="dwc__otg__driver_8c.html#7ef4ada2ebb5f1aadf3be4d7fbf8ce62">00250</a> uint32_t <a class="code" href="dwc__otg__dbg_8h.html#7ef4ada2ebb5f1aadf3be4d7fbf8ce62">g_dbg_lvl</a> = 0;         <span class="comment">/* OFF */</span>
+<a name="l00251"></a>00251 
+<a name="l00255"></a><a class="code" href="dwc__otg__driver_8c.html#1e2b7516063b70cc1eaecc8d286b0689">00255</a> <span class="keyword">static</span> ssize_t <a class="code" href="dwc__otg__driver_8c.html#1e2b7516063b70cc1eaecc8d286b0689">dbg_level_show</a>(<span class="keyword">struct</span> device_driver *drv, <span class="keywordtype">char</span> *buf)
+<a name="l00256"></a>00256 {
+<a name="l00257"></a>00257         <span class="keywordflow">return</span> sprintf(buf, <span class="stringliteral">"0x%0x\n"</span>, <a class="code" href="dwc__otg__dbg_8h.html#7ef4ada2ebb5f1aadf3be4d7fbf8ce62">g_dbg_lvl</a>);
+<a name="l00258"></a>00258 }
+<a name="l00259"></a>00259 
+<a name="l00263"></a><a class="code" href="dwc__otg__driver_8c.html#e886456741506f66ce4adc5b843dc055">00263</a> <span class="keyword">static</span> ssize_t <a class="code" href="dwc__otg__driver_8c.html#e886456741506f66ce4adc5b843dc055">dbg_level_store</a>(<span class="keyword">struct</span> device_driver *drv, <span class="keyword">const</span> <span class="keywordtype">char</span> *buf,
+<a name="l00264"></a>00264                                size_t count)
+<a name="l00265"></a>00265 {
+<a name="l00266"></a>00266         <a class="code" href="dwc__otg__dbg_8h.html#7ef4ada2ebb5f1aadf3be4d7fbf8ce62">g_dbg_lvl</a> = simple_strtoul(buf, NULL, 16);
+<a name="l00267"></a>00267         <span class="keywordflow">return</span> count;
+<a name="l00268"></a>00268 }
+<a name="l00269"></a>00269 
+<a name="l00270"></a>00270 <span class="keyword">static</span> DRIVER_ATTR(debuglevel, S_IRUGO | <a class="code" href="dwc__otg__attr_8c.html#ac2308832629daf78cb9dd123551cd8a">S_IWUSR</a>, <a class="code" href="dwc__otg__driver_8c.html#1e2b7516063b70cc1eaecc8d286b0689">dbg_level_show</a>,
+<a name="l00271"></a>00271                    <a class="code" href="dwc__otg__driver_8c.html#e886456741506f66ce4adc5b843dc055">dbg_level_store</a>);
+<a name="l00272"></a>00272 
+<a name="l00277"></a><a class="code" href="dwc__otg__driver_8c.html#fe3a3765da365671b36ba5e28dc4d38b">00277</a> <span class="keyword">static</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__driver_8c.html#fe3a3765da365671b36ba5e28dc4d38b">set_parameters</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l00278"></a>00278 {
+<a name="l00279"></a>00279         <span class="keywordtype">int</span> retval = 0;
+<a name="l00280"></a>00280         <span class="keywordtype">int</span> i;
+<a name="l00281"></a>00281 
+<a name="l00282"></a>00282         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#985f1849ab70919e756c86280a8f7ef0">otg_cap</a> != -1) {
+<a name="l00283"></a>00283                 retval +=
+<a name="l00284"></a>00284                     <a class="code" href="dwc__otg__cil_8c.html#878cc478f43c58991c446bd78f50f8f0">dwc_otg_set_param_otg_cap</a>(core_if,
+<a name="l00285"></a>00285                                               <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#985f1849ab70919e756c86280a8f7ef0">otg_cap</a>);
+<a name="l00286"></a>00286         }
+<a name="l00287"></a>00287         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#fe4469605ca0460a3e309603d7c23e86">dma_enable</a> != -1) {
+<a name="l00288"></a>00288                 retval +=
+<a name="l00289"></a>00289                     <a class="code" href="dwc__otg__cil_8c.html#b4fbe11281b8200b70202d4e0048a9d7">dwc_otg_set_param_dma_enable</a>(core_if,
+<a name="l00290"></a>00290                                                  <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.
+<a name="l00291"></a>00291                                                  <a class="code" href="structdwc__otg__driver__module__params.html#fe4469605ca0460a3e309603d7c23e86">dma_enable</a>);
+<a name="l00292"></a>00292         }
+<a name="l00293"></a>00293         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#cdceee2a19bb233c12893751f443c40d">dma_desc_enable</a> != -1) {
+<a name="l00294"></a>00294                 retval +=
+<a name="l00295"></a>00295                     <a class="code" href="dwc__otg__cil_8c.html#7eae744525314774d3b390f116db126c">dwc_otg_set_param_dma_desc_enable</a>(core_if,
+<a name="l00296"></a>00296                                                       <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.
+<a name="l00297"></a>00297                                                       <a class="code" href="structdwc__otg__driver__module__params.html#cdceee2a19bb233c12893751f443c40d">dma_desc_enable</a>);
+<a name="l00298"></a>00298         }
+<a name="l00299"></a>00299         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#bccaf8d2ce8da6d5ef0d1c81caf9e518">opt</a> != -1) {
+<a name="l00300"></a>00300                 retval +=
+<a name="l00301"></a>00301                     <a class="code" href="dwc__otg__cil_8c.html#d0603b00a0ff87007ded1c06613d6b87">dwc_otg_set_param_opt</a>(core_if, <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#bccaf8d2ce8da6d5ef0d1c81caf9e518">opt</a>);
+<a name="l00302"></a>00302         }
+<a name="l00303"></a>00303         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#19c1567261677aa53120cfae53b90f8d">dma_burst_size</a> != -1) {
+<a name="l00304"></a>00304                 retval +=
+<a name="l00305"></a>00305                     <a class="code" href="dwc__otg__cil_8c.html#920035c6082dcdfec11a20e8535e9fe9">dwc_otg_set_param_dma_burst_size</a>(core_if,
+<a name="l00306"></a>00306                                                      <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.
+<a name="l00307"></a>00307                                                      <a class="code" href="structdwc__otg__driver__module__params.html#19c1567261677aa53120cfae53b90f8d">dma_burst_size</a>);
+<a name="l00308"></a>00308         }
+<a name="l00309"></a>00309         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#6f3a0a2bf5c82d296fec31fec7b765ca">host_support_fs_ls_low_power</a> != -1) {
+<a name="l00310"></a>00310                 retval +=
+<a name="l00311"></a>00311                     <a class="code" href="dwc__otg__cil_8c.html#8bd669637630521655c455c03d470e10">dwc_otg_set_param_host_support_fs_ls_low_power</a>(core_if,
+<a name="l00312"></a>00312                                                                    <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.
+<a name="l00313"></a>00313                                                                    <a class="code" href="structdwc__otg__driver__module__params.html#6f3a0a2bf5c82d296fec31fec7b765ca">host_support_fs_ls_low_power</a>);
+<a name="l00314"></a>00314         }
+<a name="l00315"></a>00315         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#f448f6de6dcafca027bd2873b714b916">enable_dynamic_fifo</a> != -1) {
+<a name="l00316"></a>00316                 retval +=
+<a name="l00317"></a>00317                     <a class="code" href="dwc__otg__cil_8c.html#61bb728cc80220e5173d5e3126dd4fd1">dwc_otg_set_param_enable_dynamic_fifo</a>(core_if,
+<a name="l00318"></a>00318                                                           <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.
+<a name="l00319"></a>00319                                                           <a class="code" href="structdwc__otg__driver__module__params.html#f448f6de6dcafca027bd2873b714b916">enable_dynamic_fifo</a>);
+<a name="l00320"></a>00320         }
+<a name="l00321"></a>00321         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#a9ae5039d88c52fab455235bf4f8696b">data_fifo_size</a> != -1) {
+<a name="l00322"></a>00322                 retval +=
+<a name="l00323"></a>00323                     <a class="code" href="dwc__otg__cil_8c.html#69d52c46eb236816b20675ecb57975ae">dwc_otg_set_param_data_fifo_size</a>(core_if,
+<a name="l00324"></a>00324                                                      <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.
+<a name="l00325"></a>00325                                                      <a class="code" href="structdwc__otg__driver__module__params.html#a9ae5039d88c52fab455235bf4f8696b">data_fifo_size</a>);
+<a name="l00326"></a>00326         }
+<a name="l00327"></a>00327         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#707eedd2d7794728c5188e5d5056316e">dev_rx_fifo_size</a> != -1) {
+<a name="l00328"></a>00328                 retval +=
+<a name="l00329"></a>00329                     <a class="code" href="dwc__otg__cil_8c.html#0fa4db196053869ac19832c03c62913f">dwc_otg_set_param_dev_rx_fifo_size</a>(core_if,
+<a name="l00330"></a>00330                                                        <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.
+<a name="l00331"></a>00331                                                        <a class="code" href="structdwc__otg__driver__module__params.html#707eedd2d7794728c5188e5d5056316e">dev_rx_fifo_size</a>);
+<a name="l00332"></a>00332         }
+<a name="l00333"></a>00333         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#3172175dc8f08e96b63c7a8c162201f5">dev_nperio_tx_fifo_size</a> != -1) {
+<a name="l00334"></a>00334                 retval +=
+<a name="l00335"></a>00335                     <a class="code" href="dwc__otg__cil_8c.html#4f7059cecabbf8cfe5014112ba9a3d42">dwc_otg_set_param_dev_nperio_tx_fifo_size</a>(core_if,
+<a name="l00336"></a>00336                                                               <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.
+<a name="l00337"></a>00337                                                               <a class="code" href="structdwc__otg__driver__module__params.html#3172175dc8f08e96b63c7a8c162201f5">dev_nperio_tx_fifo_size</a>);
+<a name="l00338"></a>00338         }
+<a name="l00339"></a>00339         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#1f490daab4c4e08d2773f46d51f1f5f7">host_rx_fifo_size</a> != -1) {
+<a name="l00340"></a>00340                 retval +=
+<a name="l00341"></a>00341                     <a class="code" href="dwc__otg__cil_8c.html#254c1e97cf22fe34b7383165e30071eb">dwc_otg_set_param_host_rx_fifo_size</a>(core_if,
+<a name="l00342"></a>00342                                                         <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#1f490daab4c4e08d2773f46d51f1f5f7">host_rx_fifo_size</a>);
+<a name="l00343"></a>00343         }
+<a name="l00344"></a>00344         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#edf2038417f58acd8dab202a8ca19d2a">host_nperio_tx_fifo_size</a> != -1) {
+<a name="l00345"></a>00345                 retval +=
+<a name="l00346"></a>00346                     <a class="code" href="dwc__otg__cil_8c.html#a66ca9f9345a13606148b050f8690a56">dwc_otg_set_param_host_nperio_tx_fifo_size</a>(core_if,
+<a name="l00347"></a>00347                                                                <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.
+<a name="l00348"></a>00348                                                                <a class="code" href="structdwc__otg__driver__module__params.html#edf2038417f58acd8dab202a8ca19d2a">host_nperio_tx_fifo_size</a>);
+<a name="l00349"></a>00349         }
+<a name="l00350"></a>00350         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#bdc820350ca3b6aec5ac435c9712ccd5">host_perio_tx_fifo_size</a> != -1) {
+<a name="l00351"></a>00351                 retval +=
+<a name="l00352"></a>00352                     <a class="code" href="dwc__otg__cil_8c.html#e4ce399208d8a85dcb9dedd1fb8cd8ce">dwc_otg_set_param_host_perio_tx_fifo_size</a>(core_if,
+<a name="l00353"></a>00353                                                               <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.
+<a name="l00354"></a>00354                                                               <a class="code" href="structdwc__otg__driver__module__params.html#bdc820350ca3b6aec5ac435c9712ccd5">host_perio_tx_fifo_size</a>);
+<a name="l00355"></a>00355         }
+<a name="l00356"></a>00356         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#16cc5351ae1dfbcd81d56a7ec16e1748">max_transfer_size</a> != -1) {
+<a name="l00357"></a>00357                 retval +=
+<a name="l00358"></a>00358                     <a class="code" href="dwc__otg__cil_8c.html#2eee676071d6bb4eba53b413e80b045f">dwc_otg_set_param_max_transfer_size</a>(core_if,
+<a name="l00359"></a>00359                                                         <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.
+<a name="l00360"></a>00360                                                         <a class="code" href="structdwc__otg__driver__module__params.html#16cc5351ae1dfbcd81d56a7ec16e1748">max_transfer_size</a>);
+<a name="l00361"></a>00361         }
+<a name="l00362"></a>00362         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#bb7904edc790fce40ac04ed68a64217e">max_packet_count</a> != -1) {
+<a name="l00363"></a>00363                 retval +=
+<a name="l00364"></a>00364                     <a class="code" href="dwc__otg__cil_8c.html#a1c52f0740f7d0b72c980b38cc4314d1">dwc_otg_set_param_max_packet_count</a>(core_if,
+<a name="l00365"></a>00365                                                        <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.
+<a name="l00366"></a>00366                                                        <a class="code" href="structdwc__otg__driver__module__params.html#bb7904edc790fce40ac04ed68a64217e">max_packet_count</a>);
+<a name="l00367"></a>00367         }
+<a name="l00368"></a>00368         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#4727585082d86c52396adfde0cfffa17">host_channels</a> != -1) {
+<a name="l00369"></a>00369                 retval +=
+<a name="l00370"></a>00370                     <a class="code" href="dwc__otg__cil_8c.html#f802acfc49b3fbb86159036f8f317f76">dwc_otg_set_param_host_channels</a>(core_if,
+<a name="l00371"></a>00371                                                     <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.
+<a name="l00372"></a>00372                                                     <a class="code" href="structdwc__otg__driver__module__params.html#4727585082d86c52396adfde0cfffa17">host_channels</a>);
+<a name="l00373"></a>00373         }
+<a name="l00374"></a>00374         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#c1c36daec6af25fb425c85a696c445e4">dev_endpoints</a> != -1) {
+<a name="l00375"></a>00375                 retval +=
+<a name="l00376"></a>00376                     <a class="code" href="dwc__otg__cil_8c.html#75d3b409824c0ca52631277398ba8367">dwc_otg_set_param_dev_endpoints</a>(core_if,
+<a name="l00377"></a>00377                                                     <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.
+<a name="l00378"></a>00378                                                     <a class="code" href="structdwc__otg__driver__module__params.html#c1c36daec6af25fb425c85a696c445e4">dev_endpoints</a>);
+<a name="l00379"></a>00379         }
+<a name="l00380"></a>00380         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#77d1c10524440ed2e5189624157526ac">phy_type</a> != -1) {
+<a name="l00381"></a>00381                 retval +=
+<a name="l00382"></a>00382                     <a class="code" href="dwc__otg__cil_8c.html#2b7087c85c0ea1520ec2e091b80bf36b">dwc_otg_set_param_phy_type</a>(core_if,
+<a name="l00383"></a>00383                                                <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#77d1c10524440ed2e5189624157526ac">phy_type</a>);
+<a name="l00384"></a>00384         }
+<a name="l00385"></a>00385         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#e0002437cefb2b64dc92f40fd69ef29f">speed</a> != -1) {
+<a name="l00386"></a>00386                 retval +=
+<a name="l00387"></a>00387                     <a class="code" href="dwc__otg__cil_8c.html#7acd153b5577a3db825fa08d243ae856">dwc_otg_set_param_speed</a>(core_if,
+<a name="l00388"></a>00388                                             <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#e0002437cefb2b64dc92f40fd69ef29f">speed</a>);
+<a name="l00389"></a>00389         }
+<a name="l00390"></a>00390         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#91c46e96e070e983e3f91c756dd4aa64">host_ls_low_power_phy_clk</a> != -1) {
+<a name="l00391"></a>00391                 retval +=
+<a name="l00392"></a>00392                     <a class="code" href="dwc__otg__cil_8c.html#354ce49f65334e829c2694811c4f2016">dwc_otg_set_param_host_ls_low_power_phy_clk</a>(core_if,
+<a name="l00393"></a>00393                                                                 <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.
+<a name="l00394"></a>00394                                                                 <a class="code" href="structdwc__otg__driver__module__params.html#91c46e96e070e983e3f91c756dd4aa64">host_ls_low_power_phy_clk</a>);
+<a name="l00395"></a>00395         }
+<a name="l00396"></a>00396         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#6a2b8c0c6298a7b1da23d5dd5abc4da8">phy_ulpi_ddr</a> != -1) {
+<a name="l00397"></a>00397                 retval +=
+<a name="l00398"></a>00398                     <a class="code" href="dwc__otg__cil_8c.html#5dab15db053bd02c6bc9619e189a6a14">dwc_otg_set_param_phy_ulpi_ddr</a>(core_if,
+<a name="l00399"></a>00399                                                    <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.
+<a name="l00400"></a>00400                                                    <a class="code" href="structdwc__otg__driver__module__params.html#6a2b8c0c6298a7b1da23d5dd5abc4da8">phy_ulpi_ddr</a>);
+<a name="l00401"></a>00401         }
+<a name="l00402"></a>00402         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#8402de29e6ec24baa5881cb7d74914c2">phy_ulpi_ext_vbus</a> != -1) {
+<a name="l00403"></a>00403                 retval +=
+<a name="l00404"></a>00404                     <a class="code" href="dwc__otg__cil_8c.html#a12296bcb04a3b0f6f80037590e97bec">dwc_otg_set_param_phy_ulpi_ext_vbus</a>(core_if,
+<a name="l00405"></a>00405                                                         <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.
+<a name="l00406"></a>00406                                                         <a class="code" href="structdwc__otg__driver__module__params.html#8402de29e6ec24baa5881cb7d74914c2">phy_ulpi_ext_vbus</a>);
+<a name="l00407"></a>00407         }
+<a name="l00408"></a>00408         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#f6284c33f13fe2f02491fa1a0c479b25">phy_utmi_width</a> != -1) {
+<a name="l00409"></a>00409                 retval +=
+<a name="l00410"></a>00410                     <a class="code" href="dwc__otg__cil_8c.html#1eacecc96e1ab100cbf129ad6aa5f6c8">dwc_otg_set_param_phy_utmi_width</a>(core_if,
+<a name="l00411"></a>00411                                                      <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.
+<a name="l00412"></a>00412                                                      <a class="code" href="structdwc__otg__driver__module__params.html#f6284c33f13fe2f02491fa1a0c479b25">phy_utmi_width</a>);
+<a name="l00413"></a>00413         }
+<a name="l00414"></a>00414         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#33489751a5cef9e462d26e92caae3031">ulpi_fs_ls</a> != -1) {
+<a name="l00415"></a>00415                 retval +=
+<a name="l00416"></a>00416                     <a class="code" href="dwc__otg__cil_8c.html#f235e9c7b844b899d759a073a84f782f">dwc_otg_set_param_ulpi_fs_ls</a>(core_if, <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#33489751a5cef9e462d26e92caae3031">ulpi_fs_ls</a>);
+<a name="l00417"></a>00417         }
+<a name="l00418"></a>00418         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#25f8f9c3558aa01fecf8bcd1527ee6cc">ts_dline</a> != -1) {
+<a name="l00419"></a>00419                 retval +=
+<a name="l00420"></a>00420                     <a class="code" href="dwc__otg__cil_8c.html#b05c92754c0ebc3d58ea0c090b9659de">dwc_otg_set_param_ts_dline</a>(core_if,
+<a name="l00421"></a>00421                                                <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#25f8f9c3558aa01fecf8bcd1527ee6cc">ts_dline</a>);
+<a name="l00422"></a>00422         }
+<a name="l00423"></a>00423         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#4e1d822cfcc6332fcaa0471bb1ca0d54">i2c_enable</a> != -1) {
+<a name="l00424"></a>00424                 retval +=
+<a name="l00425"></a>00425                     <a class="code" href="dwc__otg__cil_8c.html#65d7407ed24c82e158a38ab2a60120c4">dwc_otg_set_param_i2c_enable</a>(core_if,
+<a name="l00426"></a>00426                                                  <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.
+<a name="l00427"></a>00427                                                  <a class="code" href="structdwc__otg__driver__module__params.html#4e1d822cfcc6332fcaa0471bb1ca0d54">i2c_enable</a>);
+<a name="l00428"></a>00428         }
+<a name="l00429"></a>00429         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#13860bb2c8d23e40088703289e6ae835">en_multiple_tx_fifo</a> != -1) {
+<a name="l00430"></a>00430                 retval +=
+<a name="l00431"></a>00431                     <a class="code" href="dwc__otg__cil_8c.html#2eefd02d72c79200072d54b4eb13e5cd">dwc_otg_set_param_en_multiple_tx_fifo</a>(core_if,
+<a name="l00432"></a>00432                                                           <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.
+<a name="l00433"></a>00433                                                           <a class="code" href="structdwc__otg__driver__module__params.html#13860bb2c8d23e40088703289e6ae835">en_multiple_tx_fifo</a>);
+<a name="l00434"></a>00434         }
+<a name="l00435"></a>00435         <span class="keywordflow">for</span> (i = 0; i &lt; 15; i++) {
+<a name="l00436"></a>00436                 <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#aada52f0668d5d52b8ac6281c8736283">dev_perio_tx_fifo_size</a>[i] != -1) {
+<a name="l00437"></a>00437                         retval +=
+<a name="l00438"></a>00438                             <a class="code" href="dwc__otg__cil_8c.html#2119a493582bea4004b5fdeba15f1609">dwc_otg_set_param_dev_perio_tx_fifo_size</a>(core_if,
+<a name="l00439"></a>00439                                                                      <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.
+<a name="l00440"></a>00440                                                                      <a class="code" href="structdwc__otg__driver__module__params.html#aada52f0668d5d52b8ac6281c8736283">dev_perio_tx_fifo_size</a>
+<a name="l00441"></a>00441                                                                      [i], i);
+<a name="l00442"></a>00442                 }
+<a name="l00443"></a>00443         }
+<a name="l00444"></a>00444 
+<a name="l00445"></a>00445         <span class="keywordflow">for</span> (i = 0; i &lt; 15; i++) {
+<a name="l00446"></a>00446                 <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#d1c3fbc5325b13e1191388b76795b848">dev_tx_fifo_size</a>[i] != -1) {
+<a name="l00447"></a>00447                         retval += <a class="code" href="dwc__otg__cil_8c.html#44bf6b41f0892f480ea6c03a2ac1e73f">dwc_otg_set_param_dev_tx_fifo_size</a>(core_if,
+<a name="l00448"></a>00448                                                                      <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.
+<a name="l00449"></a>00449                                                                      <a class="code" href="structdwc__otg__driver__module__params.html#d1c3fbc5325b13e1191388b76795b848">dev_tx_fifo_size</a>
+<a name="l00450"></a>00450                                                                      [i], i);
+<a name="l00451"></a>00451                 }
+<a name="l00452"></a>00452         }
+<a name="l00453"></a>00453         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#7fe5c7ff692926fb5cbe3b10d4123594">thr_ctl</a> != -1) {
+<a name="l00454"></a>00454                 retval +=
+<a name="l00455"></a>00455                     <a class="code" href="dwc__otg__cil_8c.html#6095d6a93f901f32522d4b950c99a8e1">dwc_otg_set_param_thr_ctl</a>(core_if,
+<a name="l00456"></a>00456                                               <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#7fe5c7ff692926fb5cbe3b10d4123594">thr_ctl</a>);
+<a name="l00457"></a>00457         }
+<a name="l00458"></a>00458         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#484412984c814a6298b05b58d94bd730">mpi_enable</a> != -1) {
+<a name="l00459"></a>00459                 retval +=
+<a name="l00460"></a>00460                     <a class="code" href="dwc__otg__cil_8c.html#7ba10fdfd2ce9f3ef4b0a2bef555a7c1">dwc_otg_set_param_mpi_enable</a>(core_if,
+<a name="l00461"></a>00461                                                  <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.
+<a name="l00462"></a>00462                                                  <a class="code" href="structdwc__otg__driver__module__params.html#484412984c814a6298b05b58d94bd730">mpi_enable</a>);
+<a name="l00463"></a>00463         }
+<a name="l00464"></a>00464         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#2e17f84d9b07732a7fdf37b13832c54a">pti_enable</a> != -1) {
+<a name="l00465"></a>00465                 retval +=
+<a name="l00466"></a>00466                     <a class="code" href="dwc__otg__cil_8c.html#63c0b4bfcf3b1c6c90c5572258439e1f">dwc_otg_set_param_pti_enable</a>(core_if,
+<a name="l00467"></a>00467                                                  <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.
+<a name="l00468"></a>00468                                                  <a class="code" href="structdwc__otg__driver__module__params.html#2e17f84d9b07732a7fdf37b13832c54a">pti_enable</a>);
+<a name="l00469"></a>00469         }
+<a name="l00470"></a>00470         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#bb4e33c533d53de007814f0e5a70dd8a">lpm_enable</a> != -1) {
+<a name="l00471"></a>00471                 retval +=
+<a name="l00472"></a>00472                     <a class="code" href="dwc__otg__cil_8c.html#e3a62b66e19a302a55046830f5eecf0c">dwc_otg_set_param_lpm_enable</a>(core_if,
+<a name="l00473"></a>00473                                                  <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.
+<a name="l00474"></a>00474                                                  <a class="code" href="structdwc__otg__driver__module__params.html#bb4e33c533d53de007814f0e5a70dd8a">lpm_enable</a>);
+<a name="l00475"></a>00475         }
+<a name="l00476"></a>00476         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#ed3802eea4e62cd79ef7d8701d45b506">ic_usb_cap</a> != -1) {
+<a name="l00477"></a>00477                 retval +=
+<a name="l00478"></a>00478                     <a class="code" href="dwc__otg__cil_8c.html#93036faefc8179eef11c8ca0b18993a8">dwc_otg_set_param_ic_usb_cap</a>(core_if,
+<a name="l00479"></a>00479                                                  <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.
+<a name="l00480"></a>00480                                                  <a class="code" href="structdwc__otg__driver__module__params.html#ed3802eea4e62cd79ef7d8701d45b506">ic_usb_cap</a>);
+<a name="l00481"></a>00481         }
+<a name="l00482"></a>00482         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#04d15f44d06c291acfeef82812bd1c65">tx_thr_length</a> != -1) {
+<a name="l00483"></a>00483                 retval +=
+<a name="l00484"></a>00484                     <a class="code" href="dwc__otg__cil_8c.html#1ed19fed8939a352f91fe1403574135e">dwc_otg_set_param_tx_thr_length</a>(core_if,
+<a name="l00485"></a>00485                                                     <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#04d15f44d06c291acfeef82812bd1c65">tx_thr_length</a>);
+<a name="l00486"></a>00486         }
+<a name="l00487"></a>00487         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#eecdc71dde5ce0543a04d541a90f79bc">rx_thr_length</a> != -1) {
+<a name="l00488"></a>00488                 retval +=
+<a name="l00489"></a>00489                     <a class="code" href="dwc__otg__cil_8c.html#20d005470a65927cb243b37619f6c6bf">dwc_otg_set_param_rx_thr_length</a>(core_if,
+<a name="l00490"></a>00490                                                     <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.
+<a name="l00491"></a>00491                                                     <a class="code" href="structdwc__otg__driver__module__params.html#eecdc71dde5ce0543a04d541a90f79bc">rx_thr_length</a>);
+<a name="l00492"></a>00492         }
+<a name="l00493"></a>00493         <span class="keywordflow">if</span>(<a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#b450246efcbc087eb36b0979040162ca">ahb_thr_ratio</a> != -1) {
+<a name="l00494"></a>00494                 retval +=
+<a name="l00495"></a>00495                     <a class="code" href="dwc__otg__cil_8c.html#9bf87dcaa6dcea51eb3d8c30439a2138">dwc_otg_set_param_ahb_thr_ratio</a>(core_if, <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#b450246efcbc087eb36b0979040162ca">ahb_thr_ratio</a>);
+<a name="l00496"></a>00496         }
+<a name="l00497"></a>00497         <span class="keywordflow">return</span> retval;
+<a name="l00498"></a>00498 }
+<a name="l00499"></a>00499 
+<a name="l00504"></a><a class="code" href="dwc__otg__driver_8c.html#8850871557165b76b72f28723e4ec450">00504</a> <span class="keyword">static</span> irqreturn_t <a class="code" href="dwc__otg__driver_8c.html#8850871557165b76b72f28723e4ec450">dwc_otg_common_irq</a>(<span class="keywordtype">int</span> irq, <span class="keywordtype">void</span> *dev)
+<a name="l00505"></a>00505 {
+<a name="l00506"></a>00506         <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = dev;
+<a name="l00507"></a>00507         int32_t retval = IRQ_NONE;
+<a name="l00508"></a>00508 
+<a name="l00509"></a>00509         retval = <a class="code" href="dwc__otg__cil__intr_8c.html#1fad5cb7f68bc87c628bc4cb5db922b8">dwc_otg_handle_common_intr</a>(otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#4cc7c9f6e473072c2ed0a5e6adb25ebe">core_if</a>);
+<a name="l00510"></a>00510         <span class="keywordflow">if</span> (retval != 0) {
+<a name="l00511"></a>00511                 <a class="code" href="dwc__otg__driver_8h.html#3af7bafbb69f04a0fd36a27fae7e8497">S3C2410X_CLEAR_EINTPEND</a>();
+<a name="l00512"></a>00512         }
+<a name="l00513"></a>00513         <span class="keywordflow">return</span> IRQ_RETVAL(retval);
+<a name="l00514"></a>00514 }
+<a name="l00515"></a>00515 
+<a name="l00525"></a><a class="code" href="dwc__otg__driver_8c.html#fe9abf2a1dda4c02d24f5cb1d7a9a94d">00525</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__driver_8c.html#fe9abf2a1dda4c02d24f5cb1d7a9a94d">dwc_otg_driver_remove</a>(
+<a name="l00526"></a>00526 #ifdef LM_INTERFACE
+<a name="l00527"></a>00527      <span class="keyword">struct</span> lm_device *_dev
+<a name="l00528"></a>00528 #elif PCI_INTERFACE
+<a name="l00529"></a>00529      <span class="keyword">struct</span> pci_dev *_dev
+<a name="l00530"></a>00530 #endif
+<a name="l00531"></a>00531 )
+<a name="l00532"></a>00532 
+<a name="l00533"></a>00533 {
+<a name="l00534"></a>00534 <span class="preprocessor">#ifdef LM_INTERFACE</span>
+<a name="l00535"></a>00535 <span class="preprocessor"></span>        <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = lm_get_drvdata(_dev);
+<a name="l00536"></a>00536 <span class="preprocessor">#elif PCI_INTERFACE</span>
+<a name="l00537"></a>00537 <span class="preprocessor"></span>        <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = pci_get_drvdata(_dev);
+<a name="l00538"></a>00538 <span class="preprocessor">#endif</span>
+<a name="l00539"></a>00539 <span class="preprocessor"></span>
+<a name="l00540"></a>00540 
+<a name="l00541"></a>00541         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#2bf62a567355d1ea38814714bd7b57ec">DBG_ANY</a>, <span class="stringliteral">"%s(%p)\n"</span>, __func__, _dev);
+<a name="l00542"></a>00542 
+<a name="l00543"></a>00543         <span class="keywordflow">if</span> (!otg_dev) {
+<a name="l00544"></a>00544                 <span class="comment">/* Memory allocation for the dwc_otg_device failed. */</span>
+<a name="l00545"></a>00545                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#2bf62a567355d1ea38814714bd7b57ec">DBG_ANY</a>, <span class="stringliteral">"%s: otg_dev NULL!\n"</span>, __func__);
+<a name="l00546"></a>00546                 <span class="keywordflow">return</span>;
+<a name="l00547"></a>00547         }
+<a name="l00548"></a>00548 <span class="preprocessor">#ifndef DWC_DEVICE_ONLY</span>
+<a name="l00549"></a>00549 <span class="preprocessor"></span>        <span class="keywordflow">if</span> (otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#834ef28e884f0d7fcac68f3bdf5c4b33">hcd</a>) {
+<a name="l00550"></a>00550                 <a class="code" href="dwc__otg__driver_8c.html#f36193b3ff33c0473956c8a15eee4f5b">hcd_remove</a>(_dev);
+<a name="l00551"></a>00551         } <span class="keywordflow">else</span> {
+<a name="l00552"></a>00552                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#2bf62a567355d1ea38814714bd7b57ec">DBG_ANY</a>, <span class="stringliteral">"%s: otg_dev-&gt;hcd NULL!\n"</span>, __func__);
+<a name="l00553"></a>00553                 <span class="keywordflow">return</span>;
+<a name="l00554"></a>00554         }
+<a name="l00555"></a>00555 <span class="preprocessor">#endif</span>
+<a name="l00556"></a>00556 <span class="preprocessor"></span>
+<a name="l00557"></a>00557 <span class="preprocessor">#ifndef DWC_HOST_ONLY</span>
+<a name="l00558"></a>00558 <span class="preprocessor"></span>        <span class="keywordflow">if</span> (otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#2a8eefbd03790ea0bbb70e0ac14e4786">pcd</a>) {
+<a name="l00559"></a>00559                 <a class="code" href="dwc__otg__driver_8c.html#7960b8e2c02d9ab89b65cb01ba08658b">pcd_remove</a>(_dev);
+<a name="l00560"></a>00560         }
+<a name="l00561"></a>00561 <span class="preprocessor">#endif</span>
+<a name="l00562"></a>00562 <span class="preprocessor"></span>        <span class="comment">/*</span>
+<a name="l00563"></a>00563 <span class="comment">         * Free the IRQ</span>
+<a name="l00564"></a>00564 <span class="comment">         */</span>
+<a name="l00565"></a>00565         <span class="keywordflow">if</span> (otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#80bfe5405d4146d3edca4e3eb2f9239b">common_irq_installed</a>) {
+<a name="l00566"></a>00566                 free_irq(_dev-&gt;irq, otg_dev);
+<a name="l00567"></a>00567         }
+<a name="l00568"></a>00568 
+<a name="l00569"></a>00569         <span class="keywordflow">if</span> (otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#4cc7c9f6e473072c2ed0a5e6adb25ebe">core_if</a>) {
+<a name="l00570"></a>00570                 <a class="code" href="dwc__otg__cil_8c.html#cc4a08b278c7afe0484b595cacf80c04">dwc_otg_cil_remove</a>(otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#4cc7c9f6e473072c2ed0a5e6adb25ebe">core_if</a>);
+<a name="l00571"></a>00571         }
+<a name="l00572"></a>00572 
+<a name="l00573"></a>00573         <span class="comment">/*</span>
+<a name="l00574"></a>00574 <span class="comment">         * Remove the device attributes</span>
+<a name="l00575"></a>00575 <span class="comment">         */</span>
+<a name="l00576"></a>00576         <a class="code" href="dwc__otg__attr_8c.html#4b0aa5ebf3661ec8ab5566b20c233674">dwc_otg_attr_remove</a>(_dev);
+<a name="l00577"></a>00577 
+<a name="l00578"></a>00578         <span class="comment">/*</span>
+<a name="l00579"></a>00579 <span class="comment">         * Return the memory.</span>
+<a name="l00580"></a>00580 <span class="comment">         */</span>
+<a name="l00581"></a>00581         <span class="keywordflow">if</span> (otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#ed96ed1109175f87fd83fa32a9c2c6fa">base</a>) {
+<a name="l00582"></a>00582                 iounmap(otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#ed96ed1109175f87fd83fa32a9c2c6fa">base</a>);
+<a name="l00583"></a>00583         }
+<a name="l00584"></a>00584         dwc_free(otg_dev);
+<a name="l00585"></a>00585 
+<a name="l00586"></a>00586         <span class="comment">/*</span>
+<a name="l00587"></a>00587 <span class="comment">         * Clear the drvdata pointer.</span>
+<a name="l00588"></a>00588 <span class="comment">         */</span>
+<a name="l00589"></a>00589 <span class="preprocessor">#ifdef LM_INTERFACE</span>
+<a name="l00590"></a>00590 <span class="preprocessor"></span>        lm_set_drvdata(_dev, 0);
+<a name="l00591"></a>00591 <span class="preprocessor">#elif PCI_INTERFACE</span>
+<a name="l00592"></a>00592 <span class="preprocessor"></span>        release_mem_region(otg_dev-&gt;rsrc_start, otg_dev-&gt;rsrc_len);
+<a name="l00593"></a>00593         pci_set_drvdata(_dev, 0);
+<a name="l00594"></a>00594 <span class="preprocessor">#endif</span>
+<a name="l00595"></a>00595 <span class="preprocessor"></span>}
+<a name="l00596"></a>00596 
+<a name="l00608"></a><a class="code" href="dwc__otg__driver_8c.html#10921617ecc621f0448d4f9ab6a0f7b7">00608</a> <span class="keyword">static</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__driver_8c.html#10921617ecc621f0448d4f9ab6a0f7b7">dwc_otg_driver_probe</a>(
+<a name="l00609"></a>00609 #ifdef LM_INTERFACE
+<a name="l00610"></a>00610 <span class="keyword">struct</span> lm_device *_dev
+<a name="l00611"></a>00611 #elif PCI_INTERFACE
+<a name="l00612"></a>00612 <span class="keyword">struct</span> pci_dev *_dev,  <span class="keyword">const</span> <span class="keyword">struct</span> pci_device_id *<span class="keywordtype">id</span>
+<a name="l00613"></a>00613 #endif
+<a name="l00614"></a>00614 )
+<a name="l00615"></a>00615 {
+<a name="l00616"></a>00616         <span class="keywordtype">int</span> retval = 0;
+<a name="l00617"></a>00617         <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *<a class="code" href="structdwc__otg__device.html">dwc_otg_device</a>;
+<a name="l00618"></a>00618 
+<a name="l00619"></a>00619         dev_dbg(&amp;_dev-&gt;dev, <span class="stringliteral">"dwc_otg_driver_probe(%p)\n"</span>, _dev);
+<a name="l00620"></a>00620 <span class="preprocessor">#ifdef LM_INTERFACE</span>
+<a name="l00621"></a>00621 <span class="preprocessor"></span>        dev_dbg(&amp;_dev-&gt;dev, <span class="stringliteral">"start=0x%08x\n"</span>, (<span class="keywordtype">unsigned</span>)_dev-&gt;resource.start);
+<a name="l00622"></a>00622 <span class="preprocessor">#elif PCI_INTERFACE</span>
+<a name="l00623"></a>00623 <span class="preprocessor"></span>        <span class="keywordflow">if</span> (!<span class="keywordtype">id</span>) {
+<a name="l00624"></a>00624         DWC_ERROR(<span class="stringliteral">"Invalid pci_device_id %p"</span>, <span class="keywordtype">id</span>);
+<a name="l00625"></a>00625                 <span class="keywordflow">return</span> -EINVAL;
+<a name="l00626"></a>00626         }
+<a name="l00627"></a>00627 
+<a name="l00628"></a>00628         <span class="keywordflow">if</span> (!_dev || (pci_enable_device(_dev) &lt; 0)) {
+<a name="l00629"></a>00629                 DWC_ERROR(<span class="stringliteral">"Invalid pci_device %p"</span>, _dev);
+<a name="l00630"></a>00630                 <span class="keywordflow">return</span> -ENODEV;
+<a name="l00631"></a>00631         }
+<a name="l00632"></a>00632         dev_dbg(&amp;_dev-&gt;dev, <span class="stringliteral">"start=0x%08x\n"</span>, (<span class="keywordtype">unsigned</span>)pci_resource_start(_dev,0));
+<a name="l00633"></a>00633         <span class="comment">/* other stuff needed as well? */</span>
+<a name="l00634"></a>00634 
+<a name="l00635"></a>00635 <span class="preprocessor">#endif</span>
+<a name="l00636"></a>00636 <span class="preprocessor"></span>
+<a name="l00637"></a>00637 
+<a name="l00638"></a>00638         dwc_otg_device = dwc_alloc(<span class="keyword">sizeof</span>(<a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a>));
+<a name="l00639"></a>00639 
+<a name="l00640"></a>00640         <span class="keywordflow">if</span> (!dwc_otg_device) {
+<a name="l00641"></a>00641                 dev_err(&amp;_dev-&gt;dev, <span class="stringliteral">"kmalloc of dwc_otg_device failed\n"</span>);
+<a name="l00642"></a>00642                 retval = -ENOMEM;
+<a name="l00643"></a>00643                 <span class="keywordflow">goto</span> fail;
+<a name="l00644"></a>00644         }
+<a name="l00645"></a>00645 
+<a name="l00646"></a>00646         memset(dwc_otg_device, 0, <span class="keyword">sizeof</span>(*dwc_otg_device));
+<a name="l00647"></a>00647         dwc_otg_device-&gt;reg_offset = 0xFFFFFFFF;
+<a name="l00648"></a>00648 
+<a name="l00649"></a>00649         <span class="comment">/*</span>
+<a name="l00650"></a>00650 <span class="comment">         * Map the DWC_otg Core memory into virtual address space.</span>
+<a name="l00651"></a>00651 <span class="comment">         */</span>
+<a name="l00652"></a>00652 <span class="preprocessor">#ifdef LM_INTERFACE</span>
+<a name="l00653"></a>00653 <span class="preprocessor"></span>        dwc_otg_device-&gt;base = ioremap(_dev-&gt;resource.start, SZ_256K);
+<a name="l00654"></a>00654 
+<a name="l00655"></a>00655         <span class="keywordflow">if</span> (!dwc_otg_device-&gt;base) {
+<a name="l00656"></a>00656                 dev_err(&amp;_dev-&gt;dev, <span class="stringliteral">"ioremap() failed\n"</span>);
+<a name="l00657"></a>00657                 retval = -ENOMEM;
+<a name="l00658"></a>00658                 <span class="keywordflow">goto</span> fail;
+<a name="l00659"></a>00659         }
+<a name="l00660"></a>00660         dev_dbg(&amp;_dev-&gt;dev, <span class="stringliteral">"base=0x%08x\n"</span>, (<span class="keywordtype">unsigned</span>)dwc_otg_device-&gt;base);
+<a name="l00661"></a>00661 <span class="preprocessor">#elif PCI_INTERFACE</span>
+<a name="l00662"></a>00662 <span class="preprocessor"></span>        _dev-&gt;current_state = PCI_D0;
+<a name="l00663"></a>00663         _dev-&gt;dev.power.power_state = PMSG_ON;
+<a name="l00664"></a>00664         
+<a name="l00665"></a>00665         <span class="keywordflow">if</span> (!_dev-&gt;irq) {
+<a name="l00666"></a>00666                 DWC_ERROR(<span class="stringliteral">"Found HC with no IRQ. Check BIOS/PCI %s setup!"</span>, pci_name(_dev));
+<a name="l00667"></a>00667                 retval = -ENODEV;
+<a name="l00668"></a>00668                 <span class="keywordflow">goto</span> fail;
+<a name="l00669"></a>00669         }
+<a name="l00670"></a>00670 
+<a name="l00671"></a>00671         dwc_otg_device-&gt;rsrc_start = pci_resource_start(_dev,0);
+<a name="l00672"></a>00672         dwc_otg_device-&gt;rsrc_len = pci_resource_len(_dev,0);
+<a name="l00673"></a>00673         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#2bf62a567355d1ea38814714bd7b57ec">DBG_ANY</a>,<span class="stringliteral">"PCI resource: start=%08x, len=%08x\n"</span>,
+<a name="l00674"></a>00674                     dwc_otg_device-&gt;rsrc_start,
+<a name="l00675"></a>00675                     dwc_otg_device-&gt;rsrc_len);
+<a name="l00676"></a>00676         <span class="keywordflow">if</span> (!request_mem_region(dwc_otg_device-&gt;rsrc_start, dwc_otg_device-&gt;rsrc_len, <span class="stringliteral">"dwc_otg"</span>)) {
+<a name="l00677"></a>00677           dev_dbg(&amp;_dev-&gt;dev, <span class="stringliteral">"error mapping memory\n"</span>);
+<a name="l00678"></a>00678           retval = -EFAULT;
+<a name="l00679"></a>00679           <span class="keywordflow">goto</span> fail;
+<a name="l00680"></a>00680         }
+<a name="l00681"></a>00681 
+<a name="l00682"></a>00682         dwc_otg_device-&gt;base = ioremap_nocache(dwc_otg_device-&gt;rsrc_start, dwc_otg_device-&gt;rsrc_len);
+<a name="l00683"></a>00683         <span class="keywordflow">if</span> (dwc_otg_device-&gt;base == NULL) {
+<a name="l00684"></a>00684                 dev_dbg(&amp;_dev-&gt;dev, <span class="stringliteral">"error mapping memory\n"</span>);
+<a name="l00685"></a>00685                 retval = -EFAULT;
+<a name="l00686"></a>00686                 <span class="keywordflow">goto</span> fail;
+<a name="l00687"></a>00687         }
+<a name="l00688"></a>00688         dev_dbg(&amp;_dev-&gt;dev, <span class="stringliteral">"base=0x%p (before adjust) \n"</span>, dwc_otg_device-&gt;base);
+<a name="l00689"></a>00689         dwc_otg_device-&gt;base = (<span class="keywordtype">char</span> *)dwc_otg_device-&gt;base;
+<a name="l00690"></a>00690         dev_dbg(&amp;_dev-&gt;dev, <span class="stringliteral">"base=0x%p (after adjust) \n"</span>, dwc_otg_device-&gt;base);
+<a name="l00691"></a>00691         dev_dbg(&amp;_dev-&gt;dev, <span class="stringliteral">"%s: mapped PA 0x%x to VA 0x%p\n"</span>, __func__,
+<a name="l00692"></a>00692                 (<span class="keywordtype">unsigned</span>)dwc_otg_device-&gt;rsrc_start, dwc_otg_device-&gt;base);
+<a name="l00693"></a>00693         <span class="comment">//</span>
+<a name="l00694"></a>00694         pci_set_drvdata(_dev, dwc_otg_device); 
+<a name="l00695"></a>00695         pci_set_master(_dev);
+<a name="l00696"></a>00696 <span class="preprocessor">#endif</span>
+<a name="l00697"></a>00697 <span class="preprocessor"></span>
+<a name="l00698"></a>00698         <span class="comment">/*</span>
+<a name="l00699"></a>00699 <span class="comment">         * Initialize driver data to point to the global DWC_otg</span>
+<a name="l00700"></a>00700 <span class="comment">         * Device structure.</span>
+<a name="l00701"></a>00701 <span class="comment">         */</span>
+<a name="l00702"></a>00702 <span class="preprocessor">#ifdef LM_INTERFACE</span>
+<a name="l00703"></a>00703 <span class="preprocessor"></span>        lm_set_drvdata(_dev, dwc_otg_device);
+<a name="l00704"></a>00704 <span class="preprocessor">#endif</span>
+<a name="l00705"></a>00705 <span class="preprocessor"></span>        dev_dbg(&amp;_dev-&gt;dev, <span class="stringliteral">"dwc_otg_device=0x%p\n"</span>, dwc_otg_device);
+<a name="l00706"></a>00706 
+<a name="l00707"></a>00707         dwc_otg_device-&gt;core_if = <a class="code" href="dwc__otg__cil_8c.html#2dc0a6c5541c1a8a014d66a8fce53f66">dwc_otg_cil_init</a>(dwc_otg_device-&gt;base);
+<a name="l00708"></a>00708         <span class="keywordflow">if</span> (!dwc_otg_device-&gt;core_if) {
+<a name="l00709"></a>00709                 dev_err(&amp;_dev-&gt;dev, <span class="stringliteral">"CIL initialization failed!\n"</span>);
+<a name="l00710"></a>00710                 retval = -ENOMEM;
+<a name="l00711"></a>00711                 <span class="keywordflow">goto</span> fail;
+<a name="l00712"></a>00712         }
+<a name="l00713"></a>00713 
+<a name="l00714"></a>00714         <span class="comment">/*</span>
+<a name="l00715"></a>00715 <span class="comment">         * Attempt to ensure this device is really a DWC_otg Controller.</span>
+<a name="l00716"></a>00716 <span class="comment">         * Read and verify the SNPSID register contents. The value should be</span>
+<a name="l00717"></a>00717 <span class="comment">         * 0x45F42XXX, which corresponds to "OT2", as in "OTG version 2.XX".</span>
+<a name="l00718"></a>00718 <span class="comment">         */</span>
+<a name="l00719"></a>00719 
+<a name="l00720"></a>00720         <span class="keywordflow">if</span> ((<a class="code" href="dwc__otg__cil_8c.html#c505c47a08029706f60ab8f3d67b70d3">dwc_otg_get_gsnpsid</a>(dwc_otg_device-&gt;core_if) &amp; 0xFFFFF000) !=
+<a name="l00721"></a>00721             0x4F542000) {
+<a name="l00722"></a>00722                 dev_err(&amp;_dev-&gt;dev, <span class="stringliteral">"Bad value for SNPSID: 0x%08x\n"</span>,
+<a name="l00723"></a>00723                         <a class="code" href="dwc__otg__cil_8c.html#c505c47a08029706f60ab8f3d67b70d3">dwc_otg_get_gsnpsid</a>(dwc_otg_device-&gt;core_if));
+<a name="l00724"></a>00724                 <a class="code" href="dwc__otg__cil_8c.html#cc4a08b278c7afe0484b595cacf80c04">dwc_otg_cil_remove</a>(dwc_otg_device-&gt;core_if);
+<a name="l00725"></a>00725                 dwc_free(dwc_otg_device);
+<a name="l00726"></a>00726                 retval = -EINVAL;
+<a name="l00727"></a>00727                 <span class="keywordflow">goto</span> fail;
+<a name="l00728"></a>00728         }
+<a name="l00729"></a>00729 
+<a name="l00730"></a>00730         <span class="comment">/*</span>
+<a name="l00731"></a>00731 <span class="comment">         * Validate parameter values.</span>
+<a name="l00732"></a>00732 <span class="comment">         */</span>
+<a name="l00733"></a>00733         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__driver_8c.html#fe3a3765da365671b36ba5e28dc4d38b">set_parameters</a>(dwc_otg_device-&gt;core_if)) {
+<a name="l00734"></a>00734                 <a class="code" href="dwc__otg__cil_8c.html#cc4a08b278c7afe0484b595cacf80c04">dwc_otg_cil_remove</a>(dwc_otg_device-&gt;core_if);
+<a name="l00735"></a>00735                 retval = -EINVAL;
+<a name="l00736"></a>00736                 <span class="keywordflow">goto</span> fail;
+<a name="l00737"></a>00737         }
+<a name="l00738"></a>00738 
+<a name="l00739"></a>00739         <span class="comment">/*</span>
+<a name="l00740"></a>00740 <span class="comment">         * Create Device Attributes in sysfs</span>
+<a name="l00741"></a>00741 <span class="comment">         */</span>
+<a name="l00742"></a>00742         <a class="code" href="dwc__otg__attr_8c.html#792fccf68b5f00d193f800822a5d888b">dwc_otg_attr_create</a>(_dev);
+<a name="l00743"></a>00743 
+<a name="l00744"></a>00744         <span class="comment">/*</span>
+<a name="l00745"></a>00745 <span class="comment">         * Disable the global interrupt until all the interrupt</span>
+<a name="l00746"></a>00746 <span class="comment">         * handlers are installed.</span>
+<a name="l00747"></a>00747 <span class="comment">         */</span>
+<a name="l00748"></a>00748         <a class="code" href="dwc__otg__cil_8c.html#9f673c38ca761d8ab7b3333b506bcbfc">dwc_otg_disable_global_interrupts</a>(dwc_otg_device-&gt;core_if);
+<a name="l00749"></a>00749 
+<a name="l00750"></a>00750         <span class="comment">/*</span>
+<a name="l00751"></a>00751 <span class="comment">         * Install the interrupt handler for the common interrupts before</span>
+<a name="l00752"></a>00752 <span class="comment">         * enabling common interrupts in core_init below.</span>
+<a name="l00753"></a>00753 <span class="comment">         */</span>
+<a name="l00754"></a>00754         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">DBG_CIL</a>, <span class="stringliteral">"registering (common) handler for irq%d\n"</span>,
+<a name="l00755"></a>00755                     _dev-&gt;irq);
+<a name="l00756"></a>00756         retval = request_irq(_dev-&gt;irq, <a class="code" href="dwc__otg__driver_8c.html#8850871557165b76b72f28723e4ec450">dwc_otg_common_irq</a>,
+<a name="l00757"></a>00757                              SA_SHIRQ, <span class="stringliteral">"dwc_otg"</span>, dwc_otg_device);
+<a name="l00758"></a>00758         <span class="keywordflow">if</span> (retval) {
+<a name="l00759"></a>00759                 DWC_ERROR(<span class="stringliteral">"request of irq%d failed\n"</span>, _dev-&gt;irq);
+<a name="l00760"></a>00760                 retval = -EBUSY;
+<a name="l00761"></a>00761                 <span class="keywordflow">goto</span> fail;
+<a name="l00762"></a>00762         } <span class="keywordflow">else</span> {
+<a name="l00763"></a>00763                 dwc_otg_device-&gt;common_irq_installed = 1;
+<a name="l00764"></a>00764         }
+<a name="l00765"></a>00765 
+<a name="l00766"></a>00766 <span class="preprocessor">#ifdef LM_INTERFACE</span>
+<a name="l00767"></a>00767 <span class="preprocessor"></span>        set_irq_type(_dev-&gt;irq, IRQT_LOW);
+<a name="l00768"></a>00768 <span class="preprocessor">#endif</span>
+<a name="l00769"></a>00769 <span class="preprocessor"></span>
+<a name="l00770"></a>00770         <span class="comment">/*</span>
+<a name="l00771"></a>00771 <span class="comment">         * Initialize the DWC_otg core.</span>
+<a name="l00772"></a>00772 <span class="comment">         */</span>
+<a name="l00773"></a>00773         <a class="code" href="dwc__otg__cil_8c.html#ce48d4f2d172600c325a82d793473d0f">dwc_otg_core_init</a>(dwc_otg_device-&gt;core_if);
+<a name="l00774"></a>00774 
+<a name="l00775"></a>00775 <span class="preprocessor">#ifndef DWC_HOST_ONLY</span>
+<a name="l00776"></a>00776 <span class="preprocessor"></span>        <span class="comment">/*</span>
+<a name="l00777"></a>00777 <span class="comment">         * Initialize the PCD</span>
+<a name="l00778"></a>00778 <span class="comment">         */</span>
+<a name="l00779"></a>00779         retval = <a class="code" href="dwc__otg__driver_8c.html#9dbc565a7942db0adbf1ec341db22901">pcd_init</a>(_dev);
+<a name="l00780"></a>00780         <span class="keywordflow">if</span> (retval != 0) {
+<a name="l00781"></a>00781                 DWC_ERROR(<span class="stringliteral">"pcd_init failed\n"</span>);
+<a name="l00782"></a>00782                 dwc_otg_device-&gt;pcd = NULL;
+<a name="l00783"></a>00783                 <span class="keywordflow">goto</span> fail;
+<a name="l00784"></a>00784         }
+<a name="l00785"></a>00785 <span class="preprocessor">#endif</span>
+<a name="l00786"></a>00786 <span class="preprocessor"></span><span class="preprocessor">#ifndef DWC_DEVICE_ONLY</span>
+<a name="l00787"></a>00787 <span class="preprocessor"></span>        <span class="comment">/*</span>
+<a name="l00788"></a>00788 <span class="comment">         * Initialize the HCD</span>
+<a name="l00789"></a>00789 <span class="comment">         */</span>
+<a name="l00790"></a>00790         retval = <a class="code" href="dwc__otg__driver_8c.html#ab12cdf65bf4ed68545a6c17cc31269f">hcd_init</a>(_dev);
+<a name="l00791"></a>00791         <span class="keywordflow">if</span> (retval != 0) {
+<a name="l00792"></a>00792                 DWC_ERROR(<span class="stringliteral">"hcd_init failed\n"</span>);
+<a name="l00793"></a>00793                 dwc_otg_device-&gt;hcd = NULL;
+<a name="l00794"></a>00794                 <span class="keywordflow">goto</span> fail;
+<a name="l00795"></a>00795         }
+<a name="l00796"></a>00796 <span class="preprocessor">#endif</span>
+<a name="l00797"></a>00797 <span class="preprocessor"></span><span class="preprocessor">#ifdef PCI_INTERFACE    </span>
+<a name="l00798"></a>00798 <span class="preprocessor"></span>        pci_set_drvdata(_dev, dwc_otg_device);
+<a name="l00799"></a>00799 <span class="preprocessor">#endif</span>
+<a name="l00800"></a>00800 <span class="preprocessor"></span>
+<a name="l00801"></a>00801         <span class="comment">/*</span>
+<a name="l00802"></a>00802 <span class="comment">         * Enable the global interrupt after all the interrupt</span>
+<a name="l00803"></a>00803 <span class="comment">         * handlers are installed.</span>
+<a name="l00804"></a>00804 <span class="comment">         */</span>
+<a name="l00805"></a>00805         <a class="code" href="dwc__otg__cil_8c.html#8b0b841d69298089b7d03b07ade8eda6">dwc_otg_enable_global_interrupts</a>(dwc_otg_device-&gt;core_if);
+<a name="l00806"></a>00806 
+<a name="l00807"></a>00807         <span class="keywordflow">return</span> 0;
+<a name="l00808"></a>00808 
+<a name="l00809"></a>00809       fail:
+<a name="l00810"></a>00810         <a class="code" href="dwc__otg__driver_8c.html#fe9abf2a1dda4c02d24f5cb1d7a9a94d">dwc_otg_driver_remove</a>(_dev);
+<a name="l00811"></a>00811         <span class="keywordflow">return</span> retval;
+<a name="l00812"></a>00812 }
+<a name="l00813"></a>00813 
+<a name="l00825"></a>00825 <span class="preprocessor">#ifdef LM_INTERFACE</span>
+<a name="l00826"></a>00826 <span class="preprocessor"></span><span class="keyword">static</span> <span class="keyword">struct </span>lm_driver dwc_otg_driver = {
+<a name="l00827"></a>00827         .drv = {
+<a name="l00828"></a>00828                 .name = (<span class="keywordtype">char</span> *)<a class="code" href="dwc__otg__driver_8c.html#3f7932dcd77bb7b05f92f759e6569fe2">dwc_driver_name</a>,
+<a name="l00829"></a>00829                 },
+<a name="l00830"></a>00830         .probe = <a class="code" href="dwc__otg__driver_8c.html#10921617ecc621f0448d4f9ab6a0f7b7">dwc_otg_driver_probe</a>,
+<a name="l00831"></a>00831         .remove = <a class="code" href="dwc__otg__driver_8c.html#fe9abf2a1dda4c02d24f5cb1d7a9a94d">dwc_otg_driver_remove</a>,
+<a name="l00832"></a>00832 };
+<a name="l00833"></a>00833 <span class="preprocessor">#elif PCI_INTERFACE</span>
+<a name="l00834"></a>00834 <span class="preprocessor"></span><span class="keyword">static</span> <span class="keyword">const</span> <span class="keyword">struct </span>pci_device_id pci_ids[] = { {
+<a name="l00835"></a>00835         PCI_DEVICE(0x16c3, 0xabcd),
+<a name="l00836"></a>00836         .driver_data = (<span class="keywordtype">unsigned</span> long) 0xdeadbeef,
+<a name="l00837"></a>00837         }, { <span class="comment">/* end: all zeroes */</span> }
+<a name="l00838"></a>00838 };
+<a name="l00839"></a>00839 MODULE_DEVICE_TABLE(pci, pci_ids);
+<a name="l00840"></a>00840 
+<a name="l00841"></a>00841 <span class="comment">/* pci driver glue; this is a "new style" PCI driver module */</span>
+<a name="l00842"></a>00842 <span class="keyword">static</span> <span class="keyword">struct </span>pci_driver dwc_otg_driver = {
+<a name="l00843"></a>00843         .name =         <span class="stringliteral">"dwc_otg"</span>,
+<a name="l00844"></a>00844         .id_table =     pci_ids,
+<a name="l00845"></a>00845 
+<a name="l00846"></a>00846         .probe =        <a class="code" href="dwc__otg__driver_8c.html#10921617ecc621f0448d4f9ab6a0f7b7">dwc_otg_driver_probe</a>,
+<a name="l00847"></a>00847         .remove =       <a class="code" href="dwc__otg__driver_8c.html#fe9abf2a1dda4c02d24f5cb1d7a9a94d">dwc_otg_driver_remove</a>,
+<a name="l00848"></a>00848 
+<a name="l00849"></a>00849         .driver = {
+<a name="l00850"></a>00850                 .name   = (<span class="keywordtype">char</span>*)<a class="code" href="dwc__otg__driver_8c.html#3f7932dcd77bb7b05f92f759e6569fe2">dwc_driver_name</a>,
+<a name="l00851"></a>00851         },
+<a name="l00852"></a>00852 };
+<a name="l00853"></a>00853 <span class="preprocessor">#endif</span>
+<a name="l00854"></a>00854 <span class="preprocessor"></span>
+<a name="l00855"></a>00855 
+<a name="l00866"></a><a class="code" href="dwc__otg__driver_8c.html#737f516e934e7f479e31bf7261dd3830">00866</a> <span class="keyword">static</span> <span class="keywordtype">int</span> __init <a class="code" href="dwc__otg__driver_8c.html#737f516e934e7f479e31bf7261dd3830">dwc_otg_driver_init</a>(<span class="keywordtype">void</span>)
+<a name="l00867"></a>00867 {
+<a name="l00868"></a>00868         <span class="keywordtype">int</span> retval = 0;
+<a name="l00869"></a>00869         <span class="keywordtype">int</span> error;
+<a name="l00870"></a>00870         printk(KERN_INFO <span class="stringliteral">"%s: version %s\n"</span>, <a class="code" href="dwc__otg__driver_8c.html#3f7932dcd77bb7b05f92f759e6569fe2">dwc_driver_name</a>,
+<a name="l00871"></a>00871                <a class="code" href="dwc__otg__driver_8c.html#7fb7b6d344624c19c1d920239458999a">DWC_DRIVER_VERSION</a>);
+<a name="l00872"></a>00872 <span class="preprocessor">#ifdef LM_INTERFACE</span>
+<a name="l00873"></a>00873 <span class="preprocessor"></span>        retval = lm_driver_register(&amp;dwc_otg_driver);
+<a name="l00874"></a>00874 <span class="preprocessor">#elif PCI_INTERFACE</span>
+<a name="l00875"></a>00875 <span class="preprocessor"></span>        retval = pci_register_driver(&amp;dwc_otg_driver);
+<a name="l00876"></a>00876 <span class="preprocessor">#endif</span>
+<a name="l00877"></a>00877 <span class="preprocessor"></span>        <span class="keywordflow">if</span> (retval &lt; 0) {
+<a name="l00878"></a>00878                 printk(KERN_ERR <span class="stringliteral">"%s retval=%d\n"</span>, __func__, retval);
+<a name="l00879"></a>00879                 <span class="keywordflow">return</span> retval;
+<a name="l00880"></a>00880         }
+<a name="l00881"></a>00881 <span class="preprocessor">#ifdef LM_INTERFACE</span>
+<a name="l00882"></a>00882 <span class="preprocessor"></span>        error = driver_create_file(&amp;dwc_otg_driver.drv, &amp;driver_attr_version);
+<a name="l00883"></a>00883         error = driver_create_file(&amp;dwc_otg_driver.drv, &amp;driver_attr_debuglevel);
+<a name="l00884"></a>00884 <span class="preprocessor">#elif PCI_INTERFACE</span>
+<a name="l00885"></a>00885 <span class="preprocessor"></span>        error = driver_create_file(&amp;dwc_otg_driver.driver, &amp;driver_attr_version);
+<a name="l00886"></a>00886         error = driver_create_file(&amp;dwc_otg_driver.driver, &amp;driver_attr_debuglevel);
+<a name="l00887"></a>00887 <span class="preprocessor">#endif</span>
+<a name="l00888"></a>00888 <span class="preprocessor"></span>        <span class="keywordflow">return</span> retval;
+<a name="l00889"></a>00889 }
+<a name="l00890"></a>00890 
+<a name="l00891"></a>00891 module_init(<a class="code" href="dwc__otg__driver_8c.html#737f516e934e7f479e31bf7261dd3830">dwc_otg_driver_init</a>);
+<a name="l00892"></a>00892 
+<a name="l00899"></a><a class="code" href="dwc__otg__driver_8c.html#e50c104d9f854418331c453b9d273dce">00899</a> <span class="keyword">static</span> <span class="keywordtype">void</span> __exit <a class="code" href="dwc__otg__driver_8c.html#e50c104d9f854418331c453b9d273dce">dwc_otg_driver_cleanup</a>(<span class="keywordtype">void</span>)
+<a name="l00900"></a>00900 {
+<a name="l00901"></a>00901         printk(KERN_DEBUG <span class="stringliteral">"dwc_otg_driver_cleanup()\n"</span>);
+<a name="l00902"></a>00902 
+<a name="l00903"></a>00903 <span class="preprocessor">#ifdef LM_INTERFACE</span>
+<a name="l00904"></a>00904 <span class="preprocessor"></span>        driver_remove_file(&amp;dwc_otg_driver.drv, &amp;driver_attr_debuglevel);
+<a name="l00905"></a>00905         driver_remove_file(&amp;dwc_otg_driver.drv, &amp;driver_attr_version);
+<a name="l00906"></a>00906         lm_driver_unregister(&amp;dwc_otg_driver);
+<a name="l00907"></a>00907 <span class="preprocessor">#elif PCI_INTERFACE</span>
+<a name="l00908"></a>00908 <span class="preprocessor"></span>        driver_remove_file(&amp;dwc_otg_driver.driver, &amp;driver_attr_debuglevel);
+<a name="l00909"></a>00909         driver_remove_file(&amp;dwc_otg_driver.driver, &amp;driver_attr_version);
+<a name="l00910"></a>00910         pci_unregister_driver(&amp;dwc_otg_driver);
+<a name="l00911"></a>00911 <span class="preprocessor">#endif</span>
+<a name="l00912"></a>00912 <span class="preprocessor"></span>
+<a name="l00913"></a>00913         printk(KERN_INFO <span class="stringliteral">"%s module removed\n"</span>, <a class="code" href="dwc__otg__driver_8c.html#3f7932dcd77bb7b05f92f759e6569fe2">dwc_driver_name</a>);
+<a name="l00914"></a>00914 }
+<a name="l00915"></a>00915 module_exit(<a class="code" href="dwc__otg__driver_8c.html#e50c104d9f854418331c453b9d273dce">dwc_otg_driver_cleanup</a>);
+<a name="l00916"></a>00916 
+<a name="l00917"></a>00917 MODULE_DESCRIPTION(<a class="code" href="dwc__otg__driver_8c.html#d78dec8459bcb2092d84be524494378b">DWC_DRIVER_DESC</a>);
+<a name="l00918"></a>00918 MODULE_AUTHOR(<span class="stringliteral">"Synopsys Inc."</span>);
+<a name="l00919"></a>00919 MODULE_LICENSE(<span class="stringliteral">"GPL"</span>);
+<a name="l00920"></a>00920 
+<a name="l00921"></a>00921 module_param_named(otg_cap, <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#985f1849ab70919e756c86280a8f7ef0">otg_cap</a>, <span class="keywordtype">int</span>, 0444);
+<a name="l00922"></a>00922 MODULE_PARM_DESC(otg_cap, <span class="stringliteral">"OTG Capabilities 0=HNP&amp;SRP 1=SRP Only 2=None"</span>);
+<a name="l00923"></a>00923 module_param_named(opt, <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#bccaf8d2ce8da6d5ef0d1c81caf9e518">opt</a>, <span class="keywordtype">int</span>, 0444);
+<a name="l00924"></a>00924 MODULE_PARM_DESC(opt, <span class="stringliteral">"OPT Mode"</span>);
+<a name="l00925"></a>00925 module_param_named(dma_enable, <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#fe4469605ca0460a3e309603d7c23e86">dma_enable</a>, <span class="keywordtype">int</span>, 0444);
+<a name="l00926"></a>00926 MODULE_PARM_DESC(dma_enable, <span class="stringliteral">"DMA Mode 0=Slave 1=DMA enabled"</span>);
+<a name="l00927"></a>00927 
+<a name="l00928"></a>00928 module_param_named(dma_desc_enable, <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#cdceee2a19bb233c12893751f443c40d">dma_desc_enable</a>, <span class="keywordtype">int</span>,
+<a name="l00929"></a>00929                    0444);
+<a name="l00930"></a>00930 MODULE_PARM_DESC(dma_desc_enable,
+<a name="l00931"></a>00931                  <span class="stringliteral">"DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled"</span>);
+<a name="l00932"></a>00932 
+<a name="l00933"></a>00933 module_param_named(dma_burst_size, <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#19c1567261677aa53120cfae53b90f8d">dma_burst_size</a>, <span class="keywordtype">int</span>,
+<a name="l00934"></a>00934                    0444);
+<a name="l00935"></a>00935 MODULE_PARM_DESC(dma_burst_size,
+<a name="l00936"></a>00936                  <span class="stringliteral">"DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256"</span>);
+<a name="l00937"></a>00937 module_param_named(speed, <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#e0002437cefb2b64dc92f40fd69ef29f">speed</a>, <span class="keywordtype">int</span>, 0444);
+<a name="l00938"></a>00938 MODULE_PARM_DESC(speed, <span class="stringliteral">"Speed 0=High Speed 1=Full Speed"</span>);
+<a name="l00939"></a>00939 module_param_named(host_support_fs_ls_low_power,
+<a name="l00940"></a>00940                    <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#6f3a0a2bf5c82d296fec31fec7b765ca">host_support_fs_ls_low_power</a>, <span class="keywordtype">int</span>,
+<a name="l00941"></a>00941                    0444);
+<a name="l00942"></a>00942 MODULE_PARM_DESC(host_support_fs_ls_low_power,
+<a name="l00943"></a>00943                  <span class="stringliteral">"Support Low Power w/FS or LS 0=Support 1=Don't Support"</span>);
+<a name="l00944"></a>00944 module_param_named(host_ls_low_power_phy_clk,
+<a name="l00945"></a>00945                    <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#91c46e96e070e983e3f91c756dd4aa64">host_ls_low_power_phy_clk</a>, <span class="keywordtype">int</span>, 0444);
+<a name="l00946"></a>00946 MODULE_PARM_DESC(host_ls_low_power_phy_clk,
+<a name="l00947"></a>00947                  <span class="stringliteral">"Low Speed Low Power Clock 0=48Mhz 1=6Mhz"</span>);
+<a name="l00948"></a>00948 module_param_named(enable_dynamic_fifo,
+<a name="l00949"></a>00949                    <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#f448f6de6dcafca027bd2873b714b916">enable_dynamic_fifo</a>, <span class="keywordtype">int</span>, 0444);
+<a name="l00950"></a>00950 MODULE_PARM_DESC(enable_dynamic_fifo, <span class="stringliteral">"0=cC Setting 1=Allow Dynamic Sizing"</span>);
+<a name="l00951"></a>00951 module_param_named(data_fifo_size, <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#a9ae5039d88c52fab455235bf4f8696b">data_fifo_size</a>, <span class="keywordtype">int</span>,
+<a name="l00952"></a>00952                    0444);
+<a name="l00953"></a>00953 MODULE_PARM_DESC(data_fifo_size,
+<a name="l00954"></a>00954                  <span class="stringliteral">"Total number of words in the data FIFO memory 32-32768"</span>);
+<a name="l00955"></a>00955 module_param_named(dev_rx_fifo_size, <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#707eedd2d7794728c5188e5d5056316e">dev_rx_fifo_size</a>,
+<a name="l00956"></a>00956                    <span class="keywordtype">int</span>, 0444);
+<a name="l00957"></a>00957 MODULE_PARM_DESC(dev_rx_fifo_size, <span class="stringliteral">"Number of words in the Rx FIFO 16-32768"</span>);
+<a name="l00958"></a>00958 module_param_named(dev_nperio_tx_fifo_size,
+<a name="l00959"></a>00959                    <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#3172175dc8f08e96b63c7a8c162201f5">dev_nperio_tx_fifo_size</a>, <span class="keywordtype">int</span>, 0444);
+<a name="l00960"></a>00960 MODULE_PARM_DESC(dev_nperio_tx_fifo_size,
+<a name="l00961"></a>00961                  <span class="stringliteral">"Number of words in the non-periodic Tx FIFO 16-32768"</span>);
+<a name="l00962"></a>00962 module_param_named(dev_perio_tx_fifo_size_1,
+<a name="l00963"></a>00963                    <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#aada52f0668d5d52b8ac6281c8736283">dev_perio_tx_fifo_size</a>[0], <span class="keywordtype">int</span>, 0444);
+<a name="l00964"></a>00964 MODULE_PARM_DESC(dev_perio_tx_fifo_size_1,
+<a name="l00965"></a>00965                  <span class="stringliteral">"Number of words in the periodic Tx FIFO 4-768"</span>);
+<a name="l00966"></a>00966 module_param_named(dev_perio_tx_fifo_size_2,
+<a name="l00967"></a>00967                    <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#aada52f0668d5d52b8ac6281c8736283">dev_perio_tx_fifo_size</a>[1], <span class="keywordtype">int</span>, 0444);
+<a name="l00968"></a>00968 MODULE_PARM_DESC(dev_perio_tx_fifo_size_2,
+<a name="l00969"></a>00969                  <span class="stringliteral">"Number of words in the periodic Tx FIFO 4-768"</span>);
+<a name="l00970"></a>00970 module_param_named(dev_perio_tx_fifo_size_3,
+<a name="l00971"></a>00971                    <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#aada52f0668d5d52b8ac6281c8736283">dev_perio_tx_fifo_size</a>[2], <span class="keywordtype">int</span>, 0444);
+<a name="l00972"></a>00972 MODULE_PARM_DESC(dev_perio_tx_fifo_size_3,
+<a name="l00973"></a>00973                  <span class="stringliteral">"Number of words in the periodic Tx FIFO 4-768"</span>);
+<a name="l00974"></a>00974 module_param_named(dev_perio_tx_fifo_size_4,
+<a name="l00975"></a>00975                    <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#aada52f0668d5d52b8ac6281c8736283">dev_perio_tx_fifo_size</a>[3], <span class="keywordtype">int</span>, 0444);
+<a name="l00976"></a>00976 MODULE_PARM_DESC(dev_perio_tx_fifo_size_4,
+<a name="l00977"></a>00977                  <span class="stringliteral">"Number of words in the periodic Tx FIFO 4-768"</span>);
+<a name="l00978"></a>00978 module_param_named(dev_perio_tx_fifo_size_5,
+<a name="l00979"></a>00979                    <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#aada52f0668d5d52b8ac6281c8736283">dev_perio_tx_fifo_size</a>[4], <span class="keywordtype">int</span>, 0444);
+<a name="l00980"></a>00980 MODULE_PARM_DESC(dev_perio_tx_fifo_size_5,
+<a name="l00981"></a>00981                  <span class="stringliteral">"Number of words in the periodic Tx FIFO 4-768"</span>);
+<a name="l00982"></a>00982 module_param_named(dev_perio_tx_fifo_size_6,
+<a name="l00983"></a>00983                    <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#aada52f0668d5d52b8ac6281c8736283">dev_perio_tx_fifo_size</a>[5], <span class="keywordtype">int</span>, 0444);
+<a name="l00984"></a>00984 MODULE_PARM_DESC(dev_perio_tx_fifo_size_6,
+<a name="l00985"></a>00985                  <span class="stringliteral">"Number of words in the periodic Tx FIFO 4-768"</span>);
+<a name="l00986"></a>00986 module_param_named(dev_perio_tx_fifo_size_7,
+<a name="l00987"></a>00987                    <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#aada52f0668d5d52b8ac6281c8736283">dev_perio_tx_fifo_size</a>[6], <span class="keywordtype">int</span>, 0444);
+<a name="l00988"></a>00988 MODULE_PARM_DESC(dev_perio_tx_fifo_size_7,
+<a name="l00989"></a>00989                  <span class="stringliteral">"Number of words in the periodic Tx FIFO 4-768"</span>);
+<a name="l00990"></a>00990 module_param_named(dev_perio_tx_fifo_size_8,
+<a name="l00991"></a>00991                    <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#aada52f0668d5d52b8ac6281c8736283">dev_perio_tx_fifo_size</a>[7], <span class="keywordtype">int</span>, 0444);
+<a name="l00992"></a>00992 MODULE_PARM_DESC(dev_perio_tx_fifo_size_8,
+<a name="l00993"></a>00993                  <span class="stringliteral">"Number of words in the periodic Tx FIFO 4-768"</span>);
+<a name="l00994"></a>00994 module_param_named(dev_perio_tx_fifo_size_9,
+<a name="l00995"></a>00995                    <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#aada52f0668d5d52b8ac6281c8736283">dev_perio_tx_fifo_size</a>[8], <span class="keywordtype">int</span>, 0444);
+<a name="l00996"></a>00996 MODULE_PARM_DESC(dev_perio_tx_fifo_size_9,
+<a name="l00997"></a>00997                  <span class="stringliteral">"Number of words in the periodic Tx FIFO 4-768"</span>);
+<a name="l00998"></a>00998 module_param_named(dev_perio_tx_fifo_size_10,
+<a name="l00999"></a>00999                    <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#aada52f0668d5d52b8ac6281c8736283">dev_perio_tx_fifo_size</a>[9], <span class="keywordtype">int</span>, 0444);
+<a name="l01000"></a>01000 MODULE_PARM_DESC(dev_perio_tx_fifo_size_10,
+<a name="l01001"></a>01001                  <span class="stringliteral">"Number of words in the periodic Tx FIFO 4-768"</span>);
+<a name="l01002"></a>01002 module_param_named(dev_perio_tx_fifo_size_11,
+<a name="l01003"></a>01003                    <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#aada52f0668d5d52b8ac6281c8736283">dev_perio_tx_fifo_size</a>[10], <span class="keywordtype">int</span>, 0444);
+<a name="l01004"></a>01004 MODULE_PARM_DESC(dev_perio_tx_fifo_size_11,
+<a name="l01005"></a>01005                  <span class="stringliteral">"Number of words in the periodic Tx FIFO 4-768"</span>);
+<a name="l01006"></a>01006 module_param_named(dev_perio_tx_fifo_size_12,
+<a name="l01007"></a>01007                    <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#aada52f0668d5d52b8ac6281c8736283">dev_perio_tx_fifo_size</a>[11], <span class="keywordtype">int</span>, 0444);
+<a name="l01008"></a>01008 MODULE_PARM_DESC(dev_perio_tx_fifo_size_12,
+<a name="l01009"></a>01009                  <span class="stringliteral">"Number of words in the periodic Tx FIFO 4-768"</span>);
+<a name="l01010"></a>01010 module_param_named(dev_perio_tx_fifo_size_13,
+<a name="l01011"></a>01011                    <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#aada52f0668d5d52b8ac6281c8736283">dev_perio_tx_fifo_size</a>[12], <span class="keywordtype">int</span>, 0444);
+<a name="l01012"></a>01012 MODULE_PARM_DESC(dev_perio_tx_fifo_size_13,
+<a name="l01013"></a>01013                  <span class="stringliteral">"Number of words in the periodic Tx FIFO 4-768"</span>);
+<a name="l01014"></a>01014 module_param_named(dev_perio_tx_fifo_size_14,
+<a name="l01015"></a>01015                    <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#aada52f0668d5d52b8ac6281c8736283">dev_perio_tx_fifo_size</a>[13], <span class="keywordtype">int</span>, 0444);
+<a name="l01016"></a>01016 MODULE_PARM_DESC(dev_perio_tx_fifo_size_14,
+<a name="l01017"></a>01017                  <span class="stringliteral">"Number of words in the periodic Tx FIFO 4-768"</span>);
+<a name="l01018"></a>01018 module_param_named(dev_perio_tx_fifo_size_15,
+<a name="l01019"></a>01019                    <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#aada52f0668d5d52b8ac6281c8736283">dev_perio_tx_fifo_size</a>[14], <span class="keywordtype">int</span>, 0444);
+<a name="l01020"></a>01020 MODULE_PARM_DESC(dev_perio_tx_fifo_size_15,
+<a name="l01021"></a>01021                  <span class="stringliteral">"Number of words in the periodic Tx FIFO 4-768"</span>);
+<a name="l01022"></a>01022 module_param_named(host_rx_fifo_size, <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#1f490daab4c4e08d2773f46d51f1f5f7">host_rx_fifo_size</a>,
+<a name="l01023"></a>01023                    <span class="keywordtype">int</span>, 0444);
+<a name="l01024"></a>01024 MODULE_PARM_DESC(host_rx_fifo_size, <span class="stringliteral">"Number of words in the Rx FIFO 16-32768"</span>);
+<a name="l01025"></a>01025 module_param_named(host_nperio_tx_fifo_size,
+<a name="l01026"></a>01026                    <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#edf2038417f58acd8dab202a8ca19d2a">host_nperio_tx_fifo_size</a>, <span class="keywordtype">int</span>, 0444);
+<a name="l01027"></a>01027 MODULE_PARM_DESC(host_nperio_tx_fifo_size,
+<a name="l01028"></a>01028                  <span class="stringliteral">"Number of words in the non-periodic Tx FIFO 16-32768"</span>);
+<a name="l01029"></a>01029 module_param_named(host_perio_tx_fifo_size,
+<a name="l01030"></a>01030                    <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#bdc820350ca3b6aec5ac435c9712ccd5">host_perio_tx_fifo_size</a>, <span class="keywordtype">int</span>, 0444);
+<a name="l01031"></a>01031 MODULE_PARM_DESC(host_perio_tx_fifo_size,
+<a name="l01032"></a>01032                  <span class="stringliteral">"Number of words in the host periodic Tx FIFO 16-32768"</span>);
+<a name="l01033"></a>01033 module_param_named(max_transfer_size, <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#16cc5351ae1dfbcd81d56a7ec16e1748">max_transfer_size</a>,
+<a name="l01034"></a>01034                    <span class="keywordtype">int</span>, 0444);
+<a name="l01036"></a>01036 MODULE_PARM_DESC(max_transfer_size,
+<a name="l01037"></a>01037                  <span class="stringliteral">"The maximum transfer size supported in bytes 2047-65535"</span>);
+<a name="l01038"></a>01038 module_param_named(max_packet_count, <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#bb7904edc790fce40ac04ed68a64217e">max_packet_count</a>,
+<a name="l01039"></a>01039                    <span class="keywordtype">int</span>, 0444);
+<a name="l01040"></a>01040 MODULE_PARM_DESC(max_packet_count,
+<a name="l01041"></a>01041                  <span class="stringliteral">"The maximum number of packets in a transfer 15-511"</span>);
+<a name="l01042"></a>01042 module_param_named(host_channels, <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#4727585082d86c52396adfde0cfffa17">host_channels</a>, <span class="keywordtype">int</span>,
+<a name="l01043"></a>01043                    0444);
+<a name="l01044"></a>01044 MODULE_PARM_DESC(host_channels,
+<a name="l01045"></a>01045                  <span class="stringliteral">"The number of host channel registers to use 1-16"</span>);
+<a name="l01046"></a>01046 module_param_named(dev_endpoints, <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#c1c36daec6af25fb425c85a696c445e4">dev_endpoints</a>, <span class="keywordtype">int</span>,
+<a name="l01047"></a>01047                    0444);
+<a name="l01048"></a>01048 MODULE_PARM_DESC(dev_endpoints,
+<a name="l01049"></a>01049                  <span class="stringliteral">"The number of endpoints in addition to EP0 available for device mode 1-15"</span>);
+<a name="l01050"></a>01050 module_param_named(phy_type, <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#77d1c10524440ed2e5189624157526ac">phy_type</a>, <span class="keywordtype">int</span>, 0444);
+<a name="l01051"></a>01051 MODULE_PARM_DESC(phy_type, <span class="stringliteral">"0=Reserved 1=UTMI+ 2=ULPI"</span>);
+<a name="l01052"></a>01052 module_param_named(phy_utmi_width, <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#f6284c33f13fe2f02491fa1a0c479b25">phy_utmi_width</a>, <span class="keywordtype">int</span>,
+<a name="l01053"></a>01053                    0444);
+<a name="l01054"></a>01054 MODULE_PARM_DESC(phy_utmi_width, <span class="stringliteral">"Specifies the UTMI+ Data Width 8 or 16 bits"</span>);
+<a name="l01055"></a>01055 module_param_named(phy_ulpi_ddr, <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#6a2b8c0c6298a7b1da23d5dd5abc4da8">phy_ulpi_ddr</a>, <span class="keywordtype">int</span>, 0444);
+<a name="l01056"></a>01056 MODULE_PARM_DESC(phy_ulpi_ddr,
+<a name="l01057"></a>01057                  <span class="stringliteral">"ULPI at double or single data rate 0=Single 1=Double"</span>);
+<a name="l01058"></a>01058 module_param_named(phy_ulpi_ext_vbus, <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#8402de29e6ec24baa5881cb7d74914c2">phy_ulpi_ext_vbus</a>,
+<a name="l01059"></a>01059                    <span class="keywordtype">int</span>, 0444);
+<a name="l01060"></a>01060 MODULE_PARM_DESC(phy_ulpi_ext_vbus,
+<a name="l01061"></a>01061                  <span class="stringliteral">"ULPI PHY using internal or external vbus 0=Internal"</span>);
+<a name="l01062"></a>01062 module_param_named(i2c_enable, <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#4e1d822cfcc6332fcaa0471bb1ca0d54">i2c_enable</a>, <span class="keywordtype">int</span>, 0444);
+<a name="l01063"></a>01063 MODULE_PARM_DESC(i2c_enable, <span class="stringliteral">"FS PHY Interface"</span>);
+<a name="l01064"></a>01064 module_param_named(ulpi_fs_ls, <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#33489751a5cef9e462d26e92caae3031">ulpi_fs_ls</a>, <span class="keywordtype">int</span>, 0444);
+<a name="l01065"></a>01065 MODULE_PARM_DESC(ulpi_fs_ls, <span class="stringliteral">"ULPI PHY FS/LS mode only"</span>);
+<a name="l01066"></a>01066 module_param_named(ts_dline, <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#25f8f9c3558aa01fecf8bcd1527ee6cc">ts_dline</a>, <span class="keywordtype">int</span>, 0444);
+<a name="l01067"></a>01067 MODULE_PARM_DESC(ts_dline, <span class="stringliteral">"Term select Dline pulsing for all PHYs"</span>);
+<a name="l01068"></a>01068 module_param_named(debug, <a class="code" href="dwc__otg__dbg_8h.html#7ef4ada2ebb5f1aadf3be4d7fbf8ce62">g_dbg_lvl</a>, <span class="keywordtype">int</span>, 0444);
+<a name="l01069"></a>01069 MODULE_PARM_DESC(debug, <span class="stringliteral">""</span>);
+<a name="l01070"></a>01070 
+<a name="l01071"></a>01071 module_param_named(en_multiple_tx_fifo,
+<a name="l01072"></a>01072                    <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#13860bb2c8d23e40088703289e6ae835">en_multiple_tx_fifo</a>, <span class="keywordtype">int</span>, 0444);
+<a name="l01073"></a>01073 MODULE_PARM_DESC(en_multiple_tx_fifo,
+<a name="l01074"></a>01074                  <span class="stringliteral">"Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled"</span>);
+<a name="l01075"></a>01075 module_param_named(dev_tx_fifo_size_1,
+<a name="l01076"></a>01076                    <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#d1c3fbc5325b13e1191388b76795b848">dev_tx_fifo_size</a>[0], <span class="keywordtype">int</span>, 0444);
+<a name="l01077"></a>01077 MODULE_PARM_DESC(dev_tx_fifo_size_1, <span class="stringliteral">"Number of words in the Tx FIFO 4-768"</span>);
+<a name="l01078"></a>01078 module_param_named(dev_tx_fifo_size_2,
+<a name="l01079"></a>01079                    <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#d1c3fbc5325b13e1191388b76795b848">dev_tx_fifo_size</a>[1], <span class="keywordtype">int</span>, 0444);
+<a name="l01080"></a>01080 MODULE_PARM_DESC(dev_tx_fifo_size_2, <span class="stringliteral">"Number of words in the Tx FIFO 4-768"</span>);
+<a name="l01081"></a>01081 module_param_named(dev_tx_fifo_size_3,
+<a name="l01082"></a>01082                    <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#d1c3fbc5325b13e1191388b76795b848">dev_tx_fifo_size</a>[2], <span class="keywordtype">int</span>, 0444);
+<a name="l01083"></a>01083 MODULE_PARM_DESC(dev_tx_fifo_size_3, <span class="stringliteral">"Number of words in the Tx FIFO 4-768"</span>);
+<a name="l01084"></a>01084 module_param_named(dev_tx_fifo_size_4,
+<a name="l01085"></a>01085                    <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#d1c3fbc5325b13e1191388b76795b848">dev_tx_fifo_size</a>[3], <span class="keywordtype">int</span>, 0444);
+<a name="l01086"></a>01086 MODULE_PARM_DESC(dev_tx_fifo_size_4, <span class="stringliteral">"Number of words in the Tx FIFO 4-768"</span>);
+<a name="l01087"></a>01087 module_param_named(dev_tx_fifo_size_5,
+<a name="l01088"></a>01088                    <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#d1c3fbc5325b13e1191388b76795b848">dev_tx_fifo_size</a>[4], <span class="keywordtype">int</span>, 0444);
+<a name="l01089"></a>01089 MODULE_PARM_DESC(dev_tx_fifo_size_5, <span class="stringliteral">"Number of words in the Tx FIFO 4-768"</span>);
+<a name="l01090"></a>01090 module_param_named(dev_tx_fifo_size_6,
+<a name="l01091"></a>01091                    <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#d1c3fbc5325b13e1191388b76795b848">dev_tx_fifo_size</a>[5], <span class="keywordtype">int</span>, 0444);
+<a name="l01092"></a>01092 MODULE_PARM_DESC(dev_tx_fifo_size_6, <span class="stringliteral">"Number of words in the Tx FIFO 4-768"</span>);
+<a name="l01093"></a>01093 module_param_named(dev_tx_fifo_size_7,
+<a name="l01094"></a>01094                    <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#d1c3fbc5325b13e1191388b76795b848">dev_tx_fifo_size</a>[6], <span class="keywordtype">int</span>, 0444);
+<a name="l01095"></a>01095 MODULE_PARM_DESC(dev_tx_fifo_size_7, <span class="stringliteral">"Number of words in the Tx FIFO 4-768"</span>);
+<a name="l01096"></a>01096 module_param_named(dev_tx_fifo_size_8,
+<a name="l01097"></a>01097                    <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#d1c3fbc5325b13e1191388b76795b848">dev_tx_fifo_size</a>[7], <span class="keywordtype">int</span>, 0444);
+<a name="l01098"></a>01098 MODULE_PARM_DESC(dev_tx_fifo_size_8, <span class="stringliteral">"Number of words in the Tx FIFO 4-768"</span>);
+<a name="l01099"></a>01099 module_param_named(dev_tx_fifo_size_9,
+<a name="l01100"></a>01100                    <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#d1c3fbc5325b13e1191388b76795b848">dev_tx_fifo_size</a>[8], <span class="keywordtype">int</span>, 0444);
+<a name="l01101"></a>01101 MODULE_PARM_DESC(dev_tx_fifo_size_9, <span class="stringliteral">"Number of words in the Tx FIFO 4-768"</span>);
+<a name="l01102"></a>01102 module_param_named(dev_tx_fifo_size_10,
+<a name="l01103"></a>01103                    <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#d1c3fbc5325b13e1191388b76795b848">dev_tx_fifo_size</a>[9], <span class="keywordtype">int</span>, 0444);
+<a name="l01104"></a>01104 MODULE_PARM_DESC(dev_tx_fifo_size_10, <span class="stringliteral">"Number of words in the Tx FIFO 4-768"</span>);
+<a name="l01105"></a>01105 module_param_named(dev_tx_fifo_size_11,
+<a name="l01106"></a>01106                    <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#d1c3fbc5325b13e1191388b76795b848">dev_tx_fifo_size</a>[10], <span class="keywordtype">int</span>, 0444);
+<a name="l01107"></a>01107 MODULE_PARM_DESC(dev_tx_fifo_size_11, <span class="stringliteral">"Number of words in the Tx FIFO 4-768"</span>);
+<a name="l01108"></a>01108 module_param_named(dev_tx_fifo_size_12,
+<a name="l01109"></a>01109                    <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#d1c3fbc5325b13e1191388b76795b848">dev_tx_fifo_size</a>[11], <span class="keywordtype">int</span>, 0444);
+<a name="l01110"></a>01110 MODULE_PARM_DESC(dev_tx_fifo_size_12, <span class="stringliteral">"Number of words in the Tx FIFO 4-768"</span>);
+<a name="l01111"></a>01111 module_param_named(dev_tx_fifo_size_13,
+<a name="l01112"></a>01112                    <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#d1c3fbc5325b13e1191388b76795b848">dev_tx_fifo_size</a>[12], <span class="keywordtype">int</span>, 0444);
+<a name="l01113"></a>01113 MODULE_PARM_DESC(dev_tx_fifo_size_13, <span class="stringliteral">"Number of words in the Tx FIFO 4-768"</span>);
+<a name="l01114"></a>01114 module_param_named(dev_tx_fifo_size_14,
+<a name="l01115"></a>01115                    <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#d1c3fbc5325b13e1191388b76795b848">dev_tx_fifo_size</a>[13], <span class="keywordtype">int</span>, 0444);
+<a name="l01116"></a>01116 MODULE_PARM_DESC(dev_tx_fifo_size_14, <span class="stringliteral">"Number of words in the Tx FIFO 4-768"</span>);
+<a name="l01117"></a>01117 module_param_named(dev_tx_fifo_size_15,
+<a name="l01118"></a>01118                    <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#d1c3fbc5325b13e1191388b76795b848">dev_tx_fifo_size</a>[14], <span class="keywordtype">int</span>, 0444);
+<a name="l01119"></a>01119 MODULE_PARM_DESC(dev_tx_fifo_size_15, <span class="stringliteral">"Number of words in the Tx FIFO 4-768"</span>);
+<a name="l01120"></a>01120 
+<a name="l01121"></a>01121 module_param_named(thr_ctl, <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#7fe5c7ff692926fb5cbe3b10d4123594">thr_ctl</a>, <span class="keywordtype">int</span>, 0444);
+<a name="l01122"></a>01122 MODULE_PARM_DESC(thr_ctl,
+<a name="l01123"></a>01123                  <span class="stringliteral">"Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled"</span>);
+<a name="l01124"></a>01124 module_param_named(tx_thr_length, <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#04d15f44d06c291acfeef82812bd1c65">tx_thr_length</a>, <span class="keywordtype">int</span>,
+<a name="l01125"></a>01125                    0444);
+<a name="l01126"></a>01126 MODULE_PARM_DESC(tx_thr_length, <span class="stringliteral">"Tx Threshold length in 32 bit DWORDs"</span>);
+<a name="l01127"></a>01127 module_param_named(rx_thr_length, <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#eecdc71dde5ce0543a04d541a90f79bc">rx_thr_length</a>, <span class="keywordtype">int</span>,
+<a name="l01128"></a>01128                    0444);
+<a name="l01129"></a>01129 MODULE_PARM_DESC(rx_thr_length, <span class="stringliteral">"Rx Threshold length in 32 bit DWORDs"</span>);
+<a name="l01130"></a>01130 
+<a name="l01131"></a>01131 module_param_named(pti_enable, <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#2e17f84d9b07732a7fdf37b13832c54a">pti_enable</a>, <span class="keywordtype">int</span>, 0444);
+<a name="l01132"></a>01132 module_param_named(mpi_enable, <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#484412984c814a6298b05b58d94bd730">mpi_enable</a>, <span class="keywordtype">int</span>, 0444);
+<a name="l01133"></a>01133 module_param_named(lpm_enable, <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#bb4e33c533d53de007814f0e5a70dd8a">lpm_enable</a>, <span class="keywordtype">int</span>, 0444);
+<a name="l01134"></a>01134 MODULE_PARM_DESC(lpm_enable, <span class="stringliteral">"LPM Enable 0=LPM Disabled 1=LPM Enabled"</span>);
+<a name="l01135"></a>01135 module_param_named(ic_usb_cap, <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#ed3802eea4e62cd79ef7d8701d45b506">ic_usb_cap</a>, <span class="keywordtype">int</span>, 0444);
+<a name="l01136"></a>01136 MODULE_PARM_DESC(ic_usb_cap,
+<a name="l01137"></a>01137                  <span class="stringliteral">"IC_USB Capability 0=IC_USB Disabled 1=IC_USB Enabled"</span>);
+<a name="l01138"></a>01138 module_param_named(ahb_thr_ratio, <a class="code" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a>.<a class="code" href="structdwc__otg__driver__module__params.html#b450246efcbc087eb36b0979040162ca">ahb_thr_ratio</a>, <span class="keywordtype">int</span>, 0444);
+<a name="l01139"></a>01139 MODULE_PARM_DESC(ahb_thr_ratio, <span class="stringliteral">"AHB Threshold Ratio"</span>);
+<a name="l01140"></a>01140 
+</pre></div><hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/dwc__otg__driver_8c.html b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__driver_8c.html
new file mode 100644
index 000000000000..33071a8d22d7
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__driver_8c.html
@@ -0,0 +1,719 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_driver.c File Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<h1>dwc_otg_driver.c File Reference</h1>The dwc_otg_driver module provides the initialization and cleanup entry points for the DWC_otg driver. <a href="#_details">More...</a>
+<p>
+<code>#include &lt;linux/kernel.h&gt;</code><br>
+<code>#include &lt;linux/module.h&gt;</code><br>
+<code>#include &lt;linux/moduleparam.h&gt;</code><br>
+<code>#include &lt;linux/init.h&gt;</code><br>
+<code>#include &lt;linux/device.h&gt;</code><br>
+<code>#include &lt;linux/errno.h&gt;</code><br>
+<code>#include &lt;linux/types.h&gt;</code><br>
+<code>#include &lt;linux/stat.h&gt;</code><br>
+<code>#include &lt;linux/version.h&gt;</code><br>
+<code>#include &lt;linux/interrupt.h&gt;</code><br>
+<code>#include &lt;linux/irq.h&gt;</code><br>
+<code>#include &lt;asm/io.h&gt;</code><br>
+<code>#include &quot;dwc_os.h&quot;</code><br>
+<code>#include &quot;<a class="el" href="dwc__otg__dbg_8h-source.html">dwc_otg_dbg.h</a>&quot;</code><br>
+<code>#include &quot;<a class="el" href="dwc__otg__driver_8h-source.html">dwc_otg_driver.h</a>&quot;</code><br>
+<code>#include &quot;<a class="el" href="dwc__otg__attr_8h-source.html">dwc_otg_attr.h</a>&quot;</code><br>
+<code>#include &quot;<a class="el" href="dwc__otg__core__if_8h-source.html">dwc_otg_core_if.h</a>&quot;</code><br>
+<code>#include &quot;<a class="el" href="dwc__otg__pcd__if_8h-source.html">dwc_otg_pcd_if.h</a>&quot;</code><br>
+<code>#include &quot;<a class="el" href="dwc__otg__hcd__if_8h-source.html">dwc_otg_hcd_if.h</a>&quot;</code><br>
+
+<p>
+<a href="dwc__otg__driver_8c-source.html">Go to the source code of this file.</a><table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Structures</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__driver__module__params.html">dwc_otg_driver_module_params</a></td></tr>
+
+<tr><td colspan="2"><br><h2>Defines</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7fb7b6d344624c19c1d920239458999a"></a><!-- doxytag: member="dwc_otg_driver.c::DWC_DRIVER_VERSION" ref="7fb7b6d344624c19c1d920239458999a" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__driver_8c.html#7fb7b6d344624c19c1d920239458999a">DWC_DRIVER_VERSION</a>&nbsp;&nbsp;&nbsp;&quot;2.90a 23-APR-2009&quot;</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="d78dec8459bcb2092d84be524494378b"></a><!-- doxytag: member="dwc_otg_driver.c::DWC_DRIVER_DESC" ref="d78dec8459bcb2092d84be524494378b" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__driver_8c.html#d78dec8459bcb2092d84be524494378b">DWC_DRIVER_DESC</a>&nbsp;&nbsp;&nbsp;&quot;HS OTG USB Controller driver&quot;</td></tr>
+
+<tr><td colspan="2"><br><h2>Functions</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="9dbc565a7942db0adbf1ec341db22901"></a><!-- doxytag: member="dwc_otg_driver.c::pcd_init" ref="9dbc565a7942db0adbf1ec341db22901" args="()" -->
+int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__driver_8c.html#9dbc565a7942db0adbf1ec341db22901">pcd_init</a> ()</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function initialized the PCD portion of the driver. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__driver_8c.html#ab12cdf65bf4ed68545a6c17cc31269f">hcd_init</a> ()</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Initializes the HCD.  <a href="#ab12cdf65bf4ed68545a6c17cc31269f"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7960b8e2c02d9ab89b65cb01ba08658b"></a><!-- doxytag: member="dwc_otg_driver.c::pcd_remove" ref="7960b8e2c02d9ab89b65cb01ba08658b" args="()" -->
+int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__driver_8c.html#7960b8e2c02d9ab89b65cb01ba08658b">pcd_remove</a> ()</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Cleanup the PCD. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__driver_8c.html#f36193b3ff33c0473956c8a15eee4f5b">hcd_remove</a> ()</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Removes the HCD.  <a href="#f36193b3ff33c0473956c8a15eee4f5b"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="6eaf4dedcf1df7eb80c48f1872212012"></a><!-- doxytag: member="dwc_otg_driver.c::version_show" ref="6eaf4dedcf1df7eb80c48f1872212012" args="(struct device_driver *dev, char *buf)" -->
+static ssize_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__driver_8c.html#6eaf4dedcf1df7eb80c48f1872212012">version_show</a> (struct device_driver *dev, char *buf)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function shows the Driver Version. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c17c8f80bcc472074f8d981287991a8c"></a><!-- doxytag: member="dwc_otg_driver.c::DRIVER_ATTR" ref="c17c8f80bcc472074f8d981287991a8c" args="(version, S_IRUGO, version_show, NULL)" -->
+static&nbsp;</td><td class="memItemRight" valign="bottom"><b>DRIVER_ATTR</b> (version, S_IRUGO, version_show, NULL)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="1e2b7516063b70cc1eaecc8d286b0689"></a><!-- doxytag: member="dwc_otg_driver.c::dbg_level_show" ref="1e2b7516063b70cc1eaecc8d286b0689" args="(struct device_driver *drv, char *buf)" -->
+static ssize_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__driver_8c.html#1e2b7516063b70cc1eaecc8d286b0689">dbg_level_show</a> (struct device_driver *drv, char *buf)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function shows the driver Debug Level. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e886456741506f66ce4adc5b843dc055"></a><!-- doxytag: member="dwc_otg_driver.c::dbg_level_store" ref="e886456741506f66ce4adc5b843dc055" args="(struct device_driver *drv, const char *buf, size_t count)" -->
+static ssize_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__driver_8c.html#e886456741506f66ce4adc5b843dc055">dbg_level_store</a> (struct device_driver *drv, const char *buf, size_t count)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function stores the driver Debug Level. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="cca1716e4b738ed1dfb6a4c83c50f801"></a><!-- doxytag: member="dwc_otg_driver.c::DRIVER_ATTR" ref="cca1716e4b738ed1dfb6a4c83c50f801" args="(debuglevel, S_IRUGO|S_IWUSR, dbg_level_show, dbg_level_store)" -->
+static&nbsp;</td><td class="memItemRight" valign="bottom"><b>DRIVER_ATTR</b> (debuglevel, S_IRUGO|<a class="el" href="dwc__otg__attr_8c.html#ac2308832629daf78cb9dd123551cd8a">S_IWUSR</a>, dbg_level_show, dbg_level_store)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="fe3a3765da365671b36ba5e28dc4d38b"></a><!-- doxytag: member="dwc_otg_driver.c::set_parameters" ref="fe3a3765da365671b36ba5e28dc4d38b" args="(dwc_otg_core_if_t *core_if)" -->
+static int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__driver_8c.html#fe3a3765da365671b36ba5e28dc4d38b">set_parameters</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function is called during module intialization to pass module parameters to the DWC_OTG CORE. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="8850871557165b76b72f28723e4ec450"></a><!-- doxytag: member="dwc_otg_driver.c::dwc_otg_common_irq" ref="8850871557165b76b72f28723e4ec450" args="(int irq, void *dev)" -->
+static irqreturn_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__driver_8c.html#8850871557165b76b72f28723e4ec450">dwc_otg_common_irq</a> (int irq, void *dev)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function is the top level interrupt handler for the Common (Device and host modes) interrupts. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__driver_8c.html#fe9abf2a1dda4c02d24f5cb1d7a9a94d">dwc_otg_driver_remove</a> ()</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function is called when a lm_device is unregistered with the dwc_otg_driver.  <a href="#fe9abf2a1dda4c02d24f5cb1d7a9a94d"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__driver_8c.html#10921617ecc621f0448d4f9ab6a0f7b7">dwc_otg_driver_probe</a> ()</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function is called when an lm_device is bound to a dwc_otg_driver.  <a href="#10921617ecc621f0448d4f9ab6a0f7b7"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static int __init&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__driver_8c.html#737f516e934e7f479e31bf7261dd3830">dwc_otg_driver_init</a> (void)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function is called when the dwc_otg_driver is installed with the insmod command.  <a href="#737f516e934e7f479e31bf7261dd3830"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="d90fb9ba87223672b3c5b41ca13e6e1c"></a><!-- doxytag: member="dwc_otg_driver.c::module_init" ref="d90fb9ba87223672b3c5b41ca13e6e1c" args="(dwc_otg_driver_init)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>module_init</b> (dwc_otg_driver_init)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static void __exit&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__driver_8c.html#e50c104d9f854418331c453b9d273dce">dwc_otg_driver_cleanup</a> (void)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function is called when the driver is removed from the kernel with the rmmod command.  <a href="#e50c104d9f854418331c453b9d273dce"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="72d1eabe43cdc2b436fabcedd7c13665"></a><!-- doxytag: member="dwc_otg_driver.c::module_exit" ref="72d1eabe43cdc2b436fabcedd7c13665" args="(dwc_otg_driver_cleanup)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>module_exit</b> (dwc_otg_driver_cleanup)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b1af4bbad9729eaf1fcf1861428a1039"></a><!-- doxytag: member="dwc_otg_driver.c::MODULE_DESCRIPTION" ref="b1af4bbad9729eaf1fcf1861428a1039" args="(DWC_DRIVER_DESC)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>MODULE_DESCRIPTION</b> (DWC_DRIVER_DESC)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="a9af0723987924e9ef7c4eaae836cbc9"></a><!-- doxytag: member="dwc_otg_driver.c::MODULE_AUTHOR" ref="a9af0723987924e9ef7c4eaae836cbc9" args="(&quot;Synopsys Inc.&quot;)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>MODULE_AUTHOR</b> (&quot;Synopsys Inc.&quot;)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="bc9a450561b6a4c48903aa92ad882126"></a><!-- doxytag: member="dwc_otg_driver.c::MODULE_LICENSE" ref="bc9a450561b6a4c48903aa92ad882126" args="(&quot;GPL&quot;)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>MODULE_LICENSE</b> (&quot;GPL&quot;)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="2fe357271f6b8e3021da1c80f066c03c"></a><!-- doxytag: member="dwc_otg_driver.c::module_param_named" ref="2fe357271f6b8e3021da1c80f066c03c" args="(otg_cap, dwc_otg_module_params.otg_cap, int, 0444)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>module_param_named</b> (otg_cap, dwc_otg_module_params.otg_cap, int, 0444)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="4a718daae9610ee65b141d1c4253ac02"></a><!-- doxytag: member="dwc_otg_driver.c::MODULE_PARM_DESC" ref="4a718daae9610ee65b141d1c4253ac02" args="(otg_cap,&quot;OTG Capabilities 0=HNP&amp;SRP 1=SRP Only 2=None&quot;)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>MODULE_PARM_DESC</b> (otg_cap,&quot;OTG Capabilities 0=HNP&amp;SRP 1=SRP Only 2=None&quot;)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="8aea04f3583c98e458123914a19f8f4d"></a><!-- doxytag: member="dwc_otg_driver.c::module_param_named" ref="8aea04f3583c98e458123914a19f8f4d" args="(opt, dwc_otg_module_params.opt, int, 0444)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>module_param_named</b> (opt, dwc_otg_module_params.opt, int, 0444)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="781be249f8d80cff5c5a05b8a74bcf71"></a><!-- doxytag: member="dwc_otg_driver.c::MODULE_PARM_DESC" ref="781be249f8d80cff5c5a05b8a74bcf71" args="(opt,&quot;OPT Mode&quot;)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>MODULE_PARM_DESC</b> (opt,&quot;OPT Mode&quot;)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7c512a01c276144419fb4e9fbf5799a7"></a><!-- doxytag: member="dwc_otg_driver.c::module_param_named" ref="7c512a01c276144419fb4e9fbf5799a7" args="(dma_enable, dwc_otg_module_params.dma_enable, int, 0444)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>module_param_named</b> (dma_enable, dwc_otg_module_params.dma_enable, int, 0444)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="53fed09b33862e2c34947022d6cc03c5"></a><!-- doxytag: member="dwc_otg_driver.c::MODULE_PARM_DESC" ref="53fed09b33862e2c34947022d6cc03c5" args="(dma_enable,&quot;DMA Mode 0=Slave 1=DMA enabled&quot;)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>MODULE_PARM_DESC</b> (dma_enable,&quot;DMA Mode 0=Slave 1=DMA enabled&quot;)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f2090a217346bfb2f41df35fa0f2cbbd"></a><!-- doxytag: member="dwc_otg_driver.c::module_param_named" ref="f2090a217346bfb2f41df35fa0f2cbbd" args="(dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int, 0444)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>module_param_named</b> (dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int, 0444)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="de7f22bee84d031acbcf34723a737526"></a><!-- doxytag: member="dwc_otg_driver.c::MODULE_PARM_DESC" ref="de7f22bee84d031acbcf34723a737526" args="(dma_desc_enable,&quot;DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled&quot;)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>MODULE_PARM_DESC</b> (dma_desc_enable,&quot;DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled&quot;)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="d4ad9a41be256deed35eb6458258c7c9"></a><!-- doxytag: member="dwc_otg_driver.c::module_param_named" ref="d4ad9a41be256deed35eb6458258c7c9" args="(dma_burst_size, dwc_otg_module_params.dma_burst_size, int, 0444)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>module_param_named</b> (dma_burst_size, dwc_otg_module_params.dma_burst_size, int, 0444)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e659251517aca2175df0c6de27f92577"></a><!-- doxytag: member="dwc_otg_driver.c::MODULE_PARM_DESC" ref="e659251517aca2175df0c6de27f92577" args="(dma_burst_size,&quot;DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256&quot;)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>MODULE_PARM_DESC</b> (dma_burst_size,&quot;DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256&quot;)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="d63417f83156a365b60fbfb0b93fe480"></a><!-- doxytag: member="dwc_otg_driver.c::module_param_named" ref="d63417f83156a365b60fbfb0b93fe480" args="(speed, dwc_otg_module_params.speed, int, 0444)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>module_param_named</b> (speed, dwc_otg_module_params.speed, int, 0444)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="1252a018856492895d777d3840690c94"></a><!-- doxytag: member="dwc_otg_driver.c::MODULE_PARM_DESC" ref="1252a018856492895d777d3840690c94" args="(speed,&quot;Speed 0=High Speed 1=Full Speed&quot;)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>MODULE_PARM_DESC</b> (speed,&quot;Speed 0=High Speed 1=Full Speed&quot;)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="deff6f05700e28deb1bbb0e3270233ad"></a><!-- doxytag: member="dwc_otg_driver.c::module_param_named" ref="deff6f05700e28deb1bbb0e3270233ad" args="(host_support_fs_ls_low_power, dwc_otg_module_params.host_support_fs_ls_low_power, int, 0444)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>module_param_named</b> (host_support_fs_ls_low_power, dwc_otg_module_params.host_support_fs_ls_low_power, int, 0444)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="dcf570f9097adf5a8d1ef285d09bfe39"></a><!-- doxytag: member="dwc_otg_driver.c::MODULE_PARM_DESC" ref="dcf570f9097adf5a8d1ef285d09bfe39" args="(host_support_fs_ls_low_power,&quot;Support Low Power w/FS or LS 0=Support 1=Don't Support&quot;)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>MODULE_PARM_DESC</b> (host_support_fs_ls_low_power,&quot;Support Low Power w/FS or LS 0=Support 1=Don't Support&quot;)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ecbc31127cb3b28facdb7ab8d934ee3a"></a><!-- doxytag: member="dwc_otg_driver.c::module_param_named" ref="ecbc31127cb3b28facdb7ab8d934ee3a" args="(host_ls_low_power_phy_clk, dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>module_param_named</b> (host_ls_low_power_phy_clk, dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="914cc8b3f7a44e3fa77f8332e2e734ee"></a><!-- doxytag: member="dwc_otg_driver.c::MODULE_PARM_DESC" ref="914cc8b3f7a44e3fa77f8332e2e734ee" args="(host_ls_low_power_phy_clk,&quot;Low Speed Low Power Clock 0=48Mhz 1=6Mhz&quot;)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>MODULE_PARM_DESC</b> (host_ls_low_power_phy_clk,&quot;Low Speed Low Power Clock 0=48Mhz 1=6Mhz&quot;)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c6f80851f3f37b0c3ea40aae830b93b7"></a><!-- doxytag: member="dwc_otg_driver.c::module_param_named" ref="c6f80851f3f37b0c3ea40aae830b93b7" args="(enable_dynamic_fifo, dwc_otg_module_params.enable_dynamic_fifo, int, 0444)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>module_param_named</b> (enable_dynamic_fifo, dwc_otg_module_params.enable_dynamic_fifo, int, 0444)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="6089f321396a8654b594bbb0cbce51ca"></a><!-- doxytag: member="dwc_otg_driver.c::MODULE_PARM_DESC" ref="6089f321396a8654b594bbb0cbce51ca" args="(enable_dynamic_fifo,&quot;0=cC Setting 1=Allow Dynamic Sizing&quot;)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>MODULE_PARM_DESC</b> (enable_dynamic_fifo,&quot;0=cC Setting 1=Allow Dynamic Sizing&quot;)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="66ad40d40b8e6e987f249e5571879fd5"></a><!-- doxytag: member="dwc_otg_driver.c::module_param_named" ref="66ad40d40b8e6e987f249e5571879fd5" args="(data_fifo_size, dwc_otg_module_params.data_fifo_size, int, 0444)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>module_param_named</b> (data_fifo_size, dwc_otg_module_params.data_fifo_size, int, 0444)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="efa6ec77fa8c3a6c81b9ce1b1fab4eac"></a><!-- doxytag: member="dwc_otg_driver.c::MODULE_PARM_DESC" ref="efa6ec77fa8c3a6c81b9ce1b1fab4eac" args="(data_fifo_size,&quot;Total number of words in the data FIFO memory 32-32768&quot;)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>MODULE_PARM_DESC</b> (data_fifo_size,&quot;Total number of words in the data FIFO memory 32-32768&quot;)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="8b43e21915aa1fd3dc215d899dcea2f1"></a><!-- doxytag: member="dwc_otg_driver.c::module_param_named" ref="8b43e21915aa1fd3dc215d899dcea2f1" args="(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size, int, 0444)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>module_param_named</b> (dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size, int, 0444)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="11d8aff1ba2b273b60d8daf5fe0a7416"></a><!-- doxytag: member="dwc_otg_driver.c::MODULE_PARM_DESC" ref="11d8aff1ba2b273b60d8daf5fe0a7416" args="(dev_rx_fifo_size,&quot;Number of words in the Rx FIFO 16-32768&quot;)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>MODULE_PARM_DESC</b> (dev_rx_fifo_size,&quot;Number of words in the Rx FIFO 16-32768&quot;)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="edfafba6c954cbe71b8c4bc47e13720d"></a><!-- doxytag: member="dwc_otg_driver.c::module_param_named" ref="edfafba6c954cbe71b8c4bc47e13720d" args="(dev_nperio_tx_fifo_size, dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>module_param_named</b> (dev_nperio_tx_fifo_size, dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="0a92555551a37863e55586bc5793fa75"></a><!-- doxytag: member="dwc_otg_driver.c::MODULE_PARM_DESC" ref="0a92555551a37863e55586bc5793fa75" args="(dev_nperio_tx_fifo_size,&quot;Number of words in the non-periodic Tx FIFO 16-32768&quot;)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>MODULE_PARM_DESC</b> (dev_nperio_tx_fifo_size,&quot;Number of words in the non-periodic Tx FIFO 16-32768&quot;)</td></tr>
+
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+&nbsp;</td><td class="memItemRight" valign="bottom"><b>module_param_named</b> (dev_tx_fifo_size_9, dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e2e66432adc183f3048c46bda37247dd"></a><!-- doxytag: member="dwc_otg_driver.c::MODULE_PARM_DESC" ref="e2e66432adc183f3048c46bda37247dd" args="(dev_tx_fifo_size_9,&quot;Number of words in the Tx FIFO 4-768&quot;)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>MODULE_PARM_DESC</b> (dev_tx_fifo_size_9,&quot;Number of words in the Tx FIFO 4-768&quot;)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="502458d0d0f9567b6e4de0aee02c0dcb"></a><!-- doxytag: member="dwc_otg_driver.c::module_param_named" ref="502458d0d0f9567b6e4de0aee02c0dcb" args="(dev_tx_fifo_size_10, dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>module_param_named</b> (dev_tx_fifo_size_10, dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="23ec98191f15c2b6d17234087fdb39a0"></a><!-- doxytag: member="dwc_otg_driver.c::MODULE_PARM_DESC" ref="23ec98191f15c2b6d17234087fdb39a0" args="(dev_tx_fifo_size_10,&quot;Number of words in the Tx FIFO 4-768&quot;)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>MODULE_PARM_DESC</b> (dev_tx_fifo_size_10,&quot;Number of words in the Tx FIFO 4-768&quot;)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="4f1ed068c00e24ea6ebc9715bdc41ebe"></a><!-- doxytag: member="dwc_otg_driver.c::module_param_named" ref="4f1ed068c00e24ea6ebc9715bdc41ebe" args="(dev_tx_fifo_size_11, dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>module_param_named</b> (dev_tx_fifo_size_11, dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b78d4822b69b924f2d52da8013ef24d9"></a><!-- doxytag: member="dwc_otg_driver.c::MODULE_PARM_DESC" ref="b78d4822b69b924f2d52da8013ef24d9" args="(dev_tx_fifo_size_11,&quot;Number of words in the Tx FIFO 4-768&quot;)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>MODULE_PARM_DESC</b> (dev_tx_fifo_size_11,&quot;Number of words in the Tx FIFO 4-768&quot;)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="093d2da0200f5843c87a73ff108c6b7b"></a><!-- doxytag: member="dwc_otg_driver.c::module_param_named" ref="093d2da0200f5843c87a73ff108c6b7b" args="(dev_tx_fifo_size_12, dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>module_param_named</b> (dev_tx_fifo_size_12, dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="707395f8a4f38d3a76c6a41f4cc82960"></a><!-- doxytag: member="dwc_otg_driver.c::MODULE_PARM_DESC" ref="707395f8a4f38d3a76c6a41f4cc82960" args="(dev_tx_fifo_size_12,&quot;Number of words in the Tx FIFO 4-768&quot;)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>MODULE_PARM_DESC</b> (dev_tx_fifo_size_12,&quot;Number of words in the Tx FIFO 4-768&quot;)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="44c76548c1186e78e98ca14a8ce8b096"></a><!-- doxytag: member="dwc_otg_driver.c::module_param_named" ref="44c76548c1186e78e98ca14a8ce8b096" args="(dev_tx_fifo_size_13, dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>module_param_named</b> (dev_tx_fifo_size_13, dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="84d83ed572c346674b1b7375a6f51ffe"></a><!-- doxytag: member="dwc_otg_driver.c::MODULE_PARM_DESC" ref="84d83ed572c346674b1b7375a6f51ffe" args="(dev_tx_fifo_size_13,&quot;Number of words in the Tx FIFO 4-768&quot;)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>MODULE_PARM_DESC</b> (dev_tx_fifo_size_13,&quot;Number of words in the Tx FIFO 4-768&quot;)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="22faa884d005d73c461eeba6c7d8aaa3"></a><!-- doxytag: member="dwc_otg_driver.c::module_param_named" ref="22faa884d005d73c461eeba6c7d8aaa3" args="(dev_tx_fifo_size_14, dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>module_param_named</b> (dev_tx_fifo_size_14, dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b29d43790d321403be819307f03aef8b"></a><!-- doxytag: member="dwc_otg_driver.c::MODULE_PARM_DESC" ref="b29d43790d321403be819307f03aef8b" args="(dev_tx_fifo_size_14,&quot;Number of words in the Tx FIFO 4-768&quot;)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>MODULE_PARM_DESC</b> (dev_tx_fifo_size_14,&quot;Number of words in the Tx FIFO 4-768&quot;)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="84953e96ae642147637bc6210e1f7ead"></a><!-- doxytag: member="dwc_otg_driver.c::module_param_named" ref="84953e96ae642147637bc6210e1f7ead" args="(dev_tx_fifo_size_15, dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>module_param_named</b> (dev_tx_fifo_size_15, dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="6a97d29dc7325c12a5711e64daa51f44"></a><!-- doxytag: member="dwc_otg_driver.c::MODULE_PARM_DESC" ref="6a97d29dc7325c12a5711e64daa51f44" args="(dev_tx_fifo_size_15,&quot;Number of words in the Tx FIFO 4-768&quot;)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>MODULE_PARM_DESC</b> (dev_tx_fifo_size_15,&quot;Number of words in the Tx FIFO 4-768&quot;)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7aac0e0d5ab1b2b9c463f8748bd1b1d4"></a><!-- doxytag: member="dwc_otg_driver.c::module_param_named" ref="7aac0e0d5ab1b2b9c463f8748bd1b1d4" args="(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>module_param_named</b> (thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e1fb4a2ab3a1e7263b864a7f149b143e"></a><!-- doxytag: member="dwc_otg_driver.c::MODULE_PARM_DESC" ref="e1fb4a2ab3a1e7263b864a7f149b143e" args="(thr_ctl,&quot;Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled&quot;)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>MODULE_PARM_DESC</b> (thr_ctl,&quot;Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled&quot;)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="98f09086dd956e7eb066f9c19815f5cd"></a><!-- doxytag: member="dwc_otg_driver.c::module_param_named" ref="98f09086dd956e7eb066f9c19815f5cd" args="(tx_thr_length, dwc_otg_module_params.tx_thr_length, int, 0444)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>module_param_named</b> (tx_thr_length, dwc_otg_module_params.tx_thr_length, int, 0444)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="79d7c1235f4efa2005a2ddf4311c4696"></a><!-- doxytag: member="dwc_otg_driver.c::MODULE_PARM_DESC" ref="79d7c1235f4efa2005a2ddf4311c4696" args="(tx_thr_length,&quot;Tx Threshold length in 32 bit DWORDs&quot;)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>MODULE_PARM_DESC</b> (tx_thr_length,&quot;Tx Threshold length in 32 bit DWORDs&quot;)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="6518ae4effd2fe4bfffa4f0ba71cfbee"></a><!-- doxytag: member="dwc_otg_driver.c::module_param_named" ref="6518ae4effd2fe4bfffa4f0ba71cfbee" args="(rx_thr_length, dwc_otg_module_params.rx_thr_length, int, 0444)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>module_param_named</b> (rx_thr_length, dwc_otg_module_params.rx_thr_length, int, 0444)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="9b3a3d1d1aeb529a725cbd58cf55da12"></a><!-- doxytag: member="dwc_otg_driver.c::MODULE_PARM_DESC" ref="9b3a3d1d1aeb529a725cbd58cf55da12" args="(rx_thr_length,&quot;Rx Threshold length in 32 bit DWORDs&quot;)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>MODULE_PARM_DESC</b> (rx_thr_length,&quot;Rx Threshold length in 32 bit DWORDs&quot;)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3bf12e374c3f8be8955a3de6fc1512af"></a><!-- doxytag: member="dwc_otg_driver.c::module_param_named" ref="3bf12e374c3f8be8955a3de6fc1512af" args="(pti_enable, dwc_otg_module_params.pti_enable, int, 0444)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>module_param_named</b> (pti_enable, dwc_otg_module_params.pti_enable, int, 0444)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7ac6fb50d8e049aa8f0b6e6880afe649"></a><!-- doxytag: member="dwc_otg_driver.c::module_param_named" ref="7ac6fb50d8e049aa8f0b6e6880afe649" args="(mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>module_param_named</b> (mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f1a5e492d6dcbab7b6e1c6c530d55265"></a><!-- doxytag: member="dwc_otg_driver.c::module_param_named" ref="f1a5e492d6dcbab7b6e1c6c530d55265" args="(lpm_enable, dwc_otg_module_params.lpm_enable, int, 0444)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>module_param_named</b> (lpm_enable, dwc_otg_module_params.lpm_enable, int, 0444)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7fb75266c9181627cc0014691dc0b464"></a><!-- doxytag: member="dwc_otg_driver.c::MODULE_PARM_DESC" ref="7fb75266c9181627cc0014691dc0b464" args="(lpm_enable,&quot;LPM Enable 0=LPM Disabled 1=LPM Enabled&quot;)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>MODULE_PARM_DESC</b> (lpm_enable,&quot;LPM Enable 0=LPM Disabled 1=LPM Enabled&quot;)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f2dffb929e887b787e117fb12a6fe03b"></a><!-- doxytag: member="dwc_otg_driver.c::module_param_named" ref="f2dffb929e887b787e117fb12a6fe03b" args="(ic_usb_cap, dwc_otg_module_params.ic_usb_cap, int, 0444)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>module_param_named</b> (ic_usb_cap, dwc_otg_module_params.ic_usb_cap, int, 0444)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="9c5941cde492e487837d7dd52ec619ad"></a><!-- doxytag: member="dwc_otg_driver.c::MODULE_PARM_DESC" ref="9c5941cde492e487837d7dd52ec619ad" args="(ic_usb_cap,&quot;IC_USB Capability 0=IC_USB Disabled 1=IC_USB Enabled&quot;)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>MODULE_PARM_DESC</b> (ic_usb_cap,&quot;IC_USB Capability 0=IC_USB Disabled 1=IC_USB Enabled&quot;)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b2cc1dae57ed8f779de4da5e0d94b558"></a><!-- doxytag: member="dwc_otg_driver.c::module_param_named" ref="b2cc1dae57ed8f779de4da5e0d94b558" args="(ahb_thr_ratio, dwc_otg_module_params.ahb_thr_ratio, int, 0444)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>module_param_named</b> (ahb_thr_ratio, dwc_otg_module_params.ahb_thr_ratio, int, 0444)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="97896ea17f46fbdd0bdcf6d90366a3b1"></a><!-- doxytag: member="dwc_otg_driver.c::MODULE_PARM_DESC" ref="97896ea17f46fbdd0bdcf6d90366a3b1" args="(ahb_thr_ratio,&quot;AHB Threshold Ratio&quot;)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>MODULE_PARM_DESC</b> (ahb_thr_ratio,&quot;AHB Threshold Ratio&quot;)</td></tr>
+
+<tr><td colspan="2"><br><h2>Variables</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3f7932dcd77bb7b05f92f759e6569fe2"></a><!-- doxytag: member="dwc_otg_driver.c::dwc_driver_name" ref="3f7932dcd77bb7b05f92f759e6569fe2" args="[]" -->
+static const char&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__driver_8c.html#3f7932dcd77bb7b05f92f759e6569fe2">dwc_driver_name</a> [] = &quot;dwc_otg&quot;</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="887d74166238890f65ffb620e39c759b"></a><!-- doxytag: member="dwc_otg_driver.c::dwc_otg_module_params" ref="887d74166238890f65ffb620e39c759b" args="" -->
+static struct <a class="el" href="structdwc__otg__driver__module__params.html">dwc_otg_driver_module_params</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_module_params</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7ef4ada2ebb5f1aadf3be4d7fbf8ce62"></a><!-- doxytag: member="dwc_otg_driver.c::g_dbg_lvl" ref="7ef4ada2ebb5f1aadf3be4d7fbf8ce62" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__driver_8c.html#7ef4ada2ebb5f1aadf3be4d7fbf8ce62">g_dbg_lvl</a> = 0</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">The Debug Level bit-mask variable. <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+The dwc_otg_driver module provides the initialization and cleanup entry points for the DWC_otg driver. 
+<p>
+This module will be dynamically installed after Linux is booted using the insmod command. When the module is installed, the dwc_otg_driver_init function is called. When the module is removed (using rmmod), the dwc_otg_driver_cleanup function is called.<p>
+This module also defines a data structure for the dwc_otg_driver, which is used in conjunction with the standard ARM lm_device structure. These structures allow the OTG driver to comply with the standard Linux driver model in which devices and drivers are registered with a bus driver. This has the benefit that Linux can expose attributes of the driver and device in its special sysfs file system. Users can then read or write files in this file system to perform diagnostics on the driver components or the device. 
+<p>
+Definition in file <a class="el" href="dwc__otg__driver_8c-source.html">dwc_otg_driver.c</a>.<hr><h2>Function Documentation</h2>
+<a class="anchor" name="ab12cdf65bf4ed68545a6c17cc31269f"></a><!-- doxytag: member="dwc_otg_driver.c::hcd_init" ref="ab12cdf65bf4ed68545a6c17cc31269f" args="()" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int hcd_init           </td>
+          <td>(</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Initializes the HCD. 
+<p>
+This function allocates memory for and initializes the static parts of the usb_hcd and <a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd</a> structures. It also registers the USB bus with the core and calls the hc_driver-&gt;start() function. It returns a negative error on failure. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__linux_8c-source.html#l00327">327</a> of file <a class="el" href="dwc__otg__hcd__linux_8c-source.html">dwc_otg_hcd_linux.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="f36193b3ff33c0473956c8a15eee4f5b"></a><!-- doxytag: member="dwc_otg_driver.c::hcd_remove" ref="f36193b3ff33c0473956c8a15eee4f5b" args="()" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void hcd_remove           </td>
+          <td>(</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Removes the HCD. 
+<p>
+Frees memory and resources associated with the HCD and deregisters the bus. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__linux_8c-source.html#l00417">417</a> of file <a class="el" href="dwc__otg__hcd__linux_8c-source.html">dwc_otg_hcd_linux.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="fe9abf2a1dda4c02d24f5cb1d7a9a94d"></a><!-- doxytag: member="dwc_otg_driver.c::dwc_otg_driver_remove" ref="fe9abf2a1dda4c02d24f5cb1d7a9a94d" args="()" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static void dwc_otg_driver_remove           </td>
+          <td>(</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function is called when a lm_device is unregistered with the dwc_otg_driver. 
+<p>
+This happens, for example, when the rmmod command is executed. The device may or may not be electrically present. If it is present, the driver stops device processing. Any resources used on behalf of this device are freed.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>_dev</em>&nbsp;</td><td></td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__driver_8c-source.html#l00525">525</a> of file <a class="el" href="dwc__otg__driver_8c-source.html">dwc_otg_driver.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="10921617ecc621f0448d4f9ab6a0f7b7"></a><!-- doxytag: member="dwc_otg_driver.c::dwc_otg_driver_probe" ref="10921617ecc621f0448d4f9ab6a0f7b7" args="()" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static int dwc_otg_driver_probe           </td>
+          <td>(</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function is called when an lm_device is bound to a dwc_otg_driver. 
+<p>
+It creates the driver components required to control the device (CIL, HCD, and PCD) and it initializes the device. The driver components are stored in a <a class="el" href="structdwc__otg__device.html">dwc_otg_device</a> structure. A reference to the <a class="el" href="structdwc__otg__device.html">dwc_otg_device</a> is saved in the lm_device. This allows the driver to access the <a class="el" href="structdwc__otg__device.html">dwc_otg_device</a> structure on subsequent calls to driver methods for this device.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>_dev</em>&nbsp;</td><td>Bus device </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__driver_8c-source.html#l00608">608</a> of file <a class="el" href="dwc__otg__driver_8c-source.html">dwc_otg_driver.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="737f516e934e7f479e31bf7261dd3830"></a><!-- doxytag: member="dwc_otg_driver.c::dwc_otg_driver_init" ref="737f516e934e7f479e31bf7261dd3830" args="(void)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static int __init dwc_otg_driver_init           </td>
+          <td>(</td>
+          <td class="paramtype">void&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function is called when the dwc_otg_driver is installed with the insmod command. 
+<p>
+It registers the dwc_otg_driver structure with the appropriate bus driver. This will cause the dwc_otg_driver_probe function to be called. In addition, the bus driver will automatically expose attributes defined for the device and driver in the special sysfs file system.<p>
+<dl compact><dt><b>Returns:</b></dt><dd></dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__driver_8c-source.html#l00866">866</a> of file <a class="el" href="dwc__otg__driver_8c-source.html">dwc_otg_driver.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="e50c104d9f854418331c453b9d273dce"></a><!-- doxytag: member="dwc_otg_driver.c::dwc_otg_driver_cleanup" ref="e50c104d9f854418331c453b9d273dce" args="(void)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static void __exit dwc_otg_driver_cleanup           </td>
+          <td>(</td>
+          <td class="paramtype">void&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function is called when the driver is removed from the kernel with the rmmod command. 
+<p>
+The driver unregisters itself with its bus driver. 
+<p>
+Definition at line <a class="el" href="dwc__otg__driver_8c-source.html#l00899">899</a> of file <a class="el" href="dwc__otg__driver_8c-source.html">dwc_otg_driver.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="e0dbd8f1a438746fa8ec7798ceb2bd50"></a><!-- doxytag: member="dwc_otg_driver.c::MODULE_PARM_DESC" ref="e0dbd8f1a438746fa8ec7798ceb2bd50" args="(max_transfer_size,&quot;The maximum transfer size supported in bytes 2047-65535&quot;)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">MODULE_PARM_DESC           </td>
+          <td>(</td>
+          <td class="paramtype">max_transfer_size&nbsp;</td>
+          <td class="paramname">, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&quot;The maximum transfer size supported in bytes 2047-65535&quot;&nbsp;</td>
+          <td class="paramname"></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000014">Todo:</a></b></dt><dd>Set the max to 512K, modify checks </dd></dl>
+
+</div>
+</div><p>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/dwc__otg__driver_8h-source.html b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__driver_8h-source.html
new file mode 100644
index 000000000000..5557004b7e19
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__driver_8h-source.html
@@ -0,0 +1,110 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_driver.h Source File</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<h1>dwc_otg_driver.h</h1><a href="dwc__otg__driver_8h.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">/* ==========================================================================</span>
+<a name="l00002"></a>00002 <span class="comment"> * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.h $</span>
+<a name="l00003"></a>00003 <span class="comment"> * $Revision: #16 $</span>
+<a name="l00004"></a>00004 <span class="comment"> * $Date: 2009/04/03 $</span>
+<a name="l00005"></a>00005 <span class="comment"> * $Change: 1225160 $</span>
+<a name="l00006"></a>00006 <span class="comment"> *</span>
+<a name="l00007"></a>00007 <span class="comment"> * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,</span>
+<a name="l00008"></a>00008 <span class="comment"> * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless</span>
+<a name="l00009"></a>00009 <span class="comment"> * otherwise expressly agreed to in writing between Synopsys and you.</span>
+<a name="l00010"></a>00010 <span class="comment"> * </span>
+<a name="l00011"></a>00011 <span class="comment"> * The Software IS NOT an item of Licensed Software or Licensed Product under</span>
+<a name="l00012"></a>00012 <span class="comment"> * any End User Software License Agreement or Agreement for Licensed Product</span>
+<a name="l00013"></a>00013 <span class="comment"> * with Synopsys or any supplement thereto. You are permitted to use and</span>
+<a name="l00014"></a>00014 <span class="comment"> * redistribute this Software in source and binary forms, with or without</span>
+<a name="l00015"></a>00015 <span class="comment"> * modification, provided that redistributions of source code must retain this</span>
+<a name="l00016"></a>00016 <span class="comment"> * notice. You may not view, use, disclose, copy or distribute this file or</span>
+<a name="l00017"></a>00017 <span class="comment"> * any information contained herein except pursuant to this license grant from</span>
+<a name="l00018"></a>00018 <span class="comment"> * Synopsys. If you do not agree with this notice, including the disclaimer</span>
+<a name="l00019"></a>00019 <span class="comment"> * below, then you are not authorized to use the Software.</span>
+<a name="l00020"></a>00020 <span class="comment"> * </span>
+<a name="l00021"></a>00021 <span class="comment"> * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS</span>
+<a name="l00022"></a>00022 <span class="comment"> * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE</span>
+<a name="l00023"></a>00023 <span class="comment"> * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE</span>
+<a name="l00024"></a>00024 <span class="comment"> * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,</span>
+<a name="l00025"></a>00025 <span class="comment"> * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES</span>
+<a name="l00026"></a>00026 <span class="comment"> * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR</span>
+<a name="l00027"></a>00027 <span class="comment"> * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER</span>
+<a name="l00028"></a>00028 <span class="comment"> * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT</span>
+<a name="l00029"></a>00029 <span class="comment"> * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY</span>
+<a name="l00030"></a>00030 <span class="comment"> * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH</span>
+<a name="l00031"></a>00031 <span class="comment"> * DAMAGE.</span>
+<a name="l00032"></a>00032 <span class="comment"> * ========================================================================== */</span>
+<a name="l00033"></a>00033 
+<a name="l00034"></a>00034 <span class="preprocessor">#ifndef __DWC_OTG_DRIVER_H__</span>
+<a name="l00035"></a>00035 <span class="preprocessor"></span><span class="preprocessor">#define __DWC_OTG_DRIVER_H__</span>
+<a name="l00036"></a>00036 <span class="preprocessor"></span>
+<a name="l00040"></a>00040 <span class="preprocessor">#include "<a class="code" href="dwc__otg__core__if_8h.html">dwc_otg_core_if.h</a>"</span>
+<a name="l00041"></a>00041 
+<a name="l00042"></a>00042 <span class="comment">/* Type declarations */</span>
+<a name="l00043"></a>00043 <span class="keyword">struct </span><a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd</a>;
+<a name="l00044"></a>00044 <span class="keyword">struct </span><a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>;
+<a name="l00045"></a>00045 
+<a name="l00046"></a>00046 <span class="preprocessor">#ifdef  PCI_INTERFACE</span>
+<a name="l00047"></a>00047 <span class="preprocessor"></span><span class="preprocessor">#include &lt;linux/pci.h&gt;</span>
+<a name="l00048"></a>00048 <span class="preprocessor">#endif</span>
+<a name="l00049"></a>00049 <span class="preprocessor"></span>
+<a name="l00050"></a>00050 
+<a name="l00051"></a>00051 
+<a name="l00056"></a><a class="code" href="structdwc__otg__device.html">00056</a> <span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code" href="structdwc__otg__device.html">dwc_otg_device</a> {
+<a name="l00058"></a><a class="code" href="structdwc__otg__device.html#ed96ed1109175f87fd83fa32a9c2c6fa">00058</a>         <span class="keywordtype">void</span> *<a class="code" href="structdwc__otg__device.html#ed96ed1109175f87fd83fa32a9c2c6fa">base</a>;
+<a name="l00059"></a>00059 
+<a name="l00060"></a>00060 <span class="preprocessor">#ifdef LM_INTERFACE</span>
+<a name="l00061"></a>00061 <span class="preprocessor"></span>        <span class="keyword">struct </span>lm_device *lmdev;
+<a name="l00062"></a>00062 <span class="preprocessor">#elif  PCI_INTERFACE</span>
+<a name="l00063"></a>00063 <span class="preprocessor"></span>        <span class="keywordtype">int</span> rsrc_start;
+<a name="l00064"></a>00064         <span class="keywordtype">int</span> rsrc_len;
+<a name="l00065"></a>00065 <span class="preprocessor">#endif</span>
+<a name="l00066"></a>00066 <span class="preprocessor"></span>
+<a name="l00068"></a><a class="code" href="structdwc__otg__device.html#4cc7c9f6e473072c2ed0a5e6adb25ebe">00068</a>         <a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *<a class="code" href="structdwc__otg__device.html#4cc7c9f6e473072c2ed0a5e6adb25ebe">core_if</a>;
+<a name="l00069"></a>00069 
+<a name="l00071"></a><a class="code" href="structdwc__otg__device.html#d2701bc8589613bec5074968e57ce6ef">00071</a>         uint32_t <a class="code" href="structdwc__otg__device.html#d2701bc8589613bec5074968e57ce6ef">reg_offset</a>;
+<a name="l00072"></a>00072 
+<a name="l00074"></a><a class="code" href="structdwc__otg__device.html#2a8eefbd03790ea0bbb70e0ac14e4786">00074</a>         <span class="keyword">struct </span><a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd</a> *<a class="code" href="structdwc__otg__device.html#2a8eefbd03790ea0bbb70e0ac14e4786">pcd</a>;
+<a name="l00075"></a>00075 
+<a name="l00077"></a><a class="code" href="structdwc__otg__device.html#834ef28e884f0d7fcac68f3bdf5c4b33">00077</a>         <span class="keyword">struct </span><a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a> *<a class="code" href="structdwc__otg__device.html#834ef28e884f0d7fcac68f3bdf5c4b33">hcd</a>;
+<a name="l00078"></a>00078 
+<a name="l00080"></a><a class="code" href="structdwc__otg__device.html#80bfe5405d4146d3edca4e3eb2f9239b">00080</a>         uint8_t <a class="code" href="structdwc__otg__device.html#80bfe5405d4146d3edca4e3eb2f9239b">common_irq_installed</a>;
+<a name="l00081"></a>00081 
+<a name="l00082"></a>00082 } <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a>;
+<a name="l00083"></a>00083 
+<a name="l00084"></a>00084 <span class="comment">/*We must clear S3C24XX_EINTPEND external interrupt register </span>
+<a name="l00085"></a>00085 <span class="comment"> * because after clearing in this register trigerred IRQ from </span>
+<a name="l00086"></a>00086 <span class="comment"> * H/W core in kernel interrupt can be occured again before OTG</span>
+<a name="l00087"></a>00087 <span class="comment"> * handlers clear all IRQ sources of Core registers because of</span>
+<a name="l00088"></a>00088 <span class="comment"> * timing latencies and Low Level IRQ Type.</span>
+<a name="l00089"></a>00089 <span class="comment"> */</span>
+<a name="l00090"></a>00090 <span class="preprocessor">#ifdef CONFIG_MACH_IPMATE</span>
+<a name="l00091"></a>00091 <span class="preprocessor"></span><span class="preprocessor">#define  S3C2410X_CLEAR_EINTPEND()   \</span>
+<a name="l00092"></a>00092 <span class="preprocessor">do { \</span>
+<a name="l00093"></a>00093 <span class="preprocessor">        __raw_writel(1UL &lt;&lt; 11,S3C24XX_EINTPEND); \</span>
+<a name="l00094"></a>00094 <span class="preprocessor">} while (0)</span>
+<a name="l00095"></a>00095 <span class="preprocessor"></span><span class="preprocessor">#else</span>
+<a name="l00096"></a><a class="code" href="dwc__otg__driver_8h.html#3af7bafbb69f04a0fd36a27fae7e8497">00096</a> <span class="preprocessor"></span><span class="preprocessor">#define  S3C2410X_CLEAR_EINTPEND()   do { } while (0)</span>
+<a name="l00097"></a>00097 <span class="preprocessor"></span><span class="preprocessor">#endif</span>
+<a name="l00098"></a>00098 <span class="preprocessor"></span>
+<a name="l00099"></a>00099 <span class="preprocessor">#endif</span>
+</pre></div><hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/dwc__otg__driver_8h.html b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__driver_8h.html
new file mode 100644
index 000000000000..c2914c1731d5
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__driver_8h.html
@@ -0,0 +1,50 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_driver.h File Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<h1>dwc_otg_driver.h File Reference</h1>This file contains the interface to the Linux driver. <a href="#_details">More...</a>
+<p>
+<code>#include &quot;<a class="el" href="dwc__otg__core__if_8h-source.html">dwc_otg_core_if.h</a>&quot;</code><br>
+
+<p>
+<a href="dwc__otg__driver_8h-source.html">Go to the source code of this file.</a><table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Structures</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__device.html">dwc_otg_device</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This structure is a wrapper that encapsulates the driver components used to manage a single DWC_otg controller.  <a href="structdwc__otg__device.html#_details">More...</a><br></td></tr>
+<tr><td colspan="2"><br><h2>Defines</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3af7bafbb69f04a0fd36a27fae7e8497"></a><!-- doxytag: member="dwc_otg_driver.h::S3C2410X_CLEAR_EINTPEND" ref="3af7bafbb69f04a0fd36a27fae7e8497" args="()" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__driver_8h.html#3af7bafbb69f04a0fd36a27fae7e8497">S3C2410X_CLEAR_EINTPEND</a>()&nbsp;&nbsp;&nbsp;do { } while (0)</td></tr>
+
+<tr><td colspan="2"><br><h2>Typedefs</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="70dce40f5a55fe7acee5343d998d5074"></a><!-- doxytag: member="dwc_otg_driver.h::dwc_otg_device_t" ref="70dce40f5a55fe7acee5343d998d5074" args="" -->
+typedef <a class="el" href="structdwc__otg__device.html">dwc_otg_device</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__driver_8h.html#70dce40f5a55fe7acee5343d998d5074">dwc_otg_device_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This structure is a wrapper that encapsulates the driver components used to manage a single DWC_otg controller. <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This file contains the interface to the Linux driver. 
+<p>
+
+<p>
+Definition in file <a class="el" href="dwc__otg__driver_8h-source.html">dwc_otg_driver.h</a>.<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd_8c-source.html b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd_8c-source.html
new file mode 100644
index 000000000000..6b48db3028fb
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd_8c-source.html
@@ -0,0 +1,2946 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd.c Source File</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<h1>dwc_otg_hcd.c</h1><a href="dwc__otg__hcd_8c.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">/* ==========================================================================</span>
+<a name="l00002"></a>00002 <span class="comment"> * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.c $</span>
+<a name="l00003"></a>00003 <span class="comment"> * $Revision: #87 $</span>
+<a name="l00004"></a>00004 <span class="comment"> * $Date: 2009/04/23 $</span>
+<a name="l00005"></a>00005 <span class="comment"> * $Change: 1239143 $</span>
+<a name="l00006"></a>00006 <span class="comment"> *</span>
+<a name="l00007"></a>00007 <span class="comment"> * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,</span>
+<a name="l00008"></a>00008 <span class="comment"> * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless</span>
+<a name="l00009"></a>00009 <span class="comment"> * otherwise expressly agreed to in writing between Synopsys and you.</span>
+<a name="l00010"></a>00010 <span class="comment"> *</span>
+<a name="l00011"></a>00011 <span class="comment"> * The Software IS NOT an item of Licensed Software or Licensed Product under</span>
+<a name="l00012"></a>00012 <span class="comment"> * any End User Software License Agreement or Agreement for Licensed Product</span>
+<a name="l00013"></a>00013 <span class="comment"> * with Synopsys or any supplement thereto. You are permitted to use and</span>
+<a name="l00014"></a>00014 <span class="comment"> * redistribute this Software in source and binary forms, with or without</span>
+<a name="l00015"></a>00015 <span class="comment"> * modification, provided that redistributions of source code must retain this</span>
+<a name="l00016"></a>00016 <span class="comment"> * notice. You may not view, use, disclose, copy or distribute this file or</span>
+<a name="l00017"></a>00017 <span class="comment"> * any information contained herein except pursuant to this license grant from</span>
+<a name="l00018"></a>00018 <span class="comment"> * Synopsys. If you do not agree with this notice, including the disclaimer</span>
+<a name="l00019"></a>00019 <span class="comment"> * below, then you are not authorized to use the Software.</span>
+<a name="l00020"></a>00020 <span class="comment"> *</span>
+<a name="l00021"></a>00021 <span class="comment"> * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS</span>
+<a name="l00022"></a>00022 <span class="comment"> * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE</span>
+<a name="l00023"></a>00023 <span class="comment"> * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE</span>
+<a name="l00024"></a>00024 <span class="comment"> * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,</span>
+<a name="l00025"></a>00025 <span class="comment"> * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES</span>
+<a name="l00026"></a>00026 <span class="comment"> * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR</span>
+<a name="l00027"></a>00027 <span class="comment"> * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER</span>
+<a name="l00028"></a>00028 <span class="comment"> * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT</span>
+<a name="l00029"></a>00029 <span class="comment"> * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY</span>
+<a name="l00030"></a>00030 <span class="comment"> * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH</span>
+<a name="l00031"></a>00031 <span class="comment"> * DAMAGE.</span>
+<a name="l00032"></a>00032 <span class="comment"> * ========================================================================== */</span>
+<a name="l00033"></a>00033 <span class="preprocessor">#ifndef DWC_DEVICE_ONLY</span>
+<a name="l00034"></a>00034 <span class="preprocessor"></span>
+<a name="l00042"></a>00042 <span class="preprocessor">#include "<a class="code" href="dwc__otg__hcd_8h.html">dwc_otg_hcd.h</a>"</span>
+<a name="l00043"></a>00043 <span class="preprocessor">#include "<a class="code" href="dwc__otg__regs_8h.html">dwc_otg_regs.h</a>"</span>
+<a name="l00044"></a>00044                 
+<a name="l00045"></a><a class="code" href="dwc__otg__hcd__if_8h.html#5595437c199432efbd3609dc87ef5afa">00045</a> <a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *<a class="code" href="dwc__otg__hcd_8c.html#5595437c199432efbd3609dc87ef5afa">dwc_otg_hcd_alloc_hcd</a>(<span class="keywordtype">void</span>)
+<a name="l00046"></a>00046 {
+<a name="l00047"></a>00047         <span class="keywordflow">return</span> dwc_alloc(<span class="keyword">sizeof</span>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a>));
+<a name="l00048"></a>00048 }
+<a name="l00049"></a>00049 
+<a name="l00054"></a><a class="code" href="dwc__otg__hcd_8c.html#4f6f55c20aa8eb215d692195f9f0280d">00054</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd_8c.html#4f6f55c20aa8eb215d692195f9f0280d">dwc_otg_hcd_connect_timeout</a>(<span class="keywordtype">void</span> *ptr)
+<a name="l00055"></a>00055 {
+<a name="l00056"></a>00056         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"%s(%p)\n"</span>, __func__, ptr);
+<a name="l00057"></a>00057         DWC_PRINTF(<span class="stringliteral">"Connect Timeout\n"</span>);
+<a name="l00058"></a>00058         __DWC_ERROR(<span class="stringliteral">"Device Not Connected/Responding\n"</span>);
+<a name="l00059"></a>00059 }
+<a name="l00060"></a>00060 
+<a name="l00061"></a>00061 <span class="preprocessor">#ifdef DEBUG</span>
+<a name="l00062"></a>00062 <span class="preprocessor"></span><span class="keyword">static</span> <span class="keywordtype">void</span> dump_channel_info(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd, <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> * qh)
+<a name="l00063"></a>00063 {
+<a name="l00064"></a>00064         <span class="keywordflow">if</span> (qh-&gt;<a class="code" href="structdwc__otg__qh.html#bbdb7d30b60b6c326301f33b35088bb4">channel</a> != NULL) {
+<a name="l00065"></a>00065                 <a class="code" href="structdwc__hc.html">dwc_hc_t</a> *hc = qh-&gt;<a class="code" href="structdwc__otg__qh.html#bbdb7d30b60b6c326301f33b35088bb4">channel</a>;
+<a name="l00066"></a>00066                 dwc_list_link_t *item;
+<a name="l00067"></a>00067                 <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *qh_item;
+<a name="l00068"></a>00068                 <span class="keywordtype">int</span> num_channels = hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#c1b433c6965aa7d48f6ca6818c592039">host_channels</a>;
+<a name="l00069"></a>00069                 <span class="keywordtype">int</span> i;
+<a name="l00070"></a>00070 
+<a name="l00071"></a>00071                 <a class="code" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *hc_regs;
+<a name="l00072"></a>00072                 <a class="code" href="unionhcchar__data.html">hcchar_data_t</a> hcchar;
+<a name="l00073"></a>00073                 <a class="code" href="unionhcsplt__data.html">hcsplt_data_t</a> hcsplt;
+<a name="l00074"></a>00074                 <a class="code" href="unionhctsiz__data.html">hctsiz_data_t</a> hctsiz;
+<a name="l00075"></a>00075                 uint32_t hcdma;
+<a name="l00076"></a>00076 
+<a name="l00077"></a>00077                 hc_regs = hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#7f7c107d4720641eb4141cd817211ac0">hc_regs</a>[hc-&gt;<a class="code" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">hc_num</a>];
+<a name="l00078"></a>00078                 hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">hcchar</a>);
+<a name="l00079"></a>00079                 hcsplt.<a class="code" href="unionhcsplt__data.html#0cd235b445ff681b846f5dccf24fd644">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#149053001a9ee21b692afde531a814de">hcsplt</a>);
+<a name="l00080"></a>00080                 hctsiz.<a class="code" href="unionhctsiz__data.html#fb41950555c60c6015294bdefe9cd39d">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#c6173f823ba754d9f9549422b6380ca2">hctsiz</a>);
+<a name="l00081"></a>00081                 hcdma = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#ab2148d4b5f1bf3a2ad438e497a8b4a3">hcdma</a>);
+<a name="l00082"></a>00082 
+<a name="l00083"></a>00083                 DWC_PRINTF(<span class="stringliteral">"  Assigned to channel %p:\n"</span>, hc);
+<a name="l00084"></a>00084                 DWC_PRINTF(<span class="stringliteral">"    hcchar 0x%08x, hcsplt 0x%08x\n"</span>, hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a>,
+<a name="l00085"></a>00085                            hcsplt.<a class="code" href="unionhcsplt__data.html#0cd235b445ff681b846f5dccf24fd644">d32</a>);
+<a name="l00086"></a>00086                 DWC_PRINTF(<span class="stringliteral">"    hctsiz 0x%08x, hcdma 0x%08x\n"</span>, hctsiz.<a class="code" href="unionhctsiz__data.html#fb41950555c60c6015294bdefe9cd39d">d32</a>,
+<a name="l00087"></a>00087                            hcdma);
+<a name="l00088"></a>00088                 DWC_PRINTF(<span class="stringliteral">"    dev_addr: %d, ep_num: %d, ep_is_in: %d\n"</span>,
+<a name="l00089"></a>00089                            hc-&gt;<a class="code" href="structdwc__hc.html#b2c7e8baff70104375f4916e9b76cef7">dev_addr</a>, hc-&gt;<a class="code" href="structdwc__hc.html#70b755f76a00b81679aeb1e0db8b2e60">ep_num</a>, hc-&gt;<a class="code" href="structdwc__hc.html#c5088d431f5efc382121f201f5d571aa">ep_is_in</a>);
+<a name="l00090"></a>00090                 DWC_PRINTF(<span class="stringliteral">"    ep_type: %d\n"</span>, hc-&gt;<a class="code" href="structdwc__hc.html#e6169fbc92e4d79686097742ad646f5c">ep_type</a>);
+<a name="l00091"></a>00091                 DWC_PRINTF(<span class="stringliteral">"    max_packet: %d\n"</span>, hc-&gt;<a class="code" href="structdwc__hc.html#bd88f02eb286ba01d8d1b049e8975ccb">max_packet</a>);
+<a name="l00092"></a>00092                 DWC_PRINTF(<span class="stringliteral">"    data_pid_start: %d\n"</span>, hc-&gt;<a class="code" href="structdwc__hc.html#513427c5e8c4603ba344d4e7f9191064">data_pid_start</a>);
+<a name="l00093"></a>00093                 DWC_PRINTF(<span class="stringliteral">"    xfer_started: %d\n"</span>, hc-&gt;<a class="code" href="structdwc__hc.html#78a1cf134604b24bfdedb4f4df9f2c1f">xfer_started</a>);
+<a name="l00094"></a>00094                 DWC_PRINTF(<span class="stringliteral">"    halt_status: %d\n"</span>, hc-&gt;<a class="code" href="structdwc__hc.html#07eca0fa02105ddaa1719387f5558b23">halt_status</a>);
+<a name="l00095"></a>00095                 DWC_PRINTF(<span class="stringliteral">"    xfer_buff: %p\n"</span>, hc-&gt;<a class="code" href="structdwc__hc.html#9dc781cb9e4bc639765beee37ce76673">xfer_buff</a>);
+<a name="l00096"></a>00096                 DWC_PRINTF(<span class="stringliteral">"    xfer_len: %d\n"</span>, hc-&gt;<a class="code" href="structdwc__hc.html#ce32fe93214f1686896e924fbf61cac7">xfer_len</a>);
+<a name="l00097"></a>00097                 DWC_PRINTF(<span class="stringliteral">"    qh: %p\n"</span>, hc-&gt;<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>);
+<a name="l00098"></a>00098                 DWC_PRINTF(<span class="stringliteral">"  NP inactive sched:\n"</span>);
+<a name="l00099"></a>00099                 DWC_LIST_FOREACH(item, &amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#64c96c47a36d71bad6e4360cec9d07ad">non_periodic_sched_inactive</a>) {
+<a name="l00100"></a>00100                         qh_item =
+<a name="l00101"></a>00101                             DWC_LIST_ENTRY(item, <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a>, qh_list_entry);
+<a name="l00102"></a>00102                         DWC_PRINTF(<span class="stringliteral">"    %p\n"</span>, qh_item);
+<a name="l00103"></a>00103                 }
+<a name="l00104"></a>00104                 DWC_PRINTF(<span class="stringliteral">"  NP active sched:\n"</span>);
+<a name="l00105"></a>00105                 DWC_LIST_FOREACH(item, &amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#ffa3041ad517da9519aa2159cdec3f61">non_periodic_sched_active</a>) {
+<a name="l00106"></a>00106                         qh_item =
+<a name="l00107"></a>00107                             DWC_LIST_ENTRY(item, <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a>, qh_list_entry);
+<a name="l00108"></a>00108                         DWC_PRINTF(<span class="stringliteral">"    %p\n"</span>, qh_item);
+<a name="l00109"></a>00109                 }
+<a name="l00110"></a>00110                 DWC_PRINTF(<span class="stringliteral">"  Channels: \n"</span>);
+<a name="l00111"></a>00111                 <span class="keywordflow">for</span> (i = 0; i &lt; num_channels; i++) {
+<a name="l00112"></a>00112                         <a class="code" href="structdwc__hc.html">dwc_hc_t</a> *hc = hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#cb393f6a676fb106e0e3d35396fb97f9">hc_ptr_array</a>[i];
+<a name="l00113"></a>00113                         DWC_PRINTF(<span class="stringliteral">"    %2d: %p\n"</span>, i, hc);
+<a name="l00114"></a>00114                 }
+<a name="l00115"></a>00115         }
+<a name="l00116"></a>00116 }
+<a name="l00117"></a>00117 <span class="preprocessor">#endif                          </span><span class="comment">/* DEBUG */</span>
+<a name="l00118"></a>00118 
+<a name="l00123"></a><a class="code" href="dwc__otg__hcd_8c.html#5a7a5af3b84b4af188fa3b60058a039c">00123</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd_8c.html#5a7a5af3b84b4af188fa3b60058a039c">hcd_start_func</a>(<span class="keywordtype">void</span> *_vp)
+<a name="l00124"></a>00124 {
+<a name="l00125"></a>00125         <a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd = (<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *) _vp;
+<a name="l00126"></a>00126 
+<a name="l00127"></a>00127         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"%s() %p\n"</span>, __func__, hcd);
+<a name="l00128"></a>00128         <span class="keywordflow">if</span> (hcd) {
+<a name="l00129"></a>00129                 hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#ffefbd33a59a14b8b46406f5aaeaa2f4">fops</a>-&gt;<a class="code" href="structdwc__otg__hcd__function__ops.html#d74a65269fe5712ac307bfd3230a29b4">start</a>(hcd);
+<a name="l00130"></a>00130         }
+<a name="l00131"></a>00131 }
+<a name="l00132"></a>00132 
+<a name="l00133"></a><a class="code" href="dwc__otg__hcd_8c.html#17f7272e6a2fe4515b3160ad4694ea55">00133</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd_8c.html#17f7272e6a2fe4515b3160ad4694ea55">del_xfer_timers</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd)
+<a name="l00134"></a>00134 {
+<a name="l00135"></a>00135 <span class="preprocessor">#ifdef DEBUG</span>
+<a name="l00136"></a>00136 <span class="preprocessor"></span>        <span class="keywordtype">int</span> i;
+<a name="l00137"></a>00137         <span class="keywordtype">int</span> num_channels = hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#c1b433c6965aa7d48f6ca6818c592039">host_channels</a>;
+<a name="l00138"></a>00138         <span class="keywordflow">for</span> (i = 0; i &lt; num_channels; i++) {
+<a name="l00139"></a>00139                 DWC_TIMER_CANCEL(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;hc_xfer_timer[i]);
+<a name="l00140"></a>00140         }
+<a name="l00141"></a>00141 <span class="preprocessor">#endif</span>
+<a name="l00142"></a>00142 <span class="preprocessor"></span>}
+<a name="l00143"></a>00143 
+<a name="l00144"></a><a class="code" href="dwc__otg__hcd_8c.html#939a9c8afc75cbe47625e392a7c66a1a">00144</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd_8c.html#939a9c8afc75cbe47625e392a7c66a1a">del_timers</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd)
+<a name="l00145"></a>00145 {
+<a name="l00146"></a>00146         <a class="code" href="dwc__otg__hcd_8c.html#17f7272e6a2fe4515b3160ad4694ea55">del_xfer_timers</a>(hcd);
+<a name="l00147"></a>00147         DWC_TIMER_CANCEL(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#de7796a41bb7d1e45ed9dbc20c995342">conn_timer</a>);
+<a name="l00148"></a>00148 }
+<a name="l00149"></a>00149 
+<a name="l00154"></a><a class="code" href="dwc__otg__hcd_8c.html#8fd9263ed86449c5440edd834cb4d766">00154</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd_8c.html#8fd9263ed86449c5440edd834cb4d766">kill_urbs_in_qh_list</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd, dwc_list_link_t * qh_list)
+<a name="l00155"></a>00155 {
+<a name="l00156"></a>00156         dwc_list_link_t *qh_item;
+<a name="l00157"></a>00157         <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *qh;
+<a name="l00158"></a>00158         <a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *qtd, *qtd_tmp;
+<a name="l00159"></a>00159 
+<a name="l00160"></a>00160         DWC_LIST_FOREACH(qh_item, qh_list) {
+<a name="l00161"></a>00161                 qh = DWC_LIST_ENTRY(qh_item, <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a>, qh_list_entry);
+<a name="l00162"></a>00162                 DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp,
+<a name="l00163"></a>00163                                          &amp;qh-&gt;<a class="code" href="structdwc__otg__qh.html#9567d266da8e796d3467fb16ae867f8e">qtd_list</a>, qtd_list_entry) {
+<a name="l00164"></a>00164                         qtd = DWC_CIRCLEQ_FIRST(&amp;qh-&gt;<a class="code" href="structdwc__otg__qh.html#9567d266da8e796d3467fb16ae867f8e">qtd_list</a>);
+<a name="l00165"></a>00165                         <span class="keywordflow">if</span> (qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#7e7767808e8eb9d71de0db00f57553f9">urb</a> != NULL) {
+<a name="l00166"></a>00166                                 hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#ffefbd33a59a14b8b46406f5aaeaa2f4">fops</a>-&gt;<a class="code" href="structdwc__otg__hcd__function__ops.html#09a989481103de7468cd46ef61ace0ce">complete</a>(hcd, qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#7e7767808e8eb9d71de0db00f57553f9">urb</a>-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#5ba0e393ef9768275db85c00e68be477">priv</a>,
+<a name="l00167"></a>00167                                                     qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#7e7767808e8eb9d71de0db00f57553f9">urb</a>,
+<a name="l00168"></a>00168                                                     -DWC_E_TIMEOUT);
+<a name="l00169"></a>00169                                 <a class="code" href="dwc__otg__hcd_8h.html#19adb6641f95448a956015b2d69ba96a">dwc_otg_hcd_qtd_remove_and_free</a>(hcd, qtd, qh);
+<a name="l00170"></a>00170                         }
+<a name="l00171"></a>00171 
+<a name="l00172"></a>00172                 }
+<a name="l00173"></a>00173         }
+<a name="l00174"></a>00174 }
+<a name="l00175"></a>00175 
+<a name="l00182"></a><a class="code" href="dwc__otg__hcd_8c.html#63f169b583c3818268def3614ac2fe0a">00182</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd_8c.html#63f169b583c3818268def3614ac2fe0a">kill_all_urbs</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd)
+<a name="l00183"></a>00183 {
+<a name="l00184"></a>00184         <a class="code" href="dwc__otg__hcd_8c.html#8fd9263ed86449c5440edd834cb4d766">kill_urbs_in_qh_list</a>(hcd, &amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#64c96c47a36d71bad6e4360cec9d07ad">non_periodic_sched_inactive</a>);
+<a name="l00185"></a>00185         <a class="code" href="dwc__otg__hcd_8c.html#8fd9263ed86449c5440edd834cb4d766">kill_urbs_in_qh_list</a>(hcd, &amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#ffa3041ad517da9519aa2159cdec3f61">non_periodic_sched_active</a>);
+<a name="l00186"></a>00186         <a class="code" href="dwc__otg__hcd_8c.html#8fd9263ed86449c5440edd834cb4d766">kill_urbs_in_qh_list</a>(hcd, &amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#2a747cacd6bdbacbef86d4157c34a312">periodic_sched_inactive</a>);
+<a name="l00187"></a>00187         <a class="code" href="dwc__otg__hcd_8c.html#8fd9263ed86449c5440edd834cb4d766">kill_urbs_in_qh_list</a>(hcd, &amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#74b089e094911a558f7b5f24681d3242">periodic_sched_ready</a>);
+<a name="l00188"></a>00188         <a class="code" href="dwc__otg__hcd_8c.html#8fd9263ed86449c5440edd834cb4d766">kill_urbs_in_qh_list</a>(hcd, &amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#4b8deae798f771135c4a99693b26873f">periodic_sched_assigned</a>);
+<a name="l00189"></a>00189         <a class="code" href="dwc__otg__hcd_8c.html#8fd9263ed86449c5440edd834cb4d766">kill_urbs_in_qh_list</a>(hcd, &amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e127912880eb487b3a2f38778c0de238">periodic_sched_queued</a>);
+<a name="l00190"></a>00190 }
+<a name="l00191"></a>00191 
+<a name="l00198"></a><a class="code" href="dwc__otg__hcd_8c.html#65c0cd2720ab3e728fffd0073b4a1aba">00198</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd_8c.html#65c0cd2720ab3e728fffd0073b4a1aba">dwc_otg_hcd_start_connect_timer</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd)
+<a name="l00199"></a>00199 {
+<a name="l00200"></a>00200         DWC_TIMER_SCHEDULE(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#de7796a41bb7d1e45ed9dbc20c995342">conn_timer</a>, 10000 <span class="comment">/* 10 secs */</span> );
+<a name="l00201"></a>00201 }
+<a name="l00202"></a>00202 
+<a name="l00208"></a><a class="code" href="dwc__otg__hcd_8c.html#a0deab93f6ca3bcfcab0085b2bf86113">00208</a> <span class="keyword">static</span> int32_t <a class="code" href="dwc__otg__hcd_8c.html#a0deab93f6ca3bcfcab0085b2bf86113">dwc_otg_hcd_session_start_cb</a>(<span class="keywordtype">void</span> *p)
+<a name="l00209"></a>00209 {
+<a name="l00210"></a>00210         <a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>;
+<a name="l00211"></a>00211         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"%s(%p)\n"</span>, __func__, p);
+<a name="l00212"></a>00212         dwc_otg_hcd = p;
+<a name="l00213"></a>00213         <a class="code" href="dwc__otg__hcd_8c.html#65c0cd2720ab3e728fffd0073b4a1aba">dwc_otg_hcd_start_connect_timer</a>(dwc_otg_hcd);
+<a name="l00214"></a>00214         <span class="keywordflow">return</span> 1;
+<a name="l00215"></a>00215 }
+<a name="l00216"></a>00216 
+<a name="l00223"></a><a class="code" href="dwc__otg__hcd_8c.html#1aaeb9f41b201877f86a17d617b828d2">00223</a> <span class="keyword">static</span> int32_t <a class="code" href="dwc__otg__hcd_8c.html#1aaeb9f41b201877f86a17d617b828d2">dwc_otg_hcd_start_cb</a>(<span class="keywordtype">void</span> *p)
+<a name="l00224"></a>00224 {
+<a name="l00225"></a>00225         <a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a> = p;
+<a name="l00226"></a>00226         <a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>;
+<a name="l00227"></a>00227         <a class="code" href="unionhprt0__data.html">hprt0_data_t</a> hprt0;
+<a name="l00228"></a>00228 
+<a name="l00229"></a>00229         <a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a> = dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>;
+<a name="l00230"></a>00230 
+<a name="l00231"></a>00231         <span class="keywordflow">if</span> (<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#5a5c5c1cf8d870101cc1fffac56d88c0">op_state</a> == <a class="code" href="dwc__otg__cil_8h.html#02d6d4d9a0fdcc4fc8c5cf8e6c8577aa">B_HOST</a>) {
+<a name="l00232"></a>00232                 <span class="comment">/*</span>
+<a name="l00233"></a>00233 <span class="comment">                 * Reset the port.  During a HNP mode switch the reset</span>
+<a name="l00234"></a>00234 <span class="comment">                 * needs to occur within 1ms and have a duration of at</span>
+<a name="l00235"></a>00235 <span class="comment">                 * least 50ms.</span>
+<a name="l00236"></a>00236 <span class="comment">                 */</span>
+<a name="l00237"></a>00237                 hprt0.<a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a> = <a class="code" href="dwc__otg__cil_8h.html#ce67da6af4023cffd25333d20992438e">dwc_otg_read_hprt0</a>(<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>);
+<a name="l00238"></a>00238                 hprt0.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#714a31048710164370292124795a9a9b">prtrst</a> = 1;
+<a name="l00239"></a>00239                 dwc_write_reg32(<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#dc8fe33e0bb3829cafa884d5fc603c4d">hprt0</a>, hprt0.<a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a>);
+<a name="l00240"></a>00240         }
+<a name="l00241"></a>00241         DWC_WORKQ_SCHEDULE_DELAYED(<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3716f6d6bc6f956a45efbe6e308386">wq_otg</a>,
+<a name="l00242"></a>00242                                    <a class="code" href="dwc__otg__hcd_8c.html#5a7a5af3b84b4af188fa3b60058a039c">hcd_start_func</a>, dwc_otg_hcd, 50,
+<a name="l00243"></a>00243                                    <span class="stringliteral">"start hcd"</span>);
+<a name="l00244"></a>00244 
+<a name="l00245"></a>00245         <span class="keywordflow">return</span> 1;
+<a name="l00246"></a>00246 }
+<a name="l00247"></a>00247 
+<a name="l00253"></a><a class="code" href="dwc__otg__hcd_8c.html#2af30c3c78408325b26e3431b2442055">00253</a> <span class="keyword">static</span> int32_t <a class="code" href="dwc__otg__hcd_8c.html#2af30c3c78408325b26e3431b2442055">dwc_otg_hcd_disconnect_cb</a>(<span class="keywordtype">void</span> *p)
+<a name="l00254"></a>00254 {
+<a name="l00255"></a>00255         <a class="code" href="uniongintsts__data.html">gintsts_data_t</a> intr;
+<a name="l00256"></a>00256         <a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a> = p;
+<a name="l00257"></a>00257 
+<a name="l00258"></a>00258         <span class="comment">/*</span>
+<a name="l00259"></a>00259 <span class="comment">         * Set status flags for the hub driver.</span>
+<a name="l00260"></a>00260 <span class="comment">         */</span>
+<a name="l00261"></a>00261         dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#9aaf2a112f5794f92dedd826342bd637">flags</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#76f573861d9316238ded198c58c228c7">b</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#cd31ac4b9658265e90773448f354f0e1">port_connect_status_change</a> = 1;
+<a name="l00262"></a>00262         dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#9aaf2a112f5794f92dedd826342bd637">flags</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#76f573861d9316238ded198c58c228c7">b</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#9314ac02ed140807687793b512f78c63">port_connect_status</a> = 0;
+<a name="l00263"></a>00263 
+<a name="l00264"></a>00264         <span class="comment">/*</span>
+<a name="l00265"></a>00265 <span class="comment">         * Shutdown any transfers in process by clearing the Tx FIFO Empty</span>
+<a name="l00266"></a>00266 <span class="comment">         * interrupt mask and status bits and disabling subsequent host</span>
+<a name="l00267"></a>00267 <span class="comment">         * channel interrupts.</span>
+<a name="l00268"></a>00268 <span class="comment">         */</span>
+<a name="l00269"></a>00269         intr.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a> = 0;
+<a name="l00270"></a>00270         intr.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#adebf5ff5bdf69a2bcf0bd4b2ba55ef4">nptxfempty</a> = 1;
+<a name="l00271"></a>00271         intr.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#54ed752629e9b8916507beca28d76162">ptxfempty</a> = 1;
+<a name="l00272"></a>00272         intr.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#e02f1a50b20ed1c4248fd76e155147e8">hcintr</a> = 1;
+<a name="l00273"></a>00273         dwc_modify_reg32(&amp;dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#48827c76da2c6b18f369e2f2483cc4b6">gintmsk</a>,
+<a name="l00274"></a>00274                          intr.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a>, 0);
+<a name="l00275"></a>00275         dwc_modify_reg32(&amp;dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>,
+<a name="l00276"></a>00276                          intr.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a>, 0);
+<a name="l00277"></a>00277 
+<a name="l00278"></a>00278         <a class="code" href="dwc__otg__hcd_8c.html#939a9c8afc75cbe47625e392a7c66a1a">del_timers</a>(dwc_otg_hcd);
+<a name="l00279"></a>00279 
+<a name="l00280"></a>00280         <span class="comment">/*</span>
+<a name="l00281"></a>00281 <span class="comment">         * Turn off the vbus power only if the core has transitioned to device</span>
+<a name="l00282"></a>00282 <span class="comment">         * mode. If still in host mode, need to keep power on to detect a</span>
+<a name="l00283"></a>00283 <span class="comment">         * reconnection.</span>
+<a name="l00284"></a>00284 <span class="comment">         */</span>
+<a name="l00285"></a>00285         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#e83fb22890bc54c6b06cedb751430e77">dwc_otg_is_device_mode</a>(dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>)) {
+<a name="l00286"></a>00286                 <span class="keywordflow">if</span> (dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#5a5c5c1cf8d870101cc1fffac56d88c0">op_state</a> != <a class="code" href="dwc__otg__cil_8h.html#da9f5eb506da71435e8976ceb38bc14d">A_SUSPEND</a>) {
+<a name="l00287"></a>00287                         <a class="code" href="unionhprt0__data.html">hprt0_data_t</a> hprt0 = {.d32 = 0 };
+<a name="l00288"></a>00288                         DWC_PRINTF(<span class="stringliteral">"Disconnect: PortPower off\n"</span>);
+<a name="l00289"></a>00289                         hprt0.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#010bd8fb208ef4eeaa288b28f8f8c3a4">prtpwr</a> = 0;
+<a name="l00290"></a>00290                         dwc_write_reg32(dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#dc8fe33e0bb3829cafa884d5fc603c4d">hprt0</a>,
+<a name="l00291"></a>00291                                         hprt0.<a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a>);
+<a name="l00292"></a>00292                 }
+<a name="l00293"></a>00293 
+<a name="l00294"></a>00294                 <a class="code" href="dwc__otg__cil_8c.html#4dd4a30dd75a819e9da38d6410cbb0a4">dwc_otg_disable_host_interrupts</a>(dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>);
+<a name="l00295"></a>00295         }
+<a name="l00296"></a>00296 
+<a name="l00297"></a>00297         <span class="comment">/* Respond with an error status to all URBs in the schedule. */</span>
+<a name="l00298"></a>00298         <a class="code" href="dwc__otg__hcd_8c.html#63f169b583c3818268def3614ac2fe0a">kill_all_urbs</a>(dwc_otg_hcd);
+<a name="l00299"></a>00299 
+<a name="l00300"></a>00300         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#f0bfe5f933e21a94ea06c96ffc086e72">dwc_otg_is_host_mode</a>(dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>)) {
+<a name="l00301"></a>00301                 <span class="comment">/* Clean up any host channels that were in use. */</span>
+<a name="l00302"></a>00302                 <span class="keywordtype">int</span> num_channels;
+<a name="l00303"></a>00303                 <span class="keywordtype">int</span> i;
+<a name="l00304"></a>00304                 <a class="code" href="structdwc__hc.html">dwc_hc_t</a> *channel;
+<a name="l00305"></a>00305                 <a class="code" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *hc_regs;
+<a name="l00306"></a>00306                 <a class="code" href="unionhcchar__data.html">hcchar_data_t</a> hcchar;
+<a name="l00307"></a>00307 
+<a name="l00308"></a>00308                 num_channels = dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#c1b433c6965aa7d48f6ca6818c592039">host_channels</a>;
+<a name="l00309"></a>00309 
+<a name="l00310"></a>00310                 <span class="keywordflow">if</span> (!dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a>) {
+<a name="l00311"></a>00311                         <span class="comment">/* Flush out any channel requests in slave mode. */</span>
+<a name="l00312"></a>00312                         <span class="keywordflow">for</span> (i = 0; i &lt; num_channels; i++) {
+<a name="l00313"></a>00313                                 channel = dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#cb393f6a676fb106e0e3d35396fb97f9">hc_ptr_array</a>[i];
+<a name="l00314"></a>00314                                 if (DWC_CIRCLEQ_EMPTY_ENTRY
+<a name="l00315"></a>00315                                     (channel, hc_list_entry)) {
+<a name="l00316"></a>00316                                         hc_regs =
+<a name="l00317"></a>00317                                             dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;
+<a name="l00318"></a>00318                                             hc_regs[i];
+<a name="l00319"></a>00319                                         hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a> =
+<a name="l00320"></a>00320                                             dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">hcchar</a>);
+<a name="l00321"></a>00321                                         if (hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#994a5305780edb0c4fe159b6cc7b14ae">chen</a>) {
+<a name="l00322"></a>00322                                                 hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#994a5305780edb0c4fe159b6cc7b14ae">chen</a> = 0;
+<a name="l00323"></a>00323                                                 hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#73c9f7f3cc4036c72ef341d1d1d9c388">chdis</a> = 1;
+<a name="l00324"></a>00324                                                 hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#11f1b16e50f90806f90953bb979d4e77">epdir</a> = 0;
+<a name="l00325"></a>00325                                                 dwc_write_reg32(&amp;hc_regs-&gt;
+<a name="l00326"></a>00326                                                                 hcchar,
+<a name="l00327"></a>00327                                                                 hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a>);
+<a name="l00328"></a>00328                                         }
+<a name="l00329"></a>00329                                 }
+<a name="l00330"></a>00330                         }
+<a name="l00331"></a>00331                 }
+<a name="l00332"></a>00332 
+<a name="l00333"></a>00333                 <span class="keywordflow">for</span> (i = 0; i &lt; num_channels; i++) {
+<a name="l00334"></a>00334                         channel = dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#cb393f6a676fb106e0e3d35396fb97f9">hc_ptr_array</a>[i];
+<a name="l00335"></a>00335                         if (DWC_CIRCLEQ_EMPTY_ENTRY(channel, hc_list_entry)) {
+<a name="l00336"></a>00336                                 hc_regs =
+<a name="l00337"></a>00337                                     dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#7f7c107d4720641eb4141cd817211ac0">hc_regs</a>[i];
+<a name="l00338"></a>00338                                 hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">hcchar</a>);
+<a name="l00339"></a>00339                                 if (hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#994a5305780edb0c4fe159b6cc7b14ae">chen</a>) {
+<a name="l00340"></a>00340                                         <span class="comment">/* Halt the channel. */</span>
+<a name="l00341"></a>00341                                         hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#73c9f7f3cc4036c72ef341d1d1d9c388">chdis</a> = 1;
+<a name="l00342"></a>00342                                         dwc_write_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">hcchar</a>,
+<a name="l00343"></a>00343                                                         hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a>);
+<a name="l00344"></a>00344                                 }
+<a name="l00345"></a>00345 
+<a name="l00346"></a>00346                                 <a class="code" href="dwc__otg__cil_8c.html#f05341f811fba7f6183db66faf50a867">dwc_otg_hc_cleanup</a>(dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>,
+<a name="l00347"></a>00347                                                    channel);
+<a name="l00348"></a>00348                                 DWC_CIRCLEQ_INSERT_TAIL(&amp;dwc_otg_hcd-&gt;
+<a name="l00349"></a>00349                                                         <a class="code" href="structdwc__otg__hcd.html#1761f2e6b8f6ba82c0e0c4e561813f0f">free_hc_list</a>, channel,
+<a name="l00350"></a>00350                                                         hc_list_entry);
+<a name="l00351"></a>00351                                 <span class="comment">/* </span>
+<a name="l00352"></a>00352 <span class="comment">                                 * Added for Descriptor DMA to prevent channel double cleanup </span>
+<a name="l00353"></a>00353 <span class="comment">                                 * in release_channel_ddma(). Which called from ep_disable</span>
+<a name="l00354"></a>00354 <span class="comment">                                 * when device disconnect.</span>
+<a name="l00355"></a>00355 <span class="comment">                                 */</span>                     
+<a name="l00356"></a>00356                                 channel-&gt;qh = NULL;                     
+<a name="l00357"></a>00357                         }
+<a name="l00358"></a>00358                 }
+<a name="l00359"></a>00359         }
+<a name="l00360"></a>00360 
+<a name="l00361"></a>00361         <span class="keywordflow">if</span> (<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>-&gt;fops-&gt;disconnect) {
+<a name="l00362"></a>00362                 <a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>-&gt;fops-&gt;disconnect(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>);
+<a name="l00363"></a>00363         }
+<a name="l00364"></a>00364 
+<a name="l00365"></a>00365         <span class="keywordflow">return</span> 1;
+<a name="l00366"></a>00366 }
+<a name="l00367"></a>00367 
+<a name="l00373"></a><a class="code" href="dwc__otg__hcd_8c.html#44e479b1c67b62a1887f93afd2106e4a">00373</a> <span class="keyword">static</span> int32_t <a class="code" href="dwc__otg__hcd_8c.html#44e479b1c67b62a1887f93afd2106e4a">dwc_otg_hcd_stop_cb</a>(<span class="keywordtype">void</span> *p)
+<a name="l00374"></a>00374 {
+<a name="l00375"></a>00375         <a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a> = p;
+<a name="l00376"></a>00376 
+<a name="l00377"></a>00377         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"%s(%p)\n"</span>, __func__, p);
+<a name="l00378"></a>00378         <a class="code" href="dwc__otg__hcd_8c.html#70c58e8a45eb7ad8ee2f2c74ba3a77f0">dwc_otg_hcd_stop</a>(dwc_otg_hcd);
+<a name="l00379"></a>00379         <span class="keywordflow">return</span> 1;
+<a name="l00380"></a>00380 }
+<a name="l00381"></a>00381 
+<a name="l00382"></a>00382 <span class="preprocessor">#ifdef CONFIG_USB_DWC_OTG_LPM</span>
+<a name="l00383"></a>00383 <span class="preprocessor"></span>
+<a name="l00388"></a>00388 <span class="keyword">static</span> <span class="keywordtype">int</span> dwc_otg_hcd_sleep_cb(<span class="keywordtype">void</span> *p)
+<a name="l00389"></a>00389 {
+<a name="l00390"></a>00390         <a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd = p;
+<a name="l00391"></a>00391 
+<a name="l00392"></a>00392         dwc_otg_hcd_free_hc_from_lpm(hcd);
+<a name="l00393"></a>00393 
+<a name="l00394"></a>00394         <span class="keywordflow">return</span> 0;
+<a name="l00395"></a>00395 }
+<a name="l00396"></a>00396 <span class="preprocessor">#endif</span>
+<a name="l00397"></a>00397 <span class="preprocessor"></span>
+<a name="l00403"></a><a class="code" href="dwc__otg__hcd_8c.html#fb35aff10c8837095302575957145f13">00403</a> <span class="keyword">static</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd_8c.html#fb35aff10c8837095302575957145f13">dwc_otg_hcd_rem_wakeup_cb</a>(<span class="keywordtype">void</span> *p)
+<a name="l00404"></a>00404 {
+<a name="l00405"></a>00405         <a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd = p;
+<a name="l00406"></a>00406 
+<a name="l00407"></a>00407         <span class="keywordflow">if</span> (hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#2b0701d814069ec69897e08374366c7b">lx_state</a> == <a class="code" href="dwc__otg__cil_8h.html#8442e49b7c783099ac17bda4f8b3bc3cd1fadb6fa31de73e8176316a0e0ba905">DWC_OTG_L2</a>) {
+<a name="l00408"></a>00408                 hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#9aaf2a112f5794f92dedd826342bd637">flags</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#76f573861d9316238ded198c58c228c7">b</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#2a6e323cb4c01153aff1adc6269c74c7">port_suspend_change</a> = 1;
+<a name="l00409"></a>00409         }
+<a name="l00410"></a>00410 <span class="preprocessor">#ifdef CONFIG_USB_DWC_OTG_LPM</span>
+<a name="l00411"></a>00411 <span class="preprocessor"></span>        <span class="keywordflow">else</span> {
+<a name="l00412"></a>00412                 hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#9aaf2a112f5794f92dedd826342bd637">flags</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#76f573861d9316238ded198c58c228c7">b</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#1900375ccea165f0efc40725f507a0bf">port_l1_change</a> = 1;
+<a name="l00413"></a>00413         }
+<a name="l00414"></a>00414 <span class="preprocessor">#endif</span>
+<a name="l00415"></a>00415 <span class="preprocessor"></span>        <span class="keywordflow">return</span> 0;
+<a name="l00416"></a>00416 }
+<a name="l00417"></a>00417 
+<a name="l00422"></a><a class="code" href="dwc__otg__hcd__if_8h.html#70c58e8a45eb7ad8ee2f2c74ba3a77f0">00422</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd_8c.html#70c58e8a45eb7ad8ee2f2c74ba3a77f0">dwc_otg_hcd_stop</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd)
+<a name="l00423"></a>00423 {
+<a name="l00424"></a>00424         <a class="code" href="unionhprt0__data.html">hprt0_data_t</a> hprt0 = {.d32 = 0 };
+<a name="l00425"></a>00425 
+<a name="l00426"></a>00426         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#e4a050e176c1c4f556da2b276a8c2b37">DBG_HCD</a>, <span class="stringliteral">"DWC OTG HCD STOP\n"</span>);
+<a name="l00427"></a>00427 
+<a name="l00428"></a>00428         <span class="comment">/*</span>
+<a name="l00429"></a>00429 <span class="comment">         * The root hub should be disconnected before this function is called.</span>
+<a name="l00430"></a>00430 <span class="comment">         * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)</span>
+<a name="l00431"></a>00431 <span class="comment">         * and the QH lists (via ..._hcd_endpoint_disable).</span>
+<a name="l00432"></a>00432 <span class="comment">         */</span>
+<a name="l00433"></a>00433 
+<a name="l00434"></a>00434         <span class="comment">/* Turn off all host-specific interrupts. */</span>
+<a name="l00435"></a>00435         <a class="code" href="dwc__otg__cil_8c.html#4dd4a30dd75a819e9da38d6410cbb0a4">dwc_otg_disable_host_interrupts</a>(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>);
+<a name="l00436"></a>00436 
+<a name="l00437"></a>00437         <span class="comment">/* Turn off the vbus power */</span>
+<a name="l00438"></a>00438         DWC_PRINTF(<span class="stringliteral">"PortPower off\n"</span>);
+<a name="l00439"></a>00439         hprt0.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#010bd8fb208ef4eeaa288b28f8f8c3a4">prtpwr</a> = 0;
+<a name="l00440"></a>00440         dwc_write_reg32(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#dc8fe33e0bb3829cafa884d5fc603c4d">hprt0</a>, hprt0.<a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a>);
+<a name="l00441"></a>00441         dwc_mdelay(1);
+<a name="l00442"></a>00442 }
+<a name="l00443"></a>00443 
+<a name="l00444"></a><a class="code" href="dwc__otg__hcd__if_8h.html#e8db09c826a847ffbaf7a5e7a60b697c">00444</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd_8c.html#e8129fbc0a4073f0a5f64fa3b0f5127b">dwc_otg_hcd_urb_enqueue</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd,
+<a name="l00445"></a>00445                             <a class="code" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> * dwc_otg_urb, <span class="keywordtype">void</span> **ep_handle)
+<a name="l00446"></a>00446 {
+<a name="l00447"></a>00447         uint64_t <a class="code" href="structdwc__otg__hcd.html#9aaf2a112f5794f92dedd826342bd637">flags</a>;
+<a name="l00448"></a>00448         <span class="keywordtype">int</span> retval = 0;
+<a name="l00449"></a>00449         <a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *qtd;
+<a name="l00450"></a>00450 
+<a name="l00451"></a>00451         <span class="keywordflow">if</span> (!hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#9aaf2a112f5794f92dedd826342bd637">flags</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#76f573861d9316238ded198c58c228c7">b</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#9314ac02ed140807687793b512f78c63">port_connect_status</a>) {
+<a name="l00452"></a>00452                 <span class="comment">/* No longer connected. */</span>
+<a name="l00453"></a>00453                 <span class="keywordflow">return</span> -DWC_E_NO_DEVICE;
+<a name="l00454"></a>00454         }
+<a name="l00455"></a>00455 
+<a name="l00456"></a>00456         qtd = <a class="code" href="dwc__otg__hcd_8h.html#5c4da8822ae027f70eda33cb783644fc">dwc_otg_hcd_qtd_create</a>(dwc_otg_urb);
+<a name="l00457"></a>00457         <span class="keywordflow">if</span> (qtd == NULL) {
+<a name="l00458"></a>00458                 DWC_ERROR(<span class="stringliteral">"DWC OTG HCD URB Enqueue failed creating QTD\n"</span>);
+<a name="l00459"></a>00459                 <span class="keywordflow">return</span> -DWC_E_NO_MEMORY;
+<a name="l00460"></a>00460         }
+<a name="l00461"></a>00461 
+<a name="l00462"></a>00462         retval =
+<a name="l00463"></a>00463             <a class="code" href="dwc__otg__hcd_8h.html#748ba77769387bfe4295cb10265053f0">dwc_otg_hcd_qtd_add</a>(qtd, hcd, (<a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> **) ep_handle);
+<a name="l00464"></a>00464         <span class="keywordflow">if</span> (retval &lt; 0) {
+<a name="l00465"></a>00465                 DWC_ERROR(<span class="stringliteral">"DWC OTG HCD URB Enqueue failed adding QTD. "</span>
+<a name="l00466"></a>00466                           <span class="stringliteral">"Error status %d\n"</span>, retval);
+<a name="l00467"></a>00467                 <a class="code" href="dwc__otg__hcd_8h.html#34434d836361462c04fb45ba9ab89fb9">dwc_otg_hcd_qtd_free</a>(qtd);
+<a name="l00468"></a>00468         } <span class="keywordflow">else</span> {
+<a name="l00469"></a>00469                 qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#f80ddcfb6edbe83a3991dd67c93a47e4">qh</a> = *ep_handle;
+<a name="l00470"></a>00470         }
+<a name="l00471"></a>00471         
+<a name="l00472"></a>00472         <span class="keywordflow">if</span> (hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a> &amp;&amp; retval == 0) {
+<a name="l00473"></a>00473                 <a class="code" href="dwc__otg__hcd_8h.html#92c49783eebc5bcffa8b8a51c2127be9">dwc_otg_transaction_type_e</a> tr_type;     
+<a name="l00474"></a>00474                 <span class="keywordflow">if</span> ((qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#f80ddcfb6edbe83a3991dd67c93a47e4">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#98b78ffd8dbc01be44b302e873e73a82">ep_type</a> == UE_BULK) &amp;&amp; !(qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#7e7767808e8eb9d71de0db00f57553f9">urb</a>-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#2f1d90765496d78d297b3e57ef4d781c">flags</a> &amp; <a class="code" href="dwc__otg__hcd__if_8h.html#973a9deb7ee08e99abf7cb7adf6a5c72">URB_GIVEBACK_ASAP</a>)) {
+<a name="l00475"></a>00475                         <span class="comment">/* Do not schedule SG transcations until qtd has URB_GIVEBACK_ASAP set */</span>
+<a name="l00476"></a>00476                         <span class="keywordflow">return</span> 0;
+<a name="l00477"></a>00477                 }
+<a name="l00478"></a>00478                 DWC_SPINLOCK_IRQSAVE(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#34f29e9c035009476495f7701c1813fd">lock</a>, &amp;flags);
+<a name="l00479"></a>00479                 tr_type = <a class="code" href="dwc__otg__hcd_8c.html#96cc299f4f0478187ed7ba49b975ffc3">dwc_otg_hcd_select_transactions</a>(hcd);
+<a name="l00480"></a>00480                 <span class="keywordflow">if</span> (tr_type != DWC_OTG_TRANSACTION_NONE) {
+<a name="l00481"></a>00481                         <a class="code" href="dwc__otg__hcd_8c.html#2f57bf2fc3013d63101f112702b913a0">dwc_otg_hcd_queue_transactions</a>(hcd, tr_type);
+<a name="l00482"></a>00482                 }
+<a name="l00483"></a>00483                 DWC_SPINUNLOCK_IRQRESTORE(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#34f29e9c035009476495f7701c1813fd">lock</a>, flags);
+<a name="l00484"></a>00484         }
+<a name="l00485"></a>00485 
+<a name="l00486"></a>00486         <span class="keywordflow">return</span> retval;
+<a name="l00487"></a>00487 }
+<a name="l00488"></a>00488 
+<a name="l00489"></a><a class="code" href="dwc__otg__hcd__if_8h.html#e7377ee6d5cdb17a4213cc96bf534a23">00489</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd_8c.html#8844d0e14480b7f0dcf5c8120cc20a4f">dwc_otg_hcd_urb_dequeue</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd,
+<a name="l00490"></a>00490                             <a class="code" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> * dwc_otg_urb)
+<a name="l00491"></a>00491 {
+<a name="l00492"></a>00492         uint64_t <a class="code" href="structdwc__otg__hcd.html#9aaf2a112f5794f92dedd826342bd637">flags</a>;
+<a name="l00493"></a>00493 
+<a name="l00494"></a>00494         <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *qh;
+<a name="l00495"></a>00495         <a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *urb_qtd;
+<a name="l00496"></a>00496 
+<a name="l00497"></a>00497         DWC_SPINLOCK_IRQSAVE(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#34f29e9c035009476495f7701c1813fd">lock</a>, &amp;flags);
+<a name="l00498"></a>00498         
+<a name="l00499"></a>00499         urb_qtd = dwc_otg_urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#68dc4d459bb70aed6083553653aadaad">qtd</a>;
+<a name="l00500"></a>00500         qh = urb_qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#f80ddcfb6edbe83a3991dd67c93a47e4">qh</a>;
+<a name="l00501"></a>00501 <span class="preprocessor">#ifdef DEBUG</span>
+<a name="l00502"></a>00502 <span class="preprocessor"></span>        <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__dbg_8h.html#7a96217c88a4d786f6cb3d4df09dee04">CHK_DEBUG_LEVEL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a> | <a class="code" href="dwc__otg__dbg_8h.html#737e22e02729647d12db8e3059ad06c9">DBG_HCD_URB</a>)) {
+<a name="l00503"></a>00503                 <span class="keywordflow">if</span> (urb_qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#c1d73f1d48eeabbdc198ad28c0882bc1">in_process</a>) {
+<a name="l00504"></a>00504                         dump_channel_info(hcd, qh);
+<a name="l00505"></a>00505                 }
+<a name="l00506"></a>00506         }
+<a name="l00507"></a>00507 <span class="preprocessor">#endif</span>
+<a name="l00508"></a>00508 <span class="preprocessor"></span>        <span class="keywordflow">if</span> (urb_qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#c1d73f1d48eeabbdc198ad28c0882bc1">in_process</a> &amp;&amp; qh-&gt;<a class="code" href="structdwc__otg__qh.html#bbdb7d30b60b6c326301f33b35088bb4">channel</a>) {
+<a name="l00509"></a>00509                 <span class="comment">/* The QTD is in process (it has been assigned to a channel). */</span>
+<a name="l00510"></a>00510                 <span class="keywordflow">if</span> (hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#9aaf2a112f5794f92dedd826342bd637">flags</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#76f573861d9316238ded198c58c228c7">b</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#9314ac02ed140807687793b512f78c63">port_connect_status</a>) {
+<a name="l00511"></a>00511                         <span class="comment">/*</span>
+<a name="l00512"></a>00512 <span class="comment">                         * If still connected (i.e. in host mode), halt the</span>
+<a name="l00513"></a>00513 <span class="comment">                         * channel so it can be used for other transfers. If</span>
+<a name="l00514"></a>00514 <span class="comment">                         * no longer connected, the host registers can't be</span>
+<a name="l00515"></a>00515 <span class="comment">                         * written to halt the channel since the core is in</span>
+<a name="l00516"></a>00516 <span class="comment">                         * device mode.</span>
+<a name="l00517"></a>00517 <span class="comment">                         */</span>
+<a name="l00518"></a>00518                         <a class="code" href="dwc__otg__cil_8c.html#de044bf6b96c1bac92259a447ae85c0f">dwc_otg_hc_halt</a>(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>, qh-&gt;<a class="code" href="structdwc__otg__qh.html#bbdb7d30b60b6c326301f33b35088bb4">channel</a>,
+<a name="l00519"></a>00519                                         DWC_OTG_HC_XFER_URB_DEQUEUE);
+<a name="l00520"></a>00520                 }
+<a name="l00521"></a>00521         }
+<a name="l00522"></a>00522 
+<a name="l00523"></a>00523         <span class="comment">/*</span>
+<a name="l00524"></a>00524 <span class="comment">         * Free the QTD and clean up the associated QH. Leave the QH in the</span>
+<a name="l00525"></a>00525 <span class="comment">         * schedule if it has any remaining QTDs.</span>
+<a name="l00526"></a>00526 <span class="comment">         */</span>
+<a name="l00527"></a>00527          
+<a name="l00528"></a>00528         <span class="keywordflow">if</span> (!hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a>) {
+<a name="l00529"></a>00529                 uint8_t b = urb_qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#c1d73f1d48eeabbdc198ad28c0882bc1">in_process</a>;        
+<a name="l00530"></a>00530                 <a class="code" href="dwc__otg__hcd_8h.html#19adb6641f95448a956015b2d69ba96a">dwc_otg_hcd_qtd_remove_and_free</a>(hcd, urb_qtd, qh);
+<a name="l00531"></a>00531                 <span class="keywordflow">if</span> (b) {
+<a name="l00532"></a>00532                         <a class="code" href="dwc__otg__hcd_8h.html#f88bc5b6beb674c909d1c09a819ba9d9">dwc_otg_hcd_qh_deactivate</a>(hcd, qh, 0);
+<a name="l00533"></a>00533                         qh-&gt;<a class="code" href="structdwc__otg__qh.html#bbdb7d30b60b6c326301f33b35088bb4">channel</a> = NULL;
+<a name="l00534"></a>00534                 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (DWC_CIRCLEQ_EMPTY(&amp;qh-&gt;<a class="code" href="structdwc__otg__qh.html#9567d266da8e796d3467fb16ae867f8e">qtd_list</a>)) {
+<a name="l00535"></a>00535                         <a class="code" href="dwc__otg__hcd_8h.html#506b89b01ee7692885daff1c17c894f8">dwc_otg_hcd_qh_remove</a>(hcd, qh);
+<a name="l00536"></a>00536                 }
+<a name="l00537"></a>00537         }
+<a name="l00538"></a>00538         <span class="keywordflow">else</span> {
+<a name="l00539"></a>00539                 <a class="code" href="dwc__otg__hcd_8h.html#19adb6641f95448a956015b2d69ba96a">dwc_otg_hcd_qtd_remove_and_free</a>(hcd, urb_qtd, qh);
+<a name="l00540"></a>00540         }
+<a name="l00541"></a>00541         
+<a name="l00542"></a>00542         DWC_SPINUNLOCK_IRQRESTORE(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#34f29e9c035009476495f7701c1813fd">lock</a>, flags);
+<a name="l00543"></a>00543 
+<a name="l00544"></a>00544         <span class="keywordflow">return</span> 0;
+<a name="l00545"></a>00545 }
+<a name="l00546"></a>00546 
+<a name="l00547"></a><a class="code" href="dwc__otg__hcd__if_8h.html#f80e9550161e354c865e3c411d661dbe">00547</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd_8c.html#f80e9550161e354c865e3c411d661dbe">dwc_otg_hcd_endpoint_disable</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd, <span class="keywordtype">void</span> *ep_handle,
+<a name="l00548"></a>00548                                  <span class="keywordtype">int</span> retry)
+<a name="l00549"></a>00549 {
+<a name="l00550"></a>00550         <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *qh = (<a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *) ep_handle;
+<a name="l00551"></a>00551         <span class="keywordtype">int</span> retval = 0;
+<a name="l00552"></a>00552         uint64_t <a class="code" href="structdwc__otg__hcd.html#9aaf2a112f5794f92dedd826342bd637">flags</a>;
+<a name="l00553"></a>00553 
+<a name="l00554"></a>00554         <span class="keywordflow">if</span> (retry &lt; 0) {
+<a name="l00555"></a>00555                 retval = -DWC_E_INVALID;
+<a name="l00556"></a>00556                 <span class="keywordflow">goto</span> done;
+<a name="l00557"></a>00557         }
+<a name="l00558"></a>00558 
+<a name="l00559"></a>00559         <span class="keywordflow">if</span> (!qh) {
+<a name="l00560"></a>00560                 <span class="keywordflow">goto</span> done;
+<a name="l00561"></a>00561         }
+<a name="l00562"></a>00562 
+<a name="l00563"></a>00563         DWC_SPINLOCK_IRQSAVE(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#34f29e9c035009476495f7701c1813fd">lock</a>, &amp;flags);
+<a name="l00564"></a>00564         
+<a name="l00565"></a>00565         <span class="keywordflow">while</span> (!DWC_CIRCLEQ_EMPTY(&amp;qh-&gt;<a class="code" href="structdwc__otg__qh.html#9567d266da8e796d3467fb16ae867f8e">qtd_list</a>) &amp;&amp; retry) {
+<a name="l00566"></a>00566                 DWC_SPINUNLOCK_IRQRESTORE(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#34f29e9c035009476495f7701c1813fd">lock</a>, flags);
+<a name="l00567"></a>00567                 retry--;
+<a name="l00568"></a>00568                 dwc_msleep(5);
+<a name="l00569"></a>00569                 DWC_SPINLOCK_IRQSAVE(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#34f29e9c035009476495f7701c1813fd">lock</a>, &amp;flags);
+<a name="l00570"></a>00570         }
+<a name="l00571"></a>00571 
+<a name="l00572"></a>00572         <a class="code" href="dwc__otg__hcd_8h.html#506b89b01ee7692885daff1c17c894f8">dwc_otg_hcd_qh_remove</a>(hcd, qh);
+<a name="l00573"></a>00573         
+<a name="l00574"></a>00574         DWC_SPINUNLOCK_IRQRESTORE(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#34f29e9c035009476495f7701c1813fd">lock</a>, flags);
+<a name="l00575"></a>00575         <span class="comment">/* </span>
+<a name="l00576"></a>00576 <span class="comment">         * Split dwc_otg_hcd_qh_remove_and_free() into qh_remove </span>
+<a name="l00577"></a>00577 <span class="comment">         * and qh_free to prevent stack dump on dwc_dma_free() with </span>
+<a name="l00578"></a>00578 <span class="comment">         * irq_disabled (spinlock_irqsave) in dwc_otg_hcd_desc_list_free() </span>
+<a name="l00579"></a>00579 <span class="comment">         * and dwc_otg_hcd_frame_list_alloc().</span>
+<a name="l00580"></a>00580 <span class="comment">         */</span>
+<a name="l00581"></a>00581         <a class="code" href="dwc__otg__hcd_8h.html#1ac731c0691ac3851edddc558fae79e0">dwc_otg_hcd_qh_free</a>(hcd, qh);
+<a name="l00582"></a>00582 
+<a name="l00583"></a>00583       done:
+<a name="l00584"></a>00584         <span class="keywordflow">return</span> retval;
+<a name="l00585"></a>00585 }
+<a name="l00586"></a>00586 
+<a name="l00590"></a><a class="code" href="dwc__otg__hcd_8c.html#106ff6cbb1499325ea75f2d97abb8e6a">00590</a> <span class="keyword">static</span> <a class="code" href="structdwc__otg__cil__callbacks.html">dwc_otg_cil_callbacks_t</a> <a class="code" href="dwc__otg__hcd_8c.html#106ff6cbb1499325ea75f2d97abb8e6a">hcd_cil_callbacks</a> = {
+<a name="l00591"></a>00591         .<a class="code" href="structdwc__otg__cil__callbacks.html#ebb662b2e0b4d187648b7f91b9d00713">start</a> = <a class="code" href="dwc__otg__hcd_8c.html#1aaeb9f41b201877f86a17d617b828d2">dwc_otg_hcd_start_cb</a>,
+<a name="l00592"></a>00592         .stop = <a class="code" href="dwc__otg__hcd_8c.html#44e479b1c67b62a1887f93afd2106e4a">dwc_otg_hcd_stop_cb</a>,
+<a name="l00593"></a>00593         .disconnect = <a class="code" href="dwc__otg__hcd_8c.html#2af30c3c78408325b26e3431b2442055">dwc_otg_hcd_disconnect_cb</a>,
+<a name="l00594"></a>00594         .session_start = <a class="code" href="dwc__otg__hcd_8c.html#a0deab93f6ca3bcfcab0085b2bf86113">dwc_otg_hcd_session_start_cb</a>,
+<a name="l00595"></a>00595         .resume_wakeup = <a class="code" href="dwc__otg__hcd_8c.html#fb35aff10c8837095302575957145f13">dwc_otg_hcd_rem_wakeup_cb</a>,
+<a name="l00596"></a>00596 <span class="preprocessor">#ifdef CONFIG_USB_DWC_OTG_LPM</span>
+<a name="l00597"></a>00597 <span class="preprocessor"></span>        .sleep = dwc_otg_hcd_sleep_cb,
+<a name="l00598"></a>00598 <span class="preprocessor">#endif</span>
+<a name="l00599"></a>00599 <span class="preprocessor"></span>        .p = 0,
+<a name="l00600"></a>00600 };
+<a name="l00601"></a>00601 
+<a name="l00605"></a><a class="code" href="dwc__otg__hcd_8c.html#ed4640393d701e9bbfd966d4006a60b8">00605</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd_8c.html#ed4640393d701e9bbfd966d4006a60b8">reset_tasklet_func</a>(<span class="keywordtype">void</span> *data)
+<a name="l00606"></a>00606 {
+<a name="l00607"></a>00607         <a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a> = (<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *) data;
+<a name="l00608"></a>00608         <a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a> = dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>;
+<a name="l00609"></a>00609         <a class="code" href="unionhprt0__data.html">hprt0_data_t</a> hprt0;
+<a name="l00610"></a>00610 
+<a name="l00611"></a>00611         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"USB RESET tasklet called\n"</span>);
+<a name="l00612"></a>00612 
+<a name="l00613"></a>00613         hprt0.<a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a> = <a class="code" href="dwc__otg__cil_8h.html#ce67da6af4023cffd25333d20992438e">dwc_otg_read_hprt0</a>(<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>);
+<a name="l00614"></a>00614         hprt0.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#714a31048710164370292124795a9a9b">prtrst</a> = 1;
+<a name="l00615"></a>00615         dwc_write_reg32(<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#dc8fe33e0bb3829cafa884d5fc603c4d">hprt0</a>, hprt0.<a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a>);
+<a name="l00616"></a>00616         dwc_mdelay(60);
+<a name="l00617"></a>00617 
+<a name="l00618"></a>00618         hprt0.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#714a31048710164370292124795a9a9b">prtrst</a> = 0;
+<a name="l00619"></a>00619         dwc_write_reg32(<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#dc8fe33e0bb3829cafa884d5fc603c4d">hprt0</a>, hprt0.<a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a>);
+<a name="l00620"></a>00620         dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#9aaf2a112f5794f92dedd826342bd637">flags</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#76f573861d9316238ded198c58c228c7">b</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#d0d63f32ed35315e8a02549521fb386e">port_reset_change</a> = 1;
+<a name="l00621"></a>00621 }
+<a name="l00622"></a>00622 
+<a name="l00623"></a><a class="code" href="dwc__otg__hcd_8c.html#d76881c1efea1a13be74ecfde85b4881">00623</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd_8c.html#d76881c1efea1a13be74ecfde85b4881">qh_list_free</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd, dwc_list_link_t * qh_list)
+<a name="l00624"></a>00624 {
+<a name="l00625"></a>00625         dwc_list_link_t *item;
+<a name="l00626"></a>00626         <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *qh;
+<a name="l00627"></a>00627 
+<a name="l00628"></a>00628         <span class="keywordflow">if</span> (!qh_list-&gt;next) {
+<a name="l00629"></a>00629                 <span class="comment">/* The list hasn't been initialized yet. */</span>
+<a name="l00630"></a>00630                 <span class="keywordflow">return</span>;
+<a name="l00631"></a>00631         }
+<a name="l00632"></a>00632 
+<a name="l00633"></a>00633         <span class="comment">/* Ensure there are no QTDs or URBs left. */</span>
+<a name="l00634"></a>00634         <a class="code" href="dwc__otg__hcd_8c.html#8fd9263ed86449c5440edd834cb4d766">kill_urbs_in_qh_list</a>(hcd, qh_list);
+<a name="l00635"></a>00635 
+<a name="l00636"></a>00636         DWC_LIST_FOREACH(item, qh_list) {
+<a name="l00637"></a>00637                 qh = DWC_LIST_ENTRY(item, <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a>, qh_list_entry);
+<a name="l00638"></a>00638                 <a class="code" href="dwc__otg__hcd_8h.html#64eb3490186ebd94fd8204d74c089a51">dwc_otg_hcd_qh_remove_and_free</a>(hcd, qh);
+<a name="l00639"></a>00639         }
+<a name="l00640"></a>00640 }
+<a name="l00641"></a>00641 
+<a name="l00646"></a><a class="code" href="dwc__otg__hcd_8c.html#7ee877a9be0c15bacbb92a7babb116d0">00646</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd_8c.html#7ee877a9be0c15bacbb92a7babb116d0">dwc_otg_hcd_free</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * <a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>)
+<a name="l00647"></a>00647 {
+<a name="l00648"></a>00648         <span class="keywordtype">int</span> i;
+<a name="l00649"></a>00649 
+<a name="l00650"></a>00650         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#e4a050e176c1c4f556da2b276a8c2b37">DBG_HCD</a>, <span class="stringliteral">"DWC OTG HCD FREE\n"</span>);
+<a name="l00651"></a>00651 
+<a name="l00652"></a>00652         <a class="code" href="dwc__otg__hcd_8c.html#939a9c8afc75cbe47625e392a7c66a1a">del_timers</a>(dwc_otg_hcd);
+<a name="l00653"></a>00653 
+<a name="l00654"></a>00654         <span class="comment">/* Free memory for QH/QTD lists */</span>
+<a name="l00655"></a>00655         <a class="code" href="dwc__otg__hcd_8c.html#d76881c1efea1a13be74ecfde85b4881">qh_list_free</a>(dwc_otg_hcd, &amp;dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#64c96c47a36d71bad6e4360cec9d07ad">non_periodic_sched_inactive</a>);
+<a name="l00656"></a>00656         <a class="code" href="dwc__otg__hcd_8c.html#d76881c1efea1a13be74ecfde85b4881">qh_list_free</a>(dwc_otg_hcd, &amp;dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#ffa3041ad517da9519aa2159cdec3f61">non_periodic_sched_active</a>);
+<a name="l00657"></a>00657         <a class="code" href="dwc__otg__hcd_8c.html#d76881c1efea1a13be74ecfde85b4881">qh_list_free</a>(dwc_otg_hcd, &amp;dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#2a747cacd6bdbacbef86d4157c34a312">periodic_sched_inactive</a>);
+<a name="l00658"></a>00658         <a class="code" href="dwc__otg__hcd_8c.html#d76881c1efea1a13be74ecfde85b4881">qh_list_free</a>(dwc_otg_hcd, &amp;dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#74b089e094911a558f7b5f24681d3242">periodic_sched_ready</a>);
+<a name="l00659"></a>00659         <a class="code" href="dwc__otg__hcd_8c.html#d76881c1efea1a13be74ecfde85b4881">qh_list_free</a>(dwc_otg_hcd, &amp;dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#4b8deae798f771135c4a99693b26873f">periodic_sched_assigned</a>);
+<a name="l00660"></a>00660         <a class="code" href="dwc__otg__hcd_8c.html#d76881c1efea1a13be74ecfde85b4881">qh_list_free</a>(dwc_otg_hcd, &amp;dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e127912880eb487b3a2f38778c0de238">periodic_sched_queued</a>);
+<a name="l00661"></a>00661 
+<a name="l00662"></a>00662         <span class="comment">/* Free memory for the host channels. */</span>
+<a name="l00663"></a>00663         <span class="keywordflow">for</span> (i = 0; i &lt; <a class="code" href="dwc__otg__core__if_8h.html#bfb88b45545f7685f668ac2f545674ec">MAX_EPS_CHANNELS</a>; i++) {
+<a name="l00664"></a>00664                 <a class="code" href="structdwc__hc.html">dwc_hc_t</a> *hc = dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#cb393f6a676fb106e0e3d35396fb97f9">hc_ptr_array</a>[i];
+<a name="l00665"></a>00665 
+<a name="l00666"></a>00666 #ifdef DEBUG
+<a name="l00667"></a>00667                 if (dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;hc_xfer_timer[i]) {
+<a name="l00668"></a>00668                         DWC_TIMER_FREE(dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;hc_xfer_timer[i]);
+<a name="l00669"></a>00669                 }
+<a name="l00670"></a>00670 <span class="preprocessor">#endif</span>
+<a name="l00671"></a>00671 <span class="preprocessor"></span>                <span class="keywordflow">if</span> (hc != NULL) {
+<a name="l00672"></a>00672                         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"HCD Free channel #%i, hc=%p\n"</span>,
+<a name="l00673"></a>00673                                     i, hc);
+<a name="l00674"></a>00674                         dwc_free(hc);
+<a name="l00675"></a>00675                 }
+<a name="l00676"></a>00676         }
+<a name="l00677"></a>00677 
+<a name="l00678"></a>00678         <span class="keywordflow">if</span> (<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>-&gt;core_if-&gt;dma_enable) {
+<a name="l00679"></a>00679                 <span class="keywordflow">if</span> (<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>-&gt;status_buf_dma) {
+<a name="l00680"></a>00680                         dwc_dma_free(<a class="code" href="dwc__otg__hcd_8h.html#d8ae8e24a91bb0b076390e96a8abee18">DWC_OTG_HCD_STATUS_BUF_SIZE</a>,
+<a name="l00681"></a>00681                                      <a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>-&gt;status_buf,
+<a name="l00682"></a>00682                                      <a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>-&gt;status_buf_dma);
+<a name="l00683"></a>00683                 }
+<a name="l00684"></a>00684         } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>-&gt;status_buf != NULL) {
+<a name="l00685"></a>00685                 dwc_free(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>-&gt;status_buf);
+<a name="l00686"></a>00686         }
+<a name="l00687"></a>00687         DWC_SPINLOCK_FREE(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>-&gt;lock);
+<a name="l00688"></a>00688         DWC_TIMER_FREE(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>-&gt;conn_timer);
+<a name="l00689"></a>00689         DWC_TASK_FREE(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>-&gt;reset_tasklet);
+<a name="l00690"></a>00690         dwc_free(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>);
+<a name="l00691"></a>00691 }
+<a name="l00692"></a>00692 
+<a name="l00693"></a><a class="code" href="dwc__otg__hcd__if_8h.html#2d38590dadee51fd767d63e0dc675f23">00693</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd_8c.html#2d38590dadee51fd767d63e0dc675f23">dwc_otg_hcd_init</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd, <a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * <a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>)
+<a name="l00694"></a>00694 {
+<a name="l00695"></a>00695         <span class="keywordtype">int</span> retval = 0;
+<a name="l00696"></a>00696         <span class="keywordtype">int</span> num_channels;
+<a name="l00697"></a>00697         <span class="keywordtype">int</span> i;
+<a name="l00698"></a>00698         <a class="code" href="structdwc__hc.html">dwc_hc_t</a> *channel;
+<a name="l00699"></a>00699 
+<a name="l00700"></a>00700         hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#34f29e9c035009476495f7701c1813fd">lock</a> = DWC_SPINLOCK_ALLOC();
+<a name="l00701"></a>00701 
+<a name="l00702"></a>00702         hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a> = <a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>;
+<a name="l00703"></a>00703         <span class="comment">/* Register the HCD CIL Callbacks */</span>
+<a name="l00704"></a>00704         <a class="code" href="dwc__otg__cil_8c.html#97c9b9d68211477e486848203def0d0f">dwc_otg_cil_register_hcd_callbacks</a>(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>,
+<a name="l00705"></a>00705                                            &amp;<a class="code" href="dwc__otg__hcd_8c.html#106ff6cbb1499325ea75f2d97abb8e6a">hcd_cil_callbacks</a>, hcd);
+<a name="l00706"></a>00706 
+<a name="l00707"></a>00707         <span class="comment">/* Initialize the non-periodic schedule. */</span>
+<a name="l00708"></a>00708         DWC_LIST_INIT(&amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#64c96c47a36d71bad6e4360cec9d07ad">non_periodic_sched_inactive</a>);
+<a name="l00709"></a>00709         DWC_LIST_INIT(&amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#ffa3041ad517da9519aa2159cdec3f61">non_periodic_sched_active</a>);
+<a name="l00710"></a>00710 
+<a name="l00711"></a>00711         <span class="comment">/* Initialize the periodic schedule. */</span>
+<a name="l00712"></a>00712         DWC_LIST_INIT(&amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#2a747cacd6bdbacbef86d4157c34a312">periodic_sched_inactive</a>);
+<a name="l00713"></a>00713         DWC_LIST_INIT(&amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#74b089e094911a558f7b5f24681d3242">periodic_sched_ready</a>);
+<a name="l00714"></a>00714         DWC_LIST_INIT(&amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#4b8deae798f771135c4a99693b26873f">periodic_sched_assigned</a>);
+<a name="l00715"></a>00715         DWC_LIST_INIT(&amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e127912880eb487b3a2f38778c0de238">periodic_sched_queued</a>);
+<a name="l00716"></a>00716 
+<a name="l00717"></a>00717         <span class="comment">/*</span>
+<a name="l00718"></a>00718 <span class="comment">         * Create a host channel descriptor for each host channel implemented</span>
+<a name="l00719"></a>00719 <span class="comment">         * in the controller. Initialize the channel descriptor array.</span>
+<a name="l00720"></a>00720 <span class="comment">         */</span>
+<a name="l00721"></a>00721         DWC_CIRCLEQ_INIT(&amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#1761f2e6b8f6ba82c0e0c4e561813f0f">free_hc_list</a>);
+<a name="l00722"></a>00722         num_channels = hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#c1b433c6965aa7d48f6ca6818c592039">host_channels</a>;
+<a name="l00723"></a>00723         DWC_MEMSET(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#cb393f6a676fb106e0e3d35396fb97f9">hc_ptr_array</a>, 0, <span class="keyword">sizeof</span>(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#cb393f6a676fb106e0e3d35396fb97f9">hc_ptr_array</a>));
+<a name="l00724"></a>00724         <span class="keywordflow">for</span> (i = 0; i &lt; num_channels; i++) {
+<a name="l00725"></a>00725                 channel = dwc_alloc(<span class="keyword">sizeof</span>(<a class="code" href="structdwc__hc.html">dwc_hc_t</a>));
+<a name="l00726"></a>00726                 <span class="keywordflow">if</span> (channel == NULL) {
+<a name="l00727"></a>00727                         retval = -DWC_E_NO_MEMORY;
+<a name="l00728"></a>00728                         DWC_ERROR(<span class="stringliteral">"%s: host channel allocation failed\n"</span>,
+<a name="l00729"></a>00729                                   __func__);
+<a name="l00730"></a>00730                         <a class="code" href="dwc__otg__hcd_8c.html#7ee877a9be0c15bacbb92a7babb116d0">dwc_otg_hcd_free</a>(hcd);
+<a name="l00731"></a>00731                         <span class="keywordflow">goto</span> out;
+<a name="l00732"></a>00732                 }
+<a name="l00733"></a>00733                 channel-&gt;<a class="code" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">hc_num</a> = i;
+<a name="l00734"></a>00734                 hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#cb393f6a676fb106e0e3d35396fb97f9">hc_ptr_array</a>[i] = channel;
+<a name="l00735"></a>00735 <span class="preprocessor">#ifdef DEBUG</span>
+<a name="l00736"></a>00736 <span class="preprocessor"></span>                hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;hc_xfer_timer[i] =
+<a name="l00737"></a>00737                     DWC_TIMER_ALLOC(<span class="stringliteral">"hc timer"</span>, hc_xfer_timeout,
+<a name="l00738"></a>00738                                     &amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;hc_xfer_info[i]);
+<a name="l00739"></a>00739 <span class="preprocessor">#endif</span>
+<a name="l00740"></a>00740 <span class="preprocessor"></span>                <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"HCD Added channel #%d, hc=%p\n"</span>, i,
+<a name="l00741"></a>00741                             channel);
+<a name="l00742"></a>00742         }
+<a name="l00743"></a>00743 
+<a name="l00744"></a>00744         <span class="comment">/* Initialize the Connection timeout timer. */</span>
+<a name="l00745"></a>00745         hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#de7796a41bb7d1e45ed9dbc20c995342">conn_timer</a> = DWC_TIMER_ALLOC(<span class="stringliteral">"Connection timer"</span>,
+<a name="l00746"></a>00746                                           <a class="code" href="dwc__otg__hcd_8c.html#4f6f55c20aa8eb215d692195f9f0280d">dwc_otg_hcd_connect_timeout</a>, 0);
+<a name="l00747"></a>00747 
+<a name="l00748"></a>00748         <span class="comment">/* Initialize reset tasklet. */</span>
+<a name="l00749"></a>00749         hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#4f2b2c551e4ac9f49afcbdbde1ddf55d">reset_tasklet</a> = DWC_TASK_ALLOC(<a class="code" href="dwc__otg__hcd_8c.html#ed4640393d701e9bbfd966d4006a60b8">reset_tasklet_func</a>, hcd);
+<a name="l00750"></a>00750 
+<a name="l00751"></a>00751         <span class="comment">/*</span>
+<a name="l00752"></a>00752 <span class="comment">         * Allocate space for storing data on status transactions. Normally no</span>
+<a name="l00753"></a>00753 <span class="comment">         * data is sent, but this space acts as a bit bucket. This must be</span>
+<a name="l00754"></a>00754 <span class="comment">         * done after usb_add_hcd since that function allocates the DMA buffer</span>
+<a name="l00755"></a>00755 <span class="comment">         * pool.</span>
+<a name="l00756"></a>00756 <span class="comment">         */</span>
+<a name="l00757"></a>00757         <span class="keywordflow">if</span> (hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a>) {
+<a name="l00758"></a>00758                 hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#68627912f0d3672096e6a98be38f66ab">status_buf</a> =
+<a name="l00759"></a>00759                     dwc_dma_alloc(<a class="code" href="dwc__otg__hcd_8h.html#d8ae8e24a91bb0b076390e96a8abee18">DWC_OTG_HCD_STATUS_BUF_SIZE</a>,
+<a name="l00760"></a>00760                                   &amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#3e752b2c5d632d848f3b1fadf543e7a4">status_buf_dma</a>);
+<a name="l00761"></a>00761         } <span class="keywordflow">else</span> {
+<a name="l00762"></a>00762                 hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#68627912f0d3672096e6a98be38f66ab">status_buf</a> = dwc_alloc(<a class="code" href="dwc__otg__hcd_8h.html#d8ae8e24a91bb0b076390e96a8abee18">DWC_OTG_HCD_STATUS_BUF_SIZE</a>);
+<a name="l00763"></a>00763         }
+<a name="l00764"></a>00764         <span class="keywordflow">if</span> (!hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#68627912f0d3672096e6a98be38f66ab">status_buf</a>) {
+<a name="l00765"></a>00765                 retval = -DWC_E_NO_MEMORY;
+<a name="l00766"></a>00766                 DWC_ERROR(<span class="stringliteral">"%s: status_buf allocation failed\n"</span>, __func__);
+<a name="l00767"></a>00767                 <a class="code" href="dwc__otg__hcd_8c.html#7ee877a9be0c15bacbb92a7babb116d0">dwc_otg_hcd_free</a>(hcd);
+<a name="l00768"></a>00768                 <span class="keywordflow">goto</span> out;
+<a name="l00769"></a>00769         }
+<a name="l00770"></a>00770 
+<a name="l00771"></a>00771         hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#9231b4c3dce89a1506a5e501ec5c7a39">otg_port</a> = 1;
+<a name="l00772"></a>00772         hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#77f16d5530f50556ed01fe7f69a135fd">frame_list</a> = NULL;
+<a name="l00773"></a>00773         hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#3421063dcac9d4e200b5d9bbb0508f3d">frame_list_dma</a> = 0;
+<a name="l00774"></a>00774 out:
+<a name="l00775"></a>00775         <span class="keywordflow">return</span> retval;
+<a name="l00776"></a>00776 }
+<a name="l00777"></a>00777 
+<a name="l00778"></a><a class="code" href="dwc__otg__hcd__if_8h.html#f347bcb363a622ced29161878d38830b">00778</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd_8c.html#f347bcb363a622ced29161878d38830b">dwc_otg_hcd_remove</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd)
+<a name="l00779"></a>00779 {
+<a name="l00780"></a>00780         <span class="comment">/* Turn off all host-specific interrupts. */</span>
+<a name="l00781"></a>00781         <a class="code" href="dwc__otg__cil_8c.html#4dd4a30dd75a819e9da38d6410cbb0a4">dwc_otg_disable_host_interrupts</a>(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>);
+<a name="l00782"></a>00782 
+<a name="l00783"></a>00783         <a class="code" href="dwc__otg__hcd_8c.html#7ee877a9be0c15bacbb92a7babb116d0">dwc_otg_hcd_free</a>(hcd);
+<a name="l00784"></a>00784 }
+<a name="l00785"></a>00785 
+<a name="l00789"></a><a class="code" href="dwc__otg__hcd_8c.html#a9b6729ba2077bed1b6d149970d5525e">00789</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd_8c.html#a9b6729ba2077bed1b6d149970d5525e">dwc_otg_hcd_reinit</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd)
+<a name="l00790"></a>00790 {
+<a name="l00791"></a>00791         <span class="keywordtype">int</span> num_channels;
+<a name="l00792"></a>00792         <span class="keywordtype">int</span> i;
+<a name="l00793"></a>00793         <a class="code" href="structdwc__hc.html">dwc_hc_t</a> *channel;
+<a name="l00794"></a>00794         <a class="code" href="structdwc__hc.html">dwc_hc_t</a> *channel_tmp;
+<a name="l00795"></a>00795 
+<a name="l00796"></a>00796         hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#9aaf2a112f5794f92dedd826342bd637">flags</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#95ad2033c30d79c28ffcfa6df44af1d5">d32</a> = 0;
+<a name="l00797"></a>00797 
+<a name="l00798"></a>00798         hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#01ab5791d6269b6b5d506f2113b94231">non_periodic_qh_ptr</a> = &amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#ffa3041ad517da9519aa2159cdec3f61">non_periodic_sched_active</a>;
+<a name="l00799"></a>00799         hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e7fff26b5cce7c6c520c89f9e3c75617">non_periodic_channels</a> = 0;
+<a name="l00800"></a>00800         hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#5754b87bd4644fbb7b90cf843c638f1c">periodic_channels</a> = 0;
+<a name="l00801"></a>00801 
+<a name="l00802"></a>00802         <span class="comment">/*</span>
+<a name="l00803"></a>00803 <span class="comment">         * Put all channels in the free channel list and clean up channel</span>
+<a name="l00804"></a>00804 <span class="comment">         * states.</span>
+<a name="l00805"></a>00805 <span class="comment">         */</span>
+<a name="l00806"></a>00806         DWC_CIRCLEQ_FOREACH_SAFE(channel, channel_tmp,
+<a name="l00807"></a>00807                                  &amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#1761f2e6b8f6ba82c0e0c4e561813f0f">free_hc_list</a>, hc_list_entry) {
+<a name="l00808"></a>00808                 DWC_CIRCLEQ_REMOVE(&amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#1761f2e6b8f6ba82c0e0c4e561813f0f">free_hc_list</a>, channel, hc_list_entry);
+<a name="l00809"></a>00809         }
+<a name="l00810"></a>00810 
+<a name="l00811"></a>00811         num_channels = hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#c1b433c6965aa7d48f6ca6818c592039">host_channels</a>;
+<a name="l00812"></a>00812         <span class="keywordflow">for</span> (i = 0; i &lt; num_channels; i++) {
+<a name="l00813"></a>00813                 channel = hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#cb393f6a676fb106e0e3d35396fb97f9">hc_ptr_array</a>[i];
+<a name="l00814"></a>00814                 DWC_CIRCLEQ_INSERT_TAIL(&amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#1761f2e6b8f6ba82c0e0c4e561813f0f">free_hc_list</a>, channel,
+<a name="l00815"></a>00815                                         hc_list_entry);
+<a name="l00816"></a>00816                 <a class="code" href="dwc__otg__cil_8c.html#f05341f811fba7f6183db66faf50a867">dwc_otg_hc_cleanup</a>(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>, channel);
+<a name="l00817"></a>00817         }
+<a name="l00818"></a>00818 
+<a name="l00819"></a>00819         <span class="comment">/* Initialize the DWC core for host mode operation. */</span>
+<a name="l00820"></a>00820         <a class="code" href="dwc__otg__cil_8c.html#04ad276f20faad71333f6293c952744e">dwc_otg_core_host_init</a>(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>);
+<a name="l00821"></a>00821 }
+<a name="l00822"></a>00822 
+<a name="l00832"></a><a class="code" href="dwc__otg__hcd_8c.html#08cefee3729196462fe6a7608046652c">00832</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd_8c.html#08cefee3729196462fe6a7608046652c">assign_and_init_hc</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd, <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> * qh)
+<a name="l00833"></a>00833 {
+<a name="l00834"></a>00834         <a class="code" href="structdwc__hc.html">dwc_hc_t</a> *hc;
+<a name="l00835"></a>00835         <a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *qtd;
+<a name="l00836"></a>00836         <a class="code" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *urb;
+<a name="l00837"></a>00837         <span class="keywordtype">void</span>* ptr = NULL;
+<a name="l00838"></a>00838 
+<a name="l00839"></a>00839         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"%s(%p,%p)\n"</span>, __func__, hcd, qh);
+<a name="l00840"></a>00840 
+<a name="l00841"></a>00841         hc = DWC_CIRCLEQ_FIRST(&amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#1761f2e6b8f6ba82c0e0c4e561813f0f">free_hc_list</a>);
+<a name="l00842"></a>00842 
+<a name="l00843"></a>00843         <span class="comment">/* Remove the host channel from the free list. */</span>
+<a name="l00844"></a>00844         DWC_CIRCLEQ_REMOVE_INIT(&amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#1761f2e6b8f6ba82c0e0c4e561813f0f">free_hc_list</a>, hc, hc_list_entry);
+<a name="l00845"></a>00845 
+<a name="l00846"></a>00846         qtd = DWC_CIRCLEQ_FIRST(&amp;qh-&gt;<a class="code" href="structdwc__otg__qh.html#9567d266da8e796d3467fb16ae867f8e">qtd_list</a>);
+<a name="l00847"></a>00847         
+<a name="l00848"></a>00848         urb = qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#7e7767808e8eb9d71de0db00f57553f9">urb</a>;
+<a name="l00849"></a>00849         qh-&gt;<a class="code" href="structdwc__otg__qh.html#bbdb7d30b60b6c326301f33b35088bb4">channel</a> = hc;
+<a name="l00850"></a>00850         
+<a name="l00851"></a>00851         qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#c1d73f1d48eeabbdc198ad28c0882bc1">in_process</a> = 1;
+<a name="l00852"></a>00852 
+<a name="l00853"></a>00853         <span class="comment">/*</span>
+<a name="l00854"></a>00854 <span class="comment">         * Use usb_pipedevice to determine device address. This address is</span>
+<a name="l00855"></a>00855 <span class="comment">         * 0 before the SET_ADDRESS command and the correct address afterward.</span>
+<a name="l00856"></a>00856 <span class="comment">         */</span>
+<a name="l00857"></a>00857         hc-&gt;<a class="code" href="structdwc__hc.html#b2c7e8baff70104375f4916e9b76cef7">dev_addr</a> = <a class="code" href="dwc__otg__hcd_8h.html#0de365358ba4472d56c1ac8074ba926b">dwc_otg_hcd_get_dev_addr</a>(&amp;urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#34ee3ac5931687b41dd726f00c558369">pipe_info</a>);
+<a name="l00858"></a>00858         hc-&gt;<a class="code" href="structdwc__hc.html#70b755f76a00b81679aeb1e0db8b2e60">ep_num</a> = <a class="code" href="dwc__otg__hcd_8h.html#367b79057f321cfa65023f4026d6c2c9">dwc_otg_hcd_get_ep_num</a>(&amp;urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#34ee3ac5931687b41dd726f00c558369">pipe_info</a>);
+<a name="l00859"></a>00859         hc-&gt;<a class="code" href="structdwc__hc.html#570b78178975193edb921af1ef36d37b">speed</a> = qh-&gt;<a class="code" href="structdwc__otg__qh.html#42459dd91e199807783000b6dc358a7d">dev_speed</a>;
+<a name="l00860"></a>00860         hc-&gt;<a class="code" href="structdwc__hc.html#bd88f02eb286ba01d8d1b049e8975ccb">max_packet</a> = <a class="code" href="dwc__otg__hcd_8h.html#bd2189f881088fe7f4ca9112ee24549b">dwc_max_packet</a>(qh-&gt;<a class="code" href="structdwc__otg__qh.html#5975c2bede1ca0c6cfe9a66fe0a52567">maxp</a>);
+<a name="l00861"></a>00861 
+<a name="l00862"></a>00862         hc-&gt;<a class="code" href="structdwc__hc.html#78a1cf134604b24bfdedb4f4df9f2c1f">xfer_started</a> = 0;
+<a name="l00863"></a>00863         hc-&gt;<a class="code" href="structdwc__hc.html#07eca0fa02105ddaa1719387f5558b23">halt_status</a> = DWC_OTG_HC_XFER_NO_HALT_STATUS;
+<a name="l00864"></a>00864         hc-&gt;<a class="code" href="structdwc__hc.html#ab0855754930fdc74978fa71772982ed">error_state</a> = (qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#18eeb9c647049aec468bf9a7861c873f">error_count</a> &gt; 0);
+<a name="l00865"></a>00865         hc-&gt;<a class="code" href="structdwc__hc.html#c3b27b33fae73aff43a9834a1ed585da">halt_on_queue</a> = 0;
+<a name="l00866"></a>00866         hc-&gt;<a class="code" href="structdwc__hc.html#2177dcde6dbb17b6bc7d0fb34e8ec95a">halt_pending</a> = 0;
+<a name="l00867"></a>00867         hc-&gt;<a class="code" href="structdwc__hc.html#961e8eae7a18c503e370c4bc513d3e55">requests</a> = 0;
+<a name="l00868"></a>00868 
+<a name="l00869"></a>00869         <span class="comment">/*</span>
+<a name="l00870"></a>00870 <span class="comment">         * The following values may be modified in the transfer type section</span>
+<a name="l00871"></a>00871 <span class="comment">         * below. The xfer_len value may be reduced when the transfer is</span>
+<a name="l00872"></a>00872 <span class="comment">         * started to accommodate the max widths of the XferSize and PktCnt</span>
+<a name="l00873"></a>00873 <span class="comment">         * fields in the HCTSIZn register.</span>
+<a name="l00874"></a>00874 <span class="comment">         */</span>
+<a name="l00875"></a>00875         hc-&gt;<a class="code" href="structdwc__hc.html#ae7184275dbb23b3a5d2af20ed224920">do_ping</a> = qh-&gt;<a class="code" href="structdwc__otg__qh.html#2c115474978a808c797c8975d72e419d">ping_state</a>;
+<a name="l00876"></a>00876         hc-&gt;<a class="code" href="structdwc__hc.html#c5088d431f5efc382121f201f5d571aa">ep_is_in</a> = (<a class="code" href="dwc__otg__hcd_8h.html#68de5629a8b45d9bec58f680fa4c820c">dwc_otg_hcd_is_pipe_in</a>(&amp;urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#34ee3ac5931687b41dd726f00c558369">pipe_info</a>) != 0);
+<a name="l00877"></a>00877         hc-&gt;<a class="code" href="structdwc__hc.html#513427c5e8c4603ba344d4e7f9191064">data_pid_start</a> = qh-&gt;<a class="code" href="structdwc__otg__qh.html#b0e001bfd76f5781926795ac47ef2c25">data_toggle</a>;
+<a name="l00878"></a>00878         hc-&gt;<a class="code" href="structdwc__hc.html#9a01b904f7ccc7178cdb80c20e8a9b0c">multi_count</a> = 1;
+<a name="l00879"></a>00879 
+<a name="l00880"></a>00880         <span class="keywordflow">if</span> (hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a>) {
+<a name="l00881"></a>00881                 hc-&gt;<a class="code" href="structdwc__hc.html#9dc781cb9e4bc639765beee37ce76673">xfer_buff</a> = (uint8_t *) urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#4e177a55239e95ae2f6c8b6b913f67fc">dma</a> + urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#742c8a97d3867ab89148eae34e0c73a6">actual_length</a>;
+<a name="l00882"></a>00882         
+<a name="l00883"></a>00883                 <span class="comment">/* For non-dword aligned case */</span>
+<a name="l00884"></a>00884                 if (((uint32_t)hc-&gt;<a class="code" href="structdwc__hc.html#9dc781cb9e4bc639765beee37ce76673">xfer_buff</a> &amp; 0x3) &amp;&amp; !hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a>) {
+<a name="l00885"></a>00885                         ptr = (uint8_t *) urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#99ae35ffcd6147ddb93b361ab3bcfe95">buf</a> + urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#742c8a97d3867ab89148eae34e0c73a6">actual_length</a>;
+<a name="l00886"></a>00886                 }
+<a name="l00887"></a>00887         } <span class="keywordflow">else</span> {
+<a name="l00888"></a>00888                 hc-&gt;<a class="code" href="structdwc__hc.html#9dc781cb9e4bc639765beee37ce76673">xfer_buff</a> = (uint8_t *) urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#99ae35ffcd6147ddb93b361ab3bcfe95">buf</a> + urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#742c8a97d3867ab89148eae34e0c73a6">actual_length</a>;
+<a name="l00889"></a>00889         }
+<a name="l00890"></a>00890         hc-&gt;<a class="code" href="structdwc__hc.html#ce32fe93214f1686896e924fbf61cac7">xfer_len</a> = urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#dca57de4fdecd894241ce24167206a45">length</a> - urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#742c8a97d3867ab89148eae34e0c73a6">actual_length</a>;
+<a name="l00891"></a>00891         hc-&gt;<a class="code" href="structdwc__hc.html#6199aaeab2d64954311c410b30270293">xfer_count</a> = 0;
+<a name="l00892"></a>00892 
+<a name="l00893"></a>00893         <span class="comment">/*</span>
+<a name="l00894"></a>00894 <span class="comment">         * Set the split attributes</span>
+<a name="l00895"></a>00895 <span class="comment">         */</span>
+<a name="l00896"></a>00896         hc-&gt;<a class="code" href="structdwc__hc.html#4365ef67d517a621a626ac5392545c6d">do_split</a> = 0;
+<a name="l00897"></a>00897         <span class="keywordflow">if</span> (qh-&gt;<a class="code" href="structdwc__otg__qh.html#8708dd009988ce20b8a8d52a4a96c5a3">do_split</a>) {
+<a name="l00898"></a>00898                 uint32_t hub_addr, port_addr;
+<a name="l00899"></a>00899                 hc-&gt;<a class="code" href="structdwc__hc.html#4365ef67d517a621a626ac5392545c6d">do_split</a> = 1;
+<a name="l00900"></a>00900                 hc-&gt;<a class="code" href="structdwc__hc.html#3cde49a724756e16eb11a027360b2d4b">xact_pos</a> = qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#ab224d64d72f2ef4f10e722ebcfa29a6">isoc_split_pos</a>;
+<a name="l00901"></a>00901                 hc-&gt;<a class="code" href="structdwc__hc.html#21e00df6fb9a555975879526118d599e">complete_split</a> = qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#6355e968a4d36edce3e22c89ac7b5001">complete_split</a>;
+<a name="l00902"></a>00902                 hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#ffefbd33a59a14b8b46406f5aaeaa2f4">fops</a>-&gt;<a class="code" href="structdwc__otg__hcd__function__ops.html#71bff93886173700d26a8950e7ea82e1">hub_info</a>(hcd, urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#5ba0e393ef9768275db85c00e68be477">priv</a>, &amp;hub_addr, &amp;port_addr);
+<a name="l00903"></a>00903                 hc-&gt;<a class="code" href="structdwc__hc.html#19d0302b6e3769eada2466b8e5e0dd91">hub_addr</a> = (uint8_t) hub_addr;
+<a name="l00904"></a>00904                 hc-&gt;<a class="code" href="structdwc__hc.html#9f597e05c37d7292f4c0d965c67ee3dd">port_addr</a> = (uint8_t) port_addr;
+<a name="l00905"></a>00905         }
+<a name="l00906"></a>00906 
+<a name="l00907"></a>00907         <span class="keywordflow">switch</span> (<a class="code" href="dwc__otg__hcd_8h.html#b97cea598797e69d011ffef89989a739">dwc_otg_hcd_get_pipe_type</a>(&amp;urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#34ee3ac5931687b41dd726f00c558369">pipe_info</a>)) {
+<a name="l00908"></a>00908         <span class="keywordflow">case</span> UE_CONTROL:
+<a name="l00909"></a>00909                 hc-&gt;<a class="code" href="structdwc__hc.html#e6169fbc92e4d79686097742ad646f5c">ep_type</a> = <a class="code" href="dwc__otg__cil_8h.html#64e5cd756330f5adab79b25cc8067bdc">DWC_OTG_EP_TYPE_CONTROL</a>;
+<a name="l00910"></a>00910                 <span class="keywordflow">switch</span> (qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#5189ec9c992974d20477481eaf96d0bb">control_phase</a>) {
+<a name="l00911"></a>00911                 <span class="keywordflow">case</span> DWC_OTG_CONTROL_SETUP:
+<a name="l00912"></a>00912                         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"  Control setup transaction\n"</span>);
+<a name="l00913"></a>00913                         hc-&gt;<a class="code" href="structdwc__hc.html#ae7184275dbb23b3a5d2af20ed224920">do_ping</a> = 0;
+<a name="l00914"></a>00914                         hc-&gt;<a class="code" href="structdwc__hc.html#c5088d431f5efc382121f201f5d571aa">ep_is_in</a> = 0;
+<a name="l00915"></a>00915                         hc-&gt;<a class="code" href="structdwc__hc.html#513427c5e8c4603ba344d4e7f9191064">data_pid_start</a> = <a class="code" href="dwc__otg__cil_8h.html#8d329f92a5ff6f9a72fc755b6b1a4e17">DWC_OTG_HC_PID_SETUP</a>;
+<a name="l00916"></a>00916                         <span class="keywordflow">if</span> (hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a>) {
+<a name="l00917"></a>00917                                 hc-&gt;<a class="code" href="structdwc__hc.html#9dc781cb9e4bc639765beee37ce76673">xfer_buff</a> = (uint8_t *) urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#497f61f9b3f6f77f6b844e31c047264d">setup_dma</a>;
+<a name="l00918"></a>00918                         } <span class="keywordflow">else</span> {
+<a name="l00919"></a>00919                                 hc-&gt;<a class="code" href="structdwc__hc.html#9dc781cb9e4bc639765beee37ce76673">xfer_buff</a> = (uint8_t *) urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#254afd954f3e24bb92841384183a317c">setup_packet</a>;
+<a name="l00920"></a>00920                         }
+<a name="l00921"></a>00921                         hc-&gt;<a class="code" href="structdwc__hc.html#ce32fe93214f1686896e924fbf61cac7">xfer_len</a> = 8;
+<a name="l00922"></a>00922                         ptr = NULL;
+<a name="l00923"></a>00923                         <span class="keywordflow">break</span>;
+<a name="l00924"></a>00924                 <span class="keywordflow">case</span> DWC_OTG_CONTROL_DATA:
+<a name="l00925"></a>00925                         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"  Control data transaction\n"</span>);
+<a name="l00926"></a>00926                         hc-&gt;<a class="code" href="structdwc__hc.html#513427c5e8c4603ba344d4e7f9191064">data_pid_start</a> = qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#e912f256e01165b573c26262247a5eff">data_toggle</a>;
+<a name="l00927"></a>00927                         <span class="keywordflow">break</span>;
+<a name="l00928"></a>00928                 <span class="keywordflow">case</span> DWC_OTG_CONTROL_STATUS:
+<a name="l00929"></a>00929                         <span class="comment">/*</span>
+<a name="l00930"></a>00930 <span class="comment">                         * Direction is opposite of data direction or IN if no</span>
+<a name="l00931"></a>00931 <span class="comment">                         * data.</span>
+<a name="l00932"></a>00932 <span class="comment">                         */</span>
+<a name="l00933"></a>00933                         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"  Control status transaction\n"</span>);
+<a name="l00934"></a>00934                         <span class="keywordflow">if</span> (urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#dca57de4fdecd894241ce24167206a45">length</a> == 0) {
+<a name="l00935"></a>00935                                 hc-&gt;<a class="code" href="structdwc__hc.html#c5088d431f5efc382121f201f5d571aa">ep_is_in</a> = 1;
+<a name="l00936"></a>00936                         } <span class="keywordflow">else</span> {
+<a name="l00937"></a>00937                                 hc-&gt;<a class="code" href="structdwc__hc.html#c5088d431f5efc382121f201f5d571aa">ep_is_in</a> =
+<a name="l00938"></a>00938                                     <a class="code" href="dwc__otg__hcd_8h.html#cf3e5e59a22ef6bd497e05710e39cad0">dwc_otg_hcd_is_pipe_out</a>(&amp;urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#34ee3ac5931687b41dd726f00c558369">pipe_info</a>);
+<a name="l00939"></a>00939                         }
+<a name="l00940"></a>00940                         <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#c5088d431f5efc382121f201f5d571aa">ep_is_in</a>) {
+<a name="l00941"></a>00941                                 hc-&gt;<a class="code" href="structdwc__hc.html#ae7184275dbb23b3a5d2af20ed224920">do_ping</a> = 0;
+<a name="l00942"></a>00942                         }
+<a name="l00943"></a>00943                         
+<a name="l00944"></a>00944                         hc-&gt;<a class="code" href="structdwc__hc.html#513427c5e8c4603ba344d4e7f9191064">data_pid_start</a> = <a class="code" href="dwc__otg__cil_8h.html#e623eb446c55928b324e9636111315e1">DWC_OTG_HC_PID_DATA1</a>;
+<a name="l00945"></a>00945 
+<a name="l00946"></a>00946                         hc-&gt;<a class="code" href="structdwc__hc.html#ce32fe93214f1686896e924fbf61cac7">xfer_len</a> = 0;
+<a name="l00947"></a>00947                         <span class="keywordflow">if</span> (hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a>) {
+<a name="l00948"></a>00948                                 hc-&gt;<a class="code" href="structdwc__hc.html#9dc781cb9e4bc639765beee37ce76673">xfer_buff</a> = (uint8_t *) hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#3e752b2c5d632d848f3b1fadf543e7a4">status_buf_dma</a>;
+<a name="l00949"></a>00949                         } <span class="keywordflow">else</span> {
+<a name="l00950"></a>00950                                 hc-&gt;<a class="code" href="structdwc__hc.html#9dc781cb9e4bc639765beee37ce76673">xfer_buff</a> = (uint8_t *) hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#68627912f0d3672096e6a98be38f66ab">status_buf</a>;
+<a name="l00951"></a>00951                         }
+<a name="l00952"></a>00952                         ptr = NULL;
+<a name="l00953"></a>00953                         <span class="keywordflow">break</span>;
+<a name="l00954"></a>00954                 }
+<a name="l00955"></a>00955                 <span class="keywordflow">break</span>;
+<a name="l00956"></a>00956         <span class="keywordflow">case</span> UE_BULK:
+<a name="l00957"></a>00957                 hc-&gt;<a class="code" href="structdwc__hc.html#e6169fbc92e4d79686097742ad646f5c">ep_type</a> = <a class="code" href="dwc__otg__cil_8h.html#9b079858cda0b917316ad9161b3881e0">DWC_OTG_EP_TYPE_BULK</a>;
+<a name="l00958"></a>00958                 <span class="keywordflow">break</span>;
+<a name="l00959"></a>00959         <span class="keywordflow">case</span> UE_INTERRUPT:
+<a name="l00960"></a>00960                 hc-&gt;<a class="code" href="structdwc__hc.html#e6169fbc92e4d79686097742ad646f5c">ep_type</a> = <a class="code" href="dwc__otg__cil_8h.html#1401d1264f88530232cf51ab31cc5347">DWC_OTG_EP_TYPE_INTR</a>;
+<a name="l00961"></a>00961                 <span class="keywordflow">break</span>;
+<a name="l00962"></a>00962         <span class="keywordflow">case</span> UE_ISOCHRONOUS:
+<a name="l00963"></a>00963                 {
+<a name="l00964"></a>00964                         <span class="keyword">struct </span><a class="code" href="structdwc__otg__hcd__iso__packet__desc.html">dwc_otg_hcd_iso_packet_desc</a> *frame_desc;
+<a name="l00965"></a>00965                         
+<a name="l00966"></a>00966                         hc-&gt;<a class="code" href="structdwc__hc.html#e6169fbc92e4d79686097742ad646f5c">ep_type</a> = <a class="code" href="dwc__otg__cil_8h.html#152a3a5e1433bd2197672f0b5105e7a4">DWC_OTG_EP_TYPE_ISOC</a>;
+<a name="l00967"></a>00967                         
+<a name="l00968"></a>00968                         <span class="keywordflow">if</span> (hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a>)
+<a name="l00969"></a>00969                                 <span class="keywordflow">break</span>;
+<a name="l00970"></a>00970                                 
+<a name="l00971"></a>00971                         frame_desc = &amp;urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#ed542f6a2d99dba2f6b71b0d8012ec8a">iso_descs</a>[qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#c67d5f885976d0698f20d113d32b4b30">isoc_frame_index</a>];
+<a name="l00972"></a>00972                         
+<a name="l00973"></a>00973                         frame_desc-&gt;<a class="code" href="structdwc__otg__hcd__iso__packet__desc.html#d070772c24621c47b49ad21c6acadb94">status</a> = 0;
+<a name="l00974"></a>00974                         
+<a name="l00975"></a>00975                         <span class="keywordflow">if</span> (hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a>) {
+<a name="l00976"></a>00976                                 hc-&gt;<a class="code" href="structdwc__hc.html#9dc781cb9e4bc639765beee37ce76673">xfer_buff</a> = (uint8_t *) urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#4e177a55239e95ae2f6c8b6b913f67fc">dma</a>;
+<a name="l00977"></a>00977                         } <span class="keywordflow">else</span> {
+<a name="l00978"></a>00978                                 hc-&gt;<a class="code" href="structdwc__hc.html#9dc781cb9e4bc639765beee37ce76673">xfer_buff</a> = (uint8_t *) urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#99ae35ffcd6147ddb93b361ab3bcfe95">buf</a>;
+<a name="l00979"></a>00979                         }
+<a name="l00980"></a>00980                         hc-&gt;<a class="code" href="structdwc__hc.html#9dc781cb9e4bc639765beee37ce76673">xfer_buff</a> +=
+<a name="l00981"></a>00981                             frame_desc-&gt;<a class="code" href="structdwc__otg__hcd__iso__packet__desc.html#246f3d147a22cd295c534253593dca4a">offset</a> + qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#839371940a7e34365e2272f3214b7e34">isoc_split_offset</a>;
+<a name="l00982"></a>00982                         hc-&gt;<a class="code" href="structdwc__hc.html#ce32fe93214f1686896e924fbf61cac7">xfer_len</a> =
+<a name="l00983"></a>00983                             frame_desc-&gt;<a class="code" href="structdwc__otg__hcd__iso__packet__desc.html#8392d21b820df0181f4e6dca91234543">length</a> - qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#839371940a7e34365e2272f3214b7e34">isoc_split_offset</a>;
+<a name="l00984"></a>00984 
+<a name="l00985"></a>00985                         <span class="comment">/* For non-dword aligned buffers */</span>
+<a name="l00986"></a>00986                         <span class="keywordflow">if</span> (((uint32_t)hc-&gt;<a class="code" href="structdwc__hc.html#9dc781cb9e4bc639765beee37ce76673">xfer_buff</a> &amp; 0x3) &amp;&amp; hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a>) {
+<a name="l00987"></a>00987                                 ptr = (uint8_t *) urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#99ae35ffcd6147ddb93b361ab3bcfe95">buf</a> + frame_desc-&gt;<a class="code" href="structdwc__otg__hcd__iso__packet__desc.html#246f3d147a22cd295c534253593dca4a">offset</a> + qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#839371940a7e34365e2272f3214b7e34">isoc_split_offset</a>;
+<a name="l00988"></a>00988                         }       
+<a name="l00989"></a>00989                         <span class="keywordflow">else</span>
+<a name="l00990"></a>00990                             ptr = NULL;
+<a name="l00991"></a>00991                         
+<a name="l00992"></a>00992                         <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#3cde49a724756e16eb11a027360b2d4b">xact_pos</a> == <a class="code" href="dwc__otg__regs_8h.html#b8a8f35d8fd73c955cc0403e87cea0c6">DWC_HCSPLIT_XACTPOS_ALL</a>) {
+<a name="l00993"></a>00993                                 <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#ce32fe93214f1686896e924fbf61cac7">xfer_len</a> &lt;= 188) {
+<a name="l00994"></a>00994                                         hc-&gt;<a class="code" href="structdwc__hc.html#3cde49a724756e16eb11a027360b2d4b">xact_pos</a> = <a class="code" href="dwc__otg__regs_8h.html#b8a8f35d8fd73c955cc0403e87cea0c6">DWC_HCSPLIT_XACTPOS_ALL</a>;
+<a name="l00995"></a>00995                                 } <span class="keywordflow">else</span> {
+<a name="l00996"></a>00996                                         hc-&gt;<a class="code" href="structdwc__hc.html#3cde49a724756e16eb11a027360b2d4b">xact_pos</a> =
+<a name="l00997"></a>00997                                             <a class="code" href="dwc__otg__regs_8h.html#c0b856e1a71e0373153d986a3cb5b135">DWC_HCSPLIT_XACTPOS_BEGIN</a>;
+<a name="l00998"></a>00998                                 }
+<a name="l00999"></a>00999                         }
+<a name="l01000"></a>01000                 }
+<a name="l01001"></a>01001                 <span class="keywordflow">break</span>;
+<a name="l01002"></a>01002         }
+<a name="l01003"></a>01003         <span class="comment">/* non DWORD-aligned buffer case */</span>     
+<a name="l01004"></a>01004         <span class="keywordflow">if</span> (ptr) {
+<a name="l01005"></a>01005                 uint32_t buf_size;
+<a name="l01006"></a>01006                 <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#e6169fbc92e4d79686097742ad646f5c">ep_type</a> != <a class="code" href="dwc__otg__cil_8h.html#152a3a5e1433bd2197672f0b5105e7a4">DWC_OTG_EP_TYPE_ISOC</a>) {
+<a name="l01007"></a>01007                         buf_size = hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#e614d1d2ee740cd972ca76ed0dffec74">max_transfer_size</a>;
+<a name="l01008"></a>01008                 } <span class="keywordflow">else</span> {                                
+<a name="l01009"></a>01009                         buf_size = 4096;
+<a name="l01010"></a>01010                 }
+<a name="l01011"></a>01011                 <span class="keywordflow">if</span> (!qh-&gt;<a class="code" href="structdwc__otg__qh.html#aac9f90a6afd9056dce79d013dd2168b">dw_align_buf</a>) {
+<a name="l01012"></a>01012                         qh-&gt;<a class="code" href="structdwc__otg__qh.html#aac9f90a6afd9056dce79d013dd2168b">dw_align_buf</a> = dwc_dma_alloc(buf_size,
+<a name="l01013"></a>01013                                                          &amp;qh-&gt;<a class="code" href="structdwc__otg__qh.html#b0b008f9d25f5e3b6e285d2830cfdca1">dw_align_buf_dma</a>);
+<a name="l01014"></a>01014                         <span class="keywordflow">if</span> (!qh-&gt;<a class="code" href="structdwc__otg__qh.html#aac9f90a6afd9056dce79d013dd2168b">dw_align_buf</a>) {
+<a name="l01015"></a>01015                                 DWC_ERROR(<span class="stringliteral">"%s: Failed to allocate memory to handle "</span>
+<a name="l01016"></a>01016                                           <span class="stringliteral">"non-dword aligned buffer case\n"</span>, __func__);
+<a name="l01017"></a>01017                                 <span class="keywordflow">return</span>;
+<a name="l01018"></a>01018                         }
+<a name="l01019"></a>01019                 }
+<a name="l01020"></a>01020                 <span class="keywordflow">if</span> (!hc-&gt;<a class="code" href="structdwc__hc.html#c5088d431f5efc382121f201f5d571aa">ep_is_in</a>) {
+<a name="l01021"></a>01021                         dwc_memcpy(qh-&gt;<a class="code" href="structdwc__otg__qh.html#aac9f90a6afd9056dce79d013dd2168b">dw_align_buf</a>, ptr, hc-&gt;<a class="code" href="structdwc__hc.html#ce32fe93214f1686896e924fbf61cac7">xfer_len</a>);
+<a name="l01022"></a>01022                 }
+<a name="l01023"></a>01023                 hc-&gt;<a class="code" href="structdwc__hc.html#e0c3ba51a04b36656baa4e70fc63cf77">align_buff</a> = qh-&gt;<a class="code" href="structdwc__otg__qh.html#b0b008f9d25f5e3b6e285d2830cfdca1">dw_align_buf_dma</a>;
+<a name="l01024"></a>01024         }
+<a name="l01025"></a>01025         <span class="keywordflow">else</span> {
+<a name="l01026"></a>01026                 hc-&gt;<a class="code" href="structdwc__hc.html#e0c3ba51a04b36656baa4e70fc63cf77">align_buff</a> = 0;
+<a name="l01027"></a>01027         }
+<a name="l01028"></a>01028 
+<a name="l01029"></a>01029         <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#e6169fbc92e4d79686097742ad646f5c">ep_type</a> == <a class="code" href="dwc__otg__cil_8h.html#1401d1264f88530232cf51ab31cc5347">DWC_OTG_EP_TYPE_INTR</a> ||
+<a name="l01030"></a>01030             hc-&gt;<a class="code" href="structdwc__hc.html#e6169fbc92e4d79686097742ad646f5c">ep_type</a> == <a class="code" href="dwc__otg__cil_8h.html#152a3a5e1433bd2197672f0b5105e7a4">DWC_OTG_EP_TYPE_ISOC</a>) {
+<a name="l01031"></a>01031                 <span class="comment">/*</span>
+<a name="l01032"></a>01032 <span class="comment">                 * This value may be modified when the transfer is started to</span>
+<a name="l01033"></a>01033 <span class="comment">                 * reflect the actual transfer length.</span>
+<a name="l01034"></a>01034 <span class="comment">                 */</span>
+<a name="l01035"></a>01035                 hc-&gt;<a class="code" href="structdwc__hc.html#9a01b904f7ccc7178cdb80c20e8a9b0c">multi_count</a> = <a class="code" href="dwc__otg__hcd_8h.html#a371dfcb8a66214c8fe226190fc1a323">dwc_hb_mult</a>(qh-&gt;<a class="code" href="structdwc__otg__qh.html#5975c2bede1ca0c6cfe9a66fe0a52567">maxp</a>);
+<a name="l01036"></a>01036         }
+<a name="l01037"></a>01037         
+<a name="l01038"></a>01038         <span class="keywordflow">if</span> (hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a>)
+<a name="l01039"></a>01039                 hc-&gt;<a class="code" href="structdwc__hc.html#f3001addf65df4d3c6a5c685d7637efd">desc_list_addr</a> = qh-&gt;<a class="code" href="structdwc__otg__qh.html#c31412bb35362e77c697352fd4c3eeaf">desc_list_dma</a>;
+<a name="l01040"></a>01040         
+<a name="l01041"></a>01041         <a class="code" href="dwc__otg__cil_8c.html#7b04d5b3b31c79c73d577cfbb231998c">dwc_otg_hc_init</a>(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>, hc);
+<a name="l01042"></a>01042         hc-&gt;<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a> = qh;
+<a name="l01043"></a>01043 }
+<a name="l01044"></a>01044 
+<a name="l01045"></a>01045 
+<a name="l01055"></a><a class="code" href="dwc__otg__hcd_8h.html#96cc299f4f0478187ed7ba49b975ffc3">01055</a> <a class="code" href="dwc__otg__hcd_8h.html#92c49783eebc5bcffa8b8a51c2127be9">dwc_otg_transaction_type_e</a> <a class="code" href="dwc__otg__hcd_8c.html#96cc299f4f0478187ed7ba49b975ffc3">dwc_otg_hcd_select_transactions</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd)
+<a name="l01056"></a>01056 {
+<a name="l01057"></a>01057         dwc_list_link_t *qh_ptr;
+<a name="l01058"></a>01058         <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *qh;
+<a name="l01059"></a>01059         <span class="keywordtype">int</span> num_channels;
+<a name="l01060"></a>01060         <a class="code" href="dwc__otg__hcd_8h.html#92c49783eebc5bcffa8b8a51c2127be9">dwc_otg_transaction_type_e</a> ret_val = DWC_OTG_TRANSACTION_NONE;
+<a name="l01061"></a>01061 
+<a name="l01062"></a>01062 <span class="preprocessor">#ifdef DEBUG_SOF</span>
+<a name="l01063"></a>01063 <span class="preprocessor"></span>        <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#e4a050e176c1c4f556da2b276a8c2b37">DBG_HCD</a>, <span class="stringliteral">"  Select Transactions\n"</span>);
+<a name="l01064"></a>01064 <span class="preprocessor">#endif</span>
+<a name="l01065"></a>01065 <span class="preprocessor"></span>
+<a name="l01066"></a>01066         <span class="comment">/* Process entries in the periodic ready list. */</span>
+<a name="l01067"></a>01067         qh_ptr = DWC_LIST_FIRST(&amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#74b089e094911a558f7b5f24681d3242">periodic_sched_ready</a>);
+<a name="l01068"></a>01068 
+<a name="l01069"></a>01069         <span class="keywordflow">while</span> (qh_ptr != &amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#74b089e094911a558f7b5f24681d3242">periodic_sched_ready</a> &amp;&amp;
+<a name="l01070"></a>01070                !DWC_CIRCLEQ_EMPTY(&amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#1761f2e6b8f6ba82c0e0c4e561813f0f">free_hc_list</a>)) {
+<a name="l01071"></a>01071 
+<a name="l01072"></a>01072                 qh = DWC_LIST_ENTRY(qh_ptr, <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a>, qh_list_entry);
+<a name="l01073"></a>01073                 <a class="code" href="dwc__otg__hcd_8c.html#08cefee3729196462fe6a7608046652c">assign_and_init_hc</a>(hcd, qh);
+<a name="l01074"></a>01074 
+<a name="l01075"></a>01075                 <span class="comment">/*</span>
+<a name="l01076"></a>01076 <span class="comment">                 * Move the QH from the periodic ready schedule to the</span>
+<a name="l01077"></a>01077 <span class="comment">                 * periodic assigned schedule.</span>
+<a name="l01078"></a>01078 <span class="comment">                 */</span>
+<a name="l01079"></a>01079                 qh_ptr = DWC_LIST_NEXT(qh_ptr);
+<a name="l01080"></a>01080                 DWC_LIST_MOVE_HEAD(&amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#4b8deae798f771135c4a99693b26873f">periodic_sched_assigned</a>,
+<a name="l01081"></a>01081                                    &amp;qh-&gt;<a class="code" href="structdwc__otg__qh.html#3e1cb9863dc72139e1832c04244c25ff">qh_list_entry</a>);
+<a name="l01082"></a>01082 
+<a name="l01083"></a>01083                 ret_val = DWC_OTG_TRANSACTION_PERIODIC;
+<a name="l01084"></a>01084         }
+<a name="l01085"></a>01085 
+<a name="l01086"></a>01086         <span class="comment">/*</span>
+<a name="l01087"></a>01087 <span class="comment">         * Process entries in the inactive portion of the non-periodic</span>
+<a name="l01088"></a>01088 <span class="comment">         * schedule. Some free host channels may not be used if they are</span>
+<a name="l01089"></a>01089 <span class="comment">         * reserved for periodic transfers.</span>
+<a name="l01090"></a>01090 <span class="comment">         */</span>
+<a name="l01091"></a>01091         qh_ptr = hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#64c96c47a36d71bad6e4360cec9d07ad">non_periodic_sched_inactive</a>.next;
+<a name="l01092"></a>01092         num_channels = hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#c1b433c6965aa7d48f6ca6818c592039">host_channels</a>;
+<a name="l01093"></a>01093         <span class="keywordflow">while</span> (qh_ptr != &amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#64c96c47a36d71bad6e4360cec9d07ad">non_periodic_sched_inactive</a> &amp;&amp;
+<a name="l01094"></a>01094                (hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e7fff26b5cce7c6c520c89f9e3c75617">non_periodic_channels</a> &lt;
+<a name="l01095"></a>01095                 num_channels - hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#5754b87bd4644fbb7b90cf843c638f1c">periodic_channels</a>) &amp;&amp;
+<a name="l01096"></a>01096                !DWC_CIRCLEQ_EMPTY(&amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#1761f2e6b8f6ba82c0e0c4e561813f0f">free_hc_list</a>)) {
+<a name="l01097"></a>01097 
+<a name="l01098"></a>01098                 qh = DWC_LIST_ENTRY(qh_ptr, <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a>, qh_list_entry);
+<a name="l01099"></a>01099 
+<a name="l01100"></a>01100                 <a class="code" href="dwc__otg__hcd_8c.html#08cefee3729196462fe6a7608046652c">assign_and_init_hc</a>(hcd, qh);
+<a name="l01101"></a>01101 
+<a name="l01102"></a>01102                 <span class="comment">/*</span>
+<a name="l01103"></a>01103 <span class="comment">                 * Move the QH from the non-periodic inactive schedule to the</span>
+<a name="l01104"></a>01104 <span class="comment">                 * non-periodic active schedule.</span>
+<a name="l01105"></a>01105 <span class="comment">                 */</span>
+<a name="l01106"></a>01106                 qh_ptr = DWC_LIST_NEXT(qh_ptr);
+<a name="l01107"></a>01107                 DWC_LIST_MOVE_HEAD(&amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#ffa3041ad517da9519aa2159cdec3f61">non_periodic_sched_active</a>,
+<a name="l01108"></a>01108                                    &amp;qh-&gt;<a class="code" href="structdwc__otg__qh.html#3e1cb9863dc72139e1832c04244c25ff">qh_list_entry</a>);
+<a name="l01109"></a>01109 
+<a name="l01110"></a>01110                 <span class="keywordflow">if</span> (ret_val == DWC_OTG_TRANSACTION_NONE) {
+<a name="l01111"></a>01111                         ret_val = DWC_OTG_TRANSACTION_NON_PERIODIC;
+<a name="l01112"></a>01112                 } <span class="keywordflow">else</span> {
+<a name="l01113"></a>01113                         ret_val = DWC_OTG_TRANSACTION_ALL;
+<a name="l01114"></a>01114                 }
+<a name="l01115"></a>01115 
+<a name="l01116"></a>01116                 hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e7fff26b5cce7c6c520c89f9e3c75617">non_periodic_channels</a>++;
+<a name="l01117"></a>01117         }
+<a name="l01118"></a>01118 
+<a name="l01119"></a>01119         <span class="keywordflow">return</span> ret_val;
+<a name="l01120"></a>01120 }
+<a name="l01139"></a><a class="code" href="dwc__otg__hcd_8c.html#8c7cd2f81cf41dbf3158f49b1d82a4f8">01139</a> <span class="keyword">static</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd_8c.html#8c7cd2f81cf41dbf3158f49b1d82a4f8">queue_transaction</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd,
+<a name="l01140"></a>01140                              <a class="code" href="structdwc__hc.html">dwc_hc_t</a> * hc, uint16_t fifo_dwords_avail)
+<a name="l01141"></a>01141 {
+<a name="l01142"></a>01142         <span class="keywordtype">int</span> retval;
+<a name="l01143"></a>01143 
+<a name="l01144"></a>01144         <span class="keywordflow">if</span> (hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a>) {
+<a name="l01145"></a>01145                 <span class="keywordflow">if</span> (hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a>) {
+<a name="l01146"></a>01146                         <span class="keywordflow">if</span> (!hc-&gt;<a class="code" href="structdwc__hc.html#78a1cf134604b24bfdedb4f4df9f2c1f">xfer_started</a> || (hc-&gt;<a class="code" href="structdwc__hc.html#e6169fbc92e4d79686097742ad646f5c">ep_type</a> == <a class="code" href="dwc__otg__cil_8h.html#152a3a5e1433bd2197672f0b5105e7a4">DWC_OTG_EP_TYPE_ISOC</a>)) {       
+<a name="l01147"></a>01147                                 <a class="code" href="dwc__otg__hcd_8h.html#9b051bad5e81a6b6d74b817c741bfaf3">dwc_otg_hcd_start_xfer_ddma</a>(hcd, hc-&gt;<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>);
+<a name="l01148"></a>01148                                 hc-&gt;<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#2c115474978a808c797c8975d72e419d">ping_state</a> = 0;
+<a name="l01149"></a>01149                         }
+<a name="l01150"></a>01150                 }
+<a name="l01151"></a>01151                 <span class="keywordflow">else</span> <span class="keywordflow">if</span> (!hc-&gt;<a class="code" href="structdwc__hc.html#78a1cf134604b24bfdedb4f4df9f2c1f">xfer_started</a>) {
+<a name="l01152"></a>01152                         <a class="code" href="dwc__otg__cil_8c.html#025af79d6a2255dba4578588be510444">dwc_otg_hc_start_transfer</a>(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>, hc);
+<a name="l01153"></a>01153                         hc-&gt;<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#2c115474978a808c797c8975d72e419d">ping_state</a> = 0;
+<a name="l01154"></a>01154                 }
+<a name="l01155"></a>01155                 retval = 0;
+<a name="l01156"></a>01156         } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#2177dcde6dbb17b6bc7d0fb34e8ec95a">halt_pending</a>) {
+<a name="l01157"></a>01157                 <span class="comment">/* Don't queue a request if the channel has been halted. */</span>
+<a name="l01158"></a>01158                 retval = 0;
+<a name="l01159"></a>01159         } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#c3b27b33fae73aff43a9834a1ed585da">halt_on_queue</a>) {
+<a name="l01160"></a>01160                 <a class="code" href="dwc__otg__cil_8c.html#de044bf6b96c1bac92259a447ae85c0f">dwc_otg_hc_halt</a>(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>, hc, hc-&gt;<a class="code" href="structdwc__hc.html#07eca0fa02105ddaa1719387f5558b23">halt_status</a>);
+<a name="l01161"></a>01161                 retval = 0;
+<a name="l01162"></a>01162         } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#ae7184275dbb23b3a5d2af20ed224920">do_ping</a>) {
+<a name="l01163"></a>01163                 <span class="keywordflow">if</span> (!hc-&gt;<a class="code" href="structdwc__hc.html#78a1cf134604b24bfdedb4f4df9f2c1f">xfer_started</a>) {
+<a name="l01164"></a>01164                         <a class="code" href="dwc__otg__cil_8c.html#025af79d6a2255dba4578588be510444">dwc_otg_hc_start_transfer</a>(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>, hc);
+<a name="l01165"></a>01165                 }
+<a name="l01166"></a>01166                 retval = 0;
+<a name="l01167"></a>01167         } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (!hc-&gt;<a class="code" href="structdwc__hc.html#c5088d431f5efc382121f201f5d571aa">ep_is_in</a> || hc-&gt;<a class="code" href="structdwc__hc.html#513427c5e8c4603ba344d4e7f9191064">data_pid_start</a> == <a class="code" href="dwc__otg__cil_8h.html#8d329f92a5ff6f9a72fc755b6b1a4e17">DWC_OTG_HC_PID_SETUP</a>) {
+<a name="l01168"></a>01168                 <span class="keywordflow">if</span> ((fifo_dwords_avail * 4) &gt;= hc-&gt;<a class="code" href="structdwc__hc.html#bd88f02eb286ba01d8d1b049e8975ccb">max_packet</a>) {
+<a name="l01169"></a>01169                         <span class="keywordflow">if</span> (!hc-&gt;<a class="code" href="structdwc__hc.html#78a1cf134604b24bfdedb4f4df9f2c1f">xfer_started</a>) {
+<a name="l01170"></a>01170                                 <a class="code" href="dwc__otg__cil_8c.html#025af79d6a2255dba4578588be510444">dwc_otg_hc_start_transfer</a>(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>, hc);
+<a name="l01171"></a>01171                                 retval = 1;
+<a name="l01172"></a>01172                         } <span class="keywordflow">else</span> {
+<a name="l01173"></a>01173                                 retval =
+<a name="l01174"></a>01174                                     <a class="code" href="dwc__otg__cil_8c.html#d848c41cdd739edd9271e1e207af9c9c">dwc_otg_hc_continue_transfer</a>(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>,
+<a name="l01175"></a>01175                                                                  hc);
+<a name="l01176"></a>01176                         }
+<a name="l01177"></a>01177                 } <span class="keywordflow">else</span> {
+<a name="l01178"></a>01178                         retval = -1;
+<a name="l01179"></a>01179                 }
+<a name="l01180"></a>01180         } <span class="keywordflow">else</span> {
+<a name="l01181"></a>01181                 <span class="keywordflow">if</span> (!hc-&gt;<a class="code" href="structdwc__hc.html#78a1cf134604b24bfdedb4f4df9f2c1f">xfer_started</a>) {
+<a name="l01182"></a>01182                         <a class="code" href="dwc__otg__cil_8c.html#025af79d6a2255dba4578588be510444">dwc_otg_hc_start_transfer</a>(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>, hc);
+<a name="l01183"></a>01183                         retval = 1;
+<a name="l01184"></a>01184                 } <span class="keywordflow">else</span> {
+<a name="l01185"></a>01185                         retval = <a class="code" href="dwc__otg__cil_8c.html#d848c41cdd739edd9271e1e207af9c9c">dwc_otg_hc_continue_transfer</a>(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>, hc);
+<a name="l01186"></a>01186                 }
+<a name="l01187"></a>01187         }
+<a name="l01188"></a>01188 
+<a name="l01189"></a>01189         <span class="keywordflow">return</span> retval;
+<a name="l01190"></a>01190 }
+<a name="l01191"></a>01191 
+<a name="l01199"></a><a class="code" href="dwc__otg__hcd_8c.html#00876268eb53e5ce91dbedcb026181ec">01199</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd_8c.html#00876268eb53e5ce91dbedcb026181ec">process_periodic_channels</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd)
+<a name="l01200"></a>01200 {
+<a name="l01201"></a>01201         <a class="code" href="unionhptxsts__data.html">hptxsts_data_t</a> tx_status;
+<a name="l01202"></a>01202         dwc_list_link_t *qh_ptr;
+<a name="l01203"></a>01203         <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *qh;
+<a name="l01204"></a>01204         <span class="keywordtype">int</span> <a class="code" href="structdwc__otg__hcd__iso__packet__desc.html#d070772c24621c47b49ad21c6acadb94">status</a>;
+<a name="l01205"></a>01205         <span class="keywordtype">int</span> no_queue_space = 0;
+<a name="l01206"></a>01206         <span class="keywordtype">int</span> no_fifo_space = 0;
+<a name="l01207"></a>01207 
+<a name="l01208"></a>01208         <a class="code" href="structdwc__otg__host__global__regs.html">dwc_otg_host_global_regs_t</a> *host_regs;
+<a name="l01209"></a>01209         host_regs = hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#ff9692c2e10ca2bc7e24f981f25179c2">host_global_regs</a>;
+<a name="l01210"></a>01210 
+<a name="l01211"></a>01211         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"Queue periodic transactions\n"</span>);
+<a name="l01212"></a>01212 <span class="preprocessor">#ifdef DEBUG</span>
+<a name="l01213"></a>01213 <span class="preprocessor"></span>        tx_status.<a class="code" href="unionhptxsts__data.html#b48d41d449d8f71c0b184b38029c26bc">d32</a> = dwc_read_reg32(&amp;host_regs-&gt;<a class="code" href="structdwc__otg__host__global__regs.html#bf1a1528a2e479d86318d49ecd52ee40">hptxsts</a>);
+<a name="l01214"></a>01214         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>,
+<a name="l01215"></a>01215                     <span class="stringliteral">"  P Tx Req Queue Space Avail (before queue): %d\n"</span>,
+<a name="l01216"></a>01216                     tx_status.<a class="code" href="unionhptxsts__data.html#a6839185cc4aeabf771f04f1b2a97ec3">b</a>.<a class="code" href="unionhptxsts__data.html#8139e6eafb7b0bbb3cbafa125d5cd28f">ptxqspcavail</a>);
+<a name="l01217"></a>01217         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"  P Tx FIFO Space Avail (before queue): %d\n"</span>,
+<a name="l01218"></a>01218                     tx_status.<a class="code" href="unionhptxsts__data.html#a6839185cc4aeabf771f04f1b2a97ec3">b</a>.<a class="code" href="unionhptxsts__data.html#0df6fb1f76396da626715d6ffc06dfa8">ptxfspcavail</a>);
+<a name="l01219"></a>01219 <span class="preprocessor">#endif</span>
+<a name="l01220"></a>01220 <span class="preprocessor"></span>
+<a name="l01221"></a>01221         qh_ptr = hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#4b8deae798f771135c4a99693b26873f">periodic_sched_assigned</a>.next;
+<a name="l01222"></a>01222         <span class="keywordflow">while</span> (qh_ptr != &amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#4b8deae798f771135c4a99693b26873f">periodic_sched_assigned</a>) {
+<a name="l01223"></a>01223                 tx_status.<a class="code" href="unionhptxsts__data.html#b48d41d449d8f71c0b184b38029c26bc">d32</a> = dwc_read_reg32(&amp;host_regs-&gt;<a class="code" href="structdwc__otg__host__global__regs.html#bf1a1528a2e479d86318d49ecd52ee40">hptxsts</a>);
+<a name="l01224"></a>01224                 <span class="keywordflow">if</span> (tx_status.<a class="code" href="unionhptxsts__data.html#a6839185cc4aeabf771f04f1b2a97ec3">b</a>.<a class="code" href="unionhptxsts__data.html#8139e6eafb7b0bbb3cbafa125d5cd28f">ptxqspcavail</a> == 0) {
+<a name="l01225"></a>01225                         no_queue_space = 1;
+<a name="l01226"></a>01226                         <span class="keywordflow">break</span>;
+<a name="l01227"></a>01227                 }
+<a name="l01228"></a>01228 
+<a name="l01229"></a>01229                 qh = DWC_LIST_ENTRY(qh_ptr, <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a>, qh_list_entry);
+<a name="l01230"></a>01230 
+<a name="l01231"></a>01231                 <span class="comment">/*</span>
+<a name="l01232"></a>01232 <span class="comment">                 * Set a flag if we're queuing high-bandwidth in slave mode.</span>
+<a name="l01233"></a>01233 <span class="comment">                 * The flag prevents any halts to get into the request queue in</span>
+<a name="l01234"></a>01234 <span class="comment">                 * the middle of multiple high-bandwidth packets getting queued.</span>
+<a name="l01235"></a>01235 <span class="comment">                 */</span>
+<a name="l01236"></a>01236                 <span class="keywordflow">if</span> (!hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a> &amp;&amp; qh-&gt;<a class="code" href="structdwc__otg__qh.html#bbdb7d30b60b6c326301f33b35088bb4">channel</a>-&gt;<a class="code" href="structdwc__hc.html#9a01b904f7ccc7178cdb80c20e8a9b0c">multi_count</a> &gt; 1) {
+<a name="l01237"></a>01237                         hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#5a6a90b40bc80e71d40f107b68f1e84c">queuing_high_bandwidth</a> = 1;
+<a name="l01238"></a>01238                 }
+<a name="l01239"></a>01239                 status =
+<a name="l01240"></a>01240                     <a class="code" href="dwc__otg__hcd_8c.html#8c7cd2f81cf41dbf3158f49b1d82a4f8">queue_transaction</a>(hcd, qh-&gt;<a class="code" href="structdwc__otg__qh.html#bbdb7d30b60b6c326301f33b35088bb4">channel</a>,
+<a name="l01241"></a>01241                                       tx_status.<a class="code" href="unionhptxsts__data.html#a6839185cc4aeabf771f04f1b2a97ec3">b</a>.<a class="code" href="unionhptxsts__data.html#0df6fb1f76396da626715d6ffc06dfa8">ptxfspcavail</a>);
+<a name="l01242"></a>01242                 <span class="keywordflow">if</span> (status &lt; 0) {
+<a name="l01243"></a>01243                         no_fifo_space = 1;
+<a name="l01244"></a>01244                         <span class="keywordflow">break</span>;
+<a name="l01245"></a>01245                 }
+<a name="l01246"></a>01246 
+<a name="l01247"></a>01247                 <span class="comment">/*</span>
+<a name="l01248"></a>01248 <span class="comment">                 * In Slave mode, stay on the current transfer until there is</span>
+<a name="l01249"></a>01249 <span class="comment">                 * nothing more to do or the high-bandwidth request count is</span>
+<a name="l01250"></a>01250 <span class="comment">                 * reached. In DMA mode, only need to queue one request. The</span>
+<a name="l01251"></a>01251 <span class="comment">                 * controller automatically handles multiple packets for</span>
+<a name="l01252"></a>01252 <span class="comment">                 * high-bandwidth transfers.</span>
+<a name="l01253"></a>01253 <span class="comment">                 */</span>
+<a name="l01254"></a>01254                 <span class="keywordflow">if</span> (hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a> || status == 0 ||
+<a name="l01255"></a>01255                     qh-&gt;<a class="code" href="structdwc__otg__qh.html#bbdb7d30b60b6c326301f33b35088bb4">channel</a>-&gt;<a class="code" href="structdwc__hc.html#961e8eae7a18c503e370c4bc513d3e55">requests</a> == qh-&gt;<a class="code" href="structdwc__otg__qh.html#bbdb7d30b60b6c326301f33b35088bb4">channel</a>-&gt;<a class="code" href="structdwc__hc.html#9a01b904f7ccc7178cdb80c20e8a9b0c">multi_count</a>) {
+<a name="l01256"></a>01256                         qh_ptr = qh_ptr-&gt;next;
+<a name="l01257"></a>01257                         <span class="comment">/*</span>
+<a name="l01258"></a>01258 <span class="comment">                         * Move the QH from the periodic assigned schedule to</span>
+<a name="l01259"></a>01259 <span class="comment">                         * the periodic queued schedule.</span>
+<a name="l01260"></a>01260 <span class="comment">                         */</span>
+<a name="l01261"></a>01261                         DWC_LIST_MOVE_HEAD(&amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e127912880eb487b3a2f38778c0de238">periodic_sched_queued</a>,
+<a name="l01262"></a>01262                                            &amp;qh-&gt;<a class="code" href="structdwc__otg__qh.html#3e1cb9863dc72139e1832c04244c25ff">qh_list_entry</a>);
+<a name="l01263"></a>01263 
+<a name="l01264"></a>01264                         <span class="comment">/* done queuing high bandwidth */</span>
+<a name="l01265"></a>01265                         hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#5a6a90b40bc80e71d40f107b68f1e84c">queuing_high_bandwidth</a> = 0;
+<a name="l01266"></a>01266                 }
+<a name="l01267"></a>01267         }
+<a name="l01268"></a>01268 
+<a name="l01269"></a>01269         <span class="keywordflow">if</span> (!hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a>) {
+<a name="l01270"></a>01270                 <a class="code" href="structdwc__otg__core__global__regs.html">dwc_otg_core_global_regs_t</a> *global_regs;
+<a name="l01271"></a>01271                 <a class="code" href="uniongintmsk__data.html">gintmsk_data_t</a> intr_mask = {.d32 = 0 };
+<a name="l01272"></a>01272 
+<a name="l01273"></a>01273                 global_regs = hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>;
+<a name="l01274"></a>01274                 intr_mask.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#3b52444894e041c660c146af2178272f">ptxfempty</a> = 1;
+<a name="l01275"></a>01275 <span class="preprocessor">#ifdef DEBUG</span>
+<a name="l01276"></a>01276 <span class="preprocessor"></span>                tx_status.<a class="code" href="unionhptxsts__data.html#b48d41d449d8f71c0b184b38029c26bc">d32</a> = dwc_read_reg32(&amp;host_regs-&gt;<a class="code" href="structdwc__otg__host__global__regs.html#bf1a1528a2e479d86318d49ecd52ee40">hptxsts</a>);
+<a name="l01277"></a>01277                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>,
+<a name="l01278"></a>01278                             <span class="stringliteral">"  P Tx Req Queue Space Avail (after queue): %d\n"</span>,
+<a name="l01279"></a>01279                             tx_status.<a class="code" href="unionhptxsts__data.html#a6839185cc4aeabf771f04f1b2a97ec3">b</a>.<a class="code" href="unionhptxsts__data.html#8139e6eafb7b0bbb3cbafa125d5cd28f">ptxqspcavail</a>);
+<a name="l01280"></a>01280                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>,
+<a name="l01281"></a>01281                             <span class="stringliteral">"  P Tx FIFO Space Avail (after queue): %d\n"</span>,
+<a name="l01282"></a>01282                             tx_status.<a class="code" href="unionhptxsts__data.html#a6839185cc4aeabf771f04f1b2a97ec3">b</a>.<a class="code" href="unionhptxsts__data.html#0df6fb1f76396da626715d6ffc06dfa8">ptxfspcavail</a>);
+<a name="l01283"></a>01283 <span class="preprocessor">#endif</span>
+<a name="l01284"></a>01284 <span class="preprocessor"></span>                <span class="keywordflow">if</span> (!DWC_LIST_EMPTY(&amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#4b8deae798f771135c4a99693b26873f">periodic_sched_assigned</a>) ||
+<a name="l01285"></a>01285                     no_queue_space || no_fifo_space) {
+<a name="l01286"></a>01286                         <span class="comment">/*</span>
+<a name="l01287"></a>01287 <span class="comment">                         * May need to queue more transactions as the request</span>
+<a name="l01288"></a>01288 <span class="comment">                         * queue or Tx FIFO empties. Enable the periodic Tx</span>
+<a name="l01289"></a>01289 <span class="comment">                         * FIFO empty interrupt. (Always use the half-empty</span>
+<a name="l01290"></a>01290 <span class="comment">                         * level to ensure that new requests are loaded as</span>
+<a name="l01291"></a>01291 <span class="comment">                         * soon as possible.)</span>
+<a name="l01292"></a>01292 <span class="comment">                         */</span>
+<a name="l01293"></a>01293                         dwc_modify_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#48827c76da2c6b18f369e2f2483cc4b6">gintmsk</a>, 0,
+<a name="l01294"></a>01294                                          intr_mask.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a>);
+<a name="l01295"></a>01295                 } <span class="keywordflow">else</span> {
+<a name="l01296"></a>01296                         <span class="comment">/*</span>
+<a name="l01297"></a>01297 <span class="comment">                         * Disable the Tx FIFO empty interrupt since there are</span>
+<a name="l01298"></a>01298 <span class="comment">                         * no more transactions that need to be queued right</span>
+<a name="l01299"></a>01299 <span class="comment">                         * now. This function is called from interrupt</span>
+<a name="l01300"></a>01300 <span class="comment">                         * handlers to queue more transactions as transfer</span>
+<a name="l01301"></a>01301 <span class="comment">                         * states change.</span>
+<a name="l01302"></a>01302 <span class="comment">                         */</span>
+<a name="l01303"></a>01303                         dwc_modify_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#48827c76da2c6b18f369e2f2483cc4b6">gintmsk</a>, intr_mask.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a>,
+<a name="l01304"></a>01304                                          0);
+<a name="l01305"></a>01305                 }
+<a name="l01306"></a>01306         }
+<a name="l01307"></a>01307 }
+<a name="l01308"></a>01308 
+<a name="l01316"></a><a class="code" href="dwc__otg__hcd_8c.html#a3f28e8605fd652c5177962e5dc8b95a">01316</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd_8c.html#a3f28e8605fd652c5177962e5dc8b95a">process_non_periodic_channels</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd)
+<a name="l01317"></a>01317 {
+<a name="l01318"></a>01318         <a class="code" href="uniongnptxsts__data.html">gnptxsts_data_t</a> tx_status;
+<a name="l01319"></a>01319         dwc_list_link_t *orig_qh_ptr;
+<a name="l01320"></a>01320         <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *qh;
+<a name="l01321"></a>01321         <span class="keywordtype">int</span> <a class="code" href="structdwc__otg__hcd__iso__packet__desc.html#d070772c24621c47b49ad21c6acadb94">status</a>;
+<a name="l01322"></a>01322         <span class="keywordtype">int</span> no_queue_space = 0;
+<a name="l01323"></a>01323         <span class="keywordtype">int</span> no_fifo_space = 0;
+<a name="l01324"></a>01324         <span class="keywordtype">int</span> more_to_do = 0;
+<a name="l01325"></a>01325 
+<a name="l01326"></a>01326         <a class="code" href="structdwc__otg__core__global__regs.html">dwc_otg_core_global_regs_t</a> *global_regs =
+<a name="l01327"></a>01327             hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>;
+<a name="l01328"></a>01328 
+<a name="l01329"></a>01329         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"Queue non-periodic transactions\n"</span>);
+<a name="l01330"></a>01330 <span class="preprocessor">#ifdef DEBUG</span>
+<a name="l01331"></a>01331 <span class="preprocessor"></span>        tx_status.<a class="code" href="uniongnptxsts__data.html#a58b5adbe6bd0344c4f585ef6aba4672">d32</a> = dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#57dabea6f6e0bf9e1ee8e94f55b9e465">gnptxsts</a>);
+<a name="l01332"></a>01332         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>,
+<a name="l01333"></a>01333                     <span class="stringliteral">"  NP Tx Req Queue Space Avail (before queue): %d\n"</span>,
+<a name="l01334"></a>01334                     tx_status.<a class="code" href="uniongnptxsts__data.html#be1d1adf7b827616ebbbf6bf564c0738">b</a>.<a class="code" href="uniongnptxsts__data.html#634ffd5e84bc422ddef043574d8f0957">nptxqspcavail</a>);
+<a name="l01335"></a>01335         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"  NP Tx FIFO Space Avail (before queue): %d\n"</span>,
+<a name="l01336"></a>01336                     tx_status.<a class="code" href="uniongnptxsts__data.html#be1d1adf7b827616ebbbf6bf564c0738">b</a>.<a class="code" href="uniongnptxsts__data.html#6c149be246bcf5ca5395f67e67648207">nptxfspcavail</a>);
+<a name="l01337"></a>01337 <span class="preprocessor">#endif</span>
+<a name="l01338"></a>01338 <span class="preprocessor"></span>        <span class="comment">/*</span>
+<a name="l01339"></a>01339 <span class="comment">         * Keep track of the starting point. Skip over the start-of-list</span>
+<a name="l01340"></a>01340 <span class="comment">         * entry.</span>
+<a name="l01341"></a>01341 <span class="comment">         */</span>
+<a name="l01342"></a>01342         <span class="keywordflow">if</span> (hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#01ab5791d6269b6b5d506f2113b94231">non_periodic_qh_ptr</a> == &amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#ffa3041ad517da9519aa2159cdec3f61">non_periodic_sched_active</a>) {
+<a name="l01343"></a>01343                 hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#01ab5791d6269b6b5d506f2113b94231">non_periodic_qh_ptr</a> = hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#01ab5791d6269b6b5d506f2113b94231">non_periodic_qh_ptr</a>-&gt;next;
+<a name="l01344"></a>01344         }
+<a name="l01345"></a>01345         orig_qh_ptr = hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#01ab5791d6269b6b5d506f2113b94231">non_periodic_qh_ptr</a>;
+<a name="l01346"></a>01346 
+<a name="l01347"></a>01347         <span class="comment">/*</span>
+<a name="l01348"></a>01348 <span class="comment">         * Process once through the active list or until no more space is</span>
+<a name="l01349"></a>01349 <span class="comment">         * available in the request queue or the Tx FIFO.</span>
+<a name="l01350"></a>01350 <span class="comment">         */</span>
+<a name="l01351"></a>01351         <span class="keywordflow">do</span> {
+<a name="l01352"></a>01352                 tx_status.<a class="code" href="uniongnptxsts__data.html#a58b5adbe6bd0344c4f585ef6aba4672">d32</a> = dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#57dabea6f6e0bf9e1ee8e94f55b9e465">gnptxsts</a>);
+<a name="l01353"></a>01353                 <span class="keywordflow">if</span> (!hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a> &amp;&amp; tx_status.<a class="code" href="uniongnptxsts__data.html#be1d1adf7b827616ebbbf6bf564c0738">b</a>.<a class="code" href="uniongnptxsts__data.html#634ffd5e84bc422ddef043574d8f0957">nptxqspcavail</a> == 0) {
+<a name="l01354"></a>01354                         no_queue_space = 1;
+<a name="l01355"></a>01355                         <span class="keywordflow">break</span>;
+<a name="l01356"></a>01356                 }
+<a name="l01357"></a>01357 
+<a name="l01358"></a>01358                 qh = DWC_LIST_ENTRY(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#01ab5791d6269b6b5d506f2113b94231">non_periodic_qh_ptr</a>, <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a>,
+<a name="l01359"></a>01359                                     qh_list_entry);
+<a name="l01360"></a>01360                 status =
+<a name="l01361"></a>01361                     <a class="code" href="dwc__otg__hcd_8c.html#8c7cd2f81cf41dbf3158f49b1d82a4f8">queue_transaction</a>(hcd, qh-&gt;<a class="code" href="structdwc__otg__qh.html#bbdb7d30b60b6c326301f33b35088bb4">channel</a>,
+<a name="l01362"></a>01362                                       tx_status.<a class="code" href="uniongnptxsts__data.html#be1d1adf7b827616ebbbf6bf564c0738">b</a>.<a class="code" href="uniongnptxsts__data.html#6c149be246bcf5ca5395f67e67648207">nptxfspcavail</a>);
+<a name="l01363"></a>01363 
+<a name="l01364"></a>01364                 <span class="keywordflow">if</span> (status &gt; 0) {
+<a name="l01365"></a>01365                         more_to_do = 1;
+<a name="l01366"></a>01366                 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (status &lt; 0) {
+<a name="l01367"></a>01367                         no_fifo_space = 1;
+<a name="l01368"></a>01368                         <span class="keywordflow">break</span>;
+<a name="l01369"></a>01369                 }
+<a name="l01370"></a>01370 
+<a name="l01371"></a>01371                 <span class="comment">/* Advance to next QH, skipping start-of-list entry. */</span>
+<a name="l01372"></a>01372                 hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#01ab5791d6269b6b5d506f2113b94231">non_periodic_qh_ptr</a> = hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#01ab5791d6269b6b5d506f2113b94231">non_periodic_qh_ptr</a>-&gt;next;
+<a name="l01373"></a>01373                 <span class="keywordflow">if</span> (hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#01ab5791d6269b6b5d506f2113b94231">non_periodic_qh_ptr</a> == &amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#ffa3041ad517da9519aa2159cdec3f61">non_periodic_sched_active</a>) {
+<a name="l01374"></a>01374                         hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#01ab5791d6269b6b5d506f2113b94231">non_periodic_qh_ptr</a> =
+<a name="l01375"></a>01375                             hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#01ab5791d6269b6b5d506f2113b94231">non_periodic_qh_ptr</a>-&gt;next;
+<a name="l01376"></a>01376                 }
+<a name="l01377"></a>01377 
+<a name="l01378"></a>01378         } <span class="keywordflow">while</span> (hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#01ab5791d6269b6b5d506f2113b94231">non_periodic_qh_ptr</a> != orig_qh_ptr);
+<a name="l01379"></a>01379 
+<a name="l01380"></a>01380         <span class="keywordflow">if</span> (!hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a>) {
+<a name="l01381"></a>01381                 <a class="code" href="uniongintmsk__data.html">gintmsk_data_t</a> intr_mask = {.d32 = 0 };
+<a name="l01382"></a>01382                 intr_mask.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#2c395e7bef31a4d9b2d1a3257c601be4">nptxfempty</a> = 1;
+<a name="l01383"></a>01383 
+<a name="l01384"></a>01384 <span class="preprocessor">#ifdef DEBUG</span>
+<a name="l01385"></a>01385 <span class="preprocessor"></span>                tx_status.<a class="code" href="uniongnptxsts__data.html#a58b5adbe6bd0344c4f585ef6aba4672">d32</a> = dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#57dabea6f6e0bf9e1ee8e94f55b9e465">gnptxsts</a>);
+<a name="l01386"></a>01386                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>,
+<a name="l01387"></a>01387                             <span class="stringliteral">"  NP Tx Req Queue Space Avail (after queue): %d\n"</span>,
+<a name="l01388"></a>01388                             tx_status.<a class="code" href="uniongnptxsts__data.html#be1d1adf7b827616ebbbf6bf564c0738">b</a>.<a class="code" href="uniongnptxsts__data.html#634ffd5e84bc422ddef043574d8f0957">nptxqspcavail</a>);
+<a name="l01389"></a>01389                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>,
+<a name="l01390"></a>01390                             <span class="stringliteral">"  NP Tx FIFO Space Avail (after queue): %d\n"</span>,
+<a name="l01391"></a>01391                             tx_status.<a class="code" href="uniongnptxsts__data.html#be1d1adf7b827616ebbbf6bf564c0738">b</a>.<a class="code" href="uniongnptxsts__data.html#6c149be246bcf5ca5395f67e67648207">nptxfspcavail</a>);
+<a name="l01392"></a>01392 <span class="preprocessor">#endif</span>
+<a name="l01393"></a>01393 <span class="preprocessor"></span>                <span class="keywordflow">if</span> (more_to_do || no_queue_space || no_fifo_space) {
+<a name="l01394"></a>01394                         <span class="comment">/*</span>
+<a name="l01395"></a>01395 <span class="comment">                         * May need to queue more transactions as the request</span>
+<a name="l01396"></a>01396 <span class="comment">                         * queue or Tx FIFO empties. Enable the non-periodic</span>
+<a name="l01397"></a>01397 <span class="comment">                         * Tx FIFO empty interrupt. (Always use the half-empty</span>
+<a name="l01398"></a>01398 <span class="comment">                         * level to ensure that new requests are loaded as</span>
+<a name="l01399"></a>01399 <span class="comment">                         * soon as possible.)</span>
+<a name="l01400"></a>01400 <span class="comment">                         */</span>
+<a name="l01401"></a>01401                         dwc_modify_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#48827c76da2c6b18f369e2f2483cc4b6">gintmsk</a>, 0,
+<a name="l01402"></a>01402                                          intr_mask.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a>);
+<a name="l01403"></a>01403                 } <span class="keywordflow">else</span> {
+<a name="l01404"></a>01404                         <span class="comment">/*</span>
+<a name="l01405"></a>01405 <span class="comment">                         * Disable the Tx FIFO empty interrupt since there are</span>
+<a name="l01406"></a>01406 <span class="comment">                         * no more transactions that need to be queued right</span>
+<a name="l01407"></a>01407 <span class="comment">                         * now. This function is called from interrupt</span>
+<a name="l01408"></a>01408 <span class="comment">                         * handlers to queue more transactions as transfer</span>
+<a name="l01409"></a>01409 <span class="comment">                         * states change.</span>
+<a name="l01410"></a>01410 <span class="comment">                         */</span>
+<a name="l01411"></a>01411                         dwc_modify_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#48827c76da2c6b18f369e2f2483cc4b6">gintmsk</a>, intr_mask.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a>,
+<a name="l01412"></a>01412                                          0);
+<a name="l01413"></a>01413                 }
+<a name="l01414"></a>01414         }
+<a name="l01415"></a>01415 }
+<a name="l01416"></a>01416 
+<a name="l01426"></a><a class="code" href="dwc__otg__hcd_8h.html#2f57bf2fc3013d63101f112702b913a0">01426</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd_8c.html#2f57bf2fc3013d63101f112702b913a0">dwc_otg_hcd_queue_transactions</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd,
+<a name="l01427"></a>01427                                            <a class="code" href="dwc__otg__hcd_8h.html#92c49783eebc5bcffa8b8a51c2127be9">dwc_otg_transaction_type_e</a> tr_type)
+<a name="l01428"></a>01428 {
+<a name="l01429"></a>01429 <span class="preprocessor">#ifdef DEBUG_SOF</span>
+<a name="l01430"></a>01430 <span class="preprocessor"></span>        <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#e4a050e176c1c4f556da2b276a8c2b37">DBG_HCD</a>, <span class="stringliteral">"Queue Transactions\n"</span>);
+<a name="l01431"></a>01431 <span class="preprocessor">#endif</span>
+<a name="l01432"></a>01432 <span class="preprocessor"></span>        <span class="comment">/* Process host channels associated with periodic transfers. */</span>
+<a name="l01433"></a>01433         <span class="keywordflow">if</span> ((tr_type == DWC_OTG_TRANSACTION_PERIODIC ||
+<a name="l01434"></a>01434              tr_type == DWC_OTG_TRANSACTION_ALL) &amp;&amp;
+<a name="l01435"></a>01435             !DWC_LIST_EMPTY(&amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#4b8deae798f771135c4a99693b26873f">periodic_sched_assigned</a>)) {
+<a name="l01436"></a>01436 
+<a name="l01437"></a>01437                 <a class="code" href="dwc__otg__hcd_8c.html#00876268eb53e5ce91dbedcb026181ec">process_periodic_channels</a>(hcd);
+<a name="l01438"></a>01438         }
+<a name="l01439"></a>01439 
+<a name="l01440"></a>01440         <span class="comment">/* Process host channels associated with non-periodic transfers. */</span>
+<a name="l01441"></a>01441         <span class="keywordflow">if</span> (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC ||
+<a name="l01442"></a>01442             tr_type == DWC_OTG_TRANSACTION_ALL) {
+<a name="l01443"></a>01443                 <span class="keywordflow">if</span> (!DWC_LIST_EMPTY(&amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#ffa3041ad517da9519aa2159cdec3f61">non_periodic_sched_active</a>)) {
+<a name="l01444"></a>01444                         <a class="code" href="dwc__otg__hcd_8c.html#a3f28e8605fd652c5177962e5dc8b95a">process_non_periodic_channels</a>(hcd);
+<a name="l01445"></a>01445                 } <span class="keywordflow">else</span> {
+<a name="l01446"></a>01446                         <span class="comment">/*</span>
+<a name="l01447"></a>01447 <span class="comment">                         * Ensure NP Tx FIFO empty interrupt is disabled when</span>
+<a name="l01448"></a>01448 <span class="comment">                         * there are no non-periodic transfers to process.</span>
+<a name="l01449"></a>01449 <span class="comment">                         */</span>
+<a name="l01450"></a>01450                         <a class="code" href="uniongintmsk__data.html">gintmsk_data_t</a> gintmsk = {.d32 = 0 };
+<a name="l01451"></a>01451                         gintmsk.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#2c395e7bef31a4d9b2d1a3257c601be4">nptxfempty</a> = 1;
+<a name="l01452"></a>01452                         dwc_modify_reg32(&amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;
+<a name="l01453"></a>01453                                          gintmsk, gintmsk.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a>, 0);
+<a name="l01454"></a>01454                 }
+<a name="l01455"></a>01455         }
+<a name="l01456"></a>01456 }
+<a name="l01457"></a>01457  
+<a name="l01458"></a>01458 <span class="preprocessor">#ifdef DWC_HS_ELECT_TST</span>
+<a name="l01459"></a>01459 <span class="preprocessor"></span><span class="comment">/*</span>
+<a name="l01460"></a>01460 <span class="comment"> * Quick and dirty hack to implement the HS Electrical Test</span>
+<a name="l01461"></a>01461 <span class="comment"> * SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature.</span>
+<a name="l01462"></a>01462 <span class="comment"> *</span>
+<a name="l01463"></a>01463 <span class="comment"> * This code was copied from our userspace app "hset". It sends a</span>
+<a name="l01464"></a>01464 <span class="comment"> * Get Device Descriptor control sequence in two parts, first the</span>
+<a name="l01465"></a>01465 <span class="comment"> * Setup packet by itself, followed some time later by the In and</span>
+<a name="l01466"></a>01466 <span class="comment"> * Ack packets. Rather than trying to figure out how to add this</span>
+<a name="l01467"></a>01467 <span class="comment"> * functionality to the normal driver code, we just hijack the</span>
+<a name="l01468"></a>01468 <span class="comment"> * hardware, using these two function to drive the hardware</span>
+<a name="l01469"></a>01469 <span class="comment"> * directly.</span>
+<a name="l01470"></a>01470 <span class="comment"> */</span>
+<a name="l01471"></a>01471 
+<a name="l01472"></a>01472 <span class="keyword">static</span> <a class="code" href="structdwc__otg__core__global__regs.html">dwc_otg_core_global_regs_t</a> *global_regs;
+<a name="l01473"></a>01473 <span class="keyword">static</span> <a class="code" href="structdwc__otg__host__global__regs.html">dwc_otg_host_global_regs_t</a> *hc_global_regs;
+<a name="l01474"></a>01474 <span class="keyword">static</span> <a class="code" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *hc_regs;
+<a name="l01475"></a>01475 <span class="keyword">static</span> uint32_t *data_fifo;
+<a name="l01476"></a>01476 
+<a name="l01477"></a>01477 <span class="keyword">static</span> <span class="keywordtype">void</span> do_setup(<span class="keywordtype">void</span>)
+<a name="l01478"></a>01478 {
+<a name="l01479"></a>01479         <a class="code" href="uniongintsts__data.html">gintsts_data_t</a> gintsts;
+<a name="l01480"></a>01480         <a class="code" href="unionhctsiz__data.html">hctsiz_data_t</a> hctsiz;
+<a name="l01481"></a>01481         <a class="code" href="unionhcchar__data.html">hcchar_data_t</a> hcchar;
+<a name="l01482"></a>01482         <a class="code" href="unionhaint__data.html">haint_data_t</a> haint;
+<a name="l01483"></a>01483         <a class="code" href="unionhcint__data.html">hcint_data_t</a> hcint;
+<a name="l01484"></a>01484 
+<a name="l01485"></a>01485         <span class="comment">/* Enable HAINTs */</span>
+<a name="l01486"></a>01486         dwc_write_reg32(&amp;hc_global_regs-&gt;<a class="code" href="structdwc__otg__host__global__regs.html#317f5059d4c2dc91da041f5c0a4819fc">haintmsk</a>, 0x0001);
+<a name="l01487"></a>01487 
+<a name="l01488"></a>01488         <span class="comment">/* Enable HCINTs */</span>
+<a name="l01489"></a>01489         dwc_write_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#830aa61c1d4326823662168ea7359205">hcintmsk</a>, 0x04a3);
+<a name="l01490"></a>01490 
+<a name="l01491"></a>01491         <span class="comment">/* Read GINTSTS */</span>
+<a name="l01492"></a>01492         gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a> = dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>);
+<a name="l01493"></a>01493 
+<a name="l01494"></a>01494         <span class="comment">/* Read HAINT */</span>
+<a name="l01495"></a>01495         haint.<a class="code" href="unionhaint__data.html#c83834650d2981b44274a89dda63a0f5">d32</a> = dwc_read_reg32(&amp;hc_global_regs-&gt;<a class="code" href="structdwc__otg__host__global__regs.html#7c41808b0a69ed7d2125eb3afbbf6c14">haint</a>);
+<a name="l01496"></a>01496 
+<a name="l01497"></a>01497         <span class="comment">/* Read HCINT */</span>
+<a name="l01498"></a>01498         hcint.<a class="code" href="unionhcint__data.html#05a82fa7693f875622db744716d7f73e">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#0dfd5bae537d58e13788508dc719480d">hcint</a>);
+<a name="l01499"></a>01499 
+<a name="l01500"></a>01500         <span class="comment">/* Read HCCHAR */</span>
+<a name="l01501"></a>01501         hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">hcchar</a>);
+<a name="l01502"></a>01502 
+<a name="l01503"></a>01503         <span class="comment">/* Clear HCINT */</span>
+<a name="l01504"></a>01504         dwc_write_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#0dfd5bae537d58e13788508dc719480d">hcint</a>, hcint.<a class="code" href="unionhcint__data.html#05a82fa7693f875622db744716d7f73e">d32</a>);
+<a name="l01505"></a>01505 
+<a name="l01506"></a>01506         <span class="comment">/* Clear HAINT */</span>
+<a name="l01507"></a>01507         dwc_write_reg32(&amp;hc_global_regs-&gt;<a class="code" href="structdwc__otg__host__global__regs.html#7c41808b0a69ed7d2125eb3afbbf6c14">haint</a>, haint.<a class="code" href="unionhaint__data.html#c83834650d2981b44274a89dda63a0f5">d32</a>);
+<a name="l01508"></a>01508 
+<a name="l01509"></a>01509         <span class="comment">/* Clear GINTSTS */</span>
+<a name="l01510"></a>01510         dwc_write_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>, gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a>);
+<a name="l01511"></a>01511 
+<a name="l01512"></a>01512         <span class="comment">/* Read GINTSTS */</span>
+<a name="l01513"></a>01513         gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a> = dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>);
+<a name="l01514"></a>01514 
+<a name="l01515"></a>01515         <span class="comment">/*</span>
+<a name="l01516"></a>01516 <span class="comment">         * Send Setup packet (Get Device Descriptor)</span>
+<a name="l01517"></a>01517 <span class="comment">         */</span>
+<a name="l01518"></a>01518 
+<a name="l01519"></a>01519         <span class="comment">/* Make sure channel is disabled */</span>
+<a name="l01520"></a>01520         hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">hcchar</a>);
+<a name="l01521"></a>01521         <span class="keywordflow">if</span> (hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#994a5305780edb0c4fe159b6cc7b14ae">chen</a>) {
+<a name="l01522"></a>01522                 hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#73c9f7f3cc4036c72ef341d1d1d9c388">chdis</a> = 1;
+<a name="l01523"></a>01523 <span class="comment">//              hcchar.b.chen = 1;</span>
+<a name="l01524"></a>01524                 dwc_write_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">hcchar</a>, hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a>);
+<a name="l01525"></a>01525                 <span class="comment">//sleep(1);</span>
+<a name="l01526"></a>01526                 dwc_mdelay(1000);
+<a name="l01527"></a>01527 
+<a name="l01528"></a>01528                 <span class="comment">/* Read GINTSTS */</span>
+<a name="l01529"></a>01529                 gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a> = dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>);
+<a name="l01530"></a>01530 
+<a name="l01531"></a>01531                 <span class="comment">/* Read HAINT */</span>
+<a name="l01532"></a>01532                 haint.<a class="code" href="unionhaint__data.html#c83834650d2981b44274a89dda63a0f5">d32</a> = dwc_read_reg32(&amp;hc_global_regs-&gt;<a class="code" href="structdwc__otg__host__global__regs.html#7c41808b0a69ed7d2125eb3afbbf6c14">haint</a>);
+<a name="l01533"></a>01533 
+<a name="l01534"></a>01534                 <span class="comment">/* Read HCINT */</span>
+<a name="l01535"></a>01535                 hcint.<a class="code" href="unionhcint__data.html#05a82fa7693f875622db744716d7f73e">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#0dfd5bae537d58e13788508dc719480d">hcint</a>);
+<a name="l01536"></a>01536 
+<a name="l01537"></a>01537                 <span class="comment">/* Read HCCHAR */</span>
+<a name="l01538"></a>01538                 hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">hcchar</a>);
+<a name="l01539"></a>01539 
+<a name="l01540"></a>01540                 <span class="comment">/* Clear HCINT */</span>
+<a name="l01541"></a>01541                 dwc_write_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#0dfd5bae537d58e13788508dc719480d">hcint</a>, hcint.<a class="code" href="unionhcint__data.html#05a82fa7693f875622db744716d7f73e">d32</a>);
+<a name="l01542"></a>01542 
+<a name="l01543"></a>01543                 <span class="comment">/* Clear HAINT */</span>
+<a name="l01544"></a>01544                 dwc_write_reg32(&amp;hc_global_regs-&gt;<a class="code" href="structdwc__otg__host__global__regs.html#7c41808b0a69ed7d2125eb3afbbf6c14">haint</a>, haint.<a class="code" href="unionhaint__data.html#c83834650d2981b44274a89dda63a0f5">d32</a>);
+<a name="l01545"></a>01545 
+<a name="l01546"></a>01546                 <span class="comment">/* Clear GINTSTS */</span>
+<a name="l01547"></a>01547                 dwc_write_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>, gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a>);
+<a name="l01548"></a>01548 
+<a name="l01549"></a>01549                 hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">hcchar</a>);
+<a name="l01550"></a>01550         }
+<a name="l01551"></a>01551 
+<a name="l01552"></a>01552         <span class="comment">/* Set HCTSIZ */</span>
+<a name="l01553"></a>01553         hctsiz.<a class="code" href="unionhctsiz__data.html#fb41950555c60c6015294bdefe9cd39d">d32</a> = 0;
+<a name="l01554"></a>01554         hctsiz.<a class="code" href="unionhctsiz__data.html#8967fa90c651bce44a3cbe90c44cf638">b</a>.<a class="code" href="unionhctsiz__data.html#6ad01d874d77aa4382f71fa68eaec12d">xfersize</a> = 8;
+<a name="l01555"></a>01555         hctsiz.<a class="code" href="unionhctsiz__data.html#8967fa90c651bce44a3cbe90c44cf638">b</a>.<a class="code" href="unionhctsiz__data.html#3ea18df5a98d33a6f8fa786252a0205b">pktcnt</a> = 1;
+<a name="l01556"></a>01556         hctsiz.<a class="code" href="unionhctsiz__data.html#8967fa90c651bce44a3cbe90c44cf638">b</a>.<a class="code" href="unionhctsiz__data.html#d8b17af02c244e47ca0c38f933a6b3f0">pid</a> = <a class="code" href="dwc__otg__cil_8h.html#8d329f92a5ff6f9a72fc755b6b1a4e17">DWC_OTG_HC_PID_SETUP</a>;
+<a name="l01557"></a>01557         dwc_write_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#c6173f823ba754d9f9549422b6380ca2">hctsiz</a>, hctsiz.<a class="code" href="unionhctsiz__data.html#fb41950555c60c6015294bdefe9cd39d">d32</a>);
+<a name="l01558"></a>01558 
+<a name="l01559"></a>01559         <span class="comment">/* Set HCCHAR */</span>
+<a name="l01560"></a>01560         hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">hcchar</a>);
+<a name="l01561"></a>01561         hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#df4deee52d932ab29e5d077cde77cbfc">eptype</a> = <a class="code" href="dwc__otg__cil_8h.html#64e5cd756330f5adab79b25cc8067bdc">DWC_OTG_EP_TYPE_CONTROL</a>;
+<a name="l01562"></a>01562         hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#11f1b16e50f90806f90953bb979d4e77">epdir</a> = 0;
+<a name="l01563"></a>01563         hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#1597f36b85006e643aaf6f4d503bebc9">epnum</a> = 0;
+<a name="l01564"></a>01564         hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#47d11a5e62f69534d8ac0606aa7ffe7d">mps</a> = 8;
+<a name="l01565"></a>01565         hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#994a5305780edb0c4fe159b6cc7b14ae">chen</a> = 1;
+<a name="l01566"></a>01566         dwc_write_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">hcchar</a>, hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a>);
+<a name="l01567"></a>01567 
+<a name="l01568"></a>01568         <span class="comment">/* Fill FIFO with Setup data for Get Device Descriptor */</span>
+<a name="l01569"></a>01569         data_fifo = (uint32_t *) ((<span class="keywordtype">char</span> *)global_regs + 0x1000);
+<a name="l01570"></a>01570         dwc_write_reg32(data_fifo++, 0x01000680);
+<a name="l01571"></a>01571         dwc_write_reg32(data_fifo++, 0x00080000);
+<a name="l01572"></a>01572 
+<a name="l01573"></a>01573         gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a> = dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>);
+<a name="l01574"></a>01574 
+<a name="l01575"></a>01575         <span class="comment">/* Wait for host channel interrupt */</span>
+<a name="l01576"></a>01576         <span class="keywordflow">do</span> {
+<a name="l01577"></a>01577                 gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a> = dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>);
+<a name="l01578"></a>01578         } <span class="keywordflow">while</span> (gintsts.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#e02f1a50b20ed1c4248fd76e155147e8">hcintr</a> == 0);
+<a name="l01579"></a>01579 
+<a name="l01580"></a>01580 
+<a name="l01581"></a>01581         <span class="comment">/* Disable HCINTs */</span>
+<a name="l01582"></a>01582         dwc_write_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#830aa61c1d4326823662168ea7359205">hcintmsk</a>, 0x0000);
+<a name="l01583"></a>01583 
+<a name="l01584"></a>01584         <span class="comment">/* Disable HAINTs */</span>
+<a name="l01585"></a>01585         dwc_write_reg32(&amp;hc_global_regs-&gt;<a class="code" href="structdwc__otg__host__global__regs.html#317f5059d4c2dc91da041f5c0a4819fc">haintmsk</a>, 0x0000);
+<a name="l01586"></a>01586 
+<a name="l01587"></a>01587         <span class="comment">/* Read HAINT */</span>
+<a name="l01588"></a>01588         haint.<a class="code" href="unionhaint__data.html#c83834650d2981b44274a89dda63a0f5">d32</a> = dwc_read_reg32(&amp;hc_global_regs-&gt;<a class="code" href="structdwc__otg__host__global__regs.html#7c41808b0a69ed7d2125eb3afbbf6c14">haint</a>);
+<a name="l01589"></a>01589 
+<a name="l01590"></a>01590         <span class="comment">/* Read HCINT */</span>
+<a name="l01591"></a>01591         hcint.<a class="code" href="unionhcint__data.html#05a82fa7693f875622db744716d7f73e">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#0dfd5bae537d58e13788508dc719480d">hcint</a>);
+<a name="l01592"></a>01592 
+<a name="l01593"></a>01593         <span class="comment">/* Read HCCHAR */</span>
+<a name="l01594"></a>01594         hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">hcchar</a>);
+<a name="l01595"></a>01595 
+<a name="l01596"></a>01596         <span class="comment">/* Clear HCINT */</span>
+<a name="l01597"></a>01597         dwc_write_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#0dfd5bae537d58e13788508dc719480d">hcint</a>, hcint.<a class="code" href="unionhcint__data.html#05a82fa7693f875622db744716d7f73e">d32</a>);
+<a name="l01598"></a>01598 
+<a name="l01599"></a>01599         <span class="comment">/* Clear HAINT */</span>
+<a name="l01600"></a>01600         dwc_write_reg32(&amp;hc_global_regs-&gt;<a class="code" href="structdwc__otg__host__global__regs.html#7c41808b0a69ed7d2125eb3afbbf6c14">haint</a>, haint.<a class="code" href="unionhaint__data.html#c83834650d2981b44274a89dda63a0f5">d32</a>);
+<a name="l01601"></a>01601 
+<a name="l01602"></a>01602         <span class="comment">/* Clear GINTSTS */</span>
+<a name="l01603"></a>01603         dwc_write_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>, gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a>);
+<a name="l01604"></a>01604 
+<a name="l01605"></a>01605         <span class="comment">/* Read GINTSTS */</span>
+<a name="l01606"></a>01606         gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a> = dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>);
+<a name="l01607"></a>01607 }
+<a name="l01608"></a>01608 
+<a name="l01609"></a>01609 <span class="keyword">static</span> <span class="keywordtype">void</span> do_in_ack(<span class="keywordtype">void</span>)
+<a name="l01610"></a>01610 {
+<a name="l01611"></a>01611         <a class="code" href="uniongintsts__data.html">gintsts_data_t</a> gintsts;
+<a name="l01612"></a>01612         <a class="code" href="unionhctsiz__data.html">hctsiz_data_t</a> hctsiz;
+<a name="l01613"></a>01613         <a class="code" href="unionhcchar__data.html">hcchar_data_t</a> hcchar;
+<a name="l01614"></a>01614         <a class="code" href="unionhaint__data.html">haint_data_t</a> haint;
+<a name="l01615"></a>01615         <a class="code" href="unionhcint__data.html">hcint_data_t</a> hcint;
+<a name="l01616"></a>01616         <a class="code" href="unionhost__grxsts__data.html">host_grxsts_data_t</a> grxsts;
+<a name="l01617"></a>01617 
+<a name="l01618"></a>01618         <span class="comment">/* Enable HAINTs */</span>
+<a name="l01619"></a>01619         dwc_write_reg32(&amp;hc_global_regs-&gt;<a class="code" href="structdwc__otg__host__global__regs.html#317f5059d4c2dc91da041f5c0a4819fc">haintmsk</a>, 0x0001);
+<a name="l01620"></a>01620 
+<a name="l01621"></a>01621         <span class="comment">/* Enable HCINTs */</span>
+<a name="l01622"></a>01622         dwc_write_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#830aa61c1d4326823662168ea7359205">hcintmsk</a>, 0x04a3);
+<a name="l01623"></a>01623 
+<a name="l01624"></a>01624         <span class="comment">/* Read GINTSTS */</span>
+<a name="l01625"></a>01625         gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a> = dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>);
+<a name="l01626"></a>01626 
+<a name="l01627"></a>01627         <span class="comment">/* Read HAINT */</span>
+<a name="l01628"></a>01628         haint.<a class="code" href="unionhaint__data.html#c83834650d2981b44274a89dda63a0f5">d32</a> = dwc_read_reg32(&amp;hc_global_regs-&gt;<a class="code" href="structdwc__otg__host__global__regs.html#7c41808b0a69ed7d2125eb3afbbf6c14">haint</a>);
+<a name="l01629"></a>01629 
+<a name="l01630"></a>01630         <span class="comment">/* Read HCINT */</span>
+<a name="l01631"></a>01631         hcint.<a class="code" href="unionhcint__data.html#05a82fa7693f875622db744716d7f73e">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#0dfd5bae537d58e13788508dc719480d">hcint</a>);
+<a name="l01632"></a>01632 
+<a name="l01633"></a>01633         <span class="comment">/* Read HCCHAR */</span>
+<a name="l01634"></a>01634         hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">hcchar</a>);
+<a name="l01635"></a>01635 
+<a name="l01636"></a>01636         <span class="comment">/* Clear HCINT */</span>
+<a name="l01637"></a>01637         dwc_write_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#0dfd5bae537d58e13788508dc719480d">hcint</a>, hcint.<a class="code" href="unionhcint__data.html#05a82fa7693f875622db744716d7f73e">d32</a>);
+<a name="l01638"></a>01638 
+<a name="l01639"></a>01639         <span class="comment">/* Clear HAINT */</span>
+<a name="l01640"></a>01640         dwc_write_reg32(&amp;hc_global_regs-&gt;<a class="code" href="structdwc__otg__host__global__regs.html#7c41808b0a69ed7d2125eb3afbbf6c14">haint</a>, haint.<a class="code" href="unionhaint__data.html#c83834650d2981b44274a89dda63a0f5">d32</a>);
+<a name="l01641"></a>01641 
+<a name="l01642"></a>01642         <span class="comment">/* Clear GINTSTS */</span>
+<a name="l01643"></a>01643         dwc_write_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>, gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a>);
+<a name="l01644"></a>01644 
+<a name="l01645"></a>01645         <span class="comment">/* Read GINTSTS */</span>
+<a name="l01646"></a>01646         gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a> = dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>);
+<a name="l01647"></a>01647 
+<a name="l01648"></a>01648         <span class="comment">/*</span>
+<a name="l01649"></a>01649 <span class="comment">         * Receive Control In packet</span>
+<a name="l01650"></a>01650 <span class="comment">         */</span>
+<a name="l01651"></a>01651 
+<a name="l01652"></a>01652         <span class="comment">/* Make sure channel is disabled */</span>
+<a name="l01653"></a>01653         hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">hcchar</a>);
+<a name="l01654"></a>01654         <span class="keywordflow">if</span> (hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#994a5305780edb0c4fe159b6cc7b14ae">chen</a>) {
+<a name="l01655"></a>01655                 hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#73c9f7f3cc4036c72ef341d1d1d9c388">chdis</a> = 1;
+<a name="l01656"></a>01656                 hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#994a5305780edb0c4fe159b6cc7b14ae">chen</a> = 1;
+<a name="l01657"></a>01657                 dwc_write_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">hcchar</a>, hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a>);
+<a name="l01658"></a>01658                 <span class="comment">//sleep(1);</span>
+<a name="l01659"></a>01659                 dwc_mdelay(1000);
+<a name="l01660"></a>01660 
+<a name="l01661"></a>01661                 <span class="comment">/* Read GINTSTS */</span>
+<a name="l01662"></a>01662                 gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a> = dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>);
+<a name="l01663"></a>01663 
+<a name="l01664"></a>01664                 <span class="comment">/* Read HAINT */</span>
+<a name="l01665"></a>01665                 haint.<a class="code" href="unionhaint__data.html#c83834650d2981b44274a89dda63a0f5">d32</a> = dwc_read_reg32(&amp;hc_global_regs-&gt;<a class="code" href="structdwc__otg__host__global__regs.html#7c41808b0a69ed7d2125eb3afbbf6c14">haint</a>);
+<a name="l01666"></a>01666 
+<a name="l01667"></a>01667                 <span class="comment">/* Read HCINT */</span>
+<a name="l01668"></a>01668                 hcint.<a class="code" href="unionhcint__data.html#05a82fa7693f875622db744716d7f73e">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#0dfd5bae537d58e13788508dc719480d">hcint</a>);
+<a name="l01669"></a>01669 
+<a name="l01670"></a>01670                 <span class="comment">/* Read HCCHAR */</span>
+<a name="l01671"></a>01671                 hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">hcchar</a>);
+<a name="l01672"></a>01672 
+<a name="l01673"></a>01673                 <span class="comment">/* Clear HCINT */</span>
+<a name="l01674"></a>01674                 dwc_write_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#0dfd5bae537d58e13788508dc719480d">hcint</a>, hcint.<a class="code" href="unionhcint__data.html#05a82fa7693f875622db744716d7f73e">d32</a>);
+<a name="l01675"></a>01675 
+<a name="l01676"></a>01676                 <span class="comment">/* Clear HAINT */</span>
+<a name="l01677"></a>01677                 dwc_write_reg32(&amp;hc_global_regs-&gt;<a class="code" href="structdwc__otg__host__global__regs.html#7c41808b0a69ed7d2125eb3afbbf6c14">haint</a>, haint.<a class="code" href="unionhaint__data.html#c83834650d2981b44274a89dda63a0f5">d32</a>);
+<a name="l01678"></a>01678 
+<a name="l01679"></a>01679                 <span class="comment">/* Clear GINTSTS */</span>
+<a name="l01680"></a>01680                 dwc_write_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>, gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a>);
+<a name="l01681"></a>01681 
+<a name="l01682"></a>01682                 hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">hcchar</a>);
+<a name="l01683"></a>01683         }
+<a name="l01684"></a>01684 
+<a name="l01685"></a>01685         <span class="comment">/* Set HCTSIZ */</span>
+<a name="l01686"></a>01686         hctsiz.<a class="code" href="unionhctsiz__data.html#fb41950555c60c6015294bdefe9cd39d">d32</a> = 0;
+<a name="l01687"></a>01687         hctsiz.<a class="code" href="unionhctsiz__data.html#8967fa90c651bce44a3cbe90c44cf638">b</a>.<a class="code" href="unionhctsiz__data.html#6ad01d874d77aa4382f71fa68eaec12d">xfersize</a> = 8;
+<a name="l01688"></a>01688         hctsiz.<a class="code" href="unionhctsiz__data.html#8967fa90c651bce44a3cbe90c44cf638">b</a>.<a class="code" href="unionhctsiz__data.html#3ea18df5a98d33a6f8fa786252a0205b">pktcnt</a> = 1;
+<a name="l01689"></a>01689         hctsiz.<a class="code" href="unionhctsiz__data.html#8967fa90c651bce44a3cbe90c44cf638">b</a>.<a class="code" href="unionhctsiz__data.html#d8b17af02c244e47ca0c38f933a6b3f0">pid</a> = <a class="code" href="dwc__otg__cil_8h.html#e623eb446c55928b324e9636111315e1">DWC_OTG_HC_PID_DATA1</a>;
+<a name="l01690"></a>01690         dwc_write_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#c6173f823ba754d9f9549422b6380ca2">hctsiz</a>, hctsiz.<a class="code" href="unionhctsiz__data.html#fb41950555c60c6015294bdefe9cd39d">d32</a>);
+<a name="l01691"></a>01691 
+<a name="l01692"></a>01692         <span class="comment">/* Set HCCHAR */</span>
+<a name="l01693"></a>01693         hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">hcchar</a>);
+<a name="l01694"></a>01694         hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#df4deee52d932ab29e5d077cde77cbfc">eptype</a> = <a class="code" href="dwc__otg__cil_8h.html#64e5cd756330f5adab79b25cc8067bdc">DWC_OTG_EP_TYPE_CONTROL</a>;
+<a name="l01695"></a>01695         hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#11f1b16e50f90806f90953bb979d4e77">epdir</a> = 1;
+<a name="l01696"></a>01696         hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#1597f36b85006e643aaf6f4d503bebc9">epnum</a> = 0;
+<a name="l01697"></a>01697         hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#47d11a5e62f69534d8ac0606aa7ffe7d">mps</a> = 8;
+<a name="l01698"></a>01698         hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#994a5305780edb0c4fe159b6cc7b14ae">chen</a> = 1;
+<a name="l01699"></a>01699         dwc_write_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">hcchar</a>, hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a>);
+<a name="l01700"></a>01700 
+<a name="l01701"></a>01701         gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a> = dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>);
+<a name="l01702"></a>01702 
+<a name="l01703"></a>01703         <span class="comment">/* Wait for receive status queue interrupt */</span>
+<a name="l01704"></a>01704         <span class="keywordflow">do</span> {
+<a name="l01705"></a>01705                 gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a> = dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>);
+<a name="l01706"></a>01706         } <span class="keywordflow">while</span> (gintsts.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#7595576956c3a0ced9ea387880943012">rxstsqlvl</a> == 0);
+<a name="l01707"></a>01707 
+<a name="l01708"></a>01708 
+<a name="l01709"></a>01709         <span class="comment">/* Read RXSTS */</span>
+<a name="l01710"></a>01710         grxsts.<a class="code" href="unionhost__grxsts__data.html#993969735da9c3615652391aae76359a">d32</a> = dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#763b05035799e1c16d34957fb62a2d17">grxstsp</a>);
+<a name="l01711"></a>01711 
+<a name="l01712"></a>01712         <span class="comment">/* Clear RXSTSQLVL in GINTSTS */</span>
+<a name="l01713"></a>01713         gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a> = 0;
+<a name="l01714"></a>01714         gintsts.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#7595576956c3a0ced9ea387880943012">rxstsqlvl</a> = 1;
+<a name="l01715"></a>01715         dwc_write_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>, gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a>);
+<a name="l01716"></a>01716 
+<a name="l01717"></a>01717         <span class="keywordflow">switch</span> (grxsts.<a class="code" href="unionhost__grxsts__data.html#9d67ba193008dd6afa7fe613c665238d">b</a>.<a class="code" href="unionhost__grxsts__data.html#6dc2553475a56a445c6e6f319feffac8">pktsts</a>) {
+<a name="l01718"></a>01718         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__regs_8h.html#d81c89ef7c3e40cfffe9ed08b7136e90">DWC_GRXSTS_PKTSTS_IN</a>:
+<a name="l01719"></a>01719                 <span class="comment">/* Read the data into the host buffer */</span>
+<a name="l01720"></a>01720                 <span class="keywordflow">if</span> (grxsts.<a class="code" href="unionhost__grxsts__data.html#9d67ba193008dd6afa7fe613c665238d">b</a>.<a class="code" href="unionhost__grxsts__data.html#026fd4d8ab68825fab038c083b8e9c60">bcnt</a> &gt; 0) {
+<a name="l01721"></a>01721                         <span class="keywordtype">int</span> i;
+<a name="l01722"></a>01722                         <span class="keywordtype">int</span> word_count = (grxsts.<a class="code" href="unionhost__grxsts__data.html#9d67ba193008dd6afa7fe613c665238d">b</a>.<a class="code" href="unionhost__grxsts__data.html#026fd4d8ab68825fab038c083b8e9c60">bcnt</a> + 3) / 4;
+<a name="l01723"></a>01723 
+<a name="l01724"></a>01724                         data_fifo = (uint32_t *) ((<span class="keywordtype">char</span> *)global_regs + 0x1000);
+<a name="l01725"></a>01725 
+<a name="l01726"></a>01726                         <span class="keywordflow">for</span> (i = 0; i &lt; word_count; i++) {
+<a name="l01727"></a>01727                                 (<span class="keywordtype">void</span>)dwc_read_reg32(data_fifo++);
+<a name="l01728"></a>01728                         }
+<a name="l01729"></a>01729                 }
+<a name="l01730"></a>01730                 <span class="keywordflow">break</span>;
+<a name="l01731"></a>01731 
+<a name="l01732"></a>01732         <span class="keywordflow">default</span>:
+<a name="l01733"></a>01733                 <span class="keywordflow">break</span>;
+<a name="l01734"></a>01734         }
+<a name="l01735"></a>01735 
+<a name="l01736"></a>01736         gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a> = dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>);
+<a name="l01737"></a>01737 
+<a name="l01738"></a>01738         <span class="comment">/* Wait for receive status queue interrupt */</span>
+<a name="l01739"></a>01739         <span class="keywordflow">do</span> {
+<a name="l01740"></a>01740                 gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a> = dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>);
+<a name="l01741"></a>01741         } <span class="keywordflow">while</span> (gintsts.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#7595576956c3a0ced9ea387880943012">rxstsqlvl</a> == 0);
+<a name="l01742"></a>01742 
+<a name="l01743"></a>01743 
+<a name="l01744"></a>01744         <span class="comment">/* Read RXSTS */</span>
+<a name="l01745"></a>01745         grxsts.<a class="code" href="unionhost__grxsts__data.html#993969735da9c3615652391aae76359a">d32</a> = dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#763b05035799e1c16d34957fb62a2d17">grxstsp</a>);
+<a name="l01746"></a>01746 
+<a name="l01747"></a>01747         <span class="comment">/* Clear RXSTSQLVL in GINTSTS */</span>
+<a name="l01748"></a>01748         gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a> = 0;
+<a name="l01749"></a>01749         gintsts.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#7595576956c3a0ced9ea387880943012">rxstsqlvl</a> = 1;
+<a name="l01750"></a>01750         dwc_write_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>, gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a>);
+<a name="l01751"></a>01751 
+<a name="l01752"></a>01752         <span class="keywordflow">switch</span> (grxsts.<a class="code" href="unionhost__grxsts__data.html#9d67ba193008dd6afa7fe613c665238d">b</a>.<a class="code" href="unionhost__grxsts__data.html#6dc2553475a56a445c6e6f319feffac8">pktsts</a>) {
+<a name="l01753"></a>01753         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__regs_8h.html#c5c019a36ea5cb66d3cb436292d8c3de">DWC_GRXSTS_PKTSTS_IN_XFER_COMP</a>:
+<a name="l01754"></a>01754                 <span class="keywordflow">break</span>;
+<a name="l01755"></a>01755 
+<a name="l01756"></a>01756         <span class="keywordflow">default</span>:
+<a name="l01757"></a>01757                 <span class="keywordflow">break</span>;
+<a name="l01758"></a>01758         }
+<a name="l01759"></a>01759 
+<a name="l01760"></a>01760         gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a> = dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>);
+<a name="l01761"></a>01761 
+<a name="l01762"></a>01762         <span class="comment">/* Wait for host channel interrupt */</span>
+<a name="l01763"></a>01763         <span class="keywordflow">do</span> {
+<a name="l01764"></a>01764                 gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a> = dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>);
+<a name="l01765"></a>01765         } <span class="keywordflow">while</span> (gintsts.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#e02f1a50b20ed1c4248fd76e155147e8">hcintr</a> == 0);
+<a name="l01766"></a>01766 
+<a name="l01767"></a>01767 
+<a name="l01768"></a>01768         <span class="comment">/* Read HAINT */</span>
+<a name="l01769"></a>01769         haint.<a class="code" href="unionhaint__data.html#c83834650d2981b44274a89dda63a0f5">d32</a> = dwc_read_reg32(&amp;hc_global_regs-&gt;<a class="code" href="structdwc__otg__host__global__regs.html#7c41808b0a69ed7d2125eb3afbbf6c14">haint</a>);
+<a name="l01770"></a>01770 
+<a name="l01771"></a>01771         <span class="comment">/* Read HCINT */</span>
+<a name="l01772"></a>01772         hcint.<a class="code" href="unionhcint__data.html#05a82fa7693f875622db744716d7f73e">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#0dfd5bae537d58e13788508dc719480d">hcint</a>);
+<a name="l01773"></a>01773 
+<a name="l01774"></a>01774         <span class="comment">/* Read HCCHAR */</span>
+<a name="l01775"></a>01775         hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">hcchar</a>);
+<a name="l01776"></a>01776 
+<a name="l01777"></a>01777         <span class="comment">/* Clear HCINT */</span>
+<a name="l01778"></a>01778         dwc_write_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#0dfd5bae537d58e13788508dc719480d">hcint</a>, hcint.<a class="code" href="unionhcint__data.html#05a82fa7693f875622db744716d7f73e">d32</a>);
+<a name="l01779"></a>01779 
+<a name="l01780"></a>01780         <span class="comment">/* Clear HAINT */</span>
+<a name="l01781"></a>01781         dwc_write_reg32(&amp;hc_global_regs-&gt;<a class="code" href="structdwc__otg__host__global__regs.html#7c41808b0a69ed7d2125eb3afbbf6c14">haint</a>, haint.<a class="code" href="unionhaint__data.html#c83834650d2981b44274a89dda63a0f5">d32</a>);
+<a name="l01782"></a>01782 
+<a name="l01783"></a>01783         <span class="comment">/* Clear GINTSTS */</span>
+<a name="l01784"></a>01784         dwc_write_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>, gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a>);
+<a name="l01785"></a>01785 
+<a name="l01786"></a>01786         <span class="comment">/* Read GINTSTS */</span>
+<a name="l01787"></a>01787         gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a> = dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>);
+<a name="l01788"></a>01788 
+<a name="l01789"></a>01789 <span class="comment">//      usleep(100000);</span>
+<a name="l01790"></a>01790 <span class="comment">//      mdelay(100);</span>
+<a name="l01791"></a>01791         dwc_mdelay(1);
+<a name="l01792"></a>01792 
+<a name="l01793"></a>01793         <span class="comment">/*</span>
+<a name="l01794"></a>01794 <span class="comment">         * Send handshake packet</span>
+<a name="l01795"></a>01795 <span class="comment">         */</span>
+<a name="l01796"></a>01796 
+<a name="l01797"></a>01797         <span class="comment">/* Read HAINT */</span>
+<a name="l01798"></a>01798         haint.<a class="code" href="unionhaint__data.html#c83834650d2981b44274a89dda63a0f5">d32</a> = dwc_read_reg32(&amp;hc_global_regs-&gt;<a class="code" href="structdwc__otg__host__global__regs.html#7c41808b0a69ed7d2125eb3afbbf6c14">haint</a>);
+<a name="l01799"></a>01799 
+<a name="l01800"></a>01800         <span class="comment">/* Read HCINT */</span>
+<a name="l01801"></a>01801         hcint.<a class="code" href="unionhcint__data.html#05a82fa7693f875622db744716d7f73e">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#0dfd5bae537d58e13788508dc719480d">hcint</a>);
+<a name="l01802"></a>01802 
+<a name="l01803"></a>01803         <span class="comment">/* Read HCCHAR */</span>
+<a name="l01804"></a>01804         hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">hcchar</a>);
+<a name="l01805"></a>01805 
+<a name="l01806"></a>01806         <span class="comment">/* Clear HCINT */</span>
+<a name="l01807"></a>01807         dwc_write_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#0dfd5bae537d58e13788508dc719480d">hcint</a>, hcint.<a class="code" href="unionhcint__data.html#05a82fa7693f875622db744716d7f73e">d32</a>);
+<a name="l01808"></a>01808 
+<a name="l01809"></a>01809         <span class="comment">/* Clear HAINT */</span>
+<a name="l01810"></a>01810         dwc_write_reg32(&amp;hc_global_regs-&gt;<a class="code" href="structdwc__otg__host__global__regs.html#7c41808b0a69ed7d2125eb3afbbf6c14">haint</a>, haint.<a class="code" href="unionhaint__data.html#c83834650d2981b44274a89dda63a0f5">d32</a>);
+<a name="l01811"></a>01811 
+<a name="l01812"></a>01812         <span class="comment">/* Clear GINTSTS */</span>
+<a name="l01813"></a>01813         dwc_write_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>, gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a>);
+<a name="l01814"></a>01814 
+<a name="l01815"></a>01815         <span class="comment">/* Read GINTSTS */</span>
+<a name="l01816"></a>01816         gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a> = dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>);
+<a name="l01817"></a>01817 
+<a name="l01818"></a>01818         <span class="comment">/* Make sure channel is disabled */</span>
+<a name="l01819"></a>01819         hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">hcchar</a>);
+<a name="l01820"></a>01820         <span class="keywordflow">if</span> (hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#994a5305780edb0c4fe159b6cc7b14ae">chen</a>) {
+<a name="l01821"></a>01821                 hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#73c9f7f3cc4036c72ef341d1d1d9c388">chdis</a> = 1;
+<a name="l01822"></a>01822                 hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#994a5305780edb0c4fe159b6cc7b14ae">chen</a> = 1;
+<a name="l01823"></a>01823                 dwc_write_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">hcchar</a>, hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a>);
+<a name="l01824"></a>01824                 <span class="comment">//sleep(1);</span>
+<a name="l01825"></a>01825                 dwc_mdelay(1000);
+<a name="l01826"></a>01826 
+<a name="l01827"></a>01827                 <span class="comment">/* Read GINTSTS */</span>
+<a name="l01828"></a>01828                 gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a> = dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>);
+<a name="l01829"></a>01829 
+<a name="l01830"></a>01830                 <span class="comment">/* Read HAINT */</span>
+<a name="l01831"></a>01831                 haint.<a class="code" href="unionhaint__data.html#c83834650d2981b44274a89dda63a0f5">d32</a> = dwc_read_reg32(&amp;hc_global_regs-&gt;<a class="code" href="structdwc__otg__host__global__regs.html#7c41808b0a69ed7d2125eb3afbbf6c14">haint</a>);
+<a name="l01832"></a>01832 
+<a name="l01833"></a>01833                 <span class="comment">/* Read HCINT */</span>
+<a name="l01834"></a>01834                 hcint.<a class="code" href="unionhcint__data.html#05a82fa7693f875622db744716d7f73e">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#0dfd5bae537d58e13788508dc719480d">hcint</a>);
+<a name="l01835"></a>01835 
+<a name="l01836"></a>01836                 <span class="comment">/* Read HCCHAR */</span>
+<a name="l01837"></a>01837                 hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">hcchar</a>);
+<a name="l01838"></a>01838 
+<a name="l01839"></a>01839                 <span class="comment">/* Clear HCINT */</span>
+<a name="l01840"></a>01840                 dwc_write_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#0dfd5bae537d58e13788508dc719480d">hcint</a>, hcint.<a class="code" href="unionhcint__data.html#05a82fa7693f875622db744716d7f73e">d32</a>);
+<a name="l01841"></a>01841 
+<a name="l01842"></a>01842                 <span class="comment">/* Clear HAINT */</span>
+<a name="l01843"></a>01843                 dwc_write_reg32(&amp;hc_global_regs-&gt;<a class="code" href="structdwc__otg__host__global__regs.html#7c41808b0a69ed7d2125eb3afbbf6c14">haint</a>, haint.<a class="code" href="unionhaint__data.html#c83834650d2981b44274a89dda63a0f5">d32</a>);
+<a name="l01844"></a>01844 
+<a name="l01845"></a>01845                 <span class="comment">/* Clear GINTSTS */</span>
+<a name="l01846"></a>01846                 dwc_write_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>, gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a>);
+<a name="l01847"></a>01847 
+<a name="l01848"></a>01848                 hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">hcchar</a>);
+<a name="l01849"></a>01849         }
+<a name="l01850"></a>01850 
+<a name="l01851"></a>01851         <span class="comment">/* Set HCTSIZ */</span>
+<a name="l01852"></a>01852         hctsiz.<a class="code" href="unionhctsiz__data.html#fb41950555c60c6015294bdefe9cd39d">d32</a> = 0;
+<a name="l01853"></a>01853         hctsiz.<a class="code" href="unionhctsiz__data.html#8967fa90c651bce44a3cbe90c44cf638">b</a>.<a class="code" href="unionhctsiz__data.html#6ad01d874d77aa4382f71fa68eaec12d">xfersize</a> = 0;
+<a name="l01854"></a>01854         hctsiz.<a class="code" href="unionhctsiz__data.html#8967fa90c651bce44a3cbe90c44cf638">b</a>.<a class="code" href="unionhctsiz__data.html#3ea18df5a98d33a6f8fa786252a0205b">pktcnt</a> = 1;
+<a name="l01855"></a>01855         hctsiz.<a class="code" href="unionhctsiz__data.html#8967fa90c651bce44a3cbe90c44cf638">b</a>.<a class="code" href="unionhctsiz__data.html#d8b17af02c244e47ca0c38f933a6b3f0">pid</a> = <a class="code" href="dwc__otg__cil_8h.html#e623eb446c55928b324e9636111315e1">DWC_OTG_HC_PID_DATA1</a>;
+<a name="l01856"></a>01856         dwc_write_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#c6173f823ba754d9f9549422b6380ca2">hctsiz</a>, hctsiz.<a class="code" href="unionhctsiz__data.html#fb41950555c60c6015294bdefe9cd39d">d32</a>);
+<a name="l01857"></a>01857 
+<a name="l01858"></a>01858         <span class="comment">/* Set HCCHAR */</span>
+<a name="l01859"></a>01859         hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">hcchar</a>);
+<a name="l01860"></a>01860         hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#df4deee52d932ab29e5d077cde77cbfc">eptype</a> = <a class="code" href="dwc__otg__cil_8h.html#64e5cd756330f5adab79b25cc8067bdc">DWC_OTG_EP_TYPE_CONTROL</a>;
+<a name="l01861"></a>01861         hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#11f1b16e50f90806f90953bb979d4e77">epdir</a> = 0;
+<a name="l01862"></a>01862         hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#1597f36b85006e643aaf6f4d503bebc9">epnum</a> = 0;
+<a name="l01863"></a>01863         hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#47d11a5e62f69534d8ac0606aa7ffe7d">mps</a> = 8;
+<a name="l01864"></a>01864         hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#994a5305780edb0c4fe159b6cc7b14ae">chen</a> = 1;
+<a name="l01865"></a>01865         dwc_write_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">hcchar</a>, hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a>);
+<a name="l01866"></a>01866 
+<a name="l01867"></a>01867         gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a> = dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>);
+<a name="l01868"></a>01868 
+<a name="l01869"></a>01869         <span class="comment">/* Wait for host channel interrupt */</span>
+<a name="l01870"></a>01870         <span class="keywordflow">do</span> {
+<a name="l01871"></a>01871                 gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a> = dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>);
+<a name="l01872"></a>01872         } <span class="keywordflow">while</span> (gintsts.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#e02f1a50b20ed1c4248fd76e155147e8">hcintr</a> == 0);
+<a name="l01873"></a>01873 
+<a name="l01874"></a>01874 
+<a name="l01875"></a>01875         <span class="comment">/* Disable HCINTs */</span>
+<a name="l01876"></a>01876         dwc_write_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#830aa61c1d4326823662168ea7359205">hcintmsk</a>, 0x0000);
+<a name="l01877"></a>01877 
+<a name="l01878"></a>01878         <span class="comment">/* Disable HAINTs */</span>
+<a name="l01879"></a>01879         dwc_write_reg32(&amp;hc_global_regs-&gt;<a class="code" href="structdwc__otg__host__global__regs.html#317f5059d4c2dc91da041f5c0a4819fc">haintmsk</a>, 0x0000);
+<a name="l01880"></a>01880 
+<a name="l01881"></a>01881         <span class="comment">/* Read HAINT */</span>
+<a name="l01882"></a>01882         haint.<a class="code" href="unionhaint__data.html#c83834650d2981b44274a89dda63a0f5">d32</a> = dwc_read_reg32(&amp;hc_global_regs-&gt;<a class="code" href="structdwc__otg__host__global__regs.html#7c41808b0a69ed7d2125eb3afbbf6c14">haint</a>);
+<a name="l01883"></a>01883 
+<a name="l01884"></a>01884         <span class="comment">/* Read HCINT */</span>
+<a name="l01885"></a>01885         hcint.<a class="code" href="unionhcint__data.html#05a82fa7693f875622db744716d7f73e">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#0dfd5bae537d58e13788508dc719480d">hcint</a>);
+<a name="l01886"></a>01886 
+<a name="l01887"></a>01887         <span class="comment">/* Read HCCHAR */</span>
+<a name="l01888"></a>01888         hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">hcchar</a>);
+<a name="l01889"></a>01889 
+<a name="l01890"></a>01890         <span class="comment">/* Clear HCINT */</span>
+<a name="l01891"></a>01891         dwc_write_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#0dfd5bae537d58e13788508dc719480d">hcint</a>, hcint.<a class="code" href="unionhcint__data.html#05a82fa7693f875622db744716d7f73e">d32</a>);
+<a name="l01892"></a>01892 
+<a name="l01893"></a>01893         <span class="comment">/* Clear HAINT */</span>
+<a name="l01894"></a>01894         dwc_write_reg32(&amp;hc_global_regs-&gt;<a class="code" href="structdwc__otg__host__global__regs.html#7c41808b0a69ed7d2125eb3afbbf6c14">haint</a>, haint.<a class="code" href="unionhaint__data.html#c83834650d2981b44274a89dda63a0f5">d32</a>);
+<a name="l01895"></a>01895 
+<a name="l01896"></a>01896         <span class="comment">/* Clear GINTSTS */</span>
+<a name="l01897"></a>01897         dwc_write_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>, gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a>);
+<a name="l01898"></a>01898 
+<a name="l01899"></a>01899         <span class="comment">/* Read GINTSTS */</span>
+<a name="l01900"></a>01900         gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a> = dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>);
+<a name="l01901"></a>01901 }
+<a name="l01902"></a>01902 <span class="preprocessor">#endif</span>
+<a name="l01903"></a>01903 <span class="preprocessor"></span>
+<a name="l01905"></a><a class="code" href="dwc__otg__hcd__if_8h.html#e3bd4e9d1f641cdd29df6633bfb1ebd2">01905</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd_8c.html#e3bd4e9d1f641cdd29df6633bfb1ebd2">dwc_otg_hcd_hub_control</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * <a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>,
+<a name="l01906"></a>01906                             uint16_t typeReq,
+<a name="l01907"></a>01907                             uint16_t wValue,
+<a name="l01908"></a>01908                             uint16_t wIndex, uint8_t * buf, uint16_t wLength)
+<a name="l01909"></a>01909 {
+<a name="l01910"></a>01910         <span class="keywordtype">int</span> retval = 0;
+<a name="l01911"></a>01911 
+<a name="l01912"></a>01912         <a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if = dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>;
+<a name="l01913"></a>01913         usb_hub_descriptor_t *hub_desc;
+<a name="l01914"></a>01914         <a class="code" href="unionhprt0__data.html">hprt0_data_t</a> hprt0 = {.d32 = 0 };
+<a name="l01915"></a>01915 
+<a name="l01916"></a>01916         uint32_t port_status;
+<a name="l01917"></a>01917 
+<a name="l01918"></a>01918         <span class="keywordflow">switch</span> (typeReq) {
+<a name="l01919"></a>01919         <span class="keywordflow">case</span> UCR_CLEAR_HUB_FEATURE:
+<a name="l01920"></a>01920                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#e4a050e176c1c4f556da2b276a8c2b37">DBG_HCD</a>, <span class="stringliteral">"DWC OTG HCD HUB CONTROL - "</span>
+<a name="l01921"></a>01921                             <span class="stringliteral">"ClearHubFeature 0x%x\n"</span>, wValue);
+<a name="l01922"></a>01922                 <span class="keywordflow">switch</span> (wValue) {
+<a name="l01923"></a>01923                 <span class="keywordflow">case</span> UHF_C_HUB_LOCAL_POWER:
+<a name="l01924"></a>01924                 <span class="keywordflow">case</span> UHF_C_HUB_OVER_CURRENT:
+<a name="l01925"></a>01925                         <span class="comment">/* Nothing required here */</span>
+<a name="l01926"></a>01926                         <span class="keywordflow">break</span>;
+<a name="l01927"></a>01927                 <span class="keywordflow">default</span>:
+<a name="l01928"></a>01928                         retval = -DWC_E_INVALID;
+<a name="l01929"></a>01929                         DWC_ERROR(<span class="stringliteral">"DWC OTG HCD - "</span>
+<a name="l01930"></a>01930                                   <span class="stringliteral">"ClearHubFeature request %xh unknown\n"</span>,
+<a name="l01931"></a>01931                                   wValue);
+<a name="l01932"></a>01932                 }
+<a name="l01933"></a>01933                 <span class="keywordflow">break</span>;
+<a name="l01934"></a>01934         <span class="keywordflow">case</span> UCR_CLEAR_PORT_FEATURE:
+<a name="l01935"></a>01935 <span class="preprocessor">#ifdef CONFIG_USB_DWC_OTG_LPM</span>
+<a name="l01936"></a>01936 <span class="preprocessor"></span>                <span class="keywordflow">if</span> (wValue != UHF_PORT_L1)
+<a name="l01937"></a>01937 <span class="preprocessor">#endif</span>
+<a name="l01938"></a>01938 <span class="preprocessor"></span>                        <span class="keywordflow">if</span> (!wIndex || wIndex &gt; 1)
+<a name="l01939"></a>01939                                 <span class="keywordflow">goto</span> error;
+<a name="l01940"></a>01940 
+<a name="l01941"></a>01941                 <span class="keywordflow">switch</span> (wValue) {
+<a name="l01942"></a>01942                 <span class="keywordflow">case</span> UHF_PORT_ENABLE:
+<a name="l01943"></a>01943                         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#2bf62a567355d1ea38814714bd7b57ec">DBG_ANY</a>, <span class="stringliteral">"DWC OTG HCD HUB CONTROL - "</span>
+<a name="l01944"></a>01944                                     <span class="stringliteral">"ClearPortFeature USB_PORT_FEAT_ENABLE\n"</span>);
+<a name="l01945"></a>01945                         hprt0.<a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a> = <a class="code" href="dwc__otg__cil_8h.html#ce67da6af4023cffd25333d20992438e">dwc_otg_read_hprt0</a>(core_if);
+<a name="l01946"></a>01946                         hprt0.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#a964274b5d22e89ca4490f66dff3c763">prtena</a> = 1;
+<a name="l01947"></a>01947                         dwc_write_reg32(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#dc8fe33e0bb3829cafa884d5fc603c4d">hprt0</a>, hprt0.<a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a>);
+<a name="l01948"></a>01948                         <span class="keywordflow">break</span>;
+<a name="l01949"></a>01949                 <span class="keywordflow">case</span> UHF_PORT_SUSPEND:
+<a name="l01950"></a>01950                         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(DBG_HCD, <span class="stringliteral">"DWC OTG HCD HUB CONTROL - "</span>
+<a name="l01951"></a>01951                                     <span class="stringliteral">"ClearPortFeature USB_PORT_FEAT_SUSPEND\n"</span>);
+<a name="l01952"></a>01952 
+<a name="l01953"></a>01953                         dwc_write_reg32(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#348ed2c9aeae6fc608f1bb813978b3f9">pcgcctl</a>, 0);
+<a name="l01954"></a>01954                         dwc_mdelay(5);
+<a name="l01955"></a>01955 
+<a name="l01956"></a>01956                         hprt0.<a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a> = <a class="code" href="dwc__otg__cil_8h.html#ce67da6af4023cffd25333d20992438e">dwc_otg_read_hprt0</a>(core_if);
+<a name="l01957"></a>01957                         hprt0.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#3f5961529636a3891a4ca9421dd535fa">prtres</a> = 1;
+<a name="l01958"></a>01958                         dwc_write_reg32(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#dc8fe33e0bb3829cafa884d5fc603c4d">hprt0</a>, hprt0.<a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a>);
+<a name="l01959"></a>01959                         hprt0.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#e7fe71d6c465ae002211c24a6ba359d2">prtsusp</a> = 0;
+<a name="l01960"></a>01960                         <span class="comment">/* Clear Resume bit */</span>
+<a name="l01961"></a>01961                         dwc_mdelay(100);
+<a name="l01962"></a>01962                         hprt0.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#3f5961529636a3891a4ca9421dd535fa">prtres</a> = 0;
+<a name="l01963"></a>01963                         dwc_write_reg32(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#dc8fe33e0bb3829cafa884d5fc603c4d">hprt0</a>, hprt0.<a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a>);
+<a name="l01964"></a>01964                         <span class="keywordflow">break</span>;
+<a name="l01965"></a>01965 <span class="preprocessor">#ifdef CONFIG_USB_DWC_OTG_LPM</span>
+<a name="l01966"></a>01966 <span class="preprocessor"></span>                <span class="keywordflow">case</span> UHF_PORT_L1:
+<a name="l01967"></a>01967                         {
+<a name="l01968"></a>01968                                 <a class="code" href="unionpcgcctl__data.html">pcgcctl_data_t</a> pcgcctl = {.d32 = 0 };
+<a name="l01969"></a>01969                                 <a class="code" href="unionglpmctl__data.html">glpmcfg_data_t</a> lpmcfg = {.d32 = 0 };
+<a name="l01970"></a>01970 
+<a name="l01971"></a>01971                                 lpmcfg.<a class="code" href="unionglpmctl__data.html#cd41461734ff898209bfb64057ef2eb8">d32</a> =
+<a name="l01972"></a>01972                                     dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;
+<a name="l01973"></a>01973                                                    glpmcfg);
+<a name="l01974"></a>01974                                 lpmcfg.<a class="code" href="unionglpmctl__data.html#bd3cc34c338226ff1cd89448f7590ff1">b</a>.<a class="code" href="unionglpmctl__data.html#63e912a05b8d29872b92263ca616fec8">en_utmi_sleep</a> = 0;
+<a name="l01975"></a>01975                                 lpmcfg.<a class="code" href="unionglpmctl__data.html#bd3cc34c338226ff1cd89448f7590ff1">b</a>.<a class="code" href="unionglpmctl__data.html#e2ceea4bfe468c7b3c800235d7ffd5d2">hird_thres</a> &amp;= (~(1 &lt;&lt; 4));
+<a name="l01976"></a>01976                                 lpmcfg.<a class="code" href="unionglpmctl__data.html#bd3cc34c338226ff1cd89448f7590ff1">b</a>.<a class="code" href="unionglpmctl__data.html#241ff25a215f16ac29b3bb6d9f4943ed">prt_sleep_sts</a> = 1;
+<a name="l01977"></a>01977                                 dwc_write_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;
+<a name="l01978"></a>01978                                                 glpmcfg, lpmcfg.<a class="code" href="unionglpmctl__data.html#cd41461734ff898209bfb64057ef2eb8">d32</a>);
+<a name="l01979"></a>01979 
+<a name="l01980"></a>01980                                 <span class="comment">/* Clear Enbl_L1Gating bit. */</span>
+<a name="l01981"></a>01981                                 pcgcctl.<a class="code" href="unionpcgcctl__data.html#f2bb76709d0ab9d08280eafb78a36279">b</a>.<a class="code" href="unionpcgcctl__data.html#6c18ad3b71ad92e548d0c6d64cc88734">enbl_sleep_gating</a> = 1;
+<a name="l01982"></a>01982                                 dwc_modify_reg32(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#348ed2c9aeae6fc608f1bb813978b3f9">pcgcctl</a>, pcgcctl.<a class="code" href="unionpcgcctl__data.html#abe048ee884143501929b27d94c52db7">d32</a>,
+<a name="l01983"></a>01983                                                  0);
+<a name="l01984"></a>01984 
+<a name="l01985"></a>01985                                 dwc_mdelay(5);
+<a name="l01986"></a>01986 
+<a name="l01987"></a>01987                                 hprt0.<a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a> = <a class="code" href="dwc__otg__cil_8h.html#ce67da6af4023cffd25333d20992438e">dwc_otg_read_hprt0</a>(core_if);
+<a name="l01988"></a>01988                                 hprt0.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#3f5961529636a3891a4ca9421dd535fa">prtres</a> = 1;
+<a name="l01989"></a>01989                                 dwc_write_reg32(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#dc8fe33e0bb3829cafa884d5fc603c4d">hprt0</a>,
+<a name="l01990"></a>01990                                                 hprt0.<a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a>);
+<a name="l01991"></a>01991                                 <span class="comment">/* This bit will be cleared in wakeup interrupt handle */</span>
+<a name="l01992"></a>01992                                 <span class="keywordflow">break</span>;
+<a name="l01993"></a>01993                         }
+<a name="l01994"></a>01994 <span class="preprocessor">#endif</span>
+<a name="l01995"></a>01995 <span class="preprocessor"></span>                <span class="keywordflow">case</span> UHF_PORT_POWER:
+<a name="l01996"></a>01996                         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(DBG_HCD, <span class="stringliteral">"DWC OTG HCD HUB CONTROL - "</span>
+<a name="l01997"></a>01997                                     <span class="stringliteral">"ClearPortFeature USB_PORT_FEAT_POWER\n"</span>);
+<a name="l01998"></a>01998                         hprt0.<a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a> = <a class="code" href="dwc__otg__cil_8h.html#ce67da6af4023cffd25333d20992438e">dwc_otg_read_hprt0</a>(core_if);
+<a name="l01999"></a>01999                         hprt0.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#010bd8fb208ef4eeaa288b28f8f8c3a4">prtpwr</a> = 0;
+<a name="l02000"></a>02000                         dwc_write_reg32(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#dc8fe33e0bb3829cafa884d5fc603c4d">hprt0</a>, hprt0.<a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a>);
+<a name="l02001"></a>02001                         <span class="keywordflow">break</span>;
+<a name="l02002"></a>02002                 <span class="keywordflow">case</span> UHF_PORT_INDICATOR:
+<a name="l02003"></a>02003                         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(DBG_HCD, <span class="stringliteral">"DWC OTG HCD HUB CONTROL - "</span>
+<a name="l02004"></a>02004                                     <span class="stringliteral">"ClearPortFeature USB_PORT_FEAT_INDICATOR\n"</span>);
+<a name="l02005"></a>02005                         <span class="comment">/* Port inidicator not supported */</span>
+<a name="l02006"></a>02006                         <span class="keywordflow">break</span>;
+<a name="l02007"></a>02007                 <span class="keywordflow">case</span> UHF_C_PORT_CONNECTION:
+<a name="l02008"></a>02008                         <span class="comment">/* Clears drivers internal connect status change</span>
+<a name="l02009"></a>02009 <span class="comment">                         * flag */</span>
+<a name="l02010"></a>02010                         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(DBG_HCD, <span class="stringliteral">"DWC OTG HCD HUB CONTROL - "</span>
+<a name="l02011"></a>02011                                     <span class="stringliteral">"ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n"</span>);
+<a name="l02012"></a>02012                         dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#9aaf2a112f5794f92dedd826342bd637">flags</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#76f573861d9316238ded198c58c228c7">b</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#cd31ac4b9658265e90773448f354f0e1">port_connect_status_change</a> = 0;
+<a name="l02013"></a>02013                         <span class="keywordflow">break</span>;
+<a name="l02014"></a>02014                 <span class="keywordflow">case</span> UHF_C_PORT_RESET:
+<a name="l02015"></a>02015                         <span class="comment">/* Clears the driver's internal Port Reset Change</span>
+<a name="l02016"></a>02016 <span class="comment">                         * flag */</span>
+<a name="l02017"></a>02017                         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(DBG_HCD, <span class="stringliteral">"DWC OTG HCD HUB CONTROL - "</span>
+<a name="l02018"></a>02018                                     <span class="stringliteral">"ClearPortFeature USB_PORT_FEAT_C_RESET\n"</span>);
+<a name="l02019"></a>02019                         dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#9aaf2a112f5794f92dedd826342bd637">flags</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#76f573861d9316238ded198c58c228c7">b</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#d0d63f32ed35315e8a02549521fb386e">port_reset_change</a> = 0;
+<a name="l02020"></a>02020                         <span class="keywordflow">break</span>;
+<a name="l02021"></a>02021                 <span class="keywordflow">case</span> UHF_C_PORT_ENABLE:
+<a name="l02022"></a>02022                         <span class="comment">/* Clears the driver's internal Port</span>
+<a name="l02023"></a>02023 <span class="comment">                         * Enable/Disable Change flag */</span>
+<a name="l02024"></a>02024                         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(DBG_HCD, <span class="stringliteral">"DWC OTG HCD HUB CONTROL - "</span>
+<a name="l02025"></a>02025                                     <span class="stringliteral">"ClearPortFeature USB_PORT_FEAT_C_ENABLE\n"</span>);
+<a name="l02026"></a>02026                         dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#9aaf2a112f5794f92dedd826342bd637">flags</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#76f573861d9316238ded198c58c228c7">b</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#d222ae08372109a312f6649f77b650e8">port_enable_change</a> = 0;
+<a name="l02027"></a>02027                         <span class="keywordflow">break</span>;
+<a name="l02028"></a>02028                 <span class="keywordflow">case</span> UHF_C_PORT_SUSPEND:
+<a name="l02029"></a>02029                         <span class="comment">/* Clears the driver's internal Port Suspend</span>
+<a name="l02030"></a>02030 <span class="comment">                         * Change flag, which is set when resume signaling on</span>
+<a name="l02031"></a>02031 <span class="comment">                         * the host port is complete */</span>
+<a name="l02032"></a>02032                         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(DBG_HCD, <span class="stringliteral">"DWC OTG HCD HUB CONTROL - "</span>
+<a name="l02033"></a>02033                                     <span class="stringliteral">"ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n"</span>);
+<a name="l02034"></a>02034                         dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#9aaf2a112f5794f92dedd826342bd637">flags</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#76f573861d9316238ded198c58c228c7">b</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#2a6e323cb4c01153aff1adc6269c74c7">port_suspend_change</a> = 0;
+<a name="l02035"></a>02035                         <span class="keywordflow">break</span>;
+<a name="l02036"></a>02036 <span class="preprocessor">#ifdef CONFIG_USB_DWC_OTG_LPM</span>
+<a name="l02037"></a>02037 <span class="preprocessor"></span>                <span class="keywordflow">case</span> UHF_C_PORT_L1:
+<a name="l02038"></a>02038                         dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#9aaf2a112f5794f92dedd826342bd637">flags</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#76f573861d9316238ded198c58c228c7">b</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#1900375ccea165f0efc40725f507a0bf">port_l1_change</a> = 0;
+<a name="l02039"></a>02039                         <span class="keywordflow">break</span>;
+<a name="l02040"></a>02040 <span class="preprocessor">#endif</span>
+<a name="l02041"></a>02041 <span class="preprocessor"></span>                <span class="keywordflow">case</span> UHF_C_PORT_OVER_CURRENT:
+<a name="l02042"></a>02042                         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(DBG_HCD, <span class="stringliteral">"DWC OTG HCD HUB CONTROL - "</span>
+<a name="l02043"></a>02043                                     <span class="stringliteral">"ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n"</span>);
+<a name="l02044"></a>02044                         dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#9aaf2a112f5794f92dedd826342bd637">flags</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#76f573861d9316238ded198c58c228c7">b</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#bc96cf12e2bc5b61ce05f15ae3297bd6">port_over_current_change</a> = 0;
+<a name="l02045"></a>02045                         <span class="keywordflow">break</span>;
+<a name="l02046"></a>02046                 <span class="keywordflow">default</span>:
+<a name="l02047"></a>02047                         retval = -DWC_E_INVALID;
+<a name="l02048"></a>02048                         DWC_ERROR(<span class="stringliteral">"DWC OTG HCD - "</span>
+<a name="l02049"></a>02049                                   <span class="stringliteral">"ClearPortFeature request %xh "</span>
+<a name="l02050"></a>02050                                   <span class="stringliteral">"unknown or unsupported\n"</span>, wValue);
+<a name="l02051"></a>02051                 }
+<a name="l02052"></a>02052                 <span class="keywordflow">break</span>;
+<a name="l02053"></a>02053         <span class="keywordflow">case</span> UCR_GET_HUB_DESCRIPTOR:
+<a name="l02054"></a>02054                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(DBG_HCD, <span class="stringliteral">"DWC OTG HCD HUB CONTROL - "</span>
+<a name="l02055"></a>02055                             <span class="stringliteral">"GetHubDescriptor\n"</span>);
+<a name="l02056"></a>02056                 hub_desc = (usb_hub_descriptor_t *) buf;
+<a name="l02057"></a>02057                 hub_desc-&gt;bDescLength = 9;
+<a name="l02058"></a>02058                 hub_desc-&gt;bDescriptorType = 0x29;
+<a name="l02059"></a>02059                 hub_desc-&gt;bNbrPorts = 1;
+<a name="l02060"></a>02060                 USETW(hub_desc-&gt;wHubCharacteristics, 0x08);
+<a name="l02061"></a>02061                 hub_desc-&gt;bPwrOn2PwrGood = 1;
+<a name="l02062"></a>02062                 hub_desc-&gt;bHubContrCurrent = 0;
+<a name="l02063"></a>02063                 hub_desc-&gt;DeviceRemovable[0] = 0;
+<a name="l02064"></a>02064                 hub_desc-&gt;DeviceRemovable[1] = 0xff;
+<a name="l02065"></a>02065                 <span class="keywordflow">break</span>;
+<a name="l02066"></a>02066         <span class="keywordflow">case</span> UCR_GET_HUB_STATUS:
+<a name="l02067"></a>02067                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(DBG_HCD, <span class="stringliteral">"DWC OTG HCD HUB CONTROL - "</span>
+<a name="l02068"></a>02068                             <span class="stringliteral">"GetHubStatus\n"</span>);
+<a name="l02069"></a>02069                 DWC_MEMSET(buf, 0, 4);
+<a name="l02070"></a>02070                 <span class="keywordflow">break</span>;
+<a name="l02071"></a>02071         <span class="keywordflow">case</span> UCR_GET_PORT_STATUS:
+<a name="l02072"></a>02072                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(DBG_HCD, <span class="stringliteral">"DWC OTG HCD HUB CONTROL - "</span>
+<a name="l02073"></a>02073                             <span class="stringliteral">"GetPortStatus\n"</span>);
+<a name="l02074"></a>02074                 <span class="keywordflow">if</span> (!wIndex || wIndex &gt; 1)
+<a name="l02075"></a>02075                         <span class="keywordflow">goto</span> error;
+<a name="l02076"></a>02076 
+<a name="l02077"></a>02077                 port_status = 0;
+<a name="l02078"></a>02078 
+<a name="l02079"></a>02079                 <span class="keywordflow">if</span> (dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#9aaf2a112f5794f92dedd826342bd637">flags</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#76f573861d9316238ded198c58c228c7">b</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#cd31ac4b9658265e90773448f354f0e1">port_connect_status_change</a>)
+<a name="l02080"></a>02080                         port_status |= (1 &lt;&lt; UHF_C_PORT_CONNECTION);
+<a name="l02081"></a>02081 
+<a name="l02082"></a>02082                 <span class="keywordflow">if</span> (dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#9aaf2a112f5794f92dedd826342bd637">flags</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#76f573861d9316238ded198c58c228c7">b</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#d222ae08372109a312f6649f77b650e8">port_enable_change</a>)
+<a name="l02083"></a>02083                         port_status |= (1 &lt;&lt; UHF_C_PORT_ENABLE);
+<a name="l02084"></a>02084 
+<a name="l02085"></a>02085                 <span class="keywordflow">if</span> (dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#9aaf2a112f5794f92dedd826342bd637">flags</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#76f573861d9316238ded198c58c228c7">b</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#2a6e323cb4c01153aff1adc6269c74c7">port_suspend_change</a>)
+<a name="l02086"></a>02086                         port_status |= (1 &lt;&lt; UHF_C_PORT_SUSPEND);
+<a name="l02087"></a>02087 
+<a name="l02088"></a>02088                 <span class="keywordflow">if</span> (dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#9aaf2a112f5794f92dedd826342bd637">flags</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#76f573861d9316238ded198c58c228c7">b</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#1900375ccea165f0efc40725f507a0bf">port_l1_change</a>)
+<a name="l02089"></a>02089                         port_status |= (1 &lt;&lt; UHF_C_PORT_L1);
+<a name="l02090"></a>02090 
+<a name="l02091"></a>02091                 <span class="keywordflow">if</span> (dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#9aaf2a112f5794f92dedd826342bd637">flags</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#76f573861d9316238ded198c58c228c7">b</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#d0d63f32ed35315e8a02549521fb386e">port_reset_change</a>) {
+<a name="l02092"></a>02092                         port_status |= (1 &lt;&lt; UHF_C_PORT_RESET);
+<a name="l02093"></a>02093                 }
+<a name="l02094"></a>02094 
+<a name="l02095"></a>02095                 <span class="keywordflow">if</span> (dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#9aaf2a112f5794f92dedd826342bd637">flags</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#76f573861d9316238ded198c58c228c7">b</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#bc96cf12e2bc5b61ce05f15ae3297bd6">port_over_current_change</a>) {
+<a name="l02096"></a>02096                         DWC_ERROR(<span class="stringliteral">"Device Not Supported\n"</span>);
+<a name="l02097"></a>02097                         port_status |= (1 &lt;&lt; UHF_C_PORT_OVER_CURRENT);
+<a name="l02098"></a>02098                 }
+<a name="l02099"></a>02099 
+<a name="l02100"></a>02100                 <span class="keywordflow">if</span> (!dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#9aaf2a112f5794f92dedd826342bd637">flags</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#76f573861d9316238ded198c58c228c7">b</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#9314ac02ed140807687793b512f78c63">port_connect_status</a>) {
+<a name="l02101"></a>02101                         <span class="comment">/*</span>
+<a name="l02102"></a>02102 <span class="comment">                         * The port is disconnected, which means the core is</span>
+<a name="l02103"></a>02103 <span class="comment">                         * either in device mode or it soon will be. Just</span>
+<a name="l02104"></a>02104 <span class="comment">                         * return 0's for the remainder of the port status</span>
+<a name="l02105"></a>02105 <span class="comment">                         * since the port register can't be read if the core</span>
+<a name="l02106"></a>02106 <span class="comment">                         * is in device mode.</span>
+<a name="l02107"></a>02107 <span class="comment">                         */</span>
+<a name="l02108"></a>02108                         *((__le32 *) buf) = dwc_cpu_to_le32(&amp;port_status);
+<a name="l02109"></a>02109                         <span class="keywordflow">break</span>;
+<a name="l02110"></a>02110                 }
+<a name="l02111"></a>02111 
+<a name="l02112"></a>02112                 hprt0.<a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a> = dwc_read_reg32(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#dc8fe33e0bb3829cafa884d5fc603c4d">hprt0</a>);
+<a name="l02113"></a>02113                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"  HPRT0: 0x%08x\n"</span>, hprt0.<a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a>);
+<a name="l02114"></a>02114 
+<a name="l02115"></a>02115                 <span class="keywordflow">if</span> (hprt0.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#39b2dee944be8ec96857a3b43d203390">prtconnsts</a>)
+<a name="l02116"></a>02116                         port_status |= (1 &lt;&lt; UHF_PORT_CONNECTION);
+<a name="l02117"></a>02117 
+<a name="l02118"></a>02118                 <span class="keywordflow">if</span> (hprt0.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#a964274b5d22e89ca4490f66dff3c763">prtena</a>)
+<a name="l02119"></a>02119                         port_status |= (1 &lt;&lt; UHF_PORT_ENABLE);
+<a name="l02120"></a>02120 
+<a name="l02121"></a>02121                 <span class="keywordflow">if</span> (hprt0.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#e7fe71d6c465ae002211c24a6ba359d2">prtsusp</a>)
+<a name="l02122"></a>02122                         port_status |= (1 &lt;&lt; UHF_PORT_SUSPEND);
+<a name="l02123"></a>02123 
+<a name="l02124"></a>02124                 <span class="keywordflow">if</span> (hprt0.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#4d8f8b654c26760791614ccbc43f180c">prtovrcurract</a>)
+<a name="l02125"></a>02125                         port_status |= (1 &lt;&lt; UHF_PORT_OVER_CURRENT);
+<a name="l02126"></a>02126 
+<a name="l02127"></a>02127                 <span class="keywordflow">if</span> (hprt0.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#714a31048710164370292124795a9a9b">prtrst</a>)
+<a name="l02128"></a>02128                         port_status |= (1 &lt;&lt; UHF_PORT_RESET);
+<a name="l02129"></a>02129 
+<a name="l02130"></a>02130                 <span class="keywordflow">if</span> (hprt0.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#010bd8fb208ef4eeaa288b28f8f8c3a4">prtpwr</a>)
+<a name="l02131"></a>02131                         port_status |= (1 &lt;&lt; UHF_PORT_POWER);
+<a name="l02132"></a>02132 
+<a name="l02133"></a>02133                 <span class="keywordflow">if</span> (hprt0.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#59f1c27b8c912de0237d2d2974fc2a22">prtspd</a> == <a class="code" href="dwc__otg__regs_8h.html#4556f79078df2164a8162fa8144142a0">DWC_HPRT0_PRTSPD_HIGH_SPEED</a>)
+<a name="l02134"></a>02134                         port_status |= (1 &lt;&lt; UHF_PORT_HIGH_SPEED);
+<a name="l02135"></a>02135                 <span class="keywordflow">else</span> <span class="keywordflow">if</span> (hprt0.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#59f1c27b8c912de0237d2d2974fc2a22">prtspd</a> == <a class="code" href="dwc__otg__regs_8h.html#db9e36d1ab76c334f6e004ee270bd36f">DWC_HPRT0_PRTSPD_LOW_SPEED</a>)
+<a name="l02136"></a>02136                         port_status |= (1 &lt;&lt; UHF_PORT_LOW_SPEED);
+<a name="l02137"></a>02137 
+<a name="l02138"></a>02138                 <span class="keywordflow">if</span> (hprt0.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#c61d714ff8f0bc62767342523347ba66">prttstctl</a>)
+<a name="l02139"></a>02139                         port_status |= (1 &lt;&lt; UHF_PORT_TEST);
+<a name="l02140"></a>02140                 <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#87d643973839554bac437d283a462e00">dwc_otg_get_lpm_portsleepstatus</a>(dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>)) {
+<a name="l02141"></a>02141                         port_status |= (1 &lt;&lt; UHF_PORT_L1);
+<a name="l02142"></a>02142                 }
+<a name="l02143"></a>02143 
+<a name="l02144"></a>02144                 <span class="comment">/* USB_PORT_FEAT_INDICATOR unsupported always 0 */</span>
+<a name="l02145"></a>02145 
+<a name="l02146"></a>02146                 *((__le32 *) buf) = dwc_cpu_to_le32(&amp;port_status);
+<a name="l02147"></a>02147 
+<a name="l02148"></a>02148                 <span class="keywordflow">break</span>;
+<a name="l02149"></a>02149         <span class="keywordflow">case</span> UCR_SET_HUB_FEATURE:
+<a name="l02150"></a>02150                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(DBG_HCD, <span class="stringliteral">"DWC OTG HCD HUB CONTROL - "</span>
+<a name="l02151"></a>02151                             <span class="stringliteral">"SetHubFeature\n"</span>);
+<a name="l02152"></a>02152                 <span class="comment">/* No HUB features supported */</span>
+<a name="l02153"></a>02153                 <span class="keywordflow">break</span>;
+<a name="l02154"></a>02154         <span class="keywordflow">case</span> UCR_SET_PORT_FEATURE:
+<a name="l02155"></a>02155                 <span class="keywordflow">if</span> (wValue != UHF_PORT_TEST &amp;&amp; (!wIndex || wIndex &gt; 1))
+<a name="l02156"></a>02156                         <span class="keywordflow">goto</span> error;
+<a name="l02157"></a>02157 
+<a name="l02158"></a>02158                 <span class="keywordflow">if</span> (!dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#9aaf2a112f5794f92dedd826342bd637">flags</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#76f573861d9316238ded198c58c228c7">b</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#9314ac02ed140807687793b512f78c63">port_connect_status</a>) {
+<a name="l02159"></a>02159                         <span class="comment">/*</span>
+<a name="l02160"></a>02160 <span class="comment">                         * The port is disconnected, which means the core is</span>
+<a name="l02161"></a>02161 <span class="comment">                         * either in device mode or it soon will be. Just</span>
+<a name="l02162"></a>02162 <span class="comment">                         * return without doing anything since the port</span>
+<a name="l02163"></a>02163 <span class="comment">                         * register can't be written if the core is in device</span>
+<a name="l02164"></a>02164 <span class="comment">                         * mode.</span>
+<a name="l02165"></a>02165 <span class="comment">                         */</span>
+<a name="l02166"></a>02166                         <span class="keywordflow">break</span>;
+<a name="l02167"></a>02167                 }
+<a name="l02168"></a>02168 
+<a name="l02169"></a>02169                 <span class="keywordflow">switch</span> (wValue) {
+<a name="l02170"></a>02170                 <span class="keywordflow">case</span> UHF_PORT_SUSPEND:
+<a name="l02171"></a>02171                         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(DBG_HCD, <span class="stringliteral">"DWC OTG HCD HUB CONTROL - "</span>
+<a name="l02172"></a>02172                                     <span class="stringliteral">"SetPortFeature - USB_PORT_FEAT_SUSPEND\n"</span>);
+<a name="l02173"></a>02173                         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__hcd_8c.html#e7d3657931984a1ce1cee5cf47cb08f3">dwc_otg_hcd_otg_port</a>(dwc_otg_hcd) == wIndex &amp;&amp;
+<a name="l02174"></a>02174                             dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#ffefbd33a59a14b8b46406f5aaeaa2f4">fops</a>-&gt;<a class="code" href="structdwc__otg__hcd__function__ops.html#24a2ee2bad4dc517fed62417a2a542d3">get_b_hnp_enable</a>(dwc_otg_hcd)) {
+<a name="l02175"></a>02175                                 <a class="code" href="uniongotgctl__data.html">gotgctl_data_t</a> gotgctl = {.d32 = 0 };
+<a name="l02176"></a>02176                                 gotgctl.b.hstsethnpen = 1;
+<a name="l02177"></a>02177                                 dwc_modify_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;
+<a name="l02178"></a>02178                                                  gotgctl, 0, gotgctl.d32);
+<a name="l02179"></a>02179                                 core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5a5c5c1cf8d870101cc1fffac56d88c0">op_state</a> = <a class="code" href="dwc__otg__cil_8h.html#da9f5eb506da71435e8976ceb38bc14d">A_SUSPEND</a>;
+<a name="l02180"></a>02180                         }
+<a name="l02181"></a>02181                         hprt0.<a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a> = <a class="code" href="dwc__otg__cil_8h.html#ce67da6af4023cffd25333d20992438e">dwc_otg_read_hprt0</a>(core_if);
+<a name="l02182"></a>02182                         hprt0.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#e7fe71d6c465ae002211c24a6ba359d2">prtsusp</a> = 1;
+<a name="l02183"></a>02183                         dwc_write_reg32(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#dc8fe33e0bb3829cafa884d5fc603c4d">hprt0</a>, hprt0.<a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a>);
+<a name="l02184"></a>02184                         {
+<a name="l02185"></a>02185                                 uint64_t flags;
+<a name="l02186"></a>02186                                 <span class="comment">/* Update lx_state */</span>
+<a name="l02187"></a>02187                                 DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#34f29e9c035009476495f7701c1813fd">lock</a>, &amp;flags);
+<a name="l02188"></a>02188                                 core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#2b0701d814069ec69897e08374366c7b">lx_state</a> = <a class="code" href="dwc__otg__cil_8h.html#8442e49b7c783099ac17bda4f8b3bc3cd1fadb6fa31de73e8176316a0e0ba905">DWC_OTG_L2</a>;
+<a name="l02189"></a>02189                                 DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#34f29e9c035009476495f7701c1813fd">lock</a>, flags);
+<a name="l02190"></a>02190                         }
+<a name="l02191"></a>02191                         <span class="comment">/* Suspend the Phy Clock */</span>
+<a name="l02192"></a>02192                         {
+<a name="l02193"></a>02193                                 <a class="code" href="unionpcgcctl__data.html">pcgcctl_data_t</a> pcgcctl = {.d32 = 0 };
+<a name="l02194"></a>02194                                 pcgcctl.<a class="code" href="unionpcgcctl__data.html#f2bb76709d0ab9d08280eafb78a36279">b</a>.<a class="code" href="unionpcgcctl__data.html#bf40184845ef70be8e59b2672cb0bedf">stoppclk</a> = 1;
+<a name="l02195"></a>02195                                 dwc_modify_reg32(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#348ed2c9aeae6fc608f1bb813978b3f9">pcgcctl</a>, 0,
+<a name="l02196"></a>02196                                                  pcgcctl.<a class="code" href="unionpcgcctl__data.html#abe048ee884143501929b27d94c52db7">d32</a>);
+<a name="l02197"></a>02197                         }
+<a name="l02198"></a>02198 
+<a name="l02199"></a>02199                         <span class="comment">/* For HNP the bus must be suspended for at least 200ms. */</span>
+<a name="l02200"></a>02200                         <span class="keywordflow">if</span> (dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#ffefbd33a59a14b8b46406f5aaeaa2f4">fops</a>-&gt;<a class="code" href="structdwc__otg__hcd__function__ops.html#24a2ee2bad4dc517fed62417a2a542d3">get_b_hnp_enable</a>(dwc_otg_hcd)) {
+<a name="l02201"></a>02201                                 dwc_mdelay(200);
+<a name="l02202"></a>02202                         }
+<a name="l02203"></a>02203                         <span class="keywordflow">break</span>;
+<a name="l02204"></a>02204                 <span class="keywordflow">case</span> UHF_PORT_POWER:
+<a name="l02205"></a>02205                         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(DBG_HCD, <span class="stringliteral">"DWC OTG HCD HUB CONTROL - "</span>
+<a name="l02206"></a>02206                                     <span class="stringliteral">"SetPortFeature - USB_PORT_FEAT_POWER\n"</span>);
+<a name="l02207"></a>02207                         hprt0.<a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a> = <a class="code" href="dwc__otg__cil_8h.html#ce67da6af4023cffd25333d20992438e">dwc_otg_read_hprt0</a>(core_if);
+<a name="l02208"></a>02208                         hprt0.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#010bd8fb208ef4eeaa288b28f8f8c3a4">prtpwr</a> = 1;
+<a name="l02209"></a>02209                         dwc_write_reg32(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#dc8fe33e0bb3829cafa884d5fc603c4d">hprt0</a>, hprt0.<a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a>);
+<a name="l02210"></a>02210                         <span class="keywordflow">break</span>;
+<a name="l02211"></a>02211                 <span class="keywordflow">case</span> UHF_PORT_RESET:
+<a name="l02212"></a>02212                         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(DBG_HCD, <span class="stringliteral">"DWC OTG HCD HUB CONTROL - "</span>
+<a name="l02213"></a>02213                                     <span class="stringliteral">"SetPortFeature - USB_PORT_FEAT_RESET\n"</span>);
+<a name="l02214"></a>02214                         {
+<a name="l02215"></a>02215                                 <a class="code" href="unionpcgcctl__data.html">pcgcctl_data_t</a> pcgcctl = {.d32 = 0 };
+<a name="l02216"></a>02216                                 pcgcctl.<a class="code" href="unionpcgcctl__data.html#f2bb76709d0ab9d08280eafb78a36279">b</a>.<a class="code" href="unionpcgcctl__data.html#6c18ad3b71ad92e548d0c6d64cc88734">enbl_sleep_gating</a> = 1;
+<a name="l02217"></a>02217                                 pcgcctl.<a class="code" href="unionpcgcctl__data.html#f2bb76709d0ab9d08280eafb78a36279">b</a>.<a class="code" href="unionpcgcctl__data.html#bf40184845ef70be8e59b2672cb0bedf">stoppclk</a> = 1;
+<a name="l02218"></a>02218                                 dwc_modify_reg32(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#348ed2c9aeae6fc608f1bb813978b3f9">pcgcctl</a>, pcgcctl.<a class="code" href="unionpcgcctl__data.html#abe048ee884143501929b27d94c52db7">d32</a>,
+<a name="l02219"></a>02219                                                  0);
+<a name="l02220"></a>02220                                 dwc_write_reg32(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#348ed2c9aeae6fc608f1bb813978b3f9">pcgcctl</a>, 0);
+<a name="l02221"></a>02221                         }
+<a name="l02222"></a>02222 <span class="preprocessor">#ifdef CONFIG_USB_DWC_OTG_LPM</span>
+<a name="l02223"></a>02223 <span class="preprocessor"></span>                        {
+<a name="l02224"></a>02224                                 <a class="code" href="unionglpmctl__data.html">glpmcfg_data_t</a> lpmcfg;
+<a name="l02225"></a>02225                                 lpmcfg.<a class="code" href="unionglpmctl__data.html#cd41461734ff898209bfb64057ef2eb8">d32</a> =
+<a name="l02226"></a>02226                                     dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;
+<a name="l02227"></a>02227                                                    glpmcfg);
+<a name="l02228"></a>02228                                 <span class="keywordflow">if</span> (lpmcfg.<a class="code" href="unionglpmctl__data.html#bd3cc34c338226ff1cd89448f7590ff1">b</a>.<a class="code" href="unionglpmctl__data.html#241ff25a215f16ac29b3bb6d9f4943ed">prt_sleep_sts</a>) {
+<a name="l02229"></a>02229                                         lpmcfg.<a class="code" href="unionglpmctl__data.html#bd3cc34c338226ff1cd89448f7590ff1">b</a>.<a class="code" href="unionglpmctl__data.html#63e912a05b8d29872b92263ca616fec8">en_utmi_sleep</a> = 0;
+<a name="l02230"></a>02230                                         lpmcfg.<a class="code" href="unionglpmctl__data.html#bd3cc34c338226ff1cd89448f7590ff1">b</a>.<a class="code" href="unionglpmctl__data.html#e2ceea4bfe468c7b3c800235d7ffd5d2">hird_thres</a> &amp;= (~(1 &lt;&lt; 4));
+<a name="l02231"></a>02231                                         dwc_write_reg32(&amp;core_if-&gt;
+<a name="l02232"></a>02232                                                         core_global_regs-&gt;
+<a name="l02233"></a>02233                                                         glpmcfg, lpmcfg.<a class="code" href="unionglpmctl__data.html#cd41461734ff898209bfb64057ef2eb8">d32</a>);
+<a name="l02234"></a>02234                                         dwc_mdelay(1);
+<a name="l02235"></a>02235                                 }
+<a name="l02236"></a>02236                         }
+<a name="l02237"></a>02237 <span class="preprocessor">#endif</span>
+<a name="l02238"></a>02238 <span class="preprocessor"></span>                        hprt0.<a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a> = <a class="code" href="dwc__otg__cil_8h.html#ce67da6af4023cffd25333d20992438e">dwc_otg_read_hprt0</a>(core_if);
+<a name="l02239"></a>02239                         <span class="comment">/* When B-Host the Port reset bit is set in</span>
+<a name="l02240"></a>02240 <span class="comment">                         * the Start HCD Callback function, so that</span>
+<a name="l02241"></a>02241 <span class="comment">                         * the reset is started within 1ms of the HNP</span>
+<a name="l02242"></a>02242 <span class="comment">                         * success interrupt. */</span>
+<a name="l02243"></a>02243                         <span class="keywordflow">if</span> (!<a class="code" href="dwc__otg__hcd_8c.html#ca25b33b440a4ef112ee459c26c14adc">dwc_otg_hcd_is_b_host</a>(dwc_otg_hcd)) {
+<a name="l02244"></a>02244                                 hprt0.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#714a31048710164370292124795a9a9b">prtrst</a> = 1;
+<a name="l02245"></a>02245                                 dwc_write_reg32(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#dc8fe33e0bb3829cafa884d5fc603c4d">hprt0</a>,
+<a name="l02246"></a>02246                                                 hprt0.<a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a>);
+<a name="l02247"></a>02247                         }
+<a name="l02248"></a>02248                         <span class="comment">/* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */</span>
+<a name="l02249"></a>02249                         dwc_mdelay(60);
+<a name="l02250"></a>02250                         hprt0.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#714a31048710164370292124795a9a9b">prtrst</a> = 0;
+<a name="l02251"></a>02251                         dwc_write_reg32(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#dc8fe33e0bb3829cafa884d5fc603c4d">hprt0</a>, hprt0.<a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a>);
+<a name="l02252"></a>02252                         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#2b0701d814069ec69897e08374366c7b">lx_state</a> = <a class="code" href="dwc__otg__cil_8h.html#8442e49b7c783099ac17bda4f8b3bc3c9743a36d9b0b8c66a11a0714fdd27fb5">DWC_OTG_L0</a>; <span class="comment">/* Now back to the on state */</span>
+<a name="l02253"></a>02253                         <span class="keywordflow">break</span>;
+<a name="l02254"></a>02254 <span class="preprocessor">#ifdef DWC_HS_ELECT_TST</span>
+<a name="l02255"></a>02255 <span class="preprocessor"></span>                <span class="keywordflow">case</span> UHF_PORT_TEST:
+<a name="l02256"></a>02256                         {
+<a name="l02257"></a>02257                                 uint32_t t;
+<a name="l02258"></a>02258                                 <a class="code" href="uniongintmsk__data.html">gintmsk_data_t</a> gintmsk;
+<a name="l02259"></a>02259 
+<a name="l02260"></a>02260                                 t = (wIndex &gt;&gt; 8);      <span class="comment">/* MSB wIndex USB */</span>
+<a name="l02261"></a>02261                                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(DBG_HCD,
+<a name="l02262"></a>02262                                             <span class="stringliteral">"DWC OTG HCD HUB CONTROL - "</span>
+<a name="l02263"></a>02263                                             <span class="stringliteral">"SetPortFeature - USB_PORT_FEAT_TEST %d\n"</span>,
+<a name="l02264"></a>02264                                             t);
+<a name="l02265"></a>02265                                 DWC_WARN(<span class="stringliteral">"USB_PORT_FEAT_TEST %d\n"</span>, t);
+<a name="l02266"></a>02266                                 <span class="keywordflow">if</span> (t &lt; 6) {
+<a name="l02267"></a>02267                                         hprt0.<a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a> = <a class="code" href="dwc__otg__cil_8h.html#ce67da6af4023cffd25333d20992438e">dwc_otg_read_hprt0</a>(core_if);
+<a name="l02268"></a>02268                                         hprt0.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#c61d714ff8f0bc62767342523347ba66">prttstctl</a> = t;
+<a name="l02269"></a>02269                                         dwc_write_reg32(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#dc8fe33e0bb3829cafa884d5fc603c4d">hprt0</a>,
+<a name="l02270"></a>02270                                                         hprt0.<a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a>);
+<a name="l02271"></a>02271                                 } <span class="keywordflow">else</span> {
+<a name="l02272"></a>02272                                         <span class="comment">/* Setup global vars with reg addresses (quick and</span>
+<a name="l02273"></a>02273 <span class="comment">                                         * dirty hack, should be cleaned up)</span>
+<a name="l02274"></a>02274 <span class="comment">                                         */</span>
+<a name="l02275"></a>02275                                         global_regs = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>;
+<a name="l02276"></a>02276                                         hc_global_regs =
+<a name="l02277"></a>02277                                             core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#ff9692c2e10ca2bc7e24f981f25179c2">host_global_regs</a>;
+<a name="l02278"></a>02278                                         hc_regs =
+<a name="l02279"></a>02279                                             (<a class="code" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *) ((<span class="keywordtype">char</span> *)
+<a name="l02280"></a>02280                                                                    global_regs +
+<a name="l02281"></a>02281                                                                    0x500);
+<a name="l02282"></a>02282                                         data_fifo =
+<a name="l02283"></a>02283                                             (uint32_t *) ((<span class="keywordtype">char</span> *)global_regs +
+<a name="l02284"></a>02284                                                           0x1000);
+<a name="l02285"></a>02285 
+<a name="l02286"></a>02286                                         <span class="keywordflow">if</span> (t == 6) {   <span class="comment">/* HS_HOST_PORT_SUSPEND_RESUME */</span>
+<a name="l02287"></a>02287                                                 <span class="comment">/* Save current interrupt mask */</span>
+<a name="l02288"></a>02288                                                 gintmsk.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a> =
+<a name="l02289"></a>02289                                                     dwc_read_reg32
+<a name="l02290"></a>02290                                                     (&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#48827c76da2c6b18f369e2f2483cc4b6">gintmsk</a>);
+<a name="l02291"></a>02291 
+<a name="l02292"></a>02292                                                 <span class="comment">/* Disable all interrupts while we muck with</span>
+<a name="l02293"></a>02293 <span class="comment">                                                 * the hardware directly</span>
+<a name="l02294"></a>02294 <span class="comment">                                                 */</span>
+<a name="l02295"></a>02295                                                 dwc_write_reg32(&amp;global_regs-&gt;
+<a name="l02296"></a>02296                                                                 gintmsk, 0);
+<a name="l02297"></a>02297 
+<a name="l02298"></a>02298                                                 <span class="comment">/* 15 second delay per the test spec */</span>
+<a name="l02299"></a>02299                                                 dwc_mdelay(15000);
+<a name="l02300"></a>02300 
+<a name="l02301"></a>02301                                                 <span class="comment">/* Drive suspend on the root port */</span>
+<a name="l02302"></a>02302                                                 hprt0.<a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a> =
+<a name="l02303"></a>02303                                                     <a class="code" href="dwc__otg__cil_8h.html#ce67da6af4023cffd25333d20992438e">dwc_otg_read_hprt0</a>(core_if);
+<a name="l02304"></a>02304                                                 hprt0.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#e7fe71d6c465ae002211c24a6ba359d2">prtsusp</a> = 1;
+<a name="l02305"></a>02305                                                 hprt0.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#3f5961529636a3891a4ca9421dd535fa">prtres</a> = 0;
+<a name="l02306"></a>02306                                                 dwc_write_reg32(core_if-&gt;
+<a name="l02307"></a>02307                                                                 host_if-&gt;hprt0,
+<a name="l02308"></a>02308                                                                 hprt0.<a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a>);
+<a name="l02309"></a>02309 
+<a name="l02310"></a>02310                                                 <span class="comment">/* 15 second delay per the test spec */</span>
+<a name="l02311"></a>02311                                                 dwc_mdelay(15000);
+<a name="l02312"></a>02312 
+<a name="l02313"></a>02313                                                 <span class="comment">/* Drive resume on the root port */</span>
+<a name="l02314"></a>02314                                                 hprt0.<a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a> =
+<a name="l02315"></a>02315                                                     <a class="code" href="dwc__otg__cil_8h.html#ce67da6af4023cffd25333d20992438e">dwc_otg_read_hprt0</a>(core_if);
+<a name="l02316"></a>02316                                                 hprt0.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#e7fe71d6c465ae002211c24a6ba359d2">prtsusp</a> = 0;
+<a name="l02317"></a>02317                                                 hprt0.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#3f5961529636a3891a4ca9421dd535fa">prtres</a> = 1;
+<a name="l02318"></a>02318                                                 dwc_write_reg32(core_if-&gt;
+<a name="l02319"></a>02319                                                                 host_if-&gt;hprt0,
+<a name="l02320"></a>02320                                                                 hprt0.<a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a>);
+<a name="l02321"></a>02321                                                 dwc_mdelay(100);
+<a name="l02322"></a>02322 
+<a name="l02323"></a>02323                                                 <span class="comment">/* Clear the resume bit */</span>
+<a name="l02324"></a>02324                                                 hprt0.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#3f5961529636a3891a4ca9421dd535fa">prtres</a> = 0;
+<a name="l02325"></a>02325                                                 dwc_write_reg32(core_if-&gt;
+<a name="l02326"></a>02326                                                                 host_if-&gt;hprt0,
+<a name="l02327"></a>02327                                                                 hprt0.<a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a>);
+<a name="l02328"></a>02328 
+<a name="l02329"></a>02329                                                 <span class="comment">/* Restore interrupts */</span>
+<a name="l02330"></a>02330                                                 dwc_write_reg32(&amp;global_regs-&gt;
+<a name="l02331"></a>02331                                                                 gintmsk,
+<a name="l02332"></a>02332                                                                 gintmsk.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a>);
+<a name="l02333"></a>02333                                         } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (t == 7) {    <span class="comment">/* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */</span>
+<a name="l02334"></a>02334                                                 <span class="comment">/* Save current interrupt mask */</span>
+<a name="l02335"></a>02335                                                 gintmsk.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a> =
+<a name="l02336"></a>02336                                                     dwc_read_reg32
+<a name="l02337"></a>02337                                                     (&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#48827c76da2c6b18f369e2f2483cc4b6">gintmsk</a>);
+<a name="l02338"></a>02338 
+<a name="l02339"></a>02339                                                 <span class="comment">/* Disable all interrupts while we muck with</span>
+<a name="l02340"></a>02340 <span class="comment">                                                 * the hardware directly</span>
+<a name="l02341"></a>02341 <span class="comment">                                                 */</span>
+<a name="l02342"></a>02342                                                 dwc_write_reg32(&amp;global_regs-&gt;
+<a name="l02343"></a>02343                                                                 gintmsk, 0);
+<a name="l02344"></a>02344 
+<a name="l02345"></a>02345                                                 <span class="comment">/* 15 second delay per the test spec */</span>
+<a name="l02346"></a>02346                                                 dwc_mdelay(15000);
+<a name="l02347"></a>02347 
+<a name="l02348"></a>02348                                                 <span class="comment">/* Send the Setup packet */</span>
+<a name="l02349"></a>02349                                                 do_setup();
+<a name="l02350"></a>02350 
+<a name="l02351"></a>02351                                                 <span class="comment">/* 15 second delay so nothing else happens for awhile */</span>
+<a name="l02352"></a>02352                                                 dwc_mdelay(15000);
+<a name="l02353"></a>02353 
+<a name="l02354"></a>02354                                                 <span class="comment">/* Restore interrupts */</span>
+<a name="l02355"></a>02355                                                 dwc_write_reg32(&amp;global_regs-&gt;
+<a name="l02356"></a>02356                                                                 gintmsk,
+<a name="l02357"></a>02357                                                                 gintmsk.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a>);
+<a name="l02358"></a>02358                                         } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (t == 8) {    <span class="comment">/* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */</span>
+<a name="l02359"></a>02359                                                 <span class="comment">/* Save current interrupt mask */</span>
+<a name="l02360"></a>02360                                                 gintmsk.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a> =
+<a name="l02361"></a>02361                                                     dwc_read_reg32
+<a name="l02362"></a>02362                                                     (&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#48827c76da2c6b18f369e2f2483cc4b6">gintmsk</a>);
+<a name="l02363"></a>02363 
+<a name="l02364"></a>02364                                                 <span class="comment">/* Disable all interrupts while we muck with</span>
+<a name="l02365"></a>02365 <span class="comment">                                                 * the hardware directly</span>
+<a name="l02366"></a>02366 <span class="comment">                                                 */</span>
+<a name="l02367"></a>02367                                                 dwc_write_reg32(&amp;global_regs-&gt;
+<a name="l02368"></a>02368                                                                 gintmsk, 0);
+<a name="l02369"></a>02369 
+<a name="l02370"></a>02370                                                 <span class="comment">/* Send the Setup packet */</span>
+<a name="l02371"></a>02371                                                 do_setup();
+<a name="l02372"></a>02372 
+<a name="l02373"></a>02373                                                 <span class="comment">/* 15 second delay so nothing else happens for awhile */</span>
+<a name="l02374"></a>02374                                                 dwc_mdelay(15000);
+<a name="l02375"></a>02375 
+<a name="l02376"></a>02376                                                 <span class="comment">/* Send the In and Ack packets */</span>
+<a name="l02377"></a>02377                                                 do_in_ack();
+<a name="l02378"></a>02378 
+<a name="l02379"></a>02379                                                 <span class="comment">/* 15 second delay so nothing else happens for awhile */</span>
+<a name="l02380"></a>02380                                                 dwc_mdelay(15000);
+<a name="l02381"></a>02381 
+<a name="l02382"></a>02382                                                 <span class="comment">/* Restore interrupts */</span>
+<a name="l02383"></a>02383                                                 dwc_write_reg32(&amp;global_regs-&gt;
+<a name="l02384"></a>02384                                                                 gintmsk,
+<a name="l02385"></a>02385                                                                 gintmsk.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a>);
+<a name="l02386"></a>02386                                         }
+<a name="l02387"></a>02387                                 }
+<a name="l02388"></a>02388                                 <span class="keywordflow">break</span>;
+<a name="l02389"></a>02389                         }
+<a name="l02390"></a>02390 <span class="preprocessor">#endif                          </span><span class="comment">/* DWC_HS_ELECT_TST */</span>
+<a name="l02391"></a>02391 
+<a name="l02392"></a>02392                 <span class="keywordflow">case</span> UHF_PORT_INDICATOR:
+<a name="l02393"></a>02393                         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(DBG_HCD, <span class="stringliteral">"DWC OTG HCD HUB CONTROL - "</span>
+<a name="l02394"></a>02394                                     <span class="stringliteral">"SetPortFeature - USB_PORT_FEAT_INDICATOR\n"</span>);
+<a name="l02395"></a>02395                         <span class="comment">/* Not supported */</span>
+<a name="l02396"></a>02396                         <span class="keywordflow">break</span>;
+<a name="l02397"></a>02397                 <span class="keywordflow">default</span>:
+<a name="l02398"></a>02398                         retval = -DWC_E_INVALID;
+<a name="l02399"></a>02399                         DWC_ERROR(<span class="stringliteral">"DWC OTG HCD - "</span>
+<a name="l02400"></a>02400                                   <span class="stringliteral">"SetPortFeature request %xh "</span>
+<a name="l02401"></a>02401                                   <span class="stringliteral">"unknown or unsupported\n"</span>, wValue);
+<a name="l02402"></a>02402                         <span class="keywordflow">break</span>;
+<a name="l02403"></a>02403                 }
+<a name="l02404"></a>02404                 <span class="keywordflow">break</span>;
+<a name="l02405"></a>02405 <span class="preprocessor">#ifdef CONFIG_USB_DWC_OTG_LPM</span>
+<a name="l02406"></a>02406 <span class="preprocessor"></span>        <span class="keywordflow">case</span> UCR_SET_AND_TEST_PORT_FEATURE:
+<a name="l02407"></a>02407                 <span class="keywordflow">if</span> (wValue != UHF_PORT_L1) {
+<a name="l02408"></a>02408                         <span class="keywordflow">goto</span> error;
+<a name="l02409"></a>02409                 }
+<a name="l02410"></a>02410                 {
+<a name="l02411"></a>02411                         <span class="keywordtype">int</span> portnum, hird, devaddr, remwake;
+<a name="l02412"></a>02412                         <a class="code" href="unionglpmctl__data.html">glpmcfg_data_t</a> lpmcfg;
+<a name="l02413"></a>02413                         uint32_t time_usecs;
+<a name="l02414"></a>02414                         <a class="code" href="uniongintsts__data.html">gintsts_data_t</a> gintsts;
+<a name="l02415"></a>02415                         <a class="code" href="uniongintmsk__data.html">gintmsk_data_t</a> gintmsk;
+<a name="l02416"></a>02416 
+<a name="l02417"></a>02417                         <span class="keywordflow">if</span> (!<a class="code" href="dwc__otg__cil_8c.html#0e0eb29733595730396da3ddf3d0ded5">dwc_otg_get_param_lpm_enable</a>(core_if)) {
+<a name="l02418"></a>02418                                 <span class="keywordflow">goto</span> error;
+<a name="l02419"></a>02419                         }
+<a name="l02420"></a>02420                         <span class="keywordflow">if</span> (wValue != UHF_PORT_L1 || wLength != 1) {
+<a name="l02421"></a>02421                                 <span class="keywordflow">goto</span> error;
+<a name="l02422"></a>02422                         }
+<a name="l02423"></a>02423                         <span class="comment">/* Check if the port currently is in SLEEP state */</span>
+<a name="l02424"></a>02424                         lpmcfg.<a class="code" href="unionglpmctl__data.html#cd41461734ff898209bfb64057ef2eb8">d32</a> =
+<a name="l02425"></a>02425                             dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#843cfb38ba366a9a46ad07ed11eb8396">glpmcfg</a>);
+<a name="l02426"></a>02426                         <span class="keywordflow">if</span> (lpmcfg.<a class="code" href="unionglpmctl__data.html#bd3cc34c338226ff1cd89448f7590ff1">b</a>.<a class="code" href="unionglpmctl__data.html#241ff25a215f16ac29b3bb6d9f4943ed">prt_sleep_sts</a>) {
+<a name="l02427"></a>02427                                 DWC_INFO(<span class="stringliteral">"Port is already in sleep mode\n"</span>);
+<a name="l02428"></a>02428                                 buf[0] = 0;     <span class="comment">/* Return success */</span>
+<a name="l02429"></a>02429                                 <span class="keywordflow">break</span>;
+<a name="l02430"></a>02430                         }
+<a name="l02431"></a>02431 
+<a name="l02432"></a>02432                         portnum = wIndex &amp; 0xf;
+<a name="l02433"></a>02433                         hird = (wIndex &gt;&gt; 4) &amp; 0xf;
+<a name="l02434"></a>02434                         devaddr = (wIndex &gt;&gt; 8) &amp; 0x7f;
+<a name="l02435"></a>02435                         remwake = (wIndex &gt;&gt; 15);
+<a name="l02436"></a>02436 
+<a name="l02437"></a>02437                         <span class="keywordflow">if</span> (portnum != 1) {
+<a name="l02438"></a>02438                                 retval = -DWC_E_INVALID;
+<a name="l02439"></a>02439                                 DWC_WARN
+<a name="l02440"></a>02440                                     (<span class="stringliteral">"Wrong port number(%d) in SetandTestPortFeature request\n"</span>,
+<a name="l02441"></a>02441                                      portnum);
+<a name="l02442"></a>02442                                 <span class="keywordflow">break</span>;
+<a name="l02443"></a>02443                         }
+<a name="l02444"></a>02444 
+<a name="l02445"></a>02445                         DWC_PRINTF
+<a name="l02446"></a>02446                             (<span class="stringliteral">"SetandTestPortFeature request: portnum = %d, hird = %d, devaddr = %d, rewake = %d\n"</span>,
+<a name="l02447"></a>02447                              portnum, hird, devaddr, remwake);
+<a name="l02448"></a>02448                         <span class="comment">/* Disable LPM interrupt */</span>
+<a name="l02449"></a>02449                         gintmsk.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a> = 0;
+<a name="l02450"></a>02450                         gintmsk.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#24f9f89b33866c5dc7b16588bc94e103">lpmtranrcvd</a> = 1;
+<a name="l02451"></a>02451                         dwc_modify_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#48827c76da2c6b18f369e2f2483cc4b6">gintmsk</a>,
+<a name="l02452"></a>02452                                          gintmsk.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a>, 0);
+<a name="l02453"></a>02453 
+<a name="l02454"></a>02454                         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__hcd__if_8h.html#b0c95e7f6cda9e15d767ad3ef6a7f1cc">dwc_otg_hcd_send_lpm</a>
+<a name="l02455"></a>02455                             (dwc_otg_hcd, devaddr, hird, remwake)) {
+<a name="l02456"></a>02456                                 retval = -DWC_E_INVALID;
+<a name="l02457"></a>02457                                 <span class="keywordflow">break</span>;
+<a name="l02458"></a>02458                         }
+<a name="l02459"></a>02459 
+<a name="l02460"></a>02460                         time_usecs = 10 * (lpmcfg.<a class="code" href="unionglpmctl__data.html#bd3cc34c338226ff1cd89448f7590ff1">b</a>.<a class="code" href="unionglpmctl__data.html#be75ed525bcfe231cd9bda6a1b8594f6">retry_count</a> + 1);
+<a name="l02461"></a>02461                         <span class="comment">/* We will consider timeout if time_usecs microseconds pass,</span>
+<a name="l02462"></a>02462 <span class="comment">                         * and we don't receive LPM transaction status.</span>
+<a name="l02463"></a>02463 <span class="comment">                         * After receiving non-error responce(ACK/NYET/STALL) from device,</span>
+<a name="l02464"></a>02464 <span class="comment">                         *  core will set lpmtranrcvd bit.</span>
+<a name="l02465"></a>02465 <span class="comment">                         */</span>
+<a name="l02466"></a>02466                         <span class="keywordflow">do</span> {
+<a name="l02467"></a>02467                                 gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a> =
+<a name="l02468"></a>02468                                     dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;
+<a name="l02469"></a>02469                                                    gintsts);
+<a name="l02470"></a>02470                                 <span class="keywordflow">if</span> (gintsts.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#50e73e91df681c835de50f8276058829">lpmtranrcvd</a>) {
+<a name="l02471"></a>02471                                         <span class="keywordflow">break</span>;
+<a name="l02472"></a>02472                                 }
+<a name="l02473"></a>02473                                 dwc_udelay(1);
+<a name="l02474"></a>02474                         } <span class="keywordflow">while</span> (--time_usecs);
+<a name="l02475"></a>02475                         <span class="comment">/* lpm_int bit will be cleared in LPM interrupt handler */</span>
+<a name="l02476"></a>02476 
+<a name="l02477"></a>02477                         <span class="comment">/* Now fill status</span>
+<a name="l02478"></a>02478 <span class="comment">                         * 0x00 - Success</span>
+<a name="l02479"></a>02479 <span class="comment">                         * 0x10 - NYET</span>
+<a name="l02480"></a>02480 <span class="comment">                         * 0x11 - Timeout</span>
+<a name="l02481"></a>02481 <span class="comment">                         */</span>
+<a name="l02482"></a>02482                         <span class="keywordflow">if</span> (!gintsts.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#50e73e91df681c835de50f8276058829">lpmtranrcvd</a>) {
+<a name="l02483"></a>02483                                 buf[0] = 0x3;   <span class="comment">/* Completion code is Timeout */</span>
+<a name="l02484"></a>02484                                 dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd);
+<a name="l02485"></a>02485                         } <span class="keywordflow">else</span> {
+<a name="l02486"></a>02486                                 lpmcfg.<a class="code" href="unionglpmctl__data.html#cd41461734ff898209bfb64057ef2eb8">d32</a> =
+<a name="l02487"></a>02487                                     dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;
+<a name="l02488"></a>02488                                                    glpmcfg);
+<a name="l02489"></a>02489                                 <span class="keywordflow">if</span> (lpmcfg.<a class="code" href="unionglpmctl__data.html#bd3cc34c338226ff1cd89448f7590ff1">b</a>.<a class="code" href="unionglpmctl__data.html#752c00118919fce173804931b058c5a8">lpm_resp</a> == 0x3) {
+<a name="l02490"></a>02490                                         <span class="comment">/* ACK responce from the device */</span>
+<a name="l02491"></a>02491                                         buf[0] = 0x00;  <span class="comment">/* Success */</span>
+<a name="l02492"></a>02492                                 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (lpmcfg.<a class="code" href="unionglpmctl__data.html#bd3cc34c338226ff1cd89448f7590ff1">b</a>.<a class="code" href="unionglpmctl__data.html#752c00118919fce173804931b058c5a8">lpm_resp</a> == 0x2) {
+<a name="l02493"></a>02493                                         <span class="comment">/* NYET responce from the device */</span>
+<a name="l02494"></a>02494                                         buf[0] = 0x2;
+<a name="l02495"></a>02495                                 } <span class="keywordflow">else</span> {
+<a name="l02496"></a>02496                                         <span class="comment">/* Otherwise responce with Timeout */</span>
+<a name="l02497"></a>02497                                         buf[0] = 0x3;
+<a name="l02498"></a>02498                                 }
+<a name="l02499"></a>02499                         }
+<a name="l02500"></a>02500                         DWC_PRINTF(<span class="stringliteral">"Device responce to LPM trans is %x\n"</span>,
+<a name="l02501"></a>02501                                    lpmcfg.<a class="code" href="unionglpmctl__data.html#bd3cc34c338226ff1cd89448f7590ff1">b</a>.<a class="code" href="unionglpmctl__data.html#752c00118919fce173804931b058c5a8">lpm_resp</a>);
+<a name="l02502"></a>02502                         dwc_modify_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#48827c76da2c6b18f369e2f2483cc4b6">gintmsk</a>, 0,
+<a name="l02503"></a>02503                                          gintmsk.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a>);
+<a name="l02504"></a>02504 
+<a name="l02505"></a>02505                         <span class="keywordflow">break</span>;
+<a name="l02506"></a>02506                 }
+<a name="l02507"></a>02507 <span class="preprocessor">#endif                          </span><span class="comment">/* CONFIG_USB_DWC_OTG_LPM */</span>
+<a name="l02508"></a>02508         <span class="keywordflow">default</span>:
+<a name="l02509"></a>02509               error:
+<a name="l02510"></a>02510                 retval = -DWC_E_INVALID;
+<a name="l02511"></a>02511                 DWC_WARN(<span class="stringliteral">"DWC OTG HCD - "</span>
+<a name="l02512"></a>02512                          <span class="stringliteral">"Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n"</span>,
+<a name="l02513"></a>02513                          typeReq, wIndex, wValue);
+<a name="l02514"></a>02514                 <span class="keywordflow">break</span>;
+<a name="l02515"></a>02515         }
+<a name="l02516"></a>02516 
+<a name="l02517"></a>02517         <span class="keywordflow">return</span> retval;
+<a name="l02518"></a>02518 }
+<a name="l02519"></a>02519 
+<a name="l02520"></a>02520 <span class="preprocessor">#ifdef CONFIG_USB_DWC_OTG_LPM</span>
+<a name="l02521"></a>02521 <span class="preprocessor"></span>
+<a name="l02522"></a>02522 <span class="keywordtype">int</span> dwc_otg_hcd_get_hc_for_lpm_tran(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd, uint8_t devaddr)
+<a name="l02523"></a>02523 {
+<a name="l02524"></a>02524         <a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if = hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>;
+<a name="l02525"></a>02525         <a class="code" href="structdwc__hc.html">dwc_hc_t</a> *hc;
+<a name="l02526"></a>02526         <a class="code" href="unionhcchar__data.html">hcchar_data_t</a> hcchar;
+<a name="l02527"></a>02527         <a class="code" href="uniongintmsk__data.html">gintmsk_data_t</a> gintmsk = {.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a> = 0 };
+<a name="l02528"></a>02528 
+<a name="l02529"></a>02529         <span class="keywordflow">if</span> (DWC_CIRCLEQ_EMPTY(&amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#1761f2e6b8f6ba82c0e0c4e561813f0f">free_hc_list</a>)) {
+<a name="l02530"></a>02530                 DWC_PRINTF(<span class="stringliteral">"No free channel to select for LPM transaction\n"</span>);
+<a name="l02531"></a>02531                 <span class="keywordflow">return</span> -1;
+<a name="l02532"></a>02532         }
+<a name="l02533"></a>02533 
+<a name="l02534"></a>02534         hc = DWC_CIRCLEQ_FIRST(&amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#1761f2e6b8f6ba82c0e0c4e561813f0f">free_hc_list</a>);
+<a name="l02535"></a>02535 
+<a name="l02536"></a>02536         <span class="comment">/* Mask host channel interrupts. */</span>
+<a name="l02537"></a>02537         gintmsk.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#3a4c193d8ff48291809dcd3ccb7c0585">hcintr</a> = 1;
+<a name="l02538"></a>02538         dwc_modify_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#48827c76da2c6b18f369e2f2483cc4b6">gintmsk</a>, gintmsk.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a>, 0);
+<a name="l02539"></a>02539 
+<a name="l02540"></a>02540         <span class="comment">/* Fill fields that core needs for LPM transaction */</span>
+<a name="l02541"></a>02541         hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#19326a679cb3507cf294d229834252a1">devaddr</a> = devaddr;
+<a name="l02542"></a>02542         hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#1597f36b85006e643aaf6f4d503bebc9">epnum</a> = 0;
+<a name="l02543"></a>02543         hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#df4deee52d932ab29e5d077cde77cbfc">eptype</a> = <a class="code" href="dwc__otg__cil_8h.html#64e5cd756330f5adab79b25cc8067bdc">DWC_OTG_EP_TYPE_CONTROL</a>;
+<a name="l02544"></a>02544         hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#47d11a5e62f69534d8ac0606aa7ffe7d">mps</a> = 64;
+<a name="l02545"></a>02545         hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#ca469c8bda88761c4d9ef74b811d71f4">lspddev</a> = (hc-&gt;<a class="code" href="structdwc__hc.html#570b78178975193edb921af1ef36d37b">speed</a> == <a class="code" href="dwc__otg__cil_8h.html#1a25260b2e1a06850c26f7b7e5128f31">DWC_OTG_EP_SPEED_LOW</a>);
+<a name="l02546"></a>02546         hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#11f1b16e50f90806f90953bb979d4e77">epdir</a> = 0;     <span class="comment">/* OUT */</span>
+<a name="l02547"></a>02547         dwc_write_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#7f7c107d4720641eb4141cd817211ac0">hc_regs</a>[hc-&gt;<a class="code" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">hc_num</a>]-&gt;hcchar,
+<a name="l02548"></a>02548                         hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a>);
+<a name="l02549"></a>02549 
+<a name="l02550"></a>02550         <span class="comment">/* Remove the host channel from the free list. */</span>
+<a name="l02551"></a>02551         DWC_CIRCLEQ_REMOVE_INIT(&amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#1761f2e6b8f6ba82c0e0c4e561813f0f">free_hc_list</a>, hc, hc_list_entry);
+<a name="l02552"></a>02552 
+<a name="l02553"></a>02553         DWC_PRINTF(<span class="stringliteral">"hcnum = %d devaddr = %d\n"</span>, hc-&gt;<a class="code" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">hc_num</a>, devaddr);
+<a name="l02554"></a>02554 
+<a name="l02555"></a>02555         <span class="keywordflow">return</span> hc-&gt;<a class="code" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">hc_num</a>;
+<a name="l02556"></a>02556 }
+<a name="l02557"></a>02557 
+<a name="l02559"></a>02559 <span class="keywordtype">void</span> dwc_otg_hcd_free_hc_from_lpm(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd)
+<a name="l02560"></a>02560 {
+<a name="l02561"></a>02561         <a class="code" href="structdwc__hc.html">dwc_hc_t</a> *hc;
+<a name="l02562"></a>02562         <a class="code" href="unionglpmctl__data.html">glpmcfg_data_t</a> lpmcfg;
+<a name="l02563"></a>02563         uint8_t hc_num;
+<a name="l02564"></a>02564 
+<a name="l02565"></a>02565         lpmcfg.<a class="code" href="unionglpmctl__data.html#cd41461734ff898209bfb64057ef2eb8">d32</a> = dwc_read_reg32(&amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#843cfb38ba366a9a46ad07ed11eb8396">glpmcfg</a>);
+<a name="l02566"></a>02566         hc_num = lpmcfg.<a class="code" href="unionglpmctl__data.html#bd3cc34c338226ff1cd89448f7590ff1">b</a>.<a class="code" href="unionglpmctl__data.html#7e6bb2a40d4e0bdfed6f868b1f670235">lpm_chan_index</a>;
+<a name="l02567"></a>02567 
+<a name="l02568"></a>02568         hc = hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#cb393f6a676fb106e0e3d35396fb97f9">hc_ptr_array</a>[hc_num];
+<a name="l02569"></a>02569 
+<a name="l02570"></a>02570         DWC_PRINTF(<span class="stringliteral">"Freeing channel %d after LPM\n"</span>, hc_num);
+<a name="l02571"></a>02571         <span class="comment">/* Return host channel to free list */</span>
+<a name="l02572"></a>02572         DWC_CIRCLEQ_INSERT_TAIL(&amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#1761f2e6b8f6ba82c0e0c4e561813f0f">free_hc_list</a>, hc, hc_list_entry);
+<a name="l02573"></a>02573 }
+<a name="l02574"></a>02574 
+<a name="l02575"></a>02575 <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd__if_8h.html#b0c95e7f6cda9e15d767ad3ef6a7f1cc">dwc_otg_hcd_send_lpm</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd, uint8_t devaddr, uint8_t hird,
+<a name="l02576"></a>02576                          uint8_t bRemoteWake)
+<a name="l02577"></a>02577 {
+<a name="l02578"></a>02578         <a class="code" href="unionglpmctl__data.html">glpmcfg_data_t</a> lpmcfg;
+<a name="l02579"></a>02579         <a class="code" href="unionpcgcctl__data.html">pcgcctl_data_t</a> pcgcctl = {.d32 = 0 };
+<a name="l02580"></a>02580         <span class="keywordtype">int</span> channel;
+<a name="l02581"></a>02581 
+<a name="l02582"></a>02582         channel = dwc_otg_hcd_get_hc_for_lpm_tran(hcd, devaddr);
+<a name="l02583"></a>02583         <span class="keywordflow">if</span> (channel &lt; 0) {
+<a name="l02584"></a>02584                 <span class="keywordflow">return</span> channel;
+<a name="l02585"></a>02585         }
+<a name="l02586"></a>02586 
+<a name="l02587"></a>02587         pcgcctl.<a class="code" href="unionpcgcctl__data.html#f2bb76709d0ab9d08280eafb78a36279">b</a>.<a class="code" href="unionpcgcctl__data.html#6c18ad3b71ad92e548d0c6d64cc88734">enbl_sleep_gating</a> = 1;
+<a name="l02588"></a>02588         dwc_modify_reg32(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#348ed2c9aeae6fc608f1bb813978b3f9">pcgcctl</a>, 0, pcgcctl.<a class="code" href="unionpcgcctl__data.html#abe048ee884143501929b27d94c52db7">d32</a>);
+<a name="l02589"></a>02589 
+<a name="l02590"></a>02590         <span class="comment">/* Read LPM config register */</span>
+<a name="l02591"></a>02591         lpmcfg.<a class="code" href="unionglpmctl__data.html#cd41461734ff898209bfb64057ef2eb8">d32</a> = dwc_read_reg32(&amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#843cfb38ba366a9a46ad07ed11eb8396">glpmcfg</a>);
+<a name="l02592"></a>02592 
+<a name="l02593"></a>02593         <span class="comment">/* Program LPM transaction fields */</span>
+<a name="l02594"></a>02594         lpmcfg.<a class="code" href="unionglpmctl__data.html#bd3cc34c338226ff1cd89448f7590ff1">b</a>.<a class="code" href="unionglpmctl__data.html#60a9c2e233e3ee15a80ae80b27d09f8b">rem_wkup_en</a> = bRemoteWake;
+<a name="l02595"></a>02595         lpmcfg.<a class="code" href="unionglpmctl__data.html#bd3cc34c338226ff1cd89448f7590ff1">b</a>.<a class="code" href="unionglpmctl__data.html#176b788935d1952606f523f2718b3512">hird</a> = hird;
+<a name="l02596"></a>02596         lpmcfg.<a class="code" href="unionglpmctl__data.html#bd3cc34c338226ff1cd89448f7590ff1">b</a>.<a class="code" href="unionglpmctl__data.html#e2ceea4bfe468c7b3c800235d7ffd5d2">hird_thres</a> = 0x1c;
+<a name="l02597"></a>02597         lpmcfg.<a class="code" href="unionglpmctl__data.html#bd3cc34c338226ff1cd89448f7590ff1">b</a>.<a class="code" href="unionglpmctl__data.html#7e6bb2a40d4e0bdfed6f868b1f670235">lpm_chan_index</a> = channel;
+<a name="l02598"></a>02598         lpmcfg.<a class="code" href="unionglpmctl__data.html#bd3cc34c338226ff1cd89448f7590ff1">b</a>.<a class="code" href="unionglpmctl__data.html#63e912a05b8d29872b92263ca616fec8">en_utmi_sleep</a> = 1;
+<a name="l02599"></a>02599         <span class="comment">/* Program LPM config register */</span>
+<a name="l02600"></a>02600         dwc_write_reg32(&amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#843cfb38ba366a9a46ad07ed11eb8396">glpmcfg</a>, lpmcfg.<a class="code" href="unionglpmctl__data.html#cd41461734ff898209bfb64057ef2eb8">d32</a>);
+<a name="l02601"></a>02601 
+<a name="l02602"></a>02602         <span class="comment">/* Send LPM transaction */</span>
+<a name="l02603"></a>02603         lpmcfg.<a class="code" href="unionglpmctl__data.html#bd3cc34c338226ff1cd89448f7590ff1">b</a>.<a class="code" href="unionglpmctl__data.html#0651e486c5502489b2cac633bb00c78e">send_lpm</a> = 1;
+<a name="l02604"></a>02604         dwc_write_reg32(&amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#843cfb38ba366a9a46ad07ed11eb8396">glpmcfg</a>, lpmcfg.<a class="code" href="unionglpmctl__data.html#cd41461734ff898209bfb64057ef2eb8">d32</a>);
+<a name="l02605"></a>02605 
+<a name="l02606"></a>02606         <span class="keywordflow">return</span> 0;
+<a name="l02607"></a>02607 }
+<a name="l02608"></a>02608 
+<a name="l02609"></a>02609 <span class="preprocessor">#endif                          </span><span class="comment">/* CONFIG_USB_DWC_OTG_LPM */</span>
+<a name="l02610"></a>02610 
+<a name="l02611"></a><a class="code" href="dwc__otg__hcd__if_8h.html#0d324c8dbb0c7cbadec8cebf943fc84b">02611</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd_8c.html#0d324c8dbb0c7cbadec8cebf943fc84b">dwc_otg_hcd_is_status_changed</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd, <span class="keywordtype">int</span> port)
+<a name="l02612"></a>02612 {
+<a name="l02613"></a>02613         <span class="keywordtype">int</span> retval;
+<a name="l02614"></a>02614 
+<a name="l02615"></a>02615         <span class="keywordflow">if</span> (port != 1) {
+<a name="l02616"></a>02616                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l02617"></a>02617         }
+<a name="l02618"></a>02618 
+<a name="l02619"></a>02619         retval = (hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#9aaf2a112f5794f92dedd826342bd637">flags</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#76f573861d9316238ded198c58c228c7">b</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#cd31ac4b9658265e90773448f354f0e1">port_connect_status_change</a> ||
+<a name="l02620"></a>02620                   hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#9aaf2a112f5794f92dedd826342bd637">flags</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#76f573861d9316238ded198c58c228c7">b</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#d0d63f32ed35315e8a02549521fb386e">port_reset_change</a> ||
+<a name="l02621"></a>02621                   hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#9aaf2a112f5794f92dedd826342bd637">flags</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#76f573861d9316238ded198c58c228c7">b</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#d222ae08372109a312f6649f77b650e8">port_enable_change</a> ||
+<a name="l02622"></a>02622                   hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#9aaf2a112f5794f92dedd826342bd637">flags</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#76f573861d9316238ded198c58c228c7">b</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#2a6e323cb4c01153aff1adc6269c74c7">port_suspend_change</a> ||
+<a name="l02623"></a>02623                   hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#9aaf2a112f5794f92dedd826342bd637">flags</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#76f573861d9316238ded198c58c228c7">b</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#bc96cf12e2bc5b61ce05f15ae3297bd6">port_over_current_change</a>);
+<a name="l02624"></a>02624 <span class="preprocessor">#ifdef DEBUG</span>
+<a name="l02625"></a>02625 <span class="preprocessor"></span>        <span class="keywordflow">if</span> (retval) {
+<a name="l02626"></a>02626                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#e4a050e176c1c4f556da2b276a8c2b37">DBG_HCD</a>, <span class="stringliteral">"DWC OTG HCD HUB STATUS DATA:"</span>
+<a name="l02627"></a>02627                             <span class="stringliteral">" Root port status changed\n"</span>);
+<a name="l02628"></a>02628                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"  port_connect_status_change: %d\n"</span>,
+<a name="l02629"></a>02629                             hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#9aaf2a112f5794f92dedd826342bd637">flags</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#76f573861d9316238ded198c58c228c7">b</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#cd31ac4b9658265e90773448f354f0e1">port_connect_status_change</a>);
+<a name="l02630"></a>02630                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"  port_reset_change: %d\n"</span>,
+<a name="l02631"></a>02631                             hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#9aaf2a112f5794f92dedd826342bd637">flags</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#76f573861d9316238ded198c58c228c7">b</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#d0d63f32ed35315e8a02549521fb386e">port_reset_change</a>);
+<a name="l02632"></a>02632                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"  port_enable_change: %d\n"</span>,
+<a name="l02633"></a>02633                             hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#9aaf2a112f5794f92dedd826342bd637">flags</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#76f573861d9316238ded198c58c228c7">b</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#d222ae08372109a312f6649f77b650e8">port_enable_change</a>);
+<a name="l02634"></a>02634                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"  port_suspend_change: %d\n"</span>,
+<a name="l02635"></a>02635                             hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#9aaf2a112f5794f92dedd826342bd637">flags</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#76f573861d9316238ded198c58c228c7">b</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#2a6e323cb4c01153aff1adc6269c74c7">port_suspend_change</a>);
+<a name="l02636"></a>02636                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"  port_over_current_change: %d\n"</span>,
+<a name="l02637"></a>02637                             hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#9aaf2a112f5794f92dedd826342bd637">flags</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#76f573861d9316238ded198c58c228c7">b</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#bc96cf12e2bc5b61ce05f15ae3297bd6">port_over_current_change</a>);
+<a name="l02638"></a>02638         }
+<a name="l02639"></a>02639 <span class="preprocessor">#endif</span>
+<a name="l02640"></a>02640 <span class="preprocessor"></span>        <span class="keywordflow">return</span> retval;
+<a name="l02641"></a>02641 }
+<a name="l02642"></a>02642 
+<a name="l02643"></a><a class="code" href="dwc__otg__hcd__if_8h.html#65b3f4d96d1b34abaa54c3bbb32ec07f">02643</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd_8c.html#f06514bd6f8c219cc72d1f467a82c056">dwc_otg_hcd_get_frame_number</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * dwc_otg_hcd)
+<a name="l02644"></a>02644 {
+<a name="l02645"></a>02645         <a class="code" href="unionhfnum__data.html">hfnum_data_t</a> hfnum;
+<a name="l02646"></a>02646         hfnum.<a class="code" href="unionhfnum__data.html#e5ccbed3af86ac88577ded328e6c9932">d32</a> = dwc_read_reg32(&amp;dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;
+<a name="l02647"></a>02647                                    host_if-&gt;host_global_regs-&gt;hfnum);
+<a name="l02648"></a>02648 
+<a name="l02649"></a>02649 <span class="preprocessor">#ifdef DEBUG_SOF</span>
+<a name="l02650"></a>02650 <span class="preprocessor"></span>        <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"DWC OTG HCD GET FRAME NUMBER %d\n"</span>,
+<a name="l02651"></a>02651                     hfnum.<a class="code" href="unionhfnum__data.html#81df6fbd20a454665803eb5790855c66">b</a>.<a class="code" href="unionhfnum__data.html#a64e8b6c4a1cd262dbc30e158f3cb8bc">frnum</a>);
+<a name="l02652"></a>02652 <span class="preprocessor">#endif</span>
+<a name="l02653"></a>02653 <span class="preprocessor"></span>        <span class="keywordflow">return</span> hfnum.<a class="code" href="unionhfnum__data.html#81df6fbd20a454665803eb5790855c66">b</a>.<a class="code" href="unionhfnum__data.html#a64e8b6c4a1cd262dbc30e158f3cb8bc">frnum</a>;
+<a name="l02654"></a>02654 }
+<a name="l02655"></a>02655 
+<a name="l02656"></a><a class="code" href="dwc__otg__hcd__if_8h.html#7242be8ebc7f7516292cbe2344ab03be">02656</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd_8c.html#7242be8ebc7f7516292cbe2344ab03be">dwc_otg_hcd_start</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd,
+<a name="l02657"></a>02657                       <span class="keyword">struct</span> <a class="code" href="structdwc__otg__hcd__function__ops.html">dwc_otg_hcd_function_ops</a> *<a class="code" href="dwc__otg__pcd__linux_8c.html#9ce9b5e49c60906c189bee157dd68acd">fops</a>)
+<a name="l02658"></a>02658 {
+<a name="l02659"></a>02659         <span class="keywordtype">int</span> retval = 0;
+<a name="l02660"></a>02660 
+<a name="l02661"></a>02661         hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#ffefbd33a59a14b8b46406f5aaeaa2f4">fops</a> = <a class="code" href="dwc__otg__pcd__linux_8c.html#9ce9b5e49c60906c189bee157dd68acd">fops</a>;
+<a name="l02662"></a>02662         <span class="keywordflow">if</span> (!<a class="code" href="dwc__otg__cil_8c.html#e83fb22890bc54c6b06cedb751430e77">dwc_otg_is_device_mode</a>(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>)) {
+<a name="l02663"></a>02663                 <a class="code" href="dwc__otg__hcd_8c.html#a9b6729ba2077bed1b6d149970d5525e">dwc_otg_hcd_reinit</a>(hcd);
+<a name="l02664"></a>02664         } <span class="keywordflow">else</span> {
+<a name="l02665"></a>02665                 retval = -DWC_E_NO_DEVICE;
+<a name="l02666"></a>02666         }
+<a name="l02667"></a>02667 
+<a name="l02668"></a>02668         <span class="keywordflow">return</span> retval;
+<a name="l02669"></a>02669 }
+<a name="l02670"></a>02670 
+<a name="l02671"></a><a class="code" href="dwc__otg__hcd__if_8h.html#7740268b2d0fd8d25aaaeacfa5aef5cf">02671</a> <span class="keywordtype">void</span> *<a class="code" href="dwc__otg__hcd_8c.html#7740268b2d0fd8d25aaaeacfa5aef5cf">dwc_otg_hcd_get_priv_data</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd)
+<a name="l02672"></a>02672 {
+<a name="l02673"></a>02673         <span class="keywordflow">return</span> hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#c019b908f209d577ccc19d29030926a1">priv</a>;
+<a name="l02674"></a>02674 }
+<a name="l02675"></a>02675 
+<a name="l02676"></a><a class="code" href="dwc__otg__hcd__if_8h.html#c73ca7d4284c8f0de7338a66607e4eb1">02676</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd_8c.html#c73ca7d4284c8f0de7338a66607e4eb1">dwc_otg_hcd_set_priv_data</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd, <span class="keywordtype">void</span> *priv_data)
+<a name="l02677"></a>02677 {
+<a name="l02678"></a>02678         hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#c019b908f209d577ccc19d29030926a1">priv</a> = priv_data;
+<a name="l02679"></a>02679 }
+<a name="l02680"></a>02680 
+<a name="l02681"></a><a class="code" href="dwc__otg__hcd__if_8h.html#e7d3657931984a1ce1cee5cf47cb08f3">02681</a> uint32_t <a class="code" href="dwc__otg__hcd_8c.html#e7d3657931984a1ce1cee5cf47cb08f3">dwc_otg_hcd_otg_port</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd)
+<a name="l02682"></a>02682 {
+<a name="l02683"></a>02683         <span class="keywordflow">return</span> hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#9231b4c3dce89a1506a5e501ec5c7a39">otg_port</a>;
+<a name="l02684"></a>02684 }
+<a name="l02685"></a>02685 
+<a name="l02686"></a><a class="code" href="dwc__otg__hcd__if_8h.html#ca25b33b440a4ef112ee459c26c14adc">02686</a> uint32_t <a class="code" href="dwc__otg__hcd_8c.html#ca25b33b440a4ef112ee459c26c14adc">dwc_otg_hcd_is_b_host</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd)
+<a name="l02687"></a>02687 {
+<a name="l02688"></a>02688         uint32_t is_b_host;
+<a name="l02689"></a>02689         <span class="keywordflow">if</span> (hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#5a5c5c1cf8d870101cc1fffac56d88c0">op_state</a> == <a class="code" href="dwc__otg__cil_8h.html#02d6d4d9a0fdcc4fc8c5cf8e6c8577aa">B_HOST</a>) {
+<a name="l02690"></a>02690                 is_b_host = 1;
+<a name="l02691"></a>02691         } <span class="keywordflow">else</span> {
+<a name="l02692"></a>02692                 is_b_host = 0;
+<a name="l02693"></a>02693         }
+<a name="l02694"></a>02694 
+<a name="l02695"></a>02695         <span class="keywordflow">return</span> is_b_host;
+<a name="l02696"></a>02696 }
+<a name="l02697"></a>02697 
+<a name="l02698"></a><a class="code" href="dwc__otg__hcd__if_8h.html#264fc9d293c76e42dded9dee2cf44283">02698</a> <a class="code" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *<a class="code" href="dwc__otg__hcd_8c.html#264fc9d293c76e42dded9dee2cf44283">dwc_otg_hcd_urb_alloc</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd,
+<a name="l02699"></a>02699                                          <span class="keywordtype">int</span> iso_desc_count, <span class="keywordtype">int</span> atomic_alloc)
+<a name="l02700"></a>02700 {
+<a name="l02701"></a>02701         <a class="code" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *dwc_otg_urb;
+<a name="l02702"></a>02702         uint32_t size;
+<a name="l02703"></a>02703 
+<a name="l02704"></a>02704         size =
+<a name="l02705"></a>02705             <span class="keyword">sizeof</span>(*dwc_otg_urb) +
+<a name="l02706"></a>02706             iso_desc_count * <span class="keyword">sizeof</span>(<span class="keyword">struct </span><a class="code" href="structdwc__otg__hcd__iso__packet__desc.html">dwc_otg_hcd_iso_packet_desc</a>);
+<a name="l02707"></a>02707         <span class="keywordflow">if</span> (atomic_alloc) {
+<a name="l02708"></a>02708                 dwc_otg_urb = dwc_alloc_atomic(size);
+<a name="l02709"></a>02709         } <span class="keywordflow">else</span> {
+<a name="l02710"></a>02710                 dwc_otg_urb = dwc_alloc(size);
+<a name="l02711"></a>02711         }
+<a name="l02712"></a>02712         dwc_otg_urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#570583697e8c1e4398969630bc2562f8">packet_count</a> = iso_desc_count;
+<a name="l02713"></a>02713 
+<a name="l02714"></a>02714         <span class="keywordflow">return</span> dwc_otg_urb;
+<a name="l02715"></a>02715 }
+<a name="l02716"></a>02716 
+<a name="l02717"></a><a class="code" href="dwc__otg__hcd__if_8h.html#6c0a7bf2d1091d6e9e1ce767329fc04a">02717</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd_8c.html#4aca8781f512198149388799a8ae9aba">dwc_otg_hcd_urb_set_pipeinfo</a>(<a class="code" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> * dwc_otg_urb,
+<a name="l02718"></a>02718                                   uint8_t dev_addr, uint8_t ep_num,
+<a name="l02719"></a>02719                                   uint8_t ep_type, uint8_t ep_dir, uint16_t mps)
+<a name="l02720"></a>02720 {
+<a name="l02721"></a>02721         <a class="code" href="dwc__otg__hcd_8h.html#4806306754f0414ad9cee3067cdda8c9">dwc_otg_hcd_fill_pipe</a>(&amp;dwc_otg_urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#34ee3ac5931687b41dd726f00c558369">pipe_info</a>, dev_addr, ep_num,
+<a name="l02722"></a>02722                               ep_type, ep_dir, mps);
+<a name="l02723"></a>02723 <span class="preprocessor">#if 0</span>
+<a name="l02724"></a>02724 <span class="preprocessor"></span>        DWC_PRINTF
+<a name="l02725"></a>02725             (<span class="stringliteral">"addr = %d, ep_num = %d, ep_dir = 0x%x, ep_type = 0x%x, mps = %d\n"</span>,
+<a name="l02726"></a>02726              dev_addr, ep_num, ep_dir, ep_type, mps);
+<a name="l02727"></a>02727 <span class="preprocessor">#endif</span>
+<a name="l02728"></a>02728 <span class="preprocessor"></span>}
+<a name="l02729"></a>02729 
+<a name="l02730"></a><a class="code" href="dwc__otg__hcd__if_8h.html#356834d51d095518b6283a343bfab2b0">02730</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd_8c.html#d141b0ed3f2eac3f8aab2d8cefe34345">dwc_otg_hcd_urb_set_params</a>(<a class="code" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> * dwc_otg_urb,
+<a name="l02731"></a>02731                                 <span class="keywordtype">void</span> *urb_handle, <span class="keywordtype">void</span> *buf, dwc_dma_t dma,
+<a name="l02732"></a>02732                                 uint32_t buflen, <span class="keywordtype">void</span> *setup_packet,
+<a name="l02733"></a>02733                                 dwc_dma_t setup_dma, uint32_t flags,
+<a name="l02734"></a>02734                                 uint16_t interval)
+<a name="l02735"></a>02735 {
+<a name="l02736"></a>02736         dwc_otg_urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#5ba0e393ef9768275db85c00e68be477">priv</a> = urb_handle;
+<a name="l02737"></a>02737         dwc_otg_urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#99ae35ffcd6147ddb93b361ab3bcfe95">buf</a> = buf;
+<a name="l02738"></a>02738         dwc_otg_urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#4e177a55239e95ae2f6c8b6b913f67fc">dma</a> = dma;
+<a name="l02739"></a>02739         dwc_otg_urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#dca57de4fdecd894241ce24167206a45">length</a> = buflen;
+<a name="l02740"></a>02740         dwc_otg_urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#254afd954f3e24bb92841384183a317c">setup_packet</a> = setup_packet;
+<a name="l02741"></a>02741         dwc_otg_urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#497f61f9b3f6f77f6b844e31c047264d">setup_dma</a> = setup_dma;
+<a name="l02742"></a>02742         dwc_otg_urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#2f1d90765496d78d297b3e57ef4d781c">flags</a> = flags;
+<a name="l02743"></a>02743         dwc_otg_urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#49c5353377e2fb173f1b34ae7be7e257">interval</a> = interval;
+<a name="l02744"></a>02744         dwc_otg_urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#101e4a6762b9911cdb85768890fa1210">status</a> = -DWC_E_IN_PROGRESS;
+<a name="l02745"></a>02745 }
+<a name="l02746"></a>02746 
+<a name="l02747"></a><a class="code" href="dwc__otg__hcd__if_8h.html#81b7aad80889affb1e63cf1307b88fb6">02747</a> uint32_t <a class="code" href="dwc__otg__hcd_8c.html#81b7aad80889affb1e63cf1307b88fb6">dwc_otg_hcd_urb_get_status</a>(<a class="code" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> * dwc_otg_urb)
+<a name="l02748"></a>02748 {
+<a name="l02749"></a>02749         <span class="keywordflow">return</span> dwc_otg_urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#101e4a6762b9911cdb85768890fa1210">status</a>;
+<a name="l02750"></a>02750 }
+<a name="l02751"></a>02751 
+<a name="l02752"></a><a class="code" href="dwc__otg__hcd__if_8h.html#3260f5db4ea20074da16b292eb1a686b">02752</a> uint32_t <a class="code" href="dwc__otg__hcd_8c.html#3260f5db4ea20074da16b292eb1a686b">dwc_otg_hcd_urb_get_actual_length</a>(<a class="code" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> * dwc_otg_urb)
+<a name="l02753"></a>02753 {
+<a name="l02754"></a>02754         <span class="keywordflow">return</span> dwc_otg_urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#742c8a97d3867ab89148eae34e0c73a6">actual_length</a>;
+<a name="l02755"></a>02755 }
+<a name="l02756"></a>02756 
+<a name="l02757"></a><a class="code" href="dwc__otg__hcd__if_8h.html#816cc30c3129fc8911a458355d977129">02757</a> uint32_t <a class="code" href="dwc__otg__hcd_8c.html#816cc30c3129fc8911a458355d977129">dwc_otg_hcd_urb_get_error_count</a>(<a class="code" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> * dwc_otg_urb)
+<a name="l02758"></a>02758 {
+<a name="l02759"></a>02759         <span class="keywordflow">return</span> dwc_otg_urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#58c7018042c94c436637ea80354e7e28">error_count</a>;
+<a name="l02760"></a>02760 }
+<a name="l02761"></a>02761 
+<a name="l02762"></a><a class="code" href="dwc__otg__hcd__if_8h.html#8617e93eba1bfd6466a9af1e6d2f731b">02762</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd_8c.html#8617e93eba1bfd6466a9af1e6d2f731b">dwc_otg_hcd_urb_set_iso_desc_params</a>(<a class="code" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> * dwc_otg_urb,
+<a name="l02763"></a>02763                                          <span class="keywordtype">int</span> desc_num, uint32_t <a class="code" href="structdwc__otg__hcd__iso__packet__desc.html#246f3d147a22cd295c534253593dca4a">offset</a>,
+<a name="l02764"></a>02764                                          uint32_t <a class="code" href="structdwc__otg__hcd__iso__packet__desc.html#8392d21b820df0181f4e6dca91234543">length</a>)
+<a name="l02765"></a>02765 {
+<a name="l02766"></a>02766         dwc_otg_urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#ed542f6a2d99dba2f6b71b0d8012ec8a">iso_descs</a>[desc_num].<a class="code" href="structdwc__otg__hcd__iso__packet__desc.html#246f3d147a22cd295c534253593dca4a">offset</a> = offset;
+<a name="l02767"></a>02767         dwc_otg_urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#ed542f6a2d99dba2f6b71b0d8012ec8a">iso_descs</a>[desc_num].<a class="code" href="structdwc__otg__hcd__iso__packet__desc.html#8392d21b820df0181f4e6dca91234543">length</a> = length;
+<a name="l02768"></a>02768 }
+<a name="l02769"></a>02769 
+<a name="l02770"></a><a class="code" href="dwc__otg__hcd__if_8h.html#fde27182e452709e10c1100ea57aa46b">02770</a> uint32_t <a class="code" href="dwc__otg__hcd_8c.html#fde27182e452709e10c1100ea57aa46b">dwc_otg_hcd_urb_get_iso_desc_status</a>(<a class="code" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> * dwc_otg_urb,
+<a name="l02771"></a>02771                                              <span class="keywordtype">int</span> desc_num)
+<a name="l02772"></a>02772 {
+<a name="l02773"></a>02773         <span class="keywordflow">return</span> dwc_otg_urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#ed542f6a2d99dba2f6b71b0d8012ec8a">iso_descs</a>[desc_num].<a class="code" href="structdwc__otg__hcd__iso__packet__desc.html#d070772c24621c47b49ad21c6acadb94">status</a>;
+<a name="l02774"></a>02774 }
+<a name="l02775"></a>02775 
+<a name="l02776"></a><a class="code" href="dwc__otg__hcd__if_8h.html#c6d28fc3e6aedb29d46a793423c4de0a">02776</a> uint32_t <a class="code" href="dwc__otg__hcd_8c.html#c6d28fc3e6aedb29d46a793423c4de0a">dwc_otg_hcd_urb_get_iso_desc_actual_length</a>(<a class="code" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *
+<a name="l02777"></a>02777                                                     dwc_otg_urb, <span class="keywordtype">int</span> desc_num)
+<a name="l02778"></a>02778 {
+<a name="l02779"></a>02779         <span class="keywordflow">return</span> dwc_otg_urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#ed542f6a2d99dba2f6b71b0d8012ec8a">iso_descs</a>[desc_num].<a class="code" href="structdwc__otg__hcd__iso__packet__desc.html#c00b967f4c613820b99efc0abda5178c">actual_length</a>;
+<a name="l02780"></a>02780 }
+<a name="l02781"></a>02781 
+<a name="l02782"></a><a class="code" href="dwc__otg__hcd__if_8h.html#5deb69c332ba937b959c9dccadd87568">02782</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd_8c.html#5deb69c332ba937b959c9dccadd87568">dwc_otg_hcd_is_bandwidth_allocated</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd, <span class="keywordtype">void</span> *ep_handle)
+<a name="l02783"></a>02783 {
+<a name="l02784"></a>02784         <span class="keywordtype">int</span> allocated = 0;
+<a name="l02785"></a>02785         <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *qh = (<a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *) ep_handle;
+<a name="l02786"></a>02786 
+<a name="l02787"></a>02787         <span class="keywordflow">if</span> (qh) {
+<a name="l02788"></a>02788                 <span class="keywordflow">if</span> (!DWC_LIST_EMPTY(&amp;qh-&gt;qh_list_entry)) {
+<a name="l02789"></a>02789                         allocated = 1;
+<a name="l02790"></a>02790                 }
+<a name="l02791"></a>02791         }
+<a name="l02792"></a>02792         <span class="keywordflow">return</span> allocated;
+<a name="l02793"></a>02793 }
+<a name="l02794"></a>02794 
+<a name="l02795"></a><a class="code" href="dwc__otg__hcd__if_8h.html#ad28eed057375c7f31663dc777edefd7">02795</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd_8c.html#ad28eed057375c7f31663dc777edefd7">dwc_otg_hcd_is_bandwidth_freed</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd, <span class="keywordtype">void</span> *ep_handle)
+<a name="l02796"></a>02796 {
+<a name="l02797"></a>02797         <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *qh = (<a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *) ep_handle;
+<a name="l02798"></a>02798         <span class="keywordtype">int</span> freed = 0;
+<a name="l02799"></a>02799         DWC_ASSERT(qh, <span class="stringliteral">"qh is not allocated\n"</span>);
+<a name="l02800"></a>02800 
+<a name="l02801"></a>02801         <span class="keywordflow">if</span> (DWC_LIST_EMPTY(&amp;qh-&gt;<a class="code" href="structdwc__otg__qh.html#3e1cb9863dc72139e1832c04244c25ff">qh_list_entry</a>)) {
+<a name="l02802"></a>02802                 freed = 1;
+<a name="l02803"></a>02803         }
+<a name="l02804"></a>02804 
+<a name="l02805"></a>02805         <span class="keywordflow">return</span> freed;
+<a name="l02806"></a>02806 }
+<a name="l02807"></a>02807 
+<a name="l02808"></a><a class="code" href="dwc__otg__hcd__if_8h.html#bd160be911ccc8f90141dae9c40276eb">02808</a> uint8_t <a class="code" href="dwc__otg__hcd_8c.html#bd160be911ccc8f90141dae9c40276eb">dwc_otg_hcd_get_ep_bandwidth</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd, <span class="keywordtype">void</span> *ep_handle)
+<a name="l02809"></a>02809 {
+<a name="l02810"></a>02810         <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *qh = (<a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *) ep_handle;
+<a name="l02811"></a>02811         DWC_ASSERT(qh, <span class="stringliteral">"qh is not allocated\n"</span>);
+<a name="l02812"></a>02812         <span class="keywordflow">return</span> qh-&gt;usecs;
+<a name="l02813"></a>02813 }
+<a name="l02814"></a>02814 
+<a name="l02815"></a><a class="code" href="dwc__otg__hcd__if_8h.html#464f920221173fe04c756a9d6657f321">02815</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd_8c.html#464f920221173fe04c756a9d6657f321">dwc_otg_hcd_dump_state</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd)
+<a name="l02816"></a>02816 {
+<a name="l02817"></a>02817 <span class="preprocessor">#ifdef DEBUG</span>
+<a name="l02818"></a>02818 <span class="preprocessor"></span>        <span class="keywordtype">int</span> num_channels;
+<a name="l02819"></a>02819         <span class="keywordtype">int</span> i;
+<a name="l02820"></a>02820         <a class="code" href="uniongnptxsts__data.html">gnptxsts_data_t</a> np_tx_status;
+<a name="l02821"></a>02821         <a class="code" href="unionhptxsts__data.html">hptxsts_data_t</a> p_tx_status;
+<a name="l02822"></a>02822 
+<a name="l02823"></a>02823         num_channels = hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#c1b433c6965aa7d48f6ca6818c592039">host_channels</a>;
+<a name="l02824"></a>02824         DWC_PRINTF(<span class="stringliteral">"\n"</span>);
+<a name="l02825"></a>02825         DWC_PRINTF
+<a name="l02826"></a>02826             (<span class="stringliteral">"************************************************************\n"</span>);
+<a name="l02827"></a>02827         DWC_PRINTF(<span class="stringliteral">"HCD State:\n"</span>);
+<a name="l02828"></a>02828         DWC_PRINTF(<span class="stringliteral">"  Num channels: %d\n"</span>, num_channels);
+<a name="l02829"></a>02829         <span class="keywordflow">for</span> (i = 0; i &lt; num_channels; i++) {
+<a name="l02830"></a>02830                 <a class="code" href="structdwc__hc.html">dwc_hc_t</a> *hc = hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#cb393f6a676fb106e0e3d35396fb97f9">hc_ptr_array</a>[i];
+<a name="l02831"></a>02831                 DWC_PRINTF(<span class="stringliteral">"  Channel %d:\n"</span>, i);
+<a name="l02832"></a>02832                 DWC_PRINTF(<span class="stringliteral">"    dev_addr: %d, ep_num: %d, ep_is_in: %d\n"</span>,
+<a name="l02833"></a>02833                            hc-&gt;dev_addr, hc-&gt;ep_num, hc-&gt;ep_is_in);
+<a name="l02834"></a>02834                 DWC_PRINTF(<span class="stringliteral">"    speed: %d\n"</span>, hc-&gt;speed);
+<a name="l02835"></a>02835                 DWC_PRINTF(<span class="stringliteral">"    ep_type: %d\n"</span>, hc-&gt;ep_type);
+<a name="l02836"></a>02836                 DWC_PRINTF(<span class="stringliteral">"    max_packet: %d\n"</span>, hc-&gt;max_packet);
+<a name="l02837"></a>02837                 DWC_PRINTF(<span class="stringliteral">"    data_pid_start: %d\n"</span>, hc-&gt;data_pid_start);
+<a name="l02838"></a>02838                 DWC_PRINTF(<span class="stringliteral">"    multi_count: %d\n"</span>, hc-&gt;multi_count);
+<a name="l02839"></a>02839                 DWC_PRINTF(<span class="stringliteral">"    xfer_started: %d\n"</span>, hc-&gt;xfer_started);
+<a name="l02840"></a>02840                 DWC_PRINTF(<span class="stringliteral">"    xfer_buff: %p\n"</span>, hc-&gt;xfer_buff);
+<a name="l02841"></a>02841                 DWC_PRINTF(<span class="stringliteral">"    xfer_len: %d\n"</span>, hc-&gt;xfer_len);
+<a name="l02842"></a>02842                 DWC_PRINTF(<span class="stringliteral">"    xfer_count: %d\n"</span>, hc-&gt;xfer_count);
+<a name="l02843"></a>02843                 DWC_PRINTF(<span class="stringliteral">"    halt_on_queue: %d\n"</span>, hc-&gt;halt_on_queue);
+<a name="l02844"></a>02844                 DWC_PRINTF(<span class="stringliteral">"    halt_pending: %d\n"</span>, hc-&gt;halt_pending);
+<a name="l02845"></a>02845                 DWC_PRINTF(<span class="stringliteral">"    halt_status: %d\n"</span>, hc-&gt;halt_status);
+<a name="l02846"></a>02846                 DWC_PRINTF(<span class="stringliteral">"    do_split: %d\n"</span>, hc-&gt;do_split);
+<a name="l02847"></a>02847                 DWC_PRINTF(<span class="stringliteral">"    complete_split: %d\n"</span>, hc-&gt;complete_split);
+<a name="l02848"></a>02848                 DWC_PRINTF(<span class="stringliteral">"    hub_addr: %d\n"</span>, hc-&gt;hub_addr);
+<a name="l02849"></a>02849                 DWC_PRINTF(<span class="stringliteral">"    port_addr: %d\n"</span>, hc-&gt;port_addr);
+<a name="l02850"></a>02850                 DWC_PRINTF(<span class="stringliteral">"    xact_pos: %d\n"</span>, hc-&gt;xact_pos);
+<a name="l02851"></a>02851                 DWC_PRINTF(<span class="stringliteral">"    requests: %d\n"</span>, hc-&gt;requests);
+<a name="l02852"></a>02852                 DWC_PRINTF(<span class="stringliteral">"    qh: %p\n"</span>, hc-&gt;qh);
+<a name="l02853"></a>02853                 <span class="keywordflow">if</span> (hc-&gt;xfer_started) {
+<a name="l02854"></a>02854                         <a class="code" href="unionhfnum__data.html">hfnum_data_t</a> hfnum;
+<a name="l02855"></a>02855                         <a class="code" href="unionhcchar__data.html">hcchar_data_t</a> hcchar;
+<a name="l02856"></a>02856                         <a class="code" href="unionhctsiz__data.html">hctsiz_data_t</a> hctsiz;
+<a name="l02857"></a>02857                         <a class="code" href="unionhcint__data.html">hcint_data_t</a> hcint;
+<a name="l02858"></a>02858                         <a class="code" href="unionhcintmsk__data.html">hcintmsk_data_t</a> hcintmsk;
+<a name="l02859"></a>02859                         hfnum.<a class="code" href="unionhfnum__data.html#e5ccbed3af86ac88577ded328e6c9932">d32</a> =
+<a name="l02860"></a>02860                             dwc_read_reg32(&amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;
+<a name="l02861"></a>02861                                            host_global_regs-&gt;hfnum);
+<a name="l02862"></a>02862                         hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a> =
+<a name="l02863"></a>02863                             dwc_read_reg32(&amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#7f7c107d4720641eb4141cd817211ac0">hc_regs</a>[i]-&gt;
+<a name="l02864"></a>02864                                            hcchar);
+<a name="l02865"></a>02865                         hctsiz.<a class="code" href="unionhctsiz__data.html#fb41950555c60c6015294bdefe9cd39d">d32</a> =
+<a name="l02866"></a>02866                             dwc_read_reg32(&amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#7f7c107d4720641eb4141cd817211ac0">hc_regs</a>[i]-&gt;
+<a name="l02867"></a>02867                                            hctsiz);
+<a name="l02868"></a>02868                         hcint.<a class="code" href="unionhcint__data.html#05a82fa7693f875622db744716d7f73e">d32</a> =
+<a name="l02869"></a>02869                             dwc_read_reg32(&amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#7f7c107d4720641eb4141cd817211ac0">hc_regs</a>[i]-&gt;
+<a name="l02870"></a>02870                                            hcint);
+<a name="l02871"></a>02871                         hcintmsk.<a class="code" href="unionhcintmsk__data.html#8868299fcc762e005b7f0bf67e5fbe30">d32</a> =
+<a name="l02872"></a>02872                             dwc_read_reg32(&amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#7f7c107d4720641eb4141cd817211ac0">hc_regs</a>[i]-&gt;
+<a name="l02873"></a>02873                                            hcintmsk);
+<a name="l02874"></a>02874                         DWC_PRINTF(<span class="stringliteral">"    hfnum: 0x%08x\n"</span>, hfnum.<a class="code" href="unionhfnum__data.html#e5ccbed3af86ac88577ded328e6c9932">d32</a>);
+<a name="l02875"></a>02875                         DWC_PRINTF(<span class="stringliteral">"    hcchar: 0x%08x\n"</span>, hcchar.d32);
+<a name="l02876"></a>02876                         DWC_PRINTF(<span class="stringliteral">"    hctsiz: 0x%08x\n"</span>, hctsiz.d32);
+<a name="l02877"></a>02877                         DWC_PRINTF(<span class="stringliteral">"    hcint: 0x%08x\n"</span>, hcint.d32);
+<a name="l02878"></a>02878                         DWC_PRINTF(<span class="stringliteral">"    hcintmsk: 0x%08x\n"</span>, hcintmsk.d32);
+<a name="l02879"></a>02879                 }
+<a name="l02880"></a>02880                 <span class="keywordflow">if</span> (hc-&gt;xfer_started &amp;&amp; hc-&gt;qh) {
+<a name="l02881"></a>02881                         <a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *qtd;
+<a name="l02882"></a>02882                         <a class="code" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *urb;
+<a name="l02883"></a>02883                         
+<a name="l02884"></a>02884                         DWC_CIRCLEQ_FOREACH(qtd, &amp;hc-&gt;<a class="code" href="structdwc__otg__qtd.html#f80ddcfb6edbe83a3991dd67c93a47e4">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#9567d266da8e796d3467fb16ae867f8e">qtd_list</a>, qtd_list_entry) {
+<a name="l02885"></a>02885                                 <span class="keywordflow">if</span>(!qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#c1d73f1d48eeabbdc198ad28c0882bc1">in_process</a>)
+<a name="l02886"></a>02886                                         <span class="keywordflow">break</span>;
+<a name="l02887"></a>02887                                 
+<a name="l02888"></a>02888                                 urb = qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#7e7767808e8eb9d71de0db00f57553f9">urb</a>;
+<a name="l02889"></a>02889                         DWC_PRINTF(<span class="stringliteral">"    URB Info:\n"</span>);
+<a name="l02890"></a>02890                         DWC_PRINTF(<span class="stringliteral">"      qtd: %p, urb: %p\n"</span>, qtd, urb);
+<a name="l02891"></a>02891                         <span class="keywordflow">if</span> (urb) {
+<a name="l02892"></a>02892                                 DWC_PRINTF(<span class="stringliteral">"      Dev: %d, EP: %d %s\n"</span>,
+<a name="l02893"></a>02893                                            <a class="code" href="dwc__otg__hcd_8h.html#0de365358ba4472d56c1ac8074ba926b">dwc_otg_hcd_get_dev_addr</a>(&amp;urb-&gt;
+<a name="l02894"></a>02894                                                                     pipe_info),
+<a name="l02895"></a>02895                                            <a class="code" href="dwc__otg__hcd_8h.html#367b79057f321cfa65023f4026d6c2c9">dwc_otg_hcd_get_ep_num</a>(&amp;urb-&gt;
+<a name="l02896"></a>02896                                                                   pipe_info),
+<a name="l02897"></a>02897                                            <a class="code" href="dwc__otg__hcd_8h.html#68de5629a8b45d9bec58f680fa4c820c">dwc_otg_hcd_is_pipe_in</a>(&amp;urb-&gt;
+<a name="l02898"></a>02898                                                                   pipe_info) ?
+<a name="l02899"></a>02899                                            <span class="stringliteral">"IN"</span> : <span class="stringliteral">"OUT"</span>);
+<a name="l02900"></a>02900                                 DWC_PRINTF(<span class="stringliteral">"      Max packet size: %d\n"</span>,
+<a name="l02901"></a>02901                                            <a class="code" href="dwc__otg__hcd_8h.html#e47df3e0ac1c8ccc916e0c0895568c88">dwc_otg_hcd_get_mps</a>(&amp;urb-&gt;
+<a name="l02902"></a>02902                                                                pipe_info));
+<a name="l02903"></a>02903                                 DWC_PRINTF(<span class="stringliteral">"      transfer_buffer: %p\n"</span>,
+<a name="l02904"></a>02904                                            urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#99ae35ffcd6147ddb93b361ab3bcfe95">buf</a>);
+<a name="l02905"></a>02905                                 DWC_PRINTF(<span class="stringliteral">"      transfer_dma: %p\n"</span>,
+<a name="l02906"></a>02906                                            (<span class="keywordtype">void</span> *)urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#4e177a55239e95ae2f6c8b6b913f67fc">dma</a>);
+<a name="l02907"></a>02907                                 DWC_PRINTF(<span class="stringliteral">"      transfer_buffer_length: %d\n"</span>,
+<a name="l02908"></a>02908                                            urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#dca57de4fdecd894241ce24167206a45">length</a>);
+<a name="l02909"></a>02909                                 DWC_PRINTF(<span class="stringliteral">"      actual_length: %d\n"</span>,
+<a name="l02910"></a>02910                                            urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#742c8a97d3867ab89148eae34e0c73a6">actual_length</a>);
+<a name="l02911"></a>02911                         }
+<a name="l02912"></a>02912                 }
+<a name="l02913"></a>02913         }
+<a name="l02914"></a>02914         }
+<a name="l02915"></a>02915         DWC_PRINTF(<span class="stringliteral">"  non_periodic_channels: %d\n"</span>, hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e7fff26b5cce7c6c520c89f9e3c75617">non_periodic_channels</a>);
+<a name="l02916"></a>02916         DWC_PRINTF(<span class="stringliteral">"  periodic_channels: %d\n"</span>, hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#5754b87bd4644fbb7b90cf843c638f1c">periodic_channels</a>);
+<a name="l02917"></a>02917         DWC_PRINTF(<span class="stringliteral">"  periodic_usecs: %d\n"</span>, hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#1f2ce690c8ded506eff8d1b567747235">periodic_usecs</a>);
+<a name="l02918"></a>02918         np_tx_status.<a class="code" href="uniongnptxsts__data.html#a58b5adbe6bd0344c4f585ef6aba4672">d32</a> =
+<a name="l02919"></a>02919             dwc_read_reg32(&amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#57dabea6f6e0bf9e1ee8e94f55b9e465">gnptxsts</a>);
+<a name="l02920"></a>02920         DWC_PRINTF(<span class="stringliteral">"  NP Tx Req Queue Space Avail: %d\n"</span>,
+<a name="l02921"></a>02921                    np_tx_status.<a class="code" href="uniongnptxsts__data.html#be1d1adf7b827616ebbbf6bf564c0738">b</a>.<a class="code" href="uniongnptxsts__data.html#634ffd5e84bc422ddef043574d8f0957">nptxqspcavail</a>);
+<a name="l02922"></a>02922         DWC_PRINTF(<span class="stringliteral">"  NP Tx FIFO Space Avail: %d\n"</span>,
+<a name="l02923"></a>02923                    np_tx_status.<a class="code" href="uniongnptxsts__data.html#be1d1adf7b827616ebbbf6bf564c0738">b</a>.<a class="code" href="uniongnptxsts__data.html#6c149be246bcf5ca5395f67e67648207">nptxfspcavail</a>);
+<a name="l02924"></a>02924         p_tx_status.<a class="code" href="unionhptxsts__data.html#b48d41d449d8f71c0b184b38029c26bc">d32</a> =
+<a name="l02925"></a>02925             dwc_read_reg32(&amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#ff9692c2e10ca2bc7e24f981f25179c2">host_global_regs</a>-&gt;<a class="code" href="structdwc__otg__host__global__regs.html#bf1a1528a2e479d86318d49ecd52ee40">hptxsts</a>);
+<a name="l02926"></a>02926         DWC_PRINTF(<span class="stringliteral">"  P Tx Req Queue Space Avail: %d\n"</span>,
+<a name="l02927"></a>02927                    p_tx_status.<a class="code" href="unionhptxsts__data.html#a6839185cc4aeabf771f04f1b2a97ec3">b</a>.<a class="code" href="unionhptxsts__data.html#8139e6eafb7b0bbb3cbafa125d5cd28f">ptxqspcavail</a>);
+<a name="l02928"></a>02928         DWC_PRINTF(<span class="stringliteral">"  P Tx FIFO Space Avail: %d\n"</span>, p_tx_status.<a class="code" href="unionhptxsts__data.html#a6839185cc4aeabf771f04f1b2a97ec3">b</a>.<a class="code" href="unionhptxsts__data.html#0df6fb1f76396da626715d6ffc06dfa8">ptxfspcavail</a>);
+<a name="l02929"></a>02929         <a class="code" href="dwc__otg__hcd_8c.html#b2c46e92cdc57b1783f445ed60cc3f38">dwc_otg_hcd_dump_frrem</a>(hcd);
+<a name="l02930"></a>02930         <a class="code" href="dwc__otg__cil_8c.html#118ecda931e2b745f76fde129ff707c2">dwc_otg_dump_global_registers</a>(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>);
+<a name="l02931"></a>02931         <a class="code" href="dwc__otg__cil_8c.html#e85d3d04799b17226fcb00ea2074ca63">dwc_otg_dump_host_registers</a>(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>);
+<a name="l02932"></a>02932         DWC_PRINTF
+<a name="l02933"></a>02933             (<span class="stringliteral">"************************************************************\n"</span>);
+<a name="l02934"></a>02934         DWC_PRINTF(<span class="stringliteral">"\n"</span>);
+<a name="l02935"></a>02935 <span class="preprocessor">#endif</span>
+<a name="l02936"></a>02936 <span class="preprocessor"></span>}
+<a name="l02937"></a>02937 
+<a name="l02938"></a>02938 <span class="preprocessor">#ifdef DEBUG</span>
+<a name="l02939"></a>02939 <span class="preprocessor"></span><span class="keywordtype">void</span> dwc_print_setup_data(uint8_t * setup)
+<a name="l02940"></a>02940 {
+<a name="l02941"></a>02941         <span class="keywordtype">int</span> i;
+<a name="l02942"></a>02942         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__dbg_8h.html#7a96217c88a4d786f6cb3d4df09dee04">CHK_DEBUG_LEVEL</a>(<a class="code" href="dwc__otg__dbg_8h.html#e4a050e176c1c4f556da2b276a8c2b37">DBG_HCD</a>)) {
+<a name="l02943"></a>02943                 DWC_PRINTF(<span class="stringliteral">"Setup Data = MSB "</span>);
+<a name="l02944"></a>02944                 <span class="keywordflow">for</span> (i = 7; i &gt;= 0; i--)
+<a name="l02945"></a>02945                         DWC_PRINTF(<span class="stringliteral">"%02x "</span>, setup[i]);
+<a name="l02946"></a>02946                 DWC_PRINTF(<span class="stringliteral">"\n"</span>);
+<a name="l02947"></a>02947                 DWC_PRINTF(<span class="stringliteral">"  bmRequestType Tranfer = %s\n"</span>,
+<a name="l02948"></a>02948                            (setup[0] &amp; 0x80) ? <span class="stringliteral">"Device-to-Host"</span> :
+<a name="l02949"></a>02949                            <span class="stringliteral">"Host-to-Device"</span>);
+<a name="l02950"></a>02950                 DWC_PRINTF(<span class="stringliteral">"  bmRequestType Type = "</span>);
+<a name="l02951"></a>02951                 <span class="keywordflow">switch</span> ((setup[0] &amp; 0x60) &gt;&gt; 5) {
+<a name="l02952"></a>02952                 <span class="keywordflow">case</span> 0:
+<a name="l02953"></a>02953                         DWC_PRINTF(<span class="stringliteral">"Standard\n"</span>);
+<a name="l02954"></a>02954                         <span class="keywordflow">break</span>;
+<a name="l02955"></a>02955                 <span class="keywordflow">case</span> 1:
+<a name="l02956"></a>02956                         DWC_PRINTF(<span class="stringliteral">"Class\n"</span>);
+<a name="l02957"></a>02957                         <span class="keywordflow">break</span>;
+<a name="l02958"></a>02958                 <span class="keywordflow">case</span> 2:
+<a name="l02959"></a>02959                         DWC_PRINTF(<span class="stringliteral">"Vendor\n"</span>);
+<a name="l02960"></a>02960                         <span class="keywordflow">break</span>;
+<a name="l02961"></a>02961                 <span class="keywordflow">case</span> 3:
+<a name="l02962"></a>02962                         DWC_PRINTF(<span class="stringliteral">"Reserved\n"</span>);
+<a name="l02963"></a>02963                         <span class="keywordflow">break</span>;
+<a name="l02964"></a>02964                 }
+<a name="l02965"></a>02965                 DWC_PRINTF(<span class="stringliteral">"  bmRequestType Recipient = "</span>);
+<a name="l02966"></a>02966                 <span class="keywordflow">switch</span> (setup[0] &amp; 0x1f) {
+<a name="l02967"></a>02967                 <span class="keywordflow">case</span> 0:
+<a name="l02968"></a>02968                         DWC_PRINTF(<span class="stringliteral">"Device\n"</span>);
+<a name="l02969"></a>02969                         <span class="keywordflow">break</span>;
+<a name="l02970"></a>02970                 <span class="keywordflow">case</span> 1:
+<a name="l02971"></a>02971                         DWC_PRINTF(<span class="stringliteral">"Interface\n"</span>);
+<a name="l02972"></a>02972                         <span class="keywordflow">break</span>;
+<a name="l02973"></a>02973                 <span class="keywordflow">case</span> 2:
+<a name="l02974"></a>02974                         DWC_PRINTF(<span class="stringliteral">"Endpoint\n"</span>);
+<a name="l02975"></a>02975                         <span class="keywordflow">break</span>;
+<a name="l02976"></a>02976                 <span class="keywordflow">case</span> 3:
+<a name="l02977"></a>02977                         DWC_PRINTF(<span class="stringliteral">"Other\n"</span>);
+<a name="l02978"></a>02978                         <span class="keywordflow">break</span>;
+<a name="l02979"></a>02979                 <span class="keywordflow">default</span>:
+<a name="l02980"></a>02980                         DWC_PRINTF(<span class="stringliteral">"Reserved\n"</span>);
+<a name="l02981"></a>02981                         <span class="keywordflow">break</span>;
+<a name="l02982"></a>02982                 }
+<a name="l02983"></a>02983                 DWC_PRINTF(<span class="stringliteral">"  bRequest = 0x%0x\n"</span>, setup[1]);
+<a name="l02984"></a>02984                 DWC_PRINTF(<span class="stringliteral">"  wValue = 0x%0x\n"</span>, *((uint16_t *) &amp; setup[2]));
+<a name="l02985"></a>02985                 DWC_PRINTF(<span class="stringliteral">"  wIndex = 0x%0x\n"</span>, *((uint16_t *) &amp; setup[4]));
+<a name="l02986"></a>02986                 DWC_PRINTF(<span class="stringliteral">"  wLength = 0x%0x\n\n"</span>, *((uint16_t *) &amp; setup[6]));
+<a name="l02987"></a>02987         }
+<a name="l02988"></a>02988 }
+<a name="l02989"></a>02989 <span class="preprocessor">#endif</span>
+<a name="l02990"></a>02990 <span class="preprocessor"></span>
+<a name="l02991"></a><a class="code" href="dwc__otg__hcd__if_8h.html#b2c46e92cdc57b1783f445ed60cc3f38">02991</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd_8c.html#b2c46e92cdc57b1783f445ed60cc3f38">dwc_otg_hcd_dump_frrem</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd)
+<a name="l02992"></a>02992 {
+<a name="l02993"></a>02993 <span class="preprocessor">#if 0</span>
+<a name="l02994"></a>02994 <span class="preprocessor"></span>        DWC_PRINTF(<span class="stringliteral">"Frame remaining at SOF:\n"</span>);
+<a name="l02995"></a>02995         DWC_PRINTF(<span class="stringliteral">"  samples %u, accum %llu, avg %llu\n"</span>,
+<a name="l02996"></a>02996                    hcd-&gt;frrem_samples, hcd-&gt;frrem_accum,
+<a name="l02997"></a>02997                    (hcd-&gt;frrem_samples &gt; 0) ?
+<a name="l02998"></a>02998                    hcd-&gt;frrem_accum / hcd-&gt;frrem_samples : 0);
+<a name="l02999"></a>02999 
+<a name="l03000"></a>03000         DWC_PRINTF(<span class="stringliteral">"\n"</span>);
+<a name="l03001"></a>03001         DWC_PRINTF(<span class="stringliteral">"Frame remaining at start_transfer (uframe 7):\n"</span>);
+<a name="l03002"></a>03002         DWC_PRINTF(<span class="stringliteral">"  samples %u, accum %llu, avg %llu\n"</span>,
+<a name="l03003"></a>03003                    hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;hfnum_7_samples,
+<a name="l03004"></a>03004                    hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;hfnum_7_frrem_accum,
+<a name="l03005"></a>03005                    (hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;hfnum_7_samples &gt;
+<a name="l03006"></a>03006                     0) ? hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;hfnum_7_frrem_accum /
+<a name="l03007"></a>03007                    hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;hfnum_7_samples : 0);
+<a name="l03008"></a>03008         DWC_PRINTF(<span class="stringliteral">"Frame remaining at start_transfer (uframe 0):\n"</span>);
+<a name="l03009"></a>03009         DWC_PRINTF(<span class="stringliteral">"  samples %u, accum %llu, avg %llu\n"</span>,
+<a name="l03010"></a>03010                    hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;hfnum_0_samples,
+<a name="l03011"></a>03011                    hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;hfnum_0_frrem_accum,
+<a name="l03012"></a>03012                    (hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;hfnum_0_samples &gt;
+<a name="l03013"></a>03013                     0) ? hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;hfnum_0_frrem_accum /
+<a name="l03014"></a>03014                    hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;hfnum_0_samples : 0);
+<a name="l03015"></a>03015         DWC_PRINTF(<span class="stringliteral">"Frame remaining at start_transfer (uframe 1-6):\n"</span>);
+<a name="l03016"></a>03016         DWC_PRINTF(<span class="stringliteral">"  samples %u, accum %llu, avg %llu\n"</span>,
+<a name="l03017"></a>03017                    hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;hfnum_other_samples,
+<a name="l03018"></a>03018                    hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;hfnum_other_frrem_accum,
+<a name="l03019"></a>03019                    (hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;hfnum_other_samples &gt;
+<a name="l03020"></a>03020                     0) ? hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;hfnum_other_frrem_accum /
+<a name="l03021"></a>03021                    hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;hfnum_other_samples : 0);
+<a name="l03022"></a>03022 
+<a name="l03023"></a>03023         DWC_PRINTF(<span class="stringliteral">"\n"</span>);
+<a name="l03024"></a>03024         DWC_PRINTF(<span class="stringliteral">"Frame remaining at sample point A (uframe 7):\n"</span>);
+<a name="l03025"></a>03025         DWC_PRINTF(<span class="stringliteral">"  samples %u, accum %llu, avg %llu\n"</span>,
+<a name="l03026"></a>03026                    hcd-&gt;hfnum_7_samples_a, hcd-&gt;hfnum_7_frrem_accum_a,
+<a name="l03027"></a>03027                    (hcd-&gt;hfnum_7_samples_a &gt; 0) ?
+<a name="l03028"></a>03028                    hcd-&gt;hfnum_7_frrem_accum_a / hcd-&gt;hfnum_7_samples_a : 0);
+<a name="l03029"></a>03029         DWC_PRINTF(<span class="stringliteral">"Frame remaining at sample point A (uframe 0):\n"</span>);
+<a name="l03030"></a>03030         DWC_PRINTF(<span class="stringliteral">"  samples %u, accum %llu, avg %llu\n"</span>,
+<a name="l03031"></a>03031                    hcd-&gt;hfnum_0_samples_a, hcd-&gt;hfnum_0_frrem_accum_a,
+<a name="l03032"></a>03032                    (hcd-&gt;hfnum_0_samples_a &gt; 0) ?
+<a name="l03033"></a>03033                    hcd-&gt;hfnum_0_frrem_accum_a / hcd-&gt;hfnum_0_samples_a : 0);
+<a name="l03034"></a>03034         DWC_PRINTF(<span class="stringliteral">"Frame remaining at sample point A (uframe 1-6):\n"</span>);
+<a name="l03035"></a>03035         DWC_PRINTF(<span class="stringliteral">"  samples %u, accum %llu, avg %llu\n"</span>,
+<a name="l03036"></a>03036                    hcd-&gt;hfnum_other_samples_a, hcd-&gt;hfnum_other_frrem_accum_a,
+<a name="l03037"></a>03037                    (hcd-&gt;hfnum_other_samples_a &gt; 0) ?
+<a name="l03038"></a>03038                    hcd-&gt;hfnum_other_frrem_accum_a /
+<a name="l03039"></a>03039                    hcd-&gt;hfnum_other_samples_a : 0);
+<a name="l03040"></a>03040 
+<a name="l03041"></a>03041         DWC_PRINTF(<span class="stringliteral">"\n"</span>);
+<a name="l03042"></a>03042         DWC_PRINTF(<span class="stringliteral">"Frame remaining at sample point B (uframe 7):\n"</span>);
+<a name="l03043"></a>03043         DWC_PRINTF(<span class="stringliteral">"  samples %u, accum %llu, avg %llu\n"</span>,
+<a name="l03044"></a>03044                    hcd-&gt;hfnum_7_samples_b, hcd-&gt;hfnum_7_frrem_accum_b,
+<a name="l03045"></a>03045                    (hcd-&gt;hfnum_7_samples_b &gt; 0) ?
+<a name="l03046"></a>03046                    hcd-&gt;hfnum_7_frrem_accum_b / hcd-&gt;hfnum_7_samples_b : 0);
+<a name="l03047"></a>03047         DWC_PRINTF(<span class="stringliteral">"Frame remaining at sample point B (uframe 0):\n"</span>);
+<a name="l03048"></a>03048         DWC_PRINTF(<span class="stringliteral">"  samples %u, accum %llu, avg %llu\n"</span>,
+<a name="l03049"></a>03049                    hcd-&gt;hfnum_0_samples_b, hcd-&gt;hfnum_0_frrem_accum_b,
+<a name="l03050"></a>03050                    (hcd-&gt;hfnum_0_samples_b &gt; 0) ?
+<a name="l03051"></a>03051                    hcd-&gt;hfnum_0_frrem_accum_b / hcd-&gt;hfnum_0_samples_b : 0);
+<a name="l03052"></a>03052         DWC_PRINTF(<span class="stringliteral">"Frame remaining at sample point B (uframe 1-6):\n"</span>);
+<a name="l03053"></a>03053         DWC_PRINTF(<span class="stringliteral">"  samples %u, accum %llu, avg %llu\n"</span>,
+<a name="l03054"></a>03054                    hcd-&gt;hfnum_other_samples_b, hcd-&gt;hfnum_other_frrem_accum_b,
+<a name="l03055"></a>03055                    (hcd-&gt;hfnum_other_samples_b &gt; 0) ?
+<a name="l03056"></a>03056                    hcd-&gt;hfnum_other_frrem_accum_b /
+<a name="l03057"></a>03057                    hcd-&gt;hfnum_other_samples_b : 0);
+<a name="l03058"></a>03058 <span class="preprocessor">#endif</span>
+<a name="l03059"></a>03059 <span class="preprocessor"></span>}
+<a name="l03060"></a>03060 
+<a name="l03061"></a>03061 <span class="preprocessor">#endif                          </span><span class="comment">/* DWC_DEVICE_ONLY */</span>
+</pre></div><hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd_8c.html b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd_8c.html
new file mode 100644
index 000000000000..91f704b52ae9
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd_8c.html
@@ -0,0 +1,1837 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd.c File Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<h1>dwc_otg_hcd.c File Reference</h1>This file implements HCD Core. <a href="#_details">More...</a>
+<p>
+<code>#include &quot;<a class="el" href="dwc__otg__hcd_8h-source.html">dwc_otg_hcd.h</a>&quot;</code><br>
+<code>#include &quot;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&quot;</code><br>
+
+<p>
+<a href="dwc__otg__hcd_8c-source.html">Go to the source code of this file.</a><table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Functions</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="5595437c199432efbd3609dc87ef5afa"></a><!-- doxytag: member="dwc_otg_hcd.c::dwc_otg_hcd_alloc_hcd" ref="5595437c199432efbd3609dc87ef5afa" args="(void)" -->
+<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8c.html#5595437c199432efbd3609dc87ef5afa">dwc_otg_hcd_alloc_hcd</a> (void)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function allocates <a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd</a> structure and returns pointer on it. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8c.html#4f6f55c20aa8eb215d692195f9f0280d">dwc_otg_hcd_connect_timeout</a> (void *ptr)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Connection timeout function.  <a href="#4f6f55c20aa8eb215d692195f9f0280d"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8c.html#5a7a5af3b84b4af188fa3b60058a039c">hcd_start_func</a> (void *_vp)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Work queue function for starting the HCD when A-Cable is connected.  <a href="#5a7a5af3b84b4af188fa3b60058a039c"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="17f7272e6a2fe4515b3160ad4694ea55"></a><!-- doxytag: member="dwc_otg_hcd.c::del_xfer_timers" ref="17f7272e6a2fe4515b3160ad4694ea55" args="(dwc_otg_hcd_t *hcd)" -->
+static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8c.html#17f7272e6a2fe4515b3160ad4694ea55">del_xfer_timers</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="939a9c8afc75cbe47625e392a7c66a1a"></a><!-- doxytag: member="dwc_otg_hcd.c::del_timers" ref="939a9c8afc75cbe47625e392a7c66a1a" args="(dwc_otg_hcd_t *hcd)" -->
+static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8c.html#939a9c8afc75cbe47625e392a7c66a1a">del_timers</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8c.html#8fd9263ed86449c5440edd834cb4d766">kill_urbs_in_qh_list</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, dwc_list_link_t *qh_list)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Processes all the URBs in a single list of QHs.  <a href="#8fd9263ed86449c5440edd834cb4d766"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8c.html#63f169b583c3818268def3614ac2fe0a">kill_all_urbs</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Responds with an error status of ETIMEDOUT to all URBs in the non-periodic and periodic schedules.  <a href="#63f169b583c3818268def3614ac2fe0a"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8c.html#65c0cd2720ab3e728fffd0073b4a1aba">dwc_otg_hcd_start_connect_timer</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Start the connection timer.  <a href="#65c0cd2720ab3e728fffd0073b4a1aba"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8c.html#a0deab93f6ca3bcfcab0085b2bf86113">dwc_otg_hcd_session_start_cb</a> (void *p)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">HCD Callback function for disconnect of the HCD.  <a href="#a0deab93f6ca3bcfcab0085b2bf86113"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8c.html#1aaeb9f41b201877f86a17d617b828d2">dwc_otg_hcd_start_cb</a> (void *p)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">HCD Callback function for starting the HCD when A-Cable is connected.  <a href="#1aaeb9f41b201877f86a17d617b828d2"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8c.html#2af30c3c78408325b26e3431b2442055">dwc_otg_hcd_disconnect_cb</a> (void *p)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">HCD Callback function for disconnect of the HCD.  <a href="#2af30c3c78408325b26e3431b2442055"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8c.html#44e479b1c67b62a1887f93afd2106e4a">dwc_otg_hcd_stop_cb</a> (void *p)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">HCD Callback function for stopping the HCD.  <a href="#44e479b1c67b62a1887f93afd2106e4a"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8c.html#fb35aff10c8837095302575957145f13">dwc_otg_hcd_rem_wakeup_cb</a> (void *p)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">HCD Callback function for Remote Wakeup.  <a href="#fb35aff10c8837095302575957145f13"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8c.html#70c58e8a45eb7ad8ee2f2c74ba3a77f0">dwc_otg_hcd_stop</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Halts the DWC_otg host mode operations in a clean manner.  <a href="#70c58e8a45eb7ad8ee2f2c74ba3a77f0"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8c.html#e8129fbc0a4073f0a5f64fa3b0f5127b">dwc_otg_hcd_urb_enqueue</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *dwc_otg_urb, void **ep_handle)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Queue URB.  <a href="#e8129fbc0a4073f0a5f64fa3b0f5127b"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8c.html#8844d0e14480b7f0dcf5c8120cc20a4f">dwc_otg_hcd_urb_dequeue</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *dwc_otg_urb)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">De-queue the specified URB.  <a href="#8844d0e14480b7f0dcf5c8120cc20a4f"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8c.html#f80e9550161e354c865e3c411d661dbe">dwc_otg_hcd_endpoint_disable</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, void *ep_handle, int retry)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Frees resources in the DWC_otg controller related to a given endpoint.  <a href="#f80e9550161e354c865e3c411d661dbe"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ed4640393d701e9bbfd966d4006a60b8"></a><!-- doxytag: member="dwc_otg_hcd.c::reset_tasklet_func" ref="ed4640393d701e9bbfd966d4006a60b8" args="(void *data)" -->
+static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8c.html#ed4640393d701e9bbfd966d4006a60b8">reset_tasklet_func</a> (void *data)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Reset tasklet function. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="d76881c1efea1a13be74ecfde85b4881"></a><!-- doxytag: member="dwc_otg_hcd.c::qh_list_free" ref="d76881c1efea1a13be74ecfde85b4881" args="(dwc_otg_hcd_t *hcd, dwc_list_link_t *qh_list)" -->
+static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8c.html#d76881c1efea1a13be74ecfde85b4881">qh_list_free</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, dwc_list_link_t *qh_list)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7ee877a9be0c15bacbb92a7babb116d0"></a><!-- doxytag: member="dwc_otg_hcd.c::dwc_otg_hcd_free" ref="7ee877a9be0c15bacbb92a7babb116d0" args="(dwc_otg_hcd_t *dwc_otg_hcd)" -->
+static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8c.html#7ee877a9be0c15bacbb92a7babb116d0">dwc_otg_hcd_free</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Frees secondary storage associated with the <a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd</a> structure contained in the struct usb_hcd field. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8c.html#2d38590dadee51fd767d63e0dc675f23">dwc_otg_hcd_init</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function should be called to initiate HCD Core.  <a href="#2d38590dadee51fd767d63e0dc675f23"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8c.html#f347bcb363a622ced29161878d38830b">dwc_otg_hcd_remove</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Frees HCD.  <a href="#f347bcb363a622ced29161878d38830b"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="a9b6729ba2077bed1b6d149970d5525e"></a><!-- doxytag: member="dwc_otg_hcd.c::dwc_otg_hcd_reinit" ref="a9b6729ba2077bed1b6d149970d5525e" args="(dwc_otg_hcd_t *hcd)" -->
+static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8c.html#a9b6729ba2077bed1b6d149970d5525e">dwc_otg_hcd_reinit</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Initializes dynamic portions of the DWC_otg HCD state. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8c.html#08cefee3729196462fe6a7608046652c">assign_and_init_hc</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *qh)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Assigns transactions from a QTD to a free host channel and initializes the host channel to perform the transactions.  <a href="#08cefee3729196462fe6a7608046652c"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="el" href="dwc__otg__hcd_8h.html#92c49783eebc5bcffa8b8a51c2127be9">dwc_otg_transaction_type_e</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8c.html#96cc299f4f0478187ed7ba49b975ffc3">dwc_otg_hcd_select_transactions</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function selects transactions from the HCD transfer schedule and assigns them to available host channels.  <a href="#96cc299f4f0478187ed7ba49b975ffc3"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8c.html#8c7cd2f81cf41dbf3158f49b1d82a4f8">queue_transaction</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__hc.html">dwc_hc_t</a> *hc, uint16_t fifo_dwords_avail)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Attempts to queue a single transaction request for a host channel associated with either a periodic or non-periodic transfer.  <a href="#8c7cd2f81cf41dbf3158f49b1d82a4f8"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8c.html#00876268eb53e5ce91dbedcb026181ec">process_periodic_channels</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Processes periodic channels for the next frame and queues transactions for these channels to the DWC_otg controller.  <a href="#00876268eb53e5ce91dbedcb026181ec"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8c.html#a3f28e8605fd652c5177962e5dc8b95a">process_non_periodic_channels</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Processes active non-periodic channels and queues transactions for these channels to the DWC_otg controller.  <a href="#a3f28e8605fd652c5177962e5dc8b95a"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8c.html#2f57bf2fc3013d63101f112702b913a0">dwc_otg_hcd_queue_transactions</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="dwc__otg__hcd_8h.html#92c49783eebc5bcffa8b8a51c2127be9">dwc_otg_transaction_type_e</a> tr_type)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function processes the currently active host channels and queues transactions for these channels to the DWC_otg controller.  <a href="#2f57bf2fc3013d63101f112702b913a0"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8c.html#e3bd4e9d1f641cdd29df6633bfb1ebd2">dwc_otg_hcd_hub_control</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>, uint16_t typeReq, uint16_t wValue, uint16_t wIndex, uint8_t *buf, uint16_t wLength)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Handles hub class-specific requests.  <a href="#e3bd4e9d1f641cdd29df6633bfb1ebd2"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8c.html#0d324c8dbb0c7cbadec8cebf943fc84b">dwc_otg_hcd_is_status_changed</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, int port)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Returns 1 if status of specified port is changed and 0 otherwise.  <a href="#0d324c8dbb0c7cbadec8cebf943fc84b"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8c.html#f06514bd6f8c219cc72d1f467a82c056">dwc_otg_hcd_get_frame_number</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Returns current frame number.  <a href="#f06514bd6f8c219cc72d1f467a82c056"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8c.html#7242be8ebc7f7516292cbe2344ab03be">dwc_otg_hcd_start</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, struct <a class="el" href="structdwc__otg__hcd__function__ops.html">dwc_otg_hcd_function_ops</a> *<a class="el" href="dwc__otg__pcd__linux_8c.html#9ce9b5e49c60906c189bee157dd68acd">fops</a>)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function initializes the HCD Core.  <a href="#7242be8ebc7f7516292cbe2344ab03be"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8c.html#7740268b2d0fd8d25aaaeacfa5aef5cf">dwc_otg_hcd_get_priv_data</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Returns private data set by dwc_otg_hcd_set_priv_data function.  <a href="#7740268b2d0fd8d25aaaeacfa5aef5cf"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8c.html#c73ca7d4284c8f0de7338a66607e4eb1">dwc_otg_hcd_set_priv_data</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, void *priv_data)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Set private data.  <a href="#c73ca7d4284c8f0de7338a66607e4eb1"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8c.html#e7d3657931984a1ce1cee5cf47cb08f3">dwc_otg_hcd_otg_port</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Returns otg port number.  <a href="#e7d3657931984a1ce1cee5cf47cb08f3"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8c.html#ca25b33b440a4ef112ee459c26c14adc">dwc_otg_hcd_is_b_host</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Returns 1 if currently core is acting as B host, and 0 otherwise.  <a href="#ca25b33b440a4ef112ee459c26c14adc"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8c.html#264fc9d293c76e42dded9dee2cf44283">dwc_otg_hcd_urb_alloc</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, int iso_desc_count, int atomic_alloc)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Allocates memory for <a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb</a> structure.  <a href="#264fc9d293c76e42dded9dee2cf44283"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8c.html#4aca8781f512198149388799a8ae9aba">dwc_otg_hcd_urb_set_pipeinfo</a> (<a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *dwc_otg_urb, uint8_t dev_addr, uint8_t ep_num, uint8_t ep_type, uint8_t ep_dir, uint16_t mps)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Set pipe information in URB.  <a href="#4aca8781f512198149388799a8ae9aba"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8c.html#d141b0ed3f2eac3f8aab2d8cefe34345">dwc_otg_hcd_urb_set_params</a> (<a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *dwc_otg_urb, void *urb_handle, void *buf, dwc_dma_t dma, uint32_t buflen, void *setup_packet, dwc_dma_t setup_dma, uint32_t flags, uint16_t interval)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Sets <a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb</a> parameters.  <a href="#d141b0ed3f2eac3f8aab2d8cefe34345"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8c.html#81b7aad80889affb1e63cf1307b88fb6">dwc_otg_hcd_urb_get_status</a> (<a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *dwc_otg_urb)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Gets status from <a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb</a>.  <a href="#81b7aad80889affb1e63cf1307b88fb6"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8c.html#3260f5db4ea20074da16b292eb1a686b">dwc_otg_hcd_urb_get_actual_length</a> (<a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *dwc_otg_urb)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Gets actual length from <a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb</a>.  <a href="#3260f5db4ea20074da16b292eb1a686b"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8c.html#816cc30c3129fc8911a458355d977129">dwc_otg_hcd_urb_get_error_count</a> (<a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *dwc_otg_urb)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Gets error count from <a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb</a>.  <a href="#816cc30c3129fc8911a458355d977129"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8c.html#8617e93eba1bfd6466a9af1e6d2f731b">dwc_otg_hcd_urb_set_iso_desc_params</a> (<a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *dwc_otg_urb, int desc_num, uint32_t offset, uint32_t length)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Set ISOC descriptor offset and length.  <a href="#8617e93eba1bfd6466a9af1e6d2f731b"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8c.html#fde27182e452709e10c1100ea57aa46b">dwc_otg_hcd_urb_get_iso_desc_status</a> (<a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *dwc_otg_urb, int desc_num)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get status of ISOC descriptor, specified by desc_num.  <a href="#fde27182e452709e10c1100ea57aa46b"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8c.html#c6d28fc3e6aedb29d46a793423c4de0a">dwc_otg_hcd_urb_get_iso_desc_actual_length</a> (<a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *dwc_otg_urb, int desc_num)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get actual length of ISOC descriptor, specified by desc_num.  <a href="#c6d28fc3e6aedb29d46a793423c4de0a"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8c.html#5deb69c332ba937b959c9dccadd87568">dwc_otg_hcd_is_bandwidth_allocated</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, void *ep_handle)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Call this function to check if bandwidth was allocated for specified endpoint.  <a href="#5deb69c332ba937b959c9dccadd87568"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8c.html#ad28eed057375c7f31663dc777edefd7">dwc_otg_hcd_is_bandwidth_freed</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, void *ep_handle)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Call this function to check if bandwidth was freed for specified endpoint.  <a href="#ad28eed057375c7f31663dc777edefd7"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8c.html#bd160be911ccc8f90141dae9c40276eb">dwc_otg_hcd_get_ep_bandwidth</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, void *ep_handle)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Returns bandwidth allocated for specified endpoint in microseconds.  <a href="#bd160be911ccc8f90141dae9c40276eb"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8c.html#464f920221173fe04c756a9d6657f321">dwc_otg_hcd_dump_state</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Dumps hcd state.  <a href="#464f920221173fe04c756a9d6657f321"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8c.html#b2c46e92cdc57b1783f445ed60cc3f38">dwc_otg_hcd_dump_frrem</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Dump the average frame remaining at SOF.  <a href="#b2c46e92cdc57b1783f445ed60cc3f38"></a><br></td></tr>
+<tr><td colspan="2"><br><h2>Variables</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static <a class="el" href="structdwc__otg__cil__callbacks.html">dwc_otg_cil_callbacks_t</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8c.html#106ff6cbb1499325ea75f2d97abb8e6a">hcd_cil_callbacks</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">HCD Callback structure for handling mode switching.  <a href="#106ff6cbb1499325ea75f2d97abb8e6a"></a><br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This file implements HCD Core. 
+<p>
+All code in this file is portable and don't use any OS specific functions. Interface provided by HCD Core is defined in <code>&lt;hcd_if.h&gt;</code> header file. 
+<p>
+Definition in file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.<hr><h2>Function Documentation</h2>
+<a class="anchor" name="4f6f55c20aa8eb215d692195f9f0280d"></a><!-- doxytag: member="dwc_otg_hcd.c::dwc_otg_hcd_connect_timeout" ref="4f6f55c20aa8eb215d692195f9f0280d" args="(void *ptr)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_hcd_connect_timeout           </td>
+          <td>(</td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>ptr</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Connection timeout function. 
+<p>
+An OTG host is required to display a message if the device does not connect within 10 seconds. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l00054">54</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="5a7a5af3b84b4af188fa3b60058a039c"></a><!-- doxytag: member="dwc_otg_hcd.c::hcd_start_func" ref="5a7a5af3b84b4af188fa3b60058a039c" args="(void *_vp)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static void hcd_start_func           </td>
+          <td>(</td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>_vp</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Work queue function for starting the HCD when A-Cable is connected. 
+<p>
+The <a class="el" href="dwc__otg__cil__intr_8c.html#fc2d933cd662b3d060747004c79203a1">hcd_start()</a> must be called in a process context. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l00123">123</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="8fd9263ed86449c5440edd834cb4d766"></a><!-- doxytag: member="dwc_otg_hcd.c::kill_urbs_in_qh_list" ref="8fd9263ed86449c5440edd834cb4d766" args="(dwc_otg_hcd_t *hcd, dwc_list_link_t *qh_list)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static void kill_urbs_in_qh_list           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">dwc_list_link_t *&nbsp;</td>
+          <td class="paramname"> <em>qh_list</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Processes all the URBs in a single list of QHs. 
+<p>
+Completes them with -ETIMEDOUT and frees the QTD. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l00154">154</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="63f169b583c3818268def3614ac2fe0a"></a><!-- doxytag: member="dwc_otg_hcd.c::kill_all_urbs" ref="63f169b583c3818268def3614ac2fe0a" args="(dwc_otg_hcd_t *hcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static void kill_all_urbs           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Responds with an error status of ETIMEDOUT to all URBs in the non-periodic and periodic schedules. 
+<p>
+The QTD associated with each URB is removed from the schedule and freed. This function may be called when a disconnect is detected or when the HCD is being stopped. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l00182">182</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="65c0cd2720ab3e728fffd0073b4a1aba"></a><!-- doxytag: member="dwc_otg_hcd.c::dwc_otg_hcd_start_connect_timer" ref="65c0cd2720ab3e728fffd0073b4a1aba" args="(dwc_otg_hcd_t *hcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static void dwc_otg_hcd_start_connect_timer           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Start the connection timer. 
+<p>
+An OTG host is required to display a message if the device does not connect within 10 seconds. The timer is deleted if a port connect interrupt occurs before the timer expires. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l00198">198</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="a0deab93f6ca3bcfcab0085b2bf86113"></a><!-- doxytag: member="dwc_otg_hcd.c::dwc_otg_hcd_session_start_cb" ref="a0deab93f6ca3bcfcab0085b2bf86113" args="(void *p)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static int32_t dwc_otg_hcd_session_start_cb           </td>
+          <td>(</td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>p</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+HCD Callback function for disconnect of the HCD. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>p</em>&nbsp;</td><td>void pointer to the <code>struct usb_hcd</code> </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l00208">208</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="1aaeb9f41b201877f86a17d617b828d2"></a><!-- doxytag: member="dwc_otg_hcd.c::dwc_otg_hcd_start_cb" ref="1aaeb9f41b201877f86a17d617b828d2" args="(void *p)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static int32_t dwc_otg_hcd_start_cb           </td>
+          <td>(</td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>p</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+HCD Callback function for starting the HCD when A-Cable is connected. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>p</em>&nbsp;</td><td>void pointer to the <code>struct usb_hcd</code> </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l00223">223</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="2af30c3c78408325b26e3431b2442055"></a><!-- doxytag: member="dwc_otg_hcd.c::dwc_otg_hcd_disconnect_cb" ref="2af30c3c78408325b26e3431b2442055" args="(void *p)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static int32_t dwc_otg_hcd_disconnect_cb           </td>
+          <td>(</td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>p</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+HCD Callback function for disconnect of the HCD. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>p</em>&nbsp;</td><td>void pointer to the <code>struct usb_hcd</code> </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l00253">253</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="44e479b1c67b62a1887f93afd2106e4a"></a><!-- doxytag: member="dwc_otg_hcd.c::dwc_otg_hcd_stop_cb" ref="44e479b1c67b62a1887f93afd2106e4a" args="(void *p)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static int32_t dwc_otg_hcd_stop_cb           </td>
+          <td>(</td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>p</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+HCD Callback function for stopping the HCD. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>p</em>&nbsp;</td><td>void pointer to the <code>struct usb_hcd</code> </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l00373">373</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="fb35aff10c8837095302575957145f13"></a><!-- doxytag: member="dwc_otg_hcd.c::dwc_otg_hcd_rem_wakeup_cb" ref="fb35aff10c8837095302575957145f13" args="(void *p)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static int dwc_otg_hcd_rem_wakeup_cb           </td>
+          <td>(</td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>p</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+HCD Callback function for Remote Wakeup. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>p</em>&nbsp;</td><td>void pointer to the <code>struct usb_hcd</code> </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l00403">403</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="70c58e8a45eb7ad8ee2f2c74ba3a77f0"></a><!-- doxytag: member="dwc_otg_hcd.c::dwc_otg_hcd_stop" ref="70c58e8a45eb7ad8ee2f2c74ba3a77f0" args="(dwc_otg_hcd_t *hcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_hcd_stop           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Halts the DWC_otg host mode operations in a clean manner. 
+<p>
+USB transfers are stopped. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l00422">422</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="e8129fbc0a4073f0a5f64fa3b0f5127b"></a><!-- doxytag: member="dwc_otg_hcd.c::dwc_otg_hcd_urb_enqueue" ref="e8129fbc0a4073f0a5f64fa3b0f5127b" args="(dwc_otg_hcd_t *hcd, dwc_otg_hcd_urb_t *dwc_otg_urb, void **ep_handle)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_hcd_urb_enqueue           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>dwc_otg_hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>dwc_otg_urb</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void **&nbsp;</td>
+          <td class="paramname"> <em>ep_handle</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Queue URB. 
+<p>
+After transfer is completes, the complete callback will be called with the URB status<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd</a></em>&nbsp;</td><td>The HCD </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>dwc_otg_urb</em>&nbsp;</td><td>DWC_OTG URB </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep_handle</em>&nbsp;</td><td>Out parameter for returning endpoint handle</td></tr>
+  </table>
+</dl>
+Returns -DWC_E_NO_DEVICE if no device is connected. Returns -DWC_E_NO_MEMORY if there is no enough memory. Returns 0 on success. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l00444">444</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="8844d0e14480b7f0dcf5c8120cc20a4f"></a><!-- doxytag: member="dwc_otg_hcd.c::dwc_otg_hcd_urb_dequeue" ref="8844d0e14480b7f0dcf5c8120cc20a4f" args="(dwc_otg_hcd_t *hcd, dwc_otg_hcd_urb_t *dwc_otg_urb)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_hcd_urb_dequeue           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>dwc_otg_hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>dwc_otg_urb</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+De-queue the specified URB. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd</a></em>&nbsp;</td><td>The HCD </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>dwc_otg_urb</em>&nbsp;</td><td>DWC_OTG URB </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l00489">489</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="f80e9550161e354c865e3c411d661dbe"></a><!-- doxytag: member="dwc_otg_hcd.c::dwc_otg_hcd_endpoint_disable" ref="f80e9550161e354c865e3c411d661dbe" args="(dwc_otg_hcd_t *hcd, void *ep_handle, int retry)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_hcd_endpoint_disable           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>ep_handle</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>retry</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Frees resources in the DWC_otg controller related to a given endpoint. 
+<p>
+Any URBs for the endpoint must already be dequeued.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep_handle</em>&nbsp;</td><td>Endpoint handle, returned by dwc_otg_hcd_urb_enqueue function </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>retry</em>&nbsp;</td><td>Number of retries if there are queued transfers.</td></tr>
+  </table>
+</dl>
+Returns -DWC_E_INVALID if invalid arguments are passed. Returns 0 on success 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l00547">547</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="2d38590dadee51fd767d63e0dc675f23"></a><!-- doxytag: member="dwc_otg_hcd.c::dwc_otg_hcd_init" ref="2d38590dadee51fd767d63e0dc675f23" args="(dwc_otg_hcd_t *hcd, dwc_otg_core_if_t *core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_hcd_init           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function should be called to initiate HCD Core. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>The DWC_OTG Core</td></tr>
+  </table>
+</dl>
+Returns -DWC_E_NO_MEMORY if no enough memory. Returns 0 on success 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l00693">693</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="f347bcb363a622ced29161878d38830b"></a><!-- doxytag: member="dwc_otg_hcd.c::dwc_otg_hcd_remove" ref="f347bcb363a622ced29161878d38830b" args="(dwc_otg_hcd_t *hcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_hcd_remove           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Frees HCD. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l00778">778</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="08cefee3729196462fe6a7608046652c"></a><!-- doxytag: member="dwc_otg_hcd.c::assign_and_init_hc" ref="08cefee3729196462fe6a7608046652c" args="(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static void assign_and_init_hc           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>qh</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Assigns transactions from a QTD to a free host channel and initializes the host channel to perform the transactions. 
+<p>
+The host channel is removed from the free list.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD state structure. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>qh</em>&nbsp;</td><td>Transactions from the first QTD for this QH are selected and assigned to a free host channel. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l00832">832</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="96cc299f4f0478187ed7ba49b975ffc3"></a><!-- doxytag: member="dwc_otg_hcd.c::dwc_otg_hcd_select_transactions" ref="96cc299f4f0478187ed7ba49b975ffc3" args="(dwc_otg_hcd_t *hcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="dwc__otg__hcd_8h.html#92c49783eebc5bcffa8b8a51c2127be9">dwc_otg_transaction_type_e</a> dwc_otg_hcd_select_transactions           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function selects transactions from the HCD transfer schedule and assigns them to available host channels. 
+<p>
+It is called from HCD interrupt handler functions.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD state structure.</td></tr>
+  </table>
+</dl>
+<dl compact><dt><b>Returns:</b></dt><dd>The types of new transactions that were assigned to host channels. </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l01055">1055</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="8c7cd2f81cf41dbf3158f49b1d82a4f8"></a><!-- doxytag: member="dwc_otg_hcd.c::queue_transaction" ref="8c7cd2f81cf41dbf3158f49b1d82a4f8" args="(dwc_otg_hcd_t *hcd, dwc_hc_t *hc, uint16_t fifo_dwords_avail)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static int queue_transaction           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__hc.html">dwc_hc_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint16_t&nbsp;</td>
+          <td class="paramname"> <em>fifo_dwords_avail</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Attempts to queue a single transaction request for a host channel associated with either a periodic or non-periodic transfer. 
+<p>
+This function assumes that there is space available in the appropriate request queue. For an OUT transfer or SETUP transaction in Slave mode, it checks whether space is available in the appropriate Tx FIFO.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD state structure. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>hc</em>&nbsp;</td><td>Host channel descriptor associated with either a periodic or non-periodic transfer. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>fifo_dwords_avail</em>&nbsp;</td><td>Number of DWORDs available in the periodic Tx FIFO for periodic transfers or the non-periodic Tx FIFO for non-periodic transfers.</td></tr>
+  </table>
+</dl>
+<dl compact><dt><b>Returns:</b></dt><dd>1 if a request is queued and more requests may be needed to complete the transfer, 0 if no more requests are required for this transfer, -1 if there is insufficient space in the Tx FIFO. </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l01139">1139</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="00876268eb53e5ce91dbedcb026181ec"></a><!-- doxytag: member="dwc_otg_hcd.c::process_periodic_channels" ref="00876268eb53e5ce91dbedcb026181ec" args="(dwc_otg_hcd_t *hcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static void process_periodic_channels           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Processes periodic channels for the next frame and queues transactions for these channels to the DWC_otg controller. 
+<p>
+After queueing transactions, the Periodic Tx FIFO Empty interrupt is enabled if there are more transactions to queue as Periodic Tx FIFO or request queue space becomes available. Otherwise, the Periodic Tx FIFO Empty interrupt is disabled. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l01199">1199</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="a3f28e8605fd652c5177962e5dc8b95a"></a><!-- doxytag: member="dwc_otg_hcd.c::process_non_periodic_channels" ref="a3f28e8605fd652c5177962e5dc8b95a" args="(dwc_otg_hcd_t *hcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static void process_non_periodic_channels           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Processes active non-periodic channels and queues transactions for these channels to the DWC_otg controller. 
+<p>
+After queueing transactions, the NP Tx FIFO Empty interrupt is enabled if there are more transactions to queue as NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx FIFO Empty interrupt is disabled. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l01316">1316</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="2f57bf2fc3013d63101f112702b913a0"></a><!-- doxytag: member="dwc_otg_hcd.c::dwc_otg_hcd_queue_transactions" ref="2f57bf2fc3013d63101f112702b913a0" args="(dwc_otg_hcd_t *hcd, dwc_otg_transaction_type_e tr_type)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_hcd_queue_transactions           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="dwc__otg__hcd_8h.html#92c49783eebc5bcffa8b8a51c2127be9">dwc_otg_transaction_type_e</a>&nbsp;</td>
+          <td class="paramname"> <em>tr_type</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function processes the currently active host channels and queues transactions for these channels to the DWC_otg controller. 
+<p>
+It is called from HCD interrupt handler functions.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD state structure. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>tr_type</em>&nbsp;</td><td>The type(s) of transactions to queue (non-periodic, periodic, or both). </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l01426">1426</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="e3bd4e9d1f641cdd29df6633bfb1ebd2"></a><!-- doxytag: member="dwc_otg_hcd.c::dwc_otg_hcd_hub_control" ref="e3bd4e9d1f641cdd29df6633bfb1ebd2" args="(dwc_otg_hcd_t *dwc_otg_hcd, uint16_t typeReq, uint16_t wValue, uint16_t wIndex, uint8_t *buf, uint16_t wLength)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_hcd_hub_control           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>dwc_otg_hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint16_t&nbsp;</td>
+          <td class="paramname"> <em>typeReq</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint16_t&nbsp;</td>
+          <td class="paramname"> <em>wValue</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint16_t&nbsp;</td>
+          <td class="paramname"> <em>wIndex</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>buf</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint16_t&nbsp;</td>
+          <td class="paramname"> <em>wLength</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Handles hub class-specific requests. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd</a></em>&nbsp;</td><td>The HCD </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>typeReq</em>&nbsp;</td><td>Request Type </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>wValue</em>&nbsp;</td><td>wValue from control request </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>wIndex</em>&nbsp;</td><td>wIndex from control request </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>buf</em>&nbsp;</td><td>data buffer </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>wLength</em>&nbsp;</td><td>data buffer length</td></tr>
+  </table>
+</dl>
+Returns -DWC_E_INVALID if invalid argument is passed Returns 0 on success 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l01905">1905</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="0d324c8dbb0c7cbadec8cebf943fc84b"></a><!-- doxytag: member="dwc_otg_hcd.c::dwc_otg_hcd_is_status_changed" ref="0d324c8dbb0c7cbadec8cebf943fc84b" args="(dwc_otg_hcd_t *hcd, int port)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_hcd_is_status_changed           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>port</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Returns 1 if status of specified port is changed and 0 otherwise. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>port</em>&nbsp;</td><td>Port number </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l02611">2611</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="f06514bd6f8c219cc72d1f467a82c056"></a><!-- doxytag: member="dwc_otg_hcd.c::dwc_otg_hcd_get_frame_number" ref="f06514bd6f8c219cc72d1f467a82c056" args="(dwc_otg_hcd_t *dwc_otg_hcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_hcd_get_frame_number           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Returns current frame number. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l02643">2643</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="7242be8ebc7f7516292cbe2344ab03be"></a><!-- doxytag: member="dwc_otg_hcd.c::dwc_otg_hcd_start" ref="7242be8ebc7f7516292cbe2344ab03be" args="(dwc_otg_hcd_t *hcd, struct dwc_otg_hcd_function_ops *fops)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_hcd_start           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">struct <a class="el" href="structdwc__otg__hcd__function__ops.html">dwc_otg_hcd_function_ops</a> *&nbsp;</td>
+          <td class="paramname"> <em>fops</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function initializes the HCD Core. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>fops</em>&nbsp;</td><td>The Function Driver Operations data structure containing pointers to all callbacks.</td></tr>
+  </table>
+</dl>
+Returns -DWC_E_NO_DEVICE if Core is currently is in device mode. Returns 0 on success 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l02656">2656</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="7740268b2d0fd8d25aaaeacfa5aef5cf"></a><!-- doxytag: member="dwc_otg_hcd.c::dwc_otg_hcd_get_priv_data" ref="7740268b2d0fd8d25aaaeacfa5aef5cf" args="(dwc_otg_hcd_t *hcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void* dwc_otg_hcd_get_priv_data           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Returns private data set by dwc_otg_hcd_set_priv_data function. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l02671">2671</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="c73ca7d4284c8f0de7338a66607e4eb1"></a><!-- doxytag: member="dwc_otg_hcd.c::dwc_otg_hcd_set_priv_data" ref="c73ca7d4284c8f0de7338a66607e4eb1" args="(dwc_otg_hcd_t *hcd, void *priv_data)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_hcd_set_priv_data           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>priv_data</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Set private data. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>priv_data</em>&nbsp;</td><td>pointer to be stored in private data </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l02676">2676</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="e7d3657931984a1ce1cee5cf47cb08f3"></a><!-- doxytag: member="dwc_otg_hcd.c::dwc_otg_hcd_otg_port" ref="e7d3657931984a1ce1cee5cf47cb08f3" args="(dwc_otg_hcd_t *hcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t dwc_otg_hcd_otg_port           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Returns otg port number. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l02681">2681</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="ca25b33b440a4ef112ee459c26c14adc"></a><!-- doxytag: member="dwc_otg_hcd.c::dwc_otg_hcd_is_b_host" ref="ca25b33b440a4ef112ee459c26c14adc" args="(dwc_otg_hcd_t *hcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t dwc_otg_hcd_is_b_host           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Returns 1 if currently core is acting as B host, and 0 otherwise. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l02686">2686</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="264fc9d293c76e42dded9dee2cf44283"></a><!-- doxytag: member="dwc_otg_hcd.c::dwc_otg_hcd_urb_alloc" ref="264fc9d293c76e42dded9dee2cf44283" args="(dwc_otg_hcd_t *hcd, int iso_desc_count, int atomic_alloc)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a>* dwc_otg_hcd_urb_alloc           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>iso_desc_count</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>atomic_alloc</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Allocates memory for <a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb</a> structure. 
+<p>
+Allocated memory should be freed by call dwc_free function.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>iso_desc_count</em>&nbsp;</td><td>Count of ISOC descriptors </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>atomic_alloc</em>&nbsp;</td><td>Specefies whether to perform atomic allocation. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l02698">2698</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="4aca8781f512198149388799a8ae9aba"></a><!-- doxytag: member="dwc_otg_hcd.c::dwc_otg_hcd_urb_set_pipeinfo" ref="4aca8781f512198149388799a8ae9aba" args="(dwc_otg_hcd_urb_t *dwc_otg_urb, uint8_t dev_addr, uint8_t ep_num, uint8_t ep_type, uint8_t ep_dir, uint16_t mps)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_hcd_urb_set_pipeinfo           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd_urb</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t&nbsp;</td>
+          <td class="paramname"> <em>devaddr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t&nbsp;</td>
+          <td class="paramname"> <em>ep_num</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t&nbsp;</td>
+          <td class="paramname"> <em>ep_type</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t&nbsp;</td>
+          <td class="paramname"> <em>ep_dir</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint16_t&nbsp;</td>
+          <td class="paramname"> <em>mps</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Set pipe information in URB. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd_urb</em>&nbsp;</td><td>DWC_OTG URB </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>devaddr</em>&nbsp;</td><td>Device Address </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep_num</em>&nbsp;</td><td>Endpoint Number </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep_type</em>&nbsp;</td><td>Endpoint Type </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep_dir</em>&nbsp;</td><td>Endpoint Direction </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>mps</em>&nbsp;</td><td>Max Packet Size </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l02717">2717</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="d141b0ed3f2eac3f8aab2d8cefe34345"></a><!-- doxytag: member="dwc_otg_hcd.c::dwc_otg_hcd_urb_set_params" ref="d141b0ed3f2eac3f8aab2d8cefe34345" args="(dwc_otg_hcd_urb_t *dwc_otg_urb, void *urb_handle, void *buf, dwc_dma_t dma, uint32_t buflen, void *setup_packet, dwc_dma_t setup_dma, uint32_t flags, uint16_t interval)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_hcd_urb_set_params           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>urb</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>urb_handle</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>buf</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">dwc_dma_t&nbsp;</td>
+          <td class="paramname"> <em>dma</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint32_t&nbsp;</td>
+          <td class="paramname"> <em>buflen</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>sp</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">dwc_dma_t&nbsp;</td>
+          <td class="paramname"> <em>sp_dma</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint32_t&nbsp;</td>
+          <td class="paramname"> <em>flags</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint16_t&nbsp;</td>
+          <td class="paramname"> <em>interval</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Sets <a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb</a> parameters. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>urb</em>&nbsp;</td><td>DWC_OTG URB allocated by dwc_otg_hcd_urb_alloc function. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>urb_handle</em>&nbsp;</td><td>Unique handle for request, this will be passed back to function driver in completion callback. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>buf</em>&nbsp;</td><td>The buffer for the data </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>dma</em>&nbsp;</td><td>The DMA buffer for the data </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>buflen</em>&nbsp;</td><td>Transfer length </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>sp</em>&nbsp;</td><td>Buffer for setup data </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>sp_dma</em>&nbsp;</td><td>DMA address of setup data buffer </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>flags</em>&nbsp;</td><td>Transfer flags </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>interval</em>&nbsp;</td><td>Polling interval for interrupt or isochronous transfers. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l02730">2730</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="81b7aad80889affb1e63cf1307b88fb6"></a><!-- doxytag: member="dwc_otg_hcd.c::dwc_otg_hcd_urb_get_status" ref="81b7aad80889affb1e63cf1307b88fb6" args="(dwc_otg_hcd_urb_t *dwc_otg_urb)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t dwc_otg_hcd_urb_get_status           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>dwc_otg_urb</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Gets status from <a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb</a>. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>dwc_otg_urb</em>&nbsp;</td><td>DWC_OTG URB </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l02747">2747</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="3260f5db4ea20074da16b292eb1a686b"></a><!-- doxytag: member="dwc_otg_hcd.c::dwc_otg_hcd_urb_get_actual_length" ref="3260f5db4ea20074da16b292eb1a686b" args="(dwc_otg_hcd_urb_t *dwc_otg_urb)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t dwc_otg_hcd_urb_get_actual_length           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>dwc_otg_urb</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Gets actual length from <a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb</a>. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>dwc_otg_urb</em>&nbsp;</td><td>DWC_OTG URB </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l02752">2752</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="816cc30c3129fc8911a458355d977129"></a><!-- doxytag: member="dwc_otg_hcd.c::dwc_otg_hcd_urb_get_error_count" ref="816cc30c3129fc8911a458355d977129" args="(dwc_otg_hcd_urb_t *dwc_otg_urb)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t dwc_otg_hcd_urb_get_error_count           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>dwc_otg_urb</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Gets error count from <a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb</a>. 
+<p>
+Only for ISOC URBs<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>dwc_otg_urb</em>&nbsp;</td><td>DWC_OTG URB </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l02757">2757</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="8617e93eba1bfd6466a9af1e6d2f731b"></a><!-- doxytag: member="dwc_otg_hcd.c::dwc_otg_hcd_urb_set_iso_desc_params" ref="8617e93eba1bfd6466a9af1e6d2f731b" args="(dwc_otg_hcd_urb_t *dwc_otg_urb, int desc_num, uint32_t offset, uint32_t length)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_hcd_urb_set_iso_desc_params           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>dwc_otg_urb</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>desc_num</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint32_t&nbsp;</td>
+          <td class="paramname"> <em>offset</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint32_t&nbsp;</td>
+          <td class="paramname"> <em>length</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Set ISOC descriptor offset and length. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>dwc_otg_urb</em>&nbsp;</td><td>DWC_OTG URB </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>desc_num</em>&nbsp;</td><td>ISOC descriptor number </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>offset</em>&nbsp;</td><td>Offset from beginig of buffer. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>length</em>&nbsp;</td><td>Transaction length </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l02762">2762</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="fde27182e452709e10c1100ea57aa46b"></a><!-- doxytag: member="dwc_otg_hcd.c::dwc_otg_hcd_urb_get_iso_desc_status" ref="fde27182e452709e10c1100ea57aa46b" args="(dwc_otg_hcd_urb_t *dwc_otg_urb, int desc_num)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t dwc_otg_hcd_urb_get_iso_desc_status           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>dwc_otg_urb</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>desc_num</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Get status of ISOC descriptor, specified by desc_num. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>dwc_otg_urb</em>&nbsp;</td><td>DWC_OTG URB </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>desc_num</em>&nbsp;</td><td>ISOC descriptor number </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l02770">2770</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="c6d28fc3e6aedb29d46a793423c4de0a"></a><!-- doxytag: member="dwc_otg_hcd.c::dwc_otg_hcd_urb_get_iso_desc_actual_length" ref="c6d28fc3e6aedb29d46a793423c4de0a" args="(dwc_otg_hcd_urb_t *dwc_otg_urb, int desc_num)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>dwc_otg_urb</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>desc_num</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Get actual length of ISOC descriptor, specified by desc_num. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>dwc_otg_urb</em>&nbsp;</td><td>DWC_OTG URB </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>desc_num</em>&nbsp;</td><td>ISOC descriptor number </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l02776">2776</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="5deb69c332ba937b959c9dccadd87568"></a><!-- doxytag: member="dwc_otg_hcd.c::dwc_otg_hcd_is_bandwidth_allocated" ref="5deb69c332ba937b959c9dccadd87568" args="(dwc_otg_hcd_t *hcd, void *ep_handle)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_hcd_is_bandwidth_allocated           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>ep_handle</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Call this function to check if bandwidth was allocated for specified endpoint. 
+<p>
+Only for ISOC and INTERRUPT endpoints.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep_handle</em>&nbsp;</td><td>Endpoint handle </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l02782">2782</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="ad28eed057375c7f31663dc777edefd7"></a><!-- doxytag: member="dwc_otg_hcd.c::dwc_otg_hcd_is_bandwidth_freed" ref="ad28eed057375c7f31663dc777edefd7" args="(dwc_otg_hcd_t *hcd, void *ep_handle)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_hcd_is_bandwidth_freed           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>ep_handle</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Call this function to check if bandwidth was freed for specified endpoint. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep_handle</em>&nbsp;</td><td>Endpoint handle </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l02795">2795</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="bd160be911ccc8f90141dae9c40276eb"></a><!-- doxytag: member="dwc_otg_hcd.c::dwc_otg_hcd_get_ep_bandwidth" ref="bd160be911ccc8f90141dae9c40276eb" args="(dwc_otg_hcd_t *hcd, void *ep_handle)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint8_t dwc_otg_hcd_get_ep_bandwidth           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>ep_handle</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Returns bandwidth allocated for specified endpoint in microseconds. 
+<p>
+Only for ISOC and INTERRUPT endpoints.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep_handle</em>&nbsp;</td><td>Endpoint handle </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l02808">2808</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="464f920221173fe04c756a9d6657f321"></a><!-- doxytag: member="dwc_otg_hcd.c::dwc_otg_hcd_dump_state" ref="464f920221173fe04c756a9d6657f321" args="(dwc_otg_hcd_t *hcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_hcd_dump_state           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Dumps hcd state. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l02815">2815</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="b2c46e92cdc57b1783f445ed60cc3f38"></a><!-- doxytag: member="dwc_otg_hcd.c::dwc_otg_hcd_dump_frrem" ref="b2c46e92cdc57b1783f445ed60cc3f38" args="(dwc_otg_hcd_t *hcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_hcd_dump_frrem           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Dump the average frame remaining at SOF. 
+<p>
+This can be used to determine average interrupt latency. Frame remaining is also shown for start transfer and two additional sample points. Currently this function is not implemented.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l02991">2991</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<hr><h2>Variable Documentation</h2>
+<a class="anchor" name="106ff6cbb1499325ea75f2d97abb8e6a"></a><!-- doxytag: member="dwc_otg_hcd.c::hcd_cil_callbacks" ref="106ff6cbb1499325ea75f2d97abb8e6a" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="structdwc__otg__cil__callbacks.html">dwc_otg_cil_callbacks_t</a> <a class="el" href="dwc__otg__hcd_8c.html#106ff6cbb1499325ea75f2d97abb8e6a">hcd_cil_callbacks</a><code> [static]</code>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Initial value:</b><div class="fragment"><pre class="fragment"> {
+        .start = <a class="code" href="dwc__otg__hcd_8c.html#1aaeb9f41b201877f86a17d617b828d2">dwc_otg_hcd_start_cb</a>,
+        .stop = <a class="code" href="dwc__otg__hcd_8c.html#44e479b1c67b62a1887f93afd2106e4a">dwc_otg_hcd_stop_cb</a>,
+        .disconnect = <a class="code" href="dwc__otg__hcd_8c.html#2af30c3c78408325b26e3431b2442055">dwc_otg_hcd_disconnect_cb</a>,
+        .session_start = <a class="code" href="dwc__otg__hcd_8c.html#a0deab93f6ca3bcfcab0085b2bf86113">dwc_otg_hcd_session_start_cb</a>,
+        .resume_wakeup = <a class="code" href="dwc__otg__hcd_8c.html#fb35aff10c8837095302575957145f13">dwc_otg_hcd_rem_wakeup_cb</a>,
+
+
+
+        .p = 0,
+}
+</pre></div>HCD Callback structure for handling mode switching. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l00590">590</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd_8h-source.html b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd_8h-source.html
new file mode 100644
index 000000000000..2012c64ce994
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd_8h-source.html
@@ -0,0 +1,517 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd.h Source File</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<h1>dwc_otg_hcd.h</h1><a href="dwc__otg__hcd_8h.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">/* ==========================================================================</span>
+<a name="l00002"></a>00002 <span class="comment"> * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.h $</span>
+<a name="l00003"></a>00003 <span class="comment"> * $Revision: #52 $</span>
+<a name="l00004"></a>00004 <span class="comment"> * $Date: 2009/04/21 $</span>
+<a name="l00005"></a>00005 <span class="comment"> * $Change: 1237472 $</span>
+<a name="l00006"></a>00006 <span class="comment"> *</span>
+<a name="l00007"></a>00007 <span class="comment"> * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,</span>
+<a name="l00008"></a>00008 <span class="comment"> * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless</span>
+<a name="l00009"></a>00009 <span class="comment"> * otherwise expressly agreed to in writing between Synopsys and you.</span>
+<a name="l00010"></a>00010 <span class="comment"> *</span>
+<a name="l00011"></a>00011 <span class="comment"> * The Software IS NOT an item of Licensed Software or Licensed Product under</span>
+<a name="l00012"></a>00012 <span class="comment"> * any End User Software License Agreement or Agreement for Licensed Product</span>
+<a name="l00013"></a>00013 <span class="comment"> * with Synopsys or any supplement thereto. You are permitted to use and</span>
+<a name="l00014"></a>00014 <span class="comment"> * redistribute this Software in source and binary forms, with or without</span>
+<a name="l00015"></a>00015 <span class="comment"> * modification, provided that redistributions of source code must retain this</span>
+<a name="l00016"></a>00016 <span class="comment"> * notice. You may not view, use, disclose, copy or distribute this file or</span>
+<a name="l00017"></a>00017 <span class="comment"> * any information contained herein except pursuant to this license grant from</span>
+<a name="l00018"></a>00018 <span class="comment"> * Synopsys. If you do not agree with this notice, including the disclaimer</span>
+<a name="l00019"></a>00019 <span class="comment"> * below, then you are not authorized to use the Software.</span>
+<a name="l00020"></a>00020 <span class="comment"> *</span>
+<a name="l00021"></a>00021 <span class="comment"> * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS</span>
+<a name="l00022"></a>00022 <span class="comment"> * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE</span>
+<a name="l00023"></a>00023 <span class="comment"> * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE</span>
+<a name="l00024"></a>00024 <span class="comment"> * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,</span>
+<a name="l00025"></a>00025 <span class="comment"> * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES</span>
+<a name="l00026"></a>00026 <span class="comment"> * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR</span>
+<a name="l00027"></a>00027 <span class="comment"> * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER</span>
+<a name="l00028"></a>00028 <span class="comment"> * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT</span>
+<a name="l00029"></a>00029 <span class="comment"> * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY</span>
+<a name="l00030"></a>00030 <span class="comment"> * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH</span>
+<a name="l00031"></a>00031 <span class="comment"> * DAMAGE.</span>
+<a name="l00032"></a>00032 <span class="comment"> * ========================================================================== */</span>
+<a name="l00033"></a>00033 <span class="preprocessor">#ifndef DWC_DEVICE_ONLY</span>
+<a name="l00034"></a>00034 <span class="preprocessor"></span><span class="preprocessor">#ifndef __DWC_HCD_H__</span>
+<a name="l00035"></a>00035 <span class="preprocessor"></span><span class="preprocessor">#define __DWC_HCD_H__</span>
+<a name="l00036"></a>00036 <span class="preprocessor"></span>
+<a name="l00037"></a>00037 <span class="preprocessor">#include &lt;usb.h&gt;</span>
+<a name="l00038"></a>00038 <span class="preprocessor">#include "<a class="code" href="dwc__otg__hcd__if_8h.html">dwc_otg_hcd_if.h</a>"</span>
+<a name="l00039"></a>00039 <span class="preprocessor">#include "<a class="code" href="dwc__otg__core__if_8h.html">dwc_otg_core_if.h</a>"</span>
+<a name="l00040"></a>00040 <span class="preprocessor">#include "dwc_list.h"</span>
+<a name="l00041"></a>00041 <span class="preprocessor">#include "<a class="code" href="dwc__otg__cil_8h.html">dwc_otg_cil.h</a>"</span>
+<a name="l00042"></a>00042 
+<a name="l00055"></a><a class="code" href="structdwc__otg__hcd__pipe__info.html">00055</a> <span class="keyword">struct </span><a class="code" href="structdwc__otg__hcd__pipe__info.html">dwc_otg_hcd_pipe_info</a> {
+<a name="l00056"></a><a class="code" href="structdwc__otg__hcd__pipe__info.html#3812ead0191c9b3bebf48fe8ea370d78">00056</a>         uint8_t <a class="code" href="structdwc__otg__hcd__pipe__info.html#3812ead0191c9b3bebf48fe8ea370d78">dev_addr</a>;
+<a name="l00057"></a><a class="code" href="structdwc__otg__hcd__pipe__info.html#57b54466daa38c3a77f48e94c5e30f0d">00057</a>         uint8_t <a class="code" href="structdwc__otg__hcd__pipe__info.html#57b54466daa38c3a77f48e94c5e30f0d">ep_num</a>;
+<a name="l00058"></a><a class="code" href="structdwc__otg__hcd__pipe__info.html#0278c3069bc464cc4dbed8f6647f5856">00058</a>         uint8_t <a class="code" href="structdwc__otg__hcd__pipe__info.html#0278c3069bc464cc4dbed8f6647f5856">pipe_type</a>;
+<a name="l00059"></a><a class="code" href="structdwc__otg__hcd__pipe__info.html#8342fc4305ea957e2fa78f2bc9e707e4">00059</a>         uint8_t <a class="code" href="structdwc__otg__hcd__pipe__info.html#8342fc4305ea957e2fa78f2bc9e707e4">pipe_dir</a>;
+<a name="l00060"></a><a class="code" href="structdwc__otg__hcd__pipe__info.html#b1d585e71a4e15bc79fc5f6d87bada6a">00060</a>         uint16_t <a class="code" href="structdwc__otg__hcd__pipe__info.html#b1d585e71a4e15bc79fc5f6d87bada6a">mps</a>;
+<a name="l00061"></a>00061 };
+<a name="l00062"></a>00062 
+<a name="l00063"></a><a class="code" href="structdwc__otg__hcd__iso__packet__desc.html">00063</a> <span class="keyword">struct </span><a class="code" href="structdwc__otg__hcd__iso__packet__desc.html">dwc_otg_hcd_iso_packet_desc</a> {
+<a name="l00064"></a><a class="code" href="structdwc__otg__hcd__iso__packet__desc.html#246f3d147a22cd295c534253593dca4a">00064</a>         uint32_t <a class="code" href="structdwc__otg__hcd__iso__packet__desc.html#246f3d147a22cd295c534253593dca4a">offset</a>;
+<a name="l00065"></a><a class="code" href="structdwc__otg__hcd__iso__packet__desc.html#8392d21b820df0181f4e6dca91234543">00065</a>         uint32_t <a class="code" href="structdwc__otg__hcd__iso__packet__desc.html#8392d21b820df0181f4e6dca91234543">length</a>;
+<a name="l00066"></a><a class="code" href="structdwc__otg__hcd__iso__packet__desc.html#c00b967f4c613820b99efc0abda5178c">00066</a>         uint32_t <a class="code" href="structdwc__otg__hcd__iso__packet__desc.html#c00b967f4c613820b99efc0abda5178c">actual_length</a>;
+<a name="l00067"></a><a class="code" href="structdwc__otg__hcd__iso__packet__desc.html#d070772c24621c47b49ad21c6acadb94">00067</a>         uint32_t <a class="code" href="structdwc__otg__hcd__iso__packet__desc.html#d070772c24621c47b49ad21c6acadb94">status</a>;
+<a name="l00068"></a>00068 };
+<a name="l00069"></a>00069 
+<a name="l00070"></a>00070 <span class="keyword">struct </span><a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd</a>;
+<a name="l00071"></a>00071 
+<a name="l00072"></a><a class="code" href="structdwc__otg__hcd__urb.html">00072</a> <span class="keyword">struct </span><a class="code" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb</a> {
+<a name="l00073"></a><a class="code" href="structdwc__otg__hcd__urb.html#5ba0e393ef9768275db85c00e68be477">00073</a>         <span class="keywordtype">void</span> *<a class="code" href="structdwc__otg__hcd__urb.html#5ba0e393ef9768275db85c00e68be477">priv</a>;
+<a name="l00074"></a><a class="code" href="structdwc__otg__hcd__urb.html#68dc4d459bb70aed6083553653aadaad">00074</a>         <span class="keyword">struct </span><a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd</a> *<a class="code" href="structdwc__otg__hcd__urb.html#68dc4d459bb70aed6083553653aadaad">qtd</a>;
+<a name="l00075"></a><a class="code" href="structdwc__otg__hcd__urb.html#99ae35ffcd6147ddb93b361ab3bcfe95">00075</a>         <span class="keywordtype">void</span> *<a class="code" href="structdwc__otg__hcd__urb.html#99ae35ffcd6147ddb93b361ab3bcfe95">buf</a>;
+<a name="l00076"></a><a class="code" href="structdwc__otg__hcd__urb.html#4e177a55239e95ae2f6c8b6b913f67fc">00076</a>         dwc_dma_t <a class="code" href="structdwc__otg__hcd__urb.html#4e177a55239e95ae2f6c8b6b913f67fc">dma</a>;
+<a name="l00077"></a><a class="code" href="structdwc__otg__hcd__urb.html#254afd954f3e24bb92841384183a317c">00077</a>         <span class="keywordtype">void</span> *<a class="code" href="structdwc__otg__hcd__urb.html#254afd954f3e24bb92841384183a317c">setup_packet</a>;
+<a name="l00078"></a><a class="code" href="structdwc__otg__hcd__urb.html#497f61f9b3f6f77f6b844e31c047264d">00078</a>         dwc_dma_t <a class="code" href="structdwc__otg__hcd__urb.html#497f61f9b3f6f77f6b844e31c047264d">setup_dma</a>;
+<a name="l00079"></a><a class="code" href="structdwc__otg__hcd__urb.html#dca57de4fdecd894241ce24167206a45">00079</a>         uint32_t <a class="code" href="structdwc__otg__hcd__urb.html#dca57de4fdecd894241ce24167206a45">length</a>;
+<a name="l00080"></a><a class="code" href="structdwc__otg__hcd__urb.html#742c8a97d3867ab89148eae34e0c73a6">00080</a>         uint32_t <a class="code" href="structdwc__otg__hcd__urb.html#742c8a97d3867ab89148eae34e0c73a6">actual_length</a>;
+<a name="l00081"></a><a class="code" href="structdwc__otg__hcd__urb.html#101e4a6762b9911cdb85768890fa1210">00081</a>         uint32_t <a class="code" href="structdwc__otg__hcd__urb.html#101e4a6762b9911cdb85768890fa1210">status</a>;
+<a name="l00082"></a><a class="code" href="structdwc__otg__hcd__urb.html#58c7018042c94c436637ea80354e7e28">00082</a>         uint32_t <a class="code" href="structdwc__otg__hcd__urb.html#58c7018042c94c436637ea80354e7e28">error_count</a>;
+<a name="l00083"></a><a class="code" href="structdwc__otg__hcd__urb.html#570583697e8c1e4398969630bc2562f8">00083</a>         uint32_t <a class="code" href="structdwc__otg__hcd__urb.html#570583697e8c1e4398969630bc2562f8">packet_count</a>;
+<a name="l00084"></a><a class="code" href="structdwc__otg__hcd__urb.html#2f1d90765496d78d297b3e57ef4d781c">00084</a>         uint32_t <a class="code" href="structdwc__otg__hcd__urb.html#2f1d90765496d78d297b3e57ef4d781c">flags</a>;
+<a name="l00085"></a><a class="code" href="structdwc__otg__hcd__urb.html#49c5353377e2fb173f1b34ae7be7e257">00085</a>         uint16_t <a class="code" href="structdwc__otg__hcd__urb.html#49c5353377e2fb173f1b34ae7be7e257">interval</a>;
+<a name="l00086"></a><a class="code" href="structdwc__otg__hcd__urb.html#34ee3ac5931687b41dd726f00c558369">00086</a>         <span class="keyword">struct </span><a class="code" href="structdwc__otg__hcd__pipe__info.html">dwc_otg_hcd_pipe_info</a> <a class="code" href="structdwc__otg__hcd__urb.html#34ee3ac5931687b41dd726f00c558369">pipe_info</a>;
+<a name="l00087"></a><a class="code" href="structdwc__otg__hcd__urb.html#ed542f6a2d99dba2f6b71b0d8012ec8a">00087</a>         <span class="keyword">struct </span><a class="code" href="structdwc__otg__hcd__iso__packet__desc.html">dwc_otg_hcd_iso_packet_desc</a> <a class="code" href="structdwc__otg__hcd__urb.html#ed542f6a2d99dba2f6b71b0d8012ec8a">iso_descs</a>[0];
+<a name="l00088"></a>00088 };
+<a name="l00089"></a>00089 
+<a name="l00090"></a><a class="code" href="dwc__otg__hcd_8h.html#367b79057f321cfa65023f4026d6c2c9">00090</a> <span class="keyword">static</span> <span class="keyword">inline</span> uint8_t <a class="code" href="dwc__otg__hcd_8h.html#367b79057f321cfa65023f4026d6c2c9">dwc_otg_hcd_get_ep_num</a>(<span class="keyword">struct</span> <a class="code" href="structdwc__otg__hcd__pipe__info.html">dwc_otg_hcd_pipe_info</a> *pipe)
+<a name="l00091"></a>00091 {
+<a name="l00092"></a>00092         <span class="keywordflow">return</span> pipe-&gt;<a class="code" href="structdwc__otg__hcd__pipe__info.html#57b54466daa38c3a77f48e94c5e30f0d">ep_num</a>;
+<a name="l00093"></a>00093 }
+<a name="l00094"></a>00094 
+<a name="l00095"></a><a class="code" href="dwc__otg__hcd_8h.html#b97cea598797e69d011ffef89989a739">00095</a> <span class="keyword">static</span> <span class="keyword">inline</span> uint8_t <a class="code" href="dwc__otg__hcd_8h.html#b97cea598797e69d011ffef89989a739">dwc_otg_hcd_get_pipe_type</a>(<span class="keyword">struct</span> <a class="code" href="structdwc__otg__hcd__pipe__info.html">dwc_otg_hcd_pipe_info</a>
+<a name="l00096"></a>00096                                                 *pipe)
+<a name="l00097"></a>00097 {
+<a name="l00098"></a>00098         <span class="keywordflow">return</span> pipe-&gt;<a class="code" href="structdwc__otg__hcd__pipe__info.html#0278c3069bc464cc4dbed8f6647f5856">pipe_type</a>;
+<a name="l00099"></a>00099 }
+<a name="l00100"></a>00100 
+<a name="l00101"></a><a class="code" href="dwc__otg__hcd_8h.html#e47df3e0ac1c8ccc916e0c0895568c88">00101</a> <span class="keyword">static</span> <span class="keyword">inline</span> uint16_t <a class="code" href="dwc__otg__hcd_8h.html#e47df3e0ac1c8ccc916e0c0895568c88">dwc_otg_hcd_get_mps</a>(<span class="keyword">struct</span> <a class="code" href="structdwc__otg__hcd__pipe__info.html">dwc_otg_hcd_pipe_info</a> *pipe)
+<a name="l00102"></a>00102 {
+<a name="l00103"></a>00103         <span class="keywordflow">return</span> pipe-&gt;<a class="code" href="structdwc__otg__hcd__pipe__info.html#b1d585e71a4e15bc79fc5f6d87bada6a">mps</a>;
+<a name="l00104"></a>00104 }
+<a name="l00105"></a>00105 
+<a name="l00106"></a><a class="code" href="dwc__otg__hcd_8h.html#0de365358ba4472d56c1ac8074ba926b">00106</a> <span class="keyword">static</span> <span class="keyword">inline</span> uint8_t <a class="code" href="dwc__otg__hcd_8h.html#0de365358ba4472d56c1ac8074ba926b">dwc_otg_hcd_get_dev_addr</a>(<span class="keyword">struct</span> <a class="code" href="structdwc__otg__hcd__pipe__info.html">dwc_otg_hcd_pipe_info</a>
+<a name="l00107"></a>00107                                                *pipe)
+<a name="l00108"></a>00108 {
+<a name="l00109"></a>00109         <span class="keywordflow">return</span> pipe-&gt;<a class="code" href="structdwc__otg__hcd__pipe__info.html#3812ead0191c9b3bebf48fe8ea370d78">dev_addr</a>;
+<a name="l00110"></a>00110 }
+<a name="l00111"></a>00111 
+<a name="l00112"></a><a class="code" href="dwc__otg__hcd_8h.html#3ae411bce062f6929961046492c96330">00112</a> <span class="keyword">static</span> <span class="keyword">inline</span> uint8_t <a class="code" href="dwc__otg__hcd_8h.html#3ae411bce062f6929961046492c96330">dwc_otg_hcd_is_pipe_isoc</a>(<span class="keyword">struct</span> <a class="code" href="structdwc__otg__hcd__pipe__info.html">dwc_otg_hcd_pipe_info</a>
+<a name="l00113"></a>00113                                                *pipe)
+<a name="l00114"></a>00114 {
+<a name="l00115"></a>00115         <span class="keywordflow">return</span> (pipe-&gt;<a class="code" href="structdwc__otg__hcd__pipe__info.html#0278c3069bc464cc4dbed8f6647f5856">pipe_type</a> == UE_ISOCHRONOUS);
+<a name="l00116"></a>00116 }
+<a name="l00117"></a>00117 
+<a name="l00118"></a><a class="code" href="dwc__otg__hcd_8h.html#9bd15e815decf74a7033c11e57d98bde">00118</a> <span class="keyword">static</span> <span class="keyword">inline</span> uint8_t <a class="code" href="dwc__otg__hcd_8h.html#9bd15e815decf74a7033c11e57d98bde">dwc_otg_hcd_is_pipe_int</a>(<span class="keyword">struct</span> <a class="code" href="structdwc__otg__hcd__pipe__info.html">dwc_otg_hcd_pipe_info</a>
+<a name="l00119"></a>00119                                               *pipe)
+<a name="l00120"></a>00120 {
+<a name="l00121"></a>00121         <span class="keywordflow">return</span> (pipe-&gt;<a class="code" href="structdwc__otg__hcd__pipe__info.html#0278c3069bc464cc4dbed8f6647f5856">pipe_type</a> == UE_INTERRUPT);
+<a name="l00122"></a>00122 }
+<a name="l00123"></a>00123 
+<a name="l00124"></a><a class="code" href="dwc__otg__hcd_8h.html#7e0a4084d0444c4375dd60250b860ad8">00124</a> <span class="keyword">static</span> <span class="keyword">inline</span> uint8_t <a class="code" href="dwc__otg__hcd_8h.html#7e0a4084d0444c4375dd60250b860ad8">dwc_otg_hcd_is_pipe_bulk</a>(<span class="keyword">struct</span> <a class="code" href="structdwc__otg__hcd__pipe__info.html">dwc_otg_hcd_pipe_info</a>
+<a name="l00125"></a>00125                                                *pipe)
+<a name="l00126"></a>00126 {
+<a name="l00127"></a>00127         <span class="keywordflow">return</span> (pipe-&gt;<a class="code" href="structdwc__otg__hcd__pipe__info.html#0278c3069bc464cc4dbed8f6647f5856">pipe_type</a> == UE_BULK);
+<a name="l00128"></a>00128 }
+<a name="l00129"></a>00129 
+<a name="l00130"></a><a class="code" href="dwc__otg__hcd_8h.html#d40e602eb8b015dc3908a23d2f8fbb7a">00130</a> <span class="keyword">static</span> <span class="keyword">inline</span> uint8_t <a class="code" href="dwc__otg__hcd_8h.html#d40e602eb8b015dc3908a23d2f8fbb7a">dwc_otg_hcd_is_pipe_control</a>(<span class="keyword">struct</span> <a class="code" href="structdwc__otg__hcd__pipe__info.html">dwc_otg_hcd_pipe_info</a>
+<a name="l00131"></a>00131                                                   *pipe)
+<a name="l00132"></a>00132 {
+<a name="l00133"></a>00133         <span class="keywordflow">return</span> (pipe-&gt;<a class="code" href="structdwc__otg__hcd__pipe__info.html#0278c3069bc464cc4dbed8f6647f5856">pipe_type</a> == UE_CONTROL);
+<a name="l00134"></a>00134 }
+<a name="l00135"></a>00135 
+<a name="l00136"></a><a class="code" href="dwc__otg__hcd_8h.html#68de5629a8b45d9bec58f680fa4c820c">00136</a> <span class="keyword">static</span> <span class="keyword">inline</span> uint8_t <a class="code" href="dwc__otg__hcd_8h.html#68de5629a8b45d9bec58f680fa4c820c">dwc_otg_hcd_is_pipe_in</a>(<span class="keyword">struct</span> <a class="code" href="structdwc__otg__hcd__pipe__info.html">dwc_otg_hcd_pipe_info</a> *pipe)
+<a name="l00137"></a>00137 {
+<a name="l00138"></a>00138         <span class="keywordflow">return</span> (pipe-&gt;<a class="code" href="structdwc__otg__hcd__pipe__info.html#8342fc4305ea957e2fa78f2bc9e707e4">pipe_dir</a> == UE_DIR_IN);
+<a name="l00139"></a>00139 }
+<a name="l00140"></a>00140 
+<a name="l00141"></a><a class="code" href="dwc__otg__hcd_8h.html#cf3e5e59a22ef6bd497e05710e39cad0">00141</a> <span class="keyword">static</span> <span class="keyword">inline</span> uint8_t <a class="code" href="dwc__otg__hcd_8h.html#cf3e5e59a22ef6bd497e05710e39cad0">dwc_otg_hcd_is_pipe_out</a>(<span class="keyword">struct</span> <a class="code" href="structdwc__otg__hcd__pipe__info.html">dwc_otg_hcd_pipe_info</a>
+<a name="l00142"></a>00142                                               *pipe)
+<a name="l00143"></a>00143 {
+<a name="l00144"></a>00144         <span class="keywordflow">return</span> (!<a class="code" href="dwc__otg__hcd_8h.html#68de5629a8b45d9bec58f680fa4c820c">dwc_otg_hcd_is_pipe_in</a>(pipe));
+<a name="l00145"></a>00145 }
+<a name="l00146"></a>00146 
+<a name="l00147"></a><a class="code" href="dwc__otg__hcd_8h.html#4806306754f0414ad9cee3067cdda8c9">00147</a> <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd_8h.html#4806306754f0414ad9cee3067cdda8c9">dwc_otg_hcd_fill_pipe</a>(<span class="keyword">struct</span> <a class="code" href="structdwc__otg__hcd__pipe__info.html">dwc_otg_hcd_pipe_info</a> *pipe,
+<a name="l00148"></a>00148                                          uint8_t devaddr, uint8_t ep_num,
+<a name="l00149"></a>00149                                          uint8_t pipe_type, uint8_t pipe_dir,
+<a name="l00150"></a>00150                                          uint16_t mps)
+<a name="l00151"></a>00151 {
+<a name="l00152"></a>00152         pipe-&gt;<a class="code" href="structdwc__otg__hcd__pipe__info.html#3812ead0191c9b3bebf48fe8ea370d78">dev_addr</a> = devaddr;
+<a name="l00153"></a>00153         pipe-&gt;<a class="code" href="structdwc__otg__hcd__pipe__info.html#57b54466daa38c3a77f48e94c5e30f0d">ep_num</a> = ep_num;
+<a name="l00154"></a>00154         pipe-&gt;<a class="code" href="structdwc__otg__hcd__pipe__info.html#0278c3069bc464cc4dbed8f6647f5856">pipe_type</a> = pipe_type;
+<a name="l00155"></a>00155         pipe-&gt;<a class="code" href="structdwc__otg__hcd__pipe__info.html#8342fc4305ea957e2fa78f2bc9e707e4">pipe_dir</a> = pipe_dir;
+<a name="l00156"></a>00156         pipe-&gt;<a class="code" href="structdwc__otg__hcd__pipe__info.html#b1d585e71a4e15bc79fc5f6d87bada6a">mps</a> = mps;
+<a name="l00157"></a>00157 }
+<a name="l00158"></a>00158 
+<a name="l00162"></a><a class="code" href="dwc__otg__hcd_8h.html#4ec934997af9e24c8eede108d399c140">00162</a> <span class="keyword">typedef</span> <span class="keyword">enum</span> <a class="code" href="dwc__otg__hcd_8h.html#4ec934997af9e24c8eede108d399c140">dwc_otg_control_phase</a> {
+<a name="l00163"></a>00163         DWC_OTG_CONTROL_SETUP,
+<a name="l00164"></a>00164         DWC_OTG_CONTROL_DATA,
+<a name="l00165"></a>00165         DWC_OTG_CONTROL_STATUS
+<a name="l00166"></a>00166 } <a class="code" href="dwc__otg__hcd_8h.html#be7c5653ee5e9d33855d2513f31b56a5">dwc_otg_control_phase_e</a>;
+<a name="l00167"></a>00167 
+<a name="l00169"></a><a class="code" href="dwc__otg__hcd_8h.html#0ab043da15526ddcd3f3698505d52d83">00169</a> <span class="keyword">typedef</span> <span class="keyword">enum</span> <a class="code" href="dwc__otg__hcd_8h.html#0ab043da15526ddcd3f3698505d52d83">dwc_otg_transaction_type</a> {
+<a name="l00170"></a>00170         DWC_OTG_TRANSACTION_NONE,
+<a name="l00171"></a>00171         DWC_OTG_TRANSACTION_PERIODIC,
+<a name="l00172"></a>00172         DWC_OTG_TRANSACTION_NON_PERIODIC,
+<a name="l00173"></a>00173         DWC_OTG_TRANSACTION_ALL
+<a name="l00174"></a>00174 } <a class="code" href="dwc__otg__hcd_8h.html#92c49783eebc5bcffa8b8a51c2127be9">dwc_otg_transaction_type_e</a>;
+<a name="l00175"></a>00175 
+<a name="l00176"></a>00176 <span class="keyword">struct </span><a class="code" href="structdwc__otg__qh.html">dwc_otg_qh</a>;
+<a name="l00177"></a>00177 
+<a name="l00191"></a><a class="code" href="structdwc__otg__qtd.html">00191</a> <span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd</a> {
+<a name="l00199"></a><a class="code" href="structdwc__otg__qtd.html#e912f256e01165b573c26262247a5eff">00199</a>         uint8_t <a class="code" href="structdwc__otg__qtd.html#e912f256e01165b573c26262247a5eff">data_toggle</a>;
+<a name="l00200"></a>00200 
+<a name="l00202"></a><a class="code" href="structdwc__otg__qtd.html#5189ec9c992974d20477481eaf96d0bb">00202</a>         <a class="code" href="dwc__otg__hcd_8h.html#be7c5653ee5e9d33855d2513f31b56a5">dwc_otg_control_phase_e</a> <a class="code" href="structdwc__otg__qtd.html#5189ec9c992974d20477481eaf96d0bb">control_phase</a>;
+<a name="l00203"></a>00203 
+<a name="l00206"></a><a class="code" href="structdwc__otg__qtd.html#6355e968a4d36edce3e22c89ac7b5001">00206</a>         uint8_t <a class="code" href="structdwc__otg__qtd.html#6355e968a4d36edce3e22c89ac7b5001">complete_split</a>;
+<a name="l00207"></a>00207 
+<a name="l00209"></a><a class="code" href="structdwc__otg__qtd.html#badffe465e850133c62c8f7e539f3fca">00209</a>         uint32_t <a class="code" href="structdwc__otg__qtd.html#badffe465e850133c62c8f7e539f3fca">ssplit_out_xfer_count</a>;
+<a name="l00210"></a>00210 
+<a name="l00215"></a><a class="code" href="structdwc__otg__qtd.html#18eeb9c647049aec468bf9a7861c873f">00215</a>         uint8_t <a class="code" href="structdwc__otg__qtd.html#18eeb9c647049aec468bf9a7861c873f">error_count</a>;
+<a name="l00216"></a>00216 
+<a name="l00224"></a><a class="code" href="structdwc__otg__qtd.html#c67d5f885976d0698f20d113d32b4b30">00224</a>         uint16_t <a class="code" href="structdwc__otg__qtd.html#c67d5f885976d0698f20d113d32b4b30">isoc_frame_index</a>;
+<a name="l00225"></a>00225 
+<a name="l00227"></a><a class="code" href="structdwc__otg__qtd.html#ab224d64d72f2ef4f10e722ebcfa29a6">00227</a>         uint8_t <a class="code" href="structdwc__otg__qtd.html#ab224d64d72f2ef4f10e722ebcfa29a6">isoc_split_pos</a>;
+<a name="l00228"></a>00228 
+<a name="l00230"></a><a class="code" href="structdwc__otg__qtd.html#839371940a7e34365e2272f3214b7e34">00230</a>         uint16_t <a class="code" href="structdwc__otg__qtd.html#839371940a7e34365e2272f3214b7e34">isoc_split_offset</a>;
+<a name="l00231"></a>00231 
+<a name="l00233"></a><a class="code" href="structdwc__otg__qtd.html#7e7767808e8eb9d71de0db00f57553f9">00233</a>         <span class="keyword">struct </span><a class="code" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb</a> *<a class="code" href="structdwc__otg__qtd.html#7e7767808e8eb9d71de0db00f57553f9">urb</a>;
+<a name="l00234"></a>00234 
+<a name="l00235"></a><a class="code" href="structdwc__otg__qtd.html#f80ddcfb6edbe83a3991dd67c93a47e4">00235</a>         <span class="keyword">struct </span><a class="code" href="structdwc__otg__qh.html">dwc_otg_qh</a> *<a class="code" href="structdwc__otg__qtd.html#f80ddcfb6edbe83a3991dd67c93a47e4">qh</a>;
+<a name="l00236"></a>00236 
+<a name="l00238"></a>00238          <a class="code" href="structdwc__otg__qtd.html#aac18e92835ac0678a83d023660f1560">DWC_CIRCLEQ_ENTRY</a>(<a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd</a>) qtd_list_entry;
+<a name="l00239"></a>00239 
+<a name="l00241"></a><a class="code" href="structdwc__otg__qtd.html#c1d73f1d48eeabbdc198ad28c0882bc1">00241</a>         uint8_t <a class="code" href="structdwc__otg__qtd.html#c1d73f1d48eeabbdc198ad28c0882bc1">in_process</a>;
+<a name="l00242"></a>00242 
+<a name="l00244"></a><a class="code" href="structdwc__otg__qtd.html#ef3021e617cf1f448bd23b1f7ab3859b">00244</a>         uint8_t <a class="code" href="structdwc__otg__qtd.html#ef3021e617cf1f448bd23b1f7ab3859b">n_desc</a>;
+<a name="l00245"></a>00245         
+<a name="l00250"></a><a class="code" href="structdwc__otg__qtd.html#c296d49e3615e35c06b83e7febc31943">00250</a>         uint16_t <a class="code" href="structdwc__otg__qtd.html#c296d49e3615e35c06b83e7febc31943">isoc_frame_index_last</a>;
+<a name="l00251"></a>00251         
+<a name="l00252"></a>00252 } <a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a>;
+<a name="l00253"></a>00253 
+<a name="l00254"></a>00254 DWC_CIRCLEQ_HEAD(dwc_otg_qtd_list, <a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd</a>);
+<a name="l00255"></a>00255 
+<a name="l00261"></a><a class="code" href="structdwc__otg__qh.html">00261</a> typedef struct <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh</a> {
+<a name="l00270"></a><a class="code" href="structdwc__otg__qh.html#98b78ffd8dbc01be44b302e873e73a82">00270</a>         uint8_t <a class="code" href="structdwc__otg__qh.html#98b78ffd8dbc01be44b302e873e73a82">ep_type</a>;
+<a name="l00271"></a><a class="code" href="structdwc__otg__qh.html#2dc622878a6617e5c803061804d5cf9f">00271</a>         uint8_t <a class="code" href="structdwc__otg__qh.html#2dc622878a6617e5c803061804d5cf9f">ep_is_in</a>;
+<a name="l00272"></a>00272 
+<a name="l00274"></a><a class="code" href="structdwc__otg__qh.html#5975c2bede1ca0c6cfe9a66fe0a52567">00274</a>         uint16_t <a class="code" href="structdwc__otg__qh.html#5975c2bede1ca0c6cfe9a66fe0a52567">maxp</a>;
+<a name="l00275"></a>00275 
+<a name="l00283"></a><a class="code" href="structdwc__otg__qh.html#42459dd91e199807783000b6dc358a7d">00283</a>         uint8_t <a class="code" href="structdwc__otg__qh.html#42459dd91e199807783000b6dc358a7d">dev_speed</a>;
+<a name="l00284"></a>00284 
+<a name="l00292"></a><a class="code" href="structdwc__otg__qh.html#b0e001bfd76f5781926795ac47ef2c25">00292</a>         uint8_t <a class="code" href="structdwc__otg__qtd.html#e912f256e01165b573c26262247a5eff">data_toggle</a>;
+<a name="l00293"></a>00293 
+<a name="l00295"></a><a class="code" href="structdwc__otg__qh.html#2c115474978a808c797c8975d72e419d">00295</a>         uint8_t <a class="code" href="structdwc__otg__qh.html#2c115474978a808c797c8975d72e419d">ping_state</a>;
+<a name="l00296"></a>00296 
+<a name="l00300"></a><a class="code" href="structdwc__otg__qh.html#9567d266da8e796d3467fb16ae867f8e">00300</a>         <span class="keyword">struct </span>dwc_otg_qtd_list qtd_list;
+<a name="l00301"></a>00301 
+<a name="l00303"></a><a class="code" href="structdwc__otg__qh.html#bbdb7d30b60b6c326301f33b35088bb4">00303</a>         <span class="keyword">struct </span><a class="code" href="structdwc__hc.html">dwc_hc</a> *channel;
+<a name="l00304"></a>00304 
+<a name="l00306"></a><a class="code" href="structdwc__otg__qh.html#8708dd009988ce20b8a8d52a4a96c5a3">00306</a>         uint8_t <a class="code" href="structdwc__hc.html#4365ef67d517a621a626ac5392545c6d">do_split</a>;
+<a name="l00307"></a>00307 
+<a name="l00312"></a><a class="code" href="structdwc__otg__qh.html#401de6aadcfc2f99773f44c6731c4646">00312</a>         uint16_t usecs;
+<a name="l00313"></a>00313 
+<a name="l00315"></a><a class="code" href="structdwc__otg__qh.html#cdbce86d457f0ea08e2efedc47c9b315">00315</a>         uint16_t interval;
+<a name="l00316"></a>00316 
+<a name="l00321"></a><a class="code" href="structdwc__otg__qh.html#977a8032f08e45a9e9bdcd558a6965d3">00321</a>         uint16_t sched_frame;
+<a name="l00322"></a>00322 
+<a name="l00324"></a><a class="code" href="structdwc__otg__qh.html#a92b9ff45f0eca459b41ca20e4d8e99c">00324</a>         uint16_t start_split_frame;
+<a name="l00325"></a>00325 
+<a name="l00332"></a><a class="code" href="structdwc__otg__qh.html#aac9f90a6afd9056dce79d013dd2168b">00332</a>         uint8_t *dw_align_buf;
+<a name="l00333"></a><a class="code" href="structdwc__otg__qh.html#b0b008f9d25f5e3b6e285d2830cfdca1">00333</a>         dwc_dma_t dw_align_buf_dma;
+<a name="l00334"></a>00334         
+<a name="l00336"></a><a class="code" href="structdwc__otg__qh.html#3e1cb9863dc72139e1832c04244c25ff">00336</a>         dwc_list_link_t qh_list_entry;
+<a name="l00337"></a>00337         
+<a name="l00342"></a><a class="code" href="structdwc__otg__qh.html#0e5f35688e54ba97054a1a7576e81150">00342</a>         <a class="code" href="structdwc__otg__host__dma__desc.html">dwc_otg_host_dma_desc_t</a> *desc_list;
+<a name="l00343"></a>00343         
+<a name="l00345"></a><a class="code" href="structdwc__otg__qh.html#c31412bb35362e77c697352fd4c3eeaf">00345</a>         dwc_dma_t desc_list_dma;
+<a name="l00346"></a>00346         
+<a name="l00352"></a><a class="code" href="structdwc__otg__qh.html#6b625d870c7854ccaff5c28fad87482a">00352</a>         uint32_t *n_bytes;
+<a name="l00353"></a>00353         
+<a name="l00355"></a><a class="code" href="structdwc__otg__qh.html#6da0f75ffa49c8ffadde42e9618ed8c8">00355</a>         uint16_t <a class="code" href="structdwc__hc.html#9a3a483b9c4e45d1ec5f475beb6a10a3">ntd</a>;
+<a name="l00356"></a>00356         
+<a name="l00358"></a><a class="code" href="structdwc__otg__qh.html#3b20e91c00b1de8d42612a8b1250b403">00358</a>         uint8_t td_first;
+<a name="l00360"></a><a class="code" href="structdwc__otg__qh.html#9bd6dc808af3f1cab76ae7819af479f9">00360</a>         uint8_t td_last;
+<a name="l00361"></a>00361         
+<a name="l00364"></a>00364 } <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a>;
+<a name="l00365"></a>00365 
+<a name="l00366"></a>00366 DWC_CIRCLEQ_HEAD(hc_list, <a class="code" href="structdwc__hc.html">dwc_hc</a>);
+<a name="l00367"></a>00367 
+<a name="l00372"></a><a class="code" href="structdwc__otg__hcd.html">00372</a> <span class="keyword">struct </span><a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a> {
+<a name="l00374"></a><a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">00374</a>         <a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if;
+<a name="l00375"></a>00375 
+<a name="l00377"></a><a class="code" href="structdwc__otg__hcd.html#ffefbd33a59a14b8b46406f5aaeaa2f4">00377</a>         <span class="keyword">struct </span><a class="code" href="structdwc__otg__hcd__function__ops.html">dwc_otg_hcd_function_ops</a> *<a class="code" href="dwc__otg__pcd__linux_8c.html#9ce9b5e49c60906c189bee157dd68acd">fops</a>;
+<a name="l00378"></a>00378 
+<a name="l00380"></a><a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html">00380</a>         <span class="keyword">volatile</span> <span class="keyword">union </span><a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html">dwc_otg_hcd_internal_flags</a> {
+<a name="l00381"></a><a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#95ad2033c30d79c28ffcfa6df44af1d5">00381</a>                 uint32_t d32;
+<a name="l00382"></a>00382                 <span class="keyword">struct </span>{
+<a name="l00383"></a><a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#cd31ac4b9658265e90773448f354f0e1">00383</a>                         <span class="keywordtype">unsigned</span> port_connect_status_change:1;
+<a name="l00384"></a><a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#9314ac02ed140807687793b512f78c63">00384</a>                         <span class="keywordtype">unsigned</span> port_connect_status:1;
+<a name="l00385"></a><a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#d0d63f32ed35315e8a02549521fb386e">00385</a>                         <span class="keywordtype">unsigned</span> port_reset_change:1;
+<a name="l00386"></a><a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#d222ae08372109a312f6649f77b650e8">00386</a>                         <span class="keywordtype">unsigned</span> port_enable_change:1;
+<a name="l00387"></a><a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#2a6e323cb4c01153aff1adc6269c74c7">00387</a>                         <span class="keywordtype">unsigned</span> port_suspend_change:1;
+<a name="l00388"></a><a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#bc96cf12e2bc5b61ce05f15ae3297bd6">00388</a>                         <span class="keywordtype">unsigned</span> port_over_current_change:1;
+<a name="l00389"></a><a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#1900375ccea165f0efc40725f507a0bf">00389</a>                         <span class="keywordtype">unsigned</span> port_l1_change:1;
+<a name="l00390"></a><a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#763f58f20d7103f86b4f40f37f501f33">00390</a>                         <span class="keywordtype">unsigned</span> reserved:26;
+<a name="l00391"></a>00391                 } b;
+<a name="l00392"></a>00392         } flags;
+<a name="l00393"></a>00393 
+<a name="l00399"></a><a class="code" href="structdwc__otg__hcd.html#64c96c47a36d71bad6e4360cec9d07ad">00399</a>         dwc_list_link_t non_periodic_sched_inactive;
+<a name="l00400"></a>00400 
+<a name="l00406"></a><a class="code" href="structdwc__otg__hcd.html#ffa3041ad517da9519aa2159cdec3f61">00406</a>         dwc_list_link_t non_periodic_sched_active;
+<a name="l00407"></a>00407 
+<a name="l00412"></a><a class="code" href="structdwc__otg__hcd.html#01ab5791d6269b6b5d506f2113b94231">00412</a>         dwc_list_link_t *non_periodic_qh_ptr;
+<a name="l00413"></a>00413 
+<a name="l00428"></a><a class="code" href="structdwc__otg__hcd.html#2a747cacd6bdbacbef86d4157c34a312">00428</a>         dwc_list_link_t periodic_sched_inactive;
+<a name="l00429"></a>00429 
+<a name="l00437"></a><a class="code" href="structdwc__otg__hcd.html#74b089e094911a558f7b5f24681d3242">00437</a>         dwc_list_link_t periodic_sched_ready;
+<a name="l00438"></a>00438 
+<a name="l00446"></a><a class="code" href="structdwc__otg__hcd.html#4b8deae798f771135c4a99693b26873f">00446</a>         dwc_list_link_t periodic_sched_assigned;
+<a name="l00447"></a>00447 
+<a name="l00457"></a><a class="code" href="structdwc__otg__hcd.html#e127912880eb487b3a2f38778c0de238">00457</a>         dwc_list_link_t periodic_sched_queued;
+<a name="l00458"></a>00458 
+<a name="l00464"></a><a class="code" href="structdwc__otg__hcd.html#1f2ce690c8ded506eff8d1b567747235">00464</a>         uint16_t periodic_usecs;
+<a name="l00465"></a>00465 
+<a name="l00470"></a><a class="code" href="structdwc__otg__hcd.html#f79fefeb7908c0ddf702331253acb292">00470</a>         uint16_t frame_number;
+<a name="l00471"></a>00471 
+<a name="l00476"></a><a class="code" href="structdwc__otg__hcd.html#1761f2e6b8f6ba82c0e0c4e561813f0f">00476</a>         <span class="keyword">struct </span>hc_list free_hc_list;
+<a name="l00483"></a><a class="code" href="structdwc__otg__hcd.html#5754b87bd4644fbb7b90cf843c638f1c">00483</a>         <span class="keywordtype">int</span> periodic_channels;
+<a name="l00484"></a>00484 
+<a name="l00488"></a><a class="code" href="structdwc__otg__hcd.html#e7fff26b5cce7c6c520c89f9e3c75617">00488</a>         <span class="keywordtype">int</span> non_periodic_channels;
+<a name="l00489"></a>00489 
+<a name="l00495"></a><a class="code" href="structdwc__otg__hcd.html#cb393f6a676fb106e0e3d35396fb97f9">00495</a>         <span class="keyword">struct </span><a class="code" href="structdwc__hc.html">dwc_hc</a> *hc_ptr_array[<a class="code" href="dwc__otg__core__if_8h.html#bfb88b45545f7685f668ac2f545674ec">MAX_EPS_CHANNELS</a>];
+<a name="l00496"></a>00496 
+<a name="l00502"></a><a class="code" href="structdwc__otg__hcd.html#68627912f0d3672096e6a98be38f66ab">00502</a>         uint8_t *status_buf;
+<a name="l00503"></a>00503 
+<a name="l00507"></a><a class="code" href="structdwc__otg__hcd.html#3e752b2c5d632d848f3b1fadf543e7a4">00507</a>         dma_addr_t status_buf_dma;
+<a name="l00508"></a><a class="code" href="dwc__otg__hcd_8h.html#d8ae8e24a91bb0b076390e96a8abee18">00508</a> <span class="preprocessor">#define DWC_OTG_HCD_STATUS_BUF_SIZE 64</span>
+<a name="l00509"></a>00509 <span class="preprocessor"></span>
+<a name="l00515"></a><a class="code" href="structdwc__otg__hcd.html#de7796a41bb7d1e45ed9dbc20c995342">00515</a>         dwc_timer_t *conn_timer;
+<a name="l00516"></a>00516 
+<a name="l00517"></a>00517         <span class="comment">/* Tasket to do a reset */</span>
+<a name="l00518"></a><a class="code" href="structdwc__otg__hcd.html#4f2b2c551e4ac9f49afcbdbde1ddf55d">00518</a>         dwc_tasklet_t *reset_tasklet;
+<a name="l00519"></a>00519 
+<a name="l00520"></a>00520         <span class="comment">/*  */</span>
+<a name="l00521"></a><a class="code" href="structdwc__otg__hcd.html#34f29e9c035009476495f7701c1813fd">00521</a>         dwc_spinlock_t *lock;
+<a name="l00522"></a>00522 
+<a name="l00526"></a><a class="code" href="structdwc__otg__hcd.html#c019b908f209d577ccc19d29030926a1">00526</a>         <span class="keywordtype">void</span> *priv;
+<a name="l00527"></a>00527 
+<a name="l00528"></a><a class="code" href="structdwc__otg__hcd.html#9231b4c3dce89a1506a5e501ec5c7a39">00528</a>         uint8_t otg_port;
+<a name="l00529"></a>00529 
+<a name="l00531"></a><a class="code" href="structdwc__otg__hcd.html#77f16d5530f50556ed01fe7f69a135fd">00531</a>         uint32_t *frame_list;
+<a name="l00532"></a>00532 
+<a name="l00534"></a><a class="code" href="structdwc__otg__hcd.html#3421063dcac9d4e200b5d9bbb0508f3d">00534</a>         dma_addr_t frame_list_dma;
+<a name="l00535"></a>00535 
+<a name="l00536"></a>00536 <span class="preprocessor">#ifdef DEBUG</span>
+<a name="l00537"></a>00537 <span class="preprocessor"></span>        uint32_t frrem_samples;
+<a name="l00538"></a>00538         uint64_t frrem_accum;
+<a name="l00539"></a>00539 
+<a name="l00540"></a>00540         uint32_t hfnum_7_samples_a;
+<a name="l00541"></a>00541         uint64_t hfnum_7_frrem_accum_a;
+<a name="l00542"></a>00542         uint32_t hfnum_0_samples_a;
+<a name="l00543"></a>00543         uint64_t hfnum_0_frrem_accum_a;
+<a name="l00544"></a>00544         uint32_t hfnum_other_samples_a;
+<a name="l00545"></a>00545         uint64_t hfnum_other_frrem_accum_a;
+<a name="l00546"></a>00546 
+<a name="l00547"></a>00547         uint32_t hfnum_7_samples_b;
+<a name="l00548"></a>00548         uint64_t hfnum_7_frrem_accum_b;
+<a name="l00549"></a>00549         uint32_t hfnum_0_samples_b;
+<a name="l00550"></a>00550         uint64_t hfnum_0_frrem_accum_b;
+<a name="l00551"></a>00551         uint32_t hfnum_other_samples_b;
+<a name="l00552"></a>00552         uint64_t hfnum_other_frrem_accum_b;
+<a name="l00553"></a>00553 <span class="preprocessor">#endif</span>
+<a name="l00554"></a>00554 <span class="preprocessor"></span>};
+<a name="l00555"></a>00555 
+<a name="l00558"></a>00558 <span class="keyword">extern</span> <a class="code" href="dwc__otg__hcd_8h.html#92c49783eebc5bcffa8b8a51c2127be9">dwc_otg_transaction_type_e</a> <a class="code" href="dwc__otg__hcd_8c.html#96cc299f4f0478187ed7ba49b975ffc3">dwc_otg_hcd_select_transactions</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a>
+<a name="l00559"></a>00559                                                                   * hcd);
+<a name="l00560"></a>00560 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd_8c.html#2f57bf2fc3013d63101f112702b913a0">dwc_otg_hcd_queue_transactions</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd,
+<a name="l00561"></a>00561                                     <a class="code" href="dwc__otg__hcd_8h.html#92c49783eebc5bcffa8b8a51c2127be9">dwc_otg_transaction_type_e</a> tr_type);
+<a name="l00562"></a>00562 
+<a name="l00567"></a>00567 <span class="keyword">extern</span> int32_t <a class="code" href="dwc__otg__hcd_8h.html#b9dde24773f2741b9ff67e2d46760dc0">dwc_otg_hcd_handle_intr</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * <a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>);
+<a name="l00568"></a>00568 <span class="keyword">extern</span> int32_t <a class="code" href="dwc__otg__hcd_8h.html#0eea8527657802e9cf0a62a00bd44a1d">dwc_otg_hcd_handle_sof_intr</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * <a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>);
+<a name="l00569"></a>00569 <span class="keyword">extern</span> int32_t <a class="code" href="dwc__otg__hcd_8h.html#9d979e33e04fc694a72242dec63aeb89">dwc_otg_hcd_handle_rx_status_q_level_intr</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *
+<a name="l00570"></a>00570                                                          <a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>);
+<a name="l00571"></a>00571 <span class="keyword">extern</span> int32_t <a class="code" href="dwc__otg__hcd_8h.html#51c953aefbc2382adee9f585fdb26f35">dwc_otg_hcd_handle_np_tx_fifo_empty_intr</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *
+<a name="l00572"></a>00572                                                         <a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>);
+<a name="l00573"></a>00573 <span class="keyword">extern</span> int32_t <a class="code" href="dwc__otg__hcd_8h.html#dcfa21f80c7732df9aaf3db59a86eb1d">dwc_otg_hcd_handle_perio_tx_fifo_empty_intr</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *
+<a name="l00574"></a>00574                                                            <a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>);
+<a name="l00575"></a>00575 <span class="keyword">extern</span> int32_t dwc_otg_hcd_handle_incomplete_periodic_intr(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *
+<a name="l00576"></a>00576                                                            <a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>);
+<a name="l00577"></a>00577 <span class="keyword">extern</span> int32_t <a class="code" href="dwc__otg__hcd_8h.html#18bb807c86935a45f5fe5940e5ded70c">dwc_otg_hcd_handle_port_intr</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * <a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>);
+<a name="l00578"></a>00578 <span class="keyword">extern</span> int32_t dwc_otg_hcd_handle_conn_id_status_change_intr(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *
+<a name="l00579"></a>00579                                                              <a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>);
+<a name="l00580"></a>00580 <span class="keyword">extern</span> int32_t dwc_otg_hcd_handle_disconnect_intr(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * <a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>);
+<a name="l00581"></a>00581 <span class="keyword">extern</span> int32_t <a class="code" href="dwc__otg__hcd_8h.html#1f28e296c0bc4146da309385d95b5d7e">dwc_otg_hcd_handle_hc_intr</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * <a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>);
+<a name="l00582"></a>00582 <span class="keyword">extern</span> int32_t <a class="code" href="dwc__otg__hcd_8h.html#019c9cc38ec85275a7ef0b0d38bf53ab">dwc_otg_hcd_handle_hc_n_intr</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * <a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>,
+<a name="l00583"></a>00583                                             uint32_t num);
+<a name="l00584"></a>00584 <span class="keyword">extern</span> int32_t dwc_otg_hcd_handle_session_req_intr(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * <a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>);
+<a name="l00585"></a>00585 <span class="keyword">extern</span> int32_t dwc_otg_hcd_handle_wakeup_detected_intr(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *
+<a name="l00586"></a>00586                                                        <a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>);
+<a name="l00592"></a>00592 <span class="comment">/* Implemented in dwc_otg_hcd_queue.c */</span>
+<a name="l00593"></a>00593 <span class="keyword">extern</span> <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *<a class="code" href="dwc__otg__hcd_8h.html#187194b7a9f28e7f7a09ac3e345c7253">dwc_otg_hcd_qh_create</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd,
+<a name="l00594"></a>00594                                            <a class="code" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> * <a class="code" href="structdwc__otg__qtd.html#7e7767808e8eb9d71de0db00f57553f9">urb</a>);
+<a name="l00595"></a>00595 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd_8h.html#1ac731c0691ac3851edddc558fae79e0">dwc_otg_hcd_qh_free</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd, <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> * <a class="code" href="structdwc__otg__qtd.html#f80ddcfb6edbe83a3991dd67c93a47e4">qh</a>);
+<a name="l00596"></a>00596 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd_8h.html#75cad4c6010d88086ddedf739db55d6b">dwc_otg_hcd_qh_add</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd, <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> * <a class="code" href="structdwc__otg__qtd.html#f80ddcfb6edbe83a3991dd67c93a47e4">qh</a>);
+<a name="l00597"></a>00597 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd_8h.html#506b89b01ee7692885daff1c17c894f8">dwc_otg_hcd_qh_remove</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd, <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> * <a class="code" href="structdwc__otg__qtd.html#f80ddcfb6edbe83a3991dd67c93a47e4">qh</a>);
+<a name="l00598"></a>00598 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd_8h.html#f88bc5b6beb674c909d1c09a819ba9d9">dwc_otg_hcd_qh_deactivate</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd, <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> * <a class="code" href="structdwc__otg__qtd.html#f80ddcfb6edbe83a3991dd67c93a47e4">qh</a>,
+<a name="l00599"></a>00599                                       <span class="keywordtype">int</span> sched_csplit);
+<a name="l00600"></a>00600 
+<a name="l00602"></a><a class="code" href="dwc__otg__hcd_8h.html#64eb3490186ebd94fd8204d74c089a51">00602</a> <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd_8h.html#64eb3490186ebd94fd8204d74c089a51">dwc_otg_hcd_qh_remove_and_free</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd,
+<a name="l00603"></a>00603                                                   <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> * <a class="code" href="structdwc__otg__qtd.html#f80ddcfb6edbe83a3991dd67c93a47e4">qh</a>)
+<a name="l00604"></a>00604 {
+<a name="l00605"></a>00605         <a class="code" href="dwc__otg__hcd_8h.html#506b89b01ee7692885daff1c17c894f8">dwc_otg_hcd_qh_remove</a>(hcd, <a class="code" href="structdwc__otg__qtd.html#f80ddcfb6edbe83a3991dd67c93a47e4">qh</a>);
+<a name="l00606"></a>00606         <a class="code" href="dwc__otg__hcd_8h.html#1ac731c0691ac3851edddc558fae79e0">dwc_otg_hcd_qh_free</a>(hcd, <a class="code" href="structdwc__otg__qtd.html#f80ddcfb6edbe83a3991dd67c93a47e4">qh</a>);
+<a name="l00607"></a>00607 }
+<a name="l00608"></a>00608 
+<a name="l00611"></a><a class="code" href="dwc__otg__hcd_8h.html#3252be9fc489fbaa293b2404642caab0">00611</a> <span class="keyword">static</span> <span class="keyword">inline</span> <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *<a class="code" href="dwc__otg__hcd_8h.html#3252be9fc489fbaa293b2404642caab0">dwc_otg_hcd_qh_alloc</a>(<span class="keywordtype">void</span>)
+<a name="l00612"></a>00612 {
+<a name="l00613"></a>00613         <span class="keywordflow">return</span> (<a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *) dwc_alloc(<span class="keyword">sizeof</span>(<a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a>));
+<a name="l00614"></a>00614 }
+<a name="l00615"></a>00615 
+<a name="l00616"></a>00616 <span class="keyword">extern</span> <a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *<a class="code" href="dwc__otg__hcd_8h.html#5c4da8822ae027f70eda33cb783644fc">dwc_otg_hcd_qtd_create</a>(<a class="code" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> * <a class="code" href="structdwc__otg__qtd.html#7e7767808e8eb9d71de0db00f57553f9">urb</a>);
+<a name="l00617"></a>00617 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd_8h.html#9ebb534f604aa8f693da162f32cf1ba4">dwc_otg_hcd_qtd_init</a>(<a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> * qtd, <a class="code" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> * <a class="code" href="structdwc__otg__qtd.html#7e7767808e8eb9d71de0db00f57553f9">urb</a>);
+<a name="l00618"></a>00618 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd_8h.html#748ba77769387bfe4295cb10265053f0">dwc_otg_hcd_qtd_add</a>(<a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> * qtd, <a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * <a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>,
+<a name="l00619"></a>00619                                <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> ** <a class="code" href="structdwc__otg__qtd.html#f80ddcfb6edbe83a3991dd67c93a47e4">qh</a>);
+<a name="l00620"></a>00620 
+<a name="l00623"></a><a class="code" href="dwc__otg__hcd_8h.html#ad58f04f541929d521f9acde9e465577">00623</a> <span class="keyword">static</span> <span class="keyword">inline</span> <a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *<a class="code" href="dwc__otg__hcd_8h.html#ad58f04f541929d521f9acde9e465577">dwc_otg_hcd_qtd_alloc</a>(<span class="keywordtype">void</span>)
+<a name="l00624"></a>00624 {
+<a name="l00625"></a>00625         <span class="keywordflow">return</span> (<a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *) dwc_alloc(<span class="keyword">sizeof</span>(<a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a>));
+<a name="l00626"></a>00626 }
+<a name="l00627"></a>00627 
+<a name="l00631"></a><a class="code" href="dwc__otg__hcd_8h.html#34434d836361462c04fb45ba9ab89fb9">00631</a> <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd_8h.html#34434d836361462c04fb45ba9ab89fb9">dwc_otg_hcd_qtd_free</a>(<a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> * qtd)
+<a name="l00632"></a>00632 {
+<a name="l00633"></a>00633         dwc_free(qtd);
+<a name="l00634"></a>00634 }
+<a name="l00635"></a>00635 
+<a name="l00641"></a><a class="code" href="dwc__otg__hcd_8h.html#2a721977443fb6bd453fbc2e8ae5355d">00641</a> <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd_8h.html#2a721977443fb6bd453fbc2e8ae5355d">dwc_otg_hcd_qtd_remove</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd,
+<a name="l00642"></a>00642                                           <a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> * qtd,
+<a name="l00643"></a>00643                                           <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> * <a class="code" href="structdwc__otg__qtd.html#f80ddcfb6edbe83a3991dd67c93a47e4">qh</a>)
+<a name="l00644"></a>00644 {
+<a name="l00645"></a>00645         uint64_t flags;
+<a name="l00646"></a>00646         DWC_SPINLOCK_IRQSAVE(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#34f29e9c035009476495f7701c1813fd">lock</a>, &amp;flags);
+<a name="l00647"></a>00647         DWC_CIRCLEQ_REMOVE(&amp;<a class="code" href="structdwc__otg__qtd.html#f80ddcfb6edbe83a3991dd67c93a47e4">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#9567d266da8e796d3467fb16ae867f8e">qtd_list</a>, qtd, qtd_list_entry);
+<a name="l00648"></a>00648         DWC_SPINUNLOCK_IRQRESTORE(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#34f29e9c035009476495f7701c1813fd">lock</a>, flags);
+<a name="l00649"></a>00649 }
+<a name="l00650"></a>00650 
+<a name="l00652"></a><a class="code" href="dwc__otg__hcd_8h.html#19adb6641f95448a956015b2d69ba96a">00652</a> <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd_8h.html#19adb6641f95448a956015b2d69ba96a">dwc_otg_hcd_qtd_remove_and_free</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd,
+<a name="l00653"></a>00653                                                    <a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> * qtd,
+<a name="l00654"></a>00654                                                    <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> * <a class="code" href="structdwc__otg__qtd.html#f80ddcfb6edbe83a3991dd67c93a47e4">qh</a>)
+<a name="l00655"></a>00655 {
+<a name="l00656"></a>00656         <a class="code" href="dwc__otg__hcd_8h.html#2a721977443fb6bd453fbc2e8ae5355d">dwc_otg_hcd_qtd_remove</a>(hcd, qtd, <a class="code" href="structdwc__otg__qtd.html#f80ddcfb6edbe83a3991dd67c93a47e4">qh</a>);
+<a name="l00657"></a>00657         <a class="code" href="dwc__otg__hcd_8h.html#34434d836361462c04fb45ba9ab89fb9">dwc_otg_hcd_qtd_free</a>(qtd);
+<a name="l00658"></a>00658 }
+<a name="l00659"></a>00659 
+<a name="l00665"></a>00665 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd_8h.html#9b051bad5e81a6b6d74b817c741bfaf3">dwc_otg_hcd_start_xfer_ddma</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd, <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> * <a class="code" href="structdwc__otg__qtd.html#f80ddcfb6edbe83a3991dd67c93a47e4">qh</a>);
+<a name="l00666"></a>00666 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd_8h.html#ca94cde3142ff1121bb0ff9bd44fa762">dwc_otg_hcd_complete_xfer_ddma</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd,
+<a name="l00667"></a>00667                                            <a class="code" href="structdwc__hc.html">dwc_hc_t</a> * hc,
+<a name="l00668"></a>00668                                            <a class="code" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> * hc_regs,
+<a name="l00669"></a>00669                                            dwc_otg_halt_status_e <a class="code" href="structdwc__hc.html#07eca0fa02105ddaa1719387f5558b23">halt_status</a>);
+<a name="l00670"></a>00670 
+<a name="l00671"></a>00671 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd_8h.html#1c5498d173c5461865a5042789927ed1">dwc_otg_hcd_qh_init_ddma</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd, <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> * <a class="code" href="structdwc__otg__qtd.html#f80ddcfb6edbe83a3991dd67c93a47e4">qh</a>);
+<a name="l00672"></a>00672 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd_8h.html#78738afd0ca62e394753f1cf196476c9">dwc_otg_hcd_qh_free_ddma</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd, <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> * <a class="code" href="structdwc__otg__qtd.html#f80ddcfb6edbe83a3991dd67c93a47e4">qh</a>);
+<a name="l00673"></a>00673 
+<a name="l00678"></a>00678 <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *dwc_urb_to_qh(<a class="code" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> * <a class="code" href="structdwc__otg__qtd.html#7e7767808e8eb9d71de0db00f57553f9">urb</a>);
+<a name="l00681"></a>00681 <span class="preprocessor">#ifdef CONFIG_USB_DWC_OTG_LPM</span>
+<a name="l00682"></a>00682 <span class="preprocessor"></span><span class="keyword">extern</span> <span class="keywordtype">int</span> dwc_otg_hcd_get_hc_for_lpm_tran(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd,
+<a name="l00683"></a>00683                                            uint8_t devaddr);
+<a name="l00684"></a>00684 <span class="keyword">extern</span> <span class="keywordtype">void</span> dwc_otg_hcd_free_hc_from_lpm(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd);
+<a name="l00685"></a>00685 <span class="preprocessor">#endif</span>
+<a name="l00686"></a>00686 <span class="preprocessor"></span>
+<a name="l00688"></a><a class="code" href="dwc__otg__hcd_8h.html#3b2ecfb8dfc0ef59a71aee04313b3a61">00688</a> <span class="preprocessor">#define dwc_list_to_qh(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qh_t, qh_list_entry)</span>
+<a name="l00689"></a>00689 <span class="preprocessor"></span>
+<a name="l00691"></a><a class="code" href="dwc__otg__hcd_8h.html#1cd61c91155aa665057d471f8a020485">00691</a> <span class="preprocessor">#define dwc_list_to_qtd(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qtd_t, qtd_list_entry)</span>
+<a name="l00692"></a>00692 <span class="preprocessor"></span>
+<a name="l00694"></a><a class="code" href="dwc__otg__hcd_8h.html#4621f3eac09a9fc1363d286bff2de06b">00694</a> <span class="preprocessor">#define dwc_qh_is_non_per(_qh_ptr_) ((_qh_ptr_-&gt;ep_type == UE_BULK) || \</span>
+<a name="l00695"></a>00695 <span class="preprocessor">                                     (_qh_ptr_-&gt;ep_type == UE_CONTROL))</span>
+<a name="l00696"></a>00696 <span class="preprocessor"></span>
+<a name="l00698"></a><a class="code" href="dwc__otg__hcd_8h.html#a371dfcb8a66214c8fe226190fc1a323">00698</a> <span class="preprocessor">#define dwc_hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) &gt;&gt; 11) &amp; 0x03))</span>
+<a name="l00699"></a>00699 <span class="preprocessor"></span>
+<a name="l00701"></a><a class="code" href="dwc__otg__hcd_8h.html#bd2189f881088fe7f4ca9112ee24549b">00701</a> <span class="preprocessor">#define dwc_max_packet(wMaxPacketSize) ((wMaxPacketSize) &amp; 0x07ff)</span>
+<a name="l00702"></a>00702 <span class="preprocessor"></span>
+<a name="l00708"></a><a class="code" href="dwc__otg__hcd_8h.html#02aa5e9853fcc705b9b5c839a249e2f8">00708</a> <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd_8h.html#02aa5e9853fcc705b9b5c839a249e2f8">dwc_frame_num_le</a>(uint16_t frame1, uint16_t frame2)
+<a name="l00709"></a>00709 {
+<a name="l00710"></a>00710         <span class="keywordflow">return</span> ((frame2 - frame1) &amp; <a class="code" href="dwc__otg__regs_8h.html#4903938414e67044883b7df5582d6eed">DWC_HFNUM_MAX_FRNUM</a>) &lt;=
+<a name="l00711"></a>00711             (DWC_HFNUM_MAX_FRNUM &gt;&gt; 1);
+<a name="l00712"></a>00712 }
+<a name="l00713"></a>00713 
+<a name="l00719"></a><a class="code" href="dwc__otg__hcd_8h.html#98e0d4310430b84fa660ab5f6e7c24b9">00719</a> <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd_8h.html#98e0d4310430b84fa660ab5f6e7c24b9">dwc_frame_num_gt</a>(uint16_t frame1, uint16_t frame2)
+<a name="l00720"></a>00720 {
+<a name="l00721"></a>00721         <span class="keywordflow">return</span> (frame1 != frame2) &amp;&amp;
+<a name="l00722"></a>00722             (((frame1 - frame2) &amp; <a class="code" href="dwc__otg__regs_8h.html#4903938414e67044883b7df5582d6eed">DWC_HFNUM_MAX_FRNUM</a>) &lt;
+<a name="l00723"></a>00723              (DWC_HFNUM_MAX_FRNUM &gt;&gt; 1));
+<a name="l00724"></a>00724 }
+<a name="l00725"></a>00725 
+<a name="l00730"></a><a class="code" href="dwc__otg__hcd_8h.html#cb175759a6b2cd291eedc276c022b500">00730</a> <span class="keyword">static</span> <span class="keyword">inline</span> uint16_t <a class="code" href="dwc__otg__hcd_8h.html#cb175759a6b2cd291eedc276c022b500">dwc_frame_num_inc</a>(uint16_t frame, uint16_t inc)
+<a name="l00731"></a>00731 {
+<a name="l00732"></a>00732         <span class="keywordflow">return</span> (frame + inc) &amp; <a class="code" href="dwc__otg__regs_8h.html#4903938414e67044883b7df5582d6eed">DWC_HFNUM_MAX_FRNUM</a>;
+<a name="l00733"></a>00733 }
+<a name="l00734"></a>00734 
+<a name="l00735"></a><a class="code" href="dwc__otg__hcd_8h.html#d6248403619d099d04320cb1b7c7ee99">00735</a> <span class="keyword">static</span> <span class="keyword">inline</span> uint16_t <a class="code" href="dwc__otg__hcd_8h.html#d6248403619d099d04320cb1b7c7ee99">dwc_full_frame_num</a>(uint16_t frame)
+<a name="l00736"></a>00736 {
+<a name="l00737"></a>00737         <span class="keywordflow">return</span> (frame &amp; <a class="code" href="dwc__otg__regs_8h.html#4903938414e67044883b7df5582d6eed">DWC_HFNUM_MAX_FRNUM</a>) &gt;&gt; 3;
+<a name="l00738"></a>00738 }
+<a name="l00739"></a>00739 
+<a name="l00740"></a><a class="code" href="dwc__otg__hcd_8h.html#62ca1eeef0a58428b2a105092290c0a4">00740</a> <span class="keyword">static</span> <span class="keyword">inline</span> uint16_t <a class="code" href="dwc__otg__hcd_8h.html#62ca1eeef0a58428b2a105092290c0a4">dwc_micro_frame_num</a>(uint16_t frame)
+<a name="l00741"></a>00741 {
+<a name="l00742"></a>00742         <span class="keywordflow">return</span> frame &amp; 0x7;
+<a name="l00743"></a>00743 }
+<a name="l00744"></a>00744 
+<a name="l00745"></a>00745 <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd_8h.html#8bce109004d7869bfdd9aa1075c6bd2c">dwc_otg_hcd_save_data_toggle</a>(<a class="code" href="structdwc__hc.html">dwc_hc_t</a> * hc,
+<a name="l00746"></a>00746                                   <a class="code" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> * hc_regs, 
+<a name="l00747"></a>00747                                   <a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> * qtd);
+<a name="l00748"></a>00748 
+<a name="l00749"></a>00749 <span class="preprocessor">#ifdef DEBUG</span>
+<a name="l00750"></a>00750 <span class="preprocessor"></span>
+<a name="l00759"></a>00759 <span class="preprocessor">#define dwc_sample_frrem(_hcd, _qh, _letter) \</span>
+<a name="l00760"></a>00760 <span class="preprocessor">{ \</span>
+<a name="l00761"></a>00761 <span class="preprocessor">        hfnum_data_t hfnum; \</span>
+<a name="l00762"></a>00762 <span class="preprocessor">        dwc_otg_qtd_t *qtd; \</span>
+<a name="l00763"></a>00763 <span class="preprocessor">        qtd = list_entry(_qh-&gt;qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); \</span>
+<a name="l00764"></a>00764 <span class="preprocessor">        if (usb_pipeint(qtd-&gt;urb-&gt;pipe) &amp;&amp; _qh-&gt;start_split_frame != 0 &amp;&amp; !qtd-&gt;complete_split) { \</span>
+<a name="l00765"></a>00765 <span class="preprocessor">                hfnum.d32 = dwc_read_reg32(&amp;_hcd-&gt;core_if-&gt;host_if-&gt;host_global_regs-&gt;hfnum); \</span>
+<a name="l00766"></a>00766 <span class="preprocessor">                switch (hfnum.b.frnum &amp; 0x7) { \</span>
+<a name="l00767"></a>00767 <span class="preprocessor">                case 7: \</span>
+<a name="l00768"></a>00768 <span class="preprocessor">                        _hcd-&gt;hfnum_7_samples_##_letter++; \</span>
+<a name="l00769"></a>00769 <span class="preprocessor">                        _hcd-&gt;hfnum_7_frrem_accum_##_letter += hfnum.b.frrem; \</span>
+<a name="l00770"></a>00770 <span class="preprocessor">                        break; \</span>
+<a name="l00771"></a>00771 <span class="preprocessor">                case 0: \</span>
+<a name="l00772"></a>00772 <span class="preprocessor">                        _hcd-&gt;hfnum_0_samples_##_letter++; \</span>
+<a name="l00773"></a>00773 <span class="preprocessor">                        _hcd-&gt;hfnum_0_frrem_accum_##_letter += hfnum.b.frrem; \</span>
+<a name="l00774"></a>00774 <span class="preprocessor">                        break; \</span>
+<a name="l00775"></a>00775 <span class="preprocessor">                default: \</span>
+<a name="l00776"></a>00776 <span class="preprocessor">                        _hcd-&gt;hfnum_other_samples_##_letter++; \</span>
+<a name="l00777"></a>00777 <span class="preprocessor">                        _hcd-&gt;hfnum_other_frrem_accum_##_letter += hfnum.b.frrem; \</span>
+<a name="l00778"></a>00778 <span class="preprocessor">                        break; \</span>
+<a name="l00779"></a>00779 <span class="preprocessor">                } \</span>
+<a name="l00780"></a>00780 <span class="preprocessor">        } \</span>
+<a name="l00781"></a>00781 <span class="preprocessor">}</span>
+<a name="l00782"></a>00782 <span class="preprocessor"></span><span class="preprocessor">#else</span>
+<a name="l00783"></a><a class="code" href="dwc__otg__hcd_8h.html#7bdda6719cefc42f2302c5c34084ba69">00783</a> <span class="preprocessor"></span><span class="preprocessor">#define dwc_sample_frrem(_hcd, _qh, _letter)</span>
+<a name="l00784"></a>00784 <span class="preprocessor"></span><span class="preprocessor">#endif</span>
+<a name="l00785"></a>00785 <span class="preprocessor"></span><span class="preprocessor">#endif</span>
+<a name="l00786"></a>00786 <span class="preprocessor"></span><span class="preprocessor">#endif                          </span><span class="comment">/* DWC_DEVICE_ONLY */</span>
+</pre></div><hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd_8h.html b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd_8h.html
new file mode 100644
index 000000000000..66fd651465a2
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd_8h.html
@@ -0,0 +1,1310 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd.h File Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<h1>dwc_otg_hcd.h File Reference</h1>This file contains the structures, constants, and interfaces for the Host Contoller Driver (HCD). <a href="#_details">More...</a>
+<p>
+<code>#include &lt;usb.h&gt;</code><br>
+<code>#include &quot;<a class="el" href="dwc__otg__hcd__if_8h-source.html">dwc_otg_hcd_if.h</a>&quot;</code><br>
+<code>#include &quot;<a class="el" href="dwc__otg__core__if_8h-source.html">dwc_otg_core_if.h</a>&quot;</code><br>
+<code>#include &quot;dwc_list.h&quot;</code><br>
+<code>#include &quot;<a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a>&quot;</code><br>
+
+<p>
+<a href="dwc__otg__hcd_8h-source.html">Go to the source code of this file.</a><table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Structures</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd__pipe__info.html">dwc_otg_hcd_pipe_info</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd__iso__packet__desc.html">dwc_otg_hcd_iso_packet_desc</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">A Queue Transfer Descriptor (QTD) holds the state of a bulk, control, interrupt, or isochronous transfer.  <a href="structdwc__otg__qtd.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__qh.html">dwc_otg_qh</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">A Queue Head (QH) holds the static characteristics of an endpoint and maintains a list of transfers (QTDs) for that endpoint.  <a href="structdwc__otg__qh.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This structure holds the state of the HCD, including the non-periodic and periodic schedules.  <a href="structdwc__otg__hcd.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">union &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html">dwc_otg_hcd::dwc_otg_hcd_internal_flags</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Internal DWC HCD Flags.  <a href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#_details">More...</a><br></td></tr>
+<tr><td colspan="2"><br><h2>Transaction Execution Functions</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="el" href="dwc__otg__hcd_8h.html#92c49783eebc5bcffa8b8a51c2127be9">dwc_otg_transaction_type_e</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#96cc299f4f0478187ed7ba49b975ffc3">dwc_otg_hcd_select_transactions</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function selects transactions from the HCD transfer schedule and assigns them to available host channels.  <a href="#96cc299f4f0478187ed7ba49b975ffc3"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#2f57bf2fc3013d63101f112702b913a0">dwc_otg_hcd_queue_transactions</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="dwc__otg__hcd_8h.html#92c49783eebc5bcffa8b8a51c2127be9">dwc_otg_transaction_type_e</a> tr_type)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function processes the currently active host channels and queues transactions for these channels to the DWC_otg controller.  <a href="#2f57bf2fc3013d63101f112702b913a0"></a><br></td></tr>
+<tr><td colspan="2"><br><h2>Interrupt Handler Functions</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#b9dde24773f2741b9ff67e2d46760dc0">dwc_otg_hcd_handle_intr</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function handles interrupts for the HCD.  <a href="#b9dde24773f2741b9ff67e2d46760dc0"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#0eea8527657802e9cf0a62a00bd44a1d">dwc_otg_hcd_handle_sof_intr</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Handles the start-of-frame interrupt in host mode.  <a href="#0eea8527657802e9cf0a62a00bd44a1d"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#9d979e33e04fc694a72242dec63aeb89">dwc_otg_hcd_handle_rx_status_q_level_intr</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Handles the Rx Status Queue Level Interrupt, which indicates that there is at least one packet in the Rx FIFO.  <a href="#9d979e33e04fc694a72242dec63aeb89"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#51c953aefbc2382adee9f585fdb26f35">dwc_otg_hcd_handle_np_tx_fifo_empty_intr</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This interrupt occurs when the non-periodic Tx FIFO is half-empty.  <a href="#51c953aefbc2382adee9f585fdb26f35"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#dcfa21f80c7732df9aaf3db59a86eb1d">dwc_otg_hcd_handle_perio_tx_fifo_empty_intr</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This interrupt occurs when the periodic Tx FIFO is half-empty.  <a href="#dcfa21f80c7732df9aaf3db59a86eb1d"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="153ffb1f85a83625614dac76886a1e07"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_otg_hcd_handle_incomplete_periodic_intr" ref="153ffb1f85a83625614dac76886a1e07" args="(dwc_otg_hcd_t *dwc_otg_hcd)" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_otg_hcd_handle_incomplete_periodic_intr</b> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#18bb807c86935a45f5fe5940e5ded70c">dwc_otg_hcd_handle_port_intr</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">There are multiple conditions that can cause a port interrupt.  <a href="#18bb807c86935a45f5fe5940e5ded70c"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="720154a1193b6668bbc2f2df5e6b9f27"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_otg_hcd_handle_conn_id_status_change_intr" ref="720154a1193b6668bbc2f2df5e6b9f27" args="(dwc_otg_hcd_t *dwc_otg_hcd)" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_otg_hcd_handle_conn_id_status_change_intr</b> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="02c77bd38ea59ba2a786392df4ecb5b8"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_otg_hcd_handle_disconnect_intr" ref="02c77bd38ea59ba2a786392df4ecb5b8" args="(dwc_otg_hcd_t *dwc_otg_hcd)" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_otg_hcd_handle_disconnect_intr</b> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#1f28e296c0bc4146da309385d95b5d7e">dwc_otg_hcd_handle_hc_intr</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This interrupt indicates that one or more host channels has a pending interrupt.  <a href="#1f28e296c0bc4146da309385d95b5d7e"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="019c9cc38ec85275a7ef0b0d38bf53ab"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_otg_hcd_handle_hc_n_intr" ref="019c9cc38ec85275a7ef0b0d38bf53ab" args="(dwc_otg_hcd_t *dwc_otg_hcd, uint32_t num)" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#019c9cc38ec85275a7ef0b0d38bf53ab">dwc_otg_hcd_handle_hc_n_intr</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>, uint32_t num)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Handles interrupt for a specific Host Channel. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="93406a45cbba24014f85e2b7074f07d2"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_otg_hcd_handle_session_req_intr" ref="93406a45cbba24014f85e2b7074f07d2" args="(dwc_otg_hcd_t *dwc_otg_hcd)" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_otg_hcd_handle_session_req_intr</b> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="9781fc0cab04bd26af3016d8094ef760"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_otg_hcd_handle_wakeup_detected_intr" ref="9781fc0cab04bd26af3016d8094ef760" args="(dwc_otg_hcd_t *dwc_otg_hcd)" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_otg_hcd_handle_wakeup_detected_intr</b> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>)</td></tr>
+
+<tr><td colspan="2"><br><h2>Schedule Queue Functions</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#187194b7a9f28e7f7a09ac3e345c7253">dwc_otg_hcd_qh_create</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *urb)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function allocates and initializes a QH.  <a href="#187194b7a9f28e7f7a09ac3e345c7253"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#1ac731c0691ac3851edddc558fae79e0">dwc_otg_hcd_qh_free</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *qh)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Free each QTD in the QH's QTD-list then free the QH.  <a href="#1ac731c0691ac3851edddc558fae79e0"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#75cad4c6010d88086ddedf739db55d6b">dwc_otg_hcd_qh_add</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *qh)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function adds a QH to either the non periodic or periodic schedule if it is not already in the schedule.  <a href="#75cad4c6010d88086ddedf739db55d6b"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#506b89b01ee7692885daff1c17c894f8">dwc_otg_hcd_qh_remove</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *qh)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Removes a QH from either the non-periodic or periodic schedule.  <a href="#506b89b01ee7692885daff1c17c894f8"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#f88bc5b6beb674c909d1c09a819ba9d9">dwc_otg_hcd_qh_deactivate</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *qh, int sched_csplit)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Deactivates a QH.  <a href="#f88bc5b6beb674c909d1c09a819ba9d9"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="64eb3490186ebd94fd8204d74c089a51"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_otg_hcd_qh_remove_and_free" ref="64eb3490186ebd94fd8204d74c089a51" args="(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)" -->
+static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#64eb3490186ebd94fd8204d74c089a51">dwc_otg_hcd_qh_remove_and_free</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *qh)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Remove and free a QH. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static <a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#3252be9fc489fbaa293b2404642caab0">dwc_otg_hcd_qh_alloc</a> (void)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Allocates memory for a QH structure.  <a href="#3252be9fc489fbaa293b2404642caab0"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#5c4da8822ae027f70eda33cb783644fc">dwc_otg_hcd_qtd_create</a> (<a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *urb)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function allocates and initializes a QTD.  <a href="#5c4da8822ae027f70eda33cb783644fc"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#9ebb534f604aa8f693da162f32cf1ba4">dwc_otg_hcd_qtd_init</a> (<a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *qtd, <a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *urb)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Initializes a QTD structure.  <a href="#9ebb534f604aa8f693da162f32cf1ba4"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#748ba77769387bfe4295cb10265053f0">dwc_otg_hcd_qtd_add</a> (<a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *qtd, <a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>, <a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> **qh)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function adds a QTD to the QTD-list of a QH.  <a href="#748ba77769387bfe4295cb10265053f0"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static <a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#ad58f04f541929d521f9acde9e465577">dwc_otg_hcd_qtd_alloc</a> (void)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Allocates memory for a QTD structure.  <a href="#ad58f04f541929d521f9acde9e465577"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#34434d836361462c04fb45ba9ab89fb9">dwc_otg_hcd_qtd_free</a> (<a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *qtd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Frees the memory for a QTD structure.  <a href="#34434d836361462c04fb45ba9ab89fb9"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#2a721977443fb6bd453fbc2e8ae5355d">dwc_otg_hcd_qtd_remove</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *qtd, <a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *qh)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Removes a QTD from list.  <a href="#2a721977443fb6bd453fbc2e8ae5355d"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="19adb6641f95448a956015b2d69ba96a"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_otg_hcd_qtd_remove_and_free" ref="19adb6641f95448a956015b2d69ba96a" args="(dwc_otg_hcd_t *hcd, dwc_otg_qtd_t *qtd, dwc_otg_qh_t *qh)" -->
+static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#19adb6641f95448a956015b2d69ba96a">dwc_otg_hcd_qtd_remove_and_free</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *qtd, <a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *qh)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Remove and free a QTD. <br></td></tr>
+<tr><td colspan="2"><br><h2>Descriptor DMA Supporting Functions</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#9b051bad5e81a6b6d74b817c741bfaf3">dwc_otg_hcd_start_xfer_ddma</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *qh)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">For Control and Bulk endpoints initializes descriptor list and starts the transfer.  <a href="#9b051bad5e81a6b6d74b817c741bfaf3"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#ca94cde3142ff1121bb0ff9bd44fa762">dwc_otg_hcd_complete_xfer_ddma</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__hc.html">dwc_hc_t</a> *hc, <a class="el" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *hc_regs, dwc_otg_halt_status_e halt_status)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function is called from interrupt handlers.  <a href="#ca94cde3142ff1121bb0ff9bd44fa762"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#1c5498d173c5461865a5042789927ed1">dwc_otg_hcd_qh_init_ddma</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *qh)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Initializes a QH structure's Descriptor DMA related members.  <a href="#1c5498d173c5461865a5042789927ed1"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#78738afd0ca62e394753f1cf196476c9">dwc_otg_hcd_qh_free_ddma</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *qh)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Frees descriptor list memory associated with the QH.  <a href="#78738afd0ca62e394753f1cf196476c9"></a><br></td></tr>
+<tr><td colspan="2"><br><h2>Internal Functions</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="041e0339d432cb37501a9dfde9ea6701"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_urb_to_qh" ref="041e0339d432cb37501a9dfde9ea6701" args="(dwc_otg_hcd_urb_t *urb)" -->
+<a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><b>dwc_urb_to_qh</b> (<a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *urb)</td></tr>
+
+<tr><td colspan="2"><br><h2>Defines</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="d8ae8e24a91bb0b076390e96a8abee18"></a><!-- doxytag: member="dwc_otg_hcd.h::DWC_OTG_HCD_STATUS_BUF_SIZE" ref="d8ae8e24a91bb0b076390e96a8abee18" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#d8ae8e24a91bb0b076390e96a8abee18">DWC_OTG_HCD_STATUS_BUF_SIZE</a>&nbsp;&nbsp;&nbsp;64</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3b2ecfb8dfc0ef59a71aee04313b3a61"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_list_to_qh" ref="3b2ecfb8dfc0ef59a71aee04313b3a61" args="(_list_head_ptr_)" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#3b2ecfb8dfc0ef59a71aee04313b3a61">dwc_list_to_qh</a>(_list_head_ptr_)&nbsp;&nbsp;&nbsp;container_of(_list_head_ptr_, <a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a>, qh_list_entry)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Gets the QH that contains the list_head. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="1cd61c91155aa665057d471f8a020485"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_list_to_qtd" ref="1cd61c91155aa665057d471f8a020485" args="(_list_head_ptr_)" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#1cd61c91155aa665057d471f8a020485">dwc_list_to_qtd</a>(_list_head_ptr_)&nbsp;&nbsp;&nbsp;container_of(_list_head_ptr_, <a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a>, qtd_list_entry)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Gets the QTD that contains the list_head. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#4621f3eac09a9fc1363d286bff2de06b">dwc_qh_is_non_per</a>(_qh_ptr_)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Check if QH is non-periodic.  <a href="#4621f3eac09a9fc1363d286bff2de06b"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="a371dfcb8a66214c8fe226190fc1a323"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_hb_mult" ref="a371dfcb8a66214c8fe226190fc1a323" args="(wMaxPacketSize)" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#a371dfcb8a66214c8fe226190fc1a323">dwc_hb_mult</a>(wMaxPacketSize)&nbsp;&nbsp;&nbsp;(1 + (((wMaxPacketSize) &gt;&gt; 11) &amp; 0x03))</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">High bandwidth multiplier as encoded in highspeed endpoint descriptors. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="bd2189f881088fe7f4ca9112ee24549b"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_max_packet" ref="bd2189f881088fe7f4ca9112ee24549b" args="(wMaxPacketSize)" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#bd2189f881088fe7f4ca9112ee24549b">dwc_max_packet</a>(wMaxPacketSize)&nbsp;&nbsp;&nbsp;((wMaxPacketSize) &amp; 0x07ff)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Packet size for any kind of endpoint descriptor. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7bdda6719cefc42f2302c5c34084ba69"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_sample_frrem" ref="7bdda6719cefc42f2302c5c34084ba69" args="(_hcd, _qh, _letter)" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#7bdda6719cefc42f2302c5c34084ba69">dwc_sample_frrem</a>(_hcd, _qh, _letter)</td></tr>
+
+<tr><td colspan="2"><br><h2>Typedefs</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="be7c5653ee5e9d33855d2513f31b56a5"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_otg_control_phase_e" ref="be7c5653ee5e9d33855d2513f31b56a5" args="" -->
+typedef enum <a class="el" href="dwc__otg__hcd_8h.html#4ec934997af9e24c8eede108d399c140">dwc_otg_control_phase</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#be7c5653ee5e9d33855d2513f31b56a5">dwc_otg_control_phase_e</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Phases for control transfers. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="92c49783eebc5bcffa8b8a51c2127be9"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_otg_transaction_type_e" ref="92c49783eebc5bcffa8b8a51c2127be9" args="" -->
+typedef enum <a class="el" href="dwc__otg__hcd_8h.html#0ab043da15526ddcd3f3698505d52d83">dwc_otg_transaction_type</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#92c49783eebc5bcffa8b8a51c2127be9">dwc_otg_transaction_type_e</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Transaction types. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef <a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#05542225d8dd075a2b981fa565bdfccc">dwc_otg_qtd_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">A Queue Transfer Descriptor (QTD) holds the state of a bulk, control, interrupt, or isochronous transfer.  <a href="#05542225d8dd075a2b981fa565bdfccc"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef <a class="el" href="structdwc__otg__qh.html">dwc_otg_qh</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#7d1300eb1d7683e646af1094fe418c0b">dwc_otg_qh_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">A Queue Head (QH) holds the static characteristics of an endpoint and maintains a list of transfers (QTDs) for that endpoint.  <a href="#7d1300eb1d7683e646af1094fe418c0b"></a><br></td></tr>
+<tr><td colspan="2"><br><h2>Enumerations</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">enum &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#4ec934997af9e24c8eede108d399c140">dwc_otg_control_phase</a> { <b>DWC_OTG_CONTROL_SETUP</b>, 
+<b>DWC_OTG_CONTROL_DATA</b>, 
+<b>DWC_OTG_CONTROL_STATUS</b>
+ }</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Phases for control transfers. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">enum &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#0ab043da15526ddcd3f3698505d52d83">dwc_otg_transaction_type</a> { <b>DWC_OTG_TRANSACTION_NONE</b>, 
+<b>DWC_OTG_TRANSACTION_PERIODIC</b>, 
+<b>DWC_OTG_TRANSACTION_NON_PERIODIC</b>, 
+<b>DWC_OTG_TRANSACTION_ALL</b>
+ }</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Transaction types. <br></td></tr>
+<tr><td colspan="2"><br><h2>Functions</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="367b79057f321cfa65023f4026d6c2c9"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_otg_hcd_get_ep_num" ref="367b79057f321cfa65023f4026d6c2c9" args="(struct dwc_otg_hcd_pipe_info *pipe)" -->
+static uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#367b79057f321cfa65023f4026d6c2c9">dwc_otg_hcd_get_ep_num</a> (struct <a class="el" href="structdwc__otg__hcd__pipe__info.html">dwc_otg_hcd_pipe_info</a> *pipe)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b97cea598797e69d011ffef89989a739"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_otg_hcd_get_pipe_type" ref="b97cea598797e69d011ffef89989a739" args="(struct dwc_otg_hcd_pipe_info *pipe)" -->
+static uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#b97cea598797e69d011ffef89989a739">dwc_otg_hcd_get_pipe_type</a> (struct <a class="el" href="structdwc__otg__hcd__pipe__info.html">dwc_otg_hcd_pipe_info</a> *pipe)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e47df3e0ac1c8ccc916e0c0895568c88"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_otg_hcd_get_mps" ref="e47df3e0ac1c8ccc916e0c0895568c88" args="(struct dwc_otg_hcd_pipe_info *pipe)" -->
+static uint16_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#e47df3e0ac1c8ccc916e0c0895568c88">dwc_otg_hcd_get_mps</a> (struct <a class="el" href="structdwc__otg__hcd__pipe__info.html">dwc_otg_hcd_pipe_info</a> *pipe)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="0de365358ba4472d56c1ac8074ba926b"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_otg_hcd_get_dev_addr" ref="0de365358ba4472d56c1ac8074ba926b" args="(struct dwc_otg_hcd_pipe_info *pipe)" -->
+static uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#0de365358ba4472d56c1ac8074ba926b">dwc_otg_hcd_get_dev_addr</a> (struct <a class="el" href="structdwc__otg__hcd__pipe__info.html">dwc_otg_hcd_pipe_info</a> *pipe)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3ae411bce062f6929961046492c96330"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_otg_hcd_is_pipe_isoc" ref="3ae411bce062f6929961046492c96330" args="(struct dwc_otg_hcd_pipe_info *pipe)" -->
+static uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#3ae411bce062f6929961046492c96330">dwc_otg_hcd_is_pipe_isoc</a> (struct <a class="el" href="structdwc__otg__hcd__pipe__info.html">dwc_otg_hcd_pipe_info</a> *pipe)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="9bd15e815decf74a7033c11e57d98bde"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_otg_hcd_is_pipe_int" ref="9bd15e815decf74a7033c11e57d98bde" args="(struct dwc_otg_hcd_pipe_info *pipe)" -->
+static uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#9bd15e815decf74a7033c11e57d98bde">dwc_otg_hcd_is_pipe_int</a> (struct <a class="el" href="structdwc__otg__hcd__pipe__info.html">dwc_otg_hcd_pipe_info</a> *pipe)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7e0a4084d0444c4375dd60250b860ad8"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_otg_hcd_is_pipe_bulk" ref="7e0a4084d0444c4375dd60250b860ad8" args="(struct dwc_otg_hcd_pipe_info *pipe)" -->
+static uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#7e0a4084d0444c4375dd60250b860ad8">dwc_otg_hcd_is_pipe_bulk</a> (struct <a class="el" href="structdwc__otg__hcd__pipe__info.html">dwc_otg_hcd_pipe_info</a> *pipe)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="d40e602eb8b015dc3908a23d2f8fbb7a"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_otg_hcd_is_pipe_control" ref="d40e602eb8b015dc3908a23d2f8fbb7a" args="(struct dwc_otg_hcd_pipe_info *pipe)" -->
+static uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#d40e602eb8b015dc3908a23d2f8fbb7a">dwc_otg_hcd_is_pipe_control</a> (struct <a class="el" href="structdwc__otg__hcd__pipe__info.html">dwc_otg_hcd_pipe_info</a> *pipe)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="68de5629a8b45d9bec58f680fa4c820c"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_otg_hcd_is_pipe_in" ref="68de5629a8b45d9bec58f680fa4c820c" args="(struct dwc_otg_hcd_pipe_info *pipe)" -->
+static uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#68de5629a8b45d9bec58f680fa4c820c">dwc_otg_hcd_is_pipe_in</a> (struct <a class="el" href="structdwc__otg__hcd__pipe__info.html">dwc_otg_hcd_pipe_info</a> *pipe)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="cf3e5e59a22ef6bd497e05710e39cad0"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_otg_hcd_is_pipe_out" ref="cf3e5e59a22ef6bd497e05710e39cad0" args="(struct dwc_otg_hcd_pipe_info *pipe)" -->
+static uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#cf3e5e59a22ef6bd497e05710e39cad0">dwc_otg_hcd_is_pipe_out</a> (struct <a class="el" href="structdwc__otg__hcd__pipe__info.html">dwc_otg_hcd_pipe_info</a> *pipe)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="4806306754f0414ad9cee3067cdda8c9"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_otg_hcd_fill_pipe" ref="4806306754f0414ad9cee3067cdda8c9" args="(struct dwc_otg_hcd_pipe_info *pipe, uint8_t devaddr, uint8_t ep_num, uint8_t pipe_type, uint8_t pipe_dir, uint16_t mps)" -->
+static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#4806306754f0414ad9cee3067cdda8c9">dwc_otg_hcd_fill_pipe</a> (struct <a class="el" href="structdwc__otg__hcd__pipe__info.html">dwc_otg_hcd_pipe_info</a> *pipe, uint8_t devaddr, uint8_t ep_num, uint8_t pipe_type, uint8_t pipe_dir, uint16_t mps)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ec4587fa46d9a511753a19d686721596"></a><!-- doxytag: member="dwc_otg_hcd.h::DWC_CIRCLEQ_HEAD" ref="ec4587fa46d9a511753a19d686721596" args="(dwc_otg_qtd_list, dwc_otg_qtd)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_CIRCLEQ_HEAD</b> (dwc_otg_qtd_list, <a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd</a>)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="178f3f9a015344c0560140b5f5b8b83a"></a><!-- doxytag: member="dwc_otg_hcd.h::DWC_CIRCLEQ_HEAD" ref="178f3f9a015344c0560140b5f5b8b83a" args="(hc_list, dwc_hc)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_CIRCLEQ_HEAD</b> (hc_list, <a class="el" href="structdwc__hc.html">dwc_hc</a>)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#02aa5e9853fcc705b9b5c839a249e2f8">dwc_frame_num_le</a> (uint16_t frame1, uint16_t frame2)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Returns true if _frame1 is less than or equal to _frame2.  <a href="#02aa5e9853fcc705b9b5c839a249e2f8"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#98e0d4310430b84fa660ab5f6e7c24b9">dwc_frame_num_gt</a> (uint16_t frame1, uint16_t frame2)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Returns true if _frame1 is greater than _frame2.  <a href="#98e0d4310430b84fa660ab5f6e7c24b9"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static uint16_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#cb175759a6b2cd291eedc276c022b500">dwc_frame_num_inc</a> (uint16_t frame, uint16_t inc)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Increments _frame by the amount specified by _inc.  <a href="#cb175759a6b2cd291eedc276c022b500"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="d6248403619d099d04320cb1b7c7ee99"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_full_frame_num" ref="d6248403619d099d04320cb1b7c7ee99" args="(uint16_t frame)" -->
+static uint16_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#d6248403619d099d04320cb1b7c7ee99">dwc_full_frame_num</a> (uint16_t frame)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="62ca1eeef0a58428b2a105092290c0a4"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_micro_frame_num" ref="62ca1eeef0a58428b2a105092290c0a4" args="(uint16_t frame)" -->
+static uint16_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#62ca1eeef0a58428b2a105092290c0a4">dwc_micro_frame_num</a> (uint16_t frame)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="8bce109004d7869bfdd9aa1075c6bd2c"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_otg_hcd_save_data_toggle" ref="8bce109004d7869bfdd9aa1075c6bd2c" args="(dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd_8h.html#8bce109004d7869bfdd9aa1075c6bd2c">dwc_otg_hcd_save_data_toggle</a> (<a class="el" href="structdwc__hc.html">dwc_hc_t</a> *hc, <a class="el" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *hc_regs, <a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *qtd)</td></tr>
+
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This file contains the structures, constants, and interfaces for the Host Contoller Driver (HCD). 
+<p>
+The Host Controller Driver (HCD) is responsible for translating requests from the USB Driver into the appropriate actions on the DWC_otg controller. It isolates the USBD from the specifics of the controller by providing an API to the USBD. 
+<p>
+Definition in file <a class="el" href="dwc__otg__hcd_8h-source.html">dwc_otg_hcd.h</a>.<hr><h2>Define Documentation</h2>
+<a class="anchor" name="4621f3eac09a9fc1363d286bff2de06b"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_qh_is_non_per" ref="4621f3eac09a9fc1363d286bff2de06b" args="(_qh_ptr_)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define dwc_qh_is_non_per          </td>
+          <td>(</td>
+          <td class="paramtype">_qh_ptr_&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment">((_qh_ptr_-&gt;ep_type == UE_BULK) || \
+                                     (_qh_ptr_-&gt;ep_type == UE_CONTROL))
+</pre></div>Check if QH is non-periodic. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8h-source.html#l00694">694</a> of file <a class="el" href="dwc__otg__hcd_8h-source.html">dwc_otg_hcd.h</a>.
+</div>
+</div><p>
+<hr><h2>Typedef Documentation</h2>
+<a class="anchor" name="05542225d8dd075a2b981fa565bdfccc"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_otg_qtd_t" ref="05542225d8dd075a2b981fa565bdfccc" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef struct <a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd</a>  <a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+A Queue Transfer Descriptor (QTD) holds the state of a bulk, control, interrupt, or isochronous transfer. 
+<p>
+A single QTD is created for each URB (of one of these types) submitted to the HCD. The transfer associated with a QTD may require one or multiple transactions.<p>
+A QTD is linked to a Queue Head, which is entered in either the non-periodic or periodic schedule for execution. When a QTD is chosen for execution, some or all of its transactions may be executed. After execution, the state of the QTD is updated. The QTD may be retired if all its transactions are complete or if an error occurred. Otherwise, it remains in the schedule so more transactions can be executed later. 
+</div>
+</div><p>
+<a class="anchor" name="7d1300eb1d7683e646af1094fe418c0b"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_otg_qh_t" ref="7d1300eb1d7683e646af1094fe418c0b" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef struct <a class="el" href="structdwc__otg__qh.html">dwc_otg_qh</a>  <a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+A Queue Head (QH) holds the static characteristics of an endpoint and maintains a list of transfers (QTDs) for that endpoint. 
+<p>
+A QH structure may be entered in either the non-periodic or periodic schedule. 
+</div>
+</div><p>
+<hr><h2>Function Documentation</h2>
+<a class="anchor" name="96cc299f4f0478187ed7ba49b975ffc3"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_otg_hcd_select_transactions" ref="96cc299f4f0478187ed7ba49b975ffc3" args="(dwc_otg_hcd_t *hcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="dwc__otg__hcd_8h.html#92c49783eebc5bcffa8b8a51c2127be9">dwc_otg_transaction_type_e</a> dwc_otg_hcd_select_transactions           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function selects transactions from the HCD transfer schedule and assigns them to available host channels. 
+<p>
+It is called from HCD interrupt handler functions.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD state structure.</td></tr>
+  </table>
+</dl>
+<dl compact><dt><b>Returns:</b></dt><dd>The types of new transactions that were assigned to host channels. </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l01055">1055</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="2f57bf2fc3013d63101f112702b913a0"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_otg_hcd_queue_transactions" ref="2f57bf2fc3013d63101f112702b913a0" args="(dwc_otg_hcd_t *hcd, dwc_otg_transaction_type_e tr_type)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_hcd_queue_transactions           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="dwc__otg__hcd_8h.html#92c49783eebc5bcffa8b8a51c2127be9">dwc_otg_transaction_type_e</a>&nbsp;</td>
+          <td class="paramname"> <em>tr_type</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function processes the currently active host channels and queues transactions for these channels to the DWC_otg controller. 
+<p>
+It is called from HCD interrupt handler functions.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD state structure. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>tr_type</em>&nbsp;</td><td>The type(s) of transactions to queue (non-periodic, periodic, or both). </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l01426">1426</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="b9dde24773f2741b9ff67e2d46760dc0"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_otg_hcd_handle_intr" ref="b9dde24773f2741b9ff67e2d46760dc0" args="(dwc_otg_hcd_t *dwc_otg_hcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t dwc_otg_hcd_handle_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>dwc_otg_hcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function handles interrupts for the HCD. 
+<p>
+
+<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000016">Todo:</a></b></dt><dd>Implement i2cintr handler. </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__intr_8c-source.html#l00043">43</a> of file <a class="el" href="dwc__otg__hcd__intr_8c-source.html">dwc_otg_hcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="0eea8527657802e9cf0a62a00bd44a1d"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_otg_hcd_handle_sof_intr" ref="0eea8527657802e9cf0a62a00bd44a1d" args="(dwc_otg_hcd_t *dwc_otg_hcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t dwc_otg_hcd_handle_sof_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Handles the start-of-frame interrupt in host mode. 
+<p>
+Non-periodic transactions may be queued to the DWC_otg controller for the current (micro)frame. Periodic transactions may be queued to the controller for the next (micro)frame. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__intr_8c-source.html#l00169">169</a> of file <a class="el" href="dwc__otg__hcd__intr_8c-source.html">dwc_otg_hcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="9d979e33e04fc694a72242dec63aeb89"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_otg_hcd_handle_rx_status_q_level_intr" ref="9d979e33e04fc694a72242dec63aeb89" args="(dwc_otg_hcd_t *dwc_otg_hcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t dwc_otg_hcd_handle_rx_status_q_level_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>dwc_otg_hcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Handles the Rx Status Queue Level Interrupt, which indicates that there is at least one packet in the Rx FIFO. 
+<p>
+The packets are moved from the FIFO to memory if the DWC_otg controller is operating in Slave mode. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__intr_8c-source.html#l00222">222</a> of file <a class="el" href="dwc__otg__hcd__intr_8c-source.html">dwc_otg_hcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="51c953aefbc2382adee9f585fdb26f35"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_otg_hcd_handle_np_tx_fifo_empty_intr" ref="51c953aefbc2382adee9f585fdb26f35" args="(dwc_otg_hcd_t *dwc_otg_hcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>dwc_otg_hcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This interrupt occurs when the non-periodic Tx FIFO is half-empty. 
+<p>
+More data packets may be written to the FIFO for OUT transfers. More requests may be written to the non-periodic request queue for IN transfers. This interrupt is enabled only in Slave mode. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__intr_8c-source.html#l00271">271</a> of file <a class="el" href="dwc__otg__hcd__intr_8c-source.html">dwc_otg_hcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="dcfa21f80c7732df9aaf3db59a86eb1d"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_otg_hcd_handle_perio_tx_fifo_empty_intr" ref="dcfa21f80c7732df9aaf3db59a86eb1d" args="(dwc_otg_hcd_t *dwc_otg_hcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>dwc_otg_hcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This interrupt occurs when the periodic Tx FIFO is half-empty. 
+<p>
+More data packets may be written to the FIFO for OUT transfers. More requests may be written to the periodic request queue for IN transfers. This interrupt is enabled only in Slave mode. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__intr_8c-source.html#l00283">283</a> of file <a class="el" href="dwc__otg__hcd__intr_8c-source.html">dwc_otg_hcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="18bb807c86935a45f5fe5940e5ded70c"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_otg_hcd_handle_port_intr" ref="18bb807c86935a45f5fe5940e5ded70c" args="(dwc_otg_hcd_t *dwc_otg_hcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t dwc_otg_hcd_handle_port_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>dwc_otg_hcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+There are multiple conditions that can cause a port interrupt. 
+<p>
+This function determines which interrupt conditions have occurred and handles them appropriately. 
+<p>
+Overcurrent Change Interrupt 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__intr_8c-source.html#l00294">294</a> of file <a class="el" href="dwc__otg__hcd__intr_8c-source.html">dwc_otg_hcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="1f28e296c0bc4146da309385d95b5d7e"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_otg_hcd_handle_hc_intr" ref="1f28e296c0bc4146da309385d95b5d7e" args="(dwc_otg_hcd_t *dwc_otg_hcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t dwc_otg_hcd_handle_hc_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>dwc_otg_hcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This interrupt indicates that one or more host channels has a pending interrupt. 
+<p>
+There are multiple conditions that can cause each host channel interrupt. This function determines which conditions have occurred for each host channel interrupt and handles them appropriately. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__intr_8c-source.html#l00453">453</a> of file <a class="el" href="dwc__otg__hcd__intr_8c-source.html">dwc_otg_hcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="187194b7a9f28e7f7a09ac3e345c7253"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_otg_hcd_qh_create" ref="187194b7a9f28e7f7a09ac3e345c7253" args="(dwc_otg_hcd_t *hcd, dwc_otg_hcd_urb_t *urb)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a>* dwc_otg_hcd_qh_create           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>urb</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function allocates and initializes a QH. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD state structure for the DWC OTG controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>urb</em>&nbsp;</td><td>Holds the information about the device/endpoint that we need to initialize the QH.</td></tr>
+  </table>
+</dl>
+<dl compact><dt><b>Returns:</b></dt><dd>Returns pointer to the newly allocated QH, or NULL on error. </dd></dl>
+
+<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000020">Todo:</a></b></dt><dd>add memflags argument </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__queue_8c-source.html#l00296">296</a> of file <a class="el" href="dwc__otg__hcd__queue_8c-source.html">dwc_otg_hcd_queue.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="1ac731c0691ac3851edddc558fae79e0"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_otg_hcd_qh_free" ref="1ac731c0691ac3851edddc558fae79e0" args="(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_hcd_qh_free           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>qh</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Free each QTD in the QH's QTD-list then free the QH. 
+<p>
+QH should already be removed from a list. QTD list should already be empty if called from URB Dequeue.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>HCD instance. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>qh</em>&nbsp;</td><td>The QH to free. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__queue_8c-source.html#l00053">53</a> of file <a class="el" href="dwc__otg__hcd__queue_8c-source.html">dwc_otg_hcd_queue.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="75cad4c6010d88086ddedf739db55d6b"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_otg_hcd_qh_add" ref="75cad4c6010d88086ddedf739db55d6b" args="(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_hcd_qh_add           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>qh</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function adds a QH to either the non periodic or periodic schedule if it is not already in the schedule. 
+<p>
+If the QH is already in the schedule, no action is taken.<p>
+<dl compact><dt><b>Returns:</b></dt><dd>0 if successful, negative error code otherwise. </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__queue_8c-source.html#l00472">472</a> of file <a class="el" href="dwc__otg__hcd__queue_8c-source.html">dwc_otg_hcd_queue.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="506b89b01ee7692885daff1c17c894f8"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_otg_hcd_qh_remove" ref="506b89b01ee7692885daff1c17c894f8" args="(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_hcd_qh_remove           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>qh</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Removes a QH from either the non-periodic or periodic schedule. 
+<p>
+Memory is not freed.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD state structure. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>qh</em>&nbsp;</td><td>QH to remove from schedule. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__queue_8c-source.html#l00522">522</a> of file <a class="el" href="dwc__otg__hcd__queue_8c-source.html">dwc_otg_hcd_queue.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="f88bc5b6beb674c909d1c09a819ba9d9"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_otg_hcd_qh_deactivate" ref="f88bc5b6beb674c909d1c09a819ba9d9" args="(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, int sched_csplit)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_hcd_qh_deactivate           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>qh</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>sched_next_periodic_split</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Deactivates a QH. 
+<p>
+For non-periodic QHs, removes the QH from the active non-periodic schedule. The QH is added to the inactive non-periodic schedule if any QTDs are still attached to the QH.<p>
+For periodic QHs, the QH is removed from the periodic queued schedule. If there are any QTDs still attached to the QH, the QH is added to either the periodic inactive schedule or the periodic ready schedule and its next scheduled frame is calculated. The QH is placed in the ready schedule if the scheduled frame has been reached already. Otherwise it's placed in the inactive schedule. If there are no QTDs attached to the QH, the QH is completely removed from the periodic schedule. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__queue_8c-source.html#l00559">559</a> of file <a class="el" href="dwc__otg__hcd__queue_8c-source.html">dwc_otg_hcd_queue.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="3252be9fc489fbaa293b2404642caab0"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_otg_hcd_qh_alloc" ref="3252be9fc489fbaa293b2404642caab0" args="(void)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static <a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a>* dwc_otg_hcd_qh_alloc           </td>
+          <td>(</td>
+          <td class="paramtype">void&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [inline, static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Allocates memory for a QH structure. 
+<p>
+<dl compact><dt><b>Returns:</b></dt><dd>Returns the memory allocate or NULL on error. </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8h-source.html#l00611">611</a> of file <a class="el" href="dwc__otg__hcd_8h-source.html">dwc_otg_hcd.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="5c4da8822ae027f70eda33cb783644fc"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_otg_hcd_qtd_create" ref="5c4da8822ae027f70eda33cb783644fc" args="(dwc_otg_hcd_urb_t *urb)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a>* dwc_otg_hcd_qtd_create           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>urb</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function allocates and initializes a QTD. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>urb</em>&nbsp;</td><td>The URB to create a QTD from. Each URB-QTD pair will end up pointing to each other so each pair should have a unique correlation.</td></tr>
+  </table>
+</dl>
+<dl compact><dt><b>Returns:</b></dt><dd>Returns pointer to the newly allocated QTD, or NULL on error. </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__queue_8c-source.html#l00643">643</a> of file <a class="el" href="dwc__otg__hcd__queue_8c-source.html">dwc_otg_hcd_queue.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="9ebb534f604aa8f693da162f32cf1ba4"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_otg_hcd_qtd_init" ref="9ebb534f604aa8f693da162f32cf1ba4" args="(dwc_otg_qtd_t *qtd, dwc_otg_hcd_urb_t *urb)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_hcd_qtd_init           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>qtd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>urb</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Initializes a QTD structure. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>qtd</em>&nbsp;</td><td>The QTD to initialize. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>urb</em>&nbsp;</td><td>The URB to use for initialization. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__queue_8c-source.html#l00661">661</a> of file <a class="el" href="dwc__otg__hcd__queue_8c-source.html">dwc_otg_hcd_queue.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="748ba77769387bfe4295cb10265053f0"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_otg_hcd_qtd_add" ref="748ba77769387bfe4295cb10265053f0" args="(dwc_otg_qtd_t *qtd, dwc_otg_hcd_t *dwc_otg_hcd, dwc_otg_qh_t **qh)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_hcd_qtd_add           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>qtd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> **&nbsp;</td>
+          <td class="paramname"> <em>qh</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function adds a QTD to the QTD-list of a QH. 
+<p>
+It will find the correct QH to place the QTD into. If it does not find a QH, then it will create a new QH. If the QH to which the QTD is added is not currently scheduled, it is placed into the proper schedule based on its EP type.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"><tt>[in]</tt>&nbsp;</td><td valign="top"><em>qtd</em>&nbsp;</td><td>The QTD to add </td></tr>
+    <tr><td valign="top"><tt>[in]</tt>&nbsp;</td><td valign="top"><em>hcd</em>&nbsp;</td><td>The DWC HCD structure </td></tr>
+    <tr><td valign="top"><tt>[out]</tt>&nbsp;</td><td valign="top"><em>qh</em>&nbsp;</td><td>out parameter to return queue head</td></tr>
+  </table>
+</dl>
+<dl compact><dt><b>Returns:</b></dt><dd>0 if successful, negative error code otherwise. </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__queue_8c-source.html#l00698">698</a> of file <a class="el" href="dwc__otg__hcd__queue_8c-source.html">dwc_otg_hcd_queue.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="ad58f04f541929d521f9acde9e465577"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_otg_hcd_qtd_alloc" ref="ad58f04f541929d521f9acde9e465577" args="(void)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static <a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a>* dwc_otg_hcd_qtd_alloc           </td>
+          <td>(</td>
+          <td class="paramtype">void&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [inline, static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Allocates memory for a QTD structure. 
+<p>
+<dl compact><dt><b>Returns:</b></dt><dd>Returns the memory allocate or NULL on error. </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8h-source.html#l00623">623</a> of file <a class="el" href="dwc__otg__hcd_8h-source.html">dwc_otg_hcd.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="34434d836361462c04fb45ba9ab89fb9"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_otg_hcd_qtd_free" ref="34434d836361462c04fb45ba9ab89fb9" args="(dwc_otg_qtd_t *qtd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static void dwc_otg_hcd_qtd_free           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>qtd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [inline, static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Frees the memory for a QTD structure. 
+<p>
+QTD should already be removed from list. <dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>qtd</em>&nbsp;</td><td>QTD to free. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8h-source.html#l00631">631</a> of file <a class="el" href="dwc__otg__hcd_8h-source.html">dwc_otg_hcd.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="2a721977443fb6bd453fbc2e8ae5355d"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_otg_hcd_qtd_remove" ref="2a721977443fb6bd453fbc2e8ae5355d" args="(dwc_otg_hcd_t *hcd, dwc_otg_qtd_t *qtd, dwc_otg_qh_t *qh)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static void dwc_otg_hcd_qtd_remove           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>qtd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>qh</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [inline, static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Removes a QTD from list. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>HCD instance. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>qtd</em>&nbsp;</td><td>QTD to remove from list. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>qh</em>&nbsp;</td><td>QTD belongs to. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8h-source.html#l00641">641</a> of file <a class="el" href="dwc__otg__hcd_8h-source.html">dwc_otg_hcd.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="9b051bad5e81a6b6d74b817c741bfaf3"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_otg_hcd_start_xfer_ddma" ref="9b051bad5e81a6b6d74b817c741bfaf3" args="(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_hcd_start_xfer_ddma           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>qh</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+For Control and Bulk endpoints initializes descriptor list and starts the transfer. 
+<p>
+For Interrupt and Isochronous endpoints initializes descriptor list then updates FrameList, marking appropriate entries as active. In case of Isochronous, the starting descriptor index is calculated based on the scheduled frame, but only on the first transfer descriptor within a session. Then starts the transfer via enabling the channel. For Isochronous endpoint the channel is not halted on XferComplete interrupt so remains assigned to the endpoint(QH) until session is done.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD state structure for the DWC OTG controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>qh</em>&nbsp;</td><td>The QH to init.</td></tr>
+  </table>
+</dl>
+<dl compact><dt><b>Returns:</b></dt><dd>0 if successful, negative error code otherwise. </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__ddma_8c-source.html#l00675">675</a> of file <a class="el" href="dwc__otg__hcd__ddma_8c-source.html">dwc_otg_hcd_ddma.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="ca94cde3142ff1121bb0ff9bd44fa762"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_otg_hcd_complete_xfer_ddma" ref="ca94cde3142ff1121bb0ff9bd44fa762" args="(dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_halt_status_e halt_status)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_hcd_complete_xfer_ddma           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__hc.html">dwc_hc_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc_regs</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">dwc_otg_halt_status_e&nbsp;</td>
+          <td class="paramname"> <em>halt_status</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function is called from interrupt handlers. 
+<p>
+Scans the descriptor list, updates URB's status and calls completion routine for the URB if it's done. Releases the channel to be used by other transfers. In case of Isochronous endpoint the channel is not halted until the end of the session, i.e. QTD list is empty. If periodic channel released the FrameList is updated accordingly.<p>
+Calls transaction selection routines to activate pending transfers.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD state structure for the DWC OTG controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>hc</em>&nbsp;</td><td>Host channel, the transfer is completed on. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>hc_regs</em>&nbsp;</td><td>Host channel registers. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>halt_status</em>&nbsp;</td><td>Reason the channel is being halted, or just XferComplete for isochronous transfer </td></tr>
+  </table>
+</dl>
+
+<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000015">Todo:</a></b></dt><dd>Consider the case when period exceeds FrameList size. Frame Rollover interrupt should be used. </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__ddma_8c-source.html#l01042">1042</a> of file <a class="el" href="dwc__otg__hcd__ddma_8c-source.html">dwc_otg_hcd_ddma.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="1c5498d173c5461865a5042789927ed1"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_otg_hcd_qh_init_ddma" ref="1c5498d173c5461865a5042789927ed1" args="(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_hcd_qh_init_ddma           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>qh</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Initializes a QH structure's Descriptor DMA related members. 
+<p>
+Allocates memory for descriptor list. On first periodic QH, allocates memory for FrameList and enables periodic scheduling.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD state structure for the DWC OTG controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>qh</em>&nbsp;</td><td>The QH to init.</td></tr>
+  </table>
+</dl>
+<dl compact><dt><b>Returns:</b></dt><dd>0 if successful, negative error code otherwise. </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__ddma_8c-source.html#l00294">294</a> of file <a class="el" href="dwc__otg__hcd__ddma_8c-source.html">dwc_otg_hcd_ddma.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="78738afd0ca62e394753f1cf196476c9"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_otg_hcd_qh_free_ddma" ref="78738afd0ca62e394753f1cf196476c9" args="(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_hcd_qh_free_ddma           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>qh</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Frees descriptor list memory associated with the QH. 
+<p>
+If QH is periodic and the last, frees FrameList memory and disables periodic scheduling.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD state structure for the DWC OTG controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>qh</em>&nbsp;</td><td>The QH to init. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__ddma_8c-source.html#l00327">327</a> of file <a class="el" href="dwc__otg__hcd__ddma_8c-source.html">dwc_otg_hcd_ddma.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="02aa5e9853fcc705b9b5c839a249e2f8"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_frame_num_le" ref="02aa5e9853fcc705b9b5c839a249e2f8" args="(uint16_t frame1, uint16_t frame2)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static int dwc_frame_num_le           </td>
+          <td>(</td>
+          <td class="paramtype">uint16_t&nbsp;</td>
+          <td class="paramname"> <em>frame1</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint16_t&nbsp;</td>
+          <td class="paramname"> <em>frame2</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [inline, static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Returns true if _frame1 is less than or equal to _frame2. 
+<p>
+The comparison is done modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the frame number when the max frame number is reached. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8h-source.html#l00708">708</a> of file <a class="el" href="dwc__otg__hcd_8h-source.html">dwc_otg_hcd.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="98e0d4310430b84fa660ab5f6e7c24b9"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_frame_num_gt" ref="98e0d4310430b84fa660ab5f6e7c24b9" args="(uint16_t frame1, uint16_t frame2)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static int dwc_frame_num_gt           </td>
+          <td>(</td>
+          <td class="paramtype">uint16_t&nbsp;</td>
+          <td class="paramname"> <em>frame1</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint16_t&nbsp;</td>
+          <td class="paramname"> <em>frame2</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [inline, static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Returns true if _frame1 is greater than _frame2. 
+<p>
+The comparison is done modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the frame number when the max frame number is reached. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8h-source.html#l00719">719</a> of file <a class="el" href="dwc__otg__hcd_8h-source.html">dwc_otg_hcd.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="cb175759a6b2cd291eedc276c022b500"></a><!-- doxytag: member="dwc_otg_hcd.h::dwc_frame_num_inc" ref="cb175759a6b2cd291eedc276c022b500" args="(uint16_t frame, uint16_t inc)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static uint16_t dwc_frame_num_inc           </td>
+          <td>(</td>
+          <td class="paramtype">uint16_t&nbsp;</td>
+          <td class="paramname"> <em>frame</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint16_t&nbsp;</td>
+          <td class="paramname"> <em>inc</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [inline, static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Increments _frame by the amount specified by _inc. 
+<p>
+The addition is done modulo DWC_HFNUM_MAX_FRNUM. Returns the incremented value. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8h-source.html#l00730">730</a> of file <a class="el" href="dwc__otg__hcd_8h-source.html">dwc_otg_hcd.h</a>.
+</div>
+</div><p>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__ddma_8c-source.html b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__ddma_8c-source.html
new file mode 100644
index 000000000000..261dc561267b
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__ddma_8c-source.html
@@ -0,0 +1,1070 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd_ddma.c Source File</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<h1>dwc_otg_hcd_ddma.c</h1><a href="dwc__otg__hcd__ddma_8c.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">/*==========================================================================</span>
+<a name="l00002"></a>00002 <span class="comment"> * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_ddma.c $</span>
+<a name="l00003"></a>00003 <span class="comment"> * $Revision: #2 $</span>
+<a name="l00004"></a>00004 <span class="comment"> * $Date: 2009/04/21 $</span>
+<a name="l00005"></a>00005 <span class="comment"> * $Change: 1237473 $</span>
+<a name="l00006"></a>00006 <span class="comment"> *</span>
+<a name="l00007"></a>00007 <span class="comment"> * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,</span>
+<a name="l00008"></a>00008 <span class="comment"> * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless</span>
+<a name="l00009"></a>00009 <span class="comment"> * otherwise expressly agreed to in writing between Synopsys and you.</span>
+<a name="l00010"></a>00010 <span class="comment"> *</span>
+<a name="l00011"></a>00011 <span class="comment"> * The Software IS NOT an item of Licensed Software or Licensed Product under</span>
+<a name="l00012"></a>00012 <span class="comment"> * any End User Software License Agreement or Agreement for Licensed Product</span>
+<a name="l00013"></a>00013 <span class="comment"> * with Synopsys or any supplement thereto. You are permitted to use and</span>
+<a name="l00014"></a>00014 <span class="comment"> * redistribute this Software in source and binary forms, with or without</span>
+<a name="l00015"></a>00015 <span class="comment"> * modification, provided that redistributions of source code must retain this</span>
+<a name="l00016"></a>00016 <span class="comment"> * notice. You may not view, use, disclose, copy or distribute this file or</span>
+<a name="l00017"></a>00017 <span class="comment"> * any information contained herein except pursuant to this license grant from</span>
+<a name="l00018"></a>00018 <span class="comment"> * Synopsys. If you do not agree with this notice, including the disclaimer</span>
+<a name="l00019"></a>00019 <span class="comment"> * below, then you are not authorized to use the Software.</span>
+<a name="l00020"></a>00020 <span class="comment"> *</span>
+<a name="l00021"></a>00021 <span class="comment"> * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS</span>
+<a name="l00022"></a>00022 <span class="comment"> * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE</span>
+<a name="l00023"></a>00023 <span class="comment"> * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE</span>
+<a name="l00024"></a>00024 <span class="comment"> * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,</span>
+<a name="l00025"></a>00025 <span class="comment"> * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES</span>
+<a name="l00026"></a>00026 <span class="comment"> * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR</span>
+<a name="l00027"></a>00027 <span class="comment"> * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER</span>
+<a name="l00028"></a>00028 <span class="comment"> * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT</span>
+<a name="l00029"></a>00029 <span class="comment"> * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY</span>
+<a name="l00030"></a>00030 <span class="comment"> * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH</span>
+<a name="l00031"></a>00031 <span class="comment"> * DAMAGE.</span>
+<a name="l00032"></a>00032 <span class="comment"> * ========================================================================== */</span>
+<a name="l00033"></a>00033 <span class="preprocessor">#ifndef DWC_DEVICE_ONLY</span>
+<a name="l00034"></a>00034 <span class="preprocessor"></span>
+<a name="l00039"></a>00039 <span class="preprocessor">#include "<a class="code" href="dwc__otg__hcd_8h.html">dwc_otg_hcd.h</a>"</span>
+<a name="l00040"></a>00040 <span class="preprocessor">#include "<a class="code" href="dwc__otg__regs_8h.html">dwc_otg_regs.h</a>"</span>
+<a name="l00041"></a>00041                 
+<a name="l00042"></a>00042                 
+<a name="l00043"></a><a class="code" href="dwc__otg__hcd__ddma_8c.html#cc7af33964cf891f1448376c2a57b309">00043</a> <span class="keyword">static</span> <span class="keyword">inline</span> uint8_t <a class="code" href="dwc__otg__hcd__ddma_8c.html#cc7af33964cf891f1448376c2a57b309">frame_list_idx</a>(uint16_t frame)
+<a name="l00044"></a>00044 {
+<a name="l00045"></a>00045         <span class="keywordflow">return</span> (frame &amp; (<a class="code" href="dwc__otg__regs_8h.html#ff2c2ac58a30e050d647d0f9a256d0bd">MAX_FRLIST_EN_NUM</a> - 1));
+<a name="l00046"></a>00046 }
+<a name="l00047"></a>00047 
+<a name="l00048"></a><a class="code" href="dwc__otg__hcd__ddma_8c.html#c4d25855998839163827c8062bd6fb8b">00048</a> <span class="keyword">static</span> <span class="keyword">inline</span> uint16_t <a class="code" href="dwc__otg__hcd__ddma_8c.html#c4d25855998839163827c8062bd6fb8b">desclist_idx_inc</a>(uint16_t idx, uint16_t inc, uint8_t <a class="code" href="structdwc__hc.html#570b78178975193edb921af1ef36d37b">speed</a>)
+<a name="l00049"></a>00049 {
+<a name="l00050"></a>00050         <span class="keywordflow">return</span> (idx + inc) &amp; 
+<a name="l00051"></a>00051                 (((speed == <a class="code" href="dwc__otg__cil_8h.html#b9dc03c6bc3c1113a935a73cf7021fbe">DWC_OTG_EP_SPEED_HIGH</a>) ? <a class="code" href="dwc__otg__regs_8h.html#b190810b3017403bd58b6346aad4e4ed">MAX_DMA_DESC_NUM_HS_ISOC</a> : <a class="code" href="dwc__otg__regs_8h.html#7f241a3ed7bd5c0d4f1a496c77cbc225">MAX_DMA_DESC_NUM_GENERIC</a>) - 1);
+<a name="l00052"></a>00052 }
+<a name="l00053"></a>00053 
+<a name="l00054"></a><a class="code" href="dwc__otg__hcd__ddma_8c.html#13186d2e949bb38420a7a19a4530a5ad">00054</a> <span class="keyword">static</span> <span class="keyword">inline</span> uint16_t <a class="code" href="dwc__otg__hcd__ddma_8c.html#13186d2e949bb38420a7a19a4530a5ad">desclist_idx_dec</a>(uint16_t idx, uint16_t inc, uint8_t <a class="code" href="structdwc__hc.html#570b78178975193edb921af1ef36d37b">speed</a>)
+<a name="l00055"></a>00055 {
+<a name="l00056"></a>00056         <span class="keywordflow">return</span> (idx - inc) &amp; 
+<a name="l00057"></a>00057                 (((speed == <a class="code" href="dwc__otg__cil_8h.html#b9dc03c6bc3c1113a935a73cf7021fbe">DWC_OTG_EP_SPEED_HIGH</a>) ? <a class="code" href="dwc__otg__regs_8h.html#b190810b3017403bd58b6346aad4e4ed">MAX_DMA_DESC_NUM_HS_ISOC</a> : <a class="code" href="dwc__otg__regs_8h.html#7f241a3ed7bd5c0d4f1a496c77cbc225">MAX_DMA_DESC_NUM_GENERIC</a>) - 1);
+<a name="l00058"></a>00058 }
+<a name="l00059"></a>00059 
+<a name="l00060"></a><a class="code" href="dwc__otg__hcd__ddma_8c.html#b7563972b1dd332dde72911900756d92">00060</a> <span class="keyword">static</span> <span class="keyword">inline</span> uint16_t <a class="code" href="dwc__otg__hcd__ddma_8c.html#b7563972b1dd332dde72911900756d92">max_desc_num</a>(<a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> * <a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>)
+<a name="l00061"></a>00061 {
+<a name="l00062"></a>00062         <span class="keywordflow">return</span> (((<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#98b78ffd8dbc01be44b302e873e73a82">ep_type</a> == UE_ISOCHRONOUS) &amp;&amp; (<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#42459dd91e199807783000b6dc358a7d">dev_speed</a> == <a class="code" href="dwc__otg__cil_8h.html#b9dc03c6bc3c1113a935a73cf7021fbe">DWC_OTG_EP_SPEED_HIGH</a>)) 
+<a name="l00063"></a>00063                                                         ?
+<a name="l00064"></a>00064                                                         <a class="code" href="dwc__otg__regs_8h.html#b190810b3017403bd58b6346aad4e4ed">MAX_DMA_DESC_NUM_HS_ISOC</a>
+<a name="l00065"></a>00065                                                         :
+<a name="l00066"></a>00066                                                         <a class="code" href="dwc__otg__regs_8h.html#7f241a3ed7bd5c0d4f1a496c77cbc225">MAX_DMA_DESC_NUM_GENERIC</a>);
+<a name="l00067"></a>00067 }
+<a name="l00068"></a><a class="code" href="dwc__otg__hcd__ddma_8c.html#357d9fe0cd782a9c88e79f47c3b58384">00068</a> <span class="keyword">static</span> <span class="keyword">inline</span> uint16_t <a class="code" href="dwc__otg__hcd__ddma_8c.html#357d9fe0cd782a9c88e79f47c3b58384">frame_incr_val</a>(<a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> * <a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>)
+<a name="l00069"></a>00069 {
+<a name="l00070"></a>00070         <span class="keywordflow">return</span> ((<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#42459dd91e199807783000b6dc358a7d">dev_speed</a> == <a class="code" href="dwc__otg__cil_8h.html#b9dc03c6bc3c1113a935a73cf7021fbe">DWC_OTG_EP_SPEED_HIGH</a>) 
+<a name="l00071"></a>00071                                                 ? ((<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#cdbce86d457f0ea08e2efedc47c9b315">interval</a> + 8 - 1) / 8)
+<a name="l00072"></a>00072                                                 :
+<a name="l00073"></a>00073                                                 <a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#cdbce86d457f0ea08e2efedc47c9b315">interval</a>);
+<a name="l00074"></a>00074 }
+<a name="l00075"></a>00075 
+<a name="l00076"></a><a class="code" href="dwc__otg__hcd__ddma_8c.html#12375cf094e35d9be3b78da6cf621d01">00076</a> <span class="keyword">static</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd__ddma_8c.html#12375cf094e35d9be3b78da6cf621d01">desc_list_alloc</a>(<a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> * <a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>)
+<a name="l00077"></a>00077 {
+<a name="l00078"></a>00078         <span class="keywordtype">int</span> retval = 0;
+<a name="l00079"></a>00079         
+<a name="l00080"></a>00080         <a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#0e5f35688e54ba97054a1a7576e81150">desc_list</a> = (<a class="code" href="structdwc__otg__host__dma__desc.html">dwc_otg_host_dma_desc_t</a> *) 
+<a name="l00081"></a>00081                                 dwc_dma_alloc(<span class="keyword">sizeof</span>(<a class="code" href="structdwc__otg__host__dma__desc.html">dwc_otg_host_dma_desc_t</a>) * <a class="code" href="dwc__otg__hcd__ddma_8c.html#b7563972b1dd332dde72911900756d92">max_desc_num</a>(<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>),
+<a name="l00082"></a>00082                                               &amp;qh-&gt;desc_list_dma
+<a name="l00083"></a>00083                                               );
+<a name="l00084"></a>00084         
+<a name="l00085"></a>00085         <span class="keywordflow">if</span> (!qh-&gt;desc_list) {
+<a name="l00086"></a>00086                 retval = -DWC_E_NO_MEMORY;
+<a name="l00087"></a>00087                 DWC_ERROR(<span class="stringliteral">"%s: DMA descriptor list allocation failed\n"</span>, __func__);
+<a name="l00088"></a>00088                 
+<a name="l00089"></a>00089         }
+<a name="l00090"></a>00090         
+<a name="l00091"></a>00091         dwc_memset(qh-&gt;desc_list, 0x00, <span class="keyword">sizeof</span>(dwc_otg_host_dma_desc_t) * <a class="code" href="dwc__otg__hcd__ddma_8c.html#b7563972b1dd332dde72911900756d92">max_desc_num</a>(qh));
+<a name="l00092"></a>00092          
+<a name="l00093"></a>00093 
+<a name="l00094"></a>00094         qh-&gt;n_bytes = (uint32_t *) dwc_alloc(<span class="keyword">sizeof</span>(uint32_t) * <a class="code" href="dwc__otg__hcd__ddma_8c.html#b7563972b1dd332dde72911900756d92">max_desc_num</a>(qh));
+<a name="l00095"></a>00095         
+<a name="l00096"></a>00096         <span class="keywordflow">if</span> (!qh-&gt;n_bytes) {
+<a name="l00097"></a>00097                 retval = -DWC_E_NO_MEMORY;
+<a name="l00098"></a>00098                 DWC_ERROR(<span class="stringliteral">"%s: Failed to allocate array for descriptors' size actual values\n"</span>,
+<a name="l00099"></a>00099                           __func__);
+<a name="l00100"></a>00100                 
+<a name="l00101"></a>00101         }       
+<a name="l00102"></a>00102         <span class="keywordflow">return</span> retval;
+<a name="l00103"></a>00103 
+<a name="l00104"></a>00104 }
+<a name="l00105"></a>00105 
+<a name="l00106"></a><a class="code" href="dwc__otg__hcd__ddma_8c.html#c062f46629017bdeeebaf90aa65f610b">00106</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd__ddma_8c.html#c062f46629017bdeeebaf90aa65f610b">desc_list_free</a>(<a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> * <a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>)
+<a name="l00107"></a>00107 {
+<a name="l00108"></a>00108         <span class="keywordflow">if</span>(<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#0e5f35688e54ba97054a1a7576e81150">desc_list</a>) {
+<a name="l00109"></a>00109                 dwc_dma_free(<a class="code" href="dwc__otg__hcd__ddma_8c.html#b7563972b1dd332dde72911900756d92">max_desc_num</a>(<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>), <a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#0e5f35688e54ba97054a1a7576e81150">desc_list</a>, <a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#c31412bb35362e77c697352fd4c3eeaf">desc_list_dma</a>);
+<a name="l00110"></a>00110                 <a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#0e5f35688e54ba97054a1a7576e81150">desc_list</a> = NULL;
+<a name="l00111"></a>00111         }
+<a name="l00112"></a>00112         
+<a name="l00113"></a>00113         <span class="keywordflow">if</span> (<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#6b625d870c7854ccaff5c28fad87482a">n_bytes</a>) {
+<a name="l00114"></a>00114                 dwc_free(<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#6b625d870c7854ccaff5c28fad87482a">n_bytes</a>);
+<a name="l00115"></a>00115                 <a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#6b625d870c7854ccaff5c28fad87482a">n_bytes</a> = NULL;
+<a name="l00116"></a>00116         }
+<a name="l00117"></a>00117 }
+<a name="l00118"></a>00118 
+<a name="l00119"></a><a class="code" href="dwc__otg__hcd__ddma_8c.html#35be74597b6abe7a7d077c2c00d64dc2">00119</a> <span class="keyword">static</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd__ddma_8c.html#35be74597b6abe7a7d077c2c00d64dc2">frame_list_alloc</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd)
+<a name="l00120"></a>00120 {
+<a name="l00121"></a>00121         <span class="keywordtype">int</span> retval = 0; 
+<a name="l00122"></a>00122         <span class="keywordflow">if</span> (hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#77f16d5530f50556ed01fe7f69a135fd">frame_list</a>)
+<a name="l00123"></a>00123                 <span class="keywordflow">return</span> 0;
+<a name="l00124"></a>00124         
+<a name="l00125"></a>00125         hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#77f16d5530f50556ed01fe7f69a135fd">frame_list</a> = dwc_dma_alloc(4 * <a class="code" href="dwc__otg__regs_8h.html#ff2c2ac58a30e050d647d0f9a256d0bd">MAX_FRLIST_EN_NUM</a>,
+<a name="l00126"></a>00126                                         &amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#3421063dcac9d4e200b5d9bbb0508f3d">frame_list_dma</a>
+<a name="l00127"></a>00127                                         );
+<a name="l00128"></a>00128         <span class="keywordflow">if</span> (!hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#77f16d5530f50556ed01fe7f69a135fd">frame_list</a>) {
+<a name="l00129"></a>00129                 retval = -DWC_E_NO_MEMORY;
+<a name="l00130"></a>00130                 DWC_ERROR(<span class="stringliteral">"%s: Frame List allocation failed\n"</span>, __func__);
+<a name="l00131"></a>00131         }
+<a name="l00132"></a>00132         
+<a name="l00133"></a>00133         dwc_memset(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#77f16d5530f50556ed01fe7f69a135fd">frame_list</a>, 0x00, 4 * <a class="code" href="dwc__otg__regs_8h.html#ff2c2ac58a30e050d647d0f9a256d0bd">MAX_FRLIST_EN_NUM</a>);
+<a name="l00134"></a>00134         
+<a name="l00135"></a>00135         <span class="keywordflow">return</span> retval;
+<a name="l00136"></a>00136 }
+<a name="l00137"></a>00137 
+<a name="l00138"></a><a class="code" href="dwc__otg__hcd__ddma_8c.html#01991072b147e11d3b7350a2ee9ee920">00138</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd__ddma_8c.html#01991072b147e11d3b7350a2ee9ee920">frame_list_free</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd)
+<a name="l00139"></a>00139 {
+<a name="l00140"></a>00140         <span class="keywordflow">if</span> (!hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#77f16d5530f50556ed01fe7f69a135fd">frame_list</a>)
+<a name="l00141"></a>00141                 <span class="keywordflow">return</span>;
+<a name="l00142"></a>00142         
+<a name="l00143"></a>00143         dwc_dma_free(4 * <a class="code" href="dwc__otg__regs_8h.html#ff2c2ac58a30e050d647d0f9a256d0bd">MAX_FRLIST_EN_NUM</a>, hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#77f16d5530f50556ed01fe7f69a135fd">frame_list</a>, hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#3421063dcac9d4e200b5d9bbb0508f3d">frame_list_dma</a>);
+<a name="l00144"></a>00144         hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#77f16d5530f50556ed01fe7f69a135fd">frame_list</a> = NULL;
+<a name="l00145"></a>00145 }
+<a name="l00146"></a>00146 
+<a name="l00147"></a><a class="code" href="dwc__otg__hcd__ddma_8c.html#5b78d71512c6143d5a50e31dc3517f6a">00147</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd__ddma_8c.html#5b78d71512c6143d5a50e31dc3517f6a">per_sched_enable</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd, uint16_t fr_list_en)
+<a name="l00148"></a>00148 {
+<a name="l00149"></a>00149                 
+<a name="l00150"></a>00150         <a class="code" href="unionhcfg__data.html">hcfg_data_t</a> hcfg;
+<a name="l00151"></a>00151 
+<a name="l00152"></a>00152         hcfg.<a class="code" href="unionhcfg__data.html#381a253b3a38a7f943dcbb42f7bf10be">d32</a> = dwc_read_reg32(&amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#ff9692c2e10ca2bc7e24f981f25179c2">host_global_regs</a>-&gt;<a class="code" href="structdwc__otg__host__global__regs.html#fd7d93b5ffcb6c7c0a84ef656e6e68de">hcfg</a>);
+<a name="l00153"></a>00153 
+<a name="l00154"></a>00154         <span class="keywordflow">if</span> (hcfg.<a class="code" href="unionhcfg__data.html#45bbb24387d58961dd2b8f2f65689bd7">b</a>.<a class="code" href="unionhcfg__data.html#995a4d09381b8d6ce2c7ac0a6c7f364a">perschedstat</a>) {
+<a name="l00155"></a>00155                 <span class="comment">/* already enabled*/</span>    
+<a name="l00156"></a>00156                 <span class="keywordflow">return</span>;
+<a name="l00157"></a>00157         }
+<a name="l00158"></a>00158         
+<a name="l00159"></a>00159         dwc_write_reg32(&amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#ff9692c2e10ca2bc7e24f981f25179c2">host_global_regs</a>-&gt;<a class="code" href="structdwc__otg__host__global__regs.html#9a6af0a2c19d7b6228c7a40c9078907b">hflbaddr</a>, hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#3421063dcac9d4e200b5d9bbb0508f3d">frame_list_dma</a>);
+<a name="l00160"></a>00160         
+<a name="l00161"></a>00161         <span class="keywordflow">switch</span>(fr_list_en) {
+<a name="l00162"></a>00162         <span class="keywordflow">case</span> 64:
+<a name="l00163"></a>00163             hcfg.<a class="code" href="unionhcfg__data.html#45bbb24387d58961dd2b8f2f65689bd7">b</a>.<a class="code" href="unionhcfg__data.html#11340031265fce764f491b23ae42dda5">frlisten</a> = 3;
+<a name="l00164"></a>00164             <span class="keywordflow">break</span>;
+<a name="l00165"></a>00165         <span class="keywordflow">case</span> 32:
+<a name="l00166"></a>00166             hcfg.<a class="code" href="unionhcfg__data.html#45bbb24387d58961dd2b8f2f65689bd7">b</a>.<a class="code" href="unionhcfg__data.html#11340031265fce764f491b23ae42dda5">frlisten</a> = 2;
+<a name="l00167"></a>00167             <span class="keywordflow">break</span>;
+<a name="l00168"></a>00168         <span class="keywordflow">case</span> 16:
+<a name="l00169"></a>00169             hcfg.<a class="code" href="unionhcfg__data.html#45bbb24387d58961dd2b8f2f65689bd7">b</a>.<a class="code" href="unionhcfg__data.html#11340031265fce764f491b23ae42dda5">frlisten</a> = 1;    
+<a name="l00170"></a>00170         <span class="keywordflow">case</span> 8:
+<a name="l00171"></a>00171             hcfg.<a class="code" href="unionhcfg__data.html#45bbb24387d58961dd2b8f2f65689bd7">b</a>.<a class="code" href="unionhcfg__data.html#11340031265fce764f491b23ae42dda5">frlisten</a> = 0;
+<a name="l00172"></a>00172         <span class="keywordflow">default</span>:
+<a name="l00173"></a>00173             <span class="keywordflow">break</span>;        
+<a name="l00174"></a>00174         }
+<a name="l00175"></a>00175         
+<a name="l00176"></a>00176         hcfg.<a class="code" href="unionhcfg__data.html#45bbb24387d58961dd2b8f2f65689bd7">b</a>.<a class="code" href="unionhcfg__data.html#b49be9c0cbc3df2bb917e1ea96c99c62">perschedena</a> = 1;
+<a name="l00177"></a>00177 
+<a name="l00178"></a>00178         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#e4a050e176c1c4f556da2b276a8c2b37">DBG_HCD</a>, <span class="stringliteral">"Enabling Periodic schedule\n"</span>);
+<a name="l00179"></a>00179         dwc_write_reg32(&amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#ff9692c2e10ca2bc7e24f981f25179c2">host_global_regs</a>-&gt;<a class="code" href="structdwc__otg__host__global__regs.html#fd7d93b5ffcb6c7c0a84ef656e6e68de">hcfg</a>, hcfg.<a class="code" href="unionhcfg__data.html#381a253b3a38a7f943dcbb42f7bf10be">d32</a>);
+<a name="l00180"></a>00180 
+<a name="l00181"></a>00181 }
+<a name="l00182"></a>00182  
+<a name="l00183"></a><a class="code" href="dwc__otg__hcd__ddma_8c.html#693b9fdfeebc77b8132cfaf461b9c8fd">00183</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd__ddma_8c.html#693b9fdfeebc77b8132cfaf461b9c8fd">per_sched_disable</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd)
+<a name="l00184"></a>00184 {
+<a name="l00185"></a>00185         <a class="code" href="unionhcfg__data.html">hcfg_data_t</a> hcfg;
+<a name="l00186"></a>00186 
+<a name="l00187"></a>00187         hcfg.<a class="code" href="unionhcfg__data.html#381a253b3a38a7f943dcbb42f7bf10be">d32</a> = dwc_read_reg32(&amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#ff9692c2e10ca2bc7e24f981f25179c2">host_global_regs</a>-&gt;<a class="code" href="structdwc__otg__host__global__regs.html#fd7d93b5ffcb6c7c0a84ef656e6e68de">hcfg</a>);
+<a name="l00188"></a>00188         
+<a name="l00189"></a>00189         <span class="keywordflow">if</span> (!hcfg.<a class="code" href="unionhcfg__data.html#45bbb24387d58961dd2b8f2f65689bd7">b</a>.<a class="code" href="unionhcfg__data.html#995a4d09381b8d6ce2c7ac0a6c7f364a">perschedstat</a>) {
+<a name="l00190"></a>00190                 <span class="comment">/* already disabled */</span>  
+<a name="l00191"></a>00191                 <span class="keywordflow">return</span>;
+<a name="l00192"></a>00192         }
+<a name="l00193"></a>00193         hcfg.<a class="code" href="unionhcfg__data.html#45bbb24387d58961dd2b8f2f65689bd7">b</a>.<a class="code" href="unionhcfg__data.html#b49be9c0cbc3df2bb917e1ea96c99c62">perschedena</a> = 0;
+<a name="l00194"></a>00194         
+<a name="l00195"></a>00195         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#e4a050e176c1c4f556da2b276a8c2b37">DBG_HCD</a>, <span class="stringliteral">"Disabling Periodic schedule\n"</span>);
+<a name="l00196"></a>00196         dwc_write_reg32(&amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#ff9692c2e10ca2bc7e24f981f25179c2">host_global_regs</a>-&gt;<a class="code" href="structdwc__otg__host__global__regs.html#fd7d93b5ffcb6c7c0a84ef656e6e68de">hcfg</a>, hcfg.<a class="code" href="unionhcfg__data.html#381a253b3a38a7f943dcbb42f7bf10be">d32</a>);
+<a name="l00197"></a>00197 }
+<a name="l00198"></a>00198 
+<a name="l00199"></a>00199 <span class="comment">/* </span>
+<a name="l00200"></a>00200 <span class="comment"> * Activates/Deactivates FrameList entries for the channel </span>
+<a name="l00201"></a>00201 <span class="comment"> * based on endpoint servicing period.</span>
+<a name="l00202"></a>00202 <span class="comment"> */</span>
+<a name="l00203"></a><a class="code" href="dwc__otg__hcd__ddma_8c.html#46c1ec7e2bd2f1177983f6676952cfdf">00203</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd__ddma_8c.html#46c1ec7e2bd2f1177983f6676952cfdf">update_frame_list</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd, <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> * <a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>, uint8_t enable)
+<a name="l00204"></a>00204 {
+<a name="l00205"></a>00205         uint16_t i, j, inc;
+<a name="l00206"></a>00206         <a class="code" href="structdwc__hc.html">dwc_hc_t</a> *hc = <a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#bbdb7d30b60b6c326301f33b35088bb4">channel</a>;
+<a name="l00207"></a>00207         
+<a name="l00208"></a>00208         inc = <a class="code" href="dwc__otg__hcd__ddma_8c.html#357d9fe0cd782a9c88e79f47c3b58384">frame_incr_val</a>(<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>);
+<a name="l00209"></a>00209         
+<a name="l00210"></a>00210         <span class="keywordflow">if</span> (<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#98b78ffd8dbc01be44b302e873e73a82">ep_type</a> == UE_ISOCHRONOUS)
+<a name="l00211"></a>00211                 i = <a class="code" href="dwc__otg__hcd__ddma_8c.html#cc7af33964cf891f1448376c2a57b309">frame_list_idx</a>(<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#977a8032f08e45a9e9bdcd558a6965d3">sched_frame</a>);
+<a name="l00212"></a>00212         <span class="keywordflow">else</span>
+<a name="l00213"></a>00213                 i = 0;
+<a name="l00214"></a>00214 
+<a name="l00215"></a>00215         j = i;
+<a name="l00216"></a>00216         <span class="keywordflow">do</span> {
+<a name="l00217"></a>00217                 <span class="keywordflow">if</span> (enable)
+<a name="l00218"></a>00218                         hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#77f16d5530f50556ed01fe7f69a135fd">frame_list</a>[j] |= (1 &lt;&lt; hc-&gt;<a class="code" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">hc_num</a>);
+<a name="l00219"></a>00219                 <span class="keywordflow">else</span>
+<a name="l00220"></a>00220                         hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#77f16d5530f50556ed01fe7f69a135fd">frame_list</a>[j] &amp;= ~(1 &lt;&lt; hc-&gt;<a class="code" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">hc_num</a>);
+<a name="l00221"></a>00221                 j = (j + inc) &amp; (<a class="code" href="dwc__otg__regs_8h.html#ff2c2ac58a30e050d647d0f9a256d0bd">MAX_FRLIST_EN_NUM</a> - 1);
+<a name="l00222"></a>00222         }
+<a name="l00223"></a>00223         <span class="keywordflow">while</span> (j != i);
+<a name="l00224"></a>00224         
+<a name="l00225"></a>00225         <span class="keywordflow">if</span> (!enable)
+<a name="l00226"></a>00226                 <span class="keywordflow">return</span>;
+<a name="l00227"></a>00227         
+<a name="l00228"></a>00228         hc-&gt;<a class="code" href="structdwc__hc.html#42c5f7b0264ee050df79dc1fe57464b7">schinfo</a> = 0;
+<a name="l00229"></a>00229         <span class="keywordflow">if</span> (<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#bbdb7d30b60b6c326301f33b35088bb4">channel</a>-&gt;<a class="code" href="structdwc__hc.html#570b78178975193edb921af1ef36d37b">speed</a> == <a class="code" href="dwc__otg__cil_8h.html#b9dc03c6bc3c1113a935a73cf7021fbe">DWC_OTG_EP_SPEED_HIGH</a>) {
+<a name="l00230"></a>00230                 j = 1;
+<a name="l00231"></a>00231                 <span class="keywordflow">for</span> (i = 0 ; i &lt; 8 / <a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#cdbce86d457f0ea08e2efedc47c9b315">interval</a>; i++) {
+<a name="l00232"></a>00232                         hc-&gt;<a class="code" href="structdwc__hc.html#42c5f7b0264ee050df79dc1fe57464b7">schinfo</a> |= j;
+<a name="l00233"></a>00233                         j = j &lt;&lt; <a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#cdbce86d457f0ea08e2efedc47c9b315">interval</a>;
+<a name="l00234"></a>00234                 }
+<a name="l00235"></a>00235         }
+<a name="l00236"></a>00236         <span class="keywordflow">else</span> {
+<a name="l00237"></a>00237                 hc-&gt;<a class="code" href="structdwc__hc.html#42c5f7b0264ee050df79dc1fe57464b7">schinfo</a> = 0xff;
+<a name="l00238"></a>00238         }       
+<a name="l00239"></a>00239 }               
+<a name="l00240"></a>00240 <span class="preprocessor">#if 1</span>
+<a name="l00241"></a><a class="code" href="dwc__otg__hcd__ddma_8c.html#9122fdf195fad109710651bbf730ca35">00241</a> <span class="preprocessor"></span><span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd__ddma_8c.html#9122fdf195fad109710651bbf730ca35">dump_frame_list</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd)
+<a name="l00242"></a>00242 {
+<a name="l00243"></a>00243         <span class="keywordtype">int</span> i = 0;
+<a name="l00244"></a>00244         DWC_PRINTF(<span class="stringliteral">"--FRAME LIST (hex) --\n"</span>);          
+<a name="l00245"></a>00245         <span class="keywordflow">for</span> (i = 0; i &lt; <a class="code" href="dwc__otg__regs_8h.html#ff2c2ac58a30e050d647d0f9a256d0bd">MAX_FRLIST_EN_NUM</a>; i++) {
+<a name="l00246"></a>00246                 DWC_PRINTF(<span class="stringliteral">"%x\t"</span>,hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#77f16d5530f50556ed01fe7f69a135fd">frame_list</a>[i]);
+<a name="l00247"></a>00247                 if (!(i % 8) &amp;&amp; i)    
+<a name="l00248"></a>00248                         DWC_PRINTF(<span class="stringliteral">"\n"</span>);
+<a name="l00249"></a>00249         }
+<a name="l00250"></a>00250         DWC_PRINTF(<span class="stringliteral">"\n----\n"</span>);
+<a name="l00251"></a>00251 
+<a name="l00252"></a>00252 }
+<a name="l00253"></a>00253 <span class="preprocessor">#endif</span>
+<a name="l00254"></a>00254 <span class="preprocessor"></span>
+<a name="l00255"></a><a class="code" href="dwc__otg__hcd__ddma_8c.html#060f60ac2e210b5da3bbe379674d2012">00255</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd__ddma_8c.html#060f60ac2e210b5da3bbe379674d2012">release_channel_ddma</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd, <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> * <a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>)
+<a name="l00256"></a>00256 {
+<a name="l00257"></a>00257         <a class="code" href="structdwc__hc.html">dwc_hc_t</a> *hc = <a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#bbdb7d30b60b6c326301f33b35088bb4">channel</a>;
+<a name="l00258"></a>00258         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__hcd_8h.html#4621f3eac09a9fc1363d286bff2de06b">dwc_qh_is_non_per</a>(<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>)) {
+<a name="l00259"></a>00259                 hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e7fff26b5cce7c6c520c89f9e3c75617">non_periodic_channels</a>--;                   
+<a name="l00260"></a>00260         }
+<a name="l00261"></a>00261         <span class="keywordflow">else</span> {
+<a name="l00262"></a>00262                 <a class="code" href="dwc__otg__hcd__ddma_8c.html#46c1ec7e2bd2f1177983f6676952cfdf">update_frame_list</a>(hcd, <a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>, 0);
+<a name="l00263"></a>00263         }
+<a name="l00264"></a>00264         <span class="comment">/* </span>
+<a name="l00265"></a>00265 <span class="comment">         * The condition is added to prevent double cleanup try in case of device</span>
+<a name="l00266"></a>00266 <span class="comment">         * disconnect. See channel cleanup in dwc_otg_hcd_disconnect_cb().</span>
+<a name="l00267"></a>00267 <span class="comment">         */</span>
+<a name="l00268"></a>00268         <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>) {   
+<a name="l00269"></a>00269                 <a class="code" href="dwc__otg__cil_8c.html#f05341f811fba7f6183db66faf50a867">dwc_otg_hc_cleanup</a>(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>, hc);
+<a name="l00270"></a>00270                 DWC_CIRCLEQ_INSERT_TAIL(&amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#1761f2e6b8f6ba82c0e0c4e561813f0f">free_hc_list</a>, hc, hc_list_entry);
+<a name="l00271"></a>00271                 hc-&gt;<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a> = NULL;
+<a name="l00272"></a>00272         }
+<a name="l00273"></a>00273         
+<a name="l00274"></a>00274         <a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#bbdb7d30b60b6c326301f33b35088bb4">channel</a> = NULL;
+<a name="l00275"></a>00275         <a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#6da0f75ffa49c8ffadde42e9618ed8c8">ntd</a> = 0;
+<a name="l00276"></a>00276         
+<a name="l00277"></a>00277         <span class="keywordflow">if</span> (<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#0e5f35688e54ba97054a1a7576e81150">desc_list</a>) {
+<a name="l00278"></a>00278                 dwc_memset(<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#0e5f35688e54ba97054a1a7576e81150">desc_list</a>, 0x00, 
+<a name="l00279"></a>00279                             <span class="keyword">sizeof</span>(<a class="code" href="structdwc__otg__host__dma__desc.html">dwc_otg_host_dma_desc_t</a>) * <a class="code" href="dwc__otg__hcd__ddma_8c.html#b7563972b1dd332dde72911900756d92">max_desc_num</a>(<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>));
+<a name="l00280"></a>00280         }
+<a name="l00281"></a>00281 }
+<a name="l00282"></a>00282 
+<a name="l00294"></a><a class="code" href="dwc__otg__hcd__ddma_8c.html#1c5498d173c5461865a5042789927ed1">00294</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd_8h.html#1c5498d173c5461865a5042789927ed1">dwc_otg_hcd_qh_init_ddma</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd, <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> * <a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>)
+<a name="l00295"></a>00295 {
+<a name="l00296"></a>00296         <span class="keywordtype">int</span> retval = 0;
+<a name="l00297"></a>00297         
+<a name="l00298"></a>00298         <span class="keywordflow">if</span> (<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#8708dd009988ce20b8a8d52a4a96c5a3">do_split</a>) {
+<a name="l00299"></a>00299                 DWC_ERROR(<span class="stringliteral">"SPLIT Transfers are not supported in Descriptor DMA.\n"</span>);
+<a name="l00300"></a>00300                 <span class="keywordflow">return</span> -1;
+<a name="l00301"></a>00301         }
+<a name="l00302"></a>00302 
+<a name="l00303"></a>00303         retval = <a class="code" href="dwc__otg__hcd__ddma_8c.html#12375cf094e35d9be3b78da6cf621d01">desc_list_alloc</a>(<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>);
+<a name="l00304"></a>00304         
+<a name="l00305"></a>00305         <span class="keywordflow">if</span> ((retval == 0) &amp;&amp; (<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#98b78ffd8dbc01be44b302e873e73a82">ep_type</a> == UE_ISOCHRONOUS || <a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#98b78ffd8dbc01be44b302e873e73a82">ep_type</a> == UE_INTERRUPT)) {
+<a name="l00306"></a>00306                 <span class="keywordflow">if</span>(!hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#77f16d5530f50556ed01fe7f69a135fd">frame_list</a>) {
+<a name="l00307"></a>00307                         retval = <a class="code" href="dwc__otg__hcd__ddma_8c.html#35be74597b6abe7a7d077c2c00d64dc2">frame_list_alloc</a>(hcd); 
+<a name="l00308"></a>00308                         <span class="comment">/* Enable periodic schedule on first periodic QH */</span>
+<a name="l00309"></a>00309                         <span class="keywordflow">if</span> (retval == 0)                
+<a name="l00310"></a>00310                                 <a class="code" href="dwc__otg__hcd__ddma_8c.html#5b78d71512c6143d5a50e31dc3517f6a">per_sched_enable</a>(hcd, <a class="code" href="dwc__otg__regs_8h.html#ff2c2ac58a30e050d647d0f9a256d0bd">MAX_FRLIST_EN_NUM</a>);
+<a name="l00311"></a>00311                 }
+<a name="l00312"></a>00312         }
+<a name="l00313"></a>00313         
+<a name="l00314"></a>00314         <a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#6da0f75ffa49c8ffadde42e9618ed8c8">ntd</a> = 0;
+<a name="l00315"></a>00315         
+<a name="l00316"></a>00316         <span class="keywordflow">return</span> retval;
+<a name="l00317"></a>00317 }
+<a name="l00318"></a>00318 
+<a name="l00327"></a><a class="code" href="dwc__otg__hcd__ddma_8c.html#78738afd0ca62e394753f1cf196476c9">00327</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd_8h.html#78738afd0ca62e394753f1cf196476c9">dwc_otg_hcd_qh_free_ddma</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd, <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> * <a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>)
+<a name="l00328"></a>00328 {
+<a name="l00329"></a>00329         <a class="code" href="dwc__otg__hcd__ddma_8c.html#c062f46629017bdeeebaf90aa65f610b">desc_list_free</a>(<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>);
+<a name="l00330"></a>00330 
+<a name="l00331"></a>00331         <span class="comment">/* </span>
+<a name="l00332"></a>00332 <span class="comment">         * Channel still assigned due to some reasons. </span>
+<a name="l00333"></a>00333 <span class="comment">         * Seen on Isoc URB dequeue. Channel halted but no subsequent</span>
+<a name="l00334"></a>00334 <span class="comment">         * ChHalted interrupt to release the channel. Afterwards</span>
+<a name="l00335"></a>00335 <span class="comment">         * when it comes here from endpoint disable routine</span>
+<a name="l00336"></a>00336 <span class="comment">         * channel remains assigned.</span>
+<a name="l00337"></a>00337 <span class="comment">         */</span>
+<a name="l00338"></a>00338         <span class="keywordflow">if</span> (<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#bbdb7d30b60b6c326301f33b35088bb4">channel</a>)
+<a name="l00339"></a>00339                 <a class="code" href="dwc__otg__hcd__ddma_8c.html#060f60ac2e210b5da3bbe379674d2012">release_channel_ddma</a>(hcd, <a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>);
+<a name="l00340"></a>00340 
+<a name="l00341"></a>00341         <span class="keywordflow">if</span> ((<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#98b78ffd8dbc01be44b302e873e73a82">ep_type</a> == UE_ISOCHRONOUS || <a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#98b78ffd8dbc01be44b302e873e73a82">ep_type</a> == UE_INTERRUPT) 
+<a name="l00342"></a>00342                         &amp;&amp; !hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#5754b87bd4644fbb7b90cf843c638f1c">periodic_channels</a> &amp;&amp; hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#77f16d5530f50556ed01fe7f69a135fd">frame_list</a>) {
+<a name="l00343"></a>00343                 
+<a name="l00344"></a>00344                 <a class="code" href="dwc__otg__hcd__ddma_8c.html#693b9fdfeebc77b8132cfaf461b9c8fd">per_sched_disable</a>(hcd); 
+<a name="l00345"></a>00345                 <a class="code" href="dwc__otg__hcd__ddma_8c.html#01991072b147e11d3b7350a2ee9ee920">frame_list_free</a>(hcd);   
+<a name="l00346"></a>00346         }
+<a name="l00347"></a>00347 }       
+<a name="l00348"></a>00348 
+<a name="l00349"></a><a class="code" href="dwc__otg__hcd__ddma_8c.html#42ed718bf245372d90fa8f92fcb69a99">00349</a> <span class="keyword">static</span> uint8_t <a class="code" href="dwc__otg__hcd__ddma_8c.html#42ed718bf245372d90fa8f92fcb69a99">frame_to_desc_idx</a>(<a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> * <a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>, uint16_t frame_idx)
+<a name="l00350"></a>00350 {
+<a name="l00351"></a>00351         <span class="keywordflow">if</span> (<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#42459dd91e199807783000b6dc358a7d">dev_speed</a> == <a class="code" href="dwc__otg__cil_8h.html#b9dc03c6bc3c1113a935a73cf7021fbe">DWC_OTG_EP_SPEED_HIGH</a>) {
+<a name="l00352"></a>00352                 <span class="comment">/* </span>
+<a name="l00353"></a>00353 <span class="comment">                 * Descriptor set(8 descriptors) index</span>
+<a name="l00354"></a>00354 <span class="comment">                 * which is 8-aligned.</span>
+<a name="l00355"></a>00355 <span class="comment">                 */</span>     
+<a name="l00356"></a>00356                 <span class="keywordflow">return</span> (frame_idx &amp; ((<a class="code" href="dwc__otg__regs_8h.html#b190810b3017403bd58b6346aad4e4ed">MAX_DMA_DESC_NUM_HS_ISOC</a> / 8) - 1)) * 8;
+<a name="l00357"></a>00357         }
+<a name="l00358"></a>00358         <span class="keywordflow">else</span> {
+<a name="l00359"></a>00359                 <span class="keywordflow">return</span> (frame_idx &amp; (<a class="code" href="dwc__otg__regs_8h.html#7f241a3ed7bd5c0d4f1a496c77cbc225">MAX_DMA_DESC_NUM_GENERIC</a> - 1));
+<a name="l00360"></a>00360         }       
+<a name="l00361"></a>00361 }
+<a name="l00362"></a>00362 
+<a name="l00363"></a>00363 <span class="comment">/* </span>
+<a name="l00364"></a>00364 <span class="comment"> * Determine starting frame for Isochronous transfer. </span>
+<a name="l00365"></a>00365 <span class="comment"> * Few frames skipped to prevent race condition with HC. </span>
+<a name="l00366"></a>00366 <span class="comment"> */</span>
+<a name="l00367"></a><a class="code" href="dwc__otg__hcd__ddma_8c.html#f9c8d06c646b374cf34925e659142709">00367</a> <span class="keyword">static</span> uint8_t <a class="code" href="dwc__otg__hcd__ddma_8c.html#f9c8d06c646b374cf34925e659142709">calc_starting_frame</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd, <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> * <a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>, uint8_t* skip_frames)
+<a name="l00368"></a>00368 {
+<a name="l00369"></a>00369         uint16_t frame = 0;
+<a name="l00370"></a>00370         hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#f79fefeb7908c0ddf702331253acb292">frame_number</a> = <a class="code" href="dwc__otg__hcd_8c.html#f06514bd6f8c219cc72d1f467a82c056">dwc_otg_hcd_get_frame_number</a>(hcd);
+<a name="l00371"></a>00371         
+<a name="l00372"></a>00372         <span class="comment">/* sched_frame is always frame number(not uFrame) both in FS and HS !! */</span>
+<a name="l00373"></a>00373         
+<a name="l00374"></a>00374         <span class="comment">/* </span>
+<a name="l00375"></a>00375 <span class="comment">         * skip_frames is used to limit activated descriptors number</span>
+<a name="l00376"></a>00376 <span class="comment">         * to avoid the situation when HC services the last activated</span>
+<a name="l00377"></a>00377 <span class="comment">         * descriptor firstly.</span>
+<a name="l00378"></a>00378 <span class="comment">         * Example for FS:</span>
+<a name="l00379"></a>00379 <span class="comment">         * Current frame is 1, scheduled frame is 3. Since HC always fetches the descriptor</span>
+<a name="l00380"></a>00380 <span class="comment">         * corresponding to curr_frame+1, the descriptor corresponding to frame 2</span>
+<a name="l00381"></a>00381 <span class="comment">         * will be fetched. If the number of descriptors is max=64 (or greather) the list will</span>
+<a name="l00382"></a>00382 <span class="comment">         * be fully programmed with Active descriptors and it is possible case(rare) that the latest </span>
+<a name="l00383"></a>00383 <span class="comment">         * descriptor(considering rollback) corresponding to frame 2 will be serviced first.</span>
+<a name="l00384"></a>00384 <span class="comment">         * HS case is more probable because, in fact, up to 11 uframes(16 in the code)</span>
+<a name="l00385"></a>00385 <span class="comment">         * may be skipped.</span>
+<a name="l00386"></a>00386 <span class="comment">         */</span>
+<a name="l00387"></a>00387         <span class="keywordflow">if</span> (<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#42459dd91e199807783000b6dc358a7d">dev_speed</a> == <a class="code" href="dwc__otg__cil_8h.html#b9dc03c6bc3c1113a935a73cf7021fbe">DWC_OTG_EP_SPEED_HIGH</a>) {
+<a name="l00388"></a>00388                 <span class="comment">/* </span>
+<a name="l00389"></a>00389 <span class="comment">                 * Consider uframe counter also, to start xfer asap.</span>
+<a name="l00390"></a>00390 <span class="comment">                 * If half of the frame elapsed skip 2 frames otherwise</span>
+<a name="l00391"></a>00391 <span class="comment">                 * just 1 frame. </span>
+<a name="l00392"></a>00392 <span class="comment">                 * Starting descriptor index must be 8-aligned, so</span>
+<a name="l00393"></a>00393 <span class="comment">                 * if the current frame is near to complete the next one</span>
+<a name="l00394"></a>00394 <span class="comment">                 * is skipped as well.</span>
+<a name="l00395"></a>00395 <span class="comment">                 */</span>
+<a name="l00396"></a>00396                         
+<a name="l00397"></a>00397                 <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__hcd_8h.html#62ca1eeef0a58428b2a105092290c0a4">dwc_micro_frame_num</a>(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#f79fefeb7908c0ddf702331253acb292">frame_number</a>)  &gt;= 5) {
+<a name="l00398"></a>00398                         *skip_frames = 2 * 8;
+<a name="l00399"></a>00399                         frame = <a class="code" href="dwc__otg__hcd_8h.html#cb175759a6b2cd291eedc276c022b500">dwc_frame_num_inc</a>(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#f79fefeb7908c0ddf702331253acb292">frame_number</a>, *skip_frames);
+<a name="l00400"></a>00400                 }       
+<a name="l00401"></a>00401                 <span class="keywordflow">else</span> {
+<a name="l00402"></a>00402                         *skip_frames = 1 * 8;
+<a name="l00403"></a>00403                         frame = <a class="code" href="dwc__otg__hcd_8h.html#cb175759a6b2cd291eedc276c022b500">dwc_frame_num_inc</a>(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#f79fefeb7908c0ddf702331253acb292">frame_number</a>, *skip_frames);
+<a name="l00404"></a>00404                 }       
+<a name="l00405"></a>00405                                  
+<a name="l00406"></a>00406                 frame = <a class="code" href="dwc__otg__hcd_8h.html#d6248403619d099d04320cb1b7c7ee99">dwc_full_frame_num</a>(frame); 
+<a name="l00407"></a>00407         } <span class="keywordflow">else</span> {
+<a name="l00408"></a>00408                 <span class="comment">/* </span>
+<a name="l00409"></a>00409 <span class="comment">                 * Two frames are skipped for FS - the current and the next.</span>
+<a name="l00410"></a>00410 <span class="comment">                 * But for descriptor programming, 1 frame(descriptor) is enough,</span>
+<a name="l00411"></a>00411 <span class="comment">                 * see example above.</span>
+<a name="l00412"></a>00412 <span class="comment">                 */</span>
+<a name="l00413"></a>00413                 *skip_frames = 1;        
+<a name="l00414"></a>00414                 frame = <a class="code" href="dwc__otg__hcd_8h.html#cb175759a6b2cd291eedc276c022b500">dwc_frame_num_inc</a>(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#f79fefeb7908c0ddf702331253acb292">frame_number</a>, 2);
+<a name="l00415"></a>00415         }
+<a name="l00416"></a>00416         
+<a name="l00417"></a>00417         <span class="keywordflow">return</span> frame;
+<a name="l00418"></a>00418 }
+<a name="l00419"></a>00419 <span class="comment">/* </span>
+<a name="l00420"></a>00420 <span class="comment"> * Calculate initial descriptor index for isochronous transfer</span>
+<a name="l00421"></a>00421 <span class="comment"> * based on scheduled frame. </span>
+<a name="l00422"></a>00422 <span class="comment"> */</span>
+<a name="l00423"></a><a class="code" href="dwc__otg__hcd__ddma_8c.html#fc5f584eb735a394a794a3022939638a">00423</a> <span class="keyword">static</span> uint8_t <a class="code" href="dwc__otg__hcd__ddma_8c.html#fc5f584eb735a394a794a3022939638a">recalc_initial_desc_idx</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd, <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> * <a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>)
+<a name="l00424"></a>00424 {
+<a name="l00425"></a>00425         uint16_t frame = 0, fr_idx, fr_idx_tmp; 
+<a name="l00426"></a>00426         uint8_t skip_frames = 0 ;
+<a name="l00427"></a>00427         <span class="comment">/* </span>
+<a name="l00428"></a>00428 <span class="comment">         * With current ISOC processing algorithm the channel is being</span>
+<a name="l00429"></a>00429 <span class="comment">         * released when no more QTDs in the list(qh-&gt;ntd == 0).</span>
+<a name="l00430"></a>00430 <span class="comment">         * Thus this function is called only when qh-&gt;ntd == 0 and qh-&gt;channel == 0. </span>
+<a name="l00431"></a>00431 <span class="comment">         *</span>
+<a name="l00432"></a>00432 <span class="comment">         * So qh-&gt;channel != NULL branch is not used and just not removed from the</span>
+<a name="l00433"></a>00433 <span class="comment">         * source file. It is required for another possible approach which is,</span>
+<a name="l00434"></a>00434 <span class="comment">         * do not disable and release the channel when ISOC session completed, </span>
+<a name="l00435"></a>00435 <span class="comment">         * just move QH to inactive schedule until new QTD arrives. </span>
+<a name="l00436"></a>00436 <span class="comment">         * On new QTD, the QH moved back to 'ready' schedule,</span>
+<a name="l00437"></a>00437 <span class="comment">         * starting frame and therefore starting desc_index are recalculated.</span>
+<a name="l00438"></a>00438 <span class="comment">         * In this case channel is released only on ep_disable.</span>
+<a name="l00439"></a>00439 <span class="comment">         */</span>
+<a name="l00440"></a>00440          
+<a name="l00441"></a>00441         <span class="comment">/* Calculate starting descriptor index. For INTERRUPT endpoint it is always 0. */</span>
+<a name="l00442"></a>00442         <span class="keywordflow">if</span> (<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#bbdb7d30b60b6c326301f33b35088bb4">channel</a>) {
+<a name="l00443"></a>00443                 frame = <a class="code" href="dwc__otg__hcd__ddma_8c.html#f9c8d06c646b374cf34925e659142709">calc_starting_frame</a>(hcd, <a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>, &amp;skip_frames);     
+<a name="l00444"></a>00444                 <span class="comment">/* </span>
+<a name="l00445"></a>00445 <span class="comment">                 * Calculate initial descriptor index based on FrameList current bitmap</span>
+<a name="l00446"></a>00446 <span class="comment">                 * and servicing period.</span>
+<a name="l00447"></a>00447 <span class="comment">                 */</span>
+<a name="l00448"></a>00448                 fr_idx_tmp = <a class="code" href="dwc__otg__hcd__ddma_8c.html#cc7af33964cf891f1448376c2a57b309">frame_list_idx</a>(frame);
+<a name="l00449"></a>00449                 fr_idx = (<a class="code" href="dwc__otg__regs_8h.html#ff2c2ac58a30e050d647d0f9a256d0bd">MAX_FRLIST_EN_NUM</a> + <a class="code" href="dwc__otg__hcd__ddma_8c.html#cc7af33964cf891f1448376c2a57b309">frame_list_idx</a>(<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#977a8032f08e45a9e9bdcd558a6965d3">sched_frame</a>) - fr_idx_tmp) 
+<a name="l00450"></a>00450                                 % <a class="code" href="dwc__otg__hcd__ddma_8c.html#357d9fe0cd782a9c88e79f47c3b58384">frame_incr_val</a>(<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>);
+<a name="l00451"></a>00451                 fr_idx = (fr_idx + fr_idx_tmp) % <a class="code" href="dwc__otg__regs_8h.html#ff2c2ac58a30e050d647d0f9a256d0bd">MAX_FRLIST_EN_NUM</a>;
+<a name="l00452"></a>00452         }
+<a name="l00453"></a>00453         <span class="keywordflow">else</span> {
+<a name="l00454"></a>00454                 <a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#977a8032f08e45a9e9bdcd558a6965d3">sched_frame</a> = <a class="code" href="dwc__otg__hcd__ddma_8c.html#f9c8d06c646b374cf34925e659142709">calc_starting_frame</a>(hcd, <a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>, &amp;skip_frames);   
+<a name="l00455"></a>00455                 fr_idx = <a class="code" href="dwc__otg__hcd__ddma_8c.html#cc7af33964cf891f1448376c2a57b309">frame_list_idx</a>(<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#977a8032f08e45a9e9bdcd558a6965d3">sched_frame</a>);
+<a name="l00456"></a>00456         }
+<a name="l00457"></a>00457         
+<a name="l00458"></a>00458         <a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#3b20e91c00b1de8d42612a8b1250b403">td_first</a> = <a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#9bd6dc808af3f1cab76ae7819af479f9">td_last</a> =  <a class="code" href="dwc__otg__hcd__ddma_8c.html#42ed718bf245372d90fa8f92fcb69a99">frame_to_desc_idx</a>(<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>, fr_idx);
+<a name="l00459"></a>00459         
+<a name="l00460"></a>00460         <span class="keywordflow">return</span> skip_frames;
+<a name="l00461"></a>00461 }
+<a name="l00462"></a>00462  
+<a name="l00463"></a><a class="code" href="dwc__otg__hcd__ddma_8c.html#7aed1ace42f0421b376041d8831c9a74">00463</a> <span class="preprocessor">#define ISOC_URB_GIVEBACK_ASAP</span>
+<a name="l00464"></a>00464 <span class="preprocessor"></span> 
+<a name="l00465"></a><a class="code" href="dwc__otg__hcd__ddma_8c.html#cf56bce31ec5dfcc2a36047c0c648784">00465</a> <span class="preprocessor">#define MAX_ISOC_XFER_SIZE_FS 1023</span>
+<a name="l00466"></a><a class="code" href="dwc__otg__hcd__ddma_8c.html#06012eeeca2d17ee7ea304b381928c4a">00466</a> <span class="preprocessor"></span><span class="preprocessor">#define MAX_ISOC_XFER_SIZE_HS 3072</span>
+<a name="l00467"></a><a class="code" href="dwc__otg__hcd__ddma_8c.html#1f389f323086b2c2697f2ab56062ead6">00467</a> <span class="preprocessor"></span><span class="preprocessor">#define DESCNUM_THRESHOLD 4</span>
+<a name="l00468"></a>00468 <span class="preprocessor"></span>
+<a name="l00469"></a><a class="code" href="dwc__otg__hcd__ddma_8c.html#f2bad2e76275e230f83be94c21a0bd75">00469</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd__ddma_8c.html#f2bad2e76275e230f83be94c21a0bd75">init_isoc_dma_desc</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd, <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> * <a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>, uint8_t skip_frames)
+<a name="l00470"></a>00470 {
+<a name="l00471"></a>00471         <span class="keyword">struct </span><a class="code" href="structdwc__otg__hcd__iso__packet__desc.html">dwc_otg_hcd_iso_packet_desc</a> *frame_desc;
+<a name="l00472"></a>00472         <a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *qtd;
+<a name="l00473"></a>00473         <a class="code" href="structdwc__otg__host__dma__desc.html">dwc_otg_host_dma_desc_t</a> *dma_desc;
+<a name="l00474"></a>00474         uint16_t idx, inc, n_desc, ntd_max, max_xfer_size;
+<a name="l00475"></a>00475         
+<a name="l00476"></a>00476         idx = qh-&gt;<a class="code" href="structdwc__otg__qh.html#9bd6dc808af3f1cab76ae7819af479f9">td_last</a>;
+<a name="l00477"></a>00477         inc = qh-&gt;<a class="code" href="structdwc__otg__qh.html#cdbce86d457f0ea08e2efedc47c9b315">interval</a>;
+<a name="l00478"></a>00478         n_desc = 0;
+<a name="l00479"></a>00479         
+<a name="l00480"></a>00480         ntd_max = (<a class="code" href="dwc__otg__hcd__ddma_8c.html#b7563972b1dd332dde72911900756d92">max_desc_num</a>(qh) + qh-&gt;<a class="code" href="structdwc__otg__qh.html#cdbce86d457f0ea08e2efedc47c9b315">interval</a> - 1) / qh-&gt;<a class="code" href="structdwc__otg__qh.html#cdbce86d457f0ea08e2efedc47c9b315">interval</a>;
+<a name="l00481"></a>00481         if (skip_frames &amp;&amp; !qh-&gt;<a class="code" href="structdwc__otg__qh.html#bbdb7d30b60b6c326301f33b35088bb4">channel</a>)
+<a name="l00482"></a>00482                 ntd_max = ntd_max - skip_frames / qh-&gt;<a class="code" href="structdwc__otg__qh.html#cdbce86d457f0ea08e2efedc47c9b315">interval</a>; 
+<a name="l00483"></a>00483         
+<a name="l00484"></a>00484         max_xfer_size = (qh-&gt;<a class="code" href="structdwc__otg__qh.html#42459dd91e199807783000b6dc358a7d">dev_speed</a> == <a class="code" href="dwc__otg__cil_8h.html#b9dc03c6bc3c1113a935a73cf7021fbe">DWC_OTG_EP_SPEED_HIGH</a>) ? <a class="code" href="dwc__otg__hcd__ddma_8c.html#06012eeeca2d17ee7ea304b381928c4a">MAX_ISOC_XFER_SIZE_HS</a> 
+<a name="l00485"></a>00485                                                                  : <a class="code" href="dwc__otg__hcd__ddma_8c.html#cf56bce31ec5dfcc2a36047c0c648784">MAX_ISOC_XFER_SIZE_FS</a>;
+<a name="l00486"></a>00486                         
+<a name="l00487"></a>00487         DWC_CIRCLEQ_FOREACH(qtd, &amp;qh-&gt;<a class="code" href="structdwc__otg__qh.html#9567d266da8e796d3467fb16ae867f8e">qtd_list</a>, qtd_list_entry) {
+<a name="l00488"></a>00488                 <span class="keywordflow">while</span> ((qh-&gt;<a class="code" href="structdwc__otg__qh.html#6da0f75ffa49c8ffadde42e9618ed8c8">ntd</a> &lt; ntd_max) &amp;&amp; (qtd-&gt;isoc_frame_index_last &lt; qtd-&gt;urb-&gt;packet_count)) {
+<a name="l00489"></a>00489                                 
+<a name="l00490"></a>00490                         dma_desc = &amp;qh-&gt;<a class="code" href="structdwc__otg__qh.html#0e5f35688e54ba97054a1a7576e81150">desc_list</a>[idx];
+<a name="l00491"></a>00491                         dwc_memset(dma_desc, 0x00, <span class="keyword">sizeof</span>(<a class="code" href="structdwc__otg__host__dma__desc.html">dwc_otg_host_dma_desc_t</a>));
+<a name="l00492"></a>00492 
+<a name="l00493"></a>00493                         frame_desc = &amp;qtd-&gt;urb-&gt;iso_descs[qtd-&gt;isoc_frame_index_last];
+<a name="l00494"></a>00494                         
+<a name="l00495"></a>00495                         <span class="keywordflow">if</span> (frame_desc-&gt;<a class="code" href="structdwc__otg__hcd__iso__packet__desc.html#8392d21b820df0181f4e6dca91234543">length</a> &gt; max_xfer_size)
+<a name="l00496"></a>00496                                 qh-&gt;<a class="code" href="structdwc__otg__qh.html#6b625d870c7854ccaff5c28fad87482a">n_bytes</a>[idx] = max_xfer_size;
+<a name="l00497"></a>00497                         <span class="keywordflow">else</span>
+<a name="l00498"></a>00498                                 qh-&gt;<a class="code" href="structdwc__otg__qh.html#6b625d870c7854ccaff5c28fad87482a">n_bytes</a>[idx] = frame_desc-&gt;<a class="code" href="structdwc__otg__hcd__iso__packet__desc.html#8392d21b820df0181f4e6dca91234543">length</a>;
+<a name="l00499"></a>00499                         dma_desc-&gt;<a class="code" href="structdwc__otg__host__dma__desc.html#1b73b25e9fca51dd00fa0607d57d9e3f">status</a>.<a class="code" href="unionhost__dma__desc__sts.html#e16a70bba7e2e196189573323c2dbe1c">b_isoc</a>.<a class="code" href="unionhost__dma__desc__sts.html#a8f68a8a5c22c3c1b530400c23083892">n_bytes</a> = qh-&gt;<a class="code" href="structdwc__otg__qh.html#6b625d870c7854ccaff5c28fad87482a">n_bytes</a>[idx];
+<a name="l00500"></a>00500                         dma_desc-&gt;<a class="code" href="structdwc__otg__host__dma__desc.html#1b73b25e9fca51dd00fa0607d57d9e3f">status</a>.<a class="code" href="unionhost__dma__desc__sts.html#e16a70bba7e2e196189573323c2dbe1c">b_isoc</a>.<a class="code" href="unionhost__dma__desc__sts.html#1c4cf70718c94a1a847e52d4dd65cbb0">a</a> = 1;
+<a name="l00501"></a>00501                         
+<a name="l00502"></a>00502                         dma_desc-&gt;<a class="code" href="structdwc__otg__host__dma__desc.html#fdc395094e1a1f9bb89c316a96d4b96b">buf</a> = qtd-&gt;urb-&gt;dma + frame_desc-&gt;<a class="code" href="structdwc__otg__hcd__iso__packet__desc.html#246f3d147a22cd295c534253593dca4a">offset</a>;
+<a name="l00503"></a>00503                         
+<a name="l00504"></a>00504                         qh-&gt;<a class="code" href="structdwc__otg__qh.html#6da0f75ffa49c8ffadde42e9618ed8c8">ntd</a>++;
+<a name="l00505"></a>00505 
+<a name="l00506"></a>00506                         qtd-&gt;isoc_frame_index_last++;
+<a name="l00507"></a>00507                         
+<a name="l00508"></a>00508 <span class="preprocessor">                #ifdef  ISOC_URB_GIVEBACK_ASAP</span>
+<a name="l00509"></a>00509 <span class="preprocessor"></span>                        <span class="comment">/* </span>
+<a name="l00510"></a>00510 <span class="comment">                         * Set IOC for each descriptor corresponding to the </span>
+<a name="l00511"></a>00511 <span class="comment">                         * last frame of the URB.</span>
+<a name="l00512"></a>00512 <span class="comment">                         */</span>     
+<a name="l00513"></a>00513                         <span class="keywordflow">if</span> (qtd-&gt;isoc_frame_index_last == qtd-&gt;urb-&gt;packet_count)
+<a name="l00514"></a>00514                                 dma_desc-&gt;<a class="code" href="structdwc__otg__host__dma__desc.html#1b73b25e9fca51dd00fa0607d57d9e3f">status</a>.<a class="code" href="unionhost__dma__desc__sts.html#e16a70bba7e2e196189573323c2dbe1c">b_isoc</a>.<a class="code" href="unionhost__dma__desc__sts.html#2efbb549924afd0deb402af9eda4a272">ioc</a> = 1;
+<a name="l00515"></a>00515                         
+<a name="l00516"></a>00516 <span class="preprocessor">                #endif  </span>
+<a name="l00517"></a>00517 <span class="preprocessor"></span>                        idx = <a class="code" href="dwc__otg__hcd__ddma_8c.html#c4d25855998839163827c8062bd6fb8b">desclist_idx_inc</a>(idx, inc, qh-&gt;<a class="code" href="structdwc__otg__qh.html#42459dd91e199807783000b6dc358a7d">dev_speed</a>);
+<a name="l00518"></a>00518                         n_desc++;
+<a name="l00519"></a>00519                         
+<a name="l00520"></a>00520                 }
+<a name="l00521"></a>00521                 qtd-&gt;in_process = 1;
+<a name="l00522"></a>00522         }
+<a name="l00523"></a>00523         
+<a name="l00524"></a>00524         qh-&gt;<a class="code" href="structdwc__otg__qh.html#9bd6dc808af3f1cab76ae7819af479f9">td_last</a> = idx;
+<a name="l00525"></a>00525         
+<a name="l00526"></a>00526 <span class="preprocessor">#ifdef  ISOC_URB_GIVEBACK_ASAP</span>
+<a name="l00527"></a>00527 <span class="preprocessor"></span>        <span class="comment">/* Set IOC for the last descriptor if descriptor list is full */</span>        
+<a name="l00528"></a>00528         <span class="keywordflow">if</span> (qh-&gt;<a class="code" href="structdwc__otg__qh.html#6da0f75ffa49c8ffadde42e9618ed8c8">ntd</a> == ntd_max) {
+<a name="l00529"></a>00529                 idx = <a class="code" href="dwc__otg__hcd__ddma_8c.html#13186d2e949bb38420a7a19a4530a5ad">desclist_idx_dec</a>(qh-&gt;<a class="code" href="structdwc__otg__qh.html#9bd6dc808af3f1cab76ae7819af479f9">td_last</a>, inc, qh-&gt;<a class="code" href="structdwc__otg__qh.html#42459dd91e199807783000b6dc358a7d">dev_speed</a>);
+<a name="l00530"></a>00530                 qh-&gt;<a class="code" href="structdwc__otg__qh.html#0e5f35688e54ba97054a1a7576e81150">desc_list</a>[idx].<a class="code" href="structdwc__otg__host__dma__desc.html#1b73b25e9fca51dd00fa0607d57d9e3f">status</a>.<a class="code" href="unionhost__dma__desc__sts.html#e16a70bba7e2e196189573323c2dbe1c">b_isoc</a>.<a class="code" href="unionhost__dma__desc__sts.html#2efbb549924afd0deb402af9eda4a272">ioc</a> = 1;
+<a name="l00531"></a>00531         }
+<a name="l00532"></a>00532 <span class="preprocessor">#else   </span>
+<a name="l00533"></a>00533 <span class="preprocessor"></span>        <span class="comment">/* </span>
+<a name="l00534"></a>00534 <span class="comment">         * Set IOC bit only for one descriptor. </span>
+<a name="l00535"></a>00535 <span class="comment">         * Always try to be ahead of HW processing,</span>
+<a name="l00536"></a>00536 <span class="comment">         * i.e. on IOC generation driver activates next descriptors but</span>
+<a name="l00537"></a>00537 <span class="comment">         * core continues to process descriptors followed the one with IOC set.</span>
+<a name="l00538"></a>00538 <span class="comment">         */</span>
+<a name="l00539"></a>00539 
+<a name="l00540"></a>00540         <span class="keywordflow">if</span> (n_desc &gt; <a class="code" href="dwc__otg__hcd__ddma_8c.html#1f389f323086b2c2697f2ab56062ead6">DESCNUM_THRESHOLD</a>) {
+<a name="l00541"></a>00541                 <span class="comment">/* </span>
+<a name="l00542"></a>00542 <span class="comment">                 * Move IOC "up". Required even if there is only one QTD </span>
+<a name="l00543"></a>00543 <span class="comment">                 * in the list, cause QTDs migth continue to be queued,</span>
+<a name="l00544"></a>00544 <span class="comment">                 * but during the activation it was only one queued.</span>
+<a name="l00545"></a>00545 <span class="comment">                 * Actually more than one QTD might be in the list if this function called </span>
+<a name="l00546"></a>00546 <span class="comment">                 * from XferCompletion - QTDs was queued during HW processing of the previous</span>
+<a name="l00547"></a>00547 <span class="comment">                 * descriptor chunk.</span>
+<a name="l00548"></a>00548 <span class="comment">                 */</span>     
+<a name="l00549"></a>00549                 idx = dwc_desclist_idx_dec(idx, inc * ((qh-&gt;<a class="code" href="structdwc__otg__qh.html#6da0f75ffa49c8ffadde42e9618ed8c8">ntd</a> + 1) / 2), qh-&gt;<a class="code" href="structdwc__otg__qh.html#42459dd91e199807783000b6dc358a7d">dev_speed</a>);
+<a name="l00550"></a>00550         }
+<a name="l00551"></a>00551         <span class="keywordflow">else</span> {
+<a name="l00552"></a>00552                 <span class="comment">/* </span>
+<a name="l00553"></a>00553 <span class="comment">                 * Set the IOC for the latest descriptor</span>
+<a name="l00554"></a>00554 <span class="comment">                 * if either number of descriptor is not greather than threshold</span>
+<a name="l00555"></a>00555 <span class="comment">                 * or no more new descriptors activated.</span>
+<a name="l00556"></a>00556 <span class="comment">                 */</span>     
+<a name="l00557"></a>00557                 idx = dwc_desclist_idx_dec(qh-&gt;<a class="code" href="structdwc__otg__qh.html#9bd6dc808af3f1cab76ae7819af479f9">td_last</a>, inc, qh-&gt;<a class="code" href="structdwc__otg__qh.html#42459dd91e199807783000b6dc358a7d">dev_speed</a>);
+<a name="l00558"></a>00558         }
+<a name="l00559"></a>00559         
+<a name="l00560"></a>00560         qh-&gt;<a class="code" href="structdwc__otg__qh.html#0e5f35688e54ba97054a1a7576e81150">desc_list</a>[idx].<a class="code" href="structdwc__otg__host__dma__desc.html#1b73b25e9fca51dd00fa0607d57d9e3f">status</a>.<a class="code" href="unionhost__dma__desc__sts.html#e16a70bba7e2e196189573323c2dbe1c">b_isoc</a>.<a class="code" href="unionhost__dma__desc__sts.html#2efbb549924afd0deb402af9eda4a272">ioc</a> = 1;
+<a name="l00561"></a>00561 <span class="preprocessor">#endif</span>
+<a name="l00562"></a>00562 <span class="preprocessor"></span>}
+<a name="l00563"></a>00563 
+<a name="l00564"></a>00564 
+<a name="l00565"></a><a class="code" href="dwc__otg__hcd__ddma_8c.html#f3630ce7f8926de36873d78a1748134f">00565</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd__ddma_8c.html#f3630ce7f8926de36873d78a1748134f">init_non_isoc_dma_desc</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd, <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> * qh)
+<a name="l00566"></a>00566 {
+<a name="l00567"></a>00567 
+<a name="l00568"></a>00568         <a class="code" href="structdwc__hc.html">dwc_hc_t</a> *hc;
+<a name="l00569"></a>00569         <a class="code" href="structdwc__otg__host__dma__desc.html">dwc_otg_host_dma_desc_t</a> *dma_desc;
+<a name="l00570"></a>00570         <a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *qtd;
+<a name="l00571"></a>00571         <span class="keywordtype">int</span>     num_packets, len, n_desc = 0;
+<a name="l00572"></a>00572         
+<a name="l00573"></a>00573         hc =  qh-&gt;<a class="code" href="structdwc__otg__qh.html#bbdb7d30b60b6c326301f33b35088bb4">channel</a>;
+<a name="l00574"></a>00574          
+<a name="l00575"></a>00575         <span class="comment">/* </span>
+<a name="l00576"></a>00576 <span class="comment">         * Start with hc-&gt;xfer_buff initialized in </span>
+<a name="l00577"></a>00577 <span class="comment">         * assign_and_init_hc(), then if SG transfer consists of multiple URBs,</span>
+<a name="l00578"></a>00578 <span class="comment">         * this pointer re-assigned to the buffer of the currently processed QTD.</span>
+<a name="l00579"></a>00579 <span class="comment">         * For non-SG request there is always one QTD active.</span>
+<a name="l00580"></a>00580 <span class="comment">         */</span>
+<a name="l00581"></a>00581         
+<a name="l00582"></a>00582         DWC_CIRCLEQ_FOREACH(qtd, &amp;qh-&gt;<a class="code" href="structdwc__otg__qh.html#9567d266da8e796d3467fb16ae867f8e">qtd_list</a>, qtd_list_entry) {
+<a name="l00583"></a>00583                         
+<a name="l00584"></a>00584                 <span class="keywordflow">if</span> (n_desc) {
+<a name="l00585"></a>00585                         <span class="comment">/* SG request - more than 1 QTDs */</span>
+<a name="l00586"></a>00586                         hc-&gt;<a class="code" href="structdwc__hc.html#9dc781cb9e4bc639765beee37ce76673">xfer_buff</a> = (uint8_t *)qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#7e7767808e8eb9d71de0db00f57553f9">urb</a>-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#4e177a55239e95ae2f6c8b6b913f67fc">dma</a> + qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#7e7767808e8eb9d71de0db00f57553f9">urb</a>-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#742c8a97d3867ab89148eae34e0c73a6">actual_length</a>;
+<a name="l00587"></a>00587                         hc-&gt;<a class="code" href="structdwc__hc.html#ce32fe93214f1686896e924fbf61cac7">xfer_len</a> = qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#7e7767808e8eb9d71de0db00f57553f9">urb</a>-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#dca57de4fdecd894241ce24167206a45">length</a> - qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#7e7767808e8eb9d71de0db00f57553f9">urb</a>-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#742c8a97d3867ab89148eae34e0c73a6">actual_length</a>;
+<a name="l00588"></a>00588                 }
+<a name="l00589"></a>00589 
+<a name="l00590"></a>00590                 qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#ef3021e617cf1f448bd23b1f7ab3859b">n_desc</a> = 0;
+<a name="l00591"></a>00591                 
+<a name="l00592"></a>00592                 <span class="keywordflow">do</span> {
+<a name="l00593"></a>00593                         dma_desc = &amp;qh-&gt;<a class="code" href="structdwc__otg__qh.html#0e5f35688e54ba97054a1a7576e81150">desc_list</a>[n_desc];
+<a name="l00594"></a>00594                         len = hc-&gt;<a class="code" href="structdwc__hc.html#ce32fe93214f1686896e924fbf61cac7">xfer_len</a>;
+<a name="l00595"></a>00595                         
+<a name="l00596"></a>00596 
+<a name="l00597"></a>00597                         <span class="keywordflow">if</span> (len &gt; <a class="code" href="dwc__otg__regs_8h.html#000f3273fb3033d587107e7eff3c1ff6">MAX_DMA_DESC_SIZE</a>)
+<a name="l00598"></a>00598                                 len = <a class="code" href="dwc__otg__regs_8h.html#000f3273fb3033d587107e7eff3c1ff6">MAX_DMA_DESC_SIZE</a> - hc-&gt;<a class="code" href="structdwc__hc.html#bd88f02eb286ba01d8d1b049e8975ccb">max_packet</a> + 1;
+<a name="l00599"></a>00599                         
+<a name="l00600"></a>00600                         <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#c5088d431f5efc382121f201f5d571aa">ep_is_in</a>) {
+<a name="l00601"></a>00601                                 <span class="keywordflow">if</span> (len &gt; 0) {
+<a name="l00602"></a>00602                                         num_packets = (len + hc-&gt;<a class="code" href="structdwc__hc.html#bd88f02eb286ba01d8d1b049e8975ccb">max_packet</a> - 1) / hc-&gt;<a class="code" href="structdwc__hc.html#bd88f02eb286ba01d8d1b049e8975ccb">max_packet</a>;
+<a name="l00603"></a>00603                                 }
+<a name="l00604"></a>00604                                 <span class="keywordflow">else</span> {
+<a name="l00605"></a>00605                                         <span class="comment">/* Need 1 packet for transfer length of 0. */</span>
+<a name="l00606"></a>00606                                         num_packets = 1;
+<a name="l00607"></a>00607                                 }
+<a name="l00608"></a>00608                                 <span class="comment">/* Always program an integral # of max packets for IN transfers. */</span>
+<a name="l00609"></a>00609                                 len = num_packets * hc-&gt;<a class="code" href="structdwc__hc.html#bd88f02eb286ba01d8d1b049e8975ccb">max_packet</a>;     
+<a name="l00610"></a>00610                         }                               
+<a name="l00611"></a>00611                                 
+<a name="l00612"></a>00612                         dma_desc-&gt;<a class="code" href="structdwc__otg__host__dma__desc.html#1b73b25e9fca51dd00fa0607d57d9e3f">status</a>.<a class="code" href="unionhost__dma__desc__sts.html#a0e53895b927bfa9e322c3a3c0a08b3b">b</a>.<a class="code" href="unionhost__dma__desc__sts.html#a8f68a8a5c22c3c1b530400c23083892">n_bytes</a> = len;
+<a name="l00613"></a>00613                         
+<a name="l00614"></a>00614                         qh-&gt;<a class="code" href="structdwc__otg__qh.html#6b625d870c7854ccaff5c28fad87482a">n_bytes</a>[n_desc] = len;
+<a name="l00615"></a>00615                         
+<a name="l00616"></a>00616 
+<a name="l00617"></a>00617                         <span class="keywordflow">if</span> ((qh-&gt;<a class="code" href="structdwc__otg__qh.html#98b78ffd8dbc01be44b302e873e73a82">ep_type</a> == UE_CONTROL) &amp;&amp; (qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#5189ec9c992974d20477481eaf96d0bb">control_phase</a> == DWC_OTG_CONTROL_SETUP))
+<a name="l00618"></a>00618                                 dma_desc-&gt;<a class="code" href="structdwc__otg__host__dma__desc.html#1b73b25e9fca51dd00fa0607d57d9e3f">status</a>.<a class="code" href="unionhost__dma__desc__sts.html#a0e53895b927bfa9e322c3a3c0a08b3b">b</a>.<a class="code" href="unionhost__dma__desc__sts.html#634060a1b436857e15e8eb8f0d6d000a">sup</a> = 1; <span class="comment">/* Setup Packet */</span>
+<a name="l00619"></a>00619                                 
+<a name="l00620"></a>00620                         dma_desc-&gt;<a class="code" href="structdwc__otg__host__dma__desc.html#1b73b25e9fca51dd00fa0607d57d9e3f">status</a>.<a class="code" href="unionhost__dma__desc__sts.html#a0e53895b927bfa9e322c3a3c0a08b3b">b</a>.<a class="code" href="unionhost__dma__desc__sts.html#1c4cf70718c94a1a847e52d4dd65cbb0">a</a> = 1; <span class="comment">/* Active descriptor */</span>
+<a name="l00621"></a>00621                         
+<a name="l00622"></a>00622                         dma_desc-&gt;<a class="code" href="structdwc__otg__host__dma__desc.html#fdc395094e1a1f9bb89c316a96d4b96b">buf</a> = (uint32_t) hc-&gt;<a class="code" href="structdwc__hc.html#9dc781cb9e4bc639765beee37ce76673">xfer_buff</a>;
+<a name="l00623"></a>00623 
+<a name="l00624"></a>00624                         <span class="comment">/* </span>
+<a name="l00625"></a>00625 <span class="comment">                         * Last descriptor(or single) of IN transfer </span>
+<a name="l00626"></a>00626 <span class="comment">                         * with actual size less than MaxPacket.</span>
+<a name="l00627"></a>00627 <span class="comment">                         */</span>
+<a name="l00628"></a>00628                         if (len &gt; hc-&gt;<a class="code" href="structdwc__hc.html#ce32fe93214f1686896e924fbf61cac7">xfer_len</a>) {
+<a name="l00629"></a>00629                                 hc-&gt;<a class="code" href="structdwc__hc.html#ce32fe93214f1686896e924fbf61cac7">xfer_len</a> = 0;
+<a name="l00630"></a>00630                         }
+<a name="l00631"></a>00631                         <span class="keywordflow">else</span> {
+<a name="l00632"></a>00632                                 hc-&gt;<a class="code" href="structdwc__hc.html#9dc781cb9e4bc639765beee37ce76673">xfer_buff</a> += len;
+<a name="l00633"></a>00633                                 hc-&gt;<a class="code" href="structdwc__hc.html#ce32fe93214f1686896e924fbf61cac7">xfer_len</a> -= len;
+<a name="l00634"></a>00634                         }
+<a name="l00635"></a>00635                         
+<a name="l00636"></a>00636                         qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#ef3021e617cf1f448bd23b1f7ab3859b">n_desc</a>++;
+<a name="l00637"></a>00637                         n_desc++;
+<a name="l00638"></a>00638                 }
+<a name="l00639"></a>00639                 <span class="keywordflow">while</span> ((hc-&gt;<a class="code" href="structdwc__hc.html#ce32fe93214f1686896e924fbf61cac7">xfer_len</a> &gt; 0) &amp;&amp; (n_desc != <a class="code" href="dwc__otg__regs_8h.html#7f241a3ed7bd5c0d4f1a496c77cbc225">MAX_DMA_DESC_NUM_GENERIC</a>));
+<a name="l00640"></a>00640                 
+<a name="l00641"></a>00641 
+<a name="l00642"></a>00642                 qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#c1d73f1d48eeabbdc198ad28c0882bc1">in_process</a> = 1;
+<a name="l00643"></a>00643                 
+<a name="l00644"></a>00644                 <span class="keywordflow">if</span> (n_desc == <a class="code" href="dwc__otg__regs_8h.html#7f241a3ed7bd5c0d4f1a496c77cbc225">MAX_DMA_DESC_NUM_GENERIC</a>)
+<a name="l00645"></a>00645                         <span class="keywordflow">break</span>;
+<a name="l00646"></a>00646         }
+<a name="l00647"></a>00647 
+<a name="l00648"></a>00648         <span class="keywordflow">if</span> (n_desc) {
+<a name="l00649"></a>00649                 <span class="comment">/* Request Transfer Complete interrupt for the last descriptor */</span>
+<a name="l00650"></a>00650                 qh-&gt;<a class="code" href="structdwc__otg__qh.html#0e5f35688e54ba97054a1a7576e81150">desc_list</a>[n_desc-1].<a class="code" href="structdwc__otg__host__dma__desc.html#1b73b25e9fca51dd00fa0607d57d9e3f">status</a>.<a class="code" href="unionhost__dma__desc__sts.html#a0e53895b927bfa9e322c3a3c0a08b3b">b</a>.<a class="code" href="unionhost__dma__desc__sts.html#2efbb549924afd0deb402af9eda4a272">ioc</a> = 1;
+<a name="l00651"></a>00651                 <span class="comment">/* End of List indicator */</span>
+<a name="l00652"></a>00652                 qh-&gt;<a class="code" href="structdwc__otg__qh.html#0e5f35688e54ba97054a1a7576e81150">desc_list</a>[n_desc-1].<a class="code" href="structdwc__otg__host__dma__desc.html#1b73b25e9fca51dd00fa0607d57d9e3f">status</a>.<a class="code" href="unionhost__dma__desc__sts.html#a0e53895b927bfa9e322c3a3c0a08b3b">b</a>.<a class="code" href="unionhost__dma__desc__sts.html#58d670cd305219a32f144a6705e649e3">eol</a> = 1;
+<a name="l00653"></a>00653                 
+<a name="l00654"></a>00654                 hc-&gt;<a class="code" href="structdwc__hc.html#9a3a483b9c4e45d1ec5f475beb6a10a3">ntd</a> = n_desc;
+<a name="l00655"></a>00655         }
+<a name="l00656"></a>00656 }
+<a name="l00657"></a>00657 
+<a name="l00675"></a><a class="code" href="dwc__otg__hcd__ddma_8c.html#9b051bad5e81a6b6d74b817c741bfaf3">00675</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd_8h.html#9b051bad5e81a6b6d74b817c741bfaf3">dwc_otg_hcd_start_xfer_ddma</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd, <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> * qh)
+<a name="l00676"></a>00676 {
+<a name="l00677"></a>00677         <span class="comment">/* Channel is already assigned */</span>
+<a name="l00678"></a>00678         <a class="code" href="structdwc__hc.html">dwc_hc_t</a> *hc = qh-&gt;<a class="code" href="structdwc__otg__qh.html#bbdb7d30b60b6c326301f33b35088bb4">channel</a>;
+<a name="l00679"></a>00679         uint8_t skip_frames = 0;
+<a name="l00680"></a>00680         
+<a name="l00681"></a>00681         <span class="keywordflow">switch</span> (hc-&gt;<a class="code" href="structdwc__hc.html#e6169fbc92e4d79686097742ad646f5c">ep_type</a>) {
+<a name="l00682"></a>00682         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__cil_8h.html#64e5cd756330f5adab79b25cc8067bdc">DWC_OTG_EP_TYPE_CONTROL</a>:
+<a name="l00683"></a>00683         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__cil_8h.html#9b079858cda0b917316ad9161b3881e0">DWC_OTG_EP_TYPE_BULK</a>:
+<a name="l00684"></a>00684                 <a class="code" href="dwc__otg__hcd__ddma_8c.html#f3630ce7f8926de36873d78a1748134f">init_non_isoc_dma_desc</a>(hcd, qh);
+<a name="l00685"></a>00685                 
+<a name="l00686"></a>00686                 <a class="code" href="dwc__otg__cil_8c.html#dbc20e9f9cadbdf4df65db3f82bbb820">dwc_otg_hc_start_transfer_ddma</a>(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>, hc);
+<a name="l00687"></a>00687                 <span class="keywordflow">break</span>;
+<a name="l00688"></a>00688         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__cil_8h.html#1401d1264f88530232cf51ab31cc5347">DWC_OTG_EP_TYPE_INTR</a>:
+<a name="l00689"></a>00689                 <a class="code" href="dwc__otg__hcd__ddma_8c.html#f3630ce7f8926de36873d78a1748134f">init_non_isoc_dma_desc</a>(hcd, qh);
+<a name="l00690"></a>00690                 
+<a name="l00691"></a>00691                 <a class="code" href="dwc__otg__hcd__ddma_8c.html#46c1ec7e2bd2f1177983f6676952cfdf">update_frame_list</a>(hcd, qh, 1);
+<a name="l00692"></a>00692                 
+<a name="l00693"></a>00693                 <a class="code" href="dwc__otg__cil_8c.html#dbc20e9f9cadbdf4df65db3f82bbb820">dwc_otg_hc_start_transfer_ddma</a>(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>, hc);
+<a name="l00694"></a>00694                 <span class="keywordflow">break</span>;
+<a name="l00695"></a>00695         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__cil_8h.html#152a3a5e1433bd2197672f0b5105e7a4">DWC_OTG_EP_TYPE_ISOC</a>:
+<a name="l00696"></a>00696                         
+<a name="l00697"></a>00697                 <span class="keywordflow">if</span>(!qh-&gt;<a class="code" href="structdwc__otg__qh.html#6da0f75ffa49c8ffadde42e9618ed8c8">ntd</a>)
+<a name="l00698"></a>00698                         skip_frames = <a class="code" href="dwc__otg__hcd__ddma_8c.html#fc5f584eb735a394a794a3022939638a">recalc_initial_desc_idx</a>(hcd, qh);
+<a name="l00699"></a>00699                 
+<a name="l00700"></a>00700                 <a class="code" href="dwc__otg__hcd__ddma_8c.html#f2bad2e76275e230f83be94c21a0bd75">init_isoc_dma_desc</a>(hcd, qh, skip_frames);
+<a name="l00701"></a>00701 
+<a name="l00702"></a>00702                 <span class="keywordflow">if</span> (!hc-&gt;<a class="code" href="structdwc__hc.html#78a1cf134604b24bfdedb4f4df9f2c1f">xfer_started</a>) {
+<a name="l00703"></a>00703 
+<a name="l00704"></a>00704                         <a class="code" href="dwc__otg__hcd__ddma_8c.html#46c1ec7e2bd2f1177983f6676952cfdf">update_frame_list</a>(hcd, qh, 1);
+<a name="l00705"></a>00705                 
+<a name="l00706"></a>00706                         <span class="comment">/* </span>
+<a name="l00707"></a>00707 <span class="comment">                         * Always set to max, instead of actual size.</span>
+<a name="l00708"></a>00708 <span class="comment">                         * Otherwise ntd will be changed with </span>
+<a name="l00709"></a>00709 <span class="comment">                         * channel being enabled. Not recommended.</span>
+<a name="l00710"></a>00710 <span class="comment">                         *</span>
+<a name="l00711"></a>00711 <span class="comment">                         */</span>     
+<a name="l00712"></a>00712                         hc-&gt;<a class="code" href="structdwc__hc.html#9a3a483b9c4e45d1ec5f475beb6a10a3">ntd</a> = <a class="code" href="dwc__otg__hcd__ddma_8c.html#b7563972b1dd332dde72911900756d92">max_desc_num</a>(qh);
+<a name="l00713"></a>00713                         <span class="comment">/* Enable channel only once for ISOC */</span> 
+<a name="l00714"></a>00714                         <a class="code" href="dwc__otg__cil_8c.html#dbc20e9f9cadbdf4df65db3f82bbb820">dwc_otg_hc_start_transfer_ddma</a>(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>, hc);
+<a name="l00715"></a>00715                 }
+<a name="l00716"></a>00716                 
+<a name="l00717"></a>00717                 <span class="keywordflow">break</span>;
+<a name="l00718"></a>00718         <span class="keywordflow">default</span>:
+<a name="l00719"></a>00719                 
+<a name="l00720"></a>00720                 <span class="keywordflow">break</span>;
+<a name="l00721"></a>00721         }
+<a name="l00722"></a>00722 }
+<a name="l00723"></a>00723 
+<a name="l00724"></a><a class="code" href="dwc__otg__hcd__ddma_8c.html#aad342d0a6056bbc5645809f24ac8507">00724</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd__ddma_8c.html#aad342d0a6056bbc5645809f24ac8507">complete_isoc_xfer_ddma</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd,
+<a name="l00725"></a>00725                                    <a class="code" href="structdwc__hc.html">dwc_hc_t</a> *hc,
+<a name="l00726"></a>00726                                    <a class="code" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *hc_regs,
+<a name="l00727"></a>00727                                    dwc_otg_halt_status_e halt_status)
+<a name="l00728"></a>00728 {
+<a name="l00729"></a>00729         <span class="keyword">struct </span><a class="code" href="structdwc__otg__hcd__iso__packet__desc.html">dwc_otg_hcd_iso_packet_desc</a>      *frame_desc;            
+<a name="l00730"></a>00730         <a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a>                           *qtd, *qtd_tmp;
+<a name="l00731"></a>00731         <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a>                            *qh;
+<a name="l00732"></a>00732         <a class="code" href="structdwc__otg__host__dma__desc.html">dwc_otg_host_dma_desc_t</a>                 *dma_desc;
+<a name="l00733"></a>00733         uint16_t                                idx, remain;
+<a name="l00734"></a>00734         uint8_t                                 urb_compl;      
+<a name="l00735"></a>00735         
+<a name="l00736"></a>00736         qh = hc-&gt;<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>;
+<a name="l00737"></a>00737         idx = qh-&gt;<a class="code" href="structdwc__otg__qh.html#3b20e91c00b1de8d42612a8b1250b403">td_first</a>;
+<a name="l00738"></a>00738         
+<a name="l00739"></a>00739 
+<a name="l00740"></a>00740         <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#07eca0fa02105ddaa1719387f5558b23">halt_status</a> == DWC_OTG_HC_XFER_URB_DEQUEUE) {
+<a name="l00741"></a>00741                 DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &amp;hc-&gt;<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#9567d266da8e796d3467fb16ae867f8e">qtd_list</a>, qtd_list_entry)
+<a name="l00742"></a>00742                         qtd-&gt;in_process = 0;
+<a name="l00743"></a>00743                 <span class="keywordflow">return</span>; 
+<a name="l00744"></a>00744         }
+<a name="l00745"></a>00745         <span class="keywordflow">else</span> <span class="keywordflow">if</span> ((halt_status == DWC_OTG_HC_XFER_AHB_ERR) || 
+<a name="l00746"></a>00746                         (halt_status == DWC_OTG_HC_XFER_BABBLE_ERR)) {
+<a name="l00747"></a>00747                 <span class="comment">/* </span>
+<a name="l00748"></a>00748 <span class="comment">                 * Channel is halted in these error cases.</span>
+<a name="l00749"></a>00749 <span class="comment">                 * Considered as serious issues.</span>
+<a name="l00750"></a>00750 <span class="comment">                 * Complete all URBs marking all frames as failed, </span>
+<a name="l00751"></a>00751 <span class="comment">                 * irrespective whether some of the descriptors(frames) succeeded or no.</span>
+<a name="l00752"></a>00752 <span class="comment">                 * Pass error code to completion routine as well, to</span>
+<a name="l00753"></a>00753 <span class="comment">                 * update urb-&gt;status, some of class drivers might use it to stop</span>
+<a name="l00754"></a>00754 <span class="comment">                 * queing transfer requests.</span>
+<a name="l00755"></a>00755 <span class="comment">                 */</span>     
+<a name="l00756"></a>00756                 <span class="keywordtype">int</span> err = (halt_status == DWC_OTG_HC_XFER_AHB_ERR) 
+<a name="l00757"></a>00757                                                         ? (-DWC_E_IO)
+<a name="l00758"></a>00758                                                         : (-DWC_E_OVERFLOW);
+<a name="l00759"></a>00759                                                 
+<a name="l00760"></a>00760                 DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &amp;hc-&gt;<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#9567d266da8e796d3467fb16ae867f8e">qtd_list</a>, qtd_list_entry) {
+<a name="l00761"></a>00761                         <span class="keywordflow">for</span>(idx = 0; idx &lt; qtd-&gt;urb-&gt;packet_count; idx++) {
+<a name="l00762"></a>00762                                 frame_desc = &amp;qtd-&gt;urb-&gt;iso_descs[idx];
+<a name="l00763"></a>00763                                 frame_desc-&gt;<a class="code" href="structdwc__otg__hcd__iso__packet__desc.html#d070772c24621c47b49ad21c6acadb94">status</a> = err;
+<a name="l00764"></a>00764                         }
+<a name="l00765"></a>00765                         hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#ffefbd33a59a14b8b46406f5aaeaa2f4">fops</a>-&gt;<a class="code" href="structdwc__otg__hcd__function__ops.html#09a989481103de7468cd46ef61ace0ce">complete</a>(hcd, qtd-&gt;urb-&gt;<a class="code" href="structdwc__otg__hcd.html#c019b908f209d577ccc19d29030926a1">priv</a>, qtd-&gt;urb, err);
+<a name="l00766"></a>00766                         <a class="code" href="dwc__otg__hcd_8h.html#19adb6641f95448a956015b2d69ba96a">dwc_otg_hcd_qtd_remove_and_free</a>(hcd, qtd, qh);
+<a name="l00767"></a>00767                 }
+<a name="l00768"></a>00768                 <span class="keywordflow">return</span>; 
+<a name="l00769"></a>00769         }
+<a name="l00770"></a>00770         
+<a name="l00771"></a>00771         
+<a name="l00772"></a>00772         DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &amp;hc-&gt;<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#9567d266da8e796d3467fb16ae867f8e">qtd_list</a>, qtd_list_entry) {
+<a name="l00773"></a>00773                 
+<a name="l00774"></a>00774                 <span class="keywordflow">if</span> (!qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#c1d73f1d48eeabbdc198ad28c0882bc1">in_process</a>)
+<a name="l00775"></a>00775                     <span class="keywordflow">break</span>;
+<a name="l00776"></a>00776                 
+<a name="l00777"></a>00777                 urb_compl = 0;
+<a name="l00778"></a>00778                 
+<a name="l00779"></a>00779                 <span class="keywordflow">do</span> {
+<a name="l00780"></a>00780 
+<a name="l00781"></a>00781                         dma_desc = &amp;qh-&gt;<a class="code" href="structdwc__otg__qh.html#0e5f35688e54ba97054a1a7576e81150">desc_list</a>[idx];
+<a name="l00782"></a>00782                         
+<a name="l00783"></a>00783                         frame_desc = &amp;qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#7e7767808e8eb9d71de0db00f57553f9">urb</a>-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#ed542f6a2d99dba2f6b71b0d8012ec8a">iso_descs</a>[qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#c67d5f885976d0698f20d113d32b4b30">isoc_frame_index</a>];
+<a name="l00784"></a>00784                         remain = hc-&gt;<a class="code" href="structdwc__hc.html#c5088d431f5efc382121f201f5d571aa">ep_is_in</a> ? dma_desc-&gt;<a class="code" href="structdwc__otg__host__dma__desc.html#1b73b25e9fca51dd00fa0607d57d9e3f">status</a>.<a class="code" href="unionhost__dma__desc__sts.html#e16a70bba7e2e196189573323c2dbe1c">b_isoc</a>.<a class="code" href="unionhost__dma__desc__sts.html#a8f68a8a5c22c3c1b530400c23083892">n_bytes</a> : 0;
+<a name="l00785"></a>00785         
+<a name="l00786"></a>00786                         <span class="keywordflow">if</span> (dma_desc-&gt;<a class="code" href="structdwc__otg__host__dma__desc.html#1b73b25e9fca51dd00fa0607d57d9e3f">status</a>.<a class="code" href="unionhost__dma__desc__sts.html#e16a70bba7e2e196189573323c2dbe1c">b_isoc</a>.<a class="code" href="unionhost__dma__desc__sts.html#828b019082523c4637758bef38805420">sts</a> == <a class="code" href="dwc__otg__regs_8h.html#175767634e612a1e3dff3207a787d402">DMA_DESC_STS_PKTERR</a>) {
+<a name="l00787"></a>00787                                 <span class="comment">/* </span>
+<a name="l00788"></a>00788 <span class="comment">                                 * XactError or, unable to complete all the transactions </span>
+<a name="l00789"></a>00789 <span class="comment">                                 * in the scheduled micro-frame/frame, </span>
+<a name="l00790"></a>00790 <span class="comment">                                 * both indicated by DMA_DESC_STS_PKTERR.</span>
+<a name="l00791"></a>00791 <span class="comment">                                 */</span>     
+<a name="l00792"></a>00792                                 qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#7e7767808e8eb9d71de0db00f57553f9">urb</a>-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#58c7018042c94c436637ea80354e7e28">error_count</a>++;
+<a name="l00793"></a>00793                                 frame_desc-&gt;<a class="code" href="structdwc__otg__hcd__iso__packet__desc.html#c00b967f4c613820b99efc0abda5178c">actual_length</a> = qh-&gt;<a class="code" href="structdwc__otg__qh.html#6b625d870c7854ccaff5c28fad87482a">n_bytes</a>[idx] - remain;
+<a name="l00794"></a>00794                                 frame_desc-&gt;<a class="code" href="structdwc__otg__hcd__iso__packet__desc.html#d070772c24621c47b49ad21c6acadb94">status</a> = -DWC_E_PROTOCOL;
+<a name="l00795"></a>00795                         }
+<a name="l00796"></a>00796                         <span class="keywordflow">else</span> {
+<a name="l00797"></a>00797                                 <span class="comment">/* Success */</span>   
+<a name="l00798"></a>00798                                                                 
+<a name="l00799"></a>00799                                 frame_desc-&gt;<a class="code" href="structdwc__otg__hcd__iso__packet__desc.html#c00b967f4c613820b99efc0abda5178c">actual_length</a> = qh-&gt;<a class="code" href="structdwc__otg__qh.html#6b625d870c7854ccaff5c28fad87482a">n_bytes</a>[idx] - remain;
+<a name="l00800"></a>00800                                 frame_desc-&gt;<a class="code" href="structdwc__otg__hcd__iso__packet__desc.html#d070772c24621c47b49ad21c6acadb94">status</a> = 0;
+<a name="l00801"></a>00801                         }
+<a name="l00802"></a>00802                         
+<a name="l00803"></a>00803                         <span class="keywordflow">if</span> (++qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#c67d5f885976d0698f20d113d32b4b30">isoc_frame_index</a> == qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#7e7767808e8eb9d71de0db00f57553f9">urb</a>-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#570583697e8c1e4398969630bc2562f8">packet_count</a>) {
+<a name="l00804"></a>00804                                 <span class="comment">/*</span>
+<a name="l00805"></a>00805 <span class="comment">                                 * urb-&gt;status is not used for isoc transfers here.</span>
+<a name="l00806"></a>00806 <span class="comment">                                 * The individual frame_desc status are used instead.</span>
+<a name="l00807"></a>00807 <span class="comment">                                 */</span>
+<a name="l00808"></a>00808 
+<a name="l00809"></a>00809                                 hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#ffefbd33a59a14b8b46406f5aaeaa2f4">fops</a>-&gt;<a class="code" href="structdwc__otg__hcd__function__ops.html#09a989481103de7468cd46ef61ace0ce">complete</a>(hcd, qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#7e7767808e8eb9d71de0db00f57553f9">urb</a>-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#5ba0e393ef9768275db85c00e68be477">priv</a>, qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#7e7767808e8eb9d71de0db00f57553f9">urb</a>, 0);
+<a name="l00810"></a>00810                                 <a class="code" href="dwc__otg__hcd_8h.html#19adb6641f95448a956015b2d69ba96a">dwc_otg_hcd_qtd_remove_and_free</a>(hcd, qtd, qh);
+<a name="l00811"></a>00811                                 
+<a name="l00812"></a>00812                                 <span class="comment">/* </span>
+<a name="l00813"></a>00813 <span class="comment">                                 * This check is necessary because urb_dequeue can be called </span>
+<a name="l00814"></a>00814 <span class="comment">                                 * from urb complete callback(sound driver example).</span>
+<a name="l00815"></a>00815 <span class="comment">                                 * All pending URBs are dequeued there, so no need for</span>
+<a name="l00816"></a>00816 <span class="comment">                                 * further processing.</span>
+<a name="l00817"></a>00817 <span class="comment">                                 */</span>
+<a name="l00818"></a>00818                                 <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#07eca0fa02105ddaa1719387f5558b23">halt_status</a> == DWC_OTG_HC_XFER_URB_DEQUEUE) {   
+<a name="l00819"></a>00819                                         <span class="keywordflow">return</span>;
+<a name="l00820"></a>00820                                 }
+<a name="l00821"></a>00821                                 
+<a name="l00822"></a>00822                                 urb_compl = 1;          
+<a name="l00823"></a>00823                                 
+<a name="l00824"></a>00824                         }
+<a name="l00825"></a>00825                         
+<a name="l00826"></a>00826                         qh-&gt;<a class="code" href="structdwc__otg__qh.html#6da0f75ffa49c8ffadde42e9618ed8c8">ntd</a>--;
+<a name="l00827"></a>00827                         
+<a name="l00828"></a>00828                         <span class="comment">/* Stop if IOC requested descriptor reached */</span>
+<a name="l00829"></a>00829                         <span class="keywordflow">if</span> (dma_desc-&gt;<a class="code" href="structdwc__otg__host__dma__desc.html#1b73b25e9fca51dd00fa0607d57d9e3f">status</a>.<a class="code" href="unionhost__dma__desc__sts.html#e16a70bba7e2e196189573323c2dbe1c">b_isoc</a>.<a class="code" href="unionhost__dma__desc__sts.html#2efbb549924afd0deb402af9eda4a272">ioc</a>) {
+<a name="l00830"></a>00830                                 idx = <a class="code" href="dwc__otg__hcd__ddma_8c.html#c4d25855998839163827c8062bd6fb8b">desclist_idx_inc</a>(idx, qh-&gt;<a class="code" href="structdwc__otg__qh.html#cdbce86d457f0ea08e2efedc47c9b315">interval</a>, hc-&gt;<a class="code" href="structdwc__hc.html#570b78178975193edb921af1ef36d37b">speed</a>);   
+<a name="l00831"></a>00831                                 <span class="keywordflow">goto</span> stop_scan;
+<a name="l00832"></a>00832                         }
+<a name="l00833"></a>00833                         
+<a name="l00834"></a>00834                         idx = <a class="code" href="dwc__otg__hcd__ddma_8c.html#c4d25855998839163827c8062bd6fb8b">desclist_idx_inc</a>(idx, qh-&gt;<a class="code" href="structdwc__otg__qh.html#cdbce86d457f0ea08e2efedc47c9b315">interval</a>, hc-&gt;<a class="code" href="structdwc__hc.html#570b78178975193edb921af1ef36d37b">speed</a>);
+<a name="l00835"></a>00835                         
+<a name="l00836"></a>00836                         <span class="keywordflow">if</span> (urb_compl)
+<a name="l00837"></a>00837                                 <span class="keywordflow">break</span>;
+<a name="l00838"></a>00838                 }
+<a name="l00839"></a>00839                 <span class="keywordflow">while</span>(idx != qh-&gt;<a class="code" href="structdwc__otg__qh.html#3b20e91c00b1de8d42612a8b1250b403">td_first</a>);
+<a name="l00840"></a>00840         }
+<a name="l00841"></a>00841 stop_scan:      
+<a name="l00842"></a>00842         qh-&gt;<a class="code" href="structdwc__otg__qh.html#3b20e91c00b1de8d42612a8b1250b403">td_first</a> = idx;
+<a name="l00843"></a>00843 }
+<a name="l00844"></a>00844         
+<a name="l00845"></a><a class="code" href="dwc__otg__hcd__ddma_8c.html#7a1a6af7f05278f5b7daa3b0a2d2fa4a">00845</a> uint8_t <a class="code" href="dwc__otg__hcd__ddma_8c.html#7a1a6af7f05278f5b7daa3b0a2d2fa4a">update_non_isoc_urb_state_ddma</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd,
+<a name="l00846"></a>00846                            <a class="code" href="structdwc__hc.html">dwc_hc_t</a> * hc,
+<a name="l00847"></a>00847                            <a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> * qtd,
+<a name="l00848"></a>00848                            <a class="code" href="structdwc__otg__host__dma__desc.html">dwc_otg_host_dma_desc_t</a> * dma_desc,
+<a name="l00849"></a>00849                            dwc_otg_halt_status_e halt_status,
+<a name="l00850"></a>00850                            uint32_t n_bytes,
+<a name="l00851"></a>00851                            uint8_t *xfer_done)
+<a name="l00852"></a>00852 {
+<a name="l00853"></a>00853 
+<a name="l00854"></a>00854         uint16_t remain = hc-&gt;<a class="code" href="structdwc__hc.html#c5088d431f5efc382121f201f5d571aa">ep_is_in</a> ? dma_desc-&gt;<a class="code" href="structdwc__otg__host__dma__desc.html#1b73b25e9fca51dd00fa0607d57d9e3f">status</a>.<a class="code" href="unionhost__dma__desc__sts.html#a0e53895b927bfa9e322c3a3c0a08b3b">b</a>.<a class="code" href="unionhost__dma__desc__sts.html#a8f68a8a5c22c3c1b530400c23083892">n_bytes</a> : 0;
+<a name="l00855"></a>00855         <a class="code" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *urb = qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#7e7767808e8eb9d71de0db00f57553f9">urb</a>;
+<a name="l00856"></a>00856         
+<a name="l00857"></a>00857         
+<a name="l00858"></a>00858         <span class="keywordflow">if</span> (halt_status == DWC_OTG_HC_XFER_AHB_ERR) {
+<a name="l00859"></a>00859                 urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#101e4a6762b9911cdb85768890fa1210">status</a> = -DWC_E_IO;
+<a name="l00860"></a>00860                 <span class="keywordflow">return</span> 1;
+<a name="l00861"></a>00861         }
+<a name="l00862"></a>00862         <span class="keywordflow">if</span> (dma_desc-&gt;<a class="code" href="structdwc__otg__host__dma__desc.html#1b73b25e9fca51dd00fa0607d57d9e3f">status</a>.<a class="code" href="unionhost__dma__desc__sts.html#a0e53895b927bfa9e322c3a3c0a08b3b">b</a>.<a class="code" href="unionhost__dma__desc__sts.html#828b019082523c4637758bef38805420">sts</a> == <a class="code" href="dwc__otg__regs_8h.html#175767634e612a1e3dff3207a787d402">DMA_DESC_STS_PKTERR</a>) {
+<a name="l00863"></a>00863                 <span class="keywordflow">switch</span> (halt_status) {
+<a name="l00864"></a>00864                 <span class="keywordflow">case</span> DWC_OTG_HC_XFER_STALL:
+<a name="l00865"></a>00865                         urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#101e4a6762b9911cdb85768890fa1210">status</a> = -DWC_E_PIPE;
+<a name="l00866"></a>00866                         <span class="keywordflow">break</span>;
+<a name="l00867"></a>00867                 <span class="keywordflow">case</span> DWC_OTG_HC_XFER_BABBLE_ERR:
+<a name="l00868"></a>00868                         urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#101e4a6762b9911cdb85768890fa1210">status</a> = -DWC_E_OVERFLOW;
+<a name="l00869"></a>00869                         <span class="keywordflow">break</span>;
+<a name="l00870"></a>00870                 <span class="keywordflow">case</span> DWC_OTG_HC_XFER_XACT_ERR:
+<a name="l00871"></a>00871                         urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#101e4a6762b9911cdb85768890fa1210">status</a> = -DWC_E_PROTOCOL;
+<a name="l00872"></a>00872                         <span class="keywordflow">break</span>;
+<a name="l00873"></a>00873                 <span class="keywordflow">default</span>:        
+<a name="l00874"></a>00874                         DWC_ERROR(<span class="stringliteral">"%s: Unhandled descriptor error status (%d)\n"</span>, __func__,
+<a name="l00875"></a>00875                                   halt_status);
+<a name="l00876"></a>00876                         <span class="keywordflow">break</span>;
+<a name="l00877"></a>00877                 }
+<a name="l00878"></a>00878                 <span class="keywordflow">return</span> 1;
+<a name="l00879"></a>00879         }
+<a name="l00880"></a>00880         
+<a name="l00881"></a>00881         <span class="keywordflow">if</span> (dma_desc-&gt;<a class="code" href="structdwc__otg__host__dma__desc.html#1b73b25e9fca51dd00fa0607d57d9e3f">status</a>.<a class="code" href="unionhost__dma__desc__sts.html#a0e53895b927bfa9e322c3a3c0a08b3b">b</a>.<a class="code" href="unionhost__dma__desc__sts.html#1c4cf70718c94a1a847e52d4dd65cbb0">a</a> == 1) {
+<a name="l00882"></a>00882                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"Active descriptor encountered on channel %d\n"</span>, hc-&gt;<a class="code" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">hc_num</a>);
+<a name="l00883"></a>00883                 <span class="keywordflow">return</span> 0;
+<a name="l00884"></a>00884         }
+<a name="l00885"></a>00885         
+<a name="l00886"></a>00886         <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#e6169fbc92e4d79686097742ad646f5c">ep_type</a> == <a class="code" href="dwc__otg__cil_8h.html#64e5cd756330f5adab79b25cc8067bdc">DWC_OTG_EP_TYPE_CONTROL</a>) {
+<a name="l00887"></a>00887             <span class="keywordflow">if</span> (qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#5189ec9c992974d20477481eaf96d0bb">control_phase</a> == DWC_OTG_CONTROL_DATA) {
+<a name="l00888"></a>00888                 urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#742c8a97d3867ab89148eae34e0c73a6">actual_length</a> += n_bytes - remain;
+<a name="l00889"></a>00889                 <span class="keywordflow">if</span> (remain || urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#742c8a97d3867ab89148eae34e0c73a6">actual_length</a> == urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#dca57de4fdecd894241ce24167206a45">length</a>) {
+<a name="l00890"></a>00890                         <span class="comment">/* </span>
+<a name="l00891"></a>00891 <span class="comment">                         * For Control Data stage do not set urb-&gt;status=0 to prevent</span>
+<a name="l00892"></a>00892 <span class="comment">                         * URB callback. Set it when Status phase done. See below.</span>
+<a name="l00893"></a>00893 <span class="comment">                         */</span>
+<a name="l00894"></a>00894                         *xfer_done = 1;
+<a name="l00895"></a>00895                 }               
+<a name="l00896"></a>00896             
+<a name="l00897"></a>00897             }
+<a name="l00898"></a>00898             <span class="keywordflow">else</span> <span class="keywordflow">if</span> (qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#5189ec9c992974d20477481eaf96d0bb">control_phase</a> == DWC_OTG_CONTROL_STATUS) {
+<a name="l00899"></a>00899                 urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#101e4a6762b9911cdb85768890fa1210">status</a> = 0;
+<a name="l00900"></a>00900                 *xfer_done = 1;
+<a name="l00901"></a>00901             }
+<a name="l00902"></a>00902             <span class="comment">/* No handling for SETUP stage */</span>
+<a name="l00903"></a>00903 
+<a name="l00904"></a>00904         }
+<a name="l00905"></a>00905         <span class="keywordflow">else</span> { 
+<a name="l00906"></a>00906             <span class="comment">/* BULK and INTR */</span>
+<a name="l00907"></a>00907             urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#742c8a97d3867ab89148eae34e0c73a6">actual_length</a> += n_bytes - remain;
+<a name="l00908"></a>00908             <span class="keywordflow">if</span> (remain || urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#742c8a97d3867ab89148eae34e0c73a6">actual_length</a> == urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#dca57de4fdecd894241ce24167206a45">length</a>) {
+<a name="l00909"></a>00909                 urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#101e4a6762b9911cdb85768890fa1210">status</a> = 0;
+<a name="l00910"></a>00910                 *xfer_done = 1;
+<a name="l00911"></a>00911             }
+<a name="l00912"></a>00912         }
+<a name="l00913"></a>00913 
+<a name="l00914"></a>00914         <span class="keywordflow">return</span> 0;
+<a name="l00915"></a>00915 }
+<a name="l00916"></a>00916 
+<a name="l00917"></a><a class="code" href="dwc__otg__hcd__ddma_8c.html#3551cf23294204324754fca2da9a99d1">00917</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd__ddma_8c.html#3551cf23294204324754fca2da9a99d1">complete_non_isoc_xfer_ddma</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd,
+<a name="l00918"></a>00918                                         <a class="code" href="structdwc__hc.html">dwc_hc_t</a> * hc,
+<a name="l00919"></a>00919                                         <a class="code" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> * hc_regs,
+<a name="l00920"></a>00920                                         dwc_otg_halt_status_e halt_status)
+<a name="l00921"></a>00921 {
+<a name="l00922"></a>00922         <a class="code" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a>       *urb = NULL;
+<a name="l00923"></a>00923         <a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a>           *qtd, *qtd_tmp;
+<a name="l00924"></a>00924         <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a>            *qh;
+<a name="l00925"></a>00925         <a class="code" href="structdwc__otg__host__dma__desc.html">dwc_otg_host_dma_desc_t</a> *dma_desc;
+<a name="l00926"></a>00926         uint32_t                n_bytes, n_desc, i;
+<a name="l00927"></a>00927         uint8_t                 failed = 0, xfer_done;
+<a name="l00928"></a>00928         
+<a name="l00929"></a>00929         n_desc = 0;
+<a name="l00930"></a>00930         
+<a name="l00931"></a>00931         qh = hc-&gt;<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>;
+<a name="l00932"></a>00932 
+<a name="l00933"></a>00933         
+<a name="l00934"></a>00934         <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#07eca0fa02105ddaa1719387f5558b23">halt_status</a> == DWC_OTG_HC_XFER_URB_DEQUEUE) {
+<a name="l00935"></a>00935                 DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &amp;hc-&gt;<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#9567d266da8e796d3467fb16ae867f8e">qtd_list</a>, qtd_list_entry) {
+<a name="l00936"></a>00936                         qtd-&gt;in_process = 0;
+<a name="l00937"></a>00937                 }
+<a name="l00938"></a>00938                 <span class="keywordflow">return</span>;
+<a name="l00939"></a>00939         }
+<a name="l00940"></a>00940         
+<a name="l00941"></a>00941         DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &amp;qh-&gt;<a class="code" href="structdwc__otg__qh.html#9567d266da8e796d3467fb16ae867f8e">qtd_list</a>, qtd_list_entry) {
+<a name="l00942"></a>00942                 
+<a name="l00943"></a>00943                 urb = qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#7e7767808e8eb9d71de0db00f57553f9">urb</a>;
+<a name="l00944"></a>00944 
+<a name="l00945"></a>00945                 n_bytes = 0; 
+<a name="l00946"></a>00946                 xfer_done = 0; 
+<a name="l00947"></a>00947                 
+<a name="l00948"></a>00948                 <span class="keywordflow">for</span> (i = 0; i &lt; qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#ef3021e617cf1f448bd23b1f7ab3859b">n_desc</a>; i++) {
+<a name="l00949"></a>00949                         dma_desc = &amp;qh-&gt;<a class="code" href="structdwc__otg__qh.html#0e5f35688e54ba97054a1a7576e81150">desc_list</a>[n_desc];
+<a name="l00950"></a>00950                 
+<a name="l00951"></a>00951                         n_bytes = qh-&gt;<a class="code" href="structdwc__otg__qh.html#6b625d870c7854ccaff5c28fad87482a">n_bytes</a>[n_desc];
+<a name="l00952"></a>00952                         
+<a name="l00953"></a>00953                         
+<a name="l00954"></a>00954                         failed = <a class="code" href="dwc__otg__hcd__ddma_8c.html#7a1a6af7f05278f5b7daa3b0a2d2fa4a">update_non_isoc_urb_state_ddma</a>(hcd, hc, qtd, dma_desc, 
+<a name="l00955"></a>00955                                                                 halt_status, n_bytes, &amp;xfer_done);
+<a name="l00956"></a>00956                         
+<a name="l00957"></a>00957                         <span class="keywordflow">if</span> (failed || (xfer_done &amp;&amp; (urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#101e4a6762b9911cdb85768890fa1210">status</a> != -DWC_E_IN_PROGRESS))) {
+<a name="l00958"></a>00958                                 
+<a name="l00959"></a>00959                                 hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#ffefbd33a59a14b8b46406f5aaeaa2f4">fops</a>-&gt;<a class="code" href="structdwc__otg__hcd__function__ops.html#09a989481103de7468cd46ef61ace0ce">complete</a>(hcd, urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#5ba0e393ef9768275db85c00e68be477">priv</a>, urb, urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#101e4a6762b9911cdb85768890fa1210">status</a>);
+<a name="l00960"></a>00960                                 <a class="code" href="dwc__otg__hcd_8h.html#19adb6641f95448a956015b2d69ba96a">dwc_otg_hcd_qtd_remove_and_free</a>(hcd, qtd, qh);
+<a name="l00961"></a>00961 
+<a name="l00962"></a>00962                                 <span class="keywordflow">if</span> (failed)
+<a name="l00963"></a>00963                                         <span class="keywordflow">goto</span> stop_scan;
+<a name="l00964"></a>00964                         }
+<a name="l00965"></a>00965                         <span class="keywordflow">else</span> <span class="keywordflow">if</span> (qh-&gt;<a class="code" href="structdwc__otg__qh.html#98b78ffd8dbc01be44b302e873e73a82">ep_type</a> == UE_CONTROL) {
+<a name="l00966"></a>00966                                 <span class="keywordflow">if</span> (qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#5189ec9c992974d20477481eaf96d0bb">control_phase</a> == DWC_OTG_CONTROL_SETUP) {
+<a name="l00967"></a>00967                                         <span class="keywordflow">if</span> (urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#dca57de4fdecd894241ce24167206a45">length</a> &gt; 0) {
+<a name="l00968"></a>00968                                                 qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#5189ec9c992974d20477481eaf96d0bb">control_phase</a> = DWC_OTG_CONTROL_DATA;
+<a name="l00969"></a>00969                                         } <span class="keywordflow">else</span> {
+<a name="l00970"></a>00970                                                 qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#5189ec9c992974d20477481eaf96d0bb">control_phase</a> = DWC_OTG_CONTROL_STATUS;
+<a name="l00971"></a>00971                                         }
+<a name="l00972"></a>00972                                         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"  Control setup transaction done\n"</span>);
+<a name="l00973"></a>00973                                 }
+<a name="l00974"></a>00974                                 <span class="keywordflow">else</span> <span class="keywordflow">if</span>(qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#5189ec9c992974d20477481eaf96d0bb">control_phase</a> == DWC_OTG_CONTROL_DATA) {
+<a name="l00975"></a>00975                                         <span class="keywordflow">if</span> (xfer_done) {
+<a name="l00976"></a>00976                                                 qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#5189ec9c992974d20477481eaf96d0bb">control_phase</a> = DWC_OTG_CONTROL_STATUS;
+<a name="l00977"></a>00977                                                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"  Control data transfer done\n"</span>);
+<a name="l00978"></a>00978                                         } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (i+1 == qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#ef3021e617cf1f448bd23b1f7ab3859b">n_desc</a>){
+<a name="l00979"></a>00979                                                 <span class="comment">/* </span>
+<a name="l00980"></a>00980 <span class="comment">                                                 * Last descriptor for Control data stage which is</span>
+<a name="l00981"></a>00981 <span class="comment">                                                 * not completed yet.</span>
+<a name="l00982"></a>00982 <span class="comment">                                                 */</span>     
+<a name="l00983"></a>00983                                                 <a class="code" href="dwc__otg__hcd_8h.html#8bce109004d7869bfdd9aa1075c6bd2c">dwc_otg_hcd_save_data_toggle</a>(hc, hc_regs, qtd);
+<a name="l00984"></a>00984                                         }
+<a name="l00985"></a>00985                                 }
+<a name="l00986"></a>00986                         }
+<a name="l00987"></a>00987                         
+<a name="l00988"></a>00988                         n_desc++;
+<a name="l00989"></a>00989                 }
+<a name="l00990"></a>00990                 
+<a name="l00991"></a>00991         }
+<a name="l00992"></a>00992         
+<a name="l00993"></a>00993 stop_scan:      
+<a name="l00994"></a>00994         
+<a name="l00995"></a>00995         <span class="keywordflow">if</span> (qh-&gt;ep_type != UE_CONTROL) {
+<a name="l00996"></a>00996                 <span class="comment">/* </span>
+<a name="l00997"></a>00997 <span class="comment">                 * Resetting the data toggle for bulk</span>
+<a name="l00998"></a>00998 <span class="comment">                 * and interrupt endpoints in case of stall. See handle_hc_stall_intr() </span>
+<a name="l00999"></a>00999 <span class="comment">                 */</span>     
+<a name="l01000"></a>01000                 <span class="keywordflow">if</span> (halt_status == DWC_OTG_HC_XFER_STALL) {     
+<a name="l01001"></a>01001                         qh-&gt;data_toggle = <a class="code" href="dwc__otg__cil_8h.html#0e843d08e80c29e82962ce9170a02a52">DWC_OTG_HC_PID_DATA0</a>; 
+<a name="l01002"></a>01002                 }
+<a name="l01003"></a>01003                 <span class="keywordflow">else</span> {
+<a name="l01004"></a>01004                         <a class="code" href="dwc__otg__hcd_8h.html#8bce109004d7869bfdd9aa1075c6bd2c">dwc_otg_hcd_save_data_toggle</a>(hc, hc_regs, qtd);
+<a name="l01005"></a>01005                 }
+<a name="l01006"></a>01006         }
+<a name="l01007"></a>01007         
+<a name="l01008"></a>01008         <span class="keywordflow">if</span> (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
+<a name="l01009"></a>01009                 <a class="code" href="unionhcint__data.html">hcint_data_t</a> hcint;
+<a name="l01010"></a>01010                 hcint.<a class="code" href="unionhcint__data.html#05a82fa7693f875622db744716d7f73e">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;hcint);
+<a name="l01011"></a>01011                 <span class="keywordflow">if</span> (hcint.<a class="code" href="unionhcint__data.html#3ab6af507f45d91a7898dd711f4368ee">b</a>.<a class="code" href="unionhcint__data.html#755e54c3dfded3653447dfdd63fd8b6a">nyet</a>) {
+<a name="l01012"></a>01012                         <span class="comment">/*</span>
+<a name="l01013"></a>01013 <span class="comment">                         * Got a NYET on the last transaction of the transfer. It</span>
+<a name="l01014"></a>01014 <span class="comment">                         * means that the endpoint should be in the PING state at the</span>
+<a name="l01015"></a>01015 <span class="comment">                         * beginning of the next transfer.</span>
+<a name="l01016"></a>01016 <span class="comment">                         */</span>
+<a name="l01017"></a>01017                         qh-&gt;ping_state = 1;
+<a name="l01018"></a>01018                         <a class="code" href="dwc__otg__cil_8h.html#071cb1f3f29f9a52775e9fff270b1c7c">clear_hc_int</a>(hc_regs, nyet);
+<a name="l01019"></a>01019                 }
+<a name="l01020"></a>01020 
+<a name="l01021"></a>01021         }
+<a name="l01022"></a>01022 
+<a name="l01023"></a>01023 }
+<a name="l01024"></a>01024 
+<a name="l01042"></a><a class="code" href="dwc__otg__hcd__ddma_8c.html#ca94cde3142ff1121bb0ff9bd44fa762">01042</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd_8h.html#ca94cde3142ff1121bb0ff9bd44fa762">dwc_otg_hcd_complete_xfer_ddma</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd,
+<a name="l01043"></a>01043                             <a class="code" href="structdwc__hc.html">dwc_hc_t</a> *hc,
+<a name="l01044"></a>01044                             <a class="code" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *hc_regs,
+<a name="l01045"></a>01045                             dwc_otg_halt_status_e halt_status)
+<a name="l01046"></a>01046 {
+<a name="l01047"></a>01047         uint8_t continue_isoc_xfer = 0;
+<a name="l01048"></a>01048         <a class="code" href="dwc__otg__hcd_8h.html#92c49783eebc5bcffa8b8a51c2127be9">dwc_otg_transaction_type_e</a> tr_type;
+<a name="l01049"></a>01049         <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *qh = hc-&gt;<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>;
+<a name="l01050"></a>01050         
+<a name="l01051"></a>01051         <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#e6169fbc92e4d79686097742ad646f5c">ep_type</a> == <a class="code" href="dwc__otg__cil_8h.html#152a3a5e1433bd2197672f0b5105e7a4">DWC_OTG_EP_TYPE_ISOC</a>) {
+<a name="l01052"></a>01052 
+<a name="l01053"></a>01053                 <a class="code" href="dwc__otg__hcd__ddma_8c.html#aad342d0a6056bbc5645809f24ac8507">complete_isoc_xfer_ddma</a>(hcd, hc, hc_regs, halt_status);
+<a name="l01054"></a>01054                 
+<a name="l01055"></a>01055                 <span class="comment">/* Release the channel if halted or session completed */</span>        
+<a name="l01056"></a>01056                 <span class="keywordflow">if</span> (halt_status != DWC_OTG_HC_XFER_COMPLETE ||
+<a name="l01057"></a>01057                                 DWC_CIRCLEQ_EMPTY(&amp;qh-&gt;<a class="code" href="structdwc__otg__qh.html#9567d266da8e796d3467fb16ae867f8e">qtd_list</a>)) {
+<a name="l01058"></a>01058 
+<a name="l01059"></a>01059                         <span class="comment">/* Halt the channel if session completed */</span>     
+<a name="l01060"></a>01060                         <span class="keywordflow">if</span> (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
+<a name="l01061"></a>01061                                 <a class="code" href="dwc__otg__cil_8c.html#de044bf6b96c1bac92259a447ae85c0f">dwc_otg_hc_halt</a>(hcd-&gt;core_if, hc, halt_status);
+<a name="l01062"></a>01062                         }       
+<a name="l01063"></a>01063                         
+<a name="l01064"></a>01064                         <a class="code" href="dwc__otg__hcd__ddma_8c.html#060f60ac2e210b5da3bbe379674d2012">release_channel_ddma</a>(hcd, qh);
+<a name="l01065"></a>01065                         <a class="code" href="dwc__otg__hcd_8h.html#506b89b01ee7692885daff1c17c894f8">dwc_otg_hcd_qh_remove</a>(hcd, qh);
+<a name="l01066"></a>01066                 }
+<a name="l01067"></a>01067                 <span class="keywordflow">else</span> {
+<a name="l01068"></a>01068                         <span class="comment">/* Keep in assigned schedule to continue transfer */</span>
+<a name="l01069"></a>01069                         DWC_LIST_MOVE_HEAD(&amp;hcd-&gt;periodic_sched_assigned,
+<a name="l01070"></a>01070                                            &amp;qh-&gt;<a class="code" href="structdwc__otg__qh.html#3e1cb9863dc72139e1832c04244c25ff">qh_list_entry</a>);
+<a name="l01071"></a>01071                         continue_isoc_xfer = 1;
+<a name="l01072"></a>01072                                 
+<a name="l01073"></a>01073                 }
+<a name="l01077"></a>01077         }
+<a name="l01078"></a>01078         <span class="keywordflow">else</span> {
+<a name="l01079"></a>01079                 <span class="comment">/* Scan descriptor list to complete the URB(s), then release the channel */</span>     
+<a name="l01080"></a>01080                 <a class="code" href="dwc__otg__hcd__ddma_8c.html#3551cf23294204324754fca2da9a99d1">complete_non_isoc_xfer_ddma</a>(hcd, hc, hc_regs, halt_status);
+<a name="l01081"></a>01081                 
+<a name="l01082"></a>01082                 <a class="code" href="dwc__otg__hcd__ddma_8c.html#060f60ac2e210b5da3bbe379674d2012">release_channel_ddma</a>(hcd, qh);
+<a name="l01083"></a>01083                 
+<a name="l01084"></a>01084                 <a class="code" href="dwc__otg__hcd_8h.html#506b89b01ee7692885daff1c17c894f8">dwc_otg_hcd_qh_remove</a>(hcd, qh);
+<a name="l01085"></a>01085                 
+<a name="l01086"></a>01086                 <span class="keywordflow">if</span> (!DWC_CIRCLEQ_EMPTY(&amp;qh-&gt;<a class="code" href="structdwc__otg__qh.html#9567d266da8e796d3467fb16ae867f8e">qtd_list</a>)) {
+<a name="l01087"></a>01087                         <span class="comment">/* Add back to inactive non-periodic schedule on normal completion */</span>
+<a name="l01088"></a>01088                         <a class="code" href="dwc__otg__hcd_8h.html#75cad4c6010d88086ddedf739db55d6b">dwc_otg_hcd_qh_add</a>(hcd, qh);
+<a name="l01089"></a>01089                 }
+<a name="l01090"></a>01090         
+<a name="l01091"></a>01091 
+<a name="l01092"></a>01092         }
+<a name="l01093"></a>01093         tr_type = <a class="code" href="dwc__otg__hcd_8c.html#96cc299f4f0478187ed7ba49b975ffc3">dwc_otg_hcd_select_transactions</a>(hcd);
+<a name="l01094"></a>01094         <span class="keywordflow">if</span> (tr_type != DWC_OTG_TRANSACTION_NONE || continue_isoc_xfer) {
+<a name="l01095"></a>01095                 <span class="keywordflow">if</span> (continue_isoc_xfer) {
+<a name="l01096"></a>01096                         <span class="keywordflow">if</span> (tr_type == DWC_OTG_TRANSACTION_NONE) {
+<a name="l01097"></a>01097                                 tr_type = DWC_OTG_TRANSACTION_PERIODIC;
+<a name="l01098"></a>01098                         } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC) {
+<a name="l01099"></a>01099                                 tr_type = DWC_OTG_TRANSACTION_ALL;
+<a name="l01100"></a>01100                         }
+<a name="l01101"></a>01101                 }
+<a name="l01102"></a>01102                 <a class="code" href="dwc__otg__hcd_8c.html#2f57bf2fc3013d63101f112702b913a0">dwc_otg_hcd_queue_transactions</a>(hcd, tr_type);
+<a name="l01103"></a>01103         }
+<a name="l01104"></a>01104 }
+<a name="l01105"></a>01105         
+<a name="l01106"></a>01106 <span class="preprocessor">#endif  </span><span class="comment">/* DWC_DEVICE_ONLY */</span>
+</pre></div><hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__ddma_8c.html b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__ddma_8c.html
new file mode 100644
index 000000000000..813b9526f3d9
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__ddma_8c.html
@@ -0,0 +1,311 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd_ddma.c File Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<h1>dwc_otg_hcd_ddma.c File Reference</h1>This file contains Descriptor DMA support implementation for host mode. <a href="#_details">More...</a>
+<p>
+<code>#include &quot;<a class="el" href="dwc__otg__hcd_8h-source.html">dwc_otg_hcd.h</a>&quot;</code><br>
+<code>#include &quot;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&quot;</code><br>
+
+<p>
+<a href="dwc__otg__hcd__ddma_8c-source.html">Go to the source code of this file.</a><table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Defines</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7aed1ace42f0421b376041d8831c9a74"></a><!-- doxytag: member="dwc_otg_hcd_ddma.c::ISOC_URB_GIVEBACK_ASAP" ref="7aed1ace42f0421b376041d8831c9a74" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__ddma_8c.html#7aed1ace42f0421b376041d8831c9a74">ISOC_URB_GIVEBACK_ASAP</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="cf56bce31ec5dfcc2a36047c0c648784"></a><!-- doxytag: member="dwc_otg_hcd_ddma.c::MAX_ISOC_XFER_SIZE_FS" ref="cf56bce31ec5dfcc2a36047c0c648784" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__ddma_8c.html#cf56bce31ec5dfcc2a36047c0c648784">MAX_ISOC_XFER_SIZE_FS</a>&nbsp;&nbsp;&nbsp;1023</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="06012eeeca2d17ee7ea304b381928c4a"></a><!-- doxytag: member="dwc_otg_hcd_ddma.c::MAX_ISOC_XFER_SIZE_HS" ref="06012eeeca2d17ee7ea304b381928c4a" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__ddma_8c.html#06012eeeca2d17ee7ea304b381928c4a">MAX_ISOC_XFER_SIZE_HS</a>&nbsp;&nbsp;&nbsp;3072</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="1f389f323086b2c2697f2ab56062ead6"></a><!-- doxytag: member="dwc_otg_hcd_ddma.c::DESCNUM_THRESHOLD" ref="1f389f323086b2c2697f2ab56062ead6" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__ddma_8c.html#1f389f323086b2c2697f2ab56062ead6">DESCNUM_THRESHOLD</a>&nbsp;&nbsp;&nbsp;4</td></tr>
+
+<tr><td colspan="2"><br><h2>Functions</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="cc7af33964cf891f1448376c2a57b309"></a><!-- doxytag: member="dwc_otg_hcd_ddma.c::frame_list_idx" ref="cc7af33964cf891f1448376c2a57b309" args="(uint16_t frame)" -->
+static uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__ddma_8c.html#cc7af33964cf891f1448376c2a57b309">frame_list_idx</a> (uint16_t frame)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c4d25855998839163827c8062bd6fb8b"></a><!-- doxytag: member="dwc_otg_hcd_ddma.c::desclist_idx_inc" ref="c4d25855998839163827c8062bd6fb8b" args="(uint16_t idx, uint16_t inc, uint8_t speed)" -->
+static uint16_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__ddma_8c.html#c4d25855998839163827c8062bd6fb8b">desclist_idx_inc</a> (uint16_t idx, uint16_t inc, uint8_t speed)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="13186d2e949bb38420a7a19a4530a5ad"></a><!-- doxytag: member="dwc_otg_hcd_ddma.c::desclist_idx_dec" ref="13186d2e949bb38420a7a19a4530a5ad" args="(uint16_t idx, uint16_t inc, uint8_t speed)" -->
+static uint16_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__ddma_8c.html#13186d2e949bb38420a7a19a4530a5ad">desclist_idx_dec</a> (uint16_t idx, uint16_t inc, uint8_t speed)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b7563972b1dd332dde72911900756d92"></a><!-- doxytag: member="dwc_otg_hcd_ddma.c::max_desc_num" ref="b7563972b1dd332dde72911900756d92" args="(dwc_otg_qh_t *qh)" -->
+static uint16_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__ddma_8c.html#b7563972b1dd332dde72911900756d92">max_desc_num</a> (<a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *qh)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="357d9fe0cd782a9c88e79f47c3b58384"></a><!-- doxytag: member="dwc_otg_hcd_ddma.c::frame_incr_val" ref="357d9fe0cd782a9c88e79f47c3b58384" args="(dwc_otg_qh_t *qh)" -->
+static uint16_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__ddma_8c.html#357d9fe0cd782a9c88e79f47c3b58384">frame_incr_val</a> (<a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *qh)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="12375cf094e35d9be3b78da6cf621d01"></a><!-- doxytag: member="dwc_otg_hcd_ddma.c::desc_list_alloc" ref="12375cf094e35d9be3b78da6cf621d01" args="(dwc_otg_qh_t *qh)" -->
+static int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__ddma_8c.html#12375cf094e35d9be3b78da6cf621d01">desc_list_alloc</a> (<a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *qh)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c062f46629017bdeeebaf90aa65f610b"></a><!-- doxytag: member="dwc_otg_hcd_ddma.c::desc_list_free" ref="c062f46629017bdeeebaf90aa65f610b" args="(dwc_otg_qh_t *qh)" -->
+static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__ddma_8c.html#c062f46629017bdeeebaf90aa65f610b">desc_list_free</a> (<a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *qh)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="35be74597b6abe7a7d077c2c00d64dc2"></a><!-- doxytag: member="dwc_otg_hcd_ddma.c::frame_list_alloc" ref="35be74597b6abe7a7d077c2c00d64dc2" args="(dwc_otg_hcd_t *hcd)" -->
+static int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__ddma_8c.html#35be74597b6abe7a7d077c2c00d64dc2">frame_list_alloc</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="01991072b147e11d3b7350a2ee9ee920"></a><!-- doxytag: member="dwc_otg_hcd_ddma.c::frame_list_free" ref="01991072b147e11d3b7350a2ee9ee920" args="(dwc_otg_hcd_t *hcd)" -->
+static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__ddma_8c.html#01991072b147e11d3b7350a2ee9ee920">frame_list_free</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="5b78d71512c6143d5a50e31dc3517f6a"></a><!-- doxytag: member="dwc_otg_hcd_ddma.c::per_sched_enable" ref="5b78d71512c6143d5a50e31dc3517f6a" args="(dwc_otg_hcd_t *hcd, uint16_t fr_list_en)" -->
+static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__ddma_8c.html#5b78d71512c6143d5a50e31dc3517f6a">per_sched_enable</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, uint16_t fr_list_en)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="693b9fdfeebc77b8132cfaf461b9c8fd"></a><!-- doxytag: member="dwc_otg_hcd_ddma.c::per_sched_disable" ref="693b9fdfeebc77b8132cfaf461b9c8fd" args="(dwc_otg_hcd_t *hcd)" -->
+static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__ddma_8c.html#693b9fdfeebc77b8132cfaf461b9c8fd">per_sched_disable</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="46c1ec7e2bd2f1177983f6676952cfdf"></a><!-- doxytag: member="dwc_otg_hcd_ddma.c::update_frame_list" ref="46c1ec7e2bd2f1177983f6676952cfdf" args="(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, uint8_t enable)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__ddma_8c.html#46c1ec7e2bd2f1177983f6676952cfdf">update_frame_list</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *qh, uint8_t enable)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="9122fdf195fad109710651bbf730ca35"></a><!-- doxytag: member="dwc_otg_hcd_ddma.c::dump_frame_list" ref="9122fdf195fad109710651bbf730ca35" args="(dwc_otg_hcd_t *hcd)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__ddma_8c.html#9122fdf195fad109710651bbf730ca35">dump_frame_list</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="060f60ac2e210b5da3bbe379674d2012"></a><!-- doxytag: member="dwc_otg_hcd_ddma.c::release_channel_ddma" ref="060f60ac2e210b5da3bbe379674d2012" args="(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)" -->
+static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__ddma_8c.html#060f60ac2e210b5da3bbe379674d2012">release_channel_ddma</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *qh)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__ddma_8c.html#1c5498d173c5461865a5042789927ed1">dwc_otg_hcd_qh_init_ddma</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *qh)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Initializes a QH structure's Descriptor DMA related members.  <a href="#1c5498d173c5461865a5042789927ed1"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__ddma_8c.html#78738afd0ca62e394753f1cf196476c9">dwc_otg_hcd_qh_free_ddma</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *qh)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Frees descriptor list memory associated with the QH.  <a href="#78738afd0ca62e394753f1cf196476c9"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="42ed718bf245372d90fa8f92fcb69a99"></a><!-- doxytag: member="dwc_otg_hcd_ddma.c::frame_to_desc_idx" ref="42ed718bf245372d90fa8f92fcb69a99" args="(dwc_otg_qh_t *qh, uint16_t frame_idx)" -->
+static uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__ddma_8c.html#42ed718bf245372d90fa8f92fcb69a99">frame_to_desc_idx</a> (<a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *qh, uint16_t frame_idx)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f9c8d06c646b374cf34925e659142709"></a><!-- doxytag: member="dwc_otg_hcd_ddma.c::calc_starting_frame" ref="f9c8d06c646b374cf34925e659142709" args="(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, uint8_t *skip_frames)" -->
+static uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__ddma_8c.html#f9c8d06c646b374cf34925e659142709">calc_starting_frame</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *qh, uint8_t *skip_frames)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="fc5f584eb735a394a794a3022939638a"></a><!-- doxytag: member="dwc_otg_hcd_ddma.c::recalc_initial_desc_idx" ref="fc5f584eb735a394a794a3022939638a" args="(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)" -->
+static uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__ddma_8c.html#fc5f584eb735a394a794a3022939638a">recalc_initial_desc_idx</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *qh)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f2bad2e76275e230f83be94c21a0bd75"></a><!-- doxytag: member="dwc_otg_hcd_ddma.c::init_isoc_dma_desc" ref="f2bad2e76275e230f83be94c21a0bd75" args="(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, uint8_t skip_frames)" -->
+static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__ddma_8c.html#f2bad2e76275e230f83be94c21a0bd75">init_isoc_dma_desc</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *qh, uint8_t skip_frames)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f3630ce7f8926de36873d78a1748134f"></a><!-- doxytag: member="dwc_otg_hcd_ddma.c::init_non_isoc_dma_desc" ref="f3630ce7f8926de36873d78a1748134f" args="(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)" -->
+static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__ddma_8c.html#f3630ce7f8926de36873d78a1748134f">init_non_isoc_dma_desc</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *qh)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__ddma_8c.html#9b051bad5e81a6b6d74b817c741bfaf3">dwc_otg_hcd_start_xfer_ddma</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *qh)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">For Control and Bulk endpoints initializes descriptor list and starts the transfer.  <a href="#9b051bad5e81a6b6d74b817c741bfaf3"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="aad342d0a6056bbc5645809f24ac8507"></a><!-- doxytag: member="dwc_otg_hcd_ddma.c::complete_isoc_xfer_ddma" ref="aad342d0a6056bbc5645809f24ac8507" args="(dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_halt_status_e halt_status)" -->
+static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__ddma_8c.html#aad342d0a6056bbc5645809f24ac8507">complete_isoc_xfer_ddma</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__hc.html">dwc_hc_t</a> *hc, <a class="el" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *hc_regs, dwc_otg_halt_status_e halt_status)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7a1a6af7f05278f5b7daa3b0a2d2fa4a"></a><!-- doxytag: member="dwc_otg_hcd_ddma.c::update_non_isoc_urb_state_ddma" ref="7a1a6af7f05278f5b7daa3b0a2d2fa4a" args="(dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_qtd_t *qtd, dwc_otg_host_dma_desc_t *dma_desc, dwc_otg_halt_status_e halt_status, uint32_t n_bytes, uint8_t *xfer_done)" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__ddma_8c.html#7a1a6af7f05278f5b7daa3b0a2d2fa4a">update_non_isoc_urb_state_ddma</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__hc.html">dwc_hc_t</a> *hc, <a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *qtd, <a class="el" href="structdwc__otg__host__dma__desc.html">dwc_otg_host_dma_desc_t</a> *dma_desc, dwc_otg_halt_status_e halt_status, uint32_t n_bytes, uint8_t *xfer_done)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3551cf23294204324754fca2da9a99d1"></a><!-- doxytag: member="dwc_otg_hcd_ddma.c::complete_non_isoc_xfer_ddma" ref="3551cf23294204324754fca2da9a99d1" args="(dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_halt_status_e halt_status)" -->
+static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__ddma_8c.html#3551cf23294204324754fca2da9a99d1">complete_non_isoc_xfer_ddma</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__hc.html">dwc_hc_t</a> *hc, <a class="el" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *hc_regs, dwc_otg_halt_status_e halt_status)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__ddma_8c.html#ca94cde3142ff1121bb0ff9bd44fa762">dwc_otg_hcd_complete_xfer_ddma</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__hc.html">dwc_hc_t</a> *hc, <a class="el" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *hc_regs, dwc_otg_halt_status_e halt_status)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function is called from interrupt handlers.  <a href="#ca94cde3142ff1121bb0ff9bd44fa762"></a><br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This file contains Descriptor DMA support implementation for host mode. 
+<p>
+
+<p>
+Definition in file <a class="el" href="dwc__otg__hcd__ddma_8c-source.html">dwc_otg_hcd_ddma.c</a>.<hr><h2>Function Documentation</h2>
+<a class="anchor" name="1c5498d173c5461865a5042789927ed1"></a><!-- doxytag: member="dwc_otg_hcd_ddma.c::dwc_otg_hcd_qh_init_ddma" ref="1c5498d173c5461865a5042789927ed1" args="(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_hcd_qh_init_ddma           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>qh</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Initializes a QH structure's Descriptor DMA related members. 
+<p>
+Allocates memory for descriptor list. On first periodic QH, allocates memory for FrameList and enables periodic scheduling.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD state structure for the DWC OTG controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>qh</em>&nbsp;</td><td>The QH to init.</td></tr>
+  </table>
+</dl>
+<dl compact><dt><b>Returns:</b></dt><dd>0 if successful, negative error code otherwise. </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__ddma_8c-source.html#l00294">294</a> of file <a class="el" href="dwc__otg__hcd__ddma_8c-source.html">dwc_otg_hcd_ddma.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="78738afd0ca62e394753f1cf196476c9"></a><!-- doxytag: member="dwc_otg_hcd_ddma.c::dwc_otg_hcd_qh_free_ddma" ref="78738afd0ca62e394753f1cf196476c9" args="(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_hcd_qh_free_ddma           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>qh</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Frees descriptor list memory associated with the QH. 
+<p>
+If QH is periodic and the last, frees FrameList memory and disables periodic scheduling.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD state structure for the DWC OTG controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>qh</em>&nbsp;</td><td>The QH to init. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__ddma_8c-source.html#l00327">327</a> of file <a class="el" href="dwc__otg__hcd__ddma_8c-source.html">dwc_otg_hcd_ddma.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="9b051bad5e81a6b6d74b817c741bfaf3"></a><!-- doxytag: member="dwc_otg_hcd_ddma.c::dwc_otg_hcd_start_xfer_ddma" ref="9b051bad5e81a6b6d74b817c741bfaf3" args="(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_hcd_start_xfer_ddma           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>qh</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+For Control and Bulk endpoints initializes descriptor list and starts the transfer. 
+<p>
+For Interrupt and Isochronous endpoints initializes descriptor list then updates FrameList, marking appropriate entries as active. In case of Isochronous, the starting descriptor index is calculated based on the scheduled frame, but only on the first transfer descriptor within a session. Then starts the transfer via enabling the channel. For Isochronous endpoint the channel is not halted on XferComplete interrupt so remains assigned to the endpoint(QH) until session is done.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD state structure for the DWC OTG controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>qh</em>&nbsp;</td><td>The QH to init.</td></tr>
+  </table>
+</dl>
+<dl compact><dt><b>Returns:</b></dt><dd>0 if successful, negative error code otherwise. </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__ddma_8c-source.html#l00675">675</a> of file <a class="el" href="dwc__otg__hcd__ddma_8c-source.html">dwc_otg_hcd_ddma.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="ca94cde3142ff1121bb0ff9bd44fa762"></a><!-- doxytag: member="dwc_otg_hcd_ddma.c::dwc_otg_hcd_complete_xfer_ddma" ref="ca94cde3142ff1121bb0ff9bd44fa762" args="(dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_halt_status_e halt_status)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_hcd_complete_xfer_ddma           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__hc.html">dwc_hc_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc_regs</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">dwc_otg_halt_status_e&nbsp;</td>
+          <td class="paramname"> <em>halt_status</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function is called from interrupt handlers. 
+<p>
+Scans the descriptor list, updates URB's status and calls completion routine for the URB if it's done. Releases the channel to be used by other transfers. In case of Isochronous endpoint the channel is not halted until the end of the session, i.e. QTD list is empty. If periodic channel released the FrameList is updated accordingly.<p>
+Calls transaction selection routines to activate pending transfers.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD state structure for the DWC OTG controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>hc</em>&nbsp;</td><td>Host channel, the transfer is completed on. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>hc_regs</em>&nbsp;</td><td>Host channel registers. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>halt_status</em>&nbsp;</td><td>Reason the channel is being halted, or just XferComplete for isochronous transfer </td></tr>
+  </table>
+</dl>
+
+<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000015">Todo:</a></b></dt><dd>Consider the case when period exceeds FrameList size. Frame Rollover interrupt should be used. </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__ddma_8c-source.html#l01042">1042</a> of file <a class="el" href="dwc__otg__hcd__ddma_8c-source.html">dwc_otg_hcd_ddma.c</a>.
+</div>
+</div><p>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__if_8h-source.html b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__if_8h-source.html
new file mode 100644
index 000000000000..11bddbcc2f30
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__if_8h-source.html
@@ -0,0 +1,191 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd_if.h Source File</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
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+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
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+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<h1>dwc_otg_hcd_if.h</h1><a href="dwc__otg__hcd__if_8h.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">/* ==========================================================================</span>
+<a name="l00002"></a>00002 <span class="comment"> * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_if.h $</span>
+<a name="l00003"></a>00003 <span class="comment"> * $Revision: #6 $</span>
+<a name="l00004"></a>00004 <span class="comment"> * $Date: 2009/04/21 $</span>
+<a name="l00005"></a>00005 <span class="comment"> * $Change: 1237474 $</span>
+<a name="l00006"></a>00006 <span class="comment"> *</span>
+<a name="l00007"></a>00007 <span class="comment"> * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,</span>
+<a name="l00008"></a>00008 <span class="comment"> * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless</span>
+<a name="l00009"></a>00009 <span class="comment"> * otherwise expressly agreed to in writing between Synopsys and you.</span>
+<a name="l00010"></a>00010 <span class="comment"> *</span>
+<a name="l00011"></a>00011 <span class="comment"> * The Software IS NOT an item of Licensed Software or Licensed Product under</span>
+<a name="l00012"></a>00012 <span class="comment"> * any End User Software License Agreement or Agreement for Licensed Product</span>
+<a name="l00013"></a>00013 <span class="comment"> * with Synopsys or any supplement thereto. You are permitted to use and</span>
+<a name="l00014"></a>00014 <span class="comment"> * redistribute this Software in source and binary forms, with or without</span>
+<a name="l00015"></a>00015 <span class="comment"> * modification, provided that redistributions of source code must retain this</span>
+<a name="l00016"></a>00016 <span class="comment"> * notice. You may not view, use, disclose, copy or distribute this file or</span>
+<a name="l00017"></a>00017 <span class="comment"> * any information contained herein except pursuant to this license grant from</span>
+<a name="l00018"></a>00018 <span class="comment"> * Synopsys. If you do not agree with this notice, including the disclaimer</span>
+<a name="l00019"></a>00019 <span class="comment"> * below, then you are not authorized to use the Software.</span>
+<a name="l00020"></a>00020 <span class="comment"> *</span>
+<a name="l00021"></a>00021 <span class="comment"> * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS</span>
+<a name="l00022"></a>00022 <span class="comment"> * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE</span>
+<a name="l00023"></a>00023 <span class="comment"> * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE</span>
+<a name="l00024"></a>00024 <span class="comment"> * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,</span>
+<a name="l00025"></a>00025 <span class="comment"> * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES</span>
+<a name="l00026"></a>00026 <span class="comment"> * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR</span>
+<a name="l00027"></a>00027 <span class="comment"> * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER</span>
+<a name="l00028"></a>00028 <span class="comment"> * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT</span>
+<a name="l00029"></a>00029 <span class="comment"> * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY</span>
+<a name="l00030"></a>00030 <span class="comment"> * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH</span>
+<a name="l00031"></a>00031 <span class="comment"> * DAMAGE.</span>
+<a name="l00032"></a>00032 <span class="comment"> * ========================================================================== */</span>
+<a name="l00033"></a>00033 <span class="preprocessor">#ifndef DWC_DEVICE_ONLY</span>
+<a name="l00034"></a>00034 <span class="preprocessor"></span><span class="preprocessor">#ifndef __DWC_HCD_IF_H__</span>
+<a name="l00035"></a>00035 <span class="preprocessor"></span><span class="preprocessor">#define __DWC_HCD_IF_H__</span>
+<a name="l00036"></a>00036 <span class="preprocessor"></span>
+<a name="l00037"></a>00037 <span class="preprocessor">#include "<a class="code" href="dwc__otg__core__if_8h.html">dwc_otg_core_if.h</a>"</span>
+<a name="l00038"></a>00038 
+<a name="l00043"></a>00043 <span class="keyword">struct </span><a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>;
+<a name="l00044"></a><a class="code" href="dwc__otg__hcd__if_8h.html#c60760d19c9d069e3bf00b4b97b74cd3">00044</a> <span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a> <a class="code" href="dwc__otg__hcd__if_8h.html#c60760d19c9d069e3bf00b4b97b74cd3">dwc_otg_hcd_t</a>;
+<a name="l00045"></a>00045 
+<a name="l00046"></a>00046 <span class="keyword">struct </span><a class="code" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb</a>;
+<a name="l00047"></a><a class="code" href="dwc__otg__hcd__if_8h.html#0e7bca23553c3dfc493b44a01454a2c4">00047</a> <span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb</a> <a class="code" href="dwc__otg__hcd__if_8h.html#0e7bca23553c3dfc493b44a01454a2c4">dwc_otg_hcd_urb_t</a>;
+<a name="l00048"></a>00048 
+<a name="l00053"></a><a class="code" href="dwc__otg__hcd__if_8h.html#76658d35c49c5594bdb795fddf8252a8">00053</a> <span class="keyword">typedef</span> int (*<a class="code" href="dwc__otg__hcd__if_8h.html#76658d35c49c5594bdb795fddf8252a8">dwc_otg_hcd_start_cb_t</a>) (<a class="code" href="dwc__otg__hcd__if_8h.html#c60760d19c9d069e3bf00b4b97b74cd3">dwc_otg_hcd_t</a> * hcd);
+<a name="l00054"></a>00054 
+<a name="l00056"></a><a class="code" href="dwc__otg__hcd__if_8h.html#8190c45625905c85a22565524abcf192">00056</a> <span class="keyword">typedef</span> int (*<a class="code" href="dwc__otg__hcd__if_8h.html#8190c45625905c85a22565524abcf192">dwc_otg_hcd_disconnect_cb_t</a>) (<a class="code" href="dwc__otg__hcd__if_8h.html#c60760d19c9d069e3bf00b4b97b74cd3">dwc_otg_hcd_t</a> * hcd);
+<a name="l00057"></a>00057 
+<a name="l00059"></a><a class="code" href="dwc__otg__hcd__if_8h.html#7893b4f0c0c2116e6cd8ba82659d7b65">00059</a> <span class="keyword">typedef</span> int (*<a class="code" href="dwc__otg__hcd__if_8h.html#7893b4f0c0c2116e6cd8ba82659d7b65">dwc_otg_hcd_hub_info_from_urb_cb_t</a>) (<a class="code" href="dwc__otg__hcd__if_8h.html#c60760d19c9d069e3bf00b4b97b74cd3">dwc_otg_hcd_t</a> * hcd,
+<a name="l00060"></a>00060                                                    <span class="keywordtype">void</span> *urb_handle,
+<a name="l00061"></a>00061                                                    uint32_t * hub_addr,
+<a name="l00062"></a>00062                                                    uint32_t * port_addr);
+<a name="l00064"></a><a class="code" href="dwc__otg__hcd__if_8h.html#d85b6d5afa41eb5b0d1365b14642e77c">00064</a> <span class="keyword">typedef</span> int (*<a class="code" href="dwc__otg__hcd__if_8h.html#d85b6d5afa41eb5b0d1365b14642e77c">dwc_otg_hcd_speed_from_urb_cb_t</a>) (<a class="code" href="dwc__otg__hcd__if_8h.html#c60760d19c9d069e3bf00b4b97b74cd3">dwc_otg_hcd_t</a> * hcd,
+<a name="l00065"></a>00065                                                 <span class="keywordtype">void</span> *urb_handle);
+<a name="l00066"></a>00066 
+<a name="l00068"></a><a class="code" href="dwc__otg__hcd__if_8h.html#87b0daec8c90b013f81b4854b64dec2e">00068</a> <span class="keyword">typedef</span> int (*<a class="code" href="dwc__otg__hcd__if_8h.html#87b0daec8c90b013f81b4854b64dec2e">dwc_otg_hcd_complete_urb_cb_t</a>) (<a class="code" href="dwc__otg__hcd__if_8h.html#c60760d19c9d069e3bf00b4b97b74cd3">dwc_otg_hcd_t</a> * hcd,
+<a name="l00069"></a>00069                                               <span class="keywordtype">void</span> *urb_handle,
+<a name="l00070"></a>00070                                               <a class="code" href="dwc__otg__hcd__if_8h.html#0e7bca23553c3dfc493b44a01454a2c4">dwc_otg_hcd_urb_t</a> * dwc_otg_urb,
+<a name="l00071"></a>00071                                               int32_t <a class="code" href="structdwc__otg__hcd__urb.html#101e4a6762b9911cdb85768890fa1210">status</a>);
+<a name="l00072"></a>00072 
+<a name="l00074"></a><a class="code" href="dwc__otg__hcd__if_8h.html#23db00d75e435cb0cb13d1e914dfd672">00074</a> <span class="keyword">typedef</span> int (*<a class="code" href="dwc__otg__hcd__if_8h.html#23db00d75e435cb0cb13d1e914dfd672">dwc_otg_hcd_get_b_hnp_enable</a>) (<a class="code" href="dwc__otg__hcd__if_8h.html#c60760d19c9d069e3bf00b4b97b74cd3">dwc_otg_hcd_t</a> * hcd);
+<a name="l00075"></a>00075 
+<a name="l00076"></a><a class="code" href="structdwc__otg__hcd__function__ops.html">00076</a> <span class="keyword">struct </span><a class="code" href="structdwc__otg__hcd__function__ops.html">dwc_otg_hcd_function_ops</a> {
+<a name="l00077"></a><a class="code" href="structdwc__otg__hcd__function__ops.html#d74a65269fe5712ac307bfd3230a29b4">00077</a>         <a class="code" href="dwc__otg__hcd__if_8h.html#76658d35c49c5594bdb795fddf8252a8">dwc_otg_hcd_start_cb_t</a> <a class="code" href="structdwc__otg__hcd__function__ops.html#d74a65269fe5712ac307bfd3230a29b4">start</a>;
+<a name="l00078"></a><a class="code" href="structdwc__otg__hcd__function__ops.html#fb7650d10a745991479af978fb519651">00078</a>         <a class="code" href="dwc__otg__hcd__if_8h.html#8190c45625905c85a22565524abcf192">dwc_otg_hcd_disconnect_cb_t</a> <a class="code" href="structdwc__otg__hcd__function__ops.html#fb7650d10a745991479af978fb519651">disconnect</a>;
+<a name="l00079"></a><a class="code" href="structdwc__otg__hcd__function__ops.html#71bff93886173700d26a8950e7ea82e1">00079</a>         <a class="code" href="dwc__otg__hcd__if_8h.html#7893b4f0c0c2116e6cd8ba82659d7b65">dwc_otg_hcd_hub_info_from_urb_cb_t</a> <a class="code" href="structdwc__otg__hcd__function__ops.html#71bff93886173700d26a8950e7ea82e1">hub_info</a>;
+<a name="l00080"></a><a class="code" href="structdwc__otg__hcd__function__ops.html#29f9b98c1a824637a5c8aec86649fdd4">00080</a>         <a class="code" href="dwc__otg__hcd__if_8h.html#d85b6d5afa41eb5b0d1365b14642e77c">dwc_otg_hcd_speed_from_urb_cb_t</a> <a class="code" href="structdwc__otg__hcd__function__ops.html#29f9b98c1a824637a5c8aec86649fdd4">speed</a>;
+<a name="l00081"></a><a class="code" href="structdwc__otg__hcd__function__ops.html#09a989481103de7468cd46ef61ace0ce">00081</a>         <a class="code" href="dwc__otg__hcd__if_8h.html#87b0daec8c90b013f81b4854b64dec2e">dwc_otg_hcd_complete_urb_cb_t</a> <a class="code" href="structdwc__otg__hcd__function__ops.html#09a989481103de7468cd46ef61ace0ce">complete</a>;
+<a name="l00082"></a><a class="code" href="structdwc__otg__hcd__function__ops.html#24a2ee2bad4dc517fed62417a2a542d3">00082</a>         <a class="code" href="dwc__otg__hcd__if_8h.html#23db00d75e435cb0cb13d1e914dfd672">dwc_otg_hcd_get_b_hnp_enable</a> <a class="code" href="structdwc__otg__hcd__function__ops.html#24a2ee2bad4dc517fed62417a2a542d3">get_b_hnp_enable</a>;
+<a name="l00083"></a>00083 };
+<a name="l00089"></a>00089 <span class="keyword">extern</span> <a class="code" href="dwc__otg__hcd__if_8h.html#c60760d19c9d069e3bf00b4b97b74cd3">dwc_otg_hcd_t</a> *<a class="code" href="dwc__otg__hcd_8c.html#5595437c199432efbd3609dc87ef5afa">dwc_otg_hcd_alloc_hcd</a>(<span class="keywordtype">void</span>);
+<a name="l00090"></a>00090 
+<a name="l00099"></a>00099 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd_8c.html#2d38590dadee51fd767d63e0dc675f23">dwc_otg_hcd_init</a>(<a class="code" href="dwc__otg__hcd__if_8h.html#c60760d19c9d069e3bf00b4b97b74cd3">dwc_otg_hcd_t</a> * hcd, <a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if);
+<a name="l00100"></a>00100 
+<a name="l00105"></a>00105 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd_8c.html#f347bcb363a622ced29161878d38830b">dwc_otg_hcd_remove</a>(<a class="code" href="dwc__otg__hcd__if_8h.html#c60760d19c9d069e3bf00b4b97b74cd3">dwc_otg_hcd_t</a> * hcd);
+<a name="l00106"></a>00106 
+<a name="l00114"></a>00114 <span class="keyword">extern</span> int32_t <a class="code" href="dwc__otg__hcd_8h.html#b9dde24773f2741b9ff67e2d46760dc0">dwc_otg_hcd_handle_intr</a>(<a class="code" href="dwc__otg__hcd__if_8h.html#c60760d19c9d069e3bf00b4b97b74cd3">dwc_otg_hcd_t</a> * <a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>);
+<a name="l00115"></a>00115 
+<a name="l00122"></a>00122 <span class="keyword">extern</span> <span class="keywordtype">void</span> *<a class="code" href="dwc__otg__hcd_8c.html#7740268b2d0fd8d25aaaeacfa5aef5cf">dwc_otg_hcd_get_priv_data</a>(<a class="code" href="dwc__otg__hcd__if_8h.html#c60760d19c9d069e3bf00b4b97b74cd3">dwc_otg_hcd_t</a> * hcd);
+<a name="l00123"></a>00123 
+<a name="l00130"></a>00130 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd_8c.html#c73ca7d4284c8f0de7338a66607e4eb1">dwc_otg_hcd_set_priv_data</a>(<a class="code" href="dwc__otg__hcd__if_8h.html#c60760d19c9d069e3bf00b4b97b74cd3">dwc_otg_hcd_t</a> * hcd, <span class="keywordtype">void</span> *priv_data);
+<a name="l00131"></a>00131 
+<a name="l00141"></a>00141 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd_8c.html#7242be8ebc7f7516292cbe2344ab03be">dwc_otg_hcd_start</a>(<a class="code" href="dwc__otg__hcd__if_8h.html#c60760d19c9d069e3bf00b4b97b74cd3">dwc_otg_hcd_t</a> * hcd,
+<a name="l00142"></a>00142                              <span class="keyword">struct</span> <a class="code" href="structdwc__otg__hcd__function__ops.html">dwc_otg_hcd_function_ops</a> *<a class="code" href="dwc__otg__pcd__linux_8c.html#9ce9b5e49c60906c189bee157dd68acd">fops</a>);
+<a name="l00143"></a>00143 
+<a name="l00150"></a>00150 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd_8c.html#70c58e8a45eb7ad8ee2f2c74ba3a77f0">dwc_otg_hcd_stop</a>(<a class="code" href="dwc__otg__hcd__if_8h.html#c60760d19c9d069e3bf00b4b97b74cd3">dwc_otg_hcd_t</a> * hcd);
+<a name="l00151"></a>00151 
+<a name="l00165"></a>00165 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd_8c.html#e3bd4e9d1f641cdd29df6633bfb1ebd2">dwc_otg_hcd_hub_control</a>(<a class="code" href="dwc__otg__hcd__if_8h.html#c60760d19c9d069e3bf00b4b97b74cd3">dwc_otg_hcd_t</a> * <a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>,
+<a name="l00166"></a>00166                                    uint16_t typeReq, uint16_t wValue,
+<a name="l00167"></a>00167                                    uint16_t wIndex, uint8_t * buf,
+<a name="l00168"></a>00168                                    uint16_t wLength);
+<a name="l00169"></a>00169 
+<a name="l00175"></a>00175 <span class="keyword">extern</span> uint32_t <a class="code" href="dwc__otg__hcd_8c.html#e7d3657931984a1ce1cee5cf47cb08f3">dwc_otg_hcd_otg_port</a>(<a class="code" href="dwc__otg__hcd__if_8h.html#c60760d19c9d069e3bf00b4b97b74cd3">dwc_otg_hcd_t</a> * hcd);
+<a name="l00176"></a>00176 
+<a name="l00182"></a>00182 <span class="keyword">extern</span> uint32_t <a class="code" href="dwc__otg__hcd_8c.html#ca25b33b440a4ef112ee459c26c14adc">dwc_otg_hcd_is_b_host</a>(<a class="code" href="dwc__otg__hcd__if_8h.html#c60760d19c9d069e3bf00b4b97b74cd3">dwc_otg_hcd_t</a> * hcd);
+<a name="l00183"></a>00183 
+<a name="l00189"></a>00189 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd_8c.html#f06514bd6f8c219cc72d1f467a82c056">dwc_otg_hcd_get_frame_number</a>(<a class="code" href="dwc__otg__hcd__if_8h.html#c60760d19c9d069e3bf00b4b97b74cd3">dwc_otg_hcd_t</a> * hcd);
+<a name="l00190"></a>00190 
+<a name="l00196"></a>00196 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd_8c.html#464f920221173fe04c756a9d6657f321">dwc_otg_hcd_dump_state</a>(<a class="code" href="dwc__otg__hcd__if_8h.html#c60760d19c9d069e3bf00b4b97b74cd3">dwc_otg_hcd_t</a> * hcd);
+<a name="l00197"></a>00197 
+<a name="l00206"></a>00206 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd_8c.html#b2c46e92cdc57b1783f445ed60cc3f38">dwc_otg_hcd_dump_frrem</a>(<a class="code" href="dwc__otg__hcd__if_8h.html#c60760d19c9d069e3bf00b4b97b74cd3">dwc_otg_hcd_t</a> * hcd);
+<a name="l00207"></a>00207 
+<a name="l00219"></a>00219 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd__if_8h.html#b0c95e7f6cda9e15d767ad3ef6a7f1cc">dwc_otg_hcd_send_lpm</a>(<a class="code" href="dwc__otg__hcd__if_8h.html#c60760d19c9d069e3bf00b4b97b74cd3">dwc_otg_hcd_t</a> * hcd, uint8_t devaddr,
+<a name="l00220"></a>00220                                 uint8_t hird, uint8_t bRemoteWake);
+<a name="l00221"></a>00221 
+<a name="l00222"></a>00222 <span class="comment">/* URB interface */</span>
+<a name="l00223"></a>00223 
+<a name="l00232"></a>00232 <span class="keyword">extern</span> <a class="code" href="dwc__otg__hcd__if_8h.html#0e7bca23553c3dfc493b44a01454a2c4">dwc_otg_hcd_urb_t</a> *<a class="code" href="dwc__otg__hcd_8c.html#264fc9d293c76e42dded9dee2cf44283">dwc_otg_hcd_urb_alloc</a>(<a class="code" href="dwc__otg__hcd__if_8h.html#c60760d19c9d069e3bf00b4b97b74cd3">dwc_otg_hcd_t</a> * hcd,
+<a name="l00233"></a>00233                                                 <span class="keywordtype">int</span> iso_desc_count,
+<a name="l00234"></a>00234                                                 <span class="keywordtype">int</span> atomic_alloc);
+<a name="l00235"></a>00235 
+<a name="l00246"></a>00246 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd_8c.html#4aca8781f512198149388799a8ae9aba">dwc_otg_hcd_urb_set_pipeinfo</a>(<a class="code" href="dwc__otg__hcd__if_8h.html#0e7bca23553c3dfc493b44a01454a2c4">dwc_otg_hcd_urb_t</a> * hcd_urb,
+<a name="l00247"></a>00247                                          uint8_t devaddr, uint8_t ep_num,
+<a name="l00248"></a>00248                                          uint8_t ep_type, uint8_t ep_dir,
+<a name="l00249"></a>00249                                          uint16_t mps);
+<a name="l00250"></a>00250 
+<a name="l00251"></a>00251 <span class="comment">/* Transfer flags */</span> 
+<a name="l00252"></a><a class="code" href="dwc__otg__hcd__if_8h.html#973a9deb7ee08e99abf7cb7adf6a5c72">00252</a> <span class="preprocessor">#define URB_GIVEBACK_ASAP 0x1</span>
+<a name="l00253"></a><a class="code" href="dwc__otg__hcd__if_8h.html#14e576ea3b30c038f925e3e6c80c64fe">00253</a> <span class="preprocessor"></span><span class="preprocessor">#define URB_SEND_ZERO_PACKET 0x2</span>
+<a name="l00254"></a>00254 <span class="preprocessor"></span>
+<a name="l00269"></a>00269 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd_8c.html#d141b0ed3f2eac3f8aab2d8cefe34345">dwc_otg_hcd_urb_set_params</a>(<a class="code" href="dwc__otg__hcd__if_8h.html#0e7bca23553c3dfc493b44a01454a2c4">dwc_otg_hcd_urb_t</a> * urb,
+<a name="l00270"></a>00270                                        <span class="keywordtype">void</span> *urb_handle, <span class="keywordtype">void</span> *buf,
+<a name="l00271"></a>00271                                        dwc_dma_t dma, uint32_t buflen, <span class="keywordtype">void</span> *sp,
+<a name="l00272"></a>00272                                        dwc_dma_t sp_dma, uint32_t flags,
+<a name="l00273"></a>00273                                        uint16_t interval);
+<a name="l00274"></a>00274 
+<a name="l00279"></a>00279 <span class="keyword">extern</span> uint32_t <a class="code" href="dwc__otg__hcd_8c.html#81b7aad80889affb1e63cf1307b88fb6">dwc_otg_hcd_urb_get_status</a>(<a class="code" href="dwc__otg__hcd__if_8h.html#0e7bca23553c3dfc493b44a01454a2c4">dwc_otg_hcd_urb_t</a> * dwc_otg_urb);
+<a name="l00280"></a>00280 
+<a name="l00285"></a>00285 <span class="keyword">extern</span> uint32_t <a class="code" href="dwc__otg__hcd_8c.html#3260f5db4ea20074da16b292eb1a686b">dwc_otg_hcd_urb_get_actual_length</a>(<a class="code" href="dwc__otg__hcd__if_8h.html#0e7bca23553c3dfc493b44a01454a2c4">dwc_otg_hcd_urb_t</a> *
+<a name="l00286"></a>00286                                                   dwc_otg_urb);
+<a name="l00287"></a>00287 
+<a name="l00292"></a>00292 <span class="keyword">extern</span> uint32_t <a class="code" href="dwc__otg__hcd_8c.html#816cc30c3129fc8911a458355d977129">dwc_otg_hcd_urb_get_error_count</a>(<a class="code" href="dwc__otg__hcd__if_8h.html#0e7bca23553c3dfc493b44a01454a2c4">dwc_otg_hcd_urb_t</a> *
+<a name="l00293"></a>00293                                                 dwc_otg_urb);
+<a name="l00294"></a>00294 
+<a name="l00302"></a>00302 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd_8c.html#8617e93eba1bfd6466a9af1e6d2f731b">dwc_otg_hcd_urb_set_iso_desc_params</a>(<a class="code" href="dwc__otg__hcd__if_8h.html#0e7bca23553c3dfc493b44a01454a2c4">dwc_otg_hcd_urb_t</a> * dwc_otg_urb,
+<a name="l00303"></a>00303                                                 <span class="keywordtype">int</span> desc_num, uint32_t offset,
+<a name="l00304"></a>00304                                                 uint32_t length);
+<a name="l00305"></a>00305 
+<a name="l00311"></a>00311 <span class="keyword">extern</span> uint32_t <a class="code" href="dwc__otg__hcd_8c.html#fde27182e452709e10c1100ea57aa46b">dwc_otg_hcd_urb_get_iso_desc_status</a>(<a class="code" href="dwc__otg__hcd__if_8h.html#0e7bca23553c3dfc493b44a01454a2c4">dwc_otg_hcd_urb_t</a> *
+<a name="l00312"></a>00312                                                     dwc_otg_urb, <span class="keywordtype">int</span> desc_num);
+<a name="l00313"></a>00313 
+<a name="l00319"></a>00319 <span class="keyword">extern</span> uint32_t <a class="code" href="dwc__otg__hcd_8c.html#c6d28fc3e6aedb29d46a793423c4de0a">dwc_otg_hcd_urb_get_iso_desc_actual_length</a>(<a class="code" href="dwc__otg__hcd__if_8h.html#0e7bca23553c3dfc493b44a01454a2c4">dwc_otg_hcd_urb_t</a> *
+<a name="l00320"></a>00320                                                            dwc_otg_urb,
+<a name="l00321"></a>00321                                                            <span class="keywordtype">int</span> desc_num);
+<a name="l00322"></a>00322 
+<a name="l00333"></a>00333 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd_8c.html#e8129fbc0a4073f0a5f64fa3b0f5127b">dwc_otg_hcd_urb_enqueue</a>(<a class="code" href="dwc__otg__hcd__if_8h.html#c60760d19c9d069e3bf00b4b97b74cd3">dwc_otg_hcd_t</a> * <a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>,
+<a name="l00334"></a>00334                                    <a class="code" href="dwc__otg__hcd__if_8h.html#0e7bca23553c3dfc493b44a01454a2c4">dwc_otg_hcd_urb_t</a> * dwc_otg_urb,
+<a name="l00335"></a>00335                                    <span class="keywordtype">void</span> **ep_handle);
+<a name="l00336"></a>00336 
+<a name="l00342"></a>00342 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd_8c.html#8844d0e14480b7f0dcf5c8120cc20a4f">dwc_otg_hcd_urb_dequeue</a>(<a class="code" href="dwc__otg__hcd__if_8h.html#c60760d19c9d069e3bf00b4b97b74cd3">dwc_otg_hcd_t</a> * <a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>,
+<a name="l00343"></a>00343                                    <a class="code" href="dwc__otg__hcd__if_8h.html#0e7bca23553c3dfc493b44a01454a2c4">dwc_otg_hcd_urb_t</a> * dwc_otg_urb);
+<a name="l00344"></a>00344 
+<a name="l00355"></a>00355 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd_8c.html#f80e9550161e354c865e3c411d661dbe">dwc_otg_hcd_endpoint_disable</a>(<a class="code" href="dwc__otg__hcd__if_8h.html#c60760d19c9d069e3bf00b4b97b74cd3">dwc_otg_hcd_t</a> * hcd, <span class="keywordtype">void</span> *ep_handle,
+<a name="l00356"></a>00356                                         <span class="keywordtype">int</span> retry);
+<a name="l00357"></a>00357 
+<a name="l00363"></a>00363 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd_8c.html#0d324c8dbb0c7cbadec8cebf943fc84b">dwc_otg_hcd_is_status_changed</a>(<a class="code" href="dwc__otg__hcd__if_8h.html#c60760d19c9d069e3bf00b4b97b74cd3">dwc_otg_hcd_t</a> * hcd, <span class="keywordtype">int</span> port);
+<a name="l00364"></a>00364 
+<a name="l00371"></a>00371 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd_8c.html#5deb69c332ba937b959c9dccadd87568">dwc_otg_hcd_is_bandwidth_allocated</a>(<a class="code" href="dwc__otg__hcd__if_8h.html#c60760d19c9d069e3bf00b4b97b74cd3">dwc_otg_hcd_t</a> * hcd,
+<a name="l00372"></a>00372                                               <span class="keywordtype">void</span> *ep_handle);
+<a name="l00373"></a>00373 
+<a name="l00379"></a>00379 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd_8c.html#ad28eed057375c7f31663dc777edefd7">dwc_otg_hcd_is_bandwidth_freed</a>(<a class="code" href="dwc__otg__hcd__if_8h.html#c60760d19c9d069e3bf00b4b97b74cd3">dwc_otg_hcd_t</a> * hcd, <span class="keywordtype">void</span> *ep_handle);
+<a name="l00380"></a>00380 
+<a name="l00387"></a>00387 <span class="keyword">extern</span> uint8_t <a class="code" href="dwc__otg__hcd_8c.html#bd160be911ccc8f90141dae9c40276eb">dwc_otg_hcd_get_ep_bandwidth</a>(<a class="code" href="dwc__otg__hcd__if_8h.html#c60760d19c9d069e3bf00b4b97b74cd3">dwc_otg_hcd_t</a> * hcd,
+<a name="l00388"></a>00388                                             <span class="keywordtype">void</span> *ep_handle);
+<a name="l00389"></a>00389 
+<a name="l00392"></a>00392 <span class="preprocessor">#endif                          </span><span class="comment">/* __DWC_HCD_IF_H__ */</span>
+<a name="l00393"></a>00393 <span class="preprocessor">#endif                          </span><span class="comment">/* DWC_DEVICE_ONLY */</span>
+</pre></div><hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__if_8h.html b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__if_8h.html
new file mode 100644
index 000000000000..3bb51aa10f3e
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__if_8h.html
@@ -0,0 +1,1381 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd_if.h File Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<h1>dwc_otg_hcd_if.h File Reference</h1>This file defines DWC_OTG HCD Core API. <a href="#_details">More...</a>
+<p>
+<code>#include &quot;<a class="el" href="dwc__otg__core__if_8h-source.html">dwc_otg_core_if.h</a>&quot;</code><br>
+
+<p>
+<a href="dwc__otg__hcd__if_8h-source.html">Go to the source code of this file.</a><table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Structures</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd__function__ops.html">dwc_otg_hcd_function_ops</a></td></tr>
+
+<tr><td colspan="2"><br><h2>HCD Core API</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="973a9deb7ee08e99abf7cb7adf6a5c72"></a><!-- doxytag: member="dwc_otg_hcd_if.h::URB_GIVEBACK_ASAP" ref="973a9deb7ee08e99abf7cb7adf6a5c72" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__if_8h.html#973a9deb7ee08e99abf7cb7adf6a5c72">URB_GIVEBACK_ASAP</a>&nbsp;&nbsp;&nbsp;0x1</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="14e576ea3b30c038f925e3e6c80c64fe"></a><!-- doxytag: member="dwc_otg_hcd_if.h::URB_SEND_ZERO_PACKET" ref="14e576ea3b30c038f925e3e6c80c64fe" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__if_8h.html#14e576ea3b30c038f925e3e6c80c64fe">URB_SEND_ZERO_PACKET</a>&nbsp;&nbsp;&nbsp;0x2</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="5595437c199432efbd3609dc87ef5afa"></a><!-- doxytag: member="dwc_otg_hcd_if.h::dwc_otg_hcd_alloc_hcd" ref="5595437c199432efbd3609dc87ef5afa" args="(void)" -->
+<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__if_8h.html#5595437c199432efbd3609dc87ef5afa">dwc_otg_hcd_alloc_hcd</a> (void)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function allocates <a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd</a> structure and returns pointer on it. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__if_8h.html#2d38590dadee51fd767d63e0dc675f23">dwc_otg_hcd_init</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function should be called to initiate HCD Core.  <a href="#2d38590dadee51fd767d63e0dc675f23"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__if_8h.html#f347bcb363a622ced29161878d38830b">dwc_otg_hcd_remove</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Frees HCD.  <a href="#f347bcb363a622ced29161878d38830b"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__if_8h.html#b9dde24773f2741b9ff67e2d46760dc0">dwc_otg_hcd_handle_intr</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function should be called on every hardware interrupt.  <a href="#b9dde24773f2741b9ff67e2d46760dc0"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__if_8h.html#7740268b2d0fd8d25aaaeacfa5aef5cf">dwc_otg_hcd_get_priv_data</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Returns private data set by dwc_otg_hcd_set_priv_data function.  <a href="#7740268b2d0fd8d25aaaeacfa5aef5cf"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__if_8h.html#c73ca7d4284c8f0de7338a66607e4eb1">dwc_otg_hcd_set_priv_data</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, void *priv_data)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Set private data.  <a href="#c73ca7d4284c8f0de7338a66607e4eb1"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__if_8h.html#7242be8ebc7f7516292cbe2344ab03be">dwc_otg_hcd_start</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, struct <a class="el" href="structdwc__otg__hcd__function__ops.html">dwc_otg_hcd_function_ops</a> *<a class="el" href="dwc__otg__pcd__linux_8c.html#9ce9b5e49c60906c189bee157dd68acd">fops</a>)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function initializes the HCD Core.  <a href="#7242be8ebc7f7516292cbe2344ab03be"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__if_8h.html#70c58e8a45eb7ad8ee2f2c74ba3a77f0">dwc_otg_hcd_stop</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Halts the DWC_otg host mode operations in a clean manner.  <a href="#70c58e8a45eb7ad8ee2f2c74ba3a77f0"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__if_8h.html#e3bd4e9d1f641cdd29df6633bfb1ebd2">dwc_otg_hcd_hub_control</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>, uint16_t typeReq, uint16_t wValue, uint16_t wIndex, uint8_t *buf, uint16_t wLength)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Handles hub class-specific requests.  <a href="#e3bd4e9d1f641cdd29df6633bfb1ebd2"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__if_8h.html#e7d3657931984a1ce1cee5cf47cb08f3">dwc_otg_hcd_otg_port</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Returns otg port number.  <a href="#e7d3657931984a1ce1cee5cf47cb08f3"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__if_8h.html#ca25b33b440a4ef112ee459c26c14adc">dwc_otg_hcd_is_b_host</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Returns 1 if currently core is acting as B host, and 0 otherwise.  <a href="#ca25b33b440a4ef112ee459c26c14adc"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__if_8h.html#65b3f4d96d1b34abaa54c3bbb32ec07f">dwc_otg_hcd_get_frame_number</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Returns current frame number.  <a href="#65b3f4d96d1b34abaa54c3bbb32ec07f"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__if_8h.html#464f920221173fe04c756a9d6657f321">dwc_otg_hcd_dump_state</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Dumps hcd state.  <a href="#464f920221173fe04c756a9d6657f321"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__if_8h.html#b2c46e92cdc57b1783f445ed60cc3f38">dwc_otg_hcd_dump_frrem</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Dump the average frame remaining at SOF.  <a href="#b2c46e92cdc57b1783f445ed60cc3f38"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__if_8h.html#b0c95e7f6cda9e15d767ad3ef6a7f1cc">dwc_otg_hcd_send_lpm</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, uint8_t devaddr, uint8_t hird, uint8_t bRemoteWake)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Sends LPM transaction to the local device.  <a href="#b0c95e7f6cda9e15d767ad3ef6a7f1cc"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__if_8h.html#264fc9d293c76e42dded9dee2cf44283">dwc_otg_hcd_urb_alloc</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, int iso_desc_count, int atomic_alloc)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Allocates memory for <a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb</a> structure.  <a href="#264fc9d293c76e42dded9dee2cf44283"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__if_8h.html#6c0a7bf2d1091d6e9e1ce767329fc04a">dwc_otg_hcd_urb_set_pipeinfo</a> (<a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *hcd_urb, uint8_t devaddr, uint8_t ep_num, uint8_t ep_type, uint8_t ep_dir, uint16_t mps)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Set pipe information in URB.  <a href="#6c0a7bf2d1091d6e9e1ce767329fc04a"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__if_8h.html#356834d51d095518b6283a343bfab2b0">dwc_otg_hcd_urb_set_params</a> (<a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *urb, void *urb_handle, void *buf, dwc_dma_t dma, uint32_t buflen, void *sp, dwc_dma_t sp_dma, uint32_t flags, uint16_t interval)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Sets <a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb</a> parameters.  <a href="#356834d51d095518b6283a343bfab2b0"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__if_8h.html#81b7aad80889affb1e63cf1307b88fb6">dwc_otg_hcd_urb_get_status</a> (<a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *dwc_otg_urb)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Gets status from <a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb</a>.  <a href="#81b7aad80889affb1e63cf1307b88fb6"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__if_8h.html#3260f5db4ea20074da16b292eb1a686b">dwc_otg_hcd_urb_get_actual_length</a> (<a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *dwc_otg_urb)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Gets actual length from <a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb</a>.  <a href="#3260f5db4ea20074da16b292eb1a686b"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__if_8h.html#816cc30c3129fc8911a458355d977129">dwc_otg_hcd_urb_get_error_count</a> (<a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *dwc_otg_urb)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Gets error count from <a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb</a>.  <a href="#816cc30c3129fc8911a458355d977129"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__if_8h.html#8617e93eba1bfd6466a9af1e6d2f731b">dwc_otg_hcd_urb_set_iso_desc_params</a> (<a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *dwc_otg_urb, int desc_num, uint32_t offset, uint32_t length)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Set ISOC descriptor offset and length.  <a href="#8617e93eba1bfd6466a9af1e6d2f731b"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__if_8h.html#fde27182e452709e10c1100ea57aa46b">dwc_otg_hcd_urb_get_iso_desc_status</a> (<a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *dwc_otg_urb, int desc_num)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get status of ISOC descriptor, specified by desc_num.  <a href="#fde27182e452709e10c1100ea57aa46b"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__if_8h.html#c6d28fc3e6aedb29d46a793423c4de0a">dwc_otg_hcd_urb_get_iso_desc_actual_length</a> (<a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *dwc_otg_urb, int desc_num)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get actual length of ISOC descriptor, specified by desc_num.  <a href="#c6d28fc3e6aedb29d46a793423c4de0a"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__if_8h.html#e8db09c826a847ffbaf7a5e7a60b697c">dwc_otg_hcd_urb_enqueue</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>, <a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *dwc_otg_urb, void **ep_handle)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Queue URB.  <a href="#e8db09c826a847ffbaf7a5e7a60b697c"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__if_8h.html#e7377ee6d5cdb17a4213cc96bf534a23">dwc_otg_hcd_urb_dequeue</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>, <a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *dwc_otg_urb)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">De-queue the specified URB.  <a href="#e7377ee6d5cdb17a4213cc96bf534a23"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__if_8h.html#f80e9550161e354c865e3c411d661dbe">dwc_otg_hcd_endpoint_disable</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, void *ep_handle, int retry)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Frees resources in the DWC_otg controller related to a given endpoint.  <a href="#f80e9550161e354c865e3c411d661dbe"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__if_8h.html#0d324c8dbb0c7cbadec8cebf943fc84b">dwc_otg_hcd_is_status_changed</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, int port)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Returns 1 if status of specified port is changed and 0 otherwise.  <a href="#0d324c8dbb0c7cbadec8cebf943fc84b"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__if_8h.html#5deb69c332ba937b959c9dccadd87568">dwc_otg_hcd_is_bandwidth_allocated</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, void *ep_handle)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Call this function to check if bandwidth was allocated for specified endpoint.  <a href="#5deb69c332ba937b959c9dccadd87568"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__if_8h.html#ad28eed057375c7f31663dc777edefd7">dwc_otg_hcd_is_bandwidth_freed</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, void *ep_handle)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Call this function to check if bandwidth was freed for specified endpoint.  <a href="#ad28eed057375c7f31663dc777edefd7"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__if_8h.html#bd160be911ccc8f90141dae9c40276eb">dwc_otg_hcd_get_ep_bandwidth</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, void *ep_handle)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Returns bandwidth allocated for specified endpoint in microseconds.  <a href="#bd160be911ccc8f90141dae9c40276eb"></a><br></td></tr>
+<tr><td colspan="2"><br><h2>HCD Function Driver Callbacks</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="76658d35c49c5594bdb795fddf8252a8"></a><!-- doxytag: member="dwc_otg_hcd_if.h::dwc_otg_hcd_start_cb_t" ref="76658d35c49c5594bdb795fddf8252a8" args="(dwc_otg_hcd_t *hcd)" -->
+typedef int(*)&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__if_8h.html#76658d35c49c5594bdb795fddf8252a8">dwc_otg_hcd_start_cb_t</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function is called whenever core switches to host mode. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="8190c45625905c85a22565524abcf192"></a><!-- doxytag: member="dwc_otg_hcd_if.h::dwc_otg_hcd_disconnect_cb_t" ref="8190c45625905c85a22565524abcf192" args="(dwc_otg_hcd_t *hcd)" -->
+typedef int(*)&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__if_8h.html#8190c45625905c85a22565524abcf192">dwc_otg_hcd_disconnect_cb_t</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function is called when device has been disconnected. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7893b4f0c0c2116e6cd8ba82659d7b65"></a><!-- doxytag: member="dwc_otg_hcd_if.h::dwc_otg_hcd_hub_info_from_urb_cb_t" ref="7893b4f0c0c2116e6cd8ba82659d7b65" args="(dwc_otg_hcd_t *hcd, void *urb_handle, uint32_t *hub_addr, uint32_t *port_addr)" -->
+typedef int(*)&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__if_8h.html#7893b4f0c0c2116e6cd8ba82659d7b65">dwc_otg_hcd_hub_info_from_urb_cb_t</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, void *urb_handle, uint32_t *hub_addr, uint32_t *port_addr)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Wrapper provides this function to HCD to core, so it can get hub information to which device is connected. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="d85b6d5afa41eb5b0d1365b14642e77c"></a><!-- doxytag: member="dwc_otg_hcd_if.h::dwc_otg_hcd_speed_from_urb_cb_t" ref="d85b6d5afa41eb5b0d1365b14642e77c" args="(dwc_otg_hcd_t *hcd, void *urb_handle)" -->
+typedef int(*)&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__if_8h.html#d85b6d5afa41eb5b0d1365b14642e77c">dwc_otg_hcd_speed_from_urb_cb_t</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, void *urb_handle)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Via this function HCD core gets device speed. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="87b0daec8c90b013f81b4854b64dec2e"></a><!-- doxytag: member="dwc_otg_hcd_if.h::dwc_otg_hcd_complete_urb_cb_t" ref="87b0daec8c90b013f81b4854b64dec2e" args="(dwc_otg_hcd_t *hcd, void *urb_handle, dwc_otg_hcd_urb_t *dwc_otg_urb, int32_t status)" -->
+typedef int(*)&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__if_8h.html#87b0daec8c90b013f81b4854b64dec2e">dwc_otg_hcd_complete_urb_cb_t</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, void *urb_handle, <a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *dwc_otg_urb, int32_t status)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function is called when urb is completed. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="23db00d75e435cb0cb13d1e914dfd672"></a><!-- doxytag: member="dwc_otg_hcd_if.h::dwc_otg_hcd_get_b_hnp_enable" ref="23db00d75e435cb0cb13d1e914dfd672" args="(dwc_otg_hcd_t *hcd)" -->
+typedef int(*)&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__if_8h.html#23db00d75e435cb0cb13d1e914dfd672">dwc_otg_hcd_get_b_hnp_enable</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Via this function HCD core gets b_hnp_enable parameter. <br></td></tr>
+<tr><td colspan="2"><br><h2>Typedefs</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c60760d19c9d069e3bf00b4b97b74cd3"></a><!-- doxytag: member="dwc_otg_hcd_if.h::dwc_otg_hcd_t" ref="c60760d19c9d069e3bf00b4b97b74cd3" args="" -->
+typedef <a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__if_8h.html#c60760d19c9d069e3bf00b4b97b74cd3">dwc_otg_hcd_t</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="0e7bca23553c3dfc493b44a01454a2c4"></a><!-- doxytag: member="dwc_otg_hcd_if.h::dwc_otg_hcd_urb_t" ref="0e7bca23553c3dfc493b44a01454a2c4" args="" -->
+typedef <a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__if_8h.html#0e7bca23553c3dfc493b44a01454a2c4">dwc_otg_hcd_urb_t</a></td></tr>
+
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This file defines DWC_OTG HCD Core API. 
+<p>
+
+<p>
+Definition in file <a class="el" href="dwc__otg__hcd__if_8h-source.html">dwc_otg_hcd_if.h</a>.<hr><h2>Function Documentation</h2>
+<a class="anchor" name="2d38590dadee51fd767d63e0dc675f23"></a><!-- doxytag: member="dwc_otg_hcd_if.h::dwc_otg_hcd_init" ref="2d38590dadee51fd767d63e0dc675f23" args="(dwc_otg_hcd_t *hcd, dwc_otg_core_if_t *core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_hcd_init           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function should be called to initiate HCD Core. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>The DWC_OTG Core</td></tr>
+  </table>
+</dl>
+Returns -DWC_E_NO_MEMORY if no enough memory. Returns 0 on success 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l00693">693</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="f347bcb363a622ced29161878d38830b"></a><!-- doxytag: member="dwc_otg_hcd_if.h::dwc_otg_hcd_remove" ref="f347bcb363a622ced29161878d38830b" args="(dwc_otg_hcd_t *hcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_hcd_remove           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Frees HCD. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l00778">778</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="b9dde24773f2741b9ff67e2d46760dc0"></a><!-- doxytag: member="dwc_otg_hcd_if.h::dwc_otg_hcd_handle_intr" ref="b9dde24773f2741b9ff67e2d46760dc0" args="(dwc_otg_hcd_t *dwc_otg_hcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t dwc_otg_hcd_handle_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>dwc_otg_hcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function should be called on every hardware interrupt. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd</a></em>&nbsp;</td><td>The HCD</td></tr>
+  </table>
+</dl>
+Returns non zero if interrupt is handled Return 0 if interrupt is not handled 
+<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000016">Todo:</a></b></dt><dd>Implement i2cintr handler. </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__intr_8c-source.html#l00043">43</a> of file <a class="el" href="dwc__otg__hcd__intr_8c-source.html">dwc_otg_hcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="7740268b2d0fd8d25aaaeacfa5aef5cf"></a><!-- doxytag: member="dwc_otg_hcd_if.h::dwc_otg_hcd_get_priv_data" ref="7740268b2d0fd8d25aaaeacfa5aef5cf" args="(dwc_otg_hcd_t *hcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void* dwc_otg_hcd_get_priv_data           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Returns private data set by dwc_otg_hcd_set_priv_data function. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l02671">2671</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="c73ca7d4284c8f0de7338a66607e4eb1"></a><!-- doxytag: member="dwc_otg_hcd_if.h::dwc_otg_hcd_set_priv_data" ref="c73ca7d4284c8f0de7338a66607e4eb1" args="(dwc_otg_hcd_t *hcd, void *priv_data)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_hcd_set_priv_data           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>priv_data</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Set private data. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>priv_data</em>&nbsp;</td><td>pointer to be stored in private data </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l02676">2676</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="7242be8ebc7f7516292cbe2344ab03be"></a><!-- doxytag: member="dwc_otg_hcd_if.h::dwc_otg_hcd_start" ref="7242be8ebc7f7516292cbe2344ab03be" args="(dwc_otg_hcd_t *hcd, struct dwc_otg_hcd_function_ops *fops)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_hcd_start           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">struct <a class="el" href="structdwc__otg__hcd__function__ops.html">dwc_otg_hcd_function_ops</a> *&nbsp;</td>
+          <td class="paramname"> <em>fops</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function initializes the HCD Core. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>fops</em>&nbsp;</td><td>The Function Driver Operations data structure containing pointers to all callbacks.</td></tr>
+  </table>
+</dl>
+Returns -DWC_E_NO_DEVICE if Core is currently is in device mode. Returns 0 on success 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l02656">2656</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="70c58e8a45eb7ad8ee2f2c74ba3a77f0"></a><!-- doxytag: member="dwc_otg_hcd_if.h::dwc_otg_hcd_stop" ref="70c58e8a45eb7ad8ee2f2c74ba3a77f0" args="(dwc_otg_hcd_t *hcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_hcd_stop           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Halts the DWC_otg host mode operations in a clean manner. 
+<p>
+USB transfers are stopped. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l00422">422</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="e3bd4e9d1f641cdd29df6633bfb1ebd2"></a><!-- doxytag: member="dwc_otg_hcd_if.h::dwc_otg_hcd_hub_control" ref="e3bd4e9d1f641cdd29df6633bfb1ebd2" args="(dwc_otg_hcd_t *dwc_otg_hcd, uint16_t typeReq, uint16_t wValue, uint16_t wIndex, uint8_t *buf, uint16_t wLength)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_hcd_hub_control           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>dwc_otg_hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint16_t&nbsp;</td>
+          <td class="paramname"> <em>typeReq</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint16_t&nbsp;</td>
+          <td class="paramname"> <em>wValue</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint16_t&nbsp;</td>
+          <td class="paramname"> <em>wIndex</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>buf</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint16_t&nbsp;</td>
+          <td class="paramname"> <em>wLength</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Handles hub class-specific requests. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd</a></em>&nbsp;</td><td>The HCD </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>typeReq</em>&nbsp;</td><td>Request Type </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>wValue</em>&nbsp;</td><td>wValue from control request </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>wIndex</em>&nbsp;</td><td>wIndex from control request </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>buf</em>&nbsp;</td><td>data buffer </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>wLength</em>&nbsp;</td><td>data buffer length</td></tr>
+  </table>
+</dl>
+Returns -DWC_E_INVALID if invalid argument is passed Returns 0 on success 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l01905">1905</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="e7d3657931984a1ce1cee5cf47cb08f3"></a><!-- doxytag: member="dwc_otg_hcd_if.h::dwc_otg_hcd_otg_port" ref="e7d3657931984a1ce1cee5cf47cb08f3" args="(dwc_otg_hcd_t *hcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t dwc_otg_hcd_otg_port           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Returns otg port number. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l02681">2681</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="ca25b33b440a4ef112ee459c26c14adc"></a><!-- doxytag: member="dwc_otg_hcd_if.h::dwc_otg_hcd_is_b_host" ref="ca25b33b440a4ef112ee459c26c14adc" args="(dwc_otg_hcd_t *hcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t dwc_otg_hcd_is_b_host           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Returns 1 if currently core is acting as B host, and 0 otherwise. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l02686">2686</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="65b3f4d96d1b34abaa54c3bbb32ec07f"></a><!-- doxytag: member="dwc_otg_hcd_if.h::dwc_otg_hcd_get_frame_number" ref="65b3f4d96d1b34abaa54c3bbb32ec07f" args="(dwc_otg_hcd_t *hcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_hcd_get_frame_number           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Returns current frame number. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l02643">2643</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="464f920221173fe04c756a9d6657f321"></a><!-- doxytag: member="dwc_otg_hcd_if.h::dwc_otg_hcd_dump_state" ref="464f920221173fe04c756a9d6657f321" args="(dwc_otg_hcd_t *hcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_hcd_dump_state           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Dumps hcd state. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l02815">2815</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="b2c46e92cdc57b1783f445ed60cc3f38"></a><!-- doxytag: member="dwc_otg_hcd_if.h::dwc_otg_hcd_dump_frrem" ref="b2c46e92cdc57b1783f445ed60cc3f38" args="(dwc_otg_hcd_t *hcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_hcd_dump_frrem           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Dump the average frame remaining at SOF. 
+<p>
+This can be used to determine average interrupt latency. Frame remaining is also shown for start transfer and two additional sample points. Currently this function is not implemented.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l02991">2991</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="b0c95e7f6cda9e15d767ad3ef6a7f1cc"></a><!-- doxytag: member="dwc_otg_hcd_if.h::dwc_otg_hcd_send_lpm" ref="b0c95e7f6cda9e15d767ad3ef6a7f1cc" args="(dwc_otg_hcd_t *hcd, uint8_t devaddr, uint8_t hird, uint8_t bRemoteWake)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_hcd_send_lpm           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t&nbsp;</td>
+          <td class="paramname"> <em>devaddr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t&nbsp;</td>
+          <td class="paramname"> <em>hird</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t&nbsp;</td>
+          <td class="paramname"> <em>bRemoteWake</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Sends LPM transaction to the local device. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>devaddr</em>&nbsp;</td><td>Device Address </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>hird</em>&nbsp;</td><td>Host initiated resume duration </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>bRemoteWake</em>&nbsp;</td><td>Value of bRemoteWake field in LPM transaction</td></tr>
+  </table>
+</dl>
+Returns negative value if sending LPM transaction was not succeeded. Returns 0 on success. 
+</div>
+</div><p>
+<a class="anchor" name="264fc9d293c76e42dded9dee2cf44283"></a><!-- doxytag: member="dwc_otg_hcd_if.h::dwc_otg_hcd_urb_alloc" ref="264fc9d293c76e42dded9dee2cf44283" args="(dwc_otg_hcd_t *hcd, int iso_desc_count, int atomic_alloc)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a>* dwc_otg_hcd_urb_alloc           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>iso_desc_count</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>atomic_alloc</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Allocates memory for <a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb</a> structure. 
+<p>
+Allocated memory should be freed by call dwc_free function.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>iso_desc_count</em>&nbsp;</td><td>Count of ISOC descriptors </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>atomic_alloc</em>&nbsp;</td><td>Specefies whether to perform atomic allocation. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l02698">2698</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="6c0a7bf2d1091d6e9e1ce767329fc04a"></a><!-- doxytag: member="dwc_otg_hcd_if.h::dwc_otg_hcd_urb_set_pipeinfo" ref="6c0a7bf2d1091d6e9e1ce767329fc04a" args="(dwc_otg_hcd_urb_t *hcd_urb, uint8_t devaddr, uint8_t ep_num, uint8_t ep_type, uint8_t ep_dir, uint16_t mps)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_hcd_urb_set_pipeinfo           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd_urb</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t&nbsp;</td>
+          <td class="paramname"> <em>devaddr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t&nbsp;</td>
+          <td class="paramname"> <em>ep_num</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t&nbsp;</td>
+          <td class="paramname"> <em>ep_type</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t&nbsp;</td>
+          <td class="paramname"> <em>ep_dir</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint16_t&nbsp;</td>
+          <td class="paramname"> <em>mps</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Set pipe information in URB. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd_urb</em>&nbsp;</td><td>DWC_OTG URB </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>devaddr</em>&nbsp;</td><td>Device Address </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep_num</em>&nbsp;</td><td>Endpoint Number </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep_type</em>&nbsp;</td><td>Endpoint Type </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep_dir</em>&nbsp;</td><td>Endpoint Direction </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>mps</em>&nbsp;</td><td>Max Packet Size </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l02717">2717</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="356834d51d095518b6283a343bfab2b0"></a><!-- doxytag: member="dwc_otg_hcd_if.h::dwc_otg_hcd_urb_set_params" ref="356834d51d095518b6283a343bfab2b0" args="(dwc_otg_hcd_urb_t *urb, void *urb_handle, void *buf, dwc_dma_t dma, uint32_t buflen, void *sp, dwc_dma_t sp_dma, uint32_t flags, uint16_t interval)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_hcd_urb_set_params           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>urb</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>urb_handle</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>buf</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">dwc_dma_t&nbsp;</td>
+          <td class="paramname"> <em>dma</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint32_t&nbsp;</td>
+          <td class="paramname"> <em>buflen</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>sp</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">dwc_dma_t&nbsp;</td>
+          <td class="paramname"> <em>sp_dma</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint32_t&nbsp;</td>
+          <td class="paramname"> <em>flags</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint16_t&nbsp;</td>
+          <td class="paramname"> <em>interval</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Sets <a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb</a> parameters. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>urb</em>&nbsp;</td><td>DWC_OTG URB allocated by dwc_otg_hcd_urb_alloc function. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>urb_handle</em>&nbsp;</td><td>Unique handle for request, this will be passed back to function driver in completion callback. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>buf</em>&nbsp;</td><td>The buffer for the data </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>dma</em>&nbsp;</td><td>The DMA buffer for the data </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>buflen</em>&nbsp;</td><td>Transfer length </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>sp</em>&nbsp;</td><td>Buffer for setup data </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>sp_dma</em>&nbsp;</td><td>DMA address of setup data buffer </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>flags</em>&nbsp;</td><td>Transfer flags </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>interval</em>&nbsp;</td><td>Polling interval for interrupt or isochronous transfers. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l02730">2730</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="81b7aad80889affb1e63cf1307b88fb6"></a><!-- doxytag: member="dwc_otg_hcd_if.h::dwc_otg_hcd_urb_get_status" ref="81b7aad80889affb1e63cf1307b88fb6" args="(dwc_otg_hcd_urb_t *dwc_otg_urb)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t dwc_otg_hcd_urb_get_status           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>dwc_otg_urb</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Gets status from <a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb</a>. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>dwc_otg_urb</em>&nbsp;</td><td>DWC_OTG URB </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l02747">2747</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="3260f5db4ea20074da16b292eb1a686b"></a><!-- doxytag: member="dwc_otg_hcd_if.h::dwc_otg_hcd_urb_get_actual_length" ref="3260f5db4ea20074da16b292eb1a686b" args="(dwc_otg_hcd_urb_t *dwc_otg_urb)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t dwc_otg_hcd_urb_get_actual_length           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>dwc_otg_urb</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Gets actual length from <a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb</a>. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>dwc_otg_urb</em>&nbsp;</td><td>DWC_OTG URB </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l02752">2752</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="816cc30c3129fc8911a458355d977129"></a><!-- doxytag: member="dwc_otg_hcd_if.h::dwc_otg_hcd_urb_get_error_count" ref="816cc30c3129fc8911a458355d977129" args="(dwc_otg_hcd_urb_t *dwc_otg_urb)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t dwc_otg_hcd_urb_get_error_count           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>dwc_otg_urb</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Gets error count from <a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb</a>. 
+<p>
+Only for ISOC URBs<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>dwc_otg_urb</em>&nbsp;</td><td>DWC_OTG URB </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l02757">2757</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="8617e93eba1bfd6466a9af1e6d2f731b"></a><!-- doxytag: member="dwc_otg_hcd_if.h::dwc_otg_hcd_urb_set_iso_desc_params" ref="8617e93eba1bfd6466a9af1e6d2f731b" args="(dwc_otg_hcd_urb_t *dwc_otg_urb, int desc_num, uint32_t offset, uint32_t length)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_hcd_urb_set_iso_desc_params           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>dwc_otg_urb</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>desc_num</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint32_t&nbsp;</td>
+          <td class="paramname"> <em>offset</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint32_t&nbsp;</td>
+          <td class="paramname"> <em>length</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Set ISOC descriptor offset and length. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>dwc_otg_urb</em>&nbsp;</td><td>DWC_OTG URB </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>desc_num</em>&nbsp;</td><td>ISOC descriptor number </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>offset</em>&nbsp;</td><td>Offset from beginig of buffer. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>length</em>&nbsp;</td><td>Transaction length </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l02762">2762</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="fde27182e452709e10c1100ea57aa46b"></a><!-- doxytag: member="dwc_otg_hcd_if.h::dwc_otg_hcd_urb_get_iso_desc_status" ref="fde27182e452709e10c1100ea57aa46b" args="(dwc_otg_hcd_urb_t *dwc_otg_urb, int desc_num)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t dwc_otg_hcd_urb_get_iso_desc_status           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>dwc_otg_urb</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>desc_num</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Get status of ISOC descriptor, specified by desc_num. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>dwc_otg_urb</em>&nbsp;</td><td>DWC_OTG URB </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>desc_num</em>&nbsp;</td><td>ISOC descriptor number </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l02770">2770</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="c6d28fc3e6aedb29d46a793423c4de0a"></a><!-- doxytag: member="dwc_otg_hcd_if.h::dwc_otg_hcd_urb_get_iso_desc_actual_length" ref="c6d28fc3e6aedb29d46a793423c4de0a" args="(dwc_otg_hcd_urb_t *dwc_otg_urb, int desc_num)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>dwc_otg_urb</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>desc_num</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Get actual length of ISOC descriptor, specified by desc_num. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>dwc_otg_urb</em>&nbsp;</td><td>DWC_OTG URB </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>desc_num</em>&nbsp;</td><td>ISOC descriptor number </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l02776">2776</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="e8db09c826a847ffbaf7a5e7a60b697c"></a><!-- doxytag: member="dwc_otg_hcd_if.h::dwc_otg_hcd_urb_enqueue" ref="e8db09c826a847ffbaf7a5e7a60b697c" args="(dwc_otg_hcd_t *dwc_otg_hcd, dwc_otg_hcd_urb_t *dwc_otg_urb, void **ep_handle)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_hcd_urb_enqueue           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>dwc_otg_hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>dwc_otg_urb</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void **&nbsp;</td>
+          <td class="paramname"> <em>ep_handle</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Queue URB. 
+<p>
+After transfer is completes, the complete callback will be called with the URB status<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd</a></em>&nbsp;</td><td>The HCD </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>dwc_otg_urb</em>&nbsp;</td><td>DWC_OTG URB </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep_handle</em>&nbsp;</td><td>Out parameter for returning endpoint handle</td></tr>
+  </table>
+</dl>
+Returns -DWC_E_NO_DEVICE if no device is connected. Returns -DWC_E_NO_MEMORY if there is no enough memory. Returns 0 on success. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l00444">444</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="e7377ee6d5cdb17a4213cc96bf534a23"></a><!-- doxytag: member="dwc_otg_hcd_if.h::dwc_otg_hcd_urb_dequeue" ref="e7377ee6d5cdb17a4213cc96bf534a23" args="(dwc_otg_hcd_t *dwc_otg_hcd, dwc_otg_hcd_urb_t *dwc_otg_urb)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_hcd_urb_dequeue           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>dwc_otg_hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>dwc_otg_urb</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+De-queue the specified URB. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd</a></em>&nbsp;</td><td>The HCD </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>dwc_otg_urb</em>&nbsp;</td><td>DWC_OTG URB </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l00489">489</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="f80e9550161e354c865e3c411d661dbe"></a><!-- doxytag: member="dwc_otg_hcd_if.h::dwc_otg_hcd_endpoint_disable" ref="f80e9550161e354c865e3c411d661dbe" args="(dwc_otg_hcd_t *hcd, void *ep_handle, int retry)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_hcd_endpoint_disable           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>ep_handle</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>retry</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Frees resources in the DWC_otg controller related to a given endpoint. 
+<p>
+Any URBs for the endpoint must already be dequeued.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep_handle</em>&nbsp;</td><td>Endpoint handle, returned by dwc_otg_hcd_urb_enqueue function </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>retry</em>&nbsp;</td><td>Number of retries if there are queued transfers.</td></tr>
+  </table>
+</dl>
+Returns -DWC_E_INVALID if invalid arguments are passed. Returns 0 on success 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l00547">547</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="0d324c8dbb0c7cbadec8cebf943fc84b"></a><!-- doxytag: member="dwc_otg_hcd_if.h::dwc_otg_hcd_is_status_changed" ref="0d324c8dbb0c7cbadec8cebf943fc84b" args="(dwc_otg_hcd_t *hcd, int port)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_hcd_is_status_changed           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>port</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Returns 1 if status of specified port is changed and 0 otherwise. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>port</em>&nbsp;</td><td>Port number </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l02611">2611</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="5deb69c332ba937b959c9dccadd87568"></a><!-- doxytag: member="dwc_otg_hcd_if.h::dwc_otg_hcd_is_bandwidth_allocated" ref="5deb69c332ba937b959c9dccadd87568" args="(dwc_otg_hcd_t *hcd, void *ep_handle)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_hcd_is_bandwidth_allocated           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>ep_handle</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Call this function to check if bandwidth was allocated for specified endpoint. 
+<p>
+Only for ISOC and INTERRUPT endpoints.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep_handle</em>&nbsp;</td><td>Endpoint handle </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l02782">2782</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="ad28eed057375c7f31663dc777edefd7"></a><!-- doxytag: member="dwc_otg_hcd_if.h::dwc_otg_hcd_is_bandwidth_freed" ref="ad28eed057375c7f31663dc777edefd7" args="(dwc_otg_hcd_t *hcd, void *ep_handle)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_hcd_is_bandwidth_freed           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>ep_handle</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Call this function to check if bandwidth was freed for specified endpoint. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep_handle</em>&nbsp;</td><td>Endpoint handle </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l02795">2795</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="bd160be911ccc8f90141dae9c40276eb"></a><!-- doxytag: member="dwc_otg_hcd_if.h::dwc_otg_hcd_get_ep_bandwidth" ref="bd160be911ccc8f90141dae9c40276eb" args="(dwc_otg_hcd_t *hcd, void *ep_handle)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint8_t dwc_otg_hcd_get_ep_bandwidth           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>ep_handle</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Returns bandwidth allocated for specified endpoint in microseconds. 
+<p>
+Only for ISOC and INTERRUPT endpoints.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep_handle</em>&nbsp;</td><td>Endpoint handle </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8c-source.html#l02808">2808</a> of file <a class="el" href="dwc__otg__hcd_8c-source.html">dwc_otg_hcd.c</a>.
+</div>
+</div><p>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__intr_8c-source.html b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__intr_8c-source.html
new file mode 100644
index 000000000000..797ab8c44884
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__intr_8c-source.html
@@ -0,0 +1,1873 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd_intr.c Source File</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<h1>dwc_otg_hcd_intr.c</h1><a href="dwc__otg__hcd__intr_8c.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">/* ==========================================================================</span>
+<a name="l00002"></a>00002 <span class="comment"> * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_intr.c $</span>
+<a name="l00003"></a>00003 <span class="comment"> * $Revision: #77 $</span>
+<a name="l00004"></a>00004 <span class="comment"> * $Date: 2009/04/21 $</span>
+<a name="l00005"></a>00005 <span class="comment"> * $Change: 1237475 $</span>
+<a name="l00006"></a>00006 <span class="comment"> *</span>
+<a name="l00007"></a>00007 <span class="comment"> * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,</span>
+<a name="l00008"></a>00008 <span class="comment"> * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless</span>
+<a name="l00009"></a>00009 <span class="comment"> * otherwise expressly agreed to in writing between Synopsys and you.</span>
+<a name="l00010"></a>00010 <span class="comment"> *</span>
+<a name="l00011"></a>00011 <span class="comment"> * The Software IS NOT an item of Licensed Software or Licensed Product under</span>
+<a name="l00012"></a>00012 <span class="comment"> * any End User Software License Agreement or Agreement for Licensed Product</span>
+<a name="l00013"></a>00013 <span class="comment"> * with Synopsys or any supplement thereto. You are permitted to use and</span>
+<a name="l00014"></a>00014 <span class="comment"> * redistribute this Software in source and binary forms, with or without</span>
+<a name="l00015"></a>00015 <span class="comment"> * modification, provided that redistributions of source code must retain this</span>
+<a name="l00016"></a>00016 <span class="comment"> * notice. You may not view, use, disclose, copy or distribute this file or</span>
+<a name="l00017"></a>00017 <span class="comment"> * any information contained herein except pursuant to this license grant from</span>
+<a name="l00018"></a>00018 <span class="comment"> * Synopsys. If you do not agree with this notice, including the disclaimer</span>
+<a name="l00019"></a>00019 <span class="comment"> * below, then you are not authorized to use the Software.</span>
+<a name="l00020"></a>00020 <span class="comment"> *</span>
+<a name="l00021"></a>00021 <span class="comment"> * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS</span>
+<a name="l00022"></a>00022 <span class="comment"> * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE</span>
+<a name="l00023"></a>00023 <span class="comment"> * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE</span>
+<a name="l00024"></a>00024 <span class="comment"> * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,</span>
+<a name="l00025"></a>00025 <span class="comment"> * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES</span>
+<a name="l00026"></a>00026 <span class="comment"> * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR</span>
+<a name="l00027"></a>00027 <span class="comment"> * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER</span>
+<a name="l00028"></a>00028 <span class="comment"> * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT</span>
+<a name="l00029"></a>00029 <span class="comment"> * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY</span>
+<a name="l00030"></a>00030 <span class="comment"> * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH</span>
+<a name="l00031"></a>00031 <span class="comment"> * DAMAGE.</span>
+<a name="l00032"></a>00032 <span class="comment"> * ========================================================================== */</span>
+<a name="l00033"></a>00033 <span class="preprocessor">#ifndef DWC_DEVICE_ONLY</span>
+<a name="l00034"></a>00034 <span class="preprocessor"></span>
+<a name="l00035"></a>00035 <span class="preprocessor">#include "<a class="code" href="dwc__otg__hcd_8h.html">dwc_otg_hcd.h</a>"</span>
+<a name="l00036"></a>00036 <span class="preprocessor">#include "<a class="code" href="dwc__otg__regs_8h.html">dwc_otg_regs.h</a>"</span>
+<a name="l00037"></a>00037 
+<a name="l00043"></a><a class="code" href="dwc__otg__hcd__intr_8c.html#b9dde24773f2741b9ff67e2d46760dc0">00043</a> int32_t <a class="code" href="dwc__otg__hcd_8h.html#b9dde24773f2741b9ff67e2d46760dc0">dwc_otg_hcd_handle_intr</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * <a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>)
+<a name="l00044"></a>00044 {
+<a name="l00045"></a>00045         <span class="keywordtype">int</span> retval = 0;
+<a name="l00046"></a>00046 
+<a name="l00047"></a>00047         <a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if = dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>;
+<a name="l00048"></a>00048         <a class="code" href="uniongintsts__data.html">gintsts_data_t</a> gintsts;
+<a name="l00049"></a>00049 <span class="preprocessor">#ifdef DEBUG</span>
+<a name="l00050"></a>00050 <span class="preprocessor"></span>        <a class="code" href="structdwc__otg__core__global__regs.html">dwc_otg_core_global_regs_t</a> *global_regs = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>;
+<a name="l00051"></a>00051 <span class="preprocessor">#endif</span>
+<a name="l00052"></a>00052 <span class="preprocessor"></span>
+<a name="l00053"></a>00053         <span class="comment">/* Check if HOST Mode */</span>
+<a name="l00054"></a>00054         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#f0bfe5f933e21a94ea06c96ffc086e72">dwc_otg_is_host_mode</a>(core_if)) {
+<a name="l00055"></a>00055                 gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a> = <a class="code" href="dwc__otg__cil_8h.html#639809e3c27026b8f956c2a133b1d433">dwc_otg_read_core_intr</a>(core_if);
+<a name="l00056"></a>00056                 <span class="keywordflow">if</span> (!gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a>) {
+<a name="l00057"></a>00057                         <span class="keywordflow">return</span> 0;
+<a name="l00058"></a>00058                 }
+<a name="l00059"></a>00059 <span class="preprocessor">#ifdef DEBUG</span>
+<a name="l00060"></a>00060 <span class="preprocessor"></span>                <span class="comment">/* Don't print debug message in the interrupt handler on SOF */</span>
+<a name="l00061"></a>00061 <span class="preprocessor">#ifndef DEBUG_SOF</span>
+<a name="l00062"></a>00062 <span class="preprocessor"></span>                <span class="keywordflow">if</span> (gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a> != <a class="code" href="dwc__otg__regs_8h.html#8cd1d59e0700e5b528deebdea7a7ac76">DWC_SOF_INTR_MASK</a>)
+<a name="l00063"></a>00063 <span class="preprocessor">#endif</span>
+<a name="l00064"></a>00064 <span class="preprocessor"></span>                        <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#e4a050e176c1c4f556da2b276a8c2b37">DBG_HCD</a>, <span class="stringliteral">"\n"</span>);
+<a name="l00065"></a>00065 <span class="preprocessor">#endif</span>
+<a name="l00066"></a>00066 <span class="preprocessor"></span>
+<a name="l00067"></a>00067 <span class="preprocessor">#ifdef DEBUG</span>
+<a name="l00068"></a>00068 <span class="preprocessor"></span><span class="preprocessor">#ifndef DEBUG_SOF</span>
+<a name="l00069"></a>00069 <span class="preprocessor"></span>                <span class="keywordflow">if</span> (gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a> != <a class="code" href="dwc__otg__regs_8h.html#8cd1d59e0700e5b528deebdea7a7ac76">DWC_SOF_INTR_MASK</a>)
+<a name="l00070"></a>00070 <span class="preprocessor">#endif</span>
+<a name="l00071"></a>00071 <span class="preprocessor"></span>                        <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(DBG_HCD,
+<a name="l00072"></a>00072                                     <span class="stringliteral">"DWC OTG HCD Interrupt Detected gintsts&amp;gintmsk=0x%08x\n"</span>,
+<a name="l00073"></a>00073                                     gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a>);
+<a name="l00074"></a>00074 <span class="preprocessor">#endif</span>
+<a name="l00075"></a>00075 <span class="preprocessor"></span>
+<a name="l00076"></a>00076                 <span class="keywordflow">if</span> (gintsts.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#3f6ba377d6b1449884bb4da1b155c61b">sofintr</a>) {
+<a name="l00077"></a>00077                         retval |= <a class="code" href="dwc__otg__hcd_8h.html#0eea8527657802e9cf0a62a00bd44a1d">dwc_otg_hcd_handle_sof_intr</a>(dwc_otg_hcd);
+<a name="l00078"></a>00078                 }
+<a name="l00079"></a>00079                 <span class="keywordflow">if</span> (gintsts.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#7595576956c3a0ced9ea387880943012">rxstsqlvl</a>) {
+<a name="l00080"></a>00080                         retval |=
+<a name="l00081"></a>00081                             <a class="code" href="dwc__otg__hcd_8h.html#9d979e33e04fc694a72242dec63aeb89">dwc_otg_hcd_handle_rx_status_q_level_intr</a>
+<a name="l00082"></a>00082                             (dwc_otg_hcd);
+<a name="l00083"></a>00083                 }
+<a name="l00084"></a>00084                 <span class="keywordflow">if</span> (gintsts.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#adebf5ff5bdf69a2bcf0bd4b2ba55ef4">nptxfempty</a>) {
+<a name="l00085"></a>00085                         retval |=
+<a name="l00086"></a>00086                             <a class="code" href="dwc__otg__hcd_8h.html#51c953aefbc2382adee9f585fdb26f35">dwc_otg_hcd_handle_np_tx_fifo_empty_intr</a>
+<a name="l00087"></a>00087                             (dwc_otg_hcd);
+<a name="l00088"></a>00088                 }
+<a name="l00089"></a>00089                 <span class="keywordflow">if</span> (gintsts.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#2e8bd51ad285fd46db48f9fb5bbb7993">i2cintr</a>) {
+<a name="l00091"></a>00091                 }
+<a name="l00092"></a>00092                 <span class="keywordflow">if</span> (gintsts.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#7490e48c2c93d20c182f00161f18b8e5">portintr</a>) {
+<a name="l00093"></a>00093                         retval |= <a class="code" href="dwc__otg__hcd_8h.html#18bb807c86935a45f5fe5940e5ded70c">dwc_otg_hcd_handle_port_intr</a>(dwc_otg_hcd);
+<a name="l00094"></a>00094                 }
+<a name="l00095"></a>00095                 <span class="keywordflow">if</span> (gintsts.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#e02f1a50b20ed1c4248fd76e155147e8">hcintr</a>) {
+<a name="l00096"></a>00096                         retval |= <a class="code" href="dwc__otg__hcd_8h.html#1f28e296c0bc4146da309385d95b5d7e">dwc_otg_hcd_handle_hc_intr</a>(dwc_otg_hcd);
+<a name="l00097"></a>00097                 }
+<a name="l00098"></a>00098                 <span class="keywordflow">if</span> (gintsts.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#54ed752629e9b8916507beca28d76162">ptxfempty</a>) {
+<a name="l00099"></a>00099                         retval |=
+<a name="l00100"></a>00100                             <a class="code" href="dwc__otg__hcd_8h.html#dcfa21f80c7732df9aaf3db59a86eb1d">dwc_otg_hcd_handle_perio_tx_fifo_empty_intr</a>
+<a name="l00101"></a>00101                             (dwc_otg_hcd);
+<a name="l00102"></a>00102                 }
+<a name="l00103"></a>00103 <span class="preprocessor">#ifdef DEBUG</span>
+<a name="l00104"></a>00104 <span class="preprocessor"></span><span class="preprocessor">#ifndef DEBUG_SOF</span>
+<a name="l00105"></a>00105 <span class="preprocessor"></span>                <span class="keywordflow">if</span> (gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a> != <a class="code" href="dwc__otg__regs_8h.html#8cd1d59e0700e5b528deebdea7a7ac76">DWC_SOF_INTR_MASK</a>)
+<a name="l00106"></a>00106 <span class="preprocessor">#endif</span>
+<a name="l00107"></a>00107 <span class="preprocessor"></span>                {
+<a name="l00108"></a>00108                         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(DBG_HCD,
+<a name="l00109"></a>00109                                     <span class="stringliteral">"DWC OTG HCD Finished Servicing Interrupts\n"</span>);
+<a name="l00110"></a>00110                         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"DWC OTG HCD gintsts=0x%08x\n"</span>,
+<a name="l00111"></a>00111                                     dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>));
+<a name="l00112"></a>00112                         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"DWC OTG HCD gintmsk=0x%08x\n"</span>,
+<a name="l00113"></a>00113                                     dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#48827c76da2c6b18f369e2f2483cc4b6">gintmsk</a>));
+<a name="l00114"></a>00114                 }
+<a name="l00115"></a>00115 <span class="preprocessor">#endif</span>
+<a name="l00116"></a>00116 <span class="preprocessor"></span>
+<a name="l00117"></a>00117 <span class="preprocessor">#ifdef DEBUG</span>
+<a name="l00118"></a>00118 <span class="preprocessor"></span><span class="preprocessor">#ifndef DEBUG_SOF</span>
+<a name="l00119"></a>00119 <span class="preprocessor"></span>                <span class="keywordflow">if</span> (gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a> != <a class="code" href="dwc__otg__regs_8h.html#8cd1d59e0700e5b528deebdea7a7ac76">DWC_SOF_INTR_MASK</a>)
+<a name="l00120"></a>00120 <span class="preprocessor">#endif</span>
+<a name="l00121"></a>00121 <span class="preprocessor"></span>                        <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(DBG_HCD, <span class="stringliteral">"\n"</span>);
+<a name="l00122"></a>00122 <span class="preprocessor">#endif</span>
+<a name="l00123"></a>00123 <span class="preprocessor"></span>
+<a name="l00124"></a>00124         }
+<a name="l00125"></a>00125 
+<a name="l00126"></a>00126         <span class="keywordflow">return</span> retval;
+<a name="l00127"></a>00127 }
+<a name="l00128"></a>00128 
+<a name="l00129"></a>00129 <span class="preprocessor">#ifdef DWC_TRACK_MISSED_SOFS</span>
+<a name="l00130"></a>00130 <span class="preprocessor"></span><span class="preprocessor">#warning Compiling code to track missed SOFs</span>
+<a name="l00131"></a>00131 <span class="preprocessor"></span><span class="preprocessor">#define FRAME_NUM_ARRAY_SIZE 1000</span>
+<a name="l00132"></a>00132 <span class="preprocessor"></span>
+<a name="l00135"></a>00135 <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">void</span> track_missed_sofs(uint16_t curr_frame_number)
+<a name="l00136"></a>00136 {
+<a name="l00137"></a>00137         <span class="keyword">static</span> uint16_t frame_num_array[FRAME_NUM_ARRAY_SIZE];
+<a name="l00138"></a>00138         <span class="keyword">static</span> uint16_t last_frame_num_array[FRAME_NUM_ARRAY_SIZE];
+<a name="l00139"></a>00139         <span class="keyword">static</span> <span class="keywordtype">int</span> frame_num_idx = 0;
+<a name="l00140"></a>00140         <span class="keyword">static</span> uint16_t last_frame_num = <a class="code" href="dwc__otg__regs_8h.html#4903938414e67044883b7df5582d6eed">DWC_HFNUM_MAX_FRNUM</a>;
+<a name="l00141"></a>00141         <span class="keyword">static</span> <span class="keywordtype">int</span> dumped_frame_num_array = 0;
+<a name="l00142"></a>00142 
+<a name="l00143"></a>00143         <span class="keywordflow">if</span> (frame_num_idx &lt; FRAME_NUM_ARRAY_SIZE) {
+<a name="l00144"></a>00144                 <span class="keywordflow">if</span> (((last_frame_num + 1) &amp; <a class="code" href="dwc__otg__regs_8h.html#4903938414e67044883b7df5582d6eed">DWC_HFNUM_MAX_FRNUM</a>) !=
+<a name="l00145"></a>00145                     curr_frame_number) {
+<a name="l00146"></a>00146                         frame_num_array[frame_num_idx] = curr_frame_number;
+<a name="l00147"></a>00147                         last_frame_num_array[frame_num_idx++] = last_frame_num;
+<a name="l00148"></a>00148                 }
+<a name="l00149"></a>00149         } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (!dumped_frame_num_array) {
+<a name="l00150"></a>00150                 <span class="keywordtype">int</span> i;
+<a name="l00151"></a>00151                 DWC_PRINTF(<span class="stringliteral">"Frame     Last Frame\n"</span>);
+<a name="l00152"></a>00152                 DWC_PRINTF(<span class="stringliteral">"-----     ----------\n"</span>);
+<a name="l00153"></a>00153                 <span class="keywordflow">for</span> (i = 0; i &lt; FRAME_NUM_ARRAY_SIZE; i++) {
+<a name="l00154"></a>00154                         DWC_PRINTF(<span class="stringliteral">"0x%04x    0x%04x\n"</span>,
+<a name="l00155"></a>00155                                    frame_num_array[i], last_frame_num_array[i]);
+<a name="l00156"></a>00156                 }
+<a name="l00157"></a>00157                 dumped_frame_num_array = 1;
+<a name="l00158"></a>00158         }
+<a name="l00159"></a>00159         last_frame_num = curr_frame_number;
+<a name="l00160"></a>00160 }
+<a name="l00161"></a>00161 <span class="preprocessor">#endif</span>
+<a name="l00162"></a>00162 <span class="preprocessor"></span>
+<a name="l00169"></a><a class="code" href="dwc__otg__hcd__intr_8c.html#bbf5740390826d69bba80651ef9bd725">00169</a> int32_t <a class="code" href="dwc__otg__hcd_8h.html#0eea8527657802e9cf0a62a00bd44a1d">dwc_otg_hcd_handle_sof_intr</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd)
+<a name="l00170"></a>00170 {
+<a name="l00171"></a>00171         <a class="code" href="unionhfnum__data.html">hfnum_data_t</a> hfnum;
+<a name="l00172"></a>00172         dwc_list_link_t *qh_entry;
+<a name="l00173"></a>00173         <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *qh;
+<a name="l00174"></a>00174         <a class="code" href="dwc__otg__hcd_8h.html#92c49783eebc5bcffa8b8a51c2127be9">dwc_otg_transaction_type_e</a> tr_type;
+<a name="l00175"></a>00175         <a class="code" href="uniongintsts__data.html">gintsts_data_t</a> gintsts = {.d32 = 0 };
+<a name="l00176"></a>00176 
+<a name="l00177"></a>00177         hfnum.<a class="code" href="unionhfnum__data.html#e5ccbed3af86ac88577ded328e6c9932">d32</a> =
+<a name="l00178"></a>00178             dwc_read_reg32(&amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#ff9692c2e10ca2bc7e24f981f25179c2">host_global_regs</a>-&gt;<a class="code" href="structdwc__otg__host__global__regs.html#cebb0d86d0776473ef30eeac61e8692c">hfnum</a>);
+<a name="l00179"></a>00179 
+<a name="l00180"></a>00180 <span class="preprocessor">#ifdef DEBUG_SOF</span>
+<a name="l00181"></a>00181 <span class="preprocessor"></span>        <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#e4a050e176c1c4f556da2b276a8c2b37">DBG_HCD</a>, <span class="stringliteral">"--Start of Frame Interrupt--\n"</span>);
+<a name="l00182"></a>00182 <span class="preprocessor">#endif</span>
+<a name="l00183"></a>00183 <span class="preprocessor"></span>        hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#f79fefeb7908c0ddf702331253acb292">frame_number</a> = hfnum.<a class="code" href="unionhfnum__data.html#81df6fbd20a454665803eb5790855c66">b</a>.<a class="code" href="unionhfnum__data.html#a64e8b6c4a1cd262dbc30e158f3cb8bc">frnum</a>;
+<a name="l00184"></a>00184 
+<a name="l00185"></a>00185 <span class="preprocessor">#ifdef DEBUG</span>
+<a name="l00186"></a>00186 <span class="preprocessor"></span>        hcd-&gt;frrem_accum += hfnum.<a class="code" href="unionhfnum__data.html#81df6fbd20a454665803eb5790855c66">b</a>.<a class="code" href="unionhfnum__data.html#2a2ce50ebd4c4da5347a2d93c4bbc996">frrem</a>;
+<a name="l00187"></a>00187         hcd-&gt;frrem_samples++;
+<a name="l00188"></a>00188 <span class="preprocessor">#endif</span>
+<a name="l00189"></a>00189 <span class="preprocessor"></span>
+<a name="l00190"></a>00190 <span class="preprocessor">#ifdef DWC_TRACK_MISSED_SOFS</span>
+<a name="l00191"></a>00191 <span class="preprocessor"></span>        track_missed_sofs(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#f79fefeb7908c0ddf702331253acb292">frame_number</a>);
+<a name="l00192"></a>00192 <span class="preprocessor">#endif</span>
+<a name="l00193"></a>00193 <span class="preprocessor"></span>        <span class="comment">/* Determine whether any periodic QHs should be executed. */</span>
+<a name="l00194"></a>00194         qh_entry = DWC_LIST_FIRST(&amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#2a747cacd6bdbacbef86d4157c34a312">periodic_sched_inactive</a>);
+<a name="l00195"></a>00195         <span class="keywordflow">while</span> (qh_entry != &amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#2a747cacd6bdbacbef86d4157c34a312">periodic_sched_inactive</a>) {
+<a name="l00196"></a>00196                 qh = DWC_LIST_ENTRY(qh_entry, <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a>, qh_list_entry);
+<a name="l00197"></a>00197                 qh_entry = qh_entry-&gt;next;
+<a name="l00198"></a>00198                 <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__hcd_8h.html#02aa5e9853fcc705b9b5c839a249e2f8">dwc_frame_num_le</a>(qh-&gt;<a class="code" href="structdwc__otg__qh.html#977a8032f08e45a9e9bdcd558a6965d3">sched_frame</a>, hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#f79fefeb7908c0ddf702331253acb292">frame_number</a>)) {
+<a name="l00199"></a>00199                         <span class="comment">/*</span>
+<a name="l00200"></a>00200 <span class="comment">                         * Move QH to the ready list to be executed next</span>
+<a name="l00201"></a>00201 <span class="comment">                         * (micro)frame.</span>
+<a name="l00202"></a>00202 <span class="comment">                         */</span>
+<a name="l00203"></a>00203                         DWC_LIST_MOVE_HEAD(&amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#74b089e094911a558f7b5f24681d3242">periodic_sched_ready</a>,
+<a name="l00204"></a>00204                                            &amp;qh-&gt;<a class="code" href="structdwc__otg__qh.html#3e1cb9863dc72139e1832c04244c25ff">qh_list_entry</a>);
+<a name="l00205"></a>00205                 }
+<a name="l00206"></a>00206         }
+<a name="l00207"></a>00207         tr_type = <a class="code" href="dwc__otg__hcd_8c.html#96cc299f4f0478187ed7ba49b975ffc3">dwc_otg_hcd_select_transactions</a>(hcd);
+<a name="l00208"></a>00208         <span class="keywordflow">if</span> (tr_type != DWC_OTG_TRANSACTION_NONE) {
+<a name="l00209"></a>00209                 <a class="code" href="dwc__otg__hcd_8c.html#2f57bf2fc3013d63101f112702b913a0">dwc_otg_hcd_queue_transactions</a>(hcd, tr_type);
+<a name="l00210"></a>00210         }
+<a name="l00211"></a>00211 
+<a name="l00212"></a>00212         <span class="comment">/* Clear interrupt */</span>
+<a name="l00213"></a>00213         gintsts.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#3f6ba377d6b1449884bb4da1b155c61b">sofintr</a> = 1;
+<a name="l00214"></a>00214         dwc_write_reg32(&amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>, gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a>);
+<a name="l00215"></a>00215 
+<a name="l00216"></a>00216         <span class="keywordflow">return</span> 1;
+<a name="l00217"></a>00217 }
+<a name="l00218"></a>00218 
+<a name="l00222"></a><a class="code" href="dwc__otg__hcd__intr_8c.html#9d979e33e04fc694a72242dec63aeb89">00222</a> int32_t <a class="code" href="dwc__otg__hcd_8h.html#9d979e33e04fc694a72242dec63aeb89">dwc_otg_hcd_handle_rx_status_q_level_intr</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * <a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>)
+<a name="l00223"></a>00223 {
+<a name="l00224"></a>00224         <a class="code" href="unionhost__grxsts__data.html">host_grxsts_data_t</a> grxsts;
+<a name="l00225"></a>00225         <a class="code" href="structdwc__hc.html">dwc_hc_t</a> *hc = NULL;
+<a name="l00226"></a>00226 
+<a name="l00227"></a>00227         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#e4a050e176c1c4f556da2b276a8c2b37">DBG_HCD</a>, <span class="stringliteral">"--RxStsQ Level Interrupt--\n"</span>);
+<a name="l00228"></a>00228 
+<a name="l00229"></a>00229         grxsts.<a class="code" href="unionhost__grxsts__data.html#993969735da9c3615652391aae76359a">d32</a> =
+<a name="l00230"></a>00230             dwc_read_reg32(&amp;dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#763b05035799e1c16d34957fb62a2d17">grxstsp</a>);
+<a name="l00231"></a>00231 
+<a name="l00232"></a>00232         hc = dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#cb393f6a676fb106e0e3d35396fb97f9">hc_ptr_array</a>[grxsts.<a class="code" href="unionhost__grxsts__data.html#9d67ba193008dd6afa7fe613c665238d">b</a>.<a class="code" href="unionhost__grxsts__data.html#684095394d11ec74a327f945c9e678bf">chnum</a>];
+<a name="l00233"></a>00233 
+<a name="l00234"></a>00234         <span class="comment">/* Packet Status */</span>
+<a name="l00235"></a>00235         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"    Ch num = %d\n"</span>, grxsts.<a class="code" href="unionhost__grxsts__data.html#9d67ba193008dd6afa7fe613c665238d">b</a>.<a class="code" href="unionhost__grxsts__data.html#684095394d11ec74a327f945c9e678bf">chnum</a>);
+<a name="l00236"></a>00236         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"    Count = %d\n"</span>, grxsts.<a class="code" href="unionhost__grxsts__data.html#9d67ba193008dd6afa7fe613c665238d">b</a>.<a class="code" href="unionhost__grxsts__data.html#026fd4d8ab68825fab038c083b8e9c60">bcnt</a>);
+<a name="l00237"></a>00237         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"    DPID = %d, hc.dpid = %d\n"</span>, grxsts.<a class="code" href="unionhost__grxsts__data.html#9d67ba193008dd6afa7fe613c665238d">b</a>.<a class="code" href="unionhost__grxsts__data.html#5c4ca6a6c4a85064dd024095607a634d">dpid</a>,
+<a name="l00238"></a>00238                     hc-&gt;<a class="code" href="structdwc__hc.html#513427c5e8c4603ba344d4e7f9191064">data_pid_start</a>);
+<a name="l00239"></a>00239         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"    PStatus = %d\n"</span>, grxsts.<a class="code" href="unionhost__grxsts__data.html#9d67ba193008dd6afa7fe613c665238d">b</a>.<a class="code" href="unionhost__grxsts__data.html#6dc2553475a56a445c6e6f319feffac8">pktsts</a>);
+<a name="l00240"></a>00240 
+<a name="l00241"></a>00241         <span class="keywordflow">switch</span> (grxsts.<a class="code" href="unionhost__grxsts__data.html#9d67ba193008dd6afa7fe613c665238d">b</a>.<a class="code" href="unionhost__grxsts__data.html#6dc2553475a56a445c6e6f319feffac8">pktsts</a>) {
+<a name="l00242"></a>00242         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__regs_8h.html#d81c89ef7c3e40cfffe9ed08b7136e90">DWC_GRXSTS_PKTSTS_IN</a>:
+<a name="l00243"></a>00243                 <span class="comment">/* Read the data into the host buffer. */</span>
+<a name="l00244"></a>00244                 <span class="keywordflow">if</span> (grxsts.<a class="code" href="unionhost__grxsts__data.html#9d67ba193008dd6afa7fe613c665238d">b</a>.<a class="code" href="unionhost__grxsts__data.html#026fd4d8ab68825fab038c083b8e9c60">bcnt</a> &gt; 0) {
+<a name="l00245"></a>00245                         <a class="code" href="dwc__otg__cil_8c.html#68f59dd23ccfffa9aa1dc590e99b7668">dwc_otg_read_packet</a>(dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>,
+<a name="l00246"></a>00246                                             hc-&gt;<a class="code" href="structdwc__hc.html#9dc781cb9e4bc639765beee37ce76673">xfer_buff</a>, grxsts.<a class="code" href="unionhost__grxsts__data.html#9d67ba193008dd6afa7fe613c665238d">b</a>.<a class="code" href="unionhost__grxsts__data.html#026fd4d8ab68825fab038c083b8e9c60">bcnt</a>);
+<a name="l00247"></a>00247 
+<a name="l00248"></a>00248                         <span class="comment">/* Update the HC fields for the next packet received. */</span>
+<a name="l00249"></a>00249                         hc-&gt;<a class="code" href="structdwc__hc.html#6199aaeab2d64954311c410b30270293">xfer_count</a> += grxsts.<a class="code" href="unionhost__grxsts__data.html#9d67ba193008dd6afa7fe613c665238d">b</a>.<a class="code" href="unionhost__grxsts__data.html#026fd4d8ab68825fab038c083b8e9c60">bcnt</a>;
+<a name="l00250"></a>00250                         hc-&gt;<a class="code" href="structdwc__hc.html#9dc781cb9e4bc639765beee37ce76673">xfer_buff</a> += grxsts.<a class="code" href="unionhost__grxsts__data.html#9d67ba193008dd6afa7fe613c665238d">b</a>.<a class="code" href="unionhost__grxsts__data.html#026fd4d8ab68825fab038c083b8e9c60">bcnt</a>;
+<a name="l00251"></a>00251                 }
+<a name="l00252"></a>00252 
+<a name="l00253"></a>00253         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__regs_8h.html#c5c019a36ea5cb66d3cb436292d8c3de">DWC_GRXSTS_PKTSTS_IN_XFER_COMP</a>:
+<a name="l00254"></a>00254         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__regs_8h.html#63be63fa3258a785d81ded62ab27b30d">DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR</a>:
+<a name="l00255"></a>00255         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__regs_8h.html#a6d1e988dc17e285244c4e587440cbef">DWC_GRXSTS_PKTSTS_CH_HALTED</a>:
+<a name="l00256"></a>00256                 <span class="comment">/* Handled in interrupt, just ignore data */</span>
+<a name="l00257"></a>00257                 <span class="keywordflow">break</span>;
+<a name="l00258"></a>00258         <span class="keywordflow">default</span>:
+<a name="l00259"></a>00259                 DWC_ERROR(<span class="stringliteral">"RX_STS_Q Interrupt: Unknown status %d\n"</span>,
+<a name="l00260"></a>00260                           grxsts.<a class="code" href="unionhost__grxsts__data.html#9d67ba193008dd6afa7fe613c665238d">b</a>.<a class="code" href="unionhost__grxsts__data.html#6dc2553475a56a445c6e6f319feffac8">pktsts</a>);
+<a name="l00261"></a>00261                 <span class="keywordflow">break</span>;
+<a name="l00262"></a>00262         }
+<a name="l00263"></a>00263 
+<a name="l00264"></a>00264         <span class="keywordflow">return</span> 1;
+<a name="l00265"></a>00265 }
+<a name="l00266"></a>00266 
+<a name="l00271"></a><a class="code" href="dwc__otg__hcd__intr_8c.html#51c953aefbc2382adee9f585fdb26f35">00271</a> int32_t <a class="code" href="dwc__otg__hcd_8h.html#51c953aefbc2382adee9f585fdb26f35">dwc_otg_hcd_handle_np_tx_fifo_empty_intr</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * <a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>)
+<a name="l00272"></a>00272 {
+<a name="l00273"></a>00273         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#e4a050e176c1c4f556da2b276a8c2b37">DBG_HCD</a>, <span class="stringliteral">"--Non-Periodic TxFIFO Empty Interrupt--\n"</span>);
+<a name="l00274"></a>00274         <a class="code" href="dwc__otg__hcd_8c.html#2f57bf2fc3013d63101f112702b913a0">dwc_otg_hcd_queue_transactions</a>(dwc_otg_hcd,
+<a name="l00275"></a>00275                                        DWC_OTG_TRANSACTION_NON_PERIODIC);
+<a name="l00276"></a>00276         <span class="keywordflow">return</span> 1;
+<a name="l00277"></a>00277 }
+<a name="l00278"></a>00278 
+<a name="l00283"></a><a class="code" href="dwc__otg__hcd__intr_8c.html#dcfa21f80c7732df9aaf3db59a86eb1d">00283</a> int32_t <a class="code" href="dwc__otg__hcd_8h.html#dcfa21f80c7732df9aaf3db59a86eb1d">dwc_otg_hcd_handle_perio_tx_fifo_empty_intr</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * <a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>)
+<a name="l00284"></a>00284 {
+<a name="l00285"></a>00285         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#e4a050e176c1c4f556da2b276a8c2b37">DBG_HCD</a>, <span class="stringliteral">"--Periodic TxFIFO Empty Interrupt--\n"</span>);
+<a name="l00286"></a>00286         <a class="code" href="dwc__otg__hcd_8c.html#2f57bf2fc3013d63101f112702b913a0">dwc_otg_hcd_queue_transactions</a>(dwc_otg_hcd,
+<a name="l00287"></a>00287                                        DWC_OTG_TRANSACTION_PERIODIC);
+<a name="l00288"></a>00288         <span class="keywordflow">return</span> 1;
+<a name="l00289"></a>00289 }
+<a name="l00290"></a>00290 
+<a name="l00294"></a><a class="code" href="dwc__otg__hcd__intr_8c.html#18bb807c86935a45f5fe5940e5ded70c">00294</a> int32_t <a class="code" href="dwc__otg__hcd_8h.html#18bb807c86935a45f5fe5940e5ded70c">dwc_otg_hcd_handle_port_intr</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * <a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>)
+<a name="l00295"></a>00295 {
+<a name="l00296"></a>00296         <span class="keywordtype">int</span> retval = 0;
+<a name="l00297"></a>00297         <a class="code" href="unionhprt0__data.html">hprt0_data_t</a> hprt0;
+<a name="l00298"></a>00298         <a class="code" href="unionhprt0__data.html">hprt0_data_t</a> hprt0_modify;
+<a name="l00299"></a>00299 
+<a name="l00300"></a>00300         hprt0.<a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a> = dwc_read_reg32(dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#dc8fe33e0bb3829cafa884d5fc603c4d">hprt0</a>);
+<a name="l00301"></a>00301         hprt0_modify.<a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a> = dwc_read_reg32(dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#dc8fe33e0bb3829cafa884d5fc603c4d">hprt0</a>);
+<a name="l00302"></a>00302 
+<a name="l00303"></a>00303         <span class="comment">/* Clear appropriate bits in HPRT0 to clear the interrupt bit in</span>
+<a name="l00304"></a>00304 <span class="comment">         * GINTSTS */</span>
+<a name="l00305"></a>00305 
+<a name="l00306"></a>00306         hprt0_modify.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#a964274b5d22e89ca4490f66dff3c763">prtena</a> = 0;
+<a name="l00307"></a>00307         hprt0_modify.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#5124a40eeafd92c9632c91a2c3132937">prtconndet</a> = 0;
+<a name="l00308"></a>00308         hprt0_modify.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#75eae10eb537e49cc1ae2dc01c18aa47">prtenchng</a> = 0;
+<a name="l00309"></a>00309         hprt0_modify.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#cc51da1d52cb824d419ef3feb6ba70b6">prtovrcurrchng</a> = 0;
+<a name="l00310"></a>00310 
+<a name="l00311"></a>00311         <span class="comment">/* Port Connect Detected</span>
+<a name="l00312"></a>00312 <span class="comment">         * Set flag and clear if detected */</span>
+<a name="l00313"></a>00313         <span class="keywordflow">if</span> (hprt0.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#5124a40eeafd92c9632c91a2c3132937">prtconndet</a>) {
+<a name="l00314"></a>00314                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#e4a050e176c1c4f556da2b276a8c2b37">DBG_HCD</a>, <span class="stringliteral">"--Port Interrupt HPRT0=0x%08x "</span>
+<a name="l00315"></a>00315                             <span class="stringliteral">"Port Connect Detected--\n"</span>, hprt0.<a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a>);
+<a name="l00316"></a>00316                 dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#9aaf2a112f5794f92dedd826342bd637">flags</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#76f573861d9316238ded198c58c228c7">b</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#cd31ac4b9658265e90773448f354f0e1">port_connect_status_change</a> = 1;
+<a name="l00317"></a>00317                 dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#9aaf2a112f5794f92dedd826342bd637">flags</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#76f573861d9316238ded198c58c228c7">b</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#9314ac02ed140807687793b512f78c63">port_connect_status</a> = 1;
+<a name="l00318"></a>00318                 hprt0_modify.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#5124a40eeafd92c9632c91a2c3132937">prtconndet</a> = 1;
+<a name="l00319"></a>00319 
+<a name="l00320"></a>00320                 <span class="comment">/* B-Device has connected, Delete the connection timer. */</span>
+<a name="l00321"></a>00321                 DWC_TIMER_CANCEL(dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#de7796a41bb7d1e45ed9dbc20c995342">conn_timer</a>);
+<a name="l00322"></a>00322 
+<a name="l00323"></a>00323                 <span class="comment">/* The Hub driver asserts a reset when it sees port connect</span>
+<a name="l00324"></a>00324 <span class="comment">                 * status change flag */</span>
+<a name="l00325"></a>00325                 retval |= 1;
+<a name="l00326"></a>00326         }
+<a name="l00327"></a>00327 
+<a name="l00328"></a>00328         <span class="comment">/* Port Enable Changed</span>
+<a name="l00329"></a>00329 <span class="comment">         * Clear if detected - Set internal flag if disabled */</span>
+<a name="l00330"></a>00330         <span class="keywordflow">if</span> (hprt0.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#75eae10eb537e49cc1ae2dc01c18aa47">prtenchng</a>) {
+<a name="l00331"></a>00331                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#e4a050e176c1c4f556da2b276a8c2b37">DBG_HCD</a>, <span class="stringliteral">"  --Port Interrupt HPRT0=0x%08x "</span>
+<a name="l00332"></a>00332                             <span class="stringliteral">"Port Enable Changed--\n"</span>, hprt0.<a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a>);
+<a name="l00333"></a>00333                 hprt0_modify.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#75eae10eb537e49cc1ae2dc01c18aa47">prtenchng</a> = 1;
+<a name="l00334"></a>00334                 <span class="keywordflow">if</span> (hprt0.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#a964274b5d22e89ca4490f66dff3c763">prtena</a> == 1) {
+<a name="l00335"></a>00335                         <span class="keywordtype">int</span> do_reset = 0;
+<a name="l00336"></a>00336                         <a class="code" href="structdwc__otg__core__params.html">dwc_otg_core_params_t</a> *params =
+<a name="l00337"></a>00337                             dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>;
+<a name="l00338"></a>00338                         <a class="code" href="structdwc__otg__core__global__regs.html">dwc_otg_core_global_regs_t</a> *global_regs =
+<a name="l00339"></a>00339                             dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>;
+<a name="l00340"></a>00340                         <a class="code" href="structdwc__otg__host__if.html">dwc_otg_host_if_t</a> *host_if =
+<a name="l00341"></a>00341                             dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>;
+<a name="l00342"></a>00342 
+<a name="l00343"></a>00343                         <span class="comment">/* Check if we need to adjust the PHY clock speed for</span>
+<a name="l00344"></a>00344 <span class="comment">                         * low power and adjust it */</span>
+<a name="l00345"></a>00345                         <span class="keywordflow">if</span> (params-&gt;<a class="code" href="structdwc__otg__core__params.html#85cad588a450b8497347af9cf166bfde">host_support_fs_ls_low_power</a>) {
+<a name="l00346"></a>00346                                 <a class="code" href="uniongusbcfg__data.html">gusbcfg_data_t</a> usbcfg;
+<a name="l00347"></a>00347 
+<a name="l00348"></a>00348                                 usbcfg.<a class="code" href="uniongusbcfg__data.html#c3d8f2d95fd61a172eb108cb72a85b47">d32</a> =
+<a name="l00349"></a>00349                                     dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#ef39e181e246447df47c56aa4e37cc42">gusbcfg</a>);
+<a name="l00350"></a>00350 
+<a name="l00351"></a>00351                                 <span class="keywordflow">if</span> (hprt0.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#59f1c27b8c912de0237d2d2974fc2a22">prtspd</a> == <a class="code" href="dwc__otg__regs_8h.html#db9e36d1ab76c334f6e004ee270bd36f">DWC_HPRT0_PRTSPD_LOW_SPEED</a>
+<a name="l00352"></a>00352                                     || hprt0.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#59f1c27b8c912de0237d2d2974fc2a22">prtspd</a> ==
+<a name="l00353"></a>00353                                     <a class="code" href="dwc__otg__regs_8h.html#1d144361f6655bb79e7503e7159e6be5">DWC_HPRT0_PRTSPD_FULL_SPEED</a>) {
+<a name="l00354"></a>00354                                         <span class="comment">/*</span>
+<a name="l00355"></a>00355 <span class="comment">                                         * Low power</span>
+<a name="l00356"></a>00356 <span class="comment">                                         */</span>
+<a name="l00357"></a>00357                                         <a class="code" href="unionhcfg__data.html">hcfg_data_t</a> hcfg;
+<a name="l00358"></a>00358                                         <span class="keywordflow">if</span> (usbcfg.<a class="code" href="uniongusbcfg__data.html#1dab81bf7260b1e23f97298c34abea06">b</a>.<a class="code" href="uniongusbcfg__data.html#9e4bac4a0ef0a045f97792f68c5f35df">phylpwrclksel</a> == 0) {
+<a name="l00359"></a>00359                                                 <span class="comment">/* Set PHY low power clock select for FS/LS devices */</span>
+<a name="l00360"></a>00360                                                 usbcfg.<a class="code" href="uniongusbcfg__data.html#1dab81bf7260b1e23f97298c34abea06">b</a>.<a class="code" href="uniongusbcfg__data.html#9e4bac4a0ef0a045f97792f68c5f35df">phylpwrclksel</a> = 1;
+<a name="l00361"></a>00361                                                 dwc_write_reg32(&amp;global_regs-&gt;
+<a name="l00362"></a>00362                                                                 gusbcfg,
+<a name="l00363"></a>00363                                                                 usbcfg.<a class="code" href="uniongusbcfg__data.html#c3d8f2d95fd61a172eb108cb72a85b47">d32</a>);
+<a name="l00364"></a>00364                                                 do_reset = 1;
+<a name="l00365"></a>00365                                         }
+<a name="l00366"></a>00366 
+<a name="l00367"></a>00367                                         hcfg.<a class="code" href="unionhcfg__data.html#381a253b3a38a7f943dcbb42f7bf10be">d32</a> =
+<a name="l00368"></a>00368                                             dwc_read_reg32(&amp;host_if-&gt;
+<a name="l00369"></a>00369                                                            host_global_regs-&gt;hcfg);
+<a name="l00370"></a>00370 
+<a name="l00371"></a>00371                                         <span class="keywordflow">if</span> (hprt0.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#59f1c27b8c912de0237d2d2974fc2a22">prtspd</a> ==
+<a name="l00372"></a>00372                                             <a class="code" href="dwc__otg__regs_8h.html#db9e36d1ab76c334f6e004ee270bd36f">DWC_HPRT0_PRTSPD_LOW_SPEED</a>
+<a name="l00373"></a>00373                                             &amp;&amp; params-&gt;
+<a name="l00374"></a>00374                                             host_ls_low_power_phy_clk ==
+<a name="l00375"></a>00375                                             <a class="code" href="dwc__otg__core__if_8h.html#5037c1f130bf6b40970dbf9a498fb918">DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ</a>)
+<a name="l00376"></a>00376                                         {
+<a name="l00377"></a>00377                                                 <span class="comment">/* 6 MHZ */</span>
+<a name="l00378"></a>00378                                                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">DBG_CIL</a>,
+<a name="l00379"></a>00379                                                             <span class="stringliteral">"FS_PHY programming HCFG to 6 MHz (Low Power)\n"</span>);
+<a name="l00380"></a>00380                                                 <span class="keywordflow">if</span> (hcfg.<a class="code" href="unionhcfg__data.html#45bbb24387d58961dd2b8f2f65689bd7">b</a>.<a class="code" href="unionhcfg__data.html#e048ad3775c6794c3ee07af86079fadf">fslspclksel</a> !=
+<a name="l00381"></a>00381                                                     <a class="code" href="dwc__otg__regs_8h.html#40a20b71af7ff9f23a2241a2e4c3c819">DWC_HCFG_6_MHZ</a>) {
+<a name="l00382"></a>00382                                                         hcfg.<a class="code" href="unionhcfg__data.html#45bbb24387d58961dd2b8f2f65689bd7">b</a>.<a class="code" href="unionhcfg__data.html#e048ad3775c6794c3ee07af86079fadf">fslspclksel</a> =
+<a name="l00383"></a>00383                                                             <a class="code" href="dwc__otg__regs_8h.html#40a20b71af7ff9f23a2241a2e4c3c819">DWC_HCFG_6_MHZ</a>;
+<a name="l00384"></a>00384                                                         dwc_write_reg32
+<a name="l00385"></a>00385                                                             (&amp;host_if-&gt;
+<a name="l00386"></a>00386                                                              host_global_regs-&gt;
+<a name="l00387"></a>00387                                                              hcfg, hcfg.<a class="code" href="unionhcfg__data.html#381a253b3a38a7f943dcbb42f7bf10be">d32</a>);
+<a name="l00388"></a>00388                                                         do_reset = 1;
+<a name="l00389"></a>00389                                                 }
+<a name="l00390"></a>00390                                         } <span class="keywordflow">else</span> {
+<a name="l00391"></a>00391                                                 <span class="comment">/* 48 MHZ */</span>
+<a name="l00392"></a>00392                                                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">DBG_CIL</a>,
+<a name="l00393"></a>00393                                                             <span class="stringliteral">"FS_PHY programming HCFG to 48 MHz ()\n"</span>);
+<a name="l00394"></a>00394                                                 <span class="keywordflow">if</span> (hcfg.<a class="code" href="unionhcfg__data.html#45bbb24387d58961dd2b8f2f65689bd7">b</a>.<a class="code" href="unionhcfg__data.html#e048ad3775c6794c3ee07af86079fadf">fslspclksel</a> !=
+<a name="l00395"></a>00395                                                     <a class="code" href="dwc__otg__regs_8h.html#556ba73fd9346d666a7c0a28fcf993a7">DWC_HCFG_48_MHZ</a>) {
+<a name="l00396"></a>00396                                                         hcfg.<a class="code" href="unionhcfg__data.html#45bbb24387d58961dd2b8f2f65689bd7">b</a>.<a class="code" href="unionhcfg__data.html#e048ad3775c6794c3ee07af86079fadf">fslspclksel</a> =
+<a name="l00397"></a>00397                                                             <a class="code" href="dwc__otg__regs_8h.html#556ba73fd9346d666a7c0a28fcf993a7">DWC_HCFG_48_MHZ</a>;
+<a name="l00398"></a>00398                                                         dwc_write_reg32
+<a name="l00399"></a>00399                                                             (&amp;host_if-&gt;
+<a name="l00400"></a>00400                                                              host_global_regs-&gt;
+<a name="l00401"></a>00401                                                              hcfg, hcfg.<a class="code" href="unionhcfg__data.html#381a253b3a38a7f943dcbb42f7bf10be">d32</a>);
+<a name="l00402"></a>00402                                                         do_reset = 1;
+<a name="l00403"></a>00403                                                 }
+<a name="l00404"></a>00404                                         }
+<a name="l00405"></a>00405                                 } <span class="keywordflow">else</span> {
+<a name="l00406"></a>00406                                         <span class="comment">/*</span>
+<a name="l00407"></a>00407 <span class="comment">                                         * Not low power</span>
+<a name="l00408"></a>00408 <span class="comment">                                         */</span>
+<a name="l00409"></a>00409                                         <span class="keywordflow">if</span> (usbcfg.<a class="code" href="uniongusbcfg__data.html#1dab81bf7260b1e23f97298c34abea06">b</a>.<a class="code" href="uniongusbcfg__data.html#9e4bac4a0ef0a045f97792f68c5f35df">phylpwrclksel</a> == 1) {
+<a name="l00410"></a>00410                                                 usbcfg.<a class="code" href="uniongusbcfg__data.html#1dab81bf7260b1e23f97298c34abea06">b</a>.<a class="code" href="uniongusbcfg__data.html#9e4bac4a0ef0a045f97792f68c5f35df">phylpwrclksel</a> = 0;
+<a name="l00411"></a>00411                                                 dwc_write_reg32(&amp;global_regs-&gt;
+<a name="l00412"></a>00412                                                                 gusbcfg,
+<a name="l00413"></a>00413                                                                 usbcfg.<a class="code" href="uniongusbcfg__data.html#c3d8f2d95fd61a172eb108cb72a85b47">d32</a>);
+<a name="l00414"></a>00414                                                 do_reset = 1;
+<a name="l00415"></a>00415                                         }
+<a name="l00416"></a>00416                                 }
+<a name="l00417"></a>00417 
+<a name="l00418"></a>00418                                 <span class="keywordflow">if</span> (do_reset) {
+<a name="l00419"></a>00419                                         DWC_TASK_SCHEDULE(dwc_otg_hcd-&gt;
+<a name="l00420"></a>00420                                                           reset_tasklet);
+<a name="l00421"></a>00421                                 }
+<a name="l00422"></a>00422                         }
+<a name="l00423"></a>00423 
+<a name="l00424"></a>00424                         <span class="keywordflow">if</span> (!do_reset) {
+<a name="l00425"></a>00425                                 <span class="comment">/* Port has been enabled set the reset change flag */</span>
+<a name="l00426"></a>00426                                 dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#9aaf2a112f5794f92dedd826342bd637">flags</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#76f573861d9316238ded198c58c228c7">b</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#d0d63f32ed35315e8a02549521fb386e">port_reset_change</a> = 1;
+<a name="l00427"></a>00427                         }
+<a name="l00428"></a>00428                 } <span class="keywordflow">else</span> {
+<a name="l00429"></a>00429                         dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#9aaf2a112f5794f92dedd826342bd637">flags</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#76f573861d9316238ded198c58c228c7">b</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#d222ae08372109a312f6649f77b650e8">port_enable_change</a> = 1;
+<a name="l00430"></a>00430                 }
+<a name="l00431"></a>00431                 retval |= 1;
+<a name="l00432"></a>00432         }
+<a name="l00433"></a>00433 
+<a name="l00435"></a>00435         <span class="keywordflow">if</span> (hprt0.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#cc51da1d52cb824d419ef3feb6ba70b6">prtovrcurrchng</a>) {
+<a name="l00436"></a>00436                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#e4a050e176c1c4f556da2b276a8c2b37">DBG_HCD</a>, <span class="stringliteral">"  --Port Interrupt HPRT0=0x%08x "</span>
+<a name="l00437"></a>00437                             <span class="stringliteral">"Port Overcurrent Changed--\n"</span>, hprt0.<a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a>);
+<a name="l00438"></a>00438                 dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#9aaf2a112f5794f92dedd826342bd637">flags</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#76f573861d9316238ded198c58c228c7">b</a>.<a class="code" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#bc96cf12e2bc5b61ce05f15ae3297bd6">port_over_current_change</a> = 1;
+<a name="l00439"></a>00439                 hprt0_modify.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#cc51da1d52cb824d419ef3feb6ba70b6">prtovrcurrchng</a> = 1;
+<a name="l00440"></a>00440                 retval |= 1;
+<a name="l00441"></a>00441         }
+<a name="l00442"></a>00442 
+<a name="l00443"></a>00443         <span class="comment">/* Clear Port Interrupts */</span>
+<a name="l00444"></a>00444         dwc_write_reg32(dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#dc8fe33e0bb3829cafa884d5fc603c4d">hprt0</a>, hprt0_modify.<a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a>);
+<a name="l00445"></a>00445 
+<a name="l00446"></a>00446         <span class="keywordflow">return</span> retval;
+<a name="l00447"></a>00447 }
+<a name="l00448"></a>00448 
+<a name="l00453"></a><a class="code" href="dwc__otg__hcd__intr_8c.html#1f28e296c0bc4146da309385d95b5d7e">00453</a> int32_t <a class="code" href="dwc__otg__hcd_8h.html#1f28e296c0bc4146da309385d95b5d7e">dwc_otg_hcd_handle_hc_intr</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * <a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>)
+<a name="l00454"></a>00454 {
+<a name="l00455"></a>00455         <span class="keywordtype">int</span> i;
+<a name="l00456"></a>00456         <span class="keywordtype">int</span> retval = 0;
+<a name="l00457"></a>00457         <a class="code" href="unionhaint__data.html">haint_data_t</a> haint;
+<a name="l00458"></a>00458 
+<a name="l00459"></a>00459         <span class="comment">/* Clear appropriate bits in HCINTn to clear the interrupt bit in</span>
+<a name="l00460"></a>00460 <span class="comment">         * GINTSTS */</span>
+<a name="l00461"></a>00461 
+<a name="l00462"></a>00462         haint.<a class="code" href="unionhaint__data.html#c83834650d2981b44274a89dda63a0f5">d32</a> = <a class="code" href="dwc__otg__cil_8h.html#ddc68d442228b5b0600e7ee26c641700">dwc_otg_read_host_all_channels_intr</a>(dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>);
+<a name="l00463"></a>00463 
+<a name="l00464"></a>00464         <span class="keywordflow">for</span> (i = 0; i &lt; dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#c1b433c6965aa7d48f6ca6818c592039">host_channels</a>; i++) {
+<a name="l00465"></a>00465                 <span class="keywordflow">if</span> (haint.<a class="code" href="unionhaint__data.html#9317187b895abebbca64c364b6c3c322">b2</a>.<a class="code" href="unionhaint__data.html#6824b5b98c861cbc8efe3ba9f70cfea0">chint</a> &amp; (1 &lt;&lt; i)) {
+<a name="l00466"></a>00466                         retval |= <a class="code" href="dwc__otg__hcd_8h.html#019c9cc38ec85275a7ef0b0d38bf53ab">dwc_otg_hcd_handle_hc_n_intr</a>(dwc_otg_hcd, i);
+<a name="l00467"></a>00467                 }
+<a name="l00468"></a>00468         }
+<a name="l00469"></a>00469 
+<a name="l00470"></a>00470         <span class="keywordflow">return</span> retval;
+<a name="l00471"></a>00471 }
+<a name="l00472"></a>00472 
+<a name="l00473"></a>00473 
+<a name="l00474"></a>00474 
+<a name="l00485"></a><a class="code" href="dwc__otg__hcd__intr_8c.html#6cdb134cbb3cdf3501ca39761137baf0">00485</a> <span class="keyword">static</span> uint32_t <a class="code" href="dwc__otg__hcd__intr_8c.html#6cdb134cbb3cdf3501ca39761137baf0">get_actual_xfer_length</a>(<a class="code" href="structdwc__hc.html">dwc_hc_t</a> * hc,
+<a name="l00486"></a>00486                                        <a class="code" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> * hc_regs,
+<a name="l00487"></a>00487                                        <a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> * qtd,
+<a name="l00488"></a>00488                                        dwc_otg_halt_status_e halt_status,
+<a name="l00489"></a>00489                                        <span class="keywordtype">int</span> *short_read)
+<a name="l00490"></a>00490 {
+<a name="l00491"></a>00491         <a class="code" href="unionhctsiz__data.html">hctsiz_data_t</a> hctsiz;
+<a name="l00492"></a>00492         uint32_t length;
+<a name="l00493"></a>00493 
+<a name="l00494"></a>00494         <span class="keywordflow">if</span> (short_read != NULL) {
+<a name="l00495"></a>00495                 *short_read = 0;
+<a name="l00496"></a>00496         }
+<a name="l00497"></a>00497         hctsiz.<a class="code" href="unionhctsiz__data.html#fb41950555c60c6015294bdefe9cd39d">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#c6173f823ba754d9f9549422b6380ca2">hctsiz</a>);
+<a name="l00498"></a>00498 
+<a name="l00499"></a>00499         <span class="keywordflow">if</span> (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
+<a name="l00500"></a>00500                 <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#c5088d431f5efc382121f201f5d571aa">ep_is_in</a>) {
+<a name="l00501"></a>00501                         length = hc-&gt;<a class="code" href="structdwc__hc.html#ce32fe93214f1686896e924fbf61cac7">xfer_len</a> - hctsiz.<a class="code" href="unionhctsiz__data.html#8967fa90c651bce44a3cbe90c44cf638">b</a>.<a class="code" href="unionhctsiz__data.html#6ad01d874d77aa4382f71fa68eaec12d">xfersize</a>;
+<a name="l00502"></a>00502                         <span class="keywordflow">if</span> (short_read != NULL) {
+<a name="l00503"></a>00503                                 *short_read = (hctsiz.<a class="code" href="unionhctsiz__data.html#8967fa90c651bce44a3cbe90c44cf638">b</a>.<a class="code" href="unionhctsiz__data.html#6ad01d874d77aa4382f71fa68eaec12d">xfersize</a> != 0);
+<a name="l00504"></a>00504                         }
+<a name="l00505"></a>00505                 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#8708dd009988ce20b8a8d52a4a96c5a3">do_split</a>) {
+<a name="l00506"></a>00506                         length = qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#badffe465e850133c62c8f7e539f3fca">ssplit_out_xfer_count</a>;
+<a name="l00507"></a>00507                 } <span class="keywordflow">else</span> {
+<a name="l00508"></a>00508                         length = hc-&gt;<a class="code" href="structdwc__hc.html#ce32fe93214f1686896e924fbf61cac7">xfer_len</a>;
+<a name="l00509"></a>00509                 }
+<a name="l00510"></a>00510         } <span class="keywordflow">else</span> {
+<a name="l00511"></a>00511                 <span class="comment">/*</span>
+<a name="l00512"></a>00512 <span class="comment">                 * Must use the hctsiz.pktcnt field to determine how much data</span>
+<a name="l00513"></a>00513 <span class="comment">                 * has been transferred. This field reflects the number of</span>
+<a name="l00514"></a>00514 <span class="comment">                 * packets that have been transferred via the USB. This is</span>
+<a name="l00515"></a>00515 <span class="comment">                 * always an integral number of packets if the transfer was</span>
+<a name="l00516"></a>00516 <span class="comment">                 * halted before its normal completion. (Can't use the</span>
+<a name="l00517"></a>00517 <span class="comment">                 * hctsiz.xfersize field because that reflects the number of</span>
+<a name="l00518"></a>00518 <span class="comment">                 * bytes transferred via the AHB, not the USB).</span>
+<a name="l00519"></a>00519 <span class="comment">                 */</span>
+<a name="l00520"></a>00520                 length =
+<a name="l00521"></a>00521                     (hc-&gt;<a class="code" href="structdwc__hc.html#6c030bc725f43025d3046d17b4fbee4e">start_pkt_count</a> - hctsiz.<a class="code" href="unionhctsiz__data.html#8967fa90c651bce44a3cbe90c44cf638">b</a>.<a class="code" href="unionhctsiz__data.html#3ea18df5a98d33a6f8fa786252a0205b">pktcnt</a>) * hc-&gt;<a class="code" href="structdwc__hc.html#bd88f02eb286ba01d8d1b049e8975ccb">max_packet</a>;
+<a name="l00522"></a>00522         }
+<a name="l00523"></a>00523 
+<a name="l00524"></a>00524         <span class="keywordflow">return</span> length;
+<a name="l00525"></a>00525 }
+<a name="l00526"></a>00526 
+<a name="l00536"></a><a class="code" href="dwc__otg__hcd__intr_8c.html#ecb30a961e8d4831e8691d45a77162e3">00536</a> <span class="keyword">static</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd__intr_8c.html#ecb30a961e8d4831e8691d45a77162e3">update_urb_state_xfer_comp</a>(<a class="code" href="structdwc__hc.html">dwc_hc_t</a> * hc,
+<a name="l00537"></a>00537                                       <a class="code" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> * hc_regs,
+<a name="l00538"></a>00538                                       <a class="code" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> * urb,
+<a name="l00539"></a>00539                                       <a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> * qtd)
+<a name="l00540"></a>00540 {
+<a name="l00541"></a>00541         <span class="keywordtype">int</span> xfer_done = 0;
+<a name="l00542"></a>00542         <span class="keywordtype">int</span> short_read = 0;
+<a name="l00543"></a>00543 
+<a name="l00544"></a>00544         <span class="keywordtype">int</span> xfer_length;
+<a name="l00545"></a>00545 
+<a name="l00546"></a>00546         xfer_length = <a class="code" href="dwc__otg__hcd__intr_8c.html#6cdb134cbb3cdf3501ca39761137baf0">get_actual_xfer_length</a>(hc, hc_regs, qtd,                                               
+<a name="l00547"></a>00547                                                      DWC_OTG_HC_XFER_COMPLETE,
+<a name="l00548"></a>00548                                                      &amp;short_read);
+<a name="l00549"></a>00549 
+<a name="l00550"></a>00550 
+<a name="l00551"></a>00551         <span class="comment">/* non DWORD-aligned buffer case handling. */</span>
+<a name="l00552"></a>00552         <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#e0c3ba51a04b36656baa4e70fc63cf77">align_buff</a> &amp;&amp; xfer_length &amp;&amp; hc-&gt;<a class="code" href="structdwc__hc.html#c5088d431f5efc382121f201f5d571aa">ep_is_in</a>) {
+<a name="l00553"></a>00553                 dwc_memcpy(urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#99ae35ffcd6147ddb93b361ab3bcfe95">buf</a> + urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#742c8a97d3867ab89148eae34e0c73a6">actual_length</a>, hc-&gt;<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#aac9f90a6afd9056dce79d013dd2168b">dw_align_buf</a>, xfer_length);
+<a name="l00554"></a>00554         }
+<a name="l00555"></a>00555 
+<a name="l00556"></a>00556         urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#742c8a97d3867ab89148eae34e0c73a6">actual_length</a> += xfer_length;
+<a name="l00557"></a>00557 
+<a name="l00558"></a>00558         <span class="keywordflow">if</span>(xfer_length &amp;&amp; (hc-&gt;<a class="code" href="structdwc__hc.html#e6169fbc92e4d79686097742ad646f5c">ep_type</a> == <a class="code" href="dwc__otg__cil_8h.html#9b079858cda0b917316ad9161b3881e0">DWC_OTG_EP_TYPE_BULK</a>) &amp;&amp;
+<a name="l00559"></a>00559            (urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#2f1d90765496d78d297b3e57ef4d781c">flags</a> &amp; <a class="code" href="dwc__otg__hcd__if_8h.html#14e576ea3b30c038f925e3e6c80c64fe">URB_SEND_ZERO_PACKET</a>) &amp;&amp; (urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#742c8a97d3867ab89148eae34e0c73a6">actual_length</a> == urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#dca57de4fdecd894241ce24167206a45">length</a>) &amp;&amp;
+<a name="l00560"></a>00560            !(urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#dca57de4fdecd894241ce24167206a45">length</a> % hc-&gt;<a class="code" href="structdwc__hc.html#bd88f02eb286ba01d8d1b049e8975ccb">max_packet</a>)) {
+<a name="l00561"></a>00561                 xfer_done = 0;
+<a name="l00562"></a>00562         } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (short_read || urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#742c8a97d3867ab89148eae34e0c73a6">actual_length</a> == urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#dca57de4fdecd894241ce24167206a45">length</a>) {
+<a name="l00563"></a>00563                 xfer_done = 1;
+<a name="l00564"></a>00564                 urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#101e4a6762b9911cdb85768890fa1210">status</a> = 0;
+<a name="l00565"></a>00565         }
+<a name="l00566"></a>00566         
+<a name="l00567"></a>00567 <span class="preprocessor">#ifdef DEBUG</span>
+<a name="l00568"></a>00568 <span class="preprocessor"></span>        {
+<a name="l00569"></a>00569                 <a class="code" href="unionhctsiz__data.html">hctsiz_data_t</a> hctsiz;
+<a name="l00570"></a>00570                 hctsiz.<a class="code" href="unionhctsiz__data.html#fb41950555c60c6015294bdefe9cd39d">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#c6173f823ba754d9f9549422b6380ca2">hctsiz</a>);
+<a name="l00571"></a>00571                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"DWC_otg: %s: %s, channel %d\n"</span>,
+<a name="l00572"></a>00572                             __func__, (hc-&gt;<a class="code" href="structdwc__hc.html#c5088d431f5efc382121f201f5d571aa">ep_is_in</a> ? <span class="stringliteral">"IN"</span> : <span class="stringliteral">"OUT"</span>),
+<a name="l00573"></a>00573                             hc-&gt;<a class="code" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">hc_num</a>);
+<a name="l00574"></a>00574                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"  hc-&gt;xfer_len %d\n"</span>, hc-&gt;<a class="code" href="structdwc__hc.html#ce32fe93214f1686896e924fbf61cac7">xfer_len</a>);
+<a name="l00575"></a>00575                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"  hctsiz.xfersize %d\n"</span>,
+<a name="l00576"></a>00576                             hctsiz.<a class="code" href="unionhctsiz__data.html#8967fa90c651bce44a3cbe90c44cf638">b</a>.<a class="code" href="unionhctsiz__data.html#6ad01d874d77aa4382f71fa68eaec12d">xfersize</a>);
+<a name="l00577"></a>00577                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"  urb-&gt;transfer_buffer_length %d\n"</span>,
+<a name="l00578"></a>00578                             urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#dca57de4fdecd894241ce24167206a45">length</a>);
+<a name="l00579"></a>00579                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"  urb-&gt;actual_length %d\n"</span>,
+<a name="l00580"></a>00580                             urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#742c8a97d3867ab89148eae34e0c73a6">actual_length</a>);
+<a name="l00581"></a>00581                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"  short_read %d, xfer_done %d\n"</span>,
+<a name="l00582"></a>00582                             short_read, xfer_done);
+<a name="l00583"></a>00583         }
+<a name="l00584"></a>00584 <span class="preprocessor">#endif</span>
+<a name="l00585"></a>00585 <span class="preprocessor"></span>
+<a name="l00586"></a>00586         <span class="keywordflow">return</span> xfer_done;
+<a name="l00587"></a>00587 }
+<a name="l00588"></a>00588 
+<a name="l00589"></a>00589 <span class="comment">/*</span>
+<a name="l00590"></a>00590 <span class="comment"> * Save the starting data toggle for the next transfer. The data toggle is</span>
+<a name="l00591"></a>00591 <span class="comment"> * saved in the QH for non-control transfers and it's saved in the QTD for</span>
+<a name="l00592"></a>00592 <span class="comment"> * control transfers.</span>
+<a name="l00593"></a>00593 <span class="comment"> */</span>
+<a name="l00594"></a><a class="code" href="dwc__otg__hcd__intr_8c.html#8bce109004d7869bfdd9aa1075c6bd2c">00594</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd_8h.html#8bce109004d7869bfdd9aa1075c6bd2c">dwc_otg_hcd_save_data_toggle</a>(<a class="code" href="structdwc__hc.html">dwc_hc_t</a> * hc,
+<a name="l00595"></a>00595                              <a class="code" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> * hc_regs, <a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> * qtd)
+<a name="l00596"></a>00596 {
+<a name="l00597"></a>00597         <a class="code" href="unionhctsiz__data.html">hctsiz_data_t</a> hctsiz;
+<a name="l00598"></a>00598         hctsiz.<a class="code" href="unionhctsiz__data.html#fb41950555c60c6015294bdefe9cd39d">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#c6173f823ba754d9f9549422b6380ca2">hctsiz</a>);
+<a name="l00599"></a>00599 
+<a name="l00600"></a>00600         <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#e6169fbc92e4d79686097742ad646f5c">ep_type</a> != <a class="code" href="dwc__otg__cil_8h.html#64e5cd756330f5adab79b25cc8067bdc">DWC_OTG_EP_TYPE_CONTROL</a>) {
+<a name="l00601"></a>00601                 <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *qh = hc-&gt;<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>;
+<a name="l00602"></a>00602                 <span class="keywordflow">if</span> (hctsiz.<a class="code" href="unionhctsiz__data.html#8967fa90c651bce44a3cbe90c44cf638">b</a>.<a class="code" href="unionhctsiz__data.html#d8b17af02c244e47ca0c38f933a6b3f0">pid</a> == <a class="code" href="dwc__otg__regs_8h.html#ab429f705d8fb6db88a206968e438217">DWC_HCTSIZ_DATA0</a>) {
+<a name="l00603"></a>00603                         qh-&gt;<a class="code" href="structdwc__otg__qh.html#b0e001bfd76f5781926795ac47ef2c25">data_toggle</a> = <a class="code" href="dwc__otg__cil_8h.html#0e843d08e80c29e82962ce9170a02a52">DWC_OTG_HC_PID_DATA0</a>;
+<a name="l00604"></a>00604                 } <span class="keywordflow">else</span> {
+<a name="l00605"></a>00605                         qh-&gt;<a class="code" href="structdwc__otg__qh.html#b0e001bfd76f5781926795ac47ef2c25">data_toggle</a> = <a class="code" href="dwc__otg__cil_8h.html#e623eb446c55928b324e9636111315e1">DWC_OTG_HC_PID_DATA1</a>;
+<a name="l00606"></a>00606                 }
+<a name="l00607"></a>00607         } <span class="keywordflow">else</span> {
+<a name="l00608"></a>00608                 <span class="keywordflow">if</span> (hctsiz.<a class="code" href="unionhctsiz__data.html#8967fa90c651bce44a3cbe90c44cf638">b</a>.<a class="code" href="unionhctsiz__data.html#d8b17af02c244e47ca0c38f933a6b3f0">pid</a> == <a class="code" href="dwc__otg__regs_8h.html#ab429f705d8fb6db88a206968e438217">DWC_HCTSIZ_DATA0</a>) {
+<a name="l00609"></a>00609                         qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#e912f256e01165b573c26262247a5eff">data_toggle</a> = <a class="code" href="dwc__otg__cil_8h.html#0e843d08e80c29e82962ce9170a02a52">DWC_OTG_HC_PID_DATA0</a>;
+<a name="l00610"></a>00610                 } <span class="keywordflow">else</span> {
+<a name="l00611"></a>00611                         qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#e912f256e01165b573c26262247a5eff">data_toggle</a> = <a class="code" href="dwc__otg__cil_8h.html#e623eb446c55928b324e9636111315e1">DWC_OTG_HC_PID_DATA1</a>;
+<a name="l00612"></a>00612                 }
+<a name="l00613"></a>00613         }
+<a name="l00614"></a>00614 }
+<a name="l00615"></a>00615 
+<a name="l00625"></a>00625 <span class="keyword">static</span> dwc_otg_halt_status_e
+<a name="l00626"></a><a class="code" href="dwc__otg__hcd__intr_8c.html#e93d54bdf873c5a31882660c2984458e">00626</a> <a class="code" href="dwc__otg__hcd__intr_8c.html#e93d54bdf873c5a31882660c2984458e">update_isoc_urb_state</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd,
+<a name="l00627"></a>00627                       <a class="code" href="structdwc__hc.html">dwc_hc_t</a> * hc,
+<a name="l00628"></a>00628                       <a class="code" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> * hc_regs,
+<a name="l00629"></a>00629                       <a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> * qtd, dwc_otg_halt_status_e halt_status)
+<a name="l00630"></a>00630 {
+<a name="l00631"></a>00631         <a class="code" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *urb = qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#7e7767808e8eb9d71de0db00f57553f9">urb</a>;
+<a name="l00632"></a>00632         dwc_otg_halt_status_e ret_val = halt_status;
+<a name="l00633"></a>00633         <span class="keyword">struct </span><a class="code" href="structdwc__otg__hcd__iso__packet__desc.html">dwc_otg_hcd_iso_packet_desc</a> *frame_desc;
+<a name="l00634"></a>00634 
+<a name="l00635"></a>00635         frame_desc = &amp;urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#ed542f6a2d99dba2f6b71b0d8012ec8a">iso_descs</a>[qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#c67d5f885976d0698f20d113d32b4b30">isoc_frame_index</a>];
+<a name="l00636"></a>00636         <span class="keywordflow">switch</span> (halt_status) {
+<a name="l00637"></a>00637         <span class="keywordflow">case</span> DWC_OTG_HC_XFER_COMPLETE:
+<a name="l00638"></a>00638                 frame_desc-&gt;<a class="code" href="structdwc__otg__hcd__iso__packet__desc.html#d070772c24621c47b49ad21c6acadb94">status</a> = 0;
+<a name="l00639"></a>00639                 frame_desc-&gt;<a class="code" href="structdwc__otg__hcd__iso__packet__desc.html#c00b967f4c613820b99efc0abda5178c">actual_length</a> =
+<a name="l00640"></a>00640                     <a class="code" href="dwc__otg__hcd__intr_8c.html#6cdb134cbb3cdf3501ca39761137baf0">get_actual_xfer_length</a>(hc, hc_regs, qtd, halt_status, NULL);
+<a name="l00641"></a>00641                     
+<a name="l00642"></a>00642                 <span class="comment">/* non DWORD-aligned buffer case handling. */</span>
+<a name="l00643"></a>00643                 <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#e0c3ba51a04b36656baa4e70fc63cf77">align_buff</a> &amp;&amp; frame_desc-&gt;<a class="code" href="structdwc__otg__hcd__iso__packet__desc.html#c00b967f4c613820b99efc0abda5178c">actual_length</a> &amp;&amp; hc-&gt;<a class="code" href="structdwc__hc.html#c5088d431f5efc382121f201f5d571aa">ep_is_in</a>) {
+<a name="l00644"></a>00644                         dwc_memcpy(urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#99ae35ffcd6147ddb93b361ab3bcfe95">buf</a> + frame_desc-&gt;<a class="code" href="structdwc__otg__hcd__iso__packet__desc.html#246f3d147a22cd295c534253593dca4a">offset</a> + qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#839371940a7e34365e2272f3214b7e34">isoc_split_offset</a>, 
+<a name="l00645"></a>00645                                    hc-&gt;<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#aac9f90a6afd9056dce79d013dd2168b">dw_align_buf</a>, frame_desc-&gt;<a class="code" href="structdwc__otg__hcd__iso__packet__desc.html#c00b967f4c613820b99efc0abda5178c">actual_length</a>);
+<a name="l00646"></a>00646                 }
+<a name="l00647"></a>00647                 
+<a name="l00648"></a>00648                 <span class="keywordflow">break</span>;
+<a name="l00649"></a>00649         <span class="keywordflow">case</span> DWC_OTG_HC_XFER_FRAME_OVERRUN:
+<a name="l00650"></a>00650                 urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#58c7018042c94c436637ea80354e7e28">error_count</a>++;
+<a name="l00651"></a>00651                 <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#c5088d431f5efc382121f201f5d571aa">ep_is_in</a>) {
+<a name="l00652"></a>00652                         frame_desc-&gt;<a class="code" href="structdwc__otg__hcd__iso__packet__desc.html#d070772c24621c47b49ad21c6acadb94">status</a> = -DWC_E_NO_STREAM_RES;
+<a name="l00653"></a>00653                 } <span class="keywordflow">else</span> {
+<a name="l00654"></a>00654                         frame_desc-&gt;<a class="code" href="structdwc__otg__hcd__iso__packet__desc.html#d070772c24621c47b49ad21c6acadb94">status</a> = -DWC_E_COMMUNICATION;
+<a name="l00655"></a>00655                 }
+<a name="l00656"></a>00656                 frame_desc-&gt;<a class="code" href="structdwc__otg__hcd__iso__packet__desc.html#c00b967f4c613820b99efc0abda5178c">actual_length</a> = 0;
+<a name="l00657"></a>00657                 <span class="keywordflow">break</span>;
+<a name="l00658"></a>00658         <span class="keywordflow">case</span> DWC_OTG_HC_XFER_BABBLE_ERR:
+<a name="l00659"></a>00659                 urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#58c7018042c94c436637ea80354e7e28">error_count</a>++;
+<a name="l00660"></a>00660                 frame_desc-&gt;<a class="code" href="structdwc__otg__hcd__iso__packet__desc.html#d070772c24621c47b49ad21c6acadb94">status</a> = -DWC_E_OVERFLOW;
+<a name="l00661"></a>00661                 <span class="comment">/* Don't need to update actual_length in this case. */</span>
+<a name="l00662"></a>00662                 <span class="keywordflow">break</span>;
+<a name="l00663"></a>00663         <span class="keywordflow">case</span> DWC_OTG_HC_XFER_XACT_ERR:
+<a name="l00664"></a>00664                 urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#58c7018042c94c436637ea80354e7e28">error_count</a>++;
+<a name="l00665"></a>00665                 frame_desc-&gt;<a class="code" href="structdwc__otg__hcd__iso__packet__desc.html#d070772c24621c47b49ad21c6acadb94">status</a> = -DWC_E_PROTOCOL;
+<a name="l00666"></a>00666                 frame_desc-&gt;<a class="code" href="structdwc__otg__hcd__iso__packet__desc.html#c00b967f4c613820b99efc0abda5178c">actual_length</a> =
+<a name="l00667"></a>00667                     <a class="code" href="dwc__otg__hcd__intr_8c.html#6cdb134cbb3cdf3501ca39761137baf0">get_actual_xfer_length</a>(hc, hc_regs, qtd, halt_status, NULL);
+<a name="l00668"></a>00668                 
+<a name="l00669"></a>00669                 <span class="comment">/* non DWORD-aligned buffer case handling. */</span>
+<a name="l00670"></a>00670                 <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#e0c3ba51a04b36656baa4e70fc63cf77">align_buff</a> &amp;&amp; frame_desc-&gt;<a class="code" href="structdwc__otg__hcd__iso__packet__desc.html#c00b967f4c613820b99efc0abda5178c">actual_length</a> &amp;&amp; hc-&gt;<a class="code" href="structdwc__hc.html#c5088d431f5efc382121f201f5d571aa">ep_is_in</a>) {
+<a name="l00671"></a>00671                         dwc_memcpy(urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#99ae35ffcd6147ddb93b361ab3bcfe95">buf</a> + frame_desc-&gt;<a class="code" href="structdwc__otg__hcd__iso__packet__desc.html#246f3d147a22cd295c534253593dca4a">offset</a> + qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#839371940a7e34365e2272f3214b7e34">isoc_split_offset</a>, 
+<a name="l00672"></a>00672                                    hc-&gt;<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#aac9f90a6afd9056dce79d013dd2168b">dw_align_buf</a>, frame_desc-&gt;<a class="code" href="structdwc__otg__hcd__iso__packet__desc.html#c00b967f4c613820b99efc0abda5178c">actual_length</a>);
+<a name="l00673"></a>00673                 }
+<a name="l00674"></a>00674                 <span class="comment">/* Skip whole frame */</span>
+<a name="l00675"></a>00675                 <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#8708dd009988ce20b8a8d52a4a96c5a3">do_split</a> &amp;&amp; (hc-&gt;<a class="code" href="structdwc__hc.html#e6169fbc92e4d79686097742ad646f5c">ep_type</a> == <a class="code" href="dwc__otg__cil_8h.html#152a3a5e1433bd2197672f0b5105e7a4">DWC_OTG_EP_TYPE_ISOC</a>) &amp;&amp; 
+<a name="l00676"></a>00676                                 hc-&gt;<a class="code" href="structdwc__hc.html#c5088d431f5efc382121f201f5d571aa">ep_is_in</a> &amp;&amp; hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a>) {
+<a name="l00677"></a>00677                         qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#6355e968a4d36edce3e22c89ac7b5001">complete_split</a> = 0;
+<a name="l00678"></a>00678                         qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#839371940a7e34365e2272f3214b7e34">isoc_split_offset</a> = 0;
+<a name="l00679"></a>00679                 }
+<a name="l00680"></a>00680                         
+<a name="l00681"></a>00681                 <span class="keywordflow">break</span>;
+<a name="l00682"></a>00682         <span class="keywordflow">default</span>:
+<a name="l00683"></a>00683                 DWC_ASSERT(1, <span class="stringliteral">"Unhandled _halt_status (%d)\n"</span>, halt_status);
+<a name="l00684"></a>00684                 <span class="keywordflow">break</span>;
+<a name="l00685"></a>00685         }
+<a name="l00686"></a>00686         <span class="keywordflow">if</span> (++qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#c67d5f885976d0698f20d113d32b4b30">isoc_frame_index</a> == urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#570583697e8c1e4398969630bc2562f8">packet_count</a>) {
+<a name="l00687"></a>00687                 <span class="comment">/*</span>
+<a name="l00688"></a>00688 <span class="comment">                 * urb-&gt;status is not used for isoc transfers.</span>
+<a name="l00689"></a>00689 <span class="comment">                 * The individual frame_desc statuses are used instead.</span>
+<a name="l00690"></a>00690 <span class="comment">                 */</span>
+<a name="l00691"></a>00691                 hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#ffefbd33a59a14b8b46406f5aaeaa2f4">fops</a>-&gt;<a class="code" href="structdwc__otg__hcd__function__ops.html#09a989481103de7468cd46ef61ace0ce">complete</a>(hcd, urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#5ba0e393ef9768275db85c00e68be477">priv</a>, urb, 0);
+<a name="l00692"></a>00692                 ret_val = DWC_OTG_HC_XFER_URB_COMPLETE;
+<a name="l00693"></a>00693         } <span class="keywordflow">else</span> {
+<a name="l00694"></a>00694                 ret_val = DWC_OTG_HC_XFER_COMPLETE;
+<a name="l00695"></a>00695         }
+<a name="l00696"></a>00696         <span class="keywordflow">return</span> ret_val;
+<a name="l00697"></a>00697 }
+<a name="l00698"></a>00698 
+<a name="l00706"></a><a class="code" href="dwc__otg__hcd__intr_8c.html#57e9a29ec2dc8cd8d119acade0ae4ff1">00706</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd__intr_8c.html#57e9a29ec2dc8cd8d119acade0ae4ff1">deactivate_qh</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd, <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> * qh, <span class="keywordtype">int</span> free_qtd)
+<a name="l00707"></a>00707 {
+<a name="l00708"></a>00708         <span class="keywordtype">int</span> continue_split = 0;
+<a name="l00709"></a>00709         <a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *qtd;
+<a name="l00710"></a>00710 
+<a name="l00711"></a>00711         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"  %s(%p,%p,%d)\n"</span>, __func__, hcd, qh, free_qtd);
+<a name="l00712"></a>00712 
+<a name="l00713"></a>00713         qtd = DWC_CIRCLEQ_FIRST(&amp;qh-&gt;<a class="code" href="structdwc__otg__qh.html#9567d266da8e796d3467fb16ae867f8e">qtd_list</a>);
+<a name="l00714"></a>00714 
+<a name="l00715"></a>00715         <span class="keywordflow">if</span> (qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#6355e968a4d36edce3e22c89ac7b5001">complete_split</a>) {
+<a name="l00716"></a>00716                 continue_split = 1;
+<a name="l00717"></a>00717         } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#ab224d64d72f2ef4f10e722ebcfa29a6">isoc_split_pos</a> == <a class="code" href="dwc__otg__regs_8h.html#2297a1a33f502bc705e5c450c9864c6c">DWC_HCSPLIT_XACTPOS_MID</a> ||
+<a name="l00718"></a>00718                    qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#ab224d64d72f2ef4f10e722ebcfa29a6">isoc_split_pos</a> == <a class="code" href="dwc__otg__regs_8h.html#fc237b3dd77c97276aa4bd50947117e2">DWC_HCSPLIT_XACTPOS_END</a>) {
+<a name="l00719"></a>00719                 continue_split = 1;
+<a name="l00720"></a>00720         }
+<a name="l00721"></a>00721 
+<a name="l00722"></a>00722         <span class="keywordflow">if</span> (free_qtd) {
+<a name="l00723"></a>00723                 <a class="code" href="dwc__otg__hcd_8h.html#19adb6641f95448a956015b2d69ba96a">dwc_otg_hcd_qtd_remove_and_free</a>(hcd, qtd, qh);
+<a name="l00724"></a>00724                 continue_split = 0;
+<a name="l00725"></a>00725         }
+<a name="l00726"></a>00726 
+<a name="l00727"></a>00727         qh-&gt;<a class="code" href="structdwc__otg__qh.html#bbdb7d30b60b6c326301f33b35088bb4">channel</a> = NULL;
+<a name="l00728"></a>00728         <a class="code" href="dwc__otg__hcd_8h.html#f88bc5b6beb674c909d1c09a819ba9d9">dwc_otg_hcd_qh_deactivate</a>(hcd, qh, continue_split);
+<a name="l00729"></a>00729 }
+<a name="l00730"></a>00730 
+<a name="l00742"></a><a class="code" href="dwc__otg__hcd__intr_8c.html#4f6bf01b14a03eeed81d27bffa5e99fc">00742</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd__intr_8c.html#4f6bf01b14a03eeed81d27bffa5e99fc">release_channel</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd,
+<a name="l00743"></a>00743                             <a class="code" href="structdwc__hc.html">dwc_hc_t</a> * hc,
+<a name="l00744"></a>00744                             <a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> * qtd,
+<a name="l00745"></a>00745                             dwc_otg_halt_status_e halt_status)
+<a name="l00746"></a>00746 {
+<a name="l00747"></a>00747         <a class="code" href="dwc__otg__hcd_8h.html#92c49783eebc5bcffa8b8a51c2127be9">dwc_otg_transaction_type_e</a> tr_type;
+<a name="l00748"></a>00748         <span class="keywordtype">int</span> free_qtd;
+<a name="l00749"></a>00749 
+<a name="l00750"></a>00750         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"  %s: channel %d, halt_status %d\n"</span>,
+<a name="l00751"></a>00751                     __func__, hc-&gt;<a class="code" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">hc_num</a>, halt_status);
+<a name="l00752"></a>00752 
+<a name="l00753"></a>00753         <span class="keywordflow">switch</span> (halt_status) {
+<a name="l00754"></a>00754         <span class="keywordflow">case</span> DWC_OTG_HC_XFER_URB_COMPLETE:
+<a name="l00755"></a>00755                 free_qtd = 1;
+<a name="l00756"></a>00756                 <span class="keywordflow">break</span>;
+<a name="l00757"></a>00757         <span class="keywordflow">case</span> DWC_OTG_HC_XFER_AHB_ERR:
+<a name="l00758"></a>00758         <span class="keywordflow">case</span> DWC_OTG_HC_XFER_STALL:
+<a name="l00759"></a>00759         <span class="keywordflow">case</span> DWC_OTG_HC_XFER_BABBLE_ERR:
+<a name="l00760"></a>00760                 free_qtd = 1;
+<a name="l00761"></a>00761                 <span class="keywordflow">break</span>;
+<a name="l00762"></a>00762         <span class="keywordflow">case</span> DWC_OTG_HC_XFER_XACT_ERR:
+<a name="l00763"></a>00763                 <span class="keywordflow">if</span> (qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#18eeb9c647049aec468bf9a7861c873f">error_count</a> &gt;= 3) {
+<a name="l00764"></a>00764                         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>,
+<a name="l00765"></a>00765                                     <span class="stringliteral">"  Complete URB with transaction error\n"</span>);
+<a name="l00766"></a>00766                         free_qtd = 1;
+<a name="l00767"></a>00767                         qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#7e7767808e8eb9d71de0db00f57553f9">urb</a>-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#101e4a6762b9911cdb85768890fa1210">status</a> = -DWC_E_PROTOCOL;
+<a name="l00768"></a>00768                         hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#ffefbd33a59a14b8b46406f5aaeaa2f4">fops</a>-&gt;<a class="code" href="structdwc__otg__hcd__function__ops.html#09a989481103de7468cd46ef61ace0ce">complete</a>(hcd, qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#7e7767808e8eb9d71de0db00f57553f9">urb</a>-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#5ba0e393ef9768275db85c00e68be477">priv</a>,
+<a name="l00769"></a>00769                                             qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#7e7767808e8eb9d71de0db00f57553f9">urb</a>, -DWC_E_PROTOCOL);
+<a name="l00770"></a>00770                 } <span class="keywordflow">else</span> {
+<a name="l00771"></a>00771                         free_qtd = 0;
+<a name="l00772"></a>00772                 }
+<a name="l00773"></a>00773                 <span class="keywordflow">break</span>;
+<a name="l00774"></a>00774         <span class="keywordflow">case</span> DWC_OTG_HC_XFER_URB_DEQUEUE:
+<a name="l00775"></a>00775                 <span class="comment">/*</span>
+<a name="l00776"></a>00776 <span class="comment">                 * The QTD has already been removed and the QH has been</span>
+<a name="l00777"></a>00777 <span class="comment">                 * deactivated. Don't want to do anything except release the</span>
+<a name="l00778"></a>00778 <span class="comment">                 * host channel and try to queue more transfers.</span>
+<a name="l00779"></a>00779 <span class="comment">                 */</span>
+<a name="l00780"></a>00780                 <span class="keywordflow">goto</span> cleanup;
+<a name="l00781"></a>00781         <span class="keywordflow">case</span> DWC_OTG_HC_XFER_NO_HALT_STATUS:
+<a name="l00782"></a>00782                 free_qtd = 0;
+<a name="l00783"></a>00783                 <span class="keywordflow">break</span>;
+<a name="l00784"></a>00784         <span class="keywordflow">default</span>:
+<a name="l00785"></a>00785                 free_qtd = 0;
+<a name="l00786"></a>00786                 <span class="keywordflow">break</span>;
+<a name="l00787"></a>00787         }
+<a name="l00788"></a>00788 
+<a name="l00789"></a>00789         <a class="code" href="dwc__otg__hcd__intr_8c.html#57e9a29ec2dc8cd8d119acade0ae4ff1">deactivate_qh</a>(hcd, hc-&gt;<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>, free_qtd);
+<a name="l00790"></a>00790 
+<a name="l00791"></a>00791       cleanup:
+<a name="l00792"></a>00792         <span class="comment">/*</span>
+<a name="l00793"></a>00793 <span class="comment">         * Release the host channel for use by other transfers. The cleanup</span>
+<a name="l00794"></a>00794 <span class="comment">         * function clears the channel interrupt enables and conditions, so</span>
+<a name="l00795"></a>00795 <span class="comment">         * there's no need to clear the Channel Halted interrupt separately.</span>
+<a name="l00796"></a>00796 <span class="comment">         */</span>
+<a name="l00797"></a>00797         <a class="code" href="dwc__otg__cil_8c.html#f05341f811fba7f6183db66faf50a867">dwc_otg_hc_cleanup</a>(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>, hc);
+<a name="l00798"></a>00798         DWC_CIRCLEQ_INSERT_TAIL(&amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#1761f2e6b8f6ba82c0e0c4e561813f0f">free_hc_list</a>, hc, hc_list_entry);
+<a name="l00799"></a>00799 
+<a name="l00800"></a>00800         <span class="keywordflow">switch</span> (hc-&gt;<a class="code" href="structdwc__hc.html#e6169fbc92e4d79686097742ad646f5c">ep_type</a>) {
+<a name="l00801"></a>00801         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__cil_8h.html#64e5cd756330f5adab79b25cc8067bdc">DWC_OTG_EP_TYPE_CONTROL</a>:
+<a name="l00802"></a>00802         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__cil_8h.html#9b079858cda0b917316ad9161b3881e0">DWC_OTG_EP_TYPE_BULK</a>:
+<a name="l00803"></a>00803                 hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e7fff26b5cce7c6c520c89f9e3c75617">non_periodic_channels</a>--;
+<a name="l00804"></a>00804                 <span class="keywordflow">break</span>;
+<a name="l00805"></a>00805 
+<a name="l00806"></a>00806         <span class="keywordflow">default</span>:
+<a name="l00807"></a>00807                 <span class="comment">/*</span>
+<a name="l00808"></a>00808 <span class="comment">                 * Don't release reservations for periodic channels here.</span>
+<a name="l00809"></a>00809 <span class="comment">                 * That's done when a periodic transfer is descheduled (i.e.</span>
+<a name="l00810"></a>00810 <span class="comment">                 * when the QH is removed from the periodic schedule).</span>
+<a name="l00811"></a>00811 <span class="comment">                 */</span>
+<a name="l00812"></a>00812                 <span class="keywordflow">break</span>;
+<a name="l00813"></a>00813         }
+<a name="l00814"></a>00814 
+<a name="l00815"></a>00815         <span class="comment">/* Try to queue more transfers now that there's a free channel. */</span>
+<a name="l00816"></a>00816         tr_type = <a class="code" href="dwc__otg__hcd_8c.html#96cc299f4f0478187ed7ba49b975ffc3">dwc_otg_hcd_select_transactions</a>(hcd);
+<a name="l00817"></a>00817         <span class="keywordflow">if</span> (tr_type != DWC_OTG_TRANSACTION_NONE) {
+<a name="l00818"></a>00818                 <a class="code" href="dwc__otg__hcd_8c.html#2f57bf2fc3013d63101f112702b913a0">dwc_otg_hcd_queue_transactions</a>(hcd, tr_type);
+<a name="l00819"></a>00819         }
+<a name="l00820"></a>00820 }
+<a name="l00821"></a>00821 
+<a name="l00822"></a>00822 
+<a name="l00833"></a><a class="code" href="dwc__otg__hcd__intr_8c.html#8b774e79e18861e9ad3ab1d0de00d47c">00833</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd__intr_8c.html#8b774e79e18861e9ad3ab1d0de00d47c">halt_channel</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd,
+<a name="l00834"></a>00834                          <a class="code" href="structdwc__hc.html">dwc_hc_t</a> * hc,
+<a name="l00835"></a>00835                          <a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> * qtd, dwc_otg_halt_status_e halt_status)
+<a name="l00836"></a>00836 {
+<a name="l00837"></a>00837         <span class="keywordflow">if</span> (hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a>) {
+<a name="l00838"></a>00838                 <a class="code" href="dwc__otg__hcd__intr_8c.html#4f6bf01b14a03eeed81d27bffa5e99fc">release_channel</a>(hcd, hc, qtd, halt_status);
+<a name="l00839"></a>00839                 <span class="keywordflow">return</span>;
+<a name="l00840"></a>00840         }
+<a name="l00841"></a>00841 
+<a name="l00842"></a>00842         <span class="comment">/* Slave mode processing... */</span>
+<a name="l00843"></a>00843         <a class="code" href="dwc__otg__cil_8c.html#de044bf6b96c1bac92259a447ae85c0f">dwc_otg_hc_halt</a>(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>, hc, halt_status);
+<a name="l00844"></a>00844 
+<a name="l00845"></a>00845         <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#c3b27b33fae73aff43a9834a1ed585da">halt_on_queue</a>) {
+<a name="l00846"></a>00846                 <a class="code" href="uniongintmsk__data.html">gintmsk_data_t</a> gintmsk = {.d32 = 0 };
+<a name="l00847"></a>00847                 <a class="code" href="structdwc__otg__core__global__regs.html">dwc_otg_core_global_regs_t</a> *global_regs;
+<a name="l00848"></a>00848                 global_regs = hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>;
+<a name="l00849"></a>00849 
+<a name="l00850"></a>00850                 <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#e6169fbc92e4d79686097742ad646f5c">ep_type</a> == <a class="code" href="dwc__otg__cil_8h.html#64e5cd756330f5adab79b25cc8067bdc">DWC_OTG_EP_TYPE_CONTROL</a> ||
+<a name="l00851"></a>00851                     hc-&gt;<a class="code" href="structdwc__hc.html#e6169fbc92e4d79686097742ad646f5c">ep_type</a> == <a class="code" href="dwc__otg__cil_8h.html#9b079858cda0b917316ad9161b3881e0">DWC_OTG_EP_TYPE_BULK</a>) {
+<a name="l00852"></a>00852                         <span class="comment">/*</span>
+<a name="l00853"></a>00853 <span class="comment">                         * Make sure the Non-periodic Tx FIFO empty interrupt</span>
+<a name="l00854"></a>00854 <span class="comment">                         * is enabled so that the non-periodic schedule will</span>
+<a name="l00855"></a>00855 <span class="comment">                         * be processed.</span>
+<a name="l00856"></a>00856 <span class="comment">                         */</span>
+<a name="l00857"></a>00857                         gintmsk.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#2c395e7bef31a4d9b2d1a3257c601be4">nptxfempty</a> = 1;
+<a name="l00858"></a>00858                         dwc_modify_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#48827c76da2c6b18f369e2f2483cc4b6">gintmsk</a>, 0, gintmsk.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a>);
+<a name="l00859"></a>00859                 } <span class="keywordflow">else</span> {
+<a name="l00860"></a>00860                         <span class="comment">/*</span>
+<a name="l00861"></a>00861 <span class="comment">                         * Move the QH from the periodic queued schedule to</span>
+<a name="l00862"></a>00862 <span class="comment">                         * the periodic assigned schedule. This allows the</span>
+<a name="l00863"></a>00863 <span class="comment">                         * halt to be queued when the periodic schedule is</span>
+<a name="l00864"></a>00864 <span class="comment">                         * processed.</span>
+<a name="l00865"></a>00865 <span class="comment">                         */</span>
+<a name="l00866"></a>00866                         DWC_LIST_MOVE_HEAD(&amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#4b8deae798f771135c4a99693b26873f">periodic_sched_assigned</a>,
+<a name="l00867"></a>00867                                            &amp;hc-&gt;<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#3e1cb9863dc72139e1832c04244c25ff">qh_list_entry</a>);
+<a name="l00868"></a>00868 
+<a name="l00869"></a>00869                         <span class="comment">/*</span>
+<a name="l00870"></a>00870 <span class="comment">                         * Make sure the Periodic Tx FIFO Empty interrupt is</span>
+<a name="l00871"></a>00871 <span class="comment">                         * enabled so that the periodic schedule will be</span>
+<a name="l00872"></a>00872 <span class="comment">                         * processed.</span>
+<a name="l00873"></a>00873 <span class="comment">                         */</span>
+<a name="l00874"></a>00874                         gintmsk.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#3b52444894e041c660c146af2178272f">ptxfempty</a> = 1;
+<a name="l00875"></a>00875                         dwc_modify_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#48827c76da2c6b18f369e2f2483cc4b6">gintmsk</a>, 0, gintmsk.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a>);
+<a name="l00876"></a>00876                 }
+<a name="l00877"></a>00877         }
+<a name="l00878"></a>00878 }
+<a name="l00879"></a>00879 
+<a name="l00885"></a><a class="code" href="dwc__otg__hcd__intr_8c.html#2fa47944efef508dddcab00b0050ef0a">00885</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd__intr_8c.html#2fa47944efef508dddcab00b0050ef0a">complete_non_periodic_xfer</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd,
+<a name="l00886"></a>00886                                        <a class="code" href="structdwc__hc.html">dwc_hc_t</a> * hc,
+<a name="l00887"></a>00887                                        <a class="code" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> * hc_regs,
+<a name="l00888"></a>00888                                        <a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> * qtd,
+<a name="l00889"></a>00889                                        dwc_otg_halt_status_e halt_status)
+<a name="l00890"></a>00890 {
+<a name="l00891"></a>00891         <a class="code" href="unionhcint__data.html">hcint_data_t</a> hcint;
+<a name="l00892"></a>00892 
+<a name="l00893"></a>00893         qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#18eeb9c647049aec468bf9a7861c873f">error_count</a> = 0;
+<a name="l00894"></a>00894 
+<a name="l00895"></a>00895         hcint.<a class="code" href="unionhcint__data.html#05a82fa7693f875622db744716d7f73e">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#0dfd5bae537d58e13788508dc719480d">hcint</a>);
+<a name="l00896"></a>00896         <span class="keywordflow">if</span> (hcint.<a class="code" href="unionhcint__data.html#3ab6af507f45d91a7898dd711f4368ee">b</a>.<a class="code" href="unionhcint__data.html#755e54c3dfded3653447dfdd63fd8b6a">nyet</a>) {
+<a name="l00897"></a>00897                 <span class="comment">/*</span>
+<a name="l00898"></a>00898 <span class="comment">                 * Got a NYET on the last transaction of the transfer. This</span>
+<a name="l00899"></a>00899 <span class="comment">                 * means that the endpoint should be in the PING state at the</span>
+<a name="l00900"></a>00900 <span class="comment">                 * beginning of the next transfer.</span>
+<a name="l00901"></a>00901 <span class="comment">                 */</span>
+<a name="l00902"></a>00902                 hc-&gt;<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#2c115474978a808c797c8975d72e419d">ping_state</a> = 1;
+<a name="l00903"></a>00903                 <a class="code" href="dwc__otg__cil_8h.html#071cb1f3f29f9a52775e9fff270b1c7c">clear_hc_int</a>(hc_regs, nyet);
+<a name="l00904"></a>00904         }
+<a name="l00905"></a>00905 
+<a name="l00906"></a>00906         <span class="comment">/*</span>
+<a name="l00907"></a>00907 <span class="comment">         * Always halt and release the host channel to make it available for</span>
+<a name="l00908"></a>00908 <span class="comment">         * more transfers. There may still be more phases for a control</span>
+<a name="l00909"></a>00909 <span class="comment">         * transfer or more data packets for a bulk transfer at this point,</span>
+<a name="l00910"></a>00910 <span class="comment">         * but the host channel is still halted. A channel will be reassigned</span>
+<a name="l00911"></a>00911 <span class="comment">         * to the transfer when the non-periodic schedule is processed after</span>
+<a name="l00912"></a>00912 <span class="comment">         * the channel is released. This allows transactions to be queued</span>
+<a name="l00913"></a>00913 <span class="comment">         * properly via dwc_otg_hcd_queue_transactions, which also enables the</span>
+<a name="l00914"></a>00914 <span class="comment">         * Tx FIFO Empty interrupt if necessary.</span>
+<a name="l00915"></a>00915 <span class="comment">         */</span>
+<a name="l00916"></a>00916         <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#c5088d431f5efc382121f201f5d571aa">ep_is_in</a>) {
+<a name="l00917"></a>00917                 <span class="comment">/*</span>
+<a name="l00918"></a>00918 <span class="comment">                 * IN transfers in Slave mode require an explicit disable to</span>
+<a name="l00919"></a>00919 <span class="comment">                 * halt the channel. (In DMA mode, this call simply releases</span>
+<a name="l00920"></a>00920 <span class="comment">                 * the channel.)</span>
+<a name="l00921"></a>00921 <span class="comment">                 */</span>
+<a name="l00922"></a>00922                 <a class="code" href="dwc__otg__hcd__intr_8c.html#8b774e79e18861e9ad3ab1d0de00d47c">halt_channel</a>(hcd, hc, qtd, halt_status);
+<a name="l00923"></a>00923         } <span class="keywordflow">else</span> {
+<a name="l00924"></a>00924                 <span class="comment">/*</span>
+<a name="l00925"></a>00925 <span class="comment">                 * The channel is automatically disabled by the core for OUT</span>
+<a name="l00926"></a>00926 <span class="comment">                 * transfers in Slave mode.</span>
+<a name="l00927"></a>00927 <span class="comment">                 */</span>
+<a name="l00928"></a>00928                 <a class="code" href="dwc__otg__hcd__intr_8c.html#4f6bf01b14a03eeed81d27bffa5e99fc">release_channel</a>(hcd, hc, qtd, halt_status);
+<a name="l00929"></a>00929         }
+<a name="l00930"></a>00930 }
+<a name="l00931"></a>00931 
+<a name="l00937"></a><a class="code" href="dwc__otg__hcd__intr_8c.html#a0fa0d4fa5f0af15860d685bb8fe3e50">00937</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd__intr_8c.html#a0fa0d4fa5f0af15860d685bb8fe3e50">complete_periodic_xfer</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd,
+<a name="l00938"></a>00938                                    <a class="code" href="structdwc__hc.html">dwc_hc_t</a> * hc,
+<a name="l00939"></a>00939                                    <a class="code" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> * hc_regs,
+<a name="l00940"></a>00940                                    <a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> * qtd,
+<a name="l00941"></a>00941                                    dwc_otg_halt_status_e halt_status)
+<a name="l00942"></a>00942 {
+<a name="l00943"></a>00943         <a class="code" href="unionhctsiz__data.html">hctsiz_data_t</a> hctsiz;
+<a name="l00944"></a>00944         qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#18eeb9c647049aec468bf9a7861c873f">error_count</a> = 0;
+<a name="l00945"></a>00945 
+<a name="l00946"></a>00946         hctsiz.<a class="code" href="unionhctsiz__data.html#fb41950555c60c6015294bdefe9cd39d">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#c6173f823ba754d9f9549422b6380ca2">hctsiz</a>);
+<a name="l00947"></a>00947         <span class="keywordflow">if</span> (!hc-&gt;<a class="code" href="structdwc__hc.html#c5088d431f5efc382121f201f5d571aa">ep_is_in</a> || hctsiz.<a class="code" href="unionhctsiz__data.html#8967fa90c651bce44a3cbe90c44cf638">b</a>.<a class="code" href="unionhctsiz__data.html#3ea18df5a98d33a6f8fa786252a0205b">pktcnt</a> == 0) {
+<a name="l00948"></a>00948                 <span class="comment">/* Core halts channel in these cases. */</span>
+<a name="l00949"></a>00949                 <a class="code" href="dwc__otg__hcd__intr_8c.html#4f6bf01b14a03eeed81d27bffa5e99fc">release_channel</a>(hcd, hc, qtd, halt_status);
+<a name="l00950"></a>00950         } <span class="keywordflow">else</span> {
+<a name="l00951"></a>00951                 <span class="comment">/* Flush any outstanding requests from the Tx queue. */</span>
+<a name="l00952"></a>00952                 <a class="code" href="dwc__otg__hcd__intr_8c.html#8b774e79e18861e9ad3ab1d0de00d47c">halt_channel</a>(hcd, hc, qtd, halt_status);
+<a name="l00953"></a>00953         }
+<a name="l00954"></a>00954 }
+<a name="l00955"></a>00955 
+<a name="l00956"></a><a class="code" href="dwc__otg__hcd__intr_8c.html#a56eb0602c101ab380581b164973fb33">00956</a> <span class="keyword">static</span> int32_t <a class="code" href="dwc__otg__hcd__intr_8c.html#a56eb0602c101ab380581b164973fb33">handle_xfercomp_isoc_split_in</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd,
+<a name="l00957"></a>00957                                              <a class="code" href="structdwc__hc.html">dwc_hc_t</a> * hc,
+<a name="l00958"></a>00958                                              <a class="code" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> * hc_regs,
+<a name="l00959"></a>00959                                              <a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> * qtd)
+<a name="l00960"></a>00960 {
+<a name="l00961"></a>00961         uint32_t len;   
+<a name="l00962"></a>00962         <span class="keyword">struct </span><a class="code" href="structdwc__otg__hcd__iso__packet__desc.html">dwc_otg_hcd_iso_packet_desc</a> *frame_desc;
+<a name="l00963"></a>00963         frame_desc = &amp;qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#7e7767808e8eb9d71de0db00f57553f9">urb</a>-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#ed542f6a2d99dba2f6b71b0d8012ec8a">iso_descs</a>[qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#c67d5f885976d0698f20d113d32b4b30">isoc_frame_index</a>];
+<a name="l00964"></a>00964                                 
+<a name="l00965"></a>00965         len = <a class="code" href="dwc__otg__hcd__intr_8c.html#6cdb134cbb3cdf3501ca39761137baf0">get_actual_xfer_length</a>(hc, hc_regs, qtd,
+<a name="l00966"></a>00966                                      DWC_OTG_HC_XFER_COMPLETE,
+<a name="l00967"></a>00967                                      NULL);
+<a name="l00968"></a>00968                      
+<a name="l00969"></a>00969         <span class="keywordflow">if</span> (!len) {
+<a name="l00970"></a>00970                 qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#6355e968a4d36edce3e22c89ac7b5001">complete_split</a> = 0;
+<a name="l00971"></a>00971                 qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#839371940a7e34365e2272f3214b7e34">isoc_split_offset</a> = 0;
+<a name="l00972"></a>00972                 <span class="keywordflow">return</span> 0;
+<a name="l00973"></a>00973         }
+<a name="l00974"></a>00974         frame_desc-&gt;<a class="code" href="structdwc__otg__hcd__iso__packet__desc.html#c00b967f4c613820b99efc0abda5178c">actual_length</a> += len;
+<a name="l00975"></a>00975         
+<a name="l00976"></a>00976         <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#e0c3ba51a04b36656baa4e70fc63cf77">align_buff</a> &amp;&amp; len)
+<a name="l00977"></a>00977                 dwc_memcpy(qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#7e7767808e8eb9d71de0db00f57553f9">urb</a>-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#99ae35ffcd6147ddb93b361ab3bcfe95">buf</a> + frame_desc-&gt;<a class="code" href="structdwc__otg__hcd__iso__packet__desc.html#246f3d147a22cd295c534253593dca4a">offset</a> + qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#839371940a7e34365e2272f3214b7e34">isoc_split_offset</a>, 
+<a name="l00978"></a>00978                                                                 hc-&gt;<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#aac9f90a6afd9056dce79d013dd2168b">dw_align_buf</a>, 
+<a name="l00979"></a>00979                                                                 len);
+<a name="l00980"></a>00980         qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#839371940a7e34365e2272f3214b7e34">isoc_split_offset</a> += len;
+<a name="l00981"></a>00981         
+<a name="l00982"></a>00982         <span class="keywordflow">if</span> (frame_desc-&gt;<a class="code" href="structdwc__otg__hcd__iso__packet__desc.html#8392d21b820df0181f4e6dca91234543">length</a> == frame_desc-&gt;<a class="code" href="structdwc__otg__hcd__iso__packet__desc.html#c00b967f4c613820b99efc0abda5178c">actual_length</a>) {
+<a name="l00983"></a>00983                 frame_desc-&gt;<a class="code" href="structdwc__otg__hcd__iso__packet__desc.html#d070772c24621c47b49ad21c6acadb94">status</a> = 0;
+<a name="l00984"></a>00984                 qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#c67d5f885976d0698f20d113d32b4b30">isoc_frame_index</a>++;
+<a name="l00985"></a>00985                 qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#6355e968a4d36edce3e22c89ac7b5001">complete_split</a> = 0;
+<a name="l00986"></a>00986                 qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#839371940a7e34365e2272f3214b7e34">isoc_split_offset</a> = 0;
+<a name="l00987"></a>00987         }
+<a name="l00988"></a>00988                         
+<a name="l00989"></a>00989         <span class="keywordflow">if</span> (qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#c67d5f885976d0698f20d113d32b4b30">isoc_frame_index</a> == qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#7e7767808e8eb9d71de0db00f57553f9">urb</a>-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#570583697e8c1e4398969630bc2562f8">packet_count</a>) {
+<a name="l00990"></a>00990                 hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#ffefbd33a59a14b8b46406f5aaeaa2f4">fops</a>-&gt;<a class="code" href="structdwc__otg__hcd__function__ops.html#09a989481103de7468cd46ef61ace0ce">complete</a>(hcd, qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#7e7767808e8eb9d71de0db00f57553f9">urb</a>-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#5ba0e393ef9768275db85c00e68be477">priv</a>, qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#7e7767808e8eb9d71de0db00f57553f9">urb</a>, 0);
+<a name="l00991"></a>00991                 <a class="code" href="dwc__otg__hcd__intr_8c.html#4f6bf01b14a03eeed81d27bffa5e99fc">release_channel</a>(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
+<a name="l00992"></a>00992         } <span class="keywordflow">else</span> {
+<a name="l00993"></a>00993                 <a class="code" href="dwc__otg__hcd__intr_8c.html#4f6bf01b14a03eeed81d27bffa5e99fc">release_channel</a>(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
+<a name="l00994"></a>00994         }
+<a name="l00995"></a>00995         
+<a name="l00996"></a>00996         <span class="keywordflow">return</span> 1; <span class="comment">/* Indicates that channel released */</span>
+<a name="l00997"></a>00997 }
+<a name="l01002"></a><a class="code" href="dwc__otg__hcd__intr_8c.html#e8bfcabff910322ef19eec9fc99fd097">01002</a> <span class="keyword">static</span> int32_t <a class="code" href="dwc__otg__hcd__intr_8c.html#e8bfcabff910322ef19eec9fc99fd097">handle_hc_xfercomp_intr</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd,
+<a name="l01003"></a>01003                                        <a class="code" href="structdwc__hc.html">dwc_hc_t</a> * hc,
+<a name="l01004"></a>01004                                        <a class="code" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> * hc_regs,
+<a name="l01005"></a>01005                                        <a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> * qtd)
+<a name="l01006"></a>01006 {
+<a name="l01007"></a>01007         <span class="keywordtype">int</span> urb_xfer_done;
+<a name="l01008"></a>01008         dwc_otg_halt_status_e halt_status = DWC_OTG_HC_XFER_COMPLETE;
+<a name="l01009"></a>01009         <a class="code" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *urb = qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#7e7767808e8eb9d71de0db00f57553f9">urb</a>;
+<a name="l01010"></a>01010         <span class="keywordtype">int</span> pipe_type = <a class="code" href="dwc__otg__hcd_8h.html#b97cea598797e69d011ffef89989a739">dwc_otg_hcd_get_pipe_type</a>(&amp;urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#34ee3ac5931687b41dd726f00c558369">pipe_info</a>);
+<a name="l01011"></a>01011 
+<a name="l01012"></a>01012         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#e4a050e176c1c4f556da2b276a8c2b37">DBG_HCD</a>, <span class="stringliteral">"--Host Channel %d Interrupt: "</span>
+<a name="l01013"></a>01013                     <span class="stringliteral">"Transfer Complete--\n"</span>, hc-&gt;<a class="code" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">hc_num</a>);
+<a name="l01014"></a>01014 
+<a name="l01015"></a>01015         <span class="keywordflow">if</span> (hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a>) {
+<a name="l01016"></a>01016                 <a class="code" href="dwc__otg__hcd_8h.html#ca94cde3142ff1121bb0ff9bd44fa762">dwc_otg_hcd_complete_xfer_ddma</a>(hcd, hc, hc_regs, halt_status);
+<a name="l01017"></a>01017                 <span class="keywordflow">if</span> (pipe_type == UE_ISOCHRONOUS) {
+<a name="l01018"></a>01018                         <span class="comment">/* Do not disable the interrupt, just clear it */</span>       
+<a name="l01019"></a>01019                         <a class="code" href="dwc__otg__cil_8h.html#071cb1f3f29f9a52775e9fff270b1c7c">clear_hc_int</a>(hc_regs, xfercomp);
+<a name="l01020"></a>01020                         <span class="keywordflow">return</span> 1;
+<a name="l01021"></a>01021                 }
+<a name="l01022"></a>01022                 <span class="keywordflow">goto</span> handle_xfercomp_done;
+<a name="l01023"></a>01023         }
+<a name="l01024"></a>01024 
+<a name="l01025"></a>01025         <span class="comment">/*</span>
+<a name="l01026"></a>01026 <span class="comment">         * Handle xfer complete on CSPLIT.</span>
+<a name="l01027"></a>01027 <span class="comment">         */</span>
+<a name="l01028"></a>01028 
+<a name="l01029"></a>01029         <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#8708dd009988ce20b8a8d52a4a96c5a3">do_split</a>) {
+<a name="l01030"></a>01030                 <span class="keywordflow">if</span> ((hc-&gt;<a class="code" href="structdwc__hc.html#e6169fbc92e4d79686097742ad646f5c">ep_type</a> == <a class="code" href="dwc__otg__cil_8h.html#152a3a5e1433bd2197672f0b5105e7a4">DWC_OTG_EP_TYPE_ISOC</a>) &amp;&amp; hc-&gt;<a class="code" href="structdwc__hc.html#c5088d431f5efc382121f201f5d571aa">ep_is_in</a> &amp;&amp; hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a>) {
+<a name="l01031"></a>01031                         <span class="keywordflow">if</span> (qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#6355e968a4d36edce3e22c89ac7b5001">complete_split</a> &amp;&amp; <a class="code" href="dwc__otg__hcd__intr_8c.html#a56eb0602c101ab380581b164973fb33">handle_xfercomp_isoc_split_in</a>(hcd, hc, hc_regs, qtd))
+<a name="l01032"></a>01032                                 <span class="keywordflow">goto</span> handle_xfercomp_done;
+<a name="l01033"></a>01033                 }
+<a name="l01034"></a>01034                 <span class="keywordflow">else</span> {
+<a name="l01035"></a>01035                 qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#6355e968a4d36edce3e22c89ac7b5001">complete_split</a> = 0;
+<a name="l01036"></a>01036         }
+<a name="l01037"></a>01037         }       
+<a name="l01038"></a>01038 
+<a name="l01039"></a>01039         <span class="comment">/* Update the QTD and URB states. */</span>
+<a name="l01040"></a>01040         <span class="keywordflow">switch</span> (pipe_type) {
+<a name="l01041"></a>01041         <span class="keywordflow">case</span> UE_CONTROL:
+<a name="l01042"></a>01042                 <span class="keywordflow">switch</span> (qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#5189ec9c992974d20477481eaf96d0bb">control_phase</a>) {
+<a name="l01043"></a>01043                 <span class="keywordflow">case</span> DWC_OTG_CONTROL_SETUP:
+<a name="l01044"></a>01044                         <span class="keywordflow">if</span> (urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#dca57de4fdecd894241ce24167206a45">length</a> &gt; 0) {
+<a name="l01045"></a>01045                                 qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#5189ec9c992974d20477481eaf96d0bb">control_phase</a> = DWC_OTG_CONTROL_DATA;
+<a name="l01046"></a>01046                         } <span class="keywordflow">else</span> {
+<a name="l01047"></a>01047                                 qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#5189ec9c992974d20477481eaf96d0bb">control_phase</a> = DWC_OTG_CONTROL_STATUS;
+<a name="l01048"></a>01048                         }
+<a name="l01049"></a>01049                         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>,
+<a name="l01050"></a>01050                                     <span class="stringliteral">"  Control setup transaction done\n"</span>);
+<a name="l01051"></a>01051                         halt_status = DWC_OTG_HC_XFER_COMPLETE;
+<a name="l01052"></a>01052                         <span class="keywordflow">break</span>;
+<a name="l01053"></a>01053                 <span class="keywordflow">case</span> DWC_OTG_CONTROL_DATA:{
+<a name="l01054"></a>01054                                 urb_xfer_done =
+<a name="l01055"></a>01055                                     <a class="code" href="dwc__otg__hcd__intr_8c.html#ecb30a961e8d4831e8691d45a77162e3">update_urb_state_xfer_comp</a>(hc, hc_regs, urb,
+<a name="l01056"></a>01056                                                                qtd);
+<a name="l01057"></a>01057                                 <span class="keywordflow">if</span> (urb_xfer_done) {
+<a name="l01058"></a>01058                                         qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#5189ec9c992974d20477481eaf96d0bb">control_phase</a> =
+<a name="l01059"></a>01059                                             DWC_OTG_CONTROL_STATUS;
+<a name="l01060"></a>01060                                         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>,
+<a name="l01061"></a>01061                                                     <span class="stringliteral">"  Control data transfer done\n"</span>);
+<a name="l01062"></a>01062                                 } <span class="keywordflow">else</span> {
+<a name="l01063"></a>01063                                         <a class="code" href="dwc__otg__hcd_8h.html#8bce109004d7869bfdd9aa1075c6bd2c">dwc_otg_hcd_save_data_toggle</a>(hc, hc_regs, qtd);
+<a name="l01064"></a>01064                                 }
+<a name="l01065"></a>01065                                 halt_status = DWC_OTG_HC_XFER_COMPLETE;
+<a name="l01066"></a>01066                                 <span class="keywordflow">break</span>;
+<a name="l01067"></a>01067                         }
+<a name="l01068"></a>01068                 <span class="keywordflow">case</span> DWC_OTG_CONTROL_STATUS:
+<a name="l01069"></a>01069                         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"  Control transfer complete\n"</span>);
+<a name="l01070"></a>01070                         <span class="keywordflow">if</span> (urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#101e4a6762b9911cdb85768890fa1210">status</a> == -DWC_E_IN_PROGRESS) {
+<a name="l01071"></a>01071                                 urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#101e4a6762b9911cdb85768890fa1210">status</a> = 0;
+<a name="l01072"></a>01072                         }
+<a name="l01073"></a>01073                         hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#ffefbd33a59a14b8b46406f5aaeaa2f4">fops</a>-&gt;<a class="code" href="structdwc__otg__hcd__function__ops.html#09a989481103de7468cd46ef61ace0ce">complete</a>(hcd, urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#5ba0e393ef9768275db85c00e68be477">priv</a>, urb, urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#101e4a6762b9911cdb85768890fa1210">status</a>);
+<a name="l01074"></a>01074                         halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
+<a name="l01075"></a>01075                         <span class="keywordflow">break</span>;
+<a name="l01076"></a>01076                 }
+<a name="l01077"></a>01077 
+<a name="l01078"></a>01078                 <a class="code" href="dwc__otg__hcd__intr_8c.html#2fa47944efef508dddcab00b0050ef0a">complete_non_periodic_xfer</a>(hcd, hc, hc_regs, qtd, halt_status);
+<a name="l01079"></a>01079                 <span class="keywordflow">break</span>;
+<a name="l01080"></a>01080         <span class="keywordflow">case</span> UE_BULK:
+<a name="l01081"></a>01081                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"  Bulk transfer complete\n"</span>);
+<a name="l01082"></a>01082                 urb_xfer_done =
+<a name="l01083"></a>01083                     <a class="code" href="dwc__otg__hcd__intr_8c.html#ecb30a961e8d4831e8691d45a77162e3">update_urb_state_xfer_comp</a>(hc, hc_regs, urb, qtd);
+<a name="l01084"></a>01084                 <span class="keywordflow">if</span> (urb_xfer_done) {
+<a name="l01085"></a>01085                         hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#ffefbd33a59a14b8b46406f5aaeaa2f4">fops</a>-&gt;<a class="code" href="structdwc__otg__hcd__function__ops.html#09a989481103de7468cd46ef61ace0ce">complete</a>(hcd, urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#5ba0e393ef9768275db85c00e68be477">priv</a>, urb, urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#101e4a6762b9911cdb85768890fa1210">status</a>);
+<a name="l01086"></a>01086                         halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
+<a name="l01087"></a>01087                 } <span class="keywordflow">else</span> {
+<a name="l01088"></a>01088                         halt_status = DWC_OTG_HC_XFER_COMPLETE;
+<a name="l01089"></a>01089                 }
+<a name="l01090"></a>01090 
+<a name="l01091"></a>01091                 <a class="code" href="dwc__otg__hcd_8h.html#8bce109004d7869bfdd9aa1075c6bd2c">dwc_otg_hcd_save_data_toggle</a>(hc, hc_regs, qtd);
+<a name="l01092"></a>01092                 <a class="code" href="dwc__otg__hcd__intr_8c.html#2fa47944efef508dddcab00b0050ef0a">complete_non_periodic_xfer</a>(hcd, hc, hc_regs, qtd, halt_status);
+<a name="l01093"></a>01093                 <span class="keywordflow">break</span>;
+<a name="l01094"></a>01094         <span class="keywordflow">case</span> UE_INTERRUPT:
+<a name="l01095"></a>01095                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"  Interrupt transfer complete\n"</span>);
+<a name="l01096"></a>01096                 <a class="code" href="dwc__otg__hcd__intr_8c.html#ecb30a961e8d4831e8691d45a77162e3">update_urb_state_xfer_comp</a>(hc, hc_regs, urb, qtd);
+<a name="l01097"></a>01097 
+<a name="l01098"></a>01098                 <span class="comment">/*</span>
+<a name="l01099"></a>01099 <span class="comment">                 * Interrupt URB is done on the first transfer complete</span>
+<a name="l01100"></a>01100 <span class="comment">                 * interrupt.</span>
+<a name="l01101"></a>01101 <span class="comment">                 */</span>
+<a name="l01102"></a>01102                 hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#ffefbd33a59a14b8b46406f5aaeaa2f4">fops</a>-&gt;<a class="code" href="structdwc__otg__hcd__function__ops.html#09a989481103de7468cd46ef61ace0ce">complete</a>(hcd, urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#5ba0e393ef9768275db85c00e68be477">priv</a>, urb, urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#101e4a6762b9911cdb85768890fa1210">status</a>);
+<a name="l01103"></a>01103                 <a class="code" href="dwc__otg__hcd_8h.html#8bce109004d7869bfdd9aa1075c6bd2c">dwc_otg_hcd_save_data_toggle</a>(hc, hc_regs, qtd);
+<a name="l01104"></a>01104                 <a class="code" href="dwc__otg__hcd__intr_8c.html#a0fa0d4fa5f0af15860d685bb8fe3e50">complete_periodic_xfer</a>(hcd, hc, hc_regs, qtd,
+<a name="l01105"></a>01105                                        DWC_OTG_HC_XFER_URB_COMPLETE);
+<a name="l01106"></a>01106                 <span class="keywordflow">break</span>;
+<a name="l01107"></a>01107         <span class="keywordflow">case</span> UE_ISOCHRONOUS:
+<a name="l01108"></a>01108                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"  Isochronous transfer complete\n"</span>);
+<a name="l01109"></a>01109                 <span class="keywordflow">if</span> (qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#ab224d64d72f2ef4f10e722ebcfa29a6">isoc_split_pos</a> == <a class="code" href="dwc__otg__regs_8h.html#b8a8f35d8fd73c955cc0403e87cea0c6">DWC_HCSPLIT_XACTPOS_ALL</a>) {
+<a name="l01110"></a>01110                         halt_status =
+<a name="l01111"></a>01111                             <a class="code" href="dwc__otg__hcd__intr_8c.html#e93d54bdf873c5a31882660c2984458e">update_isoc_urb_state</a>(hcd, hc, hc_regs, qtd,
+<a name="l01112"></a>01112                                                   DWC_OTG_HC_XFER_COMPLETE);
+<a name="l01113"></a>01113                 }
+<a name="l01114"></a>01114                 <a class="code" href="dwc__otg__hcd__intr_8c.html#a0fa0d4fa5f0af15860d685bb8fe3e50">complete_periodic_xfer</a>(hcd, hc, hc_regs, qtd, halt_status);
+<a name="l01115"></a>01115                 <span class="keywordflow">break</span>;
+<a name="l01116"></a>01116         }
+<a name="l01117"></a>01117 
+<a name="l01118"></a>01118 handle_xfercomp_done:
+<a name="l01119"></a>01119         <a class="code" href="dwc__otg__cil_8h.html#e530fa4a6ed31f67cad65969355651ef">disable_hc_int</a>(hc_regs, xfercompl);
+<a name="l01120"></a>01120 
+<a name="l01121"></a>01121         <span class="keywordflow">return</span> 1;
+<a name="l01122"></a>01122 }
+<a name="l01123"></a>01123 
+<a name="l01128"></a><a class="code" href="dwc__otg__hcd__intr_8c.html#e89fabf3023fa4f0279f312e5e9d4223">01128</a> <span class="keyword">static</span> int32_t <a class="code" href="dwc__otg__hcd__intr_8c.html#e89fabf3023fa4f0279f312e5e9d4223">handle_hc_stall_intr</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd,
+<a name="l01129"></a>01129                                     <a class="code" href="structdwc__hc.html">dwc_hc_t</a> * hc,
+<a name="l01130"></a>01130                                     <a class="code" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> * hc_regs,
+<a name="l01131"></a>01131                                     <a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> * qtd)
+<a name="l01132"></a>01132 {
+<a name="l01133"></a>01133         <a class="code" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *urb = qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#7e7767808e8eb9d71de0db00f57553f9">urb</a>;
+<a name="l01134"></a>01134         <span class="keywordtype">int</span> pipe_type = <a class="code" href="dwc__otg__hcd_8h.html#b97cea598797e69d011ffef89989a739">dwc_otg_hcd_get_pipe_type</a>(&amp;urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#34ee3ac5931687b41dd726f00c558369">pipe_info</a>);
+<a name="l01135"></a>01135 
+<a name="l01136"></a>01136         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#e4a050e176c1c4f556da2b276a8c2b37">DBG_HCD</a>, <span class="stringliteral">"--Host Channel %d Interrupt: "</span>
+<a name="l01137"></a>01137                     <span class="stringliteral">"STALL Received--\n"</span>, hc-&gt;<a class="code" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">hc_num</a>);
+<a name="l01138"></a>01138 
+<a name="l01139"></a>01139         <span class="keywordflow">if</span> (hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a>) {
+<a name="l01140"></a>01140                 <a class="code" href="dwc__otg__hcd_8h.html#ca94cde3142ff1121bb0ff9bd44fa762">dwc_otg_hcd_complete_xfer_ddma</a>(hcd, hc, hc_regs, DWC_OTG_HC_XFER_STALL);
+<a name="l01141"></a>01141                 <span class="keywordflow">goto</span> handle_stall_done;
+<a name="l01142"></a>01142         }
+<a name="l01143"></a>01143 
+<a name="l01144"></a>01144         <span class="keywordflow">if</span> (pipe_type == UE_CONTROL) {
+<a name="l01145"></a>01145                 hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#ffefbd33a59a14b8b46406f5aaeaa2f4">fops</a>-&gt;<a class="code" href="structdwc__otg__hcd__function__ops.html#09a989481103de7468cd46ef61ace0ce">complete</a>(hcd, urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#5ba0e393ef9768275db85c00e68be477">priv</a>, urb, -DWC_E_PIPE);
+<a name="l01146"></a>01146         }
+<a name="l01147"></a>01147 
+<a name="l01148"></a>01148         <span class="keywordflow">if</span> (pipe_type == UE_BULK || pipe_type == UE_INTERRUPT) {
+<a name="l01149"></a>01149                 hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#ffefbd33a59a14b8b46406f5aaeaa2f4">fops</a>-&gt;<a class="code" href="structdwc__otg__hcd__function__ops.html#09a989481103de7468cd46ef61ace0ce">complete</a>(hcd, urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#5ba0e393ef9768275db85c00e68be477">priv</a>, urb, -DWC_E_PIPE);
+<a name="l01150"></a>01150                 <span class="comment">/*</span>
+<a name="l01151"></a>01151 <span class="comment">                 * USB protocol requires resetting the data toggle for bulk</span>
+<a name="l01152"></a>01152 <span class="comment">                 * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT)</span>
+<a name="l01153"></a>01153 <span class="comment">                 * setup command is issued to the endpoint. Anticipate the</span>
+<a name="l01154"></a>01154 <span class="comment">                 * CLEAR_FEATURE command since a STALL has occurred and reset</span>
+<a name="l01155"></a>01155 <span class="comment">                 * the data toggle now.</span>
+<a name="l01156"></a>01156 <span class="comment">                 */</span>
+<a name="l01157"></a>01157                 hc-&gt;<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#b0e001bfd76f5781926795ac47ef2c25">data_toggle</a> = 0;
+<a name="l01158"></a>01158         }
+<a name="l01159"></a>01159 
+<a name="l01160"></a>01160         <a class="code" href="dwc__otg__hcd__intr_8c.html#8b774e79e18861e9ad3ab1d0de00d47c">halt_channel</a>(hcd, hc, qtd, DWC_OTG_HC_XFER_STALL);
+<a name="l01161"></a>01161 
+<a name="l01162"></a>01162 handle_stall_done:
+<a name="l01163"></a>01163         <a class="code" href="dwc__otg__cil_8h.html#e530fa4a6ed31f67cad65969355651ef">disable_hc_int</a>(hc_regs, stall);
+<a name="l01164"></a>01164 
+<a name="l01165"></a>01165         <span class="keywordflow">return</span> 1;
+<a name="l01166"></a>01166 }
+<a name="l01167"></a>01167 
+<a name="l01168"></a>01168 <span class="comment">/*</span>
+<a name="l01169"></a>01169 <span class="comment"> * Updates the state of the URB when a transfer has been stopped due to an</span>
+<a name="l01170"></a>01170 <span class="comment"> * abnormal condition before the transfer completes. Modifies the</span>
+<a name="l01171"></a>01171 <span class="comment"> * actual_length field of the URB to reflect the number of bytes that have</span>
+<a name="l01172"></a>01172 <span class="comment"> * actually been transferred via the host channel.</span>
+<a name="l01173"></a>01173 <span class="comment"> */</span>
+<a name="l01174"></a><a class="code" href="dwc__otg__hcd__intr_8c.html#0640c3606be7a8700ea4813e590ebf43">01174</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd__intr_8c.html#0640c3606be7a8700ea4813e590ebf43">update_urb_state_xfer_intr</a>(<a class="code" href="structdwc__hc.html">dwc_hc_t</a> * hc,
+<a name="l01175"></a>01175                                        <a class="code" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> * hc_regs,
+<a name="l01176"></a>01176                                        <a class="code" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> * urb,
+<a name="l01177"></a>01177                                        <a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> * qtd,
+<a name="l01178"></a>01178                                        dwc_otg_halt_status_e halt_status)
+<a name="l01179"></a>01179 {
+<a name="l01180"></a>01180         uint32_t bytes_transferred = <a class="code" href="dwc__otg__hcd__intr_8c.html#6cdb134cbb3cdf3501ca39761137baf0">get_actual_xfer_length</a>(hc, hc_regs, qtd,
+<a name="l01181"></a>01181                                                             halt_status, NULL);
+<a name="l01182"></a>01182         <span class="comment">/* non DWORD-aligned buffer case handling. */</span>
+<a name="l01183"></a>01183         <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#e0c3ba51a04b36656baa4e70fc63cf77">align_buff</a> &amp;&amp; bytes_transferred &amp;&amp; hc-&gt;<a class="code" href="structdwc__hc.html#c5088d431f5efc382121f201f5d571aa">ep_is_in</a>) {
+<a name="l01184"></a>01184                 dwc_memcpy(urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#99ae35ffcd6147ddb93b361ab3bcfe95">buf</a> + urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#742c8a97d3867ab89148eae34e0c73a6">actual_length</a>, hc-&gt;<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#aac9f90a6afd9056dce79d013dd2168b">dw_align_buf</a>, bytes_transferred);
+<a name="l01185"></a>01185         }
+<a name="l01186"></a>01186         
+<a name="l01187"></a>01187         urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#742c8a97d3867ab89148eae34e0c73a6">actual_length</a> += bytes_transferred;
+<a name="l01188"></a>01188 
+<a name="l01189"></a>01189 <span class="preprocessor">#ifdef DEBUG</span>
+<a name="l01190"></a>01190 <span class="preprocessor"></span>        {
+<a name="l01191"></a>01191                 <a class="code" href="unionhctsiz__data.html">hctsiz_data_t</a> hctsiz;
+<a name="l01192"></a>01192                 hctsiz.<a class="code" href="unionhctsiz__data.html#fb41950555c60c6015294bdefe9cd39d">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#c6173f823ba754d9f9549422b6380ca2">hctsiz</a>);
+<a name="l01193"></a>01193                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"DWC_otg: %s: %s, channel %d\n"</span>,
+<a name="l01194"></a>01194                             __func__, (hc-&gt;<a class="code" href="structdwc__hc.html#c5088d431f5efc382121f201f5d571aa">ep_is_in</a> ? <span class="stringliteral">"IN"</span> : <span class="stringliteral">"OUT"</span>),
+<a name="l01195"></a>01195                             hc-&gt;<a class="code" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">hc_num</a>);
+<a name="l01196"></a>01196                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"  hc-&gt;start_pkt_count %d\n"</span>,
+<a name="l01197"></a>01197                             hc-&gt;<a class="code" href="structdwc__hc.html#6c030bc725f43025d3046d17b4fbee4e">start_pkt_count</a>);
+<a name="l01198"></a>01198                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"  hctsiz.pktcnt %d\n"</span>, hctsiz.<a class="code" href="unionhctsiz__data.html#8967fa90c651bce44a3cbe90c44cf638">b</a>.<a class="code" href="unionhctsiz__data.html#3ea18df5a98d33a6f8fa786252a0205b">pktcnt</a>);
+<a name="l01199"></a>01199                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"  hc-&gt;max_packet %d\n"</span>, hc-&gt;<a class="code" href="structdwc__hc.html#bd88f02eb286ba01d8d1b049e8975ccb">max_packet</a>);
+<a name="l01200"></a>01200                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"  bytes_transferred %d\n"</span>,
+<a name="l01201"></a>01201                             bytes_transferred);
+<a name="l01202"></a>01202                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"  urb-&gt;actual_length %d\n"</span>,
+<a name="l01203"></a>01203                             urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#742c8a97d3867ab89148eae34e0c73a6">actual_length</a>);
+<a name="l01204"></a>01204                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"  urb-&gt;transfer_buffer_length %d\n"</span>,
+<a name="l01205"></a>01205                             urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#dca57de4fdecd894241ce24167206a45">length</a>);
+<a name="l01206"></a>01206         }
+<a name="l01207"></a>01207 <span class="preprocessor">#endif</span>
+<a name="l01208"></a>01208 <span class="preprocessor"></span>}
+<a name="l01209"></a>01209 
+<a name="l01214"></a><a class="code" href="dwc__otg__hcd__intr_8c.html#19f718e1e8f7cded3bb7431008ee0309">01214</a> <span class="keyword">static</span> int32_t <a class="code" href="dwc__otg__hcd__intr_8c.html#19f718e1e8f7cded3bb7431008ee0309">handle_hc_nak_intr</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd,
+<a name="l01215"></a>01215                                   <a class="code" href="structdwc__hc.html">dwc_hc_t</a> * hc,
+<a name="l01216"></a>01216                                   <a class="code" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> * hc_regs,
+<a name="l01217"></a>01217                                   <a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> * qtd)
+<a name="l01218"></a>01218 {
+<a name="l01219"></a>01219         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#e4a050e176c1c4f556da2b276a8c2b37">DBG_HCD</a>, <span class="stringliteral">"--Host Channel %d Interrupt: "</span>
+<a name="l01220"></a>01220                     <span class="stringliteral">"NAK Received--\n"</span>, hc-&gt;<a class="code" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">hc_num</a>);
+<a name="l01221"></a>01221 
+<a name="l01222"></a>01222         <span class="comment">/*</span>
+<a name="l01223"></a>01223 <span class="comment">         * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and</span>
+<a name="l01224"></a>01224 <span class="comment">         * interrupt.  Re-start the SSPLIT transfer.</span>
+<a name="l01225"></a>01225 <span class="comment">         */</span>
+<a name="l01226"></a>01226         <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#4365ef67d517a621a626ac5392545c6d">do_split</a>) {
+<a name="l01227"></a>01227                 <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#21e00df6fb9a555975879526118d599e">complete_split</a>) {
+<a name="l01228"></a>01228                         qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#18eeb9c647049aec468bf9a7861c873f">error_count</a> = 0;
+<a name="l01229"></a>01229                 }
+<a name="l01230"></a>01230                 qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#6355e968a4d36edce3e22c89ac7b5001">complete_split</a> = 0;
+<a name="l01231"></a>01231                 <a class="code" href="dwc__otg__hcd__intr_8c.html#8b774e79e18861e9ad3ab1d0de00d47c">halt_channel</a>(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
+<a name="l01232"></a>01232                 <span class="keywordflow">goto</span> handle_nak_done;
+<a name="l01233"></a>01233         }
+<a name="l01234"></a>01234 
+<a name="l01235"></a>01235         <span class="keywordflow">switch</span> (<a class="code" href="dwc__otg__hcd_8h.html#b97cea598797e69d011ffef89989a739">dwc_otg_hcd_get_pipe_type</a>(&amp;qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#7e7767808e8eb9d71de0db00f57553f9">urb</a>-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#34ee3ac5931687b41dd726f00c558369">pipe_info</a>)) {
+<a name="l01236"></a>01236         <span class="keywordflow">case</span> UE_CONTROL:
+<a name="l01237"></a>01237         <span class="keywordflow">case</span> UE_BULK:
+<a name="l01238"></a>01238                 <span class="keywordflow">if</span> (hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a> &amp;&amp; hc-&gt;<a class="code" href="structdwc__hc.html#c5088d431f5efc382121f201f5d571aa">ep_is_in</a>) {
+<a name="l01239"></a>01239                         <span class="comment">/*</span>
+<a name="l01240"></a>01240 <span class="comment">                         * NAK interrupts are enabled on bulk/control IN</span>
+<a name="l01241"></a>01241 <span class="comment">                         * transfers in DMA mode for the sole purpose of</span>
+<a name="l01242"></a>01242 <span class="comment">                         * resetting the error count after a transaction error</span>
+<a name="l01243"></a>01243 <span class="comment">                         * occurs. The core will continue transferring data.</span>
+<a name="l01244"></a>01244 <span class="comment">                         */</span>
+<a name="l01245"></a>01245                         qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#18eeb9c647049aec468bf9a7861c873f">error_count</a> = 0;
+<a name="l01246"></a>01246                         <span class="keywordflow">goto</span> handle_nak_done;
+<a name="l01247"></a>01247                 }
+<a name="l01248"></a>01248 
+<a name="l01249"></a>01249                 <span class="comment">/*</span>
+<a name="l01250"></a>01250 <span class="comment">                 * NAK interrupts normally occur during OUT transfers in DMA</span>
+<a name="l01251"></a>01251 <span class="comment">                 * or Slave mode. For IN transfers, more requests will be</span>
+<a name="l01252"></a>01252 <span class="comment">                 * queued as request queue space is available.</span>
+<a name="l01253"></a>01253 <span class="comment">                 */</span>
+<a name="l01254"></a>01254                 qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#18eeb9c647049aec468bf9a7861c873f">error_count</a> = 0;
+<a name="l01255"></a>01255 
+<a name="l01256"></a>01256                 <span class="keywordflow">if</span> (!hc-&gt;<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#2c115474978a808c797c8975d72e419d">ping_state</a>) {
+<a name="l01257"></a>01257                         <a class="code" href="dwc__otg__hcd__intr_8c.html#0640c3606be7a8700ea4813e590ebf43">update_urb_state_xfer_intr</a>(hc, hc_regs,
+<a name="l01258"></a>01258                                                    qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#7e7767808e8eb9d71de0db00f57553f9">urb</a>, qtd,
+<a name="l01259"></a>01259                                                    DWC_OTG_HC_XFER_NAK);
+<a name="l01260"></a>01260                         <a class="code" href="dwc__otg__hcd_8h.html#8bce109004d7869bfdd9aa1075c6bd2c">dwc_otg_hcd_save_data_toggle</a>(hc, hc_regs, qtd);
+<a name="l01261"></a>01261 
+<a name="l01262"></a>01262                         <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#570b78178975193edb921af1ef36d37b">speed</a> == <a class="code" href="dwc__otg__cil_8h.html#b9dc03c6bc3c1113a935a73cf7021fbe">DWC_OTG_EP_SPEED_HIGH</a>)
+<a name="l01263"></a>01263                                 hc-&gt;<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#2c115474978a808c797c8975d72e419d">ping_state</a> = 1;
+<a name="l01264"></a>01264                         }
+<a name="l01265"></a>01265 
+<a name="l01266"></a>01266                 <span class="comment">/*</span>
+<a name="l01267"></a>01267 <span class="comment">                 * Halt the channel so the transfer can be re-started from</span>
+<a name="l01268"></a>01268 <span class="comment">                 * the appropriate point or the PING protocol will</span>
+<a name="l01269"></a>01269 <span class="comment">                 * start/continue.</span>
+<a name="l01270"></a>01270 <span class="comment">                 */</span>
+<a name="l01271"></a>01271                 <a class="code" href="dwc__otg__hcd__intr_8c.html#8b774e79e18861e9ad3ab1d0de00d47c">halt_channel</a>(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
+<a name="l01272"></a>01272                 <span class="keywordflow">break</span>;
+<a name="l01273"></a>01273         <span class="keywordflow">case</span> UE_INTERRUPT:
+<a name="l01274"></a>01274                 qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#18eeb9c647049aec468bf9a7861c873f">error_count</a> = 0;
+<a name="l01275"></a>01275                 <a class="code" href="dwc__otg__hcd__intr_8c.html#8b774e79e18861e9ad3ab1d0de00d47c">halt_channel</a>(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
+<a name="l01276"></a>01276                 <span class="keywordflow">break</span>;
+<a name="l01277"></a>01277         <span class="keywordflow">case</span> UE_ISOCHRONOUS:
+<a name="l01278"></a>01278                 <span class="comment">/* Should never get called for isochronous transfers. */</span>
+<a name="l01279"></a>01279                 DWC_ASSERT(1, <span class="stringliteral">"NACK interrupt for ISOC transfer\n"</span>);
+<a name="l01280"></a>01280                 <span class="keywordflow">break</span>;
+<a name="l01281"></a>01281         }
+<a name="l01282"></a>01282 
+<a name="l01283"></a>01283       handle_nak_done:
+<a name="l01284"></a>01284         <a class="code" href="dwc__otg__cil_8h.html#e530fa4a6ed31f67cad65969355651ef">disable_hc_int</a>(hc_regs, nak);
+<a name="l01285"></a>01285 
+<a name="l01286"></a>01286         <span class="keywordflow">return</span> 1;
+<a name="l01287"></a>01287 }
+<a name="l01288"></a>01288 
+<a name="l01294"></a><a class="code" href="dwc__otg__hcd__intr_8c.html#243b0fb4191e46127a6823c0b5e970bb">01294</a> <span class="keyword">static</span> int32_t <a class="code" href="dwc__otg__hcd__intr_8c.html#243b0fb4191e46127a6823c0b5e970bb">handle_hc_ack_intr</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd,
+<a name="l01295"></a>01295                                   <a class="code" href="structdwc__hc.html">dwc_hc_t</a> * hc,
+<a name="l01296"></a>01296                                   <a class="code" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> * hc_regs,
+<a name="l01297"></a>01297                                   <a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> * qtd)
+<a name="l01298"></a>01298 {
+<a name="l01299"></a>01299         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#e4a050e176c1c4f556da2b276a8c2b37">DBG_HCD</a>, <span class="stringliteral">"--Host Channel %d Interrupt: "</span>
+<a name="l01300"></a>01300                     <span class="stringliteral">"ACK Received--\n"</span>, hc-&gt;<a class="code" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">hc_num</a>);
+<a name="l01301"></a>01301 
+<a name="l01302"></a>01302         <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#4365ef67d517a621a626ac5392545c6d">do_split</a>) {
+<a name="l01303"></a>01303                 <span class="comment">/*</span>
+<a name="l01304"></a>01304 <span class="comment">                 * Handle ACK on SSPLIT.</span>
+<a name="l01305"></a>01305 <span class="comment">                 * ACK should not occur in CSPLIT.</span>
+<a name="l01306"></a>01306 <span class="comment">                 */</span>
+<a name="l01307"></a>01307                 <span class="keywordflow">if</span> (!hc-&gt;<a class="code" href="structdwc__hc.html#c5088d431f5efc382121f201f5d571aa">ep_is_in</a> &amp;&amp; hc-&gt;<a class="code" href="structdwc__hc.html#513427c5e8c4603ba344d4e7f9191064">data_pid_start</a> != <a class="code" href="dwc__otg__cil_8h.html#8d329f92a5ff6f9a72fc755b6b1a4e17">DWC_OTG_HC_PID_SETUP</a>) {
+<a name="l01308"></a>01308                         qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#badffe465e850133c62c8f7e539f3fca">ssplit_out_xfer_count</a> = hc-&gt;<a class="code" href="structdwc__hc.html#ce32fe93214f1686896e924fbf61cac7">xfer_len</a>;
+<a name="l01309"></a>01309                 }
+<a name="l01310"></a>01310                 <span class="keywordflow">if</span> (!(hc-&gt;<a class="code" href="structdwc__hc.html#e6169fbc92e4d79686097742ad646f5c">ep_type</a> == <a class="code" href="dwc__otg__cil_8h.html#152a3a5e1433bd2197672f0b5105e7a4">DWC_OTG_EP_TYPE_ISOC</a> &amp;&amp; !hc-&gt;<a class="code" href="structdwc__hc.html#c5088d431f5efc382121f201f5d571aa">ep_is_in</a>)) {
+<a name="l01311"></a>01311                         <span class="comment">/* Don't need complete for isochronous out transfers. */</span>
+<a name="l01312"></a>01312                         qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#6355e968a4d36edce3e22c89ac7b5001">complete_split</a> = 1;
+<a name="l01313"></a>01313                 }
+<a name="l01314"></a>01314 
+<a name="l01315"></a>01315                 <span class="comment">/* ISOC OUT */</span>
+<a name="l01316"></a>01316                 <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#e6169fbc92e4d79686097742ad646f5c">ep_type</a> == <a class="code" href="dwc__otg__cil_8h.html#152a3a5e1433bd2197672f0b5105e7a4">DWC_OTG_EP_TYPE_ISOC</a> &amp;&amp; !hc-&gt;<a class="code" href="structdwc__hc.html#c5088d431f5efc382121f201f5d571aa">ep_is_in</a>) {
+<a name="l01317"></a>01317                         <span class="keywordflow">switch</span> (hc-&gt;<a class="code" href="structdwc__hc.html#3cde49a724756e16eb11a027360b2d4b">xact_pos</a>) {
+<a name="l01318"></a>01318                         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__regs_8h.html#b8a8f35d8fd73c955cc0403e87cea0c6">DWC_HCSPLIT_XACTPOS_ALL</a>:
+<a name="l01319"></a>01319                                 <span class="keywordflow">break</span>;
+<a name="l01320"></a>01320                         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__regs_8h.html#fc237b3dd77c97276aa4bd50947117e2">DWC_HCSPLIT_XACTPOS_END</a>:
+<a name="l01321"></a>01321                                 qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#ab224d64d72f2ef4f10e722ebcfa29a6">isoc_split_pos</a> = <a class="code" href="dwc__otg__regs_8h.html#b8a8f35d8fd73c955cc0403e87cea0c6">DWC_HCSPLIT_XACTPOS_ALL</a>;
+<a name="l01322"></a>01322                                 qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#839371940a7e34365e2272f3214b7e34">isoc_split_offset</a> = 0;
+<a name="l01323"></a>01323                                 <span class="keywordflow">break</span>;
+<a name="l01324"></a>01324                         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__regs_8h.html#c0b856e1a71e0373153d986a3cb5b135">DWC_HCSPLIT_XACTPOS_BEGIN</a>:
+<a name="l01325"></a>01325                         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__regs_8h.html#2297a1a33f502bc705e5c450c9864c6c">DWC_HCSPLIT_XACTPOS_MID</a>:
+<a name="l01326"></a>01326                                 <span class="comment">/*</span>
+<a name="l01327"></a>01327 <span class="comment">                                 * For BEGIN or MID, calculate the length for</span>
+<a name="l01328"></a>01328 <span class="comment">                                 * the next microframe to determine the correct</span>
+<a name="l01329"></a>01329 <span class="comment">                                 * SSPLIT token, either MID or END.</span>
+<a name="l01330"></a>01330 <span class="comment">                                 */</span>
+<a name="l01331"></a>01331                                 {
+<a name="l01332"></a>01332                                         <span class="keyword">struct </span><a class="code" href="structdwc__otg__hcd__iso__packet__desc.html">dwc_otg_hcd_iso_packet_desc</a>
+<a name="l01333"></a>01333                                             *frame_desc;
+<a name="l01334"></a>01334 
+<a name="l01335"></a>01335                                         frame_desc =
+<a name="l01336"></a>01336                                             &amp;qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#7e7767808e8eb9d71de0db00f57553f9">urb</a>-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#ed542f6a2d99dba2f6b71b0d8012ec8a">iso_descs</a>[qtd-&gt;
+<a name="l01337"></a>01337                                                                          isoc_frame_index];
+<a name="l01338"></a>01338                                         qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#839371940a7e34365e2272f3214b7e34">isoc_split_offset</a> += 188;
+<a name="l01339"></a>01339 
+<a name="l01340"></a>01340                                         <span class="keywordflow">if</span> ((frame_desc-&gt;<a class="code" href="structdwc__otg__hcd__iso__packet__desc.html#8392d21b820df0181f4e6dca91234543">length</a> -
+<a name="l01341"></a>01341                                              qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#839371940a7e34365e2272f3214b7e34">isoc_split_offset</a>) &lt;= 188) {
+<a name="l01342"></a>01342                                                 qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#ab224d64d72f2ef4f10e722ebcfa29a6">isoc_split_pos</a> =
+<a name="l01343"></a>01343                                                     <a class="code" href="dwc__otg__regs_8h.html#fc237b3dd77c97276aa4bd50947117e2">DWC_HCSPLIT_XACTPOS_END</a>;
+<a name="l01344"></a>01344                                         } <span class="keywordflow">else</span> {
+<a name="l01345"></a>01345                                                 qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#ab224d64d72f2ef4f10e722ebcfa29a6">isoc_split_pos</a> =
+<a name="l01346"></a>01346                                                     <a class="code" href="dwc__otg__regs_8h.html#2297a1a33f502bc705e5c450c9864c6c">DWC_HCSPLIT_XACTPOS_MID</a>;
+<a name="l01347"></a>01347                                         }
+<a name="l01348"></a>01348 
+<a name="l01349"></a>01349                                 }
+<a name="l01350"></a>01350                                 <span class="keywordflow">break</span>;
+<a name="l01351"></a>01351                         }
+<a name="l01352"></a>01352                 } <span class="keywordflow">else</span> {
+<a name="l01353"></a>01353                         <a class="code" href="dwc__otg__hcd__intr_8c.html#8b774e79e18861e9ad3ab1d0de00d47c">halt_channel</a>(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
+<a name="l01354"></a>01354                 }
+<a name="l01355"></a>01355         } <span class="keywordflow">else</span> {
+<a name="l01356"></a>01356                 qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#18eeb9c647049aec468bf9a7861c873f">error_count</a> = 0;
+<a name="l01357"></a>01357 
+<a name="l01358"></a>01358                 <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#2c115474978a808c797c8975d72e419d">ping_state</a>) {
+<a name="l01359"></a>01359                         hc-&gt;<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#2c115474978a808c797c8975d72e419d">ping_state</a> = 0;
+<a name="l01360"></a>01360                         <span class="comment">/*</span>
+<a name="l01361"></a>01361 <span class="comment">                         * Halt the channel so the transfer can be re-started</span>
+<a name="l01362"></a>01362 <span class="comment">                         * from the appropriate point. This only happens in</span>
+<a name="l01363"></a>01363 <span class="comment">                         * Slave mode. In DMA mode, the ping_state is cleared</span>
+<a name="l01364"></a>01364 <span class="comment">                         * when the transfer is started because the core</span>
+<a name="l01365"></a>01365 <span class="comment">                         * automatically executes the PING, then the transfer.</span>
+<a name="l01366"></a>01366 <span class="comment">                         */</span>
+<a name="l01367"></a>01367                         <a class="code" href="dwc__otg__hcd__intr_8c.html#8b774e79e18861e9ad3ab1d0de00d47c">halt_channel</a>(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
+<a name="l01368"></a>01368                 }
+<a name="l01369"></a>01369         }
+<a name="l01370"></a>01370 
+<a name="l01371"></a>01371         <span class="comment">/*</span>
+<a name="l01372"></a>01372 <span class="comment">         * If the ACK occurred when _not_ in the PING state, let the channel</span>
+<a name="l01373"></a>01373 <span class="comment">         * continue transferring data after clearing the error count.</span>
+<a name="l01374"></a>01374 <span class="comment">         */</span>
+<a name="l01375"></a>01375 
+<a name="l01376"></a>01376         <a class="code" href="dwc__otg__cil_8h.html#e530fa4a6ed31f67cad65969355651ef">disable_hc_int</a>(hc_regs, ack);
+<a name="l01377"></a>01377 
+<a name="l01378"></a>01378         <span class="keywordflow">return</span> 1;
+<a name="l01379"></a>01379 }
+<a name="l01380"></a>01380 
+<a name="l01388"></a><a class="code" href="dwc__otg__hcd__intr_8c.html#5093a2b94c1d5cd1988eb93d9def298f">01388</a> <span class="keyword">static</span> int32_t <a class="code" href="dwc__otg__hcd__intr_8c.html#5093a2b94c1d5cd1988eb93d9def298f">handle_hc_nyet_intr</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd,
+<a name="l01389"></a>01389                                    <a class="code" href="structdwc__hc.html">dwc_hc_t</a> * hc,
+<a name="l01390"></a>01390                                    <a class="code" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> * hc_regs,
+<a name="l01391"></a>01391                                    <a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> * qtd)
+<a name="l01392"></a>01392 {
+<a name="l01393"></a>01393         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#e4a050e176c1c4f556da2b276a8c2b37">DBG_HCD</a>, <span class="stringliteral">"--Host Channel %d Interrupt: "</span>
+<a name="l01394"></a>01394                     <span class="stringliteral">"NYET Received--\n"</span>, hc-&gt;<a class="code" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">hc_num</a>);
+<a name="l01395"></a>01395 
+<a name="l01396"></a>01396         <span class="comment">/*</span>
+<a name="l01397"></a>01397 <span class="comment">         * NYET on CSPLIT</span>
+<a name="l01398"></a>01398 <span class="comment">         * re-do the CSPLIT immediately on non-periodic</span>
+<a name="l01399"></a>01399 <span class="comment">         */</span>
+<a name="l01400"></a>01400         <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#4365ef67d517a621a626ac5392545c6d">do_split</a> &amp;&amp; hc-&gt;<a class="code" href="structdwc__hc.html#21e00df6fb9a555975879526118d599e">complete_split</a>) {
+<a name="l01401"></a>01401                 <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#c5088d431f5efc382121f201f5d571aa">ep_is_in</a> &amp;&amp; (hc-&gt;<a class="code" href="structdwc__hc.html#e6169fbc92e4d79686097742ad646f5c">ep_type</a> == <a class="code" href="dwc__otg__cil_8h.html#152a3a5e1433bd2197672f0b5105e7a4">DWC_OTG_EP_TYPE_ISOC</a>) &amp;&amp; hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a>) {        
+<a name="l01402"></a>01402                         qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#6355e968a4d36edce3e22c89ac7b5001">complete_split</a> = 0;
+<a name="l01403"></a>01403                         qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#839371940a7e34365e2272f3214b7e34">isoc_split_offset</a> = 0;
+<a name="l01404"></a>01404                         <span class="keywordflow">if</span> (++qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#c67d5f885976d0698f20d113d32b4b30">isoc_frame_index</a> == qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#7e7767808e8eb9d71de0db00f57553f9">urb</a>-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#570583697e8c1e4398969630bc2562f8">packet_count</a>) {
+<a name="l01405"></a>01405                                 hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#ffefbd33a59a14b8b46406f5aaeaa2f4">fops</a>-&gt;<a class="code" href="structdwc__otg__hcd__function__ops.html#09a989481103de7468cd46ef61ace0ce">complete</a>(hcd, qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#7e7767808e8eb9d71de0db00f57553f9">urb</a>-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#5ba0e393ef9768275db85c00e68be477">priv</a>, qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#7e7767808e8eb9d71de0db00f57553f9">urb</a>, 0);
+<a name="l01406"></a>01406                                 <a class="code" href="dwc__otg__hcd__intr_8c.html#4f6bf01b14a03eeed81d27bffa5e99fc">release_channel</a>(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);    
+<a name="l01407"></a>01407                         }
+<a name="l01408"></a>01408                         <span class="keywordflow">else</span>
+<a name="l01409"></a>01409                                 <a class="code" href="dwc__otg__hcd__intr_8c.html#4f6bf01b14a03eeed81d27bffa5e99fc">release_channel</a>(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);  
+<a name="l01410"></a>01410                         <span class="keywordflow">goto</span> handle_nyet_done;
+<a name="l01411"></a>01411                 }
+<a name="l01412"></a>01412                 
+<a name="l01413"></a>01413                 <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#e6169fbc92e4d79686097742ad646f5c">ep_type</a> == <a class="code" href="dwc__otg__cil_8h.html#1401d1264f88530232cf51ab31cc5347">DWC_OTG_EP_TYPE_INTR</a> ||
+<a name="l01414"></a>01414                     hc-&gt;<a class="code" href="structdwc__hc.html#e6169fbc92e4d79686097742ad646f5c">ep_type</a> == <a class="code" href="dwc__otg__cil_8h.html#152a3a5e1433bd2197672f0b5105e7a4">DWC_OTG_EP_TYPE_ISOC</a>) {
+<a name="l01415"></a>01415                         <span class="keywordtype">int</span> frnum = <a class="code" href="dwc__otg__hcd_8c.html#f06514bd6f8c219cc72d1f467a82c056">dwc_otg_hcd_get_frame_number</a>(hcd);
+<a name="l01416"></a>01416 
+<a name="l01417"></a>01417                         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__hcd_8h.html#d6248403619d099d04320cb1b7c7ee99">dwc_full_frame_num</a>(frnum) !=
+<a name="l01418"></a>01418                             <a class="code" href="dwc__otg__hcd_8h.html#d6248403619d099d04320cb1b7c7ee99">dwc_full_frame_num</a>(hc-&gt;<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#977a8032f08e45a9e9bdcd558a6965d3">sched_frame</a>)) {
+<a name="l01419"></a>01419                                 <span class="comment">/*</span>
+<a name="l01420"></a>01420 <span class="comment">                                 * No longer in the same full speed frame.</span>
+<a name="l01421"></a>01421 <span class="comment">                                 * Treat this as a transaction error.</span>
+<a name="l01422"></a>01422 <span class="comment">                                 */</span>
+<a name="l01423"></a>01423 <span class="preprocessor">#if 0</span>
+<a name="l01424"></a>01424 <span class="preprocessor"></span>
+<a name="l01430"></a>01430                                 qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#18eeb9c647049aec468bf9a7861c873f">error_count</a>++;
+<a name="l01431"></a>01431 <span class="preprocessor">#endif</span>
+<a name="l01432"></a>01432 <span class="preprocessor"></span>                                qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#6355e968a4d36edce3e22c89ac7b5001">complete_split</a> = 0;
+<a name="l01433"></a>01433                                 <a class="code" href="dwc__otg__hcd__intr_8c.html#8b774e79e18861e9ad3ab1d0de00d47c">halt_channel</a>(hcd, hc, qtd,
+<a name="l01434"></a>01434                                              DWC_OTG_HC_XFER_XACT_ERR);
+<a name="l01436"></a>01436                                 <span class="keywordflow">goto</span> handle_nyet_done;
+<a name="l01437"></a>01437                         }
+<a name="l01438"></a>01438                 }
+<a name="l01439"></a>01439 
+<a name="l01440"></a>01440                 <a class="code" href="dwc__otg__hcd__intr_8c.html#8b774e79e18861e9ad3ab1d0de00d47c">halt_channel</a>(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);
+<a name="l01441"></a>01441                 <span class="keywordflow">goto</span> handle_nyet_done;
+<a name="l01442"></a>01442         }
+<a name="l01443"></a>01443 
+<a name="l01444"></a>01444         hc-&gt;<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#2c115474978a808c797c8975d72e419d">ping_state</a> = 1;
+<a name="l01445"></a>01445         qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#18eeb9c647049aec468bf9a7861c873f">error_count</a> = 0;
+<a name="l01446"></a>01446 
+<a name="l01447"></a>01447         <a class="code" href="dwc__otg__hcd__intr_8c.html#0640c3606be7a8700ea4813e590ebf43">update_urb_state_xfer_intr</a>(hc, hc_regs, qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#7e7767808e8eb9d71de0db00f57553f9">urb</a>, qtd,
+<a name="l01448"></a>01448                                    DWC_OTG_HC_XFER_NYET);
+<a name="l01449"></a>01449         <a class="code" href="dwc__otg__hcd_8h.html#8bce109004d7869bfdd9aa1075c6bd2c">dwc_otg_hcd_save_data_toggle</a>(hc, hc_regs, qtd);
+<a name="l01450"></a>01450 
+<a name="l01451"></a>01451         <span class="comment">/*</span>
+<a name="l01452"></a>01452 <span class="comment">         * Halt the channel and re-start the transfer so the PING</span>
+<a name="l01453"></a>01453 <span class="comment">         * protocol will start.</span>
+<a name="l01454"></a>01454 <span class="comment">         */</span>
+<a name="l01455"></a>01455         <a class="code" href="dwc__otg__hcd__intr_8c.html#8b774e79e18861e9ad3ab1d0de00d47c">halt_channel</a>(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);
+<a name="l01456"></a>01456 
+<a name="l01457"></a>01457       handle_nyet_done:
+<a name="l01458"></a>01458         <a class="code" href="dwc__otg__cil_8h.html#e530fa4a6ed31f67cad65969355651ef">disable_hc_int</a>(hc_regs, nyet);
+<a name="l01459"></a>01459         <span class="keywordflow">return</span> 1;
+<a name="l01460"></a>01460 }
+<a name="l01461"></a>01461 
+<a name="l01466"></a><a class="code" href="dwc__otg__hcd__intr_8c.html#ab5348f52aac4081a9c35d529c1fcd79">01466</a> <span class="keyword">static</span> int32_t <a class="code" href="dwc__otg__hcd__intr_8c.html#ab5348f52aac4081a9c35d529c1fcd79">handle_hc_babble_intr</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd,
+<a name="l01467"></a>01467                                      <a class="code" href="structdwc__hc.html">dwc_hc_t</a> * hc,
+<a name="l01468"></a>01468                                      <a class="code" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> * hc_regs,
+<a name="l01469"></a>01469                                      <a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> * qtd)
+<a name="l01470"></a>01470 {
+<a name="l01471"></a>01471         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#e4a050e176c1c4f556da2b276a8c2b37">DBG_HCD</a>, <span class="stringliteral">"--Host Channel %d Interrupt: "</span>
+<a name="l01472"></a>01472                     <span class="stringliteral">"Babble Error--\n"</span>, hc-&gt;<a class="code" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">hc_num</a>);
+<a name="l01473"></a>01473         
+<a name="l01474"></a>01474         <span class="keywordflow">if</span> (hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a>) {
+<a name="l01475"></a>01475                 <a class="code" href="dwc__otg__hcd_8h.html#ca94cde3142ff1121bb0ff9bd44fa762">dwc_otg_hcd_complete_xfer_ddma</a>(hcd, hc, hc_regs, DWC_OTG_HC_XFER_BABBLE_ERR);
+<a name="l01476"></a>01476                 <span class="keywordflow">goto</span> handle_babble_done;
+<a name="l01477"></a>01477         }
+<a name="l01478"></a>01478 
+<a name="l01479"></a>01479         <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#e6169fbc92e4d79686097742ad646f5c">ep_type</a> != <a class="code" href="dwc__otg__cil_8h.html#152a3a5e1433bd2197672f0b5105e7a4">DWC_OTG_EP_TYPE_ISOC</a>) {
+<a name="l01480"></a>01480                 hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#ffefbd33a59a14b8b46406f5aaeaa2f4">fops</a>-&gt;<a class="code" href="structdwc__otg__hcd__function__ops.html#09a989481103de7468cd46ef61ace0ce">complete</a>(hcd, qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#7e7767808e8eb9d71de0db00f57553f9">urb</a>-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#5ba0e393ef9768275db85c00e68be477">priv</a>,
+<a name="l01481"></a>01481                                     qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#7e7767808e8eb9d71de0db00f57553f9">urb</a>, -DWC_E_OVERFLOW);
+<a name="l01482"></a>01482                 <a class="code" href="dwc__otg__hcd__intr_8c.html#8b774e79e18861e9ad3ab1d0de00d47c">halt_channel</a>(hcd, hc, qtd, DWC_OTG_HC_XFER_BABBLE_ERR);
+<a name="l01483"></a>01483         } <span class="keywordflow">else</span> {
+<a name="l01484"></a>01484                 dwc_otg_halt_status_e halt_status;
+<a name="l01485"></a>01485                 halt_status = <a class="code" href="dwc__otg__hcd__intr_8c.html#e93d54bdf873c5a31882660c2984458e">update_isoc_urb_state</a>(hcd, hc, hc_regs, qtd,
+<a name="l01486"></a>01486                                                     DWC_OTG_HC_XFER_BABBLE_ERR);
+<a name="l01487"></a>01487                 <a class="code" href="dwc__otg__hcd__intr_8c.html#8b774e79e18861e9ad3ab1d0de00d47c">halt_channel</a>(hcd, hc, qtd, halt_status);
+<a name="l01488"></a>01488         }
+<a name="l01489"></a>01489         
+<a name="l01490"></a>01490 handle_babble_done:
+<a name="l01491"></a>01491         <a class="code" href="dwc__otg__cil_8h.html#e530fa4a6ed31f67cad65969355651ef">disable_hc_int</a>(hc_regs, bblerr);
+<a name="l01492"></a>01492         <span class="keywordflow">return</span> 1;
+<a name="l01493"></a>01493 }
+<a name="l01494"></a>01494 
+<a name="l01499"></a><a class="code" href="dwc__otg__hcd__intr_8c.html#1edf7eebc0475898518e18dc12c1b4b9">01499</a> <span class="keyword">static</span> int32_t <a class="code" href="dwc__otg__hcd__intr_8c.html#1edf7eebc0475898518e18dc12c1b4b9">handle_hc_ahberr_intr</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd,
+<a name="l01500"></a>01500                                      <a class="code" href="structdwc__hc.html">dwc_hc_t</a> * hc,
+<a name="l01501"></a>01501                                      <a class="code" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> * hc_regs,
+<a name="l01502"></a>01502                                      <a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> * qtd)
+<a name="l01503"></a>01503 {
+<a name="l01504"></a>01504         <a class="code" href="unionhcchar__data.html">hcchar_data_t</a> hcchar;
+<a name="l01505"></a>01505         <a class="code" href="unionhcsplt__data.html">hcsplt_data_t</a> hcsplt;
+<a name="l01506"></a>01506         <a class="code" href="unionhctsiz__data.html">hctsiz_data_t</a> hctsiz;
+<a name="l01507"></a>01507         uint32_t hcdma;
+<a name="l01508"></a>01508         <span class="keywordtype">char</span> *pipetype, *speed;
+<a name="l01509"></a>01509 
+<a name="l01510"></a>01510         <a class="code" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *urb = qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#7e7767808e8eb9d71de0db00f57553f9">urb</a>;
+<a name="l01511"></a>01511 
+<a name="l01512"></a>01512         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#e4a050e176c1c4f556da2b276a8c2b37">DBG_HCD</a>, <span class="stringliteral">"--Host Channel %d Interrupt: "</span>
+<a name="l01513"></a>01513                     <span class="stringliteral">"AHB Error--\n"</span>, hc-&gt;<a class="code" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">hc_num</a>);
+<a name="l01514"></a>01514 
+<a name="l01515"></a>01515         hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">hcchar</a>);
+<a name="l01516"></a>01516         hcsplt.<a class="code" href="unionhcsplt__data.html#0cd235b445ff681b846f5dccf24fd644">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#149053001a9ee21b692afde531a814de">hcsplt</a>);
+<a name="l01517"></a>01517         hctsiz.<a class="code" href="unionhctsiz__data.html#fb41950555c60c6015294bdefe9cd39d">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#c6173f823ba754d9f9549422b6380ca2">hctsiz</a>);
+<a name="l01518"></a>01518         hcdma = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#ab2148d4b5f1bf3a2ad438e497a8b4a3">hcdma</a>);
+<a name="l01519"></a>01519 
+<a name="l01520"></a>01520         DWC_ERROR(<span class="stringliteral">"AHB ERROR, Channel %d\n"</span>, hc-&gt;<a class="code" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">hc_num</a>);
+<a name="l01521"></a>01521         DWC_ERROR(<span class="stringliteral">"  hcchar 0x%08x, hcsplt 0x%08x\n"</span>, hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a>, hcsplt.<a class="code" href="unionhcsplt__data.html#0cd235b445ff681b846f5dccf24fd644">d32</a>);
+<a name="l01522"></a>01522         DWC_ERROR(<span class="stringliteral">"  hctsiz 0x%08x, hcdma 0x%08x\n"</span>, hctsiz.<a class="code" href="unionhctsiz__data.html#fb41950555c60c6015294bdefe9cd39d">d32</a>, hcdma);
+<a name="l01523"></a>01523         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#e4a050e176c1c4f556da2b276a8c2b37">DBG_HCD</a>, <span class="stringliteral">"DWC OTG HCD URB Enqueue\n"</span>);
+<a name="l01524"></a>01524         DWC_ERROR(<span class="stringliteral">"  Device address: %d\n"</span>,
+<a name="l01525"></a>01525                   <a class="code" href="dwc__otg__hcd_8h.html#0de365358ba4472d56c1ac8074ba926b">dwc_otg_hcd_get_dev_addr</a>(&amp;urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#34ee3ac5931687b41dd726f00c558369">pipe_info</a>));
+<a name="l01526"></a>01526         DWC_ERROR(<span class="stringliteral">"  Endpoint: %d, %s\n"</span>,
+<a name="l01527"></a>01527                   <a class="code" href="dwc__otg__hcd_8h.html#367b79057f321cfa65023f4026d6c2c9">dwc_otg_hcd_get_ep_num</a>(&amp;urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#34ee3ac5931687b41dd726f00c558369">pipe_info</a>),
+<a name="l01528"></a>01528                   (<a class="code" href="dwc__otg__hcd_8h.html#68de5629a8b45d9bec58f680fa4c820c">dwc_otg_hcd_is_pipe_in</a>(&amp;urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#34ee3ac5931687b41dd726f00c558369">pipe_info</a>) ? <span class="stringliteral">"IN"</span> : <span class="stringliteral">"OUT"</span>));
+<a name="l01529"></a>01529         
+<a name="l01530"></a>01530 
+<a name="l01531"></a>01531         <span class="keywordflow">switch</span> (<a class="code" href="dwc__otg__hcd_8h.html#b97cea598797e69d011ffef89989a739">dwc_otg_hcd_get_pipe_type</a>(&amp;urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#34ee3ac5931687b41dd726f00c558369">pipe_info</a>)) {
+<a name="l01532"></a>01532 <span class="keywordflow">case</span> UE_CONTROL:
+<a name="l01533"></a>01533                 pipetype = <span class="stringliteral">"CONTROL"</span>; 
+<a name="l01534"></a>01534                 <span class="keywordflow">break</span>; 
+<a name="l01535"></a>01535         <span class="keywordflow">case</span> UE_BULK:
+<a name="l01536"></a>01536                 pipetype = <span class="stringliteral">"BULK"</span>; 
+<a name="l01537"></a>01537                 <span class="keywordflow">break</span>; 
+<a name="l01538"></a>01538         <span class="keywordflow">case</span> UE_INTERRUPT:
+<a name="l01539"></a>01539                 pipetype = <span class="stringliteral">"INTERRUPT"</span>; 
+<a name="l01540"></a>01540                 <span class="keywordflow">break</span>; 
+<a name="l01541"></a>01541         <span class="keywordflow">case</span> UE_ISOCHRONOUS:
+<a name="l01542"></a>01542                 pipetype = <span class="stringliteral">"ISOCHRONOUS"</span>; 
+<a name="l01543"></a>01543                 <span class="keywordflow">break</span>; 
+<a name="l01544"></a>01544         <span class="keywordflow">default</span>:
+<a name="l01545"></a>01545                 pipetype = <span class="stringliteral">"UNKNOWN"</span>; 
+<a name="l01546"></a>01546                 <span class="keywordflow">break</span>;
+<a name="l01547"></a>01547         }
+<a name="l01548"></a>01548         
+<a name="l01549"></a>01549         DWC_ERROR(<span class="stringliteral">"  Endpoint type: %s\n"</span>, pipetype);
+<a name="l01550"></a>01550 
+<a name="l01551"></a>01551         <span class="keywordflow">switch</span> (hc-&gt;<a class="code" href="structdwc__hc.html#570b78178975193edb921af1ef36d37b">speed</a>) {
+<a name="l01552"></a>01552         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__cil_8h.html#b9dc03c6bc3c1113a935a73cf7021fbe">DWC_OTG_EP_SPEED_HIGH</a>:
+<a name="l01553"></a>01553                 speed = <span class="stringliteral">"HIGH"</span>; 
+<a name="l01554"></a>01554                 <span class="keywordflow">break</span>; 
+<a name="l01555"></a>01555         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__cil_8h.html#2ec9a7665a34074eedf1f40681d124ef">DWC_OTG_EP_SPEED_FULL</a>:
+<a name="l01556"></a>01556                 speed = <span class="stringliteral">"FULL"</span>; 
+<a name="l01557"></a>01557                 <span class="keywordflow">break</span>; 
+<a name="l01558"></a>01558         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__cil_8h.html#1a25260b2e1a06850c26f7b7e5128f31">DWC_OTG_EP_SPEED_LOW</a>:
+<a name="l01559"></a>01559                 speed = <span class="stringliteral">"LOW"</span>; 
+<a name="l01560"></a>01560                 <span class="keywordflow">break</span>; 
+<a name="l01561"></a>01561         <span class="keywordflow">default</span>:
+<a name="l01562"></a>01562                 speed = <span class="stringliteral">"UNKNOWN"</span>; 
+<a name="l01563"></a>01563                 <span class="keywordflow">break</span>;
+<a name="l01564"></a>01564         };      
+<a name="l01565"></a>01565 
+<a name="l01566"></a>01566         DWC_ERROR(<span class="stringliteral">"  Speed: %s\n"</span>, speed);
+<a name="l01567"></a>01567         
+<a name="l01568"></a>01568         DWC_ERROR(<span class="stringliteral">"  Max packet size: %d\n"</span>,
+<a name="l01569"></a>01569                   <a class="code" href="dwc__otg__hcd_8h.html#e47df3e0ac1c8ccc916e0c0895568c88">dwc_otg_hcd_get_mps</a>(&amp;urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#34ee3ac5931687b41dd726f00c558369">pipe_info</a>));
+<a name="l01570"></a>01570         DWC_ERROR(<span class="stringliteral">"  Data buffer length: %d\n"</span>, urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#dca57de4fdecd894241ce24167206a45">length</a>);
+<a name="l01571"></a>01571         DWC_ERROR(<span class="stringliteral">"  Transfer buffer: %p, Transfer DMA: %p\n"</span>,
+<a name="l01572"></a>01572                   urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#99ae35ffcd6147ddb93b361ab3bcfe95">buf</a>, (<span class="keywordtype">void</span> *)urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#4e177a55239e95ae2f6c8b6b913f67fc">dma</a>);
+<a name="l01573"></a>01573         DWC_ERROR(<span class="stringliteral">"  Setup buffer: %p, Setup DMA: %p\n"</span>,
+<a name="l01574"></a>01574                   urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#254afd954f3e24bb92841384183a317c">setup_packet</a>, (<span class="keywordtype">void</span> *)urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#497f61f9b3f6f77f6b844e31c047264d">setup_dma</a>);
+<a name="l01575"></a>01575         DWC_ERROR(<span class="stringliteral">"  Interval: %d\n"</span>, urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#49c5353377e2fb173f1b34ae7be7e257">interval</a>);
+<a name="l01576"></a>01576 
+<a name="l01577"></a>01577         <span class="comment">/* Core haltes the channel for Descriptor DMA mode */</span>
+<a name="l01578"></a>01578         <span class="keywordflow">if</span> (hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a>) {
+<a name="l01579"></a>01579                 <a class="code" href="dwc__otg__hcd_8h.html#ca94cde3142ff1121bb0ff9bd44fa762">dwc_otg_hcd_complete_xfer_ddma</a>(hcd, hc, hc_regs, DWC_OTG_HC_XFER_AHB_ERR);
+<a name="l01580"></a>01580                 <span class="keywordflow">goto</span> handle_ahberr_done;
+<a name="l01581"></a>01581         }
+<a name="l01582"></a>01582 
+<a name="l01583"></a>01583         hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#ffefbd33a59a14b8b46406f5aaeaa2f4">fops</a>-&gt;<a class="code" href="structdwc__otg__hcd__function__ops.html#09a989481103de7468cd46ef61ace0ce">complete</a>(hcd, urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#5ba0e393ef9768275db85c00e68be477">priv</a>, urb, -DWC_E_IO);
+<a name="l01584"></a>01584 
+<a name="l01585"></a>01585         <span class="comment">/*</span>
+<a name="l01586"></a>01586 <span class="comment">         * Force a channel halt. Don't call halt_channel because that won't</span>
+<a name="l01587"></a>01587 <span class="comment">         * write to the HCCHARn register in DMA mode to force the halt.</span>
+<a name="l01588"></a>01588 <span class="comment">         */</span>
+<a name="l01589"></a>01589         <a class="code" href="dwc__otg__cil_8c.html#de044bf6b96c1bac92259a447ae85c0f">dwc_otg_hc_halt</a>(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>, hc, DWC_OTG_HC_XFER_AHB_ERR);
+<a name="l01590"></a>01590 handle_ahberr_done:
+<a name="l01591"></a>01591         <a class="code" href="dwc__otg__cil_8h.html#e530fa4a6ed31f67cad65969355651ef">disable_hc_int</a>(hc_regs, ahberr);
+<a name="l01592"></a>01592         <span class="keywordflow">return</span> 1;
+<a name="l01593"></a>01593 }
+<a name="l01594"></a>01594 
+<a name="l01599"></a><a class="code" href="dwc__otg__hcd__intr_8c.html#464af1671bd416d5db48a51fc93366ee">01599</a> <span class="keyword">static</span> int32_t <a class="code" href="dwc__otg__hcd__intr_8c.html#464af1671bd416d5db48a51fc93366ee">handle_hc_xacterr_intr</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd,
+<a name="l01600"></a>01600                                       <a class="code" href="structdwc__hc.html">dwc_hc_t</a> * hc,
+<a name="l01601"></a>01601                                       <a class="code" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> * hc_regs,
+<a name="l01602"></a>01602                                       <a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> * qtd)
+<a name="l01603"></a>01603 {
+<a name="l01604"></a>01604         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#e4a050e176c1c4f556da2b276a8c2b37">DBG_HCD</a>, <span class="stringliteral">"--Host Channel %d Interrupt: "</span>
+<a name="l01605"></a>01605                     <span class="stringliteral">"Transaction Error--\n"</span>, hc-&gt;<a class="code" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">hc_num</a>);
+<a name="l01606"></a>01606 
+<a name="l01607"></a>01607         <span class="keywordflow">if</span> (hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a>) {
+<a name="l01608"></a>01608                 <a class="code" href="dwc__otg__hcd_8h.html#ca94cde3142ff1121bb0ff9bd44fa762">dwc_otg_hcd_complete_xfer_ddma</a>(hcd, hc, hc_regs, DWC_OTG_HC_XFER_XACT_ERR);
+<a name="l01609"></a>01609                 <span class="keywordflow">goto</span> handle_xacterr_done;
+<a name="l01610"></a>01610         }
+<a name="l01611"></a>01611 
+<a name="l01612"></a>01612         <span class="keywordflow">switch</span> (<a class="code" href="dwc__otg__hcd_8h.html#b97cea598797e69d011ffef89989a739">dwc_otg_hcd_get_pipe_type</a>(&amp;qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#7e7767808e8eb9d71de0db00f57553f9">urb</a>-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#34ee3ac5931687b41dd726f00c558369">pipe_info</a>)) {
+<a name="l01613"></a>01613         <span class="keywordflow">case</span> UE_CONTROL:
+<a name="l01614"></a>01614         <span class="keywordflow">case</span> UE_BULK:
+<a name="l01615"></a>01615                 qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#18eeb9c647049aec468bf9a7861c873f">error_count</a>++;
+<a name="l01616"></a>01616                 <span class="keywordflow">if</span> (!hc-&gt;<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#2c115474978a808c797c8975d72e419d">ping_state</a>) {
+<a name="l01617"></a>01617 
+<a name="l01618"></a>01618                         <a class="code" href="dwc__otg__hcd__intr_8c.html#0640c3606be7a8700ea4813e590ebf43">update_urb_state_xfer_intr</a>(hc, hc_regs,
+<a name="l01619"></a>01619                                                    qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#7e7767808e8eb9d71de0db00f57553f9">urb</a>, qtd,
+<a name="l01620"></a>01620                                                    DWC_OTG_HC_XFER_XACT_ERR);
+<a name="l01621"></a>01621                         <a class="code" href="dwc__otg__hcd_8h.html#8bce109004d7869bfdd9aa1075c6bd2c">dwc_otg_hcd_save_data_toggle</a>(hc, hc_regs, qtd);
+<a name="l01622"></a>01622                         <span class="keywordflow">if</span> (!hc-&gt;<a class="code" href="structdwc__hc.html#c5088d431f5efc382121f201f5d571aa">ep_is_in</a> &amp;&amp; hc-&gt;<a class="code" href="structdwc__hc.html#570b78178975193edb921af1ef36d37b">speed</a> == <a class="code" href="dwc__otg__cil_8h.html#b9dc03c6bc3c1113a935a73cf7021fbe">DWC_OTG_EP_SPEED_HIGH</a>) {
+<a name="l01623"></a>01623                                 hc-&gt;<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#2c115474978a808c797c8975d72e419d">ping_state</a> = 1;
+<a name="l01624"></a>01624                         }
+<a name="l01625"></a>01625                 }
+<a name="l01626"></a>01626 
+<a name="l01627"></a>01627                 <span class="comment">/*</span>
+<a name="l01628"></a>01628 <span class="comment">                 * Halt the channel so the transfer can be re-started from</span>
+<a name="l01629"></a>01629 <span class="comment">                 * the appropriate point or the PING protocol will start.</span>
+<a name="l01630"></a>01630 <span class="comment">                 */</span>
+<a name="l01631"></a>01631                 <a class="code" href="dwc__otg__hcd__intr_8c.html#8b774e79e18861e9ad3ab1d0de00d47c">halt_channel</a>(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
+<a name="l01632"></a>01632                 <span class="keywordflow">break</span>;
+<a name="l01633"></a>01633         <span class="keywordflow">case</span> UE_INTERRUPT:
+<a name="l01634"></a>01634                 qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#18eeb9c647049aec468bf9a7861c873f">error_count</a>++;
+<a name="l01635"></a>01635                 <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#4365ef67d517a621a626ac5392545c6d">do_split</a> &amp;&amp; hc-&gt;<a class="code" href="structdwc__hc.html#21e00df6fb9a555975879526118d599e">complete_split</a>) {
+<a name="l01636"></a>01636                         qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#6355e968a4d36edce3e22c89ac7b5001">complete_split</a> = 0;
+<a name="l01637"></a>01637                 }
+<a name="l01638"></a>01638                 <a class="code" href="dwc__otg__hcd__intr_8c.html#8b774e79e18861e9ad3ab1d0de00d47c">halt_channel</a>(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
+<a name="l01639"></a>01639                 <span class="keywordflow">break</span>;
+<a name="l01640"></a>01640         <span class="keywordflow">case</span> UE_ISOCHRONOUS:
+<a name="l01641"></a>01641                 {
+<a name="l01642"></a>01642                         dwc_otg_halt_status_e halt_status;
+<a name="l01643"></a>01643                         halt_status =
+<a name="l01644"></a>01644                             <a class="code" href="dwc__otg__hcd__intr_8c.html#e93d54bdf873c5a31882660c2984458e">update_isoc_urb_state</a>(hcd, hc, hc_regs, qtd,
+<a name="l01645"></a>01645                                                   DWC_OTG_HC_XFER_XACT_ERR);
+<a name="l01646"></a>01646 
+<a name="l01647"></a>01647                         <a class="code" href="dwc__otg__hcd__intr_8c.html#8b774e79e18861e9ad3ab1d0de00d47c">halt_channel</a>(hcd, hc, qtd, halt_status);
+<a name="l01648"></a>01648                 }
+<a name="l01649"></a>01649                 <span class="keywordflow">break</span>;
+<a name="l01650"></a>01650         }
+<a name="l01651"></a>01651 handle_xacterr_done:
+<a name="l01652"></a>01652         <a class="code" href="dwc__otg__cil_8h.html#e530fa4a6ed31f67cad65969355651ef">disable_hc_int</a>(hc_regs, xacterr);
+<a name="l01653"></a>01653 
+<a name="l01654"></a>01654         <span class="keywordflow">return</span> 1;
+<a name="l01655"></a>01655 }
+<a name="l01656"></a>01656 
+<a name="l01661"></a><a class="code" href="dwc__otg__hcd__intr_8c.html#a30d61b2809dccf609bcf83cc61c9d63">01661</a> <span class="keyword">static</span> int32_t <a class="code" href="dwc__otg__hcd__intr_8c.html#a30d61b2809dccf609bcf83cc61c9d63">handle_hc_frmovrun_intr</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd,
+<a name="l01662"></a>01662                                        <a class="code" href="structdwc__hc.html">dwc_hc_t</a> * hc,
+<a name="l01663"></a>01663                                        <a class="code" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> * hc_regs,
+<a name="l01664"></a>01664                                        <a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> * qtd)
+<a name="l01665"></a>01665 {
+<a name="l01666"></a>01666         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#e4a050e176c1c4f556da2b276a8c2b37">DBG_HCD</a>, <span class="stringliteral">"--Host Channel %d Interrupt: "</span>
+<a name="l01667"></a>01667                     <span class="stringliteral">"Frame Overrun--\n"</span>, hc-&gt;<a class="code" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">hc_num</a>);
+<a name="l01668"></a>01668 
+<a name="l01669"></a>01669         <span class="keywordflow">switch</span> (<a class="code" href="dwc__otg__hcd_8h.html#b97cea598797e69d011ffef89989a739">dwc_otg_hcd_get_pipe_type</a>(&amp;qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#7e7767808e8eb9d71de0db00f57553f9">urb</a>-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#34ee3ac5931687b41dd726f00c558369">pipe_info</a>)) {
+<a name="l01670"></a>01670         <span class="keywordflow">case</span> UE_CONTROL:
+<a name="l01671"></a>01671         <span class="keywordflow">case</span> UE_BULK:
+<a name="l01672"></a>01672                 <span class="keywordflow">break</span>;
+<a name="l01673"></a>01673         <span class="keywordflow">case</span> UE_INTERRUPT:
+<a name="l01674"></a>01674                 <a class="code" href="dwc__otg__hcd__intr_8c.html#8b774e79e18861e9ad3ab1d0de00d47c">halt_channel</a>(hcd, hc, qtd, DWC_OTG_HC_XFER_FRAME_OVERRUN);
+<a name="l01675"></a>01675                 <span class="keywordflow">break</span>;
+<a name="l01676"></a>01676         <span class="keywordflow">case</span> UE_ISOCHRONOUS:
+<a name="l01677"></a>01677                 {
+<a name="l01678"></a>01678                         dwc_otg_halt_status_e halt_status;
+<a name="l01679"></a>01679                         halt_status =
+<a name="l01680"></a>01680                             <a class="code" href="dwc__otg__hcd__intr_8c.html#e93d54bdf873c5a31882660c2984458e">update_isoc_urb_state</a>(hcd, hc, hc_regs, qtd,
+<a name="l01681"></a>01681                                                   DWC_OTG_HC_XFER_FRAME_OVERRUN);
+<a name="l01682"></a>01682 
+<a name="l01683"></a>01683                         <a class="code" href="dwc__otg__hcd__intr_8c.html#8b774e79e18861e9ad3ab1d0de00d47c">halt_channel</a>(hcd, hc, qtd, halt_status);
+<a name="l01684"></a>01684                 }
+<a name="l01685"></a>01685                 <span class="keywordflow">break</span>;
+<a name="l01686"></a>01686         }
+<a name="l01687"></a>01687 
+<a name="l01688"></a>01688         <a class="code" href="dwc__otg__cil_8h.html#e530fa4a6ed31f67cad65969355651ef">disable_hc_int</a>(hc_regs, frmovrun);
+<a name="l01689"></a>01689 
+<a name="l01690"></a>01690         <span class="keywordflow">return</span> 1;
+<a name="l01691"></a>01691 }
+<a name="l01692"></a>01692 
+<a name="l01697"></a><a class="code" href="dwc__otg__hcd__intr_8c.html#f73e70f0e622267b6281e0cd6c1d89cf">01697</a> <span class="keyword">static</span> int32_t <a class="code" href="dwc__otg__hcd__intr_8c.html#f73e70f0e622267b6281e0cd6c1d89cf">handle_hc_datatglerr_intr</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd,
+<a name="l01698"></a>01698                                          <a class="code" href="structdwc__hc.html">dwc_hc_t</a> * hc,
+<a name="l01699"></a>01699                                          <a class="code" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> * hc_regs,
+<a name="l01700"></a>01700                                          <a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> * qtd)
+<a name="l01701"></a>01701 {
+<a name="l01702"></a>01702         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#e4a050e176c1c4f556da2b276a8c2b37">DBG_HCD</a>, <span class="stringliteral">"--Host Channel %d Interrupt: "</span>
+<a name="l01703"></a>01703                     <span class="stringliteral">"Data Toggle Error--\n"</span>, hc-&gt;<a class="code" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">hc_num</a>);
+<a name="l01704"></a>01704 
+<a name="l01705"></a>01705         <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#c5088d431f5efc382121f201f5d571aa">ep_is_in</a>) {
+<a name="l01706"></a>01706                 qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#18eeb9c647049aec468bf9a7861c873f">error_count</a> = 0;
+<a name="l01707"></a>01707         } <span class="keywordflow">else</span> {
+<a name="l01708"></a>01708                 DWC_ERROR(<span class="stringliteral">"Data Toggle Error on OUT transfer,"</span>
+<a name="l01709"></a>01709                           <span class="stringliteral">"channel %d\n"</span>, hc-&gt;<a class="code" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">hc_num</a>);
+<a name="l01710"></a>01710         }
+<a name="l01711"></a>01711 
+<a name="l01712"></a>01712         <a class="code" href="dwc__otg__cil_8h.html#e530fa4a6ed31f67cad65969355651ef">disable_hc_int</a>(hc_regs, datatglerr);
+<a name="l01713"></a>01713 
+<a name="l01714"></a>01714         <span class="keywordflow">return</span> 1;
+<a name="l01715"></a>01715 }
+<a name="l01716"></a>01716 
+<a name="l01717"></a>01717 <span class="preprocessor">#ifdef DEBUG</span>
+<a name="l01718"></a>01718 <span class="preprocessor"></span>
+<a name="l01724"></a>01724 <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">int</span> halt_status_ok(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd,
+<a name="l01725"></a>01725                                  <a class="code" href="structdwc__hc.html">dwc_hc_t</a> * hc,
+<a name="l01726"></a>01726                                  <a class="code" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> * hc_regs,
+<a name="l01727"></a>01727                                  <a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> * qtd)
+<a name="l01728"></a>01728 {
+<a name="l01729"></a>01729         <a class="code" href="unionhcchar__data.html">hcchar_data_t</a> hcchar;
+<a name="l01730"></a>01730         <a class="code" href="unionhctsiz__data.html">hctsiz_data_t</a> hctsiz;
+<a name="l01731"></a>01731         <a class="code" href="unionhcint__data.html">hcint_data_t</a> hcint;
+<a name="l01732"></a>01732         <a class="code" href="unionhcintmsk__data.html">hcintmsk_data_t</a> hcintmsk;
+<a name="l01733"></a>01733         <a class="code" href="unionhcsplt__data.html">hcsplt_data_t</a> hcsplt;
+<a name="l01734"></a>01734 
+<a name="l01735"></a>01735         <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#07eca0fa02105ddaa1719387f5558b23">halt_status</a> == DWC_OTG_HC_XFER_NO_HALT_STATUS) {
+<a name="l01736"></a>01736                 <span class="comment">/*</span>
+<a name="l01737"></a>01737 <span class="comment">                 * This code is here only as a check. This condition should</span>
+<a name="l01738"></a>01738 <span class="comment">                 * never happen. Ignore the halt if it does occur.</span>
+<a name="l01739"></a>01739 <span class="comment">                 */</span>
+<a name="l01740"></a>01740                 hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">hcchar</a>);
+<a name="l01741"></a>01741                 hctsiz.<a class="code" href="unionhctsiz__data.html#fb41950555c60c6015294bdefe9cd39d">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#c6173f823ba754d9f9549422b6380ca2">hctsiz</a>);
+<a name="l01742"></a>01742                 hcint.<a class="code" href="unionhcint__data.html#05a82fa7693f875622db744716d7f73e">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#0dfd5bae537d58e13788508dc719480d">hcint</a>);
+<a name="l01743"></a>01743                 hcintmsk.<a class="code" href="unionhcintmsk__data.html#8868299fcc762e005b7f0bf67e5fbe30">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#830aa61c1d4326823662168ea7359205">hcintmsk</a>);
+<a name="l01744"></a>01744                 hcsplt.<a class="code" href="unionhcsplt__data.html#0cd235b445ff681b846f5dccf24fd644">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#149053001a9ee21b692afde531a814de">hcsplt</a>);
+<a name="l01745"></a>01745                 DWC_WARN
+<a name="l01746"></a>01746                     (<span class="stringliteral">"%s: hc-&gt;halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS, "</span>
+<a name="l01747"></a>01747                      <span class="stringliteral">"channel %d, hcchar 0x%08x, hctsiz 0x%08x, "</span>
+<a name="l01748"></a>01748                      <span class="stringliteral">"hcint 0x%08x, hcintmsk 0x%08x, "</span>
+<a name="l01749"></a>01749                      <span class="stringliteral">"hcsplt 0x%08x, qtd-&gt;complete_split %d\n"</span>, __func__,
+<a name="l01750"></a>01750                      hc-&gt;<a class="code" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">hc_num</a>, hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a>, hctsiz.<a class="code" href="unionhctsiz__data.html#fb41950555c60c6015294bdefe9cd39d">d32</a>, hcint.<a class="code" href="unionhcint__data.html#05a82fa7693f875622db744716d7f73e">d32</a>,
+<a name="l01751"></a>01751                      hcintmsk.<a class="code" href="unionhcintmsk__data.html#8868299fcc762e005b7f0bf67e5fbe30">d32</a>, hcsplt.<a class="code" href="unionhcsplt__data.html#0cd235b445ff681b846f5dccf24fd644">d32</a>, qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#6355e968a4d36edce3e22c89ac7b5001">complete_split</a>);
+<a name="l01752"></a>01752 
+<a name="l01753"></a>01753                 DWC_WARN(<span class="stringliteral">"%s: no halt status, channel %d, ignoring interrupt\n"</span>,
+<a name="l01754"></a>01754                          __func__, hc-&gt;<a class="code" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">hc_num</a>);
+<a name="l01755"></a>01755                 DWC_WARN(<span class="stringliteral">"\n"</span>);
+<a name="l01756"></a>01756                 <a class="code" href="dwc__otg__cil_8h.html#071cb1f3f29f9a52775e9fff270b1c7c">clear_hc_int</a>(hc_regs, chhltd);
+<a name="l01757"></a>01757                 <span class="keywordflow">return</span> 0;
+<a name="l01758"></a>01758         }
+<a name="l01759"></a>01759 
+<a name="l01760"></a>01760         <span class="comment">/*</span>
+<a name="l01761"></a>01761 <span class="comment">         * This code is here only as a check. hcchar.chdis should</span>
+<a name="l01762"></a>01762 <span class="comment">         * never be set when the halt interrupt occurs. Halt the</span>
+<a name="l01763"></a>01763 <span class="comment">         * channel again if it does occur.</span>
+<a name="l01764"></a>01764 <span class="comment">         */</span>
+<a name="l01765"></a>01765         hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">hcchar</a>);
+<a name="l01766"></a>01766         <span class="keywordflow">if</span> (hcchar.<a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>.<a class="code" href="unionhcchar__data.html#73c9f7f3cc4036c72ef341d1d1d9c388">chdis</a>) {
+<a name="l01767"></a>01767                 DWC_WARN(<span class="stringliteral">"%s: hcchar.chdis set unexpectedly, "</span>
+<a name="l01768"></a>01768                          <span class="stringliteral">"hcchar 0x%08x, trying to halt again\n"</span>,
+<a name="l01769"></a>01769                          __func__, hcchar.<a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a>);
+<a name="l01770"></a>01770                 <a class="code" href="dwc__otg__cil_8h.html#071cb1f3f29f9a52775e9fff270b1c7c">clear_hc_int</a>(hc_regs, chhltd);
+<a name="l01771"></a>01771                 hc-&gt;<a class="code" href="structdwc__hc.html#2177dcde6dbb17b6bc7d0fb34e8ec95a">halt_pending</a> = 0;
+<a name="l01772"></a>01772                 <a class="code" href="dwc__otg__hcd__intr_8c.html#8b774e79e18861e9ad3ab1d0de00d47c">halt_channel</a>(hcd, hc, qtd, hc-&gt;<a class="code" href="structdwc__hc.html#07eca0fa02105ddaa1719387f5558b23">halt_status</a>);
+<a name="l01773"></a>01773                 <span class="keywordflow">return</span> 0;
+<a name="l01774"></a>01774         }
+<a name="l01775"></a>01775 
+<a name="l01776"></a>01776         <span class="keywordflow">return</span> 1;
+<a name="l01777"></a>01777 }
+<a name="l01778"></a>01778 <span class="preprocessor">#endif</span>
+<a name="l01779"></a>01779 <span class="preprocessor"></span>
+<a name="l01784"></a><a class="code" href="dwc__otg__hcd__intr_8c.html#d75ed153a90dbda39d4d8e6cde4358df">01784</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd__intr_8c.html#d75ed153a90dbda39d4d8e6cde4358df">handle_hc_chhltd_intr_dma</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd,
+<a name="l01785"></a>01785                                       <a class="code" href="structdwc__hc.html">dwc_hc_t</a> * hc,
+<a name="l01786"></a>01786                                       <a class="code" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> * hc_regs,
+<a name="l01787"></a>01787                                       <a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> * qtd)
+<a name="l01788"></a>01788 {
+<a name="l01789"></a>01789         <a class="code" href="unionhcint__data.html">hcint_data_t</a> hcint;
+<a name="l01790"></a>01790         <a class="code" href="unionhcintmsk__data.html">hcintmsk_data_t</a> hcintmsk;
+<a name="l01791"></a>01791         <span class="keywordtype">int</span> out_nak_enh = 0;
+<a name="l01792"></a>01792 
+<a name="l01793"></a>01793         <span class="comment">/* For core with OUT NAK enhancement, the flow for high-</span>
+<a name="l01794"></a>01794 <span class="comment">         * speed CONTROL/BULK OUT is handled a little differently.</span>
+<a name="l01795"></a>01795 <span class="comment">         */</span>
+<a name="l01796"></a>01796         <span class="keywordflow">if</span> (hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#afc495591efa54c74c1dd50278b57ffe">snpsid</a> &gt;= <a class="code" href="dwc__otg__cil_8h.html#aac1e3cc465029aa0a2965b7c6d9fc50">OTG_CORE_REV_2_71a</a>) {
+<a name="l01797"></a>01797                 <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#570b78178975193edb921af1ef36d37b">speed</a> == <a class="code" href="dwc__otg__cil_8h.html#b9dc03c6bc3c1113a935a73cf7021fbe">DWC_OTG_EP_SPEED_HIGH</a> &amp;&amp; !hc-&gt;<a class="code" href="structdwc__hc.html#c5088d431f5efc382121f201f5d571aa">ep_is_in</a> &amp;&amp;
+<a name="l01798"></a>01798                     (hc-&gt;<a class="code" href="structdwc__hc.html#e6169fbc92e4d79686097742ad646f5c">ep_type</a> == <a class="code" href="dwc__otg__cil_8h.html#64e5cd756330f5adab79b25cc8067bdc">DWC_OTG_EP_TYPE_CONTROL</a> ||
+<a name="l01799"></a>01799                      hc-&gt;<a class="code" href="structdwc__hc.html#e6169fbc92e4d79686097742ad646f5c">ep_type</a> == <a class="code" href="dwc__otg__cil_8h.html#9b079858cda0b917316ad9161b3881e0">DWC_OTG_EP_TYPE_BULK</a>)) {
+<a name="l01800"></a>01800                         out_nak_enh = 1;
+<a name="l01801"></a>01801                 }
+<a name="l01802"></a>01802         }
+<a name="l01803"></a>01803 
+<a name="l01804"></a>01804         <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#07eca0fa02105ddaa1719387f5558b23">halt_status</a> == DWC_OTG_HC_XFER_URB_DEQUEUE ||
+<a name="l01805"></a>01805             (hc-&gt;<a class="code" href="structdwc__hc.html#07eca0fa02105ddaa1719387f5558b23">halt_status</a> == DWC_OTG_HC_XFER_AHB_ERR &amp;&amp; !hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a>)) {
+<a name="l01806"></a>01806                 <span class="comment">/*</span>
+<a name="l01807"></a>01807 <span class="comment">                 * Just release the channel. A dequeue can happen on a</span>
+<a name="l01808"></a>01808 <span class="comment">                 * transfer timeout. In the case of an AHB Error, the channel</span>
+<a name="l01809"></a>01809 <span class="comment">                 * was forced to halt because there's no way to gracefully</span>
+<a name="l01810"></a>01810 <span class="comment">                 * recover.</span>
+<a name="l01811"></a>01811 <span class="comment">                 */</span>
+<a name="l01812"></a>01812                 <span class="keywordflow">if</span> (hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a>)
+<a name="l01813"></a>01813                         <a class="code" href="dwc__otg__hcd_8h.html#ca94cde3142ff1121bb0ff9bd44fa762">dwc_otg_hcd_complete_xfer_ddma</a>(hcd, hc, hc_regs, hc-&gt;<a class="code" href="structdwc__hc.html#07eca0fa02105ddaa1719387f5558b23">halt_status</a>);
+<a name="l01814"></a>01814                 <span class="keywordflow">else</span>
+<a name="l01815"></a>01815                         <a class="code" href="dwc__otg__hcd__intr_8c.html#4f6bf01b14a03eeed81d27bffa5e99fc">release_channel</a>(hcd, hc, qtd, hc-&gt;<a class="code" href="structdwc__hc.html#07eca0fa02105ddaa1719387f5558b23">halt_status</a>);
+<a name="l01816"></a>01816                 <span class="keywordflow">return</span>;
+<a name="l01817"></a>01817         }
+<a name="l01818"></a>01818 
+<a name="l01819"></a>01819         <span class="comment">/* Read the HCINTn register to determine the cause for the halt. */</span>
+<a name="l01820"></a>01820         hcint.<a class="code" href="unionhcint__data.html#05a82fa7693f875622db744716d7f73e">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#0dfd5bae537d58e13788508dc719480d">hcint</a>);
+<a name="l01821"></a>01821         hcintmsk.<a class="code" href="unionhcintmsk__data.html#8868299fcc762e005b7f0bf67e5fbe30">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#830aa61c1d4326823662168ea7359205">hcintmsk</a>);
+<a name="l01822"></a>01822 
+<a name="l01823"></a>01823         <span class="keywordflow">if</span> (hcint.<a class="code" href="unionhcint__data.html#3ab6af507f45d91a7898dd711f4368ee">b</a>.<a class="code" href="unionhcint__data.html#49385cb90c4d8c003cfac91175a646e0">xfercomp</a>) {
+<a name="l01830"></a>01830                 <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#e6169fbc92e4d79686097742ad646f5c">ep_type</a> == <a class="code" href="dwc__otg__cil_8h.html#152a3a5e1433bd2197672f0b5105e7a4">DWC_OTG_EP_TYPE_ISOC</a> &amp;&amp; !hc-&gt;<a class="code" href="structdwc__hc.html#c5088d431f5efc382121f201f5d571aa">ep_is_in</a>) {
+<a name="l01831"></a>01831                         <a class="code" href="dwc__otg__hcd__intr_8c.html#243b0fb4191e46127a6823c0b5e970bb">handle_hc_ack_intr</a>(hcd, hc, hc_regs, qtd);
+<a name="l01832"></a>01832                 }
+<a name="l01833"></a>01833                 <a class="code" href="dwc__otg__hcd__intr_8c.html#e8bfcabff910322ef19eec9fc99fd097">handle_hc_xfercomp_intr</a>(hcd, hc, hc_regs, qtd);
+<a name="l01834"></a>01834         } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (hcint.<a class="code" href="unionhcint__data.html#3ab6af507f45d91a7898dd711f4368ee">b</a>.<a class="code" href="unionhcint__data.html#cf2fb413e5758e9ebd8914b2f7605d73">stall</a>) {
+<a name="l01835"></a>01835                 <a class="code" href="dwc__otg__hcd__intr_8c.html#e89fabf3023fa4f0279f312e5e9d4223">handle_hc_stall_intr</a>(hcd, hc, hc_regs, qtd);
+<a name="l01836"></a>01836         } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (hcint.<a class="code" href="unionhcint__data.html#3ab6af507f45d91a7898dd711f4368ee">b</a>.<a class="code" href="unionhcint__data.html#86ec2d311ef29228676781f9100d195a">xacterr</a> &amp;&amp; !hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a>) {
+<a name="l01837"></a>01837                 <span class="keywordflow">if</span> (out_nak_enh) {
+<a name="l01838"></a>01838                         <span class="keywordflow">if</span> (hcint.<a class="code" href="unionhcint__data.html#3ab6af507f45d91a7898dd711f4368ee">b</a>.<a class="code" href="unionhcint__data.html#755e54c3dfded3653447dfdd63fd8b6a">nyet</a> || hcint.<a class="code" href="unionhcint__data.html#3ab6af507f45d91a7898dd711f4368ee">b</a>.<a class="code" href="unionhcint__data.html#ce65c9d3f0c7d3e5b8f163a378051c6c">nak</a> || hcint.<a class="code" href="unionhcint__data.html#3ab6af507f45d91a7898dd711f4368ee">b</a>.<a class="code" href="unionhcint__data.html#729749d6d0b5a1d4c449287f9efdd5fe">ack</a>) {
+<a name="l01839"></a>01839                                 DWC_DEBUG(<span class="stringliteral">"XactErr with NYET/NAK/ACK\n"</span>);
+<a name="l01840"></a>01840                                 qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#18eeb9c647049aec468bf9a7861c873f">error_count</a> = 0;
+<a name="l01841"></a>01841                         } <span class="keywordflow">else</span> {
+<a name="l01842"></a>01842                                 DWC_DEBUG(<span class="stringliteral">"XactErr without NYET/NAK/ACK\n"</span>);
+<a name="l01843"></a>01843                         }
+<a name="l01844"></a>01844                 }
+<a name="l01845"></a>01845 
+<a name="l01846"></a>01846                 <span class="comment">/*</span>
+<a name="l01847"></a>01847 <span class="comment">                 * Must handle xacterr before nak or ack. Could get a xacterr</span>
+<a name="l01848"></a>01848 <span class="comment">                 * at the same time as either of these on a BULK/CONTROL OUT</span>
+<a name="l01849"></a>01849 <span class="comment">                 * that started with a PING. The xacterr takes precedence.</span>
+<a name="l01850"></a>01850 <span class="comment">                 */</span>
+<a name="l01851"></a>01851                 <a class="code" href="dwc__otg__hcd__intr_8c.html#464af1671bd416d5db48a51fc93366ee">handle_hc_xacterr_intr</a>(hcd, hc, hc_regs, qtd);
+<a name="l01852"></a>01852         } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (hcint.<a class="code" href="unionhcint__data.html#3ab6af507f45d91a7898dd711f4368ee">b</a>.<a class="code" href="unionhcint__data.html#f13613b1a33edddb676d2bce8a35e447">xcs_xact</a> &amp;&amp; hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a>) {
+<a name="l01853"></a>01853                 <a class="code" href="dwc__otg__hcd__intr_8c.html#464af1671bd416d5db48a51fc93366ee">handle_hc_xacterr_intr</a>(hcd, hc, hc_regs, qtd);
+<a name="l01854"></a>01854         } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (hcint.<a class="code" href="unionhcint__data.html#3ab6af507f45d91a7898dd711f4368ee">b</a>.<a class="code" href="unionhcint__data.html#f953465ff02c518a52c48d4d6b1c09c7">ahberr</a> &amp;&amp; hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a>) {    
+<a name="l01855"></a>01855                 <a class="code" href="dwc__otg__hcd__intr_8c.html#1edf7eebc0475898518e18dc12c1b4b9">handle_hc_ahberr_intr</a>(hcd, hc, hc_regs, qtd);
+<a name="l01856"></a>01856         } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (hcint.<a class="code" href="unionhcint__data.html#3ab6af507f45d91a7898dd711f4368ee">b</a>.<a class="code" href="unionhcint__data.html#b05adf33c7be609a2daf54478f884ec4">bblerr</a>) {
+<a name="l01857"></a>01857                 <a class="code" href="dwc__otg__hcd__intr_8c.html#ab5348f52aac4081a9c35d529c1fcd79">handle_hc_babble_intr</a>(hcd, hc, hc_regs, qtd);
+<a name="l01858"></a>01858         } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (hcint.<a class="code" href="unionhcint__data.html#3ab6af507f45d91a7898dd711f4368ee">b</a>.<a class="code" href="unionhcint__data.html#06f911d323d71f86639550507322dffb">frmovrun</a>) {
+<a name="l01859"></a>01859                 <a class="code" href="dwc__otg__hcd__intr_8c.html#a30d61b2809dccf609bcf83cc61c9d63">handle_hc_frmovrun_intr</a>(hcd, hc, hc_regs, qtd);
+<a name="l01860"></a>01860         } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (!out_nak_enh) {
+<a name="l01861"></a>01861                 <span class="keywordflow">if</span> (hcint.<a class="code" href="unionhcint__data.html#3ab6af507f45d91a7898dd711f4368ee">b</a>.<a class="code" href="unionhcint__data.html#755e54c3dfded3653447dfdd63fd8b6a">nyet</a>) {
+<a name="l01862"></a>01862                         <span class="comment">/*</span>
+<a name="l01863"></a>01863 <span class="comment">                         * Must handle nyet before nak or ack. Could get a nyet at the</span>
+<a name="l01864"></a>01864 <span class="comment">                         * same time as either of those on a BULK/CONTROL OUT that</span>
+<a name="l01865"></a>01865 <span class="comment">                         * started with a PING. The nyet takes precedence.</span>
+<a name="l01866"></a>01866 <span class="comment">                         */</span>
+<a name="l01867"></a>01867                         <a class="code" href="dwc__otg__hcd__intr_8c.html#5093a2b94c1d5cd1988eb93d9def298f">handle_hc_nyet_intr</a>(hcd, hc, hc_regs, qtd);
+<a name="l01868"></a>01868                 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (hcint.<a class="code" href="unionhcint__data.html#3ab6af507f45d91a7898dd711f4368ee">b</a>.<a class="code" href="unionhcint__data.html#ce65c9d3f0c7d3e5b8f163a378051c6c">nak</a> &amp;&amp; !hcintmsk.<a class="code" href="unionhcintmsk__data.html#6835f55069c94947b580c8f01f64a075">b</a>.<a class="code" href="unionhcintmsk__data.html#32ae7d92d0eb93ced42ac3773ddc3a2f">nak</a>) {
+<a name="l01869"></a>01869                         <span class="comment">/*</span>
+<a name="l01870"></a>01870 <span class="comment">                         * If nak is not masked, it's because a non-split IN transfer</span>
+<a name="l01871"></a>01871 <span class="comment">                         * is in an error state. In that case, the nak is handled by</span>
+<a name="l01872"></a>01872 <span class="comment">                         * the nak interrupt handler, not here. Handle nak here for</span>
+<a name="l01873"></a>01873 <span class="comment">                         * BULK/CONTROL OUT transfers, which halt on a NAK to allow</span>
+<a name="l01874"></a>01874 <span class="comment">                         * rewinding the buffer pointer.</span>
+<a name="l01875"></a>01875 <span class="comment">                         */</span>
+<a name="l01876"></a>01876                         <a class="code" href="dwc__otg__hcd__intr_8c.html#19f718e1e8f7cded3bb7431008ee0309">handle_hc_nak_intr</a>(hcd, hc, hc_regs, qtd);
+<a name="l01877"></a>01877                 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (hcint.<a class="code" href="unionhcint__data.html#3ab6af507f45d91a7898dd711f4368ee">b</a>.<a class="code" href="unionhcint__data.html#729749d6d0b5a1d4c449287f9efdd5fe">ack</a> &amp;&amp; !hcintmsk.<a class="code" href="unionhcintmsk__data.html#6835f55069c94947b580c8f01f64a075">b</a>.<a class="code" href="unionhcintmsk__data.html#8d3388818a6dc098a1e1c64147d1ced9">ack</a>) {
+<a name="l01878"></a>01878                         <span class="comment">/*</span>
+<a name="l01879"></a>01879 <span class="comment">                         * If ack is not masked, it's because a non-split IN transfer</span>
+<a name="l01880"></a>01880 <span class="comment">                         * is in an error state. In that case, the ack is handled by</span>
+<a name="l01881"></a>01881 <span class="comment">                         * the ack interrupt handler, not here. Handle ack here for</span>
+<a name="l01882"></a>01882 <span class="comment">                         * split transfers. Start splits halt on ACK.</span>
+<a name="l01883"></a>01883 <span class="comment">                         */</span>
+<a name="l01884"></a>01884                         <a class="code" href="dwc__otg__hcd__intr_8c.html#243b0fb4191e46127a6823c0b5e970bb">handle_hc_ack_intr</a>(hcd, hc, hc_regs, qtd);
+<a name="l01885"></a>01885                 } <span class="keywordflow">else</span> {
+<a name="l01886"></a>01886                         <span class="keywordflow">if</span> (hc-&gt;<a class="code" href="structdwc__hc.html#e6169fbc92e4d79686097742ad646f5c">ep_type</a> == <a class="code" href="dwc__otg__cil_8h.html#1401d1264f88530232cf51ab31cc5347">DWC_OTG_EP_TYPE_INTR</a> ||
+<a name="l01887"></a>01887                             hc-&gt;<a class="code" href="structdwc__hc.html#e6169fbc92e4d79686097742ad646f5c">ep_type</a> == <a class="code" href="dwc__otg__cil_8h.html#152a3a5e1433bd2197672f0b5105e7a4">DWC_OTG_EP_TYPE_ISOC</a>) {
+<a name="l01888"></a>01888                                 <span class="comment">/*</span>
+<a name="l01889"></a>01889 <span class="comment">                                 * A periodic transfer halted with no other channel</span>
+<a name="l01890"></a>01890 <span class="comment">                                 * interrupts set. Assume it was halted by the core</span>
+<a name="l01891"></a>01891 <span class="comment">                                 * because it could not be completed in its scheduled</span>
+<a name="l01892"></a>01892 <span class="comment">                                 * (micro)frame.</span>
+<a name="l01893"></a>01893 <span class="comment">                                 */</span>
+<a name="l01894"></a>01894 <span class="preprocessor">#ifdef DEBUG</span>
+<a name="l01895"></a>01895 <span class="preprocessor"></span>                                DWC_PRINTF
+<a name="l01896"></a>01896                                     (<span class="stringliteral">"%s: Halt channel %d (assume incomplete periodic transfer)\n"</span>,
+<a name="l01897"></a>01897                                      __func__, hc-&gt;<a class="code" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">hc_num</a>);
+<a name="l01898"></a>01898 <span class="preprocessor">#endif</span>
+<a name="l01899"></a>01899 <span class="preprocessor"></span>                                <a class="code" href="dwc__otg__hcd__intr_8c.html#8b774e79e18861e9ad3ab1d0de00d47c">halt_channel</a>(hcd, hc, qtd,
+<a name="l01900"></a>01900                                              DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE);
+<a name="l01901"></a>01901                         } <span class="keywordflow">else</span> {
+<a name="l01902"></a>01902                                 DWC_ERROR
+<a name="l01903"></a>01903                                     (<span class="stringliteral">"%s: Channel %d, DMA Mode -- ChHltd set, but reason "</span>
+<a name="l01904"></a>01904                                      <span class="stringliteral">"for halting is unknown, hcint 0x%08x, intsts 0x%08x\n"</span>,
+<a name="l01905"></a>01905                                      __func__, hc-&gt;<a class="code" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">hc_num</a>, hcint.<a class="code" href="unionhcint__data.html#05a82fa7693f875622db744716d7f73e">d32</a>,
+<a name="l01906"></a>01906                                      dwc_read_reg32(&amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;
+<a name="l01907"></a>01907                                                     core_global_regs-&gt;gintsts));
+<a name="l01908"></a>01908                         }
+<a name="l01909"></a>01909         
+<a name="l01910"></a>01910                 }
+<a name="l01911"></a>01911         } <span class="keywordflow">else</span> {
+<a name="l01912"></a>01912                 DWC_PRINTF(<span class="stringliteral">"NYET/NAK/ACK/other in non-error case, 0x%08x\n"</span>,
+<a name="l01913"></a>01913                            hcint.<a class="code" href="unionhcint__data.html#05a82fa7693f875622db744716d7f73e">d32</a>);
+<a name="l01914"></a>01914         }
+<a name="l01915"></a>01915 }
+<a name="l01916"></a>01916 
+<a name="l01928"></a><a class="code" href="dwc__otg__hcd__intr_8c.html#83541cd20d3297d7d7d24052834ef019">01928</a> <span class="keyword">static</span> int32_t <a class="code" href="dwc__otg__hcd__intr_8c.html#83541cd20d3297d7d7d24052834ef019">handle_hc_chhltd_intr</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd,
+<a name="l01929"></a>01929                                      <a class="code" href="structdwc__hc.html">dwc_hc_t</a> * hc,
+<a name="l01930"></a>01930                                      <a class="code" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> * hc_regs,
+<a name="l01931"></a>01931                                      <a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> * qtd)
+<a name="l01932"></a>01932 {
+<a name="l01933"></a>01933         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#e4a050e176c1c4f556da2b276a8c2b37">DBG_HCD</a>, <span class="stringliteral">"--Host Channel %d Interrupt: "</span>
+<a name="l01934"></a>01934                     <span class="stringliteral">"Channel Halted--\n"</span>, hc-&gt;<a class="code" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">hc_num</a>);
+<a name="l01935"></a>01935 
+<a name="l01936"></a>01936         <span class="keywordflow">if</span> (hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a>) {
+<a name="l01937"></a>01937                 <a class="code" href="dwc__otg__hcd__intr_8c.html#d75ed153a90dbda39d4d8e6cde4358df">handle_hc_chhltd_intr_dma</a>(hcd, hc, hc_regs, qtd);
+<a name="l01938"></a>01938         } <span class="keywordflow">else</span> {
+<a name="l01939"></a>01939 <span class="preprocessor">#ifdef DEBUG</span>
+<a name="l01940"></a>01940 <span class="preprocessor"></span>                <span class="keywordflow">if</span> (!halt_status_ok(hcd, hc, hc_regs, qtd)) {
+<a name="l01941"></a>01941                         <span class="keywordflow">return</span> 1;
+<a name="l01942"></a>01942                 }
+<a name="l01943"></a>01943 <span class="preprocessor">#endif</span>
+<a name="l01944"></a>01944 <span class="preprocessor"></span>                <a class="code" href="dwc__otg__hcd__intr_8c.html#4f6bf01b14a03eeed81d27bffa5e99fc">release_channel</a>(hcd, hc, qtd, hc-&gt;<a class="code" href="structdwc__hc.html#07eca0fa02105ddaa1719387f5558b23">halt_status</a>);
+<a name="l01945"></a>01945         }
+<a name="l01946"></a>01946 
+<a name="l01947"></a>01947         <span class="keywordflow">return</span> 1;
+<a name="l01948"></a>01948 }
+<a name="l01949"></a>01949 
+<a name="l01951"></a><a class="code" href="dwc__otg__hcd__intr_8c.html#019c9cc38ec85275a7ef0b0d38bf53ab">01951</a> int32_t <a class="code" href="dwc__otg__hcd_8h.html#019c9cc38ec85275a7ef0b0d38bf53ab">dwc_otg_hcd_handle_hc_n_intr</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * <a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>, uint32_t num)
+<a name="l01952"></a>01952 {
+<a name="l01953"></a>01953         <span class="keywordtype">int</span> retval = 0;
+<a name="l01954"></a>01954         <a class="code" href="unionhcint__data.html">hcint_data_t</a> hcint;
+<a name="l01955"></a>01955         <a class="code" href="unionhcintmsk__data.html">hcintmsk_data_t</a> hcintmsk;
+<a name="l01956"></a>01956         <a class="code" href="structdwc__hc.html">dwc_hc_t</a> *hc;
+<a name="l01957"></a>01957         <a class="code" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *hc_regs;
+<a name="l01958"></a>01958         <a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *qtd;
+<a name="l01959"></a>01959 
+<a name="l01960"></a>01960         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"--Host Channel Interrupt--, Channel %d\n"</span>, num);
+<a name="l01961"></a>01961 
+<a name="l01962"></a>01962         hc = dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#cb393f6a676fb106e0e3d35396fb97f9">hc_ptr_array</a>[num];
+<a name="l01963"></a>01963         hc_regs = dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#7f7c107d4720641eb4141cd817211ac0">hc_regs</a>[num];
+<a name="l01964"></a>01964         qtd = DWC_CIRCLEQ_FIRST(&amp;hc-&gt;<a class="code" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a>-&gt;<a class="code" href="structdwc__otg__qh.html#9567d266da8e796d3467fb16ae867f8e">qtd_list</a>);
+<a name="l01965"></a>01965 
+<a name="l01966"></a>01966         hcint.<a class="code" href="unionhcint__data.html#05a82fa7693f875622db744716d7f73e">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#0dfd5bae537d58e13788508dc719480d">hcint</a>);
+<a name="l01967"></a>01967         hcintmsk.<a class="code" href="unionhcintmsk__data.html#8868299fcc762e005b7f0bf67e5fbe30">d32</a> = dwc_read_reg32(&amp;hc_regs-&gt;<a class="code" href="structdwc__otg__hc__regs.html#830aa61c1d4326823662168ea7359205">hcintmsk</a>);
+<a name="l01968"></a>01968         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>,
+<a name="l01969"></a>01969                     <span class="stringliteral">"  hcint 0x%08x, hcintmsk 0x%08x, hcint&amp;hcintmsk 0x%08x\n"</span>,
+<a name="l01970"></a>01970                     hcint.<a class="code" href="unionhcint__data.html#05a82fa7693f875622db744716d7f73e">d32</a>, hcintmsk.<a class="code" href="unionhcintmsk__data.html#8868299fcc762e005b7f0bf67e5fbe30">d32</a>, (hcint.<a class="code" href="unionhcint__data.html#05a82fa7693f875622db744716d7f73e">d32</a> &amp; hcintmsk.<a class="code" href="unionhcintmsk__data.html#8868299fcc762e005b7f0bf67e5fbe30">d32</a>));
+<a name="l01971"></a>01971         hcint.<a class="code" href="unionhcint__data.html#05a82fa7693f875622db744716d7f73e">d32</a> = hcint.<a class="code" href="unionhcint__data.html#05a82fa7693f875622db744716d7f73e">d32</a> &amp; hcintmsk.<a class="code" href="unionhcintmsk__data.html#8868299fcc762e005b7f0bf67e5fbe30">d32</a>;
+<a name="l01972"></a>01972 
+<a name="l01973"></a>01973         <span class="keywordflow">if</span> (!dwc_otg_hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a>) {
+<a name="l01974"></a>01974                 <span class="keywordflow">if</span> (hcint.<a class="code" href="unionhcint__data.html#3ab6af507f45d91a7898dd711f4368ee">b</a>.<a class="code" href="unionhcint__data.html#b93ceab913a49e33c5bf4dde0e62d75a">chhltd</a> &amp;&amp; hcint.<a class="code" href="unionhcint__data.html#05a82fa7693f875622db744716d7f73e">d32</a> != 0x2) {
+<a name="l01975"></a>01975                         hcint.<a class="code" href="unionhcint__data.html#3ab6af507f45d91a7898dd711f4368ee">b</a>.<a class="code" href="unionhcint__data.html#b93ceab913a49e33c5bf4dde0e62d75a">chhltd</a> = 0;
+<a name="l01976"></a>01976                 }
+<a name="l01977"></a>01977         }
+<a name="l01978"></a>01978 
+<a name="l01979"></a>01979         <span class="keywordflow">if</span> (hcint.<a class="code" href="unionhcint__data.html#3ab6af507f45d91a7898dd711f4368ee">b</a>.<a class="code" href="unionhcint__data.html#49385cb90c4d8c003cfac91175a646e0">xfercomp</a>) {
+<a name="l01980"></a>01980                 retval |=
+<a name="l01981"></a>01981                     <a class="code" href="dwc__otg__hcd__intr_8c.html#e8bfcabff910322ef19eec9fc99fd097">handle_hc_xfercomp_intr</a>(dwc_otg_hcd, hc, hc_regs, qtd);
+<a name="l01982"></a>01982                 <span class="comment">/*</span>
+<a name="l01983"></a>01983 <span class="comment">                 * If NYET occurred at same time as Xfer Complete, the NYET is</span>
+<a name="l01984"></a>01984 <span class="comment">                 * handled by the Xfer Complete interrupt handler. Don't want</span>
+<a name="l01985"></a>01985 <span class="comment">                 * to call the NYET interrupt handler in this case.</span>
+<a name="l01986"></a>01986 <span class="comment">                 */</span>
+<a name="l01987"></a>01987                 hcint.<a class="code" href="unionhcint__data.html#3ab6af507f45d91a7898dd711f4368ee">b</a>.<a class="code" href="unionhcint__data.html#755e54c3dfded3653447dfdd63fd8b6a">nyet</a> = 0;
+<a name="l01988"></a>01988         }
+<a name="l01989"></a>01989         <span class="keywordflow">if</span> (hcint.<a class="code" href="unionhcint__data.html#3ab6af507f45d91a7898dd711f4368ee">b</a>.<a class="code" href="unionhcint__data.html#b93ceab913a49e33c5bf4dde0e62d75a">chhltd</a>) {
+<a name="l01990"></a>01990                 retval |= <a class="code" href="dwc__otg__hcd__intr_8c.html#83541cd20d3297d7d7d24052834ef019">handle_hc_chhltd_intr</a>(dwc_otg_hcd, hc, hc_regs, qtd);
+<a name="l01991"></a>01991         }
+<a name="l01992"></a>01992         <span class="keywordflow">if</span> (hcint.<a class="code" href="unionhcint__data.html#3ab6af507f45d91a7898dd711f4368ee">b</a>.<a class="code" href="unionhcint__data.html#f953465ff02c518a52c48d4d6b1c09c7">ahberr</a>) {
+<a name="l01993"></a>01993                 retval |= <a class="code" href="dwc__otg__hcd__intr_8c.html#1edf7eebc0475898518e18dc12c1b4b9">handle_hc_ahberr_intr</a>(dwc_otg_hcd, hc, hc_regs, qtd);
+<a name="l01994"></a>01994         }
+<a name="l01995"></a>01995         <span class="keywordflow">if</span> (hcint.<a class="code" href="unionhcint__data.html#3ab6af507f45d91a7898dd711f4368ee">b</a>.<a class="code" href="unionhcint__data.html#cf2fb413e5758e9ebd8914b2f7605d73">stall</a>) {
+<a name="l01996"></a>01996                 retval |= <a class="code" href="dwc__otg__hcd__intr_8c.html#e89fabf3023fa4f0279f312e5e9d4223">handle_hc_stall_intr</a>(dwc_otg_hcd, hc, hc_regs, qtd);
+<a name="l01997"></a>01997         }
+<a name="l01998"></a>01998         <span class="keywordflow">if</span> (hcint.<a class="code" href="unionhcint__data.html#3ab6af507f45d91a7898dd711f4368ee">b</a>.<a class="code" href="unionhcint__data.html#ce65c9d3f0c7d3e5b8f163a378051c6c">nak</a>) {
+<a name="l01999"></a>01999                 retval |= <a class="code" href="dwc__otg__hcd__intr_8c.html#19f718e1e8f7cded3bb7431008ee0309">handle_hc_nak_intr</a>(dwc_otg_hcd, hc, hc_regs, qtd);
+<a name="l02000"></a>02000         }
+<a name="l02001"></a>02001         <span class="keywordflow">if</span> (hcint.<a class="code" href="unionhcint__data.html#3ab6af507f45d91a7898dd711f4368ee">b</a>.<a class="code" href="unionhcint__data.html#729749d6d0b5a1d4c449287f9efdd5fe">ack</a>) {
+<a name="l02002"></a>02002                 retval |= <a class="code" href="dwc__otg__hcd__intr_8c.html#243b0fb4191e46127a6823c0b5e970bb">handle_hc_ack_intr</a>(dwc_otg_hcd, hc, hc_regs, qtd);
+<a name="l02003"></a>02003         }
+<a name="l02004"></a>02004         <span class="keywordflow">if</span> (hcint.<a class="code" href="unionhcint__data.html#3ab6af507f45d91a7898dd711f4368ee">b</a>.<a class="code" href="unionhcint__data.html#755e54c3dfded3653447dfdd63fd8b6a">nyet</a>) {
+<a name="l02005"></a>02005                 retval |= <a class="code" href="dwc__otg__hcd__intr_8c.html#5093a2b94c1d5cd1988eb93d9def298f">handle_hc_nyet_intr</a>(dwc_otg_hcd, hc, hc_regs, qtd);
+<a name="l02006"></a>02006         }
+<a name="l02007"></a>02007         <span class="keywordflow">if</span> (hcint.<a class="code" href="unionhcint__data.html#3ab6af507f45d91a7898dd711f4368ee">b</a>.<a class="code" href="unionhcint__data.html#86ec2d311ef29228676781f9100d195a">xacterr</a>) {
+<a name="l02008"></a>02008                 retval |= <a class="code" href="dwc__otg__hcd__intr_8c.html#464af1671bd416d5db48a51fc93366ee">handle_hc_xacterr_intr</a>(dwc_otg_hcd, hc, hc_regs, qtd);
+<a name="l02009"></a>02009         }
+<a name="l02010"></a>02010         <span class="keywordflow">if</span> (hcint.<a class="code" href="unionhcint__data.html#3ab6af507f45d91a7898dd711f4368ee">b</a>.<a class="code" href="unionhcint__data.html#b05adf33c7be609a2daf54478f884ec4">bblerr</a>) {
+<a name="l02011"></a>02011                 retval |= <a class="code" href="dwc__otg__hcd__intr_8c.html#ab5348f52aac4081a9c35d529c1fcd79">handle_hc_babble_intr</a>(dwc_otg_hcd, hc, hc_regs, qtd);
+<a name="l02012"></a>02012         }
+<a name="l02013"></a>02013         <span class="keywordflow">if</span> (hcint.<a class="code" href="unionhcint__data.html#3ab6af507f45d91a7898dd711f4368ee">b</a>.<a class="code" href="unionhcint__data.html#06f911d323d71f86639550507322dffb">frmovrun</a>) {
+<a name="l02014"></a>02014                 retval |=
+<a name="l02015"></a>02015                     <a class="code" href="dwc__otg__hcd__intr_8c.html#a30d61b2809dccf609bcf83cc61c9d63">handle_hc_frmovrun_intr</a>(dwc_otg_hcd, hc, hc_regs, qtd);
+<a name="l02016"></a>02016         }
+<a name="l02017"></a>02017         <span class="keywordflow">if</span> (hcint.<a class="code" href="unionhcint__data.html#3ab6af507f45d91a7898dd711f4368ee">b</a>.<a class="code" href="unionhcint__data.html#2fc8618d16e6908e99c8cca3ffb54736">datatglerr</a>) {
+<a name="l02018"></a>02018                 retval |=
+<a name="l02019"></a>02019                     <a class="code" href="dwc__otg__hcd__intr_8c.html#f73e70f0e622267b6281e0cd6c1d89cf">handle_hc_datatglerr_intr</a>(dwc_otg_hcd, hc, hc_regs, qtd);
+<a name="l02020"></a>02020         }
+<a name="l02021"></a>02021 
+<a name="l02022"></a>02022         <span class="keywordflow">return</span> retval;
+<a name="l02023"></a>02023 }
+<a name="l02024"></a>02024 
+<a name="l02025"></a>02025 <span class="preprocessor">#endif                          </span><span class="comment">/* DWC_DEVICE_ONLY */</span>
+</pre></div><hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__intr_8c.html b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__intr_8c.html
new file mode 100644
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--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__intr_8c.html
@@ -0,0 +1,1252 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd_intr.c File Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
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+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
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+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<h1>dwc_otg_hcd_intr.c File Reference</h1>This file contains the implementation of the HCD Interrupt handlers. <a href="#_details">More...</a>
+<p>
+<code>#include &quot;<a class="el" href="dwc__otg__hcd_8h-source.html">dwc_otg_hcd.h</a>&quot;</code><br>
+<code>#include &quot;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&quot;</code><br>
+
+<p>
+<a href="dwc__otg__hcd__intr_8c-source.html">Go to the source code of this file.</a><table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Functions</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__intr_8c.html#b9dde24773f2741b9ff67e2d46760dc0">dwc_otg_hcd_handle_intr</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function should be called on every hardware interrupt.  <a href="#b9dde24773f2741b9ff67e2d46760dc0"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__intr_8c.html#bbf5740390826d69bba80651ef9bd725">dwc_otg_hcd_handle_sof_intr</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Handles the start-of-frame interrupt in host mode.  <a href="#bbf5740390826d69bba80651ef9bd725"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__intr_8c.html#9d979e33e04fc694a72242dec63aeb89">dwc_otg_hcd_handle_rx_status_q_level_intr</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Handles the Rx Status Queue Level Interrupt, which indicates that there is at least one packet in the Rx FIFO.  <a href="#9d979e33e04fc694a72242dec63aeb89"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__intr_8c.html#51c953aefbc2382adee9f585fdb26f35">dwc_otg_hcd_handle_np_tx_fifo_empty_intr</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This interrupt occurs when the non-periodic Tx FIFO is half-empty.  <a href="#51c953aefbc2382adee9f585fdb26f35"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__intr_8c.html#dcfa21f80c7732df9aaf3db59a86eb1d">dwc_otg_hcd_handle_perio_tx_fifo_empty_intr</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This interrupt occurs when the periodic Tx FIFO is half-empty.  <a href="#dcfa21f80c7732df9aaf3db59a86eb1d"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__intr_8c.html#18bb807c86935a45f5fe5940e5ded70c">dwc_otg_hcd_handle_port_intr</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">There are multiple conditions that can cause a port interrupt.  <a href="#18bb807c86935a45f5fe5940e5ded70c"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__intr_8c.html#1f28e296c0bc4146da309385d95b5d7e">dwc_otg_hcd_handle_hc_intr</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This interrupt indicates that one or more host channels has a pending interrupt.  <a href="#1f28e296c0bc4146da309385d95b5d7e"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__intr_8c.html#6cdb134cbb3cdf3501ca39761137baf0">get_actual_xfer_length</a> (<a class="el" href="structdwc__hc.html">dwc_hc_t</a> *hc, <a class="el" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *hc_regs, <a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *qtd, dwc_otg_halt_status_e halt_status, int *short_read)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Gets the actual length of a transfer after the transfer halts.  <a href="#6cdb134cbb3cdf3501ca39761137baf0"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__intr_8c.html#ecb30a961e8d4831e8691d45a77162e3">update_urb_state_xfer_comp</a> (<a class="el" href="structdwc__hc.html">dwc_hc_t</a> *hc, <a class="el" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *hc_regs, <a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *urb, <a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *qtd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Updates the state of the URB after a Transfer Complete interrupt on the host channel.  <a href="#ecb30a961e8d4831e8691d45a77162e3"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="8bce109004d7869bfdd9aa1075c6bd2c"></a><!-- doxytag: member="dwc_otg_hcd_intr.c::dwc_otg_hcd_save_data_toggle" ref="8bce109004d7869bfdd9aa1075c6bd2c" args="(dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__intr_8c.html#8bce109004d7869bfdd9aa1075c6bd2c">dwc_otg_hcd_save_data_toggle</a> (<a class="el" href="structdwc__hc.html">dwc_hc_t</a> *hc, <a class="el" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *hc_regs, <a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *qtd)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static dwc_otg_halt_status_e&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__intr_8c.html#e93d54bdf873c5a31882660c2984458e">update_isoc_urb_state</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__hc.html">dwc_hc_t</a> *hc, <a class="el" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *hc_regs, <a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *qtd, dwc_otg_halt_status_e halt_status)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Updates the state of an Isochronous URB when the transfer is stopped for any reason.  <a href="#e93d54bdf873c5a31882660c2984458e"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__intr_8c.html#57e9a29ec2dc8cd8d119acade0ae4ff1">deactivate_qh</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *qh, int free_qtd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Frees the first QTD in the QH's list if free_qtd is 1.  <a href="#57e9a29ec2dc8cd8d119acade0ae4ff1"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__intr_8c.html#4f6bf01b14a03eeed81d27bffa5e99fc">release_channel</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__hc.html">dwc_hc_t</a> *hc, <a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *qtd, dwc_otg_halt_status_e halt_status)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Releases a host channel for use by other transfers.  <a href="#4f6bf01b14a03eeed81d27bffa5e99fc"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__intr_8c.html#8b774e79e18861e9ad3ab1d0de00d47c">halt_channel</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__hc.html">dwc_hc_t</a> *hc, <a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *qtd, dwc_otg_halt_status_e halt_status)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Halts a host channel.  <a href="#8b774e79e18861e9ad3ab1d0de00d47c"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__intr_8c.html#2fa47944efef508dddcab00b0050ef0a">complete_non_periodic_xfer</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__hc.html">dwc_hc_t</a> *hc, <a class="el" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *hc_regs, <a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *qtd, dwc_otg_halt_status_e halt_status)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Performs common cleanup for non-periodic transfers after a Transfer Complete interrupt.  <a href="#2fa47944efef508dddcab00b0050ef0a"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__intr_8c.html#a0fa0d4fa5f0af15860d685bb8fe3e50">complete_periodic_xfer</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__hc.html">dwc_hc_t</a> *hc, <a class="el" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *hc_regs, <a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *qtd, dwc_otg_halt_status_e halt_status)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Performs common cleanup for periodic transfers after a Transfer Complete interrupt.  <a href="#a0fa0d4fa5f0af15860d685bb8fe3e50"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="a56eb0602c101ab380581b164973fb33"></a><!-- doxytag: member="dwc_otg_hcd_intr.c::handle_xfercomp_isoc_split_in" ref="a56eb0602c101ab380581b164973fb33" args="(dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)" -->
+static int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__intr_8c.html#a56eb0602c101ab380581b164973fb33">handle_xfercomp_isoc_split_in</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__hc.html">dwc_hc_t</a> *hc, <a class="el" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *hc_regs, <a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *qtd)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__intr_8c.html#e8bfcabff910322ef19eec9fc99fd097">handle_hc_xfercomp_intr</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__hc.html">dwc_hc_t</a> *hc, <a class="el" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *hc_regs, <a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *qtd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Handles a host channel Transfer Complete interrupt.  <a href="#e8bfcabff910322ef19eec9fc99fd097"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__intr_8c.html#e89fabf3023fa4f0279f312e5e9d4223">handle_hc_stall_intr</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__hc.html">dwc_hc_t</a> *hc, <a class="el" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *hc_regs, <a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *qtd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Handles a host channel STALL interrupt.  <a href="#e89fabf3023fa4f0279f312e5e9d4223"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="0640c3606be7a8700ea4813e590ebf43"></a><!-- doxytag: member="dwc_otg_hcd_intr.c::update_urb_state_xfer_intr" ref="0640c3606be7a8700ea4813e590ebf43" args="(dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_hcd_urb_t *urb, dwc_otg_qtd_t *qtd, dwc_otg_halt_status_e halt_status)" -->
+static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__intr_8c.html#0640c3606be7a8700ea4813e590ebf43">update_urb_state_xfer_intr</a> (<a class="el" href="structdwc__hc.html">dwc_hc_t</a> *hc, <a class="el" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *hc_regs, <a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *urb, <a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *qtd, dwc_otg_halt_status_e halt_status)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__intr_8c.html#19f718e1e8f7cded3bb7431008ee0309">handle_hc_nak_intr</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__hc.html">dwc_hc_t</a> *hc, <a class="el" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *hc_regs, <a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *qtd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Handles a host channel NAK interrupt.  <a href="#19f718e1e8f7cded3bb7431008ee0309"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__intr_8c.html#243b0fb4191e46127a6823c0b5e970bb">handle_hc_ack_intr</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__hc.html">dwc_hc_t</a> *hc, <a class="el" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *hc_regs, <a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *qtd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Handles a host channel ACK interrupt.  <a href="#243b0fb4191e46127a6823c0b5e970bb"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__intr_8c.html#5093a2b94c1d5cd1988eb93d9def298f">handle_hc_nyet_intr</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__hc.html">dwc_hc_t</a> *hc, <a class="el" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *hc_regs, <a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *qtd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Handles a host channel NYET interrupt.  <a href="#5093a2b94c1d5cd1988eb93d9def298f"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__intr_8c.html#ab5348f52aac4081a9c35d529c1fcd79">handle_hc_babble_intr</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__hc.html">dwc_hc_t</a> *hc, <a class="el" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *hc_regs, <a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *qtd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Handles a host channel babble interrupt.  <a href="#ab5348f52aac4081a9c35d529c1fcd79"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__intr_8c.html#1edf7eebc0475898518e18dc12c1b4b9">handle_hc_ahberr_intr</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__hc.html">dwc_hc_t</a> *hc, <a class="el" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *hc_regs, <a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *qtd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Handles a host channel AHB error interrupt.  <a href="#1edf7eebc0475898518e18dc12c1b4b9"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__intr_8c.html#464af1671bd416d5db48a51fc93366ee">handle_hc_xacterr_intr</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__hc.html">dwc_hc_t</a> *hc, <a class="el" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *hc_regs, <a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *qtd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Handles a host channel transaction error interrupt.  <a href="#464af1671bd416d5db48a51fc93366ee"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__intr_8c.html#a30d61b2809dccf609bcf83cc61c9d63">handle_hc_frmovrun_intr</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__hc.html">dwc_hc_t</a> *hc, <a class="el" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *hc_regs, <a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *qtd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Handles a host channel frame overrun interrupt.  <a href="#a30d61b2809dccf609bcf83cc61c9d63"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__intr_8c.html#f73e70f0e622267b6281e0cd6c1d89cf">handle_hc_datatglerr_intr</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__hc.html">dwc_hc_t</a> *hc, <a class="el" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *hc_regs, <a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *qtd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Handles a host channel data toggle error interrupt.  <a href="#f73e70f0e622267b6281e0cd6c1d89cf"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__intr_8c.html#d75ed153a90dbda39d4d8e6cde4358df">handle_hc_chhltd_intr_dma</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__hc.html">dwc_hc_t</a> *hc, <a class="el" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *hc_regs, <a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *qtd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Handles a host Channel Halted interrupt in DMA mode.  <a href="#d75ed153a90dbda39d4d8e6cde4358df"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__intr_8c.html#83541cd20d3297d7d7d24052834ef019">handle_hc_chhltd_intr</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__hc.html">dwc_hc_t</a> *hc, <a class="el" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *hc_regs, <a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *qtd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Handles a host channel Channel Halted interrupt.  <a href="#83541cd20d3297d7d7d24052834ef019"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="019c9cc38ec85275a7ef0b0d38bf53ab"></a><!-- doxytag: member="dwc_otg_hcd_intr.c::dwc_otg_hcd_handle_hc_n_intr" ref="019c9cc38ec85275a7ef0b0d38bf53ab" args="(dwc_otg_hcd_t *dwc_otg_hcd, uint32_t num)" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__intr_8c.html#019c9cc38ec85275a7ef0b0d38bf53ab">dwc_otg_hcd_handle_hc_n_intr</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>, uint32_t num)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Handles interrupt for a specific Host Channel. <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This file contains the implementation of the HCD Interrupt handlers. 
+<p>
+
+<p>
+Definition in file <a class="el" href="dwc__otg__hcd__intr_8c-source.html">dwc_otg_hcd_intr.c</a>.<hr><h2>Function Documentation</h2>
+<a class="anchor" name="b9dde24773f2741b9ff67e2d46760dc0"></a><!-- doxytag: member="dwc_otg_hcd_intr.c::dwc_otg_hcd_handle_intr" ref="b9dde24773f2741b9ff67e2d46760dc0" args="(dwc_otg_hcd_t *dwc_otg_hcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t dwc_otg_hcd_handle_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>dwc_otg_hcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function should be called on every hardware interrupt. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd</a></em>&nbsp;</td><td>The HCD</td></tr>
+  </table>
+</dl>
+Returns non zero if interrupt is handled Return 0 if interrupt is not handled 
+<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000016">Todo:</a></b></dt><dd>Implement i2cintr handler. </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__intr_8c-source.html#l00043">43</a> of file <a class="el" href="dwc__otg__hcd__intr_8c-source.html">dwc_otg_hcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="bbf5740390826d69bba80651ef9bd725"></a><!-- doxytag: member="dwc_otg_hcd_intr.c::dwc_otg_hcd_handle_sof_intr" ref="bbf5740390826d69bba80651ef9bd725" args="(dwc_otg_hcd_t *hcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t dwc_otg_hcd_handle_sof_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Handles the start-of-frame interrupt in host mode. 
+<p>
+Non-periodic transactions may be queued to the DWC_otg controller for the current (micro)frame. Periodic transactions may be queued to the controller for the next (micro)frame. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__intr_8c-source.html#l00169">169</a> of file <a class="el" href="dwc__otg__hcd__intr_8c-source.html">dwc_otg_hcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="9d979e33e04fc694a72242dec63aeb89"></a><!-- doxytag: member="dwc_otg_hcd_intr.c::dwc_otg_hcd_handle_rx_status_q_level_intr" ref="9d979e33e04fc694a72242dec63aeb89" args="(dwc_otg_hcd_t *dwc_otg_hcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t dwc_otg_hcd_handle_rx_status_q_level_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>dwc_otg_hcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Handles the Rx Status Queue Level Interrupt, which indicates that there is at least one packet in the Rx FIFO. 
+<p>
+The packets are moved from the FIFO to memory if the DWC_otg controller is operating in Slave mode. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__intr_8c-source.html#l00222">222</a> of file <a class="el" href="dwc__otg__hcd__intr_8c-source.html">dwc_otg_hcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="51c953aefbc2382adee9f585fdb26f35"></a><!-- doxytag: member="dwc_otg_hcd_intr.c::dwc_otg_hcd_handle_np_tx_fifo_empty_intr" ref="51c953aefbc2382adee9f585fdb26f35" args="(dwc_otg_hcd_t *dwc_otg_hcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>dwc_otg_hcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This interrupt occurs when the non-periodic Tx FIFO is half-empty. 
+<p>
+More data packets may be written to the FIFO for OUT transfers. More requests may be written to the non-periodic request queue for IN transfers. This interrupt is enabled only in Slave mode. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__intr_8c-source.html#l00271">271</a> of file <a class="el" href="dwc__otg__hcd__intr_8c-source.html">dwc_otg_hcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="dcfa21f80c7732df9aaf3db59a86eb1d"></a><!-- doxytag: member="dwc_otg_hcd_intr.c::dwc_otg_hcd_handle_perio_tx_fifo_empty_intr" ref="dcfa21f80c7732df9aaf3db59a86eb1d" args="(dwc_otg_hcd_t *dwc_otg_hcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>dwc_otg_hcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This interrupt occurs when the periodic Tx FIFO is half-empty. 
+<p>
+More data packets may be written to the FIFO for OUT transfers. More requests may be written to the periodic request queue for IN transfers. This interrupt is enabled only in Slave mode. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__intr_8c-source.html#l00283">283</a> of file <a class="el" href="dwc__otg__hcd__intr_8c-source.html">dwc_otg_hcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="18bb807c86935a45f5fe5940e5ded70c"></a><!-- doxytag: member="dwc_otg_hcd_intr.c::dwc_otg_hcd_handle_port_intr" ref="18bb807c86935a45f5fe5940e5ded70c" args="(dwc_otg_hcd_t *dwc_otg_hcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t dwc_otg_hcd_handle_port_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>dwc_otg_hcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+There are multiple conditions that can cause a port interrupt. 
+<p>
+This function determines which interrupt conditions have occurred and handles them appropriately. 
+<p>
+Overcurrent Change Interrupt 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__intr_8c-source.html#l00294">294</a> of file <a class="el" href="dwc__otg__hcd__intr_8c-source.html">dwc_otg_hcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="1f28e296c0bc4146da309385d95b5d7e"></a><!-- doxytag: member="dwc_otg_hcd_intr.c::dwc_otg_hcd_handle_hc_intr" ref="1f28e296c0bc4146da309385d95b5d7e" args="(dwc_otg_hcd_t *dwc_otg_hcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t dwc_otg_hcd_handle_hc_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>dwc_otg_hcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This interrupt indicates that one or more host channels has a pending interrupt. 
+<p>
+There are multiple conditions that can cause each host channel interrupt. This function determines which conditions have occurred for each host channel interrupt and handles them appropriately. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__intr_8c-source.html#l00453">453</a> of file <a class="el" href="dwc__otg__hcd__intr_8c-source.html">dwc_otg_hcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="6cdb134cbb3cdf3501ca39761137baf0"></a><!-- doxytag: member="dwc_otg_hcd_intr.c::get_actual_xfer_length" ref="6cdb134cbb3cdf3501ca39761137baf0" args="(dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd, dwc_otg_halt_status_e halt_status, int *short_read)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static uint32_t get_actual_xfer_length           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__hc.html">dwc_hc_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc_regs</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>qtd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">dwc_otg_halt_status_e&nbsp;</td>
+          <td class="paramname"> <em>halt_status</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int *&nbsp;</td>
+          <td class="paramname"> <em>short_read</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Gets the actual length of a transfer after the transfer halts. 
+<p>
+_halt_status holds the reason for the halt.<p>
+For IN transfers where halt_status is DWC_OTG_HC_XFER_COMPLETE, *short_read is set to 1 upon return if less than the requested number of bytes were transferred. Otherwise, *short_read is set to 0 upon return. short_read may also be NULL on entry, in which case it remains unchanged. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__intr_8c-source.html#l00485">485</a> of file <a class="el" href="dwc__otg__hcd__intr_8c-source.html">dwc_otg_hcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="ecb30a961e8d4831e8691d45a77162e3"></a><!-- doxytag: member="dwc_otg_hcd_intr.c::update_urb_state_xfer_comp" ref="ecb30a961e8d4831e8691d45a77162e3" args="(dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_hcd_urb_t *urb, dwc_otg_qtd_t *qtd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static int update_urb_state_xfer_comp           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__hc.html">dwc_hc_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc_regs</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>urb</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>qtd</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Updates the state of the URB after a Transfer Complete interrupt on the host channel. 
+<p>
+Updates the actual_length field of the URB based on the number of bytes transferred via the host channel. Sets the URB status if the data transfer is finished.<p>
+<dl compact><dt><b>Returns:</b></dt><dd>1 if the data transfer specified by the URB is completely finished, 0 otherwise. </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__intr_8c-source.html#l00536">536</a> of file <a class="el" href="dwc__otg__hcd__intr_8c-source.html">dwc_otg_hcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="e93d54bdf873c5a31882660c2984458e"></a><!-- doxytag: member="dwc_otg_hcd_intr.c::update_isoc_urb_state" ref="e93d54bdf873c5a31882660c2984458e" args="(dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd, dwc_otg_halt_status_e halt_status)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static dwc_otg_halt_status_e update_isoc_urb_state           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__hc.html">dwc_hc_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc_regs</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>qtd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">dwc_otg_halt_status_e&nbsp;</td>
+          <td class="paramname"> <em>halt_status</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Updates the state of an Isochronous URB when the transfer is stopped for any reason. 
+<p>
+The fields of the current entry in the frame descriptor array are set based on the transfer state and the input _halt_status. Completes the Isochronous URB if all the URB frames have been completed.<p>
+<dl compact><dt><b>Returns:</b></dt><dd>DWC_OTG_HC_XFER_COMPLETE if there are more frames remaining to be transferred in the URB. Otherwise return DWC_OTG_HC_XFER_URB_COMPLETE. </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__intr_8c-source.html#l00626">626</a> of file <a class="el" href="dwc__otg__hcd__intr_8c-source.html">dwc_otg_hcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="57e9a29ec2dc8cd8d119acade0ae4ff1"></a><!-- doxytag: member="dwc_otg_hcd_intr.c::deactivate_qh" ref="57e9a29ec2dc8cd8d119acade0ae4ff1" args="(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, int free_qtd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static void deactivate_qh           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>qh</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>free_qtd</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Frees the first QTD in the QH's list if free_qtd is 1. 
+<p>
+For non-periodic QHs, removes the QH from the active non-periodic schedule. If any QTDs are still linked to the QH, the QH is added to the end of the inactive non-periodic schedule. For periodic QHs, removes the QH from the periodic schedule if no more QTDs are linked to the QH. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__intr_8c-source.html#l00706">706</a> of file <a class="el" href="dwc__otg__hcd__intr_8c-source.html">dwc_otg_hcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="4f6bf01b14a03eeed81d27bffa5e99fc"></a><!-- doxytag: member="dwc_otg_hcd_intr.c::release_channel" ref="4f6bf01b14a03eeed81d27bffa5e99fc" args="(dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_qtd_t *qtd, dwc_otg_halt_status_e halt_status)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static void release_channel           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__hc.html">dwc_hc_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>qtd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">dwc_otg_halt_status_e&nbsp;</td>
+          <td class="paramname"> <em>halt_status</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Releases a host channel for use by other transfers. 
+<p>
+Attempts to select and queue more transactions since at least one host channel is available.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD state structure. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>hc</em>&nbsp;</td><td>The host channel to release. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>qtd</em>&nbsp;</td><td>The QTD associated with the host channel. This QTD may be freed if the transfer is complete or an error has occurred. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>halt_status</em>&nbsp;</td><td>Reason the channel is being released. This status determines the actions taken by this function. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__intr_8c-source.html#l00742">742</a> of file <a class="el" href="dwc__otg__hcd__intr_8c-source.html">dwc_otg_hcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="8b774e79e18861e9ad3ab1d0de00d47c"></a><!-- doxytag: member="dwc_otg_hcd_intr.c::halt_channel" ref="8b774e79e18861e9ad3ab1d0de00d47c" args="(dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_qtd_t *qtd, dwc_otg_halt_status_e halt_status)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static void halt_channel           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__hc.html">dwc_hc_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>qtd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">dwc_otg_halt_status_e&nbsp;</td>
+          <td class="paramname"> <em>halt_status</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Halts a host channel. 
+<p>
+If the channel cannot be halted immediately because the request queue is full, this function ensures that the FIFO empty interrupt for the appropriate queue is enabled so that the halt request can be queued when there is space in the request queue.<p>
+This function may also be called in DMA mode. In that case, the channel is simply released since the core always halts the channel automatically in DMA mode. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__intr_8c-source.html#l00833">833</a> of file <a class="el" href="dwc__otg__hcd__intr_8c-source.html">dwc_otg_hcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="2fa47944efef508dddcab00b0050ef0a"></a><!-- doxytag: member="dwc_otg_hcd_intr.c::complete_non_periodic_xfer" ref="2fa47944efef508dddcab00b0050ef0a" args="(dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd, dwc_otg_halt_status_e halt_status)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static void complete_non_periodic_xfer           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__hc.html">dwc_hc_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc_regs</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>qtd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">dwc_otg_halt_status_e&nbsp;</td>
+          <td class="paramname"> <em>halt_status</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Performs common cleanup for non-periodic transfers after a Transfer Complete interrupt. 
+<p>
+This function should be called after any endpoint type specific handling is finished to release the host channel. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__intr_8c-source.html#l00885">885</a> of file <a class="el" href="dwc__otg__hcd__intr_8c-source.html">dwc_otg_hcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="a0fa0d4fa5f0af15860d685bb8fe3e50"></a><!-- doxytag: member="dwc_otg_hcd_intr.c::complete_periodic_xfer" ref="a0fa0d4fa5f0af15860d685bb8fe3e50" args="(dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd, dwc_otg_halt_status_e halt_status)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static void complete_periodic_xfer           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__hc.html">dwc_hc_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc_regs</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>qtd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">dwc_otg_halt_status_e&nbsp;</td>
+          <td class="paramname"> <em>halt_status</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Performs common cleanup for periodic transfers after a Transfer Complete interrupt. 
+<p>
+This function should be called after any endpoint type specific handling is finished to release the host channel. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__intr_8c-source.html#l00937">937</a> of file <a class="el" href="dwc__otg__hcd__intr_8c-source.html">dwc_otg_hcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="e8bfcabff910322ef19eec9fc99fd097"></a><!-- doxytag: member="dwc_otg_hcd_intr.c::handle_hc_xfercomp_intr" ref="e8bfcabff910322ef19eec9fc99fd097" args="(dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static int32_t handle_hc_xfercomp_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__hc.html">dwc_hc_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc_regs</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>qtd</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Handles a host channel Transfer Complete interrupt. 
+<p>
+This handler may be called in either DMA mode or Slave mode. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__intr_8c-source.html#l01002">1002</a> of file <a class="el" href="dwc__otg__hcd__intr_8c-source.html">dwc_otg_hcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="e89fabf3023fa4f0279f312e5e9d4223"></a><!-- doxytag: member="dwc_otg_hcd_intr.c::handle_hc_stall_intr" ref="e89fabf3023fa4f0279f312e5e9d4223" args="(dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static int32_t handle_hc_stall_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__hc.html">dwc_hc_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc_regs</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>qtd</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Handles a host channel STALL interrupt. 
+<p>
+This handler may be called in either DMA mode or Slave mode. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__intr_8c-source.html#l01128">1128</a> of file <a class="el" href="dwc__otg__hcd__intr_8c-source.html">dwc_otg_hcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="19f718e1e8f7cded3bb7431008ee0309"></a><!-- doxytag: member="dwc_otg_hcd_intr.c::handle_hc_nak_intr" ref="19f718e1e8f7cded3bb7431008ee0309" args="(dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static int32_t handle_hc_nak_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__hc.html">dwc_hc_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc_regs</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>qtd</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Handles a host channel NAK interrupt. 
+<p>
+This handler may be called in either DMA mode or Slave mode. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__intr_8c-source.html#l01214">1214</a> of file <a class="el" href="dwc__otg__hcd__intr_8c-source.html">dwc_otg_hcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="243b0fb4191e46127a6823c0b5e970bb"></a><!-- doxytag: member="dwc_otg_hcd_intr.c::handle_hc_ack_intr" ref="243b0fb4191e46127a6823c0b5e970bb" args="(dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static int32_t handle_hc_ack_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__hc.html">dwc_hc_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc_regs</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>qtd</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Handles a host channel ACK interrupt. 
+<p>
+This interrupt is enabled when performing the PING protocol in Slave mode, when errors occur during either Slave mode or DMA mode, and during Start Split transactions. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__intr_8c-source.html#l01294">1294</a> of file <a class="el" href="dwc__otg__hcd__intr_8c-source.html">dwc_otg_hcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="5093a2b94c1d5cd1988eb93d9def298f"></a><!-- doxytag: member="dwc_otg_hcd_intr.c::handle_hc_nyet_intr" ref="5093a2b94c1d5cd1988eb93d9def298f" args="(dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static int32_t handle_hc_nyet_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__hc.html">dwc_hc_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc_regs</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>qtd</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Handles a host channel NYET interrupt. 
+<p>
+This interrupt should only occur on Bulk and Control OUT endpoints and for complete split transactions. If a NYET occurs at the same time as a Transfer Complete interrupt, it is handled in the xfercomp interrupt handler, not here. This handler may be called in either DMA mode or Slave mode. 
+<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000017">Todo:</a></b></dt><dd>add support for isoc release </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__intr_8c-source.html#l01388">1388</a> of file <a class="el" href="dwc__otg__hcd__intr_8c-source.html">dwc_otg_hcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="ab5348f52aac4081a9c35d529c1fcd79"></a><!-- doxytag: member="dwc_otg_hcd_intr.c::handle_hc_babble_intr" ref="ab5348f52aac4081a9c35d529c1fcd79" args="(dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static int32_t handle_hc_babble_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__hc.html">dwc_hc_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc_regs</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>qtd</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Handles a host channel babble interrupt. 
+<p>
+This handler may be called in either DMA mode or Slave mode. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__intr_8c-source.html#l01466">1466</a> of file <a class="el" href="dwc__otg__hcd__intr_8c-source.html">dwc_otg_hcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="1edf7eebc0475898518e18dc12c1b4b9"></a><!-- doxytag: member="dwc_otg_hcd_intr.c::handle_hc_ahberr_intr" ref="1edf7eebc0475898518e18dc12c1b4b9" args="(dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static int32_t handle_hc_ahberr_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__hc.html">dwc_hc_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc_regs</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>qtd</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Handles a host channel AHB error interrupt. 
+<p>
+This handler is only called in DMA mode. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__intr_8c-source.html#l01499">1499</a> of file <a class="el" href="dwc__otg__hcd__intr_8c-source.html">dwc_otg_hcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="464af1671bd416d5db48a51fc93366ee"></a><!-- doxytag: member="dwc_otg_hcd_intr.c::handle_hc_xacterr_intr" ref="464af1671bd416d5db48a51fc93366ee" args="(dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static int32_t handle_hc_xacterr_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__hc.html">dwc_hc_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc_regs</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>qtd</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Handles a host channel transaction error interrupt. 
+<p>
+This handler may be called in either DMA mode or Slave mode. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__intr_8c-source.html#l01599">1599</a> of file <a class="el" href="dwc__otg__hcd__intr_8c-source.html">dwc_otg_hcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="a30d61b2809dccf609bcf83cc61c9d63"></a><!-- doxytag: member="dwc_otg_hcd_intr.c::handle_hc_frmovrun_intr" ref="a30d61b2809dccf609bcf83cc61c9d63" args="(dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static int32_t handle_hc_frmovrun_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__hc.html">dwc_hc_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc_regs</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>qtd</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Handles a host channel frame overrun interrupt. 
+<p>
+This handler may be called in either DMA mode or Slave mode. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__intr_8c-source.html#l01661">1661</a> of file <a class="el" href="dwc__otg__hcd__intr_8c-source.html">dwc_otg_hcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="f73e70f0e622267b6281e0cd6c1d89cf"></a><!-- doxytag: member="dwc_otg_hcd_intr.c::handle_hc_datatglerr_intr" ref="f73e70f0e622267b6281e0cd6c1d89cf" args="(dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static int32_t handle_hc_datatglerr_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__hc.html">dwc_hc_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc_regs</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>qtd</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Handles a host channel data toggle error interrupt. 
+<p>
+This handler may be called in either DMA mode or Slave mode. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__intr_8c-source.html#l01697">1697</a> of file <a class="el" href="dwc__otg__hcd__intr_8c-source.html">dwc_otg_hcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="d75ed153a90dbda39d4d8e6cde4358df"></a><!-- doxytag: member="dwc_otg_hcd_intr.c::handle_hc_chhltd_intr_dma" ref="d75ed153a90dbda39d4d8e6cde4358df" args="(dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static void handle_hc_chhltd_intr_dma           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__hc.html">dwc_hc_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc_regs</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>qtd</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Handles a host Channel Halted interrupt in DMA mode. 
+<p>
+This handler determines the reason the channel halted and proceeds accordingly. 
+<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000018">Todo:</a></b></dt><dd>This is here because of a possible hardware bug. Spec says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT interrupt w/ACK bit set should occur, but I only see the XFERCOMP bit, even with it masked out. This is a workaround for that behavior. Should fix this when hardware is fixed. </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__intr_8c-source.html#l01784">1784</a> of file <a class="el" href="dwc__otg__hcd__intr_8c-source.html">dwc_otg_hcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="83541cd20d3297d7d7d24052834ef019"></a><!-- doxytag: member="dwc_otg_hcd_intr.c::handle_hc_chhltd_intr" ref="83541cd20d3297d7d7d24052834ef019" args="(dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static int32_t handle_hc_chhltd_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__hc.html">dwc_hc_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hc_regs</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>qtd</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Handles a host channel Channel Halted interrupt. 
+<p>
+In slave mode, this handler is called only when the driver specifically requests a halt. This occurs during handling other host channel interrupts (e.g. nak, xacterr, stall, nyet, etc.).<p>
+In DMA mode, this is the interrupt that occurs when the core has finished processing a transfer on a channel. Other host channel interrupts (except ahberr) are disabled in DMA mode. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__intr_8c-source.html#l01928">1928</a> of file <a class="el" href="dwc__otg__hcd__intr_8c-source.html">dwc_otg_hcd_intr.c</a>.
+</div>
+</div><p>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__linux_8c-source.html b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__linux_8c-source.html
new file mode 100644
index 000000000000..cf20761d82b6
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__linux_8c-source.html
@@ -0,0 +1,726 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd_linux.c Source File</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<h1>dwc_otg_hcd_linux.c</h1><a href="dwc__otg__hcd__linux_8c.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">/* ==========================================================================</span>
+<a name="l00002"></a>00002 <span class="comment"> * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_linux.c $</span>
+<a name="l00003"></a>00003 <span class="comment"> * $Revision: #11 $</span>
+<a name="l00004"></a>00004 <span class="comment"> * $Date: 2009/04/21 $</span>
+<a name="l00005"></a>00005 <span class="comment"> * $Change: 1237476 $</span>
+<a name="l00006"></a>00006 <span class="comment"> *</span>
+<a name="l00007"></a>00007 <span class="comment"> * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,</span>
+<a name="l00008"></a>00008 <span class="comment"> * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless</span>
+<a name="l00009"></a>00009 <span class="comment"> * otherwise expressly agreed to in writing between Synopsys and you.</span>
+<a name="l00010"></a>00010 <span class="comment"> *</span>
+<a name="l00011"></a>00011 <span class="comment"> * The Software IS NOT an item of Licensed Software or Licensed Product under</span>
+<a name="l00012"></a>00012 <span class="comment"> * any End User Software License Agreement or Agreement for Licensed Product</span>
+<a name="l00013"></a>00013 <span class="comment"> * with Synopsys or any supplement thereto. You are permitted to use and</span>
+<a name="l00014"></a>00014 <span class="comment"> * redistribute this Software in source and binary forms, with or without</span>
+<a name="l00015"></a>00015 <span class="comment"> * modification, provided that redistributions of source code must retain this</span>
+<a name="l00016"></a>00016 <span class="comment"> * notice. You may not view, use, disclose, copy or distribute this file or</span>
+<a name="l00017"></a>00017 <span class="comment"> * any information contained herein except pursuant to this license grant from</span>
+<a name="l00018"></a>00018 <span class="comment"> * Synopsys. If you do not agree with this notice, including the disclaimer</span>
+<a name="l00019"></a>00019 <span class="comment"> * below, then you are not authorized to use the Software.</span>
+<a name="l00020"></a>00020 <span class="comment"> *</span>
+<a name="l00021"></a>00021 <span class="comment"> * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS</span>
+<a name="l00022"></a>00022 <span class="comment"> * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE</span>
+<a name="l00023"></a>00023 <span class="comment"> * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE</span>
+<a name="l00024"></a>00024 <span class="comment"> * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,</span>
+<a name="l00025"></a>00025 <span class="comment"> * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES</span>
+<a name="l00026"></a>00026 <span class="comment"> * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR</span>
+<a name="l00027"></a>00027 <span class="comment"> * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER</span>
+<a name="l00028"></a>00028 <span class="comment"> * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT</span>
+<a name="l00029"></a>00029 <span class="comment"> * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY</span>
+<a name="l00030"></a>00030 <span class="comment"> * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH</span>
+<a name="l00031"></a>00031 <span class="comment"> * DAMAGE.</span>
+<a name="l00032"></a>00032 <span class="comment"> * ========================================================================== */</span>
+<a name="l00033"></a>00033 <span class="preprocessor">#ifndef DWC_DEVICE_ONLY</span>
+<a name="l00034"></a>00034 <span class="preprocessor"></span>
+<a name="l00041"></a>00041 <span class="preprocessor">#include &lt;linux/kernel.h&gt;</span>
+<a name="l00042"></a>00042 <span class="preprocessor">#include &lt;linux/module.h&gt;</span>
+<a name="l00043"></a>00043 <span class="preprocessor">#include &lt;linux/moduleparam.h&gt;</span>
+<a name="l00044"></a>00044 <span class="preprocessor">#include &lt;linux/init.h&gt;</span>
+<a name="l00045"></a>00045 <span class="preprocessor">#include &lt;linux/device.h&gt;</span>
+<a name="l00046"></a>00046 <span class="preprocessor">#include &lt;linux/errno.h&gt;</span>
+<a name="l00047"></a>00047 <span class="preprocessor">#include &lt;linux/list.h&gt;</span>
+<a name="l00048"></a>00048 <span class="preprocessor">#include &lt;linux/interrupt.h&gt;</span>
+<a name="l00049"></a>00049 <span class="preprocessor">#include &lt;linux/string.h&gt;</span>
+<a name="l00050"></a>00050 <span class="preprocessor">#include &lt;linux/dma-mapping.h&gt;</span>
+<a name="l00051"></a>00051 <span class="preprocessor">#include &lt;linux/version.h&gt;</span>
+<a name="l00052"></a>00052 <span class="preprocessor">#include &lt;asm/io.h&gt;</span>
+<a name="l00053"></a>00053 
+<a name="l00054"></a>00054 <span class="preprocessor">#ifdef LM_INTERFACE</span>
+<a name="l00055"></a>00055 <span class="preprocessor"></span><span class="preprocessor">#include &lt;asm/arch/regs-irq.h&gt;</span>
+<a name="l00056"></a>00056 <span class="preprocessor">#include &lt;asm/arch/lm.h&gt;</span>
+<a name="l00057"></a>00057 <span class="preprocessor">#include &lt;asm/arch/irqs.h&gt;</span>
+<a name="l00058"></a>00058 <span class="preprocessor">#endif</span>
+<a name="l00059"></a>00059 <span class="preprocessor"></span>
+<a name="l00060"></a>00060 <span class="preprocessor">#include &lt;linux/usb.h&gt;</span>
+<a name="l00061"></a>00061 <span class="preprocessor">#include &lt;../drivers/usb/core/hcd.h&gt;</span>
+<a name="l00062"></a>00062 
+<a name="l00063"></a>00063 <span class="preprocessor">#include "<a class="code" href="dwc__otg__hcd__if_8h.html">dwc_otg_hcd_if.h</a>"</span>
+<a name="l00064"></a>00064 <span class="preprocessor">#include "<a class="code" href="dwc__otg__dbg_8h.html">dwc_otg_dbg.h</a>"</span>
+<a name="l00065"></a>00065 <span class="preprocessor">#include "<a class="code" href="dwc__otg__driver_8h.html">dwc_otg_driver.h</a>"</span>
+<a name="l00066"></a>00066 
+<a name="l00071"></a><a class="code" href="dwc__otg__hcd__linux_8c.html#4a327046464cd55f8abafc4af8ef74aa">00071</a> <span class="preprocessor">#define dwc_ep_addr_to_endpoint(_bEndpointAddress_) ((_bEndpointAddress_ &amp; USB_ENDPOINT_NUMBER_MASK) | \</span>
+<a name="l00072"></a>00072 <span class="preprocessor">                                                     ((_bEndpointAddress_ &amp; USB_DIR_IN) != 0) &lt;&lt; 4)</span>
+<a name="l00073"></a>00073 <span class="preprocessor"></span>
+<a name="l00074"></a><a class="code" href="dwc__otg__hcd__linux_8c.html#41b49c86957a3835934c2f26fee377df">00074</a> <span class="keyword">static</span> <span class="keyword">const</span> <span class="keywordtype">char</span> <a class="code" href="dwc__otg__hcd__linux_8c.html#41b49c86957a3835934c2f26fee377df">dwc_otg_hcd_name</a>[] = <span class="stringliteral">"dwc_otg_hcd"</span>;
+<a name="l00075"></a>00075 
+<a name="l00078"></a>00078 <span class="keyword">static</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd__linux_8c.html#d9e9c76f2bc1c4f662d132c710a95a60">urb_enqueue</a>(<span class="keyword">struct</span> usb_hcd *hcd,
+<a name="l00079"></a>00079                        <span class="keyword">struct</span> usb_host_endpoint *ep,
+<a name="l00080"></a>00080                        <span class="keyword">struct</span> urb *urb, gfp_t mem_flags);
+<a name="l00081"></a>00081 
+<a name="l00082"></a>00082 <span class="keyword">static</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd__linux_8c.html#afc1f3d92fd7596140c0068bc96034f7">urb_dequeue</a>(<span class="keyword">struct</span> usb_hcd *hcd, <span class="keyword">struct</span> urb *urb);
+<a name="l00083"></a>00083 
+<a name="l00084"></a>00084 <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd__linux_8c.html#0aefc084c4c334dac85c95a43e8942c6">endpoint_disable</a>(<span class="keyword">struct</span> usb_hcd *hcd, <span class="keyword">struct</span> usb_host_endpoint *ep);
+<a name="l00085"></a>00085 
+<a name="l00086"></a>00086 <span class="keyword">static</span> irqreturn_t <a class="code" href="dwc__otg__hcd__linux_8c.html#1e911926e9d51d6d9d11f11b81da8c3d">dwc_otg_hcd_irq</a>(<span class="keyword">struct</span> usb_hcd *hcd);
+<a name="l00087"></a>00087 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil__intr_8c.html#fc2d933cd662b3d060747004c79203a1">hcd_start</a>(<span class="keyword">struct</span> usb_hcd *hcd);
+<a name="l00088"></a>00088 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil__intr_8c.html#b2721d01cc389181470095955b4e0994">hcd_stop</a>(<span class="keyword">struct</span> usb_hcd *hcd);
+<a name="l00089"></a>00089 <span class="keyword">static</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd__linux_8c.html#c78128edb8902dc96534c5bb253f99a3">get_frame_number</a>(<span class="keyword">struct</span> usb_hcd *hcd);
+<a name="l00090"></a>00090 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd__linux_8c.html#108442f4aa4dc4663d8659241ed04e9c">hub_status_data</a>(<span class="keyword">struct</span> usb_hcd *hcd, <span class="keywordtype">char</span> *buf);
+<a name="l00091"></a>00091 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd__linux_8c.html#55d196cab99083dabdacdee78dc5e339">hub_control</a>(<span class="keyword">struct</span> usb_hcd *hcd,
+<a name="l00092"></a>00092                        u16 typeReq,
+<a name="l00093"></a>00093                        u16 wValue, u16 wIndex, <span class="keywordtype">char</span> *buf, u16 wLength);
+<a name="l00094"></a>00094 
+<a name="l00095"></a><a class="code" href="structwrapper__priv__data.html">00095</a> <span class="keyword">struct </span><a class="code" href="structwrapper__priv__data.html">wrapper_priv_data</a> {
+<a name="l00096"></a><a class="code" href="structwrapper__priv__data.html#3a5cfdab2772597d857294972bb171c8">00096</a>         <a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>;
+<a name="l00097"></a>00097 };
+<a name="l00098"></a>00098 
+<a name="l00101"></a><a class="code" href="dwc__otg__hcd__linux_8c.html#ab1d492c360b963d179798f2641c02a5">00101</a> <span class="keyword">static</span> <span class="keyword">struct </span>hc_driver <a class="code" href="dwc__otg__hcd__linux_8c.html#ab1d492c360b963d179798f2641c02a5">dwc_otg_hc_driver</a> = {
+<a name="l00102"></a>00102 
+<a name="l00103"></a>00103         .description = <a class="code" href="dwc__otg__hcd__linux_8c.html#41b49c86957a3835934c2f26fee377df">dwc_otg_hcd_name</a>,
+<a name="l00104"></a>00104         .product_desc = <span class="stringliteral">"DWC OTG Controller"</span>,
+<a name="l00105"></a>00105         .hcd_priv_size = <span class="keyword">sizeof</span>(<span class="keyword">struct </span><a class="code" href="structwrapper__priv__data.html">wrapper_priv_data</a>),
+<a name="l00106"></a>00106 
+<a name="l00107"></a>00107         .irq = <a class="code" href="dwc__otg__hcd__linux_8c.html#1e911926e9d51d6d9d11f11b81da8c3d">dwc_otg_hcd_irq</a>,
+<a name="l00108"></a>00108 
+<a name="l00109"></a>00109         .flags = HCD_MEMORY | HCD_USB2,
+<a name="l00110"></a>00110 
+<a name="l00111"></a>00111         <span class="comment">//.reset =              </span>
+<a name="l00112"></a>00112         .start = <a class="code" href="dwc__otg__cil__intr_8c.html#fc2d933cd662b3d060747004c79203a1">hcd_start</a>,
+<a name="l00113"></a>00113         <span class="comment">//.suspend =            </span>
+<a name="l00114"></a>00114         <span class="comment">//.resume =             </span>
+<a name="l00115"></a>00115         .stop = <a class="code" href="dwc__otg__cil__intr_8c.html#b2721d01cc389181470095955b4e0994">hcd_stop</a>,
+<a name="l00116"></a>00116 
+<a name="l00117"></a>00117         .urb_enqueue = <a class="code" href="dwc__otg__hcd__linux_8c.html#d9e9c76f2bc1c4f662d132c710a95a60">urb_enqueue</a>,
+<a name="l00118"></a>00118         .urb_dequeue = <a class="code" href="dwc__otg__hcd__linux_8c.html#afc1f3d92fd7596140c0068bc96034f7">urb_dequeue</a>,
+<a name="l00119"></a>00119         .endpoint_disable = <a class="code" href="dwc__otg__hcd__linux_8c.html#0aefc084c4c334dac85c95a43e8942c6">endpoint_disable</a>,
+<a name="l00120"></a>00120 
+<a name="l00121"></a>00121         .get_frame_number = <a class="code" href="dwc__otg__hcd__linux_8c.html#c78128edb8902dc96534c5bb253f99a3">get_frame_number</a>,
+<a name="l00122"></a>00122 
+<a name="l00123"></a>00123         .hub_status_data = <a class="code" href="dwc__otg__hcd__linux_8c.html#108442f4aa4dc4663d8659241ed04e9c">hub_status_data</a>,
+<a name="l00124"></a>00124         .hub_control = <a class="code" href="dwc__otg__hcd__linux_8c.html#55d196cab99083dabdacdee78dc5e339">hub_control</a>,
+<a name="l00125"></a>00125         <span class="comment">//.bus_suspend =                </span>
+<a name="l00126"></a>00126         <span class="comment">//.bus_resume =         </span>
+<a name="l00127"></a>00127 };
+<a name="l00128"></a>00128 
+<a name="l00130"></a><a class="code" href="dwc__otg__hcd__linux_8c.html#bd8c86466ccd8ff8b94867d601e66116">00130</a> <span class="keyword">static</span> <span class="keyword">inline</span> <a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *<a class="code" href="dwc__otg__hcd__linux_8c.html#bd8c86466ccd8ff8b94867d601e66116">hcd_to_dwc_otg_hcd</a>(<span class="keyword">struct</span> usb_hcd *hcd)
+<a name="l00131"></a>00131 {
+<a name="l00132"></a>00132         <span class="keyword">struct </span><a class="code" href="structwrapper__priv__data.html">wrapper_priv_data</a> *p;
+<a name="l00133"></a>00133         p = (<span class="keyword">struct </span><a class="code" href="structwrapper__priv__data.html">wrapper_priv_data</a> *)(hcd-&gt;hcd_priv);
+<a name="l00134"></a>00134         <span class="keywordflow">return</span> p-&gt;<a class="code" href="structwrapper__priv__data.html#3a5cfdab2772597d857294972bb171c8">dwc_otg_hcd</a>;
+<a name="l00135"></a>00135 }
+<a name="l00136"></a>00136 
+<a name="l00138"></a><a class="code" href="dwc__otg__hcd__linux_8c.html#e314b37c9e03857c2cad95724982ad42">00138</a> <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keyword">struct </span>usb_hcd *<a class="code" href="dwc__otg__hcd__linux_8c.html#e314b37c9e03857c2cad95724982ad42">dwc_otg_hcd_to_hcd</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * <a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>)
+<a name="l00139"></a>00139 {
+<a name="l00140"></a>00140         <span class="keywordflow">return</span> <a class="code" href="dwc__otg__hcd_8c.html#7740268b2d0fd8d25aaaeacfa5aef5cf">dwc_otg_hcd_get_priv_data</a>(dwc_otg_hcd);
+<a name="l00141"></a>00141 }
+<a name="l00142"></a>00142 
+<a name="l00144"></a><a class="code" href="dwc__otg__hcd__linux_8c.html#99c594c1e3af2fa78b09c914cb334611">00144</a> <span class="keyword">inline</span> <span class="keyword">struct </span>usb_host_endpoint *<a class="code" href="dwc__otg__hcd__linux_8c.html#99c594c1e3af2fa78b09c914cb334611">dwc_urb_to_endpoint</a>(<span class="keyword">struct</span> urb *urb)
+<a name="l00145"></a>00145 {
+<a name="l00146"></a>00146         <span class="keyword">struct </span>usb_device *dev = urb-&gt;dev;
+<a name="l00147"></a>00147         <span class="keywordtype">int</span> ep_num = usb_pipeendpoint(urb-&gt;pipe);
+<a name="l00148"></a>00148 
+<a name="l00149"></a>00149         <span class="keywordflow">if</span> (usb_pipein(urb-&gt;pipe))
+<a name="l00150"></a>00150                 <span class="keywordflow">return</span> dev-&gt;ep_in[ep_num];
+<a name="l00151"></a>00151         <span class="keywordflow">else</span>
+<a name="l00152"></a>00152                 <span class="keywordflow">return</span> dev-&gt;ep_out[ep_num];
+<a name="l00153"></a>00153 }
+<a name="l00154"></a>00154 
+<a name="l00155"></a><a class="code" href="dwc__otg__hcd__linux_8c.html#8011f9b662a7f4182e762de616bbc95e">00155</a> <span class="keyword">static</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd__linux_8c.html#8011f9b662a7f4182e762de616bbc95e">_disconnect</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd)
+<a name="l00156"></a>00156 {
+<a name="l00157"></a>00157         <span class="keyword">struct </span>usb_hcd *usb_hcd = <a class="code" href="dwc__otg__hcd__linux_8c.html#e314b37c9e03857c2cad95724982ad42">dwc_otg_hcd_to_hcd</a>(hcd);
+<a name="l00158"></a>00158 
+<a name="l00159"></a>00159         usb_hcd-&gt;self.is_b_host = 0;
+<a name="l00160"></a>00160         <span class="keywordflow">return</span> 0;
+<a name="l00161"></a>00161 }
+<a name="l00162"></a>00162 
+<a name="l00163"></a><a class="code" href="dwc__otg__hcd__linux_8c.html#e11ebd665a86e6ec3fd661965acca90e">00163</a> <span class="keyword">static</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd__linux_8c.html#e11ebd665a86e6ec3fd661965acca90e">_start</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd)
+<a name="l00164"></a>00164 {
+<a name="l00165"></a>00165         <span class="keyword">struct </span>usb_hcd *usb_hcd = <a class="code" href="dwc__otg__hcd__linux_8c.html#e314b37c9e03857c2cad95724982ad42">dwc_otg_hcd_to_hcd</a>(hcd);
+<a name="l00166"></a>00166 
+<a name="l00167"></a>00167         usb_hcd-&gt;self.is_b_host = <a class="code" href="dwc__otg__hcd_8c.html#ca25b33b440a4ef112ee459c26c14adc">dwc_otg_hcd_is_b_host</a>(hcd);
+<a name="l00168"></a>00168         <a class="code" href="dwc__otg__cil__intr_8c.html#fc2d933cd662b3d060747004c79203a1">hcd_start</a>(usb_hcd);
+<a name="l00169"></a>00169 
+<a name="l00170"></a>00170         <span class="keywordflow">return</span> 0;
+<a name="l00171"></a>00171 }
+<a name="l00172"></a>00172 
+<a name="l00173"></a><a class="code" href="dwc__otg__hcd__linux_8c.html#f4fe5a6082e7cce809f3e2a4cb71a7e4">00173</a> <span class="keyword">static</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd__linux_8c.html#f4fe5a6082e7cce809f3e2a4cb71a7e4">_hub_info</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd, <span class="keywordtype">void</span> *urb_handle, uint32_t * hub_addr,
+<a name="l00174"></a>00174                      uint32_t * port_addr)
+<a name="l00175"></a>00175 {
+<a name="l00176"></a>00176         <span class="keyword">struct </span>urb *urb = (<span class="keyword">struct </span>urb *)urb_handle;
+<a name="l00177"></a>00177         <span class="keywordflow">if</span> (urb-&gt;dev-&gt;tt) {
+<a name="l00178"></a>00178                 *hub_addr = urb-&gt;dev-&gt;tt-&gt;hub-&gt;devnum;
+<a name="l00179"></a>00179         } <span class="keywordflow">else</span> {
+<a name="l00180"></a>00180                 *hub_addr = 0;
+<a name="l00181"></a>00181         }
+<a name="l00182"></a>00182         *port_addr = urb-&gt;dev-&gt;ttport;
+<a name="l00183"></a>00183         <span class="keywordflow">return</span> 0;
+<a name="l00184"></a>00184 }
+<a name="l00185"></a>00185 
+<a name="l00186"></a><a class="code" href="dwc__otg__hcd__linux_8c.html#22cff3e20b45ec02e81e54a1adacfa20">00186</a> <span class="keyword">static</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd__linux_8c.html#22cff3e20b45ec02e81e54a1adacfa20">_speed</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd, <span class="keywordtype">void</span> *urb_handle)
+<a name="l00187"></a>00187 {
+<a name="l00188"></a>00188         <span class="keyword">struct </span>urb *urb = (<span class="keyword">struct </span>urb *)urb_handle;
+<a name="l00189"></a>00189         <span class="keywordflow">return</span> urb-&gt;dev-&gt;speed;
+<a name="l00190"></a>00190 }
+<a name="l00191"></a>00191 
+<a name="l00192"></a><a class="code" href="dwc__otg__hcd__linux_8c.html#578b76a201e8e722e31afdcd2c35dac9">00192</a> <span class="keyword">static</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd__linux_8c.html#578b76a201e8e722e31afdcd2c35dac9">_get_b_hnp_enable</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd)
+<a name="l00193"></a>00193 {
+<a name="l00194"></a>00194         <span class="keyword">struct </span>usb_hcd *usb_hcd = <a class="code" href="dwc__otg__hcd__linux_8c.html#e314b37c9e03857c2cad95724982ad42">dwc_otg_hcd_to_hcd</a>(hcd);
+<a name="l00195"></a>00195         <span class="keywordflow">return</span> usb_hcd-&gt;self.b_hnp_enable;
+<a name="l00196"></a>00196 }
+<a name="l00197"></a>00197 
+<a name="l00198"></a><a class="code" href="dwc__otg__hcd__linux_8c.html#e270a6a091a674ccf6f390fdcf746b87">00198</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd__linux_8c.html#e270a6a091a674ccf6f390fdcf746b87">allocate_bus_bandwidth</a>(<span class="keyword">struct</span> usb_hcd *hcd, uint32_t bw,
+<a name="l00199"></a>00199                                    <span class="keyword">struct</span> urb *urb)
+<a name="l00200"></a>00200 {
+<a name="l00201"></a>00201         hcd_to_bus(hcd)-&gt;bandwidth_allocated += bw / urb-&gt;interval;
+<a name="l00202"></a>00202         <span class="keywordflow">if</span> (usb_pipetype(urb-&gt;pipe) == PIPE_ISOCHRONOUS) {
+<a name="l00203"></a>00203                 hcd_to_bus(hcd)-&gt;bandwidth_isoc_reqs++;
+<a name="l00204"></a>00204         } <span class="keywordflow">else</span> {
+<a name="l00205"></a>00205                 hcd_to_bus(hcd)-&gt;bandwidth_int_reqs++;
+<a name="l00206"></a>00206         }
+<a name="l00207"></a>00207 }
+<a name="l00208"></a>00208 
+<a name="l00209"></a><a class="code" href="dwc__otg__hcd__linux_8c.html#53fcd6fb7b833323112e8856070e88d8">00209</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd__linux_8c.html#53fcd6fb7b833323112e8856070e88d8">free_bus_bandwidth</a>(<span class="keyword">struct</span> usb_hcd *hcd, uint32_t bw,
+<a name="l00210"></a>00210                                <span class="keyword">struct</span> urb *urb)
+<a name="l00211"></a>00211 {
+<a name="l00212"></a>00212         hcd_to_bus(hcd)-&gt;bandwidth_allocated -= bw / urb-&gt;interval;
+<a name="l00213"></a>00213         <span class="keywordflow">if</span> (usb_pipetype(urb-&gt;pipe) == PIPE_ISOCHRONOUS) {
+<a name="l00214"></a>00214                 hcd_to_bus(hcd)-&gt;bandwidth_isoc_reqs--;
+<a name="l00215"></a>00215         } <span class="keywordflow">else</span> {
+<a name="l00216"></a>00216                 hcd_to_bus(hcd)-&gt;bandwidth_int_reqs--;
+<a name="l00217"></a>00217         }
+<a name="l00218"></a>00218 }
+<a name="l00219"></a>00219 
+<a name="l00224"></a><a class="code" href="dwc__otg__hcd__linux_8c.html#a0d18986574c384e98aa280e0475a9aa">00224</a> <span class="keyword">static</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd__linux_8c.html#a0d18986574c384e98aa280e0475a9aa">_complete</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd, <span class="keywordtype">void</span> *urb_handle,
+<a name="l00225"></a>00225                      <a class="code" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> * dwc_otg_urb, int32_t status)
+<a name="l00226"></a>00226 {
+<a name="l00227"></a>00227         <span class="keyword">struct </span>urb *urb = (<span class="keyword">struct </span>urb *)urb_handle;
+<a name="l00228"></a>00228 <span class="preprocessor">#ifdef DEBUG</span>
+<a name="l00229"></a>00229 <span class="preprocessor"></span>        <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__dbg_8h.html#7a96217c88a4d786f6cb3d4df09dee04">CHK_DEBUG_LEVEL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a> | <a class="code" href="dwc__otg__dbg_8h.html#737e22e02729647d12db8e3059ad06c9">DBG_HCD_URB</a>)) {
+<a name="l00230"></a>00230                 DWC_PRINTF(<span class="stringliteral">"%s: urb %p, device %d, ep %d %s, status=%d\n"</span>,
+<a name="l00231"></a>00231                            __func__, urb, usb_pipedevice(urb-&gt;pipe),
+<a name="l00232"></a>00232                            usb_pipeendpoint(urb-&gt;pipe),
+<a name="l00233"></a>00233                            usb_pipein(urb-&gt;pipe) ? <span class="stringliteral">"IN"</span> : <span class="stringliteral">"OUT"</span>, status);
+<a name="l00234"></a>00234                 <span class="keywordflow">if</span> (usb_pipetype(urb-&gt;pipe) == PIPE_ISOCHRONOUS) {
+<a name="l00235"></a>00235                         <span class="keywordtype">int</span> i;
+<a name="l00236"></a>00236                         <span class="keywordflow">for</span> (i = 0; i &lt; urb-&gt;number_of_packets; i++) {
+<a name="l00237"></a>00237                                 DWC_PRINTF(<span class="stringliteral">"  ISO Desc %d status: %d\n"</span>,
+<a name="l00238"></a>00238                                            i, urb-&gt;iso_frame_desc[i].status);
+<a name="l00239"></a>00239                         }
+<a name="l00240"></a>00240                 }
+<a name="l00241"></a>00241         }
+<a name="l00242"></a>00242 <span class="preprocessor">#endif</span>
+<a name="l00243"></a>00243 <span class="preprocessor"></span>
+<a name="l00244"></a>00244         urb-&gt;actual_length = <a class="code" href="dwc__otg__hcd_8c.html#3260f5db4ea20074da16b292eb1a686b">dwc_otg_hcd_urb_get_actual_length</a>(dwc_otg_urb);
+<a name="l00245"></a>00245         <span class="comment">/* Convert status value. */</span>
+<a name="l00246"></a>00246         <span class="keywordflow">switch</span> (status) {
+<a name="l00247"></a>00247         <span class="keywordflow">case</span> -DWC_E_PROTOCOL:
+<a name="l00248"></a>00248                 status = -EPROTO;
+<a name="l00249"></a>00249                 <span class="keywordflow">break</span>;
+<a name="l00250"></a>00250         <span class="keywordflow">case</span> -DWC_E_IN_PROGRESS:
+<a name="l00251"></a>00251                 status = -EINPROGRESS;
+<a name="l00252"></a>00252                 <span class="keywordflow">break</span>;
+<a name="l00253"></a>00253         <span class="keywordflow">case</span> -DWC_E_PIPE:
+<a name="l00254"></a>00254                 status = -EPIPE;
+<a name="l00255"></a>00255                 <span class="keywordflow">break</span>;
+<a name="l00256"></a>00256         <span class="keywordflow">case</span> -DWC_E_IO:
+<a name="l00257"></a>00257                 status = -EIO;
+<a name="l00258"></a>00258                 <span class="keywordflow">break</span>;
+<a name="l00259"></a>00259         <span class="keywordflow">case</span> -DWC_E_TIMEOUT:
+<a name="l00260"></a>00260                 status = -ETIMEDOUT;
+<a name="l00261"></a>00261                 <span class="keywordflow">break</span>;
+<a name="l00262"></a>00262         <span class="keywordflow">case</span> -DWC_E_OVERFLOW:
+<a name="l00263"></a>00263                 status = -EOVERFLOW;
+<a name="l00264"></a>00264                 <span class="keywordflow">break</span>;
+<a name="l00265"></a>00265         <span class="keywordflow">default</span>:
+<a name="l00266"></a>00266                 <span class="keywordflow">if</span> (status) {
+<a name="l00267"></a>00267                         DWC_PRINTF(<span class="stringliteral">"Uknown urb status %d\n"</span>, status);
+<a name="l00268"></a>00268 
+<a name="l00269"></a>00269                 }
+<a name="l00270"></a>00270         }
+<a name="l00271"></a>00271 
+<a name="l00272"></a>00272         <span class="keywordflow">if</span> (usb_pipetype(urb-&gt;pipe) == PIPE_ISOCHRONOUS) {
+<a name="l00273"></a>00273                 <span class="keywordtype">int</span> i;
+<a name="l00274"></a>00274 
+<a name="l00275"></a>00275                 urb-&gt;error_count = <a class="code" href="dwc__otg__hcd_8c.html#816cc30c3129fc8911a458355d977129">dwc_otg_hcd_urb_get_error_count</a>(dwc_otg_urb);
+<a name="l00276"></a>00276                 <span class="keywordflow">for</span> (i = 0; i &lt; urb-&gt;number_of_packets; ++i) {
+<a name="l00277"></a>00277                         urb-&gt;iso_frame_desc[i].actual_length =
+<a name="l00278"></a>00278                             <a class="code" href="dwc__otg__hcd_8c.html#c6d28fc3e6aedb29d46a793423c4de0a">dwc_otg_hcd_urb_get_iso_desc_actual_length</a>
+<a name="l00279"></a>00279                             (dwc_otg_urb, i);
+<a name="l00280"></a>00280                         urb-&gt;iso_frame_desc[i].status =
+<a name="l00281"></a>00281                             <a class="code" href="dwc__otg__hcd_8c.html#fde27182e452709e10c1100ea57aa46b">dwc_otg_hcd_urb_get_iso_desc_status</a>
+<a name="l00282"></a>00282                             (dwc_otg_urb, i);
+<a name="l00283"></a>00283                 }
+<a name="l00284"></a>00284         }
+<a name="l00285"></a>00285 
+<a name="l00286"></a>00286         urb-&gt;status = status;
+<a name="l00287"></a>00287         urb-&gt;hcpriv = NULL;
+<a name="l00288"></a>00288         <span class="keywordflow">if</span> (!status) {
+<a name="l00289"></a>00289                 <span class="keywordflow">if</span> ((urb-&gt;transfer_flags &amp; URB_SHORT_NOT_OK) &amp;&amp;
+<a name="l00290"></a>00290                     (urb-&gt;actual_length &lt; urb-&gt;transfer_buffer_length)) {
+<a name="l00291"></a>00291                         urb-&gt;status = -EREMOTEIO;
+<a name="l00292"></a>00292                 }
+<a name="l00293"></a>00293         }
+<a name="l00294"></a>00294 
+<a name="l00295"></a>00295         <span class="keywordflow">if</span> ((usb_pipetype(urb-&gt;pipe) == PIPE_ISOCHRONOUS) ||
+<a name="l00296"></a>00296             (usb_pipetype(urb-&gt;pipe) == PIPE_INTERRUPT)) {
+<a name="l00297"></a>00297                 <span class="keyword">struct </span>usb_host_endpoint *ep = <a class="code" href="dwc__otg__hcd__linux_8c.html#99c594c1e3af2fa78b09c914cb334611">dwc_urb_to_endpoint</a>(urb);
+<a name="l00298"></a>00298                 <span class="keywordflow">if</span> (ep) {
+<a name="l00299"></a>00299                         <a class="code" href="dwc__otg__hcd__linux_8c.html#53fcd6fb7b833323112e8856070e88d8">free_bus_bandwidth</a>(<a class="code" href="dwc__otg__hcd__linux_8c.html#e314b37c9e03857c2cad95724982ad42">dwc_otg_hcd_to_hcd</a>(hcd),
+<a name="l00300"></a>00300                                            <a class="code" href="dwc__otg__hcd_8c.html#bd160be911ccc8f90141dae9c40276eb">dwc_otg_hcd_get_ep_bandwidth</a>(hcd,
+<a name="l00301"></a>00301                                                                         ep-&gt;
+<a name="l00302"></a>00302                                                                         hcpriv),
+<a name="l00303"></a>00303                                            urb);
+<a name="l00304"></a>00304                 }
+<a name="l00305"></a>00305         }
+<a name="l00306"></a>00306 
+<a name="l00307"></a>00307         dwc_free(dwc_otg_urb);
+<a name="l00308"></a>00308         usb_hcd_giveback_urb(<a class="code" href="dwc__otg__hcd__linux_8c.html#e314b37c9e03857c2cad95724982ad42">dwc_otg_hcd_to_hcd</a>(hcd), urb);
+<a name="l00309"></a>00309         <span class="keywordflow">return</span> 0;
+<a name="l00310"></a>00310 }
+<a name="l00311"></a>00311 
+<a name="l00312"></a><a class="code" href="dwc__otg__hcd__linux_8c.html#430ee3db85940ea34a1702a37fbfb942">00312</a> <span class="keyword">static</span> <span class="keyword">struct </span><a class="code" href="structdwc__otg__hcd__function__ops.html">dwc_otg_hcd_function_ops</a> <a class="code" href="dwc__otg__hcd__linux_8c.html#430ee3db85940ea34a1702a37fbfb942">hcd_fops</a> = {
+<a name="l00313"></a>00313         .<a class="code" href="structdwc__otg__hcd__function__ops.html#d74a65269fe5712ac307bfd3230a29b4">start</a> = <a class="code" href="dwc__otg__hcd__linux_8c.html#e11ebd665a86e6ec3fd661965acca90e">_start</a>,
+<a name="l00314"></a>00314         .disconnect = <a class="code" href="dwc__otg__hcd__linux_8c.html#8011f9b662a7f4182e762de616bbc95e">_disconnect</a>,
+<a name="l00315"></a>00315         .hub_info = <a class="code" href="dwc__otg__hcd__linux_8c.html#f4fe5a6082e7cce809f3e2a4cb71a7e4">_hub_info</a>,
+<a name="l00316"></a>00316         .speed = <a class="code" href="dwc__otg__hcd__linux_8c.html#22cff3e20b45ec02e81e54a1adacfa20">_speed</a>,
+<a name="l00317"></a>00317         .complete = <a class="code" href="dwc__otg__hcd__linux_8c.html#a0d18986574c384e98aa280e0475a9aa">_complete</a>,
+<a name="l00318"></a>00318         .get_b_hnp_enable = <a class="code" href="dwc__otg__hcd__linux_8c.html#578b76a201e8e722e31afdcd2c35dac9">_get_b_hnp_enable</a>,
+<a name="l00319"></a>00319 };
+<a name="l00320"></a>00320 
+<a name="l00327"></a><a class="code" href="dwc__otg__hcd__linux_8c.html#ab12cdf65bf4ed68545a6c17cc31269f">00327</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__driver_8c.html#ab12cdf65bf4ed68545a6c17cc31269f">hcd_init</a>(
+<a name="l00328"></a>00328 #ifdef LM_INTERFACE
+<a name="l00329"></a>00329         <span class="keyword">struct</span> lm_device *_dev
+<a name="l00330"></a>00330 #elif  PCI_INTERFACE
+<a name="l00331"></a>00331         <span class="keyword">struct</span> pci_dev *_dev
+<a name="l00332"></a>00332 #endif
+<a name="l00333"></a>00333         )
+<a name="l00334"></a>00334 {
+<a name="l00335"></a>00335         <span class="keyword">struct </span>usb_hcd *hcd = NULL;
+<a name="l00336"></a>00336         <a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a> = NULL;
+<a name="l00337"></a>00337 <span class="preprocessor">#ifdef LM_INTERFACE</span>
+<a name="l00338"></a>00338 <span class="preprocessor"></span>        <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = lm_get_drvdata(_dev);
+<a name="l00339"></a>00339 <span class="preprocessor">#elif  PCI_INTERFACE</span>
+<a name="l00340"></a>00340 <span class="preprocessor"></span>        <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = pci_get_drvdata(_dev);
+<a name="l00341"></a>00341 <span class="preprocessor">#endif</span>
+<a name="l00342"></a>00342 <span class="preprocessor"></span>
+<a name="l00343"></a>00343         <span class="keywordtype">int</span> retval = 0;
+<a name="l00344"></a>00344 
+<a name="l00345"></a>00345         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#e4a050e176c1c4f556da2b276a8c2b37">DBG_HCD</a>, <span class="stringliteral">"DWC OTG HCD INIT\n"</span>);
+<a name="l00346"></a>00346 
+<a name="l00347"></a>00347         <span class="comment">/* Set device flags indicating whether the HCD supports DMA. */</span>
+<a name="l00348"></a>00348         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#f4f060a2decd6434bbd96703a4d1fc66">dwc_otg_is_dma_enable</a>(otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#4cc7c9f6e473072c2ed0a5e6adb25ebe">core_if</a>)) {
+<a name="l00349"></a>00349 <span class="preprocessor">#ifdef LM_INTERFACE</span>
+<a name="l00350"></a>00350 <span class="preprocessor"></span>                _dev-&gt;dev.dma_mask = (<span class="keywordtype">void</span> *)~0;
+<a name="l00351"></a>00351                 _dev-&gt;dev.coherent_dma_mask = ~0;
+<a name="l00352"></a>00352 <span class="preprocessor">#elif  PCI_INTERFACE</span>
+<a name="l00353"></a>00353 <span class="preprocessor"></span>                pci_set_dma_mask(_dev,DMA_32BIT_MASK);          
+<a name="l00354"></a>00354                 pci_set_consistent_dma_mask(_dev,DMA_32BIT_MASK);
+<a name="l00355"></a>00355 <span class="preprocessor">#endif</span>
+<a name="l00356"></a>00356 <span class="preprocessor"></span>
+<a name="l00357"></a>00357         } <span class="keywordflow">else</span> {
+<a name="l00358"></a>00358 <span class="preprocessor">#ifdef LM_INTERFACE</span>
+<a name="l00359"></a>00359 <span class="preprocessor"></span>                _dev-&gt;dev.dma_mask = (<span class="keywordtype">void</span> *)0;
+<a name="l00360"></a>00360                 _dev-&gt;dev.coherent_dma_mask = 0;
+<a name="l00361"></a>00361 <span class="preprocessor">#elif  PCI_INTERFACE</span>
+<a name="l00362"></a>00362 <span class="preprocessor"></span>                pci_set_dma_mask(_dev,0);               
+<a name="l00363"></a>00363                 pci_set_consistent_dma_mask(_dev,0);
+<a name="l00364"></a>00364 <span class="preprocessor">#endif</span>
+<a name="l00365"></a>00365 <span class="preprocessor"></span>        }
+<a name="l00366"></a>00366 
+<a name="l00367"></a>00367         <span class="comment">/*</span>
+<a name="l00368"></a>00368 <span class="comment">         * Allocate memory for the base HCD plus the DWC OTG HCD.</span>
+<a name="l00369"></a>00369 <span class="comment">         * Initialize the base HCD.</span>
+<a name="l00370"></a>00370 <span class="comment">         */</span>
+<a name="l00371"></a>00371         hcd = usb_create_hcd(&amp;<a class="code" href="dwc__otg__hcd__linux_8c.html#ab1d492c360b963d179798f2641c02a5">dwc_otg_hc_driver</a>, &amp;_dev-&gt;dev, _dev-&gt;dev.bus_id);
+<a name="l00372"></a>00372         <span class="keywordflow">if</span> (!hcd) {
+<a name="l00373"></a>00373                 retval = -ENOMEM;
+<a name="l00374"></a>00374                 <span class="keywordflow">goto</span> error1;
+<a name="l00375"></a>00375         }
+<a name="l00376"></a>00376 
+<a name="l00377"></a>00377         hcd-&gt;regs = otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#ed96ed1109175f87fd83fa32a9c2c6fa">base</a>;
+<a name="l00378"></a>00378 
+<a name="l00379"></a>00379         <span class="comment">/* Initialize the DWC OTG HCD. */</span>
+<a name="l00380"></a>00380         dwc_otg_hcd = <a class="code" href="dwc__otg__hcd_8c.html#5595437c199432efbd3609dc87ef5afa">dwc_otg_hcd_alloc_hcd</a>();
+<a name="l00381"></a>00381         <span class="keywordflow">if</span> (!dwc_otg_hcd) {
+<a name="l00382"></a>00382                 <span class="keywordflow">goto</span> error2;
+<a name="l00383"></a>00383         }
+<a name="l00384"></a>00384         ((<span class="keyword">struct </span><a class="code" href="structwrapper__priv__data.html">wrapper_priv_data</a> *)(hcd-&gt;hcd_priv))-&gt;<a class="code" href="structwrapper__priv__data.html#3a5cfdab2772597d857294972bb171c8">dwc_otg_hcd</a> =
+<a name="l00385"></a>00385             <a class="code" href="structwrapper__priv__data.html#3a5cfdab2772597d857294972bb171c8">dwc_otg_hcd</a>;
+<a name="l00386"></a>00386         otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#834ef28e884f0d7fcac68f3bdf5c4b33">hcd</a> = <a class="code" href="structwrapper__priv__data.html#3a5cfdab2772597d857294972bb171c8">dwc_otg_hcd</a>;
+<a name="l00387"></a>00387 
+<a name="l00388"></a>00388         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__hcd_8c.html#2d38590dadee51fd767d63e0dc675f23">dwc_otg_hcd_init</a>(<a class="code" href="structwrapper__priv__data.html#3a5cfdab2772597d857294972bb171c8">dwc_otg_hcd</a>, otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#4cc7c9f6e473072c2ed0a5e6adb25ebe">core_if</a>)) {
+<a name="l00389"></a>00389                 <span class="keywordflow">goto</span> error2;
+<a name="l00390"></a>00390         }
+<a name="l00391"></a>00391 
+<a name="l00392"></a>00392         hcd-&gt;self.<a class="code" href="structdwc__otg__hcd.html#9231b4c3dce89a1506a5e501ec5c7a39">otg_port</a> = <a class="code" href="dwc__otg__hcd_8c.html#e7d3657931984a1ce1cee5cf47cb08f3">dwc_otg_hcd_otg_port</a>(<a class="code" href="structwrapper__priv__data.html#3a5cfdab2772597d857294972bb171c8">dwc_otg_hcd</a>);
+<a name="l00393"></a>00393 
+<a name="l00394"></a>00394         <span class="comment">/*</span>
+<a name="l00395"></a>00395 <span class="comment">         * Finish generic HCD initialization and start the HCD. This function</span>
+<a name="l00396"></a>00396 <span class="comment">         * allocates the DMA buffer pool, registers the USB bus, requests the</span>
+<a name="l00397"></a>00397 <span class="comment">         * IRQ line, and calls hcd_start method.</span>
+<a name="l00398"></a>00398 <span class="comment">         */</span>
+<a name="l00399"></a>00399         retval = usb_add_hcd(hcd, _dev-&gt;irq, SA_SHIRQ);
+<a name="l00400"></a>00400         <span class="keywordflow">if</span> (retval &lt; 0) {
+<a name="l00401"></a>00401                 <span class="keywordflow">goto</span> error2;
+<a name="l00402"></a>00402         }
+<a name="l00403"></a>00403 
+<a name="l00404"></a>00404         <a class="code" href="dwc__otg__hcd_8c.html#c73ca7d4284c8f0de7338a66607e4eb1">dwc_otg_hcd_set_priv_data</a>(<a class="code" href="structwrapper__priv__data.html#3a5cfdab2772597d857294972bb171c8">dwc_otg_hcd</a>, hcd);
+<a name="l00405"></a>00405         <span class="keywordflow">return</span> 0;
+<a name="l00406"></a>00406 
+<a name="l00407"></a>00407       error2:
+<a name="l00408"></a>00408         usb_put_hcd(hcd);
+<a name="l00409"></a>00409       error1:
+<a name="l00410"></a>00410         <span class="keywordflow">return</span> retval;
+<a name="l00411"></a>00411 }
+<a name="l00412"></a>00412 
+<a name="l00417"></a><a class="code" href="dwc__otg__hcd__linux_8c.html#f36193b3ff33c0473956c8a15eee4f5b">00417</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__driver_8c.html#f36193b3ff33c0473956c8a15eee4f5b">hcd_remove</a>(
+<a name="l00418"></a>00418 #ifdef LM_INTERFACE
+<a name="l00419"></a>00419         <span class="keyword">struct</span> lm_device *_dev
+<a name="l00420"></a>00420 #elif  PCI_INTERFACE
+<a name="l00421"></a>00421         <span class="keyword">struct</span> pci_dev *_dev
+<a name="l00422"></a>00422 #endif
+<a name="l00423"></a>00423         )
+<a name="l00424"></a>00424 {
+<a name="l00425"></a>00425 <span class="preprocessor">#ifdef LM_INTERFACE</span>
+<a name="l00426"></a>00426 <span class="preprocessor"></span>        <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = lm_get_drvdata(_dev);
+<a name="l00427"></a>00427 <span class="preprocessor">#elif  PCI_INTERFACE</span>
+<a name="l00428"></a>00428 <span class="preprocessor"></span>        <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = pci_get_drvdata(_dev);
+<a name="l00429"></a>00429 <span class="preprocessor">#endif</span>
+<a name="l00430"></a>00430 <span class="preprocessor"></span>
+<a name="l00431"></a>00431         <a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>;
+<a name="l00432"></a>00432         <span class="keyword">struct </span>usb_hcd *hcd;
+<a name="l00433"></a>00433 
+<a name="l00434"></a>00434         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#e4a050e176c1c4f556da2b276a8c2b37">DBG_HCD</a>, <span class="stringliteral">"DWC OTG HCD REMOVE\n"</span>);
+<a name="l00435"></a>00435 
+<a name="l00436"></a>00436         <span class="keywordflow">if</span> (!otg_dev) {
+<a name="l00437"></a>00437                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#2bf62a567355d1ea38814714bd7b57ec">DBG_ANY</a>, <span class="stringliteral">"%s: otg_dev NULL!\n"</span>, __func__);
+<a name="l00438"></a>00438                 <span class="keywordflow">return</span>;
+<a name="l00439"></a>00439         }
+<a name="l00440"></a>00440 
+<a name="l00441"></a>00441         dwc_otg_hcd = otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#834ef28e884f0d7fcac68f3bdf5c4b33">hcd</a>;
+<a name="l00442"></a>00442 
+<a name="l00443"></a>00443         <span class="keywordflow">if</span> (!dwc_otg_hcd) {
+<a name="l00444"></a>00444                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#2bf62a567355d1ea38814714bd7b57ec">DBG_ANY</a>, <span class="stringliteral">"%s: otg_dev-&gt;hcd NULL!\n"</span>, __func__);
+<a name="l00445"></a>00445                 <span class="keywordflow">return</span>;
+<a name="l00446"></a>00446         }
+<a name="l00447"></a>00447 
+<a name="l00448"></a>00448         hcd = <a class="code" href="dwc__otg__hcd__linux_8c.html#e314b37c9e03857c2cad95724982ad42">dwc_otg_hcd_to_hcd</a>(dwc_otg_hcd);
+<a name="l00449"></a>00449 
+<a name="l00450"></a>00450         <span class="keywordflow">if</span> (!hcd) {
+<a name="l00451"></a>00451                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#2bf62a567355d1ea38814714bd7b57ec">DBG_ANY</a>,
+<a name="l00452"></a>00452                             <span class="stringliteral">"%s: dwc_otg_hcd_to_hcd(dwc_otg_hcd) NULL!\n"</span>,
+<a name="l00453"></a>00453                             __func__);
+<a name="l00454"></a>00454                 <span class="keywordflow">return</span>;
+<a name="l00455"></a>00455         }
+<a name="l00456"></a>00456         usb_remove_hcd(hcd);
+<a name="l00457"></a>00457         <a class="code" href="dwc__otg__hcd_8c.html#c73ca7d4284c8f0de7338a66607e4eb1">dwc_otg_hcd_set_priv_data</a>(dwc_otg_hcd, NULL);
+<a name="l00458"></a>00458         <a class="code" href="dwc__otg__hcd_8c.html#f347bcb363a622ced29161878d38830b">dwc_otg_hcd_remove</a>(dwc_otg_hcd);
+<a name="l00459"></a>00459         usb_put_hcd(hcd);
+<a name="l00460"></a>00460 }
+<a name="l00461"></a>00461 
+<a name="l00462"></a>00462 <span class="comment">/* =========================================================================</span>
+<a name="l00463"></a>00463 <span class="comment"> *  Linux HC Driver Functions</span>
+<a name="l00464"></a>00464 <span class="comment"> * ========================================================================= */</span>
+<a name="l00465"></a>00465 
+<a name="l00469"></a><a class="code" href="dwc__otg__hcd__linux_8c.html#5d7f9da64cfeb32895d6c3d1366d45cf">00469</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__cil__intr_8c.html#fc2d933cd662b3d060747004c79203a1">hcd_start</a>(<span class="keyword">struct</span> usb_hcd *hcd)
+<a name="l00470"></a>00470 {
+<a name="l00471"></a>00471         <a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a> = <a class="code" href="dwc__otg__hcd__linux_8c.html#bd8c86466ccd8ff8b94867d601e66116">hcd_to_dwc_otg_hcd</a>(hcd);
+<a name="l00472"></a>00472         <span class="keyword">struct </span>usb_bus *bus;
+<a name="l00473"></a>00473 
+<a name="l00474"></a>00474         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#e4a050e176c1c4f556da2b276a8c2b37">DBG_HCD</a>, <span class="stringliteral">"DWC OTG HCD START\n"</span>);
+<a name="l00475"></a>00475         bus = hcd_to_bus(hcd);
+<a name="l00476"></a>00476 
+<a name="l00477"></a>00477         hcd-&gt;state = HC_STATE_RUNNING;
+<a name="l00478"></a>00478         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__hcd_8c.html#7242be8ebc7f7516292cbe2344ab03be">dwc_otg_hcd_start</a>(dwc_otg_hcd, &amp;<a class="code" href="dwc__otg__hcd__linux_8c.html#430ee3db85940ea34a1702a37fbfb942">hcd_fops</a>)) {
+<a name="l00479"></a>00479                 <span class="keywordflow">return</span> 0;
+<a name="l00480"></a>00480         }
+<a name="l00481"></a>00481 
+<a name="l00482"></a>00482         <span class="comment">/* Initialize and connect root hub if one is not already attached */</span>
+<a name="l00483"></a>00483         <span class="keywordflow">if</span> (bus-&gt;root_hub) {
+<a name="l00484"></a>00484                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#e4a050e176c1c4f556da2b276a8c2b37">DBG_HCD</a>, <span class="stringliteral">"DWC OTG HCD Has Root Hub\n"</span>);
+<a name="l00485"></a>00485                 <span class="comment">/* Inform the HUB driver to resume. */</span>
+<a name="l00486"></a>00486                 usb_hcd_resume_root_hub(hcd);
+<a name="l00487"></a>00487         }
+<a name="l00488"></a>00488 
+<a name="l00489"></a>00489         <span class="keywordflow">return</span> 0;
+<a name="l00490"></a>00490 }
+<a name="l00491"></a>00491 
+<a name="l00496"></a><a class="code" href="dwc__otg__hcd__linux_8c.html#cbb6a9e932a0baf80d1fdb013ac5d679">00496</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil__intr_8c.html#b2721d01cc389181470095955b4e0994">hcd_stop</a>(<span class="keyword">struct</span> usb_hcd *hcd)
+<a name="l00497"></a>00497 {
+<a name="l00498"></a>00498         <a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a> = <a class="code" href="dwc__otg__hcd__linux_8c.html#bd8c86466ccd8ff8b94867d601e66116">hcd_to_dwc_otg_hcd</a>(hcd);
+<a name="l00499"></a>00499 
+<a name="l00500"></a>00500         <a class="code" href="dwc__otg__hcd_8c.html#70c58e8a45eb7ad8ee2f2c74ba3a77f0">dwc_otg_hcd_stop</a>(dwc_otg_hcd);
+<a name="l00501"></a>00501 }
+<a name="l00502"></a>00502 
+<a name="l00504"></a><a class="code" href="dwc__otg__hcd__linux_8c.html#c78128edb8902dc96534c5bb253f99a3">00504</a> <span class="keyword">static</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd__linux_8c.html#c78128edb8902dc96534c5bb253f99a3">get_frame_number</a>(<span class="keyword">struct</span> usb_hcd *hcd)
+<a name="l00505"></a>00505 {
+<a name="l00506"></a>00506         <a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a> = <a class="code" href="dwc__otg__hcd__linux_8c.html#bd8c86466ccd8ff8b94867d601e66116">hcd_to_dwc_otg_hcd</a>(hcd);
+<a name="l00507"></a>00507 
+<a name="l00508"></a>00508         <span class="keywordflow">return</span> <a class="code" href="dwc__otg__hcd_8c.html#f06514bd6f8c219cc72d1f467a82c056">dwc_otg_hcd_get_frame_number</a>(dwc_otg_hcd);
+<a name="l00509"></a>00509 }
+<a name="l00510"></a>00510 
+<a name="l00511"></a>00511 <span class="preprocessor">#ifdef DEBUG</span>
+<a name="l00512"></a>00512 <span class="preprocessor"></span><span class="keyword">static</span> <span class="keywordtype">void</span> dump_urb_info(<span class="keyword">struct</span> urb *urb, <span class="keywordtype">char</span> *fn_name)
+<a name="l00513"></a>00513 {
+<a name="l00514"></a>00514         DWC_PRINTF(<span class="stringliteral">"%s, urb %p\n"</span>, fn_name, urb);
+<a name="l00515"></a>00515         DWC_PRINTF(<span class="stringliteral">"  Device address: %d\n"</span>, usb_pipedevice(urb-&gt;pipe));
+<a name="l00516"></a>00516         DWC_PRINTF(<span class="stringliteral">"  Endpoint: %d, %s\n"</span>, usb_pipeendpoint(urb-&gt;pipe),
+<a name="l00517"></a>00517                    (usb_pipein(urb-&gt;pipe) ? <span class="stringliteral">"IN"</span> : <span class="stringliteral">"OUT"</span>));
+<a name="l00518"></a>00518         DWC_PRINTF(<span class="stringliteral">"  Endpoint type: %s\n"</span>, ( {
+<a name="l00519"></a>00519                                              <span class="keywordtype">char</span> *pipetype;
+<a name="l00520"></a>00520                                              <span class="keywordflow">switch</span> (usb_pipetype(urb-&gt;pipe)) {
+<a name="l00521"></a>00521 <span class="keywordflow">case</span> PIPE_CONTROL:
+<a name="l00522"></a>00522 pipetype = <span class="stringliteral">"CONTROL"</span>; <span class="keywordflow">break</span>; <span class="keywordflow">case</span> PIPE_BULK:
+<a name="l00523"></a>00523 pipetype = <span class="stringliteral">"BULK"</span>; <span class="keywordflow">break</span>; <span class="keywordflow">case</span> PIPE_INTERRUPT:
+<a name="l00524"></a>00524 pipetype = <span class="stringliteral">"INTERRUPT"</span>; <span class="keywordflow">break</span>; <span class="keywordflow">case</span> PIPE_ISOCHRONOUS:
+<a name="l00525"></a>00525 pipetype = <span class="stringliteral">"ISOCHRONOUS"</span>; <span class="keywordflow">break</span>; <span class="keywordflow">default</span>:
+<a name="l00526"></a>00526                                              pipetype = <span class="stringliteral">"UNKNOWN"</span>; <span class="keywordflow">break</span>;};
+<a name="l00527"></a>00527                                              pipetype;}
+<a name="l00528"></a>00528                    )) ;
+<a name="l00529"></a>00529         DWC_PRINTF(<span class="stringliteral">"  Speed: %s\n"</span>, ( {
+<a name="l00530"></a>00530                                      <span class="keywordtype">char</span> *speed; <span class="keywordflow">switch</span> (urb-&gt;dev-&gt;speed) {
+<a name="l00531"></a>00531 <span class="keywordflow">case</span> USB_SPEED_HIGH:
+<a name="l00532"></a>00532 speed = <span class="stringliteral">"HIGH"</span>; <span class="keywordflow">break</span>; <span class="keywordflow">case</span> USB_SPEED_FULL:
+<a name="l00533"></a>00533 speed = <span class="stringliteral">"FULL"</span>; <span class="keywordflow">break</span>; <span class="keywordflow">case</span> USB_SPEED_LOW:
+<a name="l00534"></a>00534 speed = <span class="stringliteral">"LOW"</span>; <span class="keywordflow">break</span>; <span class="keywordflow">default</span>:
+<a name="l00535"></a>00535                                      speed = <span class="stringliteral">"UNKNOWN"</span>; <span class="keywordflow">break</span>;};
+<a name="l00536"></a>00536                                      speed;}
+<a name="l00537"></a>00537                    )) ;
+<a name="l00538"></a>00538         DWC_PRINTF(<span class="stringliteral">"  Max packet size: %d\n"</span>,
+<a name="l00539"></a>00539                    usb_maxpacket(urb-&gt;dev, urb-&gt;pipe, usb_pipeout(urb-&gt;pipe)));
+<a name="l00540"></a>00540         DWC_PRINTF(<span class="stringliteral">"  Data buffer length: %d\n"</span>, urb-&gt;transfer_buffer_length);
+<a name="l00541"></a>00541         DWC_PRINTF(<span class="stringliteral">"  Transfer buffer: %p, Transfer DMA: %p\n"</span>,
+<a name="l00542"></a>00542                    urb-&gt;transfer_buffer, (<span class="keywordtype">void</span> *)urb-&gt;transfer_dma);
+<a name="l00543"></a>00543         DWC_PRINTF(<span class="stringliteral">"  Setup buffer: %p, Setup DMA: %p\n"</span>,
+<a name="l00544"></a>00544                    urb-&gt;setup_packet, (<span class="keywordtype">void</span> *)urb-&gt;setup_dma);
+<a name="l00545"></a>00545         DWC_PRINTF(<span class="stringliteral">"  Interval: %d\n"</span>, urb-&gt;interval);
+<a name="l00546"></a>00546         <span class="keywordflow">if</span> (usb_pipetype(urb-&gt;pipe) == PIPE_ISOCHRONOUS) {
+<a name="l00547"></a>00547                 <span class="keywordtype">int</span> i;
+<a name="l00548"></a>00548                 <span class="keywordflow">for</span> (i = 0; i &lt; urb-&gt;number_of_packets; i++) {
+<a name="l00549"></a>00549                         DWC_PRINTF(<span class="stringliteral">"  ISO Desc %d:\n"</span>, i);
+<a name="l00550"></a>00550                         DWC_PRINTF(<span class="stringliteral">"    offset: %d, length %d\n"</span>,
+<a name="l00551"></a>00551                                    urb-&gt;iso_frame_desc[i].offset,
+<a name="l00552"></a>00552                                    urb-&gt;iso_frame_desc[i].length);
+<a name="l00553"></a>00553                 }
+<a name="l00554"></a>00554         }
+<a name="l00555"></a>00555 }
+<a name="l00556"></a>00556 
+<a name="l00557"></a>00557 <span class="preprocessor">#endif</span>
+<a name="l00558"></a>00558 <span class="preprocessor"></span>
+<a name="l00562"></a><a class="code" href="dwc__otg__hcd__linux_8c.html#d9e9c76f2bc1c4f662d132c710a95a60">00562</a> <span class="keyword">static</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd__linux_8c.html#d9e9c76f2bc1c4f662d132c710a95a60">urb_enqueue</a>(<span class="keyword">struct</span> usb_hcd *hcd,
+<a name="l00563"></a>00563                        <span class="keyword">struct</span> usb_host_endpoint *ep,
+<a name="l00564"></a>00564                        <span class="keyword">struct</span> urb *urb, gfp_t mem_flags)
+<a name="l00565"></a>00565 {
+<a name="l00566"></a>00566         <span class="keywordtype">int</span> retval = 0;
+<a name="l00567"></a>00567         <a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a> = <a class="code" href="dwc__otg__hcd__linux_8c.html#bd8c86466ccd8ff8b94867d601e66116">hcd_to_dwc_otg_hcd</a>(hcd);
+<a name="l00568"></a>00568         <a class="code" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *dwc_otg_urb;
+<a name="l00569"></a>00569         <span class="keywordtype">int</span> i;
+<a name="l00570"></a>00570         <span class="keywordtype">int</span> alloc_bandwidth = 0;
+<a name="l00571"></a>00571         uint8_t ep_type = 0;
+<a name="l00572"></a>00572         uint32_t flags = 0;
+<a name="l00573"></a>00573         <span class="keywordtype">void</span> *buf;
+<a name="l00574"></a>00574 
+<a name="l00575"></a>00575 <span class="preprocessor">#ifdef DEBUG</span>
+<a name="l00576"></a>00576 <span class="preprocessor"></span>        <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__dbg_8h.html#7a96217c88a4d786f6cb3d4df09dee04">CHK_DEBUG_LEVEL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a> | <a class="code" href="dwc__otg__dbg_8h.html#737e22e02729647d12db8e3059ad06c9">DBG_HCD_URB</a>)) {
+<a name="l00577"></a>00577                 dump_urb_info(urb, <span class="stringliteral">"urb_enqueue"</span>);
+<a name="l00578"></a>00578         }
+<a name="l00579"></a>00579 <span class="preprocessor">#endif</span>
+<a name="l00580"></a>00580 <span class="preprocessor"></span>
+<a name="l00581"></a>00581         <span class="keywordflow">if</span> ((usb_pipetype(urb-&gt;pipe) == PIPE_ISOCHRONOUS)
+<a name="l00582"></a>00582             || (usb_pipetype(urb-&gt;pipe) == PIPE_INTERRUPT)) {
+<a name="l00583"></a>00583                 <span class="keywordflow">if</span> (!<a class="code" href="dwc__otg__hcd_8c.html#5deb69c332ba937b959c9dccadd87568">dwc_otg_hcd_is_bandwidth_allocated</a>
+<a name="l00584"></a>00584                     (dwc_otg_hcd, &amp;ep-&gt;hcpriv)) {
+<a name="l00585"></a>00585                         alloc_bandwidth = 1;
+<a name="l00586"></a>00586                 }
+<a name="l00587"></a>00587         }
+<a name="l00588"></a>00588 
+<a name="l00589"></a>00589         <span class="keywordflow">switch</span> (usb_pipetype(urb-&gt;pipe)) {
+<a name="l00590"></a>00590         <span class="keywordflow">case</span> PIPE_CONTROL:
+<a name="l00591"></a>00591                 ep_type = USB_ENDPOINT_XFER_CONTROL;
+<a name="l00592"></a>00592                 <span class="keywordflow">break</span>;
+<a name="l00593"></a>00593         <span class="keywordflow">case</span> PIPE_ISOCHRONOUS:
+<a name="l00594"></a>00594                 ep_type = USB_ENDPOINT_XFER_ISOC;
+<a name="l00595"></a>00595                 <span class="keywordflow">break</span>;
+<a name="l00596"></a>00596         <span class="keywordflow">case</span> PIPE_BULK:
+<a name="l00597"></a>00597                 ep_type = USB_ENDPOINT_XFER_BULK;
+<a name="l00598"></a>00598                 <span class="keywordflow">break</span>;
+<a name="l00599"></a>00599         <span class="keywordflow">case</span> PIPE_INTERRUPT:
+<a name="l00600"></a>00600                 ep_type = USB_ENDPOINT_XFER_INT;
+<a name="l00601"></a>00601                 <span class="keywordflow">break</span>;
+<a name="l00602"></a>00602         <span class="keywordflow">default</span>:
+<a name="l00603"></a>00603                 DWC_WARN(<span class="stringliteral">"Wrong ep type\n"</span>);
+<a name="l00604"></a>00604         }
+<a name="l00605"></a>00605 
+<a name="l00606"></a>00606         dwc_otg_urb = <a class="code" href="dwc__otg__hcd_8c.html#264fc9d293c76e42dded9dee2cf44283">dwc_otg_hcd_urb_alloc</a>(dwc_otg_hcd,
+<a name="l00607"></a>00607                                             urb-&gt;number_of_packets,
+<a name="l00608"></a>00608                                             mem_flags == GFP_ATOMIC ? 1 : 0);
+<a name="l00609"></a>00609 
+<a name="l00610"></a>00610         <a class="code" href="dwc__otg__hcd_8c.html#4aca8781f512198149388799a8ae9aba">dwc_otg_hcd_urb_set_pipeinfo</a>(dwc_otg_urb, usb_pipedevice(urb-&gt;pipe),
+<a name="l00611"></a>00611                                      usb_pipeendpoint(urb-&gt;pipe), ep_type,
+<a name="l00612"></a>00612                                      usb_pipein(urb-&gt;pipe),
+<a name="l00613"></a>00613                                      usb_maxpacket(urb-&gt;dev, urb-&gt;pipe,
+<a name="l00614"></a>00614                                                    !(usb_pipein(urb-&gt;pipe))));
+<a name="l00615"></a>00615 
+<a name="l00616"></a>00616         buf = urb-&gt;transfer_buffer;
+<a name="l00617"></a>00617         <span class="keywordflow">if</span> (hcd-&gt;self.uses_dma) {
+<a name="l00618"></a>00618                 <span class="comment">/*</span>
+<a name="l00619"></a>00619 <span class="comment">                 * Calculate virtual address from physical address,</span>
+<a name="l00620"></a>00620 <span class="comment">                 * because some class driver may not fill transfer_buffer.</span>
+<a name="l00621"></a>00621 <span class="comment">                 * In Buffer DMA mode virual address is used,</span>
+<a name="l00622"></a>00622 <span class="comment">                 * when handling non DWORD aligned buffers.</span>
+<a name="l00623"></a>00623 <span class="comment">                 */</span>
+<a name="l00624"></a>00624                 buf = phys_to_virt(urb-&gt;transfer_dma);
+<a name="l00625"></a>00625         }
+<a name="l00626"></a>00626         
+<a name="l00627"></a>00627         <span class="keywordflow">if</span> (!(urb-&gt;transfer_flags &amp; URB_NO_INTERRUPT))
+<a name="l00628"></a>00628                 flags |= <a class="code" href="dwc__otg__hcd__if_8h.html#973a9deb7ee08e99abf7cb7adf6a5c72">URB_GIVEBACK_ASAP</a>;
+<a name="l00629"></a>00629         <span class="keywordflow">if</span> (urb-&gt;transfer_flags &amp; URB_ZERO_PACKET)
+<a name="l00630"></a>00630                 flags |= <a class="code" href="dwc__otg__hcd__if_8h.html#14e576ea3b30c038f925e3e6c80c64fe">URB_SEND_ZERO_PACKET</a>;
+<a name="l00631"></a>00631 
+<a name="l00632"></a>00632         <a class="code" href="dwc__otg__hcd_8c.html#d141b0ed3f2eac3f8aab2d8cefe34345">dwc_otg_hcd_urb_set_params</a>(dwc_otg_urb, urb, buf,
+<a name="l00633"></a>00633                                    urb-&gt;transfer_dma,
+<a name="l00634"></a>00634                                    urb-&gt;transfer_buffer_length,
+<a name="l00635"></a>00635                                    urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#254afd954f3e24bb92841384183a317c">setup_packet</a>, 
+<a name="l00636"></a>00636                                    urb-&gt;setup_dma,
+<a name="l00637"></a>00637                                    flags,
+<a name="l00638"></a>00638                                    urb-&gt;interval);
+<a name="l00639"></a>00639 
+<a name="l00640"></a>00640         <span class="keywordflow">for</span> (i = 0; i &lt; urb-&gt;number_of_packets; ++i) {
+<a name="l00641"></a>00641                 <a class="code" href="dwc__otg__hcd_8c.html#8617e93eba1bfd6466a9af1e6d2f731b">dwc_otg_hcd_urb_set_iso_desc_params</a>(dwc_otg_urb, i,
+<a name="l00642"></a>00642                                                     urb-&gt;iso_frame_desc[i].
+<a name="l00643"></a>00643                                                     offset,
+<a name="l00644"></a>00644                                                     urb-&gt;iso_frame_desc[i].
+<a name="l00645"></a>00645                                                     length);
+<a name="l00646"></a>00646         }
+<a name="l00647"></a>00647 
+<a name="l00648"></a>00648         urb-&gt;hcpriv = dwc_otg_urb;
+<a name="l00649"></a>00649         retval = <a class="code" href="dwc__otg__hcd_8c.html#e8129fbc0a4073f0a5f64fa3b0f5127b">dwc_otg_hcd_urb_enqueue</a>(dwc_otg_hcd, dwc_otg_urb, &amp;ep-&gt;hcpriv);
+<a name="l00650"></a>00650         <span class="keywordflow">if</span> (!retval) {
+<a name="l00651"></a>00651                 <span class="keywordflow">if</span> (alloc_bandwidth) {
+<a name="l00652"></a>00652                         <a class="code" href="dwc__otg__hcd__linux_8c.html#e270a6a091a674ccf6f390fdcf746b87">allocate_bus_bandwidth</a>(hcd,
+<a name="l00653"></a>00653                                                <a class="code" href="dwc__otg__hcd_8c.html#bd160be911ccc8f90141dae9c40276eb">dwc_otg_hcd_get_ep_bandwidth</a>
+<a name="l00654"></a>00654                                                (dwc_otg_hcd, ep-&gt;hcpriv), urb);
+<a name="l00655"></a>00655                 }
+<a name="l00656"></a>00656         } <span class="keywordflow">else</span> {
+<a name="l00657"></a>00657                 <span class="keywordflow">if</span> (retval == -DWC_E_NO_DEVICE) {
+<a name="l00658"></a>00658                         retval = -ENODEV;
+<a name="l00659"></a>00659                 }
+<a name="l00660"></a>00660         }
+<a name="l00661"></a>00661 
+<a name="l00662"></a>00662         <span class="keywordflow">return</span> retval;
+<a name="l00663"></a>00663 }
+<a name="l00664"></a>00664 
+<a name="l00667"></a><a class="code" href="dwc__otg__hcd__linux_8c.html#afc1f3d92fd7596140c0068bc96034f7">00667</a> <span class="keyword">static</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd__linux_8c.html#afc1f3d92fd7596140c0068bc96034f7">urb_dequeue</a>(<span class="keyword">struct</span> usb_hcd *hcd, <span class="keyword">struct</span> urb *urb)
+<a name="l00668"></a>00668 {
+<a name="l00669"></a>00669         <a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>;
+<a name="l00670"></a>00670         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#e4a050e176c1c4f556da2b276a8c2b37">DBG_HCD</a>, <span class="stringliteral">"DWC OTG HCD URB Dequeue\n"</span>);
+<a name="l00671"></a>00671 
+<a name="l00672"></a>00672         dwc_otg_hcd = <a class="code" href="dwc__otg__hcd__linux_8c.html#bd8c86466ccd8ff8b94867d601e66116">hcd_to_dwc_otg_hcd</a>(hcd);
+<a name="l00673"></a>00673 
+<a name="l00674"></a>00674 <span class="preprocessor">#ifdef DEBUG</span>
+<a name="l00675"></a>00675 <span class="preprocessor"></span>        <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__dbg_8h.html#7a96217c88a4d786f6cb3d4df09dee04">CHK_DEBUG_LEVEL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a> | <a class="code" href="dwc__otg__dbg_8h.html#737e22e02729647d12db8e3059ad06c9">DBG_HCD_URB</a>)) {
+<a name="l00676"></a>00676                 dump_urb_info(urb, <span class="stringliteral">"urb_dequeue"</span>);
+<a name="l00677"></a>00677         }
+<a name="l00678"></a>00678 <span class="preprocessor">#endif</span>
+<a name="l00679"></a>00679 <span class="preprocessor"></span>        <a class="code" href="dwc__otg__hcd_8c.html#8844d0e14480b7f0dcf5c8120cc20a4f">dwc_otg_hcd_urb_dequeue</a>(dwc_otg_hcd, urb-&gt;hcpriv);
+<a name="l00680"></a>00680 
+<a name="l00681"></a>00681         dwc_free(urb-&gt;hcpriv);
+<a name="l00682"></a>00682         urb-&gt;hcpriv = NULL;
+<a name="l00683"></a>00683 
+<a name="l00684"></a>00684         <span class="comment">/* Higher layer software sets URB status. */</span>
+<a name="l00685"></a>00685         usb_hcd_giveback_urb(hcd, urb);
+<a name="l00686"></a>00686         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__dbg_8h.html#7a96217c88a4d786f6cb3d4df09dee04">CHK_DEBUG_LEVEL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a> | <a class="code" href="dwc__otg__dbg_8h.html#737e22e02729647d12db8e3059ad06c9">DBG_HCD_URB</a>)) {
+<a name="l00687"></a>00687                 DWC_PRINTF(<span class="stringliteral">"Called usb_hcd_giveback_urb()\n"</span>);
+<a name="l00688"></a>00688                 DWC_PRINTF(<span class="stringliteral">"  urb-&gt;status = %d\n"</span>, urb-&gt;status);
+<a name="l00689"></a>00689         }
+<a name="l00690"></a>00690 
+<a name="l00691"></a>00691         <span class="keywordflow">return</span> 0;
+<a name="l00692"></a>00692 }
+<a name="l00693"></a>00693 
+<a name="l00694"></a>00694 <span class="comment">/* Frees resources in the DWC_otg controller related to a given endpoint. Also</span>
+<a name="l00695"></a>00695 <span class="comment"> * clears state in the HCD related to the endpoint. Any URBs for the endpoint</span>
+<a name="l00696"></a>00696 <span class="comment"> * must already be dequeued. */</span>
+<a name="l00697"></a><a class="code" href="dwc__otg__hcd__linux_8c.html#0aefc084c4c334dac85c95a43e8942c6">00697</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd__linux_8c.html#0aefc084c4c334dac85c95a43e8942c6">endpoint_disable</a>(<span class="keyword">struct</span> usb_hcd *hcd, <span class="keyword">struct</span> usb_host_endpoint *ep)
+<a name="l00698"></a>00698 {
+<a name="l00699"></a>00699         <a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a> = <a class="code" href="dwc__otg__hcd__linux_8c.html#bd8c86466ccd8ff8b94867d601e66116">hcd_to_dwc_otg_hcd</a>(hcd);
+<a name="l00700"></a>00700 
+<a name="l00701"></a>00701         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#e4a050e176c1c4f556da2b276a8c2b37">DBG_HCD</a>,
+<a name="l00702"></a>00702                     <span class="stringliteral">"DWC OTG HCD EP DISABLE: _bEndpointAddress=0x%02x, "</span>
+<a name="l00703"></a>00703                     <span class="stringliteral">"endpoint=%d\n"</span>, ep-&gt;desc.bEndpointAddress,
+<a name="l00704"></a>00704                     <a class="code" href="dwc__otg__hcd__linux_8c.html#4a327046464cd55f8abafc4af8ef74aa">dwc_ep_addr_to_endpoint</a>(ep-&gt;desc.bEndpointAddress));
+<a name="l00705"></a>00705         <a class="code" href="dwc__otg__hcd_8c.html#f80e9550161e354c865e3c411d661dbe">dwc_otg_hcd_endpoint_disable</a>(dwc_otg_hcd, ep-&gt;hcpriv, 250);
+<a name="l00706"></a>00706         ep-&gt;hcpriv = NULL;
+<a name="l00707"></a>00707 }
+<a name="l00708"></a>00708 
+<a name="l00714"></a><a class="code" href="dwc__otg__hcd__linux_8c.html#1e911926e9d51d6d9d11f11b81da8c3d">00714</a> <span class="keyword">static</span> irqreturn_t <a class="code" href="dwc__otg__hcd__linux_8c.html#1e911926e9d51d6d9d11f11b81da8c3d">dwc_otg_hcd_irq</a>(<span class="keyword">struct</span> usb_hcd *hcd)
+<a name="l00715"></a>00715 {
+<a name="l00716"></a>00716         <a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a> = <a class="code" href="dwc__otg__hcd__linux_8c.html#bd8c86466ccd8ff8b94867d601e66116">hcd_to_dwc_otg_hcd</a>(hcd);
+<a name="l00717"></a>00717         int32_t retval = <a class="code" href="dwc__otg__hcd_8h.html#b9dde24773f2741b9ff67e2d46760dc0">dwc_otg_hcd_handle_intr</a>(dwc_otg_hcd);
+<a name="l00718"></a>00718         <span class="keywordflow">if</span> (retval != 0) {
+<a name="l00719"></a>00719                 <a class="code" href="dwc__otg__driver_8h.html#3af7bafbb69f04a0fd36a27fae7e8497">S3C2410X_CLEAR_EINTPEND</a>();
+<a name="l00720"></a>00720         }
+<a name="l00721"></a>00721         <span class="keywordflow">return</span> IRQ_RETVAL(retval);
+<a name="l00722"></a>00722 }
+<a name="l00723"></a>00723 
+<a name="l00728"></a><a class="code" href="dwc__otg__hcd__linux_8c.html#108442f4aa4dc4663d8659241ed04e9c">00728</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd__linux_8c.html#108442f4aa4dc4663d8659241ed04e9c">hub_status_data</a>(<span class="keyword">struct</span> usb_hcd *hcd, <span class="keywordtype">char</span> *buf)
+<a name="l00729"></a>00729 {
+<a name="l00730"></a>00730         <a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd</a> = <a class="code" href="dwc__otg__hcd__linux_8c.html#bd8c86466ccd8ff8b94867d601e66116">hcd_to_dwc_otg_hcd</a>(hcd);
+<a name="l00731"></a>00731 
+<a name="l00732"></a>00732         buf[0] = 0;
+<a name="l00733"></a>00733         buf[0] |= (<a class="code" href="dwc__otg__hcd_8c.html#0d324c8dbb0c7cbadec8cebf943fc84b">dwc_otg_hcd_is_status_changed</a>(dwc_otg_hcd, 1)) &lt;&lt; 1;
+<a name="l00734"></a>00734 
+<a name="l00735"></a>00735         <span class="keywordflow">return</span> (buf[0] != 0);
+<a name="l00736"></a>00736 }
+<a name="l00737"></a>00737 
+<a name="l00739"></a><a class="code" href="dwc__otg__hcd__linux_8c.html#55d196cab99083dabdacdee78dc5e339">00739</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd__linux_8c.html#55d196cab99083dabdacdee78dc5e339">hub_control</a>(<span class="keyword">struct</span> usb_hcd *hcd,
+<a name="l00740"></a>00740                 u16 typeReq, u16 wValue, u16 wIndex, <span class="keywordtype">char</span> *buf, u16 wLength)
+<a name="l00741"></a>00741 {
+<a name="l00742"></a>00742         <span class="keywordtype">int</span> retval;
+<a name="l00743"></a>00743 
+<a name="l00744"></a>00744         retval = <a class="code" href="dwc__otg__hcd_8c.html#e3bd4e9d1f641cdd29df6633bfb1ebd2">dwc_otg_hcd_hub_control</a>(<a class="code" href="dwc__otg__hcd__linux_8c.html#bd8c86466ccd8ff8b94867d601e66116">hcd_to_dwc_otg_hcd</a>(hcd),
+<a name="l00745"></a>00745                                          typeReq, wValue, wIndex, buf, wLength);
+<a name="l00746"></a>00746 
+<a name="l00747"></a>00747         <span class="keywordflow">switch</span> (retval) {
+<a name="l00748"></a>00748         <span class="keywordflow">case</span> -DWC_E_INVALID:
+<a name="l00749"></a>00749                 retval = -EINVAL;
+<a name="l00750"></a>00750                 <span class="keywordflow">break</span>;
+<a name="l00751"></a>00751         }
+<a name="l00752"></a>00752 
+<a name="l00753"></a>00753         <span class="keywordflow">return</span> retval;
+<a name="l00754"></a>00754 }
+<a name="l00755"></a>00755 
+<a name="l00756"></a>00756 <span class="preprocessor">#endif                          </span><span class="comment">/* DWC_DEVICE_ONLY */</span>
+</pre></div><hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__linux_8c.html b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__linux_8c.html
new file mode 100644
index 000000000000..e88d9714dcac
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__linux_8c.html
@@ -0,0 +1,514 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd_linux.c File Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<h1>dwc_otg_hcd_linux.c File Reference</h1>This file contains the implementation of the HCD. <a href="#_details">More...</a>
+<p>
+<code>#include &lt;linux/kernel.h&gt;</code><br>
+<code>#include &lt;linux/module.h&gt;</code><br>
+<code>#include &lt;linux/moduleparam.h&gt;</code><br>
+<code>#include &lt;linux/init.h&gt;</code><br>
+<code>#include &lt;linux/device.h&gt;</code><br>
+<code>#include &lt;linux/errno.h&gt;</code><br>
+<code>#include &lt;linux/list.h&gt;</code><br>
+<code>#include &lt;linux/interrupt.h&gt;</code><br>
+<code>#include &lt;linux/string.h&gt;</code><br>
+<code>#include &lt;linux/dma-mapping.h&gt;</code><br>
+<code>#include &lt;linux/version.h&gt;</code><br>
+<code>#include &lt;asm/io.h&gt;</code><br>
+<code>#include &lt;linux/usb.h&gt;</code><br>
+<code>#include &lt;../drivers/usb/core/hcd.h&gt;</code><br>
+<code>#include &quot;<a class="el" href="dwc__otg__hcd__if_8h-source.html">dwc_otg_hcd_if.h</a>&quot;</code><br>
+<code>#include &quot;<a class="el" href="dwc__otg__dbg_8h-source.html">dwc_otg_dbg.h</a>&quot;</code><br>
+<code>#include &quot;<a class="el" href="dwc__otg__driver_8h-source.html">dwc_otg_driver.h</a>&quot;</code><br>
+
+<p>
+<a href="dwc__otg__hcd__linux_8c-source.html">Go to the source code of this file.</a><table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Structures</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structwrapper__priv__data.html">wrapper_priv_data</a></td></tr>
+
+<tr><td colspan="2"><br><h2>Linux HC Driver API Functions</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__linux_8c.html#d9e9c76f2bc1c4f662d132c710a95a60">urb_enqueue</a> (struct usb_hcd *hcd, struct usb_host_endpoint *ep, struct urb *urb, gfp_t mem_flags)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Starts processing a USB transfer request specified by a USB Request Block (URB).  <a href="#d9e9c76f2bc1c4f662d132c710a95a60"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__linux_8c.html#afc1f3d92fd7596140c0068bc96034f7">urb_dequeue</a> (struct usb_hcd *hcd, struct urb *urb)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Aborts/cancels a USB transfer request.  <a href="#afc1f3d92fd7596140c0068bc96034f7"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="0aefc084c4c334dac85c95a43e8942c6"></a><!-- doxytag: member="dwc_otg_hcd_linux.c::endpoint_disable" ref="0aefc084c4c334dac85c95a43e8942c6" args="(struct usb_hcd *hcd, struct usb_host_endpoint *ep)" -->
+static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__linux_8c.html#0aefc084c4c334dac85c95a43e8942c6">endpoint_disable</a> (struct usb_hcd *hcd, struct usb_host_endpoint *ep)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static irqreturn_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__linux_8c.html#1e911926e9d51d6d9d11f11b81da8c3d">dwc_otg_hcd_irq</a> (struct usb_hcd *hcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Handles host mode interrupts for the DWC_otg controller.  <a href="#1e911926e9d51d6d9d11f11b81da8c3d"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__linux_8c.html#5d7f9da64cfeb32895d6c3d1366d45cf">hcd_start</a> (struct usb_hcd *hcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Initializes the DWC_otg controller and its root hub and prepares it for host mode operation.  <a href="#5d7f9da64cfeb32895d6c3d1366d45cf"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__linux_8c.html#cbb6a9e932a0baf80d1fdb013ac5d679">hcd_stop</a> (struct usb_hcd *hcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Halts the DWC_otg host mode operations in a clean manner.  <a href="#cbb6a9e932a0baf80d1fdb013ac5d679"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c78128edb8902dc96534c5bb253f99a3"></a><!-- doxytag: member="dwc_otg_hcd_linux.c::get_frame_number" ref="c78128edb8902dc96534c5bb253f99a3" args="(struct usb_hcd *hcd)" -->
+static int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__linux_8c.html#c78128edb8902dc96534c5bb253f99a3">get_frame_number</a> (struct usb_hcd *hcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Returns the current frame number. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__linux_8c.html#108442f4aa4dc4663d8659241ed04e9c">hub_status_data</a> (struct usb_hcd *hcd, char *buf)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Creates Status Change bitmap for the root hub and root port.  <a href="#108442f4aa4dc4663d8659241ed04e9c"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="55d196cab99083dabdacdee78dc5e339"></a><!-- doxytag: member="dwc_otg_hcd_linux.c::hub_control" ref="55d196cab99083dabdacdee78dc5e339" args="(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex, char *buf, u16 wLength)" -->
+int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__linux_8c.html#55d196cab99083dabdacdee78dc5e339">hub_control</a> (struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex, char *buf, u16 wLength)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Handles hub class-specific requests. <br></td></tr>
+<tr><td colspan="2"><br><h2>Defines</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__linux_8c.html#4a327046464cd55f8abafc4af8ef74aa">dwc_ep_addr_to_endpoint</a>(_bEndpointAddress_)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Gets the endpoint number from a _bEndpointAddress argument.  <a href="#4a327046464cd55f8abafc4af8ef74aa"></a><br></td></tr>
+<tr><td colspan="2"><br><h2>Functions</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="bd8c86466ccd8ff8b94867d601e66116"></a><!-- doxytag: member="dwc_otg_hcd_linux.c::hcd_to_dwc_otg_hcd" ref="bd8c86466ccd8ff8b94867d601e66116" args="(struct usb_hcd *hcd)" -->
+static <a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__linux_8c.html#bd8c86466ccd8ff8b94867d601e66116">hcd_to_dwc_otg_hcd</a> (struct usb_hcd *hcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Gets the <a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd</a> from a struct usb_hcd. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e314b37c9e03857c2cad95724982ad42"></a><!-- doxytag: member="dwc_otg_hcd_linux.c::dwc_otg_hcd_to_hcd" ref="e314b37c9e03857c2cad95724982ad42" args="(dwc_otg_hcd_t *dwc_otg_hcd)" -->
+static struct usb_hcd *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__linux_8c.html#e314b37c9e03857c2cad95724982ad42">dwc_otg_hcd_to_hcd</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Gets the struct usb_hcd that contains a dwc_otg_hcd_t. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="99c594c1e3af2fa78b09c914cb334611"></a><!-- doxytag: member="dwc_otg_hcd_linux.c::dwc_urb_to_endpoint" ref="99c594c1e3af2fa78b09c914cb334611" args="(struct urb *urb)" -->
+usb_host_endpoint *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__linux_8c.html#99c594c1e3af2fa78b09c914cb334611">dwc_urb_to_endpoint</a> (struct urb *urb)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Gets the usb_host_endpoint associated with an URB. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="8011f9b662a7f4182e762de616bbc95e"></a><!-- doxytag: member="dwc_otg_hcd_linux.c::_disconnect" ref="8011f9b662a7f4182e762de616bbc95e" args="(dwc_otg_hcd_t *hcd)" -->
+static int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__linux_8c.html#8011f9b662a7f4182e762de616bbc95e">_disconnect</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e11ebd665a86e6ec3fd661965acca90e"></a><!-- doxytag: member="dwc_otg_hcd_linux.c::_start" ref="e11ebd665a86e6ec3fd661965acca90e" args="(dwc_otg_hcd_t *hcd)" -->
+static int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__linux_8c.html#e11ebd665a86e6ec3fd661965acca90e">_start</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f4fe5a6082e7cce809f3e2a4cb71a7e4"></a><!-- doxytag: member="dwc_otg_hcd_linux.c::_hub_info" ref="f4fe5a6082e7cce809f3e2a4cb71a7e4" args="(dwc_otg_hcd_t *hcd, void *urb_handle, uint32_t *hub_addr, uint32_t *port_addr)" -->
+static int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__linux_8c.html#f4fe5a6082e7cce809f3e2a4cb71a7e4">_hub_info</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, void *urb_handle, uint32_t *hub_addr, uint32_t *port_addr)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="22cff3e20b45ec02e81e54a1adacfa20"></a><!-- doxytag: member="dwc_otg_hcd_linux.c::_speed" ref="22cff3e20b45ec02e81e54a1adacfa20" args="(dwc_otg_hcd_t *hcd, void *urb_handle)" -->
+static int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__linux_8c.html#22cff3e20b45ec02e81e54a1adacfa20">_speed</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, void *urb_handle)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="578b76a201e8e722e31afdcd2c35dac9"></a><!-- doxytag: member="dwc_otg_hcd_linux.c::_get_b_hnp_enable" ref="578b76a201e8e722e31afdcd2c35dac9" args="(dwc_otg_hcd_t *hcd)" -->
+static int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__linux_8c.html#578b76a201e8e722e31afdcd2c35dac9">_get_b_hnp_enable</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e270a6a091a674ccf6f390fdcf746b87"></a><!-- doxytag: member="dwc_otg_hcd_linux.c::allocate_bus_bandwidth" ref="e270a6a091a674ccf6f390fdcf746b87" args="(struct usb_hcd *hcd, uint32_t bw, struct urb *urb)" -->
+static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__linux_8c.html#e270a6a091a674ccf6f390fdcf746b87">allocate_bus_bandwidth</a> (struct usb_hcd *hcd, uint32_t bw, struct urb *urb)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="53fcd6fb7b833323112e8856070e88d8"></a><!-- doxytag: member="dwc_otg_hcd_linux.c::free_bus_bandwidth" ref="53fcd6fb7b833323112e8856070e88d8" args="(struct usb_hcd *hcd, uint32_t bw, struct urb *urb)" -->
+static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__linux_8c.html#53fcd6fb7b833323112e8856070e88d8">free_bus_bandwidth</a> (struct usb_hcd *hcd, uint32_t bw, struct urb *urb)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__linux_8c.html#a0d18986574c384e98aa280e0475a9aa">_complete</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, void *urb_handle, <a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *dwc_otg_urb, int32_t status)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Sets the final status of an URB and returns it to the device driver.  <a href="#a0d18986574c384e98aa280e0475a9aa"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__linux_8c.html#ab12cdf65bf4ed68545a6c17cc31269f">hcd_init</a> ()</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Initializes the HCD.  <a href="#ab12cdf65bf4ed68545a6c17cc31269f"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__linux_8c.html#f36193b3ff33c0473956c8a15eee4f5b">hcd_remove</a> ()</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Removes the HCD.  <a href="#f36193b3ff33c0473956c8a15eee4f5b"></a><br></td></tr>
+<tr><td colspan="2"><br><h2>Variables</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="41b49c86957a3835934c2f26fee377df"></a><!-- doxytag: member="dwc_otg_hcd_linux.c::dwc_otg_hcd_name" ref="41b49c86957a3835934c2f26fee377df" args="[]" -->
+static const char&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__linux_8c.html#41b49c86957a3835934c2f26fee377df">dwc_otg_hcd_name</a> [] = &quot;dwc_otg_hcd&quot;</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static struct hc_driver&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__linux_8c.html#ab1d492c360b963d179798f2641c02a5">dwc_otg_hc_driver</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static struct <a class="el" href="structdwc__otg__hcd__function__ops.html">dwc_otg_hcd_function_ops</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__linux_8c.html#430ee3db85940ea34a1702a37fbfb942">hcd_fops</a></td></tr>
+
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This file contains the implementation of the HCD. 
+<p>
+In Linux, the HCD implements the hc_driver API. 
+<p>
+Definition in file <a class="el" href="dwc__otg__hcd__linux_8c-source.html">dwc_otg_hcd_linux.c</a>.<hr><h2>Define Documentation</h2>
+<a class="anchor" name="4a327046464cd55f8abafc4af8ef74aa"></a><!-- doxytag: member="dwc_otg_hcd_linux.c::dwc_ep_addr_to_endpoint" ref="4a327046464cd55f8abafc4af8ef74aa" args="(_bEndpointAddress_)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define dwc_ep_addr_to_endpoint          </td>
+          <td>(</td>
+          <td class="paramtype">_bEndpointAddress_&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment">((_bEndpointAddress_ &amp; USB_ENDPOINT_NUMBER_MASK) | \
+                                                     ((_bEndpointAddress_ &amp; USB_DIR_IN) != 0) &lt;&lt; 4)
+</pre></div>Gets the endpoint number from a _bEndpointAddress argument. 
+<p>
+The endpoint is qualified with its direction (possible 32 endpoints per device). 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__linux_8c-source.html#l00071">71</a> of file <a class="el" href="dwc__otg__hcd__linux_8c-source.html">dwc_otg_hcd_linux.c</a>.
+</div>
+</div><p>
+<hr><h2>Function Documentation</h2>
+<a class="anchor" name="d9e9c76f2bc1c4f662d132c710a95a60"></a><!-- doxytag: member="dwc_otg_hcd_linux.c::urb_enqueue" ref="d9e9c76f2bc1c4f662d132c710a95a60" args="(struct usb_hcd *hcd, struct usb_host_endpoint *ep, struct urb *urb, gfp_t mem_flags)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static int urb_enqueue           </td>
+          <td>(</td>
+          <td class="paramtype">struct usb_hcd *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">struct usb_host_endpoint *&nbsp;</td>
+          <td class="paramname"> <em>ep</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">struct urb *&nbsp;</td>
+          <td class="paramname"> <em>urb</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">gfp_t&nbsp;</td>
+          <td class="paramname"> <em>mem_flags</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Starts processing a USB transfer request specified by a USB Request Block (URB). 
+<p>
+mem_flags indicates the type of memory allocation to use while processing this URB. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__linux_8c-source.html#l00562">562</a> of file <a class="el" href="dwc__otg__hcd__linux_8c-source.html">dwc_otg_hcd_linux.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="afc1f3d92fd7596140c0068bc96034f7"></a><!-- doxytag: member="dwc_otg_hcd_linux.c::urb_dequeue" ref="afc1f3d92fd7596140c0068bc96034f7" args="(struct usb_hcd *hcd, struct urb *urb)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static int urb_dequeue           </td>
+          <td>(</td>
+          <td class="paramtype">struct usb_hcd *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">struct urb *&nbsp;</td>
+          <td class="paramname"> <em>urb</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Aborts/cancels a USB transfer request. 
+<p>
+Always returns 0 to indicate success. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__linux_8c-source.html#l00667">667</a> of file <a class="el" href="dwc__otg__hcd__linux_8c-source.html">dwc_otg_hcd_linux.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="1e911926e9d51d6d9d11f11b81da8c3d"></a><!-- doxytag: member="dwc_otg_hcd_linux.c::dwc_otg_hcd_irq" ref="1e911926e9d51d6d9d11f11b81da8c3d" args="(struct usb_hcd *hcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static irqreturn_t dwc_otg_hcd_irq           </td>
+          <td>(</td>
+          <td class="paramtype">struct usb_hcd *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Handles host mode interrupts for the DWC_otg controller. 
+<p>
+Returns IRQ_NONE if there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid interrupt.<p>
+This function is called by the USB core when an interrupt occurs 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__linux_8c-source.html#l00714">714</a> of file <a class="el" href="dwc__otg__hcd__linux_8c-source.html">dwc_otg_hcd_linux.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="5d7f9da64cfeb32895d6c3d1366d45cf"></a><!-- doxytag: member="dwc_otg_hcd_linux.c::hcd_start" ref="5d7f9da64cfeb32895d6c3d1366d45cf" args="(struct usb_hcd *hcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int hcd_start           </td>
+          <td>(</td>
+          <td class="paramtype">struct usb_hcd *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Initializes the DWC_otg controller and its root hub and prepares it for host mode operation. 
+<p>
+Activates the root port. Returns 0 on success and a negative error code on failure. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__linux_8c-source.html#l00469">469</a> of file <a class="el" href="dwc__otg__hcd__linux_8c-source.html">dwc_otg_hcd_linux.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="cbb6a9e932a0baf80d1fdb013ac5d679"></a><!-- doxytag: member="dwc_otg_hcd_linux.c::hcd_stop" ref="cbb6a9e932a0baf80d1fdb013ac5d679" args="(struct usb_hcd *hcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void hcd_stop           </td>
+          <td>(</td>
+          <td class="paramtype">struct usb_hcd *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Halts the DWC_otg host mode operations in a clean manner. 
+<p>
+USB transfers are stopped. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__linux_8c-source.html#l00496">496</a> of file <a class="el" href="dwc__otg__hcd__linux_8c-source.html">dwc_otg_hcd_linux.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="108442f4aa4dc4663d8659241ed04e9c"></a><!-- doxytag: member="dwc_otg_hcd_linux.c::hub_status_data" ref="108442f4aa4dc4663d8659241ed04e9c" args="(struct usb_hcd *hcd, char *buf)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int hub_status_data           </td>
+          <td>(</td>
+          <td class="paramtype">struct usb_hcd *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">char *&nbsp;</td>
+          <td class="paramname"> <em>buf</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Creates Status Change bitmap for the root hub and root port. 
+<p>
+The bitmap is returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1 is the status change indicator for the single root port. Returns 1 if either change indicator is 1, otherwise returns 0. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__linux_8c-source.html#l00728">728</a> of file <a class="el" href="dwc__otg__hcd__linux_8c-source.html">dwc_otg_hcd_linux.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="a0d18986574c384e98aa280e0475a9aa"></a><!-- doxytag: member="dwc_otg_hcd_linux.c::_complete" ref="a0d18986574c384e98aa280e0475a9aa" args="(dwc_otg_hcd_t *hcd, void *urb_handle, dwc_otg_hcd_urb_t *dwc_otg_urb, int32_t status)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static int _complete           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>urb_handle</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>dwc_otg_urb</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&nbsp;</td>
+          <td class="paramname"> <em>status</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Sets the final status of an URB and returns it to the device driver. 
+<p>
+Any required cleanup of the URB is performed. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__linux_8c-source.html#l00224">224</a> of file <a class="el" href="dwc__otg__hcd__linux_8c-source.html">dwc_otg_hcd_linux.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="ab12cdf65bf4ed68545a6c17cc31269f"></a><!-- doxytag: member="dwc_otg_hcd_linux.c::hcd_init" ref="ab12cdf65bf4ed68545a6c17cc31269f" args="()" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int hcd_init           </td>
+          <td>(</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Initializes the HCD. 
+<p>
+This function allocates memory for and initializes the static parts of the usb_hcd and <a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd</a> structures. It also registers the USB bus with the core and calls the hc_driver-&gt;start() function. It returns a negative error on failure. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__linux_8c-source.html#l00327">327</a> of file <a class="el" href="dwc__otg__hcd__linux_8c-source.html">dwc_otg_hcd_linux.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="f36193b3ff33c0473956c8a15eee4f5b"></a><!-- doxytag: member="dwc_otg_hcd_linux.c::hcd_remove" ref="f36193b3ff33c0473956c8a15eee4f5b" args="()" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void hcd_remove           </td>
+          <td>(</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Removes the HCD. 
+<p>
+Frees memory and resources associated with the HCD and deregisters the bus. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__linux_8c-source.html#l00417">417</a> of file <a class="el" href="dwc__otg__hcd__linux_8c-source.html">dwc_otg_hcd_linux.c</a>.
+</div>
+</div><p>
+<hr><h2>Variable Documentation</h2>
+<a class="anchor" name="ab1d492c360b963d179798f2641c02a5"></a><!-- doxytag: member="dwc_otg_hcd_linux.c::dwc_otg_hc_driver" ref="ab1d492c360b963d179798f2641c02a5" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">struct hc_driver <a class="el" href="dwc__otg__hcd__linux_8c.html#ab1d492c360b963d179798f2641c02a5">dwc_otg_hc_driver</a><code> [static]</code>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Initial value:</b><div class="fragment"><pre class="fragment"> {
+
+        .description = <a class="code" href="dwc__otg__hcd__linux_8c.html#41b49c86957a3835934c2f26fee377df">dwc_otg_hcd_name</a>,
+        .product_desc = <span class="stringliteral">"DWC OTG Controller"</span>,
+        .hcd_priv_size = <span class="keyword">sizeof</span>(<span class="keyword">struct </span><a class="code" href="structwrapper__priv__data.html">wrapper_priv_data</a>),
+
+        .irq = <a class="code" href="dwc__otg__hcd__linux_8c.html#1e911926e9d51d6d9d11f11b81da8c3d">dwc_otg_hcd_irq</a>,
+
+        .flags = HCD_MEMORY | HCD_USB2,
+
+        
+        .start = <a class="code" href="dwc__otg__cil__intr_8c.html#fc2d933cd662b3d060747004c79203a1">hcd_start</a>,
+        
+        
+        .stop = <a class="code" href="dwc__otg__cil__intr_8c.html#b2721d01cc389181470095955b4e0994">hcd_stop</a>,
+
+        .urb_enqueue = <a class="code" href="dwc__otg__hcd__linux_8c.html#d9e9c76f2bc1c4f662d132c710a95a60">urb_enqueue</a>,
+        .urb_dequeue = <a class="code" href="dwc__otg__hcd__linux_8c.html#afc1f3d92fd7596140c0068bc96034f7">urb_dequeue</a>,
+        .endpoint_disable = <a class="code" href="dwc__otg__hcd__linux_8c.html#0aefc084c4c334dac85c95a43e8942c6">endpoint_disable</a>,
+
+        .get_frame_number = <a class="code" href="dwc__otg__hcd__linux_8c.html#c78128edb8902dc96534c5bb253f99a3">get_frame_number</a>,
+
+        .hub_status_data = <a class="code" href="dwc__otg__hcd__linux_8c.html#108442f4aa4dc4663d8659241ed04e9c">hub_status_data</a>,
+        .hub_control = <a class="code" href="dwc__otg__hcd__linux_8c.html#55d196cab99083dabdacdee78dc5e339">hub_control</a>,
+        
+        
+}
+</pre></div>
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__linux_8c-source.html#l00101">101</a> of file <a class="el" href="dwc__otg__hcd__linux_8c-source.html">dwc_otg_hcd_linux.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="430ee3db85940ea34a1702a37fbfb942"></a><!-- doxytag: member="dwc_otg_hcd_linux.c::hcd_fops" ref="430ee3db85940ea34a1702a37fbfb942" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">struct <a class="el" href="structdwc__otg__hcd__function__ops.html">dwc_otg_hcd_function_ops</a> <a class="el" href="dwc__otg__hcd__linux_8c.html#430ee3db85940ea34a1702a37fbfb942">hcd_fops</a><code> [static]</code>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Initial value:</b><div class="fragment"><pre class="fragment"> {
+        .start = <a class="code" href="dwc__otg__hcd__linux_8c.html#e11ebd665a86e6ec3fd661965acca90e">_start</a>,
+        .disconnect = <a class="code" href="dwc__otg__hcd__linux_8c.html#8011f9b662a7f4182e762de616bbc95e">_disconnect</a>,
+        .hub_info = <a class="code" href="dwc__otg__hcd__linux_8c.html#f4fe5a6082e7cce809f3e2a4cb71a7e4">_hub_info</a>,
+        .speed = <a class="code" href="dwc__otg__hcd__linux_8c.html#22cff3e20b45ec02e81e54a1adacfa20">_speed</a>,
+        .complete = <a class="code" href="dwc__otg__hcd__linux_8c.html#a0d18986574c384e98aa280e0475a9aa">_complete</a>,
+        .get_b_hnp_enable = <a class="code" href="dwc__otg__hcd__linux_8c.html#578b76a201e8e722e31afdcd2c35dac9">_get_b_hnp_enable</a>,
+}
+</pre></div>
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__linux_8c-source.html#l00312">312</a> of file <a class="el" href="dwc__otg__hcd__linux_8c-source.html">dwc_otg_hcd_linux.c</a>.
+</div>
+</div><p>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__queue_8c-source.html b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__queue_8c-source.html
new file mode 100644
index 000000000000..f6d0b56f75f2
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__queue_8c-source.html
@@ -0,0 +1,633 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd_queue.c Source File</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<h1>dwc_otg_hcd_queue.c</h1><a href="dwc__otg__hcd__queue_8c.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">/* ==========================================================================</span>
+<a name="l00002"></a>00002 <span class="comment"> * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_queue.c $</span>
+<a name="l00003"></a>00003 <span class="comment"> * $Revision: #39 $</span>
+<a name="l00004"></a>00004 <span class="comment"> * $Date: 2009/04/21 $</span>
+<a name="l00005"></a>00005 <span class="comment"> * $Change: 1237477 $</span>
+<a name="l00006"></a>00006 <span class="comment"> *</span>
+<a name="l00007"></a>00007 <span class="comment"> * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,</span>
+<a name="l00008"></a>00008 <span class="comment"> * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless</span>
+<a name="l00009"></a>00009 <span class="comment"> * otherwise expressly agreed to in writing between Synopsys and you.</span>
+<a name="l00010"></a>00010 <span class="comment"> * </span>
+<a name="l00011"></a>00011 <span class="comment"> * The Software IS NOT an item of Licensed Software or Licensed Product under</span>
+<a name="l00012"></a>00012 <span class="comment"> * any End User Software License Agreement or Agreement for Licensed Product</span>
+<a name="l00013"></a>00013 <span class="comment"> * with Synopsys or any supplement thereto. You are permitted to use and</span>
+<a name="l00014"></a>00014 <span class="comment"> * redistribute this Software in source and binary forms, with or without</span>
+<a name="l00015"></a>00015 <span class="comment"> * modification, provided that redistributions of source code must retain this</span>
+<a name="l00016"></a>00016 <span class="comment"> * notice. You may not view, use, disclose, copy or distribute this file or</span>
+<a name="l00017"></a>00017 <span class="comment"> * any information contained herein except pursuant to this license grant from</span>
+<a name="l00018"></a>00018 <span class="comment"> * Synopsys. If you do not agree with this notice, including the disclaimer</span>
+<a name="l00019"></a>00019 <span class="comment"> * below, then you are not authorized to use the Software.</span>
+<a name="l00020"></a>00020 <span class="comment"> * </span>
+<a name="l00021"></a>00021 <span class="comment"> * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS</span>
+<a name="l00022"></a>00022 <span class="comment"> * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE</span>
+<a name="l00023"></a>00023 <span class="comment"> * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE</span>
+<a name="l00024"></a>00024 <span class="comment"> * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,</span>
+<a name="l00025"></a>00025 <span class="comment"> * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES</span>
+<a name="l00026"></a>00026 <span class="comment"> * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR</span>
+<a name="l00027"></a>00027 <span class="comment"> * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER</span>
+<a name="l00028"></a>00028 <span class="comment"> * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT</span>
+<a name="l00029"></a>00029 <span class="comment"> * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY</span>
+<a name="l00030"></a>00030 <span class="comment"> * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH</span>
+<a name="l00031"></a>00031 <span class="comment"> * DAMAGE.</span>
+<a name="l00032"></a>00032 <span class="comment"> * ========================================================================== */</span>
+<a name="l00033"></a>00033 <span class="preprocessor">#ifndef DWC_DEVICE_ONLY</span>
+<a name="l00034"></a>00034 <span class="preprocessor"></span>
+<a name="l00042"></a>00042 <span class="preprocessor">#include "<a class="code" href="dwc__otg__hcd_8h.html">dwc_otg_hcd.h</a>"</span>
+<a name="l00043"></a>00043 <span class="preprocessor">#include "<a class="code" href="dwc__otg__regs_8h.html">dwc_otg_regs.h</a>"</span>
+<a name="l00044"></a>00044 
+<a name="l00053"></a><a class="code" href="dwc__otg__hcd__queue_8c.html#1ac731c0691ac3851edddc558fae79e0">00053</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd_8h.html#1ac731c0691ac3851edddc558fae79e0">dwc_otg_hcd_qh_free</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd, <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> * qh)
+<a name="l00054"></a>00054 {
+<a name="l00055"></a>00055         <a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *qtd, *qtd_tmp;
+<a name="l00056"></a>00056         uint64_t flags;
+<a name="l00057"></a>00057 
+<a name="l00058"></a>00058         <span class="comment">/* Free each QTD in the QTD list */</span>
+<a name="l00059"></a>00059         DWC_SPINLOCK_IRQSAVE(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#34f29e9c035009476495f7701c1813fd">lock</a>, &amp;flags);
+<a name="l00060"></a>00060         DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &amp;qh-&gt;<a class="code" href="structdwc__otg__qh.html#9567d266da8e796d3467fb16ae867f8e">qtd_list</a>, qtd_list_entry) {
+<a name="l00061"></a>00061                 DWC_CIRCLEQ_REMOVE(&amp;qh-&gt;<a class="code" href="structdwc__otg__qh.html#9567d266da8e796d3467fb16ae867f8e">qtd_list</a>, qtd, qtd_list_entry);
+<a name="l00062"></a>00062                 <a class="code" href="dwc__otg__hcd_8h.html#34434d836361462c04fb45ba9ab89fb9">dwc_otg_hcd_qtd_free</a>(qtd);
+<a name="l00063"></a>00063         }
+<a name="l00064"></a>00064         DWC_SPINUNLOCK_IRQRESTORE(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#34f29e9c035009476495f7701c1813fd">lock</a>, flags);
+<a name="l00065"></a>00065 
+<a name="l00066"></a>00066         <span class="keywordflow">if</span> (hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a>) {
+<a name="l00067"></a>00067                 <a class="code" href="dwc__otg__hcd_8h.html#78738afd0ca62e394753f1cf196476c9">dwc_otg_hcd_qh_free_ddma</a>(hcd, qh);
+<a name="l00068"></a>00068         }
+<a name="l00069"></a>00069         <span class="keywordflow">else</span> <span class="keywordflow">if</span> (qh-&gt;<a class="code" href="structdwc__otg__qh.html#aac9f90a6afd9056dce79d013dd2168b">dw_align_buf</a>) {
+<a name="l00070"></a>00070                 uint32_t buf_size;
+<a name="l00071"></a>00071                 <span class="keywordflow">if</span>(qh-&gt;<a class="code" href="structdwc__otg__qh.html#98b78ffd8dbc01be44b302e873e73a82">ep_type</a> == UE_ISOCHRONOUS) {
+<a name="l00072"></a>00072                         buf_size = 4096;
+<a name="l00073"></a>00073                 } <span class="keywordflow">else</span> {
+<a name="l00074"></a>00074                         buf_size = hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#e614d1d2ee740cd972ca76ed0dffec74">max_transfer_size</a>;
+<a name="l00075"></a>00075                 }
+<a name="l00076"></a>00076                 dwc_dma_free(buf_size, qh-&gt;<a class="code" href="structdwc__otg__qh.html#aac9f90a6afd9056dce79d013dd2168b">dw_align_buf</a>, qh-&gt;<a class="code" href="structdwc__otg__qh.html#b0b008f9d25f5e3b6e285d2830cfdca1">dw_align_buf_dma</a>);
+<a name="l00077"></a>00077         }
+<a name="l00078"></a>00078         
+<a name="l00079"></a>00079         
+<a name="l00080"></a>00080         
+<a name="l00081"></a>00081         dwc_free(qh);
+<a name="l00082"></a>00082         <span class="keywordflow">return</span>;
+<a name="l00083"></a>00083 }
+<a name="l00084"></a>00084 
+<a name="l00085"></a><a class="code" href="dwc__otg__hcd__queue_8c.html#e740bef95f7929a07065b699f6f087a2">00085</a> <span class="preprocessor">#define BitStuffTime(bytecount)  ((8 * 7* bytecount) / 6)</span>
+<a name="l00086"></a><a class="code" href="dwc__otg__hcd__queue_8c.html#2a974c684e456c20cc2d9bceb2e71a11">00086</a> <span class="preprocessor"></span><span class="preprocessor">#define HS_HOST_DELAY           5       </span><span class="comment">/* nanoseconds */</span>
+<a name="l00087"></a><a class="code" href="dwc__otg__hcd__queue_8c.html#8f9875d35aace115a340d2cef9c66294">00087</a> <span class="preprocessor">#define FS_LS_HOST_DELAY        1000    </span><span class="comment">/* nanoseconds */</span>
+<a name="l00088"></a><a class="code" href="dwc__otg__hcd__queue_8c.html#d596163a6f24db7fb4ee092a933e03a2">00088</a> <span class="preprocessor">#define HUB_LS_SETUP            333     </span><span class="comment">/* nanoseconds */</span>
+<a name="l00089"></a><a class="code" href="dwc__otg__hcd__queue_8c.html#1df143acbaa5817cd09c8cca89851747">00089</a> <span class="preprocessor">#define NS_TO_US(ns)            ((ns + 500) / 1000)</span>
+<a name="l00090"></a>00090 <span class="preprocessor"></span>                                <span class="comment">/* convert &amp; round nanoseconds to microseconds */</span>
+<a name="l00091"></a>00091 
+<a name="l00092"></a><a class="code" href="dwc__otg__hcd__queue_8c.html#49a9d4aa15e01fc07d68826bd05c0f4d">00092</a> <span class="keyword">static</span> uint32_t <a class="code" href="dwc__otg__hcd__queue_8c.html#49a9d4aa15e01fc07d68826bd05c0f4d">calc_bus_time</a>(<span class="keywordtype">int</span> speed, <span class="keywordtype">int</span> is_in, <span class="keywordtype">int</span> is_isoc,
+<a name="l00093"></a>00093                                           <span class="keywordtype">int</span> bytecount)
+<a name="l00094"></a>00094 {
+<a name="l00095"></a>00095         <span class="keywordtype">unsigned</span> <span class="keywordtype">long</span> retval;
+<a name="l00096"></a>00096 
+<a name="l00097"></a>00097         <span class="keywordflow">switch</span> (speed) {
+<a name="l00098"></a>00098         <span class="keywordflow">case</span> USB_SPEED_HIGH:
+<a name="l00099"></a>00099                 <span class="keywordflow">if</span> (is_isoc) {
+<a name="l00100"></a>00100                         retval =
+<a name="l00101"></a>00101                             ((38 * 8 * 2083) +
+<a name="l00102"></a>00102                              (2083 * (3 + <a class="code" href="dwc__otg__hcd__queue_8c.html#e740bef95f7929a07065b699f6f087a2">BitStuffTime</a>(bytecount)))) / 1000 +
+<a name="l00103"></a>00103                             <a class="code" href="dwc__otg__hcd__queue_8c.html#2a974c684e456c20cc2d9bceb2e71a11">HS_HOST_DELAY</a>;
+<a name="l00104"></a>00104                 } <span class="keywordflow">else</span> {
+<a name="l00105"></a>00105                         retval =
+<a name="l00106"></a>00106                             ((55 * 8 * 2083) +
+<a name="l00107"></a>00107                              (2083 * (3 + <a class="code" href="dwc__otg__hcd__queue_8c.html#e740bef95f7929a07065b699f6f087a2">BitStuffTime</a>(bytecount)))) / 1000 +
+<a name="l00108"></a>00108                             <a class="code" href="dwc__otg__hcd__queue_8c.html#2a974c684e456c20cc2d9bceb2e71a11">HS_HOST_DELAY</a>;
+<a name="l00109"></a>00109                 }
+<a name="l00110"></a>00110                 <span class="keywordflow">break</span>;
+<a name="l00111"></a>00111         <span class="keywordflow">case</span> USB_SPEED_FULL:
+<a name="l00112"></a>00112                 <span class="keywordflow">if</span> (is_isoc) {
+<a name="l00113"></a>00113                         retval =
+<a name="l00114"></a>00114                             (8354 * (31 + 10 * <a class="code" href="dwc__otg__hcd__queue_8c.html#e740bef95f7929a07065b699f6f087a2">BitStuffTime</a>(bytecount))) / 1000;
+<a name="l00115"></a>00115                         <span class="keywordflow">if</span> (is_in) {
+<a name="l00116"></a>00116                                 retval = 7268 + <a class="code" href="dwc__otg__hcd__queue_8c.html#8f9875d35aace115a340d2cef9c66294">FS_LS_HOST_DELAY</a> + retval;
+<a name="l00117"></a>00117                         } <span class="keywordflow">else</span> {
+<a name="l00118"></a>00118                                 retval = 6265 + <a class="code" href="dwc__otg__hcd__queue_8c.html#8f9875d35aace115a340d2cef9c66294">FS_LS_HOST_DELAY</a> + retval;
+<a name="l00119"></a>00119                         }
+<a name="l00120"></a>00120                 } <span class="keywordflow">else</span> {
+<a name="l00121"></a>00121                         retval =
+<a name="l00122"></a>00122                             (8354 * (31 + 10 * <a class="code" href="dwc__otg__hcd__queue_8c.html#e740bef95f7929a07065b699f6f087a2">BitStuffTime</a>(bytecount))) / 1000;
+<a name="l00123"></a>00123                         retval = 9107 + <a class="code" href="dwc__otg__hcd__queue_8c.html#8f9875d35aace115a340d2cef9c66294">FS_LS_HOST_DELAY</a> + retval;
+<a name="l00124"></a>00124                 }
+<a name="l00125"></a>00125                 <span class="keywordflow">break</span>;
+<a name="l00126"></a>00126         <span class="keywordflow">case</span> USB_SPEED_LOW:
+<a name="l00127"></a>00127                 <span class="keywordflow">if</span> (is_in) {
+<a name="l00128"></a>00128                         retval =
+<a name="l00129"></a>00129                             (67667 * (31 + 10 * <a class="code" href="dwc__otg__hcd__queue_8c.html#e740bef95f7929a07065b699f6f087a2">BitStuffTime</a>(bytecount))) /
+<a name="l00130"></a>00130                             1000;
+<a name="l00131"></a>00131                         retval =
+<a name="l00132"></a>00132                             64060 + (2 * <a class="code" href="dwc__otg__hcd__queue_8c.html#d596163a6f24db7fb4ee092a933e03a2">HUB_LS_SETUP</a>) + <a class="code" href="dwc__otg__hcd__queue_8c.html#8f9875d35aace115a340d2cef9c66294">FS_LS_HOST_DELAY</a> +
+<a name="l00133"></a>00133                             retval;
+<a name="l00134"></a>00134                 } <span class="keywordflow">else</span> {
+<a name="l00135"></a>00135                         retval =
+<a name="l00136"></a>00136                             (66700 * (31 + 10 * <a class="code" href="dwc__otg__hcd__queue_8c.html#e740bef95f7929a07065b699f6f087a2">BitStuffTime</a>(bytecount))) /
+<a name="l00137"></a>00137                             1000;
+<a name="l00138"></a>00138                         retval =
+<a name="l00139"></a>00139                             64107 + (2 * <a class="code" href="dwc__otg__hcd__queue_8c.html#d596163a6f24db7fb4ee092a933e03a2">HUB_LS_SETUP</a>) + <a class="code" href="dwc__otg__hcd__queue_8c.html#8f9875d35aace115a340d2cef9c66294">FS_LS_HOST_DELAY</a> +
+<a name="l00140"></a>00140                             retval;
+<a name="l00141"></a>00141                 }
+<a name="l00142"></a>00142                 <span class="keywordflow">break</span>;
+<a name="l00143"></a>00143         <span class="keywordflow">default</span>:
+<a name="l00144"></a>00144                 DWC_WARN(<span class="stringliteral">"Unknown device speed\n"</span>);
+<a name="l00145"></a>00145                 retval = -1;
+<a name="l00146"></a>00146         }
+<a name="l00147"></a>00147         
+<a name="l00148"></a>00148         <span class="keywordflow">return</span> <a class="code" href="dwc__otg__hcd__queue_8c.html#1df143acbaa5817cd09c8cca89851747">NS_TO_US</a>(retval);
+<a name="l00149"></a>00149 }
+<a name="l00150"></a>00150 
+<a name="l00159"></a><a class="code" href="dwc__otg__hcd__queue_8c.html#86d31a59a5f7c095cd183a06edeed5e1">00159</a> <span class="preprocessor">#define SCHEDULE_SLOP 10</span>
+<a name="l00160"></a><a class="code" href="dwc__otg__hcd__queue_8c.html#d32f8a4be67b758e9541e33746363677">00160</a> <span class="preprocessor"></span><span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd__queue_8c.html#d32f8a4be67b758e9541e33746363677">qh_init</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd, <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> * qh,
+<a name="l00161"></a>00161                          <a class="code" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> * urb)
+<a name="l00162"></a>00162 {
+<a name="l00163"></a>00163         <span class="keywordtype">char</span> *speed, *type;
+<a name="l00164"></a>00164         <span class="keywordtype">int</span> dev_speed;
+<a name="l00165"></a>00165         uint32_t hub_addr, hub_port;
+<a name="l00166"></a>00166 
+<a name="l00167"></a>00167         dwc_memset(qh, 0, <span class="keyword">sizeof</span>(<a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a>));
+<a name="l00168"></a>00168         
+<a name="l00169"></a>00169         <span class="comment">/* Initialize QH */</span>
+<a name="l00170"></a>00170         qh-&gt;<a class="code" href="structdwc__otg__qh.html#98b78ffd8dbc01be44b302e873e73a82">ep_type</a> = <a class="code" href="dwc__otg__hcd_8h.html#b97cea598797e69d011ffef89989a739">dwc_otg_hcd_get_pipe_type</a>(&amp;urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#34ee3ac5931687b41dd726f00c558369">pipe_info</a>);
+<a name="l00171"></a>00171 
+<a name="l00172"></a>00172         qh-&gt;<a class="code" href="structdwc__otg__qh.html#2dc622878a6617e5c803061804d5cf9f">ep_is_in</a> = <a class="code" href="dwc__otg__hcd_8h.html#68de5629a8b45d9bec58f680fa4c820c">dwc_otg_hcd_is_pipe_in</a>(&amp;urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#34ee3ac5931687b41dd726f00c558369">pipe_info</a>) ? 1 : 0;
+<a name="l00173"></a>00173 
+<a name="l00174"></a>00174         qh-&gt;<a class="code" href="structdwc__otg__qh.html#b0e001bfd76f5781926795ac47ef2c25">data_toggle</a> = <a class="code" href="dwc__otg__cil_8h.html#0e843d08e80c29e82962ce9170a02a52">DWC_OTG_HC_PID_DATA0</a>;
+<a name="l00175"></a>00175         qh-&gt;<a class="code" href="structdwc__otg__qh.html#5975c2bede1ca0c6cfe9a66fe0a52567">maxp</a> = <a class="code" href="dwc__otg__hcd_8h.html#e47df3e0ac1c8ccc916e0c0895568c88">dwc_otg_hcd_get_mps</a>(&amp;urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#34ee3ac5931687b41dd726f00c558369">pipe_info</a>);
+<a name="l00176"></a>00176         DWC_CIRCLEQ_INIT(&amp;qh-&gt;<a class="code" href="structdwc__otg__qh.html#9567d266da8e796d3467fb16ae867f8e">qtd_list</a>);
+<a name="l00177"></a>00177         DWC_LIST_INIT(&amp;qh-&gt;<a class="code" href="structdwc__otg__qh.html#3e1cb9863dc72139e1832c04244c25ff">qh_list_entry</a>);
+<a name="l00178"></a>00178         qh-&gt;<a class="code" href="structdwc__otg__qh.html#bbdb7d30b60b6c326301f33b35088bb4">channel</a> = NULL;
+<a name="l00179"></a>00179 
+<a name="l00180"></a>00180         <span class="comment">/* FS/LS Enpoint on HS Hub </span>
+<a name="l00181"></a>00181 <span class="comment">         * NOT virtual root hub */</span>
+<a name="l00182"></a>00182         dev_speed = hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#ffefbd33a59a14b8b46406f5aaeaa2f4">fops</a>-&gt;<a class="code" href="structdwc__otg__hcd__function__ops.html#29f9b98c1a824637a5c8aec86649fdd4">speed</a>(hcd, urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#5ba0e393ef9768275db85c00e68be477">priv</a>);
+<a name="l00183"></a>00183         hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#ffefbd33a59a14b8b46406f5aaeaa2f4">fops</a>-&gt;<a class="code" href="structdwc__otg__hcd__function__ops.html#71bff93886173700d26a8950e7ea82e1">hub_info</a>(hcd, urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#5ba0e393ef9768275db85c00e68be477">priv</a>, &amp;hub_addr, &amp;hub_port);
+<a name="l00184"></a>00184         qh-&gt;<a class="code" href="structdwc__otg__qh.html#8708dd009988ce20b8a8d52a4a96c5a3">do_split</a> = 0;
+<a name="l00185"></a>00185         <span class="keywordflow">if</span> (((dev_speed == USB_SPEED_LOW) ||
+<a name="l00186"></a>00186              (dev_speed == USB_SPEED_FULL)) &amp;&amp;
+<a name="l00187"></a>00187             (hub_addr != 0 &amp;&amp; hub_addr != 1)) {
+<a name="l00188"></a>00188                 
+<a name="l00189"></a>00189                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#e4a050e176c1c4f556da2b276a8c2b37">DBG_HCD</a>,
+<a name="l00190"></a>00190                             <span class="stringliteral">"QH init: EP %d: TT found at hub addr %d, for port %d\n"</span>,
+<a name="l00191"></a>00191                             <a class="code" href="dwc__otg__hcd_8h.html#367b79057f321cfa65023f4026d6c2c9">dwc_otg_hcd_get_ep_num</a>(&amp;urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#34ee3ac5931687b41dd726f00c558369">pipe_info</a>), hub_addr,
+<a name="l00192"></a>00192                             hub_port);
+<a name="l00193"></a>00193                 
+<a name="l00194"></a>00194                 qh-&gt;<a class="code" href="structdwc__otg__qh.html#8708dd009988ce20b8a8d52a4a96c5a3">do_split</a> = 1;
+<a name="l00195"></a>00195         }
+<a name="l00196"></a>00196 
+<a name="l00197"></a>00197         <span class="keywordflow">if</span> (qh-&gt;<a class="code" href="structdwc__otg__qh.html#98b78ffd8dbc01be44b302e873e73a82">ep_type</a> == UE_INTERRUPT || qh-&gt;<a class="code" href="structdwc__otg__qh.html#98b78ffd8dbc01be44b302e873e73a82">ep_type</a> == UE_ISOCHRONOUS) {
+<a name="l00198"></a>00198                 <span class="comment">/* Compute scheduling parameters once and save them. */</span>
+<a name="l00199"></a>00199                 <a class="code" href="unionhprt0__data.html">hprt0_data_t</a> hprt;
+<a name="l00200"></a>00200 
+<a name="l00202"></a>00202                 <span class="keywordtype">int</span> bytecount =
+<a name="l00203"></a>00203                     <a class="code" href="dwc__otg__hcd_8h.html#a371dfcb8a66214c8fe226190fc1a323">dwc_hb_mult</a>(qh-&gt;<a class="code" href="structdwc__otg__qh.html#5975c2bede1ca0c6cfe9a66fe0a52567">maxp</a>) * <a class="code" href="dwc__otg__hcd_8h.html#bd2189f881088fe7f4ca9112ee24549b">dwc_max_packet</a>(qh-&gt;<a class="code" href="structdwc__otg__qh.html#5975c2bede1ca0c6cfe9a66fe0a52567">maxp</a>);
+<a name="l00204"></a>00204 
+<a name="l00205"></a>00205                 qh-&gt;<a class="code" href="structdwc__otg__qh.html#401de6aadcfc2f99773f44c6731c4646">usecs</a> = <a class="code" href="dwc__otg__hcd__queue_8c.html#49a9d4aa15e01fc07d68826bd05c0f4d">calc_bus_time</a>((qh-&gt;<a class="code" href="structdwc__otg__qh.html#8708dd009988ce20b8a8d52a4a96c5a3">do_split</a> ? USB_SPEED_HIGH : dev_speed),
+<a name="l00206"></a>00206                                           qh-&gt;<a class="code" href="structdwc__otg__qh.html#2dc622878a6617e5c803061804d5cf9f">ep_is_in</a>,
+<a name="l00207"></a>00207                                           (qh-&gt;<a class="code" href="structdwc__otg__qh.html#98b78ffd8dbc01be44b302e873e73a82">ep_type</a> == UE_ISOCHRONOUS),
+<a name="l00208"></a>00208                                           bytecount);
+<a name="l00209"></a>00209                 <span class="comment">/* Start in a slightly future (micro)frame. */</span>
+<a name="l00210"></a>00210                 qh-&gt;<a class="code" href="structdwc__otg__qh.html#977a8032f08e45a9e9bdcd558a6965d3">sched_frame</a> = <a class="code" href="dwc__otg__hcd_8h.html#cb175759a6b2cd291eedc276c022b500">dwc_frame_num_inc</a>(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#f79fefeb7908c0ddf702331253acb292">frame_number</a>,
+<a name="l00211"></a>00211                                                     <a class="code" href="dwc__otg__hcd__queue_8c.html#86d31a59a5f7c095cd183a06edeed5e1">SCHEDULE_SLOP</a>);
+<a name="l00212"></a>00212                 qh-&gt;<a class="code" href="structdwc__otg__qh.html#cdbce86d457f0ea08e2efedc47c9b315">interval</a> = urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#49c5353377e2fb173f1b34ae7be7e257">interval</a>;
+<a name="l00213"></a>00213                 
+<a name="l00214"></a>00214 <span class="preprocessor">#if 0</span>
+<a name="l00215"></a>00215 <span class="preprocessor"></span>                <span class="comment">/* Increase interrupt polling rate for debugging. */</span>
+<a name="l00216"></a>00216                 <span class="keywordflow">if</span> (qh-&gt;<a class="code" href="structdwc__otg__qh.html#98b78ffd8dbc01be44b302e873e73a82">ep_type</a> == UE_INTERRUPT) {
+<a name="l00217"></a>00217                         qh-&gt;<a class="code" href="structdwc__otg__qh.html#cdbce86d457f0ea08e2efedc47c9b315">interval</a> = 8;
+<a name="l00218"></a>00218                 }
+<a name="l00219"></a>00219 <span class="preprocessor">#endif</span>
+<a name="l00220"></a>00220 <span class="preprocessor"></span>                hprt.<a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a> = dwc_read_reg32(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a>-&gt;<a class="code" href="structdwc__otg__host__if.html#dc8fe33e0bb3829cafa884d5fc603c4d">hprt0</a>);
+<a name="l00221"></a>00221                 <span class="keywordflow">if</span> ((hprt.<a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>.<a class="code" href="unionhprt0__data.html#59f1c27b8c912de0237d2d2974fc2a22">prtspd</a> == <a class="code" href="dwc__otg__regs_8h.html#4556f79078df2164a8162fa8144142a0">DWC_HPRT0_PRTSPD_HIGH_SPEED</a>) &amp;&amp;
+<a name="l00222"></a>00222                     ((dev_speed == USB_SPEED_LOW) ||
+<a name="l00223"></a>00223                      (dev_speed == USB_SPEED_FULL))) {
+<a name="l00224"></a>00224                         qh-&gt;<a class="code" href="structdwc__otg__qh.html#cdbce86d457f0ea08e2efedc47c9b315">interval</a> *= 8;
+<a name="l00225"></a>00225                         qh-&gt;<a class="code" href="structdwc__otg__qh.html#977a8032f08e45a9e9bdcd558a6965d3">sched_frame</a> |= 0x7;
+<a name="l00226"></a>00226                         qh-&gt;<a class="code" href="structdwc__otg__qh.html#a92b9ff45f0eca459b41ca20e4d8e99c">start_split_frame</a> = qh-&gt;<a class="code" href="structdwc__otg__qh.html#977a8032f08e45a9e9bdcd558a6965d3">sched_frame</a>;
+<a name="l00227"></a>00227                 }
+<a name="l00228"></a>00228 
+<a name="l00229"></a>00229         }
+<a name="l00230"></a>00230 
+<a name="l00231"></a>00231         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#e4a050e176c1c4f556da2b276a8c2b37">DBG_HCD</a>, <span class="stringliteral">"DWC OTG HCD QH Initialized\n"</span>);
+<a name="l00232"></a>00232         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"DWC OTG HCD QH  - qh = %p\n"</span>, qh);
+<a name="l00233"></a>00233         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"DWC OTG HCD QH  - Device Address = %d\n"</span>,
+<a name="l00234"></a>00234                     <a class="code" href="dwc__otg__hcd_8h.html#0de365358ba4472d56c1ac8074ba926b">dwc_otg_hcd_get_dev_addr</a>(&amp;urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#34ee3ac5931687b41dd726f00c558369">pipe_info</a>));
+<a name="l00235"></a>00235         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"DWC OTG HCD QH  - Endpoint %d, %s\n"</span>,
+<a name="l00236"></a>00236                     <a class="code" href="dwc__otg__hcd_8h.html#367b79057f321cfa65023f4026d6c2c9">dwc_otg_hcd_get_ep_num</a>(&amp;urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#34ee3ac5931687b41dd726f00c558369">pipe_info</a>),
+<a name="l00237"></a>00237                     <a class="code" href="dwc__otg__hcd_8h.html#68de5629a8b45d9bec58f680fa4c820c">dwc_otg_hcd_is_pipe_in</a>(&amp;urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#34ee3ac5931687b41dd726f00c558369">pipe_info</a>) ? <span class="stringliteral">"IN"</span> : <span class="stringliteral">"OUT"</span>);
+<a name="l00238"></a>00238         <span class="keywordflow">switch</span> (dev_speed) {
+<a name="l00239"></a>00239         <span class="keywordflow">case</span> USB_SPEED_LOW:
+<a name="l00240"></a>00240                 qh-&gt;<a class="code" href="structdwc__otg__qh.html#42459dd91e199807783000b6dc358a7d">dev_speed</a> = <a class="code" href="dwc__otg__cil_8h.html#1a25260b2e1a06850c26f7b7e5128f31">DWC_OTG_EP_SPEED_LOW</a>;
+<a name="l00241"></a>00241                 speed = <span class="stringliteral">"low"</span>;
+<a name="l00242"></a>00242                 <span class="keywordflow">break</span>;
+<a name="l00243"></a>00243         <span class="keywordflow">case</span> USB_SPEED_FULL:
+<a name="l00244"></a>00244                 qh-&gt;<a class="code" href="structdwc__otg__qh.html#42459dd91e199807783000b6dc358a7d">dev_speed</a> = <a class="code" href="dwc__otg__cil_8h.html#2ec9a7665a34074eedf1f40681d124ef">DWC_OTG_EP_SPEED_FULL</a>;
+<a name="l00245"></a>00245                 speed = <span class="stringliteral">"full"</span>;
+<a name="l00246"></a>00246                 <span class="keywordflow">break</span>;
+<a name="l00247"></a>00247         <span class="keywordflow">case</span> USB_SPEED_HIGH:
+<a name="l00248"></a>00248                 qh-&gt;<a class="code" href="structdwc__otg__qh.html#42459dd91e199807783000b6dc358a7d">dev_speed</a> = <a class="code" href="dwc__otg__cil_8h.html#b9dc03c6bc3c1113a935a73cf7021fbe">DWC_OTG_EP_SPEED_HIGH</a>;
+<a name="l00249"></a>00249                 speed = <span class="stringliteral">"high"</span>;
+<a name="l00250"></a>00250                 <span class="keywordflow">break</span>;
+<a name="l00251"></a>00251         <span class="keywordflow">default</span>:
+<a name="l00252"></a>00252                 speed = <span class="stringliteral">"?"</span>;
+<a name="l00253"></a>00253                 <span class="keywordflow">break</span>;
+<a name="l00254"></a>00254         }
+<a name="l00255"></a>00255         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"DWC OTG HCD QH  - Speed = %s\n"</span>, speed);
+<a name="l00256"></a>00256 
+<a name="l00257"></a>00257         <span class="keywordflow">switch</span> (qh-&gt;<a class="code" href="structdwc__otg__qh.html#98b78ffd8dbc01be44b302e873e73a82">ep_type</a>) {
+<a name="l00258"></a>00258         <span class="keywordflow">case</span> UE_ISOCHRONOUS:
+<a name="l00259"></a>00259                 type = <span class="stringliteral">"isochronous"</span>;
+<a name="l00260"></a>00260                 <span class="keywordflow">break</span>;
+<a name="l00261"></a>00261         <span class="keywordflow">case</span> UE_INTERRUPT:
+<a name="l00262"></a>00262                 type = <span class="stringliteral">"interrupt"</span>;
+<a name="l00263"></a>00263                 <span class="keywordflow">break</span>;
+<a name="l00264"></a>00264         <span class="keywordflow">case</span> UE_CONTROL:
+<a name="l00265"></a>00265                 type = <span class="stringliteral">"control"</span>;
+<a name="l00266"></a>00266                 <span class="keywordflow">break</span>;
+<a name="l00267"></a>00267         <span class="keywordflow">case</span> UE_BULK:
+<a name="l00268"></a>00268                 type = <span class="stringliteral">"bulk"</span>;
+<a name="l00269"></a>00269                 <span class="keywordflow">break</span>;
+<a name="l00270"></a>00270         <span class="keywordflow">default</span>:
+<a name="l00271"></a>00271                 type = <span class="stringliteral">"?"</span>;
+<a name="l00272"></a>00272                 <span class="keywordflow">break</span>;
+<a name="l00273"></a>00273         }
+<a name="l00274"></a>00274         
+<a name="l00275"></a>00275         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"DWC OTG HCD QH  - Type = %s\n"</span>, type);
+<a name="l00276"></a>00276 
+<a name="l00277"></a>00277 <span class="preprocessor">#ifdef DEBUG</span>
+<a name="l00278"></a>00278 <span class="preprocessor"></span>        <span class="keywordflow">if</span> (qh-&gt;<a class="code" href="structdwc__otg__qh.html#98b78ffd8dbc01be44b302e873e73a82">ep_type</a> == UE_INTERRUPT) {
+<a name="l00279"></a>00279                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">DBG_HCDV</a>, <span class="stringliteral">"DWC OTG HCD QH - usecs = %d\n"</span>,
+<a name="l00280"></a>00280                             qh-&gt;<a class="code" href="structdwc__otg__qh.html#401de6aadcfc2f99773f44c6731c4646">usecs</a>);
+<a name="l00281"></a>00281                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(DBG_HCDV, <span class="stringliteral">"DWC OTG HCD QH - interval = %d\n"</span>,
+<a name="l00282"></a>00282                             qh-&gt;<a class="code" href="structdwc__otg__qh.html#cdbce86d457f0ea08e2efedc47c9b315">interval</a>);
+<a name="l00283"></a>00283         }
+<a name="l00284"></a>00284 <span class="preprocessor">#endif</span>
+<a name="l00285"></a>00285 <span class="preprocessor"></span>
+<a name="l00286"></a>00286 }
+<a name="l00287"></a>00287 
+<a name="l00296"></a><a class="code" href="dwc__otg__hcd__queue_8c.html#187194b7a9f28e7f7a09ac3e345c7253">00296</a> <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *<a class="code" href="dwc__otg__hcd_8h.html#187194b7a9f28e7f7a09ac3e345c7253">dwc_otg_hcd_qh_create</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd,
+<a name="l00297"></a>00297                                     <a class="code" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> * urb)
+<a name="l00298"></a>00298 {
+<a name="l00299"></a>00299         <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *qh;
+<a name="l00300"></a>00300 
+<a name="l00301"></a>00301         <span class="comment">/* Allocate memory */</span>
+<a name="l00303"></a>00303         qh = <a class="code" href="dwc__otg__hcd_8h.html#3252be9fc489fbaa293b2404642caab0">dwc_otg_hcd_qh_alloc</a>();
+<a name="l00304"></a>00304         <span class="keywordflow">if</span> (qh == NULL) {
+<a name="l00305"></a>00305                 <span class="keywordflow">return</span> NULL;
+<a name="l00306"></a>00306         }
+<a name="l00307"></a>00307 
+<a name="l00308"></a>00308         <a class="code" href="dwc__otg__hcd__queue_8c.html#d32f8a4be67b758e9541e33746363677">qh_init</a>(hcd, qh, urb);
+<a name="l00309"></a>00309         
+<a name="l00310"></a>00310         <span class="keywordflow">if</span> (hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a> &amp;&amp; (<a class="code" href="dwc__otg__hcd_8h.html#1c5498d173c5461865a5042789927ed1">dwc_otg_hcd_qh_init_ddma</a>(hcd, qh) &lt; 0)) {
+<a name="l00311"></a>00311                 <a class="code" href="dwc__otg__hcd_8h.html#1ac731c0691ac3851edddc558fae79e0">dwc_otg_hcd_qh_free</a>(hcd, qh);   
+<a name="l00312"></a>00312                 <span class="keywordflow">return</span> NULL;
+<a name="l00313"></a>00313         }
+<a name="l00314"></a>00314         
+<a name="l00315"></a>00315         <span class="keywordflow">return</span> qh;
+<a name="l00316"></a>00316 }
+<a name="l00317"></a>00317 
+<a name="l00323"></a><a class="code" href="dwc__otg__hcd__queue_8c.html#debf9d35891234a74bc00832bba603bc">00323</a> <span class="keyword">static</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd__queue_8c.html#debf9d35891234a74bc00832bba603bc">periodic_channel_available</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd)
+<a name="l00324"></a>00324 {
+<a name="l00325"></a>00325         <span class="comment">/*</span>
+<a name="l00326"></a>00326 <span class="comment">         * Currently assuming that there is a dedicated host channnel for each</span>
+<a name="l00327"></a>00327 <span class="comment">         * periodic transaction plus at least one host channel for</span>
+<a name="l00328"></a>00328 <span class="comment">         * non-periodic transactions.</span>
+<a name="l00329"></a>00329 <span class="comment">         */</span>
+<a name="l00330"></a>00330         <span class="keywordtype">int</span> status;
+<a name="l00331"></a>00331         <span class="keywordtype">int</span> num_channels;
+<a name="l00332"></a>00332 
+<a name="l00333"></a>00333         num_channels = hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#c1b433c6965aa7d48f6ca6818c592039">host_channels</a>;
+<a name="l00334"></a>00334         <span class="keywordflow">if</span> ((hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#5754b87bd4644fbb7b90cf843c638f1c">periodic_channels</a> + hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e7fff26b5cce7c6c520c89f9e3c75617">non_periodic_channels</a> &lt; num_channels) &amp;&amp;
+<a name="l00335"></a>00335             (hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#5754b87bd4644fbb7b90cf843c638f1c">periodic_channels</a> &lt; num_channels - 1)) {
+<a name="l00336"></a>00336                 status = 0;
+<a name="l00337"></a>00337         } <span class="keywordflow">else</span> {
+<a name="l00338"></a>00338                 DWC_INFO(<span class="stringliteral">"%s: Total channels: %d, Periodic: %d, Non-periodic: %d\n"</span>,
+<a name="l00339"></a>00339                         __func__, num_channels, hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#5754b87bd4644fbb7b90cf843c638f1c">periodic_channels</a>, hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e7fff26b5cce7c6c520c89f9e3c75617">non_periodic_channels</a>);    <span class="comment">//NOTICE</span>
+<a name="l00340"></a>00340                 status = -DWC_E_NO_SPACE;
+<a name="l00341"></a>00341         }
+<a name="l00342"></a>00342 
+<a name="l00343"></a>00343         <span class="keywordflow">return</span> status;
+<a name="l00344"></a>00344 }
+<a name="l00345"></a>00345 
+<a name="l00356"></a><a class="code" href="dwc__otg__hcd__queue_8c.html#fee6145ab0fe7782c587916160dedb11">00356</a> <span class="keyword">static</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd__queue_8c.html#fee6145ab0fe7782c587916160dedb11">check_periodic_bandwidth</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd, <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> * qh)
+<a name="l00357"></a>00357 {
+<a name="l00358"></a>00358         <span class="keywordtype">int</span> status;
+<a name="l00359"></a>00359         int16_t max_claimed_usecs;
+<a name="l00360"></a>00360 
+<a name="l00361"></a>00361         status = 0;
+<a name="l00362"></a>00362 
+<a name="l00363"></a>00363         <span class="keywordflow">if</span> ((qh-&gt;<a class="code" href="structdwc__otg__qh.html#42459dd91e199807783000b6dc358a7d">dev_speed</a> == <a class="code" href="dwc__otg__cil_8h.html#b9dc03c6bc3c1113a935a73cf7021fbe">DWC_OTG_EP_SPEED_HIGH</a>) || qh-&gt;<a class="code" href="structdwc__otg__qh.html#8708dd009988ce20b8a8d52a4a96c5a3">do_split</a>) {
+<a name="l00364"></a>00364                 <span class="comment">/*</span>
+<a name="l00365"></a>00365 <span class="comment">                 * High speed mode.</span>
+<a name="l00366"></a>00366 <span class="comment">                 * Max periodic usecs is 80% x 125 usec = 100 usec.</span>
+<a name="l00367"></a>00367 <span class="comment">                 */</span>
+<a name="l00368"></a>00368 
+<a name="l00369"></a>00369                 max_claimed_usecs = 100 - qh-&gt;<a class="code" href="structdwc__otg__qh.html#401de6aadcfc2f99773f44c6731c4646">usecs</a>;
+<a name="l00370"></a>00370         } <span class="keywordflow">else</span> {
+<a name="l00371"></a>00371                 <span class="comment">/*</span>
+<a name="l00372"></a>00372 <span class="comment">                 * Full speed mode.</span>
+<a name="l00373"></a>00373 <span class="comment">                 * Max periodic usecs is 90% x 1000 usec = 900 usec.</span>
+<a name="l00374"></a>00374 <span class="comment">                 */</span>
+<a name="l00375"></a>00375                 max_claimed_usecs = 900 - qh-&gt;<a class="code" href="structdwc__otg__qh.html#401de6aadcfc2f99773f44c6731c4646">usecs</a>;
+<a name="l00376"></a>00376         }
+<a name="l00377"></a>00377 
+<a name="l00378"></a>00378         <span class="keywordflow">if</span> (hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#1f2ce690c8ded506eff8d1b567747235">periodic_usecs</a> &gt; max_claimed_usecs) {
+<a name="l00379"></a>00379                 DWC_INFO(<span class="stringliteral">"%s: already claimed usecs %d, required usecs %d\n"</span>, __func__, hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#1f2ce690c8ded506eff8d1b567747235">periodic_usecs</a>, qh-&gt;<a class="code" href="structdwc__otg__qh.html#401de6aadcfc2f99773f44c6731c4646">usecs</a>);        <span class="comment">//NOTICE</span>
+<a name="l00380"></a>00380                 status = -DWC_E_NO_SPACE;
+<a name="l00381"></a>00381         }
+<a name="l00382"></a>00382 
+<a name="l00383"></a>00383         <span class="keywordflow">return</span> status;
+<a name="l00384"></a>00384 }
+<a name="l00385"></a>00385 
+<a name="l00396"></a><a class="code" href="dwc__otg__hcd__queue_8c.html#4d3ef86a879b015bea87b02118aae4c9">00396</a> <span class="keyword">static</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd__queue_8c.html#4d3ef86a879b015bea87b02118aae4c9">check_max_xfer_size</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd, <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> * qh)
+<a name="l00397"></a>00397 {
+<a name="l00398"></a>00398         <span class="keywordtype">int</span> status;
+<a name="l00399"></a>00399         uint32_t max_xfer_size;
+<a name="l00400"></a>00400         uint32_t max_channel_xfer_size;
+<a name="l00401"></a>00401 
+<a name="l00402"></a>00402         status = 0;
+<a name="l00403"></a>00403 
+<a name="l00404"></a>00404         max_xfer_size = <a class="code" href="dwc__otg__hcd_8h.html#bd2189f881088fe7f4ca9112ee24549b">dwc_max_packet</a>(qh-&gt;<a class="code" href="structdwc__otg__qh.html#5975c2bede1ca0c6cfe9a66fe0a52567">maxp</a>) * <a class="code" href="dwc__otg__hcd_8h.html#a371dfcb8a66214c8fe226190fc1a323">dwc_hb_mult</a>(qh-&gt;<a class="code" href="structdwc__otg__qh.html#5975c2bede1ca0c6cfe9a66fe0a52567">maxp</a>);
+<a name="l00405"></a>00405         max_channel_xfer_size = hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#e614d1d2ee740cd972ca76ed0dffec74">max_transfer_size</a>;
+<a name="l00406"></a>00406 
+<a name="l00407"></a>00407         <span class="keywordflow">if</span> (max_xfer_size &gt; max_channel_xfer_size) {
+<a name="l00408"></a>00408                 DWC_INFO(<span class="stringliteral">"%s: Periodic xfer length %d &gt; "</span> <span class="stringliteral">"max xfer length for channel %d\n"</span>,
+<a name="l00409"></a>00409                                 __func__, max_xfer_size, max_channel_xfer_size);        <span class="comment">//NOTICE</span>
+<a name="l00410"></a>00410                 status = -DWC_E_NO_SPACE;
+<a name="l00411"></a>00411         }
+<a name="l00412"></a>00412 
+<a name="l00413"></a>00413         <span class="keywordflow">return</span> status;
+<a name="l00414"></a>00414 }
+<a name="l00415"></a>00415 
+<a name="l00425"></a><a class="code" href="dwc__otg__hcd__queue_8c.html#06b5d4bb36612e7da15a3727b1396a0c">00425</a> <span class="keyword">static</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd__queue_8c.html#06b5d4bb36612e7da15a3727b1396a0c">schedule_periodic</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd, <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> * qh)
+<a name="l00426"></a>00426 {
+<a name="l00427"></a>00427         <span class="keywordtype">int</span> status = 0;
+<a name="l00428"></a>00428 
+<a name="l00429"></a>00429         status = <a class="code" href="dwc__otg__hcd__queue_8c.html#debf9d35891234a74bc00832bba603bc">periodic_channel_available</a>(hcd);
+<a name="l00430"></a>00430         <span class="keywordflow">if</span> (status) {
+<a name="l00431"></a>00431                 DWC_INFO(<span class="stringliteral">"%s: No host channel available for periodic "</span> <span class="stringliteral">"transfer.\n"</span>, __func__);        <span class="comment">//NOTICE</span>
+<a name="l00432"></a>00432                 <span class="keywordflow">return</span> status;
+<a name="l00433"></a>00433         }
+<a name="l00434"></a>00434 
+<a name="l00435"></a>00435         status = <a class="code" href="dwc__otg__hcd__queue_8c.html#fee6145ab0fe7782c587916160dedb11">check_periodic_bandwidth</a>(hcd, qh);
+<a name="l00436"></a>00436         <span class="keywordflow">if</span> (status) {
+<a name="l00437"></a>00437                 DWC_INFO(<span class="stringliteral">"%s: Insufficient periodic bandwidth for "</span> <span class="stringliteral">"periodic transfer.\n"</span>, __func__);  <span class="comment">//NOTICE</span>
+<a name="l00438"></a>00438                 <span class="keywordflow">return</span> status;
+<a name="l00439"></a>00439         }
+<a name="l00440"></a>00440 
+<a name="l00441"></a>00441         status = <a class="code" href="dwc__otg__hcd__queue_8c.html#4d3ef86a879b015bea87b02118aae4c9">check_max_xfer_size</a>(hcd, qh);
+<a name="l00442"></a>00442         <span class="keywordflow">if</span> (status) {
+<a name="l00443"></a>00443                 DWC_INFO(<span class="stringliteral">"%s: Channel max transfer size too small "</span> <span class="stringliteral">"for periodic transfer.\n"</span>, __func__);      <span class="comment">//NOTICE</span>
+<a name="l00444"></a>00444                 <span class="keywordflow">return</span> status;
+<a name="l00445"></a>00445         }
+<a name="l00446"></a>00446 
+<a name="l00447"></a>00447         <span class="keywordflow">if</span> (hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a>) {
+<a name="l00448"></a>00448                 <span class="comment">/* Don't rely on SOF and start in ready schedule */</span>
+<a name="l00449"></a>00449                 DWC_LIST_INSERT_TAIL(&amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#74b089e094911a558f7b5f24681d3242">periodic_sched_ready</a>, &amp;qh-&gt;<a class="code" href="structdwc__otg__qh.html#3e1cb9863dc72139e1832c04244c25ff">qh_list_entry</a>);
+<a name="l00450"></a>00450         }
+<a name="l00451"></a>00451         <span class="keywordflow">else</span> {
+<a name="l00452"></a>00452         <span class="comment">/* Always start in the inactive schedule. */</span>
+<a name="l00453"></a>00453         DWC_LIST_INSERT_TAIL(&amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#2a747cacd6bdbacbef86d4157c34a312">periodic_sched_inactive</a>, &amp;qh-&gt;<a class="code" href="structdwc__otg__qh.html#3e1cb9863dc72139e1832c04244c25ff">qh_list_entry</a>);
+<a name="l00454"></a>00454         }
+<a name="l00455"></a>00455 
+<a name="l00456"></a>00456         <span class="comment">/* Reserve the periodic channel. */</span>
+<a name="l00457"></a>00457         hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#5754b87bd4644fbb7b90cf843c638f1c">periodic_channels</a>++;
+<a name="l00458"></a>00458 
+<a name="l00459"></a>00459         <span class="comment">/* Update claimed usecs per (micro)frame. */</span>
+<a name="l00460"></a>00460         hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#1f2ce690c8ded506eff8d1b567747235">periodic_usecs</a> += qh-&gt;<a class="code" href="structdwc__otg__qh.html#401de6aadcfc2f99773f44c6731c4646">usecs</a>;
+<a name="l00461"></a>00461 
+<a name="l00462"></a>00462         <span class="keywordflow">return</span> status;
+<a name="l00463"></a>00463 }
+<a name="l00464"></a>00464 
+<a name="l00472"></a><a class="code" href="dwc__otg__hcd__queue_8c.html#75cad4c6010d88086ddedf739db55d6b">00472</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd_8h.html#75cad4c6010d88086ddedf739db55d6b">dwc_otg_hcd_qh_add</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd, <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> * qh)
+<a name="l00473"></a>00473 {
+<a name="l00474"></a>00474         <span class="keywordtype">int</span> status = 0;
+<a name="l00475"></a>00475         uint64_t flags;
+<a name="l00476"></a>00476 
+<a name="l00477"></a>00477         DWC_SPINLOCK_IRQSAVE(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#34f29e9c035009476495f7701c1813fd">lock</a>, &amp;flags);
+<a name="l00478"></a>00478 
+<a name="l00479"></a>00479         <span class="keywordflow">if</span> (!DWC_LIST_EMPTY(&amp;qh-&gt;<a class="code" href="structdwc__otg__qh.html#3e1cb9863dc72139e1832c04244c25ff">qh_list_entry</a>)) {
+<a name="l00480"></a>00480                 <span class="comment">/* QH already in a schedule. */</span>
+<a name="l00481"></a>00481                 <span class="keywordflow">goto</span> done;
+<a name="l00482"></a>00482         }
+<a name="l00483"></a>00483 
+<a name="l00484"></a>00484         <span class="comment">/* Add the new QH to the appropriate schedule */</span>
+<a name="l00485"></a>00485         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__hcd_8h.html#4621f3eac09a9fc1363d286bff2de06b">dwc_qh_is_non_per</a>(qh)) {
+<a name="l00486"></a>00486                 <span class="comment">/* Always start in the inactive schedule. */</span>
+<a name="l00487"></a>00487                 DWC_LIST_INSERT_TAIL(&amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#64c96c47a36d71bad6e4360cec9d07ad">non_periodic_sched_inactive</a>,
+<a name="l00488"></a>00488                                      &amp;qh-&gt;<a class="code" href="structdwc__otg__qh.html#3e1cb9863dc72139e1832c04244c25ff">qh_list_entry</a>);
+<a name="l00489"></a>00489         } <span class="keywordflow">else</span> {
+<a name="l00490"></a>00490                 status = <a class="code" href="dwc__otg__hcd__queue_8c.html#06b5d4bb36612e7da15a3727b1396a0c">schedule_periodic</a>(hcd, qh);
+<a name="l00491"></a>00491         }
+<a name="l00492"></a>00492 
+<a name="l00493"></a>00493       done:
+<a name="l00494"></a>00494         DWC_SPINUNLOCK_IRQRESTORE(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#34f29e9c035009476495f7701c1813fd">lock</a>, flags);
+<a name="l00495"></a>00495 
+<a name="l00496"></a>00496         <span class="keywordflow">return</span> status;
+<a name="l00497"></a>00497 }
+<a name="l00498"></a>00498 
+<a name="l00505"></a><a class="code" href="dwc__otg__hcd__queue_8c.html#97dd97603c01db8288a735910b3b24a7">00505</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd__queue_8c.html#97dd97603c01db8288a735910b3b24a7">deschedule_periodic</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd, <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> * qh)
+<a name="l00506"></a>00506 {
+<a name="l00507"></a>00507         DWC_LIST_REMOVE_INIT(&amp;qh-&gt;<a class="code" href="structdwc__otg__qh.html#3e1cb9863dc72139e1832c04244c25ff">qh_list_entry</a>);
+<a name="l00508"></a>00508 
+<a name="l00509"></a>00509         <span class="comment">/* Release the periodic channel reservation. */</span>
+<a name="l00510"></a>00510         hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#5754b87bd4644fbb7b90cf843c638f1c">periodic_channels</a>--;
+<a name="l00511"></a>00511 
+<a name="l00512"></a>00512         <span class="comment">/* Update claimed usecs per (micro)frame. */</span>
+<a name="l00513"></a>00513         hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#1f2ce690c8ded506eff8d1b567747235">periodic_usecs</a> -= qh-&gt;<a class="code" href="structdwc__otg__qh.html#401de6aadcfc2f99773f44c6731c4646">usecs</a>;
+<a name="l00514"></a>00514 }
+<a name="l00515"></a>00515 
+<a name="l00522"></a><a class="code" href="dwc__otg__hcd__queue_8c.html#506b89b01ee7692885daff1c17c894f8">00522</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd_8h.html#506b89b01ee7692885daff1c17c894f8">dwc_otg_hcd_qh_remove</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd, <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> * qh)
+<a name="l00523"></a>00523 {
+<a name="l00524"></a>00524         uint64_t flags;
+<a name="l00525"></a>00525         DWC_SPINLOCK_IRQSAVE(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#34f29e9c035009476495f7701c1813fd">lock</a>, &amp;flags);
+<a name="l00526"></a>00526 
+<a name="l00527"></a>00527         <span class="keywordflow">if</span> (DWC_LIST_EMPTY(&amp;qh-&gt;<a class="code" href="structdwc__otg__qh.html#3e1cb9863dc72139e1832c04244c25ff">qh_list_entry</a>)) {
+<a name="l00528"></a>00528                 <span class="comment">/* QH is not in a schedule. */</span>
+<a name="l00529"></a>00529                 <span class="keywordflow">goto</span> done;
+<a name="l00530"></a>00530         }
+<a name="l00531"></a>00531 
+<a name="l00532"></a>00532         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__hcd_8h.html#4621f3eac09a9fc1363d286bff2de06b">dwc_qh_is_non_per</a>(qh)) {
+<a name="l00533"></a>00533                 <span class="keywordflow">if</span> (hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#01ab5791d6269b6b5d506f2113b94231">non_periodic_qh_ptr</a> == &amp;qh-&gt;<a class="code" href="structdwc__otg__qh.html#3e1cb9863dc72139e1832c04244c25ff">qh_list_entry</a>) {
+<a name="l00534"></a>00534                         hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#01ab5791d6269b6b5d506f2113b94231">non_periodic_qh_ptr</a> =
+<a name="l00535"></a>00535                             hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#01ab5791d6269b6b5d506f2113b94231">non_periodic_qh_ptr</a>-&gt;next;
+<a name="l00536"></a>00536                 }
+<a name="l00537"></a>00537                 DWC_LIST_REMOVE_INIT(&amp;qh-&gt;<a class="code" href="structdwc__otg__qh.html#3e1cb9863dc72139e1832c04244c25ff">qh_list_entry</a>);
+<a name="l00538"></a>00538         } <span class="keywordflow">else</span> {
+<a name="l00539"></a>00539                 <a class="code" href="dwc__otg__hcd__queue_8c.html#97dd97603c01db8288a735910b3b24a7">deschedule_periodic</a>(hcd, qh);
+<a name="l00540"></a>00540         }
+<a name="l00541"></a>00541 
+<a name="l00542"></a>00542       done:
+<a name="l00543"></a>00543         DWC_SPINUNLOCK_IRQRESTORE(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#34f29e9c035009476495f7701c1813fd">lock</a>, flags);
+<a name="l00544"></a>00544 }
+<a name="l00545"></a>00545 
+<a name="l00559"></a><a class="code" href="dwc__otg__hcd__queue_8c.html#793c592c73cd45f15e185ea60ad83b09">00559</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd_8h.html#f88bc5b6beb674c909d1c09a819ba9d9">dwc_otg_hcd_qh_deactivate</a>(<a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd, <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> * qh,
+<a name="l00560"></a>00560                                <span class="keywordtype">int</span> sched_next_periodic_split)
+<a name="l00561"></a>00561 {
+<a name="l00562"></a>00562         uint64_t flags;
+<a name="l00563"></a>00563         DWC_SPINLOCK_IRQSAVE(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#34f29e9c035009476495f7701c1813fd">lock</a>, &amp;flags);
+<a name="l00564"></a>00564 
+<a name="l00565"></a>00565         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__hcd_8h.html#4621f3eac09a9fc1363d286bff2de06b">dwc_qh_is_non_per</a>(qh)) {
+<a name="l00566"></a>00566                 <a class="code" href="dwc__otg__hcd_8h.html#506b89b01ee7692885daff1c17c894f8">dwc_otg_hcd_qh_remove</a>(hcd, qh);
+<a name="l00567"></a>00567                 <span class="keywordflow">if</span> (!DWC_CIRCLEQ_EMPTY(&amp;qh-&gt;<a class="code" href="structdwc__otg__qh.html#9567d266da8e796d3467fb16ae867f8e">qtd_list</a>)) {
+<a name="l00568"></a>00568                         <span class="comment">/* Add back to inactive non-periodic schedule. */</span>
+<a name="l00569"></a>00569                         <a class="code" href="dwc__otg__hcd_8h.html#75cad4c6010d88086ddedf739db55d6b">dwc_otg_hcd_qh_add</a>(hcd, qh);
+<a name="l00570"></a>00570                 }
+<a name="l00571"></a>00571         } <span class="keywordflow">else</span> {
+<a name="l00572"></a>00572                 uint16_t frame_number = <a class="code" href="dwc__otg__hcd_8c.html#f06514bd6f8c219cc72d1f467a82c056">dwc_otg_hcd_get_frame_number</a>(hcd);
+<a name="l00573"></a>00573 
+<a name="l00574"></a>00574                 <span class="keywordflow">if</span> (qh-&gt;<a class="code" href="structdwc__otg__qh.html#8708dd009988ce20b8a8d52a4a96c5a3">do_split</a>) {
+<a name="l00575"></a>00575                         <span class="comment">/* Schedule the next continuing periodic split transfer */</span>
+<a name="l00576"></a>00576                         <span class="keywordflow">if</span> (sched_next_periodic_split) {
+<a name="l00577"></a>00577 
+<a name="l00578"></a>00578                                 qh-&gt;<a class="code" href="structdwc__otg__qh.html#977a8032f08e45a9e9bdcd558a6965d3">sched_frame</a> = frame_number;
+<a name="l00579"></a>00579                                 <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__hcd_8h.html#02aa5e9853fcc705b9b5c839a249e2f8">dwc_frame_num_le</a>(frame_number,
+<a name="l00580"></a>00580                                                      <a class="code" href="dwc__otg__hcd_8h.html#cb175759a6b2cd291eedc276c022b500">dwc_frame_num_inc</a>(qh-&gt;
+<a name="l00581"></a>00581                                                                        start_split_frame,
+<a name="l00582"></a>00582                                                                        1))) {
+<a name="l00583"></a>00583                                         <span class="comment">/*</span>
+<a name="l00584"></a>00584 <span class="comment">                                         * Allow one frame to elapse after start</span>
+<a name="l00585"></a>00585 <span class="comment">                                         * split microframe before scheduling</span>
+<a name="l00586"></a>00586 <span class="comment">                                         * complete split, but DONT if we are</span>
+<a name="l00587"></a>00587 <span class="comment">                                         * doing the next start split in the</span>
+<a name="l00588"></a>00588 <span class="comment">                                         * same frame for an ISOC out.</span>
+<a name="l00589"></a>00589 <span class="comment">                                         */</span>
+<a name="l00590"></a>00590                                         <span class="keywordflow">if</span> ((qh-&gt;<a class="code" href="structdwc__otg__qh.html#98b78ffd8dbc01be44b302e873e73a82">ep_type</a> != UE_ISOCHRONOUS) ||
+<a name="l00591"></a>00591                                             (qh-&gt;<a class="code" href="structdwc__otg__qh.html#2dc622878a6617e5c803061804d5cf9f">ep_is_in</a> != 0)) {
+<a name="l00592"></a>00592                                                 qh-&gt;<a class="code" href="structdwc__otg__qh.html#977a8032f08e45a9e9bdcd558a6965d3">sched_frame</a> =
+<a name="l00593"></a>00593                                                     <a class="code" href="dwc__otg__hcd_8h.html#cb175759a6b2cd291eedc276c022b500">dwc_frame_num_inc</a>(qh-&gt;<a class="code" href="structdwc__otg__qh.html#977a8032f08e45a9e9bdcd558a6965d3">sched_frame</a>, 1);
+<a name="l00594"></a>00594                                         }
+<a name="l00595"></a>00595                                 }
+<a name="l00596"></a>00596                         } <span class="keywordflow">else</span> {
+<a name="l00597"></a>00597                                 qh-&gt;<a class="code" href="structdwc__otg__qh.html#977a8032f08e45a9e9bdcd558a6965d3">sched_frame</a> =
+<a name="l00598"></a>00598                                     <a class="code" href="dwc__otg__hcd_8h.html#cb175759a6b2cd291eedc276c022b500">dwc_frame_num_inc</a>(qh-&gt;<a class="code" href="structdwc__otg__qh.html#a92b9ff45f0eca459b41ca20e4d8e99c">start_split_frame</a>,
+<a name="l00599"></a>00599                                                       qh-&gt;<a class="code" href="structdwc__otg__qh.html#cdbce86d457f0ea08e2efedc47c9b315">interval</a>);
+<a name="l00600"></a>00600                                 <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__hcd_8h.html#02aa5e9853fcc705b9b5c839a249e2f8">dwc_frame_num_le</a>
+<a name="l00601"></a>00601                                     (qh-&gt;<a class="code" href="structdwc__otg__qh.html#977a8032f08e45a9e9bdcd558a6965d3">sched_frame</a>, frame_number)) {
+<a name="l00602"></a>00602                                         qh-&gt;<a class="code" href="structdwc__otg__qh.html#977a8032f08e45a9e9bdcd558a6965d3">sched_frame</a> = frame_number;
+<a name="l00603"></a>00603                                 }
+<a name="l00604"></a>00604                                 qh-&gt;<a class="code" href="structdwc__otg__qh.html#977a8032f08e45a9e9bdcd558a6965d3">sched_frame</a> |= 0x7;
+<a name="l00605"></a>00605                                 qh-&gt;<a class="code" href="structdwc__otg__qh.html#a92b9ff45f0eca459b41ca20e4d8e99c">start_split_frame</a> = qh-&gt;<a class="code" href="structdwc__otg__qh.html#977a8032f08e45a9e9bdcd558a6965d3">sched_frame</a>;
+<a name="l00606"></a>00606                         }
+<a name="l00607"></a>00607                 } <span class="keywordflow">else</span> {
+<a name="l00608"></a>00608                         qh-&gt;<a class="code" href="structdwc__otg__qh.html#977a8032f08e45a9e9bdcd558a6965d3">sched_frame</a> =
+<a name="l00609"></a>00609                             <a class="code" href="dwc__otg__hcd_8h.html#cb175759a6b2cd291eedc276c022b500">dwc_frame_num_inc</a>(qh-&gt;<a class="code" href="structdwc__otg__qh.html#977a8032f08e45a9e9bdcd558a6965d3">sched_frame</a>, qh-&gt;<a class="code" href="structdwc__otg__qh.html#cdbce86d457f0ea08e2efedc47c9b315">interval</a>);
+<a name="l00610"></a>00610                         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__hcd_8h.html#02aa5e9853fcc705b9b5c839a249e2f8">dwc_frame_num_le</a>(qh-&gt;<a class="code" href="structdwc__otg__qh.html#977a8032f08e45a9e9bdcd558a6965d3">sched_frame</a>, frame_number)) {
+<a name="l00611"></a>00611                                 qh-&gt;<a class="code" href="structdwc__otg__qh.html#977a8032f08e45a9e9bdcd558a6965d3">sched_frame</a> = frame_number;
+<a name="l00612"></a>00612                         }
+<a name="l00613"></a>00613                 }
+<a name="l00614"></a>00614 
+<a name="l00615"></a>00615                 <span class="keywordflow">if</span> (DWC_CIRCLEQ_EMPTY(&amp;qh-&gt;<a class="code" href="structdwc__otg__qh.html#9567d266da8e796d3467fb16ae867f8e">qtd_list</a>)) {
+<a name="l00616"></a>00616                         <a class="code" href="dwc__otg__hcd_8h.html#506b89b01ee7692885daff1c17c894f8">dwc_otg_hcd_qh_remove</a>(hcd, qh);
+<a name="l00617"></a>00617                 } <span class="keywordflow">else</span> {
+<a name="l00618"></a>00618                         <span class="comment">/*</span>
+<a name="l00619"></a>00619 <span class="comment">                         * Remove from periodic_sched_queued and move to</span>
+<a name="l00620"></a>00620 <span class="comment">                         * appropriate queue.</span>
+<a name="l00621"></a>00621 <span class="comment">                         */</span>
+<a name="l00622"></a>00622                         <span class="keywordflow">if</span> (qh-&gt;<a class="code" href="structdwc__otg__qh.html#977a8032f08e45a9e9bdcd558a6965d3">sched_frame</a> == frame_number) {
+<a name="l00623"></a>00623                                 DWC_LIST_MOVE_HEAD(&amp;hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#74b089e094911a558f7b5f24681d3242">periodic_sched_ready</a>,
+<a name="l00624"></a>00624                                                    &amp;qh-&gt;<a class="code" href="structdwc__otg__qh.html#3e1cb9863dc72139e1832c04244c25ff">qh_list_entry</a>);
+<a name="l00625"></a>00625                         } <span class="keywordflow">else</span> {
+<a name="l00626"></a>00626                                 DWC_LIST_MOVE_HEAD(&amp;hcd-&gt;
+<a name="l00627"></a>00627                                                    periodic_sched_inactive,
+<a name="l00628"></a>00628                                                    &amp;qh-&gt;<a class="code" href="structdwc__otg__qh.html#3e1cb9863dc72139e1832c04244c25ff">qh_list_entry</a>);
+<a name="l00629"></a>00629                         }
+<a name="l00630"></a>00630                 }
+<a name="l00631"></a>00631         }
+<a name="l00632"></a>00632 
+<a name="l00633"></a>00633         DWC_SPINUNLOCK_IRQRESTORE(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#34f29e9c035009476495f7701c1813fd">lock</a>, flags);
+<a name="l00634"></a>00634 }
+<a name="l00635"></a>00635 
+<a name="l00643"></a><a class="code" href="dwc__otg__hcd__queue_8c.html#5c4da8822ae027f70eda33cb783644fc">00643</a> <a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *<a class="code" href="dwc__otg__hcd_8h.html#5c4da8822ae027f70eda33cb783644fc">dwc_otg_hcd_qtd_create</a>(<a class="code" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> * urb)
+<a name="l00644"></a>00644 {
+<a name="l00645"></a>00645         <a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *qtd;
+<a name="l00646"></a>00646 
+<a name="l00647"></a>00647         qtd = <a class="code" href="dwc__otg__hcd_8h.html#ad58f04f541929d521f9acde9e465577">dwc_otg_hcd_qtd_alloc</a>();
+<a name="l00648"></a>00648         <span class="keywordflow">if</span> (qtd == NULL) {
+<a name="l00649"></a>00649                 <span class="keywordflow">return</span> NULL;
+<a name="l00650"></a>00650         }
+<a name="l00651"></a>00651 
+<a name="l00652"></a>00652         <a class="code" href="dwc__otg__hcd_8h.html#9ebb534f604aa8f693da162f32cf1ba4">dwc_otg_hcd_qtd_init</a>(qtd, urb);
+<a name="l00653"></a>00653         <span class="keywordflow">return</span> qtd;
+<a name="l00654"></a>00654 }
+<a name="l00655"></a>00655 
+<a name="l00661"></a><a class="code" href="dwc__otg__hcd__queue_8c.html#9ebb534f604aa8f693da162f32cf1ba4">00661</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__hcd_8h.html#9ebb534f604aa8f693da162f32cf1ba4">dwc_otg_hcd_qtd_init</a>(<a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> * qtd, <a class="code" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> * urb)
+<a name="l00662"></a>00662 {
+<a name="l00663"></a>00663         dwc_memset(qtd, 0, <span class="keyword">sizeof</span>(<a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a>));
+<a name="l00664"></a>00664         qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#7e7767808e8eb9d71de0db00f57553f9">urb</a> = urb;
+<a name="l00665"></a>00665         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__hcd_8h.html#b97cea598797e69d011ffef89989a739">dwc_otg_hcd_get_pipe_type</a>(&amp;urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#34ee3ac5931687b41dd726f00c558369">pipe_info</a>) == UE_CONTROL) {
+<a name="l00666"></a>00666                 <span class="comment">/*</span>
+<a name="l00667"></a>00667 <span class="comment">                 * The only time the QTD data toggle is used is on the data</span>
+<a name="l00668"></a>00668 <span class="comment">                 * phase of control transfers. This phase always starts with</span>
+<a name="l00669"></a>00669 <span class="comment">                 * DATA1.</span>
+<a name="l00670"></a>00670 <span class="comment">                 */</span>
+<a name="l00671"></a>00671                 qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#e912f256e01165b573c26262247a5eff">data_toggle</a> = <a class="code" href="dwc__otg__cil_8h.html#e623eb446c55928b324e9636111315e1">DWC_OTG_HC_PID_DATA1</a>;
+<a name="l00672"></a>00672                 qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#5189ec9c992974d20477481eaf96d0bb">control_phase</a> = DWC_OTG_CONTROL_SETUP;
+<a name="l00673"></a>00673         }
+<a name="l00674"></a>00674 
+<a name="l00675"></a>00675         <span class="comment">/* start split */</span>
+<a name="l00676"></a>00676         qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#6355e968a4d36edce3e22c89ac7b5001">complete_split</a> = 0;
+<a name="l00677"></a>00677         qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#ab224d64d72f2ef4f10e722ebcfa29a6">isoc_split_pos</a> = <a class="code" href="dwc__otg__regs_8h.html#b8a8f35d8fd73c955cc0403e87cea0c6">DWC_HCSPLIT_XACTPOS_ALL</a>;
+<a name="l00678"></a>00678         qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#839371940a7e34365e2272f3214b7e34">isoc_split_offset</a> = 0;
+<a name="l00679"></a>00679         qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#c1d73f1d48eeabbdc198ad28c0882bc1">in_process</a> = 0;
+<a name="l00680"></a>00680 
+<a name="l00681"></a>00681         <span class="comment">/* Store the qtd ptr in the urb to reference what QTD. */</span>
+<a name="l00682"></a>00682         urb-&gt;<a class="code" href="structdwc__otg__hcd__urb.html#68dc4d459bb70aed6083553653aadaad">qtd</a> = qtd;
+<a name="l00683"></a>00683         <span class="keywordflow">return</span>;
+<a name="l00684"></a>00684 }
+<a name="l00685"></a>00685 
+<a name="l00698"></a><a class="code" href="dwc__otg__hcd__queue_8c.html#c8a5d8f0fc76595496b1a0bd2f83a501">00698</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd_8h.html#748ba77769387bfe4295cb10265053f0">dwc_otg_hcd_qtd_add</a>(<a class="code" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> * qtd,
+<a name="l00699"></a>00699                         <a class="code" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> * hcd, <a class="code" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> ** qh)
+<a name="l00700"></a>00700 {
+<a name="l00701"></a>00701         <span class="keywordtype">int</span> retval = 0;
+<a name="l00702"></a>00702         uint64_t flags;
+<a name="l00703"></a>00703 
+<a name="l00704"></a>00704         <a class="code" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *urb = qtd-&gt;<a class="code" href="structdwc__otg__qtd.html#7e7767808e8eb9d71de0db00f57553f9">urb</a>;
+<a name="l00705"></a>00705 
+<a name="l00706"></a>00706         DWC_SPINLOCK_IRQSAVE(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#34f29e9c035009476495f7701c1813fd">lock</a>, &amp;flags);
+<a name="l00707"></a>00707 
+<a name="l00708"></a>00708         <span class="comment">/*</span>
+<a name="l00709"></a>00709 <span class="comment">         * Get the QH which holds the QTD-list to insert to. Create QH if it</span>
+<a name="l00710"></a>00710 <span class="comment">         * doesn't exist.</span>
+<a name="l00711"></a>00711 <span class="comment">         */</span>
+<a name="l00712"></a>00712         <span class="keywordflow">if</span> (*qh == NULL) {
+<a name="l00713"></a>00713                 *qh = <a class="code" href="dwc__otg__hcd_8h.html#187194b7a9f28e7f7a09ac3e345c7253">dwc_otg_hcd_qh_create</a>(hcd, urb);
+<a name="l00714"></a>00714                 <span class="keywordflow">if</span> (*qh == NULL) {
+<a name="l00715"></a>00715                         retval = -1;
+<a name="l00716"></a>00716                         <span class="keywordflow">goto</span> done;
+<a name="l00717"></a>00717                 }
+<a name="l00718"></a>00718         }
+<a name="l00719"></a>00719 
+<a name="l00720"></a>00720         retval = <a class="code" href="dwc__otg__hcd_8h.html#75cad4c6010d88086ddedf739db55d6b">dwc_otg_hcd_qh_add</a>(hcd, *qh);
+<a name="l00721"></a>00721         <span class="keywordflow">if</span> (retval == 0) {
+<a name="l00722"></a>00722                 DWC_CIRCLEQ_INSERT_TAIL(&amp;((*qh)-&gt;qtd_list), qtd,
+<a name="l00723"></a>00723                                         qtd_list_entry);
+<a name="l00724"></a>00724         }
+<a name="l00725"></a>00725 
+<a name="l00726"></a>00726       done:
+<a name="l00727"></a>00727         DWC_SPINUNLOCK_IRQRESTORE(hcd-&gt;<a class="code" href="structdwc__otg__hcd.html#34f29e9c035009476495f7701c1813fd">lock</a>, flags);
+<a name="l00728"></a>00728 
+<a name="l00729"></a>00729         <span class="keywordflow">return</span> retval;
+<a name="l00730"></a>00730 }
+<a name="l00731"></a>00731 
+<a name="l00732"></a>00732 <span class="preprocessor">#endif                          </span><span class="comment">/* DWC_DEVICE_ONLY */</span>
+</pre></div><hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__queue_8c.html b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__queue_8c.html
new file mode 100644
index 000000000000..13f68b1b7bd0
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__queue_8c.html
@@ -0,0 +1,667 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd_queue.c File Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<h1>dwc_otg_hcd_queue.c File Reference</h1>This file contains the functions to manage Queue Heads and Queue Transfer Descriptors. <a href="#_details">More...</a>
+<p>
+<code>#include &quot;<a class="el" href="dwc__otg__hcd_8h-source.html">dwc_otg_hcd.h</a>&quot;</code><br>
+<code>#include &quot;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&quot;</code><br>
+
+<p>
+<a href="dwc__otg__hcd__queue_8c-source.html">Go to the source code of this file.</a><table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Defines</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e740bef95f7929a07065b699f6f087a2"></a><!-- doxytag: member="dwc_otg_hcd_queue.c::BitStuffTime" ref="e740bef95f7929a07065b699f6f087a2" args="(bytecount)" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__queue_8c.html#e740bef95f7929a07065b699f6f087a2">BitStuffTime</a>(bytecount)&nbsp;&nbsp;&nbsp;((8 * 7* bytecount) / 6)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="2a974c684e456c20cc2d9bceb2e71a11"></a><!-- doxytag: member="dwc_otg_hcd_queue.c::HS_HOST_DELAY" ref="2a974c684e456c20cc2d9bceb2e71a11" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__queue_8c.html#2a974c684e456c20cc2d9bceb2e71a11">HS_HOST_DELAY</a>&nbsp;&nbsp;&nbsp;5</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="8f9875d35aace115a340d2cef9c66294"></a><!-- doxytag: member="dwc_otg_hcd_queue.c::FS_LS_HOST_DELAY" ref="8f9875d35aace115a340d2cef9c66294" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__queue_8c.html#8f9875d35aace115a340d2cef9c66294">FS_LS_HOST_DELAY</a>&nbsp;&nbsp;&nbsp;1000</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="d596163a6f24db7fb4ee092a933e03a2"></a><!-- doxytag: member="dwc_otg_hcd_queue.c::HUB_LS_SETUP" ref="d596163a6f24db7fb4ee092a933e03a2" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__queue_8c.html#d596163a6f24db7fb4ee092a933e03a2">HUB_LS_SETUP</a>&nbsp;&nbsp;&nbsp;333</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="1df143acbaa5817cd09c8cca89851747"></a><!-- doxytag: member="dwc_otg_hcd_queue.c::NS_TO_US" ref="1df143acbaa5817cd09c8cca89851747" args="(ns)" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__queue_8c.html#1df143acbaa5817cd09c8cca89851747">NS_TO_US</a>(ns)&nbsp;&nbsp;&nbsp;((ns + 500) / 1000)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__queue_8c.html#86d31a59a5f7c095cd183a06edeed5e1">SCHEDULE_SLOP</a>&nbsp;&nbsp;&nbsp;10</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Initializes a QH structure.  <a href="#86d31a59a5f7c095cd183a06edeed5e1"></a><br></td></tr>
+<tr><td colspan="2"><br><h2>Functions</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__queue_8c.html#1ac731c0691ac3851edddc558fae79e0">dwc_otg_hcd_qh_free</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *qh)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Free each QTD in the QH's QTD-list then free the QH.  <a href="#1ac731c0691ac3851edddc558fae79e0"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="49a9d4aa15e01fc07d68826bd05c0f4d"></a><!-- doxytag: member="dwc_otg_hcd_queue.c::calc_bus_time" ref="49a9d4aa15e01fc07d68826bd05c0f4d" args="(int speed, int is_in, int is_isoc, int bytecount)" -->
+static uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__queue_8c.html#49a9d4aa15e01fc07d68826bd05c0f4d">calc_bus_time</a> (int speed, int is_in, int is_isoc, int bytecount)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__queue_8c.html#d32f8a4be67b758e9541e33746363677">qh_init</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *qh, <a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *urb)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__queue_8c.html#187194b7a9f28e7f7a09ac3e345c7253">dwc_otg_hcd_qh_create</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *urb)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function allocates and initializes a QH.  <a href="#187194b7a9f28e7f7a09ac3e345c7253"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__queue_8c.html#debf9d35891234a74bc00832bba603bc">periodic_channel_available</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Checks that a channel is available for a periodic transfer.  <a href="#debf9d35891234a74bc00832bba603bc"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__queue_8c.html#fee6145ab0fe7782c587916160dedb11">check_periodic_bandwidth</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *qh)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Checks that there is sufficient bandwidth for the specified QH in the periodic schedule.  <a href="#fee6145ab0fe7782c587916160dedb11"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__queue_8c.html#4d3ef86a879b015bea87b02118aae4c9">check_max_xfer_size</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *qh)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Checks that the max transfer size allowed in a host channel is large enough to handle the maximum data transfer in a single (micro)frame for a periodic transfer.  <a href="#4d3ef86a879b015bea87b02118aae4c9"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__queue_8c.html#06b5d4bb36612e7da15a3727b1396a0c">schedule_periodic</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *qh)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Schedules an interrupt or isochronous transfer in the periodic schedule.  <a href="#06b5d4bb36612e7da15a3727b1396a0c"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__queue_8c.html#75cad4c6010d88086ddedf739db55d6b">dwc_otg_hcd_qh_add</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *qh)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function adds a QH to either the non periodic or periodic schedule if it is not already in the schedule.  <a href="#75cad4c6010d88086ddedf739db55d6b"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__queue_8c.html#97dd97603c01db8288a735910b3b24a7">deschedule_periodic</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *qh)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Removes an interrupt or isochronous transfer from the periodic schedule.  <a href="#97dd97603c01db8288a735910b3b24a7"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__queue_8c.html#506b89b01ee7692885daff1c17c894f8">dwc_otg_hcd_qh_remove</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *qh)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Removes a QH from either the non-periodic or periodic schedule.  <a href="#506b89b01ee7692885daff1c17c894f8"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__queue_8c.html#793c592c73cd45f15e185ea60ad83b09">dwc_otg_hcd_qh_deactivate</a> (<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *qh, int sched_next_periodic_split)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Deactivates a QH.  <a href="#793c592c73cd45f15e185ea60ad83b09"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__queue_8c.html#5c4da8822ae027f70eda33cb783644fc">dwc_otg_hcd_qtd_create</a> (<a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *urb)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function allocates and initializes a QTD.  <a href="#5c4da8822ae027f70eda33cb783644fc"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__queue_8c.html#9ebb534f604aa8f693da162f32cf1ba4">dwc_otg_hcd_qtd_init</a> (<a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *qtd, <a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *urb)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Initializes a QTD structure.  <a href="#9ebb534f604aa8f693da162f32cf1ba4"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__hcd__queue_8c.html#c8a5d8f0fc76595496b1a0bd2f83a501">dwc_otg_hcd_qtd_add</a> (<a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *qtd, <a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *hcd, <a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> **qh)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function adds a QTD to the QTD-list of a QH.  <a href="#c8a5d8f0fc76595496b1a0bd2f83a501"></a><br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This file contains the functions to manage Queue Heads and Queue Transfer Descriptors. 
+<p>
+
+<p>
+Definition in file <a class="el" href="dwc__otg__hcd__queue_8c-source.html">dwc_otg_hcd_queue.c</a>.<hr><h2>Define Documentation</h2>
+<a class="anchor" name="86d31a59a5f7c095cd183a06edeed5e1"></a><!-- doxytag: member="dwc_otg_hcd_queue.c::SCHEDULE_SLOP" ref="86d31a59a5f7c095cd183a06edeed5e1" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define SCHEDULE_SLOP&nbsp;&nbsp;&nbsp;10          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Initializes a QH structure. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD state structure for the DWC OTG controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>qh</em>&nbsp;</td><td>The QH to init. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>urb</em>&nbsp;</td><td>Holds the information about the device/endpoint that we need to initialize the QH. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__queue_8c-source.html#l00159">159</a> of file <a class="el" href="dwc__otg__hcd__queue_8c-source.html">dwc_otg_hcd_queue.c</a>.
+</div>
+</div><p>
+<hr><h2>Function Documentation</h2>
+<a class="anchor" name="1ac731c0691ac3851edddc558fae79e0"></a><!-- doxytag: member="dwc_otg_hcd_queue.c::dwc_otg_hcd_qh_free" ref="1ac731c0691ac3851edddc558fae79e0" args="(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_hcd_qh_free           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>qh</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Free each QTD in the QH's QTD-list then free the QH. 
+<p>
+QH should already be removed from a list. QTD list should already be empty if called from URB Dequeue.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>HCD instance. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>qh</em>&nbsp;</td><td>The QH to free. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__queue_8c-source.html#l00053">53</a> of file <a class="el" href="dwc__otg__hcd__queue_8c-source.html">dwc_otg_hcd_queue.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="d32f8a4be67b758e9541e33746363677"></a><!-- doxytag: member="dwc_otg_hcd_queue.c::qh_init" ref="d32f8a4be67b758e9541e33746363677" args="(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, dwc_otg_hcd_urb_t *urb)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void qh_init           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>qh</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>urb</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__queue_8c-source.html#l00160">160</a> of file <a class="el" href="dwc__otg__hcd__queue_8c-source.html">dwc_otg_hcd_queue.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="187194b7a9f28e7f7a09ac3e345c7253"></a><!-- doxytag: member="dwc_otg_hcd_queue.c::dwc_otg_hcd_qh_create" ref="187194b7a9f28e7f7a09ac3e345c7253" args="(dwc_otg_hcd_t *hcd, dwc_otg_hcd_urb_t *urb)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a>* dwc_otg_hcd_qh_create           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>urb</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function allocates and initializes a QH. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD state structure for the DWC OTG controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>urb</em>&nbsp;</td><td>Holds the information about the device/endpoint that we need to initialize the QH.</td></tr>
+  </table>
+</dl>
+<dl compact><dt><b>Returns:</b></dt><dd>Returns pointer to the newly allocated QH, or NULL on error. </dd></dl>
+
+<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000020">Todo:</a></b></dt><dd>add memflags argument </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__queue_8c-source.html#l00296">296</a> of file <a class="el" href="dwc__otg__hcd__queue_8c-source.html">dwc_otg_hcd_queue.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="debf9d35891234a74bc00832bba603bc"></a><!-- doxytag: member="dwc_otg_hcd_queue.c::periodic_channel_available" ref="debf9d35891234a74bc00832bba603bc" args="(dwc_otg_hcd_t *hcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static int periodic_channel_available           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Checks that a channel is available for a periodic transfer. 
+<p>
+<dl compact><dt><b>Returns:</b></dt><dd>0 if successful, negative error code otherise. </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__queue_8c-source.html#l00323">323</a> of file <a class="el" href="dwc__otg__hcd__queue_8c-source.html">dwc_otg_hcd_queue.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="fee6145ab0fe7782c587916160dedb11"></a><!-- doxytag: member="dwc_otg_hcd_queue.c::check_periodic_bandwidth" ref="fee6145ab0fe7782c587916160dedb11" args="(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static int check_periodic_bandwidth           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>qh</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Checks that there is sufficient bandwidth for the specified QH in the periodic schedule. 
+<p>
+For simplicity, this calculation assumes that all the transfers in the periodic schedule may occur in the same (micro)frame.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD state structure for the DWC OTG controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>qh</em>&nbsp;</td><td>QH containing periodic bandwidth required.</td></tr>
+  </table>
+</dl>
+<dl compact><dt><b>Returns:</b></dt><dd>0 if successful, negative error code otherwise. </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__queue_8c-source.html#l00356">356</a> of file <a class="el" href="dwc__otg__hcd__queue_8c-source.html">dwc_otg_hcd_queue.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="4d3ef86a879b015bea87b02118aae4c9"></a><!-- doxytag: member="dwc_otg_hcd_queue.c::check_max_xfer_size" ref="4d3ef86a879b015bea87b02118aae4c9" args="(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static int check_max_xfer_size           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>qh</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Checks that the max transfer size allowed in a host channel is large enough to handle the maximum data transfer in a single (micro)frame for a periodic transfer. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD state structure for the DWC OTG controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>qh</em>&nbsp;</td><td>QH for a periodic endpoint.</td></tr>
+  </table>
+</dl>
+<dl compact><dt><b>Returns:</b></dt><dd>0 if successful, negative error code otherwise. </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__queue_8c-source.html#l00396">396</a> of file <a class="el" href="dwc__otg__hcd__queue_8c-source.html">dwc_otg_hcd_queue.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="06b5d4bb36612e7da15a3727b1396a0c"></a><!-- doxytag: member="dwc_otg_hcd_queue.c::schedule_periodic" ref="06b5d4bb36612e7da15a3727b1396a0c" args="(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static int schedule_periodic           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>qh</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Schedules an interrupt or isochronous transfer in the periodic schedule. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD state structure for the DWC OTG controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>qh</em>&nbsp;</td><td>QH for the periodic transfer. The QH should already contain the scheduling information.</td></tr>
+  </table>
+</dl>
+<dl compact><dt><b>Returns:</b></dt><dd>0 if successful, negative error code otherwise. </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__queue_8c-source.html#l00425">425</a> of file <a class="el" href="dwc__otg__hcd__queue_8c-source.html">dwc_otg_hcd_queue.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="75cad4c6010d88086ddedf739db55d6b"></a><!-- doxytag: member="dwc_otg_hcd_queue.c::dwc_otg_hcd_qh_add" ref="75cad4c6010d88086ddedf739db55d6b" args="(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_hcd_qh_add           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>qh</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function adds a QH to either the non periodic or periodic schedule if it is not already in the schedule. 
+<p>
+If the QH is already in the schedule, no action is taken.<p>
+<dl compact><dt><b>Returns:</b></dt><dd>0 if successful, negative error code otherwise. </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__queue_8c-source.html#l00472">472</a> of file <a class="el" href="dwc__otg__hcd__queue_8c-source.html">dwc_otg_hcd_queue.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="97dd97603c01db8288a735910b3b24a7"></a><!-- doxytag: member="dwc_otg_hcd_queue.c::deschedule_periodic" ref="97dd97603c01db8288a735910b3b24a7" args="(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static void deschedule_periodic           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>qh</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Removes an interrupt or isochronous transfer from the periodic schedule. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD state structure for the DWC OTG controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>qh</em>&nbsp;</td><td>QH for the periodic transfer. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__queue_8c-source.html#l00505">505</a> of file <a class="el" href="dwc__otg__hcd__queue_8c-source.html">dwc_otg_hcd_queue.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="506b89b01ee7692885daff1c17c894f8"></a><!-- doxytag: member="dwc_otg_hcd_queue.c::dwc_otg_hcd_qh_remove" ref="506b89b01ee7692885daff1c17c894f8" args="(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_hcd_qh_remove           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>qh</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Removes a QH from either the non-periodic or periodic schedule. 
+<p>
+Memory is not freed.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hcd</em>&nbsp;</td><td>The HCD state structure. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>qh</em>&nbsp;</td><td>QH to remove from schedule. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__queue_8c-source.html#l00522">522</a> of file <a class="el" href="dwc__otg__hcd__queue_8c-source.html">dwc_otg_hcd_queue.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="793c592c73cd45f15e185ea60ad83b09"></a><!-- doxytag: member="dwc_otg_hcd_queue.c::dwc_otg_hcd_qh_deactivate" ref="793c592c73cd45f15e185ea60ad83b09" args="(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, int sched_next_periodic_split)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_hcd_qh_deactivate           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>qh</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>sched_next_periodic_split</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Deactivates a QH. 
+<p>
+For non-periodic QHs, removes the QH from the active non-periodic schedule. The QH is added to the inactive non-periodic schedule if any QTDs are still attached to the QH.<p>
+For periodic QHs, the QH is removed from the periodic queued schedule. If there are any QTDs still attached to the QH, the QH is added to either the periodic inactive schedule or the periodic ready schedule and its next scheduled frame is calculated. The QH is placed in the ready schedule if the scheduled frame has been reached already. Otherwise it's placed in the inactive schedule. If there are no QTDs attached to the QH, the QH is completely removed from the periodic schedule. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__queue_8c-source.html#l00559">559</a> of file <a class="el" href="dwc__otg__hcd__queue_8c-source.html">dwc_otg_hcd_queue.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="5c4da8822ae027f70eda33cb783644fc"></a><!-- doxytag: member="dwc_otg_hcd_queue.c::dwc_otg_hcd_qtd_create" ref="5c4da8822ae027f70eda33cb783644fc" args="(dwc_otg_hcd_urb_t *urb)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a>* dwc_otg_hcd_qtd_create           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>urb</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function allocates and initializes a QTD. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>urb</em>&nbsp;</td><td>The URB to create a QTD from. Each URB-QTD pair will end up pointing to each other so each pair should have a unique correlation.</td></tr>
+  </table>
+</dl>
+<dl compact><dt><b>Returns:</b></dt><dd>Returns pointer to the newly allocated QTD, or NULL on error. </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__queue_8c-source.html#l00643">643</a> of file <a class="el" href="dwc__otg__hcd__queue_8c-source.html">dwc_otg_hcd_queue.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="9ebb534f604aa8f693da162f32cf1ba4"></a><!-- doxytag: member="dwc_otg_hcd_queue.c::dwc_otg_hcd_qtd_init" ref="9ebb534f604aa8f693da162f32cf1ba4" args="(dwc_otg_qtd_t *qtd, dwc_otg_hcd_urb_t *urb)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_hcd_qtd_init           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>qtd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>urb</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Initializes a QTD structure. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>qtd</em>&nbsp;</td><td>The QTD to initialize. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>urb</em>&nbsp;</td><td>The URB to use for initialization. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__queue_8c-source.html#l00661">661</a> of file <a class="el" href="dwc__otg__hcd__queue_8c-source.html">dwc_otg_hcd_queue.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="c8a5d8f0fc76595496b1a0bd2f83a501"></a><!-- doxytag: member="dwc_otg_hcd_queue.c::dwc_otg_hcd_qtd_add" ref="c8a5d8f0fc76595496b1a0bd2f83a501" args="(dwc_otg_qtd_t *qtd, dwc_otg_hcd_t *hcd, dwc_otg_qh_t **qh)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_hcd_qtd_add           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>qtd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>hcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__qh.html">dwc_otg_qh_t</a> **&nbsp;</td>
+          <td class="paramname"> <em>qh</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function adds a QTD to the QTD-list of a QH. 
+<p>
+It will find the correct QH to place the QTD into. If it does not find a QH, then it will create a new QH. If the QH to which the QTD is added is not currently scheduled, it is placed into the proper schedule based on its EP type.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"><tt>[in]</tt>&nbsp;</td><td valign="top"><em>qtd</em>&nbsp;</td><td>The QTD to add </td></tr>
+    <tr><td valign="top"><tt>[in]</tt>&nbsp;</td><td valign="top"><em>hcd</em>&nbsp;</td><td>The DWC HCD structure </td></tr>
+    <tr><td valign="top"><tt>[out]</tt>&nbsp;</td><td valign="top"><em>qh</em>&nbsp;</td><td>out parameter to return queue head</td></tr>
+  </table>
+</dl>
+<dl compact><dt><b>Returns:</b></dt><dd>0 if successful, negative error code otherwise. </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__queue_8c-source.html#l00698">698</a> of file <a class="el" href="dwc__otg__hcd__queue_8c-source.html">dwc_otg_hcd_queue.c</a>.
+</div>
+</div><p>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd_8c-source.html b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd_8c-source.html
new file mode 100644
index 000000000000..da7e6176107e
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd_8c-source.html
@@ -0,0 +1,1851 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd.c Source File</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<h1>dwc_otg_pcd.c</h1><a href="dwc__otg__pcd_8c.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">/* ==========================================================================</span>
+<a name="l00002"></a>00002 <span class="comment"> * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.c $</span>
+<a name="l00003"></a>00003 <span class="comment"> * $Revision: #79 $</span>
+<a name="l00004"></a>00004 <span class="comment"> * $Date: 2009/04/10 $</span>
+<a name="l00005"></a>00005 <span class="comment"> * $Change: 1230501 $</span>
+<a name="l00006"></a>00006 <span class="comment"> *</span>
+<a name="l00007"></a>00007 <span class="comment"> * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,</span>
+<a name="l00008"></a>00008 <span class="comment"> * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless</span>
+<a name="l00009"></a>00009 <span class="comment"> * otherwise expressly agreed to in writing between Synopsys and you.</span>
+<a name="l00010"></a>00010 <span class="comment"> *</span>
+<a name="l00011"></a>00011 <span class="comment"> * The Software IS NOT an item of Licensed Software or Licensed Product under</span>
+<a name="l00012"></a>00012 <span class="comment"> * any End User Software License Agreement or Agreement for Licensed Product</span>
+<a name="l00013"></a>00013 <span class="comment"> * with Synopsys or any supplement thereto. You are permitted to use and</span>
+<a name="l00014"></a>00014 <span class="comment"> * redistribute this Software in source and binary forms, with or without</span>
+<a name="l00015"></a>00015 <span class="comment"> * modification, provided that redistributions of source code must retain this</span>
+<a name="l00016"></a>00016 <span class="comment"> * notice. You may not view, use, disclose, copy or distribute this file or</span>
+<a name="l00017"></a>00017 <span class="comment"> * any information contained herein except pursuant to this license grant from</span>
+<a name="l00018"></a>00018 <span class="comment"> * Synopsys. If you do not agree with this notice, including the disclaimer</span>
+<a name="l00019"></a>00019 <span class="comment"> * below, then you are not authorized to use the Software.</span>
+<a name="l00020"></a>00020 <span class="comment"> *</span>
+<a name="l00021"></a>00021 <span class="comment"> * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS</span>
+<a name="l00022"></a>00022 <span class="comment"> * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE</span>
+<a name="l00023"></a>00023 <span class="comment"> * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE</span>
+<a name="l00024"></a>00024 <span class="comment"> * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,</span>
+<a name="l00025"></a>00025 <span class="comment"> * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES</span>
+<a name="l00026"></a>00026 <span class="comment"> * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR</span>
+<a name="l00027"></a>00027 <span class="comment"> * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER</span>
+<a name="l00028"></a>00028 <span class="comment"> * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT</span>
+<a name="l00029"></a>00029 <span class="comment"> * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY</span>
+<a name="l00030"></a>00030 <span class="comment"> * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH</span>
+<a name="l00031"></a>00031 <span class="comment"> * DAMAGE.</span>
+<a name="l00032"></a>00032 <span class="comment"> * ========================================================================== */</span>
+<a name="l00033"></a>00033 <span class="preprocessor">#ifndef DWC_HOST_ONLY</span>
+<a name="l00034"></a>00034 <span class="preprocessor"></span>
+<a name="l00051"></a>00051 <span class="preprocessor">#include "<a class="code" href="dwc__otg__pcd_8h.html">dwc_otg_pcd.h</a>"</span>
+<a name="l00052"></a>00052 
+<a name="l00053"></a>00053 <span class="preprocessor">#ifdef DWC_UTE_CFI</span>
+<a name="l00054"></a>00054 <span class="preprocessor"></span><span class="preprocessor">#include "<a class="code" href="dwc__otg__cfi_8h.html">dwc_otg_cfi.h</a>"</span>
+<a name="l00055"></a>00055 
+<a name="l00056"></a>00056 <span class="keyword">extern</span> <span class="keywordtype">int</span> init_cfi(<a class="code" href="structcfiobject.html">cfiobject_t</a> * cfiobj);
+<a name="l00057"></a>00057 <span class="preprocessor">#endif</span>
+<a name="l00058"></a>00058 <span class="preprocessor"></span>
+<a name="l00059"></a><a class="code" href="dwc__otg__pcd_8c.html#4b46c226fa34cd7fc4ceec2c5e7f8ebe">00059</a> <span class="keyword">static</span> <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *<a class="code" href="dwc__otg__pcd_8c.html#4b46c226fa34cd7fc4ceec2c5e7f8ebe">get_ep_from_handle</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd, <span class="keywordtype">void</span> *handle)
+<a name="l00060"></a>00060 {
+<a name="l00061"></a>00061         <span class="keywordtype">int</span> i;
+<a name="l00062"></a>00062         <span class="keywordflow">if</span> (pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a>.<a class="code" href="structdwc__otg__pcd__ep.html#8c8fad971c6c3b1c54d334c7f9b2d03e">priv</a> == handle) {
+<a name="l00063"></a>00063                 <span class="keywordflow">return</span> &amp;pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a>;
+<a name="l00064"></a>00064         }
+<a name="l00065"></a>00065         <span class="keywordflow">for</span> (i = 0; i &lt; <a class="code" href="dwc__otg__core__if_8h.html#bfb88b45545f7685f668ac2f545674ec">MAX_EPS_CHANNELS</a> - 1; i++) {
+<a name="l00066"></a>00066                 <span class="keywordflow">if</span> (pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#dbfc8c424ea3add38db96fa87219caa8">in_ep</a>[i].<a class="code" href="structdwc__otg__pcd__ep.html#8c8fad971c6c3b1c54d334c7f9b2d03e">priv</a> == handle)
+<a name="l00067"></a>00067                         <span class="keywordflow">return</span> &amp;pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#dbfc8c424ea3add38db96fa87219caa8">in_ep</a>[i];
+<a name="l00068"></a>00068                 if (pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#b9e49a1d1fbca5ba9523e27c7108df30">out_ep</a>[i].<a class="code" href="structdwc__otg__pcd__ep.html#8c8fad971c6c3b1c54d334c7f9b2d03e">priv</a> == handle)
+<a name="l00069"></a>00069                         <span class="keywordflow">return</span> &amp;pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#b9e49a1d1fbca5ba9523e27c7108df30">out_ep</a>[i];
+<a name="l00070"></a>00070         }
+<a name="l00071"></a>00071 
+<a name="l00072"></a>00072         <span class="keywordflow">return</span> NULL;
+<a name="l00073"></a>00073 }
+<a name="l00074"></a>00074 
+<a name="l00078"></a><a class="code" href="dwc__otg__pcd_8h.html#5c9b20abc81e0f860a8f23c90b10b59e">00078</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd_8c.html#5c9b20abc81e0f860a8f23c90b10b59e">dwc_otg_request_done</a>(<a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> * ep, <a class="code" href="structdwc__otg__pcd__request.html">dwc_otg_pcd_request_t</a> * req,
+<a name="l00079"></a>00079                           int32_t status)
+<a name="l00080"></a>00080 {
+<a name="l00081"></a>00081         <span class="keywordtype">unsigned</span> stopped = ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#cce0e089118d8bf7c6278c21ded70d5a">stopped</a>;
+<a name="l00082"></a>00082 
+<a name="l00083"></a>00083         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"%s(%p)\n"</span>, __func__, ep);
+<a name="l00084"></a>00084         DWC_CIRCLEQ_REMOVE_INIT(&amp;ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#71f4fa571dfdc96f62fa4869e6add300">queue</a>, req, queue_entry);
+<a name="l00085"></a>00085 
+<a name="l00086"></a>00086         <span class="comment">/* don't modify queue heads during completion callback */</span>
+<a name="l00087"></a>00087         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#cce0e089118d8bf7c6278c21ded70d5a">stopped</a> = 1;
+<a name="l00088"></a>00088         DWC_SPINUNLOCK(ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#234391334e48cbd72710d08655c9ed16">pcd</a>-&gt;<a class="code" href="structdwc__otg__pcd.html#5d450e4d06659ab2f3b18e5c816776e4">lock</a>);
+<a name="l00089"></a>00089         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#234391334e48cbd72710d08655c9ed16">pcd</a>-&gt;<a class="code" href="structdwc__otg__pcd.html#b7001dde5db2706707a860da0030d9e6">fops</a>-&gt;<a class="code" href="structdwc__otg__pcd__function__ops.html#126db5e83cd3cc03f303eb3da668816f">complete</a>(ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#234391334e48cbd72710d08655c9ed16">pcd</a>, ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#8c8fad971c6c3b1c54d334c7f9b2d03e">priv</a>, req-&gt;<a class="code" href="structdwc__otg__pcd__request.html#e0d93b64365968aa0dcf58535aecf40c">priv</a>, status,
+<a name="l00090"></a>00090                                 req-&gt;<a class="code" href="structdwc__otg__pcd__request.html#0fd7d659f353273d8b2b22027306a2a2">actual</a>);
+<a name="l00091"></a>00091         DWC_SPINLOCK(ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#234391334e48cbd72710d08655c9ed16">pcd</a>-&gt;<a class="code" href="structdwc__otg__pcd.html#5d450e4d06659ab2f3b18e5c816776e4">lock</a>);
+<a name="l00092"></a>00092 
+<a name="l00093"></a>00093         <span class="keywordflow">if</span> (ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#234391334e48cbd72710d08655c9ed16">pcd</a>-&gt;<a class="code" href="structdwc__otg__pcd.html#3a0464b4ac677a7742e9b7c0c820414c">request_pending</a> &gt; 0) {
+<a name="l00094"></a>00094                 --ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#234391334e48cbd72710d08655c9ed16">pcd</a>-&gt;<a class="code" href="structdwc__otg__pcd.html#3a0464b4ac677a7742e9b7c0c820414c">request_pending</a>;
+<a name="l00095"></a>00095         }
+<a name="l00096"></a>00096 
+<a name="l00097"></a>00097         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#cce0e089118d8bf7c6278c21ded70d5a">stopped</a> = stopped;
+<a name="l00098"></a>00098         dwc_free(req);
+<a name="l00099"></a>00099 }
+<a name="l00100"></a>00100 
+<a name="l00104"></a><a class="code" href="dwc__otg__pcd_8h.html#e8ef6f3d831b89a753d93489827949d3">00104</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd_8c.html#e8ef6f3d831b89a753d93489827949d3">dwc_otg_request_nuke</a>(<a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> * ep)
+<a name="l00105"></a>00105 {
+<a name="l00106"></a>00106         <a class="code" href="structdwc__otg__pcd__request.html">dwc_otg_pcd_request_t</a> *req;
+<a name="l00107"></a>00107 
+<a name="l00108"></a>00108         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#cce0e089118d8bf7c6278c21ded70d5a">stopped</a> = 1;
+<a name="l00109"></a>00109 
+<a name="l00110"></a>00110         <span class="comment">/* called with irqs blocked?? */</span>
+<a name="l00111"></a>00111         <span class="keywordflow">while</span> (!DWC_CIRCLEQ_EMPTY(&amp;ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#71f4fa571dfdc96f62fa4869e6add300">queue</a>)) {
+<a name="l00112"></a>00112                 req = DWC_CIRCLEQ_FIRST(&amp;ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#71f4fa571dfdc96f62fa4869e6add300">queue</a>);
+<a name="l00113"></a>00113                 <a class="code" href="dwc__otg__pcd_8c.html#5c9b20abc81e0f860a8f23c90b10b59e">dwc_otg_request_done</a>(ep, req, -DWC_E_SHUTDOWN);
+<a name="l00114"></a>00114         }
+<a name="l00115"></a>00115 }
+<a name="l00116"></a>00116 
+<a name="l00117"></a><a class="code" href="dwc__otg__pcd__if_8h.html#187209231d66bc200444c0d52331d276">00117</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd_8c.html#187209231d66bc200444c0d52331d276">dwc_otg_pcd_start</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd,
+<a name="l00118"></a>00118                        <span class="keyword">const</span> <span class="keyword">struct</span> <a class="code" href="structdwc__otg__pcd__function__ops.html">dwc_otg_pcd_function_ops</a> *<a class="code" href="dwc__otg__pcd__linux_8c.html#9ce9b5e49c60906c189bee157dd68acd">fops</a>)
+<a name="l00119"></a>00119 {
+<a name="l00120"></a>00120         pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#b7001dde5db2706707a860da0030d9e6">fops</a> = <a class="code" href="dwc__otg__pcd__linux_8c.html#9ce9b5e49c60906c189bee157dd68acd">fops</a>;
+<a name="l00121"></a>00121 }
+<a name="l00122"></a>00122 
+<a name="l00129"></a><a class="code" href="dwc__otg__pcd_8c.html#81693a91f25fb36b1443d3e597f9e59d">00129</a> <span class="keyword">static</span> int32_t <a class="code" href="dwc__otg__pcd_8c.html#81693a91f25fb36b1443d3e597f9e59d">dwc_otg_pcd_start_cb</a>(<span class="keywordtype">void</span> *p)
+<a name="l00130"></a>00130 {
+<a name="l00131"></a>00131         <a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd = (<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *) p;
+<a name="l00132"></a>00132 
+<a name="l00133"></a>00133         <span class="comment">/*</span>
+<a name="l00134"></a>00134 <span class="comment">         * Initialized the Core for Device mode.</span>
+<a name="l00135"></a>00135 <span class="comment">         */</span>
+<a name="l00136"></a>00136         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#e83fb22890bc54c6b06cedb751430e77">dwc_otg_is_device_mode</a>(<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd))) {
+<a name="l00137"></a>00137                 <a class="code" href="dwc__otg__cil_8c.html#f79b0f3b5b96b0535e33627ee3a66eba">dwc_otg_core_dev_init</a>(<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd));
+<a name="l00138"></a>00138         }
+<a name="l00139"></a>00139         <span class="keywordflow">return</span> 1;
+<a name="l00140"></a>00140 }
+<a name="l00141"></a>00141 
+<a name="l00143"></a>00143 <span class="preprocessor">#ifdef DWC_UTE_CFI</span>
+<a name="l00144"></a>00144 <span class="preprocessor"></span>uint8_t *<a class="code" href="dwc__otg__pcd_8c.html#3951259aaef3df35d1955076a907f095">cfiw_ep_alloc_buffer</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd, <span class="keywordtype">void</span> *pep, dwc_dma_t * addr,
+<a name="l00145"></a>00145                               size_t buflen, <span class="keywordtype">int</span> flags)
+<a name="l00146"></a>00146 {
+<a name="l00147"></a>00147         <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *ep;
+<a name="l00148"></a>00148         ep = <a class="code" href="dwc__otg__pcd_8c.html#4b46c226fa34cd7fc4ceec2c5e7f8ebe">get_ep_from_handle</a>(pcd, pep);
+<a name="l00149"></a>00149         <span class="keywordflow">return</span> pcd-&gt;cfi-&gt;ops.ep_alloc_buf(pcd-&gt;cfi, pcd, ep, addr, buflen,
+<a name="l00150"></a>00150                                           flags);
+<a name="l00151"></a>00151 }
+<a name="l00152"></a>00152 <span class="preprocessor">#else</span>
+<a name="l00153"></a>00153 <span class="preprocessor"></span>uint8_t *<a class="code" href="dwc__otg__pcd_8c.html#3951259aaef3df35d1955076a907f095">cfiw_ep_alloc_buffer</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd, <span class="keywordtype">void</span> *pep, dwc_dma_t * addr,
+<a name="l00154"></a>00154                               size_t buflen, <span class="keywordtype">int</span> flags);
+<a name="l00155"></a>00155 <span class="preprocessor">#endif</span>
+<a name="l00156"></a>00156 <span class="preprocessor"></span>
+<a name="l00163"></a><a class="code" href="dwc__otg__pcd_8c.html#7bc757d00f936e5e308e950a17281675">00163</a> <span class="keyword">static</span> int32_t <a class="code" href="dwc__otg__pcd_8c.html#7bc757d00f936e5e308e950a17281675">dwc_otg_pcd_resume_cb</a>(<span class="keywordtype">void</span> *p)
+<a name="l00164"></a>00164 {
+<a name="l00165"></a>00165         <a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd = (<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *) p;
+<a name="l00166"></a>00166 
+<a name="l00167"></a>00167         <span class="keywordflow">if</span> (pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#b7001dde5db2706707a860da0030d9e6">fops</a>-&gt;<a class="code" href="structdwc__otg__pcd__function__ops.html#654870eb85c5356b6a97a514645e5d8c">resume</a>) {
+<a name="l00168"></a>00168                 pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#b7001dde5db2706707a860da0030d9e6">fops</a>-&gt;<a class="code" href="structdwc__otg__pcd__function__ops.html#654870eb85c5356b6a97a514645e5d8c">resume</a>(pcd);
+<a name="l00169"></a>00169         }
+<a name="l00170"></a>00170 
+<a name="l00171"></a>00171         <span class="comment">/* Stop the SRP timeout timer. */</span>
+<a name="l00172"></a>00172         <span class="keywordflow">if</span> ((<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;core_params-&gt;phy_type != <a class="code" href="dwc__otg__core__if_8h.html#f7395410ea596c4c660f61ff41cb38b8">DWC_PHY_TYPE_PARAM_FS</a>)
+<a name="l00173"></a>00173             || (!<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;core_params-&gt;i2c_enable)) {
+<a name="l00174"></a>00174                 <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;srp_timer_started) {
+<a name="l00175"></a>00175                         <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;srp_timer_started = 0;
+<a name="l00176"></a>00176                         DWC_TIMER_CANCEL(pcd-&gt;srp_timer);
+<a name="l00177"></a>00177                 }
+<a name="l00178"></a>00178         }
+<a name="l00179"></a>00179         <span class="keywordflow">return</span> 1;
+<a name="l00180"></a>00180 }
+<a name="l00181"></a>00181 
+<a name="l00187"></a><a class="code" href="dwc__otg__pcd_8c.html#41a824bd34aa279d07ba3a17da35cf11">00187</a> <span class="keyword">static</span> int32_t <a class="code" href="dwc__otg__pcd_8c.html#41a824bd34aa279d07ba3a17da35cf11">dwc_otg_pcd_suspend_cb</a>(<span class="keywordtype">void</span> *p)
+<a name="l00188"></a>00188 {
+<a name="l00189"></a>00189         <a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd = (<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *) p;
+<a name="l00190"></a>00190 
+<a name="l00191"></a>00191         <span class="keywordflow">if</span> (pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#b7001dde5db2706707a860da0030d9e6">fops</a>-&gt;<a class="code" href="structdwc__otg__pcd__function__ops.html#fef8ed359353cb84b7c5ac641d54d296">suspend</a>) {
+<a name="l00192"></a>00192                 pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#b7001dde5db2706707a860da0030d9e6">fops</a>-&gt;<a class="code" href="structdwc__otg__pcd__function__ops.html#fef8ed359353cb84b7c5ac641d54d296">suspend</a>(pcd);
+<a name="l00193"></a>00193         }
+<a name="l00194"></a>00194 
+<a name="l00195"></a>00195         <span class="keywordflow">return</span> 1;
+<a name="l00196"></a>00196 }
+<a name="l00197"></a>00197 
+<a name="l00204"></a><a class="code" href="dwc__otg__pcd_8c.html#00e06d719bfc4fa4c40c8a06a88eb052">00204</a> <span class="keyword">static</span> int32_t <a class="code" href="dwc__otg__pcd_8c.html#00e06d719bfc4fa4c40c8a06a88eb052">dwc_otg_pcd_stop_cb</a>(<span class="keywordtype">void</span> *p)
+<a name="l00205"></a>00205 {
+<a name="l00206"></a>00206         <a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd = (<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *) p;
+<a name="l00207"></a>00207         <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd__intr_8c.html#19e17d6a73d8a3ebf00a1d11999a5ff9">dwc_otg_pcd_stop</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * _pcd);
+<a name="l00208"></a>00208 
+<a name="l00209"></a>00209         <a class="code" href="dwc__otg__pcd__intr_8c.html#19e17d6a73d8a3ebf00a1d11999a5ff9">dwc_otg_pcd_stop</a>(pcd);
+<a name="l00210"></a>00210         <span class="keywordflow">return</span> 1;
+<a name="l00211"></a>00211 }
+<a name="l00212"></a>00212 
+<a name="l00216"></a><a class="code" href="dwc__otg__pcd_8c.html#c360aaa36ba28b977284fd482e7bc5ca">00216</a> <span class="keyword">static</span> <a class="code" href="structdwc__otg__cil__callbacks.html">dwc_otg_cil_callbacks_t</a> <a class="code" href="dwc__otg__pcd_8c.html#c360aaa36ba28b977284fd482e7bc5ca">pcd_callbacks</a> = {
+<a name="l00217"></a>00217         .<a class="code" href="structdwc__otg__cil__callbacks.html#ebb662b2e0b4d187648b7f91b9d00713">start</a> = <a class="code" href="dwc__otg__pcd_8c.html#81693a91f25fb36b1443d3e597f9e59d">dwc_otg_pcd_start_cb</a>,
+<a name="l00218"></a>00218         .stop = <a class="code" href="dwc__otg__pcd_8c.html#00e06d719bfc4fa4c40c8a06a88eb052">dwc_otg_pcd_stop_cb</a>,
+<a name="l00219"></a>00219         .suspend = <a class="code" href="dwc__otg__pcd_8c.html#41a824bd34aa279d07ba3a17da35cf11">dwc_otg_pcd_suspend_cb</a>,
+<a name="l00220"></a>00220         .resume_wakeup = <a class="code" href="dwc__otg__pcd_8c.html#7bc757d00f936e5e308e950a17281675">dwc_otg_pcd_resume_cb</a>,
+<a name="l00221"></a>00221         .p = 0,                 <span class="comment">/* Set at registration */</span>
+<a name="l00222"></a>00222 };
+<a name="l00223"></a>00223 
+<a name="l00228"></a><a class="code" href="dwc__otg__pcd_8c.html#18b4a856523673f3bf97b676c8d9717e">00228</a> <a class="code" href="structdwc__otg__dev__dma__desc.html">dwc_otg_dev_dma_desc_t</a> *<a class="code" href="dwc__otg__pcd_8c.html#18b4a856523673f3bf97b676c8d9717e">dwc_otg_ep_alloc_desc_chain</a>(uint32_t * dma_desc_addr,
+<a name="l00229"></a>00229                                                 uint32_t count)
+<a name="l00230"></a>00230 {
+<a name="l00231"></a>00231 
+<a name="l00232"></a>00232         <span class="keywordflow">return</span> dwc_dma_alloc(count * <span class="keyword">sizeof</span>(<a class="code" href="structdwc__otg__dev__dma__desc.html">dwc_otg_dev_dma_desc_t</a>), dma_desc_addr);
+<a name="l00233"></a>00233 }
+<a name="l00234"></a>00234 
+<a name="l00238"></a><a class="code" href="dwc__otg__pcd_8c.html#1926b61a7438bd9a14bd6d6a26c6a63d">00238</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd_8c.html#1926b61a7438bd9a14bd6d6a26c6a63d">dwc_otg_ep_free_desc_chain</a>(<a class="code" href="structdwc__otg__dev__dma__desc.html">dwc_otg_dev_dma_desc_t</a> * desc_addr,
+<a name="l00239"></a>00239                                 uint32_t dma_desc_addr, uint32_t count)
+<a name="l00240"></a>00240 {
+<a name="l00241"></a>00241         dwc_dma_free(count * <span class="keyword">sizeof</span>(<a class="code" href="structdwc__otg__dev__dma__desc.html">dwc_otg_dev_dma_desc_t</a>), desc_addr,
+<a name="l00242"></a>00242                      dma_desc_addr);
+<a name="l00243"></a>00243 }
+<a name="l00244"></a>00244 
+<a name="l00245"></a>00245 <span class="preprocessor">#ifdef DWC_EN_ISOC</span>
+<a name="l00246"></a>00246 <span class="preprocessor"></span>
+<a name="l00254"></a><a class="code" href="dwc__otg__pcd_8c.html#456f7e798e18c0b169fc196fb305e2ea">00254</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd_8c.html#456f7e798e18c0b169fc196fb305e2ea">dwc_otg_iso_ep_start_ddma_transfer</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if,
+<a name="l00255"></a>00255                                         <a class="code" href="structdwc__ep.html">dwc_ep_t</a> * <a class="code" href="structdwc__ep.html">dwc_ep</a>)
+<a name="l00256"></a>00256 {
+<a name="l00257"></a>00257 
+<a name="l00258"></a>00258         <a class="code" href="uniondsts__data.html">dsts_data_t</a> dsts = {.d32 = 0 };
+<a name="l00259"></a>00259         <a class="code" href="uniondepctl__data.html">depctl_data_t</a> depctl = {.d32 = 0 };
+<a name="l00260"></a>00260         <span class="keyword">volatile</span> uint32_t *addr;
+<a name="l00261"></a>00261         <span class="keywordtype">int</span> i, j;
+<a name="l00262"></a>00262 
+<a name="l00263"></a>00263         <span class="keywordflow">if</span> (dwc_ep-&gt;<a class="code" href="structdwc__ep.html#b882b6b7c857100ed20600e94ea37760">is_in</a>)
+<a name="l00264"></a>00264                 dwc_ep-&gt;<a class="code" href="structdwc__ep.html#5e5bfcc93d41670bc0d29ad5f0f35871">desc_cnt</a> = dwc_ep-&gt;<a class="code" href="structdwc__ep.html#4638b25387e59a5a4721a503b5279dfc">buf_proc_intrvl</a> / dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d9e9ffe348764ababc3165ed04f9ec6c">bInterval</a>;
+<a name="l00265"></a>00265         <span class="keywordflow">else</span>
+<a name="l00266"></a>00266                 dwc_ep-&gt;<a class="code" href="structdwc__ep.html#5e5bfcc93d41670bc0d29ad5f0f35871">desc_cnt</a> =
+<a name="l00267"></a>00267                     dwc_ep-&gt;<a class="code" href="structdwc__ep.html#4638b25387e59a5a4721a503b5279dfc">buf_proc_intrvl</a> * dwc_ep-&gt;<a class="code" href="structdwc__ep.html#fe51420474de8a9d74fc9c4adc811c4b">pkt_per_frm</a> /
+<a name="l00268"></a>00268                     dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d9e9ffe348764ababc3165ed04f9ec6c">bInterval</a>;
+<a name="l00269"></a>00269 
+<a name="l00271"></a>00271         dwc_ep-&gt;<a class="code" href="structdwc__ep.html#a4e11d12099ad64dd5048a3a210fc9f6">iso_desc_addr</a> =
+<a name="l00272"></a>00272             <a class="code" href="dwc__otg__pcd_8c.html#18b4a856523673f3bf97b676c8d9717e">dwc_otg_ep_alloc_desc_chain</a>(&amp;dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d571f49545171ea167193edac7984173">iso_dma_desc_addr</a>,
+<a name="l00273"></a>00273                                         dwc_ep-&gt;<a class="code" href="structdwc__ep.html#5e5bfcc93d41670bc0d29ad5f0f35871">desc_cnt</a> * 2);
+<a name="l00274"></a>00274         <span class="keywordflow">if</span> (dwc_ep-&gt;<a class="code" href="structdwc__ep.html#57e934b26e76939912eaa76321075a0d">desc_addr</a>) {
+<a name="l00275"></a>00275                 DWC_WARN(<span class="stringliteral">"%s, can't allocate DMA descriptor chain\n"</span>, __func__);
+<a name="l00276"></a>00276                 <span class="keywordflow">return</span>;
+<a name="l00277"></a>00277         }
+<a name="l00278"></a>00278 
+<a name="l00279"></a>00279         dsts.<a class="code" href="uniondsts__data.html#0f126daef735b142b06dbc4cdbe13814">d32</a> = dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#1ed00edd20ce5db7d07666804101ec05">dsts</a>);
+<a name="l00280"></a>00280 
+<a name="l00282"></a>00282         <span class="keywordflow">if</span> (dwc_ep-&gt;<a class="code" href="structdwc__ep.html#b882b6b7c857100ed20600e94ea37760">is_in</a> == 0) {
+<a name="l00283"></a>00283                 <a class="code" href="uniondev__dma__desc__sts.html">dev_dma_desc_sts_t</a> sts = {.d32 = 0 };
+<a name="l00284"></a>00284                 <a class="code" href="structdwc__otg__dev__dma__desc.html">dwc_otg_dev_dma_desc_t</a> *dma_desc = dwc_ep-&gt;<a class="code" href="structdwc__ep.html#a4e11d12099ad64dd5048a3a210fc9f6">iso_desc_addr</a>;
+<a name="l00285"></a>00285                 dma_addr_t dma_ad;
+<a name="l00286"></a>00286                 uint32_t data_per_desc;
+<a name="l00287"></a>00287                 <a class="code" href="structdwc__otg__dev__out__ep__regs.html">dwc_otg_dev_out_ep_regs_t</a> *out_regs =
+<a name="l00288"></a>00288                     core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">out_ep_regs</a>[dwc_ep-&gt;<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a>];
+<a name="l00289"></a>00289                 <span class="keywordtype">int</span> offset;
+<a name="l00290"></a>00290 
+<a name="l00291"></a>00291                 addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">out_ep_regs</a>[dwc_ep-&gt;<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a>]-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#2a522b71fc97658c07debf3521f7d3e5">doepctl</a>;
+<a name="l00292"></a>00292                 dma_ad = (dma_addr_t) dwc_read_reg32(&amp;(out_regs-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#006071bf54bfa1c1f5e25cf4c9f65cb1">doepdma</a>));
+<a name="l00293"></a>00293 
+<a name="l00295"></a>00295                 dma_ad = dwc_ep-&gt;<a class="code" href="structdwc__ep.html#553936d1d003413d00a24330274887f9">dma_addr0</a>;
+<a name="l00296"></a>00296 
+<a name="l00297"></a>00297                 sts.<a class="code" href="uniondev__dma__desc__sts.html#214ba099b6077c3393b179cf9a7909f7">b_iso_out</a>.<a class="code" href="uniondev__dma__desc__sts.html#05d1c1d8f6c5a1967c51c5d0e2e04261">bs</a> = <a class="code" href="dwc__otg__regs_8h.html#c2cfc53da94087a90d21d3528b005bcf">BS_HOST_READY</a>;
+<a name="l00298"></a>00298                 sts.<a class="code" href="uniondev__dma__desc__sts.html#214ba099b6077c3393b179cf9a7909f7">b_iso_out</a>.<a class="code" href="uniondev__dma__desc__sts.html#a80809cda5b19b3e36f512effef795f0">rxsts</a> = 0;
+<a name="l00299"></a>00299                 sts.<a class="code" href="uniondev__dma__desc__sts.html#214ba099b6077c3393b179cf9a7909f7">b_iso_out</a>.<a class="code" href="uniondev__dma__desc__sts.html#b728a79d6a86a0d1b6426a1b2627f2c2">l</a> = 0;
+<a name="l00300"></a>00300                 sts.<a class="code" href="uniondev__dma__desc__sts.html#214ba099b6077c3393b179cf9a7909f7">b_iso_out</a>.<a class="code" href="uniondev__dma__desc__sts.html#a850ddfa13601227c05e0ae43a538a9d">sp</a> = 0;
+<a name="l00301"></a>00301                 sts.<a class="code" href="uniondev__dma__desc__sts.html#214ba099b6077c3393b179cf9a7909f7">b_iso_out</a>.<a class="code" href="uniondev__dma__desc__sts.html#02c8be72ef6258c25094478c7cac0b12">ioc</a> = 0;
+<a name="l00302"></a>00302                 sts.<a class="code" href="uniondev__dma__desc__sts.html#214ba099b6077c3393b179cf9a7909f7">b_iso_out</a>.<a class="code" href="uniondev__dma__desc__sts.html#79bf5fe6d9949ddb671daa14b5ee298e">pid</a> = 0;
+<a name="l00303"></a>00303                 sts.<a class="code" href="uniondev__dma__desc__sts.html#214ba099b6077c3393b179cf9a7909f7">b_iso_out</a>.<a class="code" href="uniondev__dma__desc__sts.html#d9da3eccc6d247e2b5eccd4dfba7874e">framenum</a> = 0;
+<a name="l00304"></a>00304 
+<a name="l00305"></a>00305                 offset = 0;
+<a name="l00306"></a>00306                 <span class="keywordflow">for</span> (i = 0; i &lt; dwc_ep-&gt;<a class="code" href="structdwc__ep.html#5e5bfcc93d41670bc0d29ad5f0f35871">desc_cnt</a> - dwc_ep-&gt;<a class="code" href="structdwc__ep.html#fe51420474de8a9d74fc9c4adc811c4b">pkt_per_frm</a>;
+<a name="l00307"></a>00307                      i += dwc_ep-&gt;<a class="code" href="structdwc__ep.html#fe51420474de8a9d74fc9c4adc811c4b">pkt_per_frm</a>) {
+<a name="l00308"></a>00308 
+<a name="l00309"></a>00309                         <span class="keywordflow">for</span> (j = 0; j &lt; dwc_ep-&gt;<a class="code" href="structdwc__ep.html#fe51420474de8a9d74fc9c4adc811c4b">pkt_per_frm</a>; ++j) {
+<a name="l00310"></a>00310                                 data_per_desc =
+<a name="l00311"></a>00311                                     ((j + 1) * dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a> &gt;
+<a name="l00312"></a>00312                                      dwc_ep-&gt;<a class="code" href="structdwc__ep.html#4672369f4724db642856d72d5048213e">data_per_frame</a>) ? dwc_ep-&gt;
+<a name="l00313"></a>00313                                     data_per_frame -
+<a name="l00314"></a>00314                                     j * dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a> : dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a>;
+<a name="l00315"></a>00315 
+<a name="l00316"></a>00316                                 data_per_desc +=
+<a name="l00317"></a>00317                                     (data_per_desc % 4) ? (4 -
+<a name="l00318"></a>00318                                                            data_per_desc %
+<a name="l00319"></a>00319                                                            4) : 0;
+<a name="l00320"></a>00320                                 sts.<a class="code" href="uniondev__dma__desc__sts.html#214ba099b6077c3393b179cf9a7909f7">b_iso_out</a>.<a class="code" href="uniondev__dma__desc__sts.html#ede78801cd7bc514474fcbe1ef154e5a">rxbytes</a> = data_per_desc;
+<a name="l00321"></a>00321                                 dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#0454dad420ef536fe5eb7c38ef764430">buf</a> = dma_ad;
+<a name="l00322"></a>00322                                 dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#fb77b9c4ab63304073542ed2b118a64b">d32</a> = sts.<a class="code" href="uniondev__dma__desc__sts.html#fb77b9c4ab63304073542ed2b118a64b">d32</a>;
+<a name="l00323"></a>00323 
+<a name="l00324"></a>00324                                 offset += data_per_desc;
+<a name="l00325"></a>00325                                 dma_desc++;
+<a name="l00326"></a>00326                                 dma_ad += data_per_desc;
+<a name="l00327"></a>00327                         }
+<a name="l00328"></a>00328                 }
+<a name="l00329"></a>00329 
+<a name="l00330"></a>00330                 <span class="keywordflow">for</span> (j = 0; j &lt; dwc_ep-&gt;<a class="code" href="structdwc__ep.html#fe51420474de8a9d74fc9c4adc811c4b">pkt_per_frm</a> - 1; ++j) {
+<a name="l00331"></a>00331                         data_per_desc =
+<a name="l00332"></a>00332                             ((j + 1) * dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a> &gt;
+<a name="l00333"></a>00333                              dwc_ep-&gt;<a class="code" href="structdwc__ep.html#4672369f4724db642856d72d5048213e">data_per_frame</a>) ? dwc_ep-&gt;<a class="code" href="structdwc__ep.html#4672369f4724db642856d72d5048213e">data_per_frame</a> -
+<a name="l00334"></a>00334                             j * dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a> : dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a>;
+<a name="l00335"></a>00335                         data_per_desc +=
+<a name="l00336"></a>00336                             (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
+<a name="l00337"></a>00337                         sts.<a class="code" href="uniondev__dma__desc__sts.html#214ba099b6077c3393b179cf9a7909f7">b_iso_out</a>.<a class="code" href="uniondev__dma__desc__sts.html#ede78801cd7bc514474fcbe1ef154e5a">rxbytes</a> = data_per_desc;
+<a name="l00338"></a>00338                         dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#0454dad420ef536fe5eb7c38ef764430">buf</a> = dma_ad;
+<a name="l00339"></a>00339                         dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#fb77b9c4ab63304073542ed2b118a64b">d32</a> = sts.<a class="code" href="uniondev__dma__desc__sts.html#fb77b9c4ab63304073542ed2b118a64b">d32</a>;
+<a name="l00340"></a>00340 
+<a name="l00341"></a>00341                         offset += data_per_desc;
+<a name="l00342"></a>00342                         dma_desc++;
+<a name="l00343"></a>00343                         dma_ad += data_per_desc;
+<a name="l00344"></a>00344                 }
+<a name="l00345"></a>00345 
+<a name="l00346"></a>00346                 sts.<a class="code" href="uniondev__dma__desc__sts.html#214ba099b6077c3393b179cf9a7909f7">b_iso_out</a>.<a class="code" href="uniondev__dma__desc__sts.html#02c8be72ef6258c25094478c7cac0b12">ioc</a> = 1;
+<a name="l00347"></a>00347                 data_per_desc =
+<a name="l00348"></a>00348                     ((j + 1) * dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a> &gt;
+<a name="l00349"></a>00349                      dwc_ep-&gt;<a class="code" href="structdwc__ep.html#4672369f4724db642856d72d5048213e">data_per_frame</a>) ? dwc_ep-&gt;<a class="code" href="structdwc__ep.html#4672369f4724db642856d72d5048213e">data_per_frame</a> -
+<a name="l00350"></a>00350                     j * dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a> : dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a>;
+<a name="l00351"></a>00351                 data_per_desc +=
+<a name="l00352"></a>00352                     (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
+<a name="l00353"></a>00353                 sts.<a class="code" href="uniondev__dma__desc__sts.html#214ba099b6077c3393b179cf9a7909f7">b_iso_out</a>.<a class="code" href="uniondev__dma__desc__sts.html#ede78801cd7bc514474fcbe1ef154e5a">rxbytes</a> = data_per_desc;
+<a name="l00354"></a>00354 
+<a name="l00355"></a>00355                 dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#0454dad420ef536fe5eb7c38ef764430">buf</a> = dma_ad;
+<a name="l00356"></a>00356                 dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#fb77b9c4ab63304073542ed2b118a64b">d32</a> = sts.<a class="code" href="uniondev__dma__desc__sts.html#fb77b9c4ab63304073542ed2b118a64b">d32</a>;
+<a name="l00357"></a>00357                 dma_desc++;
+<a name="l00358"></a>00358 
+<a name="l00360"></a>00360                 sts.<a class="code" href="uniondev__dma__desc__sts.html#214ba099b6077c3393b179cf9a7909f7">b_iso_out</a>.<a class="code" href="uniondev__dma__desc__sts.html#02c8be72ef6258c25094478c7cac0b12">ioc</a> = 0;
+<a name="l00361"></a>00361                 dma_ad = dwc_ep-&gt;<a class="code" href="structdwc__ep.html#02dc1be77d505b19f14651fe9805c97f">dma_addr1</a>;
+<a name="l00362"></a>00362 
+<a name="l00363"></a>00363                 offset = 0;
+<a name="l00364"></a>00364                 for (i = 0; i &lt; dwc_ep-&gt;<a class="code" href="structdwc__ep.html#5e5bfcc93d41670bc0d29ad5f0f35871">desc_cnt</a> - dwc_ep-&gt;<a class="code" href="structdwc__ep.html#fe51420474de8a9d74fc9c4adc811c4b">pkt_per_frm</a>;
+<a name="l00365"></a>00365                      i += dwc_ep-&gt;<a class="code" href="structdwc__ep.html#fe51420474de8a9d74fc9c4adc811c4b">pkt_per_frm</a>) {
+<a name="l00366"></a>00366                         <span class="keywordflow">for</span> (j = 0; j &lt; dwc_ep-&gt;<a class="code" href="structdwc__ep.html#fe51420474de8a9d74fc9c4adc811c4b">pkt_per_frm</a>; ++j) {
+<a name="l00367"></a>00367                                 data_per_desc =
+<a name="l00368"></a>00368                                     ((j + 1) * dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a> &gt;
+<a name="l00369"></a>00369                                      dwc_ep-&gt;<a class="code" href="structdwc__ep.html#4672369f4724db642856d72d5048213e">data_per_frame</a>) ? dwc_ep-&gt;
+<a name="l00370"></a>00370                                     data_per_frame -
+<a name="l00371"></a>00371                                     j * dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a> : dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a>;
+<a name="l00372"></a>00372                                 data_per_desc +=
+<a name="l00373"></a>00373                                     (data_per_desc % 4) ? (4 -
+<a name="l00374"></a>00374                                                            data_per_desc %
+<a name="l00375"></a>00375                                                            4) : 0;
+<a name="l00376"></a>00376                                 sts.<a class="code" href="uniondev__dma__desc__sts.html#214ba099b6077c3393b179cf9a7909f7">b_iso_out</a>.<a class="code" href="uniondev__dma__desc__sts.html#ede78801cd7bc514474fcbe1ef154e5a">rxbytes</a> = data_per_desc;
+<a name="l00377"></a>00377                                 dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#0454dad420ef536fe5eb7c38ef764430">buf</a> = dma_ad;
+<a name="l00378"></a>00378                                 dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#fb77b9c4ab63304073542ed2b118a64b">d32</a> = sts.<a class="code" href="uniondev__dma__desc__sts.html#fb77b9c4ab63304073542ed2b118a64b">d32</a>;
+<a name="l00379"></a>00379 
+<a name="l00380"></a>00380                                 offset += data_per_desc;
+<a name="l00381"></a>00381                                 dma_desc++;
+<a name="l00382"></a>00382                                 dma_ad += data_per_desc;
+<a name="l00383"></a>00383                         }
+<a name="l00384"></a>00384                 }
+<a name="l00385"></a>00385                 <span class="keywordflow">for</span> (j = 0; j &lt; dwc_ep-&gt;<a class="code" href="structdwc__ep.html#fe51420474de8a9d74fc9c4adc811c4b">pkt_per_frm</a> - 1; ++j) {
+<a name="l00386"></a>00386                         data_per_desc =
+<a name="l00387"></a>00387                             ((j + 1) * dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a> &gt;
+<a name="l00388"></a>00388                              dwc_ep-&gt;<a class="code" href="structdwc__ep.html#4672369f4724db642856d72d5048213e">data_per_frame</a>) ? dwc_ep-&gt;<a class="code" href="structdwc__ep.html#4672369f4724db642856d72d5048213e">data_per_frame</a> -
+<a name="l00389"></a>00389                             j * dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a> : dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a>;
+<a name="l00390"></a>00390                         data_per_desc +=
+<a name="l00391"></a>00391                             (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
+<a name="l00392"></a>00392                         sts.<a class="code" href="uniondev__dma__desc__sts.html#214ba099b6077c3393b179cf9a7909f7">b_iso_out</a>.<a class="code" href="uniondev__dma__desc__sts.html#ede78801cd7bc514474fcbe1ef154e5a">rxbytes</a> = data_per_desc;
+<a name="l00393"></a>00393                         dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#0454dad420ef536fe5eb7c38ef764430">buf</a> = dma_ad;
+<a name="l00394"></a>00394                         dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#fb77b9c4ab63304073542ed2b118a64b">d32</a> = sts.<a class="code" href="uniondev__dma__desc__sts.html#fb77b9c4ab63304073542ed2b118a64b">d32</a>;
+<a name="l00395"></a>00395 
+<a name="l00396"></a>00396                         offset += data_per_desc;
+<a name="l00397"></a>00397                         dma_desc++;
+<a name="l00398"></a>00398                         dma_ad += data_per_desc;
+<a name="l00399"></a>00399                 }
+<a name="l00400"></a>00400 
+<a name="l00401"></a>00401                 sts.<a class="code" href="uniondev__dma__desc__sts.html#214ba099b6077c3393b179cf9a7909f7">b_iso_out</a>.<a class="code" href="uniondev__dma__desc__sts.html#02c8be72ef6258c25094478c7cac0b12">ioc</a> = 1;
+<a name="l00402"></a>00402                 sts.<a class="code" href="uniondev__dma__desc__sts.html#214ba099b6077c3393b179cf9a7909f7">b_iso_out</a>.<a class="code" href="uniondev__dma__desc__sts.html#b728a79d6a86a0d1b6426a1b2627f2c2">l</a> = 1;
+<a name="l00403"></a>00403                 data_per_desc =
+<a name="l00404"></a>00404                     ((j + 1) * dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a> &gt;
+<a name="l00405"></a>00405                      dwc_ep-&gt;<a class="code" href="structdwc__ep.html#4672369f4724db642856d72d5048213e">data_per_frame</a>) ? dwc_ep-&gt;<a class="code" href="structdwc__ep.html#4672369f4724db642856d72d5048213e">data_per_frame</a> -
+<a name="l00406"></a>00406                     j * dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a> : dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a>;
+<a name="l00407"></a>00407                 data_per_desc +=
+<a name="l00408"></a>00408                     (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
+<a name="l00409"></a>00409                 sts.<a class="code" href="uniondev__dma__desc__sts.html#214ba099b6077c3393b179cf9a7909f7">b_iso_out</a>.<a class="code" href="uniondev__dma__desc__sts.html#ede78801cd7bc514474fcbe1ef154e5a">rxbytes</a> = data_per_desc;
+<a name="l00410"></a>00410 
+<a name="l00411"></a>00411                 dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#0454dad420ef536fe5eb7c38ef764430">buf</a> = dma_ad;
+<a name="l00412"></a>00412                 dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#fb77b9c4ab63304073542ed2b118a64b">d32</a> = sts.<a class="code" href="uniondev__dma__desc__sts.html#fb77b9c4ab63304073542ed2b118a64b">d32</a>;
+<a name="l00413"></a>00413 
+<a name="l00414"></a>00414                 dwc_ep-&gt;<a class="code" href="structdwc__ep.html#1e9f4d08454c973c17acb3e52a2c3689">next_frame</a> = 0;
+<a name="l00415"></a>00415 
+<a name="l00417"></a>00417                 dwc_write_reg32(&amp;(out_regs-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#006071bf54bfa1c1f5e25cf4c9f65cb1">doepdma</a>),
+<a name="l00418"></a>00418                                 (uint32_t) dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d571f49545171ea167193edac7984173">iso_dma_desc_addr</a>);
+<a name="l00419"></a>00419 
+<a name="l00420"></a>00420         }
+<a name="l00422"></a>00422         <span class="keywordflow">else</span> {
+<a name="l00423"></a>00423                 <a class="code" href="uniondev__dma__desc__sts.html">dev_dma_desc_sts_t</a> sts = {.d32 = 0 };
+<a name="l00424"></a>00424                 <a class="code" href="structdwc__otg__dev__dma__desc.html">dwc_otg_dev_dma_desc_t</a> *dma_desc = dwc_ep-&gt;<a class="code" href="structdwc__ep.html#a4e11d12099ad64dd5048a3a210fc9f6">iso_desc_addr</a>;
+<a name="l00425"></a>00425                 dma_addr_t dma_ad;
+<a name="l00426"></a>00426                 <a class="code" href="structdwc__otg__dev__in__ep__regs.html">dwc_otg_dev_in_ep_regs_t</a> *in_regs =
+<a name="l00427"></a>00427                     core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[dwc_ep-&gt;<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a>];
+<a name="l00428"></a>00428                 <span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> frmnumber;
+<a name="l00429"></a>00429                 <a class="code" href="unionfifosize__data.html">fifosize_data_t</a> txfifosize, rxfifosize;
+<a name="l00430"></a>00430 
+<a name="l00431"></a>00431                 txfifosize.<a class="code" href="unionfifosize__data.html#937e01b91f0a60a5aa9f6a4eaf6ce661">d32</a> =
+<a name="l00432"></a>00432                     dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[dwc_ep-&gt;<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a>]-&gt;
+<a name="l00433"></a>00433                                    dtxfsts);
+<a name="l00434"></a>00434                 rxfifosize.<a class="code" href="unionfifosize__data.html#937e01b91f0a60a5aa9f6a4eaf6ce661">d32</a> =
+<a name="l00435"></a>00435                     dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#b1a8cc07a9541c9a73e864579602b79b">grxfsiz</a>);
+<a name="l00436"></a>00436 
+<a name="l00437"></a>00437                 addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[dwc_ep-&gt;<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a>]-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#53a5adb977e2aec66d4902c6ba293216">diepctl</a>;
+<a name="l00438"></a>00438 
+<a name="l00439"></a>00439                 dma_ad = dwc_ep-&gt;<a class="code" href="structdwc__ep.html#553936d1d003413d00a24330274887f9">dma_addr0</a>;
+<a name="l00440"></a>00440 
+<a name="l00441"></a>00441                 dsts.<a class="code" href="uniondsts__data.html#0f126daef735b142b06dbc4cdbe13814">d32</a> =
+<a name="l00442"></a>00442                     dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#1ed00edd20ce5db7d07666804101ec05">dsts</a>);
+<a name="l00443"></a>00443 
+<a name="l00444"></a>00444                 sts.<a class="code" href="uniondev__dma__desc__sts.html#324fdd57830243334b74e0579b4e9f96">b_iso_in</a>.<a class="code" href="uniondev__dma__desc__sts.html#05d1c1d8f6c5a1967c51c5d0e2e04261">bs</a> = <a class="code" href="dwc__otg__regs_8h.html#c2cfc53da94087a90d21d3528b005bcf">BS_HOST_READY</a>;
+<a name="l00445"></a>00445                 sts.<a class="code" href="uniondev__dma__desc__sts.html#324fdd57830243334b74e0579b4e9f96">b_iso_in</a>.<a class="code" href="uniondev__dma__desc__sts.html#30ebc024572822f0803d28c95914a44c">txsts</a> = 0;
+<a name="l00446"></a>00446                 sts.<a class="code" href="uniondev__dma__desc__sts.html#324fdd57830243334b74e0579b4e9f96">b_iso_in</a>.<a class="code" href="uniondev__dma__desc__sts.html#a850ddfa13601227c05e0ae43a538a9d">sp</a> =
+<a name="l00447"></a>00447                     (dwc_ep-&gt;<a class="code" href="structdwc__ep.html#4672369f4724db642856d72d5048213e">data_per_frame</a> % dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a>) ? 1 : 0;
+<a name="l00448"></a>00448                 sts.<a class="code" href="uniondev__dma__desc__sts.html#324fdd57830243334b74e0579b4e9f96">b_iso_in</a>.<a class="code" href="uniondev__dma__desc__sts.html#02c8be72ef6258c25094478c7cac0b12">ioc</a> = 0;
+<a name="l00449"></a>00449                 sts.<a class="code" href="uniondev__dma__desc__sts.html#324fdd57830243334b74e0579b4e9f96">b_iso_in</a>.<a class="code" href="uniondev__dma__desc__sts.html#79bf5fe6d9949ddb671daa14b5ee298e">pid</a> = dwc_ep-&gt;<a class="code" href="structdwc__ep.html#fe51420474de8a9d74fc9c4adc811c4b">pkt_per_frm</a>;
+<a name="l00450"></a>00450 
+<a name="l00451"></a>00451                 frmnumber = dwc_ep-&gt;<a class="code" href="structdwc__ep.html#1e9f4d08454c973c17acb3e52a2c3689">next_frame</a>;
+<a name="l00452"></a>00452 
+<a name="l00453"></a>00453                 sts.<a class="code" href="uniondev__dma__desc__sts.html#324fdd57830243334b74e0579b4e9f96">b_iso_in</a>.<a class="code" href="uniondev__dma__desc__sts.html#d9da3eccc6d247e2b5eccd4dfba7874e">framenum</a> = frmnumber;
+<a name="l00454"></a>00454                 sts.<a class="code" href="uniondev__dma__desc__sts.html#324fdd57830243334b74e0579b4e9f96">b_iso_in</a>.<a class="code" href="uniondev__dma__desc__sts.html#56cc3ad6b0e5704c6eb394f58f660eef">txbytes</a> = dwc_ep-&gt;<a class="code" href="structdwc__ep.html#4672369f4724db642856d72d5048213e">data_per_frame</a>;
+<a name="l00455"></a>00455                 sts.<a class="code" href="uniondev__dma__desc__sts.html#324fdd57830243334b74e0579b4e9f96">b_iso_in</a>.<a class="code" href="uniondev__dma__desc__sts.html#b728a79d6a86a0d1b6426a1b2627f2c2">l</a> = 0;
+<a name="l00456"></a>00456 
+<a name="l00458"></a>00458                 <span class="keywordflow">for</span> (i = 0; i &lt; dwc_ep-&gt;<a class="code" href="structdwc__ep.html#5e5bfcc93d41670bc0d29ad5f0f35871">desc_cnt</a> - 1; i++) {
+<a name="l00459"></a>00459                         dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#0454dad420ef536fe5eb7c38ef764430">buf</a> = dma_ad;
+<a name="l00460"></a>00460                         dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#fb77b9c4ab63304073542ed2b118a64b">d32</a> = sts.<a class="code" href="uniondev__dma__desc__sts.html#fb77b9c4ab63304073542ed2b118a64b">d32</a>;
+<a name="l00461"></a>00461                         dma_desc++;
+<a name="l00462"></a>00462 
+<a name="l00463"></a>00463                         dma_ad += dwc_ep-&gt;<a class="code" href="structdwc__ep.html#4672369f4724db642856d72d5048213e">data_per_frame</a>;
+<a name="l00464"></a>00464                         sts.<a class="code" href="uniondev__dma__desc__sts.html#324fdd57830243334b74e0579b4e9f96">b_iso_in</a>.<a class="code" href="uniondev__dma__desc__sts.html#d9da3eccc6d247e2b5eccd4dfba7874e">framenum</a> += dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d9e9ffe348764ababc3165ed04f9ec6c">bInterval</a>;
+<a name="l00465"></a>00465                 }
+<a name="l00466"></a>00466 
+<a name="l00467"></a>00467                 sts.<a class="code" href="uniondev__dma__desc__sts.html#324fdd57830243334b74e0579b4e9f96">b_iso_in</a>.<a class="code" href="uniondev__dma__desc__sts.html#02c8be72ef6258c25094478c7cac0b12">ioc</a> = 1;
+<a name="l00468"></a>00468                 dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#0454dad420ef536fe5eb7c38ef764430">buf</a> = dma_ad;
+<a name="l00469"></a>00469                 dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#fb77b9c4ab63304073542ed2b118a64b">d32</a> = sts.<a class="code" href="uniondev__dma__desc__sts.html#fb77b9c4ab63304073542ed2b118a64b">d32</a>;
+<a name="l00470"></a>00470                 ++dma_desc;
+<a name="l00471"></a>00471 
+<a name="l00473"></a>00473                 sts.<a class="code" href="uniondev__dma__desc__sts.html#324fdd57830243334b74e0579b4e9f96">b_iso_in</a>.<a class="code" href="uniondev__dma__desc__sts.html#02c8be72ef6258c25094478c7cac0b12">ioc</a> = 0;
+<a name="l00474"></a>00474                 dma_ad = dwc_ep-&gt;<a class="code" href="structdwc__ep.html#02dc1be77d505b19f14651fe9805c97f">dma_addr1</a>;
+<a name="l00475"></a>00475 
+<a name="l00476"></a>00476                 <span class="keywordflow">for</span> (i = 0; i &lt; dwc_ep-&gt;<a class="code" href="structdwc__ep.html#5e5bfcc93d41670bc0d29ad5f0f35871">desc_cnt</a> - dwc_ep-&gt;<a class="code" href="structdwc__ep.html#fe51420474de8a9d74fc9c4adc811c4b">pkt_per_frm</a>;
+<a name="l00477"></a>00477                      i += dwc_ep-&gt;<a class="code" href="structdwc__ep.html#fe51420474de8a9d74fc9c4adc811c4b">pkt_per_frm</a>) {
+<a name="l00478"></a>00478                         dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#0454dad420ef536fe5eb7c38ef764430">buf</a> = dma_ad;
+<a name="l00479"></a>00479                         dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#fb77b9c4ab63304073542ed2b118a64b">d32</a> = sts.<a class="code" href="uniondev__dma__desc__sts.html#fb77b9c4ab63304073542ed2b118a64b">d32</a>;
+<a name="l00480"></a>00480                         dma_desc++;
+<a name="l00481"></a>00481 
+<a name="l00482"></a>00482                         dma_ad += dwc_ep-&gt;<a class="code" href="structdwc__ep.html#4672369f4724db642856d72d5048213e">data_per_frame</a>;
+<a name="l00483"></a>00483                         sts.<a class="code" href="uniondev__dma__desc__sts.html#324fdd57830243334b74e0579b4e9f96">b_iso_in</a>.<a class="code" href="uniondev__dma__desc__sts.html#d9da3eccc6d247e2b5eccd4dfba7874e">framenum</a> += dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d9e9ffe348764ababc3165ed04f9ec6c">bInterval</a>;
+<a name="l00484"></a>00484 
+<a name="l00485"></a>00485                         sts.<a class="code" href="uniondev__dma__desc__sts.html#324fdd57830243334b74e0579b4e9f96">b_iso_in</a>.<a class="code" href="uniondev__dma__desc__sts.html#02c8be72ef6258c25094478c7cac0b12">ioc</a> = 0;
+<a name="l00486"></a>00486                 }
+<a name="l00487"></a>00487                 sts.<a class="code" href="uniondev__dma__desc__sts.html#324fdd57830243334b74e0579b4e9f96">b_iso_in</a>.<a class="code" href="uniondev__dma__desc__sts.html#02c8be72ef6258c25094478c7cac0b12">ioc</a> = 1;
+<a name="l00488"></a>00488                 sts.<a class="code" href="uniondev__dma__desc__sts.html#324fdd57830243334b74e0579b4e9f96">b_iso_in</a>.<a class="code" href="uniondev__dma__desc__sts.html#b728a79d6a86a0d1b6426a1b2627f2c2">l</a> = 1;
+<a name="l00489"></a>00489 
+<a name="l00490"></a>00490                 dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#0454dad420ef536fe5eb7c38ef764430">buf</a> = dma_ad;
+<a name="l00491"></a>00491                 dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#fb77b9c4ab63304073542ed2b118a64b">d32</a> = sts.<a class="code" href="uniondev__dma__desc__sts.html#fb77b9c4ab63304073542ed2b118a64b">d32</a>;
+<a name="l00492"></a>00492 
+<a name="l00493"></a>00493                 dwc_ep-&gt;<a class="code" href="structdwc__ep.html#1e9f4d08454c973c17acb3e52a2c3689">next_frame</a> = sts.<a class="code" href="uniondev__dma__desc__sts.html#324fdd57830243334b74e0579b4e9f96">b_iso_in</a>.<a class="code" href="uniondev__dma__desc__sts.html#d9da3eccc6d247e2b5eccd4dfba7874e">framenum</a> + dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d9e9ffe348764ababc3165ed04f9ec6c">bInterval</a>;
+<a name="l00494"></a>00494 
+<a name="l00496"></a>00496                 dwc_write_reg32(&amp;(in_regs-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#5f013840a15e0a310b8722646880a420">diepdma</a>),
+<a name="l00497"></a>00497                                 (uint32_t) dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d571f49545171ea167193edac7984173">iso_dma_desc_addr</a>);
+<a name="l00498"></a>00498         }
+<a name="l00500"></a>00500         depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a> = 0;
+<a name="l00501"></a>00501         depctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#337ceb41a9e0735e144e684b1f9e5368">epena</a> = 1;
+<a name="l00502"></a>00502         depctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#2ddb1e68ac29dfc383dacd94f76b4710">usbactep</a> = 1;
+<a name="l00503"></a>00503         depctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#0b87d0914ceee7a20ffd2d7510b6a72e">cnak</a> = 1;
+<a name="l00504"></a>00504 
+<a name="l00505"></a>00505         dwc_modify_reg32(addr, depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a>, depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a>);
+<a name="l00506"></a>00506         depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a> = dwc_read_reg32(addr);
+<a name="l00507"></a>00507 }
+<a name="l00508"></a>00508 
+<a name="l00517"></a><a class="code" href="dwc__otg__pcd_8c.html#0b13a31a7ddc82b53862cd06cfed6393">00517</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cil_8h.html#0b13a31a7ddc82b53862cd06cfed6393">dwc_otg_iso_ep_start_buf_transfer</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if,
+<a name="l00518"></a>00518                                        <a class="code" href="structdwc__ep.html">dwc_ep_t</a> * ep)
+<a name="l00519"></a>00519 {
+<a name="l00520"></a>00520         <a class="code" href="uniondepctl__data.html">depctl_data_t</a> depctl = {.d32 = 0 };
+<a name="l00521"></a>00521         <span class="keyword">volatile</span> uint32_t *addr;
+<a name="l00522"></a>00522 
+<a name="l00523"></a>00523         <span class="keywordflow">if</span> (ep-&gt;<a class="code" href="structdwc__ep.html#b882b6b7c857100ed20600e94ea37760">is_in</a>) {
+<a name="l00524"></a>00524                 addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[ep-&gt;<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a>]-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#53a5adb977e2aec66d4902c6ba293216">diepctl</a>;
+<a name="l00525"></a>00525         } <span class="keywordflow">else</span> {
+<a name="l00526"></a>00526                 addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">out_ep_regs</a>[ep-&gt;<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a>]-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#2a522b71fc97658c07debf3521f7d3e5">doepctl</a>;
+<a name="l00527"></a>00527         }
+<a name="l00528"></a>00528 
+<a name="l00529"></a>00529         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a> == 0 || core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a> != 0) {
+<a name="l00530"></a>00530                 <span class="keywordflow">return</span>;
+<a name="l00531"></a>00531         } <span class="keywordflow">else</span> {
+<a name="l00532"></a>00532                 <a class="code" href="uniondeptsiz__data.html">deptsiz_data_t</a> deptsiz = {.d32 = 0 };
+<a name="l00533"></a>00533 
+<a name="l00534"></a>00534                 ep-&gt;<a class="code" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">xfer_len</a> =
+<a name="l00535"></a>00535                     ep-&gt;<a class="code" href="structdwc__ep.html#4672369f4724db642856d72d5048213e">data_per_frame</a> * ep-&gt;<a class="code" href="structdwc__ep.html#4638b25387e59a5a4721a503b5279dfc">buf_proc_intrvl</a> / ep-&gt;<a class="code" href="structdwc__ep.html#d9e9ffe348764ababc3165ed04f9ec6c">bInterval</a>;
+<a name="l00536"></a>00536                 ep-&gt;<a class="code" href="structdwc__ep.html#46349fb0608d8c6849ced211b0628c15">pkt_cnt</a> =
+<a name="l00537"></a>00537                     (ep-&gt;<a class="code" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">xfer_len</a> - 1 + ep-&gt;<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a>) / ep-&gt;<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a>;
+<a name="l00538"></a>00538                 ep-&gt;<a class="code" href="structdwc__ep.html#23d4871510b5bcb54fbf0674d8f122bd">xfer_count</a> = 0;
+<a name="l00539"></a>00539                 ep-&gt;<a class="code" href="structdwc__ep.html#97fa9bf5c31ba734d54f70e6fe6ae8eb">xfer_buff</a> =
+<a name="l00540"></a>00540                     (ep-&gt;<a class="code" href="structdwc__ep.html#53033f174854701986545f05502e1cad">proc_buf_num</a>) ? ep-&gt;<a class="code" href="structdwc__ep.html#36ff87362a0da5bce95eaf85522d49ff">xfer_buff1</a> : ep-&gt;<a class="code" href="structdwc__ep.html#b6d727e366ac589d304256c758d2d44a">xfer_buff0</a>;
+<a name="l00541"></a>00541                 ep-&gt;<a class="code" href="structdwc__ep.html#b40ce70422b6d105a855a8df4b33d45d">dma_addr</a> =
+<a name="l00542"></a>00542                     (ep-&gt;<a class="code" href="structdwc__ep.html#53033f174854701986545f05502e1cad">proc_buf_num</a>) ? ep-&gt;<a class="code" href="structdwc__ep.html#02dc1be77d505b19f14651fe9805c97f">dma_addr1</a> : ep-&gt;<a class="code" href="structdwc__ep.html#553936d1d003413d00a24330274887f9">dma_addr0</a>;
+<a name="l00543"></a>00543 
+<a name="l00544"></a>00544                 if (ep-&gt;<a class="code" href="structdwc__ep.html#b882b6b7c857100ed20600e94ea37760">is_in</a>) {
+<a name="l00545"></a>00545                         <span class="comment">/* Program the transfer size and packet count</span>
+<a name="l00546"></a>00546 <span class="comment">                         *      as follows: xfersize = N * maxpacket +</span>
+<a name="l00547"></a>00547 <span class="comment">                         *      short_packet pktcnt = N + (short_packet</span>
+<a name="l00548"></a>00548 <span class="comment">                         *      exist ? 1 : 0)  </span>
+<a name="l00549"></a>00549 <span class="comment">                         */</span>
+<a name="l00550"></a>00550                         deptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#45a97381fba9a7d9c3bde425334a60a5">mc</a> = ep-&gt;<a class="code" href="structdwc__ep.html#fe51420474de8a9d74fc9c4adc811c4b">pkt_per_frm</a>;
+<a name="l00551"></a>00551                         deptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#cf06327d851e7cfe5c442b29bf2d6fa4">xfersize</a> = ep-&gt;<a class="code" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">xfer_len</a>;
+<a name="l00552"></a>00552                         deptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#bbd89e812371e5b555bb82373f3643d9">pktcnt</a> =
+<a name="l00553"></a>00553                             (ep-&gt;<a class="code" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">xfer_len</a> - 1 + ep-&gt;<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a>) / ep-&gt;<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a>;
+<a name="l00554"></a>00554                         dwc_write_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[ep-&gt;<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a>]-&gt;
+<a name="l00555"></a>00555                                         dieptsiz, deptsiz.<a class="code" href="uniondeptsiz__data.html#10c2b2ba8b419b0a766430a59befbbe0">d32</a>);
+<a name="l00556"></a>00556 
+<a name="l00557"></a>00557                         <span class="comment">/* Write the DMA register */</span>
+<a name="l00558"></a>00558                         dwc_write_reg32(&amp;
+<a name="l00559"></a>00559                                         (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[ep-&gt;<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a>]-&gt;
+<a name="l00560"></a>00560                                          diepdma), (uint32_t) ep-&gt;<a class="code" href="structdwc__ep.html#b40ce70422b6d105a855a8df4b33d45d">dma_addr</a>);
+<a name="l00561"></a>00561 
+<a name="l00562"></a>00562                 } <span class="keywordflow">else</span> {
+<a name="l00563"></a>00563                         deptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#bbd89e812371e5b555bb82373f3643d9">pktcnt</a> =
+<a name="l00564"></a>00564                             (ep-&gt;<a class="code" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">xfer_len</a> + (ep-&gt;<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a> - 1)) /
+<a name="l00565"></a>00565                             ep-&gt;<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a>;
+<a name="l00566"></a>00566                         deptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#cf06327d851e7cfe5c442b29bf2d6fa4">xfersize</a> = deptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#bbd89e812371e5b555bb82373f3643d9">pktcnt</a> * ep-&gt;<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a>;
+<a name="l00567"></a>00567 
+<a name="l00568"></a>00568                         dwc_write_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">out_ep_regs</a>[ep-&gt;<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a>]-&gt;
+<a name="l00569"></a>00569                                         doeptsiz, deptsiz.<a class="code" href="uniondeptsiz__data.html#10c2b2ba8b419b0a766430a59befbbe0">d32</a>);
+<a name="l00570"></a>00570 
+<a name="l00571"></a>00571                         <span class="comment">/* Write the DMA register */</span>
+<a name="l00572"></a>00572                         dwc_write_reg32(&amp;
+<a name="l00573"></a>00573                                         (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">out_ep_regs</a>[ep-&gt;<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a>]-&gt;
+<a name="l00574"></a>00574                                          doepdma), (uint32_t) ep-&gt;<a class="code" href="structdwc__ep.html#b40ce70422b6d105a855a8df4b33d45d">dma_addr</a>);
+<a name="l00575"></a>00575 
+<a name="l00576"></a>00576                 }
+<a name="l00578"></a>00578                 depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a> = 0;
+<a name="l00579"></a>00579                 dwc_modify_reg32(addr, depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a>, depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a>);
+<a name="l00580"></a>00580 
+<a name="l00581"></a>00581                 depctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#337ceb41a9e0735e144e684b1f9e5368">epena</a> = 1;
+<a name="l00582"></a>00582                 depctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#0b87d0914ceee7a20ffd2d7510b6a72e">cnak</a> = 1;
+<a name="l00583"></a>00583 
+<a name="l00584"></a>00584                 dwc_modify_reg32(addr, depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a>, depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a>);
+<a name="l00585"></a>00585         }
+<a name="l00586"></a>00586 }
+<a name="l00587"></a>00587 
+<a name="l00598"></a><a class="code" href="dwc__otg__pcd_8c.html#3f39ccc23c6f9bd4fd4ab7a5cecc67a3">00598</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd_8c.html#3f39ccc23c6f9bd4fd4ab7a5cecc67a3">dwc_otg_iso_ep_start_transfer</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if,
+<a name="l00599"></a>00599                                           <a class="code" href="structdwc__ep.html">dwc_ep_t</a> * ep)
+<a name="l00600"></a>00600 {
+<a name="l00601"></a>00601         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a>) {
+<a name="l00602"></a>00602                 <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a>) {
+<a name="l00603"></a>00603                         <span class="keywordflow">if</span> (ep-&gt;<a class="code" href="structdwc__ep.html#b882b6b7c857100ed20600e94ea37760">is_in</a>) {
+<a name="l00604"></a>00604                                 ep-&gt;<a class="code" href="structdwc__ep.html#5e5bfcc93d41670bc0d29ad5f0f35871">desc_cnt</a> = ep-&gt;<a class="code" href="structdwc__ep.html#46349fb0608d8c6849ced211b0628c15">pkt_cnt</a> / ep-&gt;<a class="code" href="structdwc__ep.html#fe51420474de8a9d74fc9c4adc811c4b">pkt_per_frm</a>;
+<a name="l00605"></a>00605                         } <span class="keywordflow">else</span> {
+<a name="l00606"></a>00606                                 ep-&gt;<a class="code" href="structdwc__ep.html#5e5bfcc93d41670bc0d29ad5f0f35871">desc_cnt</a> = ep-&gt;<a class="code" href="structdwc__ep.html#46349fb0608d8c6849ced211b0628c15">pkt_cnt</a>;
+<a name="l00607"></a>00607                         }
+<a name="l00608"></a>00608                         <a class="code" href="dwc__otg__pcd_8c.html#456f7e798e18c0b169fc196fb305e2ea">dwc_otg_iso_ep_start_ddma_transfer</a>(core_if, ep);
+<a name="l00609"></a>00609                 } <span class="keywordflow">else</span> {
+<a name="l00610"></a>00610                         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#34540b79e9a14bfa234a52ac132c5cd1">pti_enh_enable</a>) {
+<a name="l00611"></a>00611                                 <a class="code" href="dwc__otg__cil_8h.html#0b13a31a7ddc82b53862cd06cfed6393">dwc_otg_iso_ep_start_buf_transfer</a>(core_if, ep);
+<a name="l00612"></a>00612                         } <span class="keywordflow">else</span> {
+<a name="l00613"></a>00613                                 ep-&gt;<a class="code" href="structdwc__ep.html#d3bc23598a77d3cca52c70a28afc6b5e">cur_pkt_addr</a> =
+<a name="l00614"></a>00614                                     (ep-&gt;<a class="code" href="structdwc__ep.html#53033f174854701986545f05502e1cad">proc_buf_num</a>) ? ep-&gt;<a class="code" href="structdwc__ep.html#36ff87362a0da5bce95eaf85522d49ff">xfer_buff1</a> : ep-&gt;
+<a name="l00615"></a>00615                                     xfer_buff0;
+<a name="l00616"></a>00616                                 ep-&gt;<a class="code" href="structdwc__ep.html#ed4594c9f6c2bcbcf6f1bbe9e9c64061">cur_pkt_dma_addr</a> =
+<a name="l00617"></a>00617                                     (ep-&gt;<a class="code" href="structdwc__ep.html#53033f174854701986545f05502e1cad">proc_buf_num</a>) ? ep-&gt;<a class="code" href="structdwc__ep.html#02dc1be77d505b19f14651fe9805c97f">dma_addr1</a> : ep-&gt;
+<a name="l00618"></a>00618                                     dma_addr0;
+<a name="l00619"></a>00619                                 <a class="code" href="dwc__otg__cil_8c.html#0f0894ae9890260e1da839aa10af35cc">dwc_otg_iso_ep_start_frm_transfer</a>(core_if, ep);
+<a name="l00620"></a>00620                         }
+<a name="l00621"></a>00621                 }
+<a name="l00622"></a>00622         } <span class="keywordflow">else</span> {
+<a name="l00623"></a>00623                 ep-&gt;<a class="code" href="structdwc__ep.html#d3bc23598a77d3cca52c70a28afc6b5e">cur_pkt_addr</a> =
+<a name="l00624"></a>00624                     (ep-&gt;<a class="code" href="structdwc__ep.html#53033f174854701986545f05502e1cad">proc_buf_num</a>) ? ep-&gt;<a class="code" href="structdwc__ep.html#36ff87362a0da5bce95eaf85522d49ff">xfer_buff1</a> : ep-&gt;<a class="code" href="structdwc__ep.html#b6d727e366ac589d304256c758d2d44a">xfer_buff0</a>;
+<a name="l00625"></a>00625                 ep-&gt;<a class="code" href="structdwc__ep.html#ed4594c9f6c2bcbcf6f1bbe9e9c64061">cur_pkt_dma_addr</a> =
+<a name="l00626"></a>00626                     (ep-&gt;<a class="code" href="structdwc__ep.html#53033f174854701986545f05502e1cad">proc_buf_num</a>) ? ep-&gt;<a class="code" href="structdwc__ep.html#02dc1be77d505b19f14651fe9805c97f">dma_addr1</a> : ep-&gt;<a class="code" href="structdwc__ep.html#553936d1d003413d00a24330274887f9">dma_addr0</a>;
+<a name="l00627"></a>00627                 <a class="code" href="dwc__otg__cil_8c.html#0f0894ae9890260e1da839aa10af35cc">dwc_otg_iso_ep_start_frm_transfer</a>(core_if, ep);
+<a name="l00628"></a>00628         }
+<a name="l00629"></a>00629 }
+<a name="l00630"></a>00630 
+<a name="l00641"></a><a class="code" href="dwc__otg__pcd_8c.html#2898810e04a9dd19798f59cfdb56c670">00641</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd_8c.html#2898810e04a9dd19798f59cfdb56c670">dwc_otg_iso_ep_stop_transfer</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, <a class="code" href="structdwc__ep.html">dwc_ep_t</a> * ep)
+<a name="l00642"></a>00642 {
+<a name="l00643"></a>00643         <a class="code" href="uniondepctl__data.html">depctl_data_t</a> depctl = {.d32 = 0 };
+<a name="l00644"></a>00644         <span class="keyword">volatile</span> uint32_t *addr;
+<a name="l00645"></a>00645 
+<a name="l00646"></a>00646         <span class="keywordflow">if</span> (ep-&gt;<a class="code" href="structdwc__ep.html#b882b6b7c857100ed20600e94ea37760">is_in</a> == 1) {
+<a name="l00647"></a>00647                 addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[ep-&gt;<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a>]-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#53a5adb977e2aec66d4902c6ba293216">diepctl</a>;
+<a name="l00648"></a>00648         } <span class="keywordflow">else</span> {
+<a name="l00649"></a>00649                 addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">out_ep_regs</a>[ep-&gt;<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a>]-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#2a522b71fc97658c07debf3521f7d3e5">doepctl</a>;
+<a name="l00650"></a>00650         }
+<a name="l00651"></a>00651 
+<a name="l00652"></a>00652         <span class="comment">/* disable the ep */</span>
+<a name="l00653"></a>00653         depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a> = dwc_read_reg32(addr);
+<a name="l00654"></a>00654 
+<a name="l00655"></a>00655         depctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#4d76ba4ebd506d3175ec5cdc0d811654">epdis</a> = 1;
+<a name="l00656"></a>00656         depctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#ccf6e60ac8cabde8da36edb19504ba2b">snak</a> = 1;
+<a name="l00657"></a>00657 
+<a name="l00658"></a>00658         dwc_write_reg32(addr, depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a>);
+<a name="l00659"></a>00659 
+<a name="l00660"></a>00660         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a> &amp;&amp;
+<a name="l00661"></a>00661             ep-&gt;<a class="code" href="structdwc__ep.html#a4e11d12099ad64dd5048a3a210fc9f6">iso_desc_addr</a> &amp;&amp; ep-&gt;<a class="code" href="structdwc__ep.html#d571f49545171ea167193edac7984173">iso_dma_desc_addr</a>) {
+<a name="l00662"></a>00662                 <a class="code" href="dwc__otg__pcd_8c.html#1926b61a7438bd9a14bd6d6a26c6a63d">dwc_otg_ep_free_desc_chain</a>(ep-&gt;<a class="code" href="structdwc__ep.html#a4e11d12099ad64dd5048a3a210fc9f6">iso_desc_addr</a>,
+<a name="l00663"></a>00663                                            ep-&gt;<a class="code" href="structdwc__ep.html#d571f49545171ea167193edac7984173">iso_dma_desc_addr</a>,
+<a name="l00664"></a>00664                                            ep-&gt;<a class="code" href="structdwc__ep.html#5e5bfcc93d41670bc0d29ad5f0f35871">desc_cnt</a> * 2);
+<a name="l00665"></a>00665         }
+<a name="l00666"></a>00666 
+<a name="l00667"></a>00667         <span class="comment">/* reset varibales */</span>
+<a name="l00668"></a>00668         ep-&gt;<a class="code" href="structdwc__ep.html#553936d1d003413d00a24330274887f9">dma_addr0</a> = 0;
+<a name="l00669"></a>00669         ep-&gt;<a class="code" href="structdwc__ep.html#02dc1be77d505b19f14651fe9805c97f">dma_addr1</a> = 0;
+<a name="l00670"></a>00670         ep-&gt;<a class="code" href="structdwc__ep.html#b6d727e366ac589d304256c758d2d44a">xfer_buff0</a> = 0;
+<a name="l00671"></a>00671         ep-&gt;<a class="code" href="structdwc__ep.html#36ff87362a0da5bce95eaf85522d49ff">xfer_buff1</a> = 0;
+<a name="l00672"></a>00672         ep-&gt;<a class="code" href="structdwc__ep.html#4672369f4724db642856d72d5048213e">data_per_frame</a> = 0;
+<a name="l00673"></a>00673         ep-&gt;<a class="code" href="structdwc__ep.html#c505483882bd67a7b0076851f693f2cc">data_pattern_frame</a> = 0;
+<a name="l00674"></a>00674         ep-&gt;<a class="code" href="structdwc__ep.html#1b9094ddfba3cddf397fd308cdbf4c81">sync_frame</a> = 0;
+<a name="l00675"></a>00675         ep-&gt;<a class="code" href="structdwc__ep.html#4638b25387e59a5a4721a503b5279dfc">buf_proc_intrvl</a> = 0;
+<a name="l00676"></a>00676         ep-&gt;<a class="code" href="structdwc__ep.html#d9e9ffe348764ababc3165ed04f9ec6c">bInterval</a> = 0;
+<a name="l00677"></a>00677         ep-&gt;<a class="code" href="structdwc__ep.html#53033f174854701986545f05502e1cad">proc_buf_num</a> = 0;
+<a name="l00678"></a>00678         ep-&gt;<a class="code" href="structdwc__ep.html#fe51420474de8a9d74fc9c4adc811c4b">pkt_per_frm</a> = 0;
+<a name="l00679"></a>00679         ep-&gt;<a class="code" href="structdwc__ep.html#fe51420474de8a9d74fc9c4adc811c4b">pkt_per_frm</a> = 0;
+<a name="l00680"></a>00680         ep-&gt;<a class="code" href="structdwc__ep.html#5e5bfcc93d41670bc0d29ad5f0f35871">desc_cnt</a> = 0;
+<a name="l00681"></a>00681         ep-&gt;<a class="code" href="structdwc__ep.html#a4e11d12099ad64dd5048a3a210fc9f6">iso_desc_addr</a> = 0;
+<a name="l00682"></a>00682         ep-&gt;<a class="code" href="structdwc__ep.html#d571f49545171ea167193edac7984173">iso_dma_desc_addr</a> = 0;
+<a name="l00683"></a>00683 }
+<a name="l00684"></a>00684 
+<a name="l00685"></a><a class="code" href="dwc__otg__pcd__if_8h.html#e0a690ac031f8f06c2e7fb10b4633b05">00685</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__pcd_8c.html#e0a690ac031f8f06c2e7fb10b4633b05">dwc_otg_pcd_iso_ep_start</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd, <span class="keywordtype">void</span> *ep_handle,
+<a name="l00686"></a>00686                              uint8_t * buf0, uint8_t * buf1, dwc_dma_t dma0,
+<a name="l00687"></a>00687                              dwc_dma_t dma1, <span class="keywordtype">int</span> sync_frame, <span class="keywordtype">int</span> dp_frame,
+<a name="l00688"></a>00688                              <span class="keywordtype">int</span> data_per_frame, <span class="keywordtype">int</span> start_frame,
+<a name="l00689"></a>00689                              <span class="keywordtype">int</span> buf_proc_intrvl, <span class="keywordtype">void</span> *req_handle,
+<a name="l00690"></a>00690                              <span class="keywordtype">int</span> atomic_alloc)
+<a name="l00691"></a>00691 {
+<a name="l00692"></a>00692         <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *ep;
+<a name="l00693"></a>00693         uint64_t flags = 0;
+<a name="l00694"></a>00694         <a class="code" href="structdwc__ep.html">dwc_ep_t</a> *<a class="code" href="structdwc__ep.html">dwc_ep</a>;
+<a name="l00695"></a>00695         int32_t frm_data;
+<a name="l00696"></a>00696         <a class="code" href="uniondsts__data.html">dsts_data_t</a> dsts;
+<a name="l00697"></a>00697         <a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if;
+<a name="l00698"></a>00698 
+<a name="l00699"></a>00699         ep = <a class="code" href="dwc__otg__pcd_8c.html#4b46c226fa34cd7fc4ceec2c5e7f8ebe">get_ep_from_handle</a>(pcd, ep_handle);
+<a name="l00700"></a>00700 
+<a name="l00701"></a>00701         <span class="keywordflow">if</span> (!ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#86e27843c439dd0b1d12d9bf2dc6516f">desc</a> || ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a> == 0) {
+<a name="l00702"></a>00702                 DWC_WARN(<span class="stringliteral">"bad ep\n"</span>);
+<a name="l00703"></a>00703                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l00704"></a>00704         }
+<a name="l00705"></a>00705 
+<a name="l00706"></a>00706         DWC_SPINLOCK_IRQSAVE(pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5d450e4d06659ab2f3b18e5c816776e4">lock</a>, &amp;flags);
+<a name="l00707"></a>00707         core_if = <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd);
+<a name="l00708"></a>00708         dwc_ep = &amp;ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>;
+<a name="l00709"></a>00709 
+<a name="l00710"></a>00710         <span class="keywordflow">if</span> (ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#716d3c29adc54c6822935fc2ae9bef51">iso_req_handle</a>) {
+<a name="l00711"></a>00711                 DWC_WARN(<span class="stringliteral">"ISO request in progress\n"</span>);
+<a name="l00712"></a>00712         }
+<a name="l00713"></a>00713 
+<a name="l00714"></a>00714         dwc_ep-&gt;<a class="code" href="structdwc__ep.html#553936d1d003413d00a24330274887f9">dma_addr0</a> = dma0;
+<a name="l00715"></a>00715         dwc_ep-&gt;<a class="code" href="structdwc__ep.html#02dc1be77d505b19f14651fe9805c97f">dma_addr1</a> = dma1;
+<a name="l00716"></a>00716 
+<a name="l00717"></a>00717         dwc_ep-&gt;<a class="code" href="structdwc__ep.html#b6d727e366ac589d304256c758d2d44a">xfer_buff0</a> = buf0;
+<a name="l00718"></a>00718         dwc_ep-&gt;<a class="code" href="structdwc__ep.html#36ff87362a0da5bce95eaf85522d49ff">xfer_buff1</a> = buf1;
+<a name="l00719"></a>00719 
+<a name="l00720"></a>00720         dwc_ep-&gt;<a class="code" href="structdwc__ep.html#4672369f4724db642856d72d5048213e">data_per_frame</a> = data_per_frame;
+<a name="l00721"></a>00721 
+<a name="l00723"></a>00723         dwc_ep-&gt;<a class="code" href="structdwc__ep.html#c505483882bd67a7b0076851f693f2cc">data_pattern_frame</a> = dp_frame;
+<a name="l00724"></a>00724         dwc_ep-&gt;<a class="code" href="structdwc__ep.html#1b9094ddfba3cddf397fd308cdbf4c81">sync_frame</a> = sync_frame;
+<a name="l00725"></a>00725 
+<a name="l00726"></a>00726         dwc_ep-&gt;<a class="code" href="structdwc__ep.html#4638b25387e59a5a4721a503b5279dfc">buf_proc_intrvl</a> = buf_proc_intrvl;
+<a name="l00727"></a>00727 
+<a name="l00728"></a>00728         dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d9e9ffe348764ababc3165ed04f9ec6c">bInterval</a> = 1 &lt;&lt; (ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#86e27843c439dd0b1d12d9bf2dc6516f">desc</a>-&gt;bInterval - 1);
+<a name="l00729"></a>00729 
+<a name="l00730"></a>00730         dwc_ep-&gt;<a class="code" href="structdwc__ep.html#53033f174854701986545f05502e1cad">proc_buf_num</a> = 0;
+<a name="l00731"></a>00731 
+<a name="l00732"></a>00732         dwc_ep-&gt;<a class="code" href="structdwc__ep.html#fe51420474de8a9d74fc9c4adc811c4b">pkt_per_frm</a> = 0;
+<a name="l00733"></a>00733         frm_data = ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#4672369f4724db642856d72d5048213e">data_per_frame</a>;
+<a name="l00734"></a>00734         <span class="keywordflow">while</span> (frm_data &gt; 0) {
+<a name="l00735"></a>00735                 dwc_ep-&gt;<a class="code" href="structdwc__ep.html#fe51420474de8a9d74fc9c4adc811c4b">pkt_per_frm</a>++;
+<a name="l00736"></a>00736                 frm_data -= ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a>;
+<a name="l00737"></a>00737         }
+<a name="l00738"></a>00738 
+<a name="l00739"></a>00739         dsts.<a class="code" href="uniondsts__data.html#0f126daef735b142b06dbc4cdbe13814">d32</a> = dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#1ed00edd20ce5db7d07666804101ec05">dsts</a>);
+<a name="l00740"></a>00740 
+<a name="l00741"></a>00741         <span class="keywordflow">if</span> (start_frame == -1) {
+<a name="l00742"></a>00742                 dwc_ep-&gt;<a class="code" href="structdwc__ep.html#1e9f4d08454c973c17acb3e52a2c3689">next_frame</a> = dsts.<a class="code" href="uniondsts__data.html#4066fcedb7ac9a88e47aa1b2df0e89ee">b</a>.<a class="code" href="uniondsts__data.html#5a81ac4848c859cbf7d494dc345a0ce8">soffn</a> + 1;
+<a name="l00743"></a>00743                 <span class="keywordflow">if</span> (dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d9e9ffe348764ababc3165ed04f9ec6c">bInterval</a> != 1) {
+<a name="l00744"></a>00744                         dwc_ep-&gt;<a class="code" href="structdwc__ep.html#1e9f4d08454c973c17acb3e52a2c3689">next_frame</a> =
+<a name="l00745"></a>00745                             dwc_ep-&gt;<a class="code" href="structdwc__ep.html#1e9f4d08454c973c17acb3e52a2c3689">next_frame</a> + (dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d9e9ffe348764ababc3165ed04f9ec6c">bInterval</a> - 1 -
+<a name="l00746"></a>00746                                                   dwc_ep-&gt;<a class="code" href="structdwc__ep.html#1e9f4d08454c973c17acb3e52a2c3689">next_frame</a> %
+<a name="l00747"></a>00747                                                   dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d9e9ffe348764ababc3165ed04f9ec6c">bInterval</a>);
+<a name="l00748"></a>00748                 }
+<a name="l00749"></a>00749         } <span class="keywordflow">else</span> {
+<a name="l00750"></a>00750                 dwc_ep-&gt;<a class="code" href="structdwc__ep.html#1e9f4d08454c973c17acb3e52a2c3689">next_frame</a> = start_frame;
+<a name="l00751"></a>00751         }
+<a name="l00752"></a>00752 
+<a name="l00753"></a>00753         <span class="keywordflow">if</span> (!core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#34540b79e9a14bfa234a52ac132c5cd1">pti_enh_enable</a>) {
+<a name="l00754"></a>00754                 dwc_ep-&gt;<a class="code" href="structdwc__ep.html#46349fb0608d8c6849ced211b0628c15">pkt_cnt</a> =
+<a name="l00755"></a>00755                     dwc_ep-&gt;<a class="code" href="structdwc__ep.html#4638b25387e59a5a4721a503b5279dfc">buf_proc_intrvl</a> * dwc_ep-&gt;<a class="code" href="structdwc__ep.html#fe51420474de8a9d74fc9c4adc811c4b">pkt_per_frm</a> /
+<a name="l00756"></a>00756                     dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d9e9ffe348764ababc3165ed04f9ec6c">bInterval</a>;
+<a name="l00757"></a>00757         } <span class="keywordflow">else</span> {
+<a name="l00758"></a>00758                 dwc_ep-&gt;<a class="code" href="structdwc__ep.html#46349fb0608d8c6849ced211b0628c15">pkt_cnt</a> =
+<a name="l00759"></a>00759                     (dwc_ep-&gt;<a class="code" href="structdwc__ep.html#4672369f4724db642856d72d5048213e">data_per_frame</a> *
+<a name="l00760"></a>00760                      (dwc_ep-&gt;<a class="code" href="structdwc__ep.html#4638b25387e59a5a4721a503b5279dfc">buf_proc_intrvl</a> / dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d9e9ffe348764ababc3165ed04f9ec6c">bInterval</a>)
+<a name="l00761"></a>00761                      - 1 + dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a>) / dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a>;
+<a name="l00762"></a>00762         }
+<a name="l00763"></a>00763 
+<a name="l00764"></a>00764         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a>) {
+<a name="l00765"></a>00765                 dwc_ep-&gt;<a class="code" href="structdwc__ep.html#5e5bfcc93d41670bc0d29ad5f0f35871">desc_cnt</a> =
+<a name="l00766"></a>00766                     dwc_ep-&gt;<a class="code" href="structdwc__ep.html#4638b25387e59a5a4721a503b5279dfc">buf_proc_intrvl</a> * dwc_ep-&gt;<a class="code" href="structdwc__ep.html#fe51420474de8a9d74fc9c4adc811c4b">pkt_per_frm</a> /
+<a name="l00767"></a>00767                     dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d9e9ffe348764ababc3165ed04f9ec6c">bInterval</a>;
+<a name="l00768"></a>00768         }
+<a name="l00769"></a>00769 
+<a name="l00770"></a>00770         <span class="keywordflow">if</span> (atomic_alloc) {
+<a name="l00771"></a>00771                 dwc_ep-&gt;<a class="code" href="structdwc__ep.html#a8ed15a24123a2dad6861da7d61dfb48">pkt_info</a> =
+<a name="l00772"></a>00772                     dwc_alloc_atomic(<span class="keyword">sizeof</span>(<a class="code" href="structiso__pkt__info.html">iso_pkt_info_t</a>) * dwc_ep-&gt;<a class="code" href="structdwc__ep.html#46349fb0608d8c6849ced211b0628c15">pkt_cnt</a>);
+<a name="l00773"></a>00773         } <span class="keywordflow">else</span> {
+<a name="l00774"></a>00774                 dwc_ep-&gt;<a class="code" href="structdwc__ep.html#a8ed15a24123a2dad6861da7d61dfb48">pkt_info</a> =
+<a name="l00775"></a>00775                     dwc_alloc(<span class="keyword">sizeof</span>(<a class="code" href="structiso__pkt__info.html">iso_pkt_info_t</a>) * dwc_ep-&gt;<a class="code" href="structdwc__ep.html#46349fb0608d8c6849ced211b0628c15">pkt_cnt</a>);
+<a name="l00776"></a>00776         }
+<a name="l00777"></a>00777         <span class="keywordflow">if</span> (!dwc_ep-&gt;<a class="code" href="structdwc__ep.html#a8ed15a24123a2dad6861da7d61dfb48">pkt_info</a>) {
+<a name="l00778"></a>00778                 DWC_SPINUNLOCK_IRQRESTORE(pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5d450e4d06659ab2f3b18e5c816776e4">lock</a>, flags);
+<a name="l00779"></a>00779                 <span class="keywordflow">return</span> -DWC_E_NO_MEMORY;
+<a name="l00780"></a>00780         }
+<a name="l00781"></a>00781         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#34540b79e9a14bfa234a52ac132c5cd1">pti_enh_enable</a>) {
+<a name="l00782"></a>00782                 dwc_memset(dwc_ep-&gt;<a class="code" href="structdwc__ep.html#a8ed15a24123a2dad6861da7d61dfb48">pkt_info</a>, 0,
+<a name="l00783"></a>00783                            <span class="keyword">sizeof</span>(<a class="code" href="structiso__pkt__info.html">iso_pkt_info_t</a>) * dwc_ep-&gt;<a class="code" href="structdwc__ep.html#46349fb0608d8c6849ced211b0628c15">pkt_cnt</a>);
+<a name="l00784"></a>00784         }
+<a name="l00785"></a>00785 
+<a name="l00786"></a>00786         dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d4e63c7d944c2b48260b4a75c2b58925">cur_pkt</a> = 0;
+<a name="l00787"></a>00787         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#716d3c29adc54c6822935fc2ae9bef51">iso_req_handle</a> = req_handle;
+<a name="l00788"></a>00788 
+<a name="l00789"></a>00789         DWC_SPINUNLOCK_IRQRESTORE(pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5d450e4d06659ab2f3b18e5c816776e4">lock</a>, flags);
+<a name="l00790"></a>00790         <a class="code" href="dwc__otg__pcd_8c.html#3f39ccc23c6f9bd4fd4ab7a5cecc67a3">dwc_otg_iso_ep_start_transfer</a>(core_if, dwc_ep);
+<a name="l00791"></a>00791         <span class="keywordflow">return</span> 0;
+<a name="l00792"></a>00792 }
+<a name="l00793"></a>00793 
+<a name="l00794"></a><a class="code" href="dwc__otg__pcd__if_8h.html#5098f89da28c6b450e7e10b31441b945">00794</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__pcd_8c.html#5098f89da28c6b450e7e10b31441b945">dwc_otg_pcd_iso_ep_stop</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd, <span class="keywordtype">void</span> *ep_handle,
+<a name="l00795"></a>00795                             <span class="keywordtype">void</span> *req_handle)
+<a name="l00796"></a>00796 {
+<a name="l00797"></a>00797         uint64_t flags = 0;
+<a name="l00798"></a>00798         <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *ep;
+<a name="l00799"></a>00799         <a class="code" href="structdwc__ep.html">dwc_ep_t</a> *<a class="code" href="structdwc__ep.html">dwc_ep</a>;
+<a name="l00800"></a>00800 
+<a name="l00801"></a>00801         ep = <a class="code" href="dwc__otg__pcd_8c.html#4b46c226fa34cd7fc4ceec2c5e7f8ebe">get_ep_from_handle</a>(pcd, ep_handle);
+<a name="l00802"></a>00802         <span class="keywordflow">if</span> (!ep || !ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#86e27843c439dd0b1d12d9bf2dc6516f">desc</a> || ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a> == 0) {
+<a name="l00803"></a>00803                 DWC_WARN(<span class="stringliteral">"bad ep\n"</span>);
+<a name="l00804"></a>00804                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l00805"></a>00805         }
+<a name="l00806"></a>00806         dwc_ep = &amp;ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>;
+<a name="l00807"></a>00807 
+<a name="l00808"></a>00808         <a class="code" href="dwc__otg__pcd_8c.html#2898810e04a9dd19798f59cfdb56c670">dwc_otg_iso_ep_stop_transfer</a>(<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd), dwc_ep);
+<a name="l00809"></a>00809 
+<a name="l00810"></a>00810         dwc_free(dwc_ep-&gt;<a class="code" href="structdwc__ep.html#a8ed15a24123a2dad6861da7d61dfb48">pkt_info</a>);
+<a name="l00811"></a>00811         DWC_SPINLOCK_IRQSAVE(pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5d450e4d06659ab2f3b18e5c816776e4">lock</a>, &amp;flags);
+<a name="l00812"></a>00812         <span class="keywordflow">if</span> (ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#716d3c29adc54c6822935fc2ae9bef51">iso_req_handle</a> != req_handle) {
+<a name="l00813"></a>00813                 DWC_SPINUNLOCK_IRQRESTORE(pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5d450e4d06659ab2f3b18e5c816776e4">lock</a>, flags);
+<a name="l00814"></a>00814                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l00815"></a>00815         }
+<a name="l00816"></a>00816 
+<a name="l00817"></a>00817         DWC_SPINUNLOCK_IRQRESTORE(pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5d450e4d06659ab2f3b18e5c816776e4">lock</a>, flags);
+<a name="l00818"></a>00818 
+<a name="l00819"></a>00819         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#716d3c29adc54c6822935fc2ae9bef51">iso_req_handle</a> = 0;
+<a name="l00820"></a>00820         <span class="keywordflow">return</span> 0;
+<a name="l00821"></a>00821 }
+<a name="l00822"></a>00822 
+<a name="l00830"></a><a class="code" href="dwc__otg__pcd_8h.html#b4e2c352426923d4bd519cf18b68206d">00830</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd_8c.html#b4e2c352426923d4bd519cf18b68206d">dwc_otg_iso_buffer_done</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd, <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> * ep,
+<a name="l00831"></a>00831                              <span class="keywordtype">void</span> *req_handle)
+<a name="l00832"></a>00832 {
+<a name="l00833"></a>00833         <span class="keywordtype">int</span> i;
+<a name="l00834"></a>00834         <a class="code" href="structdwc__ep.html">dwc_ep_t</a> *<a class="code" href="structdwc__ep.html">dwc_ep</a>;
+<a name="l00835"></a>00835 
+<a name="l00836"></a>00836         dwc_ep = &amp;ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>;
+<a name="l00837"></a>00837 
+<a name="l00838"></a>00838         DWC_SPINUNLOCK(ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#234391334e48cbd72710d08655c9ed16">pcd</a>-&gt;<a class="code" href="structdwc__otg__pcd.html#5d450e4d06659ab2f3b18e5c816776e4">lock</a>);
+<a name="l00839"></a>00839         pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#b7001dde5db2706707a860da0030d9e6">fops</a>-&gt;<a class="code" href="structdwc__otg__pcd__function__ops.html#9714dfa4909221c0b937a9bcadf97339">isoc_complete</a>(pcd, ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#8c8fad971c6c3b1c54d334c7f9b2d03e">priv</a>, ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#716d3c29adc54c6822935fc2ae9bef51">iso_req_handle</a>,
+<a name="l00840"></a>00840                                  dwc_ep-&gt;<a class="code" href="structdwc__ep.html#53033f174854701986545f05502e1cad">proc_buf_num</a> ^ 0x1);
+<a name="l00841"></a>00841         DWC_SPINLOCK(ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#234391334e48cbd72710d08655c9ed16">pcd</a>-&gt;<a class="code" href="structdwc__otg__pcd.html#5d450e4d06659ab2f3b18e5c816776e4">lock</a>);
+<a name="l00842"></a>00842 
+<a name="l00843"></a>00843         <span class="keywordflow">for</span> (i = 0; i &lt; dwc_ep-&gt;<a class="code" href="structdwc__ep.html#46349fb0608d8c6849ced211b0628c15">pkt_cnt</a>; ++i) {
+<a name="l00844"></a>00844                 dwc_ep-&gt;<a class="code" href="structdwc__ep.html#a8ed15a24123a2dad6861da7d61dfb48">pkt_info</a>[i].<a class="code" href="structiso__pkt__info.html#1317c3b425c0ef55dbde153b04c28dd4">status</a> = 0;
+<a name="l00845"></a>00845                 dwc_ep-&gt;<a class="code" href="structdwc__ep.html#a8ed15a24123a2dad6861da7d61dfb48">pkt_info</a>[i].<a class="code" href="structiso__pkt__info.html#0c72a0585ccc93555da4db7e168f75f8">offset</a> = 0;
+<a name="l00846"></a>00846                 dwc_ep-&gt;<a class="code" href="structdwc__ep.html#a8ed15a24123a2dad6861da7d61dfb48">pkt_info</a>[i].<a class="code" href="structiso__pkt__info.html#ced82142e81778345016841e15020eb8">length</a> = 0;
+<a name="l00847"></a>00847         }
+<a name="l00848"></a>00848 }
+<a name="l00849"></a>00849 
+<a name="l00850"></a><a class="code" href="dwc__otg__pcd__if_8h.html#2f04b14612c2b58909b3a54ed71ab12e">00850</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__pcd_8c.html#2f04b14612c2b58909b3a54ed71ab12e">dwc_otg_pcd_get_iso_packet_count</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd, <span class="keywordtype">void</span> *ep_handle,
+<a name="l00851"></a>00851                                      <span class="keywordtype">void</span> *iso_req_handle)
+<a name="l00852"></a>00852 {
+<a name="l00853"></a>00853         <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *ep;
+<a name="l00854"></a>00854         <a class="code" href="structdwc__ep.html">dwc_ep_t</a> *<a class="code" href="structdwc__ep.html">dwc_ep</a>;
+<a name="l00855"></a>00855 
+<a name="l00856"></a>00856         ep = <a class="code" href="dwc__otg__pcd_8c.html#4b46c226fa34cd7fc4ceec2c5e7f8ebe">get_ep_from_handle</a>(pcd, ep_handle);
+<a name="l00857"></a>00857         dwc_ep = &amp;ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>;
+<a name="l00858"></a>00858 
+<a name="l00859"></a>00859         <span class="keywordflow">return</span> dwc_ep-&gt;<a class="code" href="structdwc__ep.html#46349fb0608d8c6849ced211b0628c15">pkt_cnt</a>;
+<a name="l00860"></a>00860 }
+<a name="l00861"></a>00861 
+<a name="l00862"></a><a class="code" href="dwc__otg__pcd__if_8h.html#21149047aa9abddac5654e4496175ac5">00862</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd_8c.html#21149047aa9abddac5654e4496175ac5">dwc_otg_pcd_get_iso_packet_params</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd, <span class="keywordtype">void</span> *ep_handle,
+<a name="l00863"></a>00863                                        <span class="keywordtype">void</span> *iso_req_handle, <span class="keywordtype">int</span> packet,
+<a name="l00864"></a>00864                                        <span class="keywordtype">int</span> *status, <span class="keywordtype">int</span> *actual, <span class="keywordtype">int</span> *offset)
+<a name="l00865"></a>00865 {
+<a name="l00866"></a>00866         <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *ep;
+<a name="l00867"></a>00867         <a class="code" href="structdwc__ep.html">dwc_ep_t</a> *<a class="code" href="structdwc__ep.html">dwc_ep</a>;
+<a name="l00868"></a>00868 
+<a name="l00869"></a>00869         ep = <a class="code" href="dwc__otg__pcd_8c.html#4b46c226fa34cd7fc4ceec2c5e7f8ebe">get_ep_from_handle</a>(pcd, ep_handle);
+<a name="l00870"></a>00870         dwc_ep = &amp;ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>;
+<a name="l00871"></a>00871 
+<a name="l00872"></a>00872         *status = dwc_ep-&gt;<a class="code" href="structdwc__ep.html#a8ed15a24123a2dad6861da7d61dfb48">pkt_info</a>[packet].<a class="code" href="structiso__pkt__info.html#1317c3b425c0ef55dbde153b04c28dd4">status</a>;
+<a name="l00873"></a>00873         *actual = dwc_ep-&gt;<a class="code" href="structdwc__ep.html#a8ed15a24123a2dad6861da7d61dfb48">pkt_info</a>[packet].<a class="code" href="structiso__pkt__info.html#ced82142e81778345016841e15020eb8">length</a>;
+<a name="l00874"></a>00874         *offset = dwc_ep-&gt;<a class="code" href="structdwc__ep.html#a8ed15a24123a2dad6861da7d61dfb48">pkt_info</a>[packet].<a class="code" href="structiso__pkt__info.html#0c72a0585ccc93555da4db7e168f75f8">offset</a>;
+<a name="l00875"></a>00875 }
+<a name="l00876"></a>00876 
+<a name="l00877"></a>00877 <span class="preprocessor">#endif                          </span><span class="comment">/* DWC_EN_ISOC */</span>
+<a name="l00878"></a>00878 
+<a name="l00879"></a><a class="code" href="dwc__otg__pcd_8c.html#dbfe9af71d4c36cbf7eb544a1df9364e">00879</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd_8c.html#dbfe9af71d4c36cbf7eb544a1df9364e">dwc_otg_pcd_init_ep</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd, <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> * pcd_ep,
+<a name="l00880"></a>00880                                 uint32_t is_in, uint32_t ep_num)
+<a name="l00881"></a>00881 {
+<a name="l00882"></a>00882         <span class="comment">/* Init EP structure */</span>
+<a name="l00883"></a>00883         pcd_ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#86e27843c439dd0b1d12d9bf2dc6516f">desc</a> = 0;
+<a name="l00884"></a>00884         pcd_ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#234391334e48cbd72710d08655c9ed16">pcd</a> = pcd;
+<a name="l00885"></a>00885         pcd_ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#cce0e089118d8bf7c6278c21ded70d5a">stopped</a> = 1;
+<a name="l00886"></a>00886         pcd_ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#bbec681b68f2f745d1cfecfedd4e64be">queue_sof</a> = 0;
+<a name="l00887"></a>00887 
+<a name="l00888"></a>00888         <span class="comment">/* Init DWC ep structure */</span>
+<a name="l00889"></a>00889         pcd_ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#b882b6b7c857100ed20600e94ea37760">is_in</a> = is_in;
+<a name="l00890"></a>00890         pcd_ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a> = ep_num;
+<a name="l00891"></a>00891         pcd_ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#63b7a1a3ee32df393ff10d8bfc5c8648">active</a> = 0;
+<a name="l00892"></a>00892         pcd_ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#ffa14f48094778143353b845b5d238cd">tx_fifo_num</a> = 0;
+<a name="l00893"></a>00893         <span class="comment">/* Control until ep is actvated */</span>
+<a name="l00894"></a>00894         pcd_ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#17b10677bd9b0a1d612dd4ce2fb0eb0f">type</a> = <a class="code" href="dwc__otg__cil_8h.html#64e5cd756330f5adab79b25cc8067bdc">DWC_OTG_EP_TYPE_CONTROL</a>;
+<a name="l00895"></a>00895         pcd_ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a> = <a class="code" href="dwc__otg__pcd__if_8h.html#cf2c48a3393f5ae43e8d88d01c2d204a">MAX_PACKET_SIZE</a>;
+<a name="l00896"></a>00896         pcd_ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#b40ce70422b6d105a855a8df4b33d45d">dma_addr</a> = 0;
+<a name="l00897"></a>00897         pcd_ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#d0cda8ded2e5142d9a1c9c17efc5812f">start_xfer_buff</a> = 0;
+<a name="l00898"></a>00898         pcd_ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#97fa9bf5c31ba734d54f70e6fe6ae8eb">xfer_buff</a> = 0;
+<a name="l00899"></a>00899         pcd_ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">xfer_len</a> = 0;
+<a name="l00900"></a>00900         pcd_ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#23d4871510b5bcb54fbf0674d8f122bd">xfer_count</a> = 0;
+<a name="l00901"></a>00901         pcd_ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#8c6340435beba0b8c025a4677602acab">sent_zlp</a> = 0;
+<a name="l00902"></a>00902         pcd_ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#5a218f200cff0491b735f43fed5176bf">total_len</a> = 0;
+<a name="l00903"></a>00903         pcd_ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#57e934b26e76939912eaa76321075a0d">desc_addr</a> = 0;
+<a name="l00904"></a>00904         pcd_ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#1a43e464429530e874472092e0e1af09">dma_desc_addr</a> = 0;
+<a name="l00905"></a>00905         DWC_CIRCLEQ_INIT(&amp;pcd_ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#71f4fa571dfdc96f62fa4869e6add300">queue</a>);
+<a name="l00906"></a>00906 }
+<a name="l00907"></a>00907 
+<a name="l00911"></a><a class="code" href="dwc__otg__pcd_8c.html#b6506996bd4b93ef4f80092a64384fae">00911</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd_8c.html#b6506996bd4b93ef4f80092a64384fae">dwc_otg_pcd_reinit</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd)
+<a name="l00912"></a>00912 {
+<a name="l00913"></a>00913         <span class="keywordtype">int</span> i;
+<a name="l00914"></a>00914         uint32_t hwcfg1;
+<a name="l00915"></a>00915         <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *ep;
+<a name="l00916"></a>00916         <span class="keywordtype">int</span> in_ep_cntr, out_ep_cntr;
+<a name="l00917"></a>00917         uint32_t num_in_eps = (<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd))-&gt;dev_if-&gt;num_in_eps;
+<a name="l00918"></a>00918         uint32_t num_out_eps = (<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd))-&gt;dev_if-&gt;num_out_eps;
+<a name="l00919"></a>00919 
+<a name="l00923"></a>00923         ep = &amp;pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a>;
+<a name="l00924"></a>00924         <a class="code" href="dwc__otg__pcd_8c.html#dbfe9af71d4c36cbf7eb544a1df9364e">dwc_otg_pcd_init_ep</a>(pcd, ep, 0, 0);
+<a name="l00925"></a>00925 
+<a name="l00926"></a>00926         in_ep_cntr = 0;
+<a name="l00927"></a>00927         hwcfg1 = (<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd))-&gt;hwcfg1.d32 &gt;&gt; 3;
+<a name="l00928"></a>00928         for (i = 1; in_ep_cntr &lt; num_in_eps; i++) {
+<a name="l00929"></a>00929                 <span class="keywordflow">if</span> ((hwcfg1 &amp; 0x1) == 0) {
+<a name="l00930"></a>00930                         <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *ep = &amp;pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#dbfc8c424ea3add38db96fa87219caa8">in_ep</a>[in_ep_cntr];
+<a name="l00931"></a>00931                         in_ep_cntr++;
+<a name="l00937"></a>00937                         <a class="code" href="dwc__otg__pcd_8c.html#dbfe9af71d4c36cbf7eb544a1df9364e">dwc_otg_pcd_init_ep</a>(pcd, ep, 1 <span class="comment">/* IN */</span> , i);
+<a name="l00938"></a>00938 
+<a name="l00939"></a>00939                         DWC_CIRCLEQ_INIT(&amp;ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#71f4fa571dfdc96f62fa4869e6add300">queue</a>);
+<a name="l00940"></a>00940                 }
+<a name="l00941"></a>00941                 hwcfg1 &gt;&gt;= 2;
+<a name="l00942"></a>00942         }
+<a name="l00943"></a>00943 
+<a name="l00944"></a>00944         out_ep_cntr = 0;
+<a name="l00945"></a>00945         hwcfg1 = (<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd))-&gt;hwcfg1.d32 &gt;&gt; 2;
+<a name="l00946"></a>00946         for (i = 1; out_ep_cntr &lt; num_out_eps; i++) {
+<a name="l00947"></a>00947                 <span class="keywordflow">if</span> ((hwcfg1 &amp; 0x1) == 0) {
+<a name="l00948"></a>00948                         <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *ep = &amp;pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#b9e49a1d1fbca5ba9523e27c7108df30">out_ep</a>[out_ep_cntr];
+<a name="l00949"></a>00949                         out_ep_cntr++;
+<a name="l00955"></a>00955                         <a class="code" href="dwc__otg__pcd_8c.html#dbfe9af71d4c36cbf7eb544a1df9364e">dwc_otg_pcd_init_ep</a>(pcd, ep, 0 <span class="comment">/* OUT */</span> , i);
+<a name="l00956"></a>00956                         DWC_CIRCLEQ_INIT(&amp;ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#71f4fa571dfdc96f62fa4869e6add300">queue</a>);
+<a name="l00957"></a>00957                 }
+<a name="l00958"></a>00958                 hwcfg1 &gt;&gt;= 2;
+<a name="l00959"></a>00959         }
+<a name="l00960"></a>00960 
+<a name="l00961"></a>00961         pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#8f6963b3fb9ab83048c4c0697c90382a">ep0state</a> = EP0_DISCONNECT;
+<a name="l00962"></a>00962         pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a>.<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a> = <a class="code" href="dwc__otg__pcd__if_8h.html#8fbbba66f80923843e99def6064a570f">MAX_EP0_SIZE</a>;
+<a name="l00963"></a>00963         pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a>.<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#17b10677bd9b0a1d612dd4ce2fb0eb0f">type</a> = <a class="code" href="dwc__otg__cil_8h.html#64e5cd756330f5adab79b25cc8067bdc">DWC_OTG_EP_TYPE_CONTROL</a>;
+<a name="l00964"></a>00964 }
+<a name="l00965"></a>00965 
+<a name="l00970"></a><a class="code" href="dwc__otg__pcd_8c.html#e1e5a9264c2ad212d697d6be1110874f">00970</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd_8c.html#e1e5a9264c2ad212d697d6be1110874f">srp_timeout</a>(<span class="keywordtype">void</span> *ptr)
+<a name="l00971"></a>00971 {
+<a name="l00972"></a>00972         <a class="code" href="uniongotgctl__data.html">gotgctl_data_t</a> gotgctl;
+<a name="l00973"></a>00973         <a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if = (<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *) ptr;
+<a name="l00974"></a>00974         <span class="keyword">volatile</span> uint32_t *addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#54034d00bb6b47ada4e0c0baa87cbd8a">gotgctl</a>;
+<a name="l00975"></a>00975 
+<a name="l00976"></a>00976         gotgctl.<a class="code" href="uniongotgctl__data.html#ebb591ab40ff41f0e06f03a795647d33">d32</a> = dwc_read_reg32(addr);
+<a name="l00977"></a>00977 
+<a name="l00978"></a>00978         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#749cdeef193b7590b036a9b1d1442b73">srp_timer_started</a> = 0;
+<a name="l00979"></a>00979 
+<a name="l00980"></a>00980         <span class="keywordflow">if</span> ((core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#8b5d4e0c98c46d0d4e80b6faf66daf72">phy_type</a> == <a class="code" href="dwc__otg__core__if_8h.html#f7395410ea596c4c660f61ff41cb38b8">DWC_PHY_TYPE_PARAM_FS</a>) &amp;&amp;
+<a name="l00981"></a>00981             (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#6b0a0ab15284a541ae079beecaf3e617">i2c_enable</a>)) {
+<a name="l00982"></a>00982                 DWC_PRINTF(<span class="stringliteral">"SRP Timeout\n"</span>);
+<a name="l00983"></a>00983 
+<a name="l00984"></a>00984                 <span class="keywordflow">if</span> ((core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#c2bb1913ed3fcc082a06d70242e9768a">srp_success</a>) &amp;&amp; (gotgctl.<a class="code" href="uniongotgctl__data.html#212c81366266e906a188f4dbfadb6dd3">b</a>.<a class="code" href="uniongotgctl__data.html#69931c3759421d5eb6f91d4c9da4dddd">bsesvld</a>)) {
+<a name="l00985"></a>00985                         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#83bca1e02fafc4bbfa9c1f2eeb19b245">pcd_cb</a> &amp;&amp; core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#83bca1e02fafc4bbfa9c1f2eeb19b245">pcd_cb</a>-&gt;<a class="code" href="structdwc__otg__cil__callbacks.html#ad1895ddf4ad83622a514a725b4129d6">resume_wakeup</a>) {
+<a name="l00986"></a>00986                                 core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#83bca1e02fafc4bbfa9c1f2eeb19b245">pcd_cb</a>-&gt;<a class="code" href="structdwc__otg__cil__callbacks.html#ad1895ddf4ad83622a514a725b4129d6">resume_wakeup</a>(core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#83bca1e02fafc4bbfa9c1f2eeb19b245">pcd_cb</a>-&gt;
+<a name="l00987"></a>00987                                                                p);
+<a name="l00988"></a>00988                         }
+<a name="l00989"></a>00989 
+<a name="l00990"></a>00990                         <span class="comment">/* Clear Session Request */</span>
+<a name="l00991"></a>00991                         gotgctl.<a class="code" href="uniongotgctl__data.html#ebb591ab40ff41f0e06f03a795647d33">d32</a> = 0;
+<a name="l00992"></a>00992                         gotgctl.<a class="code" href="uniongotgctl__data.html#212c81366266e906a188f4dbfadb6dd3">b</a>.<a class="code" href="uniongotgctl__data.html#c6b0b35d4366f74cf6fe268eda781f06">sesreq</a> = 1;
+<a name="l00993"></a>00993                         dwc_modify_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#54034d00bb6b47ada4e0c0baa87cbd8a">gotgctl</a>,
+<a name="l00994"></a>00994                                          gotgctl.<a class="code" href="uniongotgctl__data.html#ebb591ab40ff41f0e06f03a795647d33">d32</a>, 0);
+<a name="l00995"></a>00995 
+<a name="l00996"></a>00996                         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#c2bb1913ed3fcc082a06d70242e9768a">srp_success</a> = 0;
+<a name="l00997"></a>00997                 } <span class="keywordflow">else</span> {
+<a name="l00998"></a>00998                         __DWC_ERROR(<span class="stringliteral">"Device not connected/responding\n"</span>);
+<a name="l00999"></a>00999                         gotgctl.<a class="code" href="uniongotgctl__data.html#212c81366266e906a188f4dbfadb6dd3">b</a>.<a class="code" href="uniongotgctl__data.html#c6b0b35d4366f74cf6fe268eda781f06">sesreq</a> = 0;
+<a name="l01000"></a>01000                         dwc_write_reg32(addr, gotgctl.<a class="code" href="uniongotgctl__data.html#ebb591ab40ff41f0e06f03a795647d33">d32</a>);
+<a name="l01001"></a>01001                 }
+<a name="l01002"></a>01002         } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (gotgctl.<a class="code" href="uniongotgctl__data.html#212c81366266e906a188f4dbfadb6dd3">b</a>.<a class="code" href="uniongotgctl__data.html#c6b0b35d4366f74cf6fe268eda781f06">sesreq</a>) {
+<a name="l01003"></a>01003                 DWC_PRINTF(<span class="stringliteral">"SRP Timeout\n"</span>);
+<a name="l01004"></a>01004 
+<a name="l01005"></a>01005                 __DWC_ERROR(<span class="stringliteral">"Device not connected/responding\n"</span>);
+<a name="l01006"></a>01006                 gotgctl.<a class="code" href="uniongotgctl__data.html#212c81366266e906a188f4dbfadb6dd3">b</a>.<a class="code" href="uniongotgctl__data.html#c6b0b35d4366f74cf6fe268eda781f06">sesreq</a> = 0;
+<a name="l01007"></a>01007                 dwc_write_reg32(addr, gotgctl.<a class="code" href="uniongotgctl__data.html#ebb591ab40ff41f0e06f03a795647d33">d32</a>);
+<a name="l01008"></a>01008         } <span class="keywordflow">else</span> {
+<a name="l01009"></a>01009                 DWC_PRINTF(<span class="stringliteral">" SRP GOTGCTL=%0x\n"</span>, gotgctl.<a class="code" href="uniongotgctl__data.html#ebb591ab40ff41f0e06f03a795647d33">d32</a>);
+<a name="l01010"></a>01010         }
+<a name="l01011"></a>01011 }
+<a name="l01012"></a>01012 
+<a name="l01017"></a>01017 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd_8c.html#de7160b7e7b8fd622ba95392513e197c">start_next_request</a>(<a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> * ep);
+<a name="l01018"></a>01018 
+<a name="l01019"></a><a class="code" href="dwc__otg__pcd_8c.html#4d9d8f7fb8f74eb64176fba91b38cb35">01019</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd_8c.html#4d9d8f7fb8f74eb64176fba91b38cb35">start_xfer_tasklet_func</a>(<span class="keywordtype">void</span> *data)
+<a name="l01020"></a>01020 {
+<a name="l01021"></a>01021         <a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd = (<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *) data;
+<a name="l01022"></a>01022         <a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if = <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd);
+<a name="l01023"></a>01023 
+<a name="l01024"></a>01024         <span class="keywordtype">int</span> i;
+<a name="l01025"></a>01025         <a class="code" href="uniondepctl__data.html">depctl_data_t</a> diepctl;
+<a name="l01026"></a>01026 
+<a name="l01027"></a>01027         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"Start xfer tasklet\n"</span>);
+<a name="l01028"></a>01028 
+<a name="l01029"></a>01029         diepctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a> = dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[0]-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#53a5adb977e2aec66d4902c6ba293216">diepctl</a>);
+<a name="l01030"></a>01030 
+<a name="l01031"></a>01031         <span class="keywordflow">if</span> (pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a>.<a class="code" href="structdwc__otg__pcd__ep.html#bbec681b68f2f745d1cfecfedd4e64be">queue_sof</a>) {
+<a name="l01032"></a>01032                 pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a>.<a class="code" href="structdwc__otg__pcd__ep.html#bbec681b68f2f745d1cfecfedd4e64be">queue_sof</a> = 0;
+<a name="l01033"></a>01033                 <a class="code" href="dwc__otg__pcd_8c.html#de7160b7e7b8fd622ba95392513e197c">start_next_request</a>(&amp;pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a>);
+<a name="l01034"></a>01034                 <span class="comment">// break;</span>
+<a name="l01035"></a>01035         }
+<a name="l01036"></a>01036 
+<a name="l01037"></a>01037         <span class="keywordflow">for</span> (i = 0; i &lt; core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#4fae9bc1293bf2e58966c38fa5b98822">num_in_eps</a>; i++) {
+<a name="l01038"></a>01038                 <a class="code" href="uniondepctl__data.html">depctl_data_t</a> diepctl;
+<a name="l01039"></a>01039                 diepctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a> =
+<a name="l01040"></a>01040                     dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[i]-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#53a5adb977e2aec66d4902c6ba293216">diepctl</a>);
+<a name="l01041"></a>01041 
+<a name="l01042"></a>01042                 <span class="keywordflow">if</span> (pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#dbfc8c424ea3add38db96fa87219caa8">in_ep</a>[i].<a class="code" href="structdwc__otg__pcd__ep.html#bbec681b68f2f745d1cfecfedd4e64be">queue_sof</a>) {
+<a name="l01043"></a>01043                         pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#dbfc8c424ea3add38db96fa87219caa8">in_ep</a>[i].<a class="code" href="structdwc__otg__pcd__ep.html#bbec681b68f2f745d1cfecfedd4e64be">queue_sof</a> = 0;
+<a name="l01044"></a>01044                         <a class="code" href="dwc__otg__pcd_8c.html#de7160b7e7b8fd622ba95392513e197c">start_next_request</a>(&amp;pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#dbfc8c424ea3add38db96fa87219caa8">in_ep</a>[i]);
+<a name="l01045"></a>01045                         <span class="comment">// break;</span>
+<a name="l01046"></a>01046                 }
+<a name="l01047"></a>01047         }
+<a name="l01048"></a>01048 
+<a name="l01049"></a>01049         <span class="keywordflow">return</span>;
+<a name="l01050"></a>01050 }
+<a name="l01051"></a>01051 
+<a name="l01056"></a><a class="code" href="dwc__otg__pcd__if_8h.html#fc3d8c56afa93b474180cc1eb8624ab8">01056</a> <a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *<a class="code" href="dwc__otg__pcd_8c.html#fc3d8c56afa93b474180cc1eb8624ab8">dwc_otg_pcd_init</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l01057"></a>01057 {
+<a name="l01058"></a>01058         <a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd = 0;
+<a name="l01059"></a>01059         <a class="code" href="structdwc__otg__dev__if.html">dwc_otg_dev_if_t</a> *dev_if;
+<a name="l01060"></a>01060 
+<a name="l01061"></a>01061         <span class="comment">/*</span>
+<a name="l01062"></a>01062 <span class="comment">         * Allocate PCD structure</span>
+<a name="l01063"></a>01063 <span class="comment">         */</span>
+<a name="l01064"></a>01064         pcd = dwc_alloc(<span class="keyword">sizeof</span>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a>));
+<a name="l01065"></a>01065 
+<a name="l01066"></a>01066         <span class="keywordflow">if</span> (pcd == 0) {
+<a name="l01067"></a>01067                 <span class="keywordflow">return</span> NULL;
+<a name="l01068"></a>01068         }
+<a name="l01069"></a>01069 
+<a name="l01070"></a>01070         pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5d450e4d06659ab2f3b18e5c816776e4">lock</a> = DWC_SPINLOCK_ALLOC();
+<a name="l01071"></a>01071         pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">core_if</a> = core_if;
+<a name="l01072"></a>01072         <span class="keywordflow">if</span> (!pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5d450e4d06659ab2f3b18e5c816776e4">lock</a>) {
+<a name="l01073"></a>01073                 DWC_ERROR(<span class="stringliteral">"Could not allocate lock for pcd"</span>);
+<a name="l01074"></a>01074                 dwc_free(pcd);
+<a name="l01075"></a>01075                 <span class="keywordflow">return</span> NULL;
+<a name="l01076"></a>01076         }
+<a name="l01077"></a>01077         dev_if = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>;
+<a name="l01078"></a>01078 
+<a name="l01079"></a>01079         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#9c1394f3c46adde2fa7be79bf0237f9b">hwcfg4</a>.<a class="code" href="unionhwcfg4__data.html#9fb9175668e2381c568c5adbf6e5225d">b</a>.<a class="code" href="unionhwcfg4__data.html#175e8897d6e3c8ef4026413943de503b">ded_fifo_en</a>) {
+<a name="l01080"></a>01080                 DWC_PRINTF(<span class="stringliteral">"Dedicated Tx FIFOs mode\n"</span>);
+<a name="l01081"></a>01081         } <span class="keywordflow">else</span> {
+<a name="l01082"></a>01082                 DWC_PRINTF(<span class="stringliteral">"Shared Tx FIFO mode\n"</span>);
+<a name="l01083"></a>01083         }
+<a name="l01084"></a>01084 
+<a name="l01085"></a>01085         <span class="comment">/*</span>
+<a name="l01086"></a>01086 <span class="comment">         * Initialized the Core for Device mode.</span>
+<a name="l01087"></a>01087 <span class="comment">         */</span>
+<a name="l01088"></a>01088         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#e83fb22890bc54c6b06cedb751430e77">dwc_otg_is_device_mode</a>(core_if)) {
+<a name="l01089"></a>01089                 <a class="code" href="dwc__otg__cil_8c.html#f79b0f3b5b96b0535e33627ee3a66eba">dwc_otg_core_dev_init</a>(core_if);
+<a name="l01090"></a>01090         }
+<a name="l01091"></a>01091 
+<a name="l01092"></a>01092         <span class="comment">/*</span>
+<a name="l01093"></a>01093 <span class="comment">         * Register the PCD Callbacks.</span>
+<a name="l01094"></a>01094 <span class="comment">         */</span>
+<a name="l01095"></a>01095         <a class="code" href="dwc__otg__cil_8c.html#d2a92003214f444d7ec35dd0c4bb4bc0">dwc_otg_cil_register_pcd_callbacks</a>(core_if, &amp;<a class="code" href="dwc__otg__pcd_8c.html#c360aaa36ba28b977284fd482e7bc5ca">pcd_callbacks</a>, pcd);
+<a name="l01096"></a>01096 
+<a name="l01097"></a>01097         <span class="comment">/*</span>
+<a name="l01098"></a>01098 <span class="comment">         * Initialize the DMA buffer for SETUP packets</span>
+<a name="l01099"></a>01099 <span class="comment">         */</span>
+<a name="l01100"></a>01100         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;dma_enable) {
+<a name="l01101"></a>01101                 pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5ea5c519e678fbb382c2ea7d128562c1">setup_pkt</a> =
+<a name="l01102"></a>01102                     dwc_dma_alloc(<span class="keyword">sizeof</span>(*pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5ea5c519e678fbb382c2ea7d128562c1">setup_pkt</a>) * 5,
+<a name="l01103"></a>01103                                   &amp;pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#606d94ec61cca4c21e4dc9cb2e3b7064">setup_pkt_dma_handle</a>);
+<a name="l01104"></a>01104                 <span class="keywordflow">if</span> (pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5ea5c519e678fbb382c2ea7d128562c1">setup_pkt</a> == 0) {
+<a name="l01105"></a>01105                         dwc_free(pcd);
+<a name="l01106"></a>01106                         <span class="keywordflow">return</span> NULL;
+<a name="l01107"></a>01107                 }
+<a name="l01108"></a>01108 
+<a name="l01109"></a>01109                 pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#ca247241f78970f27e5c964fc04d47c8">status_buf</a> =
+<a name="l01110"></a>01110                     dwc_dma_alloc(<span class="keyword">sizeof</span>(uint16_t),
+<a name="l01111"></a>01111                                   &amp;pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#c3880dd4ce15c515ba37b90b6e7fd293">status_buf_dma_handle</a>);
+<a name="l01112"></a>01112                 <span class="keywordflow">if</span> (pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#ca247241f78970f27e5c964fc04d47c8">status_buf</a> == 0) {
+<a name="l01113"></a>01113                         dwc_dma_free(<span class="keyword">sizeof</span>(*pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5ea5c519e678fbb382c2ea7d128562c1">setup_pkt</a>) * 5,
+<a name="l01114"></a>01114                                      pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5ea5c519e678fbb382c2ea7d128562c1">setup_pkt</a>, pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#606d94ec61cca4c21e4dc9cb2e3b7064">setup_pkt_dma_handle</a>);
+<a name="l01115"></a>01115                         dwc_free(pcd);
+<a name="l01116"></a>01116                         <span class="keywordflow">return</span> NULL;
+<a name="l01117"></a>01117                 }
+<a name="l01118"></a>01118 
+<a name="l01119"></a>01119                 <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;dma_desc_enable) {
+<a name="l01120"></a>01120                         dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#f149a6cbedd5f180ff033caeee6f527e">setup_desc_addr</a>[0] =
+<a name="l01121"></a>01121                             <a class="code" href="dwc__otg__pcd_8c.html#18b4a856523673f3bf97b676c8d9717e">dwc_otg_ep_alloc_desc_chain</a>(&amp;dev_if-&gt;
+<a name="l01122"></a>01122                                                         dma_setup_desc_addr[0],
+<a name="l01123"></a>01123                                                         1);
+<a name="l01124"></a>01124                         dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#f149a6cbedd5f180ff033caeee6f527e">setup_desc_addr</a>[1] =
+<a name="l01125"></a>01125                             <a class="code" href="dwc__otg__pcd_8c.html#18b4a856523673f3bf97b676c8d9717e">dwc_otg_ep_alloc_desc_chain</a>(&amp;dev_if-&gt;
+<a name="l01126"></a>01126                                                         dma_setup_desc_addr[1],
+<a name="l01127"></a>01127                                                         1);
+<a name="l01128"></a>01128                         dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#99f44e328bbb4401aabd8e2708853238">in_desc_addr</a> =
+<a name="l01129"></a>01129                             <a class="code" href="dwc__otg__pcd_8c.html#18b4a856523673f3bf97b676c8d9717e">dwc_otg_ep_alloc_desc_chain</a>(&amp;dev_if-&gt;
+<a name="l01130"></a>01130                                                         dma_in_desc_addr, 1);
+<a name="l01131"></a>01131                         dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#8cc9be8ccaba2ef93b02b34ba7b26bad">out_desc_addr</a> =
+<a name="l01132"></a>01132                             <a class="code" href="dwc__otg__pcd_8c.html#18b4a856523673f3bf97b676c8d9717e">dwc_otg_ep_alloc_desc_chain</a>(&amp;dev_if-&gt;
+<a name="l01133"></a>01133                                                         dma_out_desc_addr, 1);
+<a name="l01134"></a>01134 
+<a name="l01135"></a>01135                         <span class="keywordflow">if</span> (dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#f149a6cbedd5f180ff033caeee6f527e">setup_desc_addr</a>[0] == 0
+<a name="l01136"></a>01136                             || dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#f149a6cbedd5f180ff033caeee6f527e">setup_desc_addr</a>[1] == 0
+<a name="l01137"></a>01137                             || dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#99f44e328bbb4401aabd8e2708853238">in_desc_addr</a> == 0
+<a name="l01138"></a>01138                             || dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#8cc9be8ccaba2ef93b02b34ba7b26bad">out_desc_addr</a> == 0) {
+<a name="l01139"></a>01139 
+<a name="l01140"></a>01140                                 <span class="keywordflow">if</span> (dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#8cc9be8ccaba2ef93b02b34ba7b26bad">out_desc_addr</a>)
+<a name="l01141"></a>01141                                         <a class="code" href="dwc__otg__pcd_8c.html#1926b61a7438bd9a14bd6d6a26c6a63d">dwc_otg_ep_free_desc_chain</a>(dev_if-&gt;
+<a name="l01142"></a>01142                                                                    out_desc_addr,
+<a name="l01143"></a>01143                                                                    dev_if-&gt;
+<a name="l01144"></a>01144                                                                    dma_out_desc_addr,
+<a name="l01145"></a>01145                                                                    1);
+<a name="l01146"></a>01146                                 <span class="keywordflow">if</span> (dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#99f44e328bbb4401aabd8e2708853238">in_desc_addr</a>)
+<a name="l01147"></a>01147                                         <a class="code" href="dwc__otg__pcd_8c.html#1926b61a7438bd9a14bd6d6a26c6a63d">dwc_otg_ep_free_desc_chain</a>(dev_if-&gt;
+<a name="l01148"></a>01148                                                                    in_desc_addr,
+<a name="l01149"></a>01149                                                                    dev_if-&gt;
+<a name="l01150"></a>01150                                                                    dma_in_desc_addr,
+<a name="l01151"></a>01151                                                                    1);
+<a name="l01152"></a>01152                                 <span class="keywordflow">if</span> (dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#f149a6cbedd5f180ff033caeee6f527e">setup_desc_addr</a>[1])
+<a name="l01153"></a>01153                                         <a class="code" href="dwc__otg__pcd_8c.html#1926b61a7438bd9a14bd6d6a26c6a63d">dwc_otg_ep_free_desc_chain</a>(dev_if-&gt;
+<a name="l01154"></a>01154                                                                    setup_desc_addr
+<a name="l01155"></a>01155                                                                    [1],
+<a name="l01156"></a>01156                                                                    dev_if-&gt;
+<a name="l01157"></a>01157                                                                    dma_setup_desc_addr
+<a name="l01158"></a>01158                                                                    [1], 1);
+<a name="l01159"></a>01159                                 <span class="keywordflow">if</span> (dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#f149a6cbedd5f180ff033caeee6f527e">setup_desc_addr</a>[0])
+<a name="l01160"></a>01160                                         <a class="code" href="dwc__otg__pcd_8c.html#1926b61a7438bd9a14bd6d6a26c6a63d">dwc_otg_ep_free_desc_chain</a>(dev_if-&gt;
+<a name="l01161"></a>01161                                                                    setup_desc_addr
+<a name="l01162"></a>01162                                                                    [0],
+<a name="l01163"></a>01163                                                                    dev_if-&gt;
+<a name="l01164"></a>01164                                                                    dma_setup_desc_addr
+<a name="l01165"></a>01165                                                                    [0], 1);
+<a name="l01166"></a>01166 
+<a name="l01167"></a>01167                                 dwc_dma_free(<span class="keyword">sizeof</span>(*pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5ea5c519e678fbb382c2ea7d128562c1">setup_pkt</a>) * 5,
+<a name="l01168"></a>01168                                              pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5ea5c519e678fbb382c2ea7d128562c1">setup_pkt</a>,
+<a name="l01169"></a>01169                                              pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#606d94ec61cca4c21e4dc9cb2e3b7064">setup_pkt_dma_handle</a>);
+<a name="l01170"></a>01170                                 dwc_dma_free(<span class="keyword">sizeof</span>(*pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#ca247241f78970f27e5c964fc04d47c8">status_buf</a>),
+<a name="l01171"></a>01171                                              pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#ca247241f78970f27e5c964fc04d47c8">status_buf</a>,
+<a name="l01172"></a>01172                                              pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#c3880dd4ce15c515ba37b90b6e7fd293">status_buf_dma_handle</a>);
+<a name="l01173"></a>01173 
+<a name="l01174"></a>01174                                 dwc_free(pcd);
+<a name="l01175"></a>01175 
+<a name="l01176"></a>01176                                 <span class="keywordflow">return</span> NULL;
+<a name="l01177"></a>01177                         }
+<a name="l01178"></a>01178                 }
+<a name="l01179"></a>01179         } <span class="keywordflow">else</span> {
+<a name="l01180"></a>01180                 pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5ea5c519e678fbb382c2ea7d128562c1">setup_pkt</a> = dwc_alloc(<span class="keyword">sizeof</span>(*pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5ea5c519e678fbb382c2ea7d128562c1">setup_pkt</a>) * 5);
+<a name="l01181"></a>01181                 <span class="keywordflow">if</span> (pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5ea5c519e678fbb382c2ea7d128562c1">setup_pkt</a> == 0) {
+<a name="l01182"></a>01182                         dwc_free(pcd);
+<a name="l01183"></a>01183                         <span class="keywordflow">return</span> NULL;
+<a name="l01184"></a>01184                 }
+<a name="l01185"></a>01185 
+<a name="l01186"></a>01186                 pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#ca247241f78970f27e5c964fc04d47c8">status_buf</a> = dwc_alloc(<span class="keyword">sizeof</span>(uint16_t));
+<a name="l01187"></a>01187                 <span class="keywordflow">if</span> (pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#ca247241f78970f27e5c964fc04d47c8">status_buf</a> == 0) {
+<a name="l01188"></a>01188                         dwc_free(pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5ea5c519e678fbb382c2ea7d128562c1">setup_pkt</a>);
+<a name="l01189"></a>01189                         dwc_free(pcd);
+<a name="l01190"></a>01190                         <span class="keywordflow">return</span> NULL;
+<a name="l01191"></a>01191                 }
+<a name="l01192"></a>01192         }
+<a name="l01193"></a>01193 
+<a name="l01194"></a>01194         <a class="code" href="dwc__otg__pcd_8c.html#b6506996bd4b93ef4f80092a64384fae">dwc_otg_pcd_reinit</a>(pcd);
+<a name="l01195"></a>01195 
+<a name="l01196"></a>01196         <span class="comment">/* Allocate the cfi object for the PCD */</span>
+<a name="l01197"></a>01197 <span class="preprocessor">#ifdef DWC_UTE_CFI</span>
+<a name="l01198"></a>01198 <span class="preprocessor"></span>        pcd-&gt;cfi = dwc_alloc(<span class="keyword">sizeof</span>(<a class="code" href="structcfiobject.html">cfiobject_t</a>));
+<a name="l01199"></a>01199         <span class="keywordflow">if</span> (NULL == pcd-&gt;cfi)
+<a name="l01200"></a>01200                 <span class="keywordflow">return</span> NULL;
+<a name="l01201"></a>01201         <span class="keywordflow">if</span> (init_cfi(pcd-&gt;cfi)) {
+<a name="l01202"></a>01202                 <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>(<span class="stringliteral">"%s: Failed to init the CFI object\n"</span>, __func__);
+<a name="l01203"></a>01203                 <span class="keywordflow">return</span> NULL;
+<a name="l01204"></a>01204         }
+<a name="l01205"></a>01205 <span class="preprocessor">#endif</span>
+<a name="l01206"></a>01206 <span class="preprocessor"></span>
+<a name="l01207"></a>01207         <span class="comment">/* Initialize tasklets */</span>
+<a name="l01208"></a>01208         pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#9b45cd00cd5835aba4236529a04b28f1">start_xfer_tasklet</a> = DWC_TASK_ALLOC(<a class="code" href="dwc__otg__pcd_8c.html#4d9d8f7fb8f74eb64176fba91b38cb35">start_xfer_tasklet_func</a>, pcd);
+<a name="l01209"></a>01209         pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#d1aed2eb03a93032a1ce80e3145bb81e">test_mode_tasklet</a> = DWC_TASK_ALLOC(<a class="code" href="dwc__otg__pcd_8h.html#9d6d6e24faab6478aef9e2217c9b5ab9">do_test_mode</a>, pcd);
+<a name="l01210"></a>01210         <span class="comment">/* Initialize timer */</span>
+<a name="l01211"></a>01211         pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#466fb6ae524fc970f164701db2e70246">srp_timer</a> = DWC_TIMER_ALLOC(<span class="stringliteral">"SRP TIMER"</span>, <a class="code" href="dwc__otg__pcd_8c.html#e1e5a9264c2ad212d697d6be1110874f">srp_timeout</a>, core_if);
+<a name="l01212"></a>01212         <span class="keywordflow">return</span> pcd;
+<a name="l01213"></a>01213 }
+<a name="l01214"></a>01214 
+<a name="l01215"></a><a class="code" href="dwc__otg__pcd__if_8h.html#aaab1535dacd5e947c1f9343d9b3ddf5">01215</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd_8c.html#aaab1535dacd5e947c1f9343d9b3ddf5">dwc_otg_pcd_remove</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd)
+<a name="l01216"></a>01216 {
+<a name="l01217"></a>01217         <a class="code" href="structdwc__otg__dev__if.html">dwc_otg_dev_if_t</a> *dev_if = <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;dev_if;
+<a name="l01218"></a>01218 
+<a name="l01219"></a>01219         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;dma_enable) {
+<a name="l01220"></a>01220                 dwc_dma_free(<span class="keyword">sizeof</span>(*pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5ea5c519e678fbb382c2ea7d128562c1">setup_pkt</a>) * 5, pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5ea5c519e678fbb382c2ea7d128562c1">setup_pkt</a>,
+<a name="l01221"></a>01221                              pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#606d94ec61cca4c21e4dc9cb2e3b7064">setup_pkt_dma_handle</a>);
+<a name="l01222"></a>01222                 dwc_dma_free(<span class="keyword">sizeof</span>(uint16_t), pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#ca247241f78970f27e5c964fc04d47c8">status_buf</a>,
+<a name="l01223"></a>01223                              pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#c3880dd4ce15c515ba37b90b6e7fd293">status_buf_dma_handle</a>);
+<a name="l01224"></a>01224                 <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;dma_desc_enable) {
+<a name="l01225"></a>01225                         <a class="code" href="dwc__otg__pcd_8c.html#1926b61a7438bd9a14bd6d6a26c6a63d">dwc_otg_ep_free_desc_chain</a>(dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#f149a6cbedd5f180ff033caeee6f527e">setup_desc_addr</a>[0],
+<a name="l01226"></a>01226                                                    dev_if-&gt;
+<a name="l01227"></a>01227                                                    dma_setup_desc_addr[0], 1);
+<a name="l01228"></a>01228                         <a class="code" href="dwc__otg__pcd_8c.html#1926b61a7438bd9a14bd6d6a26c6a63d">dwc_otg_ep_free_desc_chain</a>(dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#f149a6cbedd5f180ff033caeee6f527e">setup_desc_addr</a>[1],
+<a name="l01229"></a>01229                                                    dev_if-&gt;
+<a name="l01230"></a>01230                                                    dma_setup_desc_addr[1], 1);
+<a name="l01231"></a>01231                         <a class="code" href="dwc__otg__pcd_8c.html#1926b61a7438bd9a14bd6d6a26c6a63d">dwc_otg_ep_free_desc_chain</a>(dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#99f44e328bbb4401aabd8e2708853238">in_desc_addr</a>,
+<a name="l01232"></a>01232                                                    dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#ba2f5eede8b3deaaec8882baeea6a35b">dma_in_desc_addr</a>, 1);
+<a name="l01233"></a>01233                         <a class="code" href="dwc__otg__pcd_8c.html#1926b61a7438bd9a14bd6d6a26c6a63d">dwc_otg_ep_free_desc_chain</a>(dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#8cc9be8ccaba2ef93b02b34ba7b26bad">out_desc_addr</a>,
+<a name="l01234"></a>01234                                                    dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#3829a415bbaf0f5c3e29b1a9f3cf546b">dma_out_desc_addr</a>,
+<a name="l01235"></a>01235                                                    1);
+<a name="l01236"></a>01236                 }
+<a name="l01237"></a>01237         } <span class="keywordflow">else</span> {
+<a name="l01238"></a>01238                 dwc_free(pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5ea5c519e678fbb382c2ea7d128562c1">setup_pkt</a>);
+<a name="l01239"></a>01239                 dwc_free(pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#ca247241f78970f27e5c964fc04d47c8">status_buf</a>);
+<a name="l01240"></a>01240         }
+<a name="l01241"></a>01241         DWC_SPINLOCK_FREE(pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5d450e4d06659ab2f3b18e5c816776e4">lock</a>);
+<a name="l01242"></a>01242         DWC_TASK_FREE(pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#9b45cd00cd5835aba4236529a04b28f1">start_xfer_tasklet</a>);
+<a name="l01243"></a>01243         DWC_TASK_FREE(pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#d1aed2eb03a93032a1ce80e3145bb81e">test_mode_tasklet</a>);
+<a name="l01244"></a>01244         DWC_TIMER_FREE(pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#466fb6ae524fc970f164701db2e70246">srp_timer</a>);
+<a name="l01245"></a>01245 
+<a name="l01246"></a>01246 <span class="comment">/* Release the CFI object's dynamic memory */</span>
+<a name="l01247"></a>01247 <span class="preprocessor">#ifdef DWC_UTE_CFI</span>
+<a name="l01248"></a>01248 <span class="preprocessor"></span>        <span class="keywordflow">if</span> (pcd-&gt;cfi-&gt;ops.release) {
+<a name="l01249"></a>01249                 pcd-&gt;cfi-&gt;ops.release(pcd-&gt;cfi);
+<a name="l01250"></a>01250         }
+<a name="l01251"></a>01251 <span class="preprocessor">#endif</span>
+<a name="l01252"></a>01252 <span class="preprocessor"></span>
+<a name="l01253"></a>01253         dwc_free(pcd);
+<a name="l01254"></a>01254 }
+<a name="l01255"></a>01255 
+<a name="l01256"></a><a class="code" href="dwc__otg__pcd__if_8h.html#ae9b15825812485a06be318858e0316a">01256</a> uint32_t <a class="code" href="dwc__otg__pcd_8c.html#ae9b15825812485a06be318858e0316a">dwc_otg_pcd_is_dualspeed</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd)
+<a name="l01257"></a>01257 {
+<a name="l01258"></a>01258         <a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if = <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd);
+<a name="l01259"></a>01259 
+<a name="l01260"></a>01260         <span class="keywordflow">if</span> ((core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#d2c4f622f1c14f68c6e60e2603acd09d">speed</a> == <a class="code" href="dwc__otg__core__if_8h.html#353c64bfe6bbc9da8406528ad8220166">DWC_SPEED_PARAM_FULL</a>) ||
+<a name="l01261"></a>01261             ((core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">hwcfg2</a>.<a class="code" href="unionhwcfg2__data.html#9dcc70e2dba617cbc6c12189be5c1d6a">b</a>.<a class="code" href="unionhwcfg2__data.html#a248a2502e3c440d7b6e4ad61d396f4e">hs_phy_type</a> == 2) &amp;&amp;
+<a name="l01262"></a>01262              (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">hwcfg2</a>.<a class="code" href="unionhwcfg2__data.html#9dcc70e2dba617cbc6c12189be5c1d6a">b</a>.<a class="code" href="unionhwcfg2__data.html#e75417d7e2d1843abf6e48f67851326e">fs_phy_type</a> == 1) &amp;&amp;
+<a name="l01263"></a>01263              (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#3d7cfc3c416010102b2c671dfaa828d5">ulpi_fs_ls</a>))) {
+<a name="l01264"></a>01264                 <span class="keywordflow">return</span> 0;
+<a name="l01265"></a>01265         }
+<a name="l01266"></a>01266 
+<a name="l01267"></a>01267         <span class="keywordflow">return</span> 1;
+<a name="l01268"></a>01268 }
+<a name="l01269"></a>01269 
+<a name="l01270"></a><a class="code" href="dwc__otg__pcd__if_8h.html#07169d2569c7e071fc99045fd435f2c6">01270</a> uint32_t <a class="code" href="dwc__otg__pcd_8c.html#07169d2569c7e071fc99045fd435f2c6">dwc_otg_pcd_is_otg</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd)
+<a name="l01271"></a>01271 {
+<a name="l01272"></a>01272         <a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if = <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd);
+<a name="l01273"></a>01273         <a class="code" href="uniongusbcfg__data.html">gusbcfg_data_t</a> usbcfg = {.d32 = 0 };
+<a name="l01274"></a>01274 
+<a name="l01275"></a>01275         usbcfg.<a class="code" href="uniongusbcfg__data.html#c3d8f2d95fd61a172eb108cb72a85b47">d32</a> = dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#ef39e181e246447df47c56aa4e37cc42">gusbcfg</a>);
+<a name="l01276"></a>01276         <span class="keywordflow">if</span> (!usbcfg.<a class="code" href="uniongusbcfg__data.html#1dab81bf7260b1e23f97298c34abea06">b</a>.<a class="code" href="uniongusbcfg__data.html#44485a787b8a386fadae801869ce7810">srpcap</a> || !usbcfg.<a class="code" href="uniongusbcfg__data.html#1dab81bf7260b1e23f97298c34abea06">b</a>.<a class="code" href="uniongusbcfg__data.html#71b6330c5ccf1d21ebf79a0a829612b5">hnpcap</a>) {
+<a name="l01277"></a>01277                 <span class="keywordflow">return</span> 0;
+<a name="l01278"></a>01278         }
+<a name="l01279"></a>01279 
+<a name="l01280"></a>01280         <span class="keywordflow">return</span> 1;
+<a name="l01281"></a>01281 }
+<a name="l01282"></a>01282 
+<a name="l01287"></a><a class="code" href="dwc__otg__pcd_8c.html#5b3f2d055af51e556be50f3ada673e4a">01287</a> <span class="keyword">static</span> uint32_t <a class="code" href="dwc__otg__pcd_8c.html#5b3f2d055af51e556be50f3ada673e4a">assign_tx_fifo</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l01288"></a>01288 {
+<a name="l01289"></a>01289         uint32_t TxMsk = 1;
+<a name="l01290"></a>01290         <span class="keywordtype">int</span> i;
+<a name="l01291"></a>01291 
+<a name="l01292"></a>01292         <span class="keywordflow">for</span> (i = 0; i &lt; core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#9c1394f3c46adde2fa7be79bf0237f9b">hwcfg4</a>.<a class="code" href="unionhwcfg4__data.html#9fb9175668e2381c568c5adbf6e5225d">b</a>.<a class="code" href="unionhwcfg4__data.html#753b321350388c5e1307802ff968f9a8">num_in_eps</a>; ++i) {
+<a name="l01293"></a>01293                 <span class="keywordflow">if</span> ((TxMsk &amp; core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#b558bae74403677f08e45c692a88d4e2">tx_msk</a>) == 0) {
+<a name="l01294"></a>01294                         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#b558bae74403677f08e45c692a88d4e2">tx_msk</a> |= TxMsk;
+<a name="l01295"></a>01295                         <span class="keywordflow">return</span> i + 1;
+<a name="l01296"></a>01296                 }
+<a name="l01297"></a>01297                 TxMsk &lt;&lt;= 1;
+<a name="l01298"></a>01298         }
+<a name="l01299"></a>01299         <span class="keywordflow">return</span> 0;
+<a name="l01300"></a>01300 }
+<a name="l01301"></a>01301 
+<a name="l01306"></a><a class="code" href="dwc__otg__pcd_8c.html#1df421d3a1449ec3a927d0a006c57c38">01306</a> <span class="keyword">static</span> uint32_t <a class="code" href="dwc__otg__pcd_8c.html#1df421d3a1449ec3a927d0a006c57c38">assign_perio_tx_fifo</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if)
+<a name="l01307"></a>01307 {
+<a name="l01308"></a>01308         uint32_t PerTxMsk = 1;
+<a name="l01309"></a>01309         <span class="keywordtype">int</span> i;
+<a name="l01310"></a>01310         <span class="keywordflow">for</span> (i = 0; i &lt; core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#9c1394f3c46adde2fa7be79bf0237f9b">hwcfg4</a>.<a class="code" href="unionhwcfg4__data.html#9fb9175668e2381c568c5adbf6e5225d">b</a>.<a class="code" href="unionhwcfg4__data.html#aee60fb196cf53b610df556744e4d317">num_dev_perio_in_ep</a>; ++i) {
+<a name="l01311"></a>01311                 <span class="keywordflow">if</span> ((PerTxMsk &amp; core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#0683b28ebf5247a60247d27a1a714d27">p_tx_msk</a>) == 0) {
+<a name="l01312"></a>01312                         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#0683b28ebf5247a60247d27a1a714d27">p_tx_msk</a> |= PerTxMsk;
+<a name="l01313"></a>01313                         <span class="keywordflow">return</span> i + 1;
+<a name="l01314"></a>01314                 }
+<a name="l01315"></a>01315                 PerTxMsk &lt;&lt;= 1;
+<a name="l01316"></a>01316         }
+<a name="l01317"></a>01317         <span class="keywordflow">return</span> 0;
+<a name="l01318"></a>01318 }
+<a name="l01319"></a>01319 
+<a name="l01324"></a><a class="code" href="dwc__otg__pcd_8c.html#1bd1933ef625beee77eb026c4b1acb15">01324</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd_8c.html#1bd1933ef625beee77eb026c4b1acb15">release_perio_tx_fifo</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if,
+<a name="l01325"></a>01325                                   uint32_t fifo_num)
+<a name="l01326"></a>01326 {
+<a name="l01327"></a>01327         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#0683b28ebf5247a60247d27a1a714d27">p_tx_msk</a> =
+<a name="l01328"></a>01328             (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#0683b28ebf5247a60247d27a1a714d27">p_tx_msk</a> &amp; (1 &lt;&lt; (fifo_num - 1))) ^ core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#0683b28ebf5247a60247d27a1a714d27">p_tx_msk</a>;
+<a name="l01329"></a>01329 }
+<a name="l01330"></a>01330 
+<a name="l01335"></a><a class="code" href="dwc__otg__pcd_8c.html#bde782d98282535dc0c29a468da11f02">01335</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd_8c.html#bde782d98282535dc0c29a468da11f02">release_tx_fifo</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, uint32_t fifo_num)
+<a name="l01336"></a>01336 {
+<a name="l01337"></a>01337         core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#b558bae74403677f08e45c692a88d4e2">tx_msk</a> =
+<a name="l01338"></a>01338             (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#b558bae74403677f08e45c692a88d4e2">tx_msk</a> &amp; (1 &lt;&lt; (fifo_num - 1))) ^ core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#b558bae74403677f08e45c692a88d4e2">tx_msk</a>;
+<a name="l01339"></a>01339 }
+<a name="l01340"></a>01340 
+<a name="l01341"></a><a class="code" href="dwc__otg__pcd__if_8h.html#109bb0fec2e7ef5b5cac3763f8371551">01341</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__pcd_8c.html#b9168f11717bdc672d9a29226779e523">dwc_otg_pcd_ep_enable</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd,
+<a name="l01342"></a>01342                           <span class="keyword">const</span> uint8_t * ep_desc, <span class="keywordtype">void</span> *usb_ep)
+<a name="l01343"></a>01343 {
+<a name="l01344"></a>01344         <span class="keywordtype">int</span> num, dir;
+<a name="l01345"></a>01345         <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *ep = 0;
+<a name="l01346"></a>01346         <span class="keyword">const</span> usb_endpoint_descriptor_t *desc;
+<a name="l01347"></a>01347         uint64_t flags;
+<a name="l01348"></a>01348         <span class="keywordtype">int</span> retval = 0;
+<a name="l01349"></a>01349 
+<a name="l01350"></a>01350         desc = (<span class="keyword">const</span> usb_endpoint_descriptor_t *)ep_desc;
+<a name="l01351"></a>01351 
+<a name="l01352"></a>01352         <span class="keywordflow">if</span> (!desc) {
+<a name="l01353"></a>01353                 pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a>.<a class="code" href="structdwc__otg__pcd__ep.html#8c8fad971c6c3b1c54d334c7f9b2d03e">priv</a> = usb_ep;
+<a name="l01354"></a>01354                 ep = &amp;pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a>;
+<a name="l01355"></a>01355                 retval = -DWC_E_INVALID;
+<a name="l01356"></a>01356                 <span class="keywordflow">goto</span> out;
+<a name="l01357"></a>01357         }
+<a name="l01358"></a>01358 
+<a name="l01359"></a>01359         num = UE_GET_ADDR(desc-&gt;bEndpointAddress);
+<a name="l01360"></a>01360         dir = UE_GET_DIR(desc-&gt;bEndpointAddress);
+<a name="l01361"></a>01361 
+<a name="l01362"></a>01362         <span class="keywordflow">if</span> (!desc-&gt;wMaxPacketSize) {
+<a name="l01363"></a>01363                 DWC_WARN(<span class="stringliteral">"bad maxpacketsize\n"</span>);
+<a name="l01364"></a>01364                 retval = -DWC_E_INVALID;
+<a name="l01365"></a>01365                 <span class="keywordflow">goto</span> out;
+<a name="l01366"></a>01366         }
+<a name="l01367"></a>01367 
+<a name="l01368"></a>01368         <span class="keywordflow">if</span> (dir == UE_DIR_IN) {
+<a name="l01369"></a>01369                 ep = &amp;pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#dbfc8c424ea3add38db96fa87219caa8">in_ep</a>[num - 1];
+<a name="l01370"></a>01370         } <span class="keywordflow">else</span> {
+<a name="l01371"></a>01371                 ep = &amp;pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#b9e49a1d1fbca5ba9523e27c7108df30">out_ep</a>[num - 1];
+<a name="l01372"></a>01372         }
+<a name="l01373"></a>01373 
+<a name="l01374"></a>01374         DWC_SPINLOCK_IRQSAVE(pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5d450e4d06659ab2f3b18e5c816776e4">lock</a>, &amp;flags);
+<a name="l01375"></a>01375 
+<a name="l01376"></a>01376         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#86e27843c439dd0b1d12d9bf2dc6516f">desc</a> = desc;
+<a name="l01377"></a>01377         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#8c8fad971c6c3b1c54d334c7f9b2d03e">priv</a> = usb_ep;
+<a name="l01378"></a>01378 
+<a name="l01379"></a>01379         <span class="comment">/*</span>
+<a name="l01380"></a>01380 <span class="comment">         * Activate the EP</span>
+<a name="l01381"></a>01381 <span class="comment">         */</span>
+<a name="l01382"></a>01382         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#cce0e089118d8bf7c6278c21ded70d5a">stopped</a> = 0;
+<a name="l01383"></a>01383 
+<a name="l01384"></a>01384         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#b882b6b7c857100ed20600e94ea37760">is_in</a> = (dir == UE_DIR_IN);
+<a name="l01385"></a>01385         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a> = UGETW(desc-&gt;wMaxPacketSize);
+<a name="l01386"></a>01386 
+<a name="l01387"></a>01387         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#17b10677bd9b0a1d612dd4ce2fb0eb0f">type</a> = desc-&gt;bmAttributes &amp; UE_XFERTYPE;
+<a name="l01388"></a>01388 
+<a name="l01389"></a>01389         <span class="keywordflow">if</span> (ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#b882b6b7c857100ed20600e94ea37760">is_in</a>) {
+<a name="l01390"></a>01390                 <span class="keywordflow">if</span> (!<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;en_multiple_tx_fifo) {
+<a name="l01391"></a>01391                         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#ffa14f48094778143353b845b5d238cd">tx_fifo_num</a> = 0;
+<a name="l01392"></a>01392 
+<a name="l01393"></a>01393                         <span class="keywordflow">if</span> (ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#17b10677bd9b0a1d612dd4ce2fb0eb0f">type</a> == UE_ISOCHRONOUS) {
+<a name="l01394"></a>01394                                 <span class="comment">/*</span>
+<a name="l01395"></a>01395 <span class="comment">                                 * if ISOC EP then assign a Periodic Tx FIFO.</span>
+<a name="l01396"></a>01396 <span class="comment">                                 */</span>
+<a name="l01397"></a>01397                                 ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#ffa14f48094778143353b845b5d238cd">tx_fifo_num</a> =
+<a name="l01398"></a>01398                                     <a class="code" href="dwc__otg__pcd_8c.html#1df421d3a1449ec3a927d0a006c57c38">assign_perio_tx_fifo</a>(<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd));
+<a name="l01399"></a>01399                         }
+<a name="l01400"></a>01400                 } <span class="keywordflow">else</span> {
+<a name="l01401"></a>01401                         <span class="comment">/*</span>
+<a name="l01402"></a>01402 <span class="comment">                         * if Dedicated FIFOs mode is on then assign a Tx FIFO.</span>
+<a name="l01403"></a>01403 <span class="comment">                         */</span>
+<a name="l01404"></a>01404                         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#ffa14f48094778143353b845b5d238cd">tx_fifo_num</a> =
+<a name="l01405"></a>01405                             <a class="code" href="dwc__otg__pcd_8c.html#5b3f2d055af51e556be50f3ada673e4a">assign_tx_fifo</a>(<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd));
+<a name="l01406"></a>01406 
+<a name="l01407"></a>01407                 }
+<a name="l01408"></a>01408         }
+<a name="l01409"></a>01409         <span class="comment">/* Set initial data PID. */</span>
+<a name="l01410"></a>01410         <span class="keywordflow">if</span> (ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#17b10677bd9b0a1d612dd4ce2fb0eb0f">type</a> == UE_BULK) {
+<a name="l01411"></a>01411                 ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#4ceafa9e067ba462ab38c20ffcf8d597">data_pid_start</a> = 0;
+<a name="l01412"></a>01412         }
+<a name="l01413"></a>01413 
+<a name="l01414"></a>01414         <span class="comment">/* Alloc DMA Descriptors */</span>
+<a name="l01415"></a>01415         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;dma_desc_enable) {
+<a name="l01416"></a>01416                 <span class="keywordflow">if</span> (ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#17b10677bd9b0a1d612dd4ce2fb0eb0f">type</a> != UE_ISOCHRONOUS) {
+<a name="l01417"></a>01417                         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#57e934b26e76939912eaa76321075a0d">desc_addr</a> =
+<a name="l01418"></a>01418                             <a class="code" href="dwc__otg__pcd_8c.html#18b4a856523673f3bf97b676c8d9717e">dwc_otg_ep_alloc_desc_chain</a>(&amp;ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.
+<a name="l01419"></a>01419                                                         dma_desc_addr,
+<a name="l01420"></a>01420                                                         <a class="code" href="dwc__otg__pcd_8h.html#a1c5dc8973b5c039fd77b1e250ce29e2">MAX_DMA_DESC_CNT</a>);
+<a name="l01421"></a>01421                         <span class="keywordflow">if</span> (!ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#57e934b26e76939912eaa76321075a0d">desc_addr</a>) {
+<a name="l01422"></a>01422                                 DWC_WARN(<span class="stringliteral">"%s, can't allocate DMA descriptor\n"</span>,
+<a name="l01423"></a>01423                                          __func__);
+<a name="l01424"></a>01424                                 retval = -DWC_E_SHUTDOWN;
+<a name="l01425"></a>01425                                 DWC_SPINUNLOCK_IRQRESTORE(pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5d450e4d06659ab2f3b18e5c816776e4">lock</a>, flags);
+<a name="l01426"></a>01426                                 <span class="keywordflow">goto</span> out;
+<a name="l01427"></a>01427                         }
+<a name="l01428"></a>01428                 }
+<a name="l01429"></a>01429         }
+<a name="l01430"></a>01430 
+<a name="l01431"></a>01431         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"Activate %s: type=%d, mps=%d desc=%p\n"</span>,
+<a name="l01432"></a>01432                     (ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#b882b6b7c857100ed20600e94ea37760">is_in</a> ? <span class="stringliteral">"IN"</span> : <span class="stringliteral">"OUT"</span>),
+<a name="l01433"></a>01433                     ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#17b10677bd9b0a1d612dd4ce2fb0eb0f">type</a>, ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a>, ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#86e27843c439dd0b1d12d9bf2dc6516f">desc</a>);
+<a name="l01434"></a>01434 
+<a name="l01435"></a>01435         <a class="code" href="dwc__otg__cil_8c.html#5e5a1fb1ff70d5c42d8cf4a1c5d12b7f">dwc_otg_ep_activate</a>(<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd), &amp;ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>);
+<a name="l01436"></a>01436 
+<a name="l01437"></a>01437 <span class="preprocessor">#ifdef DWC_UTE_CFI</span>
+<a name="l01438"></a>01438 <span class="preprocessor"></span>        <span class="keywordflow">if</span> (pcd-&gt;cfi-&gt;ops.ep_enable) {
+<a name="l01439"></a>01439                 pcd-&gt;cfi-&gt;ops.ep_enable(pcd-&gt;cfi, pcd, ep);
+<a name="l01440"></a>01440         }
+<a name="l01441"></a>01441 <span class="preprocessor">#endif</span>
+<a name="l01442"></a>01442 <span class="preprocessor"></span>
+<a name="l01443"></a>01443         DWC_SPINUNLOCK_IRQRESTORE(pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5d450e4d06659ab2f3b18e5c816776e4">lock</a>, flags);
+<a name="l01444"></a>01444 
+<a name="l01445"></a>01445       out:
+<a name="l01446"></a>01446         <span class="keywordflow">return</span> retval;
+<a name="l01447"></a>01447 }
+<a name="l01448"></a>01448 
+<a name="l01449"></a><a class="code" href="dwc__otg__pcd__if_8h.html#8a2f791c79320c8c4657715a672822a4">01449</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__pcd_8c.html#8a2f791c79320c8c4657715a672822a4">dwc_otg_pcd_ep_disable</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd, <span class="keywordtype">void</span> *ep_handle)
+<a name="l01450"></a>01450 {
+<a name="l01451"></a>01451         <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *ep;
+<a name="l01452"></a>01452         uint64_t flags;
+<a name="l01453"></a>01453         <a class="code" href="structdwc__otg__dev__dma__desc.html">dwc_otg_dev_dma_desc_t</a> *desc_addr;
+<a name="l01454"></a>01454         dwc_dma_t dma_desc_addr;
+<a name="l01455"></a>01455 
+<a name="l01456"></a>01456         ep = <a class="code" href="dwc__otg__pcd_8c.html#4b46c226fa34cd7fc4ceec2c5e7f8ebe">get_ep_from_handle</a>(pcd, ep_handle);
+<a name="l01457"></a>01457 
+<a name="l01458"></a>01458         <span class="keywordflow">if</span> (!ep || !ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#86e27843c439dd0b1d12d9bf2dc6516f">desc</a>) {
+<a name="l01459"></a>01459                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"%s, %d %s not enabled\n"</span>, __func__,
+<a name="l01460"></a>01460                             ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a>, ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#b882b6b7c857100ed20600e94ea37760">is_in</a> ? <span class="stringliteral">"IN"</span> : <span class="stringliteral">"OUT"</span>);
+<a name="l01461"></a>01461                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l01462"></a>01462         }
+<a name="l01463"></a>01463 
+<a name="l01464"></a>01464         DWC_SPINLOCK_IRQSAVE(pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5d450e4d06659ab2f3b18e5c816776e4">lock</a>, &amp;flags);
+<a name="l01465"></a>01465 
+<a name="l01466"></a>01466         <a class="code" href="dwc__otg__pcd_8c.html#e8ef6f3d831b89a753d93489827949d3">dwc_otg_request_nuke</a>(ep);
+<a name="l01467"></a>01467 
+<a name="l01468"></a>01468         <a class="code" href="dwc__otg__cil_8c.html#94789f2d72adb5daf65c99eadced66b3">dwc_otg_ep_deactivate</a>(<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd), &amp;ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>);
+<a name="l01469"></a>01469         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#86e27843c439dd0b1d12d9bf2dc6516f">desc</a> = 0;
+<a name="l01470"></a>01470         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#cce0e089118d8bf7c6278c21ded70d5a">stopped</a> = 1;
+<a name="l01471"></a>01471 
+<a name="l01472"></a>01472         <span class="keywordflow">if</span> (ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#b882b6b7c857100ed20600e94ea37760">is_in</a>) {
+<a name="l01473"></a>01473                 <a class="code" href="dwc__otg__cil_8c.html#039e387cd0e0282727da3c5a36f4cdda">dwc_otg_flush_tx_fifo</a>(<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd), ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#ffa14f48094778143353b845b5d238cd">tx_fifo_num</a>);
+<a name="l01474"></a>01474                 <a class="code" href="dwc__otg__pcd_8c.html#1bd1933ef625beee77eb026c4b1acb15">release_perio_tx_fifo</a>(<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd), ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#ffa14f48094778143353b845b5d238cd">tx_fifo_num</a>);
+<a name="l01475"></a>01475                 <a class="code" href="dwc__otg__pcd_8c.html#bde782d98282535dc0c29a468da11f02">release_tx_fifo</a>(<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd), ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#ffa14f48094778143353b845b5d238cd">tx_fifo_num</a>);
+<a name="l01476"></a>01476         }
+<a name="l01477"></a>01477 
+<a name="l01478"></a>01478         <span class="comment">/* Free DMA Descriptors */</span>
+<a name="l01479"></a>01479         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;dma_desc_enable) {
+<a name="l01480"></a>01480                 <span class="keywordflow">if</span> (ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#17b10677bd9b0a1d612dd4ce2fb0eb0f">type</a> != UE_ISOCHRONOUS) {
+<a name="l01481"></a>01481                         desc_addr = ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#57e934b26e76939912eaa76321075a0d">desc_addr</a>;
+<a name="l01482"></a>01482                         dma_desc_addr = ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#1a43e464429530e874472092e0e1af09">dma_desc_addr</a>;
+<a name="l01483"></a>01483 
+<a name="l01484"></a>01484                         <span class="comment">/* Cannot call dma_free_coherent() with IRQs disabled */</span>
+<a name="l01485"></a>01485                         DWC_SPINUNLOCK_IRQRESTORE(pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5d450e4d06659ab2f3b18e5c816776e4">lock</a>, flags);
+<a name="l01486"></a>01486                         <a class="code" href="dwc__otg__pcd_8c.html#1926b61a7438bd9a14bd6d6a26c6a63d">dwc_otg_ep_free_desc_chain</a>(desc_addr, dma_desc_addr,
+<a name="l01487"></a>01487                                                    <a class="code" href="dwc__otg__pcd_8h.html#a1c5dc8973b5c039fd77b1e250ce29e2">MAX_DMA_DESC_CNT</a>);
+<a name="l01488"></a>01488 
+<a name="l01489"></a>01489                         <span class="keywordflow">goto</span> out_unlocked;
+<a name="l01490"></a>01490                 }
+<a name="l01491"></a>01491         }
+<a name="l01492"></a>01492 
+<a name="l01493"></a>01493         DWC_SPINUNLOCK_IRQRESTORE(pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5d450e4d06659ab2f3b18e5c816776e4">lock</a>, flags);
+<a name="l01494"></a>01494 
+<a name="l01495"></a>01495       out_unlocked:
+<a name="l01496"></a>01496         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"%d %s disabled\n"</span>, ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a>,
+<a name="l01497"></a>01497                     ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#b882b6b7c857100ed20600e94ea37760">is_in</a> ? <span class="stringliteral">"IN"</span> : <span class="stringliteral">"OUT"</span>);
+<a name="l01498"></a>01498         <span class="keywordflow">return</span> 0;
+<a name="l01499"></a>01499 
+<a name="l01500"></a>01500 }
+<a name="l01501"></a>01501 
+<a name="l01502"></a><a class="code" href="dwc__otg__pcd__if_8h.html#09f3d77397aa7d22a1ca32e26c8aedea">01502</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__pcd_8c.html#09f3d77397aa7d22a1ca32e26c8aedea">dwc_otg_pcd_ep_queue</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd, <span class="keywordtype">void</span> *ep_handle,
+<a name="l01503"></a>01503                          uint8_t * buf, dwc_dma_t dma_buf, uint32_t buflen,
+<a name="l01504"></a>01504                          <span class="keywordtype">int</span> zero, <span class="keywordtype">void</span> *req_handle, <span class="keywordtype">int</span> atomic_alloc)
+<a name="l01505"></a>01505 {
+<a name="l01506"></a>01506         <span class="keywordtype">int</span> prevented = 0;
+<a name="l01507"></a>01507         uint64_t flags;
+<a name="l01508"></a>01508         <a class="code" href="structdwc__otg__pcd__request.html">dwc_otg_pcd_request_t</a> *req;
+<a name="l01509"></a>01509         <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *ep;
+<a name="l01510"></a>01510         uint32_t max_transfer;
+<a name="l01511"></a>01511 
+<a name="l01512"></a>01512         ep = <a class="code" href="dwc__otg__pcd_8c.html#4b46c226fa34cd7fc4ceec2c5e7f8ebe">get_ep_from_handle</a>(pcd, ep_handle);
+<a name="l01513"></a>01513         <span class="keywordflow">if</span> ((!ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#86e27843c439dd0b1d12d9bf2dc6516f">desc</a> &amp;&amp; ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a> != 0)) {
+<a name="l01514"></a>01514                 DWC_WARN(<span class="stringliteral">"bad ep\n"</span>);
+<a name="l01515"></a>01515                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l01516"></a>01516         }
+<a name="l01517"></a>01517 
+<a name="l01518"></a>01518         <span class="keywordflow">if</span> (atomic_alloc) {
+<a name="l01519"></a>01519                 req = dwc_alloc_atomic(<span class="keyword">sizeof</span>(*req));
+<a name="l01520"></a>01520         } <span class="keywordflow">else</span> {
+<a name="l01521"></a>01521                 req = dwc_alloc(<span class="keyword">sizeof</span>(*req));
+<a name="l01522"></a>01522         }
+<a name="l01523"></a>01523 
+<a name="l01524"></a>01524         <span class="keywordflow">if</span> (!req) {
+<a name="l01525"></a>01525                 <span class="keywordflow">return</span> -DWC_E_NO_MEMORY;
+<a name="l01526"></a>01526         }
+<a name="l01527"></a>01527         DWC_CIRCLEQ_INIT_ENTRY(req, queue_entry);
+<a name="l01528"></a>01528         <span class="keywordflow">if</span> (!<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;core_params-&gt;opt) {
+<a name="l01529"></a>01529                 <span class="keywordflow">if</span> (ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a> != 0) {
+<a name="l01530"></a>01530                         DWC_ERROR(<span class="stringliteral">"queue req %p, len %d buf %p\n"</span>,
+<a name="l01531"></a>01531                                   req_handle, buflen, buf);
+<a name="l01532"></a>01532                 }
+<a name="l01533"></a>01533         }
+<a name="l01534"></a>01534 
+<a name="l01535"></a>01535         req-&gt;<a class="code" href="structdwc__otg__pcd__request.html#c46438f3d95146654a25cd219d7a1d5a">buf</a> = buf;
+<a name="l01536"></a>01536         req-&gt;<a class="code" href="structdwc__otg__pcd__request.html#df93c8905495816eb0327b192938a4a1">dma</a> = dma_buf;
+<a name="l01537"></a>01537         req-&gt;<a class="code" href="structdwc__otg__pcd__request.html#3dd3fcc889bf220b048023e8b05fab61">length</a> = buflen;
+<a name="l01538"></a>01538         req-&gt;<a class="code" href="structdwc__otg__pcd__request.html#c2c1832d46f417b63e41b5e23def6fc6">sent_zlp</a> = zero;
+<a name="l01539"></a>01539         req-&gt;<a class="code" href="structdwc__otg__pcd__request.html#e0d93b64365968aa0dcf58535aecf40c">priv</a> = req_handle;
+<a name="l01540"></a>01540 
+<a name="l01541"></a>01541         DWC_SPINLOCK_IRQSAVE(pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5d450e4d06659ab2f3b18e5c816776e4">lock</a>, &amp;flags);
+<a name="l01542"></a>01542 
+<a name="l01543"></a>01543         <span class="comment">/*</span>
+<a name="l01544"></a>01544 <span class="comment">         * For EP0 IN without premature status, zlp is required?</span>
+<a name="l01545"></a>01545 <span class="comment">         */</span>
+<a name="l01546"></a>01546         <span class="keywordflow">if</span> (ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a> == 0 &amp;&amp; ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#b882b6b7c857100ed20600e94ea37760">is_in</a>) {
+<a name="l01547"></a>01547                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"%d-OUT ZLP\n"</span>, ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a>);
+<a name="l01548"></a>01548                 <span class="comment">//_req-&gt;zero = 1;</span>
+<a name="l01549"></a>01549         }
+<a name="l01550"></a>01550 
+<a name="l01551"></a>01551         <span class="comment">/* Start the transfer */</span>
+<a name="l01552"></a>01552         <span class="keywordflow">if</span> (DWC_CIRCLEQ_EMPTY(&amp;ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#71f4fa571dfdc96f62fa4869e6add300">queue</a>) &amp;&amp; !ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#cce0e089118d8bf7c6278c21ded70d5a">stopped</a>) {
+<a name="l01553"></a>01553                 <span class="comment">/* EP0 Transfer? */</span>
+<a name="l01554"></a>01554                 <span class="keywordflow">if</span> (ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a> == 0) {
+<a name="l01555"></a>01555                         <span class="keywordflow">switch</span> (pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#8f6963b3fb9ab83048c4c0697c90382a">ep0state</a>) {
+<a name="l01556"></a>01556                         <span class="keywordflow">case</span> EP0_IN_DATA_PHASE:
+<a name="l01557"></a>01557                                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>,
+<a name="l01558"></a>01558                                             <span class="stringliteral">"%s ep0: EP0_IN_DATA_PHASE\n"</span>,
+<a name="l01559"></a>01559                                             __func__);
+<a name="l01560"></a>01560                                 <span class="keywordflow">break</span>;
+<a name="l01561"></a>01561 
+<a name="l01562"></a>01562                         <span class="keywordflow">case</span> EP0_OUT_DATA_PHASE:
+<a name="l01563"></a>01563                                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>,
+<a name="l01564"></a>01564                                             <span class="stringliteral">"%s ep0: EP0_OUT_DATA_PHASE\n"</span>,
+<a name="l01565"></a>01565                                             __func__);
+<a name="l01566"></a>01566                                 <span class="keywordflow">if</span> (pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#cbe5c4062e140ee88f51ee916c0db0ad">request_config</a>) {
+<a name="l01567"></a>01567                                         <span class="comment">/* Complete STATUS PHASE */</span>
+<a name="l01568"></a>01568                                         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#b882b6b7c857100ed20600e94ea37760">is_in</a> = 1;
+<a name="l01569"></a>01569                                         pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#8f6963b3fb9ab83048c4c0697c90382a">ep0state</a> = EP0_IN_STATUS_PHASE;
+<a name="l01570"></a>01570                                 }
+<a name="l01571"></a>01571                                 <span class="keywordflow">break</span>;
+<a name="l01572"></a>01572 
+<a name="l01573"></a>01573                         <span class="keywordflow">case</span> EP0_IN_STATUS_PHASE:
+<a name="l01574"></a>01574                                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>,
+<a name="l01575"></a>01575                                             <span class="stringliteral">"%s ep0: EP0_IN_STATUS_PHASE\n"</span>,
+<a name="l01576"></a>01576                                             __func__);
+<a name="l01577"></a>01577                                 <span class="keywordflow">break</span>;
+<a name="l01578"></a>01578 
+<a name="l01579"></a>01579                         <span class="keywordflow">default</span>:
+<a name="l01580"></a>01580                                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#2bf62a567355d1ea38814714bd7b57ec">DBG_ANY</a>, <span class="stringliteral">"ep0: odd state %d\n"</span>,
+<a name="l01581"></a>01581                                             pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#8f6963b3fb9ab83048c4c0697c90382a">ep0state</a>);
+<a name="l01582"></a>01582                                 DWC_SPINUNLOCK_IRQRESTORE(pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5d450e4d06659ab2f3b18e5c816776e4">lock</a>, flags);
+<a name="l01583"></a>01583                                 <span class="keywordflow">return</span> -DWC_E_SHUTDOWN;
+<a name="l01584"></a>01584                         }
+<a name="l01585"></a>01585 
+<a name="l01586"></a>01586                         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#b40ce70422b6d105a855a8df4b33d45d">dma_addr</a> = dma_buf;
+<a name="l01587"></a>01587                         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#d0cda8ded2e5142d9a1c9c17efc5812f">start_xfer_buff</a> = buf;
+<a name="l01588"></a>01588                         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#97fa9bf5c31ba734d54f70e6fe6ae8eb">xfer_buff</a> = buf;
+<a name="l01589"></a>01589                         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">xfer_len</a> = buflen;
+<a name="l01590"></a>01590                         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#23d4871510b5bcb54fbf0674d8f122bd">xfer_count</a> = 0;
+<a name="l01591"></a>01591                         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#8c6340435beba0b8c025a4677602acab">sent_zlp</a> = 0;
+<a name="l01592"></a>01592                         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#5a218f200cff0491b735f43fed5176bf">total_len</a> = ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">xfer_len</a>;
+<a name="l01593"></a>01593 
+<a name="l01594"></a>01594                         <span class="keywordflow">if</span> (zero) {
+<a name="l01595"></a>01595                                 <span class="keywordflow">if</span> ((ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">xfer_len</a> %
+<a name="l01596"></a>01596                                      ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a> == 0)
+<a name="l01597"></a>01597                                     &amp;&amp; (ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">xfer_len</a> != 0)) {
+<a name="l01598"></a>01598                                         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#8c6340435beba0b8c025a4677602acab">sent_zlp</a> = 1;
+<a name="l01599"></a>01599                                 }
+<a name="l01600"></a>01600 
+<a name="l01601"></a>01601                         }
+<a name="l01602"></a>01602 
+<a name="l01603"></a>01603                         <a class="code" href="dwc__otg__cil_8c.html#ee4989b24826b2a6592535282853e556">dwc_otg_ep0_start_transfer</a>(<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd),
+<a name="l01604"></a>01604                                                    &amp;ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>);
+<a name="l01605"></a>01605                 }               <span class="comment">// non-ep0 endpoints</span>
+<a name="l01606"></a>01606                 <span class="keywordflow">else</span> {
+<a name="l01607"></a>01607 <span class="preprocessor">#ifdef DWC_UTE_CFI</span>
+<a name="l01608"></a>01608 <span class="preprocessor"></span>                        <span class="keywordflow">if</span> (ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.buff_mode != BM_STANDARD) {
+<a name="l01609"></a>01609                                 <span class="comment">/* store the request length */</span>
+<a name="l01610"></a>01610                                 ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.cfi_req_len = buflen;
+<a name="l01611"></a>01611                                 pcd-&gt;cfi-&gt;ops.build_descriptors(pcd-&gt;cfi, pcd,
+<a name="l01612"></a>01612                                                                 ep, req);
+<a name="l01613"></a>01613                 } <span class="keywordflow">else</span> {
+<a name="l01614"></a>01614 <span class="preprocessor">#endif</span>
+<a name="l01615"></a>01615 <span class="preprocessor"></span>                                max_transfer =
+<a name="l01616"></a>01616                                     <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#234391334e48cbd72710d08655c9ed16">pcd</a>)-&gt;core_params-&gt;
+<a name="l01617"></a>01617                                     max_transfer_size;
+<a name="l01618"></a>01618 
+<a name="l01619"></a>01619                         <span class="comment">/* Setup and start the Transfer */</span>
+<a name="l01620"></a>01620                         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#b40ce70422b6d105a855a8df4b33d45d">dma_addr</a> = dma_buf;
+<a name="l01621"></a>01621                         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#d0cda8ded2e5142d9a1c9c17efc5812f">start_xfer_buff</a> = buf;
+<a name="l01622"></a>01622                         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#97fa9bf5c31ba734d54f70e6fe6ae8eb">xfer_buff</a> = buf;
+<a name="l01623"></a>01623                         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">xfer_len</a> = 0;
+<a name="l01624"></a>01624                         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#23d4871510b5bcb54fbf0674d8f122bd">xfer_count</a> = 0;
+<a name="l01625"></a>01625                         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#8c6340435beba0b8c025a4677602acab">sent_zlp</a> = 0;
+<a name="l01626"></a>01626                         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#5a218f200cff0491b735f43fed5176bf">total_len</a> = buflen;
+<a name="l01627"></a>01627 
+<a name="l01628"></a>01628                         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#f60095e5ebedf7f98f3bfea77ce9a755">maxxfer</a> = max_transfer;
+<a name="l01629"></a>01629                         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;dma_desc_enable) {
+<a name="l01630"></a>01630                                         uint32_t out_max_xfer =
+<a name="l01631"></a>01631                                             <a class="code" href="dwc__otg__pcd_8h.html#6dad4d4462e9819753acfc601889faec">DDMA_MAX_TRANSFER_SIZE</a> -
+<a name="l01632"></a>01632                                             (<a class="code" href="dwc__otg__pcd_8h.html#6dad4d4462e9819753acfc601889faec">DDMA_MAX_TRANSFER_SIZE</a> % 4);
+<a name="l01633"></a>01633                                 <span class="keywordflow">if</span> (ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#b882b6b7c857100ed20600e94ea37760">is_in</a>) {
+<a name="l01634"></a>01634                                         <span class="keywordflow">if</span> (ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#f60095e5ebedf7f98f3bfea77ce9a755">maxxfer</a> &gt;
+<a name="l01635"></a>01635                                             <a class="code" href="dwc__otg__pcd_8h.html#6dad4d4462e9819753acfc601889faec">DDMA_MAX_TRANSFER_SIZE</a>) {
+<a name="l01636"></a>01636                                                 ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#f60095e5ebedf7f98f3bfea77ce9a755">maxxfer</a> =
+<a name="l01637"></a>01637                                                     <a class="code" href="dwc__otg__pcd_8h.html#6dad4d4462e9819753acfc601889faec">DDMA_MAX_TRANSFER_SIZE</a>;
+<a name="l01638"></a>01638                                         }
+<a name="l01639"></a>01639                                 } <span class="keywordflow">else</span> {
+<a name="l01640"></a>01640                                                 <span class="keywordflow">if</span> (ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#f60095e5ebedf7f98f3bfea77ce9a755">maxxfer</a> &gt;
+<a name="l01641"></a>01641                                                     out_max_xfer) {
+<a name="l01642"></a>01642                                                 ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#f60095e5ebedf7f98f3bfea77ce9a755">maxxfer</a> =
+<a name="l01643"></a>01643                                                     out_max_xfer;
+<a name="l01644"></a>01644                                         }
+<a name="l01645"></a>01645                                 }
+<a name="l01646"></a>01646                         }
+<a name="l01647"></a>01647                         <span class="keywordflow">if</span> (ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#f60095e5ebedf7f98f3bfea77ce9a755">maxxfer</a> &lt; ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#5a218f200cff0491b735f43fed5176bf">total_len</a>) {
+<a name="l01648"></a>01648                                 ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#f60095e5ebedf7f98f3bfea77ce9a755">maxxfer</a> -=
+<a name="l01649"></a>01649                                             (ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#f60095e5ebedf7f98f3bfea77ce9a755">maxxfer</a> %
+<a name="l01650"></a>01650                                              ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a>);
+<a name="l01651"></a>01651                         }
+<a name="l01652"></a>01652 
+<a name="l01653"></a>01653                         <span class="keywordflow">if</span> (zero) {
+<a name="l01654"></a>01654                                 <span class="keywordflow">if</span> ((ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#5a218f200cff0491b735f43fed5176bf">total_len</a> %
+<a name="l01655"></a>01655                                              ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a> == 0)
+<a name="l01656"></a>01656                                             &amp;&amp; (ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#5a218f200cff0491b735f43fed5176bf">total_len</a> != 0)) {
+<a name="l01657"></a>01657                                         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#8c6340435beba0b8c025a4677602acab">sent_zlp</a> = 1;
+<a name="l01658"></a>01658                                 }
+<a name="l01659"></a>01659                         }
+<a name="l01660"></a>01660 <span class="preprocessor">#ifdef DWC_UTE_CFI</span>
+<a name="l01661"></a>01661 <span class="preprocessor"></span>                        }
+<a name="l01662"></a>01662 <span class="preprocessor">#endif</span>
+<a name="l01663"></a>01663 <span class="preprocessor"></span>                        <a class="code" href="dwc__otg__cil_8c.html#1278f6d58a4a2bc780e90e0b6c9b9a68">dwc_otg_ep_start_transfer</a>(<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd),
+<a name="l01664"></a>01664                                                   &amp;ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>);
+<a name="l01665"></a>01665                 }
+<a name="l01666"></a>01666         }
+<a name="l01667"></a>01667 
+<a name="l01668"></a>01668         <span class="keywordflow">if</span> ((req != 0) || prevented) {
+<a name="l01669"></a>01669                 ++pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#3a0464b4ac677a7742e9b7c0c820414c">request_pending</a>;
+<a name="l01670"></a>01670                 DWC_CIRCLEQ_INSERT_TAIL(&amp;ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#71f4fa571dfdc96f62fa4869e6add300">queue</a>, req, queue_entry);
+<a name="l01671"></a>01671                 <span class="keywordflow">if</span> (ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#b882b6b7c857100ed20600e94ea37760">is_in</a> &amp;&amp; ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#cce0e089118d8bf7c6278c21ded70d5a">stopped</a>
+<a name="l01672"></a>01672                     &amp;&amp; !(<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;dma_enable)) {
+<a name="l01674"></a>01674                         <a class="code" href="uniondiepint__data.html">diepmsk_data_t</a> diepmsk = {.d32 = 0 };
+<a name="l01675"></a>01675                         diepmsk.<a class="code" href="uniondiepint__data.html#48d2a745e0ec983a47b35b0428b0437d">b</a>.<a class="code" href="uniondiepint__data.html#7c9961f17328bbc25ca39e7ec1891e16">intktxfemp</a> = 1;
+<a name="l01676"></a>01676                         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;multiproc_int_enable) {
+<a name="l01677"></a>01677                                 dwc_modify_reg32(&amp;<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;dev_if-&gt;
+<a name="l01678"></a>01678                                                  dev_global_regs-&gt;
+<a name="l01679"></a>01679                                                  diepeachintmsk[ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a>],
+<a name="l01680"></a>01680                                                  0, diepmsk.<a class="code" href="uniondiepint__data.html#7d2c24507663bf96c280c57fbf544ef7">d32</a>);
+<a name="l01681"></a>01681                         } <span class="keywordflow">else</span> {
+<a name="l01682"></a>01682                                 dwc_modify_reg32(&amp;<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;dev_if-&gt;
+<a name="l01683"></a>01683                                                  dev_global_regs-&gt;diepmsk, 0,
+<a name="l01684"></a>01684                                                  diepmsk.<a class="code" href="uniondiepint__data.html#7d2c24507663bf96c280c57fbf544ef7">d32</a>);
+<a name="l01685"></a>01685                         }
+<a name="l01686"></a>01686 
+<a name="l01687"></a>01687                 }
+<a name="l01688"></a>01688         }
+<a name="l01689"></a>01689 
+<a name="l01690"></a>01690         DWC_SPINUNLOCK_IRQRESTORE(pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5d450e4d06659ab2f3b18e5c816776e4">lock</a>, flags);
+<a name="l01691"></a>01691 
+<a name="l01692"></a>01692         <span class="keywordflow">return</span> 0;
+<a name="l01693"></a>01693 }
+<a name="l01694"></a><a class="code" href="dwc__otg__pcd__if_8h.html#aa7546ce68d6fda67bb4cda0f69eedf3">01694</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__pcd_8c.html#aa7546ce68d6fda67bb4cda0f69eedf3">dwc_otg_pcd_ep_dequeue</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd, <span class="keywordtype">void</span> *ep_handle,
+<a name="l01695"></a>01695                            <span class="keywordtype">void</span> *req_handle)
+<a name="l01696"></a>01696 {
+<a name="l01697"></a>01697         uint64_t flags;
+<a name="l01698"></a>01698         <a class="code" href="structdwc__otg__pcd__request.html">dwc_otg_pcd_request_t</a> *req;
+<a name="l01699"></a>01699         <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *ep;
+<a name="l01700"></a>01700 
+<a name="l01701"></a>01701         ep = <a class="code" href="dwc__otg__pcd_8c.html#4b46c226fa34cd7fc4ceec2c5e7f8ebe">get_ep_from_handle</a>(pcd, ep_handle);
+<a name="l01702"></a>01702         <span class="keywordflow">if</span> (!ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#86e27843c439dd0b1d12d9bf2dc6516f">desc</a> &amp;&amp; ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a> != 0) {
+<a name="l01703"></a>01703                 DWC_WARN(<span class="stringliteral">"bad argument\n"</span>);
+<a name="l01704"></a>01704                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l01705"></a>01705         }
+<a name="l01706"></a>01706 
+<a name="l01707"></a>01707         DWC_SPINLOCK_IRQSAVE(pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5d450e4d06659ab2f3b18e5c816776e4">lock</a>, &amp;flags);
+<a name="l01708"></a>01708 
+<a name="l01709"></a>01709         <span class="comment">/* make sure it's actually queued on this endpoint */</span>
+<a name="l01710"></a>01710         DWC_CIRCLEQ_FOREACH(req, &amp;ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#71f4fa571dfdc96f62fa4869e6add300">queue</a>, queue_entry) {
+<a name="l01711"></a>01711                 <span class="keywordflow">if</span> (req-&gt;<a class="code" href="structdwc__otg__pcd__request.html#e0d93b64365968aa0dcf58535aecf40c">priv</a> == (<span class="keywordtype">void</span> *)req_handle) {
+<a name="l01712"></a>01712                         <span class="keywordflow">break</span>;
+<a name="l01713"></a>01713                 }
+<a name="l01714"></a>01714         }
+<a name="l01715"></a>01715 
+<a name="l01716"></a>01716         <span class="keywordflow">if</span> (req-&gt;<a class="code" href="structdwc__otg__pcd__request.html#e0d93b64365968aa0dcf58535aecf40c">priv</a> != (<span class="keywordtype">void</span> *)req_handle) {
+<a name="l01717"></a>01717                 DWC_SPINUNLOCK_IRQRESTORE(pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5d450e4d06659ab2f3b18e5c816776e4">lock</a>, flags);
+<a name="l01718"></a>01718                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l01719"></a>01719         }
+<a name="l01720"></a>01720 
+<a name="l01721"></a>01721         <span class="keywordflow">if</span> (!DWC_CIRCLEQ_EMPTY_ENTRY(req, queue_entry)) {
+<a name="l01722"></a>01722                 <a class="code" href="dwc__otg__pcd_8c.html#5c9b20abc81e0f860a8f23c90b10b59e">dwc_otg_request_done</a>(ep, req, -DWC_E_RESTART);
+<a name="l01723"></a>01723         } <span class="keywordflow">else</span> {
+<a name="l01724"></a>01724                 req = 0;
+<a name="l01725"></a>01725         }
+<a name="l01726"></a>01726 
+<a name="l01727"></a>01727         DWC_SPINUNLOCK_IRQRESTORE(pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5d450e4d06659ab2f3b18e5c816776e4">lock</a>, flags);
+<a name="l01728"></a>01728 
+<a name="l01729"></a>01729         <span class="keywordflow">return</span> req ? 0 : -DWC_E_SHUTDOWN;
+<a name="l01730"></a>01730 
+<a name="l01731"></a>01731 }
+<a name="l01732"></a>01732 
+<a name="l01733"></a><a class="code" href="dwc__otg__pcd__if_8h.html#f7d01b4772f08c6a08f4a22300a7b43b">01733</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__pcd_8c.html#f7d01b4772f08c6a08f4a22300a7b43b">dwc_otg_pcd_ep_halt</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd, <span class="keywordtype">void</span> *ep_handle, <span class="keywordtype">int</span> value)
+<a name="l01734"></a>01734 {
+<a name="l01735"></a>01735         <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *ep;
+<a name="l01736"></a>01736         uint64_t flags;
+<a name="l01737"></a>01737         <span class="keywordtype">int</span> retval = 0;
+<a name="l01738"></a>01738 
+<a name="l01739"></a>01739         ep = <a class="code" href="dwc__otg__pcd_8c.html#4b46c226fa34cd7fc4ceec2c5e7f8ebe">get_ep_from_handle</a>(pcd, ep_handle);
+<a name="l01740"></a>01740 
+<a name="l01741"></a>01741         <span class="keywordflow">if</span> ((!ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#86e27843c439dd0b1d12d9bf2dc6516f">desc</a> &amp;&amp; ep != &amp;pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a>) ||
+<a name="l01742"></a>01742             (ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#86e27843c439dd0b1d12d9bf2dc6516f">desc</a> &amp;&amp; (ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#86e27843c439dd0b1d12d9bf2dc6516f">desc</a>-&gt;bmAttributes == UE_ISOCHRONOUS))) {
+<a name="l01743"></a>01743                 DWC_WARN(<span class="stringliteral">"%s, bad ep\n"</span>, __func__);
+<a name="l01744"></a>01744                 <span class="keywordflow">return</span> -DWC_E_INVALID;
+<a name="l01745"></a>01745         }
+<a name="l01746"></a>01746 
+<a name="l01747"></a>01747         DWC_SPINLOCK_IRQSAVE(pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5d450e4d06659ab2f3b18e5c816776e4">lock</a>, &amp;flags);
+<a name="l01748"></a>01748         <span class="keywordflow">if</span> (!DWC_CIRCLEQ_EMPTY(&amp;ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#71f4fa571dfdc96f62fa4869e6add300">queue</a>)) {
+<a name="l01749"></a>01749                 DWC_WARN(<span class="stringliteral">"%d %s XFer In process\n"</span>, ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a>,
+<a name="l01750"></a>01750                          ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#b882b6b7c857100ed20600e94ea37760">is_in</a> ? <span class="stringliteral">"IN"</span> : <span class="stringliteral">"OUT"</span>);
+<a name="l01751"></a>01751                 retval = -DWC_E_AGAIN;
+<a name="l01752"></a>01752         } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (value == 0) {
+<a name="l01753"></a>01753                 <a class="code" href="dwc__otg__cil_8c.html#a5f77318fb1c589406927a606844007f">dwc_otg_ep_clear_stall</a>(<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd), &amp;ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>);
+<a name="l01754"></a>01754         } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (value == 1) {
+<a name="l01755"></a>01755                 <span class="keywordflow">if</span> (ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#b882b6b7c857100ed20600e94ea37760">is_in</a> == 1 &amp;&amp; <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;dma_desc_enable) {
+<a name="l01756"></a>01756                         <a class="code" href="uniondtxfsts__data.html">dtxfsts_data_t</a> txstatus;
+<a name="l01757"></a>01757                         <a class="code" href="unionfifosize__data.html">fifosize_data_t</a> txfifosize;
+<a name="l01758"></a>01758 
+<a name="l01759"></a>01759                         txfifosize.<a class="code" href="unionfifosize__data.html#937e01b91f0a60a5aa9f6a4eaf6ce661">d32</a> =
+<a name="l01760"></a>01760                             dwc_read_reg32(&amp;<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;core_global_regs-&gt;
+<a name="l01761"></a>01761                                            dptxfsiz_dieptxf[ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.
+<a name="l01762"></a>01762                                                             tx_fifo_num]);
+<a name="l01763"></a>01763                         txstatus.<a class="code" href="uniondtxfsts__data.html#684b8a9ccf83a5807e9bb3491c662c39">d32</a> =
+<a name="l01764"></a>01764                             dwc_read_reg32(&amp;<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;dev_if-&gt;
+<a name="l01765"></a>01765                                            in_ep_regs[ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a>]-&gt;dtxfsts);
+<a name="l01766"></a>01766 
+<a name="l01767"></a>01767                         <span class="keywordflow">if</span> (txstatus.<a class="code" href="uniondtxfsts__data.html#168f673549aad11d0d9fdc06ee6c5480">b</a>.<a class="code" href="uniondtxfsts__data.html#83db0e2dbe071694f549a383b7037b3b">txfspcavail</a> &lt; txfifosize.<a class="code" href="unionfifosize__data.html#4f0c71e88cc54c4efa4cd4ff43334c51">b</a>.<a class="code" href="unionfifosize__data.html#48c08d73da4d2d16d4320b93beb5ba8b">depth</a>) {
+<a name="l01768"></a>01768                                 DWC_WARN(<span class="stringliteral">"%s() Data In Tx Fifo\n"</span>, __func__);
+<a name="l01769"></a>01769                                 retval = -DWC_E_AGAIN;
+<a name="l01770"></a>01770                         } <span class="keywordflow">else</span> {
+<a name="l01771"></a>01771                                 <span class="keywordflow">if</span> (ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a> == 0) {
+<a name="l01772"></a>01772                                         pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#8f6963b3fb9ab83048c4c0697c90382a">ep0state</a> = EP0_STALL;
+<a name="l01773"></a>01773                                 }
+<a name="l01774"></a>01774 
+<a name="l01775"></a>01775                                 ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#cce0e089118d8bf7c6278c21ded70d5a">stopped</a> = 1;
+<a name="l01776"></a>01776                                 <a class="code" href="dwc__otg__cil_8c.html#5edca13178261136209ed51360c850b4">dwc_otg_ep_set_stall</a>(<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd),
+<a name="l01777"></a>01777                                                      &amp;ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>);
+<a name="l01778"></a>01778                         }
+<a name="l01779"></a>01779                 } <span class="keywordflow">else</span> {
+<a name="l01780"></a>01780                         <span class="keywordflow">if</span> (ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a> == 0) {
+<a name="l01781"></a>01781                                 pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#8f6963b3fb9ab83048c4c0697c90382a">ep0state</a> = EP0_STALL;
+<a name="l01782"></a>01782                         }
+<a name="l01783"></a>01783 
+<a name="l01784"></a>01784                         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#cce0e089118d8bf7c6278c21ded70d5a">stopped</a> = 1;
+<a name="l01785"></a>01785                         <a class="code" href="dwc__otg__cil_8c.html#5edca13178261136209ed51360c850b4">dwc_otg_ep_set_stall</a>(<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd), &amp;ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>);
+<a name="l01786"></a>01786                 }
+<a name="l01787"></a>01787         } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (value == 2) {
+<a name="l01788"></a>01788                 ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#0d30d306e370810fc819f6ef735c7e67">stall_clear_flag</a> = 0;
+<a name="l01789"></a>01789         } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (value == 3) {
+<a name="l01790"></a>01790                 ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#0d30d306e370810fc819f6ef735c7e67">stall_clear_flag</a> = 1;
+<a name="l01791"></a>01791         }
+<a name="l01792"></a>01792 
+<a name="l01793"></a>01793         DWC_SPINUNLOCK_IRQRESTORE(pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5d450e4d06659ab2f3b18e5c816776e4">lock</a>, flags);
+<a name="l01794"></a>01794 
+<a name="l01795"></a>01795         <span class="keywordflow">return</span> retval;
+<a name="l01796"></a>01796 }
+<a name="l01797"></a>01797 
+<a name="l01801"></a><a class="code" href="dwc__otg__pcd_8c.html#89fb8b7a8276390becc3370903af55e2">01801</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd_8c.html#89fb8b7a8276390becc3370903af55e2">dwc_otg_pcd_rem_wkup_from_suspend</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd, <span class="keywordtype">int</span> set)
+<a name="l01802"></a>01802 {
+<a name="l01803"></a>01803         <a class="code" href="uniondctl__data.html">dctl_data_t</a> dctl = { 0 };
+<a name="l01804"></a>01804         <a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if = <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd);
+<a name="l01805"></a>01805         <a class="code" href="uniondsts__data.html">dsts_data_t</a> dsts;
+<a name="l01806"></a>01806 
+<a name="l01807"></a>01807         dsts.<a class="code" href="uniondsts__data.html#0f126daef735b142b06dbc4cdbe13814">d32</a> = dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#1ed00edd20ce5db7d07666804101ec05">dsts</a>);
+<a name="l01808"></a>01808         <span class="keywordflow">if</span> (!dsts.<a class="code" href="uniondsts__data.html#4066fcedb7ac9a88e47aa1b2df0e89ee">b</a>.<a class="code" href="uniondsts__data.html#4c7cd8ee3877701268846b0b02ac3d97">suspsts</a>) {
+<a name="l01809"></a>01809                 DWC_WARN(<span class="stringliteral">"Remote wakeup while is not in suspend state\n"</span>);
+<a name="l01810"></a>01810         }
+<a name="l01811"></a>01811         <span class="comment">/* Check if DEVICE_REMOTE_WAKEUP feature enabled */</span>
+<a name="l01812"></a>01812         <span class="keywordflow">if</span> (pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#9d8e6d7f0ad10d580d467024e258f6f5">remote_wakeup_enable</a>) {
+<a name="l01813"></a>01813                 <span class="keywordflow">if</span> (set) {
+<a name="l01814"></a>01814                         dctl.<a class="code" href="uniondctl__data.html#a3abfa6d609d9864f1f65712b409d4d3">b</a>.<a class="code" href="uniondctl__data.html#dcae5af28dc159cd7ba85a9a2b8be51a">rmtwkupsig</a> = 1;
+<a name="l01815"></a>01815                         dwc_modify_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;
+<a name="l01816"></a>01816                                          dctl, 0, dctl.<a class="code" href="uniondctl__data.html#f49aadfd7ad95b570115b3c245b1729e">d32</a>);
+<a name="l01817"></a>01817                         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"Set Remote Wakeup\n"</span>);
+<a name="l01818"></a>01818                         dwc_mdelay(2);
+<a name="l01819"></a>01819                         dwc_modify_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;
+<a name="l01820"></a>01820                                          dctl, dctl.<a class="code" href="uniondctl__data.html#f49aadfd7ad95b570115b3c245b1729e">d32</a>, 0);
+<a name="l01821"></a>01821                         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"Clear Remote Wakeup\n"</span>);
+<a name="l01822"></a>01822                 }
+<a name="l01823"></a>01823         } <span class="keywordflow">else</span> {
+<a name="l01824"></a>01824                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"Remote Wakeup is disabled\n"</span>);
+<a name="l01825"></a>01825         }
+<a name="l01826"></a>01826 }
+<a name="l01827"></a>01827 
+<a name="l01828"></a>01828 <span class="preprocessor">#ifdef CONFIG_USB_DWC_OTG_LPM</span>
+<a name="l01829"></a>01829 <span class="preprocessor"></span>
+<a name="l01832"></a>01832 <span class="keywordtype">void</span> dwc_otg_pcd_rem_wkup_from_sleep(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd, <span class="keywordtype">int</span> set)
+<a name="l01833"></a>01833 {
+<a name="l01834"></a>01834         <a class="code" href="unionglpmctl__data.html">glpmcfg_data_t</a> lpmcfg;
+<a name="l01835"></a>01835         <a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if = <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd);
+<a name="l01836"></a>01836 
+<a name="l01837"></a>01837         lpmcfg.<a class="code" href="unionglpmctl__data.html#cd41461734ff898209bfb64057ef2eb8">d32</a> = dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#843cfb38ba366a9a46ad07ed11eb8396">glpmcfg</a>);
+<a name="l01838"></a>01838 
+<a name="l01839"></a>01839         <span class="comment">/* Check if we are in L1 state */</span>
+<a name="l01840"></a>01840         <span class="keywordflow">if</span> (!lpmcfg.<a class="code" href="unionglpmctl__data.html#bd3cc34c338226ff1cd89448f7590ff1">b</a>.<a class="code" href="unionglpmctl__data.html#241ff25a215f16ac29b3bb6d9f4943ed">prt_sleep_sts</a>) {
+<a name="l01841"></a>01841                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"Device is not in sleep state\n"</span>);
+<a name="l01842"></a>01842                 <span class="keywordflow">return</span>;
+<a name="l01843"></a>01843         }
+<a name="l01844"></a>01844 
+<a name="l01845"></a>01845         <span class="comment">/* Check if host allows remote wakeup */</span>
+<a name="l01846"></a>01846         <span class="keywordflow">if</span> (!lpmcfg.<a class="code" href="unionglpmctl__data.html#bd3cc34c338226ff1cd89448f7590ff1">b</a>.<a class="code" href="unionglpmctl__data.html#60a9c2e233e3ee15a80ae80b27d09f8b">rem_wkup_en</a>) {
+<a name="l01847"></a>01847                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"Host does not allow remote wakeup\n"</span>);
+<a name="l01848"></a>01848                 <span class="keywordflow">return</span>;
+<a name="l01849"></a>01849         }
+<a name="l01850"></a>01850 
+<a name="l01851"></a>01851         <span class="comment">/* Check if Resume OK */</span>
+<a name="l01852"></a>01852         <span class="keywordflow">if</span> (!lpmcfg.<a class="code" href="unionglpmctl__data.html#bd3cc34c338226ff1cd89448f7590ff1">b</a>.<a class="code" href="unionglpmctl__data.html#3b87473445c87d173f350828a60cacd8">sleep_state_resumeok</a>) {
+<a name="l01853"></a>01853                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"Sleep state resume is not OK\n"</span>);
+<a name="l01854"></a>01854                 <span class="keywordflow">return</span>;
+<a name="l01855"></a>01855         }
+<a name="l01856"></a>01856 
+<a name="l01857"></a>01857         lpmcfg.<a class="code" href="unionglpmctl__data.html#cd41461734ff898209bfb64057ef2eb8">d32</a> = dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#843cfb38ba366a9a46ad07ed11eb8396">glpmcfg</a>);
+<a name="l01858"></a>01858         lpmcfg.<a class="code" href="unionglpmctl__data.html#bd3cc34c338226ff1cd89448f7590ff1">b</a>.<a class="code" href="unionglpmctl__data.html#63e912a05b8d29872b92263ca616fec8">en_utmi_sleep</a> = 0;
+<a name="l01859"></a>01859         lpmcfg.<a class="code" href="unionglpmctl__data.html#bd3cc34c338226ff1cd89448f7590ff1">b</a>.<a class="code" href="unionglpmctl__data.html#e2ceea4bfe468c7b3c800235d7ffd5d2">hird_thres</a> &amp;= (~(1 &lt;&lt; 4));
+<a name="l01860"></a>01860         dwc_write_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#843cfb38ba366a9a46ad07ed11eb8396">glpmcfg</a>, lpmcfg.<a class="code" href="unionglpmctl__data.html#cd41461734ff898209bfb64057ef2eb8">d32</a>);
+<a name="l01861"></a>01861 
+<a name="l01862"></a>01862         <span class="keywordflow">if</span> (set) {
+<a name="l01863"></a>01863                 <a class="code" href="uniondctl__data.html">dctl_data_t</a> dctl = {.d32 = 0 };
+<a name="l01864"></a>01864                 dctl.<a class="code" href="uniondctl__data.html#a3abfa6d609d9864f1f65712b409d4d3">b</a>.<a class="code" href="uniondctl__data.html#dcae5af28dc159cd7ba85a9a2b8be51a">rmtwkupsig</a> = 1;
+<a name="l01865"></a>01865                 <span class="comment">/* Set RmtWkUpSig bit to start remote wakup signaling.</span>
+<a name="l01866"></a>01866 <span class="comment">                 * Hardware will automatically clear this bit.</span>
+<a name="l01867"></a>01867 <span class="comment">                 */</span>
+<a name="l01868"></a>01868                 dwc_modify_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#3779c2fc508920a831a59e696a8fa785">dctl</a>,
+<a name="l01869"></a>01869                                  0, dctl.<a class="code" href="uniondctl__data.html#f49aadfd7ad95b570115b3c245b1729e">d32</a>);
+<a name="l01870"></a>01870                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"Set Remote Wakeup\n"</span>);
+<a name="l01871"></a>01871         }
+<a name="l01872"></a>01872 
+<a name="l01873"></a>01873 }
+<a name="l01874"></a>01874 <span class="preprocessor">#endif</span>
+<a name="l01875"></a>01875 <span class="preprocessor"></span>
+<a name="l01879"></a><a class="code" href="dwc__otg__pcd__if_8h.html#24cbdd57c573d864a09a30ae3ecda89a">01879</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd_8c.html#24cbdd57c573d864a09a30ae3ecda89a">dwc_otg_pcd_remote_wakeup</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd, <span class="keywordtype">int</span> set)
+<a name="l01880"></a>01880 {
+<a name="l01881"></a>01881         <a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if = <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd);
+<a name="l01882"></a>01882         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#e83fb22890bc54c6b06cedb751430e77">dwc_otg_is_device_mode</a>(core_if)) {
+<a name="l01883"></a>01883 <span class="preprocessor">#ifdef CONFIG_USB_DWC_OTG_LPM</span>
+<a name="l01884"></a>01884 <span class="preprocessor"></span>                <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#2b0701d814069ec69897e08374366c7b">lx_state</a> == <a class="code" href="dwc__otg__cil_8h.html#8442e49b7c783099ac17bda4f8b3bc3cf5b112742a8103f3489107ad26c0ff58">DWC_OTG_L1</a>) {
+<a name="l01885"></a>01885                         dwc_otg_pcd_rem_wkup_from_sleep(pcd, set);
+<a name="l01886"></a>01886                 } <span class="keywordflow">else</span> {
+<a name="l01887"></a>01887 <span class="preprocessor">#endif</span>
+<a name="l01888"></a>01888 <span class="preprocessor"></span>                        <a class="code" href="dwc__otg__pcd_8c.html#89fb8b7a8276390becc3370903af55e2">dwc_otg_pcd_rem_wkup_from_suspend</a>(pcd, set);
+<a name="l01889"></a>01889 <span class="preprocessor">#ifdef CONFIG_USB_DWC_OTG_LPM</span>
+<a name="l01890"></a>01890 <span class="preprocessor"></span>                }
+<a name="l01891"></a>01891 <span class="preprocessor">#endif</span>
+<a name="l01892"></a>01892 <span class="preprocessor"></span>        }
+<a name="l01893"></a>01893         <span class="keywordflow">return</span>;
+<a name="l01894"></a>01894 }
+<a name="l01895"></a>01895 
+<a name="l01896"></a><a class="code" href="dwc__otg__pcd__if_8h.html#7e0d7b09dc6528626f4643deb296d68d">01896</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__pcd_8c.html#7e0d7b09dc6528626f4643deb296d68d">dwc_otg_pcd_wakeup</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd)
+<a name="l01897"></a>01897 {
+<a name="l01898"></a>01898         <a class="code" href="uniondsts__data.html">dsts_data_t</a> dsts;
+<a name="l01899"></a>01899         <a class="code" href="uniongotgctl__data.html">gotgctl_data_t</a> gotgctl;
+<a name="l01900"></a>01900         uint64_t flags;
+<a name="l01901"></a>01901 
+<a name="l01902"></a>01902         DWC_SPINLOCK_IRQSAVE(pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5d450e4d06659ab2f3b18e5c816776e4">lock</a>, &amp;flags);
+<a name="l01903"></a>01903 
+<a name="l01904"></a>01904         <span class="comment">/*</span>
+<a name="l01905"></a>01905 <span class="comment">         * This function starts the Protocol if no session is in progress. If</span>
+<a name="l01906"></a>01906 <span class="comment">         * a session is already in progress, but the device is suspended,</span>
+<a name="l01907"></a>01907 <span class="comment">         * remote wakeup signaling is started.</span>
+<a name="l01908"></a>01908 <span class="comment">         */</span>
+<a name="l01909"></a>01909 
+<a name="l01910"></a>01910         <span class="comment">/* Check if valid session */</span>
+<a name="l01911"></a>01911         gotgctl.<a class="code" href="uniongotgctl__data.html#ebb591ab40ff41f0e06f03a795647d33">d32</a> =
+<a name="l01912"></a>01912             dwc_read_reg32(&amp;(<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;core_global_regs-&gt;gotgctl));
+<a name="l01913"></a>01913         <span class="keywordflow">if</span> (gotgctl.<a class="code" href="uniongotgctl__data.html#212c81366266e906a188f4dbfadb6dd3">b</a>.<a class="code" href="uniongotgctl__data.html#69931c3759421d5eb6f91d4c9da4dddd">bsesvld</a>) {
+<a name="l01914"></a>01914                 <span class="comment">/* Check if suspend state */</span>
+<a name="l01915"></a>01915                 dsts.<a class="code" href="uniondsts__data.html#0f126daef735b142b06dbc4cdbe13814">d32</a> =
+<a name="l01916"></a>01916                     dwc_read_reg32(&amp;
+<a name="l01917"></a>01917                                    (<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;dev_if-&gt;dev_global_regs-&gt;
+<a name="l01918"></a>01918                                     dsts));
+<a name="l01919"></a>01919                 <span class="keywordflow">if</span> (dsts.<a class="code" href="uniondsts__data.html#4066fcedb7ac9a88e47aa1b2df0e89ee">b</a>.<a class="code" href="uniondsts__data.html#4c7cd8ee3877701268846b0b02ac3d97">suspsts</a>) {
+<a name="l01920"></a>01920                         <a class="code" href="dwc__otg__pcd_8c.html#24cbdd57c573d864a09a30ae3ecda89a">dwc_otg_pcd_remote_wakeup</a>(pcd, 1);
+<a name="l01921"></a>01921                 }
+<a name="l01922"></a>01922         } <span class="keywordflow">else</span> {
+<a name="l01923"></a>01923                 <a class="code" href="dwc__otg__pcd_8c.html#4be3e59162a42a79705e3ea8dc5008fa">dwc_otg_pcd_initiate_srp</a>(pcd);
+<a name="l01924"></a>01924         }
+<a name="l01925"></a>01925 
+<a name="l01926"></a>01926         DWC_SPINUNLOCK_IRQRESTORE(pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5d450e4d06659ab2f3b18e5c816776e4">lock</a>, flags);
+<a name="l01927"></a>01927         <span class="keywordflow">return</span> 0;
+<a name="l01928"></a>01928 
+<a name="l01929"></a>01929 }
+<a name="l01930"></a>01930 
+<a name="l01937"></a><a class="code" href="dwc__otg__pcd_8c.html#517f9cf3e74ebb0b9e00ea1defc56697">01937</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd_8c.html#517f9cf3e74ebb0b9e00ea1defc56697">dwc_otg_pcd_start_srp_timer</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd)
+<a name="l01938"></a>01938 {
+<a name="l01939"></a>01939         <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;srp_timer_started = 1;
+<a name="l01940"></a>01940         DWC_TIMER_SCHEDULE(pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#466fb6ae524fc970f164701db2e70246">srp_timer</a>, 6000 <span class="comment">/* 6 secs */</span> );
+<a name="l01941"></a>01941 }
+<a name="l01942"></a>01942 
+<a name="l01943"></a><a class="code" href="dwc__otg__pcd__if_8h.html#4be3e59162a42a79705e3ea8dc5008fa">01943</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd_8c.html#4be3e59162a42a79705e3ea8dc5008fa">dwc_otg_pcd_initiate_srp</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd)
+<a name="l01944"></a>01944 {
+<a name="l01945"></a>01945         uint32_t *addr =
+<a name="l01946"></a>01946             (uint32_t *) &amp; (<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;core_global_regs-&gt;gotgctl);
+<a name="l01947"></a>01947         <a class="code" href="uniongotgctl__data.html">gotgctl_data_t</a> mem;
+<a name="l01948"></a>01948         <a class="code" href="uniongotgctl__data.html">gotgctl_data_t</a> val;
+<a name="l01949"></a>01949 
+<a name="l01950"></a>01950         val.<a class="code" href="uniongotgctl__data.html#ebb591ab40ff41f0e06f03a795647d33">d32</a> = dwc_read_reg32(addr);
+<a name="l01951"></a>01951         <span class="keywordflow">if</span> (val.<a class="code" href="uniongotgctl__data.html#212c81366266e906a188f4dbfadb6dd3">b</a>.<a class="code" href="uniongotgctl__data.html#c6b0b35d4366f74cf6fe268eda781f06">sesreq</a>) {
+<a name="l01952"></a>01952                 DWC_ERROR(<span class="stringliteral">"Session Request Already active!\n"</span>);
+<a name="l01953"></a>01953                 <span class="keywordflow">return</span>;
+<a name="l01954"></a>01954         }
+<a name="l01955"></a>01955 
+<a name="l01956"></a>01956         DWC_INFO(<span class="stringliteral">"Session Request Initated\n"</span>); <span class="comment">//NOTICE</span>
+<a name="l01957"></a>01957         mem.<a class="code" href="uniongotgctl__data.html#ebb591ab40ff41f0e06f03a795647d33">d32</a> = dwc_read_reg32(addr);
+<a name="l01958"></a>01958         mem.<a class="code" href="uniongotgctl__data.html#212c81366266e906a188f4dbfadb6dd3">b</a>.<a class="code" href="uniongotgctl__data.html#c6b0b35d4366f74cf6fe268eda781f06">sesreq</a> = 1;
+<a name="l01959"></a>01959         dwc_write_reg32(addr, mem.<a class="code" href="uniongotgctl__data.html#ebb591ab40ff41f0e06f03a795647d33">d32</a>);
+<a name="l01960"></a>01960 
+<a name="l01961"></a>01961         <span class="comment">/* Start the SRP timer */</span>
+<a name="l01962"></a>01962         <a class="code" href="dwc__otg__pcd_8c.html#517f9cf3e74ebb0b9e00ea1defc56697">dwc_otg_pcd_start_srp_timer</a>(pcd);
+<a name="l01963"></a>01963         <span class="keywordflow">return</span>;
+<a name="l01964"></a>01964 }
+<a name="l01965"></a>01965 
+<a name="l01966"></a><a class="code" href="dwc__otg__pcd__if_8h.html#04876b716043a853b379d72ff3a215e5">01966</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__pcd_8c.html#04876b716043a853b379d72ff3a215e5">dwc_otg_pcd_get_frame_number</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd)
+<a name="l01967"></a>01967 {
+<a name="l01968"></a>01968         <span class="keywordflow">return</span> <a class="code" href="dwc__otg__cil_8c.html#78f20f3acf6245b189abde83d9ce78f2">dwc_otg_get_frame_number</a>(<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd));
+<a name="l01969"></a>01969 }
+<a name="l01970"></a>01970 
+<a name="l01971"></a><a class="code" href="dwc__otg__pcd__if_8h.html#676021c9b801674669cdf2d1e68d5b8c">01971</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__pcd_8c.html#676021c9b801674669cdf2d1e68d5b8c">dwc_otg_pcd_is_lpm_enabled</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd)
+<a name="l01972"></a>01972 {
+<a name="l01973"></a>01973         <span class="keywordflow">return</span> <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;core_params-&gt;lpm_enable;
+<a name="l01974"></a>01974 }
+<a name="l01975"></a>01975 
+<a name="l01976"></a><a class="code" href="dwc__otg__pcd__if_8h.html#777a6a4e250add9ba5f5f5d63d854031">01976</a> uint32_t <a class="code" href="dwc__otg__pcd_8c.html#777a6a4e250add9ba5f5f5d63d854031">get_b_hnp_enable</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd)
+<a name="l01977"></a>01977 {
+<a name="l01978"></a>01978         <span class="keywordflow">return</span> pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#e09fc5322ac0d7deec2772984c10ae90">b_hnp_enable</a>;
+<a name="l01979"></a>01979 }
+<a name="l01980"></a>01980 
+<a name="l01981"></a><a class="code" href="dwc__otg__pcd__if_8h.html#69d0bb469e15cb46f00c17398f76df99">01981</a> uint32_t <a class="code" href="dwc__otg__pcd_8c.html#69d0bb469e15cb46f00c17398f76df99">get_a_hnp_support</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd)
+<a name="l01982"></a>01982 {
+<a name="l01983"></a>01983         <span class="keywordflow">return</span> pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#e8008719644bdc23040f1a1545b7117f">a_hnp_support</a>;
+<a name="l01984"></a>01984 }
+<a name="l01985"></a>01985 
+<a name="l01986"></a><a class="code" href="dwc__otg__pcd__if_8h.html#842709a4980bc78d49726fa880922dda">01986</a> uint32_t <a class="code" href="dwc__otg__pcd_8c.html#842709a4980bc78d49726fa880922dda">get_a_alt_hnp_support</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd)
+<a name="l01987"></a>01987 {
+<a name="l01988"></a>01988         <span class="keywordflow">return</span> pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#49f2d2b04a4c07a8d53643f7681b5405">a_alt_hnp_support</a>;
+<a name="l01989"></a>01989 }
+<a name="l01990"></a>01990 
+<a name="l01991"></a><a class="code" href="dwc__otg__pcd__if_8h.html#0107dd39d549d3e10fd388337e03aeb9">01991</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__pcd_8c.html#0107dd39d549d3e10fd388337e03aeb9">dwc_otg_pcd_get_rmwkup_enable</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd)
+<a name="l01992"></a>01992 {
+<a name="l01993"></a>01993         <span class="keywordflow">return</span> pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#9d8e6d7f0ad10d580d467024e258f6f5">remote_wakeup_enable</a>;
+<a name="l01994"></a>01994 }
+<a name="l01995"></a>01995 
+<a name="l01996"></a>01996 <span class="preprocessor">#endif                          </span><span class="comment">/* DWC_HOST_ONLY */</span>
+</pre></div><hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd_8c.html b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd_8c.html
new file mode 100644
index 000000000000..bbd10a6a8033
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd_8c.html
@@ -0,0 +1,1343 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd.c File Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
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+<div class="tabs">
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+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<h1>dwc_otg_pcd.c File Reference</h1>This file implements PCD Core. <a href="#_details">More...</a>
+<p>
+<code>#include &quot;<a class="el" href="dwc__otg__pcd_8h-source.html">dwc_otg_pcd.h</a>&quot;</code><br>
+
+<p>
+<a href="dwc__otg__pcd_8c-source.html">Go to the source code of this file.</a><table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Functions</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="4b46c226fa34cd7fc4ceec2c5e7f8ebe"></a><!-- doxytag: member="dwc_otg_pcd.c::get_ep_from_handle" ref="4b46c226fa34cd7fc4ceec2c5e7f8ebe" args="(dwc_otg_pcd_t *pcd, void *handle)" -->
+static <a class="el" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8c.html#4b46c226fa34cd7fc4ceec2c5e7f8ebe">get_ep_from_handle</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, void *handle)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8c.html#5c9b20abc81e0f860a8f23c90b10b59e">dwc_otg_request_done</a> (<a class="el" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *ep, <a class="el" href="structdwc__otg__pcd__request.html">dwc_otg_pcd_request_t</a> *req, int32_t status)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function completes a request.  <a href="#5c9b20abc81e0f860a8f23c90b10b59e"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e8ef6f3d831b89a753d93489827949d3"></a><!-- doxytag: member="dwc_otg_pcd.c::dwc_otg_request_nuke" ref="e8ef6f3d831b89a753d93489827949d3" args="(dwc_otg_pcd_ep_t *ep)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8c.html#e8ef6f3d831b89a753d93489827949d3">dwc_otg_request_nuke</a> (<a class="el" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *ep)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function terminates all the requsts in the EP request queue. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8c.html#187209231d66bc200444c0d52331d276">dwc_otg_pcd_start</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, const struct <a class="el" href="structdwc__otg__pcd__function__ops.html">dwc_otg_pcd_function_ops</a> *<a class="el" href="dwc__otg__pcd__linux_8c.html#9ce9b5e49c60906c189bee157dd68acd">fops</a>)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Call this to bind the function driver to the PCD Core.  <a href="#187209231d66bc200444c0d52331d276"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8c.html#81693a91f25fb36b1443d3e597f9e59d">dwc_otg_pcd_start_cb</a> (void *p)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">PCD Callback function for initializing the PCD when switching to device mode.  <a href="#81693a91f25fb36b1443d3e597f9e59d"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3951259aaef3df35d1955076a907f095"></a><!-- doxytag: member="dwc_otg_pcd.c::cfiw_ep_alloc_buffer" ref="3951259aaef3df35d1955076a907f095" args="(dwc_otg_pcd_t *pcd, void *pep, dwc_dma_t *addr, size_t buflen, int flags)" -->
+uint8_t *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8c.html#3951259aaef3df35d1955076a907f095">cfiw_ep_alloc_buffer</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, void *pep, dwc_dma_t *addr, size_t buflen, int flags)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">CFI-specific buffer allocation function for EP. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8c.html#7bc757d00f936e5e308e950a17281675">dwc_otg_pcd_resume_cb</a> (void *p)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">PCD Callback function for notifying the PCD when resuming from suspend.  <a href="#7bc757d00f936e5e308e950a17281675"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8c.html#41a824bd34aa279d07ba3a17da35cf11">dwc_otg_pcd_suspend_cb</a> (void *p)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">PCD Callback function for notifying the PCD device is suspended.  <a href="#41a824bd34aa279d07ba3a17da35cf11"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8c.html#00e06d719bfc4fa4c40c8a06a88eb052">dwc_otg_pcd_stop_cb</a> (void *p)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">PCD Callback function for stopping the PCD when switching to Host mode.  <a href="#00e06d719bfc4fa4c40c8a06a88eb052"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="18b4a856523673f3bf97b676c8d9717e"></a><!-- doxytag: member="dwc_otg_pcd.c::dwc_otg_ep_alloc_desc_chain" ref="18b4a856523673f3bf97b676c8d9717e" args="(uint32_t *dma_desc_addr, uint32_t count)" -->
+<a class="el" href="structdwc__otg__dev__dma__desc.html">dwc_otg_dev_dma_desc_t</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8c.html#18b4a856523673f3bf97b676c8d9717e">dwc_otg_ep_alloc_desc_chain</a> (uint32_t *dma_desc_addr, uint32_t count)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function allocates a DMA Descriptor chain for the Endpoint buffer to be used for a transfer to/from the specified endpoint. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="1926b61a7438bd9a14bd6d6a26c6a63d"></a><!-- doxytag: member="dwc_otg_pcd.c::dwc_otg_ep_free_desc_chain" ref="1926b61a7438bd9a14bd6d6a26c6a63d" args="(dwc_otg_dev_dma_desc_t *desc_addr, uint32_t dma_desc_addr, uint32_t count)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8c.html#1926b61a7438bd9a14bd6d6a26c6a63d">dwc_otg_ep_free_desc_chain</a> (<a class="el" href="structdwc__otg__dev__dma__desc.html">dwc_otg_dev_dma_desc_t</a> *desc_addr, uint32_t dma_desc_addr, uint32_t count)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function frees a DMA Descriptor chain that was allocated by ep_alloc_desc. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8c.html#456f7e798e18c0b169fc196fb305e2ea">dwc_otg_iso_ep_start_ddma_transfer</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, <a class="el" href="structdwc__ep.html">dwc_ep_t</a> *<a class="el" href="structdwc__ep.html">dwc_ep</a>)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function initializes a descriptor chain for Isochronous transfer.  <a href="#456f7e798e18c0b169fc196fb305e2ea"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8c.html#0b13a31a7ddc82b53862cd06cfed6393">dwc_otg_iso_ep_start_buf_transfer</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, <a class="el" href="structdwc__ep.html">dwc_ep_t</a> *ep)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function initializes a descriptor chain for Isochronous transfer.  <a href="#0b13a31a7ddc82b53862cd06cfed6393"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8c.html#3f39ccc23c6f9bd4fd4ab7a5cecc67a3">dwc_otg_iso_ep_start_transfer</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, <a class="el" href="structdwc__ep.html">dwc_ep_t</a> *ep)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function does the setup for a data transfer for an EP and starts the transfer.  <a href="#3f39ccc23c6f9bd4fd4ab7a5cecc67a3"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8c.html#2898810e04a9dd19798f59cfdb56c670">dwc_otg_iso_ep_stop_transfer</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, <a class="el" href="structdwc__ep.html">dwc_ep_t</a> *ep)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function does the setup for a data transfer for an EP and starts the transfer.  <a href="#2898810e04a9dd19798f59cfdb56c670"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8c.html#e0a690ac031f8f06c2e7fb10b4633b05">dwc_otg_pcd_iso_ep_start</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, void *ep_handle, uint8_t *buf0, uint8_t *buf1, dwc_dma_t dma0, dwc_dma_t dma1, int sync_frame, int dp_frame, int data_per_frame, int start_frame, int buf_proc_intrvl, void *req_handle, int atomic_alloc)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Start isochronous transfers on the endpoint referenced by ep_handle.  <a href="#e0a690ac031f8f06c2e7fb10b4633b05"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8c.html#5098f89da28c6b450e7e10b31441b945">dwc_otg_pcd_iso_ep_stop</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, void *ep_handle, void *req_handle)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Stop ISOC transfers on endpoint referenced by ep_handle.  <a href="#5098f89da28c6b450e7e10b31441b945"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8c.html#b4e2c352426923d4bd519cf18b68206d">dwc_otg_iso_buffer_done</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, <a class="el" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *ep, void *req_handle)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function is used for perodical data exchnage between PCD and gadget drivers.  <a href="#b4e2c352426923d4bd519cf18b68206d"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8c.html#2f04b14612c2b58909b3a54ed71ab12e">dwc_otg_pcd_get_iso_packet_count</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, void *ep_handle, void *iso_req_handle)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get ISOC packet count.  <a href="#2f04b14612c2b58909b3a54ed71ab12e"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8c.html#21149047aa9abddac5654e4496175ac5">dwc_otg_pcd_get_iso_packet_params</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, void *ep_handle, void *iso_req_handle, int packet, int *status, int *actual, int *offset)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get ISOC packet status.  <a href="#21149047aa9abddac5654e4496175ac5"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="dbfe9af71d4c36cbf7eb544a1df9364e"></a><!-- doxytag: member="dwc_otg_pcd.c::dwc_otg_pcd_init_ep" ref="dbfe9af71d4c36cbf7eb544a1df9364e" args="(dwc_otg_pcd_t *pcd, dwc_otg_pcd_ep_t *pcd_ep, uint32_t is_in, uint32_t ep_num)" -->
+static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8c.html#dbfe9af71d4c36cbf7eb544a1df9364e">dwc_otg_pcd_init_ep</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, <a class="el" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *pcd_ep, uint32_t is_in, uint32_t ep_num)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8c.html#b6506996bd4b93ef4f80092a64384fae">dwc_otg_pcd_reinit</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Initialise ep's.  <a href="#b6506996bd4b93ef4f80092a64384fae"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8c.html#e1e5a9264c2ad212d697d6be1110874f">srp_timeout</a> (void *ptr)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function is called when the SRP timer expires.  <a href="#e1e5a9264c2ad212d697d6be1110874f"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="de7160b7e7b8fd622ba95392513e197c"></a><!-- doxytag: member="dwc_otg_pcd.c::start_next_request" ref="de7160b7e7b8fd622ba95392513e197c" args="(dwc_otg_pcd_ep_t *ep)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8c.html#de7160b7e7b8fd622ba95392513e197c">start_next_request</a> (<a class="el" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *ep)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Tasklet. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="4d9d8f7fb8f74eb64176fba91b38cb35"></a><!-- doxytag: member="dwc_otg_pcd.c::start_xfer_tasklet_func" ref="4d9d8f7fb8f74eb64176fba91b38cb35" args="(void *data)" -->
+static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8c.html#4d9d8f7fb8f74eb64176fba91b38cb35">start_xfer_tasklet_func</a> (void *data)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8c.html#fc3d8c56afa93b474180cc1eb8624ab8">dwc_otg_pcd_init</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Call this function to get pointer on dwc_otg_pcd_t, this pointer will be used for all PCD API functions.  <a href="#fc3d8c56afa93b474180cc1eb8624ab8"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8c.html#aaab1535dacd5e947c1f9343d9b3ddf5">dwc_otg_pcd_remove</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Frees PCD allocated by dwc_otg_pcd_init.  <a href="#aaab1535dacd5e947c1f9343d9b3ddf5"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ae9b15825812485a06be318858e0316a"></a><!-- doxytag: member="dwc_otg_pcd.c::dwc_otg_pcd_is_dualspeed" ref="ae9b15825812485a06be318858e0316a" args="(dwc_otg_pcd_t *pcd)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8c.html#ae9b15825812485a06be318858e0316a">dwc_otg_pcd_is_dualspeed</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function returns whether device is dualspeed. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="07169d2569c7e071fc99045fd435f2c6"></a><!-- doxytag: member="dwc_otg_pcd.c::dwc_otg_pcd_is_otg" ref="07169d2569c7e071fc99045fd435f2c6" args="(dwc_otg_pcd_t *pcd)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8c.html#07169d2569c7e071fc99045fd435f2c6">dwc_otg_pcd_is_otg</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function returns whether device is otg. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="5b3f2d055af51e556be50f3ada673e4a"></a><!-- doxytag: member="dwc_otg_pcd.c::assign_tx_fifo" ref="5b3f2d055af51e556be50f3ada673e4a" args="(dwc_otg_core_if_t *core_if)" -->
+static uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8c.html#5b3f2d055af51e556be50f3ada673e4a">assign_tx_fifo</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function assigns periodic Tx FIFO to an periodic EP in shared Tx FIFO mode. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="1df421d3a1449ec3a927d0a006c57c38"></a><!-- doxytag: member="dwc_otg_pcd.c::assign_perio_tx_fifo" ref="1df421d3a1449ec3a927d0a006c57c38" args="(dwc_otg_core_if_t *core_if)" -->
+static uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8c.html#1df421d3a1449ec3a927d0a006c57c38">assign_perio_tx_fifo</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function assigns periodic Tx FIFO to an periodic EP in shared Tx FIFO mode. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="1bd1933ef625beee77eb026c4b1acb15"></a><!-- doxytag: member="dwc_otg_pcd.c::release_perio_tx_fifo" ref="1bd1933ef625beee77eb026c4b1acb15" args="(dwc_otg_core_if_t *core_if, uint32_t fifo_num)" -->
+static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8c.html#1bd1933ef625beee77eb026c4b1acb15">release_perio_tx_fifo</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, uint32_t fifo_num)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function releases periodic Tx FIFO in shared Tx FIFO mode. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="bde782d98282535dc0c29a468da11f02"></a><!-- doxytag: member="dwc_otg_pcd.c::release_tx_fifo" ref="bde782d98282535dc0c29a468da11f02" args="(dwc_otg_core_if_t *core_if, uint32_t fifo_num)" -->
+static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8c.html#bde782d98282535dc0c29a468da11f02">release_tx_fifo</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, uint32_t fifo_num)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function releases periodic Tx FIFO in shared Tx FIFO mode. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8c.html#b9168f11717bdc672d9a29226779e523">dwc_otg_pcd_ep_enable</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, const uint8_t *ep_desc, void *usb_ep)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Enables an endpoint for use.  <a href="#b9168f11717bdc672d9a29226779e523"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8c.html#8a2f791c79320c8c4657715a672822a4">dwc_otg_pcd_ep_disable</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, void *ep_handle)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Disable the endpoint referenced by ep_handle.  <a href="#8a2f791c79320c8c4657715a672822a4"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8c.html#09f3d77397aa7d22a1ca32e26c8aedea">dwc_otg_pcd_ep_queue</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, void *ep_handle, uint8_t *buf, dwc_dma_t dma_buf, uint32_t buflen, int zero, void *req_handle, int atomic_alloc)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Queue a data transfer request on the endpoint referenced by ep_handle.  <a href="#09f3d77397aa7d22a1ca32e26c8aedea"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8c.html#aa7546ce68d6fda67bb4cda0f69eedf3">dwc_otg_pcd_ep_dequeue</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, void *ep_handle, void *req_handle)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">De-queue the specified data transfer that has not yet completed.  <a href="#aa7546ce68d6fda67bb4cda0f69eedf3"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8c.html#f7d01b4772f08c6a08f4a22300a7b43b">dwc_otg_pcd_ep_halt</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, void *ep_handle, int value)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Halt (STALL) an endpoint or clear it.  <a href="#f7d01b4772f08c6a08f4a22300a7b43b"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="89fb8b7a8276390becc3370903af55e2"></a><!-- doxytag: member="dwc_otg_pcd.c::dwc_otg_pcd_rem_wkup_from_suspend" ref="89fb8b7a8276390becc3370903af55e2" args="(dwc_otg_pcd_t *pcd, int set)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8c.html#89fb8b7a8276390becc3370903af55e2">dwc_otg_pcd_rem_wkup_from_suspend</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, int set)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function initiates remote wakeup of the host from suspend state. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="24cbdd57c573d864a09a30ae3ecda89a"></a><!-- doxytag: member="dwc_otg_pcd.c::dwc_otg_pcd_remote_wakeup" ref="24cbdd57c573d864a09a30ae3ecda89a" args="(dwc_otg_pcd_t *pcd, int set)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8c.html#24cbdd57c573d864a09a30ae3ecda89a">dwc_otg_pcd_remote_wakeup</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, int set)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Starts remote wakeup signaling. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8c.html#7e0d7b09dc6528626f4643deb296d68d">dwc_otg_pcd_wakeup</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function starts the SRP Protocol if no session is in progress.  <a href="#7e0d7b09dc6528626f4643deb296d68d"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8c.html#517f9cf3e74ebb0b9e00ea1defc56697">dwc_otg_pcd_start_srp_timer</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Start the SRP timer to detect when the SRP does not complete within 6 seconds.  <a href="#517f9cf3e74ebb0b9e00ea1defc56697"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="4be3e59162a42a79705e3ea8dc5008fa"></a><!-- doxytag: member="dwc_otg_pcd.c::dwc_otg_pcd_initiate_srp" ref="4be3e59162a42a79705e3ea8dc5008fa" args="(dwc_otg_pcd_t *pcd)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8c.html#4be3e59162a42a79705e3ea8dc5008fa">dwc_otg_pcd_initiate_srp</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Initiate SRP. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="04876b716043a853b379d72ff3a215e5"></a><!-- doxytag: member="dwc_otg_pcd.c::dwc_otg_pcd_get_frame_number" ref="04876b716043a853b379d72ff3a215e5" args="(dwc_otg_pcd_t *pcd)" -->
+int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8c.html#04876b716043a853b379d72ff3a215e5">dwc_otg_pcd_get_frame_number</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function returns current frame number. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="676021c9b801674669cdf2d1e68d5b8c"></a><!-- doxytag: member="dwc_otg_pcd.c::dwc_otg_pcd_is_lpm_enabled" ref="676021c9b801674669cdf2d1e68d5b8c" args="(dwc_otg_pcd_t *pcd)" -->
+int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8c.html#676021c9b801674669cdf2d1e68d5b8c">dwc_otg_pcd_is_lpm_enabled</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function returns 1 if LPM support is enabled, and 0 otherwise. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="777a6a4e250add9ba5f5f5d63d854031"></a><!-- doxytag: member="dwc_otg_pcd.c::get_b_hnp_enable" ref="777a6a4e250add9ba5f5f5d63d854031" args="(dwc_otg_pcd_t *pcd)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8c.html#777a6a4e250add9ba5f5f5d63d854031">get_b_hnp_enable</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">These functions allow to get hnp parameters. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="69d0bb469e15cb46f00c17398f76df99"></a><!-- doxytag: member="dwc_otg_pcd.c::get_a_hnp_support" ref="69d0bb469e15cb46f00c17398f76df99" args="(dwc_otg_pcd_t *pcd)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8c.html#69d0bb469e15cb46f00c17398f76df99">get_a_hnp_support</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="842709a4980bc78d49726fa880922dda"></a><!-- doxytag: member="dwc_otg_pcd.c::get_a_alt_hnp_support" ref="842709a4980bc78d49726fa880922dda" args="(dwc_otg_pcd_t *pcd)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8c.html#842709a4980bc78d49726fa880922dda">get_a_alt_hnp_support</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="0107dd39d549d3e10fd388337e03aeb9"></a><!-- doxytag: member="dwc_otg_pcd.c::dwc_otg_pcd_get_rmwkup_enable" ref="0107dd39d549d3e10fd388337e03aeb9" args="(dwc_otg_pcd_t *pcd)" -->
+int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8c.html#0107dd39d549d3e10fd388337e03aeb9">dwc_otg_pcd_get_rmwkup_enable</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function returns 1 if remote wakeup is allowed and 0, otherwise. <br></td></tr>
+<tr><td colspan="2"><br><h2>Variables</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static <a class="el" href="structdwc__otg__cil__callbacks.html">dwc_otg_cil_callbacks_t</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8c.html#c360aaa36ba28b977284fd482e7bc5ca">pcd_callbacks</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">PCD Callback structure for handling mode switching.  <a href="#c360aaa36ba28b977284fd482e7bc5ca"></a><br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This file implements PCD Core. 
+<p>
+All code in this file is portable and don't use any OS specific functions. PCD Core provides Interface, defined in <code>&lt;<a class="el" href="dwc__otg__pcd__if_8h.html">dwc_otg_pcd_if.h</a>&gt;</code> header file, which can be used to implement OS specific PCD interface.<p>
+An important function of the PCD is managing interrupts generated by the DWC_otg controller. The implementation of the DWC_otg device mode interrupt service routines is in <a class="el" href="dwc__otg__pcd__intr_8c.html">dwc_otg_pcd_intr.c</a>.<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000021">Todo:</a></b></dt><dd>Add Device Mode test modes (Test J mode, Test K mode, etc). <p>
+Does it work when the request size is greater than DEPTSIZ transfer size</dd></dl>
+
+<p>
+Definition in file <a class="el" href="dwc__otg__pcd_8c-source.html">dwc_otg_pcd.c</a>.<hr><h2>Function Documentation</h2>
+<a class="anchor" name="5c9b20abc81e0f860a8f23c90b10b59e"></a><!-- doxytag: member="dwc_otg_pcd.c::dwc_otg_request_done" ref="5c9b20abc81e0f860a8f23c90b10b59e" args="(dwc_otg_pcd_ep_t *ep, dwc_otg_pcd_request_t *req, int32_t status)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_request_done           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>ep</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd__request.html">dwc_otg_pcd_request_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>req</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&nbsp;</td>
+          <td class="paramname"> <em>status</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function completes a request. 
+<p>
+It call's the request call back. 
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd_8c-source.html#l00078">78</a> of file <a class="el" href="dwc__otg__pcd_8c-source.html">dwc_otg_pcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="187209231d66bc200444c0d52331d276"></a><!-- doxytag: member="dwc_otg_pcd.c::dwc_otg_pcd_start" ref="187209231d66bc200444c0d52331d276" args="(dwc_otg_pcd_t *pcd, const struct dwc_otg_pcd_function_ops *fops)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_pcd_start           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">const struct <a class="el" href="structdwc__otg__pcd__function__ops.html">dwc_otg_pcd_function_ops</a> *&nbsp;</td>
+          <td class="paramname"> <em>fops</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Call this to bind the function driver to the PCD Core. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>pcd</em>&nbsp;</td><td>Pointer on dwc_otg_pcd_t returned by dwc_otg_pcd_init function. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>fops</em>&nbsp;</td><td>The Function Driver Ops data structure containing pointers to all callbacks. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd_8c-source.html#l00117">117</a> of file <a class="el" href="dwc__otg__pcd_8c-source.html">dwc_otg_pcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="81693a91f25fb36b1443d3e597f9e59d"></a><!-- doxytag: member="dwc_otg_pcd.c::dwc_otg_pcd_start_cb" ref="81693a91f25fb36b1443d3e597f9e59d" args="(void *p)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static int32_t dwc_otg_pcd_start_cb           </td>
+          <td>(</td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>p</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+PCD Callback function for initializing the PCD when switching to device mode. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>p</em>&nbsp;</td><td>void pointer to the <code>dwc_otg_pcd_t</code> </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd_8c-source.html#l00129">129</a> of file <a class="el" href="dwc__otg__pcd_8c-source.html">dwc_otg_pcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="7bc757d00f936e5e308e950a17281675"></a><!-- doxytag: member="dwc_otg_pcd.c::dwc_otg_pcd_resume_cb" ref="7bc757d00f936e5e308e950a17281675" args="(void *p)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static int32_t dwc_otg_pcd_resume_cb           </td>
+          <td>(</td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>p</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+PCD Callback function for notifying the PCD when resuming from suspend. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>p</em>&nbsp;</td><td>void pointer to the <code>dwc_otg_pcd_t</code> </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd_8c-source.html#l00163">163</a> of file <a class="el" href="dwc__otg__pcd_8c-source.html">dwc_otg_pcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="41a824bd34aa279d07ba3a17da35cf11"></a><!-- doxytag: member="dwc_otg_pcd.c::dwc_otg_pcd_suspend_cb" ref="41a824bd34aa279d07ba3a17da35cf11" args="(void *p)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static int32_t dwc_otg_pcd_suspend_cb           </td>
+          <td>(</td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>p</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+PCD Callback function for notifying the PCD device is suspended. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>p</em>&nbsp;</td><td>void pointer to the <code>dwc_otg_pcd_t</code> </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd_8c-source.html#l00187">187</a> of file <a class="el" href="dwc__otg__pcd_8c-source.html">dwc_otg_pcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="00e06d719bfc4fa4c40c8a06a88eb052"></a><!-- doxytag: member="dwc_otg_pcd.c::dwc_otg_pcd_stop_cb" ref="00e06d719bfc4fa4c40c8a06a88eb052" args="(void *p)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static int32_t dwc_otg_pcd_stop_cb           </td>
+          <td>(</td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>p</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+PCD Callback function for stopping the PCD when switching to Host mode. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>p</em>&nbsp;</td><td>void pointer to the <code>dwc_otg_pcd_t</code> </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd_8c-source.html#l00204">204</a> of file <a class="el" href="dwc__otg__pcd_8c-source.html">dwc_otg_pcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="456f7e798e18c0b169fc196fb305e2ea"></a><!-- doxytag: member="dwc_otg_pcd.c::dwc_otg_iso_ep_start_ddma_transfer" ref="456f7e798e18c0b169fc196fb305e2ea" args="(dwc_otg_core_if_t *core_if, dwc_ep_t *dwc_ep)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_iso_ep_start_ddma_transfer           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__ep.html">dwc_ep_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>dwc_ep</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function initializes a descriptor chain for Isochronous transfer. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em><a class="el" href="structdwc__ep.html">dwc_ep</a></em>&nbsp;</td><td>The EP to start the transfer on. </td></tr>
+  </table>
+</dl>
+
+<p>
+Allocate descriptors for double buffering<p>
+ISO OUT EP<p>
+Buffer 0 descriptors setup<p>
+Buffer 1 descriptors setup<p>
+Write dma_ad into DOEPDMA register<p>
+ISO IN EP<p>
+Buffer 0 descriptors setup<p>
+Buffer 1 descriptors setup<p>
+Write dma_ad into diepdma register<p>
+Enable endpoint, clear nak 
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd_8c-source.html#l00254">254</a> of file <a class="el" href="dwc__otg__pcd_8c-source.html">dwc_otg_pcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="0b13a31a7ddc82b53862cd06cfed6393"></a><!-- doxytag: member="dwc_otg_pcd.c::dwc_otg_iso_ep_start_buf_transfer" ref="0b13a31a7ddc82b53862cd06cfed6393" args="(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_iso_ep_start_buf_transfer           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__ep.html">dwc_ep_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>ep</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function initializes a descriptor chain for Isochronous transfer. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep</em>&nbsp;</td><td>The EP to start the transfer on. </td></tr>
+  </table>
+</dl>
+
+<p>
+Enable endpoint, clear nak 
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd_8c-source.html#l00517">517</a> of file <a class="el" href="dwc__otg__pcd_8c-source.html">dwc_otg_pcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="3f39ccc23c6f9bd4fd4ab7a5cecc67a3"></a><!-- doxytag: member="dwc_otg_pcd.c::dwc_otg_iso_ep_start_transfer" ref="3f39ccc23c6f9bd4fd4ab7a5cecc67a3" args="(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static void dwc_otg_iso_ep_start_transfer           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__ep.html">dwc_ep_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>ep</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function does the setup for a data transfer for an EP and starts the transfer. 
+<p>
+For an IN transfer, the packets will be loaded into the appropriate Tx FIFO in the ISR. For OUT transfers, the packets are unloaded from the Rx FIFO in the ISR. the ISR.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep</em>&nbsp;</td><td>The EP to start the transfer on. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd_8c-source.html#l00598">598</a> of file <a class="el" href="dwc__otg__pcd_8c-source.html">dwc_otg_pcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="2898810e04a9dd19798f59cfdb56c670"></a><!-- doxytag: member="dwc_otg_pcd.c::dwc_otg_iso_ep_stop_transfer" ref="2898810e04a9dd19798f59cfdb56c670" args="(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_iso_ep_stop_transfer           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__ep.html">dwc_ep_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>ep</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function does the setup for a data transfer for an EP and starts the transfer. 
+<p>
+For an IN transfer, the packets will be loaded into the appropriate Tx FIFO in the ISR. For OUT transfers, the packets are unloaded from the Rx FIFO in the ISR. the ISR.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep</em>&nbsp;</td><td>The EP to start the transfer on. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd_8c-source.html#l00641">641</a> of file <a class="el" href="dwc__otg__pcd_8c-source.html">dwc_otg_pcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="e0a690ac031f8f06c2e7fb10b4633b05"></a><!-- doxytag: member="dwc_otg_pcd.c::dwc_otg_pcd_iso_ep_start" ref="e0a690ac031f8f06c2e7fb10b4633b05" args="(dwc_otg_pcd_t *pcd, void *ep_handle, uint8_t *buf0, uint8_t *buf1, dwc_dma_t dma0, dwc_dma_t dma1, int sync_frame, int dp_frame, int data_per_frame, int start_frame, int buf_proc_intrvl, void *req_handle, int atomic_alloc)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_pcd_iso_ep_start           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>ep_handle</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>buf0</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>buf1</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">dwc_dma_t&nbsp;</td>
+          <td class="paramname"> <em>dma0</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">dwc_dma_t&nbsp;</td>
+          <td class="paramname"> <em>dma1</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>sync_frame</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>dp_frame</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>data_per_frame</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>start_frame</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>buf_proc_intrvl</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>req_handle</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>atomic_alloc</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Start isochronous transfers on the endpoint referenced by ep_handle. 
+<p>
+For isochronous transfers duble buffering is used. After processing each of buffers comlete callback will be called with status for each transaction.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>pcd</em>&nbsp;</td><td>The PCD </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep_handle</em>&nbsp;</td><td>The handle of the endpoint </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>buf0</em>&nbsp;</td><td>The virtual address of first data buffer </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>buf1</em>&nbsp;</td><td>The virtual address of second data buffer </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>dma0</em>&nbsp;</td><td>The DMA address of first data buffer </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>dma1</em>&nbsp;</td><td>The DMA address of second data buffer </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>sync_frame</em>&nbsp;</td><td>Data pattern frame number </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>dp_frame</em>&nbsp;</td><td>Data size for pattern frame </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>data_per_frame</em>&nbsp;</td><td>Data size for regular frame </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>start_frame</em>&nbsp;</td><td>Frame number to start transfers, if -1 then start transfers ASAP. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>buf_proc_intrvl</em>&nbsp;</td><td>Interval of ISOC Buffer processing </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>req_handle</em>&nbsp;</td><td>Handle of ISOC request </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>atomic_alloc</em>&nbsp;</td><td>Specefies whether to perform atomic allocation for internal data structures.</td></tr>
+  </table>
+</dl>
+Returns -DWC_E_NO_MEMORY if there is no enough memory. Returns -DWC_E_INVALID if incorrect arguments are passed to the function. Returns -DW_E_SHUTDOWN for any other error. Returns 0 on success 
+<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000022">Todo:</a></b></dt><dd><ul>
+<li>pattern data support is to be implemented in the future </li></ul>
+</dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd_8c-source.html#l00685">685</a> of file <a class="el" href="dwc__otg__pcd_8c-source.html">dwc_otg_pcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="5098f89da28c6b450e7e10b31441b945"></a><!-- doxytag: member="dwc_otg_pcd.c::dwc_otg_pcd_iso_ep_stop" ref="5098f89da28c6b450e7e10b31441b945" args="(dwc_otg_pcd_t *pcd, void *ep_handle, void *req_handle)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_pcd_iso_ep_stop           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>ep_handle</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>req_handle</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Stop ISOC transfers on endpoint referenced by ep_handle. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>pcd</em>&nbsp;</td><td>The PCD </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep_handle</em>&nbsp;</td><td>The handle of the endpoint </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>req_handle</em>&nbsp;</td><td>Handle of ISOC request</td></tr>
+  </table>
+</dl>
+Returns -DWC_E_INVALID if incorrect arguments are passed to the function Returns 0 on success 
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd_8c-source.html#l00794">794</a> of file <a class="el" href="dwc__otg__pcd_8c-source.html">dwc_otg_pcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="b4e2c352426923d4bd519cf18b68206d"></a><!-- doxytag: member="dwc_otg_pcd.c::dwc_otg_iso_buffer_done" ref="b4e2c352426923d4bd519cf18b68206d" args="(dwc_otg_pcd_t *pcd, dwc_otg_pcd_ep_t *ep, void *req_handle)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_iso_buffer_done           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>ep</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>req_handle</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function is used for perodical data exchnage between PCD and gadget drivers. 
+<p>
+for Isochronous EPs<p>
+<ul>
+<li>Every time a sync period completes this function is called to perform data exchange between PCD and gadget </li></ul>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd_8c-source.html#l00830">830</a> of file <a class="el" href="dwc__otg__pcd_8c-source.html">dwc_otg_pcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="2f04b14612c2b58909b3a54ed71ab12e"></a><!-- doxytag: member="dwc_otg_pcd.c::dwc_otg_pcd_get_iso_packet_count" ref="2f04b14612c2b58909b3a54ed71ab12e" args="(dwc_otg_pcd_t *pcd, void *ep_handle, void *iso_req_handle)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_pcd_get_iso_packet_count           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>ep_handle</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>iso_req_handle</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Get ISOC packet count. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>pcd</em>&nbsp;</td><td>The PCD </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep_handle</em>&nbsp;</td><td>The handle of the endpoint </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>iso_req_handle</em>&nbsp;</td><td></td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd_8c-source.html#l00850">850</a> of file <a class="el" href="dwc__otg__pcd_8c-source.html">dwc_otg_pcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="21149047aa9abddac5654e4496175ac5"></a><!-- doxytag: member="dwc_otg_pcd.c::dwc_otg_pcd_get_iso_packet_params" ref="21149047aa9abddac5654e4496175ac5" args="(dwc_otg_pcd_t *pcd, void *ep_handle, void *iso_req_handle, int packet, int *status, int *actual, int *offset)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_pcd_get_iso_packet_params           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>ep_handle</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>iso_req_handle</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>packet</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int *&nbsp;</td>
+          <td class="paramname"> <em>status</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int *&nbsp;</td>
+          <td class="paramname"> <em>actual</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int *&nbsp;</td>
+          <td class="paramname"> <em>offset</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Get ISOC packet status. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>pcd</em>&nbsp;</td><td>The PCD </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep_handle</em>&nbsp;</td><td>The handle of the endpoint </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>iso_req_handle</em>&nbsp;</td><td>Isochronoush request handle </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>packet</em>&nbsp;</td><td>Number of packet </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>status</em>&nbsp;</td><td>Out parameter for returning status </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>actual</em>&nbsp;</td><td>Out parameter for returning actual length </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>offset</em>&nbsp;</td><td>Out parameter for returning offset </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd_8c-source.html#l00862">862</a> of file <a class="el" href="dwc__otg__pcd_8c-source.html">dwc_otg_pcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="b6506996bd4b93ef4f80092a64384fae"></a><!-- doxytag: member="dwc_otg_pcd.c::dwc_otg_pcd_reinit" ref="b6506996bd4b93ef4f80092a64384fae" args="(dwc_otg_pcd_t *pcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static void dwc_otg_pcd_reinit           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Initialise ep's. 
+<p>
+
+<p>
+Initialize the EP0 structure.<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000023">Todo:</a></b></dt><dd>NGS: Add direction to EP, based on contents of HWCFG1. Need a copy of HWCFG1 in pcd structure? sprintf(";r </dd></dl>
+<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000023">Todo:</a></b></dt><dd>NGS: Add direction to EP, based on contents of HWCFG1. Need a copy of HWCFG1 in pcd structure? sprintf(";r </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd_8c-source.html#l00911">911</a> of file <a class="el" href="dwc__otg__pcd_8c-source.html">dwc_otg_pcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="e1e5a9264c2ad212d697d6be1110874f"></a><!-- doxytag: member="dwc_otg_pcd.c::srp_timeout" ref="e1e5a9264c2ad212d697d6be1110874f" args="(void *ptr)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static void srp_timeout           </td>
+          <td>(</td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>ptr</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function is called when the SRP timer expires. 
+<p>
+The SRP should complete within 6 seconds. 
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd_8c-source.html#l00970">970</a> of file <a class="el" href="dwc__otg__pcd_8c-source.html">dwc_otg_pcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="fc3d8c56afa93b474180cc1eb8624ab8"></a><!-- doxytag: member="dwc_otg_pcd.c::dwc_otg_pcd_init" ref="fc3d8c56afa93b474180cc1eb8624ab8" args="(dwc_otg_core_if_t *core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a>* dwc_otg_pcd_init           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Call this function to get pointer on dwc_otg_pcd_t, this pointer will be used for all PCD API functions. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>The DWC_OTG Core </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd_8c-source.html#l01056">1056</a> of file <a class="el" href="dwc__otg__pcd_8c-source.html">dwc_otg_pcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="aaab1535dacd5e947c1f9343d9b3ddf5"></a><!-- doxytag: member="dwc_otg_pcd.c::dwc_otg_pcd_remove" ref="aaab1535dacd5e947c1f9343d9b3ddf5" args="(dwc_otg_pcd_t *pcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_pcd_remove           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Frees PCD allocated by dwc_otg_pcd_init. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>pcd</em>&nbsp;</td><td>The PCD </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd_8c-source.html#l01215">1215</a> of file <a class="el" href="dwc__otg__pcd_8c-source.html">dwc_otg_pcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="b9168f11717bdc672d9a29226779e523"></a><!-- doxytag: member="dwc_otg_pcd.c::dwc_otg_pcd_ep_enable" ref="b9168f11717bdc672d9a29226779e523" args="(dwc_otg_pcd_t *pcd, const uint8_t *ep_desc, void *usb_ep)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_pcd_ep_enable           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">const uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>ep_desc</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>ep_handle</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Enables an endpoint for use. 
+<p>
+This function enables an endpoint in the PCD. The endpoint is described by the ep_desc which has the same format as a USB ep descriptor. The ep_handle parameter is used to refer to the endpoint from other API functions and in callbacks. Normally this should be called after a SET_CONFIGURATION/SET_INTERFACE to configure the core for that interface.<p>
+Returns -DWC_E_INVALID if invalid parameters were passed. Returns -DWC_E_SHUTDOWN if any other error ocurred. Returns 0 on success.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>pcd</em>&nbsp;</td><td>The PCD </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep_desc</em>&nbsp;</td><td>Endpoint descriptor </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep_handle</em>&nbsp;</td><td>Handle on endpoint, that will be used to identify endpoint. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd_8c-source.html#l01341">1341</a> of file <a class="el" href="dwc__otg__pcd_8c-source.html">dwc_otg_pcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="8a2f791c79320c8c4657715a672822a4"></a><!-- doxytag: member="dwc_otg_pcd.c::dwc_otg_pcd_ep_disable" ref="8a2f791c79320c8c4657715a672822a4" args="(dwc_otg_pcd_t *pcd, void *ep_handle)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_pcd_ep_disable           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>ep_handle</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Disable the endpoint referenced by ep_handle. 
+<p>
+Returns -DWC_E_INVALID if invalid parameters were passed. Returns -DWC_E_SHUTDOWN if any other error ocurred. Returns 0 on success. 
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd_8c-source.html#l01449">1449</a> of file <a class="el" href="dwc__otg__pcd_8c-source.html">dwc_otg_pcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="09f3d77397aa7d22a1ca32e26c8aedea"></a><!-- doxytag: member="dwc_otg_pcd.c::dwc_otg_pcd_ep_queue" ref="09f3d77397aa7d22a1ca32e26c8aedea" args="(dwc_otg_pcd_t *pcd, void *ep_handle, uint8_t *buf, dwc_dma_t dma_buf, uint32_t buflen, int zero, void *req_handle, int atomic_alloc)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_pcd_ep_queue           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>ep_handle</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>buf</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">dwc_dma_t&nbsp;</td>
+          <td class="paramname"> <em>dma_buf</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint32_t&nbsp;</td>
+          <td class="paramname"> <em>buflen</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>zero</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>req_handle</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>atomic_alloc</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Queue a data transfer request on the endpoint referenced by ep_handle. 
+<p>
+After the transfer is completes, the complete callback will be called with the request status.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>pcd</em>&nbsp;</td><td>The PCD </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep_handle</em>&nbsp;</td><td>The handle of the endpoint </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>buf</em>&nbsp;</td><td>The buffer for the data </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>dma_buf</em>&nbsp;</td><td>The DMA buffer for the data </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>buflen</em>&nbsp;</td><td>The length of the data transfer </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>zero</em>&nbsp;</td><td>Specifies whether to send zero length last packet. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>req_handle</em>&nbsp;</td><td>Set this handle to any value to use to reference this request in the ep_dequeue function or from the complete callback </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>atomic_alloc</em>&nbsp;</td><td>If driver need to perform atomic allocations for internal data structures.</td></tr>
+  </table>
+</dl>
+Returns -DWC_E_INVALID if invalid parameters were passed. Returns -DWC_E_SHUTDOWN if any other error ocurred. Returns 0 on success. 
+<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000025">Todo:</a></b></dt><dd>NGS Create a function for this. </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd_8c-source.html#l01502">1502</a> of file <a class="el" href="dwc__otg__pcd_8c-source.html">dwc_otg_pcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="aa7546ce68d6fda67bb4cda0f69eedf3"></a><!-- doxytag: member="dwc_otg_pcd.c::dwc_otg_pcd_ep_dequeue" ref="aa7546ce68d6fda67bb4cda0f69eedf3" args="(dwc_otg_pcd_t *pcd, void *ep_handle, void *req_handle)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_pcd_ep_dequeue           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>ep_handle</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>req_handle</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+De-queue the specified data transfer that has not yet completed. 
+<p>
+Returns -DWC_E_INVALID if invalid parameters were passed. Returns -DWC_E_SHUTDOWN if any other error ocurred. Returns 0 on success. 
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd_8c-source.html#l01694">1694</a> of file <a class="el" href="dwc__otg__pcd_8c-source.html">dwc_otg_pcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="f7d01b4772f08c6a08f4a22300a7b43b"></a><!-- doxytag: member="dwc_otg_pcd.c::dwc_otg_pcd_ep_halt" ref="f7d01b4772f08c6a08f4a22300a7b43b" args="(dwc_otg_pcd_t *pcd, void *ep_handle, int value)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_pcd_ep_halt           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>ep_handle</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>value</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Halt (STALL) an endpoint or clear it. 
+<p>
+Returns -DWC_E_INVALID if invalid parameters were passed. Returns -DWC_E_SHUTDOWN if any other error ocurred. Returns -DWC_E_AGAIN if the STALL cannot be sent and must be tried again later Returns 0 on success. 
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd_8c-source.html#l01733">1733</a> of file <a class="el" href="dwc__otg__pcd_8c-source.html">dwc_otg_pcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="7e0d7b09dc6528626f4643deb296d68d"></a><!-- doxytag: member="dwc_otg_pcd.c::dwc_otg_pcd_wakeup" ref="7e0d7b09dc6528626f4643deb296d68d" args="(dwc_otg_pcd_t *pcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_pcd_wakeup           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function starts the SRP Protocol if no session is in progress. 
+<p>
+If a session is already in progress, but the device is suspended, remote wakeup signaling is started. 
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd_8c-source.html#l01896">1896</a> of file <a class="el" href="dwc__otg__pcd_8c-source.html">dwc_otg_pcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="517f9cf3e74ebb0b9e00ea1defc56697"></a><!-- doxytag: member="dwc_otg_pcd.c::dwc_otg_pcd_start_srp_timer" ref="517f9cf3e74ebb0b9e00ea1defc56697" args="(dwc_otg_pcd_t *pcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_pcd_start_srp_timer           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Start the SRP timer to detect when the SRP does not complete within 6 seconds. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>pcd</em>&nbsp;</td><td>the pcd structure. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd_8c-source.html#l01937">1937</a> of file <a class="el" href="dwc__otg__pcd_8c-source.html">dwc_otg_pcd.c</a>.
+</div>
+</div><p>
+<hr><h2>Variable Documentation</h2>
+<a class="anchor" name="c360aaa36ba28b977284fd482e7bc5ca"></a><!-- doxytag: member="dwc_otg_pcd.c::pcd_callbacks" ref="c360aaa36ba28b977284fd482e7bc5ca" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="structdwc__otg__cil__callbacks.html">dwc_otg_cil_callbacks_t</a> <a class="el" href="dwc__otg__pcd_8c.html#c360aaa36ba28b977284fd482e7bc5ca">pcd_callbacks</a><code> [static]</code>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Initial value:</b><div class="fragment"><pre class="fragment"> {
+        .start = <a class="code" href="dwc__otg__pcd_8c.html#81693a91f25fb36b1443d3e597f9e59d">dwc_otg_pcd_start_cb</a>,
+        .stop = <a class="code" href="dwc__otg__pcd_8c.html#00e06d719bfc4fa4c40c8a06a88eb052">dwc_otg_pcd_stop_cb</a>,
+        .suspend = <a class="code" href="dwc__otg__pcd_8c.html#41a824bd34aa279d07ba3a17da35cf11">dwc_otg_pcd_suspend_cb</a>,
+        .resume_wakeup = <a class="code" href="dwc__otg__pcd_8c.html#7bc757d00f936e5e308e950a17281675">dwc_otg_pcd_resume_cb</a>,
+        .p = 0,                 
+}
+</pre></div>PCD Callback structure for handling mode switching. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd_8c-source.html#l00216">216</a> of file <a class="el" href="dwc__otg__pcd_8c-source.html">dwc_otg_pcd.c</a>.
+</div>
+</div><p>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd_8h-source.html b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd_8h-source.html
new file mode 100644
index 000000000000..aabe3e08f248
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd_8h-source.html
@@ -0,0 +1,171 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd.h Source File</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<h1>dwc_otg_pcd.h</h1><a href="dwc__otg__pcd_8h.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">/* ==========================================================================</span>
+<a name="l00002"></a>00002 <span class="comment"> * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.h $</span>
+<a name="l00003"></a>00003 <span class="comment"> * $Revision: #39 $</span>
+<a name="l00004"></a>00004 <span class="comment"> * $Date: 2008/12/16 $</span>
+<a name="l00005"></a>00005 <span class="comment"> * $Change: 1153731 $</span>
+<a name="l00006"></a>00006 <span class="comment"> *</span>
+<a name="l00007"></a>00007 <span class="comment"> * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,</span>
+<a name="l00008"></a>00008 <span class="comment"> * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless</span>
+<a name="l00009"></a>00009 <span class="comment"> * otherwise expressly agreed to in writing between Synopsys and you.</span>
+<a name="l00010"></a>00010 <span class="comment"> *</span>
+<a name="l00011"></a>00011 <span class="comment"> * The Software IS NOT an item of Licensed Software or Licensed Product under</span>
+<a name="l00012"></a>00012 <span class="comment"> * any End User Software License Agreement or Agreement for Licensed Product</span>
+<a name="l00013"></a>00013 <span class="comment"> * with Synopsys or any supplement thereto. You are permitted to use and</span>
+<a name="l00014"></a>00014 <span class="comment"> * redistribute this Software in source and binary forms, with or without</span>
+<a name="l00015"></a>00015 <span class="comment"> * modification, provided that redistributions of source code must retain this</span>
+<a name="l00016"></a>00016 <span class="comment"> * notice. You may not view, use, disclose, copy or distribute this file or</span>
+<a name="l00017"></a>00017 <span class="comment"> * any information contained herein except pursuant to this license grant from</span>
+<a name="l00018"></a>00018 <span class="comment"> * Synopsys. If you do not agree with this notice, including the disclaimer</span>
+<a name="l00019"></a>00019 <span class="comment"> * below, then you are not authorized to use the Software.</span>
+<a name="l00020"></a>00020 <span class="comment"> *</span>
+<a name="l00021"></a>00021 <span class="comment"> * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS</span>
+<a name="l00022"></a>00022 <span class="comment"> * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE</span>
+<a name="l00023"></a>00023 <span class="comment"> * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE</span>
+<a name="l00024"></a>00024 <span class="comment"> * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,</span>
+<a name="l00025"></a>00025 <span class="comment"> * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES</span>
+<a name="l00026"></a>00026 <span class="comment"> * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR</span>
+<a name="l00027"></a>00027 <span class="comment"> * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER</span>
+<a name="l00028"></a>00028 <span class="comment"> * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT</span>
+<a name="l00029"></a>00029 <span class="comment"> * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY</span>
+<a name="l00030"></a>00030 <span class="comment"> * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH</span>
+<a name="l00031"></a>00031 <span class="comment"> * DAMAGE.</span>
+<a name="l00032"></a>00032 <span class="comment"> * ========================================================================== */</span>
+<a name="l00033"></a>00033 <span class="preprocessor">#ifndef DWC_HOST_ONLY</span>
+<a name="l00034"></a>00034 <span class="preprocessor"></span><span class="preprocessor">#if !defined(__DWC_PCD_H__)</span>
+<a name="l00035"></a><a class="code" href="dwc__otg__pcd_8h.html#ed26bb67f5785dc6e70289976637a310">00035</a> <span class="preprocessor"></span><span class="preprocessor">#define __DWC_PCD_H__</span>
+<a name="l00036"></a>00036 <span class="preprocessor"></span>
+<a name="l00037"></a>00037 <span class="preprocessor">#include "usb.h"</span>
+<a name="l00038"></a>00038 <span class="preprocessor">#include "<a class="code" href="dwc__otg__cil_8h.html">dwc_otg_cil.h</a>"</span>
+<a name="l00039"></a>00039 <span class="preprocessor">#include "<a class="code" href="dwc__otg__pcd__if_8h.html">dwc_otg_pcd_if.h</a>"</span>
+<a name="l00040"></a>00040 <span class="keyword">struct </span><a class="code" href="structcfiobject.html">cfiobject</a>;
+<a name="l00041"></a>00041 
+<a name="l00058"></a><a class="code" href="dwc__otg__pcd_8h.html#6dad4d4462e9819753acfc601889faec">00058</a> <span class="preprocessor">#define DDMA_MAX_TRANSFER_SIZE 65535</span>
+<a name="l00059"></a>00059 <span class="preprocessor"></span>
+<a name="l00061"></a><a class="code" href="dwc__otg__pcd_8h.html#a1c5dc8973b5c039fd77b1e250ce29e2">00061</a> <span class="preprocessor">#define MAX_DMA_DESC_CNT 64</span>
+<a name="l00062"></a>00062 <span class="preprocessor"></span>
+<a name="l00066"></a><a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">00066</a> <span class="preprocessor">#define GET_CORE_IF( _pcd ) (_pcd-&gt;core_if)</span>
+<a name="l00067"></a>00067 <span class="preprocessor"></span>
+<a name="l00071"></a><a class="code" href="dwc__otg__pcd_8h.html#f286abbd9be76db05fee7aebfeb61865">00071</a> <span class="keyword">typedef</span> <span class="keyword">enum</span> <a class="code" href="dwc__otg__pcd_8h.html#f286abbd9be76db05fee7aebfeb61865">ep0_state</a> {
+<a name="l00072"></a>00072         EP0_DISCONNECT,         <span class="comment">/* no host */</span>
+<a name="l00073"></a>00073         EP0_IDLE,
+<a name="l00074"></a>00074         EP0_IN_DATA_PHASE,
+<a name="l00075"></a>00075         EP0_OUT_DATA_PHASE,
+<a name="l00076"></a>00076         EP0_IN_STATUS_PHASE,
+<a name="l00077"></a>00077         EP0_OUT_STATUS_PHASE,
+<a name="l00078"></a>00078         EP0_STALL,
+<a name="l00079"></a>00079 } <a class="code" href="dwc__otg__pcd_8h.html#70fcb6a989e5871e16f4c1c96ffe394a">ep0state_e</a>;
+<a name="l00080"></a>00080 
+<a name="l00082"></a>00082 <span class="keyword">struct </span><a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd</a>;
+<a name="l00083"></a>00083 
+<a name="l00087"></a><a class="code" href="dwc__otg__pcd_8h.html#050b65dd6f6dfd9d8527f94bdf88a937">00087</a> <span class="keyword">typedef</span> <span class="keyword">struct </span>usb_iso_request <a class="code" href="dwc__otg__pcd_8h.html#050b65dd6f6dfd9d8527f94bdf88a937">dwc_otg_pcd_iso_request_t</a>;
+<a name="l00088"></a>00088 
+<a name="l00092"></a><a class="code" href="structdwc__otg__pcd__request.html">00092</a> <span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code" href="structdwc__otg__pcd__request.html">dwc_otg_pcd_request</a> {
+<a name="l00093"></a><a class="code" href="structdwc__otg__pcd__request.html#e0d93b64365968aa0dcf58535aecf40c">00093</a>         <span class="keywordtype">void</span> *<a class="code" href="structdwc__otg__pcd__request.html#e0d93b64365968aa0dcf58535aecf40c">priv</a>;
+<a name="l00094"></a><a class="code" href="structdwc__otg__pcd__request.html#c46438f3d95146654a25cd219d7a1d5a">00094</a>         <span class="keywordtype">void</span> *<a class="code" href="structdwc__otg__pcd__request.html#c46438f3d95146654a25cd219d7a1d5a">buf</a>;
+<a name="l00095"></a><a class="code" href="structdwc__otg__pcd__request.html#df93c8905495816eb0327b192938a4a1">00095</a>         dwc_dma_t <a class="code" href="structdwc__otg__pcd__request.html#df93c8905495816eb0327b192938a4a1">dma</a>;
+<a name="l00096"></a><a class="code" href="structdwc__otg__pcd__request.html#3dd3fcc889bf220b048023e8b05fab61">00096</a>         uint32_t <a class="code" href="structdwc__otg__pcd__request.html#3dd3fcc889bf220b048023e8b05fab61">length</a>;
+<a name="l00097"></a><a class="code" href="structdwc__otg__pcd__request.html#0fd7d659f353273d8b2b22027306a2a2">00097</a>         uint32_t <a class="code" href="structdwc__otg__pcd__request.html#0fd7d659f353273d8b2b22027306a2a2">actual</a>;
+<a name="l00098"></a><a class="code" href="structdwc__otg__pcd__request.html#c2c1832d46f417b63e41b5e23def6fc6">00098</a>         <span class="keywordtype">unsigned</span> <a class="code" href="structdwc__otg__pcd__request.html#c2c1832d46f417b63e41b5e23def6fc6">sent_zlp</a>:1;
+<a name="l00099"></a>00099 
+<a name="l00100"></a>00100          DWC_CIRCLEQ_ENTRY(<a class="code" href="structdwc__otg__pcd__request.html">dwc_otg_pcd_request</a>) queue_entry;
+<a name="l00101"></a>00101 } <a class="code" href="structdwc__otg__pcd__request.html">dwc_otg_pcd_request_t</a>;
+<a name="l00102"></a>00102 
+<a name="l00103"></a>00103 DWC_CIRCLEQ_HEAD(req_list, <a class="code" href="structdwc__otg__pcd__request.html">dwc_otg_pcd_request</a>);
+<a name="l00104"></a>00104 
+<a name="l00109"></a><a class="code" href="structdwc__otg__pcd__ep.html">00109</a> typedef struct <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep</a> {
+<a name="l00111"></a><a class="code" href="structdwc__otg__pcd__ep.html#86e27843c439dd0b1d12d9bf2dc6516f">00111</a>         <span class="keyword">const</span> usb_endpoint_descriptor_t *desc;
+<a name="l00112"></a>00112 
+<a name="l00114"></a><a class="code" href="structdwc__otg__pcd__ep.html#71f4fa571dfdc96f62fa4869e6add300">00114</a>         <span class="keyword">struct </span>req_list queue;
+<a name="l00115"></a><a class="code" href="structdwc__otg__pcd__ep.html#cce0e089118d8bf7c6278c21ded70d5a">00115</a>         <span class="keywordtype">unsigned</span> stopped:1;
+<a name="l00116"></a><a class="code" href="structdwc__otg__pcd__ep.html#510fcd32761716abec5a35594a3d3ad3">00116</a>         <span class="keywordtype">unsigned</span> disabling:1;
+<a name="l00117"></a><a class="code" href="structdwc__otg__pcd__ep.html#314db0fbde1d5eb9eae0cbe4fdef47a4">00117</a>         <span class="keywordtype">unsigned</span> <a class="code" href="structdwc__otg__pcd__request.html#df93c8905495816eb0327b192938a4a1">dma</a>:1;
+<a name="l00118"></a><a class="code" href="structdwc__otg__pcd__ep.html#bbec681b68f2f745d1cfecfedd4e64be">00118</a>         <span class="keywordtype">unsigned</span> queue_sof:1;
+<a name="l00119"></a>00119 
+<a name="l00120"></a>00120 <span class="preprocessor">#ifdef DWC_EN_ISOC</span>
+<a name="l00121"></a>00121 <span class="preprocessor"></span>
+<a name="l00122"></a><a class="code" href="structdwc__otg__pcd__ep.html#716d3c29adc54c6822935fc2ae9bef51">00122</a>         <span class="keywordtype">void</span> *iso_req_handle;
+<a name="l00123"></a>00123 <span class="preprocessor">#endif                          //_EN_ISOC_</span>
+<a name="l00124"></a>00124 <span class="preprocessor"></span>
+<a name="l00126"></a><a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">00126</a>         <a class="code" href="structdwc__ep.html">dwc_ep_t</a> <a class="code" href="structdwc__ep.html">dwc_ep</a>;
+<a name="l00127"></a>00127 
+<a name="l00129"></a><a class="code" href="structdwc__otg__pcd__ep.html#234391334e48cbd72710d08655c9ed16">00129</a>         <span class="keyword">struct </span><a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd</a> *pcd;
+<a name="l00130"></a>00130 
+<a name="l00131"></a><a class="code" href="structdwc__otg__pcd__ep.html#8c8fad971c6c3b1c54d334c7f9b2d03e">00131</a>         <span class="keywordtype">void</span> *<a class="code" href="structdwc__otg__pcd__request.html#e0d93b64365968aa0dcf58535aecf40c">priv</a>;
+<a name="l00132"></a>00132 } <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a>;
+<a name="l00133"></a>00133 
+<a name="l00137"></a><a class="code" href="structdwc__otg__pcd.html">00137</a> <span class="keyword">struct </span><a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd</a> {
+<a name="l00138"></a><a class="code" href="structdwc__otg__pcd.html#b7001dde5db2706707a860da0030d9e6">00138</a>         <span class="keyword">const</span> <span class="keyword">struct </span><a class="code" href="structdwc__otg__pcd__function__ops.html">dwc_otg_pcd_function_ops</a> *<a class="code" href="dwc__otg__pcd__linux_8c.html#9ce9b5e49c60906c189bee157dd68acd">fops</a>;
+<a name="l00140"></a><a class="code" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">00140</a>         <a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if;
+<a name="l00142"></a><a class="code" href="structdwc__otg__pcd.html#8f6963b3fb9ab83048c4c0697c90382a">00142</a>         <a class="code" href="dwc__otg__pcd_8h.html#70fcb6a989e5871e16f4c1c96ffe394a">ep0state_e</a> ep0state;
+<a name="l00144"></a><a class="code" href="structdwc__otg__pcd.html#2c8be11c3b9c7cd02684348eb028aeb5">00144</a>         <span class="keywordtype">unsigned</span> ep0_pending:1;
+<a name="l00146"></a><a class="code" href="structdwc__otg__pcd.html#cbe5c4062e140ee88f51ee916c0db0ad">00146</a>         <span class="keywordtype">unsigned</span> request_config:1;
+<a name="l00148"></a><a class="code" href="structdwc__otg__pcd.html#9d8e6d7f0ad10d580d467024e258f6f5">00148</a>         <span class="keywordtype">unsigned</span> remote_wakeup_enable:1;
+<a name="l00150"></a><a class="code" href="structdwc__otg__pcd.html#e09fc5322ac0d7deec2772984c10ae90">00150</a>         <span class="keywordtype">unsigned</span> b_hnp_enable:1;
+<a name="l00152"></a><a class="code" href="structdwc__otg__pcd.html#e8008719644bdc23040f1a1545b7117f">00152</a>         <span class="keywordtype">unsigned</span> a_hnp_support:1;
+<a name="l00154"></a><a class="code" href="structdwc__otg__pcd.html#49f2d2b04a4c07a8d53643f7681b5405">00154</a>         <span class="keywordtype">unsigned</span> a_alt_hnp_support:1;
+<a name="l00156"></a><a class="code" href="structdwc__otg__pcd.html#3a0464b4ac677a7742e9b7c0c820414c">00156</a>         <span class="keywordtype">unsigned</span> request_pending;
+<a name="l00157"></a>00157 
+<a name="l00162"></a>00162         <span class="keyword">union </span>{
+<a name="l00163"></a><a class="code" href="structdwc__otg__pcd.html#af0345bc2c877d96863ef440c923204c">00163</a>                 usb_device_request_t req;
+<a name="l00164"></a><a class="code" href="structdwc__otg__pcd.html#e4fe210f7a18b9f0c393af9cdf282d56">00164</a>                 uint32_t d32[2];
+<a name="l00165"></a>00165         } *setup_pkt;
+<a name="l00166"></a>00166 
+<a name="l00167"></a><a class="code" href="structdwc__otg__pcd.html#606d94ec61cca4c21e4dc9cb2e3b7064">00167</a>         dwc_dma_t setup_pkt_dma_handle;
+<a name="l00168"></a>00168 
+<a name="l00170"></a><a class="code" href="structdwc__otg__pcd.html#ca247241f78970f27e5c964fc04d47c8">00170</a>         uint16_t *status_buf;
+<a name="l00171"></a><a class="code" href="structdwc__otg__pcd.html#c3880dd4ce15c515ba37b90b6e7fd293">00171</a>         dwc_dma_t status_buf_dma_handle;
+<a name="l00172"></a>00172 
+<a name="l00174"></a><a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">00174</a>         <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> ep0;
+<a name="l00175"></a>00175 
+<a name="l00177"></a><a class="code" href="structdwc__otg__pcd.html#dbfc8c424ea3add38db96fa87219caa8">00177</a>         <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> in_ep[<a class="code" href="dwc__otg__core__if_8h.html#bfb88b45545f7685f668ac2f545674ec">MAX_EPS_CHANNELS</a> - 1];
+<a name="l00179"></a><a class="code" href="structdwc__otg__pcd.html#b9e49a1d1fbca5ba9523e27c7108df30">00179</a>         <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> out_ep[<a class="code" href="dwc__otg__core__if_8h.html#bfb88b45545f7685f668ac2f545674ec">MAX_EPS_CHANNELS</a> - 1];
+<a name="l00181"></a>00181 <span class="comment">//        unsigned      num_eps : 4;</span>
+<a name="l00182"></a><a class="code" href="structdwc__otg__pcd.html#5d450e4d06659ab2f3b18e5c816776e4">00182</a>         dwc_spinlock_t *lock;
+<a name="l00185"></a><a class="code" href="structdwc__otg__pcd.html#466fb6ae524fc970f164701db2e70246">00185</a>         dwc_timer_t *srp_timer;
+<a name="l00186"></a>00186 
+<a name="l00190"></a><a class="code" href="structdwc__otg__pcd.html#d1aed2eb03a93032a1ce80e3145bb81e">00190</a>         dwc_tasklet_t *test_mode_tasklet;
+<a name="l00191"></a>00191 
+<a name="l00193"></a><a class="code" href="structdwc__otg__pcd.html#9b45cd00cd5835aba4236529a04b28f1">00193</a>         dwc_tasklet_t *start_xfer_tasklet;
+<a name="l00194"></a>00194 
+<a name="l00196"></a><a class="code" href="structdwc__otg__pcd.html#577c57ee60c2ef42dce7791c85d50394">00196</a>         <span class="keywordtype">unsigned</span> test_mode;
+<a name="l00200"></a>00200 <span class="preprocessor">#ifdef DWC_UTE_CFI</span>
+<a name="l00201"></a>00201 <span class="preprocessor"></span>        <span class="keyword">struct </span><a class="code" href="structcfiobject.html">cfiobject</a> *cfi;
+<a name="l00202"></a>00202 <span class="preprocessor">#endif</span>
+<a name="l00203"></a>00203 <span class="preprocessor"></span>
+<a name="l00204"></a>00204 };
+<a name="l00205"></a>00205 
+<a name="l00206"></a>00206 <span class="comment">//FIXME this functions should be static, and this prototypes should be removed</span>
+<a name="l00207"></a>00207 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd_8c.html#e8ef6f3d831b89a753d93489827949d3">dwc_otg_request_nuke</a>(<a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> * ep);
+<a name="l00208"></a>00208 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd_8c.html#5c9b20abc81e0f860a8f23c90b10b59e">dwc_otg_request_done</a>(<a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> * ep,
+<a name="l00209"></a>00209                                  <a class="code" href="structdwc__otg__pcd__request.html">dwc_otg_pcd_request_t</a> * req, int32_t status);
+<a name="l00210"></a>00210 
+<a name="l00211"></a>00211 <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd_8c.html#b4e2c352426923d4bd519cf18b68206d">dwc_otg_iso_buffer_done</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * <a class="code" href="structcfiobject.html#bab38f9fb74c1332c70029000c7d3818">pcd</a>, <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> * ep,
+<a name="l00212"></a>00212                              <span class="keywordtype">void</span> *req_handle);
+<a name="l00213"></a>00213 
+<a name="l00214"></a>00214 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd_8h.html#9d6d6e24faab6478aef9e2217c9b5ab9">do_test_mode</a>(<span class="keywordtype">void</span> *data);
+<a name="l00215"></a>00215 <span class="preprocessor">#endif</span>
+<a name="l00216"></a>00216 <span class="preprocessor"></span><span class="preprocessor">#endif                          </span><span class="comment">/* DWC_HOST_ONLY */</span>
+</pre></div><hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd_8h.html b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd_8h.html
new file mode 100644
index 000000000000..7b122bb57d88
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd_8h.html
@@ -0,0 +1,254 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd.h File Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<h1>dwc_otg_pcd.h File Reference</h1>This file contains the structures, constants, and interfaces for the Perpherial Contoller Driver (PCD). <a href="#_details">More...</a>
+<p>
+<code>#include &quot;usb.h&quot;</code><br>
+<code>#include &quot;<a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a>&quot;</code><br>
+<code>#include &quot;<a class="el" href="dwc__otg__pcd__if_8h-source.html">dwc_otg_pcd_if.h</a>&quot;</code><br>
+
+<p>
+<a href="dwc__otg__pcd_8h-source.html">Go to the source code of this file.</a><table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Structures</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__pcd__request.html">dwc_otg_pcd_request</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">DWC_otg request structure.  <a href="structdwc__otg__pcd__request.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">PCD EP structure.  <a href="structdwc__otg__pcd__ep.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">DWC_otg PCD Structure.  <a href="structdwc__otg__pcd.html#_details">More...</a><br></td></tr>
+<tr><td colspan="2"><br><h2>Defines</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ed26bb67f5785dc6e70289976637a310"></a><!-- doxytag: member="dwc_otg_pcd.h::__DWC_PCD_H__" ref="ed26bb67f5785dc6e70289976637a310" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8h.html#ed26bb67f5785dc6e70289976637a310">__DWC_PCD_H__</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="6dad4d4462e9819753acfc601889faec"></a><!-- doxytag: member="dwc_otg_pcd.h::DDMA_MAX_TRANSFER_SIZE" ref="6dad4d4462e9819753acfc601889faec" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8h.html#6dad4d4462e9819753acfc601889faec">DDMA_MAX_TRANSFER_SIZE</a>&nbsp;&nbsp;&nbsp;65535</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Max Transfer size for any EP. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="a1c5dc8973b5c039fd77b1e250ce29e2"></a><!-- doxytag: member="dwc_otg_pcd.h::MAX_DMA_DESC_CNT" ref="a1c5dc8973b5c039fd77b1e250ce29e2" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8h.html#a1c5dc8973b5c039fd77b1e250ce29e2">MAX_DMA_DESC_CNT</a>&nbsp;&nbsp;&nbsp;64</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Max DMA Descriptor count for any EP. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="464549f9f4484651efe25b1a03692d72"></a><!-- doxytag: member="dwc_otg_pcd.h::GET_CORE_IF" ref="464549f9f4484651efe25b1a03692d72" args="(_pcd)" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(_pcd)&nbsp;&nbsp;&nbsp;(_pcd-&gt;core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get the pointer to the core_if from the pcd pointer. <br></td></tr>
+<tr><td colspan="2"><br><h2>Typedefs</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="70fcb6a989e5871e16f4c1c96ffe394a"></a><!-- doxytag: member="dwc_otg_pcd.h::ep0state_e" ref="70fcb6a989e5871e16f4c1c96ffe394a" args="" -->
+typedef enum <a class="el" href="dwc__otg__pcd_8h.html#f286abbd9be76db05fee7aebfeb61865">ep0_state</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8h.html#70fcb6a989e5871e16f4c1c96ffe394a">ep0state_e</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">States of EP0. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="050b65dd6f6dfd9d8527f94bdf88a937"></a><!-- doxytag: member="dwc_otg_pcd.h::dwc_otg_pcd_iso_request_t" ref="050b65dd6f6dfd9d8527f94bdf88a937" args="" -->
+typedef usb_iso_request&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8h.html#050b65dd6f6dfd9d8527f94bdf88a937">dwc_otg_pcd_iso_request_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">DWC_otg iso request structure. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef <a class="el" href="structdwc__otg__pcd__request.html">dwc_otg_pcd_request</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8h.html#1253ddf26039ef0a68df3eb5423f65da">dwc_otg_pcd_request_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">DWC_otg request structure.  <a href="#1253ddf26039ef0a68df3eb5423f65da"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef <a class="el" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8h.html#fa97bfbab3706fa510ecff969ce39756">dwc_otg_pcd_ep_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">PCD EP structure.  <a href="#fa97bfbab3706fa510ecff969ce39756"></a><br></td></tr>
+<tr><td colspan="2"><br><h2>Enumerations</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">enum &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8h.html#f286abbd9be76db05fee7aebfeb61865">ep0_state</a> { <br>
+&nbsp;&nbsp;<b>EP0_DISCONNECT</b>, 
+<b>EP0_IDLE</b>, 
+<b>EP0_IN_DATA_PHASE</b>, 
+<b>EP0_OUT_DATA_PHASE</b>, 
+<br>
+&nbsp;&nbsp;<b>EP0_IN_STATUS_PHASE</b>, 
+<b>EP0_OUT_STATUS_PHASE</b>, 
+<b>EP0_STALL</b>
+<br>
+ }</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">States of EP0. <br></td></tr>
+<tr><td colspan="2"><br><h2>Functions</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="649f0875764e42b69accb4ad46a45694"></a><!-- doxytag: member="dwc_otg_pcd.h::DWC_CIRCLEQ_HEAD" ref="649f0875764e42b69accb4ad46a45694" args="(req_list, dwc_otg_pcd_request)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_CIRCLEQ_HEAD</b> (req_list, <a class="el" href="structdwc__otg__pcd__request.html">dwc_otg_pcd_request</a>)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e8ef6f3d831b89a753d93489827949d3"></a><!-- doxytag: member="dwc_otg_pcd.h::dwc_otg_request_nuke" ref="e8ef6f3d831b89a753d93489827949d3" args="(dwc_otg_pcd_ep_t *ep)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8h.html#e8ef6f3d831b89a753d93489827949d3">dwc_otg_request_nuke</a> (<a class="el" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *ep)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function terminates all the requsts in the EP request queue. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8h.html#5c9b20abc81e0f860a8f23c90b10b59e">dwc_otg_request_done</a> (<a class="el" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *ep, <a class="el" href="structdwc__otg__pcd__request.html">dwc_otg_pcd_request_t</a> *req, int32_t status)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function completes a request.  <a href="#5c9b20abc81e0f860a8f23c90b10b59e"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8h.html#b4e2c352426923d4bd519cf18b68206d">dwc_otg_iso_buffer_done</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, <a class="el" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *ep, void *req_handle)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function is used for perodical data exchnage between PCD and gadget drivers.  <a href="#b4e2c352426923d4bd519cf18b68206d"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd_8h.html#9d6d6e24faab6478aef9e2217c9b5ab9">do_test_mode</a> (void *data)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function is called when the SET_FEATURE TEST_MODE Setup packet is sent from the host.  <a href="#9d6d6e24faab6478aef9e2217c9b5ab9"></a><br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This file contains the structures, constants, and interfaces for the Perpherial Contoller Driver (PCD). 
+<p>
+The Peripheral Controller Driver (PCD) for Linux will implement the Gadget API, so that the existing Gadget drivers can be used. For the Mass Storage Function driver the File-backed USB Storage Gadget (FBS) driver will be used. The FBS driver supports the Control-Bulk (CB), Control-Bulk-Interrupt (CBI), and Bulk-Only transports. 
+<p>
+Definition in file <a class="el" href="dwc__otg__pcd_8h-source.html">dwc_otg_pcd.h</a>.<hr><h2>Typedef Documentation</h2>
+<a class="anchor" name="1253ddf26039ef0a68df3eb5423f65da"></a><!-- doxytag: member="dwc_otg_pcd.h::dwc_otg_pcd_request_t" ref="1253ddf26039ef0a68df3eb5423f65da" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef struct <a class="el" href="structdwc__otg__pcd__request.html">dwc_otg_pcd_request</a>  <a class="el" href="structdwc__otg__pcd__request.html">dwc_otg_pcd_request_t</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+DWC_otg request structure. 
+<p>
+This structure is a list of requests. 
+</div>
+</div><p>
+<a class="anchor" name="fa97bfbab3706fa510ecff969ce39756"></a><!-- doxytag: member="dwc_otg_pcd.h::dwc_otg_pcd_ep_t" ref="fa97bfbab3706fa510ecff969ce39756" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef struct <a class="el" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep</a>  <a class="el" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+PCD EP structure. 
+<p>
+This structure describes an EP, there is an array of EPs in the PCD structure. 
+</div>
+</div><p>
+<hr><h2>Function Documentation</h2>
+<a class="anchor" name="5c9b20abc81e0f860a8f23c90b10b59e"></a><!-- doxytag: member="dwc_otg_pcd.h::dwc_otg_request_done" ref="5c9b20abc81e0f860a8f23c90b10b59e" args="(dwc_otg_pcd_ep_t *ep, dwc_otg_pcd_request_t *req, int32_t status)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_request_done           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>ep</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd__request.html">dwc_otg_pcd_request_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>req</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&nbsp;</td>
+          <td class="paramname"> <em>status</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function completes a request. 
+<p>
+It call's the request call back. 
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd_8c-source.html#l00078">78</a> of file <a class="el" href="dwc__otg__pcd_8c-source.html">dwc_otg_pcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="b4e2c352426923d4bd519cf18b68206d"></a><!-- doxytag: member="dwc_otg_pcd.h::dwc_otg_iso_buffer_done" ref="b4e2c352426923d4bd519cf18b68206d" args="(dwc_otg_pcd_t *pcd, dwc_otg_pcd_ep_t *ep, void *req_handle)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_iso_buffer_done           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>ep</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>req_handle</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function is used for perodical data exchnage between PCD and gadget drivers. 
+<p>
+for Isochronous EPs<p>
+<ul>
+<li>Every time a sync period completes this function is called to perform data exchange between PCD and gadget </li></ul>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd_8c-source.html#l00830">830</a> of file <a class="el" href="dwc__otg__pcd_8c-source.html">dwc_otg_pcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="9d6d6e24faab6478aef9e2217c9b5ab9"></a><!-- doxytag: member="dwc_otg_pcd.h::do_test_mode" ref="9d6d6e24faab6478aef9e2217c9b5ab9" args="(void *data)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void do_test_mode           </td>
+          <td>(</td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>data</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function is called when the SET_FEATURE TEST_MODE Setup packet is sent from the host. 
+<p>
+The Device Control register is written with the Test Mode bits set to the specified Test Mode. This is done as a tasklet so that the "Status" phase of the control transfer completes before transmitting the TEST packets.<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000033">Todo:</a></b></dt><dd>This has not been tested since the tasklet struct was put into the PCD struct!</dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__intr_8c-source.html#l01284">1284</a> of file <a class="el" href="dwc__otg__pcd__intr_8c-source.html">dwc_otg_pcd_intr.c</a>.
+</div>
+</div><p>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__if_8h-source.html b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__if_8h-source.html
new file mode 100644
index 000000000000..e8baf1de306a
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__if_8h-source.html
@@ -0,0 +1,174 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd_if.h Source File</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<h1>dwc_otg_pcd_if.h</h1><a href="dwc__otg__pcd__if_8h.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">/* ==========================================================================</span>
+<a name="l00002"></a>00002 <span class="comment"> * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_if.h $</span>
+<a name="l00003"></a>00003 <span class="comment"> * $Revision: #6 $</span>
+<a name="l00004"></a>00004 <span class="comment"> * $Date: 2009/04/03 $</span>
+<a name="l00005"></a>00005 <span class="comment"> * $Change: 1225059 $</span>
+<a name="l00006"></a>00006 <span class="comment"> *</span>
+<a name="l00007"></a>00007 <span class="comment"> * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,</span>
+<a name="l00008"></a>00008 <span class="comment"> * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless</span>
+<a name="l00009"></a>00009 <span class="comment"> * otherwise expressly agreed to in writing between Synopsys and you.</span>
+<a name="l00010"></a>00010 <span class="comment"> *</span>
+<a name="l00011"></a>00011 <span class="comment"> * The Software IS NOT an item of Licensed Software or Licensed Product under</span>
+<a name="l00012"></a>00012 <span class="comment"> * any End User Software License Agreement or Agreement for Licensed Product</span>
+<a name="l00013"></a>00013 <span class="comment"> * with Synopsys or any supplement thereto. You are permitted to use and</span>
+<a name="l00014"></a>00014 <span class="comment"> * redistribute this Software in source and binary forms, with or without</span>
+<a name="l00015"></a>00015 <span class="comment"> * modification, provided that redistributions of source code must retain this</span>
+<a name="l00016"></a>00016 <span class="comment"> * notice. You may not view, use, disclose, copy or distribute this file or</span>
+<a name="l00017"></a>00017 <span class="comment"> * any information contained herein except pursuant to this license grant from</span>
+<a name="l00018"></a>00018 <span class="comment"> * Synopsys. If you do not agree with this notice, including the disclaimer</span>
+<a name="l00019"></a>00019 <span class="comment"> * below, then you are not authorized to use the Software.</span>
+<a name="l00020"></a>00020 <span class="comment"> *</span>
+<a name="l00021"></a>00021 <span class="comment"> * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS</span>
+<a name="l00022"></a>00022 <span class="comment"> * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE</span>
+<a name="l00023"></a>00023 <span class="comment"> * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE</span>
+<a name="l00024"></a>00024 <span class="comment"> * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,</span>
+<a name="l00025"></a>00025 <span class="comment"> * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES</span>
+<a name="l00026"></a>00026 <span class="comment"> * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR</span>
+<a name="l00027"></a>00027 <span class="comment"> * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER</span>
+<a name="l00028"></a>00028 <span class="comment"> * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT</span>
+<a name="l00029"></a>00029 <span class="comment"> * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY</span>
+<a name="l00030"></a>00030 <span class="comment"> * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH</span>
+<a name="l00031"></a>00031 <span class="comment"> * DAMAGE.</span>
+<a name="l00032"></a>00032 <span class="comment"> * ========================================================================== */</span>
+<a name="l00033"></a>00033 <span class="preprocessor">#ifndef DWC_HOST_ONLY</span>
+<a name="l00034"></a>00034 <span class="preprocessor"></span>
+<a name="l00035"></a>00035 <span class="preprocessor">#if !defined(__DWC_PCD_IF_H__)</span>
+<a name="l00036"></a><a class="code" href="dwc__otg__pcd__if_8h.html#f647f1720e56adb91588a6e55179dec5">00036</a> <span class="preprocessor"></span><span class="preprocessor">#define __DWC_PCD_IF_H__</span>
+<a name="l00037"></a>00037 <span class="preprocessor"></span>
+<a name="l00038"></a>00038 <span class="preprocessor">#include "dwc_os.h"</span>
+<a name="l00039"></a>00039 <span class="preprocessor">#include "<a class="code" href="dwc__otg__core__if_8h.html">dwc_otg_core_if.h</a>"</span>
+<a name="l00040"></a>00040 
+<a name="l00045"></a>00045 <span class="keyword">struct </span><a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd</a>;
+<a name="l00046"></a><a class="code" href="dwc__otg__pcd__if_8h.html#f6503e2b4469b327ae64f650bb5721cb">00046</a> <span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd</a> <a class="code" href="dwc__otg__pcd__if_8h.html#f6503e2b4469b327ae64f650bb5721cb">dwc_otg_pcd_t</a>;
+<a name="l00047"></a>00047 
+<a name="l00049"></a><a class="code" href="dwc__otg__pcd__if_8h.html#8fbbba66f80923843e99def6064a570f">00049</a> <span class="preprocessor">#define MAX_EP0_SIZE    64</span>
+<a name="l00050"></a>00050 <span class="preprocessor"></span>
+<a name="l00051"></a><a class="code" href="dwc__otg__pcd__if_8h.html#cf2c48a3393f5ae43e8d88d01c2d204a">00051</a> <span class="preprocessor">#define MAX_PACKET_SIZE 1024</span>
+<a name="l00052"></a>00052 <span class="preprocessor"></span>
+<a name="l00061"></a><a class="code" href="dwc__otg__pcd__if_8h.html#9c448e9fa004f873c281f46f5e5a597d">00061</a> <span class="keyword">typedef</span> int (*<a class="code" href="dwc__otg__pcd__if_8h.html#9c448e9fa004f873c281f46f5e5a597d">dwc_completion_cb_t</a>) (<a class="code" href="dwc__otg__pcd__if_8h.html#f6503e2b4469b327ae64f650bb5721cb">dwc_otg_pcd_t</a> * pcd, <span class="keywordtype">void</span> *ep_handle,
+<a name="l00062"></a>00062                                     <span class="keywordtype">void</span> *req_handle, int32_t status,
+<a name="l00063"></a>00063                                     uint32_t actual);
+<a name="l00071"></a><a class="code" href="dwc__otg__pcd__if_8h.html#a6f91e357c7c7782afa7db03e95a52ed">00071</a> <span class="keyword">typedef</span> int (*<a class="code" href="dwc__otg__pcd__if_8h.html#a6f91e357c7c7782afa7db03e95a52ed">dwc_isoc_completion_cb_t</a>) (<a class="code" href="dwc__otg__pcd__if_8h.html#f6503e2b4469b327ae64f650bb5721cb">dwc_otg_pcd_t</a> * pcd, <span class="keywordtype">void</span> *ep_handle,
+<a name="l00072"></a>00072                                          <span class="keywordtype">void</span> *req_handle, <span class="keywordtype">int</span> proc_buf_num);
+<a name="l00081"></a><a class="code" href="dwc__otg__pcd__if_8h.html#a9145aeaa27da4fa1befb424f927fde7">00081</a> <span class="keyword">typedef</span> int (*<a class="code" href="dwc__otg__pcd__if_8h.html#a9145aeaa27da4fa1befb424f927fde7">dwc_setup_cb_t</a>) (<a class="code" href="dwc__otg__pcd__if_8h.html#f6503e2b4469b327ae64f650bb5721cb">dwc_otg_pcd_t</a> * pcd, uint8_t * bytes);
+<a name="l00086"></a><a class="code" href="dwc__otg__pcd__if_8h.html#959f051498d2957d47cb0d27b42546aa">00086</a> <span class="keyword">typedef</span> int (*<a class="code" href="dwc__otg__pcd__if_8h.html#959f051498d2957d47cb0d27b42546aa">dwc_disconnect_cb_t</a>) (<a class="code" href="dwc__otg__pcd__if_8h.html#f6503e2b4469b327ae64f650bb5721cb">dwc_otg_pcd_t</a> * pcd);
+<a name="l00088"></a><a class="code" href="dwc__otg__pcd__if_8h.html#4808152d074c472f4fb1aa7b662e3004">00088</a> <span class="keyword">typedef</span> int (*<a class="code" href="dwc__otg__pcd__if_8h.html#4808152d074c472f4fb1aa7b662e3004">dwc_connect_cb_t</a>) (<a class="code" href="dwc__otg__pcd__if_8h.html#f6503e2b4469b327ae64f650bb5721cb">dwc_otg_pcd_t</a> * pcd, <span class="keywordtype">int</span> speed);
+<a name="l00090"></a><a class="code" href="dwc__otg__pcd__if_8h.html#ddcaadb93595803ca5f2ffb74cd88619">00090</a> <span class="keyword">typedef</span> int (*<a class="code" href="dwc__otg__pcd__if_8h.html#ddcaadb93595803ca5f2ffb74cd88619">dwc_suspend_cb_t</a>) (<a class="code" href="dwc__otg__pcd__if_8h.html#f6503e2b4469b327ae64f650bb5721cb">dwc_otg_pcd_t</a> * pcd);
+<a name="l00093"></a><a class="code" href="dwc__otg__pcd__if_8h.html#fc48d3df458c446cc0ace0a7d7755c67">00093</a> <span class="keyword">typedef</span> int (*<a class="code" href="dwc__otg__pcd__if_8h.html#fc48d3df458c446cc0ace0a7d7755c67">dwc_sleep_cb_t</a>) (<a class="code" href="dwc__otg__pcd__if_8h.html#f6503e2b4469b327ae64f650bb5721cb">dwc_otg_pcd_t</a> * pcd);
+<a name="l00096"></a><a class="code" href="dwc__otg__pcd__if_8h.html#44d7ec17e6e087e44dd7c372e01fcfb2">00096</a> <span class="keyword">typedef</span> int (*<a class="code" href="dwc__otg__pcd__if_8h.html#44d7ec17e6e087e44dd7c372e01fcfb2">dwc_resume_cb_t</a>) (<a class="code" href="dwc__otg__pcd__if_8h.html#f6503e2b4469b327ae64f650bb5721cb">dwc_otg_pcd_t</a> * pcd);
+<a name="l00100"></a><a class="code" href="dwc__otg__pcd__if_8h.html#eef0b7f44036d8164121ed079710058b">00100</a> <span class="keyword">typedef</span> int (*<a class="code" href="dwc__otg__pcd__if_8h.html#eef0b7f44036d8164121ed079710058b">dwc_hnp_params_changed_cb_t</a>) (<a class="code" href="dwc__otg__pcd__if_8h.html#f6503e2b4469b327ae64f650bb5721cb">dwc_otg_pcd_t</a> * pcd);
+<a name="l00102"></a><a class="code" href="dwc__otg__pcd__if_8h.html#f6bba5b7b3d3ad67fbf2161717281fdd">00102</a> <span class="keyword">typedef</span> int (*<a class="code" href="dwc__otg__pcd__if_8h.html#f6bba5b7b3d3ad67fbf2161717281fdd">dwc_reset_cb_t</a>) (<a class="code" href="dwc__otg__pcd__if_8h.html#f6503e2b4469b327ae64f650bb5721cb">dwc_otg_pcd_t</a> * pcd);
+<a name="l00103"></a>00103 
+<a name="l00104"></a><a class="code" href="dwc__otg__pcd__if_8h.html#7d75df2095c14a2d985df8027359e440">00104</a> <span class="keyword">typedef</span> int (*<a class="code" href="dwc__otg__pcd__if_8h.html#7d75df2095c14a2d985df8027359e440">cfi_setup_cb_t</a>) (<a class="code" href="dwc__otg__pcd__if_8h.html#f6503e2b4469b327ae64f650bb5721cb">dwc_otg_pcd_t</a> * pcd, <span class="keywordtype">void</span> *ctrl_req_bytes);
+<a name="l00105"></a>00105 
+<a name="l00107"></a><a class="code" href="structdwc__otg__pcd__function__ops.html">00107</a> <span class="keyword">struct </span><a class="code" href="structdwc__otg__pcd__function__ops.html">dwc_otg_pcd_function_ops</a> {
+<a name="l00108"></a><a class="code" href="structdwc__otg__pcd__function__ops.html#4d3df508947b8ba75c5537617227cf9c">00108</a>         <a class="code" href="dwc__otg__pcd__if_8h.html#4808152d074c472f4fb1aa7b662e3004">dwc_connect_cb_t</a> <a class="code" href="structdwc__otg__pcd__function__ops.html#4d3df508947b8ba75c5537617227cf9c">connect</a>;
+<a name="l00109"></a><a class="code" href="structdwc__otg__pcd__function__ops.html#51b0e7dcf19398bad4f0ec459b43077a">00109</a>         <a class="code" href="dwc__otg__pcd__if_8h.html#959f051498d2957d47cb0d27b42546aa">dwc_disconnect_cb_t</a> <a class="code" href="structdwc__otg__pcd__function__ops.html#51b0e7dcf19398bad4f0ec459b43077a">disconnect</a>;
+<a name="l00110"></a><a class="code" href="structdwc__otg__pcd__function__ops.html#e99e932440749d9464e008cef78e808d">00110</a>         <a class="code" href="dwc__otg__pcd__if_8h.html#a9145aeaa27da4fa1befb424f927fde7">dwc_setup_cb_t</a> <a class="code" href="structdwc__otg__pcd__function__ops.html#e99e932440749d9464e008cef78e808d">setup</a>;
+<a name="l00111"></a><a class="code" href="structdwc__otg__pcd__function__ops.html#126db5e83cd3cc03f303eb3da668816f">00111</a>         <a class="code" href="dwc__otg__pcd__if_8h.html#9c448e9fa004f873c281f46f5e5a597d">dwc_completion_cb_t</a> <a class="code" href="structdwc__otg__pcd__function__ops.html#126db5e83cd3cc03f303eb3da668816f">complete</a>;
+<a name="l00112"></a><a class="code" href="structdwc__otg__pcd__function__ops.html#9714dfa4909221c0b937a9bcadf97339">00112</a>         <a class="code" href="dwc__otg__pcd__if_8h.html#a6f91e357c7c7782afa7db03e95a52ed">dwc_isoc_completion_cb_t</a> <a class="code" href="structdwc__otg__pcd__function__ops.html#9714dfa4909221c0b937a9bcadf97339">isoc_complete</a>;
+<a name="l00113"></a><a class="code" href="structdwc__otg__pcd__function__ops.html#fef8ed359353cb84b7c5ac641d54d296">00113</a>         <a class="code" href="dwc__otg__pcd__if_8h.html#ddcaadb93595803ca5f2ffb74cd88619">dwc_suspend_cb_t</a> <a class="code" href="structdwc__otg__pcd__function__ops.html#fef8ed359353cb84b7c5ac641d54d296">suspend</a>;
+<a name="l00114"></a><a class="code" href="structdwc__otg__pcd__function__ops.html#9b7666c7835bd611f87095d43b104f68">00114</a>         <a class="code" href="dwc__otg__pcd__if_8h.html#fc48d3df458c446cc0ace0a7d7755c67">dwc_sleep_cb_t</a> <a class="code" href="structdwc__otg__pcd__function__ops.html#9b7666c7835bd611f87095d43b104f68">sleep</a>;
+<a name="l00115"></a><a class="code" href="structdwc__otg__pcd__function__ops.html#654870eb85c5356b6a97a514645e5d8c">00115</a>         <a class="code" href="dwc__otg__pcd__if_8h.html#44d7ec17e6e087e44dd7c372e01fcfb2">dwc_resume_cb_t</a> <a class="code" href="structdwc__otg__pcd__function__ops.html#654870eb85c5356b6a97a514645e5d8c">resume</a>;
+<a name="l00116"></a><a class="code" href="structdwc__otg__pcd__function__ops.html#781da247a225731f7e8367e843081fe0">00116</a>         <a class="code" href="dwc__otg__pcd__if_8h.html#f6bba5b7b3d3ad67fbf2161717281fdd">dwc_reset_cb_t</a> <a class="code" href="structdwc__otg__pcd__function__ops.html#781da247a225731f7e8367e843081fe0">reset</a>;
+<a name="l00117"></a><a class="code" href="structdwc__otg__pcd__function__ops.html#db190030830b55d72b36255980be08d7">00117</a>         <a class="code" href="dwc__otg__pcd__if_8h.html#eef0b7f44036d8164121ed079710058b">dwc_hnp_params_changed_cb_t</a> <a class="code" href="structdwc__otg__pcd__function__ops.html#db190030830b55d72b36255980be08d7">hnp_changed</a>;
+<a name="l00118"></a><a class="code" href="structdwc__otg__pcd__function__ops.html#e717e78fcf05e0de9c6d478fee1afa87">00118</a>         <a class="code" href="dwc__otg__pcd__if_8h.html#7d75df2095c14a2d985df8027359e440">cfi_setup_cb_t</a> <a class="code" href="structdwc__otg__pcd__function__ops.html#e717e78fcf05e0de9c6d478fee1afa87">cfi_setup</a>;
+<a name="l00119"></a>00119 };
+<a name="l00130"></a>00130 <span class="keyword">extern</span> <a class="code" href="dwc__otg__pcd__if_8h.html#f6503e2b4469b327ae64f650bb5721cb">dwc_otg_pcd_t</a> *<a class="code" href="dwc__otg__pcd_8c.html#fc3d8c56afa93b474180cc1eb8624ab8">dwc_otg_pcd_init</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if);
+<a name="l00131"></a>00131 
+<a name="l00136"></a>00136 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd_8c.html#aaab1535dacd5e947c1f9343d9b3ddf5">dwc_otg_pcd_remove</a>(<a class="code" href="dwc__otg__pcd__if_8h.html#f6503e2b4469b327ae64f650bb5721cb">dwc_otg_pcd_t</a> * pcd);
+<a name="l00137"></a>00137 
+<a name="l00143"></a>00143 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd_8c.html#187209231d66bc200444c0d52331d276">dwc_otg_pcd_start</a>(<a class="code" href="dwc__otg__pcd__if_8h.html#f6503e2b4469b327ae64f650bb5721cb">dwc_otg_pcd_t</a> * pcd,
+<a name="l00144"></a>00144                               <span class="keyword">const</span> <span class="keyword">struct</span> <a class="code" href="structdwc__otg__pcd__function__ops.html">dwc_otg_pcd_function_ops</a> *<a class="code" href="dwc__otg__pcd__linux_8c.html#9ce9b5e49c60906c189bee157dd68acd">fops</a>);
+<a name="l00145"></a>00145 
+<a name="l00161"></a>00161 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__pcd_8c.html#b9168f11717bdc672d9a29226779e523">dwc_otg_pcd_ep_enable</a>(<a class="code" href="dwc__otg__pcd__if_8h.html#f6503e2b4469b327ae64f650bb5721cb">dwc_otg_pcd_t</a> * pcd,
+<a name="l00162"></a>00162                                  <span class="keyword">const</span> uint8_t * ep_desc, <span class="keywordtype">void</span> *ep_handle);
+<a name="l00163"></a>00163 
+<a name="l00169"></a>00169 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__pcd_8c.html#8a2f791c79320c8c4657715a672822a4">dwc_otg_pcd_ep_disable</a>(<a class="code" href="dwc__otg__pcd__if_8h.html#f6503e2b4469b327ae64f650bb5721cb">dwc_otg_pcd_t</a> * pcd, <span class="keywordtype">void</span> *ep_handle);
+<a name="l00170"></a>00170 
+<a name="l00189"></a>00189 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__pcd_8c.html#09f3d77397aa7d22a1ca32e26c8aedea">dwc_otg_pcd_ep_queue</a>(<a class="code" href="dwc__otg__pcd__if_8h.html#f6503e2b4469b327ae64f650bb5721cb">dwc_otg_pcd_t</a> * pcd, <span class="keywordtype">void</span> *ep_handle,
+<a name="l00190"></a>00190                                 uint8_t * buf, dwc_dma_t dma_buf,
+<a name="l00191"></a>00191                                 uint32_t buflen, <span class="keywordtype">int</span> zero, <span class="keywordtype">void</span> *req_handle,
+<a name="l00192"></a>00192                                 <span class="keywordtype">int</span> atomic_alloc);
+<a name="l00193"></a>00193 
+<a name="l00199"></a>00199 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__pcd_8c.html#aa7546ce68d6fda67bb4cda0f69eedf3">dwc_otg_pcd_ep_dequeue</a>(<a class="code" href="dwc__otg__pcd__if_8h.html#f6503e2b4469b327ae64f650bb5721cb">dwc_otg_pcd_t</a> * pcd, <span class="keywordtype">void</span> *ep_handle,
+<a name="l00200"></a>00200                                   <span class="keywordtype">void</span> *req_handle);
+<a name="l00201"></a>00201 
+<a name="l00208"></a>00208 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__pcd_8c.html#f7d01b4772f08c6a08f4a22300a7b43b">dwc_otg_pcd_ep_halt</a>(<a class="code" href="dwc__otg__pcd__if_8h.html#f6503e2b4469b327ae64f650bb5721cb">dwc_otg_pcd_t</a> * pcd, <span class="keywordtype">void</span> *ep_handle, <span class="keywordtype">int</span> value);
+<a name="l00209"></a>00209 
+<a name="l00211"></a>00211 <span class="keyword">extern</span> int32_t <a class="code" href="dwc__otg__pcd__if_8h.html#fc60361217d0c5c089f4036d73690689">dwc_otg_pcd_handle_intr</a>(<a class="code" href="dwc__otg__pcd__if_8h.html#f6503e2b4469b327ae64f650bb5721cb">dwc_otg_pcd_t</a> * pcd);
+<a name="l00212"></a>00212 
+<a name="l00214"></a>00214 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__pcd_8c.html#04876b716043a853b379d72ff3a215e5">dwc_otg_pcd_get_frame_number</a>(<a class="code" href="dwc__otg__pcd__if_8h.html#f6503e2b4469b327ae64f650bb5721cb">dwc_otg_pcd_t</a> * pcd);
+<a name="l00215"></a>00215 
+<a name="l00242"></a>00242 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__pcd_8c.html#e0a690ac031f8f06c2e7fb10b4633b05">dwc_otg_pcd_iso_ep_start</a>(<a class="code" href="dwc__otg__pcd__if_8h.html#f6503e2b4469b327ae64f650bb5721cb">dwc_otg_pcd_t</a> * pcd, <span class="keywordtype">void</span> *ep_handle,
+<a name="l00243"></a>00243                                     uint8_t * buf0, uint8_t * buf1,
+<a name="l00244"></a>00244                                     dwc_dma_t dma0, dwc_dma_t dma1,
+<a name="l00245"></a>00245                                     <span class="keywordtype">int</span> sync_frame, <span class="keywordtype">int</span> dp_frame,
+<a name="l00246"></a>00246                                     <span class="keywordtype">int</span> data_per_frame, <span class="keywordtype">int</span> start_frame,
+<a name="l00247"></a>00247                                     <span class="keywordtype">int</span> buf_proc_intrvl, <span class="keywordtype">void</span> *req_handle,
+<a name="l00248"></a>00248                                     <span class="keywordtype">int</span> atomic_alloc);
+<a name="l00249"></a>00249 
+<a name="l00259"></a>00259 <span class="keywordtype">int</span> <a class="code" href="dwc__otg__pcd_8c.html#5098f89da28c6b450e7e10b31441b945">dwc_otg_pcd_iso_ep_stop</a>(<a class="code" href="dwc__otg__pcd__if_8h.html#f6503e2b4469b327ae64f650bb5721cb">dwc_otg_pcd_t</a> * pcd, <span class="keywordtype">void</span> *ep_handle,
+<a name="l00260"></a>00260                             <span class="keywordtype">void</span> *req_handle);
+<a name="l00261"></a>00261 
+<a name="l00273"></a>00273 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd_8c.html#21149047aa9abddac5654e4496175ac5">dwc_otg_pcd_get_iso_packet_params</a>(<a class="code" href="dwc__otg__pcd__if_8h.html#f6503e2b4469b327ae64f650bb5721cb">dwc_otg_pcd_t</a> * pcd,
+<a name="l00274"></a>00274                                               <span class="keywordtype">void</span> *ep_handle,
+<a name="l00275"></a>00275                                               <span class="keywordtype">void</span> *iso_req_handle, <span class="keywordtype">int</span> packet,
+<a name="l00276"></a>00276                                               <span class="keywordtype">int</span> *status, <span class="keywordtype">int</span> *actual,
+<a name="l00277"></a>00277                                               <span class="keywordtype">int</span> *offset);
+<a name="l00278"></a>00278 
+<a name="l00285"></a>00285 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__pcd_8c.html#2f04b14612c2b58909b3a54ed71ab12e">dwc_otg_pcd_get_iso_packet_count</a>(<a class="code" href="dwc__otg__pcd__if_8h.html#f6503e2b4469b327ae64f650bb5721cb">dwc_otg_pcd_t</a> * pcd,
+<a name="l00286"></a>00286                                             <span class="keywordtype">void</span> *ep_handle,
+<a name="l00287"></a>00287                                             <span class="keywordtype">void</span> *iso_req_handle);
+<a name="l00288"></a>00288 
+<a name="l00293"></a>00293 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__pcd_8c.html#7e0d7b09dc6528626f4643deb296d68d">dwc_otg_pcd_wakeup</a>(<a class="code" href="dwc__otg__pcd__if_8h.html#f6503e2b4469b327ae64f650bb5721cb">dwc_otg_pcd_t</a> * pcd);
+<a name="l00294"></a>00294 
+<a name="l00296"></a>00296 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__pcd_8c.html#676021c9b801674669cdf2d1e68d5b8c">dwc_otg_pcd_is_lpm_enabled</a>(<a class="code" href="dwc__otg__pcd__if_8h.html#f6503e2b4469b327ae64f650bb5721cb">dwc_otg_pcd_t</a> * pcd);
+<a name="l00297"></a>00297 
+<a name="l00299"></a>00299 <span class="keyword">extern</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__pcd_8c.html#0107dd39d549d3e10fd388337e03aeb9">dwc_otg_pcd_get_rmwkup_enable</a>(<a class="code" href="dwc__otg__pcd__if_8h.html#f6503e2b4469b327ae64f650bb5721cb">dwc_otg_pcd_t</a> * pcd);
+<a name="l00300"></a>00300 
+<a name="l00302"></a>00302 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd_8c.html#4be3e59162a42a79705e3ea8dc5008fa">dwc_otg_pcd_initiate_srp</a>(<a class="code" href="dwc__otg__pcd__if_8h.html#f6503e2b4469b327ae64f650bb5721cb">dwc_otg_pcd_t</a> * pcd);
+<a name="l00303"></a>00303 
+<a name="l00305"></a>00305 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd_8c.html#24cbdd57c573d864a09a30ae3ecda89a">dwc_otg_pcd_remote_wakeup</a>(<a class="code" href="dwc__otg__pcd__if_8h.html#f6503e2b4469b327ae64f650bb5721cb">dwc_otg_pcd_t</a> * pcd, <span class="keywordtype">int</span> set);
+<a name="l00306"></a>00306 
+<a name="l00308"></a>00308 <span class="keyword">extern</span> uint32_t <a class="code" href="dwc__otg__pcd_8c.html#ae9b15825812485a06be318858e0316a">dwc_otg_pcd_is_dualspeed</a>(<a class="code" href="dwc__otg__pcd__if_8h.html#f6503e2b4469b327ae64f650bb5721cb">dwc_otg_pcd_t</a> * pcd);
+<a name="l00309"></a>00309 
+<a name="l00311"></a>00311 <span class="keyword">extern</span> uint32_t <a class="code" href="dwc__otg__pcd_8c.html#07169d2569c7e071fc99045fd435f2c6">dwc_otg_pcd_is_otg</a>(<a class="code" href="dwc__otg__pcd__if_8h.html#f6503e2b4469b327ae64f650bb5721cb">dwc_otg_pcd_t</a> * pcd);
+<a name="l00312"></a>00312 
+<a name="l00314"></a>00314 <span class="keyword">extern</span> uint32_t <a class="code" href="dwc__otg__pcd_8c.html#777a6a4e250add9ba5f5f5d63d854031">get_b_hnp_enable</a>(<a class="code" href="dwc__otg__pcd__if_8h.html#f6503e2b4469b327ae64f650bb5721cb">dwc_otg_pcd_t</a> * pcd);
+<a name="l00315"></a>00315 <span class="keyword">extern</span> uint32_t <a class="code" href="dwc__otg__pcd_8c.html#69d0bb469e15cb46f00c17398f76df99">get_a_hnp_support</a>(<a class="code" href="dwc__otg__pcd__if_8h.html#f6503e2b4469b327ae64f650bb5721cb">dwc_otg_pcd_t</a> * pcd);
+<a name="l00316"></a>00316 <span class="keyword">extern</span> uint32_t <a class="code" href="dwc__otg__pcd_8c.html#842709a4980bc78d49726fa880922dda">get_a_alt_hnp_support</a>(<a class="code" href="dwc__otg__pcd__if_8h.html#f6503e2b4469b327ae64f650bb5721cb">dwc_otg_pcd_t</a> * pcd);
+<a name="l00317"></a>00317 
+<a name="l00320"></a>00320 <span class="keyword">extern</span> uint8_t *<a class="code" href="dwc__otg__pcd_8c.html#3951259aaef3df35d1955076a907f095">cfiw_ep_alloc_buffer</a>(<a class="code" href="dwc__otg__pcd__if_8h.html#f6503e2b4469b327ae64f650bb5721cb">dwc_otg_pcd_t</a> * pcd, <span class="keywordtype">void</span> *pep,
+<a name="l00321"></a>00321                                      dwc_dma_t * addr, size_t buflen,
+<a name="l00322"></a>00322                                      <span class="keywordtype">int</span> flags);
+<a name="l00323"></a>00323 
+<a name="l00324"></a>00324 <span class="comment">/******************************************************************************/</span>
+<a name="l00325"></a>00325 
+<a name="l00328"></a>00328 <span class="preprocessor">#endif                          </span><span class="comment">/* __DWC_PCD_IF_H__ */</span>
+<a name="l00329"></a>00329 
+<a name="l00330"></a>00330 <span class="preprocessor">#endif                          </span><span class="comment">/* DWC_HOST_ONLY */</span>
+</pre></div><hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__if_8h.html b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__if_8h.html
new file mode 100644
index 000000000000..0345b1668c8b
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__if_8h.html
@@ -0,0 +1,976 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd_if.h File Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<h1>dwc_otg_pcd_if.h File Reference</h1>This file defines DWC_OTG PCD Core API. <a href="#_details">More...</a>
+<p>
+<code>#include &quot;dwc_os.h&quot;</code><br>
+<code>#include &quot;<a class="el" href="dwc__otg__core__if_8h-source.html">dwc_otg_core_if.h</a>&quot;</code><br>
+
+<p>
+<a href="dwc__otg__pcd__if_8h-source.html">Go to the source code of this file.</a><table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Structures</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__pcd__function__ops.html">dwc_otg_pcd_function_ops</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Function Driver Ops Data Structure.  <a href="structdwc__otg__pcd__function__ops.html#_details">More...</a><br></td></tr>
+<tr><td colspan="2"><br><h2>Function Driver Callbacks</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef int(*)&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__if_8h.html#9c448e9fa004f873c281f46f5e5a597d">dwc_completion_cb_t</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, void *ep_handle, void *req_handle, int32_t status, uint32_t actual)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function will be called whenever a previously queued request has completed.  <a href="#9c448e9fa004f873c281f46f5e5a597d"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef int(*)&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__if_8h.html#a6f91e357c7c7782afa7db03e95a52ed">dwc_isoc_completion_cb_t</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, void *ep_handle, void *req_handle, int proc_buf_num)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function will be called whenever a previousle queued ISOC request has completed.  <a href="#a6f91e357c7c7782afa7db03e95a52ed"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef int(*)&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__if_8h.html#a9145aeaa27da4fa1befb424f927fde7">dwc_setup_cb_t</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, uint8_t *bytes)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function should handle any SETUP request that cannot be handled by the PCD Core.  <a href="#a9145aeaa27da4fa1befb424f927fde7"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef int(*)&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__if_8h.html#959f051498d2957d47cb0d27b42546aa">dwc_disconnect_cb_t</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This is called whenever the device has been disconnected.  <a href="#959f051498d2957d47cb0d27b42546aa"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="4808152d074c472f4fb1aa7b662e3004"></a><!-- doxytag: member="dwc_otg_pcd_if.h::dwc_connect_cb_t" ref="4808152d074c472f4fb1aa7b662e3004" args="(dwc_otg_pcd_t *pcd, int speed)" -->
+typedef int(*)&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__if_8h.html#4808152d074c472f4fb1aa7b662e3004">dwc_connect_cb_t</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, int speed)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function is called when device has been connected. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ddcaadb93595803ca5f2ffb74cd88619"></a><!-- doxytag: member="dwc_otg_pcd_if.h::dwc_suspend_cb_t" ref="ddcaadb93595803ca5f2ffb74cd88619" args="(dwc_otg_pcd_t *pcd)" -->
+typedef int(*)&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__if_8h.html#ddcaadb93595803ca5f2ffb74cd88619">dwc_suspend_cb_t</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function is called when device has been suspended. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef int(*)&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__if_8h.html#fc48d3df458c446cc0ace0a7d7755c67">dwc_sleep_cb_t</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function is called when device has received LPM tokens, i.e.  <a href="#fc48d3df458c446cc0ace0a7d7755c67"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="44d7ec17e6e087e44dd7c372e01fcfb2"></a><!-- doxytag: member="dwc_otg_pcd_if.h::dwc_resume_cb_t" ref="44d7ec17e6e087e44dd7c372e01fcfb2" args="(dwc_otg_pcd_t *pcd)" -->
+typedef int(*)&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__if_8h.html#44d7ec17e6e087e44dd7c372e01fcfb2">dwc_resume_cb_t</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function is called when device has been resumed from suspend(L2) or L1 sleep state. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef int(*)&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__if_8h.html#eef0b7f44036d8164121ed079710058b">dwc_hnp_params_changed_cb_t</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function is called whenever hnp params has been changed.  <a href="#eef0b7f44036d8164121ed079710058b"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f6bba5b7b3d3ad67fbf2161717281fdd"></a><!-- doxytag: member="dwc_otg_pcd_if.h::dwc_reset_cb_t" ref="f6bba5b7b3d3ad67fbf2161717281fdd" args="(dwc_otg_pcd_t *pcd)" -->
+typedef int(*)&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__if_8h.html#f6bba5b7b3d3ad67fbf2161717281fdd">dwc_reset_cb_t</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function is called whenever USB RESET is detected. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7d75df2095c14a2d985df8027359e440"></a><!-- doxytag: member="dwc_otg_pcd_if.h::cfi_setup_cb_t" ref="7d75df2095c14a2d985df8027359e440" args="(dwc_otg_pcd_t *pcd, void *ctrl_req_bytes)" -->
+typedef int(*)&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__if_8h.html#7d75df2095c14a2d985df8027359e440">cfi_setup_cb_t</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, void *ctrl_req_bytes)</td></tr>
+
+<tr><td colspan="2"><br><h2>Function Driver Functions</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__if_8h.html#fc3d8c56afa93b474180cc1eb8624ab8">dwc_otg_pcd_init</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Call this function to get pointer on dwc_otg_pcd_t, this pointer will be used for all PCD API functions.  <a href="#fc3d8c56afa93b474180cc1eb8624ab8"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__if_8h.html#aaab1535dacd5e947c1f9343d9b3ddf5">dwc_otg_pcd_remove</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Frees PCD allocated by dwc_otg_pcd_init.  <a href="#aaab1535dacd5e947c1f9343d9b3ddf5"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__if_8h.html#187209231d66bc200444c0d52331d276">dwc_otg_pcd_start</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, const struct <a class="el" href="structdwc__otg__pcd__function__ops.html">dwc_otg_pcd_function_ops</a> *<a class="el" href="dwc__otg__pcd__linux_8c.html#9ce9b5e49c60906c189bee157dd68acd">fops</a>)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Call this to bind the function driver to the PCD Core.  <a href="#187209231d66bc200444c0d52331d276"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__if_8h.html#109bb0fec2e7ef5b5cac3763f8371551">dwc_otg_pcd_ep_enable</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, const uint8_t *ep_desc, void *ep_handle)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Enables an endpoint for use.  <a href="#109bb0fec2e7ef5b5cac3763f8371551"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__if_8h.html#8a2f791c79320c8c4657715a672822a4">dwc_otg_pcd_ep_disable</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, void *ep_handle)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Disable the endpoint referenced by ep_handle.  <a href="#8a2f791c79320c8c4657715a672822a4"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__if_8h.html#09f3d77397aa7d22a1ca32e26c8aedea">dwc_otg_pcd_ep_queue</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, void *ep_handle, uint8_t *buf, dwc_dma_t dma_buf, uint32_t buflen, int zero, void *req_handle, int atomic_alloc)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Queue a data transfer request on the endpoint referenced by ep_handle.  <a href="#09f3d77397aa7d22a1ca32e26c8aedea"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__if_8h.html#aa7546ce68d6fda67bb4cda0f69eedf3">dwc_otg_pcd_ep_dequeue</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, void *ep_handle, void *req_handle)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">De-queue the specified data transfer that has not yet completed.  <a href="#aa7546ce68d6fda67bb4cda0f69eedf3"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__if_8h.html#f7d01b4772f08c6a08f4a22300a7b43b">dwc_otg_pcd_ep_halt</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, void *ep_handle, int value)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Halt (STALL) an endpoint or clear it.  <a href="#f7d01b4772f08c6a08f4a22300a7b43b"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__if_8h.html#fc60361217d0c5c089f4036d73690689">dwc_otg_pcd_handle_intr</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function should be called on every hardware interrupt.  <a href="#fc60361217d0c5c089f4036d73690689"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="04876b716043a853b379d72ff3a215e5"></a><!-- doxytag: member="dwc_otg_pcd_if.h::dwc_otg_pcd_get_frame_number" ref="04876b716043a853b379d72ff3a215e5" args="(dwc_otg_pcd_t *pcd)" -->
+int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__if_8h.html#04876b716043a853b379d72ff3a215e5">dwc_otg_pcd_get_frame_number</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function returns current frame number. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__if_8h.html#e0a690ac031f8f06c2e7fb10b4633b05">dwc_otg_pcd_iso_ep_start</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, void *ep_handle, uint8_t *buf0, uint8_t *buf1, dwc_dma_t dma0, dwc_dma_t dma1, int sync_frame, int dp_frame, int data_per_frame, int start_frame, int buf_proc_intrvl, void *req_handle, int atomic_alloc)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Start isochronous transfers on the endpoint referenced by ep_handle.  <a href="#e0a690ac031f8f06c2e7fb10b4633b05"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__if_8h.html#5098f89da28c6b450e7e10b31441b945">dwc_otg_pcd_iso_ep_stop</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, void *ep_handle, void *req_handle)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Stop ISOC transfers on endpoint referenced by ep_handle.  <a href="#5098f89da28c6b450e7e10b31441b945"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__if_8h.html#21149047aa9abddac5654e4496175ac5">dwc_otg_pcd_get_iso_packet_params</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, void *ep_handle, void *iso_req_handle, int packet, int *status, int *actual, int *offset)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get ISOC packet status.  <a href="#21149047aa9abddac5654e4496175ac5"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__if_8h.html#2f04b14612c2b58909b3a54ed71ab12e">dwc_otg_pcd_get_iso_packet_count</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, void *ep_handle, void *iso_req_handle)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get ISOC packet count.  <a href="#2f04b14612c2b58909b3a54ed71ab12e"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__if_8h.html#7e0d7b09dc6528626f4643deb296d68d">dwc_otg_pcd_wakeup</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function starts the SRP Protocol if no session is in progress.  <a href="#7e0d7b09dc6528626f4643deb296d68d"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="676021c9b801674669cdf2d1e68d5b8c"></a><!-- doxytag: member="dwc_otg_pcd_if.h::dwc_otg_pcd_is_lpm_enabled" ref="676021c9b801674669cdf2d1e68d5b8c" args="(dwc_otg_pcd_t *pcd)" -->
+int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__if_8h.html#676021c9b801674669cdf2d1e68d5b8c">dwc_otg_pcd_is_lpm_enabled</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function returns 1 if LPM support is enabled, and 0 otherwise. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="0107dd39d549d3e10fd388337e03aeb9"></a><!-- doxytag: member="dwc_otg_pcd_if.h::dwc_otg_pcd_get_rmwkup_enable" ref="0107dd39d549d3e10fd388337e03aeb9" args="(dwc_otg_pcd_t *pcd)" -->
+int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__if_8h.html#0107dd39d549d3e10fd388337e03aeb9">dwc_otg_pcd_get_rmwkup_enable</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function returns 1 if remote wakeup is allowed and 0, otherwise. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="4be3e59162a42a79705e3ea8dc5008fa"></a><!-- doxytag: member="dwc_otg_pcd_if.h::dwc_otg_pcd_initiate_srp" ref="4be3e59162a42a79705e3ea8dc5008fa" args="(dwc_otg_pcd_t *pcd)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__if_8h.html#4be3e59162a42a79705e3ea8dc5008fa">dwc_otg_pcd_initiate_srp</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Initiate SRP. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="24cbdd57c573d864a09a30ae3ecda89a"></a><!-- doxytag: member="dwc_otg_pcd_if.h::dwc_otg_pcd_remote_wakeup" ref="24cbdd57c573d864a09a30ae3ecda89a" args="(dwc_otg_pcd_t *pcd, int set)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__if_8h.html#24cbdd57c573d864a09a30ae3ecda89a">dwc_otg_pcd_remote_wakeup</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, int set)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Starts remote wakeup signaling. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ae9b15825812485a06be318858e0316a"></a><!-- doxytag: member="dwc_otg_pcd_if.h::dwc_otg_pcd_is_dualspeed" ref="ae9b15825812485a06be318858e0316a" args="(dwc_otg_pcd_t *pcd)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__if_8h.html#ae9b15825812485a06be318858e0316a">dwc_otg_pcd_is_dualspeed</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function returns whether device is dualspeed. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="07169d2569c7e071fc99045fd435f2c6"></a><!-- doxytag: member="dwc_otg_pcd_if.h::dwc_otg_pcd_is_otg" ref="07169d2569c7e071fc99045fd435f2c6" args="(dwc_otg_pcd_t *pcd)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__if_8h.html#07169d2569c7e071fc99045fd435f2c6">dwc_otg_pcd_is_otg</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function returns whether device is otg. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="777a6a4e250add9ba5f5f5d63d854031"></a><!-- doxytag: member="dwc_otg_pcd_if.h::get_b_hnp_enable" ref="777a6a4e250add9ba5f5f5d63d854031" args="(dwc_otg_pcd_t *pcd)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__if_8h.html#777a6a4e250add9ba5f5f5d63d854031">get_b_hnp_enable</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">These functions allow to get hnp parameters. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="69d0bb469e15cb46f00c17398f76df99"></a><!-- doxytag: member="dwc_otg_pcd_if.h::get_a_hnp_support" ref="69d0bb469e15cb46f00c17398f76df99" args="(dwc_otg_pcd_t *pcd)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__if_8h.html#69d0bb469e15cb46f00c17398f76df99">get_a_hnp_support</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="842709a4980bc78d49726fa880922dda"></a><!-- doxytag: member="dwc_otg_pcd_if.h::get_a_alt_hnp_support" ref="842709a4980bc78d49726fa880922dda" args="(dwc_otg_pcd_t *pcd)" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__if_8h.html#842709a4980bc78d49726fa880922dda">get_a_alt_hnp_support</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3951259aaef3df35d1955076a907f095"></a><!-- doxytag: member="dwc_otg_pcd_if.h::cfiw_ep_alloc_buffer" ref="3951259aaef3df35d1955076a907f095" args="(dwc_otg_pcd_t *pcd, void *pep, dwc_dma_t *addr, size_t buflen, int flags)" -->
+uint8_t *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__if_8h.html#3951259aaef3df35d1955076a907f095">cfiw_ep_alloc_buffer</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, void *pep, dwc_dma_t *addr, size_t buflen, int flags)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Allocate a cfi buffer. <br></td></tr>
+<tr><td colspan="2"><br><h2>Defines</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f647f1720e56adb91588a6e55179dec5"></a><!-- doxytag: member="dwc_otg_pcd_if.h::__DWC_PCD_IF_H__" ref="f647f1720e56adb91588a6e55179dec5" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__if_8h.html#f647f1720e56adb91588a6e55179dec5">__DWC_PCD_IF_H__</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="8fbbba66f80923843e99def6064a570f"></a><!-- doxytag: member="dwc_otg_pcd_if.h::MAX_EP0_SIZE" ref="8fbbba66f80923843e99def6064a570f" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__if_8h.html#8fbbba66f80923843e99def6064a570f">MAX_EP0_SIZE</a>&nbsp;&nbsp;&nbsp;64</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Maxpacket size for EP0. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="cf2c48a3393f5ae43e8d88d01c2d204a"></a><!-- doxytag: member="dwc_otg_pcd_if.h::MAX_PACKET_SIZE" ref="cf2c48a3393f5ae43e8d88d01c2d204a" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__if_8h.html#cf2c48a3393f5ae43e8d88d01c2d204a">MAX_PACKET_SIZE</a>&nbsp;&nbsp;&nbsp;1024</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Maxpacket size for any EP. <br></td></tr>
+<tr><td colspan="2"><br><h2>Typedefs</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f6503e2b4469b327ae64f650bb5721cb"></a><!-- doxytag: member="dwc_otg_pcd_if.h::dwc_otg_pcd_t" ref="f6503e2b4469b327ae64f650bb5721cb" args="" -->
+typedef <a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__if_8h.html#f6503e2b4469b327ae64f650bb5721cb">dwc_otg_pcd_t</a></td></tr>
+
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This file defines DWC_OTG PCD Core API. 
+<p>
+
+<p>
+Definition in file <a class="el" href="dwc__otg__pcd__if_8h-source.html">dwc_otg_pcd_if.h</a>.<hr><h2>Typedef Documentation</h2>
+<a class="anchor" name="9c448e9fa004f873c281f46f5e5a597d"></a><!-- doxytag: member="dwc_otg_pcd_if.h::dwc_completion_cb_t" ref="9c448e9fa004f873c281f46f5e5a597d" args="(dwc_otg_pcd_t *pcd, void *ep_handle, void *req_handle, int32_t status, uint32_t actual)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef int(*) <a class="el" href="dwc__otg__pcd__if_8h.html#9c448e9fa004f873c281f46f5e5a597d">dwc_completion_cb_t</a>(<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, void *ep_handle, void *req_handle, int32_t status, uint32_t actual)          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function will be called whenever a previously queued request has completed. 
+<p>
+The status value will be set to -DWC_E_SHUTDOWN to indicated a failed or aborted transfer, or -DWC_E_RESTART to indicate the device was reset, or -DWC_E_TIMEOUT to indicate it timed out, or -DWC_E_INVALID to indicate invalid parameters. 
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__if_8h-source.html#l00061">61</a> of file <a class="el" href="dwc__otg__pcd__if_8h-source.html">dwc_otg_pcd_if.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="a6f91e357c7c7782afa7db03e95a52ed"></a><!-- doxytag: member="dwc_otg_pcd_if.h::dwc_isoc_completion_cb_t" ref="a6f91e357c7c7782afa7db03e95a52ed" args="(dwc_otg_pcd_t *pcd, void *ep_handle, void *req_handle, int proc_buf_num)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef int(*) <a class="el" href="dwc__otg__pcd__if_8h.html#a6f91e357c7c7782afa7db03e95a52ed">dwc_isoc_completion_cb_t</a>(<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, void *ep_handle, void *req_handle, int proc_buf_num)          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function will be called whenever a previousle queued ISOC request has completed. 
+<p>
+Count of ISOC packets could be read using dwc_otg_pcd_get_iso_packet_count function. The status of each ISOC packet could be read using dwc_otg_pcd_get_iso_packet_* functions. 
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__if_8h-source.html#l00071">71</a> of file <a class="el" href="dwc__otg__pcd__if_8h-source.html">dwc_otg_pcd_if.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="a9145aeaa27da4fa1befb424f927fde7"></a><!-- doxytag: member="dwc_otg_pcd_if.h::dwc_setup_cb_t" ref="a9145aeaa27da4fa1befb424f927fde7" args="(dwc_otg_pcd_t *pcd, uint8_t *bytes)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef int(*) <a class="el" href="dwc__otg__pcd__if_8h.html#a9145aeaa27da4fa1befb424f927fde7">dwc_setup_cb_t</a>(<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, uint8_t *bytes)          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function should handle any SETUP request that cannot be handled by the PCD Core. 
+<p>
+This includes most GET_DESCRIPTORs, SET_CONFIGS, Any class-specific requests, etc. The function must non-blocking.<p>
+Returns 0 on success. Returns -DWC_E_NOT_SUPPORTED if the request is not supported. Returns -DWC_E_INVALID if the setup request had invalid parameters or bytes. Returns -DWC_E_SHUTDOWN on any other error. 
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__if_8h-source.html#l00081">81</a> of file <a class="el" href="dwc__otg__pcd__if_8h-source.html">dwc_otg_pcd_if.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="959f051498d2957d47cb0d27b42546aa"></a><!-- doxytag: member="dwc_otg_pcd_if.h::dwc_disconnect_cb_t" ref="959f051498d2957d47cb0d27b42546aa" args="(dwc_otg_pcd_t *pcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef int(*) <a class="el" href="dwc__otg__pcd__if_8h.html#959f051498d2957d47cb0d27b42546aa">dwc_disconnect_cb_t</a>(<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This is called whenever the device has been disconnected. 
+<p>
+The function driver should take appropriate action to clean up all pending requests in the PCD Core, remove all endpoints (except ep0), and initialize back to reset state. 
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__if_8h-source.html#l00086">86</a> of file <a class="el" href="dwc__otg__pcd__if_8h-source.html">dwc_otg_pcd_if.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="fc48d3df458c446cc0ace0a7d7755c67"></a><!-- doxytag: member="dwc_otg_pcd_if.h::dwc_sleep_cb_t" ref="fc48d3df458c446cc0ace0a7d7755c67" args="(dwc_otg_pcd_t *pcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef int(*) <a class="el" href="dwc__otg__pcd__if_8h.html#fc48d3df458c446cc0ace0a7d7755c67">dwc_sleep_cb_t</a>(<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function is called when device has received LPM tokens, i.e. 
+<p>
+device has been sent to sleep state. 
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__if_8h-source.html#l00093">93</a> of file <a class="el" href="dwc__otg__pcd__if_8h-source.html">dwc_otg_pcd_if.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="eef0b7f44036d8164121ed079710058b"></a><!-- doxytag: member="dwc_otg_pcd_if.h::dwc_hnp_params_changed_cb_t" ref="eef0b7f44036d8164121ed079710058b" args="(dwc_otg_pcd_t *pcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef int(*) <a class="el" href="dwc__otg__pcd__if_8h.html#eef0b7f44036d8164121ed079710058b">dwc_hnp_params_changed_cb_t</a>(<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function is called whenever hnp params has been changed. 
+<p>
+User can call get_b_hnp_enable, get_a_hnp_support, get_a_alt_hnp_support functions to get hnp parameters. 
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__if_8h-source.html#l00100">100</a> of file <a class="el" href="dwc__otg__pcd__if_8h-source.html">dwc_otg_pcd_if.h</a>.
+</div>
+</div><p>
+<hr><h2>Function Documentation</h2>
+<a class="anchor" name="fc3d8c56afa93b474180cc1eb8624ab8"></a><!-- doxytag: member="dwc_otg_pcd_if.h::dwc_otg_pcd_init" ref="fc3d8c56afa93b474180cc1eb8624ab8" args="(dwc_otg_core_if_t *core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a>* dwc_otg_pcd_init           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Call this function to get pointer on dwc_otg_pcd_t, this pointer will be used for all PCD API functions. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>The DWC_OTG Core </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd_8c-source.html#l01056">1056</a> of file <a class="el" href="dwc__otg__pcd_8c-source.html">dwc_otg_pcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="aaab1535dacd5e947c1f9343d9b3ddf5"></a><!-- doxytag: member="dwc_otg_pcd_if.h::dwc_otg_pcd_remove" ref="aaab1535dacd5e947c1f9343d9b3ddf5" args="(dwc_otg_pcd_t *pcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_pcd_remove           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Frees PCD allocated by dwc_otg_pcd_init. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>pcd</em>&nbsp;</td><td>The PCD </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd_8c-source.html#l01215">1215</a> of file <a class="el" href="dwc__otg__pcd_8c-source.html">dwc_otg_pcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="187209231d66bc200444c0d52331d276"></a><!-- doxytag: member="dwc_otg_pcd_if.h::dwc_otg_pcd_start" ref="187209231d66bc200444c0d52331d276" args="(dwc_otg_pcd_t *pcd, const struct dwc_otg_pcd_function_ops *fops)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_pcd_start           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">const struct <a class="el" href="structdwc__otg__pcd__function__ops.html">dwc_otg_pcd_function_ops</a> *&nbsp;</td>
+          <td class="paramname"> <em>fops</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Call this to bind the function driver to the PCD Core. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>pcd</em>&nbsp;</td><td>Pointer on dwc_otg_pcd_t returned by dwc_otg_pcd_init function. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>fops</em>&nbsp;</td><td>The Function Driver Ops data structure containing pointers to all callbacks. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd_8c-source.html#l00117">117</a> of file <a class="el" href="dwc__otg__pcd_8c-source.html">dwc_otg_pcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="109bb0fec2e7ef5b5cac3763f8371551"></a><!-- doxytag: member="dwc_otg_pcd_if.h::dwc_otg_pcd_ep_enable" ref="109bb0fec2e7ef5b5cac3763f8371551" args="(dwc_otg_pcd_t *pcd, const uint8_t *ep_desc, void *ep_handle)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_pcd_ep_enable           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">const uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>ep_desc</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>ep_handle</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Enables an endpoint for use. 
+<p>
+This function enables an endpoint in the PCD. The endpoint is described by the ep_desc which has the same format as a USB ep descriptor. The ep_handle parameter is used to refer to the endpoint from other API functions and in callbacks. Normally this should be called after a SET_CONFIGURATION/SET_INTERFACE to configure the core for that interface.<p>
+Returns -DWC_E_INVALID if invalid parameters were passed. Returns -DWC_E_SHUTDOWN if any other error ocurred. Returns 0 on success.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>pcd</em>&nbsp;</td><td>The PCD </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep_desc</em>&nbsp;</td><td>Endpoint descriptor </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep_handle</em>&nbsp;</td><td>Handle on endpoint, that will be used to identify endpoint. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd_8c-source.html#l01341">1341</a> of file <a class="el" href="dwc__otg__pcd_8c-source.html">dwc_otg_pcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="8a2f791c79320c8c4657715a672822a4"></a><!-- doxytag: member="dwc_otg_pcd_if.h::dwc_otg_pcd_ep_disable" ref="8a2f791c79320c8c4657715a672822a4" args="(dwc_otg_pcd_t *pcd, void *ep_handle)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_pcd_ep_disable           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>ep_handle</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Disable the endpoint referenced by ep_handle. 
+<p>
+Returns -DWC_E_INVALID if invalid parameters were passed. Returns -DWC_E_SHUTDOWN if any other error ocurred. Returns 0 on success. 
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd_8c-source.html#l01449">1449</a> of file <a class="el" href="dwc__otg__pcd_8c-source.html">dwc_otg_pcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="09f3d77397aa7d22a1ca32e26c8aedea"></a><!-- doxytag: member="dwc_otg_pcd_if.h::dwc_otg_pcd_ep_queue" ref="09f3d77397aa7d22a1ca32e26c8aedea" args="(dwc_otg_pcd_t *pcd, void *ep_handle, uint8_t *buf, dwc_dma_t dma_buf, uint32_t buflen, int zero, void *req_handle, int atomic_alloc)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_pcd_ep_queue           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>ep_handle</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>buf</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">dwc_dma_t&nbsp;</td>
+          <td class="paramname"> <em>dma_buf</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint32_t&nbsp;</td>
+          <td class="paramname"> <em>buflen</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>zero</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>req_handle</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>atomic_alloc</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Queue a data transfer request on the endpoint referenced by ep_handle. 
+<p>
+After the transfer is completes, the complete callback will be called with the request status.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>pcd</em>&nbsp;</td><td>The PCD </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep_handle</em>&nbsp;</td><td>The handle of the endpoint </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>buf</em>&nbsp;</td><td>The buffer for the data </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>dma_buf</em>&nbsp;</td><td>The DMA buffer for the data </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>buflen</em>&nbsp;</td><td>The length of the data transfer </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>zero</em>&nbsp;</td><td>Specifies whether to send zero length last packet. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>req_handle</em>&nbsp;</td><td>Set this handle to any value to use to reference this request in the ep_dequeue function or from the complete callback </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>atomic_alloc</em>&nbsp;</td><td>If driver need to perform atomic allocations for internal data structures.</td></tr>
+  </table>
+</dl>
+Returns -DWC_E_INVALID if invalid parameters were passed. Returns -DWC_E_SHUTDOWN if any other error ocurred. Returns 0 on success. 
+<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000025">Todo:</a></b></dt><dd>NGS Create a function for this. </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd_8c-source.html#l01502">1502</a> of file <a class="el" href="dwc__otg__pcd_8c-source.html">dwc_otg_pcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="aa7546ce68d6fda67bb4cda0f69eedf3"></a><!-- doxytag: member="dwc_otg_pcd_if.h::dwc_otg_pcd_ep_dequeue" ref="aa7546ce68d6fda67bb4cda0f69eedf3" args="(dwc_otg_pcd_t *pcd, void *ep_handle, void *req_handle)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_pcd_ep_dequeue           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>ep_handle</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>req_handle</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+De-queue the specified data transfer that has not yet completed. 
+<p>
+Returns -DWC_E_INVALID if invalid parameters were passed. Returns -DWC_E_SHUTDOWN if any other error ocurred. Returns 0 on success. 
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd_8c-source.html#l01694">1694</a> of file <a class="el" href="dwc__otg__pcd_8c-source.html">dwc_otg_pcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="f7d01b4772f08c6a08f4a22300a7b43b"></a><!-- doxytag: member="dwc_otg_pcd_if.h::dwc_otg_pcd_ep_halt" ref="f7d01b4772f08c6a08f4a22300a7b43b" args="(dwc_otg_pcd_t *pcd, void *ep_handle, int value)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_pcd_ep_halt           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>ep_handle</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>value</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Halt (STALL) an endpoint or clear it. 
+<p>
+Returns -DWC_E_INVALID if invalid parameters were passed. Returns -DWC_E_SHUTDOWN if any other error ocurred. Returns -DWC_E_AGAIN if the STALL cannot be sent and must be tried again later Returns 0 on success. 
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd_8c-source.html#l01733">1733</a> of file <a class="el" href="dwc__otg__pcd_8c-source.html">dwc_otg_pcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="fc60361217d0c5c089f4036d73690689"></a><!-- doxytag: member="dwc_otg_pcd_if.h::dwc_otg_pcd_handle_intr" ref="fc60361217d0c5c089f4036d73690689" args="(dwc_otg_pcd_t *pcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t dwc_otg_pcd_handle_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function should be called on every hardware interrupt. 
+<p>
+The PCD handles the device interrupts. Many conditions can cause a device interrupt. When an interrupt occurs, the device interrupt service routine determines the cause of the interrupt and dispatches handling to the appropriate function. These interrupt handling functions are described below.<p>
+All interrupt registers are processed from LSB to MSB. 
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__intr_8c-source.html#l03971">3971</a> of file <a class="el" href="dwc__otg__pcd__intr_8c-source.html">dwc_otg_pcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="e0a690ac031f8f06c2e7fb10b4633b05"></a><!-- doxytag: member="dwc_otg_pcd_if.h::dwc_otg_pcd_iso_ep_start" ref="e0a690ac031f8f06c2e7fb10b4633b05" args="(dwc_otg_pcd_t *pcd, void *ep_handle, uint8_t *buf0, uint8_t *buf1, dwc_dma_t dma0, dwc_dma_t dma1, int sync_frame, int dp_frame, int data_per_frame, int start_frame, int buf_proc_intrvl, void *req_handle, int atomic_alloc)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_pcd_iso_ep_start           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>ep_handle</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>buf0</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint8_t *&nbsp;</td>
+          <td class="paramname"> <em>buf1</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">dwc_dma_t&nbsp;</td>
+          <td class="paramname"> <em>dma0</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">dwc_dma_t&nbsp;</td>
+          <td class="paramname"> <em>dma1</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>sync_frame</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>dp_frame</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>data_per_frame</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>start_frame</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>buf_proc_intrvl</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>req_handle</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>atomic_alloc</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Start isochronous transfers on the endpoint referenced by ep_handle. 
+<p>
+For isochronous transfers duble buffering is used. After processing each of buffers comlete callback will be called with status for each transaction.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>pcd</em>&nbsp;</td><td>The PCD </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep_handle</em>&nbsp;</td><td>The handle of the endpoint </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>buf0</em>&nbsp;</td><td>The virtual address of first data buffer </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>buf1</em>&nbsp;</td><td>The virtual address of second data buffer </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>dma0</em>&nbsp;</td><td>The DMA address of first data buffer </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>dma1</em>&nbsp;</td><td>The DMA address of second data buffer </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>sync_frame</em>&nbsp;</td><td>Data pattern frame number </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>dp_frame</em>&nbsp;</td><td>Data size for pattern frame </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>data_per_frame</em>&nbsp;</td><td>Data size for regular frame </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>start_frame</em>&nbsp;</td><td>Frame number to start transfers, if -1 then start transfers ASAP. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>buf_proc_intrvl</em>&nbsp;</td><td>Interval of ISOC Buffer processing </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>req_handle</em>&nbsp;</td><td>Handle of ISOC request </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>atomic_alloc</em>&nbsp;</td><td>Specefies whether to perform atomic allocation for internal data structures.</td></tr>
+  </table>
+</dl>
+Returns -DWC_E_NO_MEMORY if there is no enough memory. Returns -DWC_E_INVALID if incorrect arguments are passed to the function. Returns -DW_E_SHUTDOWN for any other error. Returns 0 on success 
+<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000022">Todo:</a></b></dt><dd><ul>
+<li>pattern data support is to be implemented in the future </li></ul>
+</dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd_8c-source.html#l00685">685</a> of file <a class="el" href="dwc__otg__pcd_8c-source.html">dwc_otg_pcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="5098f89da28c6b450e7e10b31441b945"></a><!-- doxytag: member="dwc_otg_pcd_if.h::dwc_otg_pcd_iso_ep_stop" ref="5098f89da28c6b450e7e10b31441b945" args="(dwc_otg_pcd_t *pcd, void *ep_handle, void *req_handle)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_pcd_iso_ep_stop           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>ep_handle</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>req_handle</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Stop ISOC transfers on endpoint referenced by ep_handle. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>pcd</em>&nbsp;</td><td>The PCD </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep_handle</em>&nbsp;</td><td>The handle of the endpoint </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>req_handle</em>&nbsp;</td><td>Handle of ISOC request</td></tr>
+  </table>
+</dl>
+Returns -DWC_E_INVALID if incorrect arguments are passed to the function Returns 0 on success 
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd_8c-source.html#l00794">794</a> of file <a class="el" href="dwc__otg__pcd_8c-source.html">dwc_otg_pcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="21149047aa9abddac5654e4496175ac5"></a><!-- doxytag: member="dwc_otg_pcd_if.h::dwc_otg_pcd_get_iso_packet_params" ref="21149047aa9abddac5654e4496175ac5" args="(dwc_otg_pcd_t *pcd, void *ep_handle, void *iso_req_handle, int packet, int *status, int *actual, int *offset)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_pcd_get_iso_packet_params           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>ep_handle</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>iso_req_handle</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>packet</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int *&nbsp;</td>
+          <td class="paramname"> <em>status</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int *&nbsp;</td>
+          <td class="paramname"> <em>actual</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int *&nbsp;</td>
+          <td class="paramname"> <em>offset</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Get ISOC packet status. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>pcd</em>&nbsp;</td><td>The PCD </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep_handle</em>&nbsp;</td><td>The handle of the endpoint </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>iso_req_handle</em>&nbsp;</td><td>Isochronoush request handle </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>packet</em>&nbsp;</td><td>Number of packet </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>status</em>&nbsp;</td><td>Out parameter for returning status </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>actual</em>&nbsp;</td><td>Out parameter for returning actual length </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>offset</em>&nbsp;</td><td>Out parameter for returning offset </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd_8c-source.html#l00862">862</a> of file <a class="el" href="dwc__otg__pcd_8c-source.html">dwc_otg_pcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="2f04b14612c2b58909b3a54ed71ab12e"></a><!-- doxytag: member="dwc_otg_pcd_if.h::dwc_otg_pcd_get_iso_packet_count" ref="2f04b14612c2b58909b3a54ed71ab12e" args="(dwc_otg_pcd_t *pcd, void *ep_handle, void *iso_req_handle)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_pcd_get_iso_packet_count           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>ep_handle</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>iso_req_handle</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Get ISOC packet count. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>pcd</em>&nbsp;</td><td>The PCD </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep_handle</em>&nbsp;</td><td>The handle of the endpoint </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>iso_req_handle</em>&nbsp;</td><td></td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd_8c-source.html#l00850">850</a> of file <a class="el" href="dwc__otg__pcd_8c-source.html">dwc_otg_pcd.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="7e0d7b09dc6528626f4643deb296d68d"></a><!-- doxytag: member="dwc_otg_pcd_if.h::dwc_otg_pcd_wakeup" ref="7e0d7b09dc6528626f4643deb296d68d" args="(dwc_otg_pcd_t *pcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int dwc_otg_pcd_wakeup           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function starts the SRP Protocol if no session is in progress. 
+<p>
+If a session is already in progress, but the device is suspended, remote wakeup signaling is started. 
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd_8c-source.html#l01896">1896</a> of file <a class="el" href="dwc__otg__pcd_8c-source.html">dwc_otg_pcd.c</a>.
+</div>
+</div><p>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__intr_8c-source.html b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__intr_8c-source.html
new file mode 100644
index 000000000000..967087f4995d
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__intr_8c-source.html
@@ -0,0 +1,3629 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd_intr.c Source File</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<h1>dwc_otg_pcd_intr.c</h1><a href="dwc__otg__pcd__intr_8c.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">/* ==========================================================================</span>
+<a name="l00002"></a>00002 <span class="comment"> * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_intr.c $</span>
+<a name="l00003"></a>00003 <span class="comment"> * $Revision: #93 $</span>
+<a name="l00004"></a>00004 <span class="comment"> * $Date: 2009/04/02 $</span>
+<a name="l00005"></a>00005 <span class="comment"> * $Change: 1224216 $</span>
+<a name="l00006"></a>00006 <span class="comment"> *</span>
+<a name="l00007"></a>00007 <span class="comment"> * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,</span>
+<a name="l00008"></a>00008 <span class="comment"> * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless</span>
+<a name="l00009"></a>00009 <span class="comment"> * otherwise expressly agreed to in writing between Synopsys and you.</span>
+<a name="l00010"></a>00010 <span class="comment"> *</span>
+<a name="l00011"></a>00011 <span class="comment"> * The Software IS NOT an item of Licensed Software or Licensed Product under</span>
+<a name="l00012"></a>00012 <span class="comment"> * any End User Software License Agreement or Agreement for Licensed Product</span>
+<a name="l00013"></a>00013 <span class="comment"> * with Synopsys or any supplement thereto. You are permitted to use and</span>
+<a name="l00014"></a>00014 <span class="comment"> * redistribute this Software in source and binary forms, with or without</span>
+<a name="l00015"></a>00015 <span class="comment"> * modification, provided that redistributions of source code must retain this</span>
+<a name="l00016"></a>00016 <span class="comment"> * notice. You may not view, use, disclose, copy or distribute this file or</span>
+<a name="l00017"></a>00017 <span class="comment"> * any information contained herein except pursuant to this license grant from</span>
+<a name="l00018"></a>00018 <span class="comment"> * Synopsys. If you do not agree with this notice, including the disclaimer</span>
+<a name="l00019"></a>00019 <span class="comment"> * below, then you are not authorized to use the Software.</span>
+<a name="l00020"></a>00020 <span class="comment"> *</span>
+<a name="l00021"></a>00021 <span class="comment"> * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS</span>
+<a name="l00022"></a>00022 <span class="comment"> * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE</span>
+<a name="l00023"></a>00023 <span class="comment"> * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE</span>
+<a name="l00024"></a>00024 <span class="comment"> * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,</span>
+<a name="l00025"></a>00025 <span class="comment"> * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES</span>
+<a name="l00026"></a>00026 <span class="comment"> * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR</span>
+<a name="l00027"></a>00027 <span class="comment"> * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER</span>
+<a name="l00028"></a>00028 <span class="comment"> * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT</span>
+<a name="l00029"></a>00029 <span class="comment"> * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY</span>
+<a name="l00030"></a>00030 <span class="comment"> * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH</span>
+<a name="l00031"></a>00031 <span class="comment"> * DAMAGE.</span>
+<a name="l00032"></a>00032 <span class="comment"> * ========================================================================== */</span>
+<a name="l00033"></a>00033 <span class="preprocessor">#ifndef DWC_HOST_ONLY</span>
+<a name="l00034"></a>00034 <span class="preprocessor"></span>
+<a name="l00035"></a>00035 <span class="preprocessor">#include "<a class="code" href="dwc__otg__pcd_8h.html">dwc_otg_pcd.h</a>"</span>
+<a name="l00036"></a>00036 
+<a name="l00037"></a>00037 <span class="preprocessor">#ifdef DWC_UTE_CFI</span>
+<a name="l00038"></a>00038 <span class="preprocessor"></span><span class="preprocessor">#include "<a class="code" href="dwc__otg__cfi_8h.html">dwc_otg_cfi.h</a>"</span>
+<a name="l00039"></a>00039 <span class="preprocessor">#endif</span>
+<a name="l00040"></a>00040 <span class="preprocessor"></span>
+<a name="l00041"></a>00041 <span class="comment">//#define PRINT_CFI_DMA_DESCS</span>
+<a name="l00042"></a>00042 
+<a name="l00043"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#1d4105869a3a5ce989afa5124218de0a">00043</a> <span class="preprocessor">#define DEBUG_EP0</span>
+<a name="l00044"></a>00044 <span class="preprocessor"></span>
+<a name="l00048"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#81a9361b81863cef6b2566ea44529185">00048</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd__intr_8c.html#81a9361b81863cef6b2566ea44529185">dwc_otg_pcd_update_otg</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd, <span class="keyword">const</span> <span class="keywordtype">unsigned</span> reset)
+<a name="l00049"></a>00049 {
+<a name="l00050"></a>00050 
+<a name="l00051"></a>00051         <span class="keywordflow">if</span> (reset) {
+<a name="l00052"></a>00052                 pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#e09fc5322ac0d7deec2772984c10ae90">b_hnp_enable</a> = 0;
+<a name="l00053"></a>00053                 pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#e8008719644bdc23040f1a1545b7117f">a_hnp_support</a> = 0;
+<a name="l00054"></a>00054                 pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#49f2d2b04a4c07a8d53643f7681b5405">a_alt_hnp_support</a> = 0;
+<a name="l00055"></a>00055         }
+<a name="l00056"></a>00056 
+<a name="l00057"></a>00057         <span class="keywordflow">if</span> (pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#b7001dde5db2706707a860da0030d9e6">fops</a>-&gt;<a class="code" href="structdwc__otg__pcd__function__ops.html#db190030830b55d72b36255980be08d7">hnp_changed</a>) {
+<a name="l00058"></a>00058                 pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#b7001dde5db2706707a860da0030d9e6">fops</a>-&gt;<a class="code" href="structdwc__otg__pcd__function__ops.html#db190030830b55d72b36255980be08d7">hnp_changed</a>(pcd);
+<a name="l00059"></a>00059         }
+<a name="l00060"></a>00060 }
+<a name="l00061"></a>00061 
+<a name="l00076"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#13cc45eef95b81189df890c10cf7ca66">00076</a> <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd__intr_8c.html#13cc45eef95b81189df890c10cf7ca66">print_ep0_state</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd)
+<a name="l00077"></a>00077 {
+<a name="l00078"></a>00078 <span class="preprocessor">#ifdef DEBUG</span>
+<a name="l00079"></a>00079 <span class="preprocessor"></span>        <span class="keywordtype">char</span> str[40];
+<a name="l00080"></a>00080 
+<a name="l00081"></a>00081         <span class="keywordflow">switch</span> (pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#8f6963b3fb9ab83048c4c0697c90382a">ep0state</a>) {
+<a name="l00082"></a>00082         <span class="keywordflow">case</span> EP0_DISCONNECT:
+<a name="l00083"></a>00083                 dwc_strcpy(str, <span class="stringliteral">"EP0_DISCONNECT"</span>);
+<a name="l00084"></a>00084                 <span class="keywordflow">break</span>;
+<a name="l00085"></a>00085         <span class="keywordflow">case</span> EP0_IDLE:
+<a name="l00086"></a>00086                 dwc_strcpy(str, <span class="stringliteral">"EP0_IDLE"</span>);
+<a name="l00087"></a>00087                 <span class="keywordflow">break</span>;
+<a name="l00088"></a>00088         <span class="keywordflow">case</span> EP0_IN_DATA_PHASE:
+<a name="l00089"></a>00089                 dwc_strcpy(str, <span class="stringliteral">"EP0_IN_DATA_PHASE"</span>);
+<a name="l00090"></a>00090                 <span class="keywordflow">break</span>;
+<a name="l00091"></a>00091         <span class="keywordflow">case</span> EP0_OUT_DATA_PHASE:
+<a name="l00092"></a>00092                 dwc_strcpy(str, <span class="stringliteral">"EP0_OUT_DATA_PHASE"</span>);
+<a name="l00093"></a>00093                 <span class="keywordflow">break</span>;
+<a name="l00094"></a>00094         <span class="keywordflow">case</span> EP0_IN_STATUS_PHASE:
+<a name="l00095"></a>00095                 dwc_strcpy(str, <span class="stringliteral">"EP0_IN_STATUS_PHASE"</span>);
+<a name="l00096"></a>00096                 <span class="keywordflow">break</span>;
+<a name="l00097"></a>00097         <span class="keywordflow">case</span> EP0_OUT_STATUS_PHASE:
+<a name="l00098"></a>00098                 dwc_strcpy(str, <span class="stringliteral">"EP0_OUT_STATUS_PHASE"</span>);
+<a name="l00099"></a>00099                 <span class="keywordflow">break</span>;
+<a name="l00100"></a>00100         <span class="keywordflow">case</span> EP0_STALL:
+<a name="l00101"></a>00101                 dwc_strcpy(str, <span class="stringliteral">"EP0_STALL"</span>);
+<a name="l00102"></a>00102                 <span class="keywordflow">break</span>;
+<a name="l00103"></a>00103         <span class="keywordflow">default</span>:
+<a name="l00104"></a>00104                 dwc_strcpy(str, <span class="stringliteral">"EP0_INVALID"</span>);
+<a name="l00105"></a>00105         }
+<a name="l00106"></a>00106 
+<a name="l00107"></a>00107         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#2bf62a567355d1ea38814714bd7b57ec">DBG_ANY</a>, <span class="stringliteral">"%s(%d)\n"</span>, str, pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#8f6963b3fb9ab83048c4c0697c90382a">ep0state</a>);
+<a name="l00108"></a>00108 <span class="preprocessor">#endif</span>
+<a name="l00109"></a>00109 <span class="preprocessor"></span>}
+<a name="l00110"></a>00110 
+<a name="l00111"></a>00111 <span class="preprocessor">#ifdef DWC_UTE_CFI</span>
+<a name="l00112"></a>00112 <span class="preprocessor"></span><span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">void</span> print_desc(<span class="keyword">struct</span> dwc_otg_dma_desc *ddesc,
+<a name="l00113"></a>00113                               <span class="keyword">const</span> uint8_t * epname, <span class="keywordtype">int</span> descnum)
+<a name="l00114"></a>00114 {
+<a name="l00115"></a>00115         <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>
+<a name="l00116"></a>00116             (<span class="stringliteral">"%s DMA_DESC(%d) buf=0x%08x bytes=0x%04x; sp=0x%x; l=0x%x; sts=0x%02x; bs=0x%02x\n"</span>,
+<a name="l00117"></a>00117              epname, descnum, ddesc-&gt;buf, ddesc-&gt;status.b.bytes,
+<a name="l00118"></a>00118              ddesc-&gt;status.b.sp, ddesc-&gt;status.b.l, ddesc-&gt;status.b.sts,
+<a name="l00119"></a>00119              ddesc-&gt;status.b.bs);
+<a name="l00120"></a>00120 }
+<a name="l00121"></a>00121 <span class="preprocessor">#endif</span>
+<a name="l00122"></a>00122 <span class="preprocessor"></span>
+<a name="l00126"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#cc3f2f1ae0ab7d33903a1d0d9097c04e">00126</a> <span class="keyword">static</span> <span class="keyword">inline</span> <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *<a class="code" href="dwc__otg__pcd__intr_8c.html#cc3f2f1ae0ab7d33903a1d0d9097c04e">get_in_ep</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd, uint32_t ep_num)
+<a name="l00127"></a>00127 {
+<a name="l00128"></a>00128         <span class="keywordtype">int</span> i;
+<a name="l00129"></a>00129         <span class="keywordtype">int</span> num_in_eps = <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;dev_if-&gt;num_in_eps;
+<a name="l00130"></a>00130         <span class="keywordflow">if</span> (ep_num == 0) {
+<a name="l00131"></a>00131                 <span class="keywordflow">return</span> &amp;pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a>;
+<a name="l00132"></a>00132         } <span class="keywordflow">else</span> {
+<a name="l00133"></a>00133                 <span class="keywordflow">for</span> (i = 0; i &lt; num_in_eps; ++i) {
+<a name="l00134"></a>00134                         <span class="keywordflow">if</span> (pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#dbfc8c424ea3add38db96fa87219caa8">in_ep</a>[i].<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a> == ep_num)
+<a name="l00135"></a>00135                                 <span class="keywordflow">return</span> &amp;pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#dbfc8c424ea3add38db96fa87219caa8">in_ep</a>[i];
+<a name="l00136"></a>00136                 }
+<a name="l00137"></a>00137                 <span class="keywordflow">return</span> 0;
+<a name="l00138"></a>00138         }
+<a name="l00139"></a>00139 }
+<a name="l00140"></a>00140 
+<a name="l00144"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#fbd54e53e1968d3b4798ea1b63b52f74">00144</a> <span class="keyword">static</span> <span class="keyword">inline</span> <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *<a class="code" href="dwc__otg__pcd__intr_8c.html#fbd54e53e1968d3b4798ea1b63b52f74">get_out_ep</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd, uint32_t ep_num)
+<a name="l00145"></a>00145 {
+<a name="l00146"></a>00146         <span class="keywordtype">int</span> i;
+<a name="l00147"></a>00147         <span class="keywordtype">int</span> num_out_eps = <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;dev_if-&gt;num_out_eps;
+<a name="l00148"></a>00148         <span class="keywordflow">if</span> (ep_num == 0) {
+<a name="l00149"></a>00149                 <span class="keywordflow">return</span> &amp;pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a>;
+<a name="l00150"></a>00150         } <span class="keywordflow">else</span> {
+<a name="l00151"></a>00151                 <span class="keywordflow">for</span> (i = 0; i &lt; num_out_eps; ++i) {
+<a name="l00152"></a>00152                         <span class="keywordflow">if</span> (pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#b9e49a1d1fbca5ba9523e27c7108df30">out_ep</a>[i].<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a> == ep_num)
+<a name="l00153"></a>00153                                 <span class="keywordflow">return</span> &amp;pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#b9e49a1d1fbca5ba9523e27c7108df30">out_ep</a>[i];
+<a name="l00154"></a>00154                 }
+<a name="l00155"></a>00155                 <span class="keywordflow">return</span> 0;
+<a name="l00156"></a>00156         }
+<a name="l00157"></a>00157 }
+<a name="l00158"></a>00158 
+<a name="l00163"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#3c351d7f51d6242296d6ea3bb1a9775c">00163</a> <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *<a class="code" href="dwc__otg__pcd__intr_8c.html#3c351d7f51d6242296d6ea3bb1a9775c">get_ep_by_addr</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd, u16 wIndex)
+<a name="l00164"></a>00164 {
+<a name="l00165"></a>00165         <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *ep;
+<a name="l00166"></a>00166         uint32_t ep_num = UE_GET_ADDR(wIndex);
+<a name="l00167"></a>00167 
+<a name="l00168"></a>00168         <span class="keywordflow">if</span> (ep_num == 0) {
+<a name="l00169"></a>00169                 ep = &amp;pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a>;
+<a name="l00170"></a>00170         } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (UE_GET_DIR(wIndex) == UE_DIR_IN) {   <span class="comment">/* in ep */</span>
+<a name="l00171"></a>00171                 ep = &amp;pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#dbfc8c424ea3add38db96fa87219caa8">in_ep</a>[ep_num - 1];
+<a name="l00172"></a>00172         } <span class="keywordflow">else</span> {
+<a name="l00173"></a>00173                 ep = &amp;pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#b9e49a1d1fbca5ba9523e27c7108df30">out_ep</a>[ep_num - 1];
+<a name="l00174"></a>00174         }
+<a name="l00175"></a>00175 
+<a name="l00176"></a>00176         <span class="keywordflow">return</span> ep;
+<a name="l00177"></a>00177 }
+<a name="l00178"></a>00178 
+<a name="l00183"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#de7160b7e7b8fd622ba95392513e197c">00183</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd_8c.html#de7160b7e7b8fd622ba95392513e197c">start_next_request</a>(<a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> * ep)
+<a name="l00184"></a>00184 {
+<a name="l00185"></a>00185         <a class="code" href="structdwc__otg__pcd__request.html">dwc_otg_pcd_request_t</a> *req = 0;
+<a name="l00186"></a>00186         uint32_t max_transfer =
+<a name="l00187"></a>00187             <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#234391334e48cbd72710d08655c9ed16">pcd</a>)-&gt;core_params-&gt;max_transfer_size;
+<a name="l00188"></a>00188 
+<a name="l00189"></a>00189 <span class="preprocessor">#ifdef DWC_UTE_CFI</span>
+<a name="l00190"></a>00190 <span class="preprocessor"></span>        <span class="keyword">struct </span><a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd</a> *pcd;
+<a name="l00191"></a>00191         pcd = ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#234391334e48cbd72710d08655c9ed16">pcd</a>;
+<a name="l00192"></a>00192 <span class="preprocessor">#endif</span>
+<a name="l00193"></a>00193 <span class="preprocessor"></span>
+<a name="l00194"></a>00194         <span class="keywordflow">if</span> (!DWC_CIRCLEQ_EMPTY(&amp;ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#71f4fa571dfdc96f62fa4869e6add300">queue</a>)) {
+<a name="l00195"></a>00195                 <a class="code" href="structdwc__otg__pcd.html#af0345bc2c877d96863ef440c923204c">req</a> = DWC_CIRCLEQ_FIRST(&amp;ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#71f4fa571dfdc96f62fa4869e6add300">queue</a>);
+<a name="l00196"></a>00196 
+<a name="l00197"></a>00197 <span class="preprocessor">#ifdef DWC_UTE_CFI</span>
+<a name="l00198"></a>00198 <span class="preprocessor"></span>                <span class="keywordflow">if</span> (ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.buff_mode != BM_STANDARD) {
+<a name="l00199"></a>00199                         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.cfi_req_len = <a class="code" href="structdwc__otg__pcd.html#af0345bc2c877d96863ef440c923204c">req</a>-&gt;length;
+<a name="l00200"></a>00200                         pcd-&gt;cfi-&gt;ops.build_descriptors(pcd-&gt;cfi, pcd, ep, <a class="code" href="structdwc__otg__pcd.html#af0345bc2c877d96863ef440c923204c">req</a>);
+<a name="l00201"></a>00201                 } <span class="keywordflow">else</span> {
+<a name="l00202"></a>00202 <span class="preprocessor">#endif</span>
+<a name="l00203"></a>00203 <span class="preprocessor"></span>                <span class="comment">/* Setup and start the Transfer */</span>
+<a name="l00204"></a>00204                 ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#b40ce70422b6d105a855a8df4b33d45d">dma_addr</a> = <a class="code" href="structdwc__otg__pcd.html#af0345bc2c877d96863ef440c923204c">req</a>-&gt;dma;
+<a name="l00205"></a>00205                 ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#d0cda8ded2e5142d9a1c9c17efc5812f">start_xfer_buff</a> = <a class="code" href="structdwc__otg__pcd.html#af0345bc2c877d96863ef440c923204c">req</a>-&gt;buf;
+<a name="l00206"></a>00206                 ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#97fa9bf5c31ba734d54f70e6fe6ae8eb">xfer_buff</a> = <a class="code" href="structdwc__otg__pcd.html#af0345bc2c877d96863ef440c923204c">req</a>-&gt;buf;
+<a name="l00207"></a>00207                 ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#8c6340435beba0b8c025a4677602acab">sent_zlp</a> = 0;
+<a name="l00208"></a>00208                 ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#5a218f200cff0491b735f43fed5176bf">total_len</a> = <a class="code" href="structdwc__otg__pcd.html#af0345bc2c877d96863ef440c923204c">req</a>-&gt;length;
+<a name="l00209"></a>00209                 ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">xfer_len</a> = 0;
+<a name="l00210"></a>00210                 ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#23d4871510b5bcb54fbf0674d8f122bd">xfer_count</a> = 0;
+<a name="l00211"></a>00211 
+<a name="l00212"></a>00212                 ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#f60095e5ebedf7f98f3bfea77ce9a755">maxxfer</a> = max_transfer;
+<a name="l00213"></a>00213                 <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#234391334e48cbd72710d08655c9ed16">pcd</a>)-&gt;dma_desc_enable) {
+<a name="l00214"></a>00214                         uint32_t out_max_xfer = <a class="code" href="dwc__otg__pcd_8h.html#6dad4d4462e9819753acfc601889faec">DDMA_MAX_TRANSFER_SIZE</a>
+<a name="l00215"></a>00215                             - (<a class="code" href="dwc__otg__pcd_8h.html#6dad4d4462e9819753acfc601889faec">DDMA_MAX_TRANSFER_SIZE</a> % 4);
+<a name="l00216"></a>00216                         <span class="keywordflow">if</span> (ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#b882b6b7c857100ed20600e94ea37760">is_in</a>) {
+<a name="l00217"></a>00217                                         <span class="keywordflow">if</span> (ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#f60095e5ebedf7f98f3bfea77ce9a755">maxxfer</a> &gt;
+<a name="l00218"></a>00218                                             <a class="code" href="dwc__otg__pcd_8h.html#6dad4d4462e9819753acfc601889faec">DDMA_MAX_TRANSFER_SIZE</a>) {
+<a name="l00219"></a>00219                                         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#f60095e5ebedf7f98f3bfea77ce9a755">maxxfer</a> =
+<a name="l00220"></a>00220                                             <a class="code" href="dwc__otg__pcd_8h.html#6dad4d4462e9819753acfc601889faec">DDMA_MAX_TRANSFER_SIZE</a>;
+<a name="l00221"></a>00221                                 }
+<a name="l00222"></a>00222                         } <span class="keywordflow">else</span> {
+<a name="l00223"></a>00223                                 <span class="keywordflow">if</span> (ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#f60095e5ebedf7f98f3bfea77ce9a755">maxxfer</a> &gt; out_max_xfer) {
+<a name="l00224"></a>00224                                                 ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#f60095e5ebedf7f98f3bfea77ce9a755">maxxfer</a> =
+<a name="l00225"></a>00225                                                     out_max_xfer;
+<a name="l00226"></a>00226                                 }
+<a name="l00227"></a>00227                         }
+<a name="l00228"></a>00228                 }
+<a name="l00229"></a>00229                 <span class="keywordflow">if</span> (ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#f60095e5ebedf7f98f3bfea77ce9a755">maxxfer</a> &lt; ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#5a218f200cff0491b735f43fed5176bf">total_len</a>) {
+<a name="l00230"></a>00230                         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#f60095e5ebedf7f98f3bfea77ce9a755">maxxfer</a> -=
+<a name="l00231"></a>00231                             (ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#f60095e5ebedf7f98f3bfea77ce9a755">maxxfer</a> % ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a>);
+<a name="l00232"></a>00232                 }
+<a name="l00233"></a>00233                 <span class="keywordflow">if</span> (<a class="code" href="structdwc__otg__pcd.html#af0345bc2c877d96863ef440c923204c">req</a>-&gt;sent_zlp) {
+<a name="l00234"></a>00234                                 <span class="keywordflow">if</span> ((ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#5a218f200cff0491b735f43fed5176bf">total_len</a> %
+<a name="l00235"></a>00235                                      ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a> == 0)
+<a name="l00236"></a>00236                                     &amp;&amp; (ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#5a218f200cff0491b735f43fed5176bf">total_len</a> != 0)) {
+<a name="l00237"></a>00237                                 ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#8c6340435beba0b8c025a4677602acab">sent_zlp</a> = 1;
+<a name="l00238"></a>00238                         }
+<a name="l00239"></a>00239 
+<a name="l00240"></a>00240                 }
+<a name="l00241"></a>00241 <span class="preprocessor">#ifdef DWC_UTE_CFI</span>
+<a name="l00242"></a>00242 <span class="preprocessor"></span>                }
+<a name="l00243"></a>00243 <span class="preprocessor">#endif</span>
+<a name="l00244"></a>00244 <span class="preprocessor"></span>                <a class="code" href="dwc__otg__cil_8c.html#1278f6d58a4a2bc780e90e0b6c9b9a68">dwc_otg_ep_start_transfer</a>(<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#234391334e48cbd72710d08655c9ed16">pcd</a>), &amp;ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>);
+<a name="l00245"></a>00245         }
+<a name="l00246"></a>00246 }
+<a name="l00247"></a>00247 
+<a name="l00252"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#669296a786dcd89220efa8d7f62b10d0">00252</a> int32_t <a class="code" href="dwc__otg__pcd__intr_8c.html#669296a786dcd89220efa8d7f62b10d0">dwc_otg_pcd_handle_sof_intr</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd)
+<a name="l00253"></a>00253 {
+<a name="l00254"></a>00254         <a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *<a class="code" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">core_if</a> = <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd);
+<a name="l00255"></a>00255 
+<a name="l00256"></a>00256         <a class="code" href="uniongintsts__data.html">gintsts_data_t</a> gintsts;
+<a name="l00257"></a>00257 
+<a name="l00258"></a>00258         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"SOF\n"</span>);
+<a name="l00259"></a>00259 
+<a name="l00260"></a>00260         <span class="comment">/* Clear interrupt */</span>
+<a name="l00261"></a>00261         gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a> = 0;
+<a name="l00262"></a>00262         gintsts.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#3f6ba377d6b1449884bb4da1b155c61b">sofintr</a> = 1;
+<a name="l00263"></a>00263         dwc_write_reg32(&amp;<a class="code" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>, gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a>);
+<a name="l00264"></a>00264 
+<a name="l00265"></a>00265         <span class="keywordflow">return</span> 1;
+<a name="l00266"></a>00266 }
+<a name="l00267"></a>00267 
+<a name="l00285"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#99560d3941c21dedd1fb1fc846cea24f">00285</a> int32_t <a class="code" href="dwc__otg__pcd__intr_8c.html#99560d3941c21dedd1fb1fc846cea24f">dwc_otg_pcd_handle_rx_status_q_level_intr</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd)
+<a name="l00286"></a>00286 {
+<a name="l00287"></a>00287         <a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *<a class="code" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">core_if</a> = <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd);
+<a name="l00288"></a>00288         <a class="code" href="structdwc__otg__core__global__regs.html">dwc_otg_core_global_regs_t</a> *global_regs = <a class="code" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>;
+<a name="l00289"></a>00289         <a class="code" href="uniongintmsk__data.html">gintmsk_data_t</a> gintmask = {.d32 = 0 };
+<a name="l00290"></a>00290         <a class="code" href="uniondevice__grxsts__data.html">device_grxsts_data_t</a> status;
+<a name="l00291"></a>00291         <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *ep;
+<a name="l00292"></a>00292         <a class="code" href="uniongintsts__data.html">gintsts_data_t</a> gintsts;
+<a name="l00293"></a>00293 <span class="preprocessor">#ifdef DEBUG</span>
+<a name="l00294"></a>00294 <span class="preprocessor"></span>        <span class="keyword">static</span> <span class="keywordtype">char</span> *dpid_str[] = { <span class="stringliteral">"D0"</span>, <span class="stringliteral">"D2"</span>, <span class="stringliteral">"D1"</span>, <span class="stringliteral">"MDATA"</span> };
+<a name="l00295"></a>00295 <span class="preprocessor">#endif</span>
+<a name="l00296"></a>00296 <span class="preprocessor"></span>
+<a name="l00297"></a>00297         <span class="comment">//DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, _pcd);</span>
+<a name="l00298"></a>00298         <span class="comment">/* Disable the Rx Status Queue Level interrupt */</span>
+<a name="l00299"></a>00299         gintmask.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#83db45f92a3a692d79199e1a850c2a62">rxstsqlvl</a> = 1;
+<a name="l00300"></a>00300         dwc_modify_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#48827c76da2c6b18f369e2f2483cc4b6">gintmsk</a>, gintmask.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a>, 0);
+<a name="l00301"></a>00301 
+<a name="l00302"></a>00302         <span class="comment">/* Get the Status from the top of the FIFO */</span>
+<a name="l00303"></a>00303         status.<a class="code" href="uniondevice__grxsts__data.html#9d454f39c05e23d376dfb0069d933986">d32</a> = dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#763b05035799e1c16d34957fb62a2d17">grxstsp</a>);
+<a name="l00304"></a>00304 
+<a name="l00305"></a>00305         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"EP:%d BCnt:%d DPID:%s "</span>
+<a name="l00306"></a>00306                     <span class="stringliteral">"pktsts:%x Frame:%d(0x%0x)\n"</span>,
+<a name="l00307"></a>00307                     status.<a class="code" href="uniondevice__grxsts__data.html#dbcda32a5bc5e5423bcf6e01d99c7686">b</a>.<a class="code" href="uniondevice__grxsts__data.html#d91e207bb8fb6e20652e6ad2474aec8e">epnum</a>, status.<a class="code" href="uniondevice__grxsts__data.html#dbcda32a5bc5e5423bcf6e01d99c7686">b</a>.<a class="code" href="uniondevice__grxsts__data.html#6162a5f256d8041bc3d1d1071e999107">bcnt</a>,
+<a name="l00308"></a>00308                     dpid_str[status.<a class="code" href="uniondevice__grxsts__data.html#dbcda32a5bc5e5423bcf6e01d99c7686">b</a>.<a class="code" href="uniondevice__grxsts__data.html#d0f4716b612b04fde649a2f689ea5b88">dpid</a>],
+<a name="l00309"></a>00309                     status.<a class="code" href="uniondevice__grxsts__data.html#dbcda32a5bc5e5423bcf6e01d99c7686">b</a>.<a class="code" href="uniondevice__grxsts__data.html#712eb005af256f84ebfc6f3083dd1ba8">pktsts</a>, status.<a class="code" href="uniondevice__grxsts__data.html#dbcda32a5bc5e5423bcf6e01d99c7686">b</a>.<a class="code" href="uniondevice__grxsts__data.html#f535ee62a482ec97ca61dc4954e358c6">fn</a>, status.<a class="code" href="uniondevice__grxsts__data.html#dbcda32a5bc5e5423bcf6e01d99c7686">b</a>.<a class="code" href="uniondevice__grxsts__data.html#f535ee62a482ec97ca61dc4954e358c6">fn</a>);
+<a name="l00310"></a>00310         <span class="comment">/* Get pointer to EP structure */</span>
+<a name="l00311"></a>00311         ep = <a class="code" href="dwc__otg__pcd__intr_8c.html#fbd54e53e1968d3b4798ea1b63b52f74">get_out_ep</a>(pcd, status.<a class="code" href="uniondevice__grxsts__data.html#dbcda32a5bc5e5423bcf6e01d99c7686">b</a>.<a class="code" href="uniondevice__grxsts__data.html#d91e207bb8fb6e20652e6ad2474aec8e">epnum</a>);
+<a name="l00312"></a>00312 
+<a name="l00313"></a>00313         <span class="keywordflow">switch</span> (status.<a class="code" href="uniondevice__grxsts__data.html#dbcda32a5bc5e5423bcf6e01d99c7686">b</a>.<a class="code" href="uniondevice__grxsts__data.html#712eb005af256f84ebfc6f3083dd1ba8">pktsts</a>) {
+<a name="l00314"></a>00314         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__regs_8h.html#de6ad4d62ad4debd7d97e27ea68bbe7f">DWC_DSTS_GOUT_NAK</a>:
+<a name="l00315"></a>00315                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"Global OUT NAK\n"</span>);
+<a name="l00316"></a>00316                 <span class="keywordflow">break</span>;
+<a name="l00317"></a>00317         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__regs_8h.html#93cbb84c3631af89d282fb1b406594f5">DWC_STS_DATA_UPDT</a>:
+<a name="l00318"></a>00318                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"OUT Data Packet\n"</span>);
+<a name="l00319"></a>00319                 <span class="keywordflow">if</span> (status.<a class="code" href="uniondevice__grxsts__data.html#dbcda32a5bc5e5423bcf6e01d99c7686">b</a>.<a class="code" href="uniondevice__grxsts__data.html#6162a5f256d8041bc3d1d1071e999107">bcnt</a> &amp;&amp; ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#97fa9bf5c31ba734d54f70e6fe6ae8eb">xfer_buff</a>) {
+<a name="l00321"></a>00321                         <a class="code" href="dwc__otg__cil_8c.html#68f59dd23ccfffa9aa1dc590e99b7668">dwc_otg_read_packet</a>(<a class="code" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">core_if</a>,
+<a name="l00322"></a>00322                                             ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#97fa9bf5c31ba734d54f70e6fe6ae8eb">xfer_buff</a>,
+<a name="l00323"></a>00323                                             status.<a class="code" href="uniondevice__grxsts__data.html#dbcda32a5bc5e5423bcf6e01d99c7686">b</a>.<a class="code" href="uniondevice__grxsts__data.html#6162a5f256d8041bc3d1d1071e999107">bcnt</a>);
+<a name="l00324"></a>00324                         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#23d4871510b5bcb54fbf0674d8f122bd">xfer_count</a> += status.<a class="code" href="uniondevice__grxsts__data.html#dbcda32a5bc5e5423bcf6e01d99c7686">b</a>.<a class="code" href="uniondevice__grxsts__data.html#6162a5f256d8041bc3d1d1071e999107">bcnt</a>;
+<a name="l00325"></a>00325                         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#97fa9bf5c31ba734d54f70e6fe6ae8eb">xfer_buff</a> += status.<a class="code" href="uniondevice__grxsts__data.html#dbcda32a5bc5e5423bcf6e01d99c7686">b</a>.<a class="code" href="uniondevice__grxsts__data.html#6162a5f256d8041bc3d1d1071e999107">bcnt</a>;
+<a name="l00326"></a>00326                 }
+<a name="l00327"></a>00327                 <span class="keywordflow">break</span>;
+<a name="l00328"></a>00328         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__regs_8h.html#53a6a9dd332c8a15f505cd0027fb4c86">DWC_STS_XFER_COMP</a>:
+<a name="l00329"></a>00329                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"OUT Complete\n"</span>);
+<a name="l00330"></a>00330                 <span class="keywordflow">break</span>;
+<a name="l00331"></a>00331         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__regs_8h.html#2f7181f56123a3d16d78e204ab6e5e96">DWC_DSTS_SETUP_COMP</a>:
+<a name="l00332"></a>00332 <span class="preprocessor">#ifdef DEBUG_EP0</span>
+<a name="l00333"></a>00333 <span class="preprocessor"></span>                <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"Setup Complete\n"</span>);
+<a name="l00334"></a>00334 <span class="preprocessor">#endif</span>
+<a name="l00335"></a>00335 <span class="preprocessor"></span>                <span class="keywordflow">break</span>;
+<a name="l00336"></a>00336         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__regs_8h.html#416a63dc7ef9b792d21b01cc257bba43">DWC_DSTS_SETUP_UPDT</a>:
+<a name="l00337"></a>00337                 <a class="code" href="dwc__otg__cil_8c.html#b56e0d90c67bbf2829e630cafd630f17">dwc_otg_read_setup_packet</a>(<a class="code" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">core_if</a>, pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5ea5c519e678fbb382c2ea7d128562c1">setup_pkt</a>-&gt;<a class="code" href="structdwc__otg__pcd.html#e4fe210f7a18b9f0c393af9cdf282d56">d32</a>);
+<a name="l00338"></a>00338 <span class="preprocessor">#ifdef DEBUG_EP0</span>
+<a name="l00339"></a>00339 <span class="preprocessor"></span>                <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>,
+<a name="l00340"></a>00340                             <span class="stringliteral">"SETUP PKT: %02x.%02x v%04x i%04x l%04x\n"</span>,
+<a name="l00341"></a>00341                             pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5ea5c519e678fbb382c2ea7d128562c1">setup_pkt</a>-&gt;<a class="code" href="structdwc__otg__pcd.html#af0345bc2c877d96863ef440c923204c">req</a>.bmRequestType,
+<a name="l00342"></a>00342                             pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5ea5c519e678fbb382c2ea7d128562c1">setup_pkt</a>-&gt;<a class="code" href="structdwc__otg__pcd.html#af0345bc2c877d96863ef440c923204c">req</a>.bRequest,
+<a name="l00343"></a>00343                             UGETW(pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5ea5c519e678fbb382c2ea7d128562c1">setup_pkt</a>-&gt;<a class="code" href="structdwc__otg__pcd.html#af0345bc2c877d96863ef440c923204c">req</a>.wValue),
+<a name="l00344"></a>00344                             UGETW(pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5ea5c519e678fbb382c2ea7d128562c1">setup_pkt</a>-&gt;<a class="code" href="structdwc__otg__pcd.html#af0345bc2c877d96863ef440c923204c">req</a>.wIndex),
+<a name="l00345"></a>00345                             UGETW(pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5ea5c519e678fbb382c2ea7d128562c1">setup_pkt</a>-&gt;<a class="code" href="structdwc__otg__pcd.html#af0345bc2c877d96863ef440c923204c">req</a>.wLength));
+<a name="l00346"></a>00346 <span class="preprocessor">#endif</span>
+<a name="l00347"></a>00347 <span class="preprocessor"></span>                ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#23d4871510b5bcb54fbf0674d8f122bd">xfer_count</a> += status.<a class="code" href="uniondevice__grxsts__data.html#dbcda32a5bc5e5423bcf6e01d99c7686">b</a>.<a class="code" href="uniondevice__grxsts__data.html#6162a5f256d8041bc3d1d1071e999107">bcnt</a>;
+<a name="l00348"></a>00348                 <span class="keywordflow">break</span>;
+<a name="l00349"></a>00349         <span class="keywordflow">default</span>:
+<a name="l00350"></a>00350                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"Invalid Packet Status (0x%0x)\n"</span>,
+<a name="l00351"></a>00351                             status.<a class="code" href="uniondevice__grxsts__data.html#dbcda32a5bc5e5423bcf6e01d99c7686">b</a>.<a class="code" href="uniondevice__grxsts__data.html#712eb005af256f84ebfc6f3083dd1ba8">pktsts</a>);
+<a name="l00352"></a>00352                 <span class="keywordflow">break</span>;
+<a name="l00353"></a>00353         }
+<a name="l00354"></a>00354 
+<a name="l00355"></a>00355         <span class="comment">/* Enable the Rx Status Queue Level interrupt */</span>
+<a name="l00356"></a>00356         dwc_modify_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#48827c76da2c6b18f369e2f2483cc4b6">gintmsk</a>, 0, gintmask.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a>);
+<a name="l00357"></a>00357         <span class="comment">/* Clear interrupt */</span>
+<a name="l00358"></a>00358         gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a> = 0;
+<a name="l00359"></a>00359         gintsts.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#7595576956c3a0ced9ea387880943012">rxstsqlvl</a> = 1;
+<a name="l00360"></a>00360         dwc_write_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>, gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a>);
+<a name="l00361"></a>00361 
+<a name="l00362"></a>00362         <span class="comment">//DWC_DEBUGPL(DBG_PCDV, "EXIT: %s\n", __func__);</span>
+<a name="l00363"></a>00363         <span class="keywordflow">return</span> 1;
+<a name="l00364"></a>00364 }
+<a name="l00365"></a>00365 
+<a name="l00378"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#fde237571d3aaa5d03376d3bee827075">00378</a> <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__pcd__intr_8c.html#fde237571d3aaa5d03376d3bee827075">get_ep_of_last_in_token</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * <a class="code" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">core_if</a>)
+<a name="l00379"></a>00379 {
+<a name="l00380"></a>00380         <a class="code" href="structdwc__otg__dev__global__regs.html">dwc_otg_device_global_regs_t</a> *dev_global_regs =
+<a name="l00381"></a>00381             <a class="code" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>;
+<a name="l00382"></a>00382         <span class="keyword">const</span> uint32_t TOKEN_Q_DEPTH = <a class="code" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">hwcfg2</a>.<a class="code" href="unionhwcfg2__data.html#9dcc70e2dba617cbc6c12189be5c1d6a">b</a>.<a class="code" href="unionhwcfg2__data.html#ba242467585b60b4d3db9882e0f39b3f">dev_token_q_depth</a>;
+<a name="l00383"></a>00383         <span class="comment">/* Number of Token Queue Registers */</span>
+<a name="l00384"></a>00384         <span class="keyword">const</span> <span class="keywordtype">int</span> DTKNQ_REG_CNT = (TOKEN_Q_DEPTH + 7) / 8;
+<a name="l00385"></a>00385         <a class="code" href="uniondtknq1__data.html">dtknq1_data_t</a> dtknqr1;
+<a name="l00386"></a>00386         uint32_t in_tkn_epnums[4];
+<a name="l00387"></a>00387         <span class="keywordtype">int</span> ndx = 0;
+<a name="l00388"></a>00388         <span class="keywordtype">int</span> i = 0;
+<a name="l00389"></a>00389         <span class="keyword">volatile</span> uint32_t *addr = &amp;dev_global_regs-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#b130a76736e0e81d5a020651109352de">dtknqr1</a>;
+<a name="l00390"></a>00390         <span class="keywordtype">int</span> epnum = 0;
+<a name="l00391"></a>00391 
+<a name="l00392"></a>00392         <span class="comment">//DWC_DEBUGPL(DBG_PCD,"dev_token_q_depth=%d\n",TOKEN_Q_DEPTH);</span>
+<a name="l00393"></a>00393 
+<a name="l00394"></a>00394         <span class="comment">/* Read the DTKNQ Registers */</span>
+<a name="l00395"></a>00395         <span class="keywordflow">for</span> (i = 0; i &lt; DTKNQ_REG_CNT; i++) {
+<a name="l00396"></a>00396                 in_tkn_epnums[i] = dwc_read_reg32(addr);
+<a name="l00397"></a>00397                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"DTKNQR%d=0x%08x\n"</span>, i + 1,
+<a name="l00398"></a>00398                             in_tkn_epnums[i]);
+<a name="l00399"></a>00399                 <span class="keywordflow">if</span> (addr == &amp;dev_global_regs-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#95088e182c3ff164d1b331bb196eb95d">dvbusdis</a>) {
+<a name="l00400"></a>00400                         addr = &amp;dev_global_regs-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#c263c55a0bb752f8939731aa2f8f6cb8">dtknqr3_dthrctl</a>;
+<a name="l00401"></a>00401                 } <span class="keywordflow">else</span> {
+<a name="l00402"></a>00402                         ++addr;
+<a name="l00403"></a>00403                 }
+<a name="l00404"></a>00404 
+<a name="l00405"></a>00405         }
+<a name="l00406"></a>00406 
+<a name="l00407"></a>00407         <span class="comment">/* Copy the DTKNQR1 data to the bit field. */</span>
+<a name="l00408"></a>00408         dtknqr1.<a class="code" href="uniondtknq1__data.html#86015789f75da8cd507db3766fe93fef">d32</a> = in_tkn_epnums[0];
+<a name="l00409"></a>00409         <span class="comment">/* Get the EP numbers */</span>
+<a name="l00410"></a>00410         in_tkn_epnums[0] = dtknqr1.<a class="code" href="uniondtknq1__data.html#fffe59f9a5f7cdf1ece03cf43caff69d">b</a>.<a class="code" href="uniondtknq1__data.html#b35b4b7cfebfe54904ac0d74bb771825">epnums0_5</a>;
+<a name="l00411"></a>00411         ndx = dtknqr1.<a class="code" href="uniondtknq1__data.html#fffe59f9a5f7cdf1ece03cf43caff69d">b</a>.<a class="code" href="uniondtknq1__data.html#33b25ddce8afe3ac2d8736f42133c284">intknwptr</a> - 1;
+<a name="l00412"></a>00412 
+<a name="l00413"></a>00413         <span class="comment">//DWC_DEBUGPL(DBG_PCDV,"ndx=%d\n",ndx);</span>
+<a name="l00414"></a>00414         <span class="keywordflow">if</span> (ndx == -1) {
+<a name="l00417"></a>00417                 <span class="keywordtype">int</span> cnt = TOKEN_Q_DEPTH;
+<a name="l00418"></a>00418                 <span class="keywordflow">if</span> (TOKEN_Q_DEPTH &lt;= 6) {
+<a name="l00419"></a>00419                         cnt = TOKEN_Q_DEPTH - 1;
+<a name="l00420"></a>00420                 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (TOKEN_Q_DEPTH &lt;= 14) {
+<a name="l00421"></a>00421                         cnt = TOKEN_Q_DEPTH - 7;
+<a name="l00422"></a>00422                 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (TOKEN_Q_DEPTH &lt;= 22) {
+<a name="l00423"></a>00423                         cnt = TOKEN_Q_DEPTH - 15;
+<a name="l00424"></a>00424                 } <span class="keywordflow">else</span> {
+<a name="l00425"></a>00425                         cnt = TOKEN_Q_DEPTH - 23;
+<a name="l00426"></a>00426                 }
+<a name="l00427"></a>00427                 epnum = (in_tkn_epnums[DTKNQ_REG_CNT - 1] &gt;&gt; (cnt * 4)) &amp; 0xF;
+<a name="l00428"></a>00428         } <span class="keywordflow">else</span> {
+<a name="l00429"></a>00429                 <span class="keywordflow">if</span> (ndx &lt;= 5) {
+<a name="l00430"></a>00430                         epnum = (in_tkn_epnums[0] &gt;&gt; (ndx * 4)) &amp; 0xF;
+<a name="l00431"></a>00431                 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (ndx &lt;= 13) {
+<a name="l00432"></a>00432                         ndx -= 6;
+<a name="l00433"></a>00433                         epnum = (in_tkn_epnums[1] &gt;&gt; (ndx * 4)) &amp; 0xF;
+<a name="l00434"></a>00434                 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (ndx &lt;= 21) {
+<a name="l00435"></a>00435                         ndx -= 14;
+<a name="l00436"></a>00436                         epnum = (in_tkn_epnums[2] &gt;&gt; (ndx * 4)) &amp; 0xF;
+<a name="l00437"></a>00437                 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (ndx &lt;= 29) {
+<a name="l00438"></a>00438                         ndx -= 22;
+<a name="l00439"></a>00439                         epnum = (in_tkn_epnums[3] &gt;&gt; (ndx * 4)) &amp; 0xF;
+<a name="l00440"></a>00440                 }
+<a name="l00441"></a>00441         }
+<a name="l00442"></a>00442         <span class="comment">//DWC_DEBUGPL(DBG_PCD,"epnum=%d\n",epnum);</span>
+<a name="l00443"></a>00443         <span class="keywordflow">return</span> epnum;
+<a name="l00444"></a>00444 }
+<a name="l00445"></a>00445 
+<a name="l00451"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#bc463d6cebcf3da1989eb6d252979554">00451</a> int32_t <a class="code" href="dwc__otg__pcd__intr_8c.html#bc463d6cebcf3da1989eb6d252979554">dwc_otg_pcd_handle_np_tx_fifo_empty_intr</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd)
+<a name="l00452"></a>00452 {
+<a name="l00453"></a>00453         <a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *<a class="code" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">core_if</a> = <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd);
+<a name="l00454"></a>00454         <a class="code" href="structdwc__otg__core__global__regs.html">dwc_otg_core_global_regs_t</a> *global_regs = <a class="code" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>;
+<a name="l00455"></a>00455         <a class="code" href="structdwc__otg__dev__in__ep__regs.html">dwc_otg_dev_in_ep_regs_t</a> *ep_regs;
+<a name="l00456"></a>00456         <a class="code" href="uniongnptxsts__data.html">gnptxsts_data_t</a> txstatus = {.d32 = 0 };
+<a name="l00457"></a>00457         <a class="code" href="uniongintsts__data.html">gintsts_data_t</a> gintsts;
+<a name="l00458"></a>00458 
+<a name="l00459"></a>00459         <span class="keywordtype">int</span> epnum = 0;
+<a name="l00460"></a>00460         <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *ep = 0;
+<a name="l00461"></a>00461         uint32_t len = 0;
+<a name="l00462"></a>00462         <span class="keywordtype">int</span> dwords;
+<a name="l00463"></a>00463 
+<a name="l00464"></a>00464         <span class="comment">/* Get the epnum from the IN Token Learning Queue. */</span>
+<a name="l00465"></a>00465         epnum = <a class="code" href="dwc__otg__pcd__intr_8c.html#fde237571d3aaa5d03376d3bee827075">get_ep_of_last_in_token</a>(<a class="code" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">core_if</a>);
+<a name="l00466"></a>00466         ep = <a class="code" href="dwc__otg__pcd__intr_8c.html#cc3f2f1ae0ab7d33903a1d0d9097c04e">get_in_ep</a>(pcd, epnum);
+<a name="l00467"></a>00467 
+<a name="l00468"></a>00468         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"NP TxFifo Empty: %d \n"</span>, epnum);
+<a name="l00469"></a>00469 
+<a name="l00470"></a>00470         ep_regs = <a class="code" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[epnum];
+<a name="l00471"></a>00471 
+<a name="l00472"></a>00472         len = ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">xfer_len</a> - ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#23d4871510b5bcb54fbf0674d8f122bd">xfer_count</a>;
+<a name="l00473"></a>00473         <span class="keywordflow">if</span> (len &gt; ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a>) {
+<a name="l00474"></a>00474                 len = ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a>;
+<a name="l00475"></a>00475         }
+<a name="l00476"></a>00476         dwords = (len + 3) / 4;
+<a name="l00477"></a>00477 
+<a name="l00478"></a>00478         <span class="comment">/* While there is space in the queue and space in the FIFO and</span>
+<a name="l00479"></a>00479 <span class="comment">         * More data to tranfer, Write packets to the Tx FIFO */</span>
+<a name="l00480"></a>00480         txstatus.<a class="code" href="uniongnptxsts__data.html#a58b5adbe6bd0344c4f585ef6aba4672">d32</a> = dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#57dabea6f6e0bf9e1ee8e94f55b9e465">gnptxsts</a>);
+<a name="l00481"></a>00481         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"b4 GNPTXSTS=0x%08x\n"</span>, txstatus.<a class="code" href="uniongnptxsts__data.html#a58b5adbe6bd0344c4f585ef6aba4672">d32</a>);
+<a name="l00482"></a>00482 
+<a name="l00483"></a>00483         <span class="keywordflow">while</span> (txstatus.<a class="code" href="uniongnptxsts__data.html#be1d1adf7b827616ebbbf6bf564c0738">b</a>.<a class="code" href="uniongnptxsts__data.html#634ffd5e84bc422ddef043574d8f0957">nptxqspcavail</a> &gt; 0 &amp;&amp;
+<a name="l00484"></a>00484                txstatus.<a class="code" href="uniongnptxsts__data.html#be1d1adf7b827616ebbbf6bf564c0738">b</a>.<a class="code" href="uniongnptxsts__data.html#6c149be246bcf5ca5395f67e67648207">nptxfspcavail</a> &gt; dwords &amp;&amp;
+<a name="l00485"></a>00485                ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#23d4871510b5bcb54fbf0674d8f122bd">xfer_count</a> &lt; ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">xfer_len</a>) {
+<a name="l00486"></a>00486                 <span class="comment">/* Write the FIFO */</span>
+<a name="l00487"></a>00487                 <a class="code" href="dwc__otg__cil_8c.html#97a11808b8b12a365a91f02b6d686d0c">dwc_otg_ep_write_packet</a>(<a class="code" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">core_if</a>, &amp;ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>, 0);
+<a name="l00488"></a>00488                 len = ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">xfer_len</a> - ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#23d4871510b5bcb54fbf0674d8f122bd">xfer_count</a>;
+<a name="l00489"></a>00489 
+<a name="l00490"></a>00490                 <span class="keywordflow">if</span> (len &gt; ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a>) {
+<a name="l00491"></a>00491                         len = ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a>;
+<a name="l00492"></a>00492                 }
+<a name="l00493"></a>00493 
+<a name="l00494"></a>00494                 dwords = (len + 3) / 4;
+<a name="l00495"></a>00495                 txstatus.<a class="code" href="uniongnptxsts__data.html#a58b5adbe6bd0344c4f585ef6aba4672">d32</a> = dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#57dabea6f6e0bf9e1ee8e94f55b9e465">gnptxsts</a>);
+<a name="l00496"></a>00496                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"GNPTXSTS=0x%08x\n"</span>, txstatus.<a class="code" href="uniongnptxsts__data.html#a58b5adbe6bd0344c4f585ef6aba4672">d32</a>);
+<a name="l00497"></a>00497         }
+<a name="l00498"></a>00498 
+<a name="l00499"></a>00499         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"GNPTXSTS=0x%08x\n"</span>,
+<a name="l00500"></a>00500                     dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#57dabea6f6e0bf9e1ee8e94f55b9e465">gnptxsts</a>));
+<a name="l00501"></a>00501 
+<a name="l00502"></a>00502         <span class="comment">/* Clear interrupt */</span>
+<a name="l00503"></a>00503         gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a> = 0;
+<a name="l00504"></a>00504         gintsts.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#adebf5ff5bdf69a2bcf0bd4b2ba55ef4">nptxfempty</a> = 1;
+<a name="l00505"></a>00505         dwc_write_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>, gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a>);
+<a name="l00506"></a>00506 
+<a name="l00507"></a>00507         <span class="keywordflow">return</span> 1;
+<a name="l00508"></a>00508 }
+<a name="l00509"></a>00509 
+<a name="l00515"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#5e53962e63763aa9df6400981b7d5354">00515</a> <span class="keyword">static</span> int32_t <a class="code" href="dwc__otg__pcd__intr_8c.html#5e53962e63763aa9df6400981b7d5354">write_empty_tx_fifo</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd, uint32_t epnum)
+<a name="l00516"></a>00516 {
+<a name="l00517"></a>00517         <a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *<a class="code" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">core_if</a> = <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd);
+<a name="l00518"></a>00518         <a class="code" href="structdwc__otg__dev__if.html">dwc_otg_dev_if_t</a> *dev_if = <a class="code" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>;
+<a name="l00519"></a>00519         <a class="code" href="structdwc__otg__dev__in__ep__regs.html">dwc_otg_dev_in_ep_regs_t</a> *ep_regs;
+<a name="l00520"></a>00520         <a class="code" href="uniondtxfsts__data.html">dtxfsts_data_t</a> txstatus = {.d32 = 0 };
+<a name="l00521"></a>00521         <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *ep = 0;
+<a name="l00522"></a>00522         uint32_t len = 0;
+<a name="l00523"></a>00523         <span class="keywordtype">int</span> dwords;
+<a name="l00524"></a>00524 
+<a name="l00525"></a>00525         ep = <a class="code" href="dwc__otg__pcd__intr_8c.html#cc3f2f1ae0ab7d33903a1d0d9097c04e">get_in_ep</a>(pcd, epnum);
+<a name="l00526"></a>00526 
+<a name="l00527"></a>00527         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"Dedicated TxFifo Empty: %d \n"</span>, epnum);
+<a name="l00528"></a>00528 
+<a name="l00529"></a>00529         ep_regs = <a class="code" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[epnum];
+<a name="l00530"></a>00530 
+<a name="l00531"></a>00531         len = ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">xfer_len</a> - ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#23d4871510b5bcb54fbf0674d8f122bd">xfer_count</a>;
+<a name="l00532"></a>00532 
+<a name="l00533"></a>00533         <span class="keywordflow">if</span> (len &gt; ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a>) {
+<a name="l00534"></a>00534                 len = ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a>;
+<a name="l00535"></a>00535         }
+<a name="l00536"></a>00536 
+<a name="l00537"></a>00537         dwords = (len + 3) / 4;
+<a name="l00538"></a>00538 
+<a name="l00539"></a>00539         <span class="comment">/* While there is space in the queue and space in the FIFO and</span>
+<a name="l00540"></a>00540 <span class="comment">         * More data to tranfer, Write packets to the Tx FIFO */</span>
+<a name="l00541"></a>00541         txstatus.<a class="code" href="uniondtxfsts__data.html#684b8a9ccf83a5807e9bb3491c662c39">d32</a> = dwc_read_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[epnum]-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#90db7d3ed2dd087e0a55a1465deb21c9">dtxfsts</a>);
+<a name="l00542"></a>00542         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"b4 dtxfsts[%d]=0x%08x\n"</span>, epnum, txstatus.<a class="code" href="uniondtxfsts__data.html#684b8a9ccf83a5807e9bb3491c662c39">d32</a>);
+<a name="l00543"></a>00543 
+<a name="l00544"></a>00544         <span class="keywordflow">while</span> (txstatus.<a class="code" href="uniondtxfsts__data.html#168f673549aad11d0d9fdc06ee6c5480">b</a>.<a class="code" href="uniondtxfsts__data.html#83db0e2dbe071694f549a383b7037b3b">txfspcavail</a> &gt; dwords &amp;&amp;
+<a name="l00545"></a>00545                ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#23d4871510b5bcb54fbf0674d8f122bd">xfer_count</a> &lt; ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">xfer_len</a> &amp;&amp;
+<a name="l00546"></a>00546                ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">xfer_len</a> != 0) {
+<a name="l00547"></a>00547                 <span class="comment">/* Write the FIFO */</span>
+<a name="l00548"></a>00548                 <a class="code" href="dwc__otg__cil_8c.html#97a11808b8b12a365a91f02b6d686d0c">dwc_otg_ep_write_packet</a>(<a class="code" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">core_if</a>, &amp;ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>, 0);
+<a name="l00549"></a>00549 
+<a name="l00550"></a>00550                 len = ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">xfer_len</a> - ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#23d4871510b5bcb54fbf0674d8f122bd">xfer_count</a>;
+<a name="l00551"></a>00551                 <span class="keywordflow">if</span> (len &gt; ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a>) {
+<a name="l00552"></a>00552                         len = ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a>;
+<a name="l00553"></a>00553                 }
+<a name="l00554"></a>00554 
+<a name="l00555"></a>00555                 dwords = (len + 3) / 4;
+<a name="l00556"></a>00556                 txstatus.<a class="code" href="uniondtxfsts__data.html#684b8a9ccf83a5807e9bb3491c662c39">d32</a> =
+<a name="l00557"></a>00557                     dwc_read_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[epnum]-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#90db7d3ed2dd087e0a55a1465deb21c9">dtxfsts</a>);
+<a name="l00558"></a>00558                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"dtxfsts[%d]=0x%08x\n"</span>, epnum,
+<a name="l00559"></a>00559                             txstatus.<a class="code" href="uniondtxfsts__data.html#684b8a9ccf83a5807e9bb3491c662c39">d32</a>);
+<a name="l00560"></a>00560         }
+<a name="l00561"></a>00561 
+<a name="l00562"></a>00562         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"b4 dtxfsts[%d]=0x%08x\n"</span>, epnum,
+<a name="l00563"></a>00563                     dwc_read_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[epnum]-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#90db7d3ed2dd087e0a55a1465deb21c9">dtxfsts</a>));
+<a name="l00564"></a>00564 
+<a name="l00565"></a>00565         <span class="keywordflow">return</span> 1;
+<a name="l00566"></a>00566 }
+<a name="l00567"></a>00567 
+<a name="l00573"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#19e17d6a73d8a3ebf00a1d11999a5ff9">00573</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd__intr_8c.html#19e17d6a73d8a3ebf00a1d11999a5ff9">dwc_otg_pcd_stop</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd)
+<a name="l00574"></a>00574 {
+<a name="l00575"></a>00575         <span class="keywordtype">int</span> i, num_in_eps, num_out_eps;
+<a name="l00576"></a>00576         <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *ep;
+<a name="l00577"></a>00577 
+<a name="l00578"></a>00578         <a class="code" href="uniongintmsk__data.html">gintmsk_data_t</a> intr_mask = {.d32 = 0 };
+<a name="l00579"></a>00579 
+<a name="l00580"></a>00580         DWC_SPINLOCK(pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5d450e4d06659ab2f3b18e5c816776e4">lock</a>);
+<a name="l00581"></a>00581 
+<a name="l00582"></a>00582         num_in_eps = <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;dev_if-&gt;num_in_eps;
+<a name="l00583"></a>00583         num_out_eps = <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;dev_if-&gt;num_out_eps;
+<a name="l00584"></a>00584 
+<a name="l00585"></a>00585         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"%s() \n"</span>, __func__);
+<a name="l00586"></a>00586         <span class="comment">/* don't disconnect drivers more than once */</span>
+<a name="l00587"></a>00587         <span class="keywordflow">if</span> (pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#8f6963b3fb9ab83048c4c0697c90382a">ep0state</a> == EP0_DISCONNECT) {
+<a name="l00588"></a>00588                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#2bf62a567355d1ea38814714bd7b57ec">DBG_ANY</a>, <span class="stringliteral">"%s() Already Disconnected\n"</span>, __func__);
+<a name="l00589"></a>00589                 <span class="keywordflow">return</span>;
+<a name="l00590"></a>00590         }
+<a name="l00591"></a>00591         pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#8f6963b3fb9ab83048c4c0697c90382a">ep0state</a> = EP0_DISCONNECT;
+<a name="l00592"></a>00592 
+<a name="l00593"></a>00593         <span class="comment">/* Reset the OTG state. */</span>
+<a name="l00594"></a>00594         <a class="code" href="dwc__otg__pcd__intr_8c.html#81a9361b81863cef6b2566ea44529185">dwc_otg_pcd_update_otg</a>(pcd, 1);
+<a name="l00595"></a>00595 
+<a name="l00596"></a>00596         <span class="comment">/* Disable the NP Tx Fifo Empty Interrupt. */</span>
+<a name="l00597"></a>00597         intr_mask.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#2c395e7bef31a4d9b2d1a3257c601be4">nptxfempty</a> = 1;
+<a name="l00598"></a>00598         dwc_modify_reg32(&amp;<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;core_global_regs-&gt;gintmsk,
+<a name="l00599"></a>00599                          intr_mask.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a>, 0);
+<a name="l00600"></a>00600 
+<a name="l00601"></a>00601         <span class="comment">/* Flush the FIFOs */</span>
+<a name="l00603"></a>00603         <a class="code" href="dwc__otg__cil_8c.html#039e387cd0e0282727da3c5a36f4cdda">dwc_otg_flush_tx_fifo</a>(<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd), 0x10);
+<a name="l00604"></a>00604         <a class="code" href="dwc__otg__cil_8c.html#fb275f0f9923cc30629fce5e3753025c">dwc_otg_flush_rx_fifo</a>(<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd));
+<a name="l00605"></a>00605 
+<a name="l00606"></a>00606         <span class="comment">/* prevent new request submissions, kill any outstanding requests  */</span>
+<a name="l00607"></a>00607         ep = &amp;pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a>;
+<a name="l00608"></a>00608         <a class="code" href="dwc__otg__pcd_8c.html#e8ef6f3d831b89a753d93489827949d3">dwc_otg_request_nuke</a>(ep);
+<a name="l00609"></a>00609         <span class="comment">/* prevent new request submissions, kill any outstanding requests  */</span>
+<a name="l00610"></a>00610         <span class="keywordflow">for</span> (i = 0; i &lt; num_in_eps; i++) {
+<a name="l00611"></a>00611                 <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *ep = &amp;pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#dbfc8c424ea3add38db96fa87219caa8">in_ep</a>[i];
+<a name="l00612"></a>00612                 <a class="code" href="dwc__otg__pcd_8c.html#e8ef6f3d831b89a753d93489827949d3">dwc_otg_request_nuke</a>(ep);
+<a name="l00613"></a>00613         }
+<a name="l00614"></a>00614         <span class="comment">/* prevent new request submissions, kill any outstanding requests  */</span>
+<a name="l00615"></a>00615         <span class="keywordflow">for</span> (i = 0; i &lt; num_out_eps; i++) {
+<a name="l00616"></a>00616                 <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *ep = &amp;pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#b9e49a1d1fbca5ba9523e27c7108df30">out_ep</a>[i];
+<a name="l00617"></a>00617                 <a class="code" href="dwc__otg__pcd_8c.html#e8ef6f3d831b89a753d93489827949d3">dwc_otg_request_nuke</a>(ep);
+<a name="l00618"></a>00618         }
+<a name="l00619"></a>00619 
+<a name="l00620"></a>00620         <span class="comment">/* report disconnect; the driver is already quiesced */</span>
+<a name="l00621"></a>00621         <span class="keywordflow">if</span> (pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#b7001dde5db2706707a860da0030d9e6">fops</a>-&gt;<a class="code" href="structdwc__otg__pcd__function__ops.html#51b0e7dcf19398bad4f0ec459b43077a">disconnect</a>) {
+<a name="l00622"></a>00622                 DWC_SPINUNLOCK(pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5d450e4d06659ab2f3b18e5c816776e4">lock</a>);
+<a name="l00623"></a>00623                 pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#b7001dde5db2706707a860da0030d9e6">fops</a>-&gt;<a class="code" href="structdwc__otg__pcd__function__ops.html#51b0e7dcf19398bad4f0ec459b43077a">disconnect</a>(pcd);
+<a name="l00624"></a>00624                 DWC_SPINLOCK(pcd-&gt;lock);
+<a name="l00625"></a>00625         }
+<a name="l00626"></a>00626         DWC_SPINUNLOCK(pcd-&gt;lock);
+<a name="l00627"></a>00627 }
+<a name="l00628"></a>00628 
+<a name="l00632"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#7d52ad6b49e7495df6c1788b325c510c">00632</a> int32_t <a class="code" href="dwc__otg__pcd__intr_8c.html#7d52ad6b49e7495df6c1788b325c510c">dwc_otg_pcd_handle_i2c_intr</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd)
+<a name="l00633"></a>00633 {
+<a name="l00634"></a>00634         <a class="code" href="uniongintmsk__data.html">gintmsk_data_t</a> intr_mask = {.d32 = 0 };
+<a name="l00635"></a>00635         <a class="code" href="uniongintsts__data.html">gintsts_data_t</a> gintsts;
+<a name="l00636"></a>00636 
+<a name="l00637"></a>00637         DWC_PRINTF(<span class="stringliteral">"INTERRUPT Handler not implemented for %s\n"</span>, <span class="stringliteral">"i2cintr"</span>);
+<a name="l00638"></a>00638         intr_mask.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#92dd84dd80b06e949668f85e6b6b7086">i2cintr</a> = 1;
+<a name="l00639"></a>00639         dwc_modify_reg32(&amp;<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;core_global_regs-&gt;gintmsk,
+<a name="l00640"></a>00640                          intr_mask.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a>, 0);
+<a name="l00641"></a>00641 
+<a name="l00642"></a>00642         <span class="comment">/* Clear interrupt */</span>
+<a name="l00643"></a>00643         gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a> = 0;
+<a name="l00644"></a>00644         gintsts.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#2e8bd51ad285fd46db48f9fb5bbb7993">i2cintr</a> = 1;
+<a name="l00645"></a>00645         dwc_write_reg32(&amp;<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;core_global_regs-&gt;gintsts,
+<a name="l00646"></a>00646                         gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a>);
+<a name="l00647"></a>00647         <span class="keywordflow">return</span> 1;
+<a name="l00648"></a>00648 }
+<a name="l00649"></a>00649 
+<a name="l00653"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#51b8dd218b31a7d79f5cef82c2a497aa">00653</a> int32_t <a class="code" href="dwc__otg__pcd__intr_8c.html#51b8dd218b31a7d79f5cef82c2a497aa">dwc_otg_pcd_handle_early_suspend_intr</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd)
+<a name="l00654"></a>00654 {
+<a name="l00655"></a>00655         <a class="code" href="uniongintsts__data.html">gintsts_data_t</a> gintsts;
+<a name="l00656"></a>00656 <span class="preprocessor">#if defined(VERBOSE)</span>
+<a name="l00657"></a>00657 <span class="preprocessor"></span>        DWC_PRINTF(<span class="stringliteral">"Early Suspend Detected\n"</span>);
+<a name="l00658"></a>00658 <span class="preprocessor">#endif</span>
+<a name="l00659"></a>00659 <span class="preprocessor"></span>        <span class="comment">/* Clear interrupt */</span>
+<a name="l00660"></a>00660         gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a> = 0;
+<a name="l00661"></a>00661         gintsts.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#2659c4ea7b295a089ee498b21b44992b">erlysuspend</a> = 1;
+<a name="l00662"></a>00662         dwc_write_reg32(&amp;<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;core_global_regs-&gt;gintsts,
+<a name="l00663"></a>00663                         gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a>);
+<a name="l00664"></a>00664         <span class="keywordflow">return</span> 1;
+<a name="l00665"></a>00665 }
+<a name="l00666"></a>00666 
+<a name="l00684"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#726b57833bb3ae4648ce7e7a7e125bf7">00684</a> <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd__intr_8c.html#726b57833bb3ae4648ce7e7a7e125bf7">ep0_out_start</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * <a class="code" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">core_if</a>,
+<a name="l00685"></a>00685                                  <a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd)
+<a name="l00686"></a>00686 {
+<a name="l00687"></a>00687         <a class="code" href="structdwc__otg__dev__if.html">dwc_otg_dev_if_t</a> *dev_if = <a class="code" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>;
+<a name="l00688"></a>00688         <a class="code" href="uniondeptsiz0__data.html">deptsiz0_data_t</a> doeptsize0 = {.d32 = 0 };
+<a name="l00689"></a>00689         <a class="code" href="structdwc__otg__dev__dma__desc.html">dwc_otg_dev_dma_desc_t</a> *dma_desc;
+<a name="l00690"></a>00690         <a class="code" href="uniondepctl__data.html">depctl_data_t</a> doepctl = {.d32 = 0 };
+<a name="l00691"></a>00691 
+<a name="l00692"></a>00692 <span class="preprocessor">#ifdef VERBOSE</span>
+<a name="l00693"></a>00693 <span class="preprocessor"></span>        <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"%s() doepctl0=%0x\n"</span>, __func__,
+<a name="l00694"></a>00694                     dwc_read_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">out_ep_regs</a>[0]-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#2a522b71fc97658c07debf3521f7d3e5">doepctl</a>));
+<a name="l00695"></a>00695 <span class="preprocessor">#endif</span>
+<a name="l00696"></a>00696 <span class="preprocessor"></span>
+<a name="l00697"></a>00697         doeptsize0.<a class="code" href="uniondeptsiz0__data.html#8e50594573fd774fc3e27404d8b1f59c">b</a>.<a class="code" href="uniondeptsiz0__data.html#60123707d51d7dfa22cd6b245402e49b">supcnt</a> = 3;
+<a name="l00698"></a>00698         doeptsize0.<a class="code" href="uniondeptsiz0__data.html#8e50594573fd774fc3e27404d8b1f59c">b</a>.<a class="code" href="uniondeptsiz0__data.html#debb8f273e4480cde57bef7677697bd0">pktcnt</a> = 1;
+<a name="l00699"></a>00699         doeptsize0.<a class="code" href="uniondeptsiz0__data.html#8e50594573fd774fc3e27404d8b1f59c">b</a>.<a class="code" href="uniondeptsiz0__data.html#1792e672dde70ead19bd0f5e7642af03">xfersize</a> = 8 * 3;
+<a name="l00700"></a>00700 
+<a name="l00701"></a>00701         <span class="keywordflow">if</span> (<a class="code" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a>) {
+<a name="l00702"></a>00702                 <span class="keywordflow">if</span> (!<a class="code" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a>) {
+<a name="l00704"></a>00704                         dwc_write_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">out_ep_regs</a>[0]-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#e756ec48787099f0a4e2ce353fce4f91">doeptsiz</a>,
+<a name="l00705"></a>00705                                         doeptsize0.<a class="code" href="uniondeptsiz0__data.html#a06fa9b1dcaee47fba9cf869027ed6f1">d32</a>);
+<a name="l00706"></a>00706 
+<a name="l00708"></a>00708                         dwc_write_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">out_ep_regs</a>[0]-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#006071bf54bfa1c1f5e25cf4c9f65cb1">doepdma</a>,
+<a name="l00709"></a>00709                                         pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#606d94ec61cca4c21e4dc9cb2e3b7064">setup_pkt_dma_handle</a>);
+<a name="l00710"></a>00710                 } <span class="keywordflow">else</span> {
+<a name="l00711"></a>00711                         dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#dd45f3935b2ebb171de8da70cddd6935">setup_desc_index</a> =
+<a name="l00712"></a>00712                             (dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#dd45f3935b2ebb171de8da70cddd6935">setup_desc_index</a> + 1) &amp; 1;
+<a name="l00713"></a>00713                         dma_desc =
+<a name="l00714"></a>00714                             dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#f149a6cbedd5f180ff033caeee6f527e">setup_desc_addr</a>[dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#dd45f3935b2ebb171de8da70cddd6935">setup_desc_index</a>];
+<a name="l00715"></a>00715 
+<a name="l00717"></a>00717                         dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#1876c32496f0067948f6282b7583aeab">b</a>.<a class="code" href="uniondev__dma__desc__sts.html#05d1c1d8f6c5a1967c51c5d0e2e04261">bs</a> = <a class="code" href="dwc__otg__regs_8h.html#e6e96a79797557986256d1a1ff104ca1">BS_HOST_BUSY</a>;
+<a name="l00718"></a>00718                         dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#1876c32496f0067948f6282b7583aeab">b</a>.<a class="code" href="uniondev__dma__desc__sts.html#b728a79d6a86a0d1b6426a1b2627f2c2">l</a> = 1;
+<a name="l00719"></a>00719                         dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#1876c32496f0067948f6282b7583aeab">b</a>.<a class="code" href="uniondev__dma__desc__sts.html#02c8be72ef6258c25094478c7cac0b12">ioc</a> = 1;
+<a name="l00720"></a>00720                         dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#1876c32496f0067948f6282b7583aeab">b</a>.<a class="code" href="uniondev__dma__desc__sts.html#9b6181d78984cb4d853945774f300ef0">bytes</a> = pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a>.<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a>;
+<a name="l00721"></a>00721                         dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#0454dad420ef536fe5eb7c38ef764430">buf</a> = pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#606d94ec61cca4c21e4dc9cb2e3b7064">setup_pkt_dma_handle</a>;
+<a name="l00722"></a>00722                         dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#1876c32496f0067948f6282b7583aeab">b</a>.<a class="code" href="uniondev__dma__desc__sts.html#05d1c1d8f6c5a1967c51c5d0e2e04261">bs</a> = <a class="code" href="dwc__otg__regs_8h.html#c2cfc53da94087a90d21d3528b005bcf">BS_HOST_READY</a>;
+<a name="l00723"></a>00723 
+<a name="l00725"></a>00725                         dwc_write_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">out_ep_regs</a>[0]-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#006071bf54bfa1c1f5e25cf4c9f65cb1">doepdma</a>,
+<a name="l00726"></a>00726                                         dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#fb3d3353afd5f9d08a8e49c48158cfb7">dma_setup_desc_addr</a>[dev_if-&gt;
+<a name="l00727"></a>00727                                                                     setup_desc_index]);
+<a name="l00728"></a>00728                 }
+<a name="l00729"></a>00729 
+<a name="l00730"></a>00730         } <span class="keywordflow">else</span> {
+<a name="l00732"></a>00732                 dwc_write_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">out_ep_regs</a>[0]-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#e756ec48787099f0a4e2ce353fce4f91">doeptsiz</a>,
+<a name="l00733"></a>00733                                 doeptsize0.<a class="code" href="uniondeptsiz0__data.html#a06fa9b1dcaee47fba9cf869027ed6f1">d32</a>);
+<a name="l00734"></a>00734         }
+<a name="l00735"></a>00735 
+<a name="l00737"></a>00737         doepctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#337ceb41a9e0735e144e684b1f9e5368">epena</a> = 1;
+<a name="l00738"></a>00738         doepctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#0b87d0914ceee7a20ffd2d7510b6a72e">cnak</a> = 1;
+<a name="l00739"></a>00739         dwc_write_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">out_ep_regs</a>[0]-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#2a522b71fc97658c07debf3521f7d3e5">doepctl</a>, doepctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a>);
+<a name="l00740"></a>00740 
+<a name="l00741"></a>00741 <span class="preprocessor">#ifdef VERBOSE</span>
+<a name="l00742"></a>00742 <span class="preprocessor"></span>        <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"doepctl0=%0x\n"</span>,
+<a name="l00743"></a>00743                     dwc_read_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">out_ep_regs</a>[0]-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#2a522b71fc97658c07debf3521f7d3e5">doepctl</a>));
+<a name="l00744"></a>00744         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"diepctl0=%0x\n"</span>,
+<a name="l00745"></a>00745                     dwc_read_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[0]-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#53a5adb977e2aec66d4902c6ba293216">diepctl</a>));
+<a name="l00746"></a>00746 <span class="preprocessor">#endif</span>
+<a name="l00747"></a>00747 <span class="preprocessor"></span>}
+<a name="l00748"></a>00748 
+<a name="l00772"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#84746037a82c1f69287033338991d34a">00772</a> int32_t <a class="code" href="dwc__otg__pcd__intr_8c.html#84746037a82c1f69287033338991d34a">dwc_otg_pcd_handle_usb_reset_intr</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd)
+<a name="l00773"></a>00773 {
+<a name="l00774"></a>00774         <a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *<a class="code" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">core_if</a> = <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd);
+<a name="l00775"></a>00775         <a class="code" href="structdwc__otg__dev__if.html">dwc_otg_dev_if_t</a> *dev_if = <a class="code" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>;
+<a name="l00776"></a>00776         <a class="code" href="uniondepctl__data.html">depctl_data_t</a> doepctl = {.d32 = 0 };
+<a name="l00777"></a>00777         <a class="code" href="uniondaint__data.html">daint_data_t</a> daintmsk = {.d32 = 0 };
+<a name="l00778"></a>00778         <a class="code" href="uniondoepint__data.html">doepmsk_data_t</a> doepmsk = {.d32 = 0 };
+<a name="l00779"></a>00779         <a class="code" href="uniondiepint__data.html">diepmsk_data_t</a> diepmsk = {.d32 = 0 };
+<a name="l00780"></a>00780         <a class="code" href="uniondcfg__data.html">dcfg_data_t</a> dcfg = {.d32 = 0 };
+<a name="l00781"></a>00781         <a class="code" href="uniongrstctl__data.html">grstctl_t</a> resetctl = {.d32 = 0 };
+<a name="l00782"></a>00782         <a class="code" href="uniondctl__data.html">dctl_data_t</a> dctl = {.d32 = 0 };
+<a name="l00783"></a>00783         <span class="keywordtype">int</span> i = 0;
+<a name="l00784"></a>00784         <a class="code" href="uniongintsts__data.html">gintsts_data_t</a> gintsts;
+<a name="l00785"></a>00785         <a class="code" href="unionpcgcctl__data.html">pcgcctl_data_t</a> power = {.d32 = 0 };
+<a name="l00786"></a>00786 
+<a name="l00787"></a>00787         power.<a class="code" href="unionpcgcctl__data.html#abe048ee884143501929b27d94c52db7">d32</a> = dwc_read_reg32(<a class="code" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#348ed2c9aeae6fc608f1bb813978b3f9">pcgcctl</a>);
+<a name="l00788"></a>00788         <span class="keywordflow">if</span> (power.<a class="code" href="unionpcgcctl__data.html#f2bb76709d0ab9d08280eafb78a36279">b</a>.<a class="code" href="unionpcgcctl__data.html#bf40184845ef70be8e59b2672cb0bedf">stoppclk</a>) {
+<a name="l00789"></a>00789                 power.<a class="code" href="unionpcgcctl__data.html#abe048ee884143501929b27d94c52db7">d32</a> = 0;
+<a name="l00790"></a>00790                 power.<a class="code" href="unionpcgcctl__data.html#f2bb76709d0ab9d08280eafb78a36279">b</a>.<a class="code" href="unionpcgcctl__data.html#bf40184845ef70be8e59b2672cb0bedf">stoppclk</a> = 1;
+<a name="l00791"></a>00791                 dwc_modify_reg32(<a class="code" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#348ed2c9aeae6fc608f1bb813978b3f9">pcgcctl</a>, power.<a class="code" href="unionpcgcctl__data.html#abe048ee884143501929b27d94c52db7">d32</a>, 0);
+<a name="l00792"></a>00792 
+<a name="l00793"></a>00793                 power.<a class="code" href="unionpcgcctl__data.html#f2bb76709d0ab9d08280eafb78a36279">b</a>.<a class="code" href="unionpcgcctl__data.html#02d7dff0f26c3ac50ad4b876f1853c17">pwrclmp</a> = 1;
+<a name="l00794"></a>00794                 dwc_modify_reg32(<a class="code" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#348ed2c9aeae6fc608f1bb813978b3f9">pcgcctl</a>, power.<a class="code" href="unionpcgcctl__data.html#abe048ee884143501929b27d94c52db7">d32</a>, 0);
+<a name="l00795"></a>00795 
+<a name="l00796"></a>00796                 power.<a class="code" href="unionpcgcctl__data.html#f2bb76709d0ab9d08280eafb78a36279">b</a>.<a class="code" href="unionpcgcctl__data.html#9708a50a6e42cd2372d65555edf5cf28">rstpdwnmodule</a> = 1;
+<a name="l00797"></a>00797                 dwc_modify_reg32(<a class="code" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#348ed2c9aeae6fc608f1bb813978b3f9">pcgcctl</a>, power.<a class="code" href="unionpcgcctl__data.html#abe048ee884143501929b27d94c52db7">d32</a>, 0);
+<a name="l00798"></a>00798         }
+<a name="l00799"></a>00799 
+<a name="l00800"></a>00800         <a class="code" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#2b0701d814069ec69897e08374366c7b">lx_state</a> = <a class="code" href="dwc__otg__cil_8h.html#8442e49b7c783099ac17bda4f8b3bc3c9743a36d9b0b8c66a11a0714fdd27fb5">DWC_OTG_L0</a>;
+<a name="l00801"></a>00801 
+<a name="l00802"></a>00802         DWC_PRINTF(<span class="stringliteral">"USB RESET\n"</span>);
+<a name="l00803"></a>00803 <span class="preprocessor">#ifdef DWC_EN_ISOC</span>
+<a name="l00804"></a>00804 <span class="preprocessor"></span>        <span class="keywordflow">for</span> (i = 1; i &lt; 16; ++i) {
+<a name="l00805"></a>00805                 <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *ep;
+<a name="l00806"></a>00806                 <a class="code" href="structdwc__ep.html">dwc_ep_t</a> *<a class="code" href="structdwc__ep.html">dwc_ep</a>;
+<a name="l00807"></a>00807                 ep = <a class="code" href="dwc__otg__pcd__intr_8c.html#cc3f2f1ae0ab7d33903a1d0d9097c04e">get_in_ep</a>(pcd, i);
+<a name="l00808"></a>00808                 <span class="keywordflow">if</span> (ep != 0) {
+<a name="l00809"></a>00809                         dwc_ep = &amp;ep-&gt;dwc_ep;
+<a name="l00810"></a>00810                         dwc_ep-&gt;<a class="code" href="structdwc__ep.html#1e9f4d08454c973c17acb3e52a2c3689">next_frame</a> = 0xffffffff;
+<a name="l00811"></a>00811                 }
+<a name="l00812"></a>00812         }
+<a name="l00813"></a>00813 <span class="preprocessor">#endif                          </span><span class="comment">/* DWC_EN_ISOC */</span>
+<a name="l00814"></a>00814 
+<a name="l00815"></a>00815         <span class="comment">/* reset the HNP settings */</span>
+<a name="l00816"></a>00816         <a class="code" href="dwc__otg__pcd__intr_8c.html#81a9361b81863cef6b2566ea44529185">dwc_otg_pcd_update_otg</a>(pcd, 1);
+<a name="l00817"></a>00817 
+<a name="l00818"></a>00818         <span class="comment">/* Clear the Remote Wakeup Signalling */</span>
+<a name="l00819"></a>00819         dctl.<a class="code" href="uniondctl__data.html#a3abfa6d609d9864f1f65712b409d4d3">b</a>.<a class="code" href="uniondctl__data.html#dcae5af28dc159cd7ba85a9a2b8be51a">rmtwkupsig</a> = 1;
+<a name="l00820"></a>00820         dwc_modify_reg32(&amp;<a class="code" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#3779c2fc508920a831a59e696a8fa785">dctl</a>, dctl.<a class="code" href="uniondctl__data.html#f49aadfd7ad95b570115b3c245b1729e">d32</a>, 0);
+<a name="l00821"></a>00821 
+<a name="l00822"></a>00822         <span class="comment">/* Set NAK for all OUT EPs */</span>
+<a name="l00823"></a>00823         doepctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#ccf6e60ac8cabde8da36edb19504ba2b">snak</a> = 1;
+<a name="l00824"></a>00824         <span class="keywordflow">for</span> (i = 0; i &lt;= dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#2f0e01cdc605623f591963fc83c8dc73">num_out_eps</a>; i++) {
+<a name="l00825"></a>00825                 dwc_write_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">out_ep_regs</a>[i]-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#2a522b71fc97658c07debf3521f7d3e5">doepctl</a>, doepctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a>);
+<a name="l00826"></a>00826         }
+<a name="l00827"></a>00827 
+<a name="l00828"></a>00828         <span class="comment">/* Flush the NP Tx FIFO */</span>
+<a name="l00829"></a>00829         <a class="code" href="dwc__otg__cil_8c.html#039e387cd0e0282727da3c5a36f4cdda">dwc_otg_flush_tx_fifo</a>(<a class="code" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">core_if</a>, 0x10);
+<a name="l00830"></a>00830         <span class="comment">/* Flush the Learning Queue */</span>
+<a name="l00831"></a>00831         resetctl.<a class="code" href="uniongrstctl__data.html#7907ac8831a2f72dec59592a093871e3">b</a>.<a class="code" href="uniongrstctl__data.html#259049fa7991ecad9ca1595763b636f9">intknqflsh</a> = 1;
+<a name="l00832"></a>00832         dwc_write_reg32(&amp;<a class="code" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#49d307957dbe53f20aa8f7a5409ee8ad">grstctl</a>, resetctl.<a class="code" href="uniongrstctl__data.html#d89d99c95bd5177fbd879d38963d3e62">d32</a>);
+<a name="l00833"></a>00833 
+<a name="l00834"></a>00834         <span class="keywordflow">if</span> (<a class="code" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#5675c8d8dd7df746fda9157dc39ba5c2">multiproc_int_enable</a>) {
+<a name="l00835"></a>00835                 daintmsk.<a class="code" href="uniondaint__data.html#a75e47f1eb750ddd9b8213086fd49317">b</a>.<a class="code" href="uniondaint__data.html#371eb39ddd249f984242ffc6bc2590ba">inep0</a> = 1;
+<a name="l00836"></a>00836                 daintmsk.<a class="code" href="uniondaint__data.html#a75e47f1eb750ddd9b8213086fd49317">b</a>.<a class="code" href="uniondaint__data.html#c7e9083edca852fb7f2f64e8671aee84">outep0</a> = 1;
+<a name="l00837"></a>00837                 dwc_write_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#e64a153683f0e0cda14b56a163651825">deachintmsk</a>,
+<a name="l00838"></a>00838                                 daintmsk.<a class="code" href="uniondaint__data.html#cf05e79bf751384bef904448a231bc41">d32</a>);
+<a name="l00839"></a>00839 
+<a name="l00840"></a>00840                 doepmsk.<a class="code" href="uniondoepint__data.html#9e966d9f85589f278dc2c0d0c7833856">b</a>.<a class="code" href="uniondoepint__data.html#b286d1b76f09a9122aca23e430b63dc8">setup</a> = 1;
+<a name="l00841"></a>00841                 doepmsk.<a class="code" href="uniondoepint__data.html#9e966d9f85589f278dc2c0d0c7833856">b</a>.<a class="code" href="uniondoepint__data.html#341f7ffa5a9da7f6b1e09e9f4cc516a3">xfercompl</a> = 1;
+<a name="l00842"></a>00842                 doepmsk.<a class="code" href="uniondoepint__data.html#9e966d9f85589f278dc2c0d0c7833856">b</a>.<a class="code" href="uniondoepint__data.html#cdfedbad6643d94271e91e135485a68d">ahberr</a> = 1;
+<a name="l00843"></a>00843                 doepmsk.<a class="code" href="uniondoepint__data.html#9e966d9f85589f278dc2c0d0c7833856">b</a>.<a class="code" href="uniondoepint__data.html#8a263ddc3ab9080b8c2e02ccead0c983">epdisabled</a> = 1;
+<a name="l00844"></a>00844 
+<a name="l00845"></a>00845                 <span class="keywordflow">if</span> (<a class="code" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a>) {
+<a name="l00846"></a>00846                         doepmsk.<a class="code" href="uniondoepint__data.html#9e966d9f85589f278dc2c0d0c7833856">b</a>.<a class="code" href="uniondoepint__data.html#038fca8f1c03d7cfe323caa4f8bda126">stsphsercvd</a> = 1;
+<a name="l00847"></a>00847                         doepmsk.<a class="code" href="uniondoepint__data.html#9e966d9f85589f278dc2c0d0c7833856">b</a>.<a class="code" href="uniondoepint__data.html#e68e77d553158195b16a790012f9627d">bna</a> = 1;
+<a name="l00848"></a>00848                 }
+<a name="l00849"></a>00849 <span class="comment">/*              </span>
+<a name="l00850"></a>00850 <span class="comment">                doepmsk.b.babble = 1;</span>
+<a name="l00851"></a>00851 <span class="comment">                doepmsk.b.nyet = 1;</span>
+<a name="l00852"></a>00852 <span class="comment">                </span>
+<a name="l00853"></a>00853 <span class="comment">                if(core_if-&gt;dma_enable) {</span>
+<a name="l00854"></a>00854 <span class="comment">                        doepmsk.b.nak = 1;</span>
+<a name="l00855"></a>00855 <span class="comment">                }</span>
+<a name="l00856"></a>00856 <span class="comment">*/</span>
+<a name="l00857"></a>00857                 dwc_write_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#304e089ed2d36d9076228b8d7e1cc515">doepeachintmsk</a>[0],
+<a name="l00858"></a>00858                                 doepmsk.<a class="code" href="uniondoepint__data.html#94f8c8fc116b430565f9322e3621b3a5">d32</a>);
+<a name="l00859"></a>00859 
+<a name="l00860"></a>00860                 diepmsk.<a class="code" href="uniondiepint__data.html#48d2a745e0ec983a47b35b0428b0437d">b</a>.<a class="code" href="uniondiepint__data.html#56e1252841323973e0ada12cc89059c9">xfercompl</a> = 1;
+<a name="l00861"></a>00861                 diepmsk.<a class="code" href="uniondiepint__data.html#48d2a745e0ec983a47b35b0428b0437d">b</a>.<a class="code" href="uniondiepint__data.html#2513e8eef259c711e9a139cb2631b142">timeout</a> = 1;
+<a name="l00862"></a>00862                 diepmsk.<a class="code" href="uniondiepint__data.html#48d2a745e0ec983a47b35b0428b0437d">b</a>.<a class="code" href="uniondiepint__data.html#3a649b75195fb5b26135d75b03cf561d">epdisabled</a> = 1;
+<a name="l00863"></a>00863                 diepmsk.<a class="code" href="uniondiepint__data.html#48d2a745e0ec983a47b35b0428b0437d">b</a>.<a class="code" href="uniondiepint__data.html#6d57fa84f687bc4f05013c1e1a7edf29">ahberr</a> = 1;
+<a name="l00864"></a>00864                 diepmsk.<a class="code" href="uniondiepint__data.html#48d2a745e0ec983a47b35b0428b0437d">b</a>.<a class="code" href="uniondiepint__data.html#103fb29d954cf12d33f7ebe6009f9a46">intknepmis</a> = 1;
+<a name="l00865"></a>00865 
+<a name="l00866"></a>00866                 <span class="keywordflow">if</span> (<a class="code" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a>) {
+<a name="l00867"></a>00867                         diepmsk.<a class="code" href="uniondiepint__data.html#48d2a745e0ec983a47b35b0428b0437d">b</a>.<a class="code" href="uniondiepint__data.html#2530c984ae3ebda73405d98080d8a57b">bna</a> = 1;
+<a name="l00868"></a>00868                 }
+<a name="l00869"></a>00869 <span class="comment">/*              </span>
+<a name="l00870"></a>00870 <span class="comment">                if(core_if-&gt;dma_enable) {</span>
+<a name="l00871"></a>00871 <span class="comment">                        diepmsk.b.nak = 1;</span>
+<a name="l00872"></a>00872 <span class="comment">                }</span>
+<a name="l00873"></a>00873 <span class="comment">*/</span>
+<a name="l00874"></a>00874                 dwc_write_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#aaf2a5c6be4130d558c291f6aaeeca4f">diepeachintmsk</a>[0],
+<a name="l00875"></a>00875                                 diepmsk.<a class="code" href="uniondiepint__data.html#7d2c24507663bf96c280c57fbf544ef7">d32</a>);
+<a name="l00876"></a>00876         } <span class="keywordflow">else</span> {
+<a name="l00877"></a>00877                 daintmsk.<a class="code" href="uniondaint__data.html#a75e47f1eb750ddd9b8213086fd49317">b</a>.<a class="code" href="uniondaint__data.html#371eb39ddd249f984242ffc6bc2590ba">inep0</a> = 1;
+<a name="l00878"></a>00878                 daintmsk.<a class="code" href="uniondaint__data.html#a75e47f1eb750ddd9b8213086fd49317">b</a>.<a class="code" href="uniondaint__data.html#c7e9083edca852fb7f2f64e8671aee84">outep0</a> = 1;
+<a name="l00879"></a>00879                 dwc_write_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#5def6c3850c041928b9a662422ee0679">daintmsk</a>,
+<a name="l00880"></a>00880                                 daintmsk.<a class="code" href="uniondaint__data.html#cf05e79bf751384bef904448a231bc41">d32</a>);
+<a name="l00881"></a>00881 
+<a name="l00882"></a>00882                 doepmsk.<a class="code" href="uniondoepint__data.html#9e966d9f85589f278dc2c0d0c7833856">b</a>.<a class="code" href="uniondoepint__data.html#b286d1b76f09a9122aca23e430b63dc8">setup</a> = 1;
+<a name="l00883"></a>00883                 doepmsk.<a class="code" href="uniondoepint__data.html#9e966d9f85589f278dc2c0d0c7833856">b</a>.<a class="code" href="uniondoepint__data.html#341f7ffa5a9da7f6b1e09e9f4cc516a3">xfercompl</a> = 1;
+<a name="l00884"></a>00884                 doepmsk.<a class="code" href="uniondoepint__data.html#9e966d9f85589f278dc2c0d0c7833856">b</a>.<a class="code" href="uniondoepint__data.html#cdfedbad6643d94271e91e135485a68d">ahberr</a> = 1;
+<a name="l00885"></a>00885                 doepmsk.<a class="code" href="uniondoepint__data.html#9e966d9f85589f278dc2c0d0c7833856">b</a>.<a class="code" href="uniondoepint__data.html#8a263ddc3ab9080b8c2e02ccead0c983">epdisabled</a> = 1;
+<a name="l00886"></a>00886 
+<a name="l00887"></a>00887                 <span class="keywordflow">if</span> (<a class="code" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a>) {
+<a name="l00888"></a>00888                         doepmsk.<a class="code" href="uniondoepint__data.html#9e966d9f85589f278dc2c0d0c7833856">b</a>.<a class="code" href="uniondoepint__data.html#038fca8f1c03d7cfe323caa4f8bda126">stsphsercvd</a> = 1;
+<a name="l00889"></a>00889                         doepmsk.<a class="code" href="uniondoepint__data.html#9e966d9f85589f278dc2c0d0c7833856">b</a>.<a class="code" href="uniondoepint__data.html#e68e77d553158195b16a790012f9627d">bna</a> = 1;
+<a name="l00890"></a>00890                 }
+<a name="l00891"></a>00891                 dwc_write_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#d6947be9d84a1d87156f81a10ebb036b">doepmsk</a>, doepmsk.<a class="code" href="uniondoepint__data.html#94f8c8fc116b430565f9322e3621b3a5">d32</a>);
+<a name="l00892"></a>00892 
+<a name="l00893"></a>00893                 diepmsk.<a class="code" href="uniondiepint__data.html#48d2a745e0ec983a47b35b0428b0437d">b</a>.<a class="code" href="uniondiepint__data.html#56e1252841323973e0ada12cc89059c9">xfercompl</a> = 1;
+<a name="l00894"></a>00894                 diepmsk.<a class="code" href="uniondiepint__data.html#48d2a745e0ec983a47b35b0428b0437d">b</a>.<a class="code" href="uniondiepint__data.html#2513e8eef259c711e9a139cb2631b142">timeout</a> = 1;
+<a name="l00895"></a>00895                 diepmsk.<a class="code" href="uniondiepint__data.html#48d2a745e0ec983a47b35b0428b0437d">b</a>.<a class="code" href="uniondiepint__data.html#3a649b75195fb5b26135d75b03cf561d">epdisabled</a> = 1;
+<a name="l00896"></a>00896                 diepmsk.<a class="code" href="uniondiepint__data.html#48d2a745e0ec983a47b35b0428b0437d">b</a>.<a class="code" href="uniondiepint__data.html#6d57fa84f687bc4f05013c1e1a7edf29">ahberr</a> = 1;
+<a name="l00897"></a>00897                 diepmsk.<a class="code" href="uniondiepint__data.html#48d2a745e0ec983a47b35b0428b0437d">b</a>.<a class="code" href="uniondiepint__data.html#103fb29d954cf12d33f7ebe6009f9a46">intknepmis</a> = 1;
+<a name="l00898"></a>00898 
+<a name="l00899"></a>00899                 <span class="keywordflow">if</span> (<a class="code" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a>) {
+<a name="l00900"></a>00900                         diepmsk.<a class="code" href="uniondiepint__data.html#48d2a745e0ec983a47b35b0428b0437d">b</a>.<a class="code" href="uniondiepint__data.html#2530c984ae3ebda73405d98080d8a57b">bna</a> = 1;
+<a name="l00901"></a>00901                 }
+<a name="l00902"></a>00902 
+<a name="l00903"></a>00903                 dwc_write_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#02e44cb182548d78c5b7d27929ca5f11">diepmsk</a>, diepmsk.<a class="code" href="uniondiepint__data.html#7d2c24507663bf96c280c57fbf544ef7">d32</a>);
+<a name="l00904"></a>00904         }
+<a name="l00905"></a>00905 
+<a name="l00906"></a>00906         <span class="comment">/* Reset Device Address */</span>
+<a name="l00907"></a>00907         dcfg.<a class="code" href="uniondcfg__data.html#efd84d3306db1b4370535a0e814612dc">d32</a> = dwc_read_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#c0c24937bbd7184884f05343f56ef1da">dcfg</a>);
+<a name="l00908"></a>00908         dcfg.<a class="code" href="uniondcfg__data.html#242c1b463f445de3fc265e8c20fde50b">b</a>.<a class="code" href="uniondcfg__data.html#71c70afb48dd124d12e43d86edd90f1e">devaddr</a> = 0;
+<a name="l00909"></a>00909         dwc_write_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#c0c24937bbd7184884f05343f56ef1da">dcfg</a>, dcfg.<a class="code" href="uniondcfg__data.html#efd84d3306db1b4370535a0e814612dc">d32</a>);
+<a name="l00910"></a>00910 
+<a name="l00911"></a>00911         <span class="comment">/* setup EP0 to receive SETUP packets */</span>
+<a name="l00912"></a>00912         <a class="code" href="dwc__otg__pcd__intr_8c.html#726b57833bb3ae4648ce7e7a7e125bf7">ep0_out_start</a>(<a class="code" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">core_if</a>, pcd);
+<a name="l00913"></a>00913 
+<a name="l00914"></a>00914         <span class="comment">/* Clear interrupt */</span>
+<a name="l00915"></a>00915         gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a> = 0;
+<a name="l00916"></a>00916         gintsts.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#76926be659d963c79dbcec91e25ce8ed">usbreset</a> = 1;
+<a name="l00917"></a>00917         dwc_write_reg32(&amp;<a class="code" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>, gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a>);
+<a name="l00918"></a>00918 
+<a name="l00919"></a>00919         <span class="keywordflow">return</span> 1;
+<a name="l00920"></a>00920 }
+<a name="l00921"></a>00921 
+<a name="l00928"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#6a3ddac8955990b9a63646c40c65446b">00928</a> <span class="keyword">static</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__pcd__intr_8c.html#6a3ddac8955990b9a63646c40c65446b">get_device_speed</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * <a class="code" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">core_if</a>)
+<a name="l00929"></a>00929 {
+<a name="l00930"></a>00930         <a class="code" href="uniondsts__data.html">dsts_data_t</a> dsts;
+<a name="l00931"></a>00931         <span class="keywordtype">int</span> speed = 0;
+<a name="l00932"></a>00932         dsts.<a class="code" href="uniondsts__data.html#0f126daef735b142b06dbc4cdbe13814">d32</a> = dwc_read_reg32(&amp;<a class="code" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#1ed00edd20ce5db7d07666804101ec05">dsts</a>);
+<a name="l00933"></a>00933 
+<a name="l00934"></a>00934         <span class="keywordflow">switch</span> (dsts.<a class="code" href="uniondsts__data.html#4066fcedb7ac9a88e47aa1b2df0e89ee">b</a>.<a class="code" href="uniondsts__data.html#f918f3d04b026687af3e1953f5c79fea">enumspd</a>) {
+<a name="l00935"></a>00935         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__regs_8h.html#2c41cb64f1ba728146bece30a622044c">DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ</a>:
+<a name="l00936"></a>00936                 speed = USB_SPEED_HIGH;
+<a name="l00937"></a>00937                 <span class="keywordflow">break</span>;
+<a name="l00938"></a>00938         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__regs_8h.html#373742ad0a97af406169cc3ada63ca04">DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ</a>:
+<a name="l00939"></a>00939         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__regs_8h.html#81dafef32b78df31eb2eeac36fd0694a">DWC_DSTS_ENUMSPD_FS_PHY_48MHZ</a>:
+<a name="l00940"></a>00940                 speed = USB_SPEED_FULL;
+<a name="l00941"></a>00941                 <span class="keywordflow">break</span>;
+<a name="l00942"></a>00942 
+<a name="l00943"></a>00943         <span class="keywordflow">case</span> <a class="code" href="dwc__otg__regs_8h.html#7df682e9f37924c859657ff26fee5cbc">DWC_DSTS_ENUMSPD_LS_PHY_6MHZ</a>:
+<a name="l00944"></a>00944                 speed = USB_SPEED_LOW;
+<a name="l00945"></a>00945                 <span class="keywordflow">break</span>;
+<a name="l00946"></a>00946         }
+<a name="l00947"></a>00947 
+<a name="l00948"></a>00948         <span class="keywordflow">return</span> speed;
+<a name="l00949"></a>00949 }
+<a name="l00950"></a>00950 
+<a name="l00956"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#c8003957f588b4bb57061208ea031468">00956</a> int32_t <a class="code" href="dwc__otg__pcd__intr_8c.html#c8003957f588b4bb57061208ea031468">dwc_otg_pcd_handle_enum_done_intr</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd)
+<a name="l00957"></a>00957 {
+<a name="l00958"></a>00958         <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *<a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a> = &amp;pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a>;
+<a name="l00959"></a>00959         <a class="code" href="uniongintsts__data.html">gintsts_data_t</a> gintsts;
+<a name="l00960"></a>00960         <a class="code" href="uniongusbcfg__data.html">gusbcfg_data_t</a> gusbcfg;
+<a name="l00961"></a>00961         <a class="code" href="structdwc__otg__core__global__regs.html">dwc_otg_core_global_regs_t</a> *global_regs =
+<a name="l00962"></a>00962             <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;core_global_regs;
+<a name="l00963"></a>00963         uint8_t utmi16b, utmi8b;
+<a name="l00964"></a>00964         <span class="keywordtype">int</span> speed;
+<a name="l00965"></a>00965         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"SPEED ENUM\n"</span>);
+<a name="l00966"></a>00966 
+<a name="l00967"></a>00967         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;snpsid &gt;= <a class="code" href="dwc__otg__cil_8h.html#51536e4844fe9022b60531eebca32a26">OTG_CORE_REV_2_60a</a>) {
+<a name="l00968"></a>00968                 utmi16b = 6;
+<a name="l00969"></a>00969                 utmi8b = 9;
+<a name="l00970"></a>00970         } <span class="keywordflow">else</span> {
+<a name="l00971"></a>00971                 utmi16b = 4;
+<a name="l00972"></a>00972                 utmi8b = 8;
+<a name="l00973"></a>00973         }
+<a name="l00974"></a>00974         <a class="code" href="dwc__otg__cil_8c.html#8ebf5023c783a2ec48a18a5b9aef4a87">dwc_otg_ep0_activate</a>(<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd), &amp;<a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>);
+<a name="l00975"></a>00975 
+<a name="l00976"></a>00976 <span class="preprocessor">#ifdef DEBUG_EP0</span>
+<a name="l00977"></a>00977 <span class="preprocessor"></span>        <a class="code" href="dwc__otg__pcd__intr_8c.html#13cc45eef95b81189df890c10cf7ca66">print_ep0_state</a>(pcd);
+<a name="l00978"></a>00978 <span class="preprocessor">#endif</span>
+<a name="l00979"></a>00979 <span class="preprocessor"></span>
+<a name="l00980"></a>00980         <span class="keywordflow">if</span> (pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#8f6963b3fb9ab83048c4c0697c90382a">ep0state</a> == EP0_DISCONNECT) {
+<a name="l00981"></a>00981                 pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#8f6963b3fb9ab83048c4c0697c90382a">ep0state</a> = EP0_IDLE;
+<a name="l00982"></a>00982         } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#8f6963b3fb9ab83048c4c0697c90382a">ep0state</a> == EP0_STALL) {
+<a name="l00983"></a>00983                 pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#8f6963b3fb9ab83048c4c0697c90382a">ep0state</a> = EP0_IDLE;
+<a name="l00984"></a>00984         }
+<a name="l00985"></a>00985 
+<a name="l00986"></a>00986         pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#8f6963b3fb9ab83048c4c0697c90382a">ep0state</a> = EP0_IDLE;
+<a name="l00987"></a>00987 
+<a name="l00988"></a>00988         <a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#cce0e089118d8bf7c6278c21ded70d5a">stopped</a> = 0;
+<a name="l00989"></a>00989 
+<a name="l00990"></a>00990         speed = <a class="code" href="dwc__otg__pcd__intr_8c.html#6a3ddac8955990b9a63646c40c65446b">get_device_speed</a>(<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd));
+<a name="l00991"></a>00991         pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#b7001dde5db2706707a860da0030d9e6">fops</a>-&gt;<a class="code" href="structdwc__otg__pcd__function__ops.html#4d3df508947b8ba75c5537617227cf9c">connect</a>(pcd, speed);
+<a name="l00992"></a>00992 
+<a name="l00993"></a>00993         <span class="comment">/* Set USB turnaround time based on device speed and PHY interface. */</span>
+<a name="l00994"></a>00994         gusbcfg.<a class="code" href="uniongusbcfg__data.html#c3d8f2d95fd61a172eb108cb72a85b47">d32</a> = dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#ef39e181e246447df47c56aa4e37cc42">gusbcfg</a>);
+<a name="l00995"></a>00995         <span class="keywordflow">if</span> (speed == USB_SPEED_HIGH) {
+<a name="l00996"></a>00996                 <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;hwcfg2.b.hs_phy_type ==
+<a name="l00997"></a>00997                     <a class="code" href="dwc__otg__regs_8h.html#0633e41edfacfabfb7ba32f972dc0479">DWC_HWCFG2_HS_PHY_TYPE_ULPI</a>) {
+<a name="l00998"></a>00998                         <span class="comment">/* ULPI interface */</span>
+<a name="l00999"></a>00999                         gusbcfg.<a class="code" href="uniongusbcfg__data.html#1dab81bf7260b1e23f97298c34abea06">b</a>.<a class="code" href="uniongusbcfg__data.html#d3e238db709189683bc41db2a67e9d61">usbtrdtim</a> = 9;
+<a name="l01000"></a>01000                 }
+<a name="l01001"></a>01001                 <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;hwcfg2.b.hs_phy_type ==
+<a name="l01002"></a>01002                     <a class="code" href="dwc__otg__regs_8h.html#e216917509a2f9a01493b5d9acc8717c">DWC_HWCFG2_HS_PHY_TYPE_UTMI</a>) {
+<a name="l01003"></a>01003                         <span class="comment">/* UTMI+ interface */</span>
+<a name="l01004"></a>01004                         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;hwcfg4.b.utmi_phy_data_width == 0) {
+<a name="l01005"></a>01005                                 gusbcfg.<a class="code" href="uniongusbcfg__data.html#1dab81bf7260b1e23f97298c34abea06">b</a>.<a class="code" href="uniongusbcfg__data.html#d3e238db709189683bc41db2a67e9d61">usbtrdtim</a> = utmi8b;
+<a name="l01006"></a>01006                         } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;hwcfg4.b.
+<a name="l01007"></a>01007                                    utmi_phy_data_width == 1) {
+<a name="l01008"></a>01008                                 gusbcfg.<a class="code" href="uniongusbcfg__data.html#1dab81bf7260b1e23f97298c34abea06">b</a>.<a class="code" href="uniongusbcfg__data.html#d3e238db709189683bc41db2a67e9d61">usbtrdtim</a> = utmi16b;
+<a name="l01009"></a>01009                         } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;core_params-&gt;
+<a name="l01010"></a>01010                                    phy_utmi_width == 8) {
+<a name="l01011"></a>01011                                 gusbcfg.<a class="code" href="uniongusbcfg__data.html#1dab81bf7260b1e23f97298c34abea06">b</a>.<a class="code" href="uniongusbcfg__data.html#d3e238db709189683bc41db2a67e9d61">usbtrdtim</a> = utmi8b;
+<a name="l01012"></a>01012                         } <span class="keywordflow">else</span> {
+<a name="l01013"></a>01013                                 gusbcfg.<a class="code" href="uniongusbcfg__data.html#1dab81bf7260b1e23f97298c34abea06">b</a>.<a class="code" href="uniongusbcfg__data.html#d3e238db709189683bc41db2a67e9d61">usbtrdtim</a> = utmi16b;
+<a name="l01014"></a>01014                         }
+<a name="l01015"></a>01015                 }
+<a name="l01016"></a>01016                 <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;hwcfg2.b.hs_phy_type ==
+<a name="l01017"></a>01017                     <a class="code" href="dwc__otg__regs_8h.html#0a3e7ebf66c6ecde6d4fc4e6d5e14d5e">DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI</a>) {
+<a name="l01018"></a>01018                         <span class="comment">/* UTMI+  OR  ULPI interface */</span>
+<a name="l01019"></a>01019                         <span class="keywordflow">if</span> (gusbcfg.<a class="code" href="uniongusbcfg__data.html#1dab81bf7260b1e23f97298c34abea06">b</a>.<a class="code" href="uniongusbcfg__data.html#f86631568e6d3682cdba6482608bdcfe">ulpi_utmi_sel</a> == 1) {
+<a name="l01020"></a>01020                                 <span class="comment">/* ULPI interface */</span>
+<a name="l01021"></a>01021                                 gusbcfg.<a class="code" href="uniongusbcfg__data.html#1dab81bf7260b1e23f97298c34abea06">b</a>.<a class="code" href="uniongusbcfg__data.html#d3e238db709189683bc41db2a67e9d61">usbtrdtim</a> = 9;
+<a name="l01022"></a>01022                         } <span class="keywordflow">else</span> {
+<a name="l01023"></a>01023                                 <span class="comment">/* UTMI+ interface */</span>
+<a name="l01024"></a>01024                                 <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;core_params-&gt;
+<a name="l01025"></a>01025                                     phy_utmi_width == 16) {
+<a name="l01026"></a>01026                                         gusbcfg.<a class="code" href="uniongusbcfg__data.html#1dab81bf7260b1e23f97298c34abea06">b</a>.<a class="code" href="uniongusbcfg__data.html#d3e238db709189683bc41db2a67e9d61">usbtrdtim</a> = utmi16b;
+<a name="l01027"></a>01027                                 } <span class="keywordflow">else</span> {
+<a name="l01028"></a>01028                                         gusbcfg.<a class="code" href="uniongusbcfg__data.html#1dab81bf7260b1e23f97298c34abea06">b</a>.<a class="code" href="uniongusbcfg__data.html#d3e238db709189683bc41db2a67e9d61">usbtrdtim</a> = utmi8b;
+<a name="l01029"></a>01029                                 }
+<a name="l01030"></a>01030                         }
+<a name="l01031"></a>01031                 }
+<a name="l01032"></a>01032         } <span class="keywordflow">else</span> {
+<a name="l01033"></a>01033                 <span class="comment">/* Full or low speed */</span>
+<a name="l01034"></a>01034                 gusbcfg.<a class="code" href="uniongusbcfg__data.html#1dab81bf7260b1e23f97298c34abea06">b</a>.<a class="code" href="uniongusbcfg__data.html#d3e238db709189683bc41db2a67e9d61">usbtrdtim</a> = 9;
+<a name="l01035"></a>01035         }
+<a name="l01036"></a>01036         dwc_write_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#ef39e181e246447df47c56aa4e37cc42">gusbcfg</a>, gusbcfg.<a class="code" href="uniongusbcfg__data.html#c3d8f2d95fd61a172eb108cb72a85b47">d32</a>);
+<a name="l01037"></a>01037 
+<a name="l01038"></a>01038         <span class="comment">/* Clear interrupt */</span>
+<a name="l01039"></a>01039         gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a> = 0;
+<a name="l01040"></a>01040         gintsts.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#84e707787b50ee3867786c8e0995f41e">enumdone</a> = 1;
+<a name="l01041"></a>01041         dwc_write_reg32(&amp;<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;core_global_regs-&gt;gintsts,
+<a name="l01042"></a>01042                         gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a>);
+<a name="l01043"></a>01043         <span class="keywordflow">return</span> 1;
+<a name="l01044"></a>01044 }
+<a name="l01045"></a>01045 
+<a name="l01051"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#7dbc68baede550f27e1507bca8e16c3b">01051</a> int32_t <a class="code" href="dwc__otg__pcd__intr_8c.html#7dbc68baede550f27e1507bca8e16c3b">dwc_otg_pcd_handle_isoc_out_packet_dropped_intr</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd)
+<a name="l01052"></a>01052 {
+<a name="l01053"></a>01053         <a class="code" href="uniongintmsk__data.html">gintmsk_data_t</a> intr_mask = {.d32 = 0 };
+<a name="l01054"></a>01054         <a class="code" href="uniongintsts__data.html">gintsts_data_t</a> gintsts;
+<a name="l01055"></a>01055 
+<a name="l01056"></a>01056         DWC_PRINTF(<span class="stringliteral">"INTERRUPT Handler not implemented for %s\n"</span>,
+<a name="l01057"></a>01057                    <span class="stringliteral">"ISOC Out Dropped"</span>);
+<a name="l01058"></a>01058 
+<a name="l01059"></a>01059         intr_mask.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#3a0a75b129ccdaed6d98d1982b374d52">isooutdrop</a> = 1;
+<a name="l01060"></a>01060         dwc_modify_reg32(&amp;<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;core_global_regs-&gt;gintmsk,
+<a name="l01061"></a>01061                          intr_mask.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a>, 0);
+<a name="l01062"></a>01062 
+<a name="l01063"></a>01063         <span class="comment">/* Clear interrupt */</span>
+<a name="l01064"></a>01064         gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a> = 0;
+<a name="l01065"></a>01065         gintsts.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#e6e931e1d6226dc110a98cd42c9a8e5f">isooutdrop</a> = 1;
+<a name="l01066"></a>01066         dwc_write_reg32(&amp;<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;core_global_regs-&gt;gintsts,
+<a name="l01067"></a>01067                         gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a>);
+<a name="l01068"></a>01068 
+<a name="l01069"></a>01069         <span class="keywordflow">return</span> 1;
+<a name="l01070"></a>01070 }
+<a name="l01071"></a>01071 
+<a name="l01077"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#a0826c93566bb0144e2fce79fd5d459a">01077</a> int32_t <a class="code" href="dwc__otg__pcd__intr_8c.html#a0826c93566bb0144e2fce79fd5d459a">dwc_otg_pcd_handle_end_periodic_frame_intr</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd)
+<a name="l01078"></a>01078 {
+<a name="l01079"></a>01079         <a class="code" href="uniongintmsk__data.html">gintmsk_data_t</a> intr_mask = {.d32 = 0 };
+<a name="l01080"></a>01080         <a class="code" href="uniongintsts__data.html">gintsts_data_t</a> gintsts;
+<a name="l01081"></a>01081         DWC_PRINTF(<span class="stringliteral">"INTERRUPT Handler not implemented for %s\n"</span>, <span class="stringliteral">"EOP"</span>);
+<a name="l01082"></a>01082 
+<a name="l01083"></a>01083         intr_mask.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#aeb61a24f3c50caacfb8fe523c85768a">eopframe</a> = 1;
+<a name="l01084"></a>01084         dwc_modify_reg32(&amp;<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;core_global_regs-&gt;gintmsk,
+<a name="l01085"></a>01085                          intr_mask.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a>, 0);
+<a name="l01086"></a>01086 
+<a name="l01087"></a>01087         <span class="comment">/* Clear interrupt */</span>
+<a name="l01088"></a>01088         gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a> = 0;
+<a name="l01089"></a>01089         gintsts.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#a731c93eb9e131fadde92da363a85527">eopframe</a> = 1;
+<a name="l01090"></a>01090         dwc_write_reg32(&amp;<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;core_global_regs-&gt;gintsts,
+<a name="l01091"></a>01091                         gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a>);
+<a name="l01092"></a>01092 
+<a name="l01093"></a>01093         <span class="keywordflow">return</span> 1;
+<a name="l01094"></a>01094 }
+<a name="l01095"></a>01095 
+<a name="l01105"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#c45cbe24b507cba84465299e2069ab43">01105</a> int32_t <a class="code" href="dwc__otg__pcd__intr_8c.html#c45cbe24b507cba84465299e2069ab43">dwc_otg_pcd_handle_ep_mismatch_intr</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * <a class="code" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">core_if</a>)
+<a name="l01106"></a>01106 {
+<a name="l01107"></a>01107         <a class="code" href="uniongintsts__data.html">gintsts_data_t</a> gintsts;
+<a name="l01108"></a>01108         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"%s(%p)\n"</span>, __func__, <a class="code" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">core_if</a>);
+<a name="l01109"></a>01109 
+<a name="l01110"></a>01110         <span class="comment">/* Clear interrupt */</span>
+<a name="l01111"></a>01111         gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a> = 0;
+<a name="l01112"></a>01112         gintsts.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#c30e01457b826afc318e5d76e9dfdded">epmismatch</a> = 1;
+<a name="l01113"></a>01113         dwc_write_reg32(&amp;<a class="code" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>, gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a>);
+<a name="l01114"></a>01114 
+<a name="l01115"></a>01115         <span class="keywordflow">return</span> 1;
+<a name="l01116"></a>01116 }
+<a name="l01117"></a>01117 
+<a name="l01121"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#325b13e198ff56e9de2600ac7f28a57d">01121</a> <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd__intr_8c.html#325b13e198ff56e9de2600ac7f28a57d">ep0_do_stall</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd, <span class="keyword">const</span> <span class="keywordtype">int</span> err_val)
+<a name="l01122"></a>01122 {
+<a name="l01123"></a>01123         <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *<a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a> = &amp;pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a>;
+<a name="l01124"></a>01124         usb_device_request_t *ctrl = &amp;pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5ea5c519e678fbb382c2ea7d128562c1">setup_pkt</a>-&gt;<a class="code" href="structdwc__otg__pcd.html#af0345bc2c877d96863ef440c923204c">req</a>;
+<a name="l01125"></a>01125         DWC_WARN(<span class="stringliteral">"req %02x.%02x protocol STALL; err %d\n"</span>,
+<a name="l01126"></a>01126                  ctrl-&gt;bmRequestType, ctrl-&gt;bRequest, err_val);
+<a name="l01127"></a>01127 
+<a name="l01128"></a>01128         <a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#b882b6b7c857100ed20600e94ea37760">is_in</a> = 1;
+<a name="l01129"></a>01129         <a class="code" href="dwc__otg__cil_8c.html#5edca13178261136209ed51360c850b4">dwc_otg_ep_set_stall</a>(<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd), &amp;<a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>);
+<a name="l01130"></a>01130         pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a>.<a class="code" href="structdwc__otg__pcd__ep.html#cce0e089118d8bf7c6278c21ded70d5a">stopped</a> = 1;
+<a name="l01131"></a>01131         pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#8f6963b3fb9ab83048c4c0697c90382a">ep0state</a> = EP0_IDLE;
+<a name="l01132"></a>01132         <a class="code" href="dwc__otg__pcd__intr_8c.html#726b57833bb3ae4648ce7e7a7e125bf7">ep0_out_start</a>(<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd), pcd);
+<a name="l01133"></a>01133 }
+<a name="l01134"></a>01134 
+<a name="l01138"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#6c417c7d86bc9540e13ca4faeaf3dfbf">01138</a> <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd__intr_8c.html#6c417c7d86bc9540e13ca4faeaf3dfbf">do_gadget_setup</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd,
+<a name="l01139"></a>01139                                    usb_device_request_t * ctrl)
+<a name="l01140"></a>01140 {
+<a name="l01141"></a>01141         <span class="keywordtype">int</span> ret = 0;
+<a name="l01142"></a>01142         DWC_SPINUNLOCK(pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5d450e4d06659ab2f3b18e5c816776e4">lock</a>);
+<a name="l01143"></a>01143         ret = pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#b7001dde5db2706707a860da0030d9e6">fops</a>-&gt;<a class="code" href="structdwc__otg__pcd__function__ops.html#e99e932440749d9464e008cef78e808d">setup</a>(pcd, (uint8_t *) ctrl);
+<a name="l01144"></a>01144         DWC_SPINLOCK(pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5d450e4d06659ab2f3b18e5c816776e4">lock</a>);
+<a name="l01145"></a>01145         <span class="keywordflow">if</span> (ret &lt; 0) {
+<a name="l01146"></a>01146                 <a class="code" href="dwc__otg__pcd__intr_8c.html#325b13e198ff56e9de2600ac7f28a57d">ep0_do_stall</a>(pcd, ret);
+<a name="l01147"></a>01147         }
+<a name="l01148"></a>01148 
+<a name="l01161"></a>01161         <span class="keywordflow">if</span> (ret == 256 + 999) {
+<a name="l01162"></a>01162                 pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#cbe5c4062e140ee88f51ee916c0db0ad">request_config</a> = 1;
+<a name="l01163"></a>01163         }
+<a name="l01164"></a>01164 }
+<a name="l01165"></a>01165 
+<a name="l01166"></a>01166 <span class="preprocessor">#ifdef DWC_UTE_CFI</span>
+<a name="l01167"></a>01167 <span class="preprocessor"></span>
+<a name="l01171"></a>01171 <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">int</span> cfi_gadget_setup(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd,
+<a name="l01172"></a>01172                                    <span class="keyword">struct</span> <a class="code" href="structcfi__usb__ctrlrequest.html">cfi_usb_ctrlrequest</a> *ctrl_req)
+<a name="l01173"></a>01173 {
+<a name="l01174"></a>01174         <span class="keywordtype">int</span> ret = 0;
+<a name="l01175"></a>01175 
+<a name="l01176"></a>01176         <span class="keywordflow">if</span> (pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#b7001dde5db2706707a860da0030d9e6">fops</a> &amp;&amp; pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#b7001dde5db2706707a860da0030d9e6">fops</a>-&gt;<a class="code" href="structdwc__otg__pcd__function__ops.html#e717e78fcf05e0de9c6d478fee1afa87">cfi_setup</a>) {
+<a name="l01177"></a>01177                 DWC_SPINUNLOCK(pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5d450e4d06659ab2f3b18e5c816776e4">lock</a>);
+<a name="l01178"></a>01178                 ret = pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#b7001dde5db2706707a860da0030d9e6">fops</a>-&gt;<a class="code" href="structdwc__otg__pcd__function__ops.html#e717e78fcf05e0de9c6d478fee1afa87">cfi_setup</a>(pcd, ctrl_req);
+<a name="l01179"></a>01179                 DWC_SPINLOCK(pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5d450e4d06659ab2f3b18e5c816776e4">lock</a>);
+<a name="l01180"></a>01180                 <span class="keywordflow">if</span> (ret &lt; 0) {
+<a name="l01181"></a>01181                         <a class="code" href="dwc__otg__pcd__intr_8c.html#325b13e198ff56e9de2600ac7f28a57d">ep0_do_stall</a>(pcd, ret);
+<a name="l01182"></a>01182                         <span class="keywordflow">return</span> ret;
+<a name="l01183"></a>01183                 }
+<a name="l01184"></a>01184         }
+<a name="l01185"></a>01185 
+<a name="l01186"></a>01186         <span class="keywordflow">return</span> ret;
+<a name="l01187"></a>01187 }
+<a name="l01188"></a>01188 <span class="preprocessor">#endif</span>
+<a name="l01189"></a>01189 <span class="preprocessor"></span>
+<a name="l01194"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#39d3face14e49b0f1ad5c978f87665fe">01194</a> <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd__intr_8c.html#39d3face14e49b0f1ad5c978f87665fe">do_setup_in_status_phase</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd)
+<a name="l01195"></a>01195 {
+<a name="l01196"></a>01196         <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *<a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a> = &amp;pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a>;
+<a name="l01197"></a>01197         <span class="keywordflow">if</span> (pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#8f6963b3fb9ab83048c4c0697c90382a">ep0state</a> == EP0_STALL) {
+<a name="l01198"></a>01198                 <span class="keywordflow">return</span>;
+<a name="l01199"></a>01199         }
+<a name="l01200"></a>01200 
+<a name="l01201"></a>01201         pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#8f6963b3fb9ab83048c4c0697c90382a">ep0state</a> = EP0_IN_STATUS_PHASE;
+<a name="l01202"></a>01202 
+<a name="l01203"></a>01203         <span class="comment">/* Prepare for more SETUP Packets */</span>
+<a name="l01204"></a>01204         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"EP0 IN ZLP\n"</span>);
+<a name="l01205"></a>01205         <a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">xfer_len</a> = 0;
+<a name="l01206"></a>01206         <a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#23d4871510b5bcb54fbf0674d8f122bd">xfer_count</a> = 0;
+<a name="l01207"></a>01207         <a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#b882b6b7c857100ed20600e94ea37760">is_in</a> = 1;
+<a name="l01208"></a>01208         <a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#b40ce70422b6d105a855a8df4b33d45d">dma_addr</a> = pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#606d94ec61cca4c21e4dc9cb2e3b7064">setup_pkt_dma_handle</a>;
+<a name="l01209"></a>01209         <a class="code" href="dwc__otg__cil_8c.html#ee4989b24826b2a6592535282853e556">dwc_otg_ep0_start_transfer</a>(<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd), &amp;<a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>);
+<a name="l01210"></a>01210 
+<a name="l01211"></a>01211         <span class="comment">/* Prepare for more SETUP Packets */</span>
+<a name="l01212"></a>01212         <span class="comment">//ep0_out_start(GET_CORE_IF(pcd), pcd);</span>
+<a name="l01213"></a>01213 }
+<a name="l01214"></a>01214 
+<a name="l01219"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#cce0022b7577cda90a2d2e78e1f8171b">01219</a> <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd__intr_8c.html#cce0022b7577cda90a2d2e78e1f8171b">do_setup_out_status_phase</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd)
+<a name="l01220"></a>01220 {
+<a name="l01221"></a>01221         <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *<a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a> = &amp;pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a>;
+<a name="l01222"></a>01222         <span class="keywordflow">if</span> (pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#8f6963b3fb9ab83048c4c0697c90382a">ep0state</a> == EP0_STALL) {
+<a name="l01223"></a>01223                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"EP0 STALLED\n"</span>);
+<a name="l01224"></a>01224                 <span class="keywordflow">return</span>;
+<a name="l01225"></a>01225         }
+<a name="l01226"></a>01226         pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#8f6963b3fb9ab83048c4c0697c90382a">ep0state</a> = EP0_OUT_STATUS_PHASE;
+<a name="l01227"></a>01227 
+<a name="l01228"></a>01228         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"EP0 OUT ZLP\n"</span>);
+<a name="l01229"></a>01229         <a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">xfer_len</a> = 0;
+<a name="l01230"></a>01230         <a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#23d4871510b5bcb54fbf0674d8f122bd">xfer_count</a> = 0;
+<a name="l01231"></a>01231         <a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#b882b6b7c857100ed20600e94ea37760">is_in</a> = 0;
+<a name="l01232"></a>01232         <a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#b40ce70422b6d105a855a8df4b33d45d">dma_addr</a> = pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#606d94ec61cca4c21e4dc9cb2e3b7064">setup_pkt_dma_handle</a>;
+<a name="l01233"></a>01233         <a class="code" href="dwc__otg__cil_8c.html#ee4989b24826b2a6592535282853e556">dwc_otg_ep0_start_transfer</a>(<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd), &amp;<a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>);
+<a name="l01234"></a>01234 
+<a name="l01235"></a>01235         <span class="comment">/* Prepare for more SETUP Packets */</span>
+<a name="l01236"></a>01236         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;dma_enable == 0) {
+<a name="l01237"></a>01237                 <a class="code" href="dwc__otg__pcd__intr_8c.html#726b57833bb3ae4648ce7e7a7e125bf7">ep0_out_start</a>(<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd), pcd);
+<a name="l01238"></a>01238         }
+<a name="l01239"></a>01239 }
+<a name="l01240"></a>01240 
+<a name="l01245"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#153d9a3b2162ef091dc24027379af19f">01245</a> <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd__intr_8c.html#153d9a3b2162ef091dc24027379af19f">pcd_clear_halt</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd, <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> * ep)
+<a name="l01246"></a>01246 {
+<a name="l01247"></a>01247         <span class="keywordflow">if</span> (ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#0d30d306e370810fc819f6ef735c7e67">stall_clear_flag</a> == 0)
+<a name="l01248"></a>01248                 <a class="code" href="dwc__otg__cil_8c.html#a5f77318fb1c589406927a606844007f">dwc_otg_ep_clear_stall</a>(<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd), &amp;ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>);
+<a name="l01249"></a>01249 
+<a name="l01250"></a>01250         <span class="comment">/* Reactive the EP */</span>
+<a name="l01251"></a>01251         <a class="code" href="dwc__otg__cil_8c.html#5e5a1fb1ff70d5c42d8cf4a1c5d12b7f">dwc_otg_ep_activate</a>(<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd), &amp;ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>);
+<a name="l01252"></a>01252         <span class="keywordflow">if</span> (ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#cce0e089118d8bf7c6278c21ded70d5a">stopped</a>) {
+<a name="l01253"></a>01253                 ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#cce0e089118d8bf7c6278c21ded70d5a">stopped</a> = 0;
+<a name="l01254"></a>01254                 <span class="comment">/* If there is a request in the EP queue start it */</span>
+<a name="l01255"></a>01255 
+<a name="l01259"></a>01259                 <span class="comment">/*</span>
+<a name="l01260"></a>01260 <span class="comment">                 * Above fixme is solved by implmenting a tasklet to call the</span>
+<a name="l01261"></a>01261 <span class="comment">                 * start_next_request(), outside of interrupt context at some</span>
+<a name="l01262"></a>01262 <span class="comment">                 * time after the current time, after a clear-halt setup packet.</span>
+<a name="l01263"></a>01263 <span class="comment">                 * Still need to implement ep mismatch in the future if a gadget</span>
+<a name="l01264"></a>01264 <span class="comment">                 * ever uses more than one endpoint at once</span>
+<a name="l01265"></a>01265 <span class="comment">                 */</span>
+<a name="l01266"></a>01266                 ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#bbec681b68f2f745d1cfecfedd4e64be">queue_sof</a> = 1;
+<a name="l01267"></a>01267                 DWC_TASK_SCHEDULE(pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#9b45cd00cd5835aba4236529a04b28f1">start_xfer_tasklet</a>);
+<a name="l01268"></a>01268         }
+<a name="l01269"></a>01269         <span class="comment">/* Start Control Status Phase */</span>
+<a name="l01270"></a>01270         <a class="code" href="dwc__otg__pcd__intr_8c.html#39d3face14e49b0f1ad5c978f87665fe">do_setup_in_status_phase</a>(pcd);
+<a name="l01271"></a>01271 }
+<a name="l01272"></a>01272 
+<a name="l01284"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#9d6d6e24faab6478aef9e2217c9b5ab9">01284</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd_8h.html#9d6d6e24faab6478aef9e2217c9b5ab9">do_test_mode</a>(<span class="keywordtype">void</span> *data)
+<a name="l01285"></a>01285 {
+<a name="l01286"></a>01286         <a class="code" href="uniondctl__data.html">dctl_data_t</a> dctl;
+<a name="l01287"></a>01287         <a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd = (<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *) data;
+<a name="l01288"></a>01288         <a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *<a class="code" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">core_if</a> = <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd);
+<a name="l01289"></a>01289         <span class="keywordtype">int</span> <a class="code" href="structdwc__otg__pcd.html#577c57ee60c2ef42dce7791c85d50394">test_mode</a> = pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#577c57ee60c2ef42dce7791c85d50394">test_mode</a>;
+<a name="l01290"></a>01290 
+<a name="l01291"></a>01291 <span class="comment">//        DWC_WARN("%s() has not been tested since being rewritten!\n", __func__);</span>
+<a name="l01292"></a>01292 
+<a name="l01293"></a>01293         dctl.<a class="code" href="uniondctl__data.html#f49aadfd7ad95b570115b3c245b1729e">d32</a> = dwc_read_reg32(&amp;<a class="code" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#3779c2fc508920a831a59e696a8fa785">dctl</a>);
+<a name="l01294"></a>01294         <span class="keywordflow">switch</span> (test_mode) {
+<a name="l01295"></a>01295         <span class="keywordflow">case</span> 1:         <span class="comment">// TEST_J</span>
+<a name="l01296"></a>01296                 dctl.<a class="code" href="uniondctl__data.html#a3abfa6d609d9864f1f65712b409d4d3">b</a>.<a class="code" href="uniondctl__data.html#ef7a2687eef3086056f30b13f3588f9e">tstctl</a> = 1;
+<a name="l01297"></a>01297                 <span class="keywordflow">break</span>;
+<a name="l01298"></a>01298 
+<a name="l01299"></a>01299         <span class="keywordflow">case</span> 2:         <span class="comment">// TEST_K</span>
+<a name="l01300"></a>01300                 dctl.<a class="code" href="uniondctl__data.html#a3abfa6d609d9864f1f65712b409d4d3">b</a>.<a class="code" href="uniondctl__data.html#ef7a2687eef3086056f30b13f3588f9e">tstctl</a> = 2;
+<a name="l01301"></a>01301                 <span class="keywordflow">break</span>;
+<a name="l01302"></a>01302 
+<a name="l01303"></a>01303         <span class="keywordflow">case</span> 3:         <span class="comment">// TEST_SE0_NAK</span>
+<a name="l01304"></a>01304                 dctl.<a class="code" href="uniondctl__data.html#a3abfa6d609d9864f1f65712b409d4d3">b</a>.<a class="code" href="uniondctl__data.html#ef7a2687eef3086056f30b13f3588f9e">tstctl</a> = 3;
+<a name="l01305"></a>01305                 <span class="keywordflow">break</span>;
+<a name="l01306"></a>01306 
+<a name="l01307"></a>01307         <span class="keywordflow">case</span> 4:         <span class="comment">// TEST_PACKET</span>
+<a name="l01308"></a>01308                 dctl.<a class="code" href="uniondctl__data.html#a3abfa6d609d9864f1f65712b409d4d3">b</a>.<a class="code" href="uniondctl__data.html#ef7a2687eef3086056f30b13f3588f9e">tstctl</a> = 4;
+<a name="l01309"></a>01309                 <span class="keywordflow">break</span>;
+<a name="l01310"></a>01310 
+<a name="l01311"></a>01311         <span class="keywordflow">case</span> 5:         <span class="comment">// TEST_FORCE_ENABLE</span>
+<a name="l01312"></a>01312                 dctl.<a class="code" href="uniondctl__data.html#a3abfa6d609d9864f1f65712b409d4d3">b</a>.<a class="code" href="uniondctl__data.html#ef7a2687eef3086056f30b13f3588f9e">tstctl</a> = 5;
+<a name="l01313"></a>01313                 <span class="keywordflow">break</span>;
+<a name="l01314"></a>01314         }
+<a name="l01315"></a>01315         dwc_write_reg32(&amp;<a class="code" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#3779c2fc508920a831a59e696a8fa785">dctl</a>, dctl.<a class="code" href="uniondctl__data.html#f49aadfd7ad95b570115b3c245b1729e">d32</a>);
+<a name="l01316"></a>01316 }
+<a name="l01317"></a>01317 
+<a name="l01321"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#f449add2b4e8de7ced10fd1bb4c5b748">01321</a> <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd__intr_8c.html#f449add2b4e8de7ced10fd1bb4c5b748">do_get_status</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd)
+<a name="l01322"></a>01322 {
+<a name="l01323"></a>01323         usb_device_request_t ctrl = pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5ea5c519e678fbb382c2ea7d128562c1">setup_pkt</a>-&gt;<a class="code" href="structdwc__otg__pcd.html#af0345bc2c877d96863ef440c923204c">req</a>;
+<a name="l01324"></a>01324         <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *ep;
+<a name="l01325"></a>01325         <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *<a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a> = &amp;pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a>;
+<a name="l01326"></a>01326         uint16_t *status = pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#ca247241f78970f27e5c964fc04d47c8">status_buf</a>;
+<a name="l01327"></a>01327 
+<a name="l01328"></a>01328 <span class="preprocessor">#ifdef DEBUG_EP0</span>
+<a name="l01329"></a>01329 <span class="preprocessor"></span>        <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>,
+<a name="l01330"></a>01330                     <span class="stringliteral">"GET_STATUS %02x.%02x v%04x i%04x l%04x\n"</span>,
+<a name="l01331"></a>01331                     ctrl.bmRequestType, ctrl.bRequest,
+<a name="l01332"></a>01332                     UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
+<a name="l01333"></a>01333                     UGETW(ctrl.wLength));
+<a name="l01334"></a>01334 <span class="preprocessor">#endif</span>
+<a name="l01335"></a>01335 <span class="preprocessor"></span>
+<a name="l01336"></a>01336         <span class="keywordflow">switch</span> (UT_GET_RECIPIENT(ctrl.bmRequestType)) {
+<a name="l01337"></a>01337         <span class="keywordflow">case</span> UT_DEVICE:
+<a name="l01338"></a>01338                 *status = 0x1;  <span class="comment">/* Self powered */</span>
+<a name="l01339"></a>01339                 *status |= pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#9d8e6d7f0ad10d580d467024e258f6f5">remote_wakeup_enable</a> &lt;&lt; 1;
+<a name="l01340"></a>01340                 <span class="keywordflow">break</span>;
+<a name="l01341"></a>01341 
+<a name="l01342"></a>01342         <span class="keywordflow">case</span> UT_INTERFACE:
+<a name="l01343"></a>01343                 *status = 0;
+<a name="l01344"></a>01344                 <span class="keywordflow">break</span>;
+<a name="l01345"></a>01345 
+<a name="l01346"></a>01346         <span class="keywordflow">case</span> UT_ENDPOINT:
+<a name="l01347"></a>01347                 ep = <a class="code" href="dwc__otg__pcd__intr_8c.html#3c351d7f51d6242296d6ea3bb1a9775c">get_ep_by_addr</a>(pcd, UGETW(ctrl.wIndex));
+<a name="l01348"></a>01348                 <span class="keywordflow">if</span> (ep == 0 || UGETW(ctrl.wLength) &gt; 2) {
+<a name="l01349"></a>01349                         <a class="code" href="dwc__otg__pcd__intr_8c.html#325b13e198ff56e9de2600ac7f28a57d">ep0_do_stall</a>(pcd, -DWC_E_NOT_SUPPORTED);
+<a name="l01350"></a>01350                         <span class="keywordflow">return</span>;
+<a name="l01351"></a>01351                 }
+<a name="l01353"></a>01353                 *status = ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#cce0e089118d8bf7c6278c21ded70d5a">stopped</a>;
+<a name="l01354"></a>01354                 <span class="keywordflow">break</span>;
+<a name="l01355"></a>01355         }
+<a name="l01356"></a>01356         pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#2c8be11c3b9c7cd02684348eb028aeb5">ep0_pending</a> = 1;
+<a name="l01357"></a>01357         <a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#d0cda8ded2e5142d9a1c9c17efc5812f">start_xfer_buff</a> = (uint8_t *) status;
+<a name="l01358"></a>01358         <a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#97fa9bf5c31ba734d54f70e6fe6ae8eb">xfer_buff</a> = (uint8_t *) status;
+<a name="l01359"></a>01359         <a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#b40ce70422b6d105a855a8df4b33d45d">dma_addr</a> = pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#c3880dd4ce15c515ba37b90b6e7fd293">status_buf_dma_handle</a>;
+<a name="l01360"></a>01360         <a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">xfer_len</a> = 2;
+<a name="l01361"></a>01361         <a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#23d4871510b5bcb54fbf0674d8f122bd">xfer_count</a> = 0;
+<a name="l01362"></a>01362         <a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#5a218f200cff0491b735f43fed5176bf">total_len</a> = <a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">xfer_len</a>;
+<a name="l01363"></a>01363         <a class="code" href="dwc__otg__cil_8c.html#ee4989b24826b2a6592535282853e556">dwc_otg_ep0_start_transfer</a>(<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd), &amp;<a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>);
+<a name="l01364"></a>01364 }
+<a name="l01365"></a>01365 
+<a name="l01369"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#3754b29956ab3a85851dea376e046db9">01369</a> <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd__intr_8c.html#3754b29956ab3a85851dea376e046db9">do_set_feature</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd)
+<a name="l01370"></a>01370 {
+<a name="l01371"></a>01371         <a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *<a class="code" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">core_if</a> = <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd);
+<a name="l01372"></a>01372         <a class="code" href="structdwc__otg__core__global__regs.html">dwc_otg_core_global_regs_t</a> *global_regs = <a class="code" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>;
+<a name="l01373"></a>01373         usb_device_request_t ctrl = pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5ea5c519e678fbb382c2ea7d128562c1">setup_pkt</a>-&gt;<a class="code" href="structdwc__otg__pcd.html#af0345bc2c877d96863ef440c923204c">req</a>;
+<a name="l01374"></a>01374         <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *ep = 0;
+<a name="l01375"></a>01375         int32_t otg_cap_param = <a class="code" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a>-&gt;<a class="code" href="structdwc__otg__core__params.html#b6960c28e9c7d82dca37645726c8f7ce">otg_cap</a>;
+<a name="l01376"></a>01376         <a class="code" href="uniongotgctl__data.html">gotgctl_data_t</a> gotgctl = {.d32 = 0 };
+<a name="l01377"></a>01377 
+<a name="l01378"></a>01378         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"SET_FEATURE:%02x.%02x v%04x i%04x l%04x\n"</span>,
+<a name="l01379"></a>01379                     ctrl.bmRequestType, ctrl.bRequest,
+<a name="l01380"></a>01380                     UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
+<a name="l01381"></a>01381                     UGETW(ctrl.wLength));
+<a name="l01382"></a>01382         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"otg_cap=%d\n"</span>, otg_cap_param);
+<a name="l01383"></a>01383 
+<a name="l01384"></a>01384         <span class="keywordflow">switch</span> (UT_GET_RECIPIENT(ctrl.bmRequestType)) {
+<a name="l01385"></a>01385         <span class="keywordflow">case</span> UT_DEVICE:
+<a name="l01386"></a>01386                 <span class="keywordflow">switch</span> (UGETW(ctrl.wValue)) {
+<a name="l01387"></a>01387                 <span class="keywordflow">case</span> UF_DEVICE_REMOTE_WAKEUP:
+<a name="l01388"></a>01388                         pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#9d8e6d7f0ad10d580d467024e258f6f5">remote_wakeup_enable</a> = 1;
+<a name="l01389"></a>01389                         <span class="keywordflow">break</span>;
+<a name="l01390"></a>01390 
+<a name="l01391"></a>01391                 <span class="keywordflow">case</span> UF_TEST_MODE:
+<a name="l01392"></a>01392                         <span class="comment">/* Setup the Test Mode tasklet to do the Test</span>
+<a name="l01393"></a>01393 <span class="comment">                         * Packet generation after the SETUP Status</span>
+<a name="l01394"></a>01394 <span class="comment">                         * phase has completed. */</span>
+<a name="l01395"></a>01395 
+<a name="l01399"></a>01399                         pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#577c57ee60c2ef42dce7791c85d50394">test_mode</a> = UGETW(ctrl.wIndex) &gt;&gt; 8;
+<a name="l01400"></a>01400                         DWC_TASK_SCHEDULE(pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#d1aed2eb03a93032a1ce80e3145bb81e">test_mode_tasklet</a>);
+<a name="l01401"></a>01401                         <span class="keywordflow">break</span>;
+<a name="l01402"></a>01402 
+<a name="l01403"></a>01403                 <span class="keywordflow">case</span> UF_DEVICE_B_HNP_ENABLE:
+<a name="l01404"></a>01404                         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>,
+<a name="l01405"></a>01405                                     <span class="stringliteral">"SET_FEATURE: USB_DEVICE_B_HNP_ENABLE\n"</span>);
+<a name="l01406"></a>01406 
+<a name="l01407"></a>01407                         <span class="comment">/* dev may initiate HNP */</span>
+<a name="l01408"></a>01408                         <span class="keywordflow">if</span> (otg_cap_param == <a class="code" href="dwc__otg__core__if_8h.html#83c71a480363001711ff07e03834c49f">DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE</a>) {
+<a name="l01409"></a>01409                                 pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#e09fc5322ac0d7deec2772984c10ae90">b_hnp_enable</a> = 1;
+<a name="l01410"></a>01410                                 <a class="code" href="dwc__otg__pcd__intr_8c.html#81a9361b81863cef6b2566ea44529185">dwc_otg_pcd_update_otg</a>(pcd, 0);
+<a name="l01411"></a>01411                                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"Request B HNP\n"</span>);
+<a name="l01414"></a>01414                                 gotgctl.<a class="code" href="uniongotgctl__data.html#212c81366266e906a188f4dbfadb6dd3">b</a>.<a class="code" href="uniongotgctl__data.html#0058cbee8b53336c28746116301ea796">devhnpen</a> = 1;
+<a name="l01415"></a>01415                                 gotgctl.<a class="code" href="uniongotgctl__data.html#212c81366266e906a188f4dbfadb6dd3">b</a>.<a class="code" href="uniongotgctl__data.html#08487ecb0860252b73815ee6e0f8eaa3">hnpreq</a> = 1;
+<a name="l01416"></a>01416                                 dwc_write_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#54034d00bb6b47ada4e0c0baa87cbd8a">gotgctl</a>,
+<a name="l01417"></a>01417                                                 gotgctl.<a class="code" href="uniongotgctl__data.html#ebb591ab40ff41f0e06f03a795647d33">d32</a>);
+<a name="l01418"></a>01418                         } <span class="keywordflow">else</span> {
+<a name="l01419"></a>01419                                 <a class="code" href="dwc__otg__pcd__intr_8c.html#325b13e198ff56e9de2600ac7f28a57d">ep0_do_stall</a>(pcd, -DWC_E_NOT_SUPPORTED);
+<a name="l01420"></a>01420                         }
+<a name="l01421"></a>01421                         <span class="keywordflow">break</span>;
+<a name="l01422"></a>01422 
+<a name="l01423"></a>01423                 <span class="keywordflow">case</span> UF_DEVICE_A_HNP_SUPPORT:
+<a name="l01424"></a>01424                         <span class="comment">/* RH port supports HNP */</span>
+<a name="l01425"></a>01425                         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>,
+<a name="l01426"></a>01426                                     <span class="stringliteral">"SET_FEATURE: USB_DEVICE_A_HNP_SUPPORT\n"</span>);
+<a name="l01427"></a>01427                         <span class="keywordflow">if</span> (otg_cap_param == <a class="code" href="dwc__otg__core__if_8h.html#83c71a480363001711ff07e03834c49f">DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE</a>) {
+<a name="l01428"></a>01428                                 pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#e8008719644bdc23040f1a1545b7117f">a_hnp_support</a> = 1;
+<a name="l01429"></a>01429                                 <a class="code" href="dwc__otg__pcd__intr_8c.html#81a9361b81863cef6b2566ea44529185">dwc_otg_pcd_update_otg</a>(pcd, 0);
+<a name="l01430"></a>01430                         } <span class="keywordflow">else</span> {
+<a name="l01431"></a>01431                                 <a class="code" href="dwc__otg__pcd__intr_8c.html#325b13e198ff56e9de2600ac7f28a57d">ep0_do_stall</a>(pcd, -DWC_E_NOT_SUPPORTED);
+<a name="l01432"></a>01432                         }
+<a name="l01433"></a>01433                         <span class="keywordflow">break</span>;
+<a name="l01434"></a>01434 
+<a name="l01435"></a>01435                 <span class="keywordflow">case</span> UF_DEVICE_A_ALT_HNP_SUPPORT:
+<a name="l01436"></a>01436                         <span class="comment">/* other RH port does */</span>
+<a name="l01437"></a>01437                         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>,
+<a name="l01438"></a>01438                                     <span class="stringliteral">"SET_FEATURE: USB_DEVICE_A_ALT_HNP_SUPPORT\n"</span>);
+<a name="l01439"></a>01439                         <span class="keywordflow">if</span> (otg_cap_param == <a class="code" href="dwc__otg__core__if_8h.html#83c71a480363001711ff07e03834c49f">DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE</a>) {
+<a name="l01440"></a>01440                                 pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#49f2d2b04a4c07a8d53643f7681b5405">a_alt_hnp_support</a> = 1;
+<a name="l01441"></a>01441                                 <a class="code" href="dwc__otg__pcd__intr_8c.html#81a9361b81863cef6b2566ea44529185">dwc_otg_pcd_update_otg</a>(pcd, 0);
+<a name="l01442"></a>01442                         } <span class="keywordflow">else</span> {
+<a name="l01443"></a>01443                                 <a class="code" href="dwc__otg__pcd__intr_8c.html#325b13e198ff56e9de2600ac7f28a57d">ep0_do_stall</a>(pcd, -DWC_E_NOT_SUPPORTED);
+<a name="l01444"></a>01444                         }
+<a name="l01445"></a>01445                         <span class="keywordflow">break</span>;
+<a name="l01446"></a>01446                 }
+<a name="l01447"></a>01447                 <a class="code" href="dwc__otg__pcd__intr_8c.html#39d3face14e49b0f1ad5c978f87665fe">do_setup_in_status_phase</a>(pcd);
+<a name="l01448"></a>01448                 <span class="keywordflow">break</span>;
+<a name="l01449"></a>01449 
+<a name="l01450"></a>01450         <span class="keywordflow">case</span> UT_INTERFACE:
+<a name="l01451"></a>01451                 <a class="code" href="dwc__otg__pcd__intr_8c.html#6c417c7d86bc9540e13ca4faeaf3dfbf">do_gadget_setup</a>(pcd, &amp;ctrl);
+<a name="l01452"></a>01452                 <span class="keywordflow">break</span>;
+<a name="l01453"></a>01453 
+<a name="l01454"></a>01454         <span class="keywordflow">case</span> UT_ENDPOINT:
+<a name="l01455"></a>01455                 <span class="keywordflow">if</span> (UGETW(ctrl.wValue) == UF_ENDPOINT_HALT) {
+<a name="l01456"></a>01456                         ep = <a class="code" href="dwc__otg__pcd__intr_8c.html#3c351d7f51d6242296d6ea3bb1a9775c">get_ep_by_addr</a>(pcd, UGETW(ctrl.wIndex));
+<a name="l01457"></a>01457                         <span class="keywordflow">if</span> (ep == 0) {
+<a name="l01458"></a>01458                                 <a class="code" href="dwc__otg__pcd__intr_8c.html#325b13e198ff56e9de2600ac7f28a57d">ep0_do_stall</a>(pcd, -DWC_E_NOT_SUPPORTED);
+<a name="l01459"></a>01459                                 <span class="keywordflow">return</span>;
+<a name="l01460"></a>01460                         }
+<a name="l01461"></a>01461                         ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#cce0e089118d8bf7c6278c21ded70d5a">stopped</a> = 1;
+<a name="l01462"></a>01462                         <a class="code" href="dwc__otg__cil_8c.html#5edca13178261136209ed51360c850b4">dwc_otg_ep_set_stall</a>(<a class="code" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">core_if</a>, &amp;ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>);
+<a name="l01463"></a>01463                 }
+<a name="l01464"></a>01464                 <a class="code" href="dwc__otg__pcd__intr_8c.html#39d3face14e49b0f1ad5c978f87665fe">do_setup_in_status_phase</a>(pcd);
+<a name="l01465"></a>01465                 <span class="keywordflow">break</span>;
+<a name="l01466"></a>01466         }
+<a name="l01467"></a>01467 }
+<a name="l01468"></a>01468 
+<a name="l01472"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#2198ea3f0136465fa325a189d4ba5140">01472</a> <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd__intr_8c.html#2198ea3f0136465fa325a189d4ba5140">do_clear_feature</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd)
+<a name="l01473"></a>01473 {
+<a name="l01474"></a>01474         usb_device_request_t ctrl = pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5ea5c519e678fbb382c2ea7d128562c1">setup_pkt</a>-&gt;<a class="code" href="structdwc__otg__pcd.html#af0345bc2c877d96863ef440c923204c">req</a>;
+<a name="l01475"></a>01475         <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *ep = 0;
+<a name="l01476"></a>01476 
+<a name="l01477"></a>01477         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>,
+<a name="l01478"></a>01478                     <span class="stringliteral">"CLEAR_FEATURE:%02x.%02x v%04x i%04x l%04x\n"</span>,
+<a name="l01479"></a>01479                     ctrl.bmRequestType, ctrl.bRequest,
+<a name="l01480"></a>01480                     UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
+<a name="l01481"></a>01481                     UGETW(ctrl.wLength));
+<a name="l01482"></a>01482 
+<a name="l01483"></a>01483         <span class="keywordflow">switch</span> (UT_GET_RECIPIENT(ctrl.bmRequestType)) {
+<a name="l01484"></a>01484         <span class="keywordflow">case</span> UT_DEVICE:
+<a name="l01485"></a>01485                 <span class="keywordflow">switch</span> (UGETW(ctrl.wValue)) {
+<a name="l01486"></a>01486                 <span class="keywordflow">case</span> UF_DEVICE_REMOTE_WAKEUP:
+<a name="l01487"></a>01487                         pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#9d8e6d7f0ad10d580d467024e258f6f5">remote_wakeup_enable</a> = 0;
+<a name="l01488"></a>01488                         <span class="keywordflow">break</span>;
+<a name="l01489"></a>01489 
+<a name="l01490"></a>01490                 <span class="keywordflow">case</span> UF_TEST_MODE:
+<a name="l01492"></a>01492                         <span class="keywordflow">break</span>;
+<a name="l01493"></a>01493                 }
+<a name="l01494"></a>01494                 <a class="code" href="dwc__otg__pcd__intr_8c.html#39d3face14e49b0f1ad5c978f87665fe">do_setup_in_status_phase</a>(pcd);
+<a name="l01495"></a>01495                 <span class="keywordflow">break</span>;
+<a name="l01496"></a>01496 
+<a name="l01497"></a>01497         <span class="keywordflow">case</span> UT_ENDPOINT:
+<a name="l01498"></a>01498                 ep = <a class="code" href="dwc__otg__pcd__intr_8c.html#3c351d7f51d6242296d6ea3bb1a9775c">get_ep_by_addr</a>(pcd, UGETW(ctrl.wIndex));
+<a name="l01499"></a>01499                 <span class="keywordflow">if</span> (ep == 0) {
+<a name="l01500"></a>01500                         <a class="code" href="dwc__otg__pcd__intr_8c.html#325b13e198ff56e9de2600ac7f28a57d">ep0_do_stall</a>(pcd, -DWC_E_NOT_SUPPORTED);
+<a name="l01501"></a>01501                         <span class="keywordflow">return</span>;
+<a name="l01502"></a>01502                 }
+<a name="l01503"></a>01503 
+<a name="l01504"></a>01504                 <a class="code" href="dwc__otg__pcd__intr_8c.html#153d9a3b2162ef091dc24027379af19f">pcd_clear_halt</a>(pcd, ep);
+<a name="l01505"></a>01505 
+<a name="l01506"></a>01506                 <span class="keywordflow">break</span>;
+<a name="l01507"></a>01507         }
+<a name="l01508"></a>01508 }
+<a name="l01509"></a>01509 
+<a name="l01513"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#f653efb69491b3e293cab4a33940ac3d">01513</a> <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd__intr_8c.html#f653efb69491b3e293cab4a33940ac3d">do_set_address</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd)
+<a name="l01514"></a>01514 {
+<a name="l01515"></a>01515         <a class="code" href="structdwc__otg__dev__if.html">dwc_otg_dev_if_t</a> *dev_if = <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;dev_if;
+<a name="l01516"></a>01516         usb_device_request_t ctrl = pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5ea5c519e678fbb382c2ea7d128562c1">setup_pkt</a>-&gt;<a class="code" href="structdwc__otg__pcd.html#af0345bc2c877d96863ef440c923204c">req</a>;
+<a name="l01517"></a>01517 
+<a name="l01518"></a>01518         <span class="keywordflow">if</span> (ctrl.bmRequestType == UT_DEVICE) {
+<a name="l01519"></a>01519                 <a class="code" href="uniondcfg__data.html">dcfg_data_t</a> dcfg = {.d32 = 0 };
+<a name="l01520"></a>01520 
+<a name="l01521"></a>01521 <span class="preprocessor">#ifdef DEBUG_EP0</span>
+<a name="l01522"></a>01522 <span class="preprocessor"></span><span class="comment">//                      DWC_DEBUGPL(DBG_PCDV, "SET_ADDRESS:%d\n", ctrl.wValue);</span>
+<a name="l01523"></a>01523 <span class="preprocessor">#endif</span>
+<a name="l01524"></a>01524 <span class="preprocessor"></span>                dcfg.<a class="code" href="uniondcfg__data.html#242c1b463f445de3fc265e8c20fde50b">b</a>.<a class="code" href="uniondcfg__data.html#71c70afb48dd124d12e43d86edd90f1e">devaddr</a> = UGETW(ctrl.wValue);
+<a name="l01525"></a>01525                 dwc_modify_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#c0c24937bbd7184884f05343f56ef1da">dcfg</a>, 0, dcfg.<a class="code" href="uniondcfg__data.html#efd84d3306db1b4370535a0e814612dc">d32</a>);
+<a name="l01526"></a>01526                 <a class="code" href="dwc__otg__pcd__intr_8c.html#39d3face14e49b0f1ad5c978f87665fe">do_setup_in_status_phase</a>(pcd);
+<a name="l01527"></a>01527         }
+<a name="l01528"></a>01528 }
+<a name="l01529"></a>01529 
+<a name="l01580"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#856a520a378e4f6f274253227080cfa1">01580</a> <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd__intr_8c.html#856a520a378e4f6f274253227080cfa1">pcd_setup</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd)
+<a name="l01581"></a>01581 {
+<a name="l01582"></a>01582         <a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *<a class="code" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">core_if</a> = <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd);
+<a name="l01583"></a>01583         <a class="code" href="structdwc__otg__dev__if.html">dwc_otg_dev_if_t</a> *dev_if = <a class="code" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">core_if</a>-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>;
+<a name="l01584"></a>01584         usb_device_request_t ctrl = pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5ea5c519e678fbb382c2ea7d128562c1">setup_pkt</a>-&gt;<a class="code" href="structdwc__otg__pcd.html#af0345bc2c877d96863ef440c923204c">req</a>;
+<a name="l01585"></a>01585         <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *<a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a> = &amp;pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a>;
+<a name="l01586"></a>01586 
+<a name="l01587"></a>01587         <a class="code" href="uniondeptsiz0__data.html">deptsiz0_data_t</a> doeptsize0 = {.d32 = 0 };
+<a name="l01588"></a>01588 
+<a name="l01589"></a>01589 <span class="preprocessor">#ifdef DWC_UTE_CFI</span>
+<a name="l01590"></a>01590 <span class="preprocessor"></span>        <span class="keywordtype">int</span> retval = 0;
+<a name="l01591"></a>01591         <span class="keyword">struct </span><a class="code" href="structcfi__usb__ctrlrequest.html">cfi_usb_ctrlrequest</a> cfi_req;
+<a name="l01592"></a>01592 <span class="preprocessor">#endif</span>
+<a name="l01593"></a>01593 <span class="preprocessor"></span>
+<a name="l01594"></a>01594 <span class="preprocessor">#ifdef DEBUG_EP0</span>
+<a name="l01595"></a>01595 <span class="preprocessor"></span>        <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"SETUP %02x.%02x v%04x i%04x l%04x\n"</span>,
+<a name="l01596"></a>01596                     ctrl.bmRequestType, ctrl.bRequest,
+<a name="l01597"></a>01597                     UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
+<a name="l01598"></a>01598                     UGETW(ctrl.wLength));
+<a name="l01599"></a>01599 <span class="preprocessor">#endif</span>
+<a name="l01600"></a>01600 <span class="preprocessor"></span>
+<a name="l01601"></a>01601         doeptsize0.<a class="code" href="uniondeptsiz0__data.html#a06fa9b1dcaee47fba9cf869027ed6f1">d32</a> = dwc_read_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">out_ep_regs</a>[0]-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#e756ec48787099f0a4e2ce353fce4f91">doeptsiz</a>);
+<a name="l01602"></a>01602 
+<a name="l01605"></a>01605         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a> &amp;&amp; core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a> == 0
+<a name="l01606"></a>01606             &amp;&amp; (doeptsize0.<a class="code" href="uniondeptsiz0__data.html#8e50594573fd774fc3e27404d8b1f59c">b</a>.<a class="code" href="uniondeptsiz0__data.html#60123707d51d7dfa22cd6b245402e49b">supcnt</a> &lt; 2)) {
+<a name="l01607"></a>01607                 DWC_ERROR
+<a name="l01608"></a>01608                     (<span class="stringliteral">"\n\n-----------    CANNOT handle &gt; 1 setup packet in DMA mode\n\n"</span>);
+<a name="l01609"></a>01609         }
+<a name="l01610"></a>01610 
+<a name="l01611"></a>01611         <span class="comment">/* Clean up the request queue */</span>
+<a name="l01612"></a>01612         <a class="code" href="dwc__otg__pcd_8c.html#e8ef6f3d831b89a753d93489827949d3">dwc_otg_request_nuke</a>(ep0);
+<a name="l01613"></a>01613         ep0-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#cce0e089118d8bf7c6278c21ded70d5a">stopped</a> = 0;
+<a name="l01614"></a>01614 
+<a name="l01615"></a>01615         <span class="keywordflow">if</span> (ctrl.bmRequestType &amp; UE_DIR_IN) {
+<a name="l01616"></a>01616                 ep0-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#b882b6b7c857100ed20600e94ea37760">is_in</a> = 1;
+<a name="l01617"></a>01617                 pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#8f6963b3fb9ab83048c4c0697c90382a">ep0state</a> = EP0_IN_DATA_PHASE;
+<a name="l01618"></a>01618         } <span class="keywordflow">else</span> {
+<a name="l01619"></a>01619                 ep0-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#b882b6b7c857100ed20600e94ea37760">is_in</a> = 0;
+<a name="l01620"></a>01620                 pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#8f6963b3fb9ab83048c4c0697c90382a">ep0state</a> = EP0_OUT_DATA_PHASE;
+<a name="l01621"></a>01621         }
+<a name="l01622"></a>01622 
+<a name="l01623"></a>01623         <span class="keywordflow">if</span> (UGETW(ctrl.wLength) == 0) {
+<a name="l01624"></a>01624                 ep0-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#b882b6b7c857100ed20600e94ea37760">is_in</a> = 1;
+<a name="l01625"></a>01625                 pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#8f6963b3fb9ab83048c4c0697c90382a">ep0state</a> = EP0_IN_STATUS_PHASE;
+<a name="l01626"></a>01626         }
+<a name="l01627"></a>01627 
+<a name="l01628"></a>01628         <span class="keywordflow">if</span> (UT_GET_TYPE(ctrl.bmRequestType) != UT_STANDARD) {
+<a name="l01629"></a>01629 
+<a name="l01630"></a>01630 <span class="preprocessor">#ifdef DWC_UTE_CFI</span>
+<a name="l01631"></a>01631 <span class="preprocessor"></span>                DWC_MEMCPY(&amp;cfi_req, &amp;ctrl, <span class="keyword">sizeof</span>(usb_device_request_t));
+<a name="l01632"></a>01632 
+<a name="l01633"></a>01633                 <span class="comment">//printk(KERN_ALERT "CFI: req_type=0x%02x; req=0x%02x\n", ctrl.bRequestType, ctrl.bRequest);</span>
+<a name="l01634"></a>01634                 <span class="keywordflow">if</span> (UT_GET_TYPE(cfi_req.bRequestType) == UT_VENDOR) {
+<a name="l01635"></a>01635                         <span class="keywordflow">if</span> (cfi_req.bRequest &gt; 0xB0 &amp;&amp; cfi_req.bRequest &lt; 0xBF) {
+<a name="l01636"></a>01636                                 retval = cfi_setup(pcd, &amp;cfi_req);
+<a name="l01637"></a>01637                                 <span class="keywordflow">if</span> (retval &lt; 0) {
+<a name="l01638"></a>01638                                         <a class="code" href="dwc__otg__pcd__intr_8c.html#325b13e198ff56e9de2600ac7f28a57d">ep0_do_stall</a>(pcd, retval);
+<a name="l01639"></a>01639                                         pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#2c8be11c3b9c7cd02684348eb028aeb5">ep0_pending</a> = 0;
+<a name="l01640"></a>01640                                         <span class="keywordflow">return</span>;
+<a name="l01641"></a>01641                                 }
+<a name="l01642"></a>01642 
+<a name="l01643"></a>01643                                 <span class="comment">/* if need gadget setup then call it and check the retval */</span>
+<a name="l01644"></a>01644                                 <span class="keywordflow">if</span> (pcd-&gt;cfi-&gt;need_gadget_att) {
+<a name="l01645"></a>01645                                         retval =
+<a name="l01646"></a>01646                                             cfi_gadget_setup(pcd,
+<a name="l01647"></a>01647                                                              &amp;pcd-&gt;cfi-&gt;
+<a name="l01648"></a>01648                                                              ctrl_req);
+<a name="l01649"></a>01649                                         <span class="keywordflow">if</span> (retval &lt; 0) {
+<a name="l01650"></a>01650                                                 pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#2c8be11c3b9c7cd02684348eb028aeb5">ep0_pending</a> = 0;
+<a name="l01651"></a>01651                                                 <span class="keywordflow">return</span>;
+<a name="l01652"></a>01652                                         }
+<a name="l01653"></a>01653                                 }
+<a name="l01654"></a>01654 
+<a name="l01655"></a>01655                                 <span class="keywordflow">if</span> (pcd-&gt;cfi-&gt;need_status_in_complete) {
+<a name="l01656"></a>01656                                         <a class="code" href="dwc__otg__pcd__intr_8c.html#39d3face14e49b0f1ad5c978f87665fe">do_setup_in_status_phase</a>(pcd);
+<a name="l01657"></a>01657                                 }
+<a name="l01658"></a>01658                                 <span class="keywordflow">return</span>;
+<a name="l01659"></a>01659                         }
+<a name="l01660"></a>01660                 }
+<a name="l01661"></a>01661 <span class="preprocessor">#endif</span>
+<a name="l01662"></a>01662 <span class="preprocessor"></span>
+<a name="l01663"></a>01663                 <span class="comment">/* handle non-standard (class/vendor) requests in the gadget driver */</span>
+<a name="l01664"></a>01664                 <a class="code" href="dwc__otg__pcd__intr_8c.html#6c417c7d86bc9540e13ca4faeaf3dfbf">do_gadget_setup</a>(pcd, &amp;ctrl);
+<a name="l01665"></a>01665                 <span class="keywordflow">return</span>;
+<a name="l01666"></a>01666         }
+<a name="l01667"></a>01667 
+<a name="l01670"></a>01670 
+<a name="l01671"></a>01671 
+<a name="l01672"></a>01672 
+<a name="l01673"></a>01673         <span class="keywordflow">switch</span> (ctrl.bRequest) {
+<a name="l01674"></a>01674         <span class="keywordflow">case</span> UR_GET_STATUS:
+<a name="l01675"></a>01675                 <a class="code" href="dwc__otg__pcd__intr_8c.html#f449add2b4e8de7ced10fd1bb4c5b748">do_get_status</a>(pcd);
+<a name="l01676"></a>01676                 <span class="keywordflow">break</span>;
+<a name="l01677"></a>01677 
+<a name="l01678"></a>01678         <span class="keywordflow">case</span> UR_CLEAR_FEATURE:
+<a name="l01679"></a>01679                 <a class="code" href="dwc__otg__pcd__intr_8c.html#2198ea3f0136465fa325a189d4ba5140">do_clear_feature</a>(pcd);
+<a name="l01680"></a>01680                 <span class="keywordflow">break</span>;
+<a name="l01681"></a>01681 
+<a name="l01682"></a>01682         <span class="keywordflow">case</span> UR_SET_FEATURE:
+<a name="l01683"></a>01683                 <a class="code" href="dwc__otg__pcd__intr_8c.html#3754b29956ab3a85851dea376e046db9">do_set_feature</a>(pcd);
+<a name="l01684"></a>01684                 <span class="keywordflow">break</span>;
+<a name="l01685"></a>01685 
+<a name="l01686"></a>01686         <span class="keywordflow">case</span> UR_SET_ADDRESS:
+<a name="l01687"></a>01687                 <a class="code" href="dwc__otg__pcd__intr_8c.html#f653efb69491b3e293cab4a33940ac3d">do_set_address</a>(pcd);
+<a name="l01688"></a>01688                 <span class="keywordflow">break</span>;
+<a name="l01689"></a>01689 
+<a name="l01690"></a>01690         <span class="keywordflow">case</span> UR_SET_INTERFACE:
+<a name="l01691"></a>01691         <span class="keywordflow">case</span> UR_SET_CONFIG:
+<a name="l01692"></a>01692 <span class="comment">//              _pcd-&gt;request_config = 1;       /* Configuration changed */</span>
+<a name="l01693"></a>01693                 <a class="code" href="dwc__otg__pcd__intr_8c.html#6c417c7d86bc9540e13ca4faeaf3dfbf">do_gadget_setup</a>(pcd, &amp;ctrl);
+<a name="l01694"></a>01694                 <span class="keywordflow">break</span>;
+<a name="l01695"></a>01695 
+<a name="l01696"></a>01696         <span class="keywordflow">case</span> UR_SYNCH_FRAME:
+<a name="l01697"></a>01697                 <a class="code" href="dwc__otg__pcd__intr_8c.html#6c417c7d86bc9540e13ca4faeaf3dfbf">do_gadget_setup</a>(pcd, &amp;ctrl);
+<a name="l01698"></a>01698                 <span class="keywordflow">break</span>;
+<a name="l01699"></a>01699 
+<a name="l01700"></a>01700         <span class="keywordflow">default</span>:
+<a name="l01701"></a>01701                 <span class="comment">/* Call the Gadget Driver's setup functions */</span>
+<a name="l01702"></a>01702                 <a class="code" href="dwc__otg__pcd__intr_8c.html#6c417c7d86bc9540e13ca4faeaf3dfbf">do_gadget_setup</a>(pcd, &amp;ctrl);
+<a name="l01703"></a>01703                 <span class="keywordflow">break</span>;
+<a name="l01704"></a>01704         }
+<a name="l01705"></a>01705 }
+<a name="l01706"></a>01706 
+<a name="l01710"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#f64bfae20151c51d3b0a6d4e523f356e">01710</a> <span class="keyword">static</span> int32_t <a class="code" href="dwc__otg__pcd__intr_8c.html#f64bfae20151c51d3b0a6d4e523f356e">ep0_complete_request</a>(<a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> * ep)
+<a name="l01711"></a>01711 {
+<a name="l01712"></a>01712         <a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if = <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#234391334e48cbd72710d08655c9ed16">pcd</a>);
+<a name="l01713"></a>01713         <a class="code" href="structdwc__otg__dev__if.html">dwc_otg_dev_if_t</a> *dev_if = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>;
+<a name="l01714"></a>01714         <a class="code" href="structdwc__otg__dev__in__ep__regs.html">dwc_otg_dev_in_ep_regs_t</a> *in_ep_regs =
+<a name="l01715"></a>01715             dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a>];
+<a name="l01716"></a>01716 <span class="preprocessor">#ifdef DEBUG_EP0</span>
+<a name="l01717"></a>01717 <span class="preprocessor"></span>        <a class="code" href="structdwc__otg__dev__out__ep__regs.html">dwc_otg_dev_out_ep_regs_t</a> *out_ep_regs =
+<a name="l01718"></a>01718             dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">out_ep_regs</a>[ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a>];
+<a name="l01719"></a>01719 <span class="preprocessor">#endif</span>
+<a name="l01720"></a>01720 <span class="preprocessor"></span>        <a class="code" href="uniondeptsiz0__data.html">deptsiz0_data_t</a> deptsiz;
+<a name="l01721"></a>01721         <a class="code" href="uniondev__dma__desc__sts.html">dev_dma_desc_sts_t</a> desc_sts;
+<a name="l01722"></a>01722         <a class="code" href="structdwc__otg__pcd__request.html">dwc_otg_pcd_request_t</a> *req;
+<a name="l01723"></a>01723         <span class="keywordtype">int</span> is_last = 0;
+<a name="l01724"></a>01724         <a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd = ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#234391334e48cbd72710d08655c9ed16">pcd</a>;
+<a name="l01725"></a>01725 
+<a name="l01726"></a>01726 <span class="preprocessor">#ifdef DWC_UTE_CFI</span>
+<a name="l01727"></a>01727 <span class="preprocessor"></span>        <span class="keyword">struct </span><a class="code" href="structcfi__usb__ctrlrequest.html">cfi_usb_ctrlrequest</a> *ctrlreq;
+<a name="l01728"></a>01728         <span class="keywordtype">int</span> retval = -DWC_E_NOT_SUPPORTED;
+<a name="l01729"></a>01729 <span class="preprocessor">#endif</span>
+<a name="l01730"></a>01730 <span class="preprocessor"></span>
+<a name="l01731"></a>01731         <span class="keywordflow">if</span> (pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#2c8be11c3b9c7cd02684348eb028aeb5">ep0_pending</a> &amp;&amp; DWC_CIRCLEQ_EMPTY(&amp;ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#71f4fa571dfdc96f62fa4869e6add300">queue</a>)) {
+<a name="l01732"></a>01732                 <span class="keywordflow">if</span> (ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#b882b6b7c857100ed20600e94ea37760">is_in</a>) {
+<a name="l01733"></a>01733 <span class="preprocessor">#ifdef DEBUG_EP0</span>
+<a name="l01734"></a>01734 <span class="preprocessor"></span>                        <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"Do setup OUT status phase\n"</span>);
+<a name="l01735"></a>01735 <span class="preprocessor">#endif</span>
+<a name="l01736"></a>01736 <span class="preprocessor"></span>                        <a class="code" href="dwc__otg__pcd__intr_8c.html#cce0022b7577cda90a2d2e78e1f8171b">do_setup_out_status_phase</a>(pcd);
+<a name="l01737"></a>01737                 } <span class="keywordflow">else</span> {
+<a name="l01738"></a>01738 <span class="preprocessor">#ifdef DEBUG_EP0</span>
+<a name="l01739"></a>01739 <span class="preprocessor"></span>                        <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"Do setup IN status phase\n"</span>);
+<a name="l01740"></a>01740 <span class="preprocessor">#endif</span>
+<a name="l01741"></a>01741 <span class="preprocessor"></span>
+<a name="l01742"></a>01742 <span class="preprocessor">#ifdef DWC_UTE_CFI</span>
+<a name="l01743"></a>01743 <span class="preprocessor"></span>                        ctrlreq = &amp;pcd-&gt;cfi-&gt;ctrl_req;
+<a name="l01744"></a>01744 
+<a name="l01745"></a>01745                         <span class="keywordflow">if</span> (UT_GET_TYPE(ctrlreq-&gt;<a class="code" href="structcfi__usb__ctrlrequest.html#6ba267845c2907b3908d3761c252b10c">bRequestType</a>) == UT_VENDOR) {
+<a name="l01746"></a>01746                                 <span class="keywordflow">if</span> (ctrlreq-&gt;<a class="code" href="structcfi__usb__ctrlrequest.html#b3083f525fa9bb97e41364418daee3fa">bRequest</a> &gt; 0xB0
+<a name="l01747"></a>01747                                     &amp;&amp; ctrlreq-&gt;<a class="code" href="structcfi__usb__ctrlrequest.html#b3083f525fa9bb97e41364418daee3fa">bRequest</a> &lt; 0xBF) {
+<a name="l01748"></a>01748 
+<a name="l01749"></a>01749                                         <span class="comment">/* Return if the PCD failed to handle the request */</span>
+<a name="l01750"></a>01750                                         <span class="keywordflow">if</span> ((retval =
+<a name="l01751"></a>01751                                              pcd-&gt;cfi-&gt;ops.
+<a name="l01752"></a>01752                                              ctrl_write_complete(pcd-&gt;cfi,
+<a name="l01753"></a>01753                                                                  pcd)) &lt; 0) {
+<a name="l01754"></a>01754                                                 <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>
+<a name="l01755"></a>01755                                                     (<span class="stringliteral">"ERROR setting a new value in the PCD(%d)\n"</span>,
+<a name="l01756"></a>01756                                                      retval);
+<a name="l01757"></a>01757                                                 <a class="code" href="dwc__otg__pcd__intr_8c.html#325b13e198ff56e9de2600ac7f28a57d">ep0_do_stall</a>(pcd, retval);
+<a name="l01758"></a>01758                                                 pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#2c8be11c3b9c7cd02684348eb028aeb5">ep0_pending</a> = 0;
+<a name="l01759"></a>01759                                                 <span class="keywordflow">return</span> 0;
+<a name="l01760"></a>01760                                         }
+<a name="l01761"></a>01761 
+<a name="l01762"></a>01762                                         <span class="comment">/* If the gadget needs to be notified on the request */</span>
+<a name="l01763"></a>01763                                         <span class="keywordflow">if</span> (pcd-&gt;cfi-&gt;need_gadget_att == 1) {
+<a name="l01764"></a>01764                                                 <span class="comment">//retval = do_gadget_setup(pcd, &amp;pcd-&gt;cfi-&gt;ctrl_req);</span>
+<a name="l01765"></a>01765                                                 retval =
+<a name="l01766"></a>01766                                                     cfi_gadget_setup(pcd,
+<a name="l01767"></a>01767                                                                      &amp;pcd-&gt;cfi-&gt;
+<a name="l01768"></a>01768                                                                      ctrl_req);
+<a name="l01769"></a>01769 
+<a name="l01770"></a>01770                                                 <span class="comment">/* Return from the function if the gadget failed to process</span>
+<a name="l01771"></a>01771 <span class="comment">                                                 * the request properly - this should never happen !!!</span>
+<a name="l01772"></a>01772 <span class="comment">                                                 */</span>
+<a name="l01773"></a>01773                                                 <span class="keywordflow">if</span> (retval &lt; 0) {
+<a name="l01774"></a>01774                                                         <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>
+<a name="l01775"></a>01775                                                             (<span class="stringliteral">"ERROR setting a new value in the gadget(%d)\n"</span>,
+<a name="l01776"></a>01776                                                              retval);
+<a name="l01777"></a>01777                                                         pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#2c8be11c3b9c7cd02684348eb028aeb5">ep0_pending</a> = 0;
+<a name="l01778"></a>01778                                                         <span class="keywordflow">return</span> 0;
+<a name="l01779"></a>01779                                                 }
+<a name="l01780"></a>01780                                         }
+<a name="l01781"></a>01781 
+<a name="l01782"></a>01782                                         <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>(<span class="stringliteral">"%s: RETVAL=%d\n"</span>, __func__,
+<a name="l01783"></a>01783                                                  retval);
+<a name="l01784"></a>01784                                         <span class="comment">/* If we hit here then the PCD and the gadget has properly</span>
+<a name="l01785"></a>01785 <span class="comment">                                         * handled the request - so send the ZLP IN to the host.</span>
+<a name="l01786"></a>01786 <span class="comment">                                         */</span>
+<a name="l01787"></a>01787                                         <span class="comment">/* @todo: MAS - decide whether we need to start the setup</span>
+<a name="l01788"></a>01788 <span class="comment">                                         * stage based on the need_setup value of the cfi object</span>
+<a name="l01789"></a>01789 <span class="comment">                                         */</span>
+<a name="l01790"></a>01790                                         <a class="code" href="dwc__otg__pcd__intr_8c.html#39d3face14e49b0f1ad5c978f87665fe">do_setup_in_status_phase</a>(pcd);
+<a name="l01791"></a>01791                                         pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#2c8be11c3b9c7cd02684348eb028aeb5">ep0_pending</a> = 0;
+<a name="l01792"></a>01792                                         <span class="keywordflow">return</span> 1;
+<a name="l01793"></a>01793                                 }
+<a name="l01794"></a>01794                         }
+<a name="l01795"></a>01795 <span class="preprocessor">#endif</span>
+<a name="l01796"></a>01796 <span class="preprocessor"></span>
+<a name="l01797"></a>01797                         <a class="code" href="dwc__otg__pcd__intr_8c.html#39d3face14e49b0f1ad5c978f87665fe">do_setup_in_status_phase</a>(pcd);
+<a name="l01798"></a>01798                 }
+<a name="l01799"></a>01799                 pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#2c8be11c3b9c7cd02684348eb028aeb5">ep0_pending</a> = 0;
+<a name="l01800"></a>01800                 <span class="keywordflow">return</span> 1;
+<a name="l01801"></a>01801         }
+<a name="l01802"></a>01802 
+<a name="l01803"></a>01803         <span class="keywordflow">if</span> (DWC_CIRCLEQ_EMPTY(&amp;ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#71f4fa571dfdc96f62fa4869e6add300">queue</a>)) {
+<a name="l01804"></a>01804                 <span class="keywordflow">return</span> 0;
+<a name="l01805"></a>01805         }
+<a name="l01806"></a>01806         req = DWC_CIRCLEQ_FIRST(&amp;ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#71f4fa571dfdc96f62fa4869e6add300">queue</a>);
+<a name="l01807"></a>01807 
+<a name="l01808"></a>01808         <span class="keywordflow">if</span> (pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#8f6963b3fb9ab83048c4c0697c90382a">ep0state</a> == EP0_OUT_STATUS_PHASE
+<a name="l01809"></a>01809             || pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#8f6963b3fb9ab83048c4c0697c90382a">ep0state</a> == EP0_IN_STATUS_PHASE) {
+<a name="l01810"></a>01810                 is_last = 1;
+<a name="l01811"></a>01811         } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#b882b6b7c857100ed20600e94ea37760">is_in</a>) {
+<a name="l01812"></a>01812                 deptsiz.<a class="code" href="uniondeptsiz0__data.html#a06fa9b1dcaee47fba9cf869027ed6f1">d32</a> = dwc_read_reg32(&amp;in_ep_regs-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#88f637b5a4e8a0c6bc87d157072255dd">dieptsiz</a>);
+<a name="l01813"></a>01813                 <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a> != 0)
+<a name="l01814"></a>01814                         desc_sts = dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#99f44e328bbb4401aabd8e2708853238">in_desc_addr</a>-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>;
+<a name="l01815"></a>01815 <span class="preprocessor">#ifdef DEBUG_EP0</span>
+<a name="l01816"></a>01816 <span class="preprocessor"></span>                <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"%d len=%d  xfersize=%d pktcnt=%d\n"</span>,
+<a name="l01817"></a>01817                             ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a>, ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">xfer_len</a>,
+<a name="l01818"></a>01818                             deptsiz.<a class="code" href="uniondeptsiz0__data.html#8e50594573fd774fc3e27404d8b1f59c">b</a>.<a class="code" href="uniondeptsiz0__data.html#1792e672dde70ead19bd0f5e7642af03">xfersize</a>, deptsiz.<a class="code" href="uniondeptsiz0__data.html#8e50594573fd774fc3e27404d8b1f59c">b</a>.<a class="code" href="uniondeptsiz0__data.html#debb8f273e4480cde57bef7677697bd0">pktcnt</a>);
+<a name="l01819"></a>01819 <span class="preprocessor">#endif</span>
+<a name="l01820"></a>01820 <span class="preprocessor"></span>
+<a name="l01821"></a>01821                 <span class="keywordflow">if</span> (((core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a> == 0)
+<a name="l01822"></a>01822                      &amp;&amp; (deptsiz.<a class="code" href="uniondeptsiz0__data.html#8e50594573fd774fc3e27404d8b1f59c">b</a>.<a class="code" href="uniondeptsiz0__data.html#1792e672dde70ead19bd0f5e7642af03">xfersize</a> == 0))
+<a name="l01823"></a>01823                     || ((core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a> != 0)
+<a name="l01824"></a>01824                         &amp;&amp; (desc_sts.<a class="code" href="uniondev__dma__desc__sts.html#1876c32496f0067948f6282b7583aeab">b</a>.<a class="code" href="uniondev__dma__desc__sts.html#9b6181d78984cb4d853945774f300ef0">bytes</a> == 0))) {
+<a name="l01825"></a>01825                         req-&gt;<a class="code" href="structdwc__otg__pcd__request.html#0fd7d659f353273d8b2b22027306a2a2">actual</a> = ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#23d4871510b5bcb54fbf0674d8f122bd">xfer_count</a>;
+<a name="l01826"></a>01826                         <span class="comment">/* Is a Zero Len Packet needed? */</span>
+<a name="l01827"></a>01827                         <span class="keywordflow">if</span> (req-&gt;<a class="code" href="structdwc__otg__pcd__request.html#c2c1832d46f417b63e41b5e23def6fc6">sent_zlp</a>) {
+<a name="l01828"></a>01828 <span class="preprocessor">#ifdef DEBUG_EP0</span>
+<a name="l01829"></a>01829 <span class="preprocessor"></span>                                <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"Setup Rx ZLP\n"</span>);
+<a name="l01830"></a>01830 <span class="preprocessor">#endif</span>
+<a name="l01831"></a>01831 <span class="preprocessor"></span>                                req-&gt;<a class="code" href="structdwc__otg__pcd__request.html#c2c1832d46f417b63e41b5e23def6fc6">sent_zlp</a> = 0;
+<a name="l01832"></a>01832                         }
+<a name="l01833"></a>01833                         <a class="code" href="dwc__otg__pcd__intr_8c.html#cce0022b7577cda90a2d2e78e1f8171b">do_setup_out_status_phase</a>(pcd);
+<a name="l01834"></a>01834                 }
+<a name="l01835"></a>01835         } <span class="keywordflow">else</span> {
+<a name="l01836"></a>01836                 <span class="comment">/* ep0-OUT */</span>
+<a name="l01837"></a>01837 <span class="preprocessor">#ifdef DEBUG_EP0</span>
+<a name="l01838"></a>01838 <span class="preprocessor"></span>                deptsiz.<a class="code" href="uniondeptsiz0__data.html#a06fa9b1dcaee47fba9cf869027ed6f1">d32</a> = dwc_read_reg32(&amp;out_ep_regs-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#e756ec48787099f0a4e2ce353fce4f91">doeptsiz</a>);
+<a name="l01839"></a>01839                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"%d len=%d xsize=%d pktcnt=%d\n"</span>,
+<a name="l01840"></a>01840                             ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a>, ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">xfer_len</a>,
+<a name="l01841"></a>01841                             deptsiz.<a class="code" href="uniondeptsiz0__data.html#8e50594573fd774fc3e27404d8b1f59c">b</a>.<a class="code" href="uniondeptsiz0__data.html#1792e672dde70ead19bd0f5e7642af03">xfersize</a>, deptsiz.<a class="code" href="uniondeptsiz0__data.html#8e50594573fd774fc3e27404d8b1f59c">b</a>.<a class="code" href="uniondeptsiz0__data.html#debb8f273e4480cde57bef7677697bd0">pktcnt</a>);
+<a name="l01842"></a>01842 <span class="preprocessor">#endif</span>
+<a name="l01843"></a>01843 <span class="preprocessor"></span>                req-&gt;<a class="code" href="structdwc__otg__pcd__request.html#0fd7d659f353273d8b2b22027306a2a2">actual</a> = ep-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#23d4871510b5bcb54fbf0674d8f122bd">xfer_count</a>;
+<a name="l01844"></a>01844 
+<a name="l01845"></a>01845                 <span class="comment">/* Is a Zero Len Packet needed? */</span>
+<a name="l01846"></a>01846                 <span class="keywordflow">if</span> (req-&gt;<a class="code" href="structdwc__otg__pcd__request.html#c2c1832d46f417b63e41b5e23def6fc6">sent_zlp</a>) {
+<a name="l01847"></a>01847 <span class="preprocessor">#ifdef DEBUG_EP0</span>
+<a name="l01848"></a>01848 <span class="preprocessor"></span>                        <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"Setup Tx ZLP\n"</span>);
+<a name="l01849"></a>01849 <span class="preprocessor">#endif</span>
+<a name="l01850"></a>01850 <span class="preprocessor"></span>                        req-&gt;<a class="code" href="structdwc__otg__pcd__request.html#c2c1832d46f417b63e41b5e23def6fc6">sent_zlp</a> = 0;
+<a name="l01851"></a>01851                 }
+<a name="l01852"></a>01852                 <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a> == 0)
+<a name="l01853"></a>01853                         <a class="code" href="dwc__otg__pcd__intr_8c.html#39d3face14e49b0f1ad5c978f87665fe">do_setup_in_status_phase</a>(pcd);
+<a name="l01854"></a>01854         }
+<a name="l01855"></a>01855 
+<a name="l01856"></a>01856         <span class="comment">/* Complete the request */</span>
+<a name="l01857"></a>01857         <span class="keywordflow">if</span> (is_last) {
+<a name="l01858"></a>01858                 <a class="code" href="dwc__otg__pcd_8c.html#5c9b20abc81e0f860a8f23c90b10b59e">dwc_otg_request_done</a>(ep, req, 0);
+<a name="l01859"></a>01859                 ep-&gt;dwc_ep.start_xfer_buff = 0;
+<a name="l01860"></a>01860                 ep-&gt;dwc_ep.xfer_buff = 0;
+<a name="l01861"></a>01861                 ep-&gt;dwc_ep.xfer_len = 0;
+<a name="l01862"></a>01862                 <span class="keywordflow">return</span> 1;
+<a name="l01863"></a>01863         }
+<a name="l01864"></a>01864         <span class="keywordflow">return</span> 0;
+<a name="l01865"></a>01865 }
+<a name="l01866"></a>01866 
+<a name="l01867"></a>01867 <span class="preprocessor">#ifdef DWC_UTE_CFI</span>
+<a name="l01868"></a>01868 <span class="preprocessor"></span>
+<a name="l01874"></a>01874 <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">int</span> cfi_calc_desc_residue(<a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> * ep)
+<a name="l01875"></a>01875 {
+<a name="l01876"></a>01876         int32_t ret = 0;
+<a name="l01877"></a>01877         <span class="keywordtype">int</span> i;
+<a name="l01878"></a>01878         <span class="keyword">struct </span>dwc_otg_dma_desc *ddesc = NULL;
+<a name="l01879"></a>01879         <span class="keyword">struct </span><a class="code" href="structcfi__ep.html">cfi_ep</a> *cfiep;
+<a name="l01880"></a>01880 
+<a name="l01881"></a>01881         <span class="comment">/* See if the pcd_ep has its respective cfi_ep mapped */</span>
+<a name="l01882"></a>01882         cfiep = <a class="code" href="dwc__otg__cfi_8h.html#c21284d5adf03032d094a36babf9b1e5">get_cfi_ep_by_pcd_ep</a>(<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#234391334e48cbd72710d08655c9ed16">pcd</a>-&gt;cfi, <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>);
+<a name="l01883"></a>01883         <span class="keywordflow">if</span> (!cfiep) {
+<a name="l01884"></a>01884                 <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>(<span class="stringliteral">"%s: Failed to find ep\n"</span>, __func__);
+<a name="l01885"></a>01885                 <span class="keywordflow">return</span> -1;
+<a name="l01886"></a>01886         }
+<a name="l01887"></a>01887 
+<a name="l01888"></a>01888         ddesc = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.descs;
+<a name="l01889"></a>01889 
+<a name="l01890"></a>01890         <span class="keywordflow">for</span> (i = 0; (i &lt; cfiep-&gt;<a class="code" href="structcfi__ep.html#73050a3011b918e8be6c2434db357514">desc_count</a>) &amp;&amp; (i &lt; MAX_DMA_DESCS_PER_EP); i++) {
+<a name="l01891"></a>01891 
+<a name="l01892"></a>01892 #<span class="keywordflow">if</span> defined(PRINT_CFI_DMA_DESCS)
+<a name="l01893"></a>01893                 print_desc(ddesc, <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;ep.name, i);
+<a name="l01894"></a>01894 #endif
+<a name="l01895"></a>01895                 ret += ddesc-&gt;status.b.bytes;
+<a name="l01896"></a>01896                 ddesc++;
+<a name="l01897"></a>01897         }
+<a name="l01898"></a>01898 
+<a name="l01899"></a>01899         <span class="keywordflow">if</span> (ret)
+<a name="l01900"></a>01900                 <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>(<span class="stringliteral">"!!!!!!!!!! WARNING (%s) - residue=%d\n"</span>, __func__,
+<a name="l01901"></a>01901                          ret);
+<a name="l01902"></a>01902 
+<a name="l01903"></a>01903         <span class="keywordflow">return</span> ret;
+<a name="l01904"></a>01904 }
+<a name="l01905"></a>01905 <span class="preprocessor">#endif</span>
+<a name="l01906"></a>01906 <span class="preprocessor"></span>
+<a name="l01911"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#c77f277130ba55b19100bde598da7d85">01911</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd__intr_8c.html#c77f277130ba55b19100bde598da7d85">complete_ep</a>(<a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> * <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>)
+<a name="l01912"></a>01912 {
+<a name="l01913"></a>01913         <a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if = <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#234391334e48cbd72710d08655c9ed16">pcd</a>);
+<a name="l01914"></a>01914         <a class="code" href="structdwc__otg__dev__if.html">dwc_otg_dev_if_t</a> *dev_if = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>;
+<a name="l01915"></a>01915         <a class="code" href="structdwc__otg__dev__in__ep__regs.html">dwc_otg_dev_in_ep_regs_t</a> *in_ep_regs =
+<a name="l01916"></a>01916             dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a>];
+<a name="l01917"></a>01917         <a class="code" href="uniondeptsiz__data.html">deptsiz_data_t</a> deptsiz;
+<a name="l01918"></a>01918         <a class="code" href="uniondev__dma__desc__sts.html">dev_dma_desc_sts_t</a> desc_sts;
+<a name="l01919"></a>01919         <a class="code" href="structdwc__otg__pcd__request.html">dwc_otg_pcd_request_t</a> *req = 0;
+<a name="l01920"></a>01920         <a class="code" href="structdwc__otg__dev__dma__desc.html">dwc_otg_dev_dma_desc_t</a> *dma_desc;
+<a name="l01921"></a>01921         uint32_t byte_count = 0;
+<a name="l01922"></a>01922         <span class="keywordtype">int</span> is_last = 0;
+<a name="l01923"></a>01923         <span class="keywordtype">int</span> i;
+<a name="l01924"></a>01924 
+<a name="l01925"></a>01925         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"%s() %d-%s\n"</span>, __func__, <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a>,
+<a name="l01926"></a>01926                     (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#b882b6b7c857100ed20600e94ea37760">is_in</a> ? <span class="stringliteral">"IN"</span> : <span class="stringliteral">"OUT"</span>));
+<a name="l01927"></a>01927 
+<a name="l01928"></a>01928         <span class="comment">/* Get any pending requests */</span>
+<a name="l01929"></a>01929         <span class="keywordflow">if</span> (!DWC_CIRCLEQ_EMPTY(&amp;<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#71f4fa571dfdc96f62fa4869e6add300">queue</a>)) {
+<a name="l01930"></a>01930                 req = DWC_CIRCLEQ_FIRST(&amp;<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#71f4fa571dfdc96f62fa4869e6add300">queue</a>);
+<a name="l01931"></a>01931                 <span class="keywordflow">if</span> (!req) {
+<a name="l01932"></a>01932                         DWC_PRINTF(<span class="stringliteral">"complete_ep 0x%p, req = NULL!\n"</span>, <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>);
+<a name="l01933"></a>01933                         <span class="keywordflow">return</span>;
+<a name="l01934"></a>01934                 }
+<a name="l01935"></a>01935         } <span class="keywordflow">else</span> {
+<a name="l01936"></a>01936                 DWC_PRINTF(<span class="stringliteral">"complete_ep 0x%p, ep-&gt;queue empty!\n"</span>, <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>);
+<a name="l01937"></a>01937                 <span class="keywordflow">return</span>;
+<a name="l01938"></a>01938         }
+<a name="l01939"></a>01939 
+<a name="l01940"></a>01940         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"Requests %d\n"</span>, <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#234391334e48cbd72710d08655c9ed16">pcd</a>-&gt;<a class="code" href="structdwc__otg__pcd.html#3a0464b4ac677a7742e9b7c0c820414c">request_pending</a>);
+<a name="l01941"></a>01941 
+<a name="l01942"></a>01942         <span class="keywordflow">if</span> (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#b882b6b7c857100ed20600e94ea37760">is_in</a>) {
+<a name="l01943"></a>01943                 deptsiz.<a class="code" href="uniondeptsiz__data.html#10c2b2ba8b419b0a766430a59befbbe0">d32</a> = dwc_read_reg32(&amp;in_ep_regs-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#88f637b5a4e8a0c6bc87d157072255dd">dieptsiz</a>);
+<a name="l01944"></a>01944 
+<a name="l01945"></a>01945                 <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a>) {
+<a name="l01946"></a>01946                         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a> == 0) {
+<a name="l01947"></a>01947                                 <span class="keywordflow">if</span> (deptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#cf06327d851e7cfe5c442b29bf2d6fa4">xfersize</a> == 0
+<a name="l01948"></a>01948                                     &amp;&amp; deptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#bbd89e812371e5b555bb82373f3643d9">pktcnt</a> == 0) {
+<a name="l01949"></a>01949                                         byte_count =
+<a name="l01950"></a>01950                                             <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">xfer_len</a> -
+<a name="l01951"></a>01951                                             <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#23d4871510b5bcb54fbf0674d8f122bd">xfer_count</a>;
+<a name="l01952"></a>01952 
+<a name="l01953"></a>01953                                         <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#97fa9bf5c31ba734d54f70e6fe6ae8eb">xfer_buff</a> += byte_count;
+<a name="l01954"></a>01954                                         <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#b40ce70422b6d105a855a8df4b33d45d">dma_addr</a> += byte_count;
+<a name="l01955"></a>01955                                         <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#23d4871510b5bcb54fbf0674d8f122bd">xfer_count</a> += byte_count;
+<a name="l01956"></a>01956 
+<a name="l01957"></a>01957                                         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>,
+<a name="l01958"></a>01958                                                     <span class="stringliteral">"%d-%s len=%d  xfersize=%d pktcnt=%d\n"</span>,
+<a name="l01959"></a>01959                                                     <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a>,
+<a name="l01960"></a>01960                                                     (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.
+<a name="l01961"></a>01961                                                      is_in ? <span class="stringliteral">"IN"</span> : <span class="stringliteral">"OUT"</span>),
+<a name="l01962"></a>01962                                                     <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">xfer_len</a>,
+<a name="l01963"></a>01963                                                     deptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#cf06327d851e7cfe5c442b29bf2d6fa4">xfersize</a>,
+<a name="l01964"></a>01964                                                     deptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#bbd89e812371e5b555bb82373f3643d9">pktcnt</a>);
+<a name="l01965"></a>01965 
+<a name="l01966"></a>01966                                         <span class="keywordflow">if</span> (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">xfer_len</a> &lt;
+<a name="l01967"></a>01967                                             <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#5a218f200cff0491b735f43fed5176bf">total_len</a>) {
+<a name="l01968"></a>01968                                                 <a class="code" href="dwc__otg__cil_8c.html#1278f6d58a4a2bc780e90e0b6c9b9a68">dwc_otg_ep_start_transfer</a>
+<a name="l01969"></a>01969                                                     (core_if, &amp;<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>);
+<a name="l01970"></a>01970                                         } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#8c6340435beba0b8c025a4677602acab">sent_zlp</a>) {
+<a name="l01971"></a>01971                                                 <span class="comment">/*      </span>
+<a name="l01972"></a>01972 <span class="comment">                                                 * This fragment of code should initiate 0 </span>
+<a name="l01973"></a>01973 <span class="comment">                                                 * length trasfer in case if it is queued</span>
+<a name="l01974"></a>01974 <span class="comment">                                                 * a trasfer with size divisible to EPs max </span>
+<a name="l01975"></a>01975 <span class="comment">                                                 * packet size and with usb_request zero field </span>
+<a name="l01976"></a>01976 <span class="comment">                                                 * is set, which means that after data is transfered, </span>
+<a name="l01977"></a>01977 <span class="comment">                                                 * it is also should be transfered </span>
+<a name="l01978"></a>01978 <span class="comment">                                                 * a 0 length packet at the end. For Slave and </span>
+<a name="l01979"></a>01979 <span class="comment">                                                 * Buffer DMA modes in this case SW has </span>
+<a name="l01980"></a>01980 <span class="comment">                                                 * to initiate 2 transfers one with transfer size, </span>
+<a name="l01981"></a>01981 <span class="comment">                                                 * and the second with 0 size. For Desriptor </span>
+<a name="l01982"></a>01982 <span class="comment">                                                 * DMA mode SW is able to initiate a transfer, </span>
+<a name="l01983"></a>01983 <span class="comment">                                                 * which will handle all the packets including </span>
+<a name="l01984"></a>01984 <span class="comment">                                                 * the last  0 legth.</span>
+<a name="l01985"></a>01985 <span class="comment">                                                 */</span>
+<a name="l01986"></a>01986                                                 <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#8c6340435beba0b8c025a4677602acab">sent_zlp</a> = 0;
+<a name="l01987"></a>01987                                                 <a class="code" href="dwc__otg__cil_8c.html#fcc9f9b12c040c3649f0b8273a24ddf7">dwc_otg_ep_start_zl_transfer</a>
+<a name="l01988"></a>01988                                                     (core_if, &amp;<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>);
+<a name="l01989"></a>01989                                         } <span class="keywordflow">else</span> {
+<a name="l01990"></a>01990                                                 is_last = 1;
+<a name="l01991"></a>01991                                         }
+<a name="l01992"></a>01992                                 } <span class="keywordflow">else</span> {
+<a name="l01993"></a>01993                                         DWC_WARN
+<a name="l01994"></a>01994                                             (<span class="stringliteral">"Incomplete transfer (%d - %s [siz=%d pkt=%d])\n"</span>,
+<a name="l01995"></a>01995                                              <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a>,
+<a name="l01996"></a>01996                                              (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#b882b6b7c857100ed20600e94ea37760">is_in</a> ? <span class="stringliteral">"IN"</span> : <span class="stringliteral">"OUT"</span>),
+<a name="l01997"></a>01997                                              deptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#cf06327d851e7cfe5c442b29bf2d6fa4">xfersize</a>,
+<a name="l01998"></a>01998                                              deptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#bbd89e812371e5b555bb82373f3643d9">pktcnt</a>);
+<a name="l01999"></a>01999                                 }
+<a name="l02000"></a>02000                         } <span class="keywordflow">else</span> {
+<a name="l02001"></a>02001                                 dma_desc = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#57e934b26e76939912eaa76321075a0d">desc_addr</a>;
+<a name="l02002"></a>02002                                 byte_count = 0;
+<a name="l02003"></a>02003                                 <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#8c6340435beba0b8c025a4677602acab">sent_zlp</a> = 0;
+<a name="l02004"></a>02004 
+<a name="l02005"></a>02005 <span class="preprocessor">#ifdef DWC_UTE_CFI</span>
+<a name="l02006"></a>02006 <span class="preprocessor"></span>                                <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>(<span class="stringliteral">"%s: BUFFER_MODE=%d\n"</span>, __func__,
+<a name="l02007"></a>02007                                          <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.buff_mode);
+<a name="l02008"></a>02008                                 <span class="keywordflow">if</span> (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.buff_mode != BM_STANDARD) {
+<a name="l02009"></a>02009                                         <span class="keywordtype">int</span> residue;
+<a name="l02010"></a>02010 
+<a name="l02011"></a>02011                                         residue = cfi_calc_desc_residue(<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>);
+<a name="l02012"></a>02012                                         <span class="keywordflow">if</span> (residue &lt; 0)
+<a name="l02013"></a>02013                                                 <span class="keywordflow">return</span>;
+<a name="l02014"></a>02014 
+<a name="l02015"></a>02015                                         byte_count = residue;
+<a name="l02016"></a>02016                                 } <span class="keywordflow">else</span> {
+<a name="l02017"></a>02017 <span class="preprocessor">#endif</span>
+<a name="l02018"></a>02018 <span class="preprocessor"></span>                                        <span class="keywordflow">for</span> (i = 0; i &lt; <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#5e5bfcc93d41670bc0d29ad5f0f35871">desc_cnt</a>;
+<a name="l02019"></a>02019                                              ++i) {
+<a name="l02020"></a>02020                                         desc_sts = dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>;
+<a name="l02021"></a>02021                                         byte_count += desc_sts.<a class="code" href="uniondev__dma__desc__sts.html#1876c32496f0067948f6282b7583aeab">b</a>.<a class="code" href="uniondev__dma__desc__sts.html#9b6181d78984cb4d853945774f300ef0">bytes</a>;
+<a name="l02022"></a>02022                                         dma_desc++;
+<a name="l02023"></a>02023                                 }
+<a name="l02024"></a>02024 <span class="preprocessor">#ifdef DWC_UTE_CFI</span>
+<a name="l02025"></a>02025 <span class="preprocessor"></span>                                }
+<a name="l02026"></a>02026 <span class="preprocessor">#endif</span>
+<a name="l02027"></a>02027 <span class="preprocessor"></span>                                <span class="keywordflow">if</span> (byte_count == 0) {
+<a name="l02028"></a>02028                                         <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#23d4871510b5bcb54fbf0674d8f122bd">xfer_count</a> =
+<a name="l02029"></a>02029                                             <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#5a218f200cff0491b735f43fed5176bf">total_len</a>;
+<a name="l02030"></a>02030                                         is_last = 1;
+<a name="l02031"></a>02031                                 } <span class="keywordflow">else</span> {
+<a name="l02032"></a>02032                                         DWC_WARN(<span class="stringliteral">"Incomplete transfer\n"</span>);
+<a name="l02033"></a>02033                                 }
+<a name="l02034"></a>02034                         }
+<a name="l02035"></a>02035                 } <span class="keywordflow">else</span> {
+<a name="l02036"></a>02036                         <span class="keywordflow">if</span> (deptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#cf06327d851e7cfe5c442b29bf2d6fa4">xfersize</a> == 0 &amp;&amp; deptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#bbd89e812371e5b555bb82373f3643d9">pktcnt</a> == 0) {
+<a name="l02037"></a>02037                                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>,
+<a name="l02038"></a>02038                                             <span class="stringliteral">"%d-%s len=%d  xfersize=%d pktcnt=%d\n"</span>,
+<a name="l02039"></a>02039                                             <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a>,
+<a name="l02040"></a>02040                                             <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#b882b6b7c857100ed20600e94ea37760">is_in</a> ? <span class="stringliteral">"IN"</span> : <span class="stringliteral">"OUT"</span>,
+<a name="l02041"></a>02041                                             <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">xfer_len</a>,
+<a name="l02042"></a>02042                                             deptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#cf06327d851e7cfe5c442b29bf2d6fa4">xfersize</a>,
+<a name="l02043"></a>02043                                             deptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#bbd89e812371e5b555bb82373f3643d9">pktcnt</a>);
+<a name="l02044"></a>02044 
+<a name="l02045"></a>02045                                 <span class="comment">/*      Check if the whole transfer was completed,  </span>
+<a name="l02046"></a>02046 <span class="comment">                                 *      if no, setup transfer for next portion of data</span>
+<a name="l02047"></a>02047 <span class="comment">                                 */</span>
+<a name="l02048"></a>02048                                 <span class="keywordflow">if</span> (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">xfer_len</a> &lt; <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#5a218f200cff0491b735f43fed5176bf">total_len</a>) {
+<a name="l02049"></a>02049                                         <a class="code" href="dwc__otg__cil_8c.html#1278f6d58a4a2bc780e90e0b6c9b9a68">dwc_otg_ep_start_transfer</a>(core_if,
+<a name="l02050"></a>02050                                                                   &amp;<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>);
+<a name="l02051"></a>02051                                 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#8c6340435beba0b8c025a4677602acab">sent_zlp</a>) {
+<a name="l02052"></a>02052                                         <span class="comment">/*      </span>
+<a name="l02053"></a>02053 <span class="comment">                                         * This fragment of code should initiate 0 </span>
+<a name="l02054"></a>02054 <span class="comment">                                         * length trasfer in case if it is queued</span>
+<a name="l02055"></a>02055 <span class="comment">                                         * a trasfer with size divisible to EPs max </span>
+<a name="l02056"></a>02056 <span class="comment">                                         * packet size and with usb_request zero field </span>
+<a name="l02057"></a>02057 <span class="comment">                                         * is set, which means that after data is transfered, </span>
+<a name="l02058"></a>02058 <span class="comment">                                         * it is also should be transfered </span>
+<a name="l02059"></a>02059 <span class="comment">                                         * a 0 length packet at the end. For Slave and </span>
+<a name="l02060"></a>02060 <span class="comment">                                         * Buffer DMA modes in this case SW has </span>
+<a name="l02061"></a>02061 <span class="comment">                                         * to initiate 2 transfers one with transfer size, </span>
+<a name="l02062"></a>02062 <span class="comment">                                         * and the second with 0 size. For Desriptor </span>
+<a name="l02063"></a>02063 <span class="comment">                                         * DMA mode SW is able to initiate a transfer, </span>
+<a name="l02064"></a>02064 <span class="comment">                                         * which will handle all the packets including </span>
+<a name="l02065"></a>02065 <span class="comment">                                         * the last  0 legth.</span>
+<a name="l02066"></a>02066 <span class="comment">                                         */</span>
+<a name="l02067"></a>02067                                         <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#8c6340435beba0b8c025a4677602acab">sent_zlp</a> = 0;
+<a name="l02068"></a>02068                                         <a class="code" href="dwc__otg__cil_8c.html#fcc9f9b12c040c3649f0b8273a24ddf7">dwc_otg_ep_start_zl_transfer</a>(core_if,
+<a name="l02069"></a>02069                                                                      &amp;<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;
+<a name="l02070"></a>02070                                                                      <a class="code" href="structdwc__ep.html">dwc_ep</a>);
+<a name="l02071"></a>02071                                 } <span class="keywordflow">else</span> {
+<a name="l02072"></a>02072                                         is_last = 1;
+<a name="l02073"></a>02073                                 }
+<a name="l02074"></a>02074                         } <span class="keywordflow">else</span> {
+<a name="l02075"></a>02075                                 DWC_WARN
+<a name="l02076"></a>02076                                     (<span class="stringliteral">"Incomplete transfer (%d-%s [siz=%d pkt=%d])\n"</span>,
+<a name="l02077"></a>02077                                      <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a>,
+<a name="l02078"></a>02078                                      (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#b882b6b7c857100ed20600e94ea37760">is_in</a> ? <span class="stringliteral">"IN"</span> : <span class="stringliteral">"OUT"</span>),
+<a name="l02079"></a>02079                                      deptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#cf06327d851e7cfe5c442b29bf2d6fa4">xfersize</a>, deptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#bbd89e812371e5b555bb82373f3643d9">pktcnt</a>);
+<a name="l02080"></a>02080                         }
+<a name="l02081"></a>02081                 }
+<a name="l02082"></a>02082         } <span class="keywordflow">else</span> {
+<a name="l02083"></a>02083                 <a class="code" href="structdwc__otg__dev__out__ep__regs.html">dwc_otg_dev_out_ep_regs_t</a> *out_ep_regs =
+<a name="l02084"></a>02084                     dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">out_ep_regs</a>[<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a>];
+<a name="l02085"></a>02085                 desc_sts.<a class="code" href="uniondev__dma__desc__sts.html#fb77b9c4ab63304073542ed2b118a64b">d32</a> = 0;
+<a name="l02086"></a>02086                 <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a>) {
+<a name="l02087"></a>02087                         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a>) {
+<a name="l02088"></a>02088                                 dma_desc = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#57e934b26e76939912eaa76321075a0d">desc_addr</a>;
+<a name="l02089"></a>02089                                 byte_count = 0;
+<a name="l02090"></a>02090                                 <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#8c6340435beba0b8c025a4677602acab">sent_zlp</a> = 0;
+<a name="l02091"></a>02091 
+<a name="l02092"></a>02092 <span class="preprocessor">#ifdef DWC_UTE_CFI</span>
+<a name="l02093"></a>02093 <span class="preprocessor"></span>                                <a class="code" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">CFI_INFO</a>(<span class="stringliteral">"%s: BUFFER_MODE=%d\n"</span>, __func__,
+<a name="l02094"></a>02094                                          <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.buff_mode);
+<a name="l02095"></a>02095                                 <span class="keywordflow">if</span> (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.buff_mode != BM_STANDARD) {
+<a name="l02096"></a>02096                                         <span class="keywordtype">int</span> residue;
+<a name="l02097"></a>02097                                         residue = cfi_calc_desc_residue(<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>);
+<a name="l02098"></a>02098                                         <span class="keywordflow">if</span> (residue &lt; 0)
+<a name="l02099"></a>02099                                                 <span class="keywordflow">return</span>;
+<a name="l02100"></a>02100                                         byte_count = residue;
+<a name="l02101"></a>02101                                 } <span class="keywordflow">else</span> {
+<a name="l02102"></a>02102 <span class="preprocessor">#endif</span>
+<a name="l02103"></a>02103 <span class="preprocessor"></span>
+<a name="l02104"></a>02104                                         <span class="keywordflow">for</span> (i = 0; i &lt; <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#5e5bfcc93d41670bc0d29ad5f0f35871">desc_cnt</a>;
+<a name="l02105"></a>02105                                              ++i) {
+<a name="l02106"></a>02106                                         desc_sts = dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>;
+<a name="l02107"></a>02107                                         byte_count += desc_sts.<a class="code" href="uniondev__dma__desc__sts.html#1876c32496f0067948f6282b7583aeab">b</a>.<a class="code" href="uniondev__dma__desc__sts.html#9b6181d78984cb4d853945774f300ef0">bytes</a>;
+<a name="l02108"></a>02108                                         dma_desc++;
+<a name="l02109"></a>02109                                 }
+<a name="l02110"></a>02110 
+<a name="l02111"></a>02111 <span class="preprocessor">#ifdef DWC_UTE_CFI</span>
+<a name="l02112"></a>02112 <span class="preprocessor"></span>                                }
+<a name="l02113"></a>02113 <span class="preprocessor">#endif</span>
+<a name="l02114"></a>02114 <span class="preprocessor"></span>                                <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#23d4871510b5bcb54fbf0674d8f122bd">xfer_count</a> = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#5a218f200cff0491b735f43fed5176bf">total_len</a>
+<a name="l02115"></a>02115                                     - byte_count +
+<a name="l02116"></a>02116                                     ((4 - (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#5a218f200cff0491b735f43fed5176bf">total_len</a> &amp; 0x3)) &amp; 0x3);
+<a name="l02117"></a>02117                                 is_last = 1;
+<a name="l02118"></a>02118                         } <span class="keywordflow">else</span> {
+<a name="l02119"></a>02119                                 deptsiz.<a class="code" href="uniondeptsiz__data.html#10c2b2ba8b419b0a766430a59befbbe0">d32</a> = 0;
+<a name="l02120"></a>02120                                 deptsiz.<a class="code" href="uniondeptsiz__data.html#10c2b2ba8b419b0a766430a59befbbe0">d32</a> =
+<a name="l02121"></a>02121                                     dwc_read_reg32(&amp;out_ep_regs-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#e756ec48787099f0a4e2ce353fce4f91">doeptsiz</a>);
+<a name="l02122"></a>02122 
+<a name="l02123"></a>02123                                 byte_count = (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">xfer_len</a> -
+<a name="l02124"></a>02124                                               <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#23d4871510b5bcb54fbf0674d8f122bd">xfer_count</a> -
+<a name="l02125"></a>02125                                               deptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#cf06327d851e7cfe5c442b29bf2d6fa4">xfersize</a>);
+<a name="l02126"></a>02126                                 <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#97fa9bf5c31ba734d54f70e6fe6ae8eb">xfer_buff</a> += byte_count;
+<a name="l02127"></a>02127                                 <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#b40ce70422b6d105a855a8df4b33d45d">dma_addr</a> += byte_count;
+<a name="l02128"></a>02128                                 <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#23d4871510b5bcb54fbf0674d8f122bd">xfer_count</a> += byte_count;
+<a name="l02129"></a>02129 
+<a name="l02130"></a>02130                                 <span class="comment">/*      Check if the whole transfer was completed,  </span>
+<a name="l02131"></a>02131 <span class="comment">                                 *      if no, setup transfer for next portion of data</span>
+<a name="l02132"></a>02132 <span class="comment">                                 */</span>
+<a name="l02133"></a>02133                                 <span class="keywordflow">if</span> (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">xfer_len</a> &lt; <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#5a218f200cff0491b735f43fed5176bf">total_len</a>) {
+<a name="l02134"></a>02134                                         <a class="code" href="dwc__otg__cil_8c.html#1278f6d58a4a2bc780e90e0b6c9b9a68">dwc_otg_ep_start_transfer</a>(core_if,
+<a name="l02135"></a>02135                                                                   &amp;<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>);
+<a name="l02136"></a>02136                                 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#8c6340435beba0b8c025a4677602acab">sent_zlp</a>) {
+<a name="l02137"></a>02137                                         <span class="comment">/*      </span>
+<a name="l02138"></a>02138 <span class="comment">                                         * This fragment of code should initiate 0 </span>
+<a name="l02139"></a>02139 <span class="comment">                                         * length trasfer in case if it is queued</span>
+<a name="l02140"></a>02140 <span class="comment">                                         * a trasfer with size divisible to EPs max </span>
+<a name="l02141"></a>02141 <span class="comment">                                         * packet size and with usb_request zero field </span>
+<a name="l02142"></a>02142 <span class="comment">                                         * is set, which means that after data is transfered, </span>
+<a name="l02143"></a>02143 <span class="comment">                                         * it is also should be transfered </span>
+<a name="l02144"></a>02144 <span class="comment">                                         * a 0 length packet at the end. For Slave and </span>
+<a name="l02145"></a>02145 <span class="comment">                                         * Buffer DMA modes in this case SW has </span>
+<a name="l02146"></a>02146 <span class="comment">                                         * to initiate 2 transfers one with transfer size, </span>
+<a name="l02147"></a>02147 <span class="comment">                                         * and the second with 0 size. For Desriptor </span>
+<a name="l02148"></a>02148 <span class="comment">                                         * DMA mode SW is able to initiate a transfer, </span>
+<a name="l02149"></a>02149 <span class="comment">                                         * which will handle all the packets including </span>
+<a name="l02150"></a>02150 <span class="comment">                                         * the last  0 legth.</span>
+<a name="l02151"></a>02151 <span class="comment">                                         */</span>
+<a name="l02152"></a>02152                                         <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#8c6340435beba0b8c025a4677602acab">sent_zlp</a> = 0;
+<a name="l02153"></a>02153                                         <a class="code" href="dwc__otg__cil_8c.html#fcc9f9b12c040c3649f0b8273a24ddf7">dwc_otg_ep_start_zl_transfer</a>(core_if,
+<a name="l02154"></a>02154                                                                      &amp;<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;
+<a name="l02155"></a>02155                                                                      <a class="code" href="structdwc__ep.html">dwc_ep</a>);
+<a name="l02156"></a>02156                                 } <span class="keywordflow">else</span> {
+<a name="l02157"></a>02157                                         is_last = 1;
+<a name="l02158"></a>02158                                 }
+<a name="l02159"></a>02159                         }
+<a name="l02160"></a>02160                 } <span class="keywordflow">else</span> {
+<a name="l02161"></a>02161                         <span class="comment">/*      Check if the whole transfer was completed,  </span>
+<a name="l02162"></a>02162 <span class="comment">                         *      if no, setup transfer for next portion of data</span>
+<a name="l02163"></a>02163 <span class="comment">                         */</span>
+<a name="l02164"></a>02164                         <span class="keywordflow">if</span> (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">xfer_len</a> &lt; <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#5a218f200cff0491b735f43fed5176bf">total_len</a>) {
+<a name="l02165"></a>02165                                 <a class="code" href="dwc__otg__cil_8c.html#1278f6d58a4a2bc780e90e0b6c9b9a68">dwc_otg_ep_start_transfer</a>(core_if, &amp;<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>);
+<a name="l02166"></a>02166                         } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#8c6340435beba0b8c025a4677602acab">sent_zlp</a>) {
+<a name="l02167"></a>02167                                 <span class="comment">/*      </span>
+<a name="l02168"></a>02168 <span class="comment">                                 * This fragment of code should initiate 0 </span>
+<a name="l02169"></a>02169 <span class="comment">                                 * length trasfer in case if it is queued</span>
+<a name="l02170"></a>02170 <span class="comment">                                 * a trasfer with size divisible to EPs max </span>
+<a name="l02171"></a>02171 <span class="comment">                                 * packet size and with usb_request zero field </span>
+<a name="l02172"></a>02172 <span class="comment">                                 * is set, which means that after data is transfered, </span>
+<a name="l02173"></a>02173 <span class="comment">                                 * it is also should be transfered </span>
+<a name="l02174"></a>02174 <span class="comment">                                 * a 0 length packet at the end. For Slave and </span>
+<a name="l02175"></a>02175 <span class="comment">                                 * Buffer DMA modes in this case SW has </span>
+<a name="l02176"></a>02176 <span class="comment">                                 * to initiate 2 transfers one with transfer size, </span>
+<a name="l02177"></a>02177 <span class="comment">                                 * and the second with 0 size. For Desriptor </span>
+<a name="l02178"></a>02178 <span class="comment">                                 * DMA mode SW is able to initiate a transfer, </span>
+<a name="l02179"></a>02179 <span class="comment">                                 * which will handle all the packets including </span>
+<a name="l02180"></a>02180 <span class="comment">                                 * the last  0 legth.</span>
+<a name="l02181"></a>02181 <span class="comment">                                 */</span>
+<a name="l02182"></a>02182                                 <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#8c6340435beba0b8c025a4677602acab">sent_zlp</a> = 0;
+<a name="l02183"></a>02183                                 <a class="code" href="dwc__otg__cil_8c.html#fcc9f9b12c040c3649f0b8273a24ddf7">dwc_otg_ep_start_zl_transfer</a>(core_if,
+<a name="l02184"></a>02184                                                              &amp;<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>);
+<a name="l02185"></a>02185                         } <span class="keywordflow">else</span> {
+<a name="l02186"></a>02186                                 is_last = 1;
+<a name="l02187"></a>02187                         }
+<a name="l02188"></a>02188                 }
+<a name="l02189"></a>02189 
+<a name="l02190"></a>02190                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>,
+<a name="l02191"></a>02191                             <span class="stringliteral">"addr %p,    %d-%s len=%d cnt=%d xsize=%d pktcnt=%d\n"</span>,
+<a name="l02192"></a>02192                             &amp;out_ep_regs-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#e756ec48787099f0a4e2ce353fce4f91">doeptsiz</a>, <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a>,
+<a name="l02193"></a>02193                             <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#b882b6b7c857100ed20600e94ea37760">is_in</a> ? <span class="stringliteral">"IN"</span> : <span class="stringliteral">"OUT"</span>,
+<a name="l02194"></a>02194                             <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">xfer_len</a>, <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#23d4871510b5bcb54fbf0674d8f122bd">xfer_count</a>,
+<a name="l02195"></a>02195                             deptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#cf06327d851e7cfe5c442b29bf2d6fa4">xfersize</a>, deptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#bbd89e812371e5b555bb82373f3643d9">pktcnt</a>);
+<a name="l02196"></a>02196         }
+<a name="l02197"></a>02197 
+<a name="l02198"></a>02198         <span class="comment">/* Complete the request */</span>
+<a name="l02199"></a>02199         <span class="keywordflow">if</span> (is_last) {
+<a name="l02200"></a>02200 <span class="preprocessor">#ifdef DWC_UTE_CFI</span>
+<a name="l02201"></a>02201 <span class="preprocessor"></span>                <span class="keywordflow">if</span> (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.buff_mode != BM_STANDARD) {
+<a name="l02202"></a>02202                         req-&gt;<a class="code" href="structdwc__otg__pcd__request.html#0fd7d659f353273d8b2b22027306a2a2">actual</a> = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.cfi_req_len - byte_count;
+<a name="l02203"></a>02203                 } <span class="keywordflow">else</span> {
+<a name="l02204"></a>02204 <span class="preprocessor">#endif</span>
+<a name="l02205"></a>02205 <span class="preprocessor"></span>                req-&gt;<a class="code" href="structdwc__otg__pcd__request.html#0fd7d659f353273d8b2b22027306a2a2">actual</a> = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#23d4871510b5bcb54fbf0674d8f122bd">xfer_count</a>;
+<a name="l02206"></a>02206 <span class="preprocessor">#ifdef DWC_UTE_CFI</span>
+<a name="l02207"></a>02207 <span class="preprocessor"></span>                }
+<a name="l02208"></a>02208 <span class="preprocessor">#endif</span>
+<a name="l02209"></a>02209 <span class="preprocessor"></span>
+<a name="l02210"></a>02210                 <a class="code" href="dwc__otg__pcd_8c.html#5c9b20abc81e0f860a8f23c90b10b59e">dwc_otg_request_done</a>(<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>, req, 0);
+<a name="l02211"></a>02211 
+<a name="l02212"></a>02212                 <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#d0cda8ded2e5142d9a1c9c17efc5812f">start_xfer_buff</a> = 0;
+<a name="l02213"></a>02213                 <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#97fa9bf5c31ba734d54f70e6fe6ae8eb">xfer_buff</a> = 0;
+<a name="l02214"></a>02214                 <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">xfer_len</a> = 0;
+<a name="l02215"></a>02215 
+<a name="l02216"></a>02216                 <span class="comment">/* If there is a request in the queue start it. */</span>
+<a name="l02217"></a>02217                 <a class="code" href="dwc__otg__pcd_8c.html#de7160b7e7b8fd622ba95392513e197c">start_next_request</a>(<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>);
+<a name="l02218"></a>02218         }
+<a name="l02219"></a>02219 }
+<a name="l02220"></a>02220 
+<a name="l02221"></a>02221 <span class="preprocessor">#ifdef DWC_EN_ISOC</span>
+<a name="l02222"></a>02222 <span class="preprocessor"></span>
+<a name="l02227"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#1edc1970063b8383cda91e9d8581f3ac">02227</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd__intr_8c.html#1edc1970063b8383cda91e9d8581f3ac">dwc_otg_pcd_handle_iso_bna</a>(<a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> * <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>)
+<a name="l02228"></a>02228 {
+<a name="l02229"></a>02229         <a class="code" href="structdwc__ep.html">dwc_ep_t</a> *<a class="code" href="structdwc__ep.html">dwc_ep</a> = &amp;<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>;
+<a name="l02230"></a>02230         <span class="keyword">volatile</span> uint32_t *addr;
+<a name="l02231"></a>02231         <a class="code" href="uniondepctl__data.html">depctl_data_t</a> depctl = {.d32 = 0 };
+<a name="l02232"></a>02232         <a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#234391334e48cbd72710d08655c9ed16">pcd</a>;
+<a name="l02233"></a>02233         <a class="code" href="structdwc__otg__dev__dma__desc.html">dwc_otg_dev_dma_desc_t</a> *dma_desc;
+<a name="l02234"></a>02234         <span class="keywordtype">int</span> i;
+<a name="l02235"></a>02235 
+<a name="l02236"></a>02236         dma_desc =
+<a name="l02237"></a>02237             dwc_ep-&gt;<a class="code" href="structdwc__ep.html#a4e11d12099ad64dd5048a3a210fc9f6">iso_desc_addr</a> + dwc_ep-&gt;<a class="code" href="structdwc__ep.html#5e5bfcc93d41670bc0d29ad5f0f35871">desc_cnt</a> * (dwc_ep-&gt;<a class="code" href="structdwc__ep.html#53033f174854701986545f05502e1cad">proc_buf_num</a>);
+<a name="l02238"></a>02238 
+<a name="l02239"></a>02239         <span class="keywordflow">if</span> (dwc_ep-&gt;<a class="code" href="structdwc__ep.html#b882b6b7c857100ed20600e94ea37760">is_in</a>) {
+<a name="l02240"></a>02240                 <a class="code" href="uniondev__dma__desc__sts.html">dev_dma_desc_sts_t</a> sts = {.d32 = 0 };
+<a name="l02241"></a>02241                 <span class="keywordflow">for</span> (i = 0; i &lt; dwc_ep-&gt;<a class="code" href="structdwc__ep.html#5e5bfcc93d41670bc0d29ad5f0f35871">desc_cnt</a>; ++i, ++dma_desc) {
+<a name="l02242"></a>02242                         sts.<a class="code" href="uniondev__dma__desc__sts.html#fb77b9c4ab63304073542ed2b118a64b">d32</a> = dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#fb77b9c4ab63304073542ed2b118a64b">d32</a>;
+<a name="l02243"></a>02243                         sts.<a class="code" href="uniondev__dma__desc__sts.html#324fdd57830243334b74e0579b4e9f96">b_iso_in</a>.<a class="code" href="uniondev__dma__desc__sts.html#05d1c1d8f6c5a1967c51c5d0e2e04261">bs</a> = <a class="code" href="dwc__otg__regs_8h.html#c2cfc53da94087a90d21d3528b005bcf">BS_HOST_READY</a>;
+<a name="l02244"></a>02244                         dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#fb77b9c4ab63304073542ed2b118a64b">d32</a> = sts.<a class="code" href="uniondev__dma__desc__sts.html#fb77b9c4ab63304073542ed2b118a64b">d32</a>;
+<a name="l02245"></a>02245                 }
+<a name="l02246"></a>02246         } <span class="keywordflow">else</span> {
+<a name="l02247"></a>02247                 <a class="code" href="uniondev__dma__desc__sts.html">dev_dma_desc_sts_t</a> sts = {.d32 = 0 };
+<a name="l02248"></a>02248                 <span class="keywordflow">for</span> (i = 0; i &lt; dwc_ep-&gt;<a class="code" href="structdwc__ep.html#5e5bfcc93d41670bc0d29ad5f0f35871">desc_cnt</a>; ++i, ++dma_desc) {
+<a name="l02249"></a>02249                         sts.<a class="code" href="uniondev__dma__desc__sts.html#fb77b9c4ab63304073542ed2b118a64b">d32</a> = dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#fb77b9c4ab63304073542ed2b118a64b">d32</a>;
+<a name="l02250"></a>02250                         sts.<a class="code" href="uniondev__dma__desc__sts.html#214ba099b6077c3393b179cf9a7909f7">b_iso_out</a>.<a class="code" href="uniondev__dma__desc__sts.html#05d1c1d8f6c5a1967c51c5d0e2e04261">bs</a> = <a class="code" href="dwc__otg__regs_8h.html#c2cfc53da94087a90d21d3528b005bcf">BS_HOST_READY</a>;
+<a name="l02251"></a>02251                         dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#fb77b9c4ab63304073542ed2b118a64b">d32</a> = sts.<a class="code" href="uniondev__dma__desc__sts.html#fb77b9c4ab63304073542ed2b118a64b">d32</a>;
+<a name="l02252"></a>02252                 }
+<a name="l02253"></a>02253         }
+<a name="l02254"></a>02254 
+<a name="l02255"></a>02255         <span class="keywordflow">if</span> (dwc_ep-&gt;<a class="code" href="structdwc__ep.html#b882b6b7c857100ed20600e94ea37760">is_in</a> == 0) {
+<a name="l02256"></a>02256                 addr =
+<a name="l02257"></a>02257                     &amp;<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;dev_if-&gt;out_ep_regs[dwc_ep-&gt;<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a>]-&gt;
+<a name="l02258"></a>02258                     doepctl;
+<a name="l02259"></a>02259         } <span class="keywordflow">else</span> {
+<a name="l02260"></a>02260                 addr =
+<a name="l02261"></a>02261                     &amp;<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;dev_if-&gt;in_ep_regs[<a class="code" href="structdwc__ep.html">dwc_ep</a>-&gt;num]-&gt;diepctl;
+<a name="l02262"></a>02262         }
+<a name="l02263"></a>02263         depctl.b.epena = 1;
+<a name="l02264"></a>02264         dwc_modify_reg32(addr, depctl.d32, depctl.d32);
+<a name="l02265"></a>02265 }
+<a name="l02266"></a>02266 
+<a name="l02274"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#17428b2360118cc59ab9d5cbcef8a14b">02274</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd__intr_8c.html#17428b2360118cc59ab9d5cbcef8a14b">set_current_pkt_info</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, <a class="code" href="structdwc__ep.html">dwc_ep_t</a> * <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>)
+<a name="l02275"></a>02275 {
+<a name="l02276"></a>02276         <a class="code" href="uniondeptsiz__data.html">deptsiz_data_t</a> deptsiz = {.d32 = 0 };
+<a name="l02277"></a>02277         dma_addr_t dma_addr;
+<a name="l02278"></a>02278         uint32_t offset;
+<a name="l02279"></a>02279 
+<a name="l02280"></a>02280         <span class="keywordflow">if</span> (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;proc_buf_num)
+<a name="l02281"></a>02281                 dma_addr = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;dma_addr1;
+<a name="l02282"></a>02282         <span class="keywordflow">else</span>
+<a name="l02283"></a>02283                 dma_addr = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;dma_addr0;
+<a name="l02284"></a>02284 
+<a name="l02285"></a>02285         <span class="keywordflow">if</span> (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;is_in) {
+<a name="l02286"></a>02286                 deptsiz.<a class="code" href="uniondeptsiz__data.html#10c2b2ba8b419b0a766430a59befbbe0">d32</a> =
+<a name="l02287"></a>02287                     dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;num]-&gt;
+<a name="l02288"></a>02288                                    dieptsiz);
+<a name="l02289"></a>02289                 offset = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;data_per_frame;
+<a name="l02290"></a>02290         } <span class="keywordflow">else</span> {
+<a name="l02291"></a>02291                 deptsiz.<a class="code" href="uniondeptsiz__data.html#10c2b2ba8b419b0a766430a59befbbe0">d32</a> =
+<a name="l02292"></a>02292                     dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">out_ep_regs</a>[<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;num]-&gt;
+<a name="l02293"></a>02293                                    doeptsiz);
+<a name="l02294"></a>02294                 offset =
+<a name="l02295"></a>02295                     <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;data_per_frame +
+<a name="l02296"></a>02296                     (0x4 &amp; (0x4 - (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;data_per_frame &amp; 0x3)));
+<a name="l02297"></a>02297         }
+<a name="l02298"></a>02298 
+<a name="l02299"></a>02299         <span class="keywordflow">if</span> (!deptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#cf06327d851e7cfe5c442b29bf2d6fa4">xfersize</a>) {
+<a name="l02300"></a>02300                 <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;pkt_info[<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;cur_pkt].length = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;data_per_frame;
+<a name="l02301"></a>02301                 <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;pkt_info[<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;cur_pkt].offset =
+<a name="l02302"></a>02302                     <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;cur_pkt_dma_addr - dma_addr;
+<a name="l02303"></a>02303                 <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;pkt_info[<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;cur_pkt].status = 0;
+<a name="l02304"></a>02304         } <span class="keywordflow">else</span> {
+<a name="l02305"></a>02305                 <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;pkt_info[<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;cur_pkt].length = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;data_per_frame;
+<a name="l02306"></a>02306                 <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;pkt_info[<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;cur_pkt].offset =
+<a name="l02307"></a>02307                     <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;cur_pkt_dma_addr - dma_addr;
+<a name="l02308"></a>02308                 <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;pkt_info[<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;cur_pkt].status = -DWC_E_NO_DATA;
+<a name="l02309"></a>02309         }
+<a name="l02310"></a>02310         <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;cur_pkt_addr += offset;
+<a name="l02311"></a>02311         <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;cur_pkt_dma_addr += offset;
+<a name="l02312"></a>02312         <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;cur_pkt++;
+<a name="l02313"></a>02313 }
+<a name="l02314"></a>02314 
+<a name="l02322"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#e5ed26b3ab2380cb92773df1720ec752">02322</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd__intr_8c.html#e5ed26b3ab2380cb92773df1720ec752">set_ddma_iso_pkts_info</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if,
+<a name="l02323"></a>02323                                    <a class="code" href="structdwc__ep.html">dwc_ep_t</a> * <a class="code" href="structdwc__ep.html">dwc_ep</a>)
+<a name="l02324"></a>02324 {
+<a name="l02325"></a>02325         <a class="code" href="structdwc__otg__dev__dma__desc.html">dwc_otg_dev_dma_desc_t</a> *dma_desc;
+<a name="l02326"></a>02326         <a class="code" href="uniondev__dma__desc__sts.html">dev_dma_desc_sts_t</a> sts = {.d32 = 0 };
+<a name="l02327"></a>02327         <a class="code" href="structiso__pkt__info.html">iso_pkt_info_t</a> *iso_packet;
+<a name="l02328"></a>02328         uint32_t data_per_desc;
+<a name="l02329"></a>02329         uint32_t offset;
+<a name="l02330"></a>02330         <span class="keywordtype">int</span> i, j;
+<a name="l02331"></a>02331 
+<a name="l02332"></a>02332         iso_packet = dwc_ep-&gt;<a class="code" href="structdwc__ep.html#a8ed15a24123a2dad6861da7d61dfb48">pkt_info</a>;
+<a name="l02333"></a>02333 
+<a name="l02336"></a>02336         <span class="keywordflow">if</span> (dwc_ep-&gt;<a class="code" href="structdwc__ep.html#b882b6b7c857100ed20600e94ea37760">is_in</a> == 0) {
+<a name="l02337"></a>02337                 dma_desc =
+<a name="l02338"></a>02338                     dwc_ep-&gt;<a class="code" href="structdwc__ep.html#a4e11d12099ad64dd5048a3a210fc9f6">iso_desc_addr</a> +
+<a name="l02339"></a>02339                     dwc_ep-&gt;<a class="code" href="structdwc__ep.html#5e5bfcc93d41670bc0d29ad5f0f35871">desc_cnt</a> * dwc_ep-&gt;<a class="code" href="structdwc__ep.html#53033f174854701986545f05502e1cad">proc_buf_num</a>;
+<a name="l02340"></a>02340                 offset = 0;
+<a name="l02341"></a>02341 
+<a name="l02342"></a>02342                 <span class="keywordflow">for</span> (i = 0; i &lt; dwc_ep-&gt;<a class="code" href="structdwc__ep.html#5e5bfcc93d41670bc0d29ad5f0f35871">desc_cnt</a> - dwc_ep-&gt;<a class="code" href="structdwc__ep.html#fe51420474de8a9d74fc9c4adc811c4b">pkt_per_frm</a>;
+<a name="l02343"></a>02343                      i += dwc_ep-&gt;<a class="code" href="structdwc__ep.html#fe51420474de8a9d74fc9c4adc811c4b">pkt_per_frm</a>) {
+<a name="l02344"></a>02344                         <span class="keywordflow">for</span> (j = 0; j &lt; dwc_ep-&gt;<a class="code" href="structdwc__ep.html#fe51420474de8a9d74fc9c4adc811c4b">pkt_per_frm</a>; ++j) {
+<a name="l02345"></a>02345                                 data_per_desc =
+<a name="l02346"></a>02346                                     ((j + 1) * dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a> &gt;
+<a name="l02347"></a>02347                                      dwc_ep-&gt;<a class="code" href="structdwc__ep.html#4672369f4724db642856d72d5048213e">data_per_frame</a>) ? dwc_ep-&gt;
+<a name="l02348"></a>02348                                     data_per_frame -
+<a name="l02349"></a>02349                                     j * dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a> : dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a>;
+<a name="l02350"></a>02350                                 data_per_desc +=
+<a name="l02351"></a>02351                                     (data_per_desc % 4) ? (4 -
+<a name="l02352"></a>02352                                                            data_per_desc %
+<a name="l02353"></a>02353                                                            4) : 0;
+<a name="l02354"></a>02354 
+<a name="l02355"></a>02355                                 sts.<a class="code" href="uniondev__dma__desc__sts.html#fb77b9c4ab63304073542ed2b118a64b">d32</a> = dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#fb77b9c4ab63304073542ed2b118a64b">d32</a>;
+<a name="l02356"></a>02356 
+<a name="l02357"></a>02357                                 <span class="comment">/* Write status in iso_packet_decsriptor  */</span>
+<a name="l02358"></a>02358                                 iso_packet-&gt;<a class="code" href="structiso__pkt__info.html#1317c3b425c0ef55dbde153b04c28dd4">status</a> =
+<a name="l02359"></a>02359                                     sts.<a class="code" href="uniondev__dma__desc__sts.html#214ba099b6077c3393b179cf9a7909f7">b_iso_out</a>.<a class="code" href="uniondev__dma__desc__sts.html#a80809cda5b19b3e36f512effef795f0">rxsts</a> +
+<a name="l02360"></a>02360                                     (sts.<a class="code" href="uniondev__dma__desc__sts.html#214ba099b6077c3393b179cf9a7909f7">b_iso_out</a>.<a class="code" href="uniondev__dma__desc__sts.html#05d1c1d8f6c5a1967c51c5d0e2e04261">bs</a> ^ <a class="code" href="dwc__otg__regs_8h.html#b20f6432003d81072ed8b7cd66d6305b">BS_DMA_DONE</a>);
+<a name="l02361"></a>02361                                 if (iso_packet-&gt;<a class="code" href="structiso__pkt__info.html#1317c3b425c0ef55dbde153b04c28dd4">status</a>) {
+<a name="l02362"></a>02362                                         iso_packet-&gt;<a class="code" href="structiso__pkt__info.html#1317c3b425c0ef55dbde153b04c28dd4">status</a> = -DWC_E_NO_DATA;
+<a name="l02363"></a>02363                                 }
+<a name="l02364"></a>02364 
+<a name="l02365"></a>02365                                 <span class="comment">/* Received data length */</span>
+<a name="l02366"></a>02366                                 <span class="keywordflow">if</span> (!sts.<a class="code" href="uniondev__dma__desc__sts.html#214ba099b6077c3393b179cf9a7909f7">b_iso_out</a>.<a class="code" href="uniondev__dma__desc__sts.html#ede78801cd7bc514474fcbe1ef154e5a">rxbytes</a>) {
+<a name="l02367"></a>02367                                         iso_packet-&gt;<a class="code" href="structiso__pkt__info.html#ced82142e81778345016841e15020eb8">length</a> =
+<a name="l02368"></a>02368                                             data_per_desc -
+<a name="l02369"></a>02369                                             sts.<a class="code" href="uniondev__dma__desc__sts.html#214ba099b6077c3393b179cf9a7909f7">b_iso_out</a>.<a class="code" href="uniondev__dma__desc__sts.html#ede78801cd7bc514474fcbe1ef154e5a">rxbytes</a>;
+<a name="l02370"></a>02370                                 } <span class="keywordflow">else</span> {
+<a name="l02371"></a>02371                                         iso_packet-&gt;<a class="code" href="structiso__pkt__info.html#ced82142e81778345016841e15020eb8">length</a> =
+<a name="l02372"></a>02372                                             data_per_desc -
+<a name="l02373"></a>02373                                             sts.<a class="code" href="uniondev__dma__desc__sts.html#214ba099b6077c3393b179cf9a7909f7">b_iso_out</a>.<a class="code" href="uniondev__dma__desc__sts.html#ede78801cd7bc514474fcbe1ef154e5a">rxbytes</a> + (4 -
+<a name="l02374"></a>02374                                                                      dwc_ep-&gt;
+<a name="l02375"></a>02375                                                                      data_per_frame
+<a name="l02376"></a>02376                                                                      % 4);
+<a name="l02377"></a>02377                                 }
+<a name="l02378"></a>02378 
+<a name="l02379"></a>02379                                 iso_packet-&gt;<a class="code" href="structiso__pkt__info.html#0c72a0585ccc93555da4db7e168f75f8">offset</a> = offset;
+<a name="l02380"></a>02380 
+<a name="l02381"></a>02381                                 offset += data_per_desc;
+<a name="l02382"></a>02382                                 dma_desc++;
+<a name="l02383"></a>02383                                 iso_packet++;
+<a name="l02384"></a>02384                         }
+<a name="l02385"></a>02385                 }
+<a name="l02386"></a>02386 
+<a name="l02387"></a>02387                 <span class="keywordflow">for</span> (j = 0; j &lt; <a class="code" href="structdwc__ep.html">dwc_ep</a>-&gt;pkt_per_frm - 1; ++j) {
+<a name="l02388"></a>02388                         data_per_desc =
+<a name="l02389"></a>02389                             ((j + 1) * <a class="code" href="structdwc__ep.html">dwc_ep</a>-&gt;maxpacket &gt;
+<a name="l02390"></a>02390                              <a class="code" href="structdwc__ep.html">dwc_ep</a>-&gt;data_per_frame) ? <a class="code" href="structdwc__ep.html">dwc_ep</a>-&gt;data_per_frame -
+<a name="l02391"></a>02391                             j * <a class="code" href="structdwc__ep.html">dwc_ep</a>-&gt;maxpacket : <a class="code" href="structdwc__ep.html">dwc_ep</a>-&gt;maxpacket;
+<a name="l02392"></a>02392                         data_per_desc +=
+<a name="l02393"></a>02393                             (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
+<a name="l02394"></a>02394 
+<a name="l02395"></a>02395                         sts.d32 = dma_desc-&gt;<a class="code" href="structiso__pkt__info.html#1317c3b425c0ef55dbde153b04c28dd4">status</a>.d32;
+<a name="l02396"></a>02396 
+<a name="l02397"></a>02397                         <span class="comment">/* Write status in iso_packet_decsriptor  */</span>
+<a name="l02398"></a>02398                         iso_packet-&gt;status =
+<a name="l02399"></a>02399                             sts.b_iso_out.rxsts +
+<a name="l02400"></a>02400                             (sts.b_iso_out.bs ^ <a class="code" href="dwc__otg__regs_8h.html#b20f6432003d81072ed8b7cd66d6305b">BS_DMA_DONE</a>);
+<a name="l02401"></a>02401                         if (iso_packet-&gt;status) {
+<a name="l02402"></a>02402                                 iso_packet-&gt;status = -DWC_E_NO_DATA;
+<a name="l02403"></a>02403                         }
+<a name="l02404"></a>02404 
+<a name="l02405"></a>02405                         <span class="comment">/* Received data length */</span>
+<a name="l02406"></a>02406                         iso_packet-&gt;length =
+<a name="l02407"></a>02407                             <a class="code" href="structdwc__ep.html">dwc_ep</a>-&gt;data_per_frame - sts.b_iso_out.rxbytes;
+<a name="l02408"></a>02408 
+<a name="l02409"></a>02409                         iso_packet-&gt;offset = offset;
+<a name="l02410"></a>02410 
+<a name="l02411"></a>02411                         offset += data_per_desc;
+<a name="l02412"></a>02412                         iso_packet++;
+<a name="l02413"></a>02413                         dma_desc++;
+<a name="l02414"></a>02414                 }
+<a name="l02415"></a>02415 
+<a name="l02416"></a>02416                 sts.d32 = dma_desc-&gt;status.d32;
+<a name="l02417"></a>02417 
+<a name="l02418"></a>02418                 <span class="comment">/* Write status in iso_packet_decsriptor  */</span>
+<a name="l02419"></a>02419                 iso_packet-&gt;status =
+<a name="l02420"></a>02420                     sts.b_iso_out.rxsts + (sts.b_iso_out.bs ^ <a class="code" href="dwc__otg__regs_8h.html#b20f6432003d81072ed8b7cd66d6305b">BS_DMA_DONE</a>);
+<a name="l02421"></a>02421                 <span class="keywordflow">if</span> (iso_packet-&gt;status) {
+<a name="l02422"></a>02422                         iso_packet-&gt;status = -DWC_E_NO_DATA;
+<a name="l02423"></a>02423                 }
+<a name="l02424"></a>02424                 <span class="comment">/* Received data length */</span>
+<a name="l02425"></a>02425                 <span class="keywordflow">if</span> (!sts.b_iso_out.rxbytes) {
+<a name="l02426"></a>02426                         iso_packet-&gt;length =
+<a name="l02427"></a>02427                             <a class="code" href="structdwc__ep.html">dwc_ep</a>-&gt;data_per_frame - sts.b_iso_out.rxbytes;
+<a name="l02428"></a>02428                 } <span class="keywordflow">else</span> {
+<a name="l02429"></a>02429                         iso_packet-&gt;length =
+<a name="l02430"></a>02430                             <a class="code" href="structdwc__ep.html">dwc_ep</a>-&gt;data_per_frame - sts.b_iso_out.rxbytes +
+<a name="l02431"></a>02431                             (4 - <a class="code" href="structdwc__ep.html">dwc_ep</a>-&gt;data_per_frame % 4);
+<a name="l02432"></a>02432                 }
+<a name="l02433"></a>02433 
+<a name="l02434"></a>02434                 iso_packet-&gt;offset = offset;
+<a name="l02435"></a>02435         } <span class="keywordflow">else</span> {
+<a name="l02438"></a>02438                 dma_desc =
+<a name="l02439"></a>02439                     <a class="code" href="structdwc__ep.html">dwc_ep</a>-&gt;iso_desc_addr +
+<a name="l02440"></a>02440                     <a class="code" href="structdwc__ep.html">dwc_ep</a>-&gt;desc_cnt * <a class="code" href="structdwc__ep.html">dwc_ep</a>-&gt;proc_buf_num;
+<a name="l02441"></a>02441 
+<a name="l02442"></a>02442                 <span class="keywordflow">for</span> (i = 0; i &lt; <a class="code" href="structdwc__ep.html">dwc_ep</a>-&gt;desc_cnt - 1; i++) {
+<a name="l02443"></a>02443                         sts.d32 = dma_desc-&gt;status.d32;
+<a name="l02444"></a>02444 
+<a name="l02445"></a>02445                         <span class="comment">/* Write status in iso packet descriptor */</span>
+<a name="l02446"></a>02446                         iso_packet-&gt;status =
+<a name="l02447"></a>02447                             sts.b_iso_in.txsts +
+<a name="l02448"></a>02448                             (sts.b_iso_in.bs ^ <a class="code" href="dwc__otg__regs_8h.html#b20f6432003d81072ed8b7cd66d6305b">BS_DMA_DONE</a>);
+<a name="l02449"></a>02449                         if (iso_packet-&gt;status != 0) {
+<a name="l02450"></a>02450                                 iso_packet-&gt;status = -DWC_E_NO_DATA;
+<a name="l02451"></a>02451 
+<a name="l02452"></a>02452                         }
+<a name="l02453"></a>02453                         <span class="comment">/* Bytes has been transfered */</span>
+<a name="l02454"></a>02454                         iso_packet-&gt;length =
+<a name="l02455"></a>02455                             <a class="code" href="structdwc__ep.html">dwc_ep</a>-&gt;data_per_frame - sts.b_iso_in.txbytes;
+<a name="l02456"></a>02456 
+<a name="l02457"></a>02457                         dma_desc++;
+<a name="l02458"></a>02458                         iso_packet++;
+<a name="l02459"></a>02459                 }
+<a name="l02460"></a>02460 
+<a name="l02461"></a>02461                 sts.d32 = dma_desc-&gt;status.d32;
+<a name="l02462"></a>02462                 <span class="keywordflow">while</span> (sts.b_iso_in.bs == <a class="code" href="dwc__otg__regs_8h.html#3110b1318d89fe11ee69f3ccbe219c4e">BS_DMA_BUSY</a>) {
+<a name="l02463"></a>02463                         sts.d32 = dma_desc-&gt;status.d32;
+<a name="l02464"></a>02464                 }
+<a name="l02465"></a>02465 
+<a name="l02466"></a>02466                 <span class="comment">/* Write status in iso packet descriptor ??? do be done with ERROR codes */</span>
+<a name="l02467"></a>02467                 iso_packet-&gt;status =
+<a name="l02468"></a>02468                     sts.b_iso_in.txsts + (sts.b_iso_in.bs ^ <a class="code" href="dwc__otg__regs_8h.html#b20f6432003d81072ed8b7cd66d6305b">BS_DMA_DONE</a>);
+<a name="l02469"></a>02469                 <span class="keywordflow">if</span> (iso_packet-&gt;status != 0) {
+<a name="l02470"></a>02470                         iso_packet-&gt;status = -DWC_E_NO_DATA;
+<a name="l02471"></a>02471                 }
+<a name="l02472"></a>02472 
+<a name="l02473"></a>02473                 <span class="comment">/* Bytes has been transfered */</span>
+<a name="l02474"></a>02474                 iso_packet-&gt;length =
+<a name="l02475"></a>02475                     <a class="code" href="structdwc__ep.html">dwc_ep</a>-&gt;data_per_frame - sts.b_iso_in.txbytes;
+<a name="l02476"></a>02476         }
+<a name="l02477"></a>02477 }
+<a name="l02478"></a>02478 
+<a name="l02486"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#c3f6fb3131e0786ec75a9c4a29fea297">02486</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd__intr_8c.html#c3f6fb3131e0786ec75a9c4a29fea297">reinit_ddma_iso_xfer</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, <a class="code" href="structdwc__ep.html">dwc_ep_t</a> * <a class="code" href="structdwc__ep.html">dwc_ep</a>)
+<a name="l02487"></a>02487 {
+<a name="l02488"></a>02488         <span class="keywordtype">int</span> i, j;
+<a name="l02489"></a>02489         <a class="code" href="structdwc__otg__dev__dma__desc.html">dwc_otg_dev_dma_desc_t</a> *dma_desc;
+<a name="l02490"></a>02490         dma_addr_t dma_ad;
+<a name="l02491"></a>02491         <span class="keyword">volatile</span> uint32_t *addr;
+<a name="l02492"></a>02492         <a class="code" href="uniondev__dma__desc__sts.html">dev_dma_desc_sts_t</a> sts = {.d32 = 0 };
+<a name="l02493"></a>02493         uint32_t data_per_desc;
+<a name="l02494"></a>02494 
+<a name="l02495"></a>02495         <span class="keywordflow">if</span> (dwc_ep-&gt;<a class="code" href="structdwc__ep.html#b882b6b7c857100ed20600e94ea37760">is_in</a> == 0) {
+<a name="l02496"></a>02496                 addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">out_ep_regs</a>[dwc_ep-&gt;<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a>]-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#2a522b71fc97658c07debf3521f7d3e5">doepctl</a>;
+<a name="l02497"></a>02497         } <span class="keywordflow">else</span> {
+<a name="l02498"></a>02498                 addr = &amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[dwc_ep-&gt;<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a>]-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#53a5adb977e2aec66d4902c6ba293216">diepctl</a>;
+<a name="l02499"></a>02499         }
+<a name="l02500"></a>02500 
+<a name="l02501"></a>02501         <span class="keywordflow">if</span> (dwc_ep-&gt;<a class="code" href="structdwc__ep.html#53033f174854701986545f05502e1cad">proc_buf_num</a> == 0) {
+<a name="l02503"></a>02503                 dma_ad = dwc_ep-&gt;<a class="code" href="structdwc__ep.html#553936d1d003413d00a24330274887f9">dma_addr0</a>;
+<a name="l02504"></a>02504         } <span class="keywordflow">else</span> {
+<a name="l02506"></a>02506                 dma_ad = dwc_ep-&gt;<a class="code" href="structdwc__ep.html#02dc1be77d505b19f14651fe9805c97f">dma_addr1</a>;
+<a name="l02507"></a>02507         }
+<a name="l02508"></a>02508 
+<a name="l02511"></a>02511         <span class="keywordflow">if</span> (dwc_ep-&gt;<a class="code" href="structdwc__ep.html#b882b6b7c857100ed20600e94ea37760">is_in</a> == 0) {
+<a name="l02512"></a>02512                 dma_desc =
+<a name="l02513"></a>02513                     dwc_ep-&gt;<a class="code" href="structdwc__ep.html#a4e11d12099ad64dd5048a3a210fc9f6">iso_desc_addr</a> +
+<a name="l02514"></a>02514                     dwc_ep-&gt;<a class="code" href="structdwc__ep.html#5e5bfcc93d41670bc0d29ad5f0f35871">desc_cnt</a> * dwc_ep-&gt;<a class="code" href="structdwc__ep.html#53033f174854701986545f05502e1cad">proc_buf_num</a>;
+<a name="l02515"></a>02515 
+<a name="l02516"></a>02516                 sts.<a class="code" href="uniondev__dma__desc__sts.html#214ba099b6077c3393b179cf9a7909f7">b_iso_out</a>.<a class="code" href="uniondev__dma__desc__sts.html#05d1c1d8f6c5a1967c51c5d0e2e04261">bs</a> = <a class="code" href="dwc__otg__regs_8h.html#c2cfc53da94087a90d21d3528b005bcf">BS_HOST_READY</a>;
+<a name="l02517"></a>02517                 sts.<a class="code" href="uniondev__dma__desc__sts.html#214ba099b6077c3393b179cf9a7909f7">b_iso_out</a>.<a class="code" href="uniondev__dma__desc__sts.html#a80809cda5b19b3e36f512effef795f0">rxsts</a> = 0;
+<a name="l02518"></a>02518                 sts.<a class="code" href="uniondev__dma__desc__sts.html#214ba099b6077c3393b179cf9a7909f7">b_iso_out</a>.<a class="code" href="uniondev__dma__desc__sts.html#b728a79d6a86a0d1b6426a1b2627f2c2">l</a> = 0;
+<a name="l02519"></a>02519                 sts.<a class="code" href="uniondev__dma__desc__sts.html#214ba099b6077c3393b179cf9a7909f7">b_iso_out</a>.<a class="code" href="uniondev__dma__desc__sts.html#a850ddfa13601227c05e0ae43a538a9d">sp</a> = 0;
+<a name="l02520"></a>02520                 sts.<a class="code" href="uniondev__dma__desc__sts.html#214ba099b6077c3393b179cf9a7909f7">b_iso_out</a>.<a class="code" href="uniondev__dma__desc__sts.html#02c8be72ef6258c25094478c7cac0b12">ioc</a> = 0;
+<a name="l02521"></a>02521                 sts.<a class="code" href="uniondev__dma__desc__sts.html#214ba099b6077c3393b179cf9a7909f7">b_iso_out</a>.<a class="code" href="uniondev__dma__desc__sts.html#79bf5fe6d9949ddb671daa14b5ee298e">pid</a> = 0;
+<a name="l02522"></a>02522                 sts.<a class="code" href="uniondev__dma__desc__sts.html#214ba099b6077c3393b179cf9a7909f7">b_iso_out</a>.<a class="code" href="uniondev__dma__desc__sts.html#d9da3eccc6d247e2b5eccd4dfba7874e">framenum</a> = 0;
+<a name="l02523"></a>02523 
+<a name="l02524"></a>02524                 <span class="keywordflow">for</span> (i = 0; i &lt; dwc_ep-&gt;<a class="code" href="structdwc__ep.html#5e5bfcc93d41670bc0d29ad5f0f35871">desc_cnt</a> - dwc_ep-&gt;<a class="code" href="structdwc__ep.html#fe51420474de8a9d74fc9c4adc811c4b">pkt_per_frm</a>;
+<a name="l02525"></a>02525                      i += dwc_ep-&gt;<a class="code" href="structdwc__ep.html#fe51420474de8a9d74fc9c4adc811c4b">pkt_per_frm</a>) {
+<a name="l02526"></a>02526                         <span class="keywordflow">for</span> (j = 0; j &lt; dwc_ep-&gt;<a class="code" href="structdwc__ep.html#fe51420474de8a9d74fc9c4adc811c4b">pkt_per_frm</a>; ++j) {
+<a name="l02527"></a>02527                                 data_per_desc =
+<a name="l02528"></a>02528                                     ((j + 1) * dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a> &gt;
+<a name="l02529"></a>02529                                      dwc_ep-&gt;<a class="code" href="structdwc__ep.html#4672369f4724db642856d72d5048213e">data_per_frame</a>) ? dwc_ep-&gt;
+<a name="l02530"></a>02530                                     data_per_frame -
+<a name="l02531"></a>02531                                     j * dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a> : dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a>;
+<a name="l02532"></a>02532                                 data_per_desc +=
+<a name="l02533"></a>02533                                     (data_per_desc % 4) ? (4 -
+<a name="l02534"></a>02534                                                            data_per_desc %
+<a name="l02535"></a>02535                                                            4) : 0;
+<a name="l02536"></a>02536                                 sts.<a class="code" href="uniondev__dma__desc__sts.html#214ba099b6077c3393b179cf9a7909f7">b_iso_out</a>.<a class="code" href="uniondev__dma__desc__sts.html#ede78801cd7bc514474fcbe1ef154e5a">rxbytes</a> = data_per_desc;
+<a name="l02537"></a>02537                                 dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#0454dad420ef536fe5eb7c38ef764430">buf</a> = dma_ad;
+<a name="l02538"></a>02538                                 dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#fb77b9c4ab63304073542ed2b118a64b">d32</a> = sts.<a class="code" href="uniondev__dma__desc__sts.html#fb77b9c4ab63304073542ed2b118a64b">d32</a>;
+<a name="l02539"></a>02539 
+<a name="l02540"></a>02540                                 dma_ad += data_per_desc;
+<a name="l02541"></a>02541                                 dma_desc++;
+<a name="l02542"></a>02542                         }
+<a name="l02543"></a>02543                 }
+<a name="l02544"></a>02544 
+<a name="l02545"></a>02545                 <span class="keywordflow">for</span> (j = 0; j &lt; dwc_ep-&gt;<a class="code" href="structdwc__ep.html#fe51420474de8a9d74fc9c4adc811c4b">pkt_per_frm</a> - 1; ++j) {
+<a name="l02546"></a>02546 
+<a name="l02547"></a>02547                         data_per_desc =
+<a name="l02548"></a>02548                             ((j + 1) * dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a> &gt;
+<a name="l02549"></a>02549                              dwc_ep-&gt;<a class="code" href="structdwc__ep.html#4672369f4724db642856d72d5048213e">data_per_frame</a>) ? dwc_ep-&gt;<a class="code" href="structdwc__ep.html#4672369f4724db642856d72d5048213e">data_per_frame</a> -
+<a name="l02550"></a>02550                             j * dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a> : dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a>;
+<a name="l02551"></a>02551                         data_per_desc +=
+<a name="l02552"></a>02552                             (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
+<a name="l02553"></a>02553                         sts.<a class="code" href="uniondev__dma__desc__sts.html#214ba099b6077c3393b179cf9a7909f7">b_iso_out</a>.<a class="code" href="uniondev__dma__desc__sts.html#ede78801cd7bc514474fcbe1ef154e5a">rxbytes</a> = data_per_desc;
+<a name="l02554"></a>02554 
+<a name="l02555"></a>02555                         dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#0454dad420ef536fe5eb7c38ef764430">buf</a> = dma_ad;
+<a name="l02556"></a>02556                         dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#fb77b9c4ab63304073542ed2b118a64b">d32</a> = sts.<a class="code" href="uniondev__dma__desc__sts.html#fb77b9c4ab63304073542ed2b118a64b">d32</a>;
+<a name="l02557"></a>02557 
+<a name="l02558"></a>02558                         dma_desc++;
+<a name="l02559"></a>02559                         dma_ad += data_per_desc;
+<a name="l02560"></a>02560                 }
+<a name="l02561"></a>02561 
+<a name="l02562"></a>02562                 sts.<a class="code" href="uniondev__dma__desc__sts.html#214ba099b6077c3393b179cf9a7909f7">b_iso_out</a>.<a class="code" href="uniondev__dma__desc__sts.html#02c8be72ef6258c25094478c7cac0b12">ioc</a> = 1;
+<a name="l02563"></a>02563                 sts.<a class="code" href="uniondev__dma__desc__sts.html#214ba099b6077c3393b179cf9a7909f7">b_iso_out</a>.<a class="code" href="uniondev__dma__desc__sts.html#b728a79d6a86a0d1b6426a1b2627f2c2">l</a> = dwc_ep-&gt;<a class="code" href="structdwc__ep.html#53033f174854701986545f05502e1cad">proc_buf_num</a>;
+<a name="l02564"></a>02564 
+<a name="l02565"></a>02565                 data_per_desc =
+<a name="l02566"></a>02566                     ((j + 1) * dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a> &gt;
+<a name="l02567"></a>02567                      dwc_ep-&gt;<a class="code" href="structdwc__ep.html#4672369f4724db642856d72d5048213e">data_per_frame</a>) ? dwc_ep-&gt;<a class="code" href="structdwc__ep.html#4672369f4724db642856d72d5048213e">data_per_frame</a> -
+<a name="l02568"></a>02568                     j * dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a> : dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a>;
+<a name="l02569"></a>02569                 data_per_desc +=
+<a name="l02570"></a>02570                     (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
+<a name="l02571"></a>02571                 sts.<a class="code" href="uniondev__dma__desc__sts.html#214ba099b6077c3393b179cf9a7909f7">b_iso_out</a>.<a class="code" href="uniondev__dma__desc__sts.html#ede78801cd7bc514474fcbe1ef154e5a">rxbytes</a> = data_per_desc;
+<a name="l02572"></a>02572 
+<a name="l02573"></a>02573                 dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#0454dad420ef536fe5eb7c38ef764430">buf</a> = dma_ad;
+<a name="l02574"></a>02574                 dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#fb77b9c4ab63304073542ed2b118a64b">d32</a> = sts.<a class="code" href="uniondev__dma__desc__sts.html#fb77b9c4ab63304073542ed2b118a64b">d32</a>;
+<a name="l02575"></a>02575         } <span class="keywordflow">else</span> {
+<a name="l02578"></a>02578                 dma_desc =
+<a name="l02579"></a>02579                     dwc_ep-&gt;<a class="code" href="structdwc__ep.html#a4e11d12099ad64dd5048a3a210fc9f6">iso_desc_addr</a> +
+<a name="l02580"></a>02580                     dwc_ep-&gt;<a class="code" href="structdwc__ep.html#5e5bfcc93d41670bc0d29ad5f0f35871">desc_cnt</a> * dwc_ep-&gt;<a class="code" href="structdwc__ep.html#53033f174854701986545f05502e1cad">proc_buf_num</a>;
+<a name="l02581"></a>02581 
+<a name="l02582"></a>02582                 sts.<a class="code" href="uniondev__dma__desc__sts.html#324fdd57830243334b74e0579b4e9f96">b_iso_in</a>.<a class="code" href="uniondev__dma__desc__sts.html#05d1c1d8f6c5a1967c51c5d0e2e04261">bs</a> = <a class="code" href="dwc__otg__regs_8h.html#c2cfc53da94087a90d21d3528b005bcf">BS_HOST_READY</a>;
+<a name="l02583"></a>02583                 sts.<a class="code" href="uniondev__dma__desc__sts.html#324fdd57830243334b74e0579b4e9f96">b_iso_in</a>.<a class="code" href="uniondev__dma__desc__sts.html#30ebc024572822f0803d28c95914a44c">txsts</a> = 0;
+<a name="l02584"></a>02584                 sts.<a class="code" href="uniondev__dma__desc__sts.html#324fdd57830243334b74e0579b4e9f96">b_iso_in</a>.<a class="code" href="uniondev__dma__desc__sts.html#a850ddfa13601227c05e0ae43a538a9d">sp</a> = 0;
+<a name="l02585"></a>02585                 sts.<a class="code" href="uniondev__dma__desc__sts.html#324fdd57830243334b74e0579b4e9f96">b_iso_in</a>.<a class="code" href="uniondev__dma__desc__sts.html#02c8be72ef6258c25094478c7cac0b12">ioc</a> = 0;
+<a name="l02586"></a>02586                 sts.<a class="code" href="uniondev__dma__desc__sts.html#324fdd57830243334b74e0579b4e9f96">b_iso_in</a>.<a class="code" href="uniondev__dma__desc__sts.html#79bf5fe6d9949ddb671daa14b5ee298e">pid</a> = dwc_ep-&gt;<a class="code" href="structdwc__ep.html#fe51420474de8a9d74fc9c4adc811c4b">pkt_per_frm</a>;
+<a name="l02587"></a>02587                 sts.<a class="code" href="uniondev__dma__desc__sts.html#324fdd57830243334b74e0579b4e9f96">b_iso_in</a>.<a class="code" href="uniondev__dma__desc__sts.html#d9da3eccc6d247e2b5eccd4dfba7874e">framenum</a> = dwc_ep-&gt;<a class="code" href="structdwc__ep.html#1e9f4d08454c973c17acb3e52a2c3689">next_frame</a>;
+<a name="l02588"></a>02588                 sts.<a class="code" href="uniondev__dma__desc__sts.html#324fdd57830243334b74e0579b4e9f96">b_iso_in</a>.<a class="code" href="uniondev__dma__desc__sts.html#56cc3ad6b0e5704c6eb394f58f660eef">txbytes</a> = dwc_ep-&gt;<a class="code" href="structdwc__ep.html#4672369f4724db642856d72d5048213e">data_per_frame</a>;
+<a name="l02589"></a>02589                 sts.<a class="code" href="uniondev__dma__desc__sts.html#324fdd57830243334b74e0579b4e9f96">b_iso_in</a>.<a class="code" href="uniondev__dma__desc__sts.html#b728a79d6a86a0d1b6426a1b2627f2c2">l</a> = 0;
+<a name="l02590"></a>02590 
+<a name="l02591"></a>02591                 <span class="keywordflow">for</span> (i = 0; i &lt; dwc_ep-&gt;<a class="code" href="structdwc__ep.html#5e5bfcc93d41670bc0d29ad5f0f35871">desc_cnt</a> - 1; i++) {
+<a name="l02592"></a>02592                         dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#0454dad420ef536fe5eb7c38ef764430">buf</a> = dma_ad;
+<a name="l02593"></a>02593                         dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#fb77b9c4ab63304073542ed2b118a64b">d32</a> = sts.<a class="code" href="uniondev__dma__desc__sts.html#fb77b9c4ab63304073542ed2b118a64b">d32</a>;
+<a name="l02594"></a>02594 
+<a name="l02595"></a>02595                         sts.<a class="code" href="uniondev__dma__desc__sts.html#324fdd57830243334b74e0579b4e9f96">b_iso_in</a>.<a class="code" href="uniondev__dma__desc__sts.html#d9da3eccc6d247e2b5eccd4dfba7874e">framenum</a> += dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d9e9ffe348764ababc3165ed04f9ec6c">bInterval</a>;
+<a name="l02596"></a>02596                         dma_ad += dwc_ep-&gt;<a class="code" href="structdwc__ep.html#4672369f4724db642856d72d5048213e">data_per_frame</a>;
+<a name="l02597"></a>02597                         dma_desc++;
+<a name="l02598"></a>02598                 }
+<a name="l02599"></a>02599 
+<a name="l02600"></a>02600                 sts.<a class="code" href="uniondev__dma__desc__sts.html#324fdd57830243334b74e0579b4e9f96">b_iso_in</a>.<a class="code" href="uniondev__dma__desc__sts.html#02c8be72ef6258c25094478c7cac0b12">ioc</a> = 1;
+<a name="l02601"></a>02601                 sts.<a class="code" href="uniondev__dma__desc__sts.html#324fdd57830243334b74e0579b4e9f96">b_iso_in</a>.<a class="code" href="uniondev__dma__desc__sts.html#b728a79d6a86a0d1b6426a1b2627f2c2">l</a> = dwc_ep-&gt;<a class="code" href="structdwc__ep.html#53033f174854701986545f05502e1cad">proc_buf_num</a>;
+<a name="l02602"></a>02602 
+<a name="l02603"></a>02603                 dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#0454dad420ef536fe5eb7c38ef764430">buf</a> = dma_ad;
+<a name="l02604"></a>02604                 dma_desc-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>.<a class="code" href="uniondev__dma__desc__sts.html#fb77b9c4ab63304073542ed2b118a64b">d32</a> = sts.<a class="code" href="uniondev__dma__desc__sts.html#fb77b9c4ab63304073542ed2b118a64b">d32</a>;
+<a name="l02605"></a>02605 
+<a name="l02606"></a>02606                 dwc_ep-&gt;<a class="code" href="structdwc__ep.html#1e9f4d08454c973c17acb3e52a2c3689">next_frame</a> =
+<a name="l02607"></a>02607                     sts.<a class="code" href="uniondev__dma__desc__sts.html#324fdd57830243334b74e0579b4e9f96">b_iso_in</a>.<a class="code" href="uniondev__dma__desc__sts.html#d9da3eccc6d247e2b5eccd4dfba7874e">framenum</a> + dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d9e9ffe348764ababc3165ed04f9ec6c">bInterval</a> * 1;
+<a name="l02608"></a>02608         }
+<a name="l02609"></a>02609         dwc_ep-&gt;<a class="code" href="structdwc__ep.html#53033f174854701986545f05502e1cad">proc_buf_num</a> = (dwc_ep-&gt;<a class="code" href="structdwc__ep.html#53033f174854701986545f05502e1cad">proc_buf_num</a> ^ 1) &amp; 0x1;
+<a name="l02610"></a>02610 }
+<a name="l02611"></a>02611 
+<a name="l02620"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#41cfc0d590740640795b350998bcc2c4">02620</a> <span class="keyword">static</span> uint32_t <a class="code" href="dwc__otg__pcd__intr_8c.html#41cfc0d590740640795b350998bcc2c4">handle_iso_out_pkt_dropped</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if,
+<a name="l02621"></a>02621                                            <a class="code" href="structdwc__ep.html">dwc_ep_t</a> * <a class="code" href="structdwc__ep.html">dwc_ep</a>)
+<a name="l02622"></a>02622 {
+<a name="l02623"></a>02623         uint32_t dma_addr;
+<a name="l02624"></a>02624         uint32_t drp_pkt;
+<a name="l02625"></a>02625         uint32_t drp_pkt_cnt;
+<a name="l02626"></a>02626         <a class="code" href="uniondeptsiz__data.html">deptsiz_data_t</a> deptsiz = {.d32 = 0 };
+<a name="l02627"></a>02627         <a class="code" href="uniondepctl__data.html">depctl_data_t</a> depctl = {.d32 = 0 };
+<a name="l02628"></a>02628         <span class="keywordtype">int</span> i;
+<a name="l02629"></a>02629 
+<a name="l02630"></a>02630         deptsiz.<a class="code" href="uniondeptsiz__data.html#10c2b2ba8b419b0a766430a59befbbe0">d32</a> =
+<a name="l02631"></a>02631             dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">out_ep_regs</a>[dwc_ep-&gt;<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a>]-&gt;
+<a name="l02632"></a>02632                            doeptsiz);
+<a name="l02633"></a>02633 
+<a name="l02634"></a>02634         drp_pkt = dwc_ep-&gt;<a class="code" href="structdwc__ep.html#46349fb0608d8c6849ced211b0628c15">pkt_cnt</a> - deptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#bbd89e812371e5b555bb82373f3643d9">pktcnt</a>;
+<a name="l02635"></a>02635         drp_pkt_cnt = dwc_ep-&gt;<a class="code" href="structdwc__ep.html#fe51420474de8a9d74fc9c4adc811c4b">pkt_per_frm</a> - (drp_pkt % dwc_ep-&gt;<a class="code" href="structdwc__ep.html#fe51420474de8a9d74fc9c4adc811c4b">pkt_per_frm</a>);
+<a name="l02636"></a>02636 
+<a name="l02637"></a>02637         <span class="comment">/* Setting dropped packets status */</span>
+<a name="l02638"></a>02638         <span class="keywordflow">for</span> (i = 0; i &lt; drp_pkt_cnt; ++i) {
+<a name="l02639"></a>02639                 dwc_ep-&gt;<a class="code" href="structdwc__ep.html#a8ed15a24123a2dad6861da7d61dfb48">pkt_info</a>[drp_pkt].<a class="code" href="structiso__pkt__info.html#1317c3b425c0ef55dbde153b04c28dd4">status</a> = -DWC_E_NO_DATA;
+<a name="l02640"></a>02640                 drp_pkt++;
+<a name="l02641"></a>02641                 deptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#bbd89e812371e5b555bb82373f3643d9">pktcnt</a>--;
+<a name="l02642"></a>02642         }
+<a name="l02643"></a>02643 
+<a name="l02644"></a>02644         <span class="keywordflow">if</span> (deptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#bbd89e812371e5b555bb82373f3643d9">pktcnt</a> &gt; 0) {
+<a name="l02645"></a>02645                 deptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#cf06327d851e7cfe5c442b29bf2d6fa4">xfersize</a> =
+<a name="l02646"></a>02646                     dwc_ep-&gt;<a class="code" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">xfer_len</a> - (dwc_ep-&gt;<a class="code" href="structdwc__ep.html#46349fb0608d8c6849ced211b0628c15">pkt_cnt</a> -
+<a name="l02647"></a>02647                                         deptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#bbd89e812371e5b555bb82373f3643d9">pktcnt</a>) * dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a>;
+<a name="l02648"></a>02648         } <span class="keywordflow">else</span> {
+<a name="l02649"></a>02649                 deptsiz.b.xfersize = 0;
+<a name="l02650"></a>02650                 deptsiz.b.pktcnt = 0;
+<a name="l02651"></a>02651         }
+<a name="l02652"></a>02652 
+<a name="l02653"></a>02653         dwc_write_reg32(&amp;core_if-&gt;dev_if-&gt;out_ep_regs[<a class="code" href="structdwc__ep.html">dwc_ep</a>-&gt;num]-&gt;doeptsiz,
+<a name="l02654"></a>02654                         deptsiz.d32);
+<a name="l02655"></a>02655 
+<a name="l02656"></a>02656         <span class="keywordflow">if</span> (deptsiz.b.pktcnt &gt; 0) {
+<a name="l02657"></a>02657                 <span class="keywordflow">if</span> (<a class="code" href="structdwc__ep.html">dwc_ep</a>-&gt;proc_buf_num) {
+<a name="l02658"></a>02658                         dma_addr =
+<a name="l02659"></a>02659                             <a class="code" href="structdwc__ep.html">dwc_ep</a>-&gt;dma_addr1 + <a class="code" href="structdwc__ep.html">dwc_ep</a>-&gt;xfer_len -
+<a name="l02660"></a>02660                             deptsiz.b.xfersize;
+<a name="l02661"></a>02661                 } <span class="keywordflow">else</span> {
+<a name="l02662"></a>02662                         dma_addr =
+<a name="l02663"></a>02663                             <a class="code" href="structdwc__ep.html">dwc_ep</a>-&gt;dma_addr0 + <a class="code" href="structdwc__ep.html">dwc_ep</a>-&gt;xfer_len -
+<a name="l02664"></a>02664                             deptsiz.b.xfersize;;
+<a name="l02665"></a>02665                 }
+<a name="l02666"></a>02666 
+<a name="l02667"></a>02667                 dwc_write_reg32(&amp;core_if-&gt;dev_if-&gt;out_ep_regs[<a class="code" href="structdwc__ep.html">dwc_ep</a>-&gt;num]-&gt;
+<a name="l02668"></a>02668                                 doepdma, dma_addr);
+<a name="l02669"></a>02669 
+<a name="l02671"></a>02671                 depctl.d32 = 0;
+<a name="l02672"></a>02672                 depctl.b.epena = 1;
+<a name="l02673"></a>02673                 depctl.b.cnak = 1;
+<a name="l02674"></a>02674 
+<a name="l02675"></a>02675                 dwc_modify_reg32(&amp;core_if-&gt;dev_if-&gt;out_ep_regs[<a class="code" href="structdwc__ep.html">dwc_ep</a>-&gt;num]-&gt;
+<a name="l02676"></a>02676                                  doepctl, depctl.d32, depctl.d32);
+<a name="l02677"></a>02677                 <span class="keywordflow">return</span> 0;
+<a name="l02678"></a>02678         } <span class="keywordflow">else</span> {
+<a name="l02679"></a>02679                 <span class="keywordflow">return</span> 1;
+<a name="l02680"></a>02680         }
+<a name="l02681"></a>02681 }
+<a name="l02682"></a>02682 
+<a name="l02690"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#a356ecc4053e9700785a27dbfdd6b2db">02690</a> <span class="keyword">static</span> uint32_t <a class="code" href="dwc__otg__pcd__intr_8c.html#a356ecc4053e9700785a27dbfdd6b2db">set_iso_pkts_info</a>(<a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> * core_if, <a class="code" href="structdwc__ep.html">dwc_ep_t</a> * <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>)
+<a name="l02691"></a>02691 {
+<a name="l02692"></a>02692         <span class="keywordtype">int</span> i, j;
+<a name="l02693"></a>02693         dma_addr_t dma_ad;
+<a name="l02694"></a>02694         <a class="code" href="structiso__pkt__info.html">iso_pkt_info_t</a> *packet_info = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;pkt_info;
+<a name="l02695"></a>02695         uint32_t offset;
+<a name="l02696"></a>02696         uint32_t frame_data;
+<a name="l02697"></a>02697         <a class="code" href="uniondeptsiz__data.html">deptsiz_data_t</a> deptsiz;
+<a name="l02698"></a>02698 
+<a name="l02699"></a>02699         <span class="keywordflow">if</span> (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;proc_buf_num == 0) {
+<a name="l02701"></a>02701                 dma_ad = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;dma_addr0;
+<a name="l02702"></a>02702         } <span class="keywordflow">else</span> {
+<a name="l02704"></a>02704                 dma_ad = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;dma_addr1;
+<a name="l02705"></a>02705         }
+<a name="l02706"></a>02706 
+<a name="l02707"></a>02707         <span class="keywordflow">if</span> (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;is_in) {
+<a name="l02708"></a>02708                 deptsiz.<a class="code" href="uniondeptsiz__data.html#10c2b2ba8b419b0a766430a59befbbe0">d32</a> =
+<a name="l02709"></a>02709                     dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;num]-&gt;
+<a name="l02710"></a>02710                                    dieptsiz);
+<a name="l02711"></a>02711         } <span class="keywordflow">else</span> {
+<a name="l02712"></a>02712                 deptsiz.<a class="code" href="uniondeptsiz__data.html#10c2b2ba8b419b0a766430a59befbbe0">d32</a> =
+<a name="l02713"></a>02713                     dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">out_ep_regs</a>[<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;num]-&gt;
+<a name="l02714"></a>02714                                    doeptsiz);
+<a name="l02715"></a>02715         }
+<a name="l02716"></a>02716 
+<a name="l02717"></a>02717         <span class="keywordflow">if</span> (!deptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#cf06327d851e7cfe5c442b29bf2d6fa4">xfersize</a>) {
+<a name="l02718"></a>02718                 offset = 0;
+<a name="l02719"></a>02719                 <span class="keywordflow">for</span> (i = 0; i &lt; <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;pkt_cnt; i += <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;pkt_per_frm) {
+<a name="l02720"></a>02720                         frame_data = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;data_per_frame;
+<a name="l02721"></a>02721                         for (j = 0; j &lt; <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;pkt_per_frm; ++j) {
+<a name="l02722"></a>02722 
+<a name="l02723"></a>02723                                 <span class="comment">/* Packet status - is not set as initially </span>
+<a name="l02724"></a>02724 <span class="comment">                                 * it is set to 0 and if packet was sent </span>
+<a name="l02725"></a>02725 <span class="comment">                                 successfully, status field will remain 0*/</span>
+<a name="l02726"></a>02726 
+<a name="l02727"></a>02727                                 <span class="comment">/* Bytes has been transfered */</span>
+<a name="l02728"></a>02728                                 packet_info-&gt;<a class="code" href="structiso__pkt__info.html#ced82142e81778345016841e15020eb8">length</a> =
+<a name="l02729"></a>02729                                     (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;maxpacket &lt;
+<a name="l02730"></a>02730                                      frame_data) ? <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;maxpacket : frame_data;
+<a name="l02731"></a>02731 
+<a name="l02732"></a>02732                                 <span class="comment">/* Received packet offset */</span>
+<a name="l02733"></a>02733                                 packet_info-&gt;<a class="code" href="structiso__pkt__info.html#0c72a0585ccc93555da4db7e168f75f8">offset</a> = offset;
+<a name="l02734"></a>02734                                 offset += packet_info-&gt;<a class="code" href="structiso__pkt__info.html#ced82142e81778345016841e15020eb8">length</a>;
+<a name="l02735"></a>02735                                 frame_data -= packet_info-&gt;<a class="code" href="structiso__pkt__info.html#ced82142e81778345016841e15020eb8">length</a>;
+<a name="l02736"></a>02736 
+<a name="l02737"></a>02737                                 packet_info++;
+<a name="l02738"></a>02738                         }
+<a name="l02739"></a>02739                 }
+<a name="l02740"></a>02740                 <span class="keywordflow">return</span> 1;
+<a name="l02741"></a>02741         } <span class="keywordflow">else</span> {
+<a name="l02742"></a>02742                 <span class="comment">/* This is a workaround for in case of Transfer Complete with </span>
+<a name="l02743"></a>02743 <span class="comment">                 * PktDrpSts interrupts merging - in this case Transfer complete </span>
+<a name="l02744"></a>02744 <span class="comment">                 * interrupt for Isoc Out Endpoint is asserted without PktDrpSts </span>
+<a name="l02745"></a>02745 <span class="comment">                 * set and with DOEPTSIZ register non zero. Investigations showed,</span>
+<a name="l02746"></a>02746 <span class="comment">                 * that this happens when Out packet is dropped, but because of </span>
+<a name="l02747"></a>02747 <span class="comment">                 * interrupts merging during first interrupt handling PktDrpSts</span>
+<a name="l02748"></a>02748 <span class="comment">                 * bit is cleared and for next merged interrupts it is not reset.</span>
+<a name="l02749"></a>02749 <span class="comment">                 * In this case SW hadles the interrupt as if PktDrpSts bit is set.</span>
+<a name="l02750"></a>02750 <span class="comment">                 */</span>
+<a name="l02751"></a>02751                 <span class="keywordflow">if</span> (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;is_in) {
+<a name="l02752"></a>02752                         <span class="keywordflow">return</span> 1;
+<a name="l02753"></a>02753                 } <span class="keywordflow">else</span> {
+<a name="l02754"></a>02754                         <span class="keywordflow">return</span> <a class="code" href="dwc__otg__pcd__intr_8c.html#41cfc0d590740640795b350998bcc2c4">handle_iso_out_pkt_dropped</a>(core_if, <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>);
+<a name="l02755"></a>02755                 }
+<a name="l02756"></a>02756         }
+<a name="l02757"></a>02757 }
+<a name="l02758"></a>02758 
+<a name="l02766"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#05965765a43225780ae08f2c3928f782">02766</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd__intr_8c.html#05965765a43225780ae08f2c3928f782">complete_iso_ep</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd, <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> * <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>)
+<a name="l02767"></a>02767 {
+<a name="l02768"></a>02768         <a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if = <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#234391334e48cbd72710d08655c9ed16">pcd</a>);
+<a name="l02769"></a>02769         <a class="code" href="structdwc__ep.html">dwc_ep_t</a> *<a class="code" href="structdwc__ep.html">dwc_ep</a> = &amp;<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>;
+<a name="l02770"></a>02770         uint8_t is_last = 0;
+<a name="l02771"></a>02771 
+<a name="l02772"></a>02772         <span class="keywordflow">if</span>(<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#1e9f4d08454c973c17acb3e52a2c3689">next_frame</a> == 0xffffffff) {
+<a name="l02773"></a>02773                 DWC_WARN(<span class="stringliteral">"Next frame is not set!\n"</span>);
+<a name="l02774"></a>02774                 <span class="keywordflow">return</span>;
+<a name="l02775"></a>02775         }
+<a name="l02776"></a>02776 
+<a name="l02777"></a>02777         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a>) {
+<a name="l02778"></a>02778                 <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a>) {
+<a name="l02779"></a>02779                         <a class="code" href="dwc__otg__pcd__intr_8c.html#e5ed26b3ab2380cb92773df1720ec752">set_ddma_iso_pkts_info</a>(core_if, dwc_ep);
+<a name="l02780"></a>02780                         <a class="code" href="dwc__otg__pcd__intr_8c.html#c3f6fb3131e0786ec75a9c4a29fea297">reinit_ddma_iso_xfer</a>(core_if, dwc_ep);
+<a name="l02781"></a>02781                         is_last = 1;
+<a name="l02782"></a>02782                 } <span class="keywordflow">else</span> {
+<a name="l02783"></a>02783                         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#34540b79e9a14bfa234a52ac132c5cd1">pti_enh_enable</a>) {
+<a name="l02784"></a>02784                                 <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__pcd__intr_8c.html#a356ecc4053e9700785a27dbfdd6b2db">set_iso_pkts_info</a>(core_if, dwc_ep)) {
+<a name="l02785"></a>02785                                         dwc_ep-&gt;<a class="code" href="structdwc__ep.html#53033f174854701986545f05502e1cad">proc_buf_num</a> =
+<a name="l02786"></a>02786                                             (dwc_ep-&gt;<a class="code" href="structdwc__ep.html#53033f174854701986545f05502e1cad">proc_buf_num</a> ^ 1) &amp; 0x1;
+<a name="l02787"></a>02787                                         <a class="code" href="dwc__otg__cil_8h.html#0b13a31a7ddc82b53862cd06cfed6393">dwc_otg_iso_ep_start_buf_transfer</a>
+<a name="l02788"></a>02788                                             (core_if, dwc_ep);
+<a name="l02789"></a>02789                                         is_last = 1;
+<a name="l02790"></a>02790                                 }
+<a name="l02791"></a>02791                         } <span class="keywordflow">else</span> {
+<a name="l02792"></a>02792                                 <a class="code" href="dwc__otg__pcd__intr_8c.html#17428b2360118cc59ab9d5cbcef8a14b">set_current_pkt_info</a>(core_if, dwc_ep);
+<a name="l02793"></a>02793                                 <span class="keywordflow">if</span> (dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d4e63c7d944c2b48260b4a75c2b58925">cur_pkt</a> &gt;= dwc_ep-&gt;<a class="code" href="structdwc__ep.html#46349fb0608d8c6849ced211b0628c15">pkt_cnt</a>) {
+<a name="l02794"></a>02794                                         is_last = 1;
+<a name="l02795"></a>02795                                         dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d4e63c7d944c2b48260b4a75c2b58925">cur_pkt</a> = 0;
+<a name="l02796"></a>02796                                         dwc_ep-&gt;<a class="code" href="structdwc__ep.html#53033f174854701986545f05502e1cad">proc_buf_num</a> =
+<a name="l02797"></a>02797                                             (dwc_ep-&gt;<a class="code" href="structdwc__ep.html#53033f174854701986545f05502e1cad">proc_buf_num</a> ^ 1) &amp; 0x1;
+<a name="l02798"></a>02798                                         <span class="keywordflow">if</span> (dwc_ep-&gt;<a class="code" href="structdwc__ep.html#53033f174854701986545f05502e1cad">proc_buf_num</a>) {
+<a name="l02799"></a>02799                                                 dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d3bc23598a77d3cca52c70a28afc6b5e">cur_pkt_addr</a> =
+<a name="l02800"></a>02800                                                     dwc_ep-&gt;<a class="code" href="structdwc__ep.html#36ff87362a0da5bce95eaf85522d49ff">xfer_buff1</a>;
+<a name="l02801"></a>02801                                                 dwc_ep-&gt;<a class="code" href="structdwc__ep.html#ed4594c9f6c2bcbcf6f1bbe9e9c64061">cur_pkt_dma_addr</a> =
+<a name="l02802"></a>02802                                                     dwc_ep-&gt;<a class="code" href="structdwc__ep.html#02dc1be77d505b19f14651fe9805c97f">dma_addr1</a>;
+<a name="l02803"></a>02803                                         } <span class="keywordflow">else</span> {
+<a name="l02804"></a>02804                                                 dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d3bc23598a77d3cca52c70a28afc6b5e">cur_pkt_addr</a> =
+<a name="l02805"></a>02805                                                     dwc_ep-&gt;<a class="code" href="structdwc__ep.html#b6d727e366ac589d304256c758d2d44a">xfer_buff0</a>;
+<a name="l02806"></a>02806                                                 dwc_ep-&gt;<a class="code" href="structdwc__ep.html#ed4594c9f6c2bcbcf6f1bbe9e9c64061">cur_pkt_dma_addr</a> =
+<a name="l02807"></a>02807                                                     dwc_ep-&gt;<a class="code" href="structdwc__ep.html#553936d1d003413d00a24330274887f9">dma_addr0</a>;
+<a name="l02808"></a>02808                                         }
+<a name="l02809"></a>02809 
+<a name="l02810"></a>02810                                 }
+<a name="l02811"></a>02811                                 <a class="code" href="dwc__otg__cil_8c.html#0f0894ae9890260e1da839aa10af35cc">dwc_otg_iso_ep_start_frm_transfer</a>(core_if,
+<a name="l02812"></a>02812                                                                   dwc_ep);
+<a name="l02813"></a>02813                         }
+<a name="l02814"></a>02814                 }
+<a name="l02815"></a>02815         } <span class="keywordflow">else</span> {
+<a name="l02816"></a>02816                 <a class="code" href="dwc__otg__pcd__intr_8c.html#17428b2360118cc59ab9d5cbcef8a14b">set_current_pkt_info</a>(core_if, dwc_ep);
+<a name="l02817"></a>02817                 <span class="keywordflow">if</span> (dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d4e63c7d944c2b48260b4a75c2b58925">cur_pkt</a> &gt;= dwc_ep-&gt;<a class="code" href="structdwc__ep.html#46349fb0608d8c6849ced211b0628c15">pkt_cnt</a>) {
+<a name="l02818"></a>02818                         is_last = 1;
+<a name="l02819"></a>02819                         dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d4e63c7d944c2b48260b4a75c2b58925">cur_pkt</a> = 0;
+<a name="l02820"></a>02820                         dwc_ep-&gt;<a class="code" href="structdwc__ep.html#53033f174854701986545f05502e1cad">proc_buf_num</a> = (dwc_ep-&gt;<a class="code" href="structdwc__ep.html#53033f174854701986545f05502e1cad">proc_buf_num</a> ^ 1) &amp; 0x1;
+<a name="l02821"></a>02821                         <span class="keywordflow">if</span> (dwc_ep-&gt;<a class="code" href="structdwc__ep.html#53033f174854701986545f05502e1cad">proc_buf_num</a>) {
+<a name="l02822"></a>02822                                 dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d3bc23598a77d3cca52c70a28afc6b5e">cur_pkt_addr</a> = dwc_ep-&gt;<a class="code" href="structdwc__ep.html#36ff87362a0da5bce95eaf85522d49ff">xfer_buff1</a>;
+<a name="l02823"></a>02823                                 dwc_ep-&gt;<a class="code" href="structdwc__ep.html#ed4594c9f6c2bcbcf6f1bbe9e9c64061">cur_pkt_dma_addr</a> = dwc_ep-&gt;<a class="code" href="structdwc__ep.html#02dc1be77d505b19f14651fe9805c97f">dma_addr1</a>;
+<a name="l02824"></a>02824                         } <span class="keywordflow">else</span> {
+<a name="l02825"></a>02825                                 dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d3bc23598a77d3cca52c70a28afc6b5e">cur_pkt_addr</a> = dwc_ep-&gt;<a class="code" href="structdwc__ep.html#b6d727e366ac589d304256c758d2d44a">xfer_buff0</a>;
+<a name="l02826"></a>02826                                 dwc_ep-&gt;<a class="code" href="structdwc__ep.html#ed4594c9f6c2bcbcf6f1bbe9e9c64061">cur_pkt_dma_addr</a> = dwc_ep-&gt;<a class="code" href="structdwc__ep.html#553936d1d003413d00a24330274887f9">dma_addr0</a>;
+<a name="l02827"></a>02827                         }
+<a name="l02828"></a>02828 
+<a name="l02829"></a>02829                 }
+<a name="l02830"></a>02830                 <a class="code" href="dwc__otg__cil_8c.html#0f0894ae9890260e1da839aa10af35cc">dwc_otg_iso_ep_start_frm_transfer</a>(core_if, dwc_ep);
+<a name="l02831"></a>02831         }
+<a name="l02832"></a>02832         <span class="keywordflow">if</span> (is_last)
+<a name="l02833"></a>02833                 <a class="code" href="dwc__otg__pcd_8c.html#b4e2c352426923d4bd519cf18b68206d">dwc_otg_iso_buffer_done</a>(pcd, <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>, <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#716d3c29adc54c6822935fc2ae9bef51">iso_req_handle</a>);
+<a name="l02834"></a>02834 }
+<a name="l02835"></a>02835 <span class="preprocessor">#endif                          </span><span class="comment">/* DWC_EN_ISOC */</span>
+<a name="l02836"></a>02836 
+<a name="l02843"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#4991119b51de03163a3677c36bc0ee3b">02843</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd__intr_8c.html#4991119b51de03163a3677c36bc0ee3b">handle_ep0</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd)
+<a name="l02844"></a>02844 {
+<a name="l02845"></a>02845         <a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if = <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd);
+<a name="l02846"></a>02846         <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *ep0 = &amp;pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a>;
+<a name="l02847"></a>02847         <a class="code" href="uniondev__dma__desc__sts.html">dev_dma_desc_sts_t</a> desc_sts;
+<a name="l02848"></a>02848         <a class="code" href="uniondeptsiz0__data.html">deptsiz0_data_t</a> deptsiz;
+<a name="l02849"></a>02849         uint32_t byte_count;
+<a name="l02850"></a>02850 
+<a name="l02851"></a>02851 <span class="preprocessor">#ifdef DEBUG_EP0</span>
+<a name="l02852"></a>02852 <span class="preprocessor"></span>        <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"%s()\n"</span>, __func__);
+<a name="l02853"></a>02853         <a class="code" href="dwc__otg__pcd__intr_8c.html#13cc45eef95b81189df890c10cf7ca66">print_ep0_state</a>(pcd);
+<a name="l02854"></a>02854 <span class="preprocessor">#endif</span>
+<a name="l02855"></a>02855 <span class="preprocessor"></span>
+<a name="l02856"></a>02856 <span class="comment">//      DWC_PRINTF("HANDLE EP0\n");</span>
+<a name="l02857"></a>02857 
+<a name="l02858"></a>02858         <span class="keywordflow">switch</span> (pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#8f6963b3fb9ab83048c4c0697c90382a">ep0state</a>) {
+<a name="l02859"></a>02859         <span class="keywordflow">case</span> EP0_DISCONNECT:
+<a name="l02860"></a>02860                 <span class="keywordflow">break</span>;
+<a name="l02861"></a>02861 
+<a name="l02862"></a>02862         <span class="keywordflow">case</span> EP0_IDLE:
+<a name="l02863"></a>02863                 pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#cbe5c4062e140ee88f51ee916c0db0ad">request_config</a> = 0;
+<a name="l02864"></a>02864 
+<a name="l02865"></a>02865                 <a class="code" href="dwc__otg__pcd__intr_8c.html#856a520a378e4f6f274253227080cfa1">pcd_setup</a>(pcd);
+<a name="l02866"></a>02866                 <span class="keywordflow">break</span>;
+<a name="l02867"></a>02867 
+<a name="l02868"></a>02868         <span class="keywordflow">case</span> EP0_IN_DATA_PHASE:
+<a name="l02869"></a>02869 <span class="preprocessor">#ifdef DEBUG_EP0</span>
+<a name="l02870"></a>02870 <span class="preprocessor"></span>                <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"DATA_IN EP%d-%s: type=%d, mps=%d\n"</span>,
+<a name="l02871"></a>02871                             ep0-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a>, (ep0-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#b882b6b7c857100ed20600e94ea37760">is_in</a> ? <span class="stringliteral">"IN"</span> : <span class="stringliteral">"OUT"</span>),
+<a name="l02872"></a>02872                             ep0-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#17b10677bd9b0a1d612dd4ce2fb0eb0f">type</a>, ep0-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a>);
+<a name="l02873"></a>02873 <span class="preprocessor">#endif</span>
+<a name="l02874"></a>02874 <span class="preprocessor"></span>
+<a name="l02875"></a>02875                 <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a> != 0) {
+<a name="l02876"></a>02876                         <span class="comment">/*</span>
+<a name="l02877"></a>02877 <span class="comment">                         * For EP0 we can only program 1 packet at a time so we</span>
+<a name="l02878"></a>02878 <span class="comment">                         * need to do the make calculations after each complete.</span>
+<a name="l02879"></a>02879 <span class="comment">                         * Call write_packet to make the calculations, as in</span>
+<a name="l02880"></a>02880 <span class="comment">                         * slave mode, and use those values to determine if we</span>
+<a name="l02881"></a>02881 <span class="comment">                         * can complete.</span>
+<a name="l02882"></a>02882 <span class="comment">                         */</span>
+<a name="l02883"></a>02883                         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a> == 0) {
+<a name="l02884"></a>02884                                 deptsiz.<a class="code" href="uniondeptsiz0__data.html#a06fa9b1dcaee47fba9cf869027ed6f1">d32</a> =
+<a name="l02885"></a>02885                                     dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;
+<a name="l02886"></a>02886                                                    in_ep_regs[0]-&gt;dieptsiz);
+<a name="l02887"></a>02887                                 byte_count =
+<a name="l02888"></a>02888                                     ep0-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">xfer_len</a> - deptsiz.<a class="code" href="uniondeptsiz0__data.html#8e50594573fd774fc3e27404d8b1f59c">b</a>.<a class="code" href="uniondeptsiz0__data.html#1792e672dde70ead19bd0f5e7642af03">xfersize</a>;
+<a name="l02889"></a>02889                         } <span class="keywordflow">else</span> {
+<a name="l02890"></a>02890                                 desc_sts =
+<a name="l02891"></a>02891                                     core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#99f44e328bbb4401aabd8e2708853238">in_desc_addr</a>-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>;
+<a name="l02892"></a>02892                                 byte_count =
+<a name="l02893"></a>02893                                     ep0-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">xfer_len</a> - desc_sts.<a class="code" href="uniondev__dma__desc__sts.html#1876c32496f0067948f6282b7583aeab">b</a>.<a class="code" href="uniondev__dma__desc__sts.html#9b6181d78984cb4d853945774f300ef0">bytes</a>;
+<a name="l02894"></a>02894                         }
+<a name="l02895"></a>02895                         ep0-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#23d4871510b5bcb54fbf0674d8f122bd">xfer_count</a> += byte_count;
+<a name="l02896"></a>02896                         ep0-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#97fa9bf5c31ba734d54f70e6fe6ae8eb">xfer_buff</a> += byte_count;
+<a name="l02897"></a>02897                         ep0-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#b40ce70422b6d105a855a8df4b33d45d">dma_addr</a> += byte_count;
+<a name="l02898"></a>02898                 }
+<a name="l02899"></a>02899                 <span class="keywordflow">if</span> (ep0-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#23d4871510b5bcb54fbf0674d8f122bd">xfer_count</a> &lt; ep0-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#5a218f200cff0491b735f43fed5176bf">total_len</a>) {
+<a name="l02900"></a>02900                         <a class="code" href="dwc__otg__cil_8c.html#d8c1e6f7860c482df84db003b52c369c">dwc_otg_ep0_continue_transfer</a>(<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd),
+<a name="l02901"></a>02901                                                       &amp;ep0-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>);
+<a name="l02902"></a>02902                         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"CONTINUE TRANSFER\n"</span>);
+<a name="l02903"></a>02903                 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (ep0-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#8c6340435beba0b8c025a4677602acab">sent_zlp</a>) {
+<a name="l02904"></a>02904                         <a class="code" href="dwc__otg__cil_8c.html#d8c1e6f7860c482df84db003b52c369c">dwc_otg_ep0_continue_transfer</a>(<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd),
+<a name="l02905"></a>02905                                                       &amp;ep0-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>);
+<a name="l02906"></a>02906                         ep0-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#8c6340435beba0b8c025a4677602acab">sent_zlp</a> = 0;
+<a name="l02907"></a>02907                         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"CONTINUE TRANSFER\n"</span>);
+<a name="l02908"></a>02908                 } <span class="keywordflow">else</span> {
+<a name="l02909"></a>02909                         <a class="code" href="dwc__otg__pcd__intr_8c.html#f64bfae20151c51d3b0a6d4e523f356e">ep0_complete_request</a>(ep0);
+<a name="l02910"></a>02910                         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"COMPLETE TRANSFER\n"</span>);
+<a name="l02911"></a>02911                 }
+<a name="l02912"></a>02912                 <span class="keywordflow">break</span>;
+<a name="l02913"></a>02913         <span class="keywordflow">case</span> EP0_OUT_DATA_PHASE:
+<a name="l02914"></a>02914 <span class="preprocessor">#ifdef DEBUG_EP0</span>
+<a name="l02915"></a>02915 <span class="preprocessor"></span>                <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"DATA_OUT EP%d-%s: type=%d, mps=%d\n"</span>,
+<a name="l02916"></a>02916                             ep0-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a>, (ep0-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#b882b6b7c857100ed20600e94ea37760">is_in</a> ? <span class="stringliteral">"IN"</span> : <span class="stringliteral">"OUT"</span>),
+<a name="l02917"></a>02917                             ep0-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#17b10677bd9b0a1d612dd4ce2fb0eb0f">type</a>, ep0-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a>);
+<a name="l02918"></a>02918 <span class="preprocessor">#endif</span>
+<a name="l02919"></a>02919 <span class="preprocessor"></span>                <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a> != 0) {
+<a name="l02920"></a>02920                         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a> == 0) {
+<a name="l02921"></a>02921                                 deptsiz.<a class="code" href="uniondeptsiz0__data.html#a06fa9b1dcaee47fba9cf869027ed6f1">d32</a> =
+<a name="l02922"></a>02922                                     dwc_read_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;
+<a name="l02923"></a>02923                                                    out_ep_regs[0]-&gt;doeptsiz);
+<a name="l02924"></a>02924                                 byte_count =
+<a name="l02925"></a>02925                                     ep0-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a> - deptsiz.<a class="code" href="uniondeptsiz0__data.html#8e50594573fd774fc3e27404d8b1f59c">b</a>.<a class="code" href="uniondeptsiz0__data.html#1792e672dde70ead19bd0f5e7642af03">xfersize</a>;
+<a name="l02926"></a>02926                         } <span class="keywordflow">else</span> {
+<a name="l02927"></a>02927                                 desc_sts =
+<a name="l02928"></a>02928                                     core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#8cc9be8ccaba2ef93b02b34ba7b26bad">out_desc_addr</a>-&gt;<a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>;
+<a name="l02929"></a>02929                                 byte_count =
+<a name="l02930"></a>02930                                     ep0-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a> - desc_sts.<a class="code" href="uniondev__dma__desc__sts.html#1876c32496f0067948f6282b7583aeab">b</a>.<a class="code" href="uniondev__dma__desc__sts.html#9b6181d78984cb4d853945774f300ef0">bytes</a>;
+<a name="l02931"></a>02931                         }
+<a name="l02932"></a>02932                         ep0-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#23d4871510b5bcb54fbf0674d8f122bd">xfer_count</a> += byte_count;
+<a name="l02933"></a>02933                         ep0-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#97fa9bf5c31ba734d54f70e6fe6ae8eb">xfer_buff</a> += byte_count;
+<a name="l02934"></a>02934                         ep0-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#b40ce70422b6d105a855a8df4b33d45d">dma_addr</a> += byte_count;
+<a name="l02935"></a>02935                 }
+<a name="l02936"></a>02936                 <span class="keywordflow">if</span> (ep0-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#23d4871510b5bcb54fbf0674d8f122bd">xfer_count</a> &lt; ep0-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#5a218f200cff0491b735f43fed5176bf">total_len</a>) {
+<a name="l02937"></a>02937                         <a class="code" href="dwc__otg__cil_8c.html#d8c1e6f7860c482df84db003b52c369c">dwc_otg_ep0_continue_transfer</a>(<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd),
+<a name="l02938"></a>02938                                                       &amp;ep0-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>);
+<a name="l02939"></a>02939                         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"CONTINUE TRANSFER\n"</span>);
+<a name="l02940"></a>02940                 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (ep0-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#8c6340435beba0b8c025a4677602acab">sent_zlp</a>) {
+<a name="l02941"></a>02941                         <a class="code" href="dwc__otg__cil_8c.html#d8c1e6f7860c482df84db003b52c369c">dwc_otg_ep0_continue_transfer</a>(<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd),
+<a name="l02942"></a>02942                                                       &amp;ep0-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>);
+<a name="l02943"></a>02943                         ep0-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#8c6340435beba0b8c025a4677602acab">sent_zlp</a> = 0;
+<a name="l02944"></a>02944                         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"CONTINUE TRANSFER\n"</span>);
+<a name="l02945"></a>02945                 } <span class="keywordflow">else</span> {
+<a name="l02946"></a>02946                         <a class="code" href="dwc__otg__pcd__intr_8c.html#f64bfae20151c51d3b0a6d4e523f356e">ep0_complete_request</a>(ep0);
+<a name="l02947"></a>02947                         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"COMPLETE TRANSFER\n"</span>);
+<a name="l02948"></a>02948                 }
+<a name="l02949"></a>02949                 <span class="keywordflow">break</span>;
+<a name="l02950"></a>02950 
+<a name="l02951"></a>02951         <span class="keywordflow">case</span> EP0_IN_STATUS_PHASE:
+<a name="l02952"></a>02952         <span class="keywordflow">case</span> EP0_OUT_STATUS_PHASE:
+<a name="l02953"></a>02953                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"CASE: EP0_STATUS\n"</span>);
+<a name="l02954"></a>02954                 <a class="code" href="dwc__otg__pcd__intr_8c.html#f64bfae20151c51d3b0a6d4e523f356e">ep0_complete_request</a>(ep0);
+<a name="l02955"></a>02955                 pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#8f6963b3fb9ab83048c4c0697c90382a">ep0state</a> = EP0_IDLE;
+<a name="l02956"></a>02956                 ep0-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#cce0e089118d8bf7c6278c21ded70d5a">stopped</a> = 1;
+<a name="l02957"></a>02957                 ep0-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#b882b6b7c857100ed20600e94ea37760">is_in</a> = 0;  <span class="comment">/* OUT for next SETUP */</span>
+<a name="l02958"></a>02958 
+<a name="l02959"></a>02959                 <span class="comment">/* Prepare for more SETUP Packets */</span>
+<a name="l02960"></a>02960                 <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a>) {
+<a name="l02961"></a>02961                         <a class="code" href="dwc__otg__pcd__intr_8c.html#726b57833bb3ae4648ce7e7a7e125bf7">ep0_out_start</a>(core_if, pcd);
+<a name="l02962"></a>02962                 }
+<a name="l02963"></a>02963                 <span class="keywordflow">break</span>;
+<a name="l02964"></a>02964 
+<a name="l02965"></a>02965         <span class="keywordflow">case</span> EP0_STALL:
+<a name="l02966"></a>02966                 DWC_ERROR(<span class="stringliteral">"EP0 STALLed, should not get here pcd_setup()\n"</span>);
+<a name="l02967"></a>02967                 <span class="keywordflow">break</span>;
+<a name="l02968"></a>02968         }
+<a name="l02969"></a>02969 <span class="preprocessor">#ifdef DEBUG_EP0</span>
+<a name="l02970"></a>02970 <span class="preprocessor"></span>        <a class="code" href="dwc__otg__pcd__intr_8c.html#13cc45eef95b81189df890c10cf7ca66">print_ep0_state</a>(pcd);
+<a name="l02971"></a>02971 <span class="preprocessor">#endif</span>
+<a name="l02972"></a>02972 <span class="preprocessor"></span>}
+<a name="l02973"></a>02973 
+<a name="l02977"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#ed405cebf67cd1a89efd15a2935c8cef">02977</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd__intr_8c.html#ed405cebf67cd1a89efd15a2935c8cef">restart_transfer</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd, <span class="keyword">const</span> uint32_t epnum)
+<a name="l02978"></a>02978 {
+<a name="l02979"></a>02979         <a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if;
+<a name="l02980"></a>02980         <a class="code" href="structdwc__otg__dev__if.html">dwc_otg_dev_if_t</a> *dev_if;
+<a name="l02981"></a>02981         <a class="code" href="uniondeptsiz__data.html">deptsiz_data_t</a> dieptsiz = {.d32 = 0 };
+<a name="l02982"></a>02982         <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>;
+<a name="l02983"></a>02983 
+<a name="l02984"></a>02984         <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a> = <a class="code" href="dwc__otg__pcd__intr_8c.html#cc3f2f1ae0ab7d33903a1d0d9097c04e">get_in_ep</a>(pcd, epnum);
+<a name="l02985"></a>02985 
+<a name="l02986"></a>02986 <span class="preprocessor">#ifdef DWC_EN_ISOC</span>
+<a name="l02987"></a>02987 <span class="preprocessor"></span>        <span class="keywordflow">if</span> (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#17b10677bd9b0a1d612dd4ce2fb0eb0f">type</a> == <a class="code" href="dwc__otg__cil_8h.html#152a3a5e1433bd2197672f0b5105e7a4">DWC_OTG_EP_TYPE_ISOC</a>) {
+<a name="l02988"></a>02988                 <span class="keywordflow">return</span>;
+<a name="l02989"></a>02989         }
+<a name="l02990"></a>02990 <span class="preprocessor">#endif                          </span><span class="comment">/* DWC_EN_ISOC  */</span>
+<a name="l02991"></a>02991 
+<a name="l02992"></a>02992         core_if = <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd);
+<a name="l02993"></a>02993         dev_if = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>;
+<a name="l02994"></a>02994 
+<a name="l02995"></a>02995         dieptsiz.<a class="code" href="uniondeptsiz__data.html#10c2b2ba8b419b0a766430a59befbbe0">d32</a> = dwc_read_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[epnum]-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#88f637b5a4e8a0c6bc87d157072255dd">dieptsiz</a>);
+<a name="l02996"></a>02996 
+<a name="l02997"></a>02997         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"xfer_buff=%p xfer_count=%0x xfer_len=%0x"</span>
+<a name="l02998"></a>02998                     <span class="stringliteral">" stopped=%d\n"</span>, <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#97fa9bf5c31ba734d54f70e6fe6ae8eb">xfer_buff</a>,
+<a name="l02999"></a>02999                     <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#23d4871510b5bcb54fbf0674d8f122bd">xfer_count</a>, <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">xfer_len</a>, <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#cce0e089118d8bf7c6278c21ded70d5a">stopped</a>);
+<a name="l03000"></a>03000         <span class="comment">/*</span>
+<a name="l03001"></a>03001 <span class="comment">         * If xfersize is 0 and pktcnt in not 0, resend the last packet.</span>
+<a name="l03002"></a>03002 <span class="comment">         */</span>
+<a name="l03003"></a>03003         <span class="keywordflow">if</span> (dieptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#bbd89e812371e5b555bb82373f3643d9">pktcnt</a> &amp;&amp; dieptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#cf06327d851e7cfe5c442b29bf2d6fa4">xfersize</a> == 0 &amp;&amp;
+<a name="l03004"></a>03004             <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#d0cda8ded2e5142d9a1c9c17efc5812f">start_xfer_buff</a> != 0) {
+<a name="l03005"></a>03005                 <span class="keywordflow">if</span> (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#5a218f200cff0491b735f43fed5176bf">total_len</a> &lt;= <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a>) {
+<a name="l03006"></a>03006                         <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#23d4871510b5bcb54fbf0674d8f122bd">xfer_count</a> = 0;
+<a name="l03007"></a>03007                         <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#97fa9bf5c31ba734d54f70e6fe6ae8eb">xfer_buff</a> = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#d0cda8ded2e5142d9a1c9c17efc5812f">start_xfer_buff</a>;
+<a name="l03008"></a>03008                         <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">xfer_len</a> = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#23d4871510b5bcb54fbf0674d8f122bd">xfer_count</a>;
+<a name="l03009"></a>03009                 } <span class="keywordflow">else</span> {
+<a name="l03010"></a>03010                         <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#23d4871510b5bcb54fbf0674d8f122bd">xfer_count</a> -= <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a>;
+<a name="l03011"></a>03011                         <span class="comment">/* convert packet size to dwords. */</span>
+<a name="l03012"></a>03012                         <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#97fa9bf5c31ba734d54f70e6fe6ae8eb">xfer_buff</a> -= <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a>;
+<a name="l03013"></a>03013                         <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">xfer_len</a> = <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#23d4871510b5bcb54fbf0674d8f122bd">xfer_count</a>;
+<a name="l03014"></a>03014                 }
+<a name="l03015"></a>03015                 <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#cce0e089118d8bf7c6278c21ded70d5a">stopped</a> = 0;
+<a name="l03016"></a>03016                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"xfer_buff=%p xfer_count=%0x "</span>
+<a name="l03017"></a>03017                             <span class="stringliteral">"xfer_len=%0x stopped=%d\n"</span>,
+<a name="l03018"></a>03018                             <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#97fa9bf5c31ba734d54f70e6fe6ae8eb">xfer_buff</a>,
+<a name="l03019"></a>03019                             <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#23d4871510b5bcb54fbf0674d8f122bd">xfer_count</a>, <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">xfer_len</a>,
+<a name="l03020"></a>03020                             <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#cce0e089118d8bf7c6278c21ded70d5a">stopped</a>);
+<a name="l03021"></a>03021                 <span class="keywordflow">if</span> (epnum == 0) {
+<a name="l03022"></a>03022                         <a class="code" href="dwc__otg__cil_8c.html#ee4989b24826b2a6592535282853e556">dwc_otg_ep0_start_transfer</a>(core_if, &amp;<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>);
+<a name="l03023"></a>03023                 } <span class="keywordflow">else</span> {
+<a name="l03024"></a>03024                         <a class="code" href="dwc__otg__cil_8c.html#1278f6d58a4a2bc780e90e0b6c9b9a68">dwc_otg_ep_start_transfer</a>(core_if, &amp;<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>);
+<a name="l03025"></a>03025                 }
+<a name="l03026"></a>03026         }
+<a name="l03027"></a>03027 }
+<a name="l03028"></a>03028 
+<a name="l03032"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#6c9df42abc5cb6f676a44918207c91b7">03032</a> <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd__intr_8c.html#6c9df42abc5cb6f676a44918207c91b7">handle_in_ep_disable_intr</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd,
+<a name="l03033"></a>03033                                              <span class="keyword">const</span> uint32_t epnum)
+<a name="l03034"></a>03034 {
+<a name="l03035"></a>03035         <a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if = <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd);
+<a name="l03036"></a>03036         <a class="code" href="structdwc__otg__dev__if.html">dwc_otg_dev_if_t</a> *dev_if = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>;
+<a name="l03037"></a>03037         <a class="code" href="uniondeptsiz__data.html">deptsiz_data_t</a> dieptsiz = {.d32 = 0 };
+<a name="l03038"></a>03038         <a class="code" href="uniondctl__data.html">dctl_data_t</a> dctl = {.d32 = 0 };
+<a name="l03039"></a>03039         <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>;
+<a name="l03040"></a>03040         <a class="code" href="structdwc__ep.html">dwc_ep_t</a> *<a class="code" href="structdwc__ep.html">dwc_ep</a>;
+<a name="l03041"></a>03041 
+<a name="l03042"></a>03042         <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a> = <a class="code" href="dwc__otg__pcd__intr_8c.html#cc3f2f1ae0ab7d33903a1d0d9097c04e">get_in_ep</a>(pcd, epnum);
+<a name="l03043"></a>03043         dwc_ep = &amp;<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>;
+<a name="l03044"></a>03044 
+<a name="l03045"></a>03045         <span class="keywordflow">if</span> (dwc_ep-&gt;<a class="code" href="structdwc__ep.html#17b10677bd9b0a1d612dd4ce2fb0eb0f">type</a> == <a class="code" href="dwc__otg__cil_8h.html#152a3a5e1433bd2197672f0b5105e7a4">DWC_OTG_EP_TYPE_ISOC</a>) {
+<a name="l03046"></a>03046                 <a class="code" href="dwc__otg__cil_8c.html#039e387cd0e0282727da3c5a36f4cdda">dwc_otg_flush_tx_fifo</a>(core_if, dwc_ep-&gt;<a class="code" href="structdwc__ep.html#ffa14f48094778143353b845b5d238cd">tx_fifo_num</a>);
+<a name="l03047"></a>03047                 <span class="keywordflow">return</span>;
+<a name="l03048"></a>03048         }
+<a name="l03049"></a>03049 
+<a name="l03050"></a>03050         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"diepctl%d=%0x\n"</span>, epnum,
+<a name="l03051"></a>03051                     dwc_read_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[epnum]-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#53a5adb977e2aec66d4902c6ba293216">diepctl</a>));
+<a name="l03052"></a>03052         dieptsiz.<a class="code" href="uniondeptsiz__data.html#10c2b2ba8b419b0a766430a59befbbe0">d32</a> = dwc_read_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[epnum]-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#88f637b5a4e8a0c6bc87d157072255dd">dieptsiz</a>);
+<a name="l03053"></a>03053 
+<a name="l03054"></a>03054         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#2bf62a567355d1ea38814714bd7b57ec">DBG_ANY</a>, <span class="stringliteral">"pktcnt=%d size=%d\n"</span>,
+<a name="l03055"></a>03055                     dieptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#bbd89e812371e5b555bb82373f3643d9">pktcnt</a>, dieptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#cf06327d851e7cfe5c442b29bf2d6fa4">xfersize</a>);
+<a name="l03056"></a>03056 
+<a name="l03057"></a>03057         <span class="keywordflow">if</span> (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#cce0e089118d8bf7c6278c21ded70d5a">stopped</a>) {
+<a name="l03058"></a>03058                 <span class="comment">/* Flush the Tx FIFO */</span>
+<a name="l03059"></a>03059                 <a class="code" href="dwc__otg__cil_8c.html#039e387cd0e0282727da3c5a36f4cdda">dwc_otg_flush_tx_fifo</a>(core_if, dwc_ep-&gt;<a class="code" href="structdwc__ep.html#ffa14f48094778143353b845b5d238cd">tx_fifo_num</a>);
+<a name="l03060"></a>03060                 <span class="comment">/* Clear the Global IN NP NAK */</span>
+<a name="l03061"></a>03061                 dctl.<a class="code" href="uniondctl__data.html#f49aadfd7ad95b570115b3c245b1729e">d32</a> = 0;
+<a name="l03062"></a>03062                 dctl.<a class="code" href="uniondctl__data.html#a3abfa6d609d9864f1f65712b409d4d3">b</a>.<a class="code" href="uniondctl__data.html#6feecf1184cd67b8b8ede2e2030a5dba">cgnpinnak</a> = 1;
+<a name="l03063"></a>03063                 dwc_modify_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#3779c2fc508920a831a59e696a8fa785">dctl</a>, dctl.<a class="code" href="uniondctl__data.html#f49aadfd7ad95b570115b3c245b1729e">d32</a>, 0);
+<a name="l03064"></a>03064                 <span class="comment">/* Restart the transaction */</span>
+<a name="l03065"></a>03065                 <span class="keywordflow">if</span> (dieptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#bbd89e812371e5b555bb82373f3643d9">pktcnt</a> != 0 || dieptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#cf06327d851e7cfe5c442b29bf2d6fa4">xfersize</a> != 0) {
+<a name="l03066"></a>03066                         <a class="code" href="dwc__otg__pcd__intr_8c.html#ed405cebf67cd1a89efd15a2935c8cef">restart_transfer</a>(pcd, epnum);
+<a name="l03067"></a>03067                 }
+<a name="l03068"></a>03068         } <span class="keywordflow">else</span> {
+<a name="l03069"></a>03069                 <span class="comment">/* Restart the transaction */</span>
+<a name="l03070"></a>03070                 <span class="keywordflow">if</span> (dieptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#bbd89e812371e5b555bb82373f3643d9">pktcnt</a> != 0 || dieptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#cf06327d851e7cfe5c442b29bf2d6fa4">xfersize</a> != 0) {
+<a name="l03071"></a>03071                         <a class="code" href="dwc__otg__pcd__intr_8c.html#ed405cebf67cd1a89efd15a2935c8cef">restart_transfer</a>(pcd, epnum);
+<a name="l03072"></a>03072                 }
+<a name="l03073"></a>03073                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#2bf62a567355d1ea38814714bd7b57ec">DBG_ANY</a>, <span class="stringliteral">"STOPPED!!!\n"</span>);
+<a name="l03074"></a>03074         }
+<a name="l03075"></a>03075 }
+<a name="l03076"></a>03076 
+<a name="l03080"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#65d4f747d13e368916ee0e16d202119b">03080</a> <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd__intr_8c.html#65d4f747d13e368916ee0e16d202119b">handle_in_ep_timeout_intr</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd,
+<a name="l03081"></a>03081                                              <span class="keyword">const</span> uint32_t epnum)
+<a name="l03082"></a>03082 {
+<a name="l03083"></a>03083         <a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if = <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd);
+<a name="l03084"></a>03084         <a class="code" href="structdwc__otg__dev__if.html">dwc_otg_dev_if_t</a> *dev_if = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>;
+<a name="l03085"></a>03085 
+<a name="l03086"></a>03086 <span class="preprocessor">#ifdef DEBUG</span>
+<a name="l03087"></a>03087 <span class="preprocessor"></span>        <a class="code" href="uniondeptsiz__data.html">deptsiz_data_t</a> dieptsiz = {.d32 = 0 };
+<a name="l03088"></a>03088         uint32_t num = 0;
+<a name="l03089"></a>03089 <span class="preprocessor">#endif</span>
+<a name="l03090"></a>03090 <span class="preprocessor"></span>        <a class="code" href="uniondctl__data.html">dctl_data_t</a> dctl = {.d32 = 0 };
+<a name="l03091"></a>03091         <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>;
+<a name="l03092"></a>03092 
+<a name="l03093"></a>03093         <a class="code" href="uniongintmsk__data.html">gintmsk_data_t</a> intr_mask = {.d32 = 0 };
+<a name="l03094"></a>03094 
+<a name="l03095"></a>03095         <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a> = <a class="code" href="dwc__otg__pcd__intr_8c.html#cc3f2f1ae0ab7d33903a1d0d9097c04e">get_in_ep</a>(pcd, epnum);
+<a name="l03096"></a>03096 
+<a name="l03097"></a>03097         <span class="comment">/* Disable the NP Tx Fifo Empty Interrrupt */</span>
+<a name="l03098"></a>03098         <span class="keywordflow">if</span> (!core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a>) {
+<a name="l03099"></a>03099                 intr_mask.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#2c395e7bef31a4d9b2d1a3257c601be4">nptxfempty</a> = 1;
+<a name="l03100"></a>03100                 dwc_modify_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#48827c76da2c6b18f369e2f2483cc4b6">gintmsk</a>,
+<a name="l03101"></a>03101                                  intr_mask.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a>, 0);
+<a name="l03102"></a>03102         }
+<a name="l03105"></a>03105         <span class="comment">/*</span>
+<a name="l03106"></a>03106 <span class="comment">         * Non-periodic EP</span>
+<a name="l03107"></a>03107 <span class="comment">         */</span>
+<a name="l03108"></a>03108         <span class="comment">/* Enable the Global IN NAK Effective Interrupt */</span>
+<a name="l03109"></a>03109         intr_mask.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#83a6fb180ef8b18faf8d02ba8b50c841">ginnakeff</a> = 1;
+<a name="l03110"></a>03110         dwc_modify_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#48827c76da2c6b18f369e2f2483cc4b6">gintmsk</a>, 0, intr_mask.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a>);
+<a name="l03111"></a>03111 
+<a name="l03112"></a>03112         <span class="comment">/* Set Global IN NAK */</span>
+<a name="l03113"></a>03113         dctl.<a class="code" href="uniondctl__data.html#a3abfa6d609d9864f1f65712b409d4d3">b</a>.<a class="code" href="uniondctl__data.html#2349dad5149cd3fcfd8fe3abcd77c32e">sgnpinnak</a> = 1;
+<a name="l03114"></a>03114         dwc_modify_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#3779c2fc508920a831a59e696a8fa785">dctl</a>, dctl.<a class="code" href="uniondctl__data.html#f49aadfd7ad95b570115b3c245b1729e">d32</a>, dctl.<a class="code" href="uniondctl__data.html#f49aadfd7ad95b570115b3c245b1729e">d32</a>);
+<a name="l03115"></a>03115 
+<a name="l03116"></a>03116         <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#cce0e089118d8bf7c6278c21ded70d5a">stopped</a> = 1;
+<a name="l03117"></a>03117 
+<a name="l03118"></a>03118 <span class="preprocessor">#ifdef DEBUG</span>
+<a name="l03119"></a>03119 <span class="preprocessor"></span>        dieptsiz.<a class="code" href="uniondeptsiz__data.html#10c2b2ba8b419b0a766430a59befbbe0">d32</a> = dwc_read_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[num]-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#88f637b5a4e8a0c6bc87d157072255dd">dieptsiz</a>);
+<a name="l03120"></a>03120         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#2bf62a567355d1ea38814714bd7b57ec">DBG_ANY</a>, <span class="stringliteral">"pktcnt=%d size=%d\n"</span>,
+<a name="l03121"></a>03121                     dieptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#bbd89e812371e5b555bb82373f3643d9">pktcnt</a>, dieptsiz.<a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>.<a class="code" href="uniondeptsiz__data.html#cf06327d851e7cfe5c442b29bf2d6fa4">xfersize</a>);
+<a name="l03122"></a>03122 <span class="preprocessor">#endif</span>
+<a name="l03123"></a>03123 <span class="preprocessor"></span>
+<a name="l03124"></a>03124 <span class="preprocessor">#ifdef DISABLE_PERIODIC_EP</span>
+<a name="l03125"></a>03125 <span class="preprocessor"></span>        <span class="comment">/*</span>
+<a name="l03126"></a>03126 <span class="comment">         * Set the NAK bit for this EP to</span>
+<a name="l03127"></a>03127 <span class="comment">         * start the disable process.</span>
+<a name="l03128"></a>03128 <span class="comment">         */</span>
+<a name="l03129"></a>03129         diepctl.d32 = 0;
+<a name="l03130"></a>03130         diepctl.b.snak = 1;
+<a name="l03131"></a>03131         dwc_modify_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[num]-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#53a5adb977e2aec66d4902c6ba293216">diepctl</a>, diepctl.d32,
+<a name="l03132"></a>03132                          diepctl.d32);
+<a name="l03133"></a>03133         <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#510fcd32761716abec5a35594a3d3ad3">disabling</a> = 1;
+<a name="l03134"></a>03134         <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#cce0e089118d8bf7c6278c21ded70d5a">stopped</a> = 1;
+<a name="l03135"></a>03135 <span class="preprocessor">#endif</span>
+<a name="l03136"></a>03136 <span class="preprocessor"></span>}
+<a name="l03137"></a>03137 
+<a name="l03141"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#273ccc8e8cdb9e2075844f2f922b53bf">03141</a> <span class="keyword">static</span> <span class="keyword">inline</span> int32_t <a class="code" href="dwc__otg__pcd__intr_8c.html#273ccc8e8cdb9e2075844f2f922b53bf">handle_in_ep_nak_intr</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd,
+<a name="l03142"></a>03142                                             <span class="keyword">const</span> uint32_t epnum)
+<a name="l03143"></a>03143 {
+<a name="l03145"></a>03145         <a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if;
+<a name="l03146"></a>03146         <a class="code" href="uniondiepint__data.html">diepmsk_data_t</a> intr_mask = {.d32 = 0 };
+<a name="l03147"></a>03147 
+<a name="l03148"></a>03148         DWC_PRINTF(<span class="stringliteral">"INTERRUPT Handler not implemented for %s\n"</span>, <span class="stringliteral">"IN EP NAK"</span>);
+<a name="l03149"></a>03149         core_if = <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd);
+<a name="l03150"></a>03150         intr_mask.<a class="code" href="uniondiepint__data.html#48d2a745e0ec983a47b35b0428b0437d">b</a>.<a class="code" href="uniondiepint__data.html#3ade814b2bef3085bb6fa32e94ea1aac">nak</a> = 1;
+<a name="l03151"></a>03151 
+<a name="l03152"></a>03152         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5675c8d8dd7df746fda9157dc39ba5c2">multiproc_int_enable</a>) {
+<a name="l03153"></a>03153                 dwc_modify_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;
+<a name="l03154"></a>03154                                  diepeachintmsk[epnum], intr_mask.<a class="code" href="uniondiepint__data.html#7d2c24507663bf96c280c57fbf544ef7">d32</a>, 0);
+<a name="l03155"></a>03155         } <span class="keywordflow">else</span> {
+<a name="l03156"></a>03156                 dwc_modify_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#02e44cb182548d78c5b7d27929ca5f11">diepmsk</a>,
+<a name="l03157"></a>03157                                  intr_mask.<a class="code" href="uniondiepint__data.html#7d2c24507663bf96c280c57fbf544ef7">d32</a>, 0);
+<a name="l03158"></a>03158         }
+<a name="l03159"></a>03159 
+<a name="l03160"></a>03160         <span class="keywordflow">return</span> 1;
+<a name="l03161"></a>03161 }
+<a name="l03162"></a>03162 
+<a name="l03166"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#42aef7ea134cccf7cdb53e7e1428bc4a">03166</a> <span class="keyword">static</span> <span class="keyword">inline</span> int32_t <a class="code" href="dwc__otg__pcd__intr_8c.html#42aef7ea134cccf7cdb53e7e1428bc4a">handle_out_ep_babble_intr</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd,
+<a name="l03167"></a>03167                                                 <span class="keyword">const</span> uint32_t epnum)
+<a name="l03168"></a>03168 {
+<a name="l03170"></a>03170         <a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if;
+<a name="l03171"></a>03171         <a class="code" href="uniondoepint__data.html">doepmsk_data_t</a> intr_mask = {.d32 = 0 };
+<a name="l03172"></a>03172 
+<a name="l03173"></a>03173         DWC_PRINTF(<span class="stringliteral">"INTERRUPT Handler not implemented for %s\n"</span>,
+<a name="l03174"></a>03174                    <span class="stringliteral">"OUT EP Babble"</span>);
+<a name="l03175"></a>03175         core_if = <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd);
+<a name="l03176"></a>03176         intr_mask.<a class="code" href="uniondoepint__data.html#9e966d9f85589f278dc2c0d0c7833856">b</a>.<a class="code" href="uniondoepint__data.html#c555371bda41092d89992523563dadbb">babble</a> = 1;
+<a name="l03177"></a>03177 
+<a name="l03178"></a>03178         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5675c8d8dd7df746fda9157dc39ba5c2">multiproc_int_enable</a>) {
+<a name="l03179"></a>03179                 dwc_modify_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;
+<a name="l03180"></a>03180                                  doepeachintmsk[epnum], intr_mask.<a class="code" href="uniondoepint__data.html#94f8c8fc116b430565f9322e3621b3a5">d32</a>, 0);
+<a name="l03181"></a>03181         } <span class="keywordflow">else</span> {
+<a name="l03182"></a>03182                 dwc_modify_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#d6947be9d84a1d87156f81a10ebb036b">doepmsk</a>,
+<a name="l03183"></a>03183                                  intr_mask.<a class="code" href="uniondoepint__data.html#94f8c8fc116b430565f9322e3621b3a5">d32</a>, 0);
+<a name="l03184"></a>03184         }
+<a name="l03185"></a>03185 
+<a name="l03186"></a>03186         <span class="keywordflow">return</span> 1;
+<a name="l03187"></a>03187 }
+<a name="l03188"></a>03188 
+<a name="l03192"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#252929e585c84eaf0485869cd7734244">03192</a> <span class="keyword">static</span> <span class="keyword">inline</span> int32_t <a class="code" href="dwc__otg__pcd__intr_8c.html#252929e585c84eaf0485869cd7734244">handle_out_ep_nak_intr</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd,
+<a name="l03193"></a>03193                                              <span class="keyword">const</span> uint32_t epnum)
+<a name="l03194"></a>03194 {
+<a name="l03196"></a>03196         <a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if;
+<a name="l03197"></a>03197         <a class="code" href="uniondoepint__data.html">doepmsk_data_t</a> intr_mask = {.d32 = 0 };
+<a name="l03198"></a>03198 
+<a name="l03199"></a>03199         DWC_PRINTF(<span class="stringliteral">"INTERRUPT Handler not implemented for %s\n"</span>, <span class="stringliteral">"OUT EP NAK"</span>);
+<a name="l03200"></a>03200         core_if = <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd);
+<a name="l03201"></a>03201         intr_mask.<a class="code" href="uniondoepint__data.html#9e966d9f85589f278dc2c0d0c7833856">b</a>.<a class="code" href="uniondoepint__data.html#2ac99fbbb1bcf135d5db41e096e8b95b">nak</a> = 1;
+<a name="l03202"></a>03202 
+<a name="l03203"></a>03203         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5675c8d8dd7df746fda9157dc39ba5c2">multiproc_int_enable</a>) {
+<a name="l03204"></a>03204                 dwc_modify_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;
+<a name="l03205"></a>03205                                  doepeachintmsk[epnum], intr_mask.<a class="code" href="uniondoepint__data.html#94f8c8fc116b430565f9322e3621b3a5">d32</a>, 0);
+<a name="l03206"></a>03206         } <span class="keywordflow">else</span> {
+<a name="l03207"></a>03207                 dwc_modify_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#d6947be9d84a1d87156f81a10ebb036b">doepmsk</a>,
+<a name="l03208"></a>03208                                  intr_mask.<a class="code" href="uniondoepint__data.html#94f8c8fc116b430565f9322e3621b3a5">d32</a>, 0);
+<a name="l03209"></a>03209         }
+<a name="l03210"></a>03210 
+<a name="l03211"></a>03211         <span class="keywordflow">return</span> 1;
+<a name="l03212"></a>03212 }
+<a name="l03213"></a>03213 
+<a name="l03217"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#926d9068c1950cc406d50828e72a31db">03217</a> <span class="keyword">static</span> <span class="keyword">inline</span> int32_t <a class="code" href="dwc__otg__pcd__intr_8c.html#926d9068c1950cc406d50828e72a31db">handle_out_ep_nyet_intr</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd,
+<a name="l03218"></a>03218                                               <span class="keyword">const</span> uint32_t epnum)
+<a name="l03219"></a>03219 {
+<a name="l03221"></a>03221         <a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if;
+<a name="l03222"></a>03222         <a class="code" href="uniondoepint__data.html">doepmsk_data_t</a> intr_mask = {.d32 = 0 };
+<a name="l03223"></a>03223 
+<a name="l03224"></a>03224         DWC_PRINTF(<span class="stringliteral">"INTERRUPT Handler not implemented for %s\n"</span>, <span class="stringliteral">"OUT EP NYET"</span>);
+<a name="l03225"></a>03225         core_if = <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd);
+<a name="l03226"></a>03226         intr_mask.<a class="code" href="uniondoepint__data.html#9e966d9f85589f278dc2c0d0c7833856">b</a>.<a class="code" href="uniondoepint__data.html#f35ad8ba20b8941b6ad00dc75586454f">nyet</a> = 1;
+<a name="l03227"></a>03227 
+<a name="l03228"></a>03228         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5675c8d8dd7df746fda9157dc39ba5c2">multiproc_int_enable</a>) {
+<a name="l03229"></a>03229                 dwc_modify_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;
+<a name="l03230"></a>03230                                  doepeachintmsk[epnum], intr_mask.<a class="code" href="uniondoepint__data.html#94f8c8fc116b430565f9322e3621b3a5">d32</a>, 0);
+<a name="l03231"></a>03231         } <span class="keywordflow">else</span> {
+<a name="l03232"></a>03232                 dwc_modify_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;<a class="code" href="structdwc__otg__dev__global__regs.html#d6947be9d84a1d87156f81a10ebb036b">doepmsk</a>,
+<a name="l03233"></a>03233                                  intr_mask.<a class="code" href="uniondoepint__data.html#94f8c8fc116b430565f9322e3621b3a5">d32</a>, 0);
+<a name="l03234"></a>03234         }
+<a name="l03235"></a>03235 
+<a name="l03236"></a>03236         <span class="keywordflow">return</span> 1;
+<a name="l03237"></a>03237 }
+<a name="l03238"></a>03238 
+<a name="l03255"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#321d4a511db985443b132c044fc2d69e">03255</a> <span class="keyword">static</span> int32_t <a class="code" href="dwc__otg__pcd__intr_8c.html#321d4a511db985443b132c044fc2d69e">dwc_otg_pcd_handle_in_ep_intr</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd)
+<a name="l03256"></a>03256 {
+<a name="l03257"></a>03257 <span class="preprocessor">#define CLEAR_IN_EP_INTR(__core_if,__epnum,__intr) \</span>
+<a name="l03258"></a>03258 <span class="preprocessor">do { \</span>
+<a name="l03259"></a>03259 <span class="preprocessor">                diepint_data_t diepint = {.d32=0}; \</span>
+<a name="l03260"></a>03260 <span class="preprocessor">                diepint.b.__intr = 1; \</span>
+<a name="l03261"></a>03261 <span class="preprocessor">                dwc_write_reg32(&amp;__core_if-&gt;dev_if-&gt;in_ep_regs[__epnum]-&gt;diepint, \</span>
+<a name="l03262"></a>03262 <span class="preprocessor">                diepint.d32); \</span>
+<a name="l03263"></a>03263 <span class="preprocessor">} while (0)</span>
+<a name="l03264"></a>03264 <span class="preprocessor"></span>
+<a name="l03265"></a>03265         <a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if = <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd);
+<a name="l03266"></a>03266         <a class="code" href="structdwc__otg__dev__if.html">dwc_otg_dev_if_t</a> *dev_if = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>;
+<a name="l03267"></a>03267         <a class="code" href="uniondiepint__data.html">diepint_data_t</a> diepint = {.d32 = 0 };
+<a name="l03268"></a>03268         <a class="code" href="uniondctl__data.html">dctl_data_t</a> dctl = {.d32 = 0 };
+<a name="l03269"></a>03269         <a class="code" href="uniondepctl__data.html">depctl_data_t</a> depctl = {.d32 = 0 };
+<a name="l03270"></a>03270         uint32_t ep_intr;
+<a name="l03271"></a>03271         uint32_t epnum = 0;
+<a name="l03272"></a>03272         <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>;
+<a name="l03273"></a>03273         <a class="code" href="structdwc__ep.html">dwc_ep_t</a> *<a class="code" href="structdwc__ep.html">dwc_ep</a>;
+<a name="l03274"></a>03274         <a class="code" href="uniongintmsk__data.html">gintmsk_data_t</a> intr_mask = {.d32 = 0 };
+<a name="l03275"></a>03275 
+<a name="l03276"></a>03276         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"%s(%p)\n"</span>, __func__, pcd);
+<a name="l03277"></a>03277 
+<a name="l03278"></a>03278         <span class="comment">/* Read in the device interrupt bits */</span>
+<a name="l03279"></a>03279         ep_intr = <a class="code" href="dwc__otg__cil_8h.html#574c9a2a3f7fa76d93e735daf2c64e2f">dwc_otg_read_dev_all_in_ep_intr</a>(core_if);
+<a name="l03280"></a>03280 
+<a name="l03281"></a>03281         <span class="comment">/* Service the Device IN interrupts for each endpoint */</span>
+<a name="l03282"></a>03282         <span class="keywordflow">while</span> (ep_intr) {
+<a name="l03283"></a>03283                 <span class="keywordflow">if</span> (ep_intr &amp; 0x1) {
+<a name="l03284"></a>03284                         uint32_t empty_msk;
+<a name="l03285"></a>03285                         <span class="comment">/* Get EP pointer */</span>
+<a name="l03286"></a>03286                         <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a> = <a class="code" href="dwc__otg__pcd__intr_8c.html#cc3f2f1ae0ab7d33903a1d0d9097c04e">get_in_ep</a>(pcd, epnum);
+<a name="l03287"></a>03287                         dwc_ep = &amp;<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>;
+<a name="l03288"></a>03288 
+<a name="l03289"></a>03289                         depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a> =
+<a name="l03290"></a>03290                             dwc_read_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[epnum]-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#53a5adb977e2aec66d4902c6ba293216">diepctl</a>);
+<a name="l03291"></a>03291                         empty_msk =
+<a name="l03292"></a>03292                             dwc_read_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>-&gt;
+<a name="l03293"></a>03293                                            dtknqr4_fifoemptymsk);
+<a name="l03294"></a>03294 
+<a name="l03295"></a>03295                         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>,
+<a name="l03296"></a>03296                                     <span class="stringliteral">"IN EP INTERRUPT - %d\nepmty_msk - %8x  diepctl - %8x\n"</span>,
+<a name="l03297"></a>03297                                     epnum, empty_msk, depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a>);
+<a name="l03298"></a>03298 
+<a name="l03299"></a>03299                         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>,
+<a name="l03300"></a>03300                                     <span class="stringliteral">"EP%d-%s: type=%d, mps=%d\n"</span>,
+<a name="l03301"></a>03301                                     dwc_ep-&gt;<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a>, (dwc_ep-&gt;<a class="code" href="structdwc__ep.html#b882b6b7c857100ed20600e94ea37760">is_in</a> ? <span class="stringliteral">"IN"</span> : <span class="stringliteral">"OUT"</span>),
+<a name="l03302"></a>03302                                     dwc_ep-&gt;<a class="code" href="structdwc__ep.html#17b10677bd9b0a1d612dd4ce2fb0eb0f">type</a>, dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a>);
+<a name="l03303"></a>03303 
+<a name="l03304"></a>03304                         diepint.<a class="code" href="uniondiepint__data.html#7d2c24507663bf96c280c57fbf544ef7">d32</a> =
+<a name="l03305"></a>03305                             <a class="code" href="dwc__otg__cil_8h.html#d14e93e73613cfa13336db4da4ee2f20">dwc_otg_read_dev_in_ep_intr</a>(core_if, dwc_ep);
+<a name="l03306"></a>03306 
+<a name="l03307"></a>03307                         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>,
+<a name="l03308"></a>03308                                     <span class="stringliteral">"EP %d Interrupt Register - 0x%x\n"</span>, epnum,
+<a name="l03309"></a>03309                                     diepint.<a class="code" href="uniondiepint__data.html#7d2c24507663bf96c280c57fbf544ef7">d32</a>);
+<a name="l03310"></a>03310                         <span class="comment">/* Transfer complete */</span>
+<a name="l03311"></a>03311                         <span class="keywordflow">if</span> (diepint.<a class="code" href="uniondiepint__data.html#48d2a745e0ec983a47b35b0428b0437d">b</a>.<a class="code" href="uniondiepint__data.html#56e1252841323973e0ada12cc89059c9">xfercompl</a>) {
+<a name="l03312"></a>03312                                 <span class="comment">/* Disable the NP Tx FIFO Empty</span>
+<a name="l03313"></a>03313 <span class="comment">                                 * Interrrupt */</span>
+<a name="l03314"></a>03314                                 <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#31d08d1ebcd290b05139b0fcd24048ec">en_multiple_tx_fifo</a> == 0) {
+<a name="l03315"></a>03315                                         intr_mask.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#2c395e7bef31a4d9b2d1a3257c601be4">nptxfempty</a> = 1;
+<a name="l03316"></a>03316                                         dwc_modify_reg32(&amp;core_if-&gt;
+<a name="l03317"></a>03317                                                          core_global_regs-&gt;
+<a name="l03318"></a>03318                                                          gintmsk, intr_mask.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a>,
+<a name="l03319"></a>03319                                                          0);
+<a name="l03320"></a>03320                                 } <span class="keywordflow">else</span> {
+<a name="l03321"></a>03321                                         <span class="comment">/* Disable the Tx FIFO Empty Interrupt for this EP */</span>
+<a name="l03322"></a>03322                                         uint32_t fifoemptymsk =
+<a name="l03323"></a>03323                                             0x1 &lt;&lt; dwc_ep-&gt;<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a>;
+<a name="l03324"></a>03324                                         dwc_modify_reg32(&amp;core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;
+<a name="l03325"></a>03325                                                          dev_global_regs-&gt;
+<a name="l03326"></a>03326                                                          dtknqr4_fifoemptymsk,
+<a name="l03327"></a>03327                                                          fifoemptymsk, 0);
+<a name="l03328"></a>03328                                 }
+<a name="l03329"></a>03329                                 <span class="comment">/* Clear the bit in DIEPINTn for this interrupt */</span>
+<a name="l03330"></a>03330                                 CLEAR_IN_EP_INTR(core_if, epnum, xfercompl);
+<a name="l03331"></a>03331 
+<a name="l03332"></a>03332                                 <span class="comment">/* Complete the transfer */</span>
+<a name="l03333"></a>03333                                 <span class="keywordflow">if</span> (epnum == 0) {
+<a name="l03334"></a>03334                                         <a class="code" href="dwc__otg__pcd__intr_8c.html#4991119b51de03163a3677c36bc0ee3b">handle_ep0</a>(pcd);
+<a name="l03335"></a>03335                                 }
+<a name="l03336"></a>03336 <span class="preprocessor">#ifdef DWC_EN_ISOC</span>
+<a name="l03337"></a>03337 <span class="preprocessor"></span>                                <span class="keywordflow">else</span> <span class="keywordflow">if</span> (dwc_ep-&gt;<a class="code" href="structdwc__ep.html#17b10677bd9b0a1d612dd4ce2fb0eb0f">type</a> == <a class="code" href="dwc__otg__cil_8h.html#152a3a5e1433bd2197672f0b5105e7a4">DWC_OTG_EP_TYPE_ISOC</a>) {
+<a name="l03338"></a>03338                                         <span class="keywordflow">if</span> (!<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#cce0e089118d8bf7c6278c21ded70d5a">stopped</a>)
+<a name="l03339"></a>03339                                                 <a class="code" href="dwc__otg__pcd__intr_8c.html#05965765a43225780ae08f2c3928f782">complete_iso_ep</a>(pcd, <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>);
+<a name="l03340"></a>03340                                 }
+<a name="l03341"></a>03341 <span class="preprocessor">#endif                          </span><span class="comment">/* DWC_EN_ISOC */</span>
+<a name="l03342"></a>03342                                 <span class="keywordflow">else</span> {
+<a name="l03343"></a>03343 
+<a name="l03344"></a>03344                                         <a class="code" href="dwc__otg__pcd__intr_8c.html#c77f277130ba55b19100bde598da7d85">complete_ep</a>(<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>);
+<a name="l03345"></a>03345                                 }
+<a name="l03346"></a>03346                         }
+<a name="l03347"></a>03347                         <span class="comment">/* Endpoint disable      */</span>
+<a name="l03348"></a>03348                         <span class="keywordflow">if</span> (diepint.<a class="code" href="uniondiepint__data.html#48d2a745e0ec983a47b35b0428b0437d">b</a>.<a class="code" href="uniondiepint__data.html#3a649b75195fb5b26135d75b03cf561d">epdisabled</a>) {
+<a name="l03349"></a>03349                                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#2bf62a567355d1ea38814714bd7b57ec">DBG_ANY</a>, <span class="stringliteral">"EP%d IN disabled\n"</span>,
+<a name="l03350"></a>03350                                             epnum);
+<a name="l03351"></a>03351                                 <a class="code" href="dwc__otg__pcd__intr_8c.html#6c9df42abc5cb6f676a44918207c91b7">handle_in_ep_disable_intr</a>(pcd, epnum);
+<a name="l03352"></a>03352 
+<a name="l03353"></a>03353                                 <span class="comment">/* Clear the bit in DIEPINTn for this interrupt */</span>
+<a name="l03354"></a>03354                                 CLEAR_IN_EP_INTR(core_if, epnum, epdisabled);
+<a name="l03355"></a>03355                         }
+<a name="l03356"></a>03356                         <span class="comment">/* AHB Error */</span>
+<a name="l03357"></a>03357                         <span class="keywordflow">if</span> (diepint.<a class="code" href="uniondiepint__data.html#48d2a745e0ec983a47b35b0428b0437d">b</a>.<a class="code" href="uniondiepint__data.html#6d57fa84f687bc4f05013c1e1a7edf29">ahberr</a>) {
+<a name="l03358"></a>03358                                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#2bf62a567355d1ea38814714bd7b57ec">DBG_ANY</a>, <span class="stringliteral">"EP%d IN AHB Error\n"</span>,
+<a name="l03359"></a>03359                                             epnum);
+<a name="l03360"></a>03360                                 <span class="comment">/* Clear the bit in DIEPINTn for this interrupt */</span>
+<a name="l03361"></a>03361                                 CLEAR_IN_EP_INTR(core_if, epnum, ahberr);
+<a name="l03362"></a>03362                         }
+<a name="l03363"></a>03363                         <span class="comment">/* TimeOUT Handshake (non-ISOC IN EPs) */</span>
+<a name="l03364"></a>03364                         <span class="keywordflow">if</span> (diepint.<a class="code" href="uniondiepint__data.html#48d2a745e0ec983a47b35b0428b0437d">b</a>.<a class="code" href="uniondiepint__data.html#2513e8eef259c711e9a139cb2631b142">timeout</a>) {
+<a name="l03365"></a>03365                                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#2bf62a567355d1ea38814714bd7b57ec">DBG_ANY</a>, <span class="stringliteral">"EP%d IN Time-out\n"</span>,
+<a name="l03366"></a>03366                                             epnum);
+<a name="l03367"></a>03367                                 <a class="code" href="dwc__otg__pcd__intr_8c.html#65d4f747d13e368916ee0e16d202119b">handle_in_ep_timeout_intr</a>(pcd, epnum);
+<a name="l03368"></a>03368 
+<a name="l03369"></a>03369                                 CLEAR_IN_EP_INTR(core_if, epnum, timeout);
+<a name="l03370"></a>03370                         }
+<a name="l03372"></a>03372                         <span class="keywordflow">if</span> (diepint.<a class="code" href="uniondiepint__data.html#48d2a745e0ec983a47b35b0428b0437d">b</a>.<a class="code" href="uniondiepint__data.html#7c9961f17328bbc25ca39e7ec1891e16">intktxfemp</a>) {
+<a name="l03373"></a>03373                                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#2bf62a567355d1ea38814714bd7b57ec">DBG_ANY</a>,
+<a name="l03374"></a>03374                                             <span class="stringliteral">"EP%d IN TKN TxFifo Empty\n"</span>,
+<a name="l03375"></a>03375                                             epnum);
+<a name="l03376"></a>03376                                 <span class="keywordflow">if</span> (!<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#cce0e089118d8bf7c6278c21ded70d5a">stopped</a> &amp;&amp; epnum != 0) {
+<a name="l03377"></a>03377 
+<a name="l03378"></a>03378                                         <a class="code" href="uniondiepint__data.html">diepmsk_data_t</a> diepmsk = {.d32 = 0 };
+<a name="l03379"></a>03379                                         diepmsk.<a class="code" href="uniondiepint__data.html#48d2a745e0ec983a47b35b0428b0437d">b</a>.<a class="code" href="uniondiepint__data.html#7c9961f17328bbc25ca39e7ec1891e16">intktxfemp</a> = 1;
+<a name="l03380"></a>03380 
+<a name="l03381"></a>03381                                         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5675c8d8dd7df746fda9157dc39ba5c2">multiproc_int_enable</a>) {
+<a name="l03382"></a>03382                                                 dwc_modify_reg32(&amp;dev_if-&gt;
+<a name="l03383"></a>03383                                                                  dev_global_regs-&gt;
+<a name="l03384"></a>03384                                                                  diepeachintmsk
+<a name="l03385"></a>03385                                                                  [epnum],
+<a name="l03386"></a>03386                                                                  diepmsk.<a class="code" href="uniondiepint__data.html#7d2c24507663bf96c280c57fbf544ef7">d32</a>,
+<a name="l03387"></a>03387                                                                  0);
+<a name="l03388"></a>03388                                         } <span class="keywordflow">else</span> {
+<a name="l03389"></a>03389                                                 dwc_modify_reg32(&amp;dev_if-&gt;
+<a name="l03390"></a>03390                                                                  dev_global_regs-&gt;
+<a name="l03391"></a>03391                                                                  diepmsk,
+<a name="l03392"></a>03392                                                                  diepmsk.<a class="code" href="uniondiepint__data.html#7d2c24507663bf96c280c57fbf544ef7">d32</a>,
+<a name="l03393"></a>03393                                                                  0);
+<a name="l03394"></a>03394                                         }
+<a name="l03395"></a>03395                                 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a>
+<a name="l03396"></a>03396                                            &amp;&amp; epnum == 0
+<a name="l03397"></a>03397                                            &amp;&amp; pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#8f6963b3fb9ab83048c4c0697c90382a">ep0state</a> ==
+<a name="l03398"></a>03398                                            EP0_OUT_STATUS_PHASE) {
+<a name="l03399"></a>03399                                         <span class="comment">// EP0 IN set STALL</span>
+<a name="l03400"></a>03400                                         depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a> =
+<a name="l03401"></a>03401                                             dwc_read_reg32(&amp;dev_if-&gt;
+<a name="l03402"></a>03402                                                            in_ep_regs[epnum]-&gt;
+<a name="l03403"></a>03403                                                            diepctl);
+<a name="l03404"></a>03404 
+<a name="l03405"></a>03405                                         <span class="comment">/* set the disable and stall bits */</span>
+<a name="l03406"></a>03406                                         <span class="keywordflow">if</span> (depctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#337ceb41a9e0735e144e684b1f9e5368">epena</a>) {
+<a name="l03407"></a>03407                                                 depctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#4d76ba4ebd506d3175ec5cdc0d811654">epdis</a> = 1;
+<a name="l03408"></a>03408                                         }
+<a name="l03409"></a>03409                                         depctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#f7ad1bcf91d28b8a4aa8d3a343dd83e4">stall</a> = 1;
+<a name="l03410"></a>03410                                         dwc_write_reg32(&amp;dev_if-&gt;
+<a name="l03411"></a>03411                                                         in_ep_regs[epnum]-&gt;
+<a name="l03412"></a>03412                                                         diepctl, depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a>);
+<a name="l03413"></a>03413                                 }
+<a name="l03414"></a>03414                                 CLEAR_IN_EP_INTR(core_if, epnum, intktxfemp);
+<a name="l03415"></a>03415                         }
+<a name="l03417"></a>03417                         <span class="keywordflow">if</span> (diepint.<a class="code" href="uniondiepint__data.html#48d2a745e0ec983a47b35b0428b0437d">b</a>.<a class="code" href="uniondiepint__data.html#103fb29d954cf12d33f7ebe6009f9a46">intknepmis</a>) {
+<a name="l03418"></a>03418                                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#2bf62a567355d1ea38814714bd7b57ec">DBG_ANY</a>,
+<a name="l03419"></a>03419                                             <span class="stringliteral">"EP%d IN TKN EP Mismatch\n"</span>, epnum);
+<a name="l03420"></a>03420                                 CLEAR_IN_EP_INTR(core_if, epnum, intknepmis);
+<a name="l03421"></a>03421                         }
+<a name="l03423"></a>03423                         <span class="keywordflow">if</span> (diepint.<a class="code" href="uniondiepint__data.html#48d2a745e0ec983a47b35b0428b0437d">b</a>.<a class="code" href="uniondiepint__data.html#9186a1106fe57e01ce720a50ceb5864f">inepnakeff</a>) {
+<a name="l03424"></a>03424                                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#2bf62a567355d1ea38814714bd7b57ec">DBG_ANY</a>,
+<a name="l03425"></a>03425                                             <span class="stringliteral">"EP%d IN EP NAK Effective\n"</span>,
+<a name="l03426"></a>03426                                             epnum);
+<a name="l03427"></a>03427                                 <span class="comment">/* Periodic EP */</span>
+<a name="l03428"></a>03428                                 <span class="keywordflow">if</span> (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#510fcd32761716abec5a35594a3d3ad3">disabling</a>) {
+<a name="l03429"></a>03429                                         depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a> = 0;
+<a name="l03430"></a>03430                                         depctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#ccf6e60ac8cabde8da36edb19504ba2b">snak</a> = 1;
+<a name="l03431"></a>03431                                         depctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#4d76ba4ebd506d3175ec5cdc0d811654">epdis</a> = 1;
+<a name="l03432"></a>03432                                         dwc_modify_reg32(&amp;dev_if-&gt;
+<a name="l03433"></a>03433                                                          in_ep_regs[epnum]-&gt;
+<a name="l03434"></a>03434                                                          diepctl, depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a>,
+<a name="l03435"></a>03435                                                          depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a>);
+<a name="l03436"></a>03436                                 }
+<a name="l03437"></a>03437                                 CLEAR_IN_EP_INTR(core_if, epnum, inepnakeff);
+<a name="l03438"></a>03438 
+<a name="l03439"></a>03439                         }
+<a name="l03440"></a>03440 
+<a name="l03442"></a>03442                         <span class="keywordflow">if</span> (diepint.<a class="code" href="uniondiepint__data.html#48d2a745e0ec983a47b35b0428b0437d">b</a>.<a class="code" href="uniondiepint__data.html#de84fb009990e97bfa46f825d5358429">emptyintr</a>) {
+<a name="l03443"></a>03443                                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#2bf62a567355d1ea38814714bd7b57ec">DBG_ANY</a>,
+<a name="l03444"></a>03444                                             <span class="stringliteral">"EP%d Tx FIFO Empty Intr \n"</span>,
+<a name="l03445"></a>03445                                             epnum);
+<a name="l03446"></a>03446                                 <a class="code" href="dwc__otg__pcd__intr_8c.html#5e53962e63763aa9df6400981b7d5354">write_empty_tx_fifo</a>(pcd, epnum);
+<a name="l03447"></a>03447 
+<a name="l03448"></a>03448                                 CLEAR_IN_EP_INTR(core_if, epnum, emptyintr);
+<a name="l03449"></a>03449 
+<a name="l03450"></a>03450                         }
+<a name="l03451"></a>03451 
+<a name="l03453"></a>03453                         <span class="keywordflow">if</span> (diepint.<a class="code" href="uniondiepint__data.html#48d2a745e0ec983a47b35b0428b0437d">b</a>.<a class="code" href="uniondiepint__data.html#2530c984ae3ebda73405d98080d8a57b">bna</a>) {
+<a name="l03454"></a>03454                                 CLEAR_IN_EP_INTR(core_if, epnum, bna);
+<a name="l03455"></a>03455                                 <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a>) {
+<a name="l03456"></a>03456 <span class="preprocessor">#ifdef DWC_EN_ISOC</span>
+<a name="l03457"></a>03457 <span class="preprocessor"></span>                                        <span class="keywordflow">if</span> (dwc_ep-&gt;<a class="code" href="structdwc__ep.html#17b10677bd9b0a1d612dd4ce2fb0eb0f">type</a> ==
+<a name="l03458"></a>03458                                             <a class="code" href="dwc__otg__cil_8h.html#152a3a5e1433bd2197672f0b5105e7a4">DWC_OTG_EP_TYPE_ISOC</a>) {
+<a name="l03459"></a>03459                                                 <span class="comment">/*</span>
+<a name="l03460"></a>03460 <span class="comment">                                                 * This checking is performed to prevent first "false" BNA </span>
+<a name="l03461"></a>03461 <span class="comment">                                                 * handling occuring right after reconnect </span>
+<a name="l03462"></a>03462 <span class="comment">                                                 */</span>
+<a name="l03463"></a>03463                                                 <span class="keywordflow">if</span> (dwc_ep-&gt;<a class="code" href="structdwc__ep.html#1e9f4d08454c973c17acb3e52a2c3689">next_frame</a> !=
+<a name="l03464"></a>03464                                                     0xffffffff)
+<a name="l03465"></a>03465                                                         <a class="code" href="dwc__otg__pcd__intr_8c.html#1edc1970063b8383cda91e9d8581f3ac">dwc_otg_pcd_handle_iso_bna</a>
+<a name="l03466"></a>03466                                                             (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>);
+<a name="l03467"></a>03467                                         } <span class="keywordflow">else</span>
+<a name="l03468"></a>03468 <span class="preprocessor">#endif                          </span><span class="comment">/* DWC_EN_ISOC */</span>
+<a name="l03469"></a>03469                                         {
+<a name="l03470"></a>03470                                                 dctl.<a class="code" href="uniondctl__data.html#f49aadfd7ad95b570115b3c245b1729e">d32</a> =
+<a name="l03471"></a>03471                                                     dwc_read_reg32(&amp;dev_if-&gt;
+<a name="l03472"></a>03472                                                                    dev_global_regs-&gt;
+<a name="l03473"></a>03473                                                                    dctl);
+<a name="l03474"></a>03474 
+<a name="l03475"></a>03475                                                 <span class="comment">/* If Global Continue on BNA is disabled - disable EP */</span>
+<a name="l03476"></a>03476                                                 <span class="keywordflow">if</span> (!dctl.<a class="code" href="uniondctl__data.html#a3abfa6d609d9864f1f65712b409d4d3">b</a>.<a class="code" href="uniondctl__data.html#212c36aaab3763a6de5cca56999c0263">gcontbna</a>) {
+<a name="l03477"></a>03477                                                         depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a> = 0;
+<a name="l03478"></a>03478                                                         depctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#ccf6e60ac8cabde8da36edb19504ba2b">snak</a> = 1;
+<a name="l03479"></a>03479                                                         depctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#4d76ba4ebd506d3175ec5cdc0d811654">epdis</a> = 1;
+<a name="l03480"></a>03480                                                         dwc_modify_reg32
+<a name="l03481"></a>03481                                                             (&amp;dev_if-&gt;
+<a name="l03482"></a>03482                                                              in_ep_regs[epnum]-&gt;
+<a name="l03483"></a>03483                                                              diepctl,
+<a name="l03484"></a>03484                                                              depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a>,
+<a name="l03485"></a>03485                                                              depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a>);
+<a name="l03486"></a>03486                                                 } <span class="keywordflow">else</span> {
+<a name="l03487"></a>03487                                                         <a class="code" href="dwc__otg__pcd_8c.html#de7160b7e7b8fd622ba95392513e197c">start_next_request</a>(<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>);
+<a name="l03488"></a>03488                                                 }
+<a name="l03489"></a>03489                                         }
+<a name="l03490"></a>03490                                 }
+<a name="l03491"></a>03491                         }
+<a name="l03492"></a>03492                         <span class="comment">/* NAK Interrutp */</span>
+<a name="l03493"></a>03493                         <span class="keywordflow">if</span> (diepint.<a class="code" href="uniondiepint__data.html#48d2a745e0ec983a47b35b0428b0437d">b</a>.<a class="code" href="uniondiepint__data.html#3ade814b2bef3085bb6fa32e94ea1aac">nak</a>) {
+<a name="l03494"></a>03494                                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#2bf62a567355d1ea38814714bd7b57ec">DBG_ANY</a>, <span class="stringliteral">"EP%d IN NAK Interrupt\n"</span>,
+<a name="l03495"></a>03495                                             epnum);
+<a name="l03496"></a>03496                                 <a class="code" href="dwc__otg__pcd__intr_8c.html#273ccc8e8cdb9e2075844f2f922b53bf">handle_in_ep_nak_intr</a>(pcd, epnum);
+<a name="l03497"></a>03497 
+<a name="l03498"></a>03498                                 CLEAR_IN_EP_INTR(core_if, epnum, nak);
+<a name="l03499"></a>03499                         }
+<a name="l03500"></a>03500                 }
+<a name="l03501"></a>03501                 epnum++;
+<a name="l03502"></a>03502                 ep_intr &gt;&gt;= 1;
+<a name="l03503"></a>03503         }
+<a name="l03504"></a>03504 
+<a name="l03505"></a>03505         <span class="keywordflow">return</span> 1;
+<a name="l03506"></a>03506 <span class="preprocessor">#undef CLEAR_IN_EP_INTR</span>
+<a name="l03507"></a>03507 <span class="preprocessor"></span>}
+<a name="l03508"></a>03508 
+<a name="l03522"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#8b24f400f2eb83ea262e27f5cd1bb707">03522</a> <span class="keyword">static</span> int32_t <a class="code" href="dwc__otg__pcd__intr_8c.html#8b24f400f2eb83ea262e27f5cd1bb707">dwc_otg_pcd_handle_out_ep_intr</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd)
+<a name="l03523"></a>03523 {
+<a name="l03524"></a>03524 <span class="preprocessor">#define CLEAR_OUT_EP_INTR(__core_if,__epnum,__intr) \</span>
+<a name="l03525"></a>03525 <span class="preprocessor">do { \</span>
+<a name="l03526"></a>03526 <span class="preprocessor">                doepint_data_t doepint = {.d32=0}; \</span>
+<a name="l03527"></a>03527 <span class="preprocessor">                doepint.b.__intr = 1; \</span>
+<a name="l03528"></a>03528 <span class="preprocessor">                dwc_write_reg32(&amp;__core_if-&gt;dev_if-&gt;out_ep_regs[__epnum]-&gt;doepint, \</span>
+<a name="l03529"></a>03529 <span class="preprocessor">                doepint.d32); \</span>
+<a name="l03530"></a>03530 <span class="preprocessor">} while (0)</span>
+<a name="l03531"></a>03531 <span class="preprocessor"></span>
+<a name="l03532"></a>03532         <a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if = <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd);
+<a name="l03533"></a>03533         <a class="code" href="structdwc__otg__dev__if.html">dwc_otg_dev_if_t</a> *dev_if = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>;
+<a name="l03534"></a>03534         uint32_t ep_intr;
+<a name="l03535"></a>03535         <a class="code" href="uniondoepint__data.html">doepint_data_t</a> doepint = {.d32 = 0 };
+<a name="l03536"></a>03536         <a class="code" href="uniondctl__data.html">dctl_data_t</a> dctl = {.d32 = 0 };
+<a name="l03537"></a>03537         <a class="code" href="uniondepctl__data.html">depctl_data_t</a> doepctl = {.d32 = 0 };
+<a name="l03538"></a>03538         uint32_t epnum = 0;
+<a name="l03539"></a>03539         <a class="code" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>;
+<a name="l03540"></a>03540         <a class="code" href="structdwc__ep.html">dwc_ep_t</a> *<a class="code" href="structdwc__ep.html">dwc_ep</a>;
+<a name="l03541"></a>03541 
+<a name="l03542"></a>03542         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"%s()\n"</span>, __func__);
+<a name="l03543"></a>03543 
+<a name="l03544"></a>03544         <span class="comment">/* Read in the device interrupt bits */</span>
+<a name="l03545"></a>03545         ep_intr = <a class="code" href="dwc__otg__cil_8h.html#43d4fc3ed87fc91c58c0299a9f3e82fe">dwc_otg_read_dev_all_out_ep_intr</a>(core_if);
+<a name="l03546"></a>03546 
+<a name="l03547"></a>03547         <span class="keywordflow">while</span> (ep_intr) {
+<a name="l03548"></a>03548                 <span class="keywordflow">if</span> (ep_intr &amp; 0x1) {
+<a name="l03549"></a>03549                         <span class="comment">/* Get EP pointer */</span>
+<a name="l03550"></a>03550                         <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a> = <a class="code" href="dwc__otg__pcd__intr_8c.html#fbd54e53e1968d3b4798ea1b63b52f74">get_out_ep</a>(pcd, epnum);
+<a name="l03551"></a>03551                         dwc_ep = &amp;<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>-&gt;<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>;
+<a name="l03552"></a>03552 
+<a name="l03553"></a>03553 <span class="preprocessor">#ifdef VERBOSE</span>
+<a name="l03554"></a>03554 <span class="preprocessor"></span>                        <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>,
+<a name="l03555"></a>03555                                     <span class="stringliteral">"EP%d-%s: type=%d, mps=%d\n"</span>,
+<a name="l03556"></a>03556                                     dwc_ep-&gt;<a class="code" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a>, (dwc_ep-&gt;<a class="code" href="structdwc__ep.html#b882b6b7c857100ed20600e94ea37760">is_in</a> ? <span class="stringliteral">"IN"</span> : <span class="stringliteral">"OUT"</span>),
+<a name="l03557"></a>03557                                     dwc_ep-&gt;<a class="code" href="structdwc__ep.html#17b10677bd9b0a1d612dd4ce2fb0eb0f">type</a>, dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a>);
+<a name="l03558"></a>03558 <span class="preprocessor">#endif</span>
+<a name="l03559"></a>03559 <span class="preprocessor"></span>                        doepint.<a class="code" href="uniondoepint__data.html#94f8c8fc116b430565f9322e3621b3a5">d32</a> =
+<a name="l03560"></a>03560                             <a class="code" href="dwc__otg__cil_8h.html#01199eaadd2a7b875c1841d13ee3728b">dwc_otg_read_dev_out_ep_intr</a>(core_if, dwc_ep);
+<a name="l03561"></a>03561 
+<a name="l03562"></a>03562                         <span class="comment">/* Transfer complete */</span>
+<a name="l03563"></a>03563                         <span class="keywordflow">if</span> (doepint.<a class="code" href="uniondoepint__data.html#9e966d9f85589f278dc2c0d0c7833856">b</a>.<a class="code" href="uniondoepint__data.html#341f7ffa5a9da7f6b1e09e9f4cc516a3">xfercompl</a>) {
+<a name="l03564"></a>03564 
+<a name="l03565"></a>03565                                 <span class="keywordflow">if</span> (epnum == 0) {
+<a name="l03566"></a>03566                                         <span class="comment">/* Clear the bit in DOEPINTn for this interrupt */</span>
+<a name="l03567"></a>03567                                         CLEAR_OUT_EP_INTR(core_if, epnum,
+<a name="l03568"></a>03568                                                           xfercompl);
+<a name="l03569"></a>03569                                         <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a> == 0
+<a name="l03570"></a>03570                                             || pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#8f6963b3fb9ab83048c4c0697c90382a">ep0state</a> != EP0_IDLE)
+<a name="l03571"></a>03571                                                 <a class="code" href="dwc__otg__pcd__intr_8c.html#4991119b51de03163a3677c36bc0ee3b">handle_ep0</a>(pcd);
+<a name="l03572"></a>03572 <span class="preprocessor">#ifdef DWC_EN_ISOC</span>
+<a name="l03573"></a>03573 <span class="preprocessor"></span>                                } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (dwc_ep-&gt;<a class="code" href="structdwc__ep.html#17b10677bd9b0a1d612dd4ce2fb0eb0f">type</a> == <a class="code" href="dwc__otg__cil_8h.html#152a3a5e1433bd2197672f0b5105e7a4">DWC_OTG_EP_TYPE_ISOC</a>) {
+<a name="l03574"></a>03574                                         <span class="keywordflow">if</span> (doepint.<a class="code" href="uniondoepint__data.html#9e966d9f85589f278dc2c0d0c7833856">b</a>.<a class="code" href="uniondoepint__data.html#0c8fc4f5245a9874c0c3b61d1c6f719d">pktdrpsts</a> == 0) {
+<a name="l03575"></a>03575                                                 <span class="comment">/* Clear the bit in DOEPINTn for this interrupt */</span>
+<a name="l03576"></a>03576                                                 CLEAR_OUT_EP_INTR(core_if,
+<a name="l03577"></a>03577                                                                   epnum,
+<a name="l03578"></a>03578                                                                   xfercompl);
+<a name="l03579"></a>03579                                                 <a class="code" href="dwc__otg__pcd__intr_8c.html#05965765a43225780ae08f2c3928f782">complete_iso_ep</a>(pcd, <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>);
+<a name="l03580"></a>03580                                         } <span class="keywordflow">else</span> {
+<a name="l03581"></a>03581 
+<a name="l03582"></a>03582                                                 <a class="code" href="uniondoepint__data.html">doepint_data_t</a> doepint = {.<a class="code" href="uniondoepint__data.html#94f8c8fc116b430565f9322e3621b3a5">d32</a> =
+<a name="l03583"></a>03583                                                             0 };
+<a name="l03584"></a>03584                                                 doepint.<a class="code" href="uniondoepint__data.html#9e966d9f85589f278dc2c0d0c7833856">b</a>.<a class="code" href="uniondoepint__data.html#341f7ffa5a9da7f6b1e09e9f4cc516a3">xfercompl</a> = 1;
+<a name="l03585"></a>03585                                                 doepint.<a class="code" href="uniondoepint__data.html#9e966d9f85589f278dc2c0d0c7833856">b</a>.<a class="code" href="uniondoepint__data.html#0c8fc4f5245a9874c0c3b61d1c6f719d">pktdrpsts</a> = 1;
+<a name="l03586"></a>03586                                                 dwc_write_reg32(&amp;core_if-&gt;
+<a name="l03587"></a>03587                                                                 dev_if-&gt;
+<a name="l03588"></a>03588                                                                 out_ep_regs
+<a name="l03589"></a>03589                                                                 [epnum]-&gt;
+<a name="l03590"></a>03590                                                                 doepint,
+<a name="l03591"></a>03591                                                                 doepint.<a class="code" href="uniondoepint__data.html#94f8c8fc116b430565f9322e3621b3a5">d32</a>);
+<a name="l03592"></a>03592                                                 <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__pcd__intr_8c.html#41cfc0d590740640795b350998bcc2c4">handle_iso_out_pkt_dropped</a>
+<a name="l03593"></a>03593                                                     (core_if, dwc_ep)) {
+<a name="l03594"></a>03594                                                         <a class="code" href="dwc__otg__pcd__intr_8c.html#05965765a43225780ae08f2c3928f782">complete_iso_ep</a>(pcd,
+<a name="l03595"></a>03595                                                                         <a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>);
+<a name="l03596"></a>03596                                                 }
+<a name="l03597"></a>03597                                         }
+<a name="l03598"></a>03598 <span class="preprocessor">#endif                          </span><span class="comment">/* DWC_EN_ISOC */</span>
+<a name="l03599"></a>03599                                 } <span class="keywordflow">else</span> {
+<a name="l03600"></a>03600                                         <span class="comment">/* Clear the bit in DOEPINTn for this interrupt */</span>
+<a name="l03601"></a>03601                                         CLEAR_OUT_EP_INTR(core_if, epnum,
+<a name="l03602"></a>03602                                                           xfercompl);
+<a name="l03603"></a>03603                                         <a class="code" href="dwc__otg__pcd__intr_8c.html#c77f277130ba55b19100bde598da7d85">complete_ep</a>(<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>);
+<a name="l03604"></a>03604                                 }
+<a name="l03605"></a>03605 
+<a name="l03606"></a>03606                         }
+<a name="l03607"></a>03607 
+<a name="l03608"></a>03608                         <span class="comment">/* Endpoint disable      */</span>
+<a name="l03609"></a>03609                         <span class="keywordflow">if</span> (doepint.<a class="code" href="uniondoepint__data.html#9e966d9f85589f278dc2c0d0c7833856">b</a>.<a class="code" href="uniondoepint__data.html#8a263ddc3ab9080b8c2e02ccead0c983">epdisabled</a>) {
+<a name="l03610"></a>03610 
+<a name="l03611"></a>03611                                 <span class="comment">/* Clear the bit in DOEPINTn for this interrupt */</span>
+<a name="l03612"></a>03612                                 CLEAR_OUT_EP_INTR(core_if, epnum, epdisabled);
+<a name="l03613"></a>03613                         }
+<a name="l03614"></a>03614                         <span class="comment">/* AHB Error */</span>
+<a name="l03615"></a>03615                         <span class="keywordflow">if</span> (doepint.<a class="code" href="uniondoepint__data.html#9e966d9f85589f278dc2c0d0c7833856">b</a>.<a class="code" href="uniondoepint__data.html#cdfedbad6643d94271e91e135485a68d">ahberr</a>) {
+<a name="l03616"></a>03616                                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"EP%d OUT AHB Error\n"</span>,
+<a name="l03617"></a>03617                                             epnum);
+<a name="l03618"></a>03618                                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"EP DMA REG         %d \n"</span>,
+<a name="l03619"></a>03619                                             core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a>-&gt;
+<a name="l03620"></a>03620                                             out_ep_regs[epnum]-&gt;doepdma);
+<a name="l03621"></a>03621                                 CLEAR_OUT_EP_INTR(core_if, epnum, ahberr);
+<a name="l03622"></a>03622                         }
+<a name="l03623"></a>03623                         <span class="comment">/* Setup Phase Done (contorl EPs) */</span>
+<a name="l03624"></a>03624                         <span class="keywordflow">if</span> (doepint.<a class="code" href="uniondoepint__data.html#9e966d9f85589f278dc2c0d0c7833856">b</a>.<a class="code" href="uniondoepint__data.html#b286d1b76f09a9122aca23e430b63dc8">setup</a>) {
+<a name="l03625"></a>03625 <span class="preprocessor">#ifdef DEBUG_EP0</span>
+<a name="l03626"></a>03626 <span class="preprocessor"></span>                                <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"EP%d SETUP Done\n"</span>,
+<a name="l03627"></a>03627                                             epnum);
+<a name="l03628"></a>03628 <span class="preprocessor">#endif</span>
+<a name="l03629"></a>03629 <span class="preprocessor"></span>                                CLEAR_OUT_EP_INTR(core_if, epnum, setup);
+<a name="l03630"></a>03630 
+<a name="l03631"></a>03631                                 <a class="code" href="dwc__otg__pcd__intr_8c.html#4991119b51de03163a3677c36bc0ee3b">handle_ep0</a>(pcd);
+<a name="l03632"></a>03632                         }
+<a name="l03633"></a>03633 
+<a name="l03635"></a>03635                         <span class="keywordflow">if</span> (doepint.<a class="code" href="uniondoepint__data.html#9e966d9f85589f278dc2c0d0c7833856">b</a>.<a class="code" href="uniondoepint__data.html#e68e77d553158195b16a790012f9627d">bna</a>) {
+<a name="l03636"></a>03636                                 CLEAR_OUT_EP_INTR(core_if, epnum, bna);
+<a name="l03637"></a>03637                                 <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a>) {
+<a name="l03638"></a>03638 <span class="preprocessor">#ifdef DWC_EN_ISOC</span>
+<a name="l03639"></a>03639 <span class="preprocessor"></span>                                        <span class="keywordflow">if</span> (dwc_ep-&gt;<a class="code" href="structdwc__ep.html#17b10677bd9b0a1d612dd4ce2fb0eb0f">type</a> ==
+<a name="l03640"></a>03640                                             <a class="code" href="dwc__otg__cil_8h.html#152a3a5e1433bd2197672f0b5105e7a4">DWC_OTG_EP_TYPE_ISOC</a>) {
+<a name="l03641"></a>03641                                                 <span class="comment">/*</span>
+<a name="l03642"></a>03642 <span class="comment">                                                 * This checking is performed to prevent first "false" BNA </span>
+<a name="l03643"></a>03643 <span class="comment">                                                 * handling occuring right after reconnect </span>
+<a name="l03644"></a>03644 <span class="comment">                                                 */</span>
+<a name="l03645"></a>03645                                                 <span class="keywordflow">if</span> (dwc_ep-&gt;<a class="code" href="structdwc__ep.html#1e9f4d08454c973c17acb3e52a2c3689">next_frame</a> !=
+<a name="l03646"></a>03646                                                     0xffffffff)
+<a name="l03647"></a>03647                                                         <a class="code" href="dwc__otg__pcd__intr_8c.html#1edc1970063b8383cda91e9d8581f3ac">dwc_otg_pcd_handle_iso_bna</a>
+<a name="l03648"></a>03648                                                             (<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>);
+<a name="l03649"></a>03649                                         } <span class="keywordflow">else</span>
+<a name="l03650"></a>03650 <span class="preprocessor">#endif                          </span><span class="comment">/* DWC_EN_ISOC */</span>
+<a name="l03651"></a>03651                                         {
+<a name="l03652"></a>03652                                                 dctl.<a class="code" href="uniondctl__data.html#f49aadfd7ad95b570115b3c245b1729e">d32</a> =
+<a name="l03653"></a>03653                                                     dwc_read_reg32(&amp;dev_if-&gt;
+<a name="l03654"></a>03654                                                                    dev_global_regs-&gt;
+<a name="l03655"></a>03655                                                                    dctl);
+<a name="l03656"></a>03656 
+<a name="l03657"></a>03657                                                 <span class="comment">/* If Global Continue on BNA is disabled - disable EP */</span>
+<a name="l03658"></a>03658                                                 <span class="keywordflow">if</span> (!dctl.<a class="code" href="uniondctl__data.html#a3abfa6d609d9864f1f65712b409d4d3">b</a>.<a class="code" href="uniondctl__data.html#212c36aaab3763a6de5cca56999c0263">gcontbna</a>) {
+<a name="l03659"></a>03659                                                         doepctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a> = 0;
+<a name="l03660"></a>03660                                                         doepctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#ccf6e60ac8cabde8da36edb19504ba2b">snak</a> = 1;
+<a name="l03661"></a>03661                                                         doepctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#4d76ba4ebd506d3175ec5cdc0d811654">epdis</a> = 1;
+<a name="l03662"></a>03662                                                         dwc_modify_reg32
+<a name="l03663"></a>03663                                                             (&amp;dev_if-&gt;
+<a name="l03664"></a>03664                                                              out_ep_regs
+<a name="l03665"></a>03665                                                              [epnum]-&gt;doepctl,
+<a name="l03666"></a>03666                                                              doepctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a>,
+<a name="l03667"></a>03667                                                              doepctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a>);
+<a name="l03668"></a>03668                                                 } <span class="keywordflow">else</span> {
+<a name="l03669"></a>03669                                                         <a class="code" href="dwc__otg__pcd_8c.html#de7160b7e7b8fd622ba95392513e197c">start_next_request</a>(<a class="code" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a>);
+<a name="l03670"></a>03670                                                 }
+<a name="l03671"></a>03671                                         }
+<a name="l03672"></a>03672                                 }
+<a name="l03673"></a>03673                         }
+<a name="l03674"></a>03674                         <span class="keywordflow">if</span> (doepint.<a class="code" href="uniondoepint__data.html#9e966d9f85589f278dc2c0d0c7833856">b</a>.<a class="code" href="uniondoepint__data.html#038fca8f1c03d7cfe323caa4f8bda126">stsphsercvd</a>) {
+<a name="l03675"></a>03675                                 CLEAR_OUT_EP_INTR(core_if, epnum, stsphsercvd);
+<a name="l03676"></a>03676                                 <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a>) {
+<a name="l03677"></a>03677                                         <a class="code" href="dwc__otg__pcd__intr_8c.html#39d3face14e49b0f1ad5c978f87665fe">do_setup_in_status_phase</a>(pcd);
+<a name="l03678"></a>03678                                 }
+<a name="l03679"></a>03679                         }
+<a name="l03680"></a>03680                         <span class="comment">/* Babble Interrutp */</span>
+<a name="l03681"></a>03681                         <span class="keywordflow">if</span> (doepint.<a class="code" href="uniondoepint__data.html#9e966d9f85589f278dc2c0d0c7833856">b</a>.<a class="code" href="uniondoepint__data.html#c555371bda41092d89992523563dadbb">babble</a>) {
+<a name="l03682"></a>03682                                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#2bf62a567355d1ea38814714bd7b57ec">DBG_ANY</a>, <span class="stringliteral">"EP%d OUT Babble\n"</span>,
+<a name="l03683"></a>03683                                             epnum);
+<a name="l03684"></a>03684                                 <a class="code" href="dwc__otg__pcd__intr_8c.html#42aef7ea134cccf7cdb53e7e1428bc4a">handle_out_ep_babble_intr</a>(pcd, epnum);
+<a name="l03685"></a>03685 
+<a name="l03686"></a>03686                                 CLEAR_OUT_EP_INTR(core_if, epnum, babble);
+<a name="l03687"></a>03687                         }
+<a name="l03688"></a>03688                         <span class="comment">/* NAK Interrutp */</span>
+<a name="l03689"></a>03689                         <span class="keywordflow">if</span> (doepint.<a class="code" href="uniondoepint__data.html#9e966d9f85589f278dc2c0d0c7833856">b</a>.<a class="code" href="uniondoepint__data.html#2ac99fbbb1bcf135d5db41e096e8b95b">nak</a>) {
+<a name="l03690"></a>03690                                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#2bf62a567355d1ea38814714bd7b57ec">DBG_ANY</a>, <span class="stringliteral">"EP%d OUT NAK\n"</span>, epnum);
+<a name="l03691"></a>03691                                 <a class="code" href="dwc__otg__pcd__intr_8c.html#252929e585c84eaf0485869cd7734244">handle_out_ep_nak_intr</a>(pcd, epnum);
+<a name="l03692"></a>03692 
+<a name="l03693"></a>03693                                 CLEAR_OUT_EP_INTR(core_if, epnum, nak);
+<a name="l03694"></a>03694                         }
+<a name="l03695"></a>03695                         <span class="comment">/* NYET Interrutp */</span>
+<a name="l03696"></a>03696                         <span class="keywordflow">if</span> (doepint.<a class="code" href="uniondoepint__data.html#9e966d9f85589f278dc2c0d0c7833856">b</a>.<a class="code" href="uniondoepint__data.html#f35ad8ba20b8941b6ad00dc75586454f">nyet</a>) {
+<a name="l03697"></a>03697                                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#2bf62a567355d1ea38814714bd7b57ec">DBG_ANY</a>, <span class="stringliteral">"EP%d OUT NYET\n"</span>, epnum);
+<a name="l03698"></a>03698                                 <a class="code" href="dwc__otg__pcd__intr_8c.html#926d9068c1950cc406d50828e72a31db">handle_out_ep_nyet_intr</a>(pcd, epnum);
+<a name="l03699"></a>03699 
+<a name="l03700"></a>03700                                 CLEAR_OUT_EP_INTR(core_if, epnum, nyet);
+<a name="l03701"></a>03701                         }
+<a name="l03702"></a>03702                 }
+<a name="l03703"></a>03703 
+<a name="l03704"></a>03704                 epnum++;
+<a name="l03705"></a>03705                 ep_intr &gt;&gt;= 1;
+<a name="l03706"></a>03706         }
+<a name="l03707"></a>03707 
+<a name="l03708"></a>03708         <span class="keywordflow">return</span> 1;
+<a name="l03709"></a>03709 
+<a name="l03710"></a>03710 <span class="preprocessor">#undef CLEAR_OUT_EP_INTR</span>
+<a name="l03711"></a>03711 <span class="preprocessor"></span>}
+<a name="l03712"></a>03712 
+<a name="l03725"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#aa9fd9a6774ed616e31df65fe326351b">03725</a> int32_t <a class="code" href="dwc__otg__pcd__intr_8c.html#aa9fd9a6774ed616e31df65fe326351b">dwc_otg_pcd_handle_incomplete_isoc_in_intr</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd)
+<a name="l03726"></a>03726 {
+<a name="l03727"></a>03727         <a class="code" href="uniongintsts__data.html">gintsts_data_t</a> gintsts;
+<a name="l03728"></a>03728 
+<a name="l03729"></a>03729 <span class="preprocessor">#ifdef DWC_EN_ISOC</span>
+<a name="l03730"></a>03730 <span class="preprocessor"></span>        <a class="code" href="structdwc__otg__dev__if.html">dwc_otg_dev_if_t</a> *dev_if;
+<a name="l03731"></a>03731         <a class="code" href="uniondeptsiz__data.html">deptsiz_data_t</a> deptsiz = {.d32 = 0 };
+<a name="l03732"></a>03732         <a class="code" href="uniondepctl__data.html">depctl_data_t</a> depctl = {.d32 = 0 };
+<a name="l03733"></a>03733         <a class="code" href="uniondsts__data.html">dsts_data_t</a> dsts = {.d32 = 0 };
+<a name="l03734"></a>03734         <a class="code" href="structdwc__ep.html">dwc_ep_t</a> *<a class="code" href="structdwc__ep.html">dwc_ep</a>;
+<a name="l03735"></a>03735         <span class="keywordtype">int</span> i;
+<a name="l03736"></a>03736 
+<a name="l03737"></a>03737         dev_if = <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;dev_if;
+<a name="l03738"></a>03738 
+<a name="l03739"></a>03739         <span class="keywordflow">for</span> (i = 1; i &lt;= dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#4fae9bc1293bf2e58966c38fa5b98822">num_in_eps</a>; ++i) {
+<a name="l03740"></a>03740                 dwc_ep = &amp;pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#dbfc8c424ea3add38db96fa87219caa8">in_ep</a>[i].<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>;
+<a name="l03741"></a>03741                 if (dwc_ep-&gt;<a class="code" href="structdwc__ep.html#63b7a1a3ee32df393ff10d8bfc5c8648">active</a> &amp;&amp; dwc_ep-&gt;<a class="code" href="structdwc__ep.html#17b10677bd9b0a1d612dd4ce2fb0eb0f">type</a> == <a class="code" href="dwc__otg__cil_8h.html#152a3a5e1433bd2197672f0b5105e7a4">DWC_OTG_EP_TYPE_ISOC</a>) {
+<a name="l03742"></a>03742                         deptsiz.<a class="code" href="uniondeptsiz__data.html#10c2b2ba8b419b0a766430a59befbbe0">d32</a> =
+<a name="l03743"></a>03743                             dwc_read_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[i]-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#88f637b5a4e8a0c6bc87d157072255dd">dieptsiz</a>);
+<a name="l03744"></a>03744                         depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a> =
+<a name="l03745"></a>03745                             dwc_read_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[i]-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#53a5adb977e2aec66d4902c6ba293216">diepctl</a>);
+<a name="l03746"></a>03746 
+<a name="l03747"></a>03747                         if (depctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#4d76ba4ebd506d3175ec5cdc0d811654">epdis</a> &amp;&amp; deptsiz.<a class="code" href="uniondeptsiz__data.html#10c2b2ba8b419b0a766430a59befbbe0">d32</a>) {
+<a name="l03748"></a>03748                                 <a class="code" href="dwc__otg__pcd__intr_8c.html#17428b2360118cc59ab9d5cbcef8a14b">set_current_pkt_info</a>(<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd), dwc_ep);
+<a name="l03749"></a>03749                                 <span class="keywordflow">if</span> (dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d4e63c7d944c2b48260b4a75c2b58925">cur_pkt</a> &gt;= dwc_ep-&gt;<a class="code" href="structdwc__ep.html#46349fb0608d8c6849ced211b0628c15">pkt_cnt</a>) {
+<a name="l03750"></a>03750                                         dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d4e63c7d944c2b48260b4a75c2b58925">cur_pkt</a> = 0;
+<a name="l03751"></a>03751                                         dwc_ep-&gt;<a class="code" href="structdwc__ep.html#53033f174854701986545f05502e1cad">proc_buf_num</a> =
+<a name="l03752"></a>03752                                             (dwc_ep-&gt;<a class="code" href="structdwc__ep.html#53033f174854701986545f05502e1cad">proc_buf_num</a> ^ 1) &amp; 0x1;
+<a name="l03753"></a>03753 
+<a name="l03754"></a>03754                                         if (dwc_ep-&gt;<a class="code" href="structdwc__ep.html#53033f174854701986545f05502e1cad">proc_buf_num</a>) {
+<a name="l03755"></a>03755                                                 dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d3bc23598a77d3cca52c70a28afc6b5e">cur_pkt_addr</a> =
+<a name="l03756"></a>03756                                                     dwc_ep-&gt;<a class="code" href="structdwc__ep.html#36ff87362a0da5bce95eaf85522d49ff">xfer_buff1</a>;
+<a name="l03757"></a>03757                                                 dwc_ep-&gt;<a class="code" href="structdwc__ep.html#ed4594c9f6c2bcbcf6f1bbe9e9c64061">cur_pkt_dma_addr</a> =
+<a name="l03758"></a>03758                                                     dwc_ep-&gt;<a class="code" href="structdwc__ep.html#02dc1be77d505b19f14651fe9805c97f">dma_addr1</a>;
+<a name="l03759"></a>03759                                         } <span class="keywordflow">else</span> {
+<a name="l03760"></a>03760                                                 dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d3bc23598a77d3cca52c70a28afc6b5e">cur_pkt_addr</a> =
+<a name="l03761"></a>03761                                                     dwc_ep-&gt;<a class="code" href="structdwc__ep.html#b6d727e366ac589d304256c758d2d44a">xfer_buff0</a>;
+<a name="l03762"></a>03762                                                 dwc_ep-&gt;<a class="code" href="structdwc__ep.html#ed4594c9f6c2bcbcf6f1bbe9e9c64061">cur_pkt_dma_addr</a> =
+<a name="l03763"></a>03763                                                     dwc_ep-&gt;<a class="code" href="structdwc__ep.html#553936d1d003413d00a24330274887f9">dma_addr0</a>;
+<a name="l03764"></a>03764                                         }
+<a name="l03765"></a>03765 
+<a name="l03766"></a>03766                                 }
+<a name="l03767"></a>03767 
+<a name="l03768"></a>03768                                 dsts.d32 =
+<a name="l03769"></a>03769                                     dwc_read_reg32(&amp;<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;dev_if-&gt;
+<a name="l03770"></a>03770                                                    dev_global_regs-&gt;dsts);
+<a name="l03771"></a>03771                                 <a class="code" href="structdwc__ep.html">dwc_ep</a>-&gt;next_frame = dsts.b.soffn;
+<a name="l03772"></a>03772 
+<a name="l03773"></a>03773                                 <a class="code" href="dwc__otg__cil_8c.html#0f0894ae9890260e1da839aa10af35cc">dwc_otg_iso_ep_start_frm_transfer</a>(<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>
+<a name="l03774"></a>03774                                                                   (pcd),
+<a name="l03775"></a>03775                                                                   <a class="code" href="structdwc__ep.html">dwc_ep</a>);
+<a name="l03776"></a>03776                         }
+<a name="l03777"></a>03777                 }
+<a name="l03778"></a>03778         }
+<a name="l03779"></a>03779 
+<a name="l03780"></a>03780 <span class="preprocessor">#else</span>
+<a name="l03781"></a>03781 <span class="preprocessor"></span>        <a class="code" href="uniongintmsk__data.html">gintmsk_data_t</a> intr_mask = {.d32 = 0 };
+<a name="l03782"></a>03782         DWC_PRINTF(<span class="stringliteral">"INTERRUPT Handler not implemented for %s\n"</span>,
+<a name="l03783"></a>03783                    <span class="stringliteral">"IN ISOC Incomplete"</span>);
+<a name="l03784"></a>03784 
+<a name="l03785"></a>03785         intr_mask.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#3f9eeb4c73291b7943b7187ba34c90f4">incomplisoin</a> = 1;
+<a name="l03786"></a>03786         dwc_modify_reg32(&amp;<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;core_global_regs-&gt;gintmsk,
+<a name="l03787"></a>03787                          intr_mask.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a>, 0);
+<a name="l03788"></a>03788 <span class="preprocessor">#endif                          //DWC_EN_ISOC</span>
+<a name="l03789"></a>03789 <span class="preprocessor"></span>
+<a name="l03790"></a>03790         <span class="comment">/* Clear interrupt */</span>
+<a name="l03791"></a>03791         gintsts.d32 = 0;
+<a name="l03792"></a>03792         gintsts.b.incomplisoin = 1;
+<a name="l03793"></a>03793         dwc_write_reg32(&amp;<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;core_global_regs-&gt;gintsts,
+<a name="l03794"></a>03794                         gintsts.d32);
+<a name="l03795"></a>03795 
+<a name="l03796"></a>03796         <span class="keywordflow">return</span> 1;
+<a name="l03797"></a>03797 }
+<a name="l03798"></a>03798 
+<a name="l03814"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#8277c5761c3865fbb3646ba496a4901e">03814</a> int32_t <a class="code" href="dwc__otg__pcd__intr_8c.html#8277c5761c3865fbb3646ba496a4901e">dwc_otg_pcd_handle_incomplete_isoc_out_intr</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd)
+<a name="l03815"></a>03815 {
+<a name="l03816"></a>03816 
+<a name="l03817"></a>03817         <a class="code" href="uniongintsts__data.html">gintsts_data_t</a> gintsts;
+<a name="l03818"></a>03818 
+<a name="l03819"></a>03819 <span class="preprocessor">#ifdef DWC_EN_ISOC</span>
+<a name="l03820"></a>03820 <span class="preprocessor"></span>        <a class="code" href="structdwc__otg__dev__if.html">dwc_otg_dev_if_t</a> *dev_if;
+<a name="l03821"></a>03821         <a class="code" href="uniondeptsiz__data.html">deptsiz_data_t</a> deptsiz = {.d32 = 0 };
+<a name="l03822"></a>03822         <a class="code" href="uniondepctl__data.html">depctl_data_t</a> depctl = {.d32 = 0 };
+<a name="l03823"></a>03823         <a class="code" href="uniondsts__data.html">dsts_data_t</a> dsts = {.d32 = 0 };
+<a name="l03824"></a>03824         <a class="code" href="structdwc__ep.html">dwc_ep_t</a> *<a class="code" href="structdwc__ep.html">dwc_ep</a>;
+<a name="l03825"></a>03825         <span class="keywordtype">int</span> i;
+<a name="l03826"></a>03826 
+<a name="l03827"></a>03827         dev_if = <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;dev_if;
+<a name="l03828"></a>03828 
+<a name="l03829"></a>03829         <span class="keywordflow">for</span> (i = 1; i &lt;= dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#2f0e01cdc605623f591963fc83c8dc73">num_out_eps</a>; ++i) {
+<a name="l03830"></a>03830                 dwc_ep = &amp;pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#dbfc8c424ea3add38db96fa87219caa8">in_ep</a>[i].<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>;
+<a name="l03831"></a>03831                 if (pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#b9e49a1d1fbca5ba9523e27c7108df30">out_ep</a>[i].<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#63b7a1a3ee32df393ff10d8bfc5c8648">active</a> &amp;&amp;
+<a name="l03832"></a>03832                     pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#b9e49a1d1fbca5ba9523e27c7108df30">out_ep</a>[i].<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>.<a class="code" href="structdwc__ep.html#17b10677bd9b0a1d612dd4ce2fb0eb0f">type</a> == <a class="code" href="dwc__otg__cil_8h.html#152a3a5e1433bd2197672f0b5105e7a4">DWC_OTG_EP_TYPE_ISOC</a>) {
+<a name="l03833"></a>03833                         deptsiz.<a class="code" href="uniondeptsiz__data.html#10c2b2ba8b419b0a766430a59befbbe0">d32</a> =
+<a name="l03834"></a>03834                             dwc_read_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">out_ep_regs</a>[i]-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#e756ec48787099f0a4e2ce353fce4f91">doeptsiz</a>);
+<a name="l03835"></a>03835                         depctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a> =
+<a name="l03836"></a>03836                             dwc_read_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">out_ep_regs</a>[i]-&gt;<a class="code" href="structdwc__otg__dev__out__ep__regs.html#2a522b71fc97658c07debf3521f7d3e5">doepctl</a>);
+<a name="l03837"></a>03837 
+<a name="l03838"></a>03838                         if (depctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#4d76ba4ebd506d3175ec5cdc0d811654">epdis</a> &amp;&amp; deptsiz.<a class="code" href="uniondeptsiz__data.html#10c2b2ba8b419b0a766430a59befbbe0">d32</a>) {
+<a name="l03839"></a>03839                                 <a class="code" href="dwc__otg__pcd__intr_8c.html#17428b2360118cc59ab9d5cbcef8a14b">set_current_pkt_info</a>(<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd),
+<a name="l03840"></a>03840                                                      &amp;pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#b9e49a1d1fbca5ba9523e27c7108df30">out_ep</a>[i].<a class="code" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a>);
+<a name="l03841"></a>03841                                 if (dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d4e63c7d944c2b48260b4a75c2b58925">cur_pkt</a> &gt;= dwc_ep-&gt;<a class="code" href="structdwc__ep.html#46349fb0608d8c6849ced211b0628c15">pkt_cnt</a>) {
+<a name="l03842"></a>03842                                         dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d4e63c7d944c2b48260b4a75c2b58925">cur_pkt</a> = 0;
+<a name="l03843"></a>03843                                         dwc_ep-&gt;<a class="code" href="structdwc__ep.html#53033f174854701986545f05502e1cad">proc_buf_num</a> =
+<a name="l03844"></a>03844                                             (dwc_ep-&gt;<a class="code" href="structdwc__ep.html#53033f174854701986545f05502e1cad">proc_buf_num</a> ^ 1) &amp; 0x1;
+<a name="l03845"></a>03845 
+<a name="l03846"></a>03846                                         if (dwc_ep-&gt;<a class="code" href="structdwc__ep.html#53033f174854701986545f05502e1cad">proc_buf_num</a>) {
+<a name="l03847"></a>03847                                                 dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d3bc23598a77d3cca52c70a28afc6b5e">cur_pkt_addr</a> =
+<a name="l03848"></a>03848                                                     dwc_ep-&gt;<a class="code" href="structdwc__ep.html#36ff87362a0da5bce95eaf85522d49ff">xfer_buff1</a>;
+<a name="l03849"></a>03849                                                 dwc_ep-&gt;<a class="code" href="structdwc__ep.html#ed4594c9f6c2bcbcf6f1bbe9e9c64061">cur_pkt_dma_addr</a> =
+<a name="l03850"></a>03850                                                     dwc_ep-&gt;<a class="code" href="structdwc__ep.html#02dc1be77d505b19f14651fe9805c97f">dma_addr1</a>;
+<a name="l03851"></a>03851                                         } <span class="keywordflow">else</span> {
+<a name="l03852"></a>03852                                                 dwc_ep-&gt;<a class="code" href="structdwc__ep.html#d3bc23598a77d3cca52c70a28afc6b5e">cur_pkt_addr</a> =
+<a name="l03853"></a>03853                                                     dwc_ep-&gt;<a class="code" href="structdwc__ep.html#b6d727e366ac589d304256c758d2d44a">xfer_buff0</a>;
+<a name="l03854"></a>03854                                                 dwc_ep-&gt;<a class="code" href="structdwc__ep.html#ed4594c9f6c2bcbcf6f1bbe9e9c64061">cur_pkt_dma_addr</a> =
+<a name="l03855"></a>03855                                                     dwc_ep-&gt;<a class="code" href="structdwc__ep.html#553936d1d003413d00a24330274887f9">dma_addr0</a>;
+<a name="l03856"></a>03856                                         }
+<a name="l03857"></a>03857 
+<a name="l03858"></a>03858                                 }
+<a name="l03859"></a>03859 
+<a name="l03860"></a>03860                                 dsts.d32 =
+<a name="l03861"></a>03861                                     dwc_read_reg32(&amp;<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;dev_if-&gt;
+<a name="l03862"></a>03862                                                    dev_global_regs-&gt;dsts);
+<a name="l03863"></a>03863                                 <a class="code" href="structdwc__ep.html">dwc_ep</a>-&gt;next_frame = dsts.b.soffn;
+<a name="l03864"></a>03864 
+<a name="l03865"></a>03865                                 <a class="code" href="dwc__otg__cil_8c.html#0f0894ae9890260e1da839aa10af35cc">dwc_otg_iso_ep_start_frm_transfer</a>(<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>
+<a name="l03866"></a>03866                                                                   (pcd),
+<a name="l03867"></a>03867                                                                   <a class="code" href="structdwc__ep.html">dwc_ep</a>);
+<a name="l03868"></a>03868                         }
+<a name="l03869"></a>03869                 }
+<a name="l03870"></a>03870         }
+<a name="l03871"></a>03871 <span class="preprocessor">#else</span>
+<a name="l03872"></a>03872 <span class="preprocessor"></span>
+<a name="l03873"></a>03873         <a class="code" href="uniongintmsk__data.html">gintmsk_data_t</a> intr_mask = {.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a> = 0 };
+<a name="l03874"></a>03874 
+<a name="l03875"></a>03875         DWC_PRINTF(<span class="stringliteral">"INTERRUPT Handler not implemented for %s\n"</span>,
+<a name="l03876"></a>03876                    <span class="stringliteral">"OUT ISOC Incomplete"</span>);
+<a name="l03877"></a>03877 
+<a name="l03878"></a>03878         intr_mask.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#c63c107070bd7623766e39cd06ec7c97">incomplisoout</a> = 1;
+<a name="l03879"></a>03879         dwc_modify_reg32(&amp;<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;core_global_regs-&gt;gintmsk,
+<a name="l03880"></a>03880                          intr_mask.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a>, 0);
+<a name="l03881"></a>03881 
+<a name="l03882"></a>03882 <span class="preprocessor">#endif                          </span><span class="comment">/* DWC_EN_ISOC */</span>
+<a name="l03883"></a>03883 
+<a name="l03884"></a>03884         <span class="comment">/* Clear interrupt */</span>
+<a name="l03885"></a>03885         gintsts.d32 = 0;
+<a name="l03886"></a>03886         gintsts.b.incomplisoout = 1;
+<a name="l03887"></a>03887         dwc_write_reg32(&amp;<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;core_global_regs-&gt;gintsts,
+<a name="l03888"></a>03888                         gintsts.d32);
+<a name="l03889"></a>03889 
+<a name="l03890"></a>03890         <span class="keywordflow">return</span> 1;
+<a name="l03891"></a>03891 }
+<a name="l03892"></a>03892 
+<a name="l03897"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#c24d0c885fe79e75d6f738fd9bd9c0d7">03897</a> int32_t <a class="code" href="dwc__otg__pcd__intr_8c.html#c24d0c885fe79e75d6f738fd9bd9c0d7">dwc_otg_pcd_handle_in_nak_effective</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd)
+<a name="l03898"></a>03898 {
+<a name="l03899"></a>03899         <a class="code" href="structdwc__otg__dev__if.html">dwc_otg_dev_if_t</a> *dev_if = <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;dev_if;
+<a name="l03900"></a>03900         <a class="code" href="uniondepctl__data.html">depctl_data_t</a> diepctl = {.d32 = 0 };
+<a name="l03901"></a>03901         <a class="code" href="uniondepctl__data.html">depctl_data_t</a> diepctl_rd = {.d32 = 0 };
+<a name="l03902"></a>03902         <a class="code" href="uniongintmsk__data.html">gintmsk_data_t</a> intr_mask = {.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a> = 0 };
+<a name="l03903"></a>03903         <a class="code" href="uniongintsts__data.html">gintsts_data_t</a> gintsts;
+<a name="l03904"></a>03904         <span class="keywordtype">int</span> i;
+<a name="l03905"></a>03905 
+<a name="l03906"></a>03906         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"Global IN NAK Effective\n"</span>);
+<a name="l03907"></a>03907 
+<a name="l03908"></a>03908         <span class="comment">/* Disable all active IN EPs */</span>
+<a name="l03909"></a>03909         diepctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#4d76ba4ebd506d3175ec5cdc0d811654">epdis</a> = 1;
+<a name="l03910"></a>03910         diepctl.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#ccf6e60ac8cabde8da36edb19504ba2b">snak</a> = 1;
+<a name="l03911"></a>03911 
+<a name="l03912"></a>03912         <span class="keywordflow">for</span> (i = 0; i &lt;= dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#4fae9bc1293bf2e58966c38fa5b98822">num_in_eps</a>; i++) {
+<a name="l03913"></a>03913                 diepctl_rd.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a> =
+<a name="l03914"></a>03914                     dwc_read_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[i]-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#53a5adb977e2aec66d4902c6ba293216">diepctl</a>);
+<a name="l03915"></a>03915                 if (diepctl_rd.<a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>.<a class="code" href="uniondepctl__data.html#337ceb41a9e0735e144e684b1f9e5368">epena</a>) {
+<a name="l03916"></a>03916                         dwc_write_reg32(&amp;dev_if-&gt;<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[i]-&gt;<a class="code" href="structdwc__otg__dev__in__ep__regs.html#53a5adb977e2aec66d4902c6ba293216">diepctl</a>,
+<a name="l03917"></a>03917                                         diepctl.<a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a>);
+<a name="l03918"></a>03918                 }
+<a name="l03919"></a>03919         }
+<a name="l03920"></a>03920         <span class="comment">/* Disable the Global IN NAK Effective Interrupt */</span>
+<a name="l03921"></a>03921         intr_mask.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#83a6fb180ef8b18faf8d02ba8b50c841">ginnakeff</a> = 1;
+<a name="l03922"></a>03922         dwc_modify_reg32(&amp;<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;core_global_regs-&gt;gintmsk,
+<a name="l03923"></a>03923                          intr_mask.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a>, 0);
+<a name="l03924"></a>03924 
+<a name="l03925"></a>03925         <span class="comment">/* Clear interrupt */</span>
+<a name="l03926"></a>03926         gintsts.d32 = 0;
+<a name="l03927"></a>03927         gintsts.b.ginnakeff = 1;
+<a name="l03928"></a>03928         dwc_write_reg32(&amp;<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;core_global_regs-&gt;gintsts,
+<a name="l03929"></a>03929                         gintsts.d32);
+<a name="l03930"></a>03930 
+<a name="l03931"></a>03931         <span class="keywordflow">return</span> 1;
+<a name="l03932"></a>03932 }
+<a name="l03933"></a>03933 
+<a name="l03938"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#81859010d39b3d8f3348ad0c3ec52ba7">03938</a> int32_t <a class="code" href="dwc__otg__pcd__intr_8c.html#81859010d39b3d8f3348ad0c3ec52ba7">dwc_otg_pcd_handle_out_nak_effective</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd)
+<a name="l03939"></a>03939 {
+<a name="l03940"></a>03940         <a class="code" href="uniongintmsk__data.html">gintmsk_data_t</a> intr_mask = {.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a> = 0 };
+<a name="l03941"></a>03941         <a class="code" href="uniongintsts__data.html">gintsts_data_t</a> gintsts;
+<a name="l03942"></a>03942 
+<a name="l03943"></a>03943         DWC_PRINTF(<span class="stringliteral">"INTERRUPT Handler not implemented for %s\n"</span>,
+<a name="l03944"></a>03944                    <span class="stringliteral">"Global IN NAK Effective\n"</span>);
+<a name="l03945"></a>03945         <span class="comment">/* Disable the Global IN NAK Effective Interrupt */</span>
+<a name="l03946"></a>03946         intr_mask.<a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>.<a class="code" href="uniongintmsk__data.html#1a47902a93203910433a35fab3f5b8a1">goutnakeff</a> = 1;
+<a name="l03947"></a>03947         dwc_modify_reg32(&amp;<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;core_global_regs-&gt;gintmsk,
+<a name="l03948"></a>03948                          intr_mask.<a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a>, 0);
+<a name="l03949"></a>03949 
+<a name="l03950"></a>03950         <span class="comment">/* Clear interrupt */</span>
+<a name="l03951"></a>03951         gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a> = 0;
+<a name="l03952"></a>03952         gintsts.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#5fd87ed0462f444df968567f310488f7">goutnakeff</a> = 1;
+<a name="l03953"></a>03953         dwc_write_reg32(&amp;<a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd)-&gt;core_global_regs-&gt;gintsts,
+<a name="l03954"></a>03954                         gintsts.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a>);
+<a name="l03955"></a>03955 
+<a name="l03956"></a>03956         <span class="keywordflow">return</span> 1;
+<a name="l03957"></a>03957 }
+<a name="l03958"></a>03958 
+<a name="l03971"></a><a class="code" href="dwc__otg__pcd__intr_8c.html#fc60361217d0c5c089f4036d73690689">03971</a> int32_t <a class="code" href="dwc__otg__pcd__if_8h.html#fc60361217d0c5c089f4036d73690689">dwc_otg_pcd_handle_intr</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd)
+<a name="l03972"></a>03972 {
+<a name="l03973"></a>03973         <a class="code" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if = <a class="code" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">GET_CORE_IF</a>(pcd);
+<a name="l03974"></a>03974 <span class="preprocessor">#ifdef VERBOSE</span>
+<a name="l03975"></a>03975 <span class="preprocessor"></span>        <a class="code" href="structdwc__otg__core__global__regs.html">dwc_otg_core_global_regs_t</a> *global_regs = core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a>;
+<a name="l03976"></a>03976 <span class="preprocessor">#endif</span>
+<a name="l03977"></a>03977 <span class="preprocessor"></span>        <a class="code" href="uniongintsts__data.html">gintsts_data_t</a> gintr_status;
+<a name="l03978"></a>03978         int32_t retval = 0;
+<a name="l03979"></a>03979 
+<a name="l03980"></a>03980 <span class="preprocessor">#ifdef VERBOSE</span>
+<a name="l03981"></a>03981 <span class="preprocessor"></span>        <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#2bf62a567355d1ea38814714bd7b57ec">DBG_ANY</a>, <span class="stringliteral">"%s() gintsts=%08x  gintmsk=%08x\n"</span>,
+<a name="l03982"></a>03982                     __func__,
+<a name="l03983"></a>03983                     dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>),
+<a name="l03984"></a>03984                     dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#48827c76da2c6b18f369e2f2483cc4b6">gintmsk</a>));
+<a name="l03985"></a>03985 <span class="preprocessor">#endif</span>
+<a name="l03986"></a>03986 <span class="preprocessor"></span>
+<a name="l03987"></a>03987         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__cil_8c.html#e83fb22890bc54c6b06cedb751430e77">dwc_otg_is_device_mode</a>(core_if)) {
+<a name="l03988"></a>03988                 DWC_SPINLOCK(pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5d450e4d06659ab2f3b18e5c816776e4">lock</a>);
+<a name="l03989"></a>03989 <span class="preprocessor">#ifdef VERBOSE</span>
+<a name="l03990"></a>03990 <span class="preprocessor"></span>                <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"%s() gintsts=%08x  gintmsk=%08x\n"</span>,
+<a name="l03991"></a>03991                             __func__,
+<a name="l03992"></a>03992                             dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>),
+<a name="l03993"></a>03993                             dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#48827c76da2c6b18f369e2f2483cc4b6">gintmsk</a>));
+<a name="l03994"></a>03994 <span class="preprocessor">#endif</span>
+<a name="l03995"></a>03995 <span class="preprocessor"></span>
+<a name="l03996"></a>03996                 gintr_status.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a> = <a class="code" href="dwc__otg__cil_8h.html#639809e3c27026b8f956c2a133b1d433">dwc_otg_read_core_intr</a>(core_if);
+<a name="l03997"></a>03997 
+<a name="l03998"></a>03998                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"%s: gintsts&amp;gintmsk=%08x\n"</span>,
+<a name="l03999"></a>03999                             __func__, gintr_status.<a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a>);
+<a name="l04000"></a>04000 
+<a name="l04001"></a>04001                 <span class="keywordflow">if</span> (gintr_status.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#3f6ba377d6b1449884bb4da1b155c61b">sofintr</a>) {
+<a name="l04002"></a>04002                         retval |= <a class="code" href="dwc__otg__pcd__intr_8c.html#669296a786dcd89220efa8d7f62b10d0">dwc_otg_pcd_handle_sof_intr</a>(pcd);
+<a name="l04003"></a>04003                 }
+<a name="l04004"></a>04004                 <span class="keywordflow">if</span> (gintr_status.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#7595576956c3a0ced9ea387880943012">rxstsqlvl</a>) {
+<a name="l04005"></a>04005                         retval |=
+<a name="l04006"></a>04006                             <a class="code" href="dwc__otg__pcd__intr_8c.html#99560d3941c21dedd1fb1fc846cea24f">dwc_otg_pcd_handle_rx_status_q_level_intr</a>(pcd);
+<a name="l04007"></a>04007                 }
+<a name="l04008"></a>04008                 <span class="keywordflow">if</span> (gintr_status.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#adebf5ff5bdf69a2bcf0bd4b2ba55ef4">nptxfempty</a>) {
+<a name="l04009"></a>04009                         retval |= <a class="code" href="dwc__otg__pcd__intr_8c.html#bc463d6cebcf3da1989eb6d252979554">dwc_otg_pcd_handle_np_tx_fifo_empty_intr</a>(pcd);
+<a name="l04010"></a>04010                 }
+<a name="l04011"></a>04011                 <span class="keywordflow">if</span> (gintr_status.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#15a2e362768704ab6143fea33fc8755b">ginnakeff</a>) {
+<a name="l04012"></a>04012                         retval |= <a class="code" href="dwc__otg__pcd__intr_8c.html#c24d0c885fe79e75d6f738fd9bd9c0d7">dwc_otg_pcd_handle_in_nak_effective</a>(pcd);
+<a name="l04013"></a>04013                 }
+<a name="l04014"></a>04014                 <span class="keywordflow">if</span> (gintr_status.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#5fd87ed0462f444df968567f310488f7">goutnakeff</a>) {
+<a name="l04015"></a>04015                         retval |= <a class="code" href="dwc__otg__pcd__intr_8c.html#81859010d39b3d8f3348ad0c3ec52ba7">dwc_otg_pcd_handle_out_nak_effective</a>(pcd);
+<a name="l04016"></a>04016                 }
+<a name="l04017"></a>04017                 <span class="keywordflow">if</span> (gintr_status.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#2e8bd51ad285fd46db48f9fb5bbb7993">i2cintr</a>) {
+<a name="l04018"></a>04018                         retval |= <a class="code" href="dwc__otg__pcd__intr_8c.html#7d52ad6b49e7495df6c1788b325c510c">dwc_otg_pcd_handle_i2c_intr</a>(pcd);
+<a name="l04019"></a>04019                 }
+<a name="l04020"></a>04020                 <span class="keywordflow">if</span> (gintr_status.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#2659c4ea7b295a089ee498b21b44992b">erlysuspend</a>) {
+<a name="l04021"></a>04021                         retval |= <a class="code" href="dwc__otg__pcd__intr_8c.html#51b8dd218b31a7d79f5cef82c2a497aa">dwc_otg_pcd_handle_early_suspend_intr</a>(pcd);
+<a name="l04022"></a>04022                 }
+<a name="l04023"></a>04023                 <span class="keywordflow">if</span> (gintr_status.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#76926be659d963c79dbcec91e25ce8ed">usbreset</a>) {
+<a name="l04024"></a>04024                         retval |= <a class="code" href="dwc__otg__pcd__intr_8c.html#84746037a82c1f69287033338991d34a">dwc_otg_pcd_handle_usb_reset_intr</a>(pcd);
+<a name="l04025"></a>04025                 }
+<a name="l04026"></a>04026                 <span class="keywordflow">if</span> (gintr_status.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#84e707787b50ee3867786c8e0995f41e">enumdone</a>) {
+<a name="l04027"></a>04027                         retval |= <a class="code" href="dwc__otg__pcd__intr_8c.html#c8003957f588b4bb57061208ea031468">dwc_otg_pcd_handle_enum_done_intr</a>(pcd);
+<a name="l04028"></a>04028                 }
+<a name="l04029"></a>04029                 <span class="keywordflow">if</span> (gintr_status.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#e6e931e1d6226dc110a98cd42c9a8e5f">isooutdrop</a>) {
+<a name="l04030"></a>04030                         retval |=
+<a name="l04031"></a>04031                             <a class="code" href="dwc__otg__pcd__intr_8c.html#7dbc68baede550f27e1507bca8e16c3b">dwc_otg_pcd_handle_isoc_out_packet_dropped_intr</a>
+<a name="l04032"></a>04032                             (pcd);
+<a name="l04033"></a>04033                 }
+<a name="l04034"></a>04034                 <span class="keywordflow">if</span> (gintr_status.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#a731c93eb9e131fadde92da363a85527">eopframe</a>) {
+<a name="l04035"></a>04035                         retval |=
+<a name="l04036"></a>04036                             <a class="code" href="dwc__otg__pcd__intr_8c.html#a0826c93566bb0144e2fce79fd5d459a">dwc_otg_pcd_handle_end_periodic_frame_intr</a>(pcd);
+<a name="l04037"></a>04037                 }
+<a name="l04038"></a>04038                 <span class="keywordflow">if</span> (gintr_status.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#c30e01457b826afc318e5d76e9dfdded">epmismatch</a>) {
+<a name="l04039"></a>04039                         retval |= <a class="code" href="dwc__otg__pcd__intr_8c.html#c45cbe24b507cba84465299e2069ab43">dwc_otg_pcd_handle_ep_mismatch_intr</a>(core_if);
+<a name="l04040"></a>04040                 }
+<a name="l04041"></a>04041                 <span class="keywordflow">if</span> (gintr_status.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#e4e48a2a194cf95d934800a85c12784f">inepint</a>) {
+<a name="l04042"></a>04042                         <span class="keywordflow">if</span> (!core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5675c8d8dd7df746fda9157dc39ba5c2">multiproc_int_enable</a>) {
+<a name="l04043"></a>04043                                 retval |= <a class="code" href="dwc__otg__pcd__intr_8c.html#321d4a511db985443b132c044fc2d69e">dwc_otg_pcd_handle_in_ep_intr</a>(pcd);
+<a name="l04044"></a>04044                         }
+<a name="l04045"></a>04045                 }
+<a name="l04046"></a>04046                 <span class="keywordflow">if</span> (gintr_status.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#58c08d29fa4b120748eb01b0d989facf">outepintr</a>) {
+<a name="l04047"></a>04047                         <span class="keywordflow">if</span> (!core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5675c8d8dd7df746fda9157dc39ba5c2">multiproc_int_enable</a>) {
+<a name="l04048"></a>04048                                 retval |= <a class="code" href="dwc__otg__pcd__intr_8c.html#8b24f400f2eb83ea262e27f5cd1bb707">dwc_otg_pcd_handle_out_ep_intr</a>(pcd);
+<a name="l04049"></a>04049                         }
+<a name="l04050"></a>04050                 }
+<a name="l04051"></a>04051                 <span class="keywordflow">if</span> (gintr_status.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#6a2b4a287af4632cec2207fe6fb91e86">incomplisoin</a>) {
+<a name="l04052"></a>04052                         retval |=
+<a name="l04053"></a>04053                             <a class="code" href="dwc__otg__pcd__intr_8c.html#aa9fd9a6774ed616e31df65fe326351b">dwc_otg_pcd_handle_incomplete_isoc_in_intr</a>(pcd);
+<a name="l04054"></a>04054                 }
+<a name="l04055"></a>04055                 <span class="keywordflow">if</span> (gintr_status.<a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>.<a class="code" href="uniongintsts__data.html#519e2237cad3f43ebb7665e8d24c0180">incomplisoout</a>) {
+<a name="l04056"></a>04056                         retval |=
+<a name="l04057"></a>04057                             <a class="code" href="dwc__otg__pcd__intr_8c.html#8277c5761c3865fbb3646ba496a4901e">dwc_otg_pcd_handle_incomplete_isoc_out_intr</a>(pcd);
+<a name="l04058"></a>04058                 }
+<a name="l04059"></a>04059 
+<a name="l04060"></a>04060                 <span class="comment">/* In MPI mode De vice Endpoints intterrupts are asserted </span>
+<a name="l04061"></a>04061 <span class="comment">                 * without setting outepintr and inepint bits set, so these</span>
+<a name="l04062"></a>04062 <span class="comment">                 * Interrupt handlers are called without checking these bit-fields</span>
+<a name="l04063"></a>04063 <span class="comment">                 */</span>
+<a name="l04064"></a>04064                 <span class="keywordflow">if</span> (core_if-&gt;<a class="code" href="structdwc__otg__core__if.html#5675c8d8dd7df746fda9157dc39ba5c2">multiproc_int_enable</a>) {
+<a name="l04065"></a>04065                         retval |= <a class="code" href="dwc__otg__pcd__intr_8c.html#321d4a511db985443b132c044fc2d69e">dwc_otg_pcd_handle_in_ep_intr</a>(pcd);
+<a name="l04066"></a>04066                         retval |= <a class="code" href="dwc__otg__pcd__intr_8c.html#8b24f400f2eb83ea262e27f5cd1bb707">dwc_otg_pcd_handle_out_ep_intr</a>(pcd);
+<a name="l04067"></a>04067                 }
+<a name="l04068"></a>04068 <span class="preprocessor">#ifdef VERBOSE</span>
+<a name="l04069"></a>04069 <span class="preprocessor"></span>                <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"%s() gintsts=%0x\n"</span>, __func__,
+<a name="l04070"></a>04070                             dwc_read_reg32(&amp;global_regs-&gt;<a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>));
+<a name="l04071"></a>04071 <span class="preprocessor">#endif</span>
+<a name="l04072"></a>04072 <span class="preprocessor"></span>                DWC_SPINUNLOCK(pcd-&gt;<a class="code" href="structdwc__otg__pcd.html#5d450e4d06659ab2f3b18e5c816776e4">lock</a>);
+<a name="l04073"></a>04073         }
+<a name="l04074"></a>04074         <span class="keywordflow">return</span> retval;
+<a name="l04075"></a>04075 }
+<a name="l04076"></a>04076 
+<a name="l04077"></a>04077 <span class="preprocessor">#endif                          </span><span class="comment">/* DWC_HOST_ONLY */</span>
+</pre></div><hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__intr_8c.html b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__intr_8c.html
new file mode 100644
index 000000000000..0356970db980
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__intr_8c.html
@@ -0,0 +1,1599 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd_intr.c File Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<h1>dwc_otg_pcd_intr.c File Reference</h1>This file contains the implementation of the PCD Interrupt handlers. <a href="#_details">More...</a>
+<p>
+<code>#include &quot;<a class="el" href="dwc__otg__pcd_8h-source.html">dwc_otg_pcd.h</a>&quot;</code><br>
+
+<p>
+<a href="dwc__otg__pcd__intr_8c-source.html">Go to the source code of this file.</a><table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Defines</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="1d4105869a3a5ce989afa5124218de0a"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::DEBUG_EP0" ref="1d4105869a3a5ce989afa5124218de0a" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#1d4105869a3a5ce989afa5124218de0a">DEBUG_EP0</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>CLEAR_IN_EP_INTR</b>(__core_if, __epnum, __intr)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><b>CLEAR_OUT_EP_INTR</b>(__core_if, __epnum, __intr)</td></tr>
+
+<tr><td colspan="2"><br><h2>Functions</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="81a9361b81863cef6b2566ea44529185"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::dwc_otg_pcd_update_otg" ref="81a9361b81863cef6b2566ea44529185" args="(dwc_otg_pcd_t *pcd, const unsigned reset)" -->
+static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#81a9361b81863cef6b2566ea44529185">dwc_otg_pcd_update_otg</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, const unsigned reset)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function updates OTG. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="13cc45eef95b81189df890c10cf7ca66"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::print_ep0_state" ref="13cc45eef95b81189df890c10cf7ca66" args="(dwc_otg_pcd_t *pcd)" -->
+static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#13cc45eef95b81189df890c10cf7ca66">print_ep0_state</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function prints the ep0 state for debug purposes. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="cc3f2f1ae0ab7d33903a1d0d9097c04e"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::get_in_ep" ref="cc3f2f1ae0ab7d33903a1d0d9097c04e" args="(dwc_otg_pcd_t *pcd, uint32_t ep_num)" -->
+static <a class="el" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#cc3f2f1ae0ab7d33903a1d0d9097c04e">get_in_ep</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, uint32_t ep_num)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function returns pointer to in ep struct with number ep_num. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="fbd54e53e1968d3b4798ea1b63b52f74"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::get_out_ep" ref="fbd54e53e1968d3b4798ea1b63b52f74" args="(dwc_otg_pcd_t *pcd, uint32_t ep_num)" -->
+static <a class="el" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#fbd54e53e1968d3b4798ea1b63b52f74">get_out_ep</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, uint32_t ep_num)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function returns pointer to out ep struct with number ep_num. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3c351d7f51d6242296d6ea3bb1a9775c"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::get_ep_by_addr" ref="3c351d7f51d6242296d6ea3bb1a9775c" args="(dwc_otg_pcd_t *pcd, u16 wIndex)" -->
+<a class="el" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#3c351d7f51d6242296d6ea3bb1a9775c">get_ep_by_addr</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, u16 wIndex)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This functions gets a pointer to an EP from the wIndex address value of the control request. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="de7160b7e7b8fd622ba95392513e197c"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::start_next_request" ref="de7160b7e7b8fd622ba95392513e197c" args="(dwc_otg_pcd_ep_t *ep)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#de7160b7e7b8fd622ba95392513e197c">start_next_request</a> (<a class="el" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *ep)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Tasklet. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#669296a786dcd89220efa8d7f62b10d0">dwc_otg_pcd_handle_sof_intr</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function handles the SOF Interrupts.  <a href="#669296a786dcd89220efa8d7f62b10d0"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#99560d3941c21dedd1fb1fc846cea24f">dwc_otg_pcd_handle_rx_status_q_level_intr</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function handles the Rx Status Queue Level Interrupt, which indicates that there is a least one packet in the Rx FIFO.  <a href="#99560d3941c21dedd1fb1fc846cea24f"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#fde237571d3aaa5d03376d3bee827075">get_ep_of_last_in_token</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function examines the Device IN Token Learning Queue to determine the EP number of the last IN token received.  <a href="#fde237571d3aaa5d03376d3bee827075"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#bc463d6cebcf3da1989eb6d252979554">dwc_otg_pcd_handle_np_tx_fifo_empty_intr</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This interrupt occurs when the non-periodic Tx FIFO is half-empty.  <a href="#bc463d6cebcf3da1989eb6d252979554"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#5e53962e63763aa9df6400981b7d5354">write_empty_tx_fifo</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, uint32_t epnum)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function is called when dedicated Tx FIFO Empty interrupt occurs.  <a href="#5e53962e63763aa9df6400981b7d5354"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#19e17d6a73d8a3ebf00a1d11999a5ff9">dwc_otg_pcd_stop</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function is called when the Device is disconnected.  <a href="#19e17d6a73d8a3ebf00a1d11999a5ff9"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#7d52ad6b49e7495df6c1788b325c510c">dwc_otg_pcd_handle_i2c_intr</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This interrupt indicates that .  <a href="#7d52ad6b49e7495df6c1788b325c510c"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#51b8dd218b31a7d79f5cef82c2a497aa">dwc_otg_pcd_handle_early_suspend_intr</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This interrupt indicates that .  <a href="#51b8dd218b31a7d79f5cef82c2a497aa"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#726b57833bb3ae4648ce7e7a7e125bf7">ep0_out_start</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, <a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function configures EPO to receive SETUP packets.  <a href="#726b57833bb3ae4648ce7e7a7e125bf7"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#84746037a82c1f69287033338991d34a">dwc_otg_pcd_handle_usb_reset_intr</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This interrupt occurs when a USB Reset is detected.  <a href="#84746037a82c1f69287033338991d34a"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#6a3ddac8955990b9a63646c40c65446b">get_device_speed</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get the device speed from the device status register and convert it to USB speed constant.  <a href="#6a3ddac8955990b9a63646c40c65446b"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#c8003957f588b4bb57061208ea031468">dwc_otg_pcd_handle_enum_done_intr</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Read the device status register and set the device speed in the data structure.  <a href="#c8003957f588b4bb57061208ea031468"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#7dbc68baede550f27e1507bca8e16c3b">dwc_otg_pcd_handle_isoc_out_packet_dropped_intr</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This interrupt indicates that the ISO OUT Packet was dropped due to Rx FIFO full or Rx Status Queue Full.  <a href="#7dbc68baede550f27e1507bca8e16c3b"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#a0826c93566bb0144e2fce79fd5d459a">dwc_otg_pcd_handle_end_periodic_frame_intr</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This interrupt indicates the end of the portion of the micro-frame for periodic transactions.  <a href="#a0826c93566bb0144e2fce79fd5d459a"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#c45cbe24b507cba84465299e2069ab43">dwc_otg_pcd_handle_ep_mismatch_intr</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This interrupt indicates that EP of the packet on the top of the non-periodic Tx FIFO does not match EP of the IN Token received.  <a href="#c45cbe24b507cba84465299e2069ab43"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="325b13e198ff56e9de2600ac7f28a57d"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::ep0_do_stall" ref="325b13e198ff56e9de2600ac7f28a57d" args="(dwc_otg_pcd_t *pcd, const int err_val)" -->
+static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#325b13e198ff56e9de2600ac7f28a57d">ep0_do_stall</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, const int err_val)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This funcion stalls EP0. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#6c417c7d86bc9540e13ca4faeaf3dfbf">do_gadget_setup</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, usb_device_request_t *ctrl)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This functions delegates the setup command to the gadget driver.  <a href="#6c417c7d86bc9540e13ca4faeaf3dfbf"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="39d3face14e49b0f1ad5c978f87665fe"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::do_setup_in_status_phase" ref="39d3face14e49b0f1ad5c978f87665fe" args="(dwc_otg_pcd_t *pcd)" -->
+static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#39d3face14e49b0f1ad5c978f87665fe">do_setup_in_status_phase</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function starts the Zero-Length Packet for the IN status phase of a 2 stage control transfer. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="cce0022b7577cda90a2d2e78e1f8171b"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::do_setup_out_status_phase" ref="cce0022b7577cda90a2d2e78e1f8171b" args="(dwc_otg_pcd_t *pcd)" -->
+static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#cce0022b7577cda90a2d2e78e1f8171b">do_setup_out_status_phase</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function starts the Zero-Length Packet for the OUT status phase of a 2 stage control transfer. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#153d9a3b2162ef091dc24027379af19f">pcd_clear_halt</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, <a class="el" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *ep)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Clear the EP halt (STALL) and if pending requests start the transfer.  <a href="#153d9a3b2162ef091dc24027379af19f"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#9d6d6e24faab6478aef9e2217c9b5ab9">do_test_mode</a> (void *data)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function is called when the SET_FEATURE TEST_MODE Setup packet is sent from the host.  <a href="#9d6d6e24faab6478aef9e2217c9b5ab9"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#f449add2b4e8de7ced10fd1bb4c5b748">do_get_status</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function process the GET_STATUS Setup Commands.  <a href="#f449add2b4e8de7ced10fd1bb4c5b748"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#3754b29956ab3a85851dea376e046db9">do_set_feature</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function process the SET_FEATURE Setup Commands.  <a href="#3754b29956ab3a85851dea376e046db9"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#2198ea3f0136465fa325a189d4ba5140">do_clear_feature</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function process the CLEAR_FEATURE Setup Commands.  <a href="#2198ea3f0136465fa325a189d4ba5140"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f653efb69491b3e293cab4a33940ac3d"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::do_set_address" ref="f653efb69491b3e293cab4a33940ac3d" args="(dwc_otg_pcd_t *pcd)" -->
+static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#f653efb69491b3e293cab4a33940ac3d">do_set_address</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function process the SET_ADDRESS Setup Commands. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#856a520a378e4f6f274253227080cfa1">pcd_setup</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function processes SETUP commands.  <a href="#856a520a378e4f6f274253227080cfa1"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f64bfae20151c51d3b0a6d4e523f356e"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::ep0_complete_request" ref="f64bfae20151c51d3b0a6d4e523f356e" args="(dwc_otg_pcd_ep_t *ep)" -->
+static int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#f64bfae20151c51d3b0a6d4e523f356e">ep0_complete_request</a> (<a class="el" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *ep)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function completes the ep0 control transfer. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#c77f277130ba55b19100bde598da7d85">complete_ep</a> (<a class="el" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *ep)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function completes the request for the EP.  <a href="#c77f277130ba55b19100bde598da7d85"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="1edc1970063b8383cda91e9d8581f3ac"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::dwc_otg_pcd_handle_iso_bna" ref="1edc1970063b8383cda91e9d8581f3ac" args="(dwc_otg_pcd_ep_t *ep)" -->
+static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#1edc1970063b8383cda91e9d8581f3ac">dwc_otg_pcd_handle_iso_bna</a> (<a class="el" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *ep)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function BNA interrupt for Isochronous EPs. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#17428b2360118cc59ab9d5cbcef8a14b">set_current_pkt_info</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, <a class="el" href="structdwc__ep.html">dwc_ep_t</a> *ep)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function sets latest iso packet information(non-PTI mode).  <a href="#17428b2360118cc59ab9d5cbcef8a14b"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#e5ed26b3ab2380cb92773df1720ec752">set_ddma_iso_pkts_info</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, <a class="el" href="structdwc__ep.html">dwc_ep_t</a> *<a class="el" href="structdwc__ep.html">dwc_ep</a>)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function sets latest iso packet information(DDMA mode).  <a href="#e5ed26b3ab2380cb92773df1720ec752"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#c3f6fb3131e0786ec75a9c4a29fea297">reinit_ddma_iso_xfer</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, <a class="el" href="structdwc__ep.html">dwc_ep_t</a> *<a class="el" href="structdwc__ep.html">dwc_ep</a>)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function reinitialize DMA Descriptors for Isochronous transfer.  <a href="#c3f6fb3131e0786ec75a9c4a29fea297"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#41cfc0d590740640795b350998bcc2c4">handle_iso_out_pkt_dropped</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, <a class="el" href="structdwc__ep.html">dwc_ep_t</a> *<a class="el" href="structdwc__ep.html">dwc_ep</a>)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function is to handle Iso EP transfer complete interrupt in case Iso out packet was dropped.  <a href="#41cfc0d590740640795b350998bcc2c4"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#a356ecc4053e9700785a27dbfdd6b2db">set_iso_pkts_info</a> (<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *core_if, <a class="el" href="structdwc__ep.html">dwc_ep_t</a> *ep)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function sets iso packets information(PTI mode).  <a href="#a356ecc4053e9700785a27dbfdd6b2db"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#05965765a43225780ae08f2c3928f782">complete_iso_ep</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, <a class="el" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *ep)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function is to handle Iso EP transfer complete interrupt.  <a href="#05965765a43225780ae08f2c3928f782"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#4991119b51de03163a3677c36bc0ee3b">handle_ep0</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function handles EP0 Control transfers.  <a href="#4991119b51de03163a3677c36bc0ee3b"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ed405cebf67cd1a89efd15a2935c8cef"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::restart_transfer" ref="ed405cebf67cd1a89efd15a2935c8cef" args="(dwc_otg_pcd_t *pcd, const uint32_t epnum)" -->
+static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#ed405cebf67cd1a89efd15a2935c8cef">restart_transfer</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, const uint32_t epnum)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Restart transfer. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="6c9df42abc5cb6f676a44918207c91b7"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::handle_in_ep_disable_intr" ref="6c9df42abc5cb6f676a44918207c91b7" args="(dwc_otg_pcd_t *pcd, const uint32_t epnum)" -->
+static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#6c9df42abc5cb6f676a44918207c91b7">handle_in_ep_disable_intr</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, const uint32_t epnum)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">handle the IN EP disable interrupt. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#65d4f747d13e368916ee0e16d202119b">handle_in_ep_timeout_intr</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, const uint32_t epnum)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Handler for the IN EP timeout handshake interrupt.  <a href="#65d4f747d13e368916ee0e16d202119b"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#273ccc8e8cdb9e2075844f2f922b53bf">handle_in_ep_nak_intr</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, const uint32_t epnum)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Handler for the IN EP NAK interrupt.  <a href="#273ccc8e8cdb9e2075844f2f922b53bf"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#42aef7ea134cccf7cdb53e7e1428bc4a">handle_out_ep_babble_intr</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, const uint32_t epnum)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Handler for the OUT EP Babble interrupt.  <a href="#42aef7ea134cccf7cdb53e7e1428bc4a"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#252929e585c84eaf0485869cd7734244">handle_out_ep_nak_intr</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, const uint32_t epnum)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Handler for the OUT EP NAK interrupt.  <a href="#252929e585c84eaf0485869cd7734244"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#926d9068c1950cc406d50828e72a31db">handle_out_ep_nyet_intr</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, const uint32_t epnum)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Handler for the OUT EP NYET interrupt.  <a href="#926d9068c1950cc406d50828e72a31db"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#321d4a511db985443b132c044fc2d69e">dwc_otg_pcd_handle_in_ep_intr</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This interrupt indicates that an IN EP has a pending Interrupt.  <a href="#321d4a511db985443b132c044fc2d69e"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#8b24f400f2eb83ea262e27f5cd1bb707">dwc_otg_pcd_handle_out_ep_intr</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This interrupt indicates that an OUT EP has a pending Interrupt.  <a href="#8b24f400f2eb83ea262e27f5cd1bb707"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#aa9fd9a6774ed616e31df65fe326351b">dwc_otg_pcd_handle_incomplete_isoc_in_intr</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Incomplete ISO IN Transfer Interrupt.  <a href="#aa9fd9a6774ed616e31df65fe326351b"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#8277c5761c3865fbb3646ba496a4901e">dwc_otg_pcd_handle_incomplete_isoc_out_intr</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Incomplete ISO OUT Transfer Interrupt.  <a href="#8277c5761c3865fbb3646ba496a4901e"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c24d0c885fe79e75d6f738fd9bd9c0d7"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::dwc_otg_pcd_handle_in_nak_effective" ref="c24d0c885fe79e75d6f738fd9bd9c0d7" args="(dwc_otg_pcd_t *pcd)" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#c24d0c885fe79e75d6f738fd9bd9c0d7">dwc_otg_pcd_handle_in_nak_effective</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function handles the Global IN NAK Effective interrupt. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="81859010d39b3d8f3348ad0c3ec52ba7"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::dwc_otg_pcd_handle_out_nak_effective" ref="81859010d39b3d8f3348ad0c3ec52ba7" args="(dwc_otg_pcd_t *pcd)" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#81859010d39b3d8f3348ad0c3ec52ba7">dwc_otg_pcd_handle_out_nak_effective</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">OUT NAK Effective. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__intr_8c.html#fc60361217d0c5c089f4036d73690689">dwc_otg_pcd_handle_intr</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function should be called on every hardware interrupt.  <a href="#fc60361217d0c5c089f4036d73690689"></a><br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This file contains the implementation of the PCD Interrupt handlers. 
+<p>
+The PCD handles the device interrupts. Many conditions can cause a device interrupt. When an interrupt occurs, the device interrupt service routine determines the cause of the interrupt and dispatches handling to the appropriate function. These interrupt handling functions are described below. All interrupt registers are processed from LSB to MSB. 
+<p>
+Definition in file <a class="el" href="dwc__otg__pcd__intr_8c-source.html">dwc_otg_pcd_intr.c</a>.<hr><h2>Define Documentation</h2>
+<a class="anchor" name="d52033d9f52a0eb279293001990b187c"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::CLEAR_IN_EP_INTR" ref="d52033d9f52a0eb279293001990b187c" args="(__core_if, __epnum, __intr)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define CLEAR_IN_EP_INTR          </td>
+          <td>(</td>
+          <td class="paramtype">__core_if,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">__epnum,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">__intr&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keywordflow">do</span> { \
+                <a class="code" href="uniondiepint__data.html">diepint_data_t</a> diepint = {.d32=0}; \
+                diepint.<a class="code" href="uniondiepint__data.html#48d2a745e0ec983a47b35b0428b0437d">b</a>.__intr = 1; \
+                dwc_write_reg32(&amp;__core_if-&gt;dev_if-&gt;in_ep_regs[__epnum]-&gt;diepint, \
+                diepint.<a class="code" href="uniondiepint__data.html#7d2c24507663bf96c280c57fbf544ef7">d32</a>); \
+} <span class="keywordflow">while</span> (0)
+</pre></div>
+</div>
+</div><p>
+<a class="anchor" name="d6d2a852568e99dc9f19f5a61e6c8fb3"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::CLEAR_OUT_EP_INTR" ref="d6d2a852568e99dc9f19f5a61e6c8fb3" args="(__core_if, __epnum, __intr)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define CLEAR_OUT_EP_INTR          </td>
+          <td>(</td>
+          <td class="paramtype">__core_if,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">__epnum,         <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">__intr&nbsp;</td>
+          <td class="paramname">          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Value:</b><div class="fragment"><pre class="fragment"><span class="keywordflow">do</span> { \
+                <a class="code" href="uniondoepint__data.html">doepint_data_t</a> doepint = {.d32=0}; \
+                doepint.<a class="code" href="uniondoepint__data.html#9e966d9f85589f278dc2c0d0c7833856">b</a>.__intr = 1; \
+                dwc_write_reg32(&amp;__core_if-&gt;dev_if-&gt;out_ep_regs[__epnum]-&gt;doepint, \
+                doepint.<a class="code" href="uniondoepint__data.html#94f8c8fc116b430565f9322e3621b3a5">d32</a>); \
+} <span class="keywordflow">while</span> (0)
+</pre></div>
+</div>
+</div><p>
+<hr><h2>Function Documentation</h2>
+<a class="anchor" name="669296a786dcd89220efa8d7f62b10d0"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::dwc_otg_pcd_handle_sof_intr" ref="669296a786dcd89220efa8d7f62b10d0" args="(dwc_otg_pcd_t *pcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t dwc_otg_pcd_handle_sof_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function handles the SOF Interrupts. 
+<p>
+At this time the SOF Interrupt is disabled. 
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__intr_8c-source.html#l00252">252</a> of file <a class="el" href="dwc__otg__pcd__intr_8c-source.html">dwc_otg_pcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="99560d3941c21dedd1fb1fc846cea24f"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::dwc_otg_pcd_handle_rx_status_q_level_intr" ref="99560d3941c21dedd1fb1fc846cea24f" args="(dwc_otg_pcd_t *pcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t dwc_otg_pcd_handle_rx_status_q_level_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function handles the Rx Status Queue Level Interrupt, which indicates that there is a least one packet in the Rx FIFO. 
+<p>
+The packets are moved from the FIFO to memory, where they will be processed when the Endpoint Interrupt Register indicates Transfer Complete or SETUP Phase Done.<p>
+Repeat the following until the Rx Status Queue is empty:<ol type=1>
+<li>Read the Receive Status Pop Register (GRXSTSP) to get Packet info</li><li>If Receive FIFO is empty then skip to step Clear the interrupt and exit</li><li>If SETUP Packet call dwc_otg_read_setup_packet to copy the SETUP data to the buffer</li><li>If OUT Data Packet call dwc_otg_read_packet to copy the data to the destination buffer </li></ol>
+
+<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000026">Todo:</a></b></dt><dd>NGS Check for buffer overflow? </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__intr_8c-source.html#l00285">285</a> of file <a class="el" href="dwc__otg__pcd__intr_8c-source.html">dwc_otg_pcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="fde237571d3aaa5d03376d3bee827075"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::get_ep_of_last_in_token" ref="fde237571d3aaa5d03376d3bee827075" args="(dwc_otg_core_if_t *core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static int get_ep_of_last_in_token           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [inline, static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function examines the Device IN Token Learning Queue to determine the EP number of the last IN token received. 
+<p>
+This implementation is for the Mass Storage device where there are only 2 IN EPs (Control-IN and BULK-IN).<p>
+The EP numbers for the first six IN Tokens are in DTKNQR1 and there are 8 EP Numbers in each of the other possible DTKNQ Registers.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+  </table>
+</dl>
+
+<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000027">Todo:</a></b></dt><dd>Find a simpler way to calculate the max queue position. </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__intr_8c-source.html#l00378">378</a> of file <a class="el" href="dwc__otg__pcd__intr_8c-source.html">dwc_otg_pcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="bc463d6cebcf3da1989eb6d252979554"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::dwc_otg_pcd_handle_np_tx_fifo_empty_intr" ref="bc463d6cebcf3da1989eb6d252979554" args="(dwc_otg_pcd_t *pcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t dwc_otg_pcd_handle_np_tx_fifo_empty_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This interrupt occurs when the non-periodic Tx FIFO is half-empty. 
+<p>
+The active request is checked for the next packet to be loaded into the non-periodic Tx FIFO. 
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__intr_8c-source.html#l00451">451</a> of file <a class="el" href="dwc__otg__pcd__intr_8c-source.html">dwc_otg_pcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="5e53962e63763aa9df6400981b7d5354"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::write_empty_tx_fifo" ref="5e53962e63763aa9df6400981b7d5354" args="(dwc_otg_pcd_t *pcd, uint32_t epnum)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static int32_t write_empty_tx_fifo           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint32_t&nbsp;</td>
+          <td class="paramname"> <em>epnum</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function is called when dedicated Tx FIFO Empty interrupt occurs. 
+<p>
+The active request is checked for the next packet to be loaded into apropriate Tx FIFO. 
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__intr_8c-source.html#l00515">515</a> of file <a class="el" href="dwc__otg__pcd__intr_8c-source.html">dwc_otg_pcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="19e17d6a73d8a3ebf00a1d11999a5ff9"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::dwc_otg_pcd_stop" ref="19e17d6a73d8a3ebf00a1d11999a5ff9" args="(dwc_otg_pcd_t *pcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void dwc_otg_pcd_stop           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function is called when the Device is disconnected. 
+<p>
+It stops any active requests and informs the Gadget driver of the disconnect. 
+<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000028">Todo:</a></b></dt><dd>NGS Flush Periodic FIFOs </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__intr_8c-source.html#l00573">573</a> of file <a class="el" href="dwc__otg__pcd__intr_8c-source.html">dwc_otg_pcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="7d52ad6b49e7495df6c1788b325c510c"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::dwc_otg_pcd_handle_i2c_intr" ref="7d52ad6b49e7495df6c1788b325c510c" args="(dwc_otg_pcd_t *pcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t dwc_otg_pcd_handle_i2c_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This interrupt indicates that . 
+<p>
+.. 
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__intr_8c-source.html#l00632">632</a> of file <a class="el" href="dwc__otg__pcd__intr_8c-source.html">dwc_otg_pcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="51b8dd218b31a7d79f5cef82c2a497aa"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::dwc_otg_pcd_handle_early_suspend_intr" ref="51b8dd218b31a7d79f5cef82c2a497aa" args="(dwc_otg_pcd_t *pcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t dwc_otg_pcd_handle_early_suspend_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This interrupt indicates that . 
+<p>
+.. 
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__intr_8c-source.html#l00653">653</a> of file <a class="el" href="dwc__otg__pcd__intr_8c-source.html">dwc_otg_pcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="726b57833bb3ae4648ce7e7a7e125bf7"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::ep0_out_start" ref="726b57833bb3ae4648ce7e7a7e125bf7" args="(dwc_otg_core_if_t *core_if, dwc_otg_pcd_t *pcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static void ep0_out_start           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [inline, static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function configures EPO to receive SETUP packets. 
+<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000029">Todo:</a></b></dt><dd>NGS: Update the comments from the HW FS.</dd></dl>
+<ol type=1>
+<li>Program the following fields in the endpoint specific registers for Control OUT EP 0, in order to receive a setup packet</li></ol>
+<ul>
+<li>DOEPTSIZ0.Packet Count = 3 (To receive up to 3 back to back setup packets)</li><li>DOEPTSIZE0.Transfer Size = 24 Bytes (To receive up to 3 back to back setup packets)<ul>
+<li>In DMA mode, DOEPDMA0 Register with a memory address to store any setup packets received</li></ul>
+</li></ul>
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>pcd</em>&nbsp;</td><td>Programming view of the PCD. </td></tr>
+  </table>
+</dl>
+
+<p>
+put here as for Hermes mode deptisz register should not be written<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000029">Todo:</a></b></dt><dd>dma needs to handle multiple setup packets (up to 3) </dd></dl>
+<p>
+DMA Descriptor Setup<p>
+DOEPDMA0 Register write<p>
+put here as for Hermes mode deptisz register should not be written<p>
+DOEPCTL0 Register write 
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__intr_8c-source.html#l00684">684</a> of file <a class="el" href="dwc__otg__pcd__intr_8c-source.html">dwc_otg_pcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="84746037a82c1f69287033338991d34a"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::dwc_otg_pcd_handle_usb_reset_intr" ref="84746037a82c1f69287033338991d34a" args="(dwc_otg_pcd_t *pcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t dwc_otg_pcd_handle_usb_reset_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This interrupt occurs when a USB Reset is detected. 
+<p>
+When the USB Reset Interrupt occurs the device state is set to DEFAULT and the EP0 state is set to IDLE.<ol type=1>
+<li>Set the NAK bit for all OUT endpoints (DOEPCTLn.SNAK = 1)</li><li>Unmask the following interrupt bits<ul>
+<li>DAINTMSK.INEP0 = 1 (Control 0 IN endpoint)</li></ul>
+</li></ol>
+<ul>
+<li>DAINTMSK.OUTEP0 = 1 (Control 0 OUT endpoint)</li><li>DOEPMSK.SETUP = 1</li><li>DOEPMSK.XferCompl = 1</li><li>DIEPMSK.XferCompl = 1</li><li>DIEPMSK.TimeOut = 1</li></ul>
+<ol type=1>
+<li>Program the following fields in the endpoint specific registers for Control OUT EP 0, in order to receive a setup packet</li></ol>
+<ul>
+<li>DOEPTSIZ0.Packet Count = 3 (To receive up to 3 back to back setup packets)</li><li>DOEPTSIZE0.Transfer Size = 24 Bytes (To receive up to 3 back to back setup packets)<ul>
+<li>In DMA mode, DOEPDMA0 Register with a memory address to store any setup packets received At this point, all the required initialization, except for enabling the control 0 OUT endpoint is done, for receiving SETUP packets. </li></ul>
+</li></ul>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__intr_8c-source.html#l00772">772</a> of file <a class="el" href="dwc__otg__pcd__intr_8c-source.html">dwc_otg_pcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="6a3ddac8955990b9a63646c40c65446b"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::get_device_speed" ref="6a3ddac8955990b9a63646c40c65446b" args="(dwc_otg_core_if_t *core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static int get_device_speed           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Get the device speed from the device status register and convert it to USB speed constant. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__intr_8c-source.html#l00928">928</a> of file <a class="el" href="dwc__otg__pcd__intr_8c-source.html">dwc_otg_pcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="c8003957f588b4bb57061208ea031468"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::dwc_otg_pcd_handle_enum_done_intr" ref="c8003957f588b4bb57061208ea031468" args="(dwc_otg_pcd_t *pcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t dwc_otg_pcd_handle_enum_done_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Read the device status register and set the device speed in the data structure. 
+<p>
+Set up EP0 to receive SETUP packets by calling dwc_ep0_activate. 
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__intr_8c-source.html#l00956">956</a> of file <a class="el" href="dwc__otg__pcd__intr_8c-source.html">dwc_otg_pcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="7dbc68baede550f27e1507bca8e16c3b"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::dwc_otg_pcd_handle_isoc_out_packet_dropped_intr" ref="7dbc68baede550f27e1507bca8e16c3b" args="(dwc_otg_pcd_t *pcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t dwc_otg_pcd_handle_isoc_out_packet_dropped_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This interrupt indicates that the ISO OUT Packet was dropped due to Rx FIFO full or Rx Status Queue Full. 
+<p>
+If this interrupt occurs read all the data from the Rx FIFO. 
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__intr_8c-source.html#l01051">1051</a> of file <a class="el" href="dwc__otg__pcd__intr_8c-source.html">dwc_otg_pcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="a0826c93566bb0144e2fce79fd5d459a"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::dwc_otg_pcd_handle_end_periodic_frame_intr" ref="a0826c93566bb0144e2fce79fd5d459a" args="(dwc_otg_pcd_t *pcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t dwc_otg_pcd_handle_end_periodic_frame_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This interrupt indicates the end of the portion of the micro-frame for periodic transactions. 
+<p>
+If there is a periodic transaction for the next frame, load the packets into the EP periodic Tx FIFO. 
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__intr_8c-source.html#l01077">1077</a> of file <a class="el" href="dwc__otg__pcd__intr_8c-source.html">dwc_otg_pcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="c45cbe24b507cba84465299e2069ab43"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::dwc_otg_pcd_handle_ep_mismatch_intr" ref="c45cbe24b507cba84465299e2069ab43" args="(dwc_otg_core_if_t *core_if)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t dwc_otg_pcd_handle_ep_mismatch_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This interrupt indicates that EP of the packet on the top of the non-periodic Tx FIFO does not match EP of the IN Token received. 
+<p>
+The "Device IN Token Queue" Registers are read to determine the order the IN Tokens have been received. The non-periodic Tx FIFO is flushed, so it can be reloaded in the order seen in the IN Token Queue. 
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__intr_8c-source.html#l01105">1105</a> of file <a class="el" href="dwc__otg__pcd__intr_8c-source.html">dwc_otg_pcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="6c417c7d86bc9540e13ca4faeaf3dfbf"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::do_gadget_setup" ref="6c417c7d86bc9540e13ca4faeaf3dfbf" args="(dwc_otg_pcd_t *pcd, usb_device_request_t *ctrl)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static void do_gadget_setup           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">usb_device_request_t *&nbsp;</td>
+          <td class="paramname"> <em>ctrl</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [inline, static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This functions delegates the setup command to the gadget driver. 
+<p>
+
+<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000031">Todo:</a></b></dt><dd>This is a g_file_storage gadget driver specific workaround: a DELAYED_STATUS result from the fsg_setup routine will result in the gadget queueing a EP0 IN status phase for a two-stage control transfer. Exactly the same as a SET_CONFIGURATION/SET_INTERFACE except that this is a class specific request. Need a generic way to know when the gadget driver will queue the status phase. Can we assume when we call the gadget driver setup() function that it will always queue and require the following flag? Need to look into this. </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__intr_8c-source.html#l01138">1138</a> of file <a class="el" href="dwc__otg__pcd__intr_8c-source.html">dwc_otg_pcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="153d9a3b2162ef091dc24027379af19f"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::pcd_clear_halt" ref="153d9a3b2162ef091dc24027379af19f" args="(dwc_otg_pcd_t *pcd, dwc_otg_pcd_ep_t *ep)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static void pcd_clear_halt           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>ep</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [inline, static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Clear the EP halt (STALL) and if pending requests start the transfer. 
+<p>
+
+<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000032">Todo:</a></b></dt><dd>FIXME: this causes an EP mismatch in DMA mode. epmismatch not yet implemented. </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__intr_8c-source.html#l01245">1245</a> of file <a class="el" href="dwc__otg__pcd__intr_8c-source.html">dwc_otg_pcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="9d6d6e24faab6478aef9e2217c9b5ab9"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::do_test_mode" ref="9d6d6e24faab6478aef9e2217c9b5ab9" args="(void *data)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void do_test_mode           </td>
+          <td>(</td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>data</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function is called when the SET_FEATURE TEST_MODE Setup packet is sent from the host. 
+<p>
+The Device Control register is written with the Test Mode bits set to the specified Test Mode. This is done as a tasklet so that the "Status" phase of the control transfer completes before transmitting the TEST packets.<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000033">Todo:</a></b></dt><dd>This has not been tested since the tasklet struct was put into the PCD struct!</dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__intr_8c-source.html#l01284">1284</a> of file <a class="el" href="dwc__otg__pcd__intr_8c-source.html">dwc_otg_pcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="f449add2b4e8de7ced10fd1bb4c5b748"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::do_get_status" ref="f449add2b4e8de7ced10fd1bb4c5b748" args="(dwc_otg_pcd_t *pcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static void do_get_status           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [inline, static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function process the GET_STATUS Setup Commands. 
+<p>
+
+<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000034">Todo:</a></b></dt><dd>check for EP stall </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__intr_8c-source.html#l01321">1321</a> of file <a class="el" href="dwc__otg__pcd__intr_8c-source.html">dwc_otg_pcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="3754b29956ab3a85851dea376e046db9"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::do_set_feature" ref="3754b29956ab3a85851dea376e046db9" args="(dwc_otg_pcd_t *pcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static void do_set_feature           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [inline, static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function process the SET_FEATURE Setup Commands. 
+<p>
+
+<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000035">Todo:</a></b></dt><dd>This has not been tested since the tasklet struct was put into the PCD struct! </dd></dl>
+<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000035">Todo:</a></b></dt><dd>Is the gotgctl.devhnpen cleared by a USB Reset? </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__intr_8c-source.html#l01369">1369</a> of file <a class="el" href="dwc__otg__pcd__intr_8c-source.html">dwc_otg_pcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="2198ea3f0136465fa325a189d4ba5140"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::do_clear_feature" ref="2198ea3f0136465fa325a189d4ba5140" args="(dwc_otg_pcd_t *pcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static void do_clear_feature           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [inline, static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function process the CLEAR_FEATURE Setup Commands. 
+<p>
+
+<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000037">Todo:</a></b></dt><dd>Add CLEAR_FEATURE for TEST modes. </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__intr_8c-source.html#l01472">1472</a> of file <a class="el" href="dwc__otg__pcd__intr_8c-source.html">dwc_otg_pcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="856a520a378e4f6f274253227080cfa1"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::pcd_setup" ref="856a520a378e4f6f274253227080cfa1" args="(dwc_otg_pcd_t *pcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static void pcd_setup           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [inline, static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function processes SETUP commands. 
+<p>
+In Linux, the USB Command processing is done in two places - the first being the PCD and the second in the Gadget Driver (for example, the File-Backed Storage Gadget Driver).<p>
+<table border="1" cellspacing="3" cellpadding="3">
+<tr>
+<td>Command </td><td>Driver </td><td>Description<p>
+</td></tr>
+<tr>
+<td>GET_STATUS </td><td>PCD </td><td>Command is processed as defined in chapter 9 of the USB 2.0 Specification chapter 9 <p>
+</td></tr>
+<tr>
+<td>CLEAR_FEATURE </td><td>PCD </td><td>The Device and Endpoint requests are the ENDPOINT_HALT feature is procesed, all others the interface requests are ignored.<p>
+</td></tr>
+<tr>
+<td>SET_FEATURE </td><td>PCD </td><td>The Device and Endpoint requests are processed by the PCD. Interface requests are passed to the Gadget Driver.<p>
+</td></tr>
+<tr>
+<td>SET_ADDRESS </td><td>PCD </td><td>Program the DCFG reg, with device address received <p>
+</td></tr>
+<tr>
+<td>GET_DESCRIPTOR </td><td>Gadget Driver </td><td>Return the requested descriptor<p>
+</td></tr>
+<tr>
+<td>SET_DESCRIPTOR </td><td>Gadget Driver </td><td>Optional - not implemented by any of the existing Gadget Drivers.<p>
+</td></tr>
+<tr>
+<td>SET_CONFIGURATION </td><td>Gadget Driver </td><td>Disable all EPs and enable EPs for new configuration.<p>
+</td></tr>
+<tr>
+<td>GET_CONFIGURATION </td><td>Gadget Driver </td><td>Return the current configuration<p>
+</td></tr>
+<tr>
+<td>SET_INTERFACE </td><td>Gadget Driver </td><td>Disable all EPs and enable EPs for new configuration.<p>
+</td></tr>
+<tr>
+<td>GET_INTERFACE </td><td>Gadget Driver </td><td>Return the current interface.<p>
+</td></tr>
+<tr>
+<td>SYNC_FRAME </td><td>PCD </td><td>Display debug message. </td></tr>
+</table>
+<p>
+When the SETUP Phase Done interrupt occurs, the PCD SETUP commands are processed by pcd_setup. Calling the Function Driver's setup function from pcd_setup processes the gadget SETUP commands. 
+<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000038">Todo:</a></b></dt><dd>handle &gt; 1 setup packet , assert error for now </dd></dl>
+<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000038">Todo:</a></b></dt><dd>NGS: Handle bad setup packet? </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__intr_8c-source.html#l01580">1580</a> of file <a class="el" href="dwc__otg__pcd__intr_8c-source.html">dwc_otg_pcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="c77f277130ba55b19100bde598da7d85"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::complete_ep" ref="c77f277130ba55b19100bde598da7d85" args="(dwc_otg_pcd_ep_t *ep)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static void complete_ep           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>ep</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function completes the request for the EP. 
+<p>
+If there are additional requests for the EP in the queue they will be started. 
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__intr_8c-source.html#l01911">1911</a> of file <a class="el" href="dwc__otg__pcd__intr_8c-source.html">dwc_otg_pcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="17428b2360118cc59ab9d5cbcef8a14b"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::set_current_pkt_info" ref="17428b2360118cc59ab9d5cbcef8a14b" args="(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void set_current_pkt_info           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__ep.html">dwc_ep_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>ep</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function sets latest iso packet information(non-PTI mode). 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep</em>&nbsp;</td><td>The EP to start the transfer on. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__intr_8c-source.html#l02274">2274</a> of file <a class="el" href="dwc__otg__pcd__intr_8c-source.html">dwc_otg_pcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="e5ed26b3ab2380cb92773df1720ec752"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::set_ddma_iso_pkts_info" ref="e5ed26b3ab2380cb92773df1720ec752" args="(dwc_otg_core_if_t *core_if, dwc_ep_t *dwc_ep)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static void set_ddma_iso_pkts_info           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__ep.html">dwc_ep_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>dwc_ep</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function sets latest iso packet information(DDMA mode). 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em><a class="el" href="structdwc__ep.html">dwc_ep</a></em>&nbsp;</td><td>The EP to start the transfer on. </td></tr>
+  </table>
+</dl>
+
+<p>
+Reinit closed DMA Descriptors<p>
+ISO OUT EP<p>
+ISO IN EP 
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__intr_8c-source.html#l02322">2322</a> of file <a class="el" href="dwc__otg__pcd__intr_8c-source.html">dwc_otg_pcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="c3f6fb3131e0786ec75a9c4a29fea297"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::reinit_ddma_iso_xfer" ref="c3f6fb3131e0786ec75a9c4a29fea297" args="(dwc_otg_core_if_t *core_if, dwc_ep_t *dwc_ep)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static void reinit_ddma_iso_xfer           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__ep.html">dwc_ep_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>dwc_ep</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function reinitialize DMA Descriptors for Isochronous transfer. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em><a class="el" href="structdwc__ep.html">dwc_ep</a></em>&nbsp;</td><td>The EP to start the transfer on. </td></tr>
+  </table>
+</dl>
+
+<p>
+Buffer 0 descriptors setup<p>
+Buffer 1 descriptors setup<p>
+Reinit closed DMA Descriptors<p>
+ISO OUT EP<p>
+ISO IN EP 
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__intr_8c-source.html#l02486">2486</a> of file <a class="el" href="dwc__otg__pcd__intr_8c-source.html">dwc_otg_pcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="41cfc0d590740640795b350998bcc2c4"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::handle_iso_out_pkt_dropped" ref="41cfc0d590740640795b350998bcc2c4" args="(dwc_otg_core_if_t *core_if, dwc_ep_t *dwc_ep)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static uint32_t handle_iso_out_pkt_dropped           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__ep.html">dwc_ep_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>dwc_ep</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function is to handle Iso EP transfer complete interrupt in case Iso out packet was dropped. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em><a class="el" href="structdwc__ep.html">dwc_ep</a></em>&nbsp;</td><td>The EP for wihich transfer complete was asserted </td></tr>
+  </table>
+</dl>
+
+<p>
+Re-enable endpoint, clear nak 
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__intr_8c-source.html#l02620">2620</a> of file <a class="el" href="dwc__otg__pcd__intr_8c-source.html">dwc_otg_pcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="a356ecc4053e9700785a27dbfdd6b2db"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::set_iso_pkts_info" ref="a356ecc4053e9700785a27dbfdd6b2db" args="(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static uint32_t set_iso_pkts_info           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>core_if</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__ep.html">dwc_ep_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>ep</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function sets iso packets information(PTI mode). 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>core_if</em>&nbsp;</td><td>Programming view of DWC_otg controller. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep</em>&nbsp;</td><td>The EP to start the transfer on. </td></tr>
+  </table>
+</dl>
+
+<p>
+Buffer 0 descriptors setup<p>
+Buffer 1 descriptors setup 
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__intr_8c-source.html#l02690">2690</a> of file <a class="el" href="dwc__otg__pcd__intr_8c-source.html">dwc_otg_pcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="05965765a43225780ae08f2c3928f782"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::complete_iso_ep" ref="05965765a43225780ae08f2c3928f782" args="(dwc_otg_pcd_t *pcd, dwc_otg_pcd_ep_t *ep)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static void complete_iso_ep           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>ep</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function is to handle Iso EP transfer complete interrupt. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>pcd</em>&nbsp;</td><td>The PCD </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ep</em>&nbsp;</td><td>The EP for which transfer complete was asserted </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__intr_8c-source.html#l02766">2766</a> of file <a class="el" href="dwc__otg__pcd__intr_8c-source.html">dwc_otg_pcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="4991119b51de03163a3677c36bc0ee3b"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::handle_ep0" ref="4991119b51de03163a3677c36bc0ee3b" args="(dwc_otg_pcd_t *pcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static void handle_ep0           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function handles EP0 Control transfers. 
+<p>
+The state of the control tranfers are tracked in <code>ep0state</code>. 
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__intr_8c-source.html#l02843">2843</a> of file <a class="el" href="dwc__otg__pcd__intr_8c-source.html">dwc_otg_pcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="65d4f747d13e368916ee0e16d202119b"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::handle_in_ep_timeout_intr" ref="65d4f747d13e368916ee0e16d202119b" args="(dwc_otg_pcd_t *pcd, const uint32_t epnum)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static void handle_in_ep_timeout_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">const uint32_t&nbsp;</td>
+          <td class="paramname"> <em>epnum</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [inline, static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Handler for the IN EP timeout handshake interrupt. 
+<p>
+
+<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000040">Todo:</a></b></dt><dd>NGS Check EP type. Implement for Periodic EPs </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__intr_8c-source.html#l03080">3080</a> of file <a class="el" href="dwc__otg__pcd__intr_8c-source.html">dwc_otg_pcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="273ccc8e8cdb9e2075844f2f922b53bf"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::handle_in_ep_nak_intr" ref="273ccc8e8cdb9e2075844f2f922b53bf" args="(dwc_otg_pcd_t *pcd, const uint32_t epnum)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static int32_t handle_in_ep_nak_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">const uint32_t&nbsp;</td>
+          <td class="paramname"> <em>epnum</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [inline, static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Handler for the IN EP NAK interrupt. 
+<p>
+
+<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000041">Todo:</a></b></dt><dd>implement ISR </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__intr_8c-source.html#l03141">3141</a> of file <a class="el" href="dwc__otg__pcd__intr_8c-source.html">dwc_otg_pcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="42aef7ea134cccf7cdb53e7e1428bc4a"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::handle_out_ep_babble_intr" ref="42aef7ea134cccf7cdb53e7e1428bc4a" args="(dwc_otg_pcd_t *pcd, const uint32_t epnum)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static int32_t handle_out_ep_babble_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">const uint32_t&nbsp;</td>
+          <td class="paramname"> <em>epnum</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [inline, static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Handler for the OUT EP Babble interrupt. 
+<p>
+
+<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000042">Todo:</a></b></dt><dd>implement ISR </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__intr_8c-source.html#l03166">3166</a> of file <a class="el" href="dwc__otg__pcd__intr_8c-source.html">dwc_otg_pcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="252929e585c84eaf0485869cd7734244"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::handle_out_ep_nak_intr" ref="252929e585c84eaf0485869cd7734244" args="(dwc_otg_pcd_t *pcd, const uint32_t epnum)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static int32_t handle_out_ep_nak_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">const uint32_t&nbsp;</td>
+          <td class="paramname"> <em>epnum</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [inline, static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Handler for the OUT EP NAK interrupt. 
+<p>
+
+<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000043">Todo:</a></b></dt><dd>implement ISR </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__intr_8c-source.html#l03192">3192</a> of file <a class="el" href="dwc__otg__pcd__intr_8c-source.html">dwc_otg_pcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="926d9068c1950cc406d50828e72a31db"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::handle_out_ep_nyet_intr" ref="926d9068c1950cc406d50828e72a31db" args="(dwc_otg_pcd_t *pcd, const uint32_t epnum)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static int32_t handle_out_ep_nyet_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">const uint32_t&nbsp;</td>
+          <td class="paramname"> <em>epnum</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [inline, static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Handler for the OUT EP NYET interrupt. 
+<p>
+
+<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000044">Todo:</a></b></dt><dd>implement ISR </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__intr_8c-source.html#l03217">3217</a> of file <a class="el" href="dwc__otg__pcd__intr_8c-source.html">dwc_otg_pcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="321d4a511db985443b132c044fc2d69e"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::dwc_otg_pcd_handle_in_ep_intr" ref="321d4a511db985443b132c044fc2d69e" args="(dwc_otg_pcd_t *pcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static int32_t dwc_otg_pcd_handle_in_ep_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This interrupt indicates that an IN EP has a pending Interrupt. 
+<p>
+The sequence for handling the IN EP interrupt is shown below:<ol type=1>
+<li>Read the Device All Endpoint Interrupt register</li><li>Repeat the following for each IN EP interrupt bit set (from LSB to MSB).</li><li>Read the Device Endpoint Interrupt (DIEPINTn) register</li><li>If "Transfer Complete" call the request complete function</li><li>If "Endpoint Disabled" complete the EP disable procedure.</li><li>If "AHB Error Interrupt" log error</li><li>If "Time-out Handshake" log error</li><li>If "IN Token Received when TxFIFO Empty" write packet to Tx FIFO.</li><li>If "IN Token EP Mismatch" (disable, this is handled by EP Mismatch Interrupt) </li></ol>
+
+<p>
+IN Token received with TxF Empty<p>
+IN Token Received with EP mismatch<p>
+IN Endpoint NAK Effective<p>
+IN EP Tx FIFO Empty Intr<p>
+IN EP BNA Intr 
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__intr_8c-source.html#l03255">3255</a> of file <a class="el" href="dwc__otg__pcd__intr_8c-source.html">dwc_otg_pcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="8b24f400f2eb83ea262e27f5cd1bb707"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::dwc_otg_pcd_handle_out_ep_intr" ref="8b24f400f2eb83ea262e27f5cd1bb707" args="(dwc_otg_pcd_t *pcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static int32_t dwc_otg_pcd_handle_out_ep_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This interrupt indicates that an OUT EP has a pending Interrupt. 
+<p>
+The sequence for handling the OUT EP interrupt is shown below:<ol type=1>
+<li>Read the Device All Endpoint Interrupt register</li><li>Repeat the following for each OUT EP interrupt bit set (from LSB to MSB).</li><li>Read the Device Endpoint Interrupt (DOEPINTn) register</li><li>If "Transfer Complete" call the request complete function</li><li>If "Endpoint Disabled" complete the EP disable procedure.</li><li>If "AHB Error Interrupt" log error</li><li>If "Setup Phase Done" process Setup Packet (See Standard USB Command Processing) </li></ol>
+
+<p>
+OUT EP BNA Intr 
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__intr_8c-source.html#l03522">3522</a> of file <a class="el" href="dwc__otg__pcd__intr_8c-source.html">dwc_otg_pcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="aa9fd9a6774ed616e31df65fe326351b"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::dwc_otg_pcd_handle_incomplete_isoc_in_intr" ref="aa9fd9a6774ed616e31df65fe326351b" args="(dwc_otg_pcd_t *pcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t dwc_otg_pcd_handle_incomplete_isoc_in_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Incomplete ISO IN Transfer Interrupt. 
+<p>
+This interrupt indicates one of the following conditions occurred while transmitting an ISOC transaction.<ul>
+<li>Corrupted IN Token for ISOC EP.</li><li>Packet not complete in FIFO. The follow actions will be taken:<ol type=a>
+<li>Determine the EP</li><li>Set incomplete flag in <a class="el" href="structdwc__ep.html">dwc_ep</a> structure</li><li>Disable EP; when "Endpoint Disabled" interrupt is received Flush FIFO </li></ol>
+</li></ul>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__intr_8c-source.html#l03725">3725</a> of file <a class="el" href="dwc__otg__pcd__intr_8c-source.html">dwc_otg_pcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="8277c5761c3865fbb3646ba496a4901e"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::dwc_otg_pcd_handle_incomplete_isoc_out_intr" ref="8277c5761c3865fbb3646ba496a4901e" args="(dwc_otg_pcd_t *pcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t dwc_otg_pcd_handle_incomplete_isoc_out_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Incomplete ISO OUT Transfer Interrupt. 
+<p>
+This interrupt indicates that the core has dropped an ISO OUT packet. The following conditions can be the cause:<ul>
+<li>FIFO Full, the entire packet would not fit in the FIFO.</li><li>CRC Error</li><li>Corrupted Token The follow actions will be taken:<ol type=a>
+<li>Determine the EP</li><li>Set incomplete flag in <a class="el" href="structdwc__ep.html">dwc_ep</a> structure</li><li>Read any data from the FIFO</li><li>Disable EP. when "Endpoint Disabled" interrupt is received re-enable EP. </li></ol>
+</li></ul>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__intr_8c-source.html#l03814">3814</a> of file <a class="el" href="dwc__otg__pcd__intr_8c-source.html">dwc_otg_pcd_intr.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="fc60361217d0c5c089f4036d73690689"></a><!-- doxytag: member="dwc_otg_pcd_intr.c::dwc_otg_pcd_handle_intr" ref="fc60361217d0c5c089f4036d73690689" args="(dwc_otg_pcd_t *pcd)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t dwc_otg_pcd_handle_intr           </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td>
+          <td class="paramname"> <em>pcd</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function should be called on every hardware interrupt. 
+<p>
+The PCD handles the device interrupts. Many conditions can cause a device interrupt. When an interrupt occurs, the device interrupt service routine determines the cause of the interrupt and dispatches handling to the appropriate function. These interrupt handling functions are described below.<p>
+All interrupt registers are processed from LSB to MSB. 
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__intr_8c-source.html#l03971">3971</a> of file <a class="el" href="dwc__otg__pcd__intr_8c-source.html">dwc_otg_pcd_intr.c</a>.
+</div>
+</div><p>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__linux_8c-source.html b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__linux_8c-source.html
new file mode 100644
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--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__linux_8c-source.html
@@ -0,0 +1,997 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd_linux.c Source File</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
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+<h1>dwc_otg_pcd_linux.c</h1><a href="dwc__otg__pcd__linux_8c.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001  <span class="comment">/* ==========================================================================</span>
+<a name="l00002"></a>00002 <span class="comment">  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_linux.c $</span>
+<a name="l00003"></a>00003 <span class="comment">  * $Revision: #7 $</span>
+<a name="l00004"></a>00004 <span class="comment">  * $Date: 2009/04/03 $</span>
+<a name="l00005"></a>00005 <span class="comment">  * $Change: 1225160 $</span>
+<a name="l00006"></a>00006 <span class="comment">  *</span>
+<a name="l00007"></a>00007 <span class="comment">  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,</span>
+<a name="l00008"></a>00008 <span class="comment">  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless</span>
+<a name="l00009"></a>00009 <span class="comment">  * otherwise expressly agreed to in writing between Synopsys and you.</span>
+<a name="l00010"></a>00010 <span class="comment">  *</span>
+<a name="l00011"></a>00011 <span class="comment">  * The Software IS NOT an item of Licensed Software or Licensed Product under</span>
+<a name="l00012"></a>00012 <span class="comment">  * any End User Software License Agreement or Agreement for Licensed Product</span>
+<a name="l00013"></a>00013 <span class="comment">  * with Synopsys or any supplement thereto. You are permitted to use and</span>
+<a name="l00014"></a>00014 <span class="comment">  * redistribute this Software in source and binary forms, with or without</span>
+<a name="l00015"></a>00015 <span class="comment">  * modification, provided that redistributions of source code must retain this</span>
+<a name="l00016"></a>00016 <span class="comment">  * notice. You may not view, use, disclose, copy or distribute this file or</span>
+<a name="l00017"></a>00017 <span class="comment">  * any information contained herein except pursuant to this license grant from</span>
+<a name="l00018"></a>00018 <span class="comment">  * Synopsys. If you do not agree with this notice, including the disclaimer</span>
+<a name="l00019"></a>00019 <span class="comment">  * below, then you are not authorized to use the Software.</span>
+<a name="l00020"></a>00020 <span class="comment">  *</span>
+<a name="l00021"></a>00021 <span class="comment">  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS</span>
+<a name="l00022"></a>00022 <span class="comment">  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE</span>
+<a name="l00023"></a>00023 <span class="comment">  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE</span>
+<a name="l00024"></a>00024 <span class="comment">  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,</span>
+<a name="l00025"></a>00025 <span class="comment">  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES</span>
+<a name="l00026"></a>00026 <span class="comment">  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR</span>
+<a name="l00027"></a>00027 <span class="comment">  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER</span>
+<a name="l00028"></a>00028 <span class="comment">  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT</span>
+<a name="l00029"></a>00029 <span class="comment">  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY</span>
+<a name="l00030"></a>00030 <span class="comment">  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH</span>
+<a name="l00031"></a>00031 <span class="comment">  * DAMAGE.</span>
+<a name="l00032"></a>00032 <span class="comment">  * ========================================================================== */</span>
+<a name="l00033"></a>00033 <span class="preprocessor">#ifndef DWC_HOST_ONLY</span>
+<a name="l00034"></a>00034 <span class="preprocessor"></span>
+<a name="l00056"></a>00056 <span class="preprocessor">#include &lt;linux/kernel.h&gt;</span>
+<a name="l00057"></a>00057 <span class="preprocessor">#include &lt;linux/module.h&gt;</span>
+<a name="l00058"></a>00058 <span class="preprocessor">#include &lt;linux/moduleparam.h&gt;</span>
+<a name="l00059"></a>00059 <span class="preprocessor">#include &lt;linux/init.h&gt;</span>
+<a name="l00060"></a>00060 <span class="preprocessor">#include &lt;linux/device.h&gt;</span>
+<a name="l00061"></a>00061 <span class="preprocessor">#include &lt;linux/errno.h&gt;</span>
+<a name="l00062"></a>00062 <span class="preprocessor">#include &lt;linux/list.h&gt;</span>
+<a name="l00063"></a>00063 <span class="preprocessor">#include &lt;linux/interrupt.h&gt;</span>
+<a name="l00064"></a>00064 <span class="preprocessor">#include &lt;linux/string.h&gt;</span>
+<a name="l00065"></a>00065 <span class="preprocessor">#include &lt;linux/dma-mapping.h&gt;</span>
+<a name="l00066"></a>00066 <span class="preprocessor">#include &lt;linux/version.h&gt;</span>
+<a name="l00067"></a>00067 
+<a name="l00068"></a>00068 <span class="preprocessor">#ifdef LM_INTERFACE</span>
+<a name="l00069"></a>00069 <span class="preprocessor"></span><span class="preprocessor"># include &lt;asm/arch/regs-irq.h&gt;</span>
+<a name="l00070"></a>00070 <span class="preprocessor"># include &lt;asm/arch/lm.h&gt;</span>
+<a name="l00071"></a>00071 <span class="preprocessor"># include &lt;asm/arch/irqs.h&gt;</span>
+<a name="l00072"></a>00072 <span class="preprocessor">#endif</span>
+<a name="l00073"></a>00073 <span class="preprocessor"></span>
+<a name="l00074"></a>00074 <span class="preprocessor">#include &lt;asm/io.h&gt;</span>
+<a name="l00075"></a>00075 <span class="preprocessor"># include &lt;linux/usb_ch9.h&gt;</span>
+<a name="l00076"></a>00076 <span class="preprocessor">#include &lt;linux/usb_gadget.h&gt;</span>
+<a name="l00077"></a>00077 
+<a name="l00078"></a>00078 <span class="preprocessor">#include "<a class="code" href="dwc__otg__pcd__if_8h.html">dwc_otg_pcd_if.h</a>"</span>
+<a name="l00079"></a>00079 <span class="preprocessor">#include "<a class="code" href="dwc__otg__driver_8h.html">dwc_otg_driver.h</a>"</span>
+<a name="l00080"></a>00080 <span class="preprocessor">#include "<a class="code" href="dwc__otg__dbg_8h.html">dwc_otg_dbg.h</a>"</span>
+<a name="l00081"></a>00081 
+<a name="l00082"></a><a class="code" href="structgadget__wrapper.html">00082</a> <span class="keyword">static</span> <span class="keyword">struct </span><a class="code" href="structgadget__wrapper.html">gadget_wrapper</a> {
+<a name="l00083"></a><a class="code" href="structgadget__wrapper.html#cdc4a50b5415cc484f77c61a63db3e94">00083</a>         <a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *<a class="code" href="structgadget__wrapper.html#cdc4a50b5415cc484f77c61a63db3e94">pcd</a>;
+<a name="l00084"></a>00084 
+<a name="l00085"></a><a class="code" href="structgadget__wrapper.html#a1f30b68c6b42bc728c45c329312d7b1">00085</a>         <span class="keyword">struct </span>usb_gadget gadget;
+<a name="l00086"></a><a class="code" href="structgadget__wrapper.html#8997a3c90f9eb0a8f40f5762ffc5ce60">00086</a>         <span class="keyword">struct </span>usb_gadget_driver *<a class="code" href="structgadget__wrapper.html#8997a3c90f9eb0a8f40f5762ffc5ce60">driver</a>;
+<a name="l00087"></a>00087 
+<a name="l00088"></a><a class="code" href="structgadget__wrapper.html#8f28c6610592157ecef50de726919162">00088</a>         <span class="keyword">struct </span>usb_ep ep0;
+<a name="l00089"></a><a class="code" href="structgadget__wrapper.html#9b57a0085afa3decabffc89943866931">00089</a>         <span class="keyword">struct </span>usb_ep in_ep[16];
+<a name="l00090"></a><a class="code" href="structgadget__wrapper.html#c420e5ba1a1c2d83d62471c423180d3c">00090</a>         <span class="keyword">struct </span>usb_ep out_ep[16];
+<a name="l00091"></a>00091 
+<a name="l00092"></a>00092 } *<a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>;
+<a name="l00093"></a>00093 
+<a name="l00094"></a>00094 <span class="comment">/* Display the contents of the buffer */</span>
+<a name="l00095"></a>00095 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__cfi_8h.html#8d8df6d136115ec977eb6bf20148547a">dump_msg</a>(<span class="keyword">const</span> u8 * buf, <span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> length);
+<a name="l00096"></a>00096 
+<a name="l00097"></a>00097 <span class="comment">/* USB Endpoint Operations */</span>
+<a name="l00098"></a>00098 <span class="comment">/*</span>
+<a name="l00099"></a>00099 <span class="comment"> * The following sections briefly describe the behavior of the Gadget</span>
+<a name="l00100"></a>00100 <span class="comment"> * API endpoint operations implemented in the DWC_otg driver</span>
+<a name="l00101"></a>00101 <span class="comment"> * software. Detailed descriptions of the generic behavior of each of</span>
+<a name="l00102"></a>00102 <span class="comment"> * these functions can be found in the Linux header file</span>
+<a name="l00103"></a>00103 <span class="comment"> * include/linux/usb_gadget.h.</span>
+<a name="l00104"></a>00104 <span class="comment"> *</span>
+<a name="l00105"></a>00105 <span class="comment"> * The Gadget API provides wrapper functions for each of the function</span>
+<a name="l00106"></a>00106 <span class="comment"> * pointers defined in usb_ep_ops. The Gadget Driver calls the wrapper</span>
+<a name="l00107"></a>00107 <span class="comment"> * function, which then calls the underlying PCD function. The</span>
+<a name="l00108"></a>00108 <span class="comment"> * following sections are named according to the wrapper</span>
+<a name="l00109"></a>00109 <span class="comment"> * functions. Within each section, the corresponding DWC_otg PCD</span>
+<a name="l00110"></a>00110 <span class="comment"> * function name is specified.</span>
+<a name="l00111"></a>00111 <span class="comment"> *</span>
+<a name="l00112"></a>00112 <span class="comment"> */</span>
+<a name="l00113"></a>00113 
+<a name="l00121"></a><a class="code" href="dwc__otg__pcd__linux_8c.html#9761890d7f741f9421d82254c9846f31">00121</a> <span class="keyword">static</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__pcd__linux_8c.html#9761890d7f741f9421d82254c9846f31">ep_enable</a>(<span class="keyword">struct</span> usb_ep *usb_ep,
+<a name="l00122"></a>00122                      <span class="keyword">const</span> <span class="keyword">struct</span> usb_endpoint_descriptor *ep_desc)
+<a name="l00123"></a>00123 {
+<a name="l00124"></a>00124         <span class="keywordtype">int</span> retval;
+<a name="l00125"></a>00125 
+<a name="l00126"></a>00126         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"%s(%p,%p)\n"</span>, __func__, usb_ep, ep_desc);
+<a name="l00127"></a>00127 
+<a name="l00128"></a>00128         <span class="keywordflow">if</span> (!usb_ep || !ep_desc || ep_desc-&gt;bDescriptorType != USB_DT_ENDPOINT) {
+<a name="l00129"></a>00129                 DWC_WARN(<span class="stringliteral">"%s, bad ep or descriptor\n"</span>, __func__);
+<a name="l00130"></a>00130                 <span class="keywordflow">return</span> -EINVAL;
+<a name="l00131"></a>00131         }
+<a name="l00132"></a>00132         <span class="keywordflow">if</span> (usb_ep == &amp;<a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;ep0) {
+<a name="l00133"></a>00133                 DWC_WARN(<span class="stringliteral">"%s, bad ep(0)\n"</span>, __func__);
+<a name="l00134"></a>00134                 <span class="keywordflow">return</span> -EINVAL;
+<a name="l00135"></a>00135         }
+<a name="l00136"></a>00136 
+<a name="l00137"></a>00137         <span class="comment">/* Check FIFO size? */</span>
+<a name="l00138"></a>00138         <span class="keywordflow">if</span> (!ep_desc-&gt;wMaxPacketSize) {
+<a name="l00139"></a>00139                 DWC_WARN(<span class="stringliteral">"%s, bad %s maxpacket\n"</span>, __func__, usb_ep-&gt;name);
+<a name="l00140"></a>00140                 <span class="keywordflow">return</span> -ERANGE;
+<a name="l00141"></a>00141         }
+<a name="l00142"></a>00142 
+<a name="l00143"></a>00143         <span class="keywordflow">if</span> (!<a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;driver ||
+<a name="l00144"></a>00144             <a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;gadget.speed == USB_SPEED_UNKNOWN) {
+<a name="l00145"></a>00145                 DWC_WARN(<span class="stringliteral">"%s, bogus device state\n"</span>, __func__);
+<a name="l00146"></a>00146                 <span class="keywordflow">return</span> -ESHUTDOWN;
+<a name="l00147"></a>00147         }
+<a name="l00148"></a>00148 
+<a name="l00149"></a>00149         retval = <a class="code" href="dwc__otg__pcd_8c.html#b9168f11717bdc672d9a29226779e523">dwc_otg_pcd_ep_enable</a>(<a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;pcd,
+<a name="l00150"></a>00150                                        (<span class="keyword">const</span> uint8_t *)ep_desc,
+<a name="l00151"></a>00151                                        (<span class="keywordtype">void</span> *)usb_ep);
+<a name="l00152"></a>00152         <span class="keywordflow">if</span> (retval) {
+<a name="l00153"></a>00153                 DWC_WARN(<span class="stringliteral">"dwc_otg_pcd_ep_enable failed\n"</span>);
+<a name="l00154"></a>00154                 <span class="keywordflow">return</span> -EINVAL;
+<a name="l00155"></a>00155         }
+<a name="l00156"></a>00156 
+<a name="l00157"></a>00157         usb_ep-&gt;maxpacket = le16_to_cpu(ep_desc-&gt;wMaxPacketSize);
+<a name="l00158"></a>00158 
+<a name="l00159"></a>00159         <span class="keywordflow">return</span> 0;
+<a name="l00160"></a>00160 }
+<a name="l00161"></a>00161 
+<a name="l00170"></a><a class="code" href="dwc__otg__pcd__linux_8c.html#1708514cb93c5da43a8f634de1c0f5e7">00170</a> <span class="keyword">static</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__pcd__linux_8c.html#1708514cb93c5da43a8f634de1c0f5e7">ep_disable</a>(<span class="keyword">struct</span> usb_ep *usb_ep)
+<a name="l00171"></a>00171 {
+<a name="l00172"></a>00172         <span class="keywordtype">int</span> retval;
+<a name="l00173"></a>00173 
+<a name="l00174"></a>00174         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"%s(%p)\n"</span>, __func__, usb_ep);
+<a name="l00175"></a>00175         <span class="keywordflow">if</span> (!usb_ep) {
+<a name="l00176"></a>00176                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"%s, %s not enabled\n"</span>, __func__,
+<a name="l00177"></a>00177                             usb_ep ? usb_ep-&gt;name : NULL);
+<a name="l00178"></a>00178                 <span class="keywordflow">return</span> -EINVAL;
+<a name="l00179"></a>00179         }
+<a name="l00180"></a>00180 
+<a name="l00181"></a>00181         retval = <a class="code" href="dwc__otg__pcd_8c.html#8a2f791c79320c8c4657715a672822a4">dwc_otg_pcd_ep_disable</a>(<a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;pcd, usb_ep);
+<a name="l00182"></a>00182         <span class="keywordflow">if</span> (retval) {
+<a name="l00183"></a>00183                 retval = -EINVAL;
+<a name="l00184"></a>00184         }
+<a name="l00185"></a>00185 
+<a name="l00186"></a>00186         <span class="keywordflow">return</span> retval;
+<a name="l00187"></a>00187 }
+<a name="l00188"></a>00188 
+<a name="l00196"></a><a class="code" href="dwc__otg__pcd__linux_8c.html#e5a3f75b9a06a4707d1d0ec5957daa7d">00196</a> <span class="keyword">static</span> <span class="keyword">struct </span>usb_request *<a class="code" href="dwc__otg__pcd__linux_8c.html#e5a3f75b9a06a4707d1d0ec5957daa7d">dwc_otg_pcd_alloc_request</a>(<span class="keyword">struct</span> usb_ep *ep,
+<a name="l00197"></a>00197                                                      gfp_t gfp_flags)
+<a name="l00198"></a>00198 {
+<a name="l00199"></a>00199         <span class="keyword">struct </span>usb_request *usb_req;
+<a name="l00200"></a>00200 
+<a name="l00201"></a>00201         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"%s(%p,%d)\n"</span>, __func__, ep, gfp_flags);
+<a name="l00202"></a>00202         <span class="keywordflow">if</span> (0 == ep) {
+<a name="l00203"></a>00203                 DWC_WARN(<span class="stringliteral">"%s() %s\n"</span>, __func__, <span class="stringliteral">"Invalid EP!\n"</span>);
+<a name="l00204"></a>00204                 <span class="keywordflow">return</span> 0;
+<a name="l00205"></a>00205         }
+<a name="l00206"></a>00206         usb_req = kmalloc(<span class="keyword">sizeof</span>(*usb_req), gfp_flags);
+<a name="l00207"></a>00207         <span class="keywordflow">if</span> (0 == usb_req) {
+<a name="l00208"></a>00208                 DWC_WARN(<span class="stringliteral">"%s() %s\n"</span>, __func__, <span class="stringliteral">"request allocation failed!\n"</span>);
+<a name="l00209"></a>00209                 <span class="keywordflow">return</span> 0;
+<a name="l00210"></a>00210         }
+<a name="l00211"></a>00211         memset(usb_req, 0, <span class="keyword">sizeof</span>(*usb_req));
+<a name="l00212"></a>00212         usb_req-&gt;dma = DWC_INVALID_DMA_ADDR;
+<a name="l00213"></a>00213 
+<a name="l00214"></a>00214         <span class="keywordflow">return</span> usb_req;
+<a name="l00215"></a>00215 }
+<a name="l00216"></a>00216 
+<a name="l00223"></a><a class="code" href="dwc__otg__pcd__linux_8c.html#348338816bfc0e711c4b875997ed00d9">00223</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd__linux_8c.html#348338816bfc0e711c4b875997ed00d9">dwc_otg_pcd_free_request</a>(<span class="keyword">struct</span> usb_ep *ep, <span class="keyword">struct</span> usb_request *req)
+<a name="l00224"></a>00224 {
+<a name="l00225"></a>00225         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"%s(%p,%p)\n"</span>, __func__, ep, req);
+<a name="l00226"></a>00226 
+<a name="l00227"></a>00227         <span class="keywordflow">if</span> (0 == ep || 0 == req) {
+<a name="l00228"></a>00228                 DWC_WARN(<span class="stringliteral">"%s() %s\n"</span>, __func__,
+<a name="l00229"></a>00229                          <span class="stringliteral">"Invalid ep or req argument!\n"</span>);
+<a name="l00230"></a>00230                 <span class="keywordflow">return</span>;
+<a name="l00231"></a>00231         }
+<a name="l00232"></a>00232 
+<a name="l00233"></a>00233         kfree(req);
+<a name="l00234"></a>00234 }
+<a name="l00235"></a>00235 
+<a name="l00246"></a><a class="code" href="dwc__otg__pcd__linux_8c.html#295957efef868247c889aa3f5050af00">00246</a> <span class="keyword">static</span> <span class="keywordtype">void</span> *<a class="code" href="dwc__otg__pcd__linux_8c.html#295957efef868247c889aa3f5050af00">dwc_otg_pcd_alloc_buffer</a>(<span class="keyword">struct</span> usb_ep *usb_ep, <span class="keywordtype">unsigned</span> bytes,
+<a name="l00247"></a>00247                                       dma_addr_t * dma, gfp_t gfp_flags)
+<a name="l00248"></a>00248 {
+<a name="l00249"></a>00249         <span class="keywordtype">void</span> *buf;
+<a name="l00250"></a>00250         <a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd = 0;
+<a name="l00251"></a>00251 
+<a name="l00252"></a>00252         pcd = <a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;pcd;
+<a name="l00253"></a>00253 
+<a name="l00254"></a>00254         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"%s(%p,%d,%p,%0x)\n"</span>, __func__, usb_ep, bytes,
+<a name="l00255"></a>00255                     dma, gfp_flags);
+<a name="l00256"></a>00256 
+<a name="l00257"></a>00257         <span class="comment">/* Check dword alignment */</span>
+<a name="l00258"></a>00258         <span class="keywordflow">if</span> ((bytes &amp; 0x3UL) != 0) {
+<a name="l00259"></a>00259                 DWC_WARN(<span class="stringliteral">"%s() Buffer size is not a multiple of"</span>
+<a name="l00260"></a>00260                          <span class="stringliteral">"DWORD size (%d)"</span>, __func__, bytes);
+<a name="l00261"></a>00261         }
+<a name="l00262"></a>00262 
+<a name="l00263"></a>00263         buf = dma_alloc_coherent(NULL, bytes, dma, gfp_flags);
+<a name="l00264"></a>00264 
+<a name="l00265"></a>00265         <span class="comment">/* Check dword alignment */</span>
+<a name="l00266"></a>00266         <span class="keywordflow">if</span> (((<span class="keywordtype">int</span>)buf &amp; 0x3UL) != 0) {
+<a name="l00267"></a>00267                 DWC_WARN(<span class="stringliteral">"%s() Buffer is not DWORD aligned (%p)"</span>,
+<a name="l00268"></a>00268                          __func__, buf);
+<a name="l00269"></a>00269         }
+<a name="l00270"></a>00270 
+<a name="l00271"></a>00271         <span class="keywordflow">return</span> buf;
+<a name="l00272"></a>00272 }
+<a name="l00273"></a>00273 
+<a name="l00282"></a><a class="code" href="dwc__otg__pcd__linux_8c.html#675a197388a82da27f74c11ffdbf874b">00282</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd__linux_8c.html#675a197388a82da27f74c11ffdbf874b">dwc_otg_pcd_free_buffer</a>(<span class="keyword">struct</span> usb_ep *usb_ep, <span class="keywordtype">void</span> *buf,
+<a name="l00283"></a>00283                                     dma_addr_t dma, <span class="keywordtype">unsigned</span> bytes)
+<a name="l00284"></a>00284 {
+<a name="l00285"></a>00285         <a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd = 0;
+<a name="l00286"></a>00286 
+<a name="l00287"></a>00287         pcd = <a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;pcd;
+<a name="l00288"></a>00288 
+<a name="l00289"></a>00289         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"%s(%p,%0x,%d)\n"</span>, __func__, buf, dma, bytes);
+<a name="l00290"></a>00290 
+<a name="l00291"></a>00291         dma_free_coherent(NULL, bytes, buf, dma);
+<a name="l00292"></a>00292 }
+<a name="l00293"></a>00293 
+<a name="l00308"></a><a class="code" href="dwc__otg__pcd__linux_8c.html#f97bea831037135af73c3c202e3e01dc">00308</a> <span class="keyword">static</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__pcd__linux_8c.html#f97bea831037135af73c3c202e3e01dc">ep_queue</a>(<span class="keyword">struct</span> usb_ep *usb_ep, <span class="keyword">struct</span> usb_request *usb_req,
+<a name="l00309"></a>00309                     gfp_t gfp_flags)
+<a name="l00310"></a>00310 {
+<a name="l00311"></a>00311         <a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd;
+<a name="l00312"></a>00312         <span class="keywordtype">int</span> retval;
+<a name="l00313"></a>00313 
+<a name="l00314"></a>00314         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"%s(%p,%p,%d)\n"</span>,
+<a name="l00315"></a>00315                     __func__, usb_ep, usb_req, gfp_flags);
+<a name="l00316"></a>00316 
+<a name="l00317"></a>00317         <span class="keywordflow">if</span> (!usb_req || !usb_req-&gt;complete || !usb_req-&gt;buf) {
+<a name="l00318"></a>00318                 DWC_WARN(<span class="stringliteral">"bad params\n"</span>);
+<a name="l00319"></a>00319                 <span class="keywordflow">return</span> -EINVAL;
+<a name="l00320"></a>00320         }
+<a name="l00321"></a>00321 
+<a name="l00322"></a>00322         <span class="keywordflow">if</span> (!usb_ep) {
+<a name="l00323"></a>00323                 DWC_WARN(<span class="stringliteral">"bad ep\n"</span>);
+<a name="l00324"></a>00324                 <span class="keywordflow">return</span> -EINVAL;
+<a name="l00325"></a>00325         }
+<a name="l00326"></a>00326 
+<a name="l00327"></a>00327         pcd = <a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;pcd;
+<a name="l00328"></a>00328         <span class="keywordflow">if</span> (!<a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;driver ||
+<a name="l00329"></a>00329             <a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;gadget.speed == USB_SPEED_UNKNOWN) {
+<a name="l00330"></a>00330                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"gadget.speed=%d\n"</span>,
+<a name="l00331"></a>00331                             <a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;gadget.speed);
+<a name="l00332"></a>00332                 DWC_WARN(<span class="stringliteral">"bogus device state\n"</span>);
+<a name="l00333"></a>00333                 <span class="keywordflow">return</span> -ESHUTDOWN;
+<a name="l00334"></a>00334         }
+<a name="l00335"></a>00335 
+<a name="l00336"></a>00336         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"%s queue req %p, len %d buf %p\n"</span>,
+<a name="l00337"></a>00337                     usb_ep-&gt;name, usb_req, usb_req-&gt;length, usb_req-&gt;buf);
+<a name="l00338"></a>00338 
+<a name="l00339"></a>00339         usb_req-&gt;status = -EINPROGRESS;
+<a name="l00340"></a>00340         usb_req-&gt;actual = 0;
+<a name="l00341"></a>00341 
+<a name="l00342"></a>00342         retval = <a class="code" href="dwc__otg__pcd_8c.html#09f3d77397aa7d22a1ca32e26c8aedea">dwc_otg_pcd_ep_queue</a>(pcd, usb_ep, usb_req-&gt;buf, usb_req-&gt;dma,
+<a name="l00343"></a>00343                                       usb_req-&gt;length, usb_req-&gt;zero, usb_req,
+<a name="l00344"></a>00344                                       gfp_flags == GFP_ATOMIC ? 1 : 0);
+<a name="l00345"></a>00345         <span class="keywordflow">if</span> (retval) {
+<a name="l00346"></a>00346                 <span class="keywordflow">return</span> -EINVAL;
+<a name="l00347"></a>00347         }
+<a name="l00348"></a>00348 
+<a name="l00349"></a>00349         <span class="keywordflow">return</span> 0;
+<a name="l00350"></a>00350 }
+<a name="l00351"></a>00351 
+<a name="l00355"></a><a class="code" href="dwc__otg__pcd__linux_8c.html#e2e4913a926acc55f4e57c3ff8f97c08">00355</a> <span class="keyword">static</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__pcd__linux_8c.html#e2e4913a926acc55f4e57c3ff8f97c08">ep_dequeue</a>(<span class="keyword">struct</span> usb_ep *usb_ep, <span class="keyword">struct</span> usb_request *usb_req)
+<a name="l00356"></a>00356 {
+<a name="l00357"></a>00357         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"%s(%p,%p)\n"</span>, __func__, usb_ep, usb_req);
+<a name="l00358"></a>00358 
+<a name="l00359"></a>00359         <span class="keywordflow">if</span> (!usb_ep || !usb_req) {
+<a name="l00360"></a>00360                 DWC_WARN(<span class="stringliteral">"bad argument\n"</span>);
+<a name="l00361"></a>00361                 <span class="keywordflow">return</span> -EINVAL;
+<a name="l00362"></a>00362         }
+<a name="l00363"></a>00363         <span class="keywordflow">if</span> (!<a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;driver ||
+<a name="l00364"></a>00364             <a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;gadget.speed == USB_SPEED_UNKNOWN) {
+<a name="l00365"></a>00365                 DWC_WARN(<span class="stringliteral">"bogus device state\n"</span>);
+<a name="l00366"></a>00366                 <span class="keywordflow">return</span> -ESHUTDOWN;
+<a name="l00367"></a>00367         }
+<a name="l00368"></a>00368         <span class="keywordflow">if</span> (<a class="code" href="dwc__otg__pcd_8c.html#aa7546ce68d6fda67bb4cda0f69eedf3">dwc_otg_pcd_ep_dequeue</a>(<a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;pcd, usb_ep, usb_req)) {
+<a name="l00369"></a>00369                 <span class="keywordflow">return</span> -EINVAL;
+<a name="l00370"></a>00370         }
+<a name="l00371"></a>00371 
+<a name="l00372"></a>00372         <span class="keywordflow">return</span> 0;
+<a name="l00373"></a>00373 }
+<a name="l00374"></a>00374 
+<a name="l00391"></a><a class="code" href="dwc__otg__pcd__linux_8c.html#8ee99e0e68c8e50e94c242805b158cb2">00391</a> <span class="keyword">static</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__pcd__linux_8c.html#8ee99e0e68c8e50e94c242805b158cb2">ep_halt</a>(<span class="keyword">struct</span> usb_ep *usb_ep, <span class="keywordtype">int</span> value)
+<a name="l00392"></a>00392 {
+<a name="l00393"></a>00393         <span class="keywordtype">int</span> retval = 0;
+<a name="l00394"></a>00394 
+<a name="l00395"></a>00395         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"HALT %s %d\n"</span>, usb_ep-&gt;name, value);
+<a name="l00396"></a>00396 
+<a name="l00397"></a>00397         <span class="keywordflow">if</span> (!usb_ep) {
+<a name="l00398"></a>00398                 DWC_WARN(<span class="stringliteral">"bad ep\n"</span>);
+<a name="l00399"></a>00399                 <span class="keywordflow">return</span> -EINVAL;
+<a name="l00400"></a>00400         }
+<a name="l00401"></a>00401 
+<a name="l00402"></a>00402         retval = <a class="code" href="dwc__otg__pcd_8c.html#f7d01b4772f08c6a08f4a22300a7b43b">dwc_otg_pcd_ep_halt</a>(<a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;pcd, usb_ep, value);
+<a name="l00403"></a>00403         <span class="keywordflow">if</span> (retval == -DWC_E_AGAIN) {
+<a name="l00404"></a>00404                 <span class="keywordflow">return</span> -EAGAIN;
+<a name="l00405"></a>00405         } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (retval) {
+<a name="l00406"></a>00406                 retval = -EINVAL;
+<a name="l00407"></a>00407         }
+<a name="l00408"></a>00408 
+<a name="l00409"></a>00409         <span class="keywordflow">return</span> retval;
+<a name="l00410"></a>00410 }
+<a name="l00411"></a>00411 
+<a name="l00412"></a>00412 <span class="preprocessor">#ifdef DWC_EN_ISOC</span>
+<a name="l00413"></a>00413 <span class="preprocessor"></span>
+<a name="l00422"></a><a class="code" href="dwc__otg__pcd__linux_8c.html#eb3df484c8c344613a2a9b23e24036a8">00422</a> <span class="keyword">static</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__pcd__linux_8c.html#eb3df484c8c344613a2a9b23e24036a8">iso_ep_start</a>(<span class="keyword">struct</span> usb_ep *usb_ep, <span class="keyword">struct</span> usb_iso_request *req,
+<a name="l00423"></a>00423                         gfp_t gfp_flags)
+<a name="l00424"></a>00424 {
+<a name="l00425"></a>00425         <span class="keywordtype">int</span> retval = 0;
+<a name="l00426"></a>00426 
+<a name="l00427"></a>00427         <span class="keywordflow">if</span> (!req || !req-&gt;process_buffer || !req-&gt;buf0 || !req-&gt;buf1) {
+<a name="l00428"></a>00428                 DWC_WARN(<span class="stringliteral">"bad params\n"</span>);
+<a name="l00429"></a>00429                 <span class="keywordflow">return</span> -EINVAL;
+<a name="l00430"></a>00430         }
+<a name="l00431"></a>00431 
+<a name="l00432"></a>00432         <span class="keywordflow">if</span> (!usb_ep) {
+<a name="l00433"></a>00433                 DWC_PRINTF(<span class="stringliteral">"bad params\n"</span>);
+<a name="l00434"></a>00434                 <span class="keywordflow">return</span> -EINVAL;
+<a name="l00435"></a>00435         }
+<a name="l00436"></a>00436 
+<a name="l00437"></a>00437         req-&gt;status = -EINPROGRESS;
+<a name="l00438"></a>00438 
+<a name="l00439"></a>00439         retval =
+<a name="l00440"></a>00440             <a class="code" href="dwc__otg__pcd_8c.html#e0a690ac031f8f06c2e7fb10b4633b05">dwc_otg_pcd_iso_ep_start</a>(<a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;pcd, usb_ep, req-&gt;buf0,
+<a name="l00441"></a>00441                                      req-&gt;buf1, req-&gt;dma0, req-&gt;dma1,
+<a name="l00442"></a>00442                                      req-&gt;sync_frame, req-&gt;data_pattern_frame,
+<a name="l00443"></a>00443                                      req-&gt;data_per_frame,
+<a name="l00444"></a>00444                                      req-&gt;flags &amp; USB_REQ_ISO_ASAP ? -1 : req-&gt;
+<a name="l00445"></a>00445                                      start_frame, req-&gt;buf_proc_intrvl, req,
+<a name="l00446"></a>00446                                      gfp_flags == GFP_ATOMIC ? 1 : 0);
+<a name="l00447"></a>00447 
+<a name="l00448"></a>00448         <span class="keywordflow">if</span> (retval) {
+<a name="l00449"></a>00449                 <span class="keywordflow">return</span> -EINVAL;
+<a name="l00450"></a>00450         }
+<a name="l00451"></a>00451 
+<a name="l00452"></a>00452         <span class="keywordflow">return</span> retval;
+<a name="l00453"></a>00453 }
+<a name="l00454"></a>00454 
+<a name="l00458"></a><a class="code" href="dwc__otg__pcd__linux_8c.html#cecdcaa060d30ac09414419545a5d1c6">00458</a> <span class="keyword">static</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__pcd__linux_8c.html#cecdcaa060d30ac09414419545a5d1c6">iso_ep_stop</a>(<span class="keyword">struct</span> usb_ep *usb_ep, <span class="keyword">struct</span> usb_iso_request *req)
+<a name="l00459"></a>00459 {
+<a name="l00460"></a>00460         <span class="keywordtype">int</span> retval = 0;
+<a name="l00461"></a>00461         <span class="keywordflow">if</span> (!usb_ep) {
+<a name="l00462"></a>00462                 DWC_WARN(<span class="stringliteral">"bad ep\n"</span>);
+<a name="l00463"></a>00463         }
+<a name="l00464"></a>00464 
+<a name="l00465"></a>00465         <span class="keywordflow">if</span> (!<a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;driver ||
+<a name="l00466"></a>00466             <a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;gadget.speed == USB_SPEED_UNKNOWN) {
+<a name="l00467"></a>00467                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"gadget.speed=%d\n"</span>,
+<a name="l00468"></a>00468                             <a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;gadget.speed);
+<a name="l00469"></a>00469                 DWC_WARN(<span class="stringliteral">"bogus device state\n"</span>);
+<a name="l00470"></a>00470         }
+<a name="l00471"></a>00471 
+<a name="l00472"></a>00472         <a class="code" href="dwc__otg__pcd_8c.html#5098f89da28c6b450e7e10b31441b945">dwc_otg_pcd_iso_ep_stop</a>(<a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;pcd, usb_ep, req);
+<a name="l00473"></a>00473         <span class="keywordflow">if</span> (retval) {
+<a name="l00474"></a>00474                 retval = -EINVAL;
+<a name="l00475"></a>00475         }
+<a name="l00476"></a>00476 
+<a name="l00477"></a>00477         <span class="keywordflow">return</span> retval;
+<a name="l00478"></a>00478 }
+<a name="l00479"></a>00479 
+<a name="l00480"></a><a class="code" href="dwc__otg__pcd__linux_8c.html#94fd50b5e9d41d1d38a503d819fc07c4">00480</a> <span class="keyword">static</span> <span class="keyword">struct </span>usb_iso_request *<a class="code" href="dwc__otg__pcd__linux_8c.html#94fd50b5e9d41d1d38a503d819fc07c4">alloc_iso_request</a>(<span class="keyword">struct</span> usb_ep *ep,
+<a name="l00481"></a>00481                                                  <span class="keywordtype">int</span> packets, gfp_t gfp_flags)
+<a name="l00482"></a>00482 {
+<a name="l00483"></a>00483         <span class="keyword">struct </span>usb_iso_request *pReq = NULL;
+<a name="l00484"></a>00484         uint32_t req_size;
+<a name="l00485"></a>00485 
+<a name="l00486"></a>00486         req_size = <span class="keyword">sizeof</span>(<span class="keyword">struct </span>usb_iso_request);
+<a name="l00487"></a>00487         req_size +=
+<a name="l00488"></a>00488             (2 * packets * (<span class="keyword">sizeof</span>(<span class="keyword">struct </span>usb_gadget_iso_packet_descriptor)));
+<a name="l00489"></a>00489 
+<a name="l00490"></a>00490         pReq = kmalloc(req_size, gfp_flags);
+<a name="l00491"></a>00491         <span class="keywordflow">if</span> (!pReq) {
+<a name="l00492"></a>00492                 DWC_WARN(<span class="stringliteral">"Can't allocate Iso Request\n"</span>);
+<a name="l00493"></a>00493                 <span class="keywordflow">return</span> 0;
+<a name="l00494"></a>00494         }
+<a name="l00495"></a>00495         pReq-&gt;iso_packet_desc0 = (<span class="keywordtype">void</span> *)(pReq + 1);
+<a name="l00496"></a>00496 
+<a name="l00497"></a>00497         pReq-&gt;iso_packet_desc1 = pReq-&gt;iso_packet_desc0 + packets;
+<a name="l00498"></a>00498 
+<a name="l00499"></a>00499         <span class="keywordflow">return</span> pReq;
+<a name="l00500"></a>00500 }
+<a name="l00501"></a>00501 
+<a name="l00502"></a><a class="code" href="dwc__otg__pcd__linux_8c.html#a9a7bc869bc7f3d05804059f3277d11a">00502</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd__linux_8c.html#a9a7bc869bc7f3d05804059f3277d11a">free_iso_request</a>(<span class="keyword">struct</span> usb_ep *ep, <span class="keyword">struct</span> usb_iso_request *req)
+<a name="l00503"></a>00503 {
+<a name="l00504"></a>00504         kfree(req);
+<a name="l00505"></a>00505 }
+<a name="l00506"></a>00506 
+<a name="l00507"></a><a class="code" href="dwc__otg__pcd__linux_8c.html#8d23bf781df0ba0fb4a0133d08c09dc1">00507</a> <span class="keyword">static</span> <span class="keyword">struct </span>usb_isoc_ep_ops <a class="code" href="dwc__otg__pcd__linux_8c.html#8d23bf781df0ba0fb4a0133d08c09dc1">dwc_otg_pcd_ep_ops</a> = {
+<a name="l00508"></a>00508         .ep_ops = {
+<a name="l00509"></a>00509                    .enable = <a class="code" href="dwc__otg__pcd__linux_8c.html#9761890d7f741f9421d82254c9846f31">ep_enable</a>,
+<a name="l00510"></a>00510                    .disable = <a class="code" href="dwc__otg__pcd__linux_8c.html#1708514cb93c5da43a8f634de1c0f5e7">ep_disable</a>,
+<a name="l00511"></a>00511 
+<a name="l00512"></a>00512                    .alloc_request = <a class="code" href="dwc__otg__pcd__linux_8c.html#e5a3f75b9a06a4707d1d0ec5957daa7d">dwc_otg_pcd_alloc_request</a>,
+<a name="l00513"></a>00513                    .free_request = <a class="code" href="dwc__otg__pcd__linux_8c.html#348338816bfc0e711c4b875997ed00d9">dwc_otg_pcd_free_request</a>,
+<a name="l00514"></a>00514 
+<a name="l00515"></a>00515                    .alloc_buffer = <a class="code" href="dwc__otg__pcd__linux_8c.html#295957efef868247c889aa3f5050af00">dwc_otg_pcd_alloc_buffer</a>,
+<a name="l00516"></a>00516                    .free_buffer = <a class="code" href="dwc__otg__pcd__linux_8c.html#675a197388a82da27f74c11ffdbf874b">dwc_otg_pcd_free_buffer</a>,
+<a name="l00517"></a>00517 
+<a name="l00518"></a>00518                    .queue = <a class="code" href="dwc__otg__pcd__linux_8c.html#f97bea831037135af73c3c202e3e01dc">ep_queue</a>,
+<a name="l00519"></a>00519                    .dequeue = <a class="code" href="dwc__otg__pcd__linux_8c.html#e2e4913a926acc55f4e57c3ff8f97c08">ep_dequeue</a>,
+<a name="l00520"></a>00520 
+<a name="l00521"></a>00521                    .set_halt = <a class="code" href="dwc__otg__pcd__linux_8c.html#8ee99e0e68c8e50e94c242805b158cb2">ep_halt</a>,
+<a name="l00522"></a>00522                    .fifo_status = 0,
+<a name="l00523"></a>00523                    .fifo_flush = 0,
+<a name="l00524"></a>00524                    },
+<a name="l00525"></a>00525         .iso_ep_start = <a class="code" href="dwc__otg__pcd__linux_8c.html#eb3df484c8c344613a2a9b23e24036a8">iso_ep_start</a>,
+<a name="l00526"></a>00526         .iso_ep_stop = <a class="code" href="dwc__otg__pcd__linux_8c.html#cecdcaa060d30ac09414419545a5d1c6">iso_ep_stop</a>,
+<a name="l00527"></a>00527         .alloc_iso_request = <a class="code" href="dwc__otg__pcd__linux_8c.html#94fd50b5e9d41d1d38a503d819fc07c4">alloc_iso_request</a>,
+<a name="l00528"></a>00528         .free_iso_request = <a class="code" href="dwc__otg__pcd__linux_8c.html#a9a7bc869bc7f3d05804059f3277d11a">free_iso_request</a>,
+<a name="l00529"></a>00529 };
+<a name="l00530"></a>00530 
+<a name="l00531"></a>00531 <span class="preprocessor">#else</span>
+<a name="l00532"></a>00532 <span class="preprocessor"></span>
+<a name="l00533"></a>00533 <span class="keyword">static</span> <span class="keyword">struct </span>usb_ep_ops <a class="code" href="dwc__otg__pcd__linux_8c.html#8d23bf781df0ba0fb4a0133d08c09dc1">dwc_otg_pcd_ep_ops</a> = {
+<a name="l00534"></a>00534         .enable = <a class="code" href="dwc__otg__pcd__linux_8c.html#9761890d7f741f9421d82254c9846f31">ep_enable</a>,
+<a name="l00535"></a>00535         .disable = <a class="code" href="dwc__otg__pcd__linux_8c.html#1708514cb93c5da43a8f634de1c0f5e7">ep_disable</a>,
+<a name="l00536"></a>00536 
+<a name="l00537"></a>00537         .alloc_request = <a class="code" href="dwc__otg__pcd__linux_8c.html#e5a3f75b9a06a4707d1d0ec5957daa7d">dwc_otg_pcd_alloc_request</a>,
+<a name="l00538"></a>00538         .free_request = <a class="code" href="dwc__otg__pcd__linux_8c.html#348338816bfc0e711c4b875997ed00d9">dwc_otg_pcd_free_request</a>,
+<a name="l00539"></a>00539 
+<a name="l00540"></a>00540         .alloc_buffer = <a class="code" href="dwc__otg__pcd__linux_8c.html#295957efef868247c889aa3f5050af00">dwc_otg_pcd_alloc_buffer</a>,
+<a name="l00541"></a>00541         .free_buffer = <a class="code" href="dwc__otg__pcd__linux_8c.html#675a197388a82da27f74c11ffdbf874b">dwc_otg_pcd_free_buffer</a>,
+<a name="l00542"></a>00542 
+<a name="l00543"></a>00543         .queue = <a class="code" href="dwc__otg__pcd__linux_8c.html#f97bea831037135af73c3c202e3e01dc">ep_queue</a>,
+<a name="l00544"></a>00544         .dequeue = <a class="code" href="dwc__otg__pcd__linux_8c.html#e2e4913a926acc55f4e57c3ff8f97c08">ep_dequeue</a>,
+<a name="l00545"></a>00545 
+<a name="l00546"></a>00546         .set_halt = <a class="code" href="dwc__otg__pcd__linux_8c.html#8ee99e0e68c8e50e94c242805b158cb2">ep_halt</a>,
+<a name="l00547"></a>00547         .fifo_status = 0,
+<a name="l00548"></a>00548         .fifo_flush = 0,
+<a name="l00549"></a>00549 
+<a name="l00550"></a>00550 };
+<a name="l00551"></a>00551 
+<a name="l00552"></a>00552 <span class="preprocessor">#endif                          </span><span class="comment">/* _EN_ISOC_ */</span>
+<a name="l00553"></a>00553 <span class="comment">/*      Gadget Operations */</span>
+<a name="l00572"></a><a class="code" href="dwc__otg__pcd__linux_8c.html#7af23be44d3ad24c67cd1e22579dd90e">00572</a> <span class="keyword">static</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd__linux_8c.html#c78128edb8902dc96534c5bb253f99a3">get_frame_number</a>(<span class="keyword">struct</span> usb_gadget *gadget)
+<a name="l00573"></a>00573 {
+<a name="l00574"></a>00574         <span class="keyword">struct </span><a class="code" href="structgadget__wrapper.html">gadget_wrapper</a> *d;
+<a name="l00575"></a>00575 
+<a name="l00576"></a>00576         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"%s(%p)\n"</span>, __func__, gadget);
+<a name="l00577"></a>00577 
+<a name="l00578"></a>00578         <span class="keywordflow">if</span> (gadget == 0) {
+<a name="l00579"></a>00579                 <span class="keywordflow">return</span> -ENODEV;
+<a name="l00580"></a>00580         }
+<a name="l00581"></a>00581 
+<a name="l00582"></a>00582         d = container_of(gadget, <span class="keyword">struct</span> <a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>, gadget);
+<a name="l00583"></a>00583         <span class="keywordflow">return</span> <a class="code" href="dwc__otg__pcd_8c.html#04876b716043a853b379d72ff3a215e5">dwc_otg_pcd_get_frame_number</a>(d-&gt;<a class="code" href="structgadget__wrapper.html#cdc4a50b5415cc484f77c61a63db3e94">pcd</a>);
+<a name="l00584"></a>00584 }
+<a name="l00585"></a>00585 
+<a name="l00586"></a>00586 <span class="preprocessor">#ifdef CONFIG_USB_DWC_OTG_LPM</span>
+<a name="l00587"></a>00587 <span class="preprocessor"></span><span class="keyword">static</span> <span class="keywordtype">int</span> test_lpm_enabled(<span class="keyword">struct</span> usb_gadget *<a class="code" href="structgadget__wrapper.html#a1f30b68c6b42bc728c45c329312d7b1">gadget</a>)
+<a name="l00588"></a>00588 {
+<a name="l00589"></a>00589         <span class="keyword">struct </span><a class="code" href="structgadget__wrapper.html">gadget_wrapper</a> *d;
+<a name="l00590"></a>00590 
+<a name="l00591"></a>00591         d = container_of(gadget, <span class="keyword">struct</span> <a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>, gadget);
+<a name="l00592"></a>00592 
+<a name="l00593"></a>00593         <span class="keywordflow">return</span> <a class="code" href="dwc__otg__pcd_8c.html#676021c9b801674669cdf2d1e68d5b8c">dwc_otg_pcd_is_lpm_enabled</a>(d-&gt;<a class="code" href="structgadget__wrapper.html#cdc4a50b5415cc484f77c61a63db3e94">pcd</a>);
+<a name="l00594"></a>00594 }
+<a name="l00595"></a>00595 <span class="preprocessor">#endif</span>
+<a name="l00596"></a>00596 <span class="preprocessor"></span>
+<a name="l00603"></a><a class="code" href="dwc__otg__pcd__linux_8c.html#6a6034564b7cc6d8cebfbe02a944cd2c">00603</a> <span class="keyword">static</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__pcd__linux_8c.html#6a6034564b7cc6d8cebfbe02a944cd2c">wakeup</a>(<span class="keyword">struct</span> usb_gadget *<a class="code" href="structgadget__wrapper.html#a1f30b68c6b42bc728c45c329312d7b1">gadget</a>)
+<a name="l00604"></a>00604 {
+<a name="l00605"></a>00605         <span class="keyword">struct </span><a class="code" href="structgadget__wrapper.html">gadget_wrapper</a> *d;
+<a name="l00606"></a>00606 
+<a name="l00607"></a>00607         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"%s(%p)\n"</span>, __func__, gadget);
+<a name="l00608"></a>00608 
+<a name="l00609"></a>00609         <span class="keywordflow">if</span> (gadget == 0) {
+<a name="l00610"></a>00610                 <span class="keywordflow">return</span> -ENODEV;
+<a name="l00611"></a>00611         } <span class="keywordflow">else</span> {
+<a name="l00612"></a>00612                 d = container_of(gadget, <span class="keyword">struct</span> <a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>, gadget);
+<a name="l00613"></a>00613         }
+<a name="l00614"></a>00614         <a class="code" href="dwc__otg__pcd_8c.html#7e0d7b09dc6528626f4643deb296d68d">dwc_otg_pcd_wakeup</a>(d-&gt;<a class="code" href="structgadget__wrapper.html#cdc4a50b5415cc484f77c61a63db3e94">pcd</a>);
+<a name="l00615"></a>00615         <span class="keywordflow">return</span> 0;
+<a name="l00616"></a>00616 }
+<a name="l00617"></a>00617 
+<a name="l00618"></a><a class="code" href="dwc__otg__pcd__linux_8c.html#592a942ef237021f608d03dd8b57bc54">00618</a> <span class="keyword">static</span> <span class="keyword">const</span> <span class="keyword">struct </span>usb_gadget_ops <a class="code" href="dwc__otg__pcd__linux_8c.html#592a942ef237021f608d03dd8b57bc54">dwc_otg_pcd_ops</a> = {
+<a name="l00619"></a>00619         .get_frame = <a class="code" href="dwc__otg__hcd__linux_8c.html#c78128edb8902dc96534c5bb253f99a3">get_frame_number</a>,
+<a name="l00620"></a>00620         .wakeup = <a class="code" href="dwc__otg__pcd__linux_8c.html#6a6034564b7cc6d8cebfbe02a944cd2c">wakeup</a>,
+<a name="l00621"></a>00621 <span class="preprocessor">#ifdef CONFIG_USB_DWC_OTG_LPM</span>
+<a name="l00622"></a>00622 <span class="preprocessor"></span>        .lpm_support = test_lpm_enabled,
+<a name="l00623"></a>00623 <span class="preprocessor">#endif</span>
+<a name="l00624"></a>00624 <span class="preprocessor"></span>        <span class="comment">// current versions must always be self-powered</span>
+<a name="l00625"></a>00625 };
+<a name="l00626"></a>00626 
+<a name="l00627"></a><a class="code" href="dwc__otg__pcd__linux_8c.html#4a1481839b3d869d882f984a6c6ed9e5">00627</a> <span class="keyword">static</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__pcd__linux_8c.html#4a1481839b3d869d882f984a6c6ed9e5">_setup</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd, uint8_t * bytes)
+<a name="l00628"></a>00628 {
+<a name="l00629"></a>00629         <span class="keywordtype">int</span> retval = -DWC_E_NOT_SUPPORTED;
+<a name="l00630"></a>00630         <span class="keywordflow">if</span> (<a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;driver &amp;&amp; <a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;driver-&gt;setup) {
+<a name="l00631"></a>00631                 retval = <a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;driver-&gt;setup(&amp;<a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;gadget,
+<a name="l00632"></a>00632                                                        (<span class="keyword">struct</span> usb_ctrlrequest
+<a name="l00633"></a>00633                                                         *)bytes);
+<a name="l00634"></a>00634         }
+<a name="l00635"></a>00635 
+<a name="l00636"></a>00636         <span class="keywordflow">if</span> (retval == -ENOTSUPP) {
+<a name="l00637"></a>00637                 retval = -DWC_E_NOT_SUPPORTED;
+<a name="l00638"></a>00638         } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (retval &lt; 0) {
+<a name="l00639"></a>00639                 retval = -DWC_E_INVALID;
+<a name="l00640"></a>00640         }
+<a name="l00641"></a>00641 
+<a name="l00642"></a>00642         <span class="keywordflow">return</span> retval;
+<a name="l00643"></a>00643 }
+<a name="l00644"></a>00644 
+<a name="l00645"></a>00645 <span class="preprocessor">#ifdef DWC_EN_ISOC</span>
+<a name="l00646"></a><a class="code" href="dwc__otg__pcd__linux_8c.html#737e47386e05da8cf6cbf85a289f5454">00646</a> <span class="preprocessor"></span><span class="keyword">static</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__pcd__linux_8c.html#737e47386e05da8cf6cbf85a289f5454">_isoc_complete</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd, <span class="keywordtype">void</span> *ep_handle,
+<a name="l00647"></a>00647                           <span class="keywordtype">void</span> *req_handle, <span class="keywordtype">int</span> proc_buf_num)
+<a name="l00648"></a>00648 {
+<a name="l00649"></a>00649         <span class="keywordtype">int</span> i, packet_count;
+<a name="l00650"></a>00650         <span class="keyword">struct </span>usb_gadget_iso_packet_descriptor *iso_packet = 0;
+<a name="l00651"></a>00651         <span class="keyword">struct </span>usb_iso_request *iso_req = req_handle;
+<a name="l00652"></a>00652 
+<a name="l00653"></a>00653         <span class="keywordflow">if</span> (proc_buf_num) {
+<a name="l00654"></a>00654                 iso_packet = iso_req-&gt;iso_packet_desc1;
+<a name="l00655"></a>00655         } <span class="keywordflow">else</span> {
+<a name="l00656"></a>00656                 iso_packet = iso_req-&gt;iso_packet_desc0;
+<a name="l00657"></a>00657         }
+<a name="l00658"></a>00658         packet_count =
+<a name="l00659"></a>00659             <a class="code" href="dwc__otg__pcd_8c.html#2f04b14612c2b58909b3a54ed71ab12e">dwc_otg_pcd_get_iso_packet_count</a>(pcd, ep_handle, req_handle);
+<a name="l00660"></a>00660         <span class="keywordflow">for</span> (i = 0; i &lt; packet_count; ++i) {
+<a name="l00661"></a>00661                 <span class="keywordtype">int</span> status;
+<a name="l00662"></a>00662                 <span class="keywordtype">int</span> actual;
+<a name="l00663"></a>00663                 <span class="keywordtype">int</span> offset;
+<a name="l00664"></a>00664                 <a class="code" href="dwc__otg__pcd_8c.html#21149047aa9abddac5654e4496175ac5">dwc_otg_pcd_get_iso_packet_params</a>(pcd, ep_handle, req_handle,
+<a name="l00665"></a>00665                                                   i, &amp;status, &amp;actual, &amp;offset);
+<a name="l00666"></a>00666                 <span class="keywordflow">switch</span> (status) {
+<a name="l00667"></a>00667                 <span class="keywordflow">case</span> -DWC_E_NO_DATA:
+<a name="l00668"></a>00668                         status = -ENODATA;
+<a name="l00669"></a>00669                         <span class="keywordflow">break</span>;
+<a name="l00670"></a>00670                 <span class="keywordflow">default</span>:
+<a name="l00671"></a>00671                         <span class="keywordflow">if</span> (status) {
+<a name="l00672"></a>00672                                 DWC_PRINTF(<span class="stringliteral">"unknown status in isoc packet\n"</span>);
+<a name="l00673"></a>00673                         }
+<a name="l00674"></a>00674 
+<a name="l00675"></a>00675                 }
+<a name="l00676"></a>00676                 iso_packet[i].status = status;
+<a name="l00677"></a>00677                 iso_packet[i].offset = offset;
+<a name="l00678"></a>00678                 iso_packet[i].actual_length = actual;
+<a name="l00679"></a>00679         }
+<a name="l00680"></a>00680 
+<a name="l00681"></a>00681         iso_req-&gt;status = 0;
+<a name="l00682"></a>00682         iso_req-&gt;process_buffer(ep_handle, iso_req);
+<a name="l00683"></a>00683 
+<a name="l00684"></a>00684         <span class="keywordflow">return</span> 0;
+<a name="l00685"></a>00685 }
+<a name="l00686"></a>00686 <span class="preprocessor">#endif                          </span><span class="comment">/* DWC_EN_ISOC */</span>
+<a name="l00687"></a>00687 
+<a name="l00688"></a><a class="code" href="dwc__otg__pcd__linux_8c.html#e1d629bc692aa1e42584459867b1aeaa">00688</a> <span class="keyword">static</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd__linux_8c.html#a0d18986574c384e98aa280e0475a9aa">_complete</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd, <span class="keywordtype">void</span> *ep_handle,
+<a name="l00689"></a>00689                      <span class="keywordtype">void</span> *req_handle, int32_t status, uint32_t actual)
+<a name="l00690"></a>00690 {
+<a name="l00691"></a>00691         <span class="keyword">struct </span>usb_request *req = (<span class="keyword">struct </span>usb_request *)req_handle;
+<a name="l00692"></a>00692 
+<a name="l00693"></a>00693         <span class="keywordflow">if</span> (req &amp;&amp; req-&gt;complete) {
+<a name="l00694"></a>00694                 <span class="keywordflow">switch</span> (status) {
+<a name="l00695"></a>00695                 <span class="keywordflow">case</span> -DWC_E_SHUTDOWN:
+<a name="l00696"></a>00696                         req-&gt;status = -ESHUTDOWN;
+<a name="l00697"></a>00697                         <span class="keywordflow">break</span>;
+<a name="l00698"></a>00698                 <span class="keywordflow">case</span> -DWC_E_RESTART:
+<a name="l00699"></a>00699                         req-&gt;status = -ECONNRESET;
+<a name="l00700"></a>00700                         <span class="keywordflow">break</span>;
+<a name="l00701"></a>00701                 <span class="keywordflow">case</span> -DWC_E_INVALID:
+<a name="l00702"></a>00702                         req-&gt;status = -EINVAL;
+<a name="l00703"></a>00703                         <span class="keywordflow">break</span>;
+<a name="l00704"></a>00704                 <span class="keywordflow">case</span> -DWC_E_TIMEOUT:
+<a name="l00705"></a>00705                         req-&gt;status = -ETIMEDOUT;
+<a name="l00706"></a>00706                         <span class="keywordflow">break</span>;
+<a name="l00707"></a>00707                 <span class="keywordflow">default</span>:
+<a name="l00708"></a>00708                         req-&gt;status = status;
+<a name="l00709"></a>00709 
+<a name="l00710"></a>00710                 }
+<a name="l00711"></a>00711                 req-&gt;actual = actual;
+<a name="l00712"></a>00712                 req-&gt;complete(ep_handle, req);
+<a name="l00713"></a>00713         }
+<a name="l00714"></a>00714 
+<a name="l00715"></a>00715         <span class="keywordflow">return</span> 0;
+<a name="l00716"></a>00716 }
+<a name="l00717"></a>00717 
+<a name="l00718"></a><a class="code" href="dwc__otg__pcd__linux_8c.html#c7c1c4f8fe8e62f1d9e6f75de5563658">00718</a> <span class="keyword">static</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__pcd__linux_8c.html#c7c1c4f8fe8e62f1d9e6f75de5563658">_connect</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd, <span class="keywordtype">int</span> speed)
+<a name="l00719"></a>00719 {
+<a name="l00720"></a>00720         <a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;gadget.speed = speed;
+<a name="l00721"></a>00721         <span class="keywordflow">return</span> 0;
+<a name="l00722"></a>00722 }
+<a name="l00723"></a>00723 
+<a name="l00724"></a><a class="code" href="dwc__otg__pcd__linux_8c.html#682f9829330d06521a5d4c00702e4580">00724</a> <span class="keyword">static</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__hcd__linux_8c.html#8011f9b662a7f4182e762de616bbc95e">_disconnect</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd)
+<a name="l00725"></a>00725 {
+<a name="l00726"></a>00726         <span class="keywordflow">if</span> (<a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;driver &amp;&amp; <a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;driver-&gt;disconnect) {
+<a name="l00727"></a>00727                 <a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;driver-&gt;disconnect(&amp;<a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;gadget);
+<a name="l00728"></a>00728         }
+<a name="l00729"></a>00729         <span class="keywordflow">return</span> 0;
+<a name="l00730"></a>00730 }
+<a name="l00731"></a>00731 
+<a name="l00732"></a><a class="code" href="dwc__otg__pcd__linux_8c.html#86cdfe71d125da339e17e52049fc5ea0">00732</a> <span class="keyword">static</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__pcd__linux_8c.html#86cdfe71d125da339e17e52049fc5ea0">_resume</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd)
+<a name="l00733"></a>00733 {
+<a name="l00734"></a>00734         <span class="keywordflow">if</span> (<a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;driver &amp;&amp; <a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;driver-&gt;resume) {
+<a name="l00735"></a>00735                 <a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;driver-&gt;resume(&amp;<a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;gadget);
+<a name="l00736"></a>00736         }
+<a name="l00737"></a>00737 
+<a name="l00738"></a>00738         <span class="keywordflow">return</span> 0;
+<a name="l00739"></a>00739 }
+<a name="l00740"></a>00740 
+<a name="l00741"></a><a class="code" href="dwc__otg__pcd__linux_8c.html#7f479ecaee0801b55b4f0bd0f36f8b67">00741</a> <span class="keyword">static</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__pcd__linux_8c.html#7f479ecaee0801b55b4f0bd0f36f8b67">_suspend</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd)
+<a name="l00742"></a>00742 {
+<a name="l00743"></a>00743         <span class="keywordflow">if</span> (<a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;driver &amp;&amp; <a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;driver-&gt;suspend) {
+<a name="l00744"></a>00744                 <a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;driver-&gt;suspend(&amp;<a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;gadget);
+<a name="l00745"></a>00745         }
+<a name="l00746"></a>00746         <span class="keywordflow">return</span> 0;
+<a name="l00747"></a>00747 }
+<a name="l00748"></a>00748 
+<a name="l00752"></a><a class="code" href="dwc__otg__pcd__linux_8c.html#9e8595e1d36e6b1ffbc27c4862957a08">00752</a> <span class="keyword">static</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__pcd__linux_8c.html#9e8595e1d36e6b1ffbc27c4862957a08">_hnp_changed</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd)
+<a name="l00753"></a>00753 {
+<a name="l00754"></a>00754 
+<a name="l00755"></a>00755         <span class="keywordflow">if</span> (!<a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;gadget.is_otg)
+<a name="l00756"></a>00756                 <span class="keywordflow">return</span> 0;
+<a name="l00757"></a>00757 
+<a name="l00758"></a>00758         <a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;gadget.b_hnp_enable = <a class="code" href="dwc__otg__pcd_8c.html#777a6a4e250add9ba5f5f5d63d854031">get_b_hnp_enable</a>(pcd);
+<a name="l00759"></a>00759         <a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;gadget.a_hnp_support = <a class="code" href="dwc__otg__pcd_8c.html#69d0bb469e15cb46f00c17398f76df99">get_a_hnp_support</a>(pcd);
+<a name="l00760"></a>00760         <a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;gadget.a_alt_hnp_support = <a class="code" href="dwc__otg__pcd_8c.html#842709a4980bc78d49726fa880922dda">get_a_alt_hnp_support</a>(pcd);
+<a name="l00761"></a>00761         <span class="keywordflow">return</span> 0;
+<a name="l00762"></a>00762 }
+<a name="l00763"></a>00763 
+<a name="l00764"></a><a class="code" href="dwc__otg__pcd__linux_8c.html#208cf9e0227e5f81e015ed3ac5bacec4">00764</a> <span class="keyword">static</span> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__pcd__linux_8c.html#208cf9e0227e5f81e015ed3ac5bacec4">_reset</a>(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd)
+<a name="l00765"></a>00765 {
+<a name="l00766"></a>00766         <span class="keywordflow">return</span> 0;
+<a name="l00767"></a>00767 }
+<a name="l00768"></a>00768 
+<a name="l00769"></a>00769 <span class="preprocessor">#ifdef DWC_UTE_CFI</span>
+<a name="l00770"></a>00770 <span class="preprocessor"></span><span class="keyword">static</span> <span class="keywordtype">int</span> _cfi_setup(<a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> * pcd, <span class="keywordtype">void</span> *cfi_req)
+<a name="l00771"></a>00771 {
+<a name="l00772"></a>00772         <span class="keywordtype">int</span> retval = -DWC_E_INVALID;
+<a name="l00773"></a>00773         <span class="keywordflow">if</span> (<a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;driver-&gt;cfi_feature_setup) {
+<a name="l00774"></a>00774                 retval =
+<a name="l00775"></a>00775                     <a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;driver-&gt;cfi_feature_setup(&amp;<a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;
+<a name="l00776"></a>00776                                                               gadget,
+<a name="l00777"></a>00777                                                               (<span class="keyword">struct</span>
+<a name="l00778"></a>00778                                                                <a class="code" href="structcfi__usb__ctrlrequest.html">cfi_usb_ctrlrequest</a>
+<a name="l00779"></a>00779                                                                *)cfi_req);
+<a name="l00780"></a>00780         }
+<a name="l00781"></a>00781 
+<a name="l00782"></a>00782         <span class="keywordflow">return</span> retval;
+<a name="l00783"></a>00783 }
+<a name="l00784"></a>00784 <span class="preprocessor">#endif</span>
+<a name="l00785"></a>00785 <span class="preprocessor"></span>
+<a name="l00786"></a><a class="code" href="dwc__otg__pcd__linux_8c.html#9ce9b5e49c60906c189bee157dd68acd">00786</a> <span class="keyword">static</span> <span class="keyword">const</span> <span class="keyword">struct </span><a class="code" href="structdwc__otg__pcd__function__ops.html">dwc_otg_pcd_function_ops</a> <a class="code" href="dwc__otg__pcd__linux_8c.html#9ce9b5e49c60906c189bee157dd68acd">fops</a> = {
+<a name="l00787"></a>00787         .<a class="code" href="structdwc__otg__pcd__function__ops.html#126db5e83cd3cc03f303eb3da668816f">complete</a> = <a class="code" href="dwc__otg__hcd__linux_8c.html#a0d18986574c384e98aa280e0475a9aa">_complete</a>,
+<a name="l00788"></a>00788 <span class="preprocessor">#ifdef DWC_EN_ISOC</span>
+<a name="l00789"></a>00789 <span class="preprocessor"></span>        .isoc_complete = <a class="code" href="dwc__otg__pcd__linux_8c.html#737e47386e05da8cf6cbf85a289f5454">_isoc_complete</a>,
+<a name="l00790"></a>00790 <span class="preprocessor">#endif</span>
+<a name="l00791"></a>00791 <span class="preprocessor"></span>        .setup = <a class="code" href="dwc__otg__pcd__linux_8c.html#4a1481839b3d869d882f984a6c6ed9e5">_setup</a>,
+<a name="l00792"></a>00792         .disconnect = <a class="code" href="dwc__otg__hcd__linux_8c.html#8011f9b662a7f4182e762de616bbc95e">_disconnect</a>,
+<a name="l00793"></a>00793         .connect = <a class="code" href="dwc__otg__pcd__linux_8c.html#c7c1c4f8fe8e62f1d9e6f75de5563658">_connect</a>,
+<a name="l00794"></a>00794         .resume = <a class="code" href="dwc__otg__pcd__linux_8c.html#86cdfe71d125da339e17e52049fc5ea0">_resume</a>,
+<a name="l00795"></a>00795         .suspend = <a class="code" href="dwc__otg__pcd__linux_8c.html#7f479ecaee0801b55b4f0bd0f36f8b67">_suspend</a>,
+<a name="l00796"></a>00796         .hnp_changed = <a class="code" href="dwc__otg__pcd__linux_8c.html#9e8595e1d36e6b1ffbc27c4862957a08">_hnp_changed</a>,
+<a name="l00797"></a>00797         .reset = <a class="code" href="dwc__otg__pcd__linux_8c.html#208cf9e0227e5f81e015ed3ac5bacec4">_reset</a>,
+<a name="l00798"></a>00798 <span class="preprocessor">#ifdef DWC_UTE_CFI</span>
+<a name="l00799"></a>00799 <span class="preprocessor"></span>        .cfi_setup = _cfi_setup,
+<a name="l00800"></a>00800 <span class="preprocessor">#endif</span>
+<a name="l00801"></a>00801 <span class="preprocessor"></span>};
+<a name="l00802"></a>00802 
+<a name="l00806"></a><a class="code" href="dwc__otg__pcd__linux_8c.html#0ac432e212bd3ffbab9b29b1bf999fe4">00806</a> <span class="keyword">static</span> irqreturn_t <a class="code" href="dwc__otg__pcd__linux_8c.html#0ac432e212bd3ffbab9b29b1bf999fe4">dwc_otg_pcd_irq</a>(<span class="keywordtype">int</span> irq, <span class="keywordtype">void</span> *dev)
+<a name="l00807"></a>00807 {
+<a name="l00808"></a>00808         <a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd = dev;
+<a name="l00809"></a>00809         int32_t retval = IRQ_NONE;
+<a name="l00810"></a>00810 
+<a name="l00811"></a>00811         retval = <a class="code" href="dwc__otg__pcd__if_8h.html#fc60361217d0c5c089f4036d73690689">dwc_otg_pcd_handle_intr</a>(pcd);
+<a name="l00812"></a>00812         <span class="keywordflow">if</span> (retval != 0) {
+<a name="l00813"></a>00813                 <a class="code" href="dwc__otg__driver_8h.html#3af7bafbb69f04a0fd36a27fae7e8497">S3C2410X_CLEAR_EINTPEND</a>();
+<a name="l00814"></a>00814         }
+<a name="l00815"></a>00815         <span class="keywordflow">return</span> IRQ_RETVAL(retval);
+<a name="l00816"></a>00816 }
+<a name="l00817"></a>00817 
+<a name="l00824"></a><a class="code" href="dwc__otg__pcd__linux_8c.html#647f81bc0edc9007af3ff2ba04e884f3">00824</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd__linux_8c.html#647f81bc0edc9007af3ff2ba04e884f3">gadget_add_eps</a>(<span class="keyword">struct</span> <a class="code" href="structgadget__wrapper.html">gadget_wrapper</a> *d)
+<a name="l00825"></a>00825 {
+<a name="l00826"></a>00826         <span class="keyword">static</span> <span class="keyword">const</span> <span class="keywordtype">char</span> *names[] = {
+<a name="l00827"></a>00827 
+<a name="l00828"></a>00828                 <span class="stringliteral">"ep0"</span>,
+<a name="l00829"></a>00829                 <span class="stringliteral">"ep1in"</span>,
+<a name="l00830"></a>00830                 <span class="stringliteral">"ep2in"</span>,
+<a name="l00831"></a>00831                 <span class="stringliteral">"ep3in"</span>,
+<a name="l00832"></a>00832                 <span class="stringliteral">"ep4in"</span>,
+<a name="l00833"></a>00833                 <span class="stringliteral">"ep5in"</span>,
+<a name="l00834"></a>00834                 <span class="stringliteral">"ep6in"</span>,
+<a name="l00835"></a>00835                 <span class="stringliteral">"ep7in"</span>,
+<a name="l00836"></a>00836                 <span class="stringliteral">"ep8in"</span>,
+<a name="l00837"></a>00837                 <span class="stringliteral">"ep9in"</span>,
+<a name="l00838"></a>00838                 <span class="stringliteral">"ep10in"</span>,
+<a name="l00839"></a>00839                 <span class="stringliteral">"ep11in"</span>,
+<a name="l00840"></a>00840                 <span class="stringliteral">"ep12in"</span>,
+<a name="l00841"></a>00841                 <span class="stringliteral">"ep13in"</span>,
+<a name="l00842"></a>00842                 <span class="stringliteral">"ep14in"</span>,
+<a name="l00843"></a>00843                 <span class="stringliteral">"ep15in"</span>,
+<a name="l00844"></a>00844                 <span class="stringliteral">"ep1out"</span>,
+<a name="l00845"></a>00845                 <span class="stringliteral">"ep2out"</span>,
+<a name="l00846"></a>00846                 <span class="stringliteral">"ep3out"</span>,
+<a name="l00847"></a>00847                 <span class="stringliteral">"ep4out"</span>,
+<a name="l00848"></a>00848                 <span class="stringliteral">"ep5out"</span>,
+<a name="l00849"></a>00849                 <span class="stringliteral">"ep6out"</span>,
+<a name="l00850"></a>00850                 <span class="stringliteral">"ep7out"</span>,
+<a name="l00851"></a>00851                 <span class="stringliteral">"ep8out"</span>,
+<a name="l00852"></a>00852                 <span class="stringliteral">"ep9out"</span>,
+<a name="l00853"></a>00853                 <span class="stringliteral">"ep10out"</span>,
+<a name="l00854"></a>00854                 <span class="stringliteral">"ep11out"</span>,
+<a name="l00855"></a>00855                 <span class="stringliteral">"ep12out"</span>,
+<a name="l00856"></a>00856                 <span class="stringliteral">"ep13out"</span>,
+<a name="l00857"></a>00857                 <span class="stringliteral">"ep14out"</span>,
+<a name="l00858"></a>00858                 <span class="stringliteral">"ep15out"</span>
+<a name="l00859"></a>00859         };
+<a name="l00860"></a>00860 
+<a name="l00861"></a>00861         <span class="keywordtype">int</span> i;
+<a name="l00862"></a>00862         <span class="keyword">struct </span>usb_ep *ep;
+<a name="l00863"></a>00863 
+<a name="l00864"></a>00864         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"%s\n"</span>, __func__);
+<a name="l00865"></a>00865 
+<a name="l00866"></a>00866         INIT_LIST_HEAD(&amp;d-&gt;<a class="code" href="structgadget__wrapper.html#a1f30b68c6b42bc728c45c329312d7b1">gadget</a>.ep_list);
+<a name="l00867"></a>00867         d-&gt;<a class="code" href="structgadget__wrapper.html#a1f30b68c6b42bc728c45c329312d7b1">gadget</a>.ep0 = &amp;d-&gt;<a class="code" href="structgadget__wrapper.html#8f28c6610592157ecef50de726919162">ep0</a>;
+<a name="l00868"></a>00868         d-&gt;<a class="code" href="structgadget__wrapper.html#a1f30b68c6b42bc728c45c329312d7b1">gadget</a>.speed = USB_SPEED_UNKNOWN;
+<a name="l00869"></a>00869 
+<a name="l00870"></a>00870         INIT_LIST_HEAD(&amp;d-&gt;<a class="code" href="structgadget__wrapper.html#a1f30b68c6b42bc728c45c329312d7b1">gadget</a>.ep0-&gt;ep_list);
+<a name="l00871"></a>00871 
+<a name="l00875"></a>00875         ep = &amp;d-&gt;<a class="code" href="structgadget__wrapper.html#8f28c6610592157ecef50de726919162">ep0</a>;
+<a name="l00876"></a>00876 
+<a name="l00877"></a>00877         <span class="comment">/* Init the usb_ep structure. */</span>
+<a name="l00878"></a>00878         ep-&gt;name = names[0];
+<a name="l00879"></a>00879         ep-&gt;ops = (<span class="keyword">struct </span>usb_ep_ops *)&amp;<a class="code" href="dwc__otg__pcd__linux_8c.html#8d23bf781df0ba0fb4a0133d08c09dc1">dwc_otg_pcd_ep_ops</a>;
+<a name="l00880"></a>00880 
+<a name="l00885"></a>00885         ep-&gt;maxpacket = <a class="code" href="dwc__otg__pcd__if_8h.html#cf2c48a3393f5ae43e8d88d01c2d204a">MAX_PACKET_SIZE</a>;
+<a name="l00886"></a>00886         <a class="code" href="dwc__otg__pcd_8c.html#b9168f11717bdc672d9a29226779e523">dwc_otg_pcd_ep_enable</a>(d-&gt;<a class="code" href="structgadget__wrapper.html#cdc4a50b5415cc484f77c61a63db3e94">pcd</a>, NULL, ep);
+<a name="l00887"></a>00887 
+<a name="l00888"></a>00888         list_add_tail(&amp;ep-&gt;ep_list, &amp;d-&gt;<a class="code" href="structgadget__wrapper.html#a1f30b68c6b42bc728c45c329312d7b1">gadget</a>.ep_list);
+<a name="l00889"></a>00889 
+<a name="l00894"></a>00894         <span class="keywordflow">for</span> (i = 0; i &lt; 15; i++) {
+<a name="l00895"></a>00895                 ep = &amp;d-&gt;<a class="code" href="structgadget__wrapper.html#9b57a0085afa3decabffc89943866931">in_ep</a>[i];
+<a name="l00896"></a>00896 
+<a name="l00897"></a>00897                 <span class="comment">/* Init the usb_ep structure. */</span>
+<a name="l00898"></a>00898                 ep-&gt;name = names[i + 1];
+<a name="l00899"></a>00899                 ep-&gt;ops = (<span class="keyword">struct</span> usb_ep_ops *)&amp;<a class="code" href="dwc__otg__pcd__linux_8c.html#8d23bf781df0ba0fb4a0133d08c09dc1">dwc_otg_pcd_ep_ops</a>;
+<a name="l00900"></a>00900 
+<a name="l00905"></a>00905                 ep-&gt;maxpacket = <a class="code" href="dwc__otg__pcd__if_8h.html#cf2c48a3393f5ae43e8d88d01c2d204a">MAX_PACKET_SIZE</a>;
+<a name="l00906"></a>00906                 list_add_tail(&amp;ep-&gt;ep_list, &amp;d-&gt;<a class="code" href="structgadget__wrapper.html#a1f30b68c6b42bc728c45c329312d7b1">gadget</a>.ep_list);
+<a name="l00907"></a>00907         }
+<a name="l00908"></a>00908 
+<a name="l00909"></a>00909         <span class="keywordflow">for</span> (i = 0; i &lt; 15; i++) {
+<a name="l00910"></a>00910                 ep = &amp;d-&gt;<a class="code" href="structgadget__wrapper.html#c420e5ba1a1c2d83d62471c423180d3c">out_ep</a>[i];
+<a name="l00911"></a>00911 
+<a name="l00912"></a>00912                 <span class="comment">/* Init the usb_ep structure. */</span>
+<a name="l00913"></a>00913                 ep-&gt;name = names[15 + i + 1];
+<a name="l00914"></a>00914                 ep-&gt;ops = (<span class="keyword">struct</span> usb_ep_ops *)&amp;<a class="code" href="dwc__otg__pcd__linux_8c.html#8d23bf781df0ba0fb4a0133d08c09dc1">dwc_otg_pcd_ep_ops</a>;
+<a name="l00915"></a>00915 
+<a name="l00920"></a>00920                 ep-&gt;maxpacket = <a class="code" href="dwc__otg__pcd__if_8h.html#cf2c48a3393f5ae43e8d88d01c2d204a">MAX_PACKET_SIZE</a>;
+<a name="l00921"></a>00921 
+<a name="l00922"></a>00922                 list_add_tail(&amp;ep-&gt;ep_list, &amp;d-&gt;<a class="code" href="structgadget__wrapper.html#a1f30b68c6b42bc728c45c329312d7b1">gadget</a>.ep_list);
+<a name="l00923"></a>00923         }
+<a name="l00924"></a>00924 
+<a name="l00925"></a>00925         <span class="comment">/* remove ep0 from the list.  There is a ep0 pointer. */</span>
+<a name="l00926"></a>00926         list_del_init(&amp;d-&gt;<a class="code" href="structgadget__wrapper.html#8f28c6610592157ecef50de726919162">ep0</a>.ep_list);
+<a name="l00927"></a>00927 
+<a name="l00928"></a>00928         d-&gt;<a class="code" href="structgadget__wrapper.html#8f28c6610592157ecef50de726919162">ep0</a>.maxpacket = <a class="code" href="dwc__otg__pcd__if_8h.html#8fbbba66f80923843e99def6064a570f">MAX_EP0_SIZE</a>;
+<a name="l00929"></a>00929 }
+<a name="l00930"></a>00930 
+<a name="l00937"></a><a class="code" href="dwc__otg__pcd__linux_8c.html#6cbde69780790137d41fd45558236000">00937</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd__linux_8c.html#6cbde69780790137d41fd45558236000">dwc_otg_pcd_gadget_release</a>(<span class="keyword">struct</span> device *dev)
+<a name="l00938"></a>00938 {
+<a name="l00939"></a>00939         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"%s(%p)\n"</span>, __func__, dev);
+<a name="l00940"></a>00940 }
+<a name="l00941"></a>00941 
+<a name="l00942"></a><a class="code" href="dwc__otg__pcd__linux_8c.html#e0f94c48914d5f911f7623a53c5385a9">00942</a> <span class="keyword">static</span> <span class="keyword">struct </span><a class="code" href="structgadget__wrapper.html">gadget_wrapper</a> *<a class="code" href="dwc__otg__pcd__linux_8c.html#e0f94c48914d5f911f7623a53c5385a9">alloc_wrapper</a>(
+<a name="l00943"></a>00943 #ifdef LM_INTERFACE
+<a name="l00944"></a>00944         <span class="keyword">struct</span> lm_device *_dev
+<a name="l00945"></a>00945 #elif  PCI_INTERFACE
+<a name="l00946"></a>00946         <span class="keyword">struct</span> pci_dev *_dev
+<a name="l00947"></a>00947 #endif
+<a name="l00948"></a>00948         )
+<a name="l00949"></a>00949 {
+<a name="l00950"></a>00950         <span class="keyword">static</span> <span class="keywordtype">char</span> pcd_name[] = <span class="stringliteral">"dwc_otg_pcd"</span>;
+<a name="l00951"></a>00951 <span class="preprocessor">#ifdef LM_INTERFACE</span>
+<a name="l00952"></a>00952 <span class="preprocessor"></span>        <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = lm_get_drvdata(_dev);
+<a name="l00953"></a>00953 <span class="preprocessor">#elif PCI_INTERFACE</span>
+<a name="l00954"></a>00954 <span class="preprocessor"></span>        <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = pci_get_drvdata(_dev);
+<a name="l00955"></a>00955 <span class="preprocessor">#endif</span>
+<a name="l00956"></a>00956 <span class="preprocessor"></span>
+<a name="l00957"></a>00957         <span class="keyword">struct </span><a class="code" href="structgadget__wrapper.html">gadget_wrapper</a> *d;
+<a name="l00958"></a>00958         <span class="keywordtype">int</span> retval;
+<a name="l00959"></a>00959 
+<a name="l00960"></a>00960         d = dwc_alloc(<span class="keyword">sizeof</span>(*d));
+<a name="l00961"></a>00961         <span class="keywordflow">if</span> (d == NULL) {
+<a name="l00962"></a>00962                 <span class="keywordflow">return</span> NULL;
+<a name="l00963"></a>00963         }
+<a name="l00964"></a>00964 
+<a name="l00965"></a>00965         memset(d, 0, <span class="keyword">sizeof</span>(*d));
+<a name="l00966"></a>00966 
+<a name="l00967"></a>00967         d-&gt;gadget.name = pcd_name;
+<a name="l00968"></a>00968         d-&gt;pcd = otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#2a8eefbd03790ea0bbb70e0ac14e4786">pcd</a>;
+<a name="l00969"></a>00969         strcpy(d-&gt;gadget.dev.bus_id, <span class="stringliteral">"gadget"</span>);
+<a name="l00970"></a>00970 
+<a name="l00971"></a>00971         d-&gt;gadget.dev.parent = &amp;_dev-&gt;dev;
+<a name="l00972"></a>00972         d-&gt;gadget.dev.release = <a class="code" href="dwc__otg__pcd__linux_8c.html#6cbde69780790137d41fd45558236000">dwc_otg_pcd_gadget_release</a>;
+<a name="l00973"></a>00973         d-&gt;gadget.ops = &amp;<a class="code" href="dwc__otg__pcd__linux_8c.html#592a942ef237021f608d03dd8b57bc54">dwc_otg_pcd_ops</a>;
+<a name="l00974"></a>00974         d-&gt;gadget.is_dualspeed = <a class="code" href="dwc__otg__pcd_8c.html#ae9b15825812485a06be318858e0316a">dwc_otg_pcd_is_dualspeed</a>(otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#2a8eefbd03790ea0bbb70e0ac14e4786">pcd</a>);
+<a name="l00975"></a>00975         d-&gt;gadget.is_otg = <a class="code" href="dwc__otg__pcd_8c.html#07169d2569c7e071fc99045fd435f2c6">dwc_otg_pcd_is_otg</a>(otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#2a8eefbd03790ea0bbb70e0ac14e4786">pcd</a>);
+<a name="l00976"></a>00976 
+<a name="l00977"></a>00977         d-&gt;driver = 0;
+<a name="l00978"></a>00978         <span class="comment">/* Register the gadget device */</span>
+<a name="l00979"></a>00979         retval = device_register(&amp;d-&gt;gadget.dev);
+<a name="l00980"></a>00980         <span class="keywordflow">if</span> (retval != 0) {
+<a name="l00981"></a>00981                 DWC_ERROR(<span class="stringliteral">"device_register failed\n"</span>);
+<a name="l00982"></a>00982                 dwc_free(d);
+<a name="l00983"></a>00983                 <span class="keywordflow">return</span> NULL;
+<a name="l00984"></a>00984         }
+<a name="l00985"></a>00985 
+<a name="l00986"></a>00986         <span class="keywordflow">return</span> d;
+<a name="l00987"></a>00987 }
+<a name="l00988"></a>00988 
+<a name="l00989"></a><a class="code" href="dwc__otg__pcd__linux_8c.html#8893dc41eae659439546d874c6e9977f">00989</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__pcd__linux_8c.html#8893dc41eae659439546d874c6e9977f">free_wrapper</a>(<span class="keyword">struct</span> <a class="code" href="structgadget__wrapper.html">gadget_wrapper</a> *d)
+<a name="l00990"></a>00990 {
+<a name="l00991"></a>00991         <span class="keywordflow">if</span> (d-&gt;<a class="code" href="structgadget__wrapper.html#8997a3c90f9eb0a8f40f5762ffc5ce60">driver</a>) {
+<a name="l00992"></a>00992                 <span class="comment">/* should have been done already by driver model core */</span>
+<a name="l00993"></a>00993                 DWC_WARN(<span class="stringliteral">"driver '%s' is still registered\n"</span>,
+<a name="l00994"></a>00994                          d-&gt;<a class="code" href="structgadget__wrapper.html#8997a3c90f9eb0a8f40f5762ffc5ce60">driver</a>-&gt;driver.name);
+<a name="l00995"></a>00995                 <a class="code" href="dwc__otg__pcd__linux_8c.html#fa4a24d0806fbb6e3135d27d24a6a00d">usb_gadget_unregister_driver</a>(d-&gt;<a class="code" href="structgadget__wrapper.html#8997a3c90f9eb0a8f40f5762ffc5ce60">driver</a>);
+<a name="l00996"></a>00996         }
+<a name="l00997"></a>00997 
+<a name="l00998"></a>00998         device_unregister(&amp;d-&gt;<a class="code" href="structgadget__wrapper.html#a1f30b68c6b42bc728c45c329312d7b1">gadget</a>.dev);
+<a name="l00999"></a>00999         dwc_free(d);
+<a name="l01000"></a>01000 }
+<a name="l01001"></a>01001 
+<a name="l01006"></a><a class="code" href="dwc__otg__pcd__linux_8c.html#9dbc565a7942db0adbf1ec341db22901">01006</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__driver_8c.html#9dbc565a7942db0adbf1ec341db22901">pcd_init</a>(
+<a name="l01007"></a>01007 #ifdef LM_INTERFACE
+<a name="l01008"></a>01008         <span class="keyword">struct</span> lm_device *_dev
+<a name="l01009"></a>01009 #elif  PCI_INTERFACE
+<a name="l01010"></a>01010         <span class="keyword">struct</span> pci_dev *_dev
+<a name="l01011"></a>01011 #endif
+<a name="l01012"></a>01012         )
+<a name="l01013"></a>01013 
+<a name="l01014"></a>01014 {
+<a name="l01015"></a>01015 <span class="preprocessor">#ifdef LM_INTERFACE</span>
+<a name="l01016"></a>01016 <span class="preprocessor"></span>        <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = lm_get_drvdata(_dev);
+<a name="l01017"></a>01017 <span class="preprocessor">#elif  PCI_INTERFACE</span>
+<a name="l01018"></a>01018 <span class="preprocessor"></span>        <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = pci_get_drvdata(_dev);
+<a name="l01019"></a>01019 <span class="preprocessor">#endif</span>
+<a name="l01020"></a>01020 <span class="preprocessor"></span>
+<a name="l01021"></a>01021         <span class="keywordtype">int</span> retval = 0;
+<a name="l01022"></a>01022 
+<a name="l01023"></a>01023         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"%s(%p)\n"</span>, __func__, _dev);
+<a name="l01024"></a>01024 
+<a name="l01025"></a>01025         otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#2a8eefbd03790ea0bbb70e0ac14e4786">pcd</a> = <a class="code" href="dwc__otg__pcd_8c.html#fc3d8c56afa93b474180cc1eb8624ab8">dwc_otg_pcd_init</a>(otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#4cc7c9f6e473072c2ed0a5e6adb25ebe">core_if</a>);
+<a name="l01026"></a>01026 
+<a name="l01027"></a>01027         <span class="keywordflow">if</span> (!otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#2a8eefbd03790ea0bbb70e0ac14e4786">pcd</a>) {
+<a name="l01028"></a>01028                 DWC_ERROR(<span class="stringliteral">"dwc_otg_pcd_init failed\n"</span>);
+<a name="l01029"></a>01029                 <span class="keywordflow">return</span> -ENOMEM;
+<a name="l01030"></a>01030         }
+<a name="l01031"></a>01031 
+<a name="l01032"></a>01032         <a class="code" href="structgadget__wrapper.html">gadget_wrapper</a> = <a class="code" href="dwc__otg__pcd__linux_8c.html#e0f94c48914d5f911f7623a53c5385a9">alloc_wrapper</a>(_dev);
+<a name="l01033"></a>01033 
+<a name="l01034"></a>01034         <span class="comment">/*</span>
+<a name="l01035"></a>01035 <span class="comment">         * Initialize EP structures</span>
+<a name="l01036"></a>01036 <span class="comment">         */</span>
+<a name="l01037"></a>01037         <a class="code" href="dwc__otg__pcd__linux_8c.html#647f81bc0edc9007af3ff2ba04e884f3">gadget_add_eps</a>(<a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>);
+<a name="l01038"></a>01038 
+<a name="l01039"></a>01039         <span class="comment">/*</span>
+<a name="l01040"></a>01040 <span class="comment">         * Setup interupt handler</span>
+<a name="l01041"></a>01041 <span class="comment">         */</span>
+<a name="l01042"></a>01042         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#2bf62a567355d1ea38814714bd7b57ec">DBG_ANY</a>, <span class="stringliteral">"registering handler for irq%d\n"</span>, _dev-&gt;irq);
+<a name="l01043"></a>01043         retval = request_irq(_dev-&gt;irq, <a class="code" href="dwc__otg__pcd__linux_8c.html#0ac432e212bd3ffbab9b29b1bf999fe4">dwc_otg_pcd_irq</a>,
+<a name="l01044"></a>01044                              SA_SHIRQ, <a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;gadget.name,
+<a name="l01045"></a>01045                              otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#2a8eefbd03790ea0bbb70e0ac14e4786">pcd</a>);
+<a name="l01046"></a>01046         <span class="keywordflow">if</span> (retval != 0) {
+<a name="l01047"></a>01047                 DWC_ERROR(<span class="stringliteral">"request of irq%d failed\n"</span>, _dev-&gt;irq);
+<a name="l01048"></a>01048                 <a class="code" href="dwc__otg__pcd__linux_8c.html#8893dc41eae659439546d874c6e9977f">free_wrapper</a>(<a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>);
+<a name="l01049"></a>01049                 <span class="keywordflow">return</span> -EBUSY;
+<a name="l01050"></a>01050         }
+<a name="l01051"></a>01051 
+<a name="l01052"></a>01052         <a class="code" href="dwc__otg__pcd_8c.html#187209231d66bc200444c0d52331d276">dwc_otg_pcd_start</a>(<a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;pcd, &amp;<a class="code" href="dwc__otg__pcd__linux_8c.html#9ce9b5e49c60906c189bee157dd68acd">fops</a>);
+<a name="l01053"></a>01053 
+<a name="l01054"></a>01054         <span class="keywordflow">return</span> retval;
+<a name="l01055"></a>01055 }
+<a name="l01056"></a>01056 
+<a name="l01060"></a><a class="code" href="dwc__otg__pcd__linux_8c.html#03129ea5120095af86c98558792aeae8">01060</a> <span class="keywordtype">void</span> <a class="code" href="dwc__otg__driver_8c.html#7960b8e2c02d9ab89b65cb01ba08658b">pcd_remove</a>(
+<a name="l01061"></a>01061 #ifdef LM_INTERFACE
+<a name="l01062"></a>01062         <span class="keyword">struct</span> lm_device *_dev
+<a name="l01063"></a>01063 #elif  PCI_INTERFACE
+<a name="l01064"></a>01064         <span class="keyword">struct</span> pci_dev *_dev
+<a name="l01065"></a>01065 #endif
+<a name="l01066"></a>01066         )
+<a name="l01067"></a>01067 {
+<a name="l01068"></a>01068 <span class="preprocessor">#ifdef LM_INTERFACE</span>
+<a name="l01069"></a>01069 <span class="preprocessor"></span>        <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = lm_get_drvdata(_dev);
+<a name="l01070"></a>01070 <span class="preprocessor">#elif  PCI_INTERFACE</span>
+<a name="l01071"></a>01071 <span class="preprocessor"></span>        <a class="code" href="structdwc__otg__device.html">dwc_otg_device_t</a> *otg_dev = pci_get_drvdata(_dev);
+<a name="l01072"></a>01072 <span class="preprocessor">#endif</span>
+<a name="l01073"></a>01073 <span class="preprocessor"></span>        <a class="code" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *<a class="code" href="structgadget__wrapper.html#cdc4a50b5415cc484f77c61a63db3e94">pcd</a> = otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#2a8eefbd03790ea0bbb70e0ac14e4786">pcd</a>;
+<a name="l01074"></a>01074 
+<a name="l01075"></a>01075         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"%s(%p)\n"</span>, __func__, _dev);
+<a name="l01076"></a>01076 
+<a name="l01077"></a>01077         <span class="comment">/*</span>
+<a name="l01078"></a>01078 <span class="comment">         * Free the IRQ</span>
+<a name="l01079"></a>01079 <span class="comment">         */</span>
+<a name="l01080"></a>01080         free_irq(_dev-&gt;irq, <a class="code" href="structgadget__wrapper.html#cdc4a50b5415cc484f77c61a63db3e94">pcd</a>);
+<a name="l01081"></a>01081         <a class="code" href="dwc__otg__pcd_8c.html#aaab1535dacd5e947c1f9343d9b3ddf5">dwc_otg_pcd_remove</a>(otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#2a8eefbd03790ea0bbb70e0ac14e4786">pcd</a>);
+<a name="l01082"></a>01082         <a class="code" href="dwc__otg__pcd__linux_8c.html#8893dc41eae659439546d874c6e9977f">free_wrapper</a>(<a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>);
+<a name="l01083"></a>01083         otg_dev-&gt;<a class="code" href="structdwc__otg__device.html#2a8eefbd03790ea0bbb70e0ac14e4786">pcd</a> = 0;
+<a name="l01084"></a>01084 }
+<a name="l01085"></a>01085 
+<a name="l01096"></a><a class="code" href="dwc__otg__pcd__linux_8c.html#8c1ba129028b3b16909973eb30b85d2c">01096</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__pcd__linux_8c.html#8c1ba129028b3b16909973eb30b85d2c">usb_gadget_register_driver</a>(<span class="keyword">struct</span> usb_gadget_driver *<a class="code" href="structgadget__wrapper.html#8997a3c90f9eb0a8f40f5762ffc5ce60">driver</a>)
+<a name="l01097"></a>01097 {
+<a name="l01098"></a>01098         <span class="keywordtype">int</span> retval;
+<a name="l01099"></a>01099 
+<a name="l01100"></a>01100         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"registering gadget driver '%s'\n"</span>,
+<a name="l01101"></a>01101                     driver-&gt;driver.name);
+<a name="l01102"></a>01102 
+<a name="l01103"></a>01103         <span class="keywordflow">if</span> (!driver || driver-&gt;speed == USB_SPEED_UNKNOWN ||
+<a name="l01104"></a>01104             !driver-&gt;bind ||
+<a name="l01105"></a>01105             !driver-&gt;unbind || !driver-&gt;disconnect || !driver-&gt;setup) {
+<a name="l01106"></a>01106                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"EINVAL\n"</span>);
+<a name="l01107"></a>01107                 <span class="keywordflow">return</span> -EINVAL;
+<a name="l01108"></a>01108         }
+<a name="l01109"></a>01109         <span class="keywordflow">if</span> (<a class="code" href="structgadget__wrapper.html">gadget_wrapper</a> == 0) {
+<a name="l01110"></a>01110                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"ENODEV\n"</span>);
+<a name="l01111"></a>01111                 <span class="keywordflow">return</span> -ENODEV;
+<a name="l01112"></a>01112         }
+<a name="l01113"></a>01113         <span class="keywordflow">if</span> (<a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;driver != 0) {
+<a name="l01114"></a>01114                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">DBG_PCDV</a>, <span class="stringliteral">"EBUSY (%p)\n"</span>, <a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;driver);
+<a name="l01115"></a>01115                 <span class="keywordflow">return</span> -EBUSY;
+<a name="l01116"></a>01116         }
+<a name="l01117"></a>01117 
+<a name="l01118"></a>01118         <span class="comment">/* hook up the driver */</span>
+<a name="l01119"></a>01119         <a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;driver = driver;
+<a name="l01120"></a>01120         <a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;gadget.dev.driver = &amp;driver-&gt;driver;
+<a name="l01121"></a>01121 
+<a name="l01122"></a>01122         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">DBG_PCD</a>, <span class="stringliteral">"bind to driver %s\n"</span>, driver-&gt;driver.name);
+<a name="l01123"></a>01123         retval = driver-&gt;bind(&amp;<a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;gadget);
+<a name="l01124"></a>01124         <span class="keywordflow">if</span> (retval) {
+<a name="l01125"></a>01125                 DWC_ERROR(<span class="stringliteral">"bind to driver %s --&gt; error %d\n"</span>,
+<a name="l01126"></a>01126                           driver-&gt;driver.name, retval);
+<a name="l01127"></a>01127                 <a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;driver = 0;
+<a name="l01128"></a>01128                 <a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;gadget.dev.driver = 0;
+<a name="l01129"></a>01129                 <span class="keywordflow">return</span> retval;
+<a name="l01130"></a>01130         }
+<a name="l01131"></a>01131         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#2bf62a567355d1ea38814714bd7b57ec">DBG_ANY</a>, <span class="stringliteral">"registered gadget driver '%s'\n"</span>,
+<a name="l01132"></a>01132                     driver-&gt;driver.name);
+<a name="l01133"></a>01133         <span class="keywordflow">return</span> 0;
+<a name="l01134"></a>01134 }
+<a name="l01135"></a>01135 
+<a name="l01136"></a>01136 EXPORT_SYMBOL(<a class="code" href="dwc__otg__pcd__linux_8c.html#8c1ba129028b3b16909973eb30b85d2c">usb_gadget_register_driver</a>);
+<a name="l01137"></a>01137 
+<a name="l01143"></a><a class="code" href="dwc__otg__pcd__linux_8c.html#fa4a24d0806fbb6e3135d27d24a6a00d">01143</a> <span class="keywordtype">int</span> <a class="code" href="dwc__otg__pcd__linux_8c.html#fa4a24d0806fbb6e3135d27d24a6a00d">usb_gadget_unregister_driver</a>(<span class="keyword">struct</span> usb_gadget_driver *<a class="code" href="structgadget__wrapper.html#8997a3c90f9eb0a8f40f5762ffc5ce60">driver</a>)
+<a name="l01144"></a>01144 {
+<a name="l01145"></a>01145         <span class="comment">//DWC_DEBUGPL(DBG_PCDV,"%s(%p)\n", __func__, _driver);</span>
+<a name="l01146"></a>01146 
+<a name="l01147"></a>01147         <span class="keywordflow">if</span> (<a class="code" href="structgadget__wrapper.html">gadget_wrapper</a> == 0) {
+<a name="l01148"></a>01148                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#2bf62a567355d1ea38814714bd7b57ec">DBG_ANY</a>, <span class="stringliteral">"%s Return(%d): s_pcd==0\n"</span>, __func__,
+<a name="l01149"></a>01149                             -ENODEV);
+<a name="l01150"></a>01150                 <span class="keywordflow">return</span> -ENODEV;
+<a name="l01151"></a>01151         }
+<a name="l01152"></a>01152         <span class="keywordflow">if</span> (driver == 0 || driver != <a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;driver) {
+<a name="l01153"></a>01153                 <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#2bf62a567355d1ea38814714bd7b57ec">DBG_ANY</a>, <span class="stringliteral">"%s Return(%d): driver?\n"</span>, __func__,
+<a name="l01154"></a>01154                             -EINVAL);
+<a name="l01155"></a>01155                 <span class="keywordflow">return</span> -EINVAL;
+<a name="l01156"></a>01156         }
+<a name="l01157"></a>01157 
+<a name="l01158"></a>01158         driver-&gt;unbind(&amp;<a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;gadget);
+<a name="l01159"></a>01159         <a class="code" href="structgadget__wrapper.html">gadget_wrapper</a>-&gt;driver = 0;
+<a name="l01160"></a>01160 
+<a name="l01161"></a>01161         <a class="code" href="dwc__otg__dbg_8h.html#ed38f5a57cb756e97a17c0926cc9a10e">DWC_DEBUGPL</a>(<a class="code" href="dwc__otg__dbg_8h.html#2bf62a567355d1ea38814714bd7b57ec">DBG_ANY</a>, <span class="stringliteral">"unregistered driver '%s'\n"</span>, driver-&gt;driver.name);
+<a name="l01162"></a>01162         <span class="keywordflow">return</span> 0;
+<a name="l01163"></a>01163 }
+<a name="l01164"></a>01164 
+<a name="l01165"></a>01165 EXPORT_SYMBOL(<a class="code" href="dwc__otg__pcd__linux_8c.html#fa4a24d0806fbb6e3135d27d24a6a00d">usb_gadget_unregister_driver</a>);
+<a name="l01166"></a>01166 
+<a name="l01167"></a>01167 <span class="preprocessor">#endif                          </span><span class="comment">/* DWC_HOST_ONLY */</span>
+</pre></div><hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__linux_8c.html b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__linux_8c.html
new file mode 100644
index 000000000000..26ee9dffb0ee
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__linux_8c.html
@@ -0,0 +1,796 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd_linux.c File Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<h1>dwc_otg_pcd_linux.c File Reference</h1>This file implements the Peripheral Controller Driver. <a href="#_details">More...</a>
+<p>
+<code>#include &lt;linux/kernel.h&gt;</code><br>
+<code>#include &lt;linux/module.h&gt;</code><br>
+<code>#include &lt;linux/moduleparam.h&gt;</code><br>
+<code>#include &lt;linux/init.h&gt;</code><br>
+<code>#include &lt;linux/device.h&gt;</code><br>
+<code>#include &lt;linux/errno.h&gt;</code><br>
+<code>#include &lt;linux/list.h&gt;</code><br>
+<code>#include &lt;linux/interrupt.h&gt;</code><br>
+<code>#include &lt;linux/string.h&gt;</code><br>
+<code>#include &lt;linux/dma-mapping.h&gt;</code><br>
+<code>#include &lt;linux/version.h&gt;</code><br>
+<code>#include &lt;asm/io.h&gt;</code><br>
+<code>#include &lt;linux/usb_ch9.h&gt;</code><br>
+<code>#include &lt;linux/usb_gadget.h&gt;</code><br>
+<code>#include &quot;<a class="el" href="dwc__otg__pcd__if_8h-source.html">dwc_otg_pcd_if.h</a>&quot;</code><br>
+<code>#include &quot;<a class="el" href="dwc__otg__driver_8h-source.html">dwc_otg_driver.h</a>&quot;</code><br>
+<code>#include &quot;<a class="el" href="dwc__otg__dbg_8h-source.html">dwc_otg_dbg.h</a>&quot;</code><br>
+
+<p>
+<a href="dwc__otg__pcd__linux_8c-source.html">Go to the source code of this file.</a><table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Structures</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structgadget__wrapper.html">gadget_wrapper</a></td></tr>
+
+<tr><td colspan="2"><br><h2>Functions</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="eb12bc37beddd62e97bf95f1459c646c"></a><!-- doxytag: member="dwc_otg_pcd_linux.c::dump_msg" ref="eb12bc37beddd62e97bf95f1459c646c" args="(const u8 *buf, unsigned int length)" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><b>dump_msg</b> (const u8 *buf, unsigned int length)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__linux_8c.html#9761890d7f741f9421d82254c9846f31">ep_enable</a> (struct usb_ep *usb_ep, const struct usb_endpoint_descriptor *ep_desc)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function is called by the Gadget Driver for each EP to be configured for the current configuration (SET_CONFIGURATION).  <a href="#9761890d7f741f9421d82254c9846f31"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__linux_8c.html#1708514cb93c5da43a8f634de1c0f5e7">ep_disable</a> (struct usb_ep *usb_ep)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function is called when an EP is disabled due to disconnect or change in configuration.  <a href="#1708514cb93c5da43a8f634de1c0f5e7"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static struct usb_request *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__linux_8c.html#e5a3f75b9a06a4707d1d0ec5957daa7d">dwc_otg_pcd_alloc_request</a> (struct usb_ep *ep, gfp_t gfp_flags)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function allocates a request object to use with the specified endpoint.  <a href="#e5a3f75b9a06a4707d1d0ec5957daa7d"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__linux_8c.html#348338816bfc0e711c4b875997ed00d9">dwc_otg_pcd_free_request</a> (struct usb_ep *ep, struct usb_request *req)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function frees a request object.  <a href="#348338816bfc0e711c4b875997ed00d9"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static void *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__linux_8c.html#295957efef868247c889aa3f5050af00">dwc_otg_pcd_alloc_buffer</a> (struct usb_ep *usb_ep, unsigned bytes, dma_addr_t *dma, gfp_t gfp_flags)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function allocates an I/O buffer to be used for a transfer to/from the specified endpoint.  <a href="#295957efef868247c889aa3f5050af00"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__linux_8c.html#675a197388a82da27f74c11ffdbf874b">dwc_otg_pcd_free_buffer</a> (struct usb_ep *usb_ep, void *buf, dma_addr_t dma, unsigned bytes)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function frees an I/O buffer that was allocated by alloc_buffer.  <a href="#675a197388a82da27f74c11ffdbf874b"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__linux_8c.html#f97bea831037135af73c3c202e3e01dc">ep_queue</a> (struct usb_ep *usb_ep, struct usb_request *usb_req, gfp_t gfp_flags)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function is used to submit an I/O Request to an EP.  <a href="#f97bea831037135af73c3c202e3e01dc"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e2e4913a926acc55f4e57c3ff8f97c08"></a><!-- doxytag: member="dwc_otg_pcd_linux.c::ep_dequeue" ref="e2e4913a926acc55f4e57c3ff8f97c08" args="(struct usb_ep *usb_ep, struct usb_request *usb_req)" -->
+static int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__linux_8c.html#e2e4913a926acc55f4e57c3ff8f97c08">ep_dequeue</a> (struct usb_ep *usb_ep, struct usb_request *usb_req)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function cancels an I/O request from an EP. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__linux_8c.html#8ee99e0e68c8e50e94c242805b158cb2">ep_halt</a> (struct usb_ep *usb_ep, int value)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">usb_ep_set_halt stalls an endpoint.  <a href="#8ee99e0e68c8e50e94c242805b158cb2"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__linux_8c.html#eb3df484c8c344613a2a9b23e24036a8">iso_ep_start</a> (struct usb_ep *usb_ep, struct usb_iso_request *req, gfp_t gfp_flags)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function is used to submit an ISOC Transfer Request to an EP.  <a href="#eb3df484c8c344613a2a9b23e24036a8"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="cecdcaa060d30ac09414419545a5d1c6"></a><!-- doxytag: member="dwc_otg_pcd_linux.c::iso_ep_stop" ref="cecdcaa060d30ac09414419545a5d1c6" args="(struct usb_ep *usb_ep, struct usb_iso_request *req)" -->
+static int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__linux_8c.html#cecdcaa060d30ac09414419545a5d1c6">iso_ep_stop</a> (struct usb_ep *usb_ep, struct usb_iso_request *req)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function stops ISO EP Periodic Data Transfer. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="94fd50b5e9d41d1d38a503d819fc07c4"></a><!-- doxytag: member="dwc_otg_pcd_linux.c::alloc_iso_request" ref="94fd50b5e9d41d1d38a503d819fc07c4" args="(struct usb_ep *ep, int packets, gfp_t gfp_flags)" -->
+static struct usb_iso_request *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__linux_8c.html#94fd50b5e9d41d1d38a503d819fc07c4">alloc_iso_request</a> (struct usb_ep *ep, int packets, gfp_t gfp_flags)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="a9a7bc869bc7f3d05804059f3277d11a"></a><!-- doxytag: member="dwc_otg_pcd_linux.c::free_iso_request" ref="a9a7bc869bc7f3d05804059f3277d11a" args="(struct usb_ep *ep, struct usb_iso_request *req)" -->
+static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__linux_8c.html#a9a7bc869bc7f3d05804059f3277d11a">free_iso_request</a> (struct usb_ep *ep, struct usb_iso_request *req)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7af23be44d3ad24c67cd1e22579dd90e"></a><!-- doxytag: member="dwc_otg_pcd_linux.c::get_frame_number" ref="7af23be44d3ad24c67cd1e22579dd90e" args="(struct usb_gadget *gadget)" -->
+static int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__linux_8c.html#7af23be44d3ad24c67cd1e22579dd90e">get_frame_number</a> (struct usb_gadget *gadget)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Gets the USB Frame number of the last SOF. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__linux_8c.html#6a6034564b7cc6d8cebfbe02a944cd2c">wakeup</a> (struct usb_gadget *gadget)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Initiates Session Request Protocol (SRP) to wakeup the host if no session is in progress.  <a href="#6a6034564b7cc6d8cebfbe02a944cd2c"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="4a1481839b3d869d882f984a6c6ed9e5"></a><!-- doxytag: member="dwc_otg_pcd_linux.c::_setup" ref="4a1481839b3d869d882f984a6c6ed9e5" args="(dwc_otg_pcd_t *pcd, uint8_t *bytes)" -->
+static int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__linux_8c.html#4a1481839b3d869d882f984a6c6ed9e5">_setup</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, uint8_t *bytes)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="737e47386e05da8cf6cbf85a289f5454"></a><!-- doxytag: member="dwc_otg_pcd_linux.c::_isoc_complete" ref="737e47386e05da8cf6cbf85a289f5454" args="(dwc_otg_pcd_t *pcd, void *ep_handle, void *req_handle, int proc_buf_num)" -->
+static int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__linux_8c.html#737e47386e05da8cf6cbf85a289f5454">_isoc_complete</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, void *ep_handle, void *req_handle, int proc_buf_num)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e1d629bc692aa1e42584459867b1aeaa"></a><!-- doxytag: member="dwc_otg_pcd_linux.c::_complete" ref="e1d629bc692aa1e42584459867b1aeaa" args="(dwc_otg_pcd_t *pcd, void *ep_handle, void *req_handle, int32_t status, uint32_t actual)" -->
+static int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__linux_8c.html#e1d629bc692aa1e42584459867b1aeaa">_complete</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, void *ep_handle, void *req_handle, int32_t status, uint32_t actual)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c7c1c4f8fe8e62f1d9e6f75de5563658"></a><!-- doxytag: member="dwc_otg_pcd_linux.c::_connect" ref="c7c1c4f8fe8e62f1d9e6f75de5563658" args="(dwc_otg_pcd_t *pcd, int speed)" -->
+static int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__linux_8c.html#c7c1c4f8fe8e62f1d9e6f75de5563658">_connect</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd, int speed)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="682f9829330d06521a5d4c00702e4580"></a><!-- doxytag: member="dwc_otg_pcd_linux.c::_disconnect" ref="682f9829330d06521a5d4c00702e4580" args="(dwc_otg_pcd_t *pcd)" -->
+static int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__linux_8c.html#682f9829330d06521a5d4c00702e4580">_disconnect</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="86cdfe71d125da339e17e52049fc5ea0"></a><!-- doxytag: member="dwc_otg_pcd_linux.c::_resume" ref="86cdfe71d125da339e17e52049fc5ea0" args="(dwc_otg_pcd_t *pcd)" -->
+static int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__linux_8c.html#86cdfe71d125da339e17e52049fc5ea0">_resume</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7f479ecaee0801b55b4f0bd0f36f8b67"></a><!-- doxytag: member="dwc_otg_pcd_linux.c::_suspend" ref="7f479ecaee0801b55b4f0bd0f36f8b67" args="(dwc_otg_pcd_t *pcd)" -->
+static int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__linux_8c.html#7f479ecaee0801b55b4f0bd0f36f8b67">_suspend</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="9e8595e1d36e6b1ffbc27c4862957a08"></a><!-- doxytag: member="dwc_otg_pcd_linux.c::_hnp_changed" ref="9e8595e1d36e6b1ffbc27c4862957a08" args="(dwc_otg_pcd_t *pcd)" -->
+static int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__linux_8c.html#9e8595e1d36e6b1ffbc27c4862957a08">_hnp_changed</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function updates the otg values in the gadget structure. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="208cf9e0227e5f81e015ed3ac5bacec4"></a><!-- doxytag: member="dwc_otg_pcd_linux.c::_reset" ref="208cf9e0227e5f81e015ed3ac5bacec4" args="(dwc_otg_pcd_t *pcd)" -->
+static int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__linux_8c.html#208cf9e0227e5f81e015ed3ac5bacec4">_reset</a> (<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *pcd)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="0ac432e212bd3ffbab9b29b1bf999fe4"></a><!-- doxytag: member="dwc_otg_pcd_linux.c::dwc_otg_pcd_irq" ref="0ac432e212bd3ffbab9b29b1bf999fe4" args="(int irq, void *dev)" -->
+static irqreturn_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__linux_8c.html#0ac432e212bd3ffbab9b29b1bf999fe4">dwc_otg_pcd_irq</a> (int irq, void *dev)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function is the top level PCD interrupt handler. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__linux_8c.html#647f81bc0edc9007af3ff2ba04e884f3">gadget_add_eps</a> (struct <a class="el" href="structgadget__wrapper.html">gadget_wrapper</a> *d)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function initialized the usb_ep structures to there default state.  <a href="#647f81bc0edc9007af3ff2ba04e884f3"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__linux_8c.html#6cbde69780790137d41fd45558236000">dwc_otg_pcd_gadget_release</a> (struct device *dev)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function releases the Gadget device.  <a href="#6cbde69780790137d41fd45558236000"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e0f94c48914d5f911f7623a53c5385a9"></a><!-- doxytag: member="dwc_otg_pcd_linux.c::alloc_wrapper" ref="e0f94c48914d5f911f7623a53c5385a9" args="()" -->
+static struct <a class="el" href="structgadget__wrapper.html">gadget_wrapper</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__linux_8c.html#e0f94c48914d5f911f7623a53c5385a9">alloc_wrapper</a> ()</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="8893dc41eae659439546d874c6e9977f"></a><!-- doxytag: member="dwc_otg_pcd_linux.c::free_wrapper" ref="8893dc41eae659439546d874c6e9977f" args="(struct gadget_wrapper *d)" -->
+static void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__linux_8c.html#8893dc41eae659439546d874c6e9977f">free_wrapper</a> (struct <a class="el" href="structgadget__wrapper.html">gadget_wrapper</a> *d)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="9dbc565a7942db0adbf1ec341db22901"></a><!-- doxytag: member="dwc_otg_pcd_linux.c::pcd_init" ref="9dbc565a7942db0adbf1ec341db22901" args="()" -->
+int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__linux_8c.html#9dbc565a7942db0adbf1ec341db22901">pcd_init</a> ()</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function initialized the PCD portion of the driver. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="03129ea5120095af86c98558792aeae8"></a><!-- doxytag: member="dwc_otg_pcd_linux.c::pcd_remove" ref="03129ea5120095af86c98558792aeae8" args="()" -->
+void&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__linux_8c.html#03129ea5120095af86c98558792aeae8">pcd_remove</a> ()</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Cleanup the PCD. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__linux_8c.html#8c1ba129028b3b16909973eb30b85d2c">usb_gadget_register_driver</a> (struct usb_gadget_driver *driver)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function registers a gadget driver with the PCD.  <a href="#8c1ba129028b3b16909973eb30b85d2c"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="91e3d41e4501e626f0fa1418c7c2c1b7"></a><!-- doxytag: member="dwc_otg_pcd_linux.c::EXPORT_SYMBOL" ref="91e3d41e4501e626f0fa1418c7c2c1b7" args="(usb_gadget_register_driver)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>EXPORT_SYMBOL</b> (usb_gadget_register_driver)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__linux_8c.html#fa4a24d0806fbb6e3135d27d24a6a00d">usb_gadget_unregister_driver</a> (struct usb_gadget_driver *driver)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This function unregisters a gadget driver.  <a href="#fa4a24d0806fbb6e3135d27d24a6a00d"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="0b678ae7db0add99e06907852056838f"></a><!-- doxytag: member="dwc_otg_pcd_linux.c::EXPORT_SYMBOL" ref="0b678ae7db0add99e06907852056838f" args="(usb_gadget_unregister_driver)" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>EXPORT_SYMBOL</b> (usb_gadget_unregister_driver)</td></tr>
+
+<tr><td colspan="2"><br><h2>Variables</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static struct usb_isoc_ep_ops&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__linux_8c.html#8d23bf781df0ba0fb4a0133d08c09dc1">dwc_otg_pcd_ep_ops</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static struct usb_gadget_ops&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__linux_8c.html#592a942ef237021f608d03dd8b57bc54">dwc_otg_pcd_ops</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">static struct <a class="el" href="structdwc__otg__pcd__function__ops.html">dwc_otg_pcd_function_ops</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__pcd__linux_8c.html#9ce9b5e49c60906c189bee157dd68acd">fops</a></td></tr>
+
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This file implements the Peripheral Controller Driver. 
+<p>
+The Peripheral Controller Driver (PCD) is responsible for translating requests from the Function Driver into the appropriate actions on the DWC_otg controller. It isolates the Function Driver from the specifics of the controller by providing an API to the Function Driver.<p>
+The Peripheral Controller Driver for Linux will implement the Gadget API, so that the existing Gadget drivers can be used. (Gadget Driver is the Linux terminology for a Function Driver.)<p>
+The Linux Gadget API is defined in the header file <code>&lt;linux/usb_gadget.h&gt;</code>. The USB EP operations API is defined in the structure <code>usb_ep_ops</code> and the USB Controller API is defined in the structure <code>usb_gadget_ops</code>. 
+<p>
+Definition in file <a class="el" href="dwc__otg__pcd__linux_8c-source.html">dwc_otg_pcd_linux.c</a>.<hr><h2>Function Documentation</h2>
+<a class="anchor" name="9761890d7f741f9421d82254c9846f31"></a><!-- doxytag: member="dwc_otg_pcd_linux.c::ep_enable" ref="9761890d7f741f9421d82254c9846f31" args="(struct usb_ep *usb_ep, const struct usb_endpoint_descriptor *ep_desc)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static int ep_enable           </td>
+          <td>(</td>
+          <td class="paramtype">struct usb_ep *&nbsp;</td>
+          <td class="paramname"> <em>usb_ep</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">const struct usb_endpoint_descriptor *&nbsp;</td>
+          <td class="paramname"> <em>ep_desc</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function is called by the Gadget Driver for each EP to be configured for the current configuration (SET_CONFIGURATION). 
+<p>
+This function initializes the dwc_otg_ep_t data structure, and then calls dwc_otg_ep_activate. 
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__linux_8c-source.html#l00121">121</a> of file <a class="el" href="dwc__otg__pcd__linux_8c-source.html">dwc_otg_pcd_linux.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="1708514cb93c5da43a8f634de1c0f5e7"></a><!-- doxytag: member="dwc_otg_pcd_linux.c::ep_disable" ref="1708514cb93c5da43a8f634de1c0f5e7" args="(struct usb_ep *usb_ep)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static int ep_disable           </td>
+          <td>(</td>
+          <td class="paramtype">struct usb_ep *&nbsp;</td>
+          <td class="paramname"> <em>usb_ep</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function is called when an EP is disabled due to disconnect or change in configuration. 
+<p>
+Any pending requests will terminate with a status of -ESHUTDOWN.<p>
+This function modifies the dwc_otg_ep_t data structure for this EP, and then calls dwc_otg_ep_deactivate. 
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__linux_8c-source.html#l00170">170</a> of file <a class="el" href="dwc__otg__pcd__linux_8c-source.html">dwc_otg_pcd_linux.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="e5a3f75b9a06a4707d1d0ec5957daa7d"></a><!-- doxytag: member="dwc_otg_pcd_linux.c::dwc_otg_pcd_alloc_request" ref="e5a3f75b9a06a4707d1d0ec5957daa7d" args="(struct usb_ep *ep, gfp_t gfp_flags)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static struct usb_request* dwc_otg_pcd_alloc_request           </td>
+          <td>(</td>
+          <td class="paramtype">struct usb_ep *&nbsp;</td>
+          <td class="paramname"> <em>ep</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">gfp_t&nbsp;</td>
+          <td class="paramname"> <em>gfp_flags</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function allocates a request object to use with the specified endpoint. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>ep</em>&nbsp;</td><td>The endpoint to be used with with the request </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>gfp_flags</em>&nbsp;</td><td>the GFP_* flags to use. </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__linux_8c-source.html#l00196">196</a> of file <a class="el" href="dwc__otg__pcd__linux_8c-source.html">dwc_otg_pcd_linux.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="348338816bfc0e711c4b875997ed00d9"></a><!-- doxytag: member="dwc_otg_pcd_linux.c::dwc_otg_pcd_free_request" ref="348338816bfc0e711c4b875997ed00d9" args="(struct usb_ep *ep, struct usb_request *req)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static void dwc_otg_pcd_free_request           </td>
+          <td>(</td>
+          <td class="paramtype">struct usb_ep *&nbsp;</td>
+          <td class="paramname"> <em>ep</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">struct usb_request *&nbsp;</td>
+          <td class="paramname"> <em>req</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function frees a request object. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>ep</em>&nbsp;</td><td>The endpoint associated with the request </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>req</em>&nbsp;</td><td>The request being freed </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__linux_8c-source.html#l00223">223</a> of file <a class="el" href="dwc__otg__pcd__linux_8c-source.html">dwc_otg_pcd_linux.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="295957efef868247c889aa3f5050af00"></a><!-- doxytag: member="dwc_otg_pcd_linux.c::dwc_otg_pcd_alloc_buffer" ref="295957efef868247c889aa3f5050af00" args="(struct usb_ep *usb_ep, unsigned bytes, dma_addr_t *dma, gfp_t gfp_flags)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static void* dwc_otg_pcd_alloc_buffer           </td>
+          <td>(</td>
+          <td class="paramtype">struct usb_ep *&nbsp;</td>
+          <td class="paramname"> <em>usb_ep</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">unsigned&nbsp;</td>
+          <td class="paramname"> <em>bytes</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">dma_addr_t *&nbsp;</td>
+          <td class="paramname"> <em>dma</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">gfp_t&nbsp;</td>
+          <td class="paramname"> <em>gfp_flags</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function allocates an I/O buffer to be used for a transfer to/from the specified endpoint. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>usb_ep</em>&nbsp;</td><td>The endpoint to be used with with the request </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>bytes</em>&nbsp;</td><td>The desired number of bytes for the buffer </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>dma</em>&nbsp;</td><td>Pointer to the buffer's DMA address; must be valid </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>gfp_flags</em>&nbsp;</td><td>the GFP_* flags to use. </td></tr>
+  </table>
+</dl>
+<dl compact><dt><b>Returns:</b></dt><dd>address of a new buffer or null is buffer could not be allocated. </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__linux_8c-source.html#l00246">246</a> of file <a class="el" href="dwc__otg__pcd__linux_8c-source.html">dwc_otg_pcd_linux.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="675a197388a82da27f74c11ffdbf874b"></a><!-- doxytag: member="dwc_otg_pcd_linux.c::dwc_otg_pcd_free_buffer" ref="675a197388a82da27f74c11ffdbf874b" args="(struct usb_ep *usb_ep, void *buf, dma_addr_t dma, unsigned bytes)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static void dwc_otg_pcd_free_buffer           </td>
+          <td>(</td>
+          <td class="paramtype">struct usb_ep *&nbsp;</td>
+          <td class="paramname"> <em>usb_ep</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&nbsp;</td>
+          <td class="paramname"> <em>buf</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">dma_addr_t&nbsp;</td>
+          <td class="paramname"> <em>dma</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">unsigned&nbsp;</td>
+          <td class="paramname"> <em>bytes</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function frees an I/O buffer that was allocated by alloc_buffer. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>usb_ep</em>&nbsp;</td><td>the endpoint associated with the buffer </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>buf</em>&nbsp;</td><td>address of the buffer </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>dma</em>&nbsp;</td><td>The buffer's DMA address </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>bytes</em>&nbsp;</td><td>The number of bytes of the buffer </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__linux_8c-source.html#l00282">282</a> of file <a class="el" href="dwc__otg__pcd__linux_8c-source.html">dwc_otg_pcd_linux.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="f97bea831037135af73c3c202e3e01dc"></a><!-- doxytag: member="dwc_otg_pcd_linux.c::ep_queue" ref="f97bea831037135af73c3c202e3e01dc" args="(struct usb_ep *usb_ep, struct usb_request *usb_req, gfp_t gfp_flags)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static int ep_queue           </td>
+          <td>(</td>
+          <td class="paramtype">struct usb_ep *&nbsp;</td>
+          <td class="paramname"> <em>usb_ep</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">struct usb_request *&nbsp;</td>
+          <td class="paramname"> <em>usb_req</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">gfp_t&nbsp;</td>
+          <td class="paramname"> <em>gfp_flags</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function is used to submit an I/O Request to an EP. 
+<p>
+<ul>
+<li>When the request completes the request's completion callback is called to return the request to the driver.</li><li>An EP, except control EPs, may have multiple requests pending.</li><li>Once submitted the request cannot be examined or modified.</li><li>Each request is turned into one or more packets.</li><li>A BULK EP can queue any amount of data; the transfer is packetized.</li><li>Zero length Packets are specified with the request 'zero' flag. </li></ul>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__linux_8c-source.html#l00308">308</a> of file <a class="el" href="dwc__otg__pcd__linux_8c-source.html">dwc_otg_pcd_linux.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="8ee99e0e68c8e50e94c242805b158cb2"></a><!-- doxytag: member="dwc_otg_pcd_linux.c::ep_halt" ref="8ee99e0e68c8e50e94c242805b158cb2" args="(struct usb_ep *usb_ep, int value)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static int ep_halt           </td>
+          <td>(</td>
+          <td class="paramtype">struct usb_ep *&nbsp;</td>
+          <td class="paramname"> <em>usb_ep</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int&nbsp;</td>
+          <td class="paramname"> <em>value</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+usb_ep_set_halt stalls an endpoint. 
+<p>
+usb_ep_clear_halt clears an endpoint halt and resets its data toggle.<p>
+Both of these functions are implemented with the same underlying function. The behavior depends on the value argument.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"><tt>[in]</tt>&nbsp;</td><td valign="top"><em>usb_ep</em>&nbsp;</td><td>the Endpoint to halt or clear halt. </td></tr>
+    <tr><td valign="top"><tt>[in]</tt>&nbsp;</td><td valign="top"><em>value</em>&nbsp;</td><td><ul>
+<li>0 means clear_halt.</li><li>1 means set_halt,</li><li>2 means clear stall lock flag.</li><li>3 means set stall lock flag. </li></ul>
+</td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__linux_8c-source.html#l00391">391</a> of file <a class="el" href="dwc__otg__pcd__linux_8c-source.html">dwc_otg_pcd_linux.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="eb3df484c8c344613a2a9b23e24036a8"></a><!-- doxytag: member="dwc_otg_pcd_linux.c::iso_ep_start" ref="eb3df484c8c344613a2a9b23e24036a8" args="(struct usb_ep *usb_ep, struct usb_iso_request *req, gfp_t gfp_flags)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static int iso_ep_start           </td>
+          <td>(</td>
+          <td class="paramtype">struct usb_ep *&nbsp;</td>
+          <td class="paramname"> <em>usb_ep</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">struct usb_iso_request *&nbsp;</td>
+          <td class="paramname"> <em>req</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">gfp_t&nbsp;</td>
+          <td class="paramname"> <em>gfp_flags</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function is used to submit an ISOC Transfer Request to an EP. 
+<p>
+<ul>
+<li>Every time a sync period completes the request's completion callback is called to provide data to the gadget driver.</li><li>Once submitted the request cannot be modified.</li><li>Each request is turned into periodic data packets untill ISO Transfer is stopped.. </li></ul>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__linux_8c-source.html#l00422">422</a> of file <a class="el" href="dwc__otg__pcd__linux_8c-source.html">dwc_otg_pcd_linux.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="6a6034564b7cc6d8cebfbe02a944cd2c"></a><!-- doxytag: member="dwc_otg_pcd_linux.c::wakeup" ref="6a6034564b7cc6d8cebfbe02a944cd2c" args="(struct usb_gadget *gadget)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static int wakeup           </td>
+          <td>(</td>
+          <td class="paramtype">struct usb_gadget *&nbsp;</td>
+          <td class="paramname"> <em>gadget</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Initiates Session Request Protocol (SRP) to wakeup the host if no session is in progress. 
+<p>
+If a session is already in progress, but the device is suspended, remote wakeup signaling is started. 
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__linux_8c-source.html#l00603">603</a> of file <a class="el" href="dwc__otg__pcd__linux_8c-source.html">dwc_otg_pcd_linux.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="647f81bc0edc9007af3ff2ba04e884f3"></a><!-- doxytag: member="dwc_otg_pcd_linux.c::gadget_add_eps" ref="647f81bc0edc9007af3ff2ba04e884f3" args="(struct gadget_wrapper *d)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void gadget_add_eps           </td>
+          <td>(</td>
+          <td class="paramtype">struct <a class="el" href="structgadget__wrapper.html">gadget_wrapper</a> *&nbsp;</td>
+          <td class="paramname"> <em>d</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function initialized the usb_ep structures to there default state. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>d</em>&nbsp;</td><td>Pointer on <a class="el" href="structgadget__wrapper.html">gadget_wrapper</a>. </td></tr>
+  </table>
+</dl>
+
+<p>
+Initialize the EP0 structure.<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000045">Todo:</a></b></dt><dd>NGS: What should the max packet size be set to here? Before EP type is set? </dd></dl>
+<p>
+Initialize the EP structures.<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000045">Todo:</a></b></dt><dd>NGS: What should the max packet size be set to here? Before EP type is set? </dd></dl>
+<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000045">Todo:</a></b></dt><dd>NGS: What should the max packet size be set to here? Before EP type is set? </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__linux_8c-source.html#l00824">824</a> of file <a class="el" href="dwc__otg__pcd__linux_8c-source.html">dwc_otg_pcd_linux.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="6cbde69780790137d41fd45558236000"></a><!-- doxytag: member="dwc_otg_pcd_linux.c::dwc_otg_pcd_gadget_release" ref="6cbde69780790137d41fd45558236000" args="(struct device *dev)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">static void dwc_otg_pcd_gadget_release           </td>
+          <td>(</td>
+          <td class="paramtype">struct device *&nbsp;</td>
+          <td class="paramname"> <em>dev</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"><code> [static]</code></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function releases the Gadget device. 
+<p>
+required by device_unregister().<p>
+<dl compact><dt><b><a class="el" href="todo.html#_todo000048">Todo:</a></b></dt><dd>Should this do something? Should it free the PCD? </dd></dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__linux_8c-source.html#l00937">937</a> of file <a class="el" href="dwc__otg__pcd__linux_8c-source.html">dwc_otg_pcd_linux.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="8c1ba129028b3b16909973eb30b85d2c"></a><!-- doxytag: member="dwc_otg_pcd_linux.c::usb_gadget_register_driver" ref="8c1ba129028b3b16909973eb30b85d2c" args="(struct usb_gadget_driver *driver)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int usb_gadget_register_driver           </td>
+          <td>(</td>
+          <td class="paramtype">struct usb_gadget_driver *&nbsp;</td>
+          <td class="paramname"> <em>driver</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function registers a gadget driver with the PCD. 
+<p>
+When a driver is successfully registered, it will receive control requests including set_configuration(), which enables non-control requests. then usb traffic follows until a disconnect is reported. then a host may connect again, or the driver might get unbound.<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>driver</em>&nbsp;</td><td>The driver being registered </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__linux_8c-source.html#l01096">1096</a> of file <a class="el" href="dwc__otg__pcd__linux_8c-source.html">dwc_otg_pcd_linux.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="fa4a24d0806fbb6e3135d27d24a6a00d"></a><!-- doxytag: member="dwc_otg_pcd_linux.c::usb_gadget_unregister_driver" ref="fa4a24d0806fbb6e3135d27d24a6a00d" args="(struct usb_gadget_driver *driver)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int usb_gadget_unregister_driver           </td>
+          <td>(</td>
+          <td class="paramtype">struct usb_gadget_driver *&nbsp;</td>
+          <td class="paramname"> <em>driver</em>          </td>
+          <td>&nbsp;)&nbsp;</td>
+          <td width="100%"></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This function unregisters a gadget driver. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>driver</em>&nbsp;</td><td>The driver being unregistered </td></tr>
+  </table>
+</dl>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__linux_8c-source.html#l01143">1143</a> of file <a class="el" href="dwc__otg__pcd__linux_8c-source.html">dwc_otg_pcd_linux.c</a>.
+</div>
+</div><p>
+<hr><h2>Variable Documentation</h2>
+<a class="anchor" name="8d23bf781df0ba0fb4a0133d08c09dc1"></a><!-- doxytag: member="dwc_otg_pcd_linux.c::dwc_otg_pcd_ep_ops" ref="8d23bf781df0ba0fb4a0133d08c09dc1" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">struct usb_isoc_ep_ops <a class="el" href="dwc__otg__pcd__linux_8c.html#8d23bf781df0ba0fb4a0133d08c09dc1">dwc_otg_pcd_ep_ops</a><code> [static]</code>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Initial value:</b><div class="fragment"><pre class="fragment"> {
+        .ep_ops = {
+                   .enable = <a class="code" href="dwc__otg__pcd__linux_8c.html#9761890d7f741f9421d82254c9846f31">ep_enable</a>,
+                   .disable = <a class="code" href="dwc__otg__pcd__linux_8c.html#1708514cb93c5da43a8f634de1c0f5e7">ep_disable</a>,
+
+                   .alloc_request = <a class="code" href="dwc__otg__pcd__linux_8c.html#e5a3f75b9a06a4707d1d0ec5957daa7d">dwc_otg_pcd_alloc_request</a>,
+                   .free_request = <a class="code" href="dwc__otg__pcd__linux_8c.html#348338816bfc0e711c4b875997ed00d9">dwc_otg_pcd_free_request</a>,
+
+                   .alloc_buffer = <a class="code" href="dwc__otg__pcd__linux_8c.html#295957efef868247c889aa3f5050af00">dwc_otg_pcd_alloc_buffer</a>,
+                   .free_buffer = <a class="code" href="dwc__otg__pcd__linux_8c.html#675a197388a82da27f74c11ffdbf874b">dwc_otg_pcd_free_buffer</a>,
+
+                   .queue = <a class="code" href="dwc__otg__pcd__linux_8c.html#f97bea831037135af73c3c202e3e01dc">ep_queue</a>,
+                   .dequeue = <a class="code" href="dwc__otg__pcd__linux_8c.html#e2e4913a926acc55f4e57c3ff8f97c08">ep_dequeue</a>,
+
+                   .set_halt = <a class="code" href="dwc__otg__pcd__linux_8c.html#8ee99e0e68c8e50e94c242805b158cb2">ep_halt</a>,
+                   .fifo_status = 0,
+                   .fifo_flush = 0,
+                   },
+        .iso_ep_start = <a class="code" href="dwc__otg__pcd__linux_8c.html#eb3df484c8c344613a2a9b23e24036a8">iso_ep_start</a>,
+        .iso_ep_stop = <a class="code" href="dwc__otg__pcd__linux_8c.html#cecdcaa060d30ac09414419545a5d1c6">iso_ep_stop</a>,
+        .alloc_iso_request = <a class="code" href="dwc__otg__pcd__linux_8c.html#94fd50b5e9d41d1d38a503d819fc07c4">alloc_iso_request</a>,
+        .free_iso_request = <a class="code" href="dwc__otg__pcd__linux_8c.html#a9a7bc869bc7f3d05804059f3277d11a">free_iso_request</a>,
+}
+</pre></div>
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__linux_8c-source.html#l00507">507</a> of file <a class="el" href="dwc__otg__pcd__linux_8c-source.html">dwc_otg_pcd_linux.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="592a942ef237021f608d03dd8b57bc54"></a><!-- doxytag: member="dwc_otg_pcd_linux.c::dwc_otg_pcd_ops" ref="592a942ef237021f608d03dd8b57bc54" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">struct usb_gadget_ops <a class="el" href="dwc__otg__pcd__linux_8c.html#592a942ef237021f608d03dd8b57bc54">dwc_otg_pcd_ops</a><code> [static]</code>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Initial value:</b><div class="fragment"><pre class="fragment"> {
+        .get_frame = <a class="code" href="dwc__otg__hcd__linux_8c.html#c78128edb8902dc96534c5bb253f99a3">get_frame_number</a>,
+        .wakeup = <a class="code" href="dwc__otg__pcd__linux_8c.html#6a6034564b7cc6d8cebfbe02a944cd2c">wakeup</a>,
+
+
+
+        
+}
+</pre></div>
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__linux_8c-source.html#l00618">618</a> of file <a class="el" href="dwc__otg__pcd__linux_8c-source.html">dwc_otg_pcd_linux.c</a>.
+</div>
+</div><p>
+<a class="anchor" name="9ce9b5e49c60906c189bee157dd68acd"></a><!-- doxytag: member="dwc_otg_pcd_linux.c::fops" ref="9ce9b5e49c60906c189bee157dd68acd" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">struct <a class="el" href="structdwc__otg__pcd__function__ops.html">dwc_otg_pcd_function_ops</a> <a class="el" href="dwc__otg__pcd__linux_8c.html#9ce9b5e49c60906c189bee157dd68acd">fops</a><code> [static]</code>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+<b>Initial value:</b><div class="fragment"><pre class="fragment"> {
+        .complete = <a class="code" href="dwc__otg__hcd__linux_8c.html#a0d18986574c384e98aa280e0475a9aa">_complete</a>,
+
+        .isoc_complete = <a class="code" href="dwc__otg__pcd__linux_8c.html#737e47386e05da8cf6cbf85a289f5454">_isoc_complete</a>,
+
+        .setup = <a class="code" href="dwc__otg__pcd__linux_8c.html#4a1481839b3d869d882f984a6c6ed9e5">_setup</a>,
+        .disconnect = <a class="code" href="dwc__otg__hcd__linux_8c.html#8011f9b662a7f4182e762de616bbc95e">_disconnect</a>,
+        .connect = <a class="code" href="dwc__otg__pcd__linux_8c.html#c7c1c4f8fe8e62f1d9e6f75de5563658">_connect</a>,
+        .resume = <a class="code" href="dwc__otg__pcd__linux_8c.html#86cdfe71d125da339e17e52049fc5ea0">_resume</a>,
+        .suspend = <a class="code" href="dwc__otg__pcd__linux_8c.html#7f479ecaee0801b55b4f0bd0f36f8b67">_suspend</a>,
+        .hnp_changed = <a class="code" href="dwc__otg__pcd__linux_8c.html#9e8595e1d36e6b1ffbc27c4862957a08">_hnp_changed</a>,
+        .reset = <a class="code" href="dwc__otg__pcd__linux_8c.html#208cf9e0227e5f81e015ed3ac5bacec4">_reset</a>,
+
+
+
+}
+</pre></div>
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__linux_8c-source.html#l00786">786</a> of file <a class="el" href="dwc__otg__pcd__linux_8c-source.html">dwc_otg_pcd_linux.c</a>.
+</div>
+</div><p>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/dwc__otg__regs_8h-source.html b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__regs_8h-source.html
new file mode 100644
index 000000000000..6efa7f867a1b
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__regs_8h-source.html
@@ -0,0 +1,1260 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_regs.h Source File</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
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+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<h1>dwc_otg_regs.h</h1><a href="dwc__otg__regs_8h.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">/* ==========================================================================</span>
+<a name="l00002"></a>00002 <span class="comment"> * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_regs.h $</span>
+<a name="l00003"></a>00003 <span class="comment"> * $Revision: #76 $</span>
+<a name="l00004"></a>00004 <span class="comment"> * $Date: 2009/04/02 $</span>
+<a name="l00005"></a>00005 <span class="comment"> * $Change: 1224216 $</span>
+<a name="l00006"></a>00006 <span class="comment"> *</span>
+<a name="l00007"></a>00007 <span class="comment"> * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,</span>
+<a name="l00008"></a>00008 <span class="comment"> * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless</span>
+<a name="l00009"></a>00009 <span class="comment"> * otherwise expressly agreed to in writing between Synopsys and you.</span>
+<a name="l00010"></a>00010 <span class="comment"> * </span>
+<a name="l00011"></a>00011 <span class="comment"> * The Software IS NOT an item of Licensed Software or Licensed Product under</span>
+<a name="l00012"></a>00012 <span class="comment"> * any End User Software License Agreement or Agreement for Licensed Product</span>
+<a name="l00013"></a>00013 <span class="comment"> * with Synopsys or any supplement thereto. You are permitted to use and</span>
+<a name="l00014"></a>00014 <span class="comment"> * redistribute this Software in source and binary forms, with or without</span>
+<a name="l00015"></a>00015 <span class="comment"> * modification, provided that redistributions of source code must retain this</span>
+<a name="l00016"></a>00016 <span class="comment"> * notice. You may not view, use, disclose, copy or distribute this file or</span>
+<a name="l00017"></a>00017 <span class="comment"> * any information contained herein except pursuant to this license grant from</span>
+<a name="l00018"></a>00018 <span class="comment"> * Synopsys. If you do not agree with this notice, including the disclaimer</span>
+<a name="l00019"></a>00019 <span class="comment"> * below, then you are not authorized to use the Software.</span>
+<a name="l00020"></a>00020 <span class="comment"> * </span>
+<a name="l00021"></a>00021 <span class="comment"> * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS</span>
+<a name="l00022"></a>00022 <span class="comment"> * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE</span>
+<a name="l00023"></a>00023 <span class="comment"> * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE</span>
+<a name="l00024"></a>00024 <span class="comment"> * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,</span>
+<a name="l00025"></a>00025 <span class="comment"> * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES</span>
+<a name="l00026"></a>00026 <span class="comment"> * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR</span>
+<a name="l00027"></a>00027 <span class="comment"> * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER</span>
+<a name="l00028"></a>00028 <span class="comment"> * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT</span>
+<a name="l00029"></a>00029 <span class="comment"> * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY</span>
+<a name="l00030"></a>00030 <span class="comment"> * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH</span>
+<a name="l00031"></a>00031 <span class="comment"> * DAMAGE.</span>
+<a name="l00032"></a>00032 <span class="comment"> * ========================================================================== */</span>
+<a name="l00033"></a>00033 
+<a name="l00034"></a>00034 <span class="preprocessor">#ifndef __DWC_OTG_REGS_H__</span>
+<a name="l00035"></a>00035 <span class="preprocessor"></span><span class="preprocessor">#define __DWC_OTG_REGS_H__</span>
+<a name="l00036"></a>00036 <span class="preprocessor"></span>
+<a name="l00037"></a>00037 <span class="preprocessor">#include "<a class="code" href="dwc__otg__core__if_8h.html">dwc_otg_core_if.h</a>"</span>
+<a name="l00038"></a>00038 
+<a name="l00066"></a>00066 <span class="comment">/****************************************************************************/</span>
+<a name="l00071"></a><a class="code" href="structdwc__otg__core__global__regs.html">00071</a> <span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code" href="structdwc__otg__core__global__regs.html">dwc_otg_core_global_regs</a> {
+<a name="l00073"></a><a class="code" href="structdwc__otg__core__global__regs.html#54034d00bb6b47ada4e0c0baa87cbd8a">00073</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__core__global__regs.html#54034d00bb6b47ada4e0c0baa87cbd8a">gotgctl</a>;
+<a name="l00075"></a><a class="code" href="structdwc__otg__core__global__regs.html#69cc290cfdfe6900890f7a5a16b3137c">00075</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__core__global__regs.html#69cc290cfdfe6900890f7a5a16b3137c">gotgint</a>;
+<a name="l00077"></a><a class="code" href="structdwc__otg__core__global__regs.html#537c95e57269fabf29c6b36ad8e1ed45">00077</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__core__global__regs.html#537c95e57269fabf29c6b36ad8e1ed45">gahbcfg</a>;
+<a name="l00078"></a>00078 
+<a name="l00079"></a><a class="code" href="dwc__otg__regs_8h.html#d9d4b173bf321ff42fce0e9deff98e14">00079</a> <span class="preprocessor">#define DWC_GLBINTRMASK         0x0001</span>
+<a name="l00080"></a><a class="code" href="dwc__otg__regs_8h.html#560957ddd2a723670ef56420c4180254">00080</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_DMAENABLE           0x0020</span>
+<a name="l00081"></a><a class="code" href="dwc__otg__regs_8h.html#7022f94899c9292fb3bbde4467c8b8f0">00081</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_NPTXEMPTYLVL_EMPTY  0x0080</span>
+<a name="l00082"></a><a class="code" href="dwc__otg__regs_8h.html#079b5cc58466a4e15679e69256084554">00082</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_NPTXEMPTYLVL_HALFEMPTY      0x0000</span>
+<a name="l00083"></a><a class="code" href="dwc__otg__regs_8h.html#cf27d55f3aae7ee1a3b542bd0440be38">00083</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_PTXEMPTYLVL_EMPTY   0x0100</span>
+<a name="l00084"></a><a class="code" href="dwc__otg__regs_8h.html#33e16da6d4da8316b50fdeb3c05c5930">00084</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_PTXEMPTYLVL_HALFEMPTY       0x0000</span>
+<a name="l00085"></a>00085 <span class="preprocessor"></span>
+<a name="l00087"></a><a class="code" href="structdwc__otg__core__global__regs.html#ef39e181e246447df47c56aa4e37cc42">00087</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__core__global__regs.html#ef39e181e246447df47c56aa4e37cc42">gusbcfg</a>;
+<a name="l00089"></a><a class="code" href="structdwc__otg__core__global__regs.html#49d307957dbe53f20aa8f7a5409ee8ad">00089</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__core__global__regs.html#49d307957dbe53f20aa8f7a5409ee8ad">grstctl</a>;
+<a name="l00091"></a><a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">00091</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a>;
+<a name="l00093"></a><a class="code" href="structdwc__otg__core__global__regs.html#48827c76da2c6b18f369e2f2483cc4b6">00093</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__core__global__regs.html#48827c76da2c6b18f369e2f2483cc4b6">gintmsk</a>;
+<a name="l00095"></a><a class="code" href="structdwc__otg__core__global__regs.html#5e688c41f25ba8081f34cb1b2b052dbc">00095</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__core__global__regs.html#5e688c41f25ba8081f34cb1b2b052dbc">grxstsr</a>;
+<a name="l00097"></a><a class="code" href="structdwc__otg__core__global__regs.html#763b05035799e1c16d34957fb62a2d17">00097</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__core__global__regs.html#763b05035799e1c16d34957fb62a2d17">grxstsp</a>;
+<a name="l00099"></a><a class="code" href="structdwc__otg__core__global__regs.html#b1a8cc07a9541c9a73e864579602b79b">00099</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__core__global__regs.html#b1a8cc07a9541c9a73e864579602b79b">grxfsiz</a>;
+<a name="l00101"></a><a class="code" href="structdwc__otg__core__global__regs.html#20fb70fe34a1a65d085b1d4e5f8d9106">00101</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__core__global__regs.html#20fb70fe34a1a65d085b1d4e5f8d9106">gnptxfsiz</a>;
+<a name="l00104"></a><a class="code" href="structdwc__otg__core__global__regs.html#57dabea6f6e0bf9e1ee8e94f55b9e465">00104</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__core__global__regs.html#57dabea6f6e0bf9e1ee8e94f55b9e465">gnptxsts</a>;
+<a name="l00106"></a><a class="code" href="structdwc__otg__core__global__regs.html#8ecf68262dbcdb6901f3011cfe35a144">00106</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__core__global__regs.html#8ecf68262dbcdb6901f3011cfe35a144">gi2cctl</a>;
+<a name="l00108"></a><a class="code" href="structdwc__otg__core__global__regs.html#a12db668367caef8386d2ba20289e437">00108</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__core__global__regs.html#a12db668367caef8386d2ba20289e437">gpvndctl</a>;
+<a name="l00110"></a><a class="code" href="structdwc__otg__core__global__regs.html#694546400c443d41b449772c8573f3e8">00110</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__core__global__regs.html#694546400c443d41b449772c8573f3e8">ggpio</a>;
+<a name="l00112"></a><a class="code" href="structdwc__otg__core__global__regs.html#8735ca2e93c1e984ac2d5bcf0cda96d7">00112</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__core__global__regs.html#8735ca2e93c1e984ac2d5bcf0cda96d7">guid</a>;
+<a name="l00114"></a><a class="code" href="structdwc__otg__core__global__regs.html#30798436df220217c3960ac4a46710dc">00114</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__core__global__regs.html#30798436df220217c3960ac4a46710dc">gsnpsid</a>;
+<a name="l00116"></a><a class="code" href="structdwc__otg__core__global__regs.html#56d2988ff8fedbbde479ffe8d4e84b75">00116</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__core__global__regs.html#56d2988ff8fedbbde479ffe8d4e84b75">ghwcfg1</a>;
+<a name="l00118"></a><a class="code" href="structdwc__otg__core__global__regs.html#b0f241f53ca7b3be1c94bd684ed61f79">00118</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__core__global__regs.html#b0f241f53ca7b3be1c94bd684ed61f79">ghwcfg2</a>;
+<a name="l00119"></a><a class="code" href="dwc__otg__regs_8h.html#b06d547ae50b58fd46847daa34578122">00119</a> <span class="preprocessor">#define DWC_SLAVE_ONLY_ARCH 0</span>
+<a name="l00120"></a><a class="code" href="dwc__otg__regs_8h.html#bc493e89caf2ae15aa2b306099b8a927">00120</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_EXT_DMA_ARCH 1</span>
+<a name="l00121"></a><a class="code" href="dwc__otg__regs_8h.html#f91a3e3ec200595566b8df5e40485fda">00121</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_INT_DMA_ARCH 2</span>
+<a name="l00122"></a>00122 <span class="preprocessor"></span>
+<a name="l00123"></a><a class="code" href="dwc__otg__regs_8h.html#8d3140b85bae33e2d7955693c61fd490">00123</a> <span class="preprocessor">#define DWC_MODE_HNP_SRP_CAPABLE        0</span>
+<a name="l00124"></a><a class="code" href="dwc__otg__regs_8h.html#ecd675d5698ebf873bad50c6d2241296">00124</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_MODE_SRP_ONLY_CAPABLE       1</span>
+<a name="l00125"></a><a class="code" href="dwc__otg__regs_8h.html#42740812c78415753c76ea58e2dd6a50">00125</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_MODE_NO_HNP_SRP_CAPABLE             2</span>
+<a name="l00126"></a><a class="code" href="dwc__otg__regs_8h.html#0e5bc465c451f7ce8402ce94c355398e">00126</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_MODE_SRP_CAPABLE_DEVICE             3</span>
+<a name="l00127"></a><a class="code" href="dwc__otg__regs_8h.html#74152fd1bf534e043a53efd98a982bb6">00127</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_MODE_NO_SRP_CAPABLE_DEVICE  4</span>
+<a name="l00128"></a><a class="code" href="dwc__otg__regs_8h.html#bbca30221d8415bad1c254e5cb240eaa">00128</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_MODE_SRP_CAPABLE_HOST       5</span>
+<a name="l00129"></a><a class="code" href="dwc__otg__regs_8h.html#91a7255e685d172cfa7b6be0eaab5102">00129</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_MODE_NO_SRP_CAPABLE_HOST    6</span>
+<a name="l00130"></a>00130 <span class="preprocessor"></span>
+<a name="l00132"></a><a class="code" href="structdwc__otg__core__global__regs.html#57ddcc14f581f5d6276122f9747aff72">00132</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__core__global__regs.html#57ddcc14f581f5d6276122f9747aff72">ghwcfg3</a>;
+<a name="l00134"></a><a class="code" href="structdwc__otg__core__global__regs.html#e1df73c776d3b31d5f0a501ccdeb1d2d">00134</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__core__global__regs.html#e1df73c776d3b31d5f0a501ccdeb1d2d">ghwcfg4</a>;
+<a name="l00136"></a><a class="code" href="structdwc__otg__core__global__regs.html#843cfb38ba366a9a46ad07ed11eb8396">00136</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__core__global__regs.html#843cfb38ba366a9a46ad07ed11eb8396">glpmcfg</a>;
+<a name="l00138"></a><a class="code" href="structdwc__otg__core__global__regs.html#61b9a23f780477ed03ef8236a393fb2e">00138</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__core__global__regs.html#61b9a23f780477ed03ef8236a393fb2e">reserved</a>[42];
+<a name="l00140"></a><a class="code" href="structdwc__otg__core__global__regs.html#94ae41f04d5a4244a8ebc23e51187e96">00140</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__core__global__regs.html#94ae41f04d5a4244a8ebc23e51187e96">hptxfsiz</a>;
+<a name="l00144"></a><a class="code" href="structdwc__otg__core__global__regs.html#efd9e780825f992dbc6cf46d2d72869e">00144</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__core__global__regs.html#efd9e780825f992dbc6cf46d2d72869e">dptxfsiz_dieptxf</a>[15];
+<a name="l00145"></a>00145 } <a class="code" href="structdwc__otg__core__global__regs.html">dwc_otg_core_global_regs_t</a>;
+<a name="l00146"></a>00146 
+<a name="l00152"></a><a class="code" href="uniongotgctl__data.html">00152</a> <span class="keyword">typedef</span> <span class="keyword">union </span><a class="code" href="uniongotgctl__data.html">gotgctl_data</a> {
+<a name="l00154"></a><a class="code" href="uniongotgctl__data.html#ebb591ab40ff41f0e06f03a795647d33">00154</a>         uint32_t <a class="code" href="uniongotgctl__data.html#ebb591ab40ff41f0e06f03a795647d33">d32</a>;
+<a name="l00156"></a>00156         <span class="keyword">struct </span>{
+<a name="l00157"></a><a class="code" href="uniongotgctl__data.html#5239dbbb4b31210a35a7104abb688801">00157</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongotgctl__data.html#5239dbbb4b31210a35a7104abb688801">sesreqscs</a>:1;
+<a name="l00158"></a><a class="code" href="uniongotgctl__data.html#c6b0b35d4366f74cf6fe268eda781f06">00158</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongotgctl__data.html#c6b0b35d4366f74cf6fe268eda781f06">sesreq</a>:1;
+<a name="l00159"></a><a class="code" href="uniongotgctl__data.html#8a1159d33534011e702124f11e32346a">00159</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongotgctl__data.html#8a1159d33534011e702124f11e32346a">reserved2_7</a>:6;
+<a name="l00160"></a><a class="code" href="uniongotgctl__data.html#20b17868fc09a12b163732d5bbc84d8d">00160</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongotgctl__data.html#20b17868fc09a12b163732d5bbc84d8d">hstnegscs</a>:1;
+<a name="l00161"></a><a class="code" href="uniongotgctl__data.html#08487ecb0860252b73815ee6e0f8eaa3">00161</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongotgctl__data.html#08487ecb0860252b73815ee6e0f8eaa3">hnpreq</a>:1;
+<a name="l00162"></a><a class="code" href="uniongotgctl__data.html#7d45791d3622a59ff43ab248bbb1b2c1">00162</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongotgctl__data.html#7d45791d3622a59ff43ab248bbb1b2c1">hstsethnpen</a>:1;
+<a name="l00163"></a><a class="code" href="uniongotgctl__data.html#0058cbee8b53336c28746116301ea796">00163</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongotgctl__data.html#0058cbee8b53336c28746116301ea796">devhnpen</a>:1;
+<a name="l00164"></a><a class="code" href="uniongotgctl__data.html#8cdb9c356cb2bd7c08fd03277d018abe">00164</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongotgctl__data.html#8cdb9c356cb2bd7c08fd03277d018abe">reserved12_15</a>:4;
+<a name="l00165"></a><a class="code" href="uniongotgctl__data.html#777151f3c8c1b3117493aee2cd7a2e5c">00165</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongotgctl__data.html#777151f3c8c1b3117493aee2cd7a2e5c">conidsts</a>:1;
+<a name="l00166"></a><a class="code" href="uniongotgctl__data.html#10d4ca93b77030eb791dba2486d337d8">00166</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongotgctl__data.html#10d4ca93b77030eb791dba2486d337d8">reserved17</a>:1;
+<a name="l00167"></a><a class="code" href="uniongotgctl__data.html#e16505965a031d2e488a26378a14a834">00167</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongotgctl__data.html#e16505965a031d2e488a26378a14a834">asesvld</a>:1;
+<a name="l00168"></a><a class="code" href="uniongotgctl__data.html#69931c3759421d5eb6f91d4c9da4dddd">00168</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongotgctl__data.html#69931c3759421d5eb6f91d4c9da4dddd">bsesvld</a>:1;
+<a name="l00169"></a><a class="code" href="uniongotgctl__data.html#540a9022e5ff38c2a656b8ebd59070cb">00169</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongotgctl__data.html#540a9022e5ff38c2a656b8ebd59070cb">currmod</a>:1;
+<a name="l00170"></a><a class="code" href="uniongotgctl__data.html#c4e3970718da78ebc91f6cf46a2944ae">00170</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongotgctl__data.html#c4e3970718da78ebc91f6cf46a2944ae">reserved21_31</a>:11;
+<a name="l00171"></a>00171         } <a class="code" href="uniongotgctl__data.html#212c81366266e906a188f4dbfadb6dd3">b</a>;
+<a name="l00172"></a>00172 } <a class="code" href="uniongotgctl__data.html">gotgctl_data_t</a>;
+<a name="l00173"></a>00173 
+<a name="l00179"></a><a class="code" href="uniongotgint__data.html">00179</a> <span class="keyword">typedef</span> <span class="keyword">union </span><a class="code" href="uniongotgint__data.html">gotgint_data</a> {
+<a name="l00181"></a><a class="code" href="uniongotgint__data.html#8a343df4fc4e68b802be7629864308e2">00181</a>         uint32_t <a class="code" href="uniongotgint__data.html#8a343df4fc4e68b802be7629864308e2">d32</a>;
+<a name="l00183"></a>00183         <span class="keyword">struct </span>{
+<a name="l00185"></a><a class="code" href="uniongotgint__data.html#8da0f04fa16cee7d0446e47e9e459df8">00185</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongotgint__data.html#8da0f04fa16cee7d0446e47e9e459df8">reserved0_1</a>:2;
+<a name="l00186"></a>00186 
+<a name="l00188"></a><a class="code" href="uniongotgint__data.html#58a04bef67e26229efe95f12938d18e8">00188</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongotgint__data.html#58a04bef67e26229efe95f12938d18e8">sesenddet</a>:1;
+<a name="l00189"></a>00189 
+<a name="l00190"></a><a class="code" href="uniongotgint__data.html#55e5d90b1cbab85d6928246c45d5a14c">00190</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongotgint__data.html#55e5d90b1cbab85d6928246c45d5a14c">reserved3_7</a>:5;
+<a name="l00191"></a>00191 
+<a name="l00193"></a><a class="code" href="uniongotgint__data.html#99a56305c7cc48086ef34c15bbc40ca6">00193</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongotgint__data.html#99a56305c7cc48086ef34c15bbc40ca6">sesreqsucstschng</a>:1;
+<a name="l00195"></a><a class="code" href="uniongotgint__data.html#e41c62fee3da6113b23594cec6fb0c67">00195</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongotgint__data.html#e41c62fee3da6113b23594cec6fb0c67">hstnegsucstschng</a>:1;
+<a name="l00196"></a>00196 
+<a name="l00197"></a><a class="code" href="uniongotgint__data.html#0bbecd636a8dcdc464880f70de8b8dec">00197</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongotgint__data.html#0bbecd636a8dcdc464880f70de8b8dec">reserver10_16</a>:7;
+<a name="l00198"></a>00198 
+<a name="l00200"></a><a class="code" href="uniongotgint__data.html#7cd2a34cef45f168eb3ee197c101d164">00200</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongotgint__data.html#7cd2a34cef45f168eb3ee197c101d164">hstnegdet</a>:1;
+<a name="l00202"></a><a class="code" href="uniongotgint__data.html#f216cb4939e1a348fbffaff87fc42772">00202</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongotgint__data.html#f216cb4939e1a348fbffaff87fc42772">adevtoutchng</a>:1;
+<a name="l00204"></a><a class="code" href="uniongotgint__data.html#7bac6821d07d401731213dc0e94852ca">00204</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongotgint__data.html#7bac6821d07d401731213dc0e94852ca">debdone</a>:1;
+<a name="l00205"></a>00205 
+<a name="l00206"></a><a class="code" href="uniongotgint__data.html#7ef91e2737b9a29324c79310e94a0bca">00206</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongotgint__data.html#7ef91e2737b9a29324c79310e94a0bca">reserved31_20</a>:12;
+<a name="l00207"></a>00207 
+<a name="l00208"></a>00208         } <a class="code" href="uniongotgint__data.html#e48c5633608687c8895da201199c2a7c">b</a>;
+<a name="l00209"></a>00209 } <a class="code" href="uniongotgint__data.html">gotgint_data_t</a>;
+<a name="l00210"></a>00210 
+<a name="l00216"></a><a class="code" href="uniongahbcfg__data.html">00216</a> <span class="keyword">typedef</span> <span class="keyword">union </span><a class="code" href="uniongahbcfg__data.html">gahbcfg_data</a> {
+<a name="l00218"></a><a class="code" href="uniongahbcfg__data.html#2532b75f838946009af8806c924f0c08">00218</a>         uint32_t <a class="code" href="uniongahbcfg__data.html#2532b75f838946009af8806c924f0c08">d32</a>;
+<a name="l00220"></a>00220         <span class="keyword">struct </span>{
+<a name="l00221"></a><a class="code" href="uniongahbcfg__data.html#f75957f35be7ecd70616f5d0bcfb1e51">00221</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongahbcfg__data.html#f75957f35be7ecd70616f5d0bcfb1e51">glblintrmsk</a>:1;
+<a name="l00222"></a><a class="code" href="dwc__otg__regs_8h.html#a093dbf54151ef01db550174a2a4ad41">00222</a> <span class="preprocessor">#define DWC_GAHBCFG_GLBINT_ENABLE               1</span>
+<a name="l00223"></a>00223 <span class="preprocessor"></span>
+<a name="l00224"></a><a class="code" href="uniongahbcfg__data.html#b8f9a94aa77eb5abc379c438bf68f3d0">00224</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongahbcfg__data.html#b8f9a94aa77eb5abc379c438bf68f3d0">hburstlen</a>:4;
+<a name="l00225"></a><a class="code" href="dwc__otg__regs_8h.html#8dceb2d2defa2395d00d9a41d2ce9c2b">00225</a> <span class="preprocessor">#define DWC_GAHBCFG_INT_DMA_BURST_SINGLE        0</span>
+<a name="l00226"></a><a class="code" href="dwc__otg__regs_8h.html#e817b2bec10af4c5e95f10a78e031bcc">00226</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_GAHBCFG_INT_DMA_BURST_INCR          1</span>
+<a name="l00227"></a><a class="code" href="dwc__otg__regs_8h.html#f3ed2114e59350a94162f596461c758f">00227</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_GAHBCFG_INT_DMA_BURST_INCR4         3</span>
+<a name="l00228"></a><a class="code" href="dwc__otg__regs_8h.html#7494f8fa74d6526d38867d7c8b254183">00228</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_GAHBCFG_INT_DMA_BURST_INCR8         5</span>
+<a name="l00229"></a><a class="code" href="dwc__otg__regs_8h.html#07f5766941fd10e92ed221d37a758f4f">00229</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_GAHBCFG_INT_DMA_BURST_INCR16        7</span>
+<a name="l00230"></a>00230 <span class="preprocessor"></span>
+<a name="l00231"></a><a class="code" href="uniongahbcfg__data.html#f39c07c45326af38a267b0e308496b5c">00231</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongahbcfg__data.html#f39c07c45326af38a267b0e308496b5c">dmaenable</a>:1;
+<a name="l00232"></a><a class="code" href="dwc__otg__regs_8h.html#15510bbfb4d9729c5b5a7dc9ff2ff741">00232</a> <span class="preprocessor">#define DWC_GAHBCFG_DMAENABLE                   1</span>
+<a name="l00233"></a><a class="code" href="uniongahbcfg__data.html#dbd9a753c076249c2d9e1c6d917194e4">00233</a> <span class="preprocessor"></span>                <span class="keywordtype">unsigned</span> <a class="code" href="uniongahbcfg__data.html#dbd9a753c076249c2d9e1c6d917194e4">reserved</a>:1;
+<a name="l00234"></a><a class="code" href="uniongahbcfg__data.html#00758ec639d12cc80fd98b1a6526c454">00234</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongahbcfg__data.html#00758ec639d12cc80fd98b1a6526c454">nptxfemplvl_txfemplvl</a>:1;
+<a name="l00235"></a><a class="code" href="uniongahbcfg__data.html#e45b68a6e6e681e58d70fd8e70f9542f">00235</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongahbcfg__data.html#e45b68a6e6e681e58d70fd8e70f9542f">ptxfemplvl</a>:1;
+<a name="l00236"></a><a class="code" href="dwc__otg__regs_8h.html#bed45675c271744db00ee5445383c1dd">00236</a> <span class="preprocessor">#define DWC_GAHBCFG_TXFEMPTYLVL_EMPTY           1</span>
+<a name="l00237"></a><a class="code" href="dwc__otg__regs_8h.html#0ec8d38e3f85707561b300ae1b339b71">00237</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY       0</span>
+<a name="l00238"></a><a class="code" href="uniongahbcfg__data.html#f5fcb22471add360aa70f3512dab7ecd">00238</a> <span class="preprocessor"></span>                <span class="keywordtype">unsigned</span> <a class="code" href="uniongahbcfg__data.html#f5fcb22471add360aa70f3512dab7ecd">reserved9_31</a>:23;
+<a name="l00239"></a>00239         } <a class="code" href="uniongahbcfg__data.html#aa9726048597c5bb54ea38eda976e1a4">b</a>;
+<a name="l00240"></a>00240 } <a class="code" href="uniongahbcfg__data.html">gahbcfg_data_t</a>;
+<a name="l00241"></a>00241 
+<a name="l00247"></a><a class="code" href="uniongusbcfg__data.html">00247</a> <span class="keyword">typedef</span> <span class="keyword">union </span><a class="code" href="uniongusbcfg__data.html">gusbcfg_data</a> {
+<a name="l00249"></a><a class="code" href="uniongusbcfg__data.html#c3d8f2d95fd61a172eb108cb72a85b47">00249</a>         uint32_t <a class="code" href="uniongusbcfg__data.html#c3d8f2d95fd61a172eb108cb72a85b47">d32</a>;
+<a name="l00251"></a>00251         <span class="keyword">struct </span>{
+<a name="l00252"></a><a class="code" href="uniongusbcfg__data.html#5dd00ef14661fce822a6ece15cf16799">00252</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongusbcfg__data.html#5dd00ef14661fce822a6ece15cf16799">toutcal</a>:3;
+<a name="l00253"></a><a class="code" href="uniongusbcfg__data.html#f5e1a41cbdf6ae4b30a929ff3de8c99c">00253</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongusbcfg__data.html#f5e1a41cbdf6ae4b30a929ff3de8c99c">phyif</a>:1;
+<a name="l00254"></a><a class="code" href="uniongusbcfg__data.html#f86631568e6d3682cdba6482608bdcfe">00254</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongusbcfg__data.html#f86631568e6d3682cdba6482608bdcfe">ulpi_utmi_sel</a>:1;
+<a name="l00255"></a><a class="code" href="uniongusbcfg__data.html#8f23ebcf05c1bc48b4e406e98d828f78">00255</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongusbcfg__data.html#8f23ebcf05c1bc48b4e406e98d828f78">fsintf</a>:1;
+<a name="l00256"></a><a class="code" href="uniongusbcfg__data.html#6680455bce7433ccec13377a20912e04">00256</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongusbcfg__data.html#6680455bce7433ccec13377a20912e04">physel</a>:1;
+<a name="l00257"></a><a class="code" href="uniongusbcfg__data.html#e6dc05942f880adfaee600bc9e0ba33b">00257</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongusbcfg__data.html#e6dc05942f880adfaee600bc9e0ba33b">ddrsel</a>:1;
+<a name="l00258"></a><a class="code" href="uniongusbcfg__data.html#44485a787b8a386fadae801869ce7810">00258</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongusbcfg__data.html#44485a787b8a386fadae801869ce7810">srpcap</a>:1;
+<a name="l00259"></a><a class="code" href="uniongusbcfg__data.html#71b6330c5ccf1d21ebf79a0a829612b5">00259</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongusbcfg__data.html#71b6330c5ccf1d21ebf79a0a829612b5">hnpcap</a>:1;
+<a name="l00260"></a><a class="code" href="uniongusbcfg__data.html#d3e238db709189683bc41db2a67e9d61">00260</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongusbcfg__data.html#d3e238db709189683bc41db2a67e9d61">usbtrdtim</a>:4;
+<a name="l00261"></a><a class="code" href="uniongusbcfg__data.html#3ac9a67298febe31dc67c802a7f77f0a">00261</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongusbcfg__data.html#3ac9a67298febe31dc67c802a7f77f0a">nptxfrwnden</a>:1;
+<a name="l00262"></a><a class="code" href="uniongusbcfg__data.html#9e4bac4a0ef0a045f97792f68c5f35df">00262</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongusbcfg__data.html#9e4bac4a0ef0a045f97792f68c5f35df">phylpwrclksel</a>:1;
+<a name="l00263"></a><a class="code" href="uniongusbcfg__data.html#ef6e00f543156d1af19662c3ee86830d">00263</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongusbcfg__data.html#ef6e00f543156d1af19662c3ee86830d">otgutmifssel</a>:1;
+<a name="l00264"></a><a class="code" href="uniongusbcfg__data.html#de6d061bf2d0d8c909e6f7d701977b73">00264</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongusbcfg__data.html#de6d061bf2d0d8c909e6f7d701977b73">ulpi_fsls</a>:1;
+<a name="l00265"></a><a class="code" href="uniongusbcfg__data.html#404cb37d84dd990f4df89fc904bb7a63">00265</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongusbcfg__data.html#404cb37d84dd990f4df89fc904bb7a63">ulpi_auto_res</a>:1;
+<a name="l00266"></a><a class="code" href="uniongusbcfg__data.html#017fa2eb1df13d0917ffc6b243e5064c">00266</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongusbcfg__data.html#017fa2eb1df13d0917ffc6b243e5064c">ulpi_clk_sus_m</a>:1;
+<a name="l00267"></a><a class="code" href="uniongusbcfg__data.html#f4784a3028f221e2aed6138ecef53048">00267</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongusbcfg__data.html#f4784a3028f221e2aed6138ecef53048">ulpi_ext_vbus_drv</a>:1;
+<a name="l00268"></a><a class="code" href="uniongusbcfg__data.html#b71576ecb647b9d81aa8c9b45c9fe14d">00268</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongusbcfg__data.html#b71576ecb647b9d81aa8c9b45c9fe14d">ulpi_int_vbus_indicator</a>:1;
+<a name="l00269"></a><a class="code" href="uniongusbcfg__data.html#d075f50f1d962c57ff491291f66f1778">00269</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongusbcfg__data.html#d075f50f1d962c57ff491291f66f1778">term_sel_dl_pulse</a>:1;
+<a name="l00270"></a><a class="code" href="uniongusbcfg__data.html#b6472dd64884f1b91bb5e7f27cfff97e">00270</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongusbcfg__data.html#b6472dd64884f1b91bb5e7f27cfff97e">reserved23_25</a>:3;
+<a name="l00271"></a><a class="code" href="uniongusbcfg__data.html#b729e853539aafb4bab1e4e9ac57916a">00271</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongusbcfg__data.html#b729e853539aafb4bab1e4e9ac57916a">ic_usb_cap</a>:1;
+<a name="l00272"></a><a class="code" href="uniongusbcfg__data.html#6805b1ea875bbb9cd31e877fd66c8559">00272</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongusbcfg__data.html#6805b1ea875bbb9cd31e877fd66c8559">ic_traffic_pull_remove</a>:1;
+<a name="l00273"></a><a class="code" href="uniongusbcfg__data.html#581b301bfa1951e1bd8ee20aa7256dc2">00273</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongusbcfg__data.html#581b301bfa1951e1bd8ee20aa7256dc2">tx_end_delay</a>:1;
+<a name="l00274"></a><a class="code" href="uniongusbcfg__data.html#eccc976f536ce6742e0df01df7d8b095">00274</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongusbcfg__data.html#eccc976f536ce6742e0df01df7d8b095">reserved29_31</a>:3;
+<a name="l00275"></a>00275         } <a class="code" href="uniongusbcfg__data.html#1dab81bf7260b1e23f97298c34abea06">b</a>;
+<a name="l00276"></a>00276 } <a class="code" href="uniongusbcfg__data.html">gusbcfg_data_t</a>;
+<a name="l00277"></a>00277 
+<a name="l00283"></a><a class="code" href="unionglpmctl__data.html">00283</a> <span class="keyword">typedef</span> <span class="keyword">union </span><a class="code" href="unionglpmctl__data.html">glpmctl_data</a> {
+<a name="l00285"></a><a class="code" href="unionglpmctl__data.html#cd41461734ff898209bfb64057ef2eb8">00285</a>         uint32_t <a class="code" href="unionglpmctl__data.html#cd41461734ff898209bfb64057ef2eb8">d32</a>;
+<a name="l00287"></a>00287         <span class="keyword">struct </span>{
+<a name="l00292"></a><a class="code" href="unionglpmctl__data.html#cf0a4cfcd158e41eb3811048e723890f">00292</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionglpmctl__data.html#cf0a4cfcd158e41eb3811048e723890f">lpm_cap_en</a>:1;
+<a name="l00297"></a><a class="code" href="unionglpmctl__data.html#1898203022af680f08036de89e86e4b0">00297</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionglpmctl__data.html#1898203022af680f08036de89e86e4b0">appl_resp</a>:1;
+<a name="l00306"></a><a class="code" href="unionglpmctl__data.html#176b788935d1952606f523f2718b3512">00306</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionglpmctl__data.html#176b788935d1952606f523f2718b3512">hird</a>:4;
+<a name="l00315"></a><a class="code" href="unionglpmctl__data.html#60a9c2e233e3ee15a80ae80b27d09f8b">00315</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionglpmctl__data.html#60a9c2e233e3ee15a80ae80b27d09f8b">rem_wkup_en</a>:1;
+<a name="l00320"></a><a class="code" href="unionglpmctl__data.html#63e912a05b8d29872b92263ca616fec8">00320</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionglpmctl__data.html#63e912a05b8d29872b92263ca616fec8">en_utmi_sleep</a>:1;
+<a name="l00323"></a><a class="code" href="unionglpmctl__data.html#e2ceea4bfe468c7b3c800235d7ffd5d2">00323</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionglpmctl__data.html#e2ceea4bfe468c7b3c800235d7ffd5d2">hird_thres</a>:5;
+<a name="l00334"></a><a class="code" href="unionglpmctl__data.html#752c00118919fce173804931b058c5a8">00334</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionglpmctl__data.html#752c00118919fce173804931b058c5a8">lpm_resp</a>:2;
+<a name="l00339"></a><a class="code" href="unionglpmctl__data.html#241ff25a215f16ac29b3bb6d9f4943ed">00339</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionglpmctl__data.html#241ff25a215f16ac29b3bb6d9f4943ed">prt_sleep_sts</a>:1;
+<a name="l00344"></a><a class="code" href="unionglpmctl__data.html#3b87473445c87d173f350828a60cacd8">00344</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionglpmctl__data.html#3b87473445c87d173f350828a60cacd8">sleep_state_resumeok</a>:1;
+<a name="l00350"></a><a class="code" href="unionglpmctl__data.html#7e6bb2a40d4e0bdfed6f868b1f670235">00350</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionglpmctl__data.html#7e6bb2a40d4e0bdfed6f868b1f670235">lpm_chan_index</a>:4;
+<a name="l00355"></a><a class="code" href="unionglpmctl__data.html#be75ed525bcfe231cd9bda6a1b8594f6">00355</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionglpmctl__data.html#be75ed525bcfe231cd9bda6a1b8594f6">retry_count</a>:3;
+<a name="l00361"></a><a class="code" href="unionglpmctl__data.html#0651e486c5502489b2cac633bb00c78e">00361</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionglpmctl__data.html#0651e486c5502489b2cac633bb00c78e">send_lpm</a>:1;
+<a name="l00366"></a><a class="code" href="unionglpmctl__data.html#67ddd4b3576e04a06d5fff707c8bbf18">00366</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionglpmctl__data.html#67ddd4b3576e04a06d5fff707c8bbf18">retry_count_sts</a>:3;
+<a name="l00367"></a><a class="code" href="unionglpmctl__data.html#b0b1d669c4161e9ffb1454d85bd243d2">00367</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionglpmctl__data.html#b0b1d669c4161e9ffb1454d85bd243d2">reserved28_29</a>:2;
+<a name="l00375"></a><a class="code" href="unionglpmctl__data.html#76c64ead46647c39aa76edebf2f63444">00375</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionglpmctl__data.html#76c64ead46647c39aa76edebf2f63444">hsic_connect</a>:1;
+<a name="l00379"></a><a class="code" href="unionglpmctl__data.html#f664636955d9476647937d13d48f068e">00379</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionglpmctl__data.html#f664636955d9476647937d13d48f068e">inv_sel_hsic</a>:1;
+<a name="l00380"></a>00380         } <a class="code" href="unionglpmctl__data.html#bd3cc34c338226ff1cd89448f7590ff1">b</a>;
+<a name="l00381"></a>00381 } <a class="code" href="unionglpmctl__data.html">glpmcfg_data_t</a>;
+<a name="l00382"></a>00382 
+<a name="l00388"></a><a class="code" href="uniongrstctl__data.html">00388</a> <span class="keyword">typedef</span> <span class="keyword">union </span><a class="code" href="uniongrstctl__data.html">grstctl_data</a> {
+<a name="l00390"></a><a class="code" href="uniongrstctl__data.html#d89d99c95bd5177fbd879d38963d3e62">00390</a>         uint32_t <a class="code" href="uniongrstctl__data.html#d89d99c95bd5177fbd879d38963d3e62">d32</a>;
+<a name="l00392"></a>00392         <span class="keyword">struct </span>{
+<a name="l00428"></a><a class="code" href="uniongrstctl__data.html#82df3462742f67d18b2964fafc0d9c02">00428</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongrstctl__data.html#82df3462742f67d18b2964fafc0d9c02">csftrst</a>:1;
+<a name="l00435"></a><a class="code" href="uniongrstctl__data.html#7418a85aa4ffaa77c49f046202c97c01">00435</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongrstctl__data.html#7418a85aa4ffaa77c49f046202c97c01">hsftrst</a>:1;
+<a name="l00444"></a><a class="code" href="uniongrstctl__data.html#6bf39518efe967ed4c7f9db6d3811a90">00444</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongrstctl__data.html#6bf39518efe967ed4c7f9db6d3811a90">hstfrm</a>:1;
+<a name="l00448"></a><a class="code" href="uniongrstctl__data.html#259049fa7991ecad9ca1595763b636f9">00448</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongrstctl__data.html#259049fa7991ecad9ca1595763b636f9">intknqflsh</a>:1;
+<a name="l00463"></a><a class="code" href="uniongrstctl__data.html#88467c1f0580f4837d229d85b35c97a7">00463</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongrstctl__data.html#88467c1f0580f4837d229d85b35c97a7">rxfflsh</a>:1;
+<a name="l00478"></a><a class="code" href="uniongrstctl__data.html#8a5fcfc953bd0ba61beb36739c70b0ef">00478</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongrstctl__data.html#8a5fcfc953bd0ba61beb36739c70b0ef">txfflsh</a>:1;
+<a name="l00479"></a>00479 
+<a name="l00495"></a><a class="code" href="uniongrstctl__data.html#d074ddfa3331eeb6d088e35f4f627481">00495</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongrstctl__data.html#d074ddfa3331eeb6d088e35f4f627481">txfnum</a>:5;
+<a name="l00497"></a><a class="code" href="uniongrstctl__data.html#8c0515740955d128e3c8dd51ca5417ea">00497</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongrstctl__data.html#8c0515740955d128e3c8dd51ca5417ea">reserved11_29</a>:19;
+<a name="l00500"></a><a class="code" href="uniongrstctl__data.html#13e11d4c86ca39b8edf3c1878708fad1">00500</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongrstctl__data.html#13e11d4c86ca39b8edf3c1878708fad1">dmareq</a>:1;
+<a name="l00503"></a><a class="code" href="uniongrstctl__data.html#587c5ec6713e2626db517105ab9aea3e">00503</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongrstctl__data.html#587c5ec6713e2626db517105ab9aea3e">ahbidle</a>:1;
+<a name="l00504"></a>00504         } <a class="code" href="uniongrstctl__data.html#7907ac8831a2f72dec59592a093871e3">b</a>;
+<a name="l00505"></a>00505 } <a class="code" href="uniongrstctl__data.html">grstctl_t</a>;
+<a name="l00506"></a>00506 
+<a name="l00512"></a><a class="code" href="uniongintmsk__data.html">00512</a> <span class="keyword">typedef</span> <span class="keyword">union </span><a class="code" href="uniongintmsk__data.html">gintmsk_data</a> {
+<a name="l00514"></a><a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">00514</a>         uint32_t <a class="code" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a>;
+<a name="l00516"></a>00516         <span class="keyword">struct </span>{
+<a name="l00517"></a><a class="code" href="uniongintmsk__data.html#74efe8733ca57d2b6147f8d42178c95c">00517</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintmsk__data.html#74efe8733ca57d2b6147f8d42178c95c">reserved0</a>:1;
+<a name="l00518"></a><a class="code" href="uniongintmsk__data.html#f62315fe9de8bb3bc371cb0a51927496">00518</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintmsk__data.html#f62315fe9de8bb3bc371cb0a51927496">modemismatch</a>:1;
+<a name="l00519"></a><a class="code" href="uniongintmsk__data.html#6c9d578034af4f2ca08447fdac22ff88">00519</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintmsk__data.html#6c9d578034af4f2ca08447fdac22ff88">otgintr</a>:1;
+<a name="l00520"></a><a class="code" href="uniongintmsk__data.html#d9cb28e92090a5da3c00d35768d90c82">00520</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintmsk__data.html#d9cb28e92090a5da3c00d35768d90c82">sofintr</a>:1;
+<a name="l00521"></a><a class="code" href="uniongintmsk__data.html#83db45f92a3a692d79199e1a850c2a62">00521</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintmsk__data.html#83db45f92a3a692d79199e1a850c2a62">rxstsqlvl</a>:1;
+<a name="l00522"></a><a class="code" href="uniongintmsk__data.html#2c395e7bef31a4d9b2d1a3257c601be4">00522</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintmsk__data.html#2c395e7bef31a4d9b2d1a3257c601be4">nptxfempty</a>:1;
+<a name="l00523"></a><a class="code" href="uniongintmsk__data.html#83a6fb180ef8b18faf8d02ba8b50c841">00523</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintmsk__data.html#83a6fb180ef8b18faf8d02ba8b50c841">ginnakeff</a>:1;
+<a name="l00524"></a><a class="code" href="uniongintmsk__data.html#1a47902a93203910433a35fab3f5b8a1">00524</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintmsk__data.html#1a47902a93203910433a35fab3f5b8a1">goutnakeff</a>:1;
+<a name="l00525"></a><a class="code" href="uniongintmsk__data.html#b82d0335e1b637612cc3d8442d9e52cc">00525</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintmsk__data.html#b82d0335e1b637612cc3d8442d9e52cc">reserved8</a>:1;
+<a name="l00526"></a><a class="code" href="uniongintmsk__data.html#92dd84dd80b06e949668f85e6b6b7086">00526</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintmsk__data.html#92dd84dd80b06e949668f85e6b6b7086">i2cintr</a>:1;
+<a name="l00527"></a><a class="code" href="uniongintmsk__data.html#0c455b6461081720584a8acc4e0e18a5">00527</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintmsk__data.html#0c455b6461081720584a8acc4e0e18a5">erlysuspend</a>:1;
+<a name="l00528"></a><a class="code" href="uniongintmsk__data.html#3b93f1ae00dcd1dcc4d6d19547f26b56">00528</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintmsk__data.html#3b93f1ae00dcd1dcc4d6d19547f26b56">usbsuspend</a>:1;
+<a name="l00529"></a><a class="code" href="uniongintmsk__data.html#de79426e6a5436e34cf4b1ac42a72ee6">00529</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintmsk__data.html#de79426e6a5436e34cf4b1ac42a72ee6">usbreset</a>:1;
+<a name="l00530"></a><a class="code" href="uniongintmsk__data.html#895f1c1537debec62da4fd248249859c">00530</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintmsk__data.html#895f1c1537debec62da4fd248249859c">enumdone</a>:1;
+<a name="l00531"></a><a class="code" href="uniongintmsk__data.html#3a0a75b129ccdaed6d98d1982b374d52">00531</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintmsk__data.html#3a0a75b129ccdaed6d98d1982b374d52">isooutdrop</a>:1;
+<a name="l00532"></a><a class="code" href="uniongintmsk__data.html#aeb61a24f3c50caacfb8fe523c85768a">00532</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintmsk__data.html#aeb61a24f3c50caacfb8fe523c85768a">eopframe</a>:1;
+<a name="l00533"></a><a class="code" href="uniongintmsk__data.html#e5f7668978b7c4898dccda363be492ae">00533</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintmsk__data.html#e5f7668978b7c4898dccda363be492ae">reserved16</a>:1;
+<a name="l00534"></a><a class="code" href="uniongintmsk__data.html#3a21d0006e144647b43ef910b9183da9">00534</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintmsk__data.html#3a21d0006e144647b43ef910b9183da9">epmismatch</a>:1;
+<a name="l00535"></a><a class="code" href="uniongintmsk__data.html#bcae4c9dd3d0f153b379dfbc6c830fc5">00535</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintmsk__data.html#bcae4c9dd3d0f153b379dfbc6c830fc5">inepintr</a>:1;
+<a name="l00536"></a><a class="code" href="uniongintmsk__data.html#d48fe24e3e91bc1bcbc1c790c1b67f96">00536</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintmsk__data.html#d48fe24e3e91bc1bcbc1c790c1b67f96">outepintr</a>:1;
+<a name="l00537"></a><a class="code" href="uniongintmsk__data.html#3f9eeb4c73291b7943b7187ba34c90f4">00537</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintmsk__data.html#3f9eeb4c73291b7943b7187ba34c90f4">incomplisoin</a>:1;
+<a name="l00538"></a><a class="code" href="uniongintmsk__data.html#c63c107070bd7623766e39cd06ec7c97">00538</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintmsk__data.html#c63c107070bd7623766e39cd06ec7c97">incomplisoout</a>:1;
+<a name="l00539"></a><a class="code" href="uniongintmsk__data.html#1cc5065ff41bfe410b53631392f0e2a7">00539</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintmsk__data.html#1cc5065ff41bfe410b53631392f0e2a7">reserved22_23</a>:2;
+<a name="l00540"></a><a class="code" href="uniongintmsk__data.html#c907c60cbc7b157e730b053b40f4a2b3">00540</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintmsk__data.html#c907c60cbc7b157e730b053b40f4a2b3">portintr</a>:1;
+<a name="l00541"></a><a class="code" href="uniongintmsk__data.html#3a4c193d8ff48291809dcd3ccb7c0585">00541</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintmsk__data.html#3a4c193d8ff48291809dcd3ccb7c0585">hcintr</a>:1;
+<a name="l00542"></a><a class="code" href="uniongintmsk__data.html#3b52444894e041c660c146af2178272f">00542</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintmsk__data.html#3b52444894e041c660c146af2178272f">ptxfempty</a>:1;
+<a name="l00543"></a><a class="code" href="uniongintmsk__data.html#24f9f89b33866c5dc7b16588bc94e103">00543</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintmsk__data.html#24f9f89b33866c5dc7b16588bc94e103">lpmtranrcvd</a>:1;
+<a name="l00544"></a><a class="code" href="uniongintmsk__data.html#ade723f4f136cfa884e5bf536d913f14">00544</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintmsk__data.html#ade723f4f136cfa884e5bf536d913f14">conidstschng</a>:1;
+<a name="l00545"></a><a class="code" href="uniongintmsk__data.html#0ff313bfc712a2f3d71bc1a5f1a17ce2">00545</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintmsk__data.html#0ff313bfc712a2f3d71bc1a5f1a17ce2">disconnect</a>:1;
+<a name="l00546"></a><a class="code" href="uniongintmsk__data.html#aabb586a72e2a76982bfaa780e482212">00546</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintmsk__data.html#aabb586a72e2a76982bfaa780e482212">sessreqintr</a>:1;
+<a name="l00547"></a><a class="code" href="uniongintmsk__data.html#d3cde0fd62a006ec3f5db615f1e62da5">00547</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintmsk__data.html#d3cde0fd62a006ec3f5db615f1e62da5">wkupintr</a>:1;
+<a name="l00548"></a>00548         } <a class="code" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a>;
+<a name="l00549"></a>00549 } <a class="code" href="uniongintmsk__data.html">gintmsk_data_t</a>;
+<a name="l00555"></a><a class="code" href="uniongintsts__data.html">00555</a> <span class="keyword">typedef</span> <span class="keyword">union </span><a class="code" href="uniongintsts__data.html">gintsts_data</a> {
+<a name="l00557"></a><a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">00557</a>         uint32_t <a class="code" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a>;
+<a name="l00558"></a><a class="code" href="dwc__otg__regs_8h.html#8cd1d59e0700e5b528deebdea7a7ac76">00558</a> <span class="preprocessor">#define DWC_SOF_INTR_MASK 0x0008</span>
+<a name="l00559"></a>00559 <span class="preprocessor"></span>
+<a name="l00560"></a>00560         <span class="keyword">struct </span>{
+<a name="l00561"></a><a class="code" href="dwc__otg__regs_8h.html#dc3fa334f676024ecd75f63f885d4ec3">00561</a> <span class="preprocessor">#define DWC_HOST_MODE 1</span>
+<a name="l00562"></a><a class="code" href="uniongintsts__data.html#f0815c8bea0a37c98b12a08481b2980c">00562</a> <span class="preprocessor"></span>                <span class="keywordtype">unsigned</span> <a class="code" href="uniongintsts__data.html#f0815c8bea0a37c98b12a08481b2980c">curmode</a>:1;
+<a name="l00563"></a><a class="code" href="uniongintsts__data.html#5fda463a80eb6927b2b875d64e8a0753">00563</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintsts__data.html#5fda463a80eb6927b2b875d64e8a0753">modemismatch</a>:1;
+<a name="l00564"></a><a class="code" href="uniongintsts__data.html#7934c11c40b0b60137edbdaa2be45542">00564</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintsts__data.html#7934c11c40b0b60137edbdaa2be45542">otgintr</a>:1;
+<a name="l00565"></a><a class="code" href="uniongintsts__data.html#3f6ba377d6b1449884bb4da1b155c61b">00565</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintsts__data.html#3f6ba377d6b1449884bb4da1b155c61b">sofintr</a>:1;
+<a name="l00566"></a><a class="code" href="uniongintsts__data.html#7595576956c3a0ced9ea387880943012">00566</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintsts__data.html#7595576956c3a0ced9ea387880943012">rxstsqlvl</a>:1;
+<a name="l00567"></a><a class="code" href="uniongintsts__data.html#adebf5ff5bdf69a2bcf0bd4b2ba55ef4">00567</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintsts__data.html#adebf5ff5bdf69a2bcf0bd4b2ba55ef4">nptxfempty</a>:1;
+<a name="l00568"></a><a class="code" href="uniongintsts__data.html#15a2e362768704ab6143fea33fc8755b">00568</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintsts__data.html#15a2e362768704ab6143fea33fc8755b">ginnakeff</a>:1;
+<a name="l00569"></a><a class="code" href="uniongintsts__data.html#5fd87ed0462f444df968567f310488f7">00569</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintsts__data.html#5fd87ed0462f444df968567f310488f7">goutnakeff</a>:1;
+<a name="l00570"></a><a class="code" href="uniongintsts__data.html#704fa166643640f4c9b6c6de037d860a">00570</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintsts__data.html#704fa166643640f4c9b6c6de037d860a">reserved8</a>:1;
+<a name="l00571"></a><a class="code" href="uniongintsts__data.html#2e8bd51ad285fd46db48f9fb5bbb7993">00571</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintsts__data.html#2e8bd51ad285fd46db48f9fb5bbb7993">i2cintr</a>:1;
+<a name="l00572"></a><a class="code" href="uniongintsts__data.html#2659c4ea7b295a089ee498b21b44992b">00572</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintsts__data.html#2659c4ea7b295a089ee498b21b44992b">erlysuspend</a>:1;
+<a name="l00573"></a><a class="code" href="uniongintsts__data.html#de67a7536cdb9305e24f05d771708bce">00573</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintsts__data.html#de67a7536cdb9305e24f05d771708bce">usbsuspend</a>:1;
+<a name="l00574"></a><a class="code" href="uniongintsts__data.html#76926be659d963c79dbcec91e25ce8ed">00574</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintsts__data.html#76926be659d963c79dbcec91e25ce8ed">usbreset</a>:1;
+<a name="l00575"></a><a class="code" href="uniongintsts__data.html#84e707787b50ee3867786c8e0995f41e">00575</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintsts__data.html#84e707787b50ee3867786c8e0995f41e">enumdone</a>:1;
+<a name="l00576"></a><a class="code" href="uniongintsts__data.html#e6e931e1d6226dc110a98cd42c9a8e5f">00576</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintsts__data.html#e6e931e1d6226dc110a98cd42c9a8e5f">isooutdrop</a>:1;
+<a name="l00577"></a><a class="code" href="uniongintsts__data.html#a731c93eb9e131fadde92da363a85527">00577</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintsts__data.html#a731c93eb9e131fadde92da363a85527">eopframe</a>:1;
+<a name="l00578"></a><a class="code" href="uniongintsts__data.html#912b165c3b774baedd294b678df9c2c0">00578</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintsts__data.html#912b165c3b774baedd294b678df9c2c0">intokenrx</a>:1;
+<a name="l00579"></a><a class="code" href="uniongintsts__data.html#c30e01457b826afc318e5d76e9dfdded">00579</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintsts__data.html#c30e01457b826afc318e5d76e9dfdded">epmismatch</a>:1;
+<a name="l00580"></a><a class="code" href="uniongintsts__data.html#e4e48a2a194cf95d934800a85c12784f">00580</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintsts__data.html#e4e48a2a194cf95d934800a85c12784f">inepint</a>:1;
+<a name="l00581"></a><a class="code" href="uniongintsts__data.html#58c08d29fa4b120748eb01b0d989facf">00581</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintsts__data.html#58c08d29fa4b120748eb01b0d989facf">outepintr</a>:1;
+<a name="l00582"></a><a class="code" href="uniongintsts__data.html#6a2b4a287af4632cec2207fe6fb91e86">00582</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintsts__data.html#6a2b4a287af4632cec2207fe6fb91e86">incomplisoin</a>:1;
+<a name="l00583"></a><a class="code" href="uniongintsts__data.html#519e2237cad3f43ebb7665e8d24c0180">00583</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintsts__data.html#519e2237cad3f43ebb7665e8d24c0180">incomplisoout</a>:1;
+<a name="l00584"></a><a class="code" href="uniongintsts__data.html#dbb68c65fa6a899acf2bf74dac94790e">00584</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintsts__data.html#dbb68c65fa6a899acf2bf74dac94790e">reserved22_23</a>:2;
+<a name="l00585"></a><a class="code" href="uniongintsts__data.html#7490e48c2c93d20c182f00161f18b8e5">00585</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintsts__data.html#7490e48c2c93d20c182f00161f18b8e5">portintr</a>:1;
+<a name="l00586"></a><a class="code" href="uniongintsts__data.html#e02f1a50b20ed1c4248fd76e155147e8">00586</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintsts__data.html#e02f1a50b20ed1c4248fd76e155147e8">hcintr</a>:1;
+<a name="l00587"></a><a class="code" href="uniongintsts__data.html#54ed752629e9b8916507beca28d76162">00587</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintsts__data.html#54ed752629e9b8916507beca28d76162">ptxfempty</a>:1;
+<a name="l00588"></a><a class="code" href="uniongintsts__data.html#50e73e91df681c835de50f8276058829">00588</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintsts__data.html#50e73e91df681c835de50f8276058829">lpmtranrcvd</a>:1;
+<a name="l00589"></a><a class="code" href="uniongintsts__data.html#86b8b53e53486db96a8faf6307c248df">00589</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintsts__data.html#86b8b53e53486db96a8faf6307c248df">conidstschng</a>:1;
+<a name="l00590"></a><a class="code" href="uniongintsts__data.html#45d8d681263dcfc7c2b6cf30ee689f28">00590</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintsts__data.html#45d8d681263dcfc7c2b6cf30ee689f28">disconnect</a>:1;
+<a name="l00591"></a><a class="code" href="uniongintsts__data.html#c8b14c042daab677d0c4ae691d573995">00591</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintsts__data.html#c8b14c042daab677d0c4ae691d573995">sessreqintr</a>:1;
+<a name="l00592"></a><a class="code" href="uniongintsts__data.html#d2e845fd68f2e8abe6b7445dbde9d2a4">00592</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongintsts__data.html#d2e845fd68f2e8abe6b7445dbde9d2a4">wkupintr</a>:1;
+<a name="l00593"></a>00593         } <a class="code" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a>;
+<a name="l00594"></a>00594 } <a class="code" href="uniongintsts__data.html">gintsts_data_t</a>;
+<a name="l00595"></a>00595 
+<a name="l00601"></a><a class="code" href="uniondevice__grxsts__data.html">00601</a> <span class="keyword">typedef</span> <span class="keyword">union </span><a class="code" href="uniondevice__grxsts__data.html">device_grxsts_data</a> {
+<a name="l00603"></a><a class="code" href="uniondevice__grxsts__data.html#9d454f39c05e23d376dfb0069d933986">00603</a>         uint32_t <a class="code" href="uniondevice__grxsts__data.html#9d454f39c05e23d376dfb0069d933986">d32</a>;
+<a name="l00605"></a>00605         <span class="keyword">struct </span>{
+<a name="l00606"></a><a class="code" href="uniondevice__grxsts__data.html#d91e207bb8fb6e20652e6ad2474aec8e">00606</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondevice__grxsts__data.html#d91e207bb8fb6e20652e6ad2474aec8e">epnum</a>:4;
+<a name="l00607"></a><a class="code" href="uniondevice__grxsts__data.html#6162a5f256d8041bc3d1d1071e999107">00607</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondevice__grxsts__data.html#6162a5f256d8041bc3d1d1071e999107">bcnt</a>:11;
+<a name="l00608"></a><a class="code" href="uniondevice__grxsts__data.html#d0f4716b612b04fde649a2f689ea5b88">00608</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondevice__grxsts__data.html#d0f4716b612b04fde649a2f689ea5b88">dpid</a>:2;
+<a name="l00609"></a>00609 
+<a name="l00610"></a><a class="code" href="dwc__otg__regs_8h.html#93cbb84c3631af89d282fb1b406594f5">00610</a> <span class="preprocessor">#define DWC_STS_DATA_UPDT               0x2     // OUT Data Packet</span>
+<a name="l00611"></a><a class="code" href="dwc__otg__regs_8h.html#53a6a9dd332c8a15f505cd0027fb4c86">00611</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_STS_XFER_COMP               0x3     // OUT Data Transfer Complete</span>
+<a name="l00612"></a>00612 <span class="preprocessor"></span>
+<a name="l00613"></a><a class="code" href="dwc__otg__regs_8h.html#de6ad4d62ad4debd7d97e27ea68bbe7f">00613</a> <span class="preprocessor">#define DWC_DSTS_GOUT_NAK               0x1     // Global OUT NAK</span>
+<a name="l00614"></a><a class="code" href="dwc__otg__regs_8h.html#2f7181f56123a3d16d78e204ab6e5e96">00614</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_DSTS_SETUP_COMP             0x4     // Setup Phase Complete</span>
+<a name="l00615"></a><a class="code" href="dwc__otg__regs_8h.html#416a63dc7ef9b792d21b01cc257bba43">00615</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_DSTS_SETUP_UPDT 0x6 // SETUP Packet</span>
+<a name="l00616"></a><a class="code" href="uniondevice__grxsts__data.html#712eb005af256f84ebfc6f3083dd1ba8">00616</a> <span class="preprocessor"></span>                <span class="keywordtype">unsigned</span> <a class="code" href="uniondevice__grxsts__data.html#712eb005af256f84ebfc6f3083dd1ba8">pktsts</a>:4;
+<a name="l00617"></a><a class="code" href="uniondevice__grxsts__data.html#f535ee62a482ec97ca61dc4954e358c6">00617</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondevice__grxsts__data.html#f535ee62a482ec97ca61dc4954e358c6">fn</a>:4;
+<a name="l00618"></a><a class="code" href="uniondevice__grxsts__data.html#95064e007a2dd525524d59af9f27eb36">00618</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondevice__grxsts__data.html#95064e007a2dd525524d59af9f27eb36">reserved</a>:7;
+<a name="l00619"></a>00619         } <a class="code" href="uniondevice__grxsts__data.html#dbcda32a5bc5e5423bcf6e01d99c7686">b</a>;
+<a name="l00620"></a>00620 } <a class="code" href="uniondevice__grxsts__data.html">device_grxsts_data_t</a>;
+<a name="l00621"></a>00621 
+<a name="l00627"></a><a class="code" href="unionhost__grxsts__data.html">00627</a> <span class="keyword">typedef</span> <span class="keyword">union </span><a class="code" href="unionhost__grxsts__data.html">host_grxsts_data</a> {
+<a name="l00629"></a><a class="code" href="unionhost__grxsts__data.html#993969735da9c3615652391aae76359a">00629</a>         uint32_t <a class="code" href="unionhost__grxsts__data.html#993969735da9c3615652391aae76359a">d32</a>;
+<a name="l00631"></a>00631         <span class="keyword">struct </span>{
+<a name="l00632"></a><a class="code" href="unionhost__grxsts__data.html#684095394d11ec74a327f945c9e678bf">00632</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhost__grxsts__data.html#684095394d11ec74a327f945c9e678bf">chnum</a>:4;
+<a name="l00633"></a><a class="code" href="unionhost__grxsts__data.html#026fd4d8ab68825fab038c083b8e9c60">00633</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhost__grxsts__data.html#026fd4d8ab68825fab038c083b8e9c60">bcnt</a>:11;
+<a name="l00634"></a><a class="code" href="unionhost__grxsts__data.html#5c4ca6a6c4a85064dd024095607a634d">00634</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhost__grxsts__data.html#5c4ca6a6c4a85064dd024095607a634d">dpid</a>:2;
+<a name="l00635"></a>00635 
+<a name="l00636"></a><a class="code" href="unionhost__grxsts__data.html#6dc2553475a56a445c6e6f319feffac8">00636</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhost__grxsts__data.html#6dc2553475a56a445c6e6f319feffac8">pktsts</a>:4;
+<a name="l00637"></a><a class="code" href="dwc__otg__regs_8h.html#d81c89ef7c3e40cfffe9ed08b7136e90">00637</a> <span class="preprocessor">#define DWC_GRXSTS_PKTSTS_IN                      0x2</span>
+<a name="l00638"></a><a class="code" href="dwc__otg__regs_8h.html#c5c019a36ea5cb66d3cb436292d8c3de">00638</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_GRXSTS_PKTSTS_IN_XFER_COMP    0x3</span>
+<a name="l00639"></a><a class="code" href="dwc__otg__regs_8h.html#63be63fa3258a785d81ded62ab27b30d">00639</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR 0x5</span>
+<a name="l00640"></a><a class="code" href="dwc__otg__regs_8h.html#a6d1e988dc17e285244c4e587440cbef">00640</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_GRXSTS_PKTSTS_CH_HALTED               0x7</span>
+<a name="l00641"></a>00641 <span class="preprocessor"></span>
+<a name="l00642"></a><a class="code" href="unionhost__grxsts__data.html#36fd3990562635838b4fce804de87d38">00642</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhost__grxsts__data.html#36fd3990562635838b4fce804de87d38">reserved</a>:11;
+<a name="l00643"></a>00643         } <a class="code" href="unionhost__grxsts__data.html#9d67ba193008dd6afa7fe613c665238d">b</a>;
+<a name="l00644"></a>00644 } <a class="code" href="unionhost__grxsts__data.html">host_grxsts_data_t</a>;
+<a name="l00645"></a>00645 
+<a name="l00651"></a><a class="code" href="unionfifosize__data.html">00651</a> <span class="keyword">typedef</span> <span class="keyword">union </span><a class="code" href="unionfifosize__data.html">fifosize_data</a> {
+<a name="l00653"></a><a class="code" href="unionfifosize__data.html#937e01b91f0a60a5aa9f6a4eaf6ce661">00653</a>         uint32_t <a class="code" href="unionfifosize__data.html#937e01b91f0a60a5aa9f6a4eaf6ce661">d32</a>;
+<a name="l00655"></a>00655         <span class="keyword">struct </span>{
+<a name="l00656"></a><a class="code" href="unionfifosize__data.html#26d78332a532cf9c0337c89edbff5f1b">00656</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionfifosize__data.html#26d78332a532cf9c0337c89edbff5f1b">startaddr</a>:16;
+<a name="l00657"></a><a class="code" href="unionfifosize__data.html#48c08d73da4d2d16d4320b93beb5ba8b">00657</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionfifosize__data.html#48c08d73da4d2d16d4320b93beb5ba8b">depth</a>:16;
+<a name="l00658"></a>00658         } <a class="code" href="unionfifosize__data.html#4f0c71e88cc54c4efa4cd4ff43334c51">b</a>;
+<a name="l00659"></a>00659 } <a class="code" href="unionfifosize__data.html">fifosize_data_t</a>;
+<a name="l00660"></a>00660 
+<a name="l00667"></a><a class="code" href="uniongnptxsts__data.html">00667</a> <span class="keyword">typedef</span> <span class="keyword">union </span><a class="code" href="uniongnptxsts__data.html">gnptxsts_data</a> {
+<a name="l00669"></a><a class="code" href="uniongnptxsts__data.html#a58b5adbe6bd0344c4f585ef6aba4672">00669</a>         uint32_t <a class="code" href="uniongnptxsts__data.html#a58b5adbe6bd0344c4f585ef6aba4672">d32</a>;
+<a name="l00671"></a>00671         <span class="keyword">struct </span>{
+<a name="l00672"></a><a class="code" href="uniongnptxsts__data.html#6c149be246bcf5ca5395f67e67648207">00672</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongnptxsts__data.html#6c149be246bcf5ca5395f67e67648207">nptxfspcavail</a>:16;
+<a name="l00673"></a><a class="code" href="uniongnptxsts__data.html#634ffd5e84bc422ddef043574d8f0957">00673</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongnptxsts__data.html#634ffd5e84bc422ddef043574d8f0957">nptxqspcavail</a>:8;
+<a name="l00684"></a><a class="code" href="uniongnptxsts__data.html#8aeca3e7350acc25b9c0623eea88bfc3">00684</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongnptxsts__data.html#8aeca3e7350acc25b9c0623eea88bfc3">nptxqtop_terminate</a>:1;
+<a name="l00685"></a><a class="code" href="uniongnptxsts__data.html#7675d024cc57442bd67d63551cb5dfcc">00685</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongnptxsts__data.html#7675d024cc57442bd67d63551cb5dfcc">nptxqtop_token</a>:2;
+<a name="l00686"></a><a class="code" href="uniongnptxsts__data.html#6f593581592d2c904db11b39f8275ed9">00686</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongnptxsts__data.html#6f593581592d2c904db11b39f8275ed9">nptxqtop_chnep</a>:4;
+<a name="l00687"></a><a class="code" href="uniongnptxsts__data.html#035aa5b790dd66e425a77291b849920f">00687</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongnptxsts__data.html#035aa5b790dd66e425a77291b849920f">reserved</a>:1;
+<a name="l00688"></a>00688         } <a class="code" href="uniongnptxsts__data.html#be1d1adf7b827616ebbbf6bf564c0738">b</a>;
+<a name="l00689"></a>00689 } <a class="code" href="uniongnptxsts__data.html">gnptxsts_data_t</a>;
+<a name="l00690"></a>00690 
+<a name="l00697"></a><a class="code" href="uniondtxfsts__data.html">00697</a> <span class="keyword">typedef</span> <span class="keyword">union </span><a class="code" href="uniondtxfsts__data.html">dtxfsts_data</a> {
+<a name="l00699"></a><a class="code" href="uniondtxfsts__data.html#684b8a9ccf83a5807e9bb3491c662c39">00699</a>         uint32_t <a class="code" href="uniondtxfsts__data.html#684b8a9ccf83a5807e9bb3491c662c39">d32</a>;
+<a name="l00701"></a>00701         <span class="keyword">struct </span>{
+<a name="l00702"></a><a class="code" href="uniondtxfsts__data.html#83db0e2dbe071694f549a383b7037b3b">00702</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondtxfsts__data.html#83db0e2dbe071694f549a383b7037b3b">txfspcavail</a>:16;
+<a name="l00703"></a><a class="code" href="uniondtxfsts__data.html#7bf9687e9efb791c8d3da9e50fde6096">00703</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondtxfsts__data.html#7bf9687e9efb791c8d3da9e50fde6096">reserved</a>:16;
+<a name="l00704"></a>00704         } <a class="code" href="uniondtxfsts__data.html#168f673549aad11d0d9fdc06ee6c5480">b</a>;
+<a name="l00705"></a>00705 } <a class="code" href="uniondtxfsts__data.html">dtxfsts_data_t</a>;
+<a name="l00706"></a>00706 
+<a name="l00712"></a><a class="code" href="uniongi2cctl__data.html">00712</a> <span class="keyword">typedef</span> <span class="keyword">union </span><a class="code" href="uniongi2cctl__data.html">gi2cctl_data</a> {
+<a name="l00714"></a><a class="code" href="uniongi2cctl__data.html#97e9ae4e52d9bd9370027b5da5f65787">00714</a>         uint32_t <a class="code" href="uniongi2cctl__data.html#97e9ae4e52d9bd9370027b5da5f65787">d32</a>;
+<a name="l00716"></a>00716         <span class="keyword">struct </span>{
+<a name="l00717"></a><a class="code" href="uniongi2cctl__data.html#7324a24ede0ab8ddcd9fbb1c5c558ff5">00717</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongi2cctl__data.html#7324a24ede0ab8ddcd9fbb1c5c558ff5">rwdata</a>:8;
+<a name="l00718"></a><a class="code" href="uniongi2cctl__data.html#9c6113a7da88fc158f2ffabe4b0bfcb6">00718</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongi2cctl__data.html#9c6113a7da88fc158f2ffabe4b0bfcb6">regaddr</a>:8;
+<a name="l00719"></a><a class="code" href="uniongi2cctl__data.html#5641294f472040bc6c4f7e70e84500f0">00719</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongi2cctl__data.html#5641294f472040bc6c4f7e70e84500f0">addr</a>:7;
+<a name="l00720"></a><a class="code" href="uniongi2cctl__data.html#6a14bacfd6c36d22071a79cb0fb53e77">00720</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongi2cctl__data.html#6a14bacfd6c36d22071a79cb0fb53e77">i2cen</a>:1;
+<a name="l00721"></a><a class="code" href="uniongi2cctl__data.html#58c5fecd71f1bf68dc3e6939e5b56335">00721</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongi2cctl__data.html#58c5fecd71f1bf68dc3e6939e5b56335">ack</a>:1;
+<a name="l00722"></a><a class="code" href="uniongi2cctl__data.html#96fcad9de22d851a74f900458c2ac325">00722</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongi2cctl__data.html#96fcad9de22d851a74f900458c2ac325">i2csuspctl</a>:1;
+<a name="l00723"></a><a class="code" href="uniongi2cctl__data.html#78d1a33a0a81bbca4e89e2f578b27ca2">00723</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongi2cctl__data.html#78d1a33a0a81bbca4e89e2f578b27ca2">i2cdevaddr</a>:2;
+<a name="l00724"></a><a class="code" href="uniongi2cctl__data.html#208c2f1fe8cff50b174028b7573ae03f">00724</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongi2cctl__data.html#208c2f1fe8cff50b174028b7573ae03f">reserved</a>:2;
+<a name="l00725"></a><a class="code" href="uniongi2cctl__data.html#afc04461ec8ca28e870cb2374b862961">00725</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongi2cctl__data.html#afc04461ec8ca28e870cb2374b862961">rw</a>:1;
+<a name="l00726"></a><a class="code" href="uniongi2cctl__data.html#b28daedf73bcb4d651f8fbc03bb69778">00726</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniongi2cctl__data.html#b28daedf73bcb4d651f8fbc03bb69778">bsydne</a>:1;
+<a name="l00727"></a>00727         } <a class="code" href="uniongi2cctl__data.html#5cd3b77fc770fc81b9cf9330cac214a8">b</a>;
+<a name="l00728"></a>00728 } <a class="code" href="uniongi2cctl__data.html">gi2cctl_data_t</a>;
+<a name="l00729"></a>00729 
+<a name="l00735"></a><a class="code" href="unionhwcfg1__data.html">00735</a> <span class="keyword">typedef</span> <span class="keyword">union </span><a class="code" href="unionhwcfg1__data.html">hwcfg1_data</a> {
+<a name="l00737"></a><a class="code" href="unionhwcfg1__data.html#9ca836052f9bd01e0b70902862ed09a4">00737</a>         uint32_t <a class="code" href="unionhwcfg1__data.html#9ca836052f9bd01e0b70902862ed09a4">d32</a>;
+<a name="l00739"></a>00739         <span class="keyword">struct </span>{
+<a name="l00740"></a><a class="code" href="unionhwcfg1__data.html#b58699c49f54de158d6edc4e57716668">00740</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg1__data.html#b58699c49f54de158d6edc4e57716668">ep_dir0</a>:2;
+<a name="l00741"></a><a class="code" href="unionhwcfg1__data.html#a62adc1641ef86ed0967061fe0480197">00741</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg1__data.html#a62adc1641ef86ed0967061fe0480197">ep_dir1</a>:2;
+<a name="l00742"></a><a class="code" href="unionhwcfg1__data.html#03607d2fd2913d3bd20035bc66105e77">00742</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg1__data.html#03607d2fd2913d3bd20035bc66105e77">ep_dir2</a>:2;
+<a name="l00743"></a><a class="code" href="unionhwcfg1__data.html#9beabdd8094db63c0359a7ef22f2266d">00743</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg1__data.html#9beabdd8094db63c0359a7ef22f2266d">ep_dir3</a>:2;
+<a name="l00744"></a><a class="code" href="unionhwcfg1__data.html#393899c7a69f9c36ab1b0ef15ab58568">00744</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg1__data.html#393899c7a69f9c36ab1b0ef15ab58568">ep_dir4</a>:2;
+<a name="l00745"></a><a class="code" href="unionhwcfg1__data.html#ef4cd3ba5b57ad791d1dfc237fcb7b2b">00745</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg1__data.html#ef4cd3ba5b57ad791d1dfc237fcb7b2b">ep_dir5</a>:2;
+<a name="l00746"></a><a class="code" href="unionhwcfg1__data.html#1521515b71e5bb03b1102fb3333c1bbc">00746</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg1__data.html#1521515b71e5bb03b1102fb3333c1bbc">ep_dir6</a>:2;
+<a name="l00747"></a><a class="code" href="unionhwcfg1__data.html#ddc5b4c31dc56456bdca5660d4608f28">00747</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg1__data.html#ddc5b4c31dc56456bdca5660d4608f28">ep_dir7</a>:2;
+<a name="l00748"></a><a class="code" href="unionhwcfg1__data.html#a0d189caec30660152f1fd3abd1176f2">00748</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg1__data.html#a0d189caec30660152f1fd3abd1176f2">ep_dir8</a>:2;
+<a name="l00749"></a><a class="code" href="unionhwcfg1__data.html#0c21e8d57df291e8d3b2dbb67c52956e">00749</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg1__data.html#0c21e8d57df291e8d3b2dbb67c52956e">ep_dir9</a>:2;
+<a name="l00750"></a><a class="code" href="unionhwcfg1__data.html#1dba400b1d532a89de3f2c4410e9ab4d">00750</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg1__data.html#1dba400b1d532a89de3f2c4410e9ab4d">ep_dir10</a>:2;
+<a name="l00751"></a><a class="code" href="unionhwcfg1__data.html#c5b95969c9c9ffd9f641f7a495e90621">00751</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg1__data.html#c5b95969c9c9ffd9f641f7a495e90621">ep_dir11</a>:2;
+<a name="l00752"></a><a class="code" href="unionhwcfg1__data.html#a88f6d54f42966f47e77dddd015f5aad">00752</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg1__data.html#a88f6d54f42966f47e77dddd015f5aad">ep_dir12</a>:2;
+<a name="l00753"></a><a class="code" href="unionhwcfg1__data.html#708fa9af8f43442846ed4a122cbf5610">00753</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg1__data.html#708fa9af8f43442846ed4a122cbf5610">ep_dir13</a>:2;
+<a name="l00754"></a><a class="code" href="unionhwcfg1__data.html#c930e82427e44ae78db85730665ed2a8">00754</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg1__data.html#c930e82427e44ae78db85730665ed2a8">ep_dir14</a>:2;
+<a name="l00755"></a><a class="code" href="unionhwcfg1__data.html#cb596169ca88921f58ab84d0a38a4cc8">00755</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg1__data.html#cb596169ca88921f58ab84d0a38a4cc8">ep_dir15</a>:2;
+<a name="l00756"></a>00756         } <a class="code" href="unionhwcfg1__data.html#fc54d55ec3ffbba9312c1d0c7611f605">b</a>;
+<a name="l00757"></a>00757 } <a class="code" href="unionhwcfg1__data.html">hwcfg1_data_t</a>;
+<a name="l00758"></a>00758 
+<a name="l00764"></a><a class="code" href="unionhwcfg2__data.html">00764</a> <span class="keyword">typedef</span> <span class="keyword">union </span><a class="code" href="unionhwcfg2__data.html">hwcfg2_data</a> {
+<a name="l00766"></a><a class="code" href="unionhwcfg2__data.html#2a2482b24bbfa8cdd589e376184d1e3b">00766</a>         uint32_t <a class="code" href="unionhwcfg2__data.html#2a2482b24bbfa8cdd589e376184d1e3b">d32</a>;
+<a name="l00768"></a>00768         <span class="keyword">struct </span>{
+<a name="l00769"></a>00769                 <span class="comment">/* GHWCFG2 */</span>
+<a name="l00770"></a><a class="code" href="unionhwcfg2__data.html#592df9b97ff9342b839d2ed76d54c652">00770</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg2__data.html#592df9b97ff9342b839d2ed76d54c652">op_mode</a>:3;
+<a name="l00771"></a><a class="code" href="dwc__otg__regs_8h.html#8af3c99831b24f4f12a6d5c8d738b5c1">00771</a> <span class="preprocessor">#define DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG 0</span>
+<a name="l00772"></a><a class="code" href="dwc__otg__regs_8h.html#184dedc2208935e427ec8d70f63acc03">00772</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG 1</span>
+<a name="l00773"></a><a class="code" href="dwc__otg__regs_8h.html#9f259c90ff1115e85ad4ffc7dab0186b">00773</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG 2</span>
+<a name="l00774"></a><a class="code" href="dwc__otg__regs_8h.html#1f8de01acf1cfba7684a6b541cdacc72">00774</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3</span>
+<a name="l00775"></a><a class="code" href="dwc__otg__regs_8h.html#f3d7ebd02f23f2520561832a4972d3c6">00775</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4</span>
+<a name="l00776"></a><a class="code" href="dwc__otg__regs_8h.html#77eccf27fae160a4ad7f72b1b43864c3">00776</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST 5</span>
+<a name="l00777"></a><a class="code" href="dwc__otg__regs_8h.html#dc5c9ee91aa1e0070aa05fd7d958ab8f">00777</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6</span>
+<a name="l00778"></a>00778 <span class="preprocessor"></span>
+<a name="l00779"></a><a class="code" href="unionhwcfg2__data.html#e5000f58c6a0f09c75375b4c912af0eb">00779</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg2__data.html#e5000f58c6a0f09c75375b4c912af0eb">architecture</a>:2;
+<a name="l00780"></a><a class="code" href="unionhwcfg2__data.html#6ef3a94368c53a22c222795bfc2306e3">00780</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg2__data.html#6ef3a94368c53a22c222795bfc2306e3">point2point</a>:1;
+<a name="l00781"></a><a class="code" href="unionhwcfg2__data.html#a248a2502e3c440d7b6e4ad61d396f4e">00781</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg2__data.html#a248a2502e3c440d7b6e4ad61d396f4e">hs_phy_type</a>:2;
+<a name="l00782"></a><a class="code" href="dwc__otg__regs_8h.html#7286edbddfc6b83cf2082a0ad88932ae">00782</a> <span class="preprocessor">#define DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0</span>
+<a name="l00783"></a><a class="code" href="dwc__otg__regs_8h.html#e216917509a2f9a01493b5d9acc8717c">00783</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_HWCFG2_HS_PHY_TYPE_UTMI 1</span>
+<a name="l00784"></a><a class="code" href="dwc__otg__regs_8h.html#0633e41edfacfabfb7ba32f972dc0479">00784</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_HWCFG2_HS_PHY_TYPE_ULPI 2</span>
+<a name="l00785"></a><a class="code" href="dwc__otg__regs_8h.html#0a3e7ebf66c6ecde6d4fc4e6d5e14d5e">00785</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI 3</span>
+<a name="l00786"></a>00786 <span class="preprocessor"></span>
+<a name="l00787"></a><a class="code" href="unionhwcfg2__data.html#e75417d7e2d1843abf6e48f67851326e">00787</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg2__data.html#e75417d7e2d1843abf6e48f67851326e">fs_phy_type</a>:2;
+<a name="l00788"></a><a class="code" href="unionhwcfg2__data.html#9f827f334b58643849598ce1fa314c5a">00788</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg2__data.html#9f827f334b58643849598ce1fa314c5a">num_dev_ep</a>:4;
+<a name="l00789"></a><a class="code" href="unionhwcfg2__data.html#83708a4d45e8d019892367c5ae9f6fd0">00789</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg2__data.html#83708a4d45e8d019892367c5ae9f6fd0">num_host_chan</a>:4;
+<a name="l00790"></a><a class="code" href="unionhwcfg2__data.html#d0d29d530b38b3dcd58c88a2ef9688bb">00790</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg2__data.html#d0d29d530b38b3dcd58c88a2ef9688bb">perio_ep_supported</a>:1;
+<a name="l00791"></a><a class="code" href="unionhwcfg2__data.html#b6bfbfe650352dec82a02d15677fe88d">00791</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg2__data.html#b6bfbfe650352dec82a02d15677fe88d">dynamic_fifo</a>:1;
+<a name="l00792"></a><a class="code" href="unionhwcfg2__data.html#53c36944e5bd45e6f3ecbe933d7246eb">00792</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg2__data.html#53c36944e5bd45e6f3ecbe933d7246eb">multi_proc_int</a>:1;
+<a name="l00793"></a><a class="code" href="unionhwcfg2__data.html#a46116164804fe814867f833d03080ac">00793</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg2__data.html#a46116164804fe814867f833d03080ac">reserved21</a>:1;
+<a name="l00794"></a><a class="code" href="unionhwcfg2__data.html#1369a191c7bd2f717cef2bce7a97ee67">00794</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg2__data.html#1369a191c7bd2f717cef2bce7a97ee67">nonperio_tx_q_depth</a>:2;
+<a name="l00795"></a><a class="code" href="unionhwcfg2__data.html#857bb59069e203a94ffd32538c60058f">00795</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg2__data.html#857bb59069e203a94ffd32538c60058f">host_perio_tx_q_depth</a>:2;
+<a name="l00796"></a><a class="code" href="unionhwcfg2__data.html#ba242467585b60b4d3db9882e0f39b3f">00796</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg2__data.html#ba242467585b60b4d3db9882e0f39b3f">dev_token_q_depth</a>:5;
+<a name="l00797"></a><a class="code" href="unionhwcfg2__data.html#097d9eac7baa9ff9b49198cdd9896885">00797</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg2__data.html#097d9eac7baa9ff9b49198cdd9896885">reserved31</a>:1;
+<a name="l00798"></a>00798         } <a class="code" href="unionhwcfg2__data.html#9dcc70e2dba617cbc6c12189be5c1d6a">b</a>;
+<a name="l00799"></a>00799 } <a class="code" href="unionhwcfg2__data.html">hwcfg2_data_t</a>;
+<a name="l00800"></a>00800 
+<a name="l00806"></a><a class="code" href="unionhwcfg3__data.html">00806</a> <span class="keyword">typedef</span> <span class="keyword">union </span><a class="code" href="unionhwcfg3__data.html">hwcfg3_data</a> {
+<a name="l00808"></a><a class="code" href="unionhwcfg3__data.html#9daf160f3fc0cc8e4e68c037f6c2f9d7">00808</a>         uint32_t <a class="code" href="unionhwcfg3__data.html#9daf160f3fc0cc8e4e68c037f6c2f9d7">d32</a>;
+<a name="l00810"></a>00810         <span class="keyword">struct </span>{
+<a name="l00811"></a>00811                 <span class="comment">/* GHWCFG3 */</span>
+<a name="l00812"></a><a class="code" href="unionhwcfg3__data.html#66f311995decf2f11d620aa6a56fa26e">00812</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg3__data.html#66f311995decf2f11d620aa6a56fa26e">xfer_size_cntr_width</a>:4;
+<a name="l00813"></a><a class="code" href="unionhwcfg3__data.html#a397ea503f5155d8e3a66cc82d7937f2">00813</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg3__data.html#a397ea503f5155d8e3a66cc82d7937f2">packet_size_cntr_width</a>:3;
+<a name="l00814"></a><a class="code" href="unionhwcfg3__data.html#dcd27bbcb3f0e0f5fbd6e7e8b7db1865">00814</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg3__data.html#dcd27bbcb3f0e0f5fbd6e7e8b7db1865">otg_func</a>:1;
+<a name="l00815"></a><a class="code" href="unionhwcfg3__data.html#dd2115f4a4bfa47b2c9c9a7b5f42e203">00815</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg3__data.html#dd2115f4a4bfa47b2c9c9a7b5f42e203">i2c</a>:1;
+<a name="l00816"></a><a class="code" href="unionhwcfg3__data.html#5008cb6cf85beb23f391e8ccf7306884">00816</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg3__data.html#5008cb6cf85beb23f391e8ccf7306884">vendor_ctrl_if</a>:1;
+<a name="l00817"></a><a class="code" href="unionhwcfg3__data.html#37ea87e07a63864a3b985df59fe98c8d">00817</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg3__data.html#37ea87e07a63864a3b985df59fe98c8d">optional_features</a>:1;
+<a name="l00818"></a><a class="code" href="unionhwcfg3__data.html#2aee57ed6a1fb0c63830b9f3b3754373">00818</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg3__data.html#2aee57ed6a1fb0c63830b9f3b3754373">synch_reset_type</a>:1;
+<a name="l00819"></a><a class="code" href="unionhwcfg3__data.html#a01a48361a21cb9dfbbd555823b8531b">00819</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg3__data.html#a01a48361a21cb9dfbbd555823b8531b">otg_enable_ic_usb</a>:1;
+<a name="l00820"></a><a class="code" href="unionhwcfg3__data.html#8c83b7ac3a4bb366119aeb3195126445">00820</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg3__data.html#8c83b7ac3a4bb366119aeb3195126445">otg_enable_hsic</a>:1;
+<a name="l00821"></a><a class="code" href="unionhwcfg3__data.html#7ef81a007358254606fa96f0c620f8a8">00821</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg3__data.html#7ef81a007358254606fa96f0c620f8a8">reserved14</a>:1;
+<a name="l00822"></a><a class="code" href="unionhwcfg3__data.html#2b9c39a4ce021bfd039729ccf2c2c503">00822</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg3__data.html#2b9c39a4ce021bfd039729ccf2c2c503">otg_lpm_en</a>:1;
+<a name="l00823"></a><a class="code" href="unionhwcfg3__data.html#f885715ddb953dbe95acc08e49264706">00823</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg3__data.html#f885715ddb953dbe95acc08e49264706">dfifo_depth</a>:16;
+<a name="l00824"></a>00824         } <a class="code" href="unionhwcfg3__data.html#928c5de42f8af177ce34712123b5093c">b</a>;
+<a name="l00825"></a>00825 } <a class="code" href="unionhwcfg3__data.html">hwcfg3_data_t</a>;
+<a name="l00826"></a>00826 
+<a name="l00832"></a><a class="code" href="unionhwcfg4__data.html">00832</a> <span class="keyword">typedef</span> <span class="keyword">union </span><a class="code" href="unionhwcfg4__data.html">hwcfg4_data</a> {
+<a name="l00834"></a><a class="code" href="unionhwcfg4__data.html#edcdf66b3add0e05ce0006b0b0de8dd0">00834</a>         uint32_t <a class="code" href="unionhwcfg4__data.html#edcdf66b3add0e05ce0006b0b0de8dd0">d32</a>;
+<a name="l00836"></a>00836         <span class="keyword">struct </span>{
+<a name="l00837"></a><a class="code" href="unionhwcfg4__data.html#aee60fb196cf53b610df556744e4d317">00837</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg4__data.html#aee60fb196cf53b610df556744e4d317">num_dev_perio_in_ep</a>:4;
+<a name="l00838"></a><a class="code" href="unionhwcfg4__data.html#3227ec0129191d0d099f0dce7f18c546">00838</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg4__data.html#3227ec0129191d0d099f0dce7f18c546">power_optimiz</a>:1;
+<a name="l00839"></a><a class="code" href="unionhwcfg4__data.html#0a12e214e53ded595dfa11157129ab8c">00839</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg4__data.html#0a12e214e53ded595dfa11157129ab8c">min_ahb_freq</a>:9;
+<a name="l00840"></a><a class="code" href="unionhwcfg4__data.html#31e5336f64bdea1bb8e1e358375b20f0">00840</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg4__data.html#31e5336f64bdea1bb8e1e358375b20f0">utmi_phy_data_width</a>:2;
+<a name="l00841"></a><a class="code" href="unionhwcfg4__data.html#51130a20d8311e691ea8b8565bbe3080">00841</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg4__data.html#51130a20d8311e691ea8b8565bbe3080">num_dev_mode_ctrl_ep</a>:4;
+<a name="l00842"></a><a class="code" href="unionhwcfg4__data.html#be353f75bb8cd8b14fc5f8db2d51da55">00842</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg4__data.html#be353f75bb8cd8b14fc5f8db2d51da55">iddig_filt_en</a>:1;
+<a name="l00843"></a><a class="code" href="unionhwcfg4__data.html#5cbe1c265b6623dff23460111142db7d">00843</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg4__data.html#5cbe1c265b6623dff23460111142db7d">vbus_valid_filt_en</a>:1;
+<a name="l00844"></a><a class="code" href="unionhwcfg4__data.html#109cd4df5b8b9035bf37aae2cbcbc15e">00844</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg4__data.html#109cd4df5b8b9035bf37aae2cbcbc15e">a_valid_filt_en</a>:1;
+<a name="l00845"></a><a class="code" href="unionhwcfg4__data.html#2f741788949e2fea24c129b1a4e10331">00845</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg4__data.html#2f741788949e2fea24c129b1a4e10331">b_valid_filt_en</a>:1;
+<a name="l00846"></a><a class="code" href="unionhwcfg4__data.html#d5dc6949986ee9ac55ccf542b855fddf">00846</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg4__data.html#d5dc6949986ee9ac55ccf542b855fddf">session_end_filt_en</a>:1;
+<a name="l00847"></a><a class="code" href="unionhwcfg4__data.html#175e8897d6e3c8ef4026413943de503b">00847</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg4__data.html#175e8897d6e3c8ef4026413943de503b">ded_fifo_en</a>:1;
+<a name="l00848"></a><a class="code" href="unionhwcfg4__data.html#753b321350388c5e1307802ff968f9a8">00848</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg4__data.html#753b321350388c5e1307802ff968f9a8">num_in_eps</a>:4;
+<a name="l00849"></a><a class="code" href="unionhwcfg4__data.html#988888a48e9088d0e9f889818eb63509">00849</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg4__data.html#988888a48e9088d0e9f889818eb63509">desc_dma</a>:1;
+<a name="l00850"></a><a class="code" href="unionhwcfg4__data.html#9562305cf5dd89816939792a66879542">00850</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhwcfg4__data.html#9562305cf5dd89816939792a66879542">desc_dma_dyn</a>:1;
+<a name="l00851"></a>00851         } <a class="code" href="unionhwcfg4__data.html#9fb9175668e2381c568c5adbf6e5225d">b</a>;
+<a name="l00852"></a>00852 } <a class="code" href="unionhwcfg4__data.html">hwcfg4_data_t</a>;
+<a name="l00853"></a>00853 
+<a name="l00855"></a>00855 <span class="comment">// Device Registers</span>
+<a name="l00865"></a><a class="code" href="structdwc__otg__dev__global__regs.html">00865</a> <span class="comment"></span><span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code" href="structdwc__otg__dev__global__regs.html">dwc_otg_dev_global_regs</a> {
+<a name="l00867"></a><a class="code" href="structdwc__otg__dev__global__regs.html#c0c24937bbd7184884f05343f56ef1da">00867</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__dev__global__regs.html#c0c24937bbd7184884f05343f56ef1da">dcfg</a>;
+<a name="l00869"></a><a class="code" href="structdwc__otg__dev__global__regs.html#3779c2fc508920a831a59e696a8fa785">00869</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__dev__global__regs.html#3779c2fc508920a831a59e696a8fa785">dctl</a>;
+<a name="l00871"></a><a class="code" href="structdwc__otg__dev__global__regs.html#1ed00edd20ce5db7d07666804101ec05">00871</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__dev__global__regs.html#1ed00edd20ce5db7d07666804101ec05">dsts</a>;
+<a name="l00873"></a><a class="code" href="structdwc__otg__dev__global__regs.html#8d6452da1d0e266737d77e55fc15f72c">00873</a>         uint32_t <a class="code" href="structdwc__otg__dev__global__regs.html#8d6452da1d0e266737d77e55fc15f72c">unused</a>;
+<a name="l00876"></a><a class="code" href="structdwc__otg__dev__global__regs.html#02e44cb182548d78c5b7d27929ca5f11">00876</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__dev__global__regs.html#02e44cb182548d78c5b7d27929ca5f11">diepmsk</a>;
+<a name="l00879"></a><a class="code" href="structdwc__otg__dev__global__regs.html#d6947be9d84a1d87156f81a10ebb036b">00879</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__dev__global__regs.html#d6947be9d84a1d87156f81a10ebb036b">doepmsk</a>;
+<a name="l00881"></a><a class="code" href="structdwc__otg__dev__global__regs.html#2e25df2fbec9d398742709524056cbd5">00881</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__dev__global__regs.html#2e25df2fbec9d398742709524056cbd5">daint</a>;
+<a name="l00884"></a><a class="code" href="structdwc__otg__dev__global__regs.html#5def6c3850c041928b9a662422ee0679">00884</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__dev__global__regs.html#5def6c3850c041928b9a662422ee0679">daintmsk</a>;
+<a name="l00887"></a><a class="code" href="structdwc__otg__dev__global__regs.html#b130a76736e0e81d5a020651109352de">00887</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__dev__global__regs.html#b130a76736e0e81d5a020651109352de">dtknqr1</a>;
+<a name="l00890"></a><a class="code" href="structdwc__otg__dev__global__regs.html#27968db886161264e7820bcf4a746e5d">00890</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__dev__global__regs.html#27968db886161264e7820bcf4a746e5d">dtknqr2</a>;
+<a name="l00892"></a><a class="code" href="structdwc__otg__dev__global__regs.html#95088e182c3ff164d1b331bb196eb95d">00892</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__dev__global__regs.html#95088e182c3ff164d1b331bb196eb95d">dvbusdis</a>;
+<a name="l00894"></a><a class="code" href="structdwc__otg__dev__global__regs.html#8747dbe01b5a4cbd2c980bf39fdb4737">00894</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__dev__global__regs.html#8747dbe01b5a4cbd2c980bf39fdb4737">dvbuspulse</a>;
+<a name="l00898"></a><a class="code" href="structdwc__otg__dev__global__regs.html#c263c55a0bb752f8939731aa2f8f6cb8">00898</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__dev__global__regs.html#c263c55a0bb752f8939731aa2f8f6cb8">dtknqr3_dthrctl</a>;
+<a name="l00902"></a><a class="code" href="structdwc__otg__dev__global__regs.html#fbc2b776c2150842813e4681dd43bedc">00902</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__dev__global__regs.html#fbc2b776c2150842813e4681dd43bedc">dtknqr4_fifoemptymsk</a>;
+<a name="l00905"></a><a class="code" href="structdwc__otg__dev__global__regs.html#4795bc8eab569241a3f8e6aad5d99ac7">00905</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__dev__global__regs.html#4795bc8eab569241a3f8e6aad5d99ac7">deachint</a>;
+<a name="l00908"></a><a class="code" href="structdwc__otg__dev__global__regs.html#e64a153683f0e0cda14b56a163651825">00908</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__dev__global__regs.html#e64a153683f0e0cda14b56a163651825">deachintmsk</a>;
+<a name="l00911"></a><a class="code" href="structdwc__otg__dev__global__regs.html#aaf2a5c6be4130d558c291f6aaeeca4f">00911</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__dev__global__regs.html#aaf2a5c6be4130d558c291f6aaeeca4f">diepeachintmsk</a>[<a class="code" href="dwc__otg__core__if_8h.html#bfb88b45545f7685f668ac2f545674ec">MAX_EPS_CHANNELS</a>];
+<a name="l00914"></a><a class="code" href="structdwc__otg__dev__global__regs.html#304e089ed2d36d9076228b8d7e1cc515">00914</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__dev__global__regs.html#304e089ed2d36d9076228b8d7e1cc515">doepeachintmsk</a>[<a class="code" href="dwc__otg__core__if_8h.html#bfb88b45545f7685f668ac2f545674ec">MAX_EPS_CHANNELS</a>];
+<a name="l00915"></a>00915 } <a class="code" href="structdwc__otg__dev__global__regs.html">dwc_otg_device_global_regs_t</a>;
+<a name="l00916"></a>00916 
+<a name="l00923"></a><a class="code" href="uniondcfg__data.html">00923</a> <span class="keyword">typedef</span> <span class="keyword">union </span><a class="code" href="uniondcfg__data.html">dcfg_data</a> {
+<a name="l00925"></a><a class="code" href="uniondcfg__data.html#efd84d3306db1b4370535a0e814612dc">00925</a>         uint32_t <a class="code" href="uniondcfg__data.html#efd84d3306db1b4370535a0e814612dc">d32</a>;
+<a name="l00927"></a>00927         <span class="keyword">struct </span>{
+<a name="l00929"></a><a class="code" href="uniondcfg__data.html#28ffb9fb43686fe553fbe80f1ead62a4">00929</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondcfg__data.html#28ffb9fb43686fe553fbe80f1ead62a4">devspd</a>:2;
+<a name="l00931"></a><a class="code" href="uniondcfg__data.html#bfe8fbad12896d96cbeb686243f9602e">00931</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondcfg__data.html#bfe8fbad12896d96cbeb686243f9602e">nzstsouthshk</a>:1;
+<a name="l00932"></a><a class="code" href="dwc__otg__regs_8h.html#867bd5c96203c1cf32fbbe78ca893a72">00932</a> <span class="preprocessor">#define DWC_DCFG_SEND_STALL 1</span>
+<a name="l00933"></a>00933 <span class="preprocessor"></span>
+<a name="l00934"></a><a class="code" href="uniondcfg__data.html#34ff0184038007f588650f208026ef1a">00934</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondcfg__data.html#34ff0184038007f588650f208026ef1a">reserved3</a>:1;
+<a name="l00936"></a><a class="code" href="uniondcfg__data.html#71c70afb48dd124d12e43d86edd90f1e">00936</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondcfg__data.html#71c70afb48dd124d12e43d86edd90f1e">devaddr</a>:7;
+<a name="l00938"></a><a class="code" href="uniondcfg__data.html#f4ed8f15f1716ff0f9366badac18fbb4">00938</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondcfg__data.html#f4ed8f15f1716ff0f9366badac18fbb4">perfrint</a>:2;
+<a name="l00939"></a><a class="code" href="dwc__otg__regs_8h.html#d5b5378a658017c4f9cbdd8e4462d4fc">00939</a> <span class="preprocessor">#define DWC_DCFG_FRAME_INTERVAL_80 0</span>
+<a name="l00940"></a><a class="code" href="dwc__otg__regs_8h.html#0724fae5fc15468eabad5dd76c39e74f">00940</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_DCFG_FRAME_INTERVAL_85 1</span>
+<a name="l00941"></a><a class="code" href="dwc__otg__regs_8h.html#3652689417367e081e78a6cc0df59686">00941</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_DCFG_FRAME_INTERVAL_90 2</span>
+<a name="l00942"></a><a class="code" href="dwc__otg__regs_8h.html#12d2316f6beb751fca190b3865baeb50">00942</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_DCFG_FRAME_INTERVAL_95 3</span>
+<a name="l00943"></a>00943 <span class="preprocessor"></span>
+<a name="l00944"></a><a class="code" href="uniondcfg__data.html#b6b4268d55a7dd952a0406c94abc8be0">00944</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondcfg__data.html#b6b4268d55a7dd952a0406c94abc8be0">reserved13_17</a>:5;
+<a name="l00946"></a><a class="code" href="uniondcfg__data.html#9292b8ce264ebdb8a26c28883443a4df">00946</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondcfg__data.html#9292b8ce264ebdb8a26c28883443a4df">epmscnt</a>:5;
+<a name="l00948"></a><a class="code" href="uniondcfg__data.html#d83666dcf5675453a387915ce1653d54">00948</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondcfg__data.html#d83666dcf5675453a387915ce1653d54">descdma</a>:1;
+<a name="l00949"></a>00949         } <a class="code" href="uniondcfg__data.html#242c1b463f445de3fc265e8c20fde50b">b</a>;
+<a name="l00950"></a>00950 } <a class="code" href="uniondcfg__data.html">dcfg_data_t</a>;
+<a name="l00951"></a>00951 
+<a name="l00957"></a><a class="code" href="uniondctl__data.html">00957</a> <span class="keyword">typedef</span> <span class="keyword">union </span><a class="code" href="uniondctl__data.html">dctl_data</a> {
+<a name="l00959"></a><a class="code" href="uniondctl__data.html#f49aadfd7ad95b570115b3c245b1729e">00959</a>         uint32_t <a class="code" href="uniondctl__data.html#f49aadfd7ad95b570115b3c245b1729e">d32</a>;
+<a name="l00961"></a>00961         <span class="keyword">struct </span>{
+<a name="l00963"></a><a class="code" href="uniondctl__data.html#dcae5af28dc159cd7ba85a9a2b8be51a">00963</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondctl__data.html#dcae5af28dc159cd7ba85a9a2b8be51a">rmtwkupsig</a>:1;
+<a name="l00965"></a><a class="code" href="uniondctl__data.html#3416d438405187a683c67f5006f7bfc8">00965</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondctl__data.html#3416d438405187a683c67f5006f7bfc8">sftdiscon</a>:1;
+<a name="l00967"></a><a class="code" href="uniondctl__data.html#26ba184e018a813e96527822f9e26fde">00967</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondctl__data.html#26ba184e018a813e96527822f9e26fde">gnpinnaksts</a>:1;
+<a name="l00969"></a><a class="code" href="uniondctl__data.html#995d969d60e86b2ea662eb831c882b44">00969</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondctl__data.html#995d969d60e86b2ea662eb831c882b44">goutnaksts</a>:1;
+<a name="l00971"></a><a class="code" href="uniondctl__data.html#ef7a2687eef3086056f30b13f3588f9e">00971</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondctl__data.html#ef7a2687eef3086056f30b13f3588f9e">tstctl</a>:3;
+<a name="l00973"></a><a class="code" href="uniondctl__data.html#2349dad5149cd3fcfd8fe3abcd77c32e">00973</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondctl__data.html#2349dad5149cd3fcfd8fe3abcd77c32e">sgnpinnak</a>:1;
+<a name="l00975"></a><a class="code" href="uniondctl__data.html#6feecf1184cd67b8b8ede2e2030a5dba">00975</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondctl__data.html#6feecf1184cd67b8b8ede2e2030a5dba">cgnpinnak</a>:1;
+<a name="l00977"></a><a class="code" href="uniondctl__data.html#28bd2f29264841207cd740ce9ec7fa91">00977</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondctl__data.html#28bd2f29264841207cd740ce9ec7fa91">sgoutnak</a>:1;
+<a name="l00979"></a><a class="code" href="uniondctl__data.html#7ffb7af3cfeb7efb811eb3c7fa7f3440">00979</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondctl__data.html#7ffb7af3cfeb7efb811eb3c7fa7f3440">cgoutnak</a>:1;
+<a name="l00980"></a>00980 
+<a name="l00982"></a><a class="code" href="uniondctl__data.html#216f929e4d24b0c3005cd0add0de7a27">00982</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondctl__data.html#216f929e4d24b0c3005cd0add0de7a27">pwronprgdone</a>:1;
+<a name="l00984"></a><a class="code" href="uniondctl__data.html#212c36aaab3763a6de5cca56999c0263">00984</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondctl__data.html#212c36aaab3763a6de5cca56999c0263">gcontbna</a>:1;
+<a name="l00986"></a><a class="code" href="uniondctl__data.html#6ceae1404558a4ffec4dab1c4702c7c8">00986</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondctl__data.html#6ceae1404558a4ffec4dab1c4702c7c8">gmc</a>:2;
+<a name="l00988"></a><a class="code" href="uniondctl__data.html#a817a529df5c5fc57135560014b90dcc">00988</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondctl__data.html#a817a529df5c5fc57135560014b90dcc">ifrmnum</a>:1;
+<a name="l00990"></a><a class="code" href="uniondctl__data.html#422c27727aa788391b807b62011bd464">00990</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondctl__data.html#422c27727aa788391b807b62011bd464">nakonbble</a>:1;
+<a name="l00991"></a>00991 
+<a name="l00992"></a><a class="code" href="uniondctl__data.html#dccb4bb22e6b46b3b92f495e8bdcd857">00992</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondctl__data.html#dccb4bb22e6b46b3b92f495e8bdcd857">reserved17_31</a>:15;
+<a name="l00993"></a>00993         } <a class="code" href="uniondctl__data.html#a3abfa6d609d9864f1f65712b409d4d3">b</a>;
+<a name="l00994"></a>00994 } <a class="code" href="uniondctl__data.html">dctl_data_t</a>;
+<a name="l00995"></a>00995 
+<a name="l01001"></a><a class="code" href="uniondsts__data.html">01001</a> <span class="keyword">typedef</span> <span class="keyword">union </span><a class="code" href="uniondsts__data.html">dsts_data</a> {
+<a name="l01003"></a><a class="code" href="uniondsts__data.html#0f126daef735b142b06dbc4cdbe13814">01003</a>         uint32_t <a class="code" href="uniondsts__data.html#0f126daef735b142b06dbc4cdbe13814">d32</a>;
+<a name="l01005"></a>01005         <span class="keyword">struct </span>{
+<a name="l01007"></a><a class="code" href="uniondsts__data.html#4c7cd8ee3877701268846b0b02ac3d97">01007</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondsts__data.html#4c7cd8ee3877701268846b0b02ac3d97">suspsts</a>:1;
+<a name="l01009"></a><a class="code" href="uniondsts__data.html#f918f3d04b026687af3e1953f5c79fea">01009</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondsts__data.html#f918f3d04b026687af3e1953f5c79fea">enumspd</a>:2;
+<a name="l01010"></a><a class="code" href="dwc__otg__regs_8h.html#2c41cb64f1ba728146bece30a622044c">01010</a> <span class="preprocessor">#define DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0</span>
+<a name="l01011"></a><a class="code" href="dwc__otg__regs_8h.html#373742ad0a97af406169cc3ada63ca04">01011</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1</span>
+<a name="l01012"></a><a class="code" href="dwc__otg__regs_8h.html#7df682e9f37924c859657ff26fee5cbc">01012</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_DSTS_ENUMSPD_LS_PHY_6MHZ               2</span>
+<a name="l01013"></a><a class="code" href="dwc__otg__regs_8h.html#81dafef32b78df31eb2eeac36fd0694a">01013</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_DSTS_ENUMSPD_FS_PHY_48MHZ              3</span>
+<a name="l01014"></a>01014 <span class="preprocessor"></span>
+<a name="l01015"></a><a class="code" href="uniondsts__data.html#fc57a31e440fcf11b233c8c208df83be">01015</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondsts__data.html#fc57a31e440fcf11b233c8c208df83be">errticerr</a>:1;
+<a name="l01016"></a><a class="code" href="uniondsts__data.html#5d3df4c5b52ea3e0cf3311d64ae6a05d">01016</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondsts__data.html#5d3df4c5b52ea3e0cf3311d64ae6a05d">reserved4_7</a>:4;
+<a name="l01018"></a><a class="code" href="uniondsts__data.html#5a81ac4848c859cbf7d494dc345a0ce8">01018</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondsts__data.html#5a81ac4848c859cbf7d494dc345a0ce8">soffn</a>:14;
+<a name="l01019"></a><a class="code" href="uniondsts__data.html#6cf6e0bdb54164703f46ac1ac7258c38">01019</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondsts__data.html#6cf6e0bdb54164703f46ac1ac7258c38">reserved22_31</a>:10;
+<a name="l01020"></a>01020         } <a class="code" href="uniondsts__data.html#4066fcedb7ac9a88e47aa1b2df0e89ee">b</a>;
+<a name="l01021"></a>01021 } <a class="code" href="uniondsts__data.html">dsts_data_t</a>;
+<a name="l01022"></a>01022 
+<a name="l01030"></a><a class="code" href="uniondiepint__data.html">01030</a> <span class="keyword">typedef</span> <span class="keyword">union </span><a class="code" href="uniondiepint__data.html">diepint_data</a> {
+<a name="l01032"></a><a class="code" href="uniondiepint__data.html#7d2c24507663bf96c280c57fbf544ef7">01032</a>         uint32_t <a class="code" href="uniondiepint__data.html#7d2c24507663bf96c280c57fbf544ef7">d32</a>;
+<a name="l01034"></a>01034         <span class="keyword">struct </span>{
+<a name="l01036"></a><a class="code" href="uniondiepint__data.html#56e1252841323973e0ada12cc89059c9">01036</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondiepint__data.html#56e1252841323973e0ada12cc89059c9">xfercompl</a>:1;
+<a name="l01038"></a><a class="code" href="uniondiepint__data.html#3a649b75195fb5b26135d75b03cf561d">01038</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondiepint__data.html#3a649b75195fb5b26135d75b03cf561d">epdisabled</a>:1;
+<a name="l01040"></a><a class="code" href="uniondiepint__data.html#6d57fa84f687bc4f05013c1e1a7edf29">01040</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondiepint__data.html#6d57fa84f687bc4f05013c1e1a7edf29">ahberr</a>:1;
+<a name="l01042"></a><a class="code" href="uniondiepint__data.html#2513e8eef259c711e9a139cb2631b142">01042</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondiepint__data.html#2513e8eef259c711e9a139cb2631b142">timeout</a>:1;
+<a name="l01044"></a><a class="code" href="uniondiepint__data.html#7c9961f17328bbc25ca39e7ec1891e16">01044</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondiepint__data.html#7c9961f17328bbc25ca39e7ec1891e16">intktxfemp</a>:1;
+<a name="l01046"></a><a class="code" href="uniondiepint__data.html#103fb29d954cf12d33f7ebe6009f9a46">01046</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondiepint__data.html#103fb29d954cf12d33f7ebe6009f9a46">intknepmis</a>:1;
+<a name="l01048"></a><a class="code" href="uniondiepint__data.html#9186a1106fe57e01ce720a50ceb5864f">01048</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondiepint__data.html#9186a1106fe57e01ce720a50ceb5864f">inepnakeff</a>:1;
+<a name="l01050"></a><a class="code" href="uniondiepint__data.html#de84fb009990e97bfa46f825d5358429">01050</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondiepint__data.html#de84fb009990e97bfa46f825d5358429">emptyintr</a>:1;
+<a name="l01051"></a>01051 
+<a name="l01052"></a><a class="code" href="uniondiepint__data.html#90d0e6a99275eccd4a50f62644de9152">01052</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondiepint__data.html#90d0e6a99275eccd4a50f62644de9152">txfifoundrn</a>:1;
+<a name="l01053"></a>01053 
+<a name="l01055"></a><a class="code" href="uniondiepint__data.html#2530c984ae3ebda73405d98080d8a57b">01055</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondiepint__data.html#2530c984ae3ebda73405d98080d8a57b">bna</a>:1;
+<a name="l01056"></a>01056 
+<a name="l01057"></a><a class="code" href="uniondiepint__data.html#ba6d7c79905ec53a74a9db0bac336986">01057</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondiepint__data.html#ba6d7c79905ec53a74a9db0bac336986">reserved10_12</a>:3;
+<a name="l01059"></a><a class="code" href="uniondiepint__data.html#3ade814b2bef3085bb6fa32e94ea1aac">01059</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondiepint__data.html#3ade814b2bef3085bb6fa32e94ea1aac">nak</a>:1;
+<a name="l01060"></a>01060 
+<a name="l01061"></a><a class="code" href="uniondiepint__data.html#6fcd49001dc57506b9b1bbd74b4cb360">01061</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondiepint__data.html#6fcd49001dc57506b9b1bbd74b4cb360">reserved14_31</a>:18;
+<a name="l01062"></a>01062         } <a class="code" href="uniondiepint__data.html#48d2a745e0ec983a47b35b0428b0437d">b</a>;
+<a name="l01063"></a>01063 } <a class="code" href="uniondiepint__data.html">diepint_data_t</a>;
+<a name="l01064"></a>01064 
+<a name="l01069"></a><a class="code" href="dwc__otg__regs_8h.html#0a168a8839d24b08e39eebb131447531">01069</a> <span class="keyword">typedef</span> <span class="keyword">union </span><a class="code" href="uniondiepint__data.html">diepint_data</a> <a class="code" href="dwc__otg__regs_8h.html#0a168a8839d24b08e39eebb131447531">diepmsk_data_t</a>;
+<a name="l01070"></a>01070 
+<a name="l01078"></a><a class="code" href="uniondoepint__data.html">01078</a> <span class="keyword">typedef</span> <span class="keyword">union </span><a class="code" href="uniondoepint__data.html">doepint_data</a> {
+<a name="l01080"></a><a class="code" href="uniondoepint__data.html#94f8c8fc116b430565f9322e3621b3a5">01080</a>         uint32_t <a class="code" href="uniondoepint__data.html#94f8c8fc116b430565f9322e3621b3a5">d32</a>;
+<a name="l01082"></a>01082         <span class="keyword">struct </span>{
+<a name="l01084"></a><a class="code" href="uniondoepint__data.html#341f7ffa5a9da7f6b1e09e9f4cc516a3">01084</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondoepint__data.html#341f7ffa5a9da7f6b1e09e9f4cc516a3">xfercompl</a>:1;
+<a name="l01086"></a><a class="code" href="uniondoepint__data.html#8a263ddc3ab9080b8c2e02ccead0c983">01086</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondoepint__data.html#8a263ddc3ab9080b8c2e02ccead0c983">epdisabled</a>:1;
+<a name="l01088"></a><a class="code" href="uniondoepint__data.html#cdfedbad6643d94271e91e135485a68d">01088</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondoepint__data.html#cdfedbad6643d94271e91e135485a68d">ahberr</a>:1;
+<a name="l01090"></a><a class="code" href="uniondoepint__data.html#b286d1b76f09a9122aca23e430b63dc8">01090</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondoepint__data.html#b286d1b76f09a9122aca23e430b63dc8">setup</a>:1;
+<a name="l01092"></a><a class="code" href="uniondoepint__data.html#3f02a0e998438229ec34bb1a8c1f4192">01092</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondoepint__data.html#3f02a0e998438229ec34bb1a8c1f4192">outtknepdis</a>:1;
+<a name="l01093"></a>01093 
+<a name="l01094"></a><a class="code" href="uniondoepint__data.html#038fca8f1c03d7cfe323caa4f8bda126">01094</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondoepint__data.html#038fca8f1c03d7cfe323caa4f8bda126">stsphsercvd</a>:1;
+<a name="l01096"></a><a class="code" href="uniondoepint__data.html#84e49d0a3324691b004bedc6af146747">01096</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondoepint__data.html#84e49d0a3324691b004bedc6af146747">back2backsetup</a>:1;
+<a name="l01097"></a>01097 
+<a name="l01098"></a><a class="code" href="uniondoepint__data.html#97829cea3541ebb1fb07dd5b24f0d415">01098</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondoepint__data.html#97829cea3541ebb1fb07dd5b24f0d415">reserved7</a>:1;
+<a name="l01100"></a><a class="code" href="uniondoepint__data.html#dc9d4f243e80cd6796fcc334498fa4cc">01100</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondoepint__data.html#dc9d4f243e80cd6796fcc334498fa4cc">outpkterr</a>:1;
+<a name="l01102"></a><a class="code" href="uniondoepint__data.html#e68e77d553158195b16a790012f9627d">01102</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondoepint__data.html#e68e77d553158195b16a790012f9627d">bna</a>:1;
+<a name="l01103"></a>01103 
+<a name="l01104"></a><a class="code" href="uniondoepint__data.html#f01b0c085f14ead4c6fd5b1eafdcd497">01104</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondoepint__data.html#f01b0c085f14ead4c6fd5b1eafdcd497">reserved10</a>:1;
+<a name="l01106"></a><a class="code" href="uniondoepint__data.html#0c8fc4f5245a9874c0c3b61d1c6f719d">01106</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondoepint__data.html#0c8fc4f5245a9874c0c3b61d1c6f719d">pktdrpsts</a>:1;
+<a name="l01108"></a><a class="code" href="uniondoepint__data.html#c555371bda41092d89992523563dadbb">01108</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondoepint__data.html#c555371bda41092d89992523563dadbb">babble</a>:1;
+<a name="l01110"></a><a class="code" href="uniondoepint__data.html#2ac99fbbb1bcf135d5db41e096e8b95b">01110</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondoepint__data.html#2ac99fbbb1bcf135d5db41e096e8b95b">nak</a>:1;
+<a name="l01112"></a><a class="code" href="uniondoepint__data.html#f35ad8ba20b8941b6ad00dc75586454f">01112</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondoepint__data.html#f35ad8ba20b8941b6ad00dc75586454f">nyet</a>:1;
+<a name="l01113"></a>01113 
+<a name="l01114"></a><a class="code" href="uniondoepint__data.html#d5fb6ae977f62553cdc355128399468a">01114</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondoepint__data.html#d5fb6ae977f62553cdc355128399468a">reserved15_31</a>:17;
+<a name="l01115"></a>01115         } <a class="code" href="uniondoepint__data.html#9e966d9f85589f278dc2c0d0c7833856">b</a>;
+<a name="l01116"></a>01116 } <a class="code" href="uniondoepint__data.html">doepint_data_t</a>;
+<a name="l01117"></a>01117 
+<a name="l01122"></a><a class="code" href="dwc__otg__regs_8h.html#722a9ff3c92f6c195b9ee3c3838b6bbb">01122</a> <span class="keyword">typedef</span> <span class="keyword">union </span><a class="code" href="uniondoepint__data.html">doepint_data</a> <a class="code" href="dwc__otg__regs_8h.html#722a9ff3c92f6c195b9ee3c3838b6bbb">doepmsk_data_t</a>;
+<a name="l01123"></a>01123 
+<a name="l01130"></a><a class="code" href="uniondaint__data.html">01130</a> <span class="keyword">typedef</span> <span class="keyword">union </span><a class="code" href="uniondaint__data.html">daint_data</a> {
+<a name="l01132"></a><a class="code" href="uniondaint__data.html#cf05e79bf751384bef904448a231bc41">01132</a>         uint32_t <a class="code" href="uniondaint__data.html#cf05e79bf751384bef904448a231bc41">d32</a>;
+<a name="l01134"></a>01134         <span class="keyword">struct </span>{
+<a name="l01136"></a><a class="code" href="uniondaint__data.html#dbc4f689d070e6cbc112ec910f8bc36a">01136</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondaint__data.html#dbc4f689d070e6cbc112ec910f8bc36a">in</a>:16;
+<a name="l01138"></a><a class="code" href="uniondaint__data.html#8462ad2dc1692f1253b769445382e2d4">01138</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondaint__data.html#8462ad2dc1692f1253b769445382e2d4">out</a>:16;
+<a name="l01139"></a>01139         } <a class="code" href="uniondaint__data.html#5d048f0d5695317b05317d3c5ec4f79d">ep</a>;
+<a name="l01140"></a>01140         <span class="keyword">struct </span>{
+<a name="l01142"></a><a class="code" href="uniondaint__data.html#371eb39ddd249f984242ffc6bc2590ba">01142</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondaint__data.html#371eb39ddd249f984242ffc6bc2590ba">inep0</a>:1;
+<a name="l01143"></a><a class="code" href="uniondaint__data.html#af6849b786344ddee9cd7f884199434c">01143</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondaint__data.html#af6849b786344ddee9cd7f884199434c">inep1</a>:1;
+<a name="l01144"></a><a class="code" href="uniondaint__data.html#a52a2d17ef3dbea8fa25217629181a7c">01144</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondaint__data.html#a52a2d17ef3dbea8fa25217629181a7c">inep2</a>:1;
+<a name="l01145"></a><a class="code" href="uniondaint__data.html#7152eb0ccf903be2810d1e25fef9bfb5">01145</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondaint__data.html#7152eb0ccf903be2810d1e25fef9bfb5">inep3</a>:1;
+<a name="l01146"></a><a class="code" href="uniondaint__data.html#f1e4c6eb79afda585c260a93c111aa12">01146</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondaint__data.html#f1e4c6eb79afda585c260a93c111aa12">inep4</a>:1;
+<a name="l01147"></a><a class="code" href="uniondaint__data.html#4175dc0a3f230773225f0971c31bc129">01147</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondaint__data.html#4175dc0a3f230773225f0971c31bc129">inep5</a>:1;
+<a name="l01148"></a><a class="code" href="uniondaint__data.html#40b670d2fc2b799a6278a16326441b1f">01148</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondaint__data.html#40b670d2fc2b799a6278a16326441b1f">inep6</a>:1;
+<a name="l01149"></a><a class="code" href="uniondaint__data.html#8beeff7b54bd1902946425ab6a0d9d22">01149</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondaint__data.html#8beeff7b54bd1902946425ab6a0d9d22">inep7</a>:1;
+<a name="l01150"></a><a class="code" href="uniondaint__data.html#baf8f1fe4bde7d02d61c93b5c7059f57">01150</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondaint__data.html#baf8f1fe4bde7d02d61c93b5c7059f57">inep8</a>:1;
+<a name="l01151"></a><a class="code" href="uniondaint__data.html#ae119c728bcdf52e9504fedd16b0886b">01151</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondaint__data.html#ae119c728bcdf52e9504fedd16b0886b">inep9</a>:1;
+<a name="l01152"></a><a class="code" href="uniondaint__data.html#f7560a6b186b5a690382e443b12feee8">01152</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondaint__data.html#f7560a6b186b5a690382e443b12feee8">inep10</a>:1;
+<a name="l01153"></a><a class="code" href="uniondaint__data.html#67745fd9faa3ca8d8da6e937d782cc3e">01153</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondaint__data.html#67745fd9faa3ca8d8da6e937d782cc3e">inep11</a>:1;
+<a name="l01154"></a><a class="code" href="uniondaint__data.html#bbae9ce28263f0973e46ed65367f898b">01154</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondaint__data.html#bbae9ce28263f0973e46ed65367f898b">inep12</a>:1;
+<a name="l01155"></a><a class="code" href="uniondaint__data.html#dc51893893bfeddf1e842a89d778b6d8">01155</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondaint__data.html#dc51893893bfeddf1e842a89d778b6d8">inep13</a>:1;
+<a name="l01156"></a><a class="code" href="uniondaint__data.html#8235ebce9e66c2d0e76edf7a1a5cd877">01156</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondaint__data.html#8235ebce9e66c2d0e76edf7a1a5cd877">inep14</a>:1;
+<a name="l01157"></a><a class="code" href="uniondaint__data.html#419952bb56b11f01e7f0995e138237de">01157</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondaint__data.html#419952bb56b11f01e7f0995e138237de">inep15</a>:1;
+<a name="l01159"></a><a class="code" href="uniondaint__data.html#c7e9083edca852fb7f2f64e8671aee84">01159</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondaint__data.html#c7e9083edca852fb7f2f64e8671aee84">outep0</a>:1;
+<a name="l01160"></a><a class="code" href="uniondaint__data.html#32fab893aee2c30b343fcef45a2b663b">01160</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondaint__data.html#32fab893aee2c30b343fcef45a2b663b">outep1</a>:1;
+<a name="l01161"></a><a class="code" href="uniondaint__data.html#ab37e9518e23799029192a422ca6a3ca">01161</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondaint__data.html#ab37e9518e23799029192a422ca6a3ca">outep2</a>:1;
+<a name="l01162"></a><a class="code" href="uniondaint__data.html#db7e607293c77325f6940d33c56bc502">01162</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondaint__data.html#db7e607293c77325f6940d33c56bc502">outep3</a>:1;
+<a name="l01163"></a><a class="code" href="uniondaint__data.html#17ad350597358b4795cf861409ba228c">01163</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondaint__data.html#17ad350597358b4795cf861409ba228c">outep4</a>:1;
+<a name="l01164"></a><a class="code" href="uniondaint__data.html#d50c4c8564d64cc4c176bcadd031b625">01164</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondaint__data.html#d50c4c8564d64cc4c176bcadd031b625">outep5</a>:1;
+<a name="l01165"></a><a class="code" href="uniondaint__data.html#d23b2e895318d194c683f2c6bb2ccbbe">01165</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondaint__data.html#d23b2e895318d194c683f2c6bb2ccbbe">outep6</a>:1;
+<a name="l01166"></a><a class="code" href="uniondaint__data.html#f8891bc2ff5fe8989c5119461e6ab126">01166</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondaint__data.html#f8891bc2ff5fe8989c5119461e6ab126">outep7</a>:1;
+<a name="l01167"></a><a class="code" href="uniondaint__data.html#29c28a7d96343bfcc1f43faa72e83722">01167</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondaint__data.html#29c28a7d96343bfcc1f43faa72e83722">outep8</a>:1;
+<a name="l01168"></a><a class="code" href="uniondaint__data.html#8ad45fbc3efeb84ed83dc44b80e83c05">01168</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondaint__data.html#8ad45fbc3efeb84ed83dc44b80e83c05">outep9</a>:1;
+<a name="l01169"></a><a class="code" href="uniondaint__data.html#1c2f136c1e7820cb09f31b7d7e8ddcf4">01169</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondaint__data.html#1c2f136c1e7820cb09f31b7d7e8ddcf4">outep10</a>:1;
+<a name="l01170"></a><a class="code" href="uniondaint__data.html#f1df69d381a3a93148371edd890f375e">01170</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondaint__data.html#f1df69d381a3a93148371edd890f375e">outep11</a>:1;
+<a name="l01171"></a><a class="code" href="uniondaint__data.html#fc51e98e345b027d0e015cebe87914a3">01171</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondaint__data.html#fc51e98e345b027d0e015cebe87914a3">outep12</a>:1;
+<a name="l01172"></a><a class="code" href="uniondaint__data.html#fdb431a548b60ebf8ca6aea82c64b841">01172</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondaint__data.html#fdb431a548b60ebf8ca6aea82c64b841">outep13</a>:1;
+<a name="l01173"></a><a class="code" href="uniondaint__data.html#14a49a0718676557899e5f121583778e">01173</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondaint__data.html#14a49a0718676557899e5f121583778e">outep14</a>:1;
+<a name="l01174"></a><a class="code" href="uniondaint__data.html#f3223d420d13e35899760843900cc8ea">01174</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondaint__data.html#f3223d420d13e35899760843900cc8ea">outep15</a>:1;
+<a name="l01175"></a>01175         } b;
+<a name="l01176"></a>01176 } <a class="code" href="uniondaint__data.html">daint_data_t</a>;
+<a name="l01177"></a>01177 
+<a name="l01184"></a><a class="code" href="uniondtknq1__data.html">01184</a> <span class="keyword">typedef</span> <span class="keyword">union </span><a class="code" href="uniondtknq1__data.html">dtknq1_data</a> {
+<a name="l01186"></a><a class="code" href="uniondtknq1__data.html#86015789f75da8cd507db3766fe93fef">01186</a>         uint32_t <a class="code" href="uniondtknq1__data.html#86015789f75da8cd507db3766fe93fef">d32</a>;
+<a name="l01188"></a>01188         <span class="keyword">struct </span>{
+<a name="l01190"></a><a class="code" href="uniondtknq1__data.html#33b25ddce8afe3ac2d8736f42133c284">01190</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondtknq1__data.html#33b25ddce8afe3ac2d8736f42133c284">intknwptr</a>:5;
+<a name="l01192"></a><a class="code" href="uniondtknq1__data.html#08d3442422c47ce894571c92470195c9">01192</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondtknq1__data.html#08d3442422c47ce894571c92470195c9">reserved05_06</a>:2;
+<a name="l01194"></a><a class="code" href="uniondtknq1__data.html#9ae9021519e7fa501c86093c7718dbb4">01194</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondtknq1__data.html#9ae9021519e7fa501c86093c7718dbb4">wrap_bit</a>:1;
+<a name="l01196"></a><a class="code" href="uniondtknq1__data.html#b35b4b7cfebfe54904ac0d74bb771825">01196</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondtknq1__data.html#b35b4b7cfebfe54904ac0d74bb771825">epnums0_5</a>:24;
+<a name="l01197"></a>01197         } <a class="code" href="uniondtknq1__data.html#fffe59f9a5f7cdf1ece03cf43caff69d">b</a>;
+<a name="l01198"></a>01198 } <a class="code" href="uniondtknq1__data.html">dtknq1_data_t</a>;
+<a name="l01199"></a>01199 
+<a name="l01205"></a><a class="code" href="uniondthrctl__data.html">01205</a> <span class="keyword">typedef</span> <span class="keyword">union </span><a class="code" href="uniondthrctl__data.html">dthrctl_data</a> {
+<a name="l01207"></a><a class="code" href="uniondthrctl__data.html#f66c52fe9278bb6ed52c811ddbed16a5">01207</a>         uint32_t <a class="code" href="uniondthrctl__data.html#f66c52fe9278bb6ed52c811ddbed16a5">d32</a>;
+<a name="l01209"></a>01209         <span class="keyword">struct </span>{
+<a name="l01211"></a><a class="code" href="uniondthrctl__data.html#9b9e309f454fb10621cbaeafe068af47">01211</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondthrctl__data.html#9b9e309f454fb10621cbaeafe068af47">non_iso_thr_en</a>:1;
+<a name="l01213"></a><a class="code" href="uniondthrctl__data.html#f69727f09d4443c01038ba7b163814f8">01213</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondthrctl__data.html#f69727f09d4443c01038ba7b163814f8">iso_thr_en</a>:1;
+<a name="l01215"></a><a class="code" href="uniondthrctl__data.html#75959c97b938bf99faa602c933938340">01215</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondthrctl__data.html#75959c97b938bf99faa602c933938340">tx_thr_len</a>:9;
+<a name="l01217"></a><a class="code" href="uniondthrctl__data.html#00bbf39ee16616cc14410549c1e97c45">01217</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondthrctl__data.html#00bbf39ee16616cc14410549c1e97c45">ahb_thr_ratio</a>:2;
+<a name="l01219"></a><a class="code" href="uniondthrctl__data.html#a9f51dc49f7e07a49dc8fad22699fa6c">01219</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondthrctl__data.html#a9f51dc49f7e07a49dc8fad22699fa6c">reserved13_15</a>:3;
+<a name="l01221"></a><a class="code" href="uniondthrctl__data.html#0a73132b4e481b250e1b5f533b807bcb">01221</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondthrctl__data.html#0a73132b4e481b250e1b5f533b807bcb">rx_thr_en</a>:1;
+<a name="l01223"></a><a class="code" href="uniondthrctl__data.html#210370ba2134a296e1c1dcc8b2f05461">01223</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondthrctl__data.html#210370ba2134a296e1c1dcc8b2f05461">rx_thr_len</a>:9;
+<a name="l01225"></a><a class="code" href="uniondthrctl__data.html#79c053fcb32c8fdceffebf8dda9f3785">01225</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondthrctl__data.html#79c053fcb32c8fdceffebf8dda9f3785">reserved26_31</a>:6;
+<a name="l01226"></a>01226         } <a class="code" href="uniondthrctl__data.html#298be6991ca44e5e1ca558471789d33f">b</a>;
+<a name="l01227"></a>01227 } <a class="code" href="uniondthrctl__data.html">dthrctl_data_t</a>;
+<a name="l01228"></a>01228 
+<a name="l01239"></a><a class="code" href="structdwc__otg__dev__in__ep__regs.html">01239</a> <span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code" href="structdwc__otg__dev__in__ep__regs.html">dwc_otg_dev_in_ep_regs</a> {
+<a name="l01242"></a><a class="code" href="structdwc__otg__dev__in__ep__regs.html#53a5adb977e2aec66d4902c6ba293216">01242</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__dev__in__ep__regs.html#53a5adb977e2aec66d4902c6ba293216">diepctl</a>;
+<a name="l01244"></a><a class="code" href="structdwc__otg__dev__in__ep__regs.html#4a6af6187ad26a0059b4b2b4706aaa6d">01244</a>         uint32_t <a class="code" href="structdwc__otg__dev__in__ep__regs.html#4a6af6187ad26a0059b4b2b4706aaa6d">reserved04</a>;
+<a name="l01247"></a><a class="code" href="structdwc__otg__dev__in__ep__regs.html#4d6d6309ef5e09ad9048655ced6a2769">01247</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__dev__in__ep__regs.html#4d6d6309ef5e09ad9048655ced6a2769">diepint</a>;
+<a name="l01249"></a><a class="code" href="structdwc__otg__dev__in__ep__regs.html#6d896f525592c1e1d12d33dba999ccd6">01249</a>         uint32_t <a class="code" href="structdwc__otg__dev__in__ep__regs.html#6d896f525592c1e1d12d33dba999ccd6">reserved0C</a>;
+<a name="l01252"></a><a class="code" href="structdwc__otg__dev__in__ep__regs.html#88f637b5a4e8a0c6bc87d157072255dd">01252</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__dev__in__ep__regs.html#88f637b5a4e8a0c6bc87d157072255dd">dieptsiz</a>;
+<a name="l01255"></a><a class="code" href="structdwc__otg__dev__in__ep__regs.html#5f013840a15e0a310b8722646880a420">01255</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__dev__in__ep__regs.html#5f013840a15e0a310b8722646880a420">diepdma</a>;
+<a name="l01258"></a><a class="code" href="structdwc__otg__dev__in__ep__regs.html#90db7d3ed2dd087e0a55a1465deb21c9">01258</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__dev__in__ep__regs.html#90db7d3ed2dd087e0a55a1465deb21c9">dtxfsts</a>;
+<a name="l01261"></a><a class="code" href="structdwc__otg__dev__in__ep__regs.html#aa24ec8b19877c7f2f20802afc6f9cef">01261</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__dev__in__ep__regs.html#aa24ec8b19877c7f2f20802afc6f9cef">diepdmab</a>;
+<a name="l01262"></a>01262 } <a class="code" href="structdwc__otg__dev__in__ep__regs.html">dwc_otg_dev_in_ep_regs_t</a>;
+<a name="l01263"></a>01263 
+<a name="l01274"></a><a class="code" href="structdwc__otg__dev__out__ep__regs.html">01274</a> <span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code" href="structdwc__otg__dev__out__ep__regs.html">dwc_otg_dev_out_ep_regs</a> {
+<a name="l01277"></a><a class="code" href="structdwc__otg__dev__out__ep__regs.html#2a522b71fc97658c07debf3521f7d3e5">01277</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__dev__out__ep__regs.html#2a522b71fc97658c07debf3521f7d3e5">doepctl</a>;
+<a name="l01280"></a><a class="code" href="structdwc__otg__dev__out__ep__regs.html#f23e8e9750d99b1c4b5ac0c674e8733e">01280</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__dev__out__ep__regs.html#f23e8e9750d99b1c4b5ac0c674e8733e">doepfn</a>;
+<a name="l01283"></a><a class="code" href="structdwc__otg__dev__out__ep__regs.html#81d837c801dcfa30f17b567419a86f62">01283</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__dev__out__ep__regs.html#81d837c801dcfa30f17b567419a86f62">doepint</a>;
+<a name="l01285"></a><a class="code" href="structdwc__otg__dev__out__ep__regs.html#9e4014081779b42d9da9a59b2361fe9b">01285</a>         uint32_t <a class="code" href="structdwc__otg__dev__out__ep__regs.html#9e4014081779b42d9da9a59b2361fe9b">reserved0C</a>;
+<a name="l01288"></a><a class="code" href="structdwc__otg__dev__out__ep__regs.html#e756ec48787099f0a4e2ce353fce4f91">01288</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__dev__out__ep__regs.html#e756ec48787099f0a4e2ce353fce4f91">doeptsiz</a>;
+<a name="l01291"></a><a class="code" href="structdwc__otg__dev__out__ep__regs.html#006071bf54bfa1c1f5e25cf4c9f65cb1">01291</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__dev__out__ep__regs.html#006071bf54bfa1c1f5e25cf4c9f65cb1">doepdma</a>;
+<a name="l01293"></a><a class="code" href="structdwc__otg__dev__out__ep__regs.html#f78d72b82ee55e6a35cada1bd89d5659">01293</a>         uint32_t <a class="code" href="structdwc__otg__dev__out__ep__regs.html#f78d72b82ee55e6a35cada1bd89d5659">unused</a>;
+<a name="l01296"></a><a class="code" href="structdwc__otg__dev__out__ep__regs.html#baff3c1aea7aed57a42fa0015f15e0fa">01296</a>         uint32_t <a class="code" href="structdwc__otg__dev__out__ep__regs.html#baff3c1aea7aed57a42fa0015f15e0fa">doepdmab</a>;
+<a name="l01297"></a>01297 } <a class="code" href="structdwc__otg__dev__out__ep__regs.html">dwc_otg_dev_out_ep_regs_t</a>;
+<a name="l01298"></a>01298 
+<a name="l01304"></a><a class="code" href="uniondepctl__data.html">01304</a> <span class="keyword">typedef</span> <span class="keyword">union </span><a class="code" href="uniondepctl__data.html">depctl_data</a> {
+<a name="l01306"></a><a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">01306</a>         uint32_t <a class="code" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a>;
+<a name="l01308"></a>01308         <span class="keyword">struct </span>{
+<a name="l01316"></a><a class="code" href="uniondepctl__data.html#5899d20333186341271c2d0b7781b98c">01316</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondepctl__data.html#5899d20333186341271c2d0b7781b98c">mps</a>:11;
+<a name="l01317"></a><a class="code" href="dwc__otg__regs_8h.html#8ed30be9c5fc70ceb62f8e974ef5d58f">01317</a> <span class="preprocessor">#define DWC_DEP0CTL_MPS_64       0</span>
+<a name="l01318"></a><a class="code" href="dwc__otg__regs_8h.html#1571f704fa9a27aed09f5bf9f1fee3cd">01318</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_DEP0CTL_MPS_32       1</span>
+<a name="l01319"></a><a class="code" href="dwc__otg__regs_8h.html#f5eb5941743a925692ca3008e795f0c9">01319</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_DEP0CTL_MPS_16       2</span>
+<a name="l01320"></a><a class="code" href="dwc__otg__regs_8h.html#3207e5140ff0395b34f637942ab5b191">01320</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_DEP0CTL_MPS_8        3</span>
+<a name="l01321"></a>01321 <span class="preprocessor"></span>
+<a name="l01325"></a><a class="code" href="uniondepctl__data.html#3bdea97ec728985cbc4b9305f3ed8e96">01325</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondepctl__data.html#3bdea97ec728985cbc4b9305f3ed8e96">nextep</a>:4;
+<a name="l01326"></a>01326 
+<a name="l01328"></a><a class="code" href="uniondepctl__data.html#2ddb1e68ac29dfc383dacd94f76b4710">01328</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondepctl__data.html#2ddb1e68ac29dfc383dacd94f76b4710">usbactep</a>:1;
+<a name="l01329"></a>01329 
+<a name="l01344"></a><a class="code" href="uniondepctl__data.html#ea2f031d4f4dd0580caa5707d50dd0c1">01344</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondepctl__data.html#ea2f031d4f4dd0580caa5707d50dd0c1">dpid</a>:1;
+<a name="l01345"></a>01345 
+<a name="l01347"></a><a class="code" href="uniondepctl__data.html#98d3916b91f9d3d6c460d0ffaffd7b8b">01347</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondepctl__data.html#98d3916b91f9d3d6c460d0ffaffd7b8b">naksts</a>:1;
+<a name="l01348"></a>01348 
+<a name="l01354"></a><a class="code" href="uniondepctl__data.html#f119782e7db731a3d4bf6c500b4ba5d2">01354</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondepctl__data.html#f119782e7db731a3d4bf6c500b4ba5d2">eptype</a>:2;
+<a name="l01355"></a>01355 
+<a name="l01359"></a><a class="code" href="uniondepctl__data.html#27d9b0c9fa7b2c1a053d1ec7a1f69962">01359</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondepctl__data.html#27d9b0c9fa7b2c1a053d1ec7a1f69962">snp</a>:1;
+<a name="l01360"></a>01360 
+<a name="l01362"></a><a class="code" href="uniondepctl__data.html#f7ad1bcf91d28b8a4aa8d3a343dd83e4">01362</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondepctl__data.html#f7ad1bcf91d28b8a4aa8d3a343dd83e4">stall</a>:1;
+<a name="l01363"></a>01363 
+<a name="l01367"></a><a class="code" href="uniondepctl__data.html#89fd2f9f2183a32181e9a04bf3251c43">01367</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondepctl__data.html#89fd2f9f2183a32181e9a04bf3251c43">txfnum</a>:4;
+<a name="l01368"></a>01368 
+<a name="l01370"></a><a class="code" href="uniondepctl__data.html#0b87d0914ceee7a20ffd2d7510b6a72e">01370</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondepctl__data.html#0b87d0914ceee7a20ffd2d7510b6a72e">cnak</a>:1;
+<a name="l01372"></a><a class="code" href="uniondepctl__data.html#ccf6e60ac8cabde8da36edb19504ba2b">01372</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondepctl__data.html#ccf6e60ac8cabde8da36edb19504ba2b">snak</a>:1;
+<a name="l01381"></a><a class="code" href="uniondepctl__data.html#90d89b642aafd60a6c62db5bf8396de9">01381</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondepctl__data.html#90d89b642aafd60a6c62db5bf8396de9">setd0pid</a>:1;
+<a name="l01389"></a><a class="code" href="uniondepctl__data.html#9c0962acc0c23fe46a7738ad36634c25">01389</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondepctl__data.html#9c0962acc0c23fe46a7738ad36634c25">setd1pid</a>:1;
+<a name="l01390"></a>01390 
+<a name="l01392"></a><a class="code" href="uniondepctl__data.html#4d76ba4ebd506d3175ec5cdc0d811654">01392</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondepctl__data.html#4d76ba4ebd506d3175ec5cdc0d811654">epdis</a>:1;
+<a name="l01394"></a><a class="code" href="uniondepctl__data.html#337ceb41a9e0735e144e684b1f9e5368">01394</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondepctl__data.html#337ceb41a9e0735e144e684b1f9e5368">epena</a>:1;
+<a name="l01395"></a>01395         } <a class="code" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a>;
+<a name="l01396"></a>01396 } <a class="code" href="uniondepctl__data.html">depctl_data_t</a>;
+<a name="l01397"></a>01397 
+<a name="l01403"></a><a class="code" href="uniondeptsiz__data.html">01403</a> <span class="keyword">typedef</span> <span class="keyword">union </span><a class="code" href="uniondeptsiz__data.html">deptsiz_data</a> {
+<a name="l01405"></a><a class="code" href="uniondeptsiz__data.html#10c2b2ba8b419b0a766430a59befbbe0">01405</a>         uint32_t <a class="code" href="uniondeptsiz__data.html#10c2b2ba8b419b0a766430a59befbbe0">d32</a>;
+<a name="l01407"></a>01407         <span class="keyword">struct </span>{
+<a name="l01409"></a><a class="code" href="uniondeptsiz__data.html#cf06327d851e7cfe5c442b29bf2d6fa4">01409</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondeptsiz__data.html#cf06327d851e7cfe5c442b29bf2d6fa4">xfersize</a>:19;
+<a name="l01411"></a><a class="code" href="uniondeptsiz__data.html#bbd89e812371e5b555bb82373f3643d9">01411</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondeptsiz__data.html#bbd89e812371e5b555bb82373f3643d9">pktcnt</a>:10;
+<a name="l01413"></a><a class="code" href="uniondeptsiz__data.html#45a97381fba9a7d9c3bde425334a60a5">01413</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondeptsiz__data.html#45a97381fba9a7d9c3bde425334a60a5">mc</a>:2;
+<a name="l01414"></a><a class="code" href="uniondeptsiz__data.html#19515de87199335d65ebbd0e04a13f87">01414</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondeptsiz__data.html#19515de87199335d65ebbd0e04a13f87">reserved</a>:1;
+<a name="l01415"></a>01415         } <a class="code" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a>;
+<a name="l01416"></a>01416 } <a class="code" href="uniondeptsiz__data.html">deptsiz_data_t</a>;
+<a name="l01417"></a>01417 
+<a name="l01423"></a><a class="code" href="uniondeptsiz0__data.html">01423</a> <span class="keyword">typedef</span> <span class="keyword">union </span><a class="code" href="uniondeptsiz0__data.html">deptsiz0_data</a> {
+<a name="l01425"></a><a class="code" href="uniondeptsiz0__data.html#a06fa9b1dcaee47fba9cf869027ed6f1">01425</a>         uint32_t <a class="code" href="uniondeptsiz0__data.html#a06fa9b1dcaee47fba9cf869027ed6f1">d32</a>;
+<a name="l01427"></a>01427         <span class="keyword">struct </span>{
+<a name="l01429"></a><a class="code" href="uniondeptsiz0__data.html#1792e672dde70ead19bd0f5e7642af03">01429</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondeptsiz0__data.html#1792e672dde70ead19bd0f5e7642af03">xfersize</a>:7;
+<a name="l01431"></a><a class="code" href="uniondeptsiz0__data.html#c7fc04a01e440f0ed58541fd64a1b9be">01431</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondeptsiz0__data.html#c7fc04a01e440f0ed58541fd64a1b9be">reserved7_18</a>:12;
+<a name="l01433"></a><a class="code" href="uniondeptsiz0__data.html#debb8f273e4480cde57bef7677697bd0">01433</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondeptsiz0__data.html#debb8f273e4480cde57bef7677697bd0">pktcnt</a>:1;
+<a name="l01435"></a><a class="code" href="uniondeptsiz0__data.html#6a0d46284aeed1dd01b301ec503cc5c4">01435</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondeptsiz0__data.html#6a0d46284aeed1dd01b301ec503cc5c4">reserved20_28</a>:9;
+<a name="l01437"></a><a class="code" href="uniondeptsiz0__data.html#60123707d51d7dfa22cd6b245402e49b">01437</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondeptsiz0__data.html#60123707d51d7dfa22cd6b245402e49b">supcnt</a>:2;
+<a name="l01438"></a><a class="code" href="uniondeptsiz0__data.html#54b64c3a39b487b090048869c4a237e1">01438</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondeptsiz0__data.html#54b64c3a39b487b090048869c4a237e1">reserved31</a>;
+<a name="l01439"></a>01439         } <a class="code" href="uniondeptsiz0__data.html#8e50594573fd774fc3e27404d8b1f59c">b</a>;
+<a name="l01440"></a>01440 } <a class="code" href="uniondeptsiz0__data.html">deptsiz0_data_t</a>;
+<a name="l01441"></a>01441 
+<a name="l01443"></a>01443 <span class="comment">// DMA Descriptor Specific Structures</span>
+<a name="l01444"></a>01444 <span class="comment">//</span>
+<a name="l01445"></a>01445 
+<a name="l01448"></a><a class="code" href="dwc__otg__regs_8h.html#c2cfc53da94087a90d21d3528b005bcf">01448</a> <span class="preprocessor">#define BS_HOST_READY   0x0</span>
+<a name="l01449"></a><a class="code" href="dwc__otg__regs_8h.html#3110b1318d89fe11ee69f3ccbe219c4e">01449</a> <span class="preprocessor"></span><span class="preprocessor">#define BS_DMA_BUSY             0x1</span>
+<a name="l01450"></a><a class="code" href="dwc__otg__regs_8h.html#b20f6432003d81072ed8b7cd66d6305b">01450</a> <span class="preprocessor"></span><span class="preprocessor">#define BS_DMA_DONE             0x2</span>
+<a name="l01451"></a><a class="code" href="dwc__otg__regs_8h.html#e6e96a79797557986256d1a1ff104ca1">01451</a> <span class="preprocessor"></span><span class="preprocessor">#define BS_HOST_BUSY    0x3</span>
+<a name="l01452"></a>01452 <span class="preprocessor"></span>
+<a name="l01455"></a><a class="code" href="dwc__otg__regs_8h.html#cc9b21a293ad5a9103a64d76314a052e">01455</a> <span class="preprocessor">#define RTS_SUCCESS             0x0</span>
+<a name="l01456"></a><a class="code" href="dwc__otg__regs_8h.html#46f9d43df5fef233f4f5415d4719c1da">01456</a> <span class="preprocessor"></span><span class="preprocessor">#define RTS_BUFFLUSH    0x1</span>
+<a name="l01457"></a><a class="code" href="dwc__otg__regs_8h.html#1fa264096eca908e709d19b87a53f13f">01457</a> <span class="preprocessor"></span><span class="preprocessor">#define RTS_RESERVED    0x2</span>
+<a name="l01458"></a><a class="code" href="dwc__otg__regs_8h.html#55b69fa65e7d41448646c88fc0642408">01458</a> <span class="preprocessor"></span><span class="preprocessor">#define RTS_BUFERR              0x3</span>
+<a name="l01459"></a>01459 <span class="preprocessor"></span>
+<a name="l01466"></a><a class="code" href="uniondev__dma__desc__sts.html">01466</a> <span class="keyword">typedef</span> <span class="keyword">union </span><a class="code" href="uniondev__dma__desc__sts.html">dev_dma_desc_sts</a> {
+<a name="l01468"></a><a class="code" href="uniondev__dma__desc__sts.html#fb77b9c4ab63304073542ed2b118a64b">01468</a>         uint32_t <a class="code" href="uniondev__dma__desc__sts.html#fb77b9c4ab63304073542ed2b118a64b">d32</a>;
+<a name="l01470"></a>01470         <span class="keyword">struct </span>{
+<a name="l01472"></a><a class="code" href="uniondev__dma__desc__sts.html#9b6181d78984cb4d853945774f300ef0">01472</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondev__dma__desc__sts.html#9b6181d78984cb4d853945774f300ef0">bytes</a>:16;
+<a name="l01473"></a>01473 
+<a name="l01474"></a><a class="code" href="uniondev__dma__desc__sts.html#a87eecf4647accc23a4e409c6c2ad47c">01474</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondev__dma__desc__sts.html#a87eecf4647accc23a4e409c6c2ad47c">reserved16_22</a>:7;
+<a name="l01476"></a><a class="code" href="uniondev__dma__desc__sts.html#01c54383fd48fc31a3dd93ef54c417e8">01476</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondev__dma__desc__sts.html#01c54383fd48fc31a3dd93ef54c417e8">mtrf</a>:1;
+<a name="l01478"></a><a class="code" href="uniondev__dma__desc__sts.html#88d65d05f6561525543d09d0137c8967">01478</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondev__dma__desc__sts.html#88d65d05f6561525543d09d0137c8967">sr</a>:1;
+<a name="l01480"></a><a class="code" href="uniondev__dma__desc__sts.html#02c8be72ef6258c25094478c7cac0b12">01480</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondev__dma__desc__sts.html#02c8be72ef6258c25094478c7cac0b12">ioc</a>:1;
+<a name="l01482"></a><a class="code" href="uniondev__dma__desc__sts.html#a850ddfa13601227c05e0ae43a538a9d">01482</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondev__dma__desc__sts.html#a850ddfa13601227c05e0ae43a538a9d">sp</a>:1;
+<a name="l01484"></a><a class="code" href="uniondev__dma__desc__sts.html#b728a79d6a86a0d1b6426a1b2627f2c2">01484</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondev__dma__desc__sts.html#b728a79d6a86a0d1b6426a1b2627f2c2">l</a>:1;
+<a name="l01486"></a><a class="code" href="uniondev__dma__desc__sts.html#2be04f03ca64c3484260b2235aef3b9b">01486</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondev__dma__desc__sts.html#2be04f03ca64c3484260b2235aef3b9b">sts</a>:2;
+<a name="l01488"></a><a class="code" href="uniondev__dma__desc__sts.html#05d1c1d8f6c5a1967c51c5d0e2e04261">01488</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondev__dma__desc__sts.html#05d1c1d8f6c5a1967c51c5d0e2e04261">bs</a>:2;
+<a name="l01489"></a>01489         } <a class="code" href="uniondev__dma__desc__sts.html#1876c32496f0067948f6282b7583aeab">b</a>;
+<a name="l01490"></a>01490 
+<a name="l01491"></a>01491 <span class="preprocessor">#ifdef DWC_EN_ISOC</span>
+<a name="l01492"></a>01492 <span class="preprocessor"></span>
+<a name="l01493"></a>01493         <span class="keyword">struct </span>{
+<a name="l01495"></a><a class="code" href="uniondev__dma__desc__sts.html#ede78801cd7bc514474fcbe1ef154e5a">01495</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondev__dma__desc__sts.html#ede78801cd7bc514474fcbe1ef154e5a">rxbytes</a>:11;
+<a name="l01496"></a>01496 
+<a name="l01497"></a><a class="code" href="uniondev__dma__desc__sts.html#268998cfefef876150fff80a33ba70a6">01497</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondev__dma__desc__sts.html#268998cfefef876150fff80a33ba70a6">reserved11</a>:1;
+<a name="l01499"></a><a class="code" href="uniondev__dma__desc__sts.html#d9da3eccc6d247e2b5eccd4dfba7874e">01499</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondev__dma__desc__sts.html#d9da3eccc6d247e2b5eccd4dfba7874e">framenum</a>:11;
+<a name="l01501"></a><a class="code" href="uniondev__dma__desc__sts.html#79bf5fe6d9949ddb671daa14b5ee298e">01501</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondev__dma__desc__sts.html#79bf5fe6d9949ddb671daa14b5ee298e">pid</a>:2;
+<a name="l01503"></a>01503                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondev__dma__desc__sts.html#02c8be72ef6258c25094478c7cac0b12">ioc</a>:1;
+<a name="l01505"></a>01505                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondev__dma__desc__sts.html#a850ddfa13601227c05e0ae43a538a9d">sp</a>:1;
+<a name="l01507"></a>01507                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondev__dma__desc__sts.html#b728a79d6a86a0d1b6426a1b2627f2c2">l</a>:1;
+<a name="l01509"></a><a class="code" href="uniondev__dma__desc__sts.html#a80809cda5b19b3e36f512effef795f0">01509</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondev__dma__desc__sts.html#a80809cda5b19b3e36f512effef795f0">rxsts</a>:2;
+<a name="l01511"></a>01511                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondev__dma__desc__sts.html#05d1c1d8f6c5a1967c51c5d0e2e04261">bs</a>:2;
+<a name="l01512"></a>01512         } <a class="code" href="uniondev__dma__desc__sts.html#214ba099b6077c3393b179cf9a7909f7">b_iso_out</a>;
+<a name="l01513"></a>01513 
+<a name="l01515"></a>01515         <span class="keyword">struct </span>{
+<a name="l01517"></a><a class="code" href="uniondev__dma__desc__sts.html#56cc3ad6b0e5704c6eb394f58f660eef">01517</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondev__dma__desc__sts.html#56cc3ad6b0e5704c6eb394f58f660eef">txbytes</a>:12;
+<a name="l01519"></a>01519                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondev__dma__desc__sts.html#d9da3eccc6d247e2b5eccd4dfba7874e">framenum</a>:11;
+<a name="l01521"></a>01521                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondev__dma__desc__sts.html#79bf5fe6d9949ddb671daa14b5ee298e">pid</a>:2;
+<a name="l01523"></a>01523                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondev__dma__desc__sts.html#02c8be72ef6258c25094478c7cac0b12">ioc</a>:1;
+<a name="l01525"></a>01525                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondev__dma__desc__sts.html#a850ddfa13601227c05e0ae43a538a9d">sp</a>:1;
+<a name="l01527"></a>01527                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondev__dma__desc__sts.html#b728a79d6a86a0d1b6426a1b2627f2c2">l</a>:1;
+<a name="l01529"></a><a class="code" href="uniondev__dma__desc__sts.html#30ebc024572822f0803d28c95914a44c">01529</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondev__dma__desc__sts.html#30ebc024572822f0803d28c95914a44c">txsts</a>:2;
+<a name="l01531"></a>01531                 <span class="keywordtype">unsigned</span> <a class="code" href="uniondev__dma__desc__sts.html#05d1c1d8f6c5a1967c51c5d0e2e04261">bs</a>:2;
+<a name="l01532"></a>01532         } <a class="code" href="uniondev__dma__desc__sts.html#324fdd57830243334b74e0579b4e9f96">b_iso_in</a>;
+<a name="l01533"></a>01533 <span class="preprocessor">#endif                          </span><span class="comment">/* DWC_EN_ISOC */</span>
+<a name="l01534"></a>01534 } <a class="code" href="uniondev__dma__desc__sts.html">dev_dma_desc_sts_t</a>;
+<a name="l01535"></a>01535 
+<a name="l01542"></a><a class="code" href="structdwc__otg__dev__dma__desc.html">01542</a> <span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code" href="structdwc__otg__dev__dma__desc.html">dwc_otg_dev_dma_desc</a> {
+<a name="l01544"></a><a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">01544</a>         <a class="code" href="uniondev__dma__desc__sts.html">dev_dma_desc_sts_t</a> <a class="code" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a>;
+<a name="l01546"></a><a class="code" href="structdwc__otg__dev__dma__desc.html#0454dad420ef536fe5eb7c38ef764430">01546</a>         uint32_t <a class="code" href="structdwc__otg__dev__dma__desc.html#0454dad420ef536fe5eb7c38ef764430">buf</a>;
+<a name="l01547"></a>01547 } <a class="code" href="structdwc__otg__dev__dma__desc.html">dwc_otg_dev_dma_desc_t</a>;
+<a name="l01548"></a>01548 
+<a name="l01554"></a><a class="code" href="structdwc__otg__dev__if.html">01554</a> <span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code" href="structdwc__otg__dev__if.html">dwc_otg_dev_if</a> {
+<a name="l01558"></a><a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">01558</a>         <a class="code" href="structdwc__otg__dev__global__regs.html">dwc_otg_device_global_regs_t</a> *<a class="code" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a>;
+<a name="l01559"></a><a class="code" href="dwc__otg__regs_8h.html#4ea9445cbc89c8cc6bbf01c9dd7a9883">01559</a> <span class="preprocessor">#define DWC_DEV_GLOBAL_REG_OFFSET 0x800</span>
+<a name="l01560"></a>01560 <span class="preprocessor"></span>
+<a name="l01564"></a><a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">01564</a>         <a class="code" href="structdwc__otg__dev__in__ep__regs.html">dwc_otg_dev_in_ep_regs_t</a> *<a class="code" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a>[<a class="code" href="dwc__otg__core__if_8h.html#bfb88b45545f7685f668ac2f545674ec">MAX_EPS_CHANNELS</a>];
+<a name="l01565"></a><a class="code" href="dwc__otg__regs_8h.html#57eeaae2d9cf530fbae00d3f462cc7da">01565</a> <span class="preprocessor">#define DWC_DEV_IN_EP_REG_OFFSET 0x900</span>
+<a name="l01566"></a><a class="code" href="dwc__otg__regs_8h.html#c9c83030effbf067775d9111e4d90895">01566</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_EP_REG_OFFSET 0x20</span>
+<a name="l01567"></a>01567 <span class="preprocessor"></span>
+<a name="l01569"></a><a class="code" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">01569</a>         <a class="code" href="structdwc__otg__dev__out__ep__regs.html">dwc_otg_dev_out_ep_regs_t</a> *<a class="code" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">out_ep_regs</a>[<a class="code" href="dwc__otg__core__if_8h.html#bfb88b45545f7685f668ac2f545674ec">MAX_EPS_CHANNELS</a>];
+<a name="l01570"></a><a class="code" href="dwc__otg__regs_8h.html#7234e42a2bcd47aca0d67a414eb0598e">01570</a> <span class="preprocessor">#define DWC_DEV_OUT_EP_REG_OFFSET 0xB00</span>
+<a name="l01571"></a>01571 <span class="preprocessor"></span>
+<a name="l01572"></a>01572         <span class="comment">/* Device configuration information */</span>
+<a name="l01573"></a><a class="code" href="structdwc__otg__dev__if.html#8a602da4cbdc4fc88c785471426ed63c">01573</a>         uint8_t <a class="code" href="structdwc__otg__dev__if.html#8a602da4cbdc4fc88c785471426ed63c">speed</a>;                           
+<a name="l01574"></a><a class="code" href="structdwc__otg__dev__if.html#4fae9bc1293bf2e58966c38fa5b98822">01574</a>         uint8_t <a class="code" href="structdwc__otg__dev__if.html#4fae9bc1293bf2e58966c38fa5b98822">num_in_eps</a>;              
+<a name="l01575"></a><a class="code" href="structdwc__otg__dev__if.html#2f0e01cdc605623f591963fc83c8dc73">01575</a>         uint8_t <a class="code" href="structdwc__otg__dev__if.html#2f0e01cdc605623f591963fc83c8dc73">num_out_eps</a>;             
+<a name="l01578"></a><a class="code" href="structdwc__otg__dev__if.html#817a953b04c45cf346d7a7d6fc274150">01578</a>         uint16_t <a class="code" href="structdwc__otg__dev__if.html#817a953b04c45cf346d7a7d6fc274150">perio_tx_fifo_size</a>[<a class="code" href="dwc__otg__core__if_8h.html#13bb22067644d357537c2905fe5ffb8c">MAX_PERIO_FIFOS</a>];
+<a name="l01579"></a>01579 
+<a name="l01581"></a><a class="code" href="structdwc__otg__dev__if.html#ea32a81a3c0a752e6d6274f8fd6faef9">01581</a>         uint16_t <a class="code" href="structdwc__otg__dev__if.html#ea32a81a3c0a752e6d6274f8fd6faef9">tx_fifo_size</a>[<a class="code" href="dwc__otg__core__if_8h.html#050db6129005b993e573311dc42bc1a8">MAX_TX_FIFOS</a>];
+<a name="l01582"></a>01582 
+<a name="l01584"></a><a class="code" href="structdwc__otg__dev__if.html#839ada1cbeff50af91f5db00f4b36ec4">01584</a>         uint16_t <a class="code" href="structdwc__otg__dev__if.html#839ada1cbeff50af91f5db00f4b36ec4">rx_thr_en</a>;
+<a name="l01585"></a><a class="code" href="structdwc__otg__dev__if.html#76af117a05ad95e5e5c534a1afcdae22">01585</a>         uint16_t <a class="code" href="structdwc__otg__dev__if.html#76af117a05ad95e5e5c534a1afcdae22">iso_tx_thr_en</a>;
+<a name="l01586"></a><a class="code" href="structdwc__otg__dev__if.html#c4c1cdbb40f37e3403d62ae00b4819eb">01586</a>         uint16_t <a class="code" href="structdwc__otg__dev__if.html#c4c1cdbb40f37e3403d62ae00b4819eb">non_iso_tx_thr_en</a>;
+<a name="l01587"></a>01587 
+<a name="l01588"></a><a class="code" href="structdwc__otg__dev__if.html#e1ec98fc03446d7e172572a973107d62">01588</a>         uint16_t <a class="code" href="structdwc__otg__dev__if.html#e1ec98fc03446d7e172572a973107d62">rx_thr_length</a>;
+<a name="l01589"></a><a class="code" href="structdwc__otg__dev__if.html#55206f9ce7b0c2614e2c534d01acd6c4">01589</a>         uint16_t <a class="code" href="structdwc__otg__dev__if.html#55206f9ce7b0c2614e2c534d01acd6c4">tx_thr_length</a>;
+<a name="l01590"></a>01590 
+<a name="l01597"></a><a class="code" href="structdwc__otg__dev__if.html#fb3d3353afd5f9d08a8e49c48158cfb7">01597</a>         dwc_dma_t <a class="code" href="structdwc__otg__dev__if.html#fb3d3353afd5f9d08a8e49c48158cfb7">dma_setup_desc_addr</a>[2];
+<a name="l01598"></a><a class="code" href="structdwc__otg__dev__if.html#f149a6cbedd5f180ff033caeee6f527e">01598</a>         <a class="code" href="structdwc__otg__dev__dma__desc.html">dwc_otg_dev_dma_desc_t</a> *<a class="code" href="structdwc__otg__dev__if.html#f149a6cbedd5f180ff033caeee6f527e">setup_desc_addr</a>[2];
+<a name="l01599"></a>01599 
+<a name="l01601"></a><a class="code" href="structdwc__otg__dev__if.html#ade28f08143342505c705db1fc0865a9">01601</a>         <a class="code" href="structdwc__otg__dev__dma__desc.html">dwc_otg_dev_dma_desc_t</a> *<a class="code" href="structdwc__otg__dev__if.html#ade28f08143342505c705db1fc0865a9">psetup</a>;
+<a name="l01602"></a>01602 
+<a name="l01604"></a><a class="code" href="structdwc__otg__dev__if.html#dd45f3935b2ebb171de8da70cddd6935">01604</a>         uint32_t <a class="code" href="structdwc__otg__dev__if.html#dd45f3935b2ebb171de8da70cddd6935">setup_desc_index</a>;
+<a name="l01605"></a>01605 
+<a name="l01607"></a><a class="code" href="structdwc__otg__dev__if.html#ba2f5eede8b3deaaec8882baeea6a35b">01607</a>         dwc_dma_t <a class="code" href="structdwc__otg__dev__if.html#ba2f5eede8b3deaaec8882baeea6a35b">dma_in_desc_addr</a>;
+<a name="l01608"></a><a class="code" href="structdwc__otg__dev__if.html#99f44e328bbb4401aabd8e2708853238">01608</a>         <a class="code" href="structdwc__otg__dev__dma__desc.html">dwc_otg_dev_dma_desc_t</a> *<a class="code" href="structdwc__otg__dev__if.html#99f44e328bbb4401aabd8e2708853238">in_desc_addr</a>;
+<a name="l01609"></a>01609 
+<a name="l01611"></a><a class="code" href="structdwc__otg__dev__if.html#3829a415bbaf0f5c3e29b1a9f3cf546b">01611</a>         dwc_dma_t <a class="code" href="structdwc__otg__dev__if.html#3829a415bbaf0f5c3e29b1a9f3cf546b">dma_out_desc_addr</a>;
+<a name="l01612"></a><a class="code" href="structdwc__otg__dev__if.html#8cc9be8ccaba2ef93b02b34ba7b26bad">01612</a>         <a class="code" href="structdwc__otg__dev__dma__desc.html">dwc_otg_dev_dma_desc_t</a> *<a class="code" href="structdwc__otg__dev__if.html#8cc9be8ccaba2ef93b02b34ba7b26bad">out_desc_addr</a>;
+<a name="l01613"></a>01613 
+<a name="l01615"></a><a class="code" href="structdwc__otg__dev__if.html#aaabcd21be1be15804b0cf49119ce883">01615</a>         uint32_t <a class="code" href="structdwc__otg__dev__if.html#aaabcd21be1be15804b0cf49119ce883">spd</a>;
+<a name="l01616"></a>01616 
+<a name="l01617"></a>01617 } <a class="code" href="structdwc__otg__dev__if.html">dwc_otg_dev_if_t</a>;
+<a name="l01618"></a>01618 
+<a name="l01620"></a>01620 <span class="comment">// Host Mode Register Structures</span>
+<a name="l01621"></a>01621 <span class="comment">//</span>
+<a name="l01627"></a><a class="code" href="structdwc__otg__host__global__regs.html">01627</a> <span class="comment"></span><span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code" href="structdwc__otg__host__global__regs.html">dwc_otg_host_global_regs</a> {
+<a name="l01629"></a><a class="code" href="structdwc__otg__host__global__regs.html#fd7d93b5ffcb6c7c0a84ef656e6e68de">01629</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__host__global__regs.html#fd7d93b5ffcb6c7c0a84ef656e6e68de">hcfg</a>;
+<a name="l01631"></a><a class="code" href="structdwc__otg__host__global__regs.html#d5ad893315e7b0dde27a3c5867dc56d0">01631</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__host__global__regs.html#d5ad893315e7b0dde27a3c5867dc56d0">hfir</a>;
+<a name="l01633"></a><a class="code" href="structdwc__otg__host__global__regs.html#cebb0d86d0776473ef30eeac61e8692c">01633</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__host__global__regs.html#cebb0d86d0776473ef30eeac61e8692c">hfnum</a>;
+<a name="l01635"></a><a class="code" href="structdwc__otg__host__global__regs.html#fa21568e8b2f87538105f7109a9d1719">01635</a>         uint32_t <a class="code" href="structdwc__otg__host__global__regs.html#fa21568e8b2f87538105f7109a9d1719">reserved40C</a>;
+<a name="l01637"></a><a class="code" href="structdwc__otg__host__global__regs.html#bf1a1528a2e479d86318d49ecd52ee40">01637</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__host__global__regs.html#bf1a1528a2e479d86318d49ecd52ee40">hptxsts</a>;
+<a name="l01639"></a><a class="code" href="structdwc__otg__host__global__regs.html#7c41808b0a69ed7d2125eb3afbbf6c14">01639</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__host__global__regs.html#7c41808b0a69ed7d2125eb3afbbf6c14">haint</a>;
+<a name="l01641"></a><a class="code" href="structdwc__otg__host__global__regs.html#317f5059d4c2dc91da041f5c0a4819fc">01641</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__host__global__regs.html#317f5059d4c2dc91da041f5c0a4819fc">haintmsk</a>;
+<a name="l01643"></a><a class="code" href="structdwc__otg__host__global__regs.html#9a6af0a2c19d7b6228c7a40c9078907b">01643</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__host__global__regs.html#9a6af0a2c19d7b6228c7a40c9078907b">hflbaddr</a>;
+<a name="l01644"></a>01644 } <a class="code" href="structdwc__otg__host__global__regs.html">dwc_otg_host_global_regs_t</a>;
+<a name="l01645"></a>01645 
+<a name="l01646"></a>01646 
+<a name="l01652"></a><a class="code" href="unionhcfg__data.html">01652</a> <span class="keyword">typedef</span> <span class="keyword">union </span><a class="code" href="unionhcfg__data.html">hcfg_data</a>
+<a name="l01653"></a>01653 {
+<a name="l01655"></a><a class="code" href="unionhcfg__data.html#381a253b3a38a7f943dcbb42f7bf10be">01655</a>         uint32_t <a class="code" href="unionhcfg__data.html#381a253b3a38a7f943dcbb42f7bf10be">d32</a>;
+<a name="l01656"></a>01656 
+<a name="l01658"></a>01658         <span class="keyword">struct </span>
+<a name="l01659"></a>01659 <span class="keyword">        </span>{
+<a name="l01661"></a><a class="code" href="unionhcfg__data.html#e048ad3775c6794c3ee07af86079fadf">01661</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcfg__data.html#e048ad3775c6794c3ee07af86079fadf">fslspclksel</a>:2;
+<a name="l01662"></a><a class="code" href="dwc__otg__regs_8h.html#398b117902d7a5594388a5086bb2de21">01662</a> <span class="preprocessor">#define DWC_HCFG_30_60_MHZ 0</span>
+<a name="l01663"></a><a class="code" href="dwc__otg__regs_8h.html#556ba73fd9346d666a7c0a28fcf993a7">01663</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_HCFG_48_MHZ    1</span>
+<a name="l01664"></a><a class="code" href="dwc__otg__regs_8h.html#40a20b71af7ff9f23a2241a2e4c3c819">01664</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_HCFG_6_MHZ     2</span>
+<a name="l01665"></a>01665 <span class="preprocessor"></span>
+<a name="l01667"></a><a class="code" href="unionhcfg__data.html#c047f55e398b8a94aef27a66ed78f2de">01667</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcfg__data.html#c047f55e398b8a94aef27a66ed78f2de">fslssupp</a>:1;
+<a name="l01668"></a><a class="code" href="unionhcfg__data.html#fcbdeb7668bb4e9f6cf150052ae2d014">01668</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcfg__data.html#fcbdeb7668bb4e9f6cf150052ae2d014">reserved3_22</a> : 20;
+<a name="l01670"></a><a class="code" href="unionhcfg__data.html#7ec04d77b1c0d3cc25165e77e9bce5f4">01670</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcfg__data.html#7ec04d77b1c0d3cc25165e77e9bce5f4">descdma</a> : 1;
+<a name="l01672"></a><a class="code" href="unionhcfg__data.html#11340031265fce764f491b23ae42dda5">01672</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcfg__data.html#11340031265fce764f491b23ae42dda5">frlisten</a>: 2;
+<a name="l01674"></a><a class="code" href="unionhcfg__data.html#b49be9c0cbc3df2bb917e1ea96c99c62">01674</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcfg__data.html#b49be9c0cbc3df2bb917e1ea96c99c62">perschedena</a>: 1;
+<a name="l01676"></a><a class="code" href="unionhcfg__data.html#995a4d09381b8d6ce2c7ac0a6c7f364a">01676</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcfg__data.html#995a4d09381b8d6ce2c7ac0a6c7f364a">perschedstat</a>: 1;
+<a name="l01677"></a>01677         } <a class="code" href="unionhcfg__data.html#45bbb24387d58961dd2b8f2f65689bd7">b</a>;
+<a name="l01678"></a>01678 } <a class="code" href="unionhcfg__data.html">hcfg_data_t</a>;
+<a name="l01679"></a>01679 
+<a name="l01684"></a><a class="code" href="unionhfir__data.html">01684</a> <span class="keyword">typedef</span> <span class="keyword">union </span><a class="code" href="unionhfir__data.html">hfir_data</a> {
+<a name="l01686"></a><a class="code" href="unionhfir__data.html#859d5325dbf422643fb86695328c206d">01686</a>         uint32_t <a class="code" href="unionhfir__data.html#859d5325dbf422643fb86695328c206d">d32</a>;
+<a name="l01687"></a>01687 
+<a name="l01689"></a>01689         <span class="keyword">struct </span>{
+<a name="l01690"></a><a class="code" href="unionhfir__data.html#5302611bdf96e87f3a7f30319212bcc2">01690</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhfir__data.html#5302611bdf96e87f3a7f30319212bcc2">frint</a>:16;
+<a name="l01691"></a><a class="code" href="unionhfir__data.html#ea1f95b5e0c86d531a8d76a2784efe1d">01691</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhfir__data.html#ea1f95b5e0c86d531a8d76a2784efe1d">reserved</a>:16;
+<a name="l01692"></a>01692         } <a class="code" href="unionhfir__data.html#01ffc2aff6bf358564585c2ee7d513c8">b</a>;
+<a name="l01693"></a>01693 } <a class="code" href="unionhfir__data.html">hfir_data_t</a>;
+<a name="l01694"></a>01694 
+<a name="l01699"></a><a class="code" href="unionhfnum__data.html">01699</a> <span class="keyword">typedef</span> <span class="keyword">union </span><a class="code" href="unionhfnum__data.html">hfnum_data</a> {
+<a name="l01701"></a><a class="code" href="unionhfnum__data.html#e5ccbed3af86ac88577ded328e6c9932">01701</a>         uint32_t <a class="code" href="unionhfnum__data.html#e5ccbed3af86ac88577ded328e6c9932">d32</a>;
+<a name="l01702"></a>01702 
+<a name="l01704"></a>01704         <span class="keyword">struct </span>{
+<a name="l01705"></a><a class="code" href="unionhfnum__data.html#a64e8b6c4a1cd262dbc30e158f3cb8bc">01705</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhfnum__data.html#a64e8b6c4a1cd262dbc30e158f3cb8bc">frnum</a>:16;
+<a name="l01706"></a><a class="code" href="dwc__otg__regs_8h.html#4903938414e67044883b7df5582d6eed">01706</a> <span class="preprocessor">#define DWC_HFNUM_MAX_FRNUM 0x3FFF</span>
+<a name="l01707"></a><a class="code" href="unionhfnum__data.html#2a2ce50ebd4c4da5347a2d93c4bbc996">01707</a> <span class="preprocessor"></span>                <span class="keywordtype">unsigned</span> <a class="code" href="unionhfnum__data.html#2a2ce50ebd4c4da5347a2d93c4bbc996">frrem</a>:16;
+<a name="l01708"></a>01708         } <a class="code" href="unionhfnum__data.html#81df6fbd20a454665803eb5790855c66">b</a>;
+<a name="l01709"></a>01709 } <a class="code" href="unionhfnum__data.html">hfnum_data_t</a>;
+<a name="l01710"></a>01710 
+<a name="l01711"></a><a class="code" href="unionhptxsts__data.html">01711</a> <span class="keyword">typedef</span> <span class="keyword">union </span><a class="code" href="unionhptxsts__data.html">hptxsts_data</a> {
+<a name="l01713"></a><a class="code" href="unionhptxsts__data.html#b48d41d449d8f71c0b184b38029c26bc">01713</a>         uint32_t <a class="code" href="unionhptxsts__data.html#b48d41d449d8f71c0b184b38029c26bc">d32</a>;
+<a name="l01714"></a>01714 
+<a name="l01716"></a>01716         <span class="keyword">struct </span>{
+<a name="l01717"></a><a class="code" href="unionhptxsts__data.html#0df6fb1f76396da626715d6ffc06dfa8">01717</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhptxsts__data.html#0df6fb1f76396da626715d6ffc06dfa8">ptxfspcavail</a>:16;
+<a name="l01718"></a><a class="code" href="unionhptxsts__data.html#8139e6eafb7b0bbb3cbafa125d5cd28f">01718</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhptxsts__data.html#8139e6eafb7b0bbb3cbafa125d5cd28f">ptxqspcavail</a>:8;
+<a name="l01728"></a><a class="code" href="unionhptxsts__data.html#3c8a2ed8f4185130a28a452c0a9967f4">01728</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhptxsts__data.html#3c8a2ed8f4185130a28a452c0a9967f4">ptxqtop_terminate</a>:1;
+<a name="l01729"></a><a class="code" href="unionhptxsts__data.html#e51712fd406526683b5c3311bd3dab8d">01729</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhptxsts__data.html#e51712fd406526683b5c3311bd3dab8d">ptxqtop_token</a>:2;
+<a name="l01730"></a><a class="code" href="unionhptxsts__data.html#6fdf33c3add1fa286beaa252610b20ec">01730</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhptxsts__data.html#6fdf33c3add1fa286beaa252610b20ec">ptxqtop_chnum</a>:4;
+<a name="l01731"></a><a class="code" href="unionhptxsts__data.html#6b18b0bdf10050b08ac265e9143fdd63">01731</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhptxsts__data.html#6b18b0bdf10050b08ac265e9143fdd63">ptxqtop_odd</a>:1;
+<a name="l01732"></a>01732         } <a class="code" href="unionhptxsts__data.html#a6839185cc4aeabf771f04f1b2a97ec3">b</a>;
+<a name="l01733"></a>01733 } <a class="code" href="unionhptxsts__data.html">hptxsts_data_t</a>;
+<a name="l01734"></a>01734 
+<a name="l01741"></a><a class="code" href="unionhprt0__data.html">01741</a> <span class="keyword">typedef</span> <span class="keyword">union </span><a class="code" href="unionhprt0__data.html">hprt0_data</a> {
+<a name="l01743"></a><a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">01743</a>         uint32_t <a class="code" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a>;
+<a name="l01745"></a>01745         <span class="keyword">struct </span>{
+<a name="l01746"></a><a class="code" href="unionhprt0__data.html#39b2dee944be8ec96857a3b43d203390">01746</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhprt0__data.html#39b2dee944be8ec96857a3b43d203390">prtconnsts</a>:1;
+<a name="l01747"></a><a class="code" href="unionhprt0__data.html#5124a40eeafd92c9632c91a2c3132937">01747</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhprt0__data.html#5124a40eeafd92c9632c91a2c3132937">prtconndet</a>:1;
+<a name="l01748"></a><a class="code" href="unionhprt0__data.html#a964274b5d22e89ca4490f66dff3c763">01748</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhprt0__data.html#a964274b5d22e89ca4490f66dff3c763">prtena</a>:1;
+<a name="l01749"></a><a class="code" href="unionhprt0__data.html#75eae10eb537e49cc1ae2dc01c18aa47">01749</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhprt0__data.html#75eae10eb537e49cc1ae2dc01c18aa47">prtenchng</a>:1;
+<a name="l01750"></a><a class="code" href="unionhprt0__data.html#4d8f8b654c26760791614ccbc43f180c">01750</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhprt0__data.html#4d8f8b654c26760791614ccbc43f180c">prtovrcurract</a>:1;
+<a name="l01751"></a><a class="code" href="unionhprt0__data.html#cc51da1d52cb824d419ef3feb6ba70b6">01751</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhprt0__data.html#cc51da1d52cb824d419ef3feb6ba70b6">prtovrcurrchng</a>:1;
+<a name="l01752"></a><a class="code" href="unionhprt0__data.html#3f5961529636a3891a4ca9421dd535fa">01752</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhprt0__data.html#3f5961529636a3891a4ca9421dd535fa">prtres</a>:1;
+<a name="l01753"></a><a class="code" href="unionhprt0__data.html#e7fe71d6c465ae002211c24a6ba359d2">01753</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhprt0__data.html#e7fe71d6c465ae002211c24a6ba359d2">prtsusp</a>:1;
+<a name="l01754"></a><a class="code" href="unionhprt0__data.html#714a31048710164370292124795a9a9b">01754</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhprt0__data.html#714a31048710164370292124795a9a9b">prtrst</a>:1;
+<a name="l01755"></a><a class="code" href="unionhprt0__data.html#dda1ec89253bbfe9a1592a133fe2c392">01755</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhprt0__data.html#dda1ec89253bbfe9a1592a133fe2c392">reserved9</a>:1;
+<a name="l01756"></a><a class="code" href="unionhprt0__data.html#85a83fc17905d43dc604dce7f0869c63">01756</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhprt0__data.html#85a83fc17905d43dc604dce7f0869c63">prtlnsts</a>:2;
+<a name="l01757"></a><a class="code" href="unionhprt0__data.html#010bd8fb208ef4eeaa288b28f8f8c3a4">01757</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhprt0__data.html#010bd8fb208ef4eeaa288b28f8f8c3a4">prtpwr</a>:1;
+<a name="l01758"></a><a class="code" href="unionhprt0__data.html#c61d714ff8f0bc62767342523347ba66">01758</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhprt0__data.html#c61d714ff8f0bc62767342523347ba66">prttstctl</a>:4;
+<a name="l01759"></a><a class="code" href="unionhprt0__data.html#59f1c27b8c912de0237d2d2974fc2a22">01759</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhprt0__data.html#59f1c27b8c912de0237d2d2974fc2a22">prtspd</a>:2;
+<a name="l01760"></a><a class="code" href="dwc__otg__regs_8h.html#4556f79078df2164a8162fa8144142a0">01760</a> <span class="preprocessor">#define DWC_HPRT0_PRTSPD_HIGH_SPEED 0</span>
+<a name="l01761"></a><a class="code" href="dwc__otg__regs_8h.html#1d144361f6655bb79e7503e7159e6be5">01761</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_HPRT0_PRTSPD_FULL_SPEED 1</span>
+<a name="l01762"></a><a class="code" href="dwc__otg__regs_8h.html#db9e36d1ab76c334f6e004ee270bd36f">01762</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_HPRT0_PRTSPD_LOW_SPEED      2</span>
+<a name="l01763"></a><a class="code" href="unionhprt0__data.html#cfabc8a060c6d404c883186ec6bc9508">01763</a> <span class="preprocessor"></span>                <span class="keywordtype">unsigned</span> <a class="code" href="unionhprt0__data.html#cfabc8a060c6d404c883186ec6bc9508">reserved19_31</a>:13;
+<a name="l01764"></a>01764         } <a class="code" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a>;
+<a name="l01765"></a>01765 } <a class="code" href="unionhprt0__data.html">hprt0_data_t</a>;
+<a name="l01766"></a>01766 
+<a name="l01771"></a><a class="code" href="unionhaint__data.html">01771</a> <span class="keyword">typedef</span> <span class="keyword">union </span><a class="code" href="unionhaint__data.html">haint_data</a> {
+<a name="l01773"></a><a class="code" href="unionhaint__data.html#c83834650d2981b44274a89dda63a0f5">01773</a>         uint32_t <a class="code" href="unionhaint__data.html#c83834650d2981b44274a89dda63a0f5">d32</a>;
+<a name="l01775"></a>01775         <span class="keyword">struct </span>{
+<a name="l01776"></a><a class="code" href="unionhaint__data.html#4518de0451164b403fd446119606c798">01776</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhaint__data.html#4518de0451164b403fd446119606c798">ch0</a>:1;
+<a name="l01777"></a><a class="code" href="unionhaint__data.html#111c951f2c033e42b8d341f968ccc387">01777</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhaint__data.html#111c951f2c033e42b8d341f968ccc387">ch1</a>:1;
+<a name="l01778"></a><a class="code" href="unionhaint__data.html#4f22391988e52ce0cf4c26114352d491">01778</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhaint__data.html#4f22391988e52ce0cf4c26114352d491">ch2</a>:1;
+<a name="l01779"></a><a class="code" href="unionhaint__data.html#595c465c0d89f2fc5b213436243f3301">01779</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhaint__data.html#595c465c0d89f2fc5b213436243f3301">ch3</a>:1;
+<a name="l01780"></a><a class="code" href="unionhaint__data.html#daec53008bfef01a4eae6a287476be28">01780</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhaint__data.html#daec53008bfef01a4eae6a287476be28">ch4</a>:1;
+<a name="l01781"></a><a class="code" href="unionhaint__data.html#236e813b0d2c40105d98eabaaa83668a">01781</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhaint__data.html#236e813b0d2c40105d98eabaaa83668a">ch5</a>:1;
+<a name="l01782"></a><a class="code" href="unionhaint__data.html#4b32ecbff1ca92fb9a6ed7c85163b068">01782</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhaint__data.html#4b32ecbff1ca92fb9a6ed7c85163b068">ch6</a>:1;
+<a name="l01783"></a><a class="code" href="unionhaint__data.html#858da0223b1c8c714704083fc3bb8716">01783</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhaint__data.html#858da0223b1c8c714704083fc3bb8716">ch7</a>:1;
+<a name="l01784"></a><a class="code" href="unionhaint__data.html#a2b5aa5c0ad6f2ddd237f2fc4d5772f5">01784</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhaint__data.html#a2b5aa5c0ad6f2ddd237f2fc4d5772f5">ch8</a>:1;
+<a name="l01785"></a><a class="code" href="unionhaint__data.html#991c29e3cf0a85ef17178df828fd1474">01785</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhaint__data.html#991c29e3cf0a85ef17178df828fd1474">ch9</a>:1;
+<a name="l01786"></a><a class="code" href="unionhaint__data.html#07c1c428e4e756aa65338659fc2f20d1">01786</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhaint__data.html#07c1c428e4e756aa65338659fc2f20d1">ch10</a>:1;
+<a name="l01787"></a><a class="code" href="unionhaint__data.html#5234dd8c3b0aa7d46154aa89f6fe2635">01787</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhaint__data.html#5234dd8c3b0aa7d46154aa89f6fe2635">ch11</a>:1;
+<a name="l01788"></a><a class="code" href="unionhaint__data.html#43ab83f803054d0a5557471380186f8f">01788</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhaint__data.html#43ab83f803054d0a5557471380186f8f">ch12</a>:1;
+<a name="l01789"></a><a class="code" href="unionhaint__data.html#7764f0ba6f46901a0c800dcc8c158643">01789</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhaint__data.html#7764f0ba6f46901a0c800dcc8c158643">ch13</a>:1;
+<a name="l01790"></a><a class="code" href="unionhaint__data.html#46a15c2faf17d049b71fcd46d1a58842">01790</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhaint__data.html#46a15c2faf17d049b71fcd46d1a58842">ch14</a>:1;
+<a name="l01791"></a><a class="code" href="unionhaint__data.html#58435a2988a1d8a2dd11c64b8246bfcf">01791</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhaint__data.html#58435a2988a1d8a2dd11c64b8246bfcf">ch15</a>:1;
+<a name="l01792"></a><a class="code" href="unionhaint__data.html#08adf6a68f6ae5051eb461477afbe2cf">01792</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhaint__data.html#08adf6a68f6ae5051eb461477afbe2cf">reserved</a>:16;
+<a name="l01793"></a>01793         } <a class="code" href="unionhaint__data.html#4ca1bd2581863c172fe667b226cfa2aa">b</a>;
+<a name="l01794"></a>01794 
+<a name="l01795"></a>01795         <span class="keyword">struct </span>{
+<a name="l01796"></a><a class="code" href="unionhaint__data.html#6824b5b98c861cbc8efe3ba9f70cfea0">01796</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhaint__data.html#6824b5b98c861cbc8efe3ba9f70cfea0">chint</a>:16;
+<a name="l01797"></a>01797                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhaint__data.html#08adf6a68f6ae5051eb461477afbe2cf">reserved</a>:16;
+<a name="l01798"></a>01798         } b2;
+<a name="l01799"></a>01799 } <a class="code" href="unionhaint__data.html">haint_data_t</a>;
+<a name="l01800"></a>01800 
+<a name="l01805"></a><a class="code" href="unionhaintmsk__data.html">01805</a> <span class="keyword">typedef</span> <span class="keyword">union </span><a class="code" href="unionhaintmsk__data.html">haintmsk_data</a> {
+<a name="l01807"></a><a class="code" href="unionhaintmsk__data.html#65f3e5dbc7a62b6fb57426abaaffc6a2">01807</a>         uint32_t <a class="code" href="unionhaintmsk__data.html#65f3e5dbc7a62b6fb57426abaaffc6a2">d32</a>;
+<a name="l01809"></a>01809         <span class="keyword">struct </span>{
+<a name="l01810"></a><a class="code" href="unionhaintmsk__data.html#dd096952e3d38ffa5db796e3a7334e7b">01810</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhaintmsk__data.html#dd096952e3d38ffa5db796e3a7334e7b">ch0</a>:1;
+<a name="l01811"></a><a class="code" href="unionhaintmsk__data.html#c79960e27bba0c730936148272b14d3b">01811</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhaintmsk__data.html#c79960e27bba0c730936148272b14d3b">ch1</a>:1;
+<a name="l01812"></a><a class="code" href="unionhaintmsk__data.html#0ecac53d912d941c9139af6591f93261">01812</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhaintmsk__data.html#0ecac53d912d941c9139af6591f93261">ch2</a>:1;
+<a name="l01813"></a><a class="code" href="unionhaintmsk__data.html#40feb12ac2af27dfb5772dcaec2c17c2">01813</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhaintmsk__data.html#40feb12ac2af27dfb5772dcaec2c17c2">ch3</a>:1;
+<a name="l01814"></a><a class="code" href="unionhaintmsk__data.html#5692699f367a57de45bab48856a35624">01814</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhaintmsk__data.html#5692699f367a57de45bab48856a35624">ch4</a>:1;
+<a name="l01815"></a><a class="code" href="unionhaintmsk__data.html#e49e1e6e4bea7ee8375c7e9da57d0217">01815</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhaintmsk__data.html#e49e1e6e4bea7ee8375c7e9da57d0217">ch5</a>:1;
+<a name="l01816"></a><a class="code" href="unionhaintmsk__data.html#df9d27f0be312e3c56cbd20736cb8e07">01816</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhaintmsk__data.html#df9d27f0be312e3c56cbd20736cb8e07">ch6</a>:1;
+<a name="l01817"></a><a class="code" href="unionhaintmsk__data.html#df61ec0f4ee97164b1a1aa1d8d0bd4b8">01817</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhaintmsk__data.html#df61ec0f4ee97164b1a1aa1d8d0bd4b8">ch7</a>:1;
+<a name="l01818"></a><a class="code" href="unionhaintmsk__data.html#1c05566d9af4c7401cc95ed613b62252">01818</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhaintmsk__data.html#1c05566d9af4c7401cc95ed613b62252">ch8</a>:1;
+<a name="l01819"></a><a class="code" href="unionhaintmsk__data.html#f12b0a59f2e663d15e9f69866c5bf701">01819</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhaintmsk__data.html#f12b0a59f2e663d15e9f69866c5bf701">ch9</a>:1;
+<a name="l01820"></a><a class="code" href="unionhaintmsk__data.html#e815617fd288b134798fa5e2dd23af67">01820</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhaintmsk__data.html#e815617fd288b134798fa5e2dd23af67">ch10</a>:1;
+<a name="l01821"></a><a class="code" href="unionhaintmsk__data.html#51e0430615e457c51a8f12f3c8c6246b">01821</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhaintmsk__data.html#51e0430615e457c51a8f12f3c8c6246b">ch11</a>:1;
+<a name="l01822"></a><a class="code" href="unionhaintmsk__data.html#a7e151fe0676bde7a2ac43ee5b6f1b73">01822</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhaintmsk__data.html#a7e151fe0676bde7a2ac43ee5b6f1b73">ch12</a>:1;
+<a name="l01823"></a><a class="code" href="unionhaintmsk__data.html#3ad05d0ef4e63250fc7b3af9f1654271">01823</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhaintmsk__data.html#3ad05d0ef4e63250fc7b3af9f1654271">ch13</a>:1;
+<a name="l01824"></a><a class="code" href="unionhaintmsk__data.html#3f0cf3851a6f6b74c33a71a3b255372b">01824</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhaintmsk__data.html#3f0cf3851a6f6b74c33a71a3b255372b">ch14</a>:1;
+<a name="l01825"></a><a class="code" href="unionhaintmsk__data.html#da69c5905fb9a16f50f9a0a8c0c9b125">01825</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhaintmsk__data.html#da69c5905fb9a16f50f9a0a8c0c9b125">ch15</a>:1;
+<a name="l01826"></a><a class="code" href="unionhaintmsk__data.html#b538c489375d2ca28e852a1b0366a532">01826</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhaintmsk__data.html#b538c489375d2ca28e852a1b0366a532">reserved</a>:16;
+<a name="l01827"></a>01827         } <a class="code" href="unionhaintmsk__data.html#03f75072e5548a4addea100a40e0ac89">b</a>;
+<a name="l01828"></a>01828 
+<a name="l01829"></a>01829         <span class="keyword">struct </span>{
+<a name="l01830"></a><a class="code" href="unionhaintmsk__data.html#80030e17495460223602afd3aad1287c">01830</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhaintmsk__data.html#80030e17495460223602afd3aad1287c">chint</a>:16;
+<a name="l01831"></a>01831                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhaintmsk__data.html#b538c489375d2ca28e852a1b0366a532">reserved</a>:16;
+<a name="l01832"></a>01832         } b2;
+<a name="l01833"></a>01833 } <a class="code" href="unionhaintmsk__data.html">haintmsk_data_t</a>;
+<a name="l01834"></a>01834 
+<a name="l01838"></a><a class="code" href="structdwc__otg__hc__regs.html">01838</a> <span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs</a> 
+<a name="l01839"></a>01839 {
+<a name="l01841"></a><a class="code" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">01841</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">hcchar</a>;
+<a name="l01843"></a><a class="code" href="structdwc__otg__hc__regs.html#149053001a9ee21b692afde531a814de">01843</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__hc__regs.html#149053001a9ee21b692afde531a814de">hcsplt</a>;
+<a name="l01845"></a><a class="code" href="structdwc__otg__hc__regs.html#0dfd5bae537d58e13788508dc719480d">01845</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__hc__regs.html#0dfd5bae537d58e13788508dc719480d">hcint</a>;
+<a name="l01847"></a><a class="code" href="structdwc__otg__hc__regs.html#830aa61c1d4326823662168ea7359205">01847</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__hc__regs.html#830aa61c1d4326823662168ea7359205">hcintmsk</a>;
+<a name="l01849"></a><a class="code" href="structdwc__otg__hc__regs.html#c6173f823ba754d9f9549422b6380ca2">01849</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__hc__regs.html#c6173f823ba754d9f9549422b6380ca2">hctsiz</a>;
+<a name="l01851"></a><a class="code" href="structdwc__otg__hc__regs.html#ab2148d4b5f1bf3a2ad438e497a8b4a3">01851</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__hc__regs.html#ab2148d4b5f1bf3a2ad438e497a8b4a3">hcdma</a>;
+<a name="l01852"></a><a class="code" href="structdwc__otg__hc__regs.html#a0a3f7d7424594783afc83c7e8b22a69">01852</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__hc__regs.html#a0a3f7d7424594783afc83c7e8b22a69">reserved</a>;
+<a name="l01854"></a><a class="code" href="structdwc__otg__hc__regs.html#602f4c6eceb8e9d4fa61f35d4149f355">01854</a>         <span class="keyword">volatile</span> uint32_t <a class="code" href="structdwc__otg__hc__regs.html#602f4c6eceb8e9d4fa61f35d4149f355">hcdmab</a>;
+<a name="l01855"></a>01855 } <a class="code" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a>;
+<a name="l01856"></a>01856 
+<a name="l01863"></a><a class="code" href="unionhcchar__data.html">01863</a> <span class="keyword">typedef</span> <span class="keyword">union </span><a class="code" href="unionhcchar__data.html">hcchar_data</a> {
+<a name="l01865"></a><a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">01865</a>         uint32_t <a class="code" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a>;
+<a name="l01866"></a>01866 
+<a name="l01868"></a>01868         <span class="keyword">struct </span>{
+<a name="l01870"></a><a class="code" href="unionhcchar__data.html#47d11a5e62f69534d8ac0606aa7ffe7d">01870</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcchar__data.html#47d11a5e62f69534d8ac0606aa7ffe7d">mps</a>:11;
+<a name="l01871"></a>01871 
+<a name="l01873"></a><a class="code" href="unionhcchar__data.html#1597f36b85006e643aaf6f4d503bebc9">01873</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcchar__data.html#1597f36b85006e643aaf6f4d503bebc9">epnum</a>:4;
+<a name="l01874"></a>01874 
+<a name="l01876"></a><a class="code" href="unionhcchar__data.html#11f1b16e50f90806f90953bb979d4e77">01876</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcchar__data.html#11f1b16e50f90806f90953bb979d4e77">epdir</a>:1;
+<a name="l01877"></a>01877 
+<a name="l01878"></a><a class="code" href="unionhcchar__data.html#40e9041243226810913a7f227fd84c9a">01878</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcchar__data.html#40e9041243226810913a7f227fd84c9a">reserved</a>:1;
+<a name="l01879"></a>01879 
+<a name="l01881"></a><a class="code" href="unionhcchar__data.html#ca469c8bda88761c4d9ef74b811d71f4">01881</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcchar__data.html#ca469c8bda88761c4d9ef74b811d71f4">lspddev</a>:1;
+<a name="l01882"></a>01882 
+<a name="l01884"></a><a class="code" href="unionhcchar__data.html#df4deee52d932ab29e5d077cde77cbfc">01884</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcchar__data.html#df4deee52d932ab29e5d077cde77cbfc">eptype</a>:2;
+<a name="l01885"></a>01885 
+<a name="l01887"></a><a class="code" href="unionhcchar__data.html#9c0f515663251779e4960ec5613ce6fe">01887</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcchar__data.html#9c0f515663251779e4960ec5613ce6fe">multicnt</a>:2;
+<a name="l01888"></a>01888 
+<a name="l01890"></a><a class="code" href="unionhcchar__data.html#19326a679cb3507cf294d229834252a1">01890</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcchar__data.html#19326a679cb3507cf294d229834252a1">devaddr</a>:7;
+<a name="l01891"></a>01891 
+<a name="l01896"></a><a class="code" href="unionhcchar__data.html#1eae01428cc22feed785eedff05c86da">01896</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcchar__data.html#1eae01428cc22feed785eedff05c86da">oddfrm</a>:1;
+<a name="l01897"></a>01897 
+<a name="l01899"></a><a class="code" href="unionhcchar__data.html#73c9f7f3cc4036c72ef341d1d1d9c388">01899</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcchar__data.html#73c9f7f3cc4036c72ef341d1d1d9c388">chdis</a>:1;
+<a name="l01900"></a>01900 
+<a name="l01902"></a><a class="code" href="unionhcchar__data.html#994a5305780edb0c4fe159b6cc7b14ae">01902</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcchar__data.html#994a5305780edb0c4fe159b6cc7b14ae">chen</a>:1;
+<a name="l01903"></a>01903         } <a class="code" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a>;
+<a name="l01904"></a>01904 } <a class="code" href="unionhcchar__data.html">hcchar_data_t</a>;
+<a name="l01905"></a>01905 
+<a name="l01906"></a><a class="code" href="unionhcsplt__data.html">01906</a> <span class="keyword">typedef</span> <span class="keyword">union </span><a class="code" href="unionhcsplt__data.html">hcsplt_data</a> {
+<a name="l01908"></a><a class="code" href="unionhcsplt__data.html#0cd235b445ff681b846f5dccf24fd644">01908</a>         uint32_t <a class="code" href="unionhcsplt__data.html#0cd235b445ff681b846f5dccf24fd644">d32</a>;
+<a name="l01909"></a>01909 
+<a name="l01911"></a>01911         <span class="keyword">struct </span>{
+<a name="l01913"></a><a class="code" href="unionhcsplt__data.html#e1c0812d6f655ea9915a6152c9f16cd6">01913</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcsplt__data.html#e1c0812d6f655ea9915a6152c9f16cd6">prtaddr</a>:7;
+<a name="l01914"></a>01914 
+<a name="l01916"></a><a class="code" href="unionhcsplt__data.html#2843e0a36458a9a4c2d5ed6da3027b36">01916</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcsplt__data.html#2843e0a36458a9a4c2d5ed6da3027b36">hubaddr</a>:7;
+<a name="l01917"></a>01917 
+<a name="l01919"></a><a class="code" href="unionhcsplt__data.html#68e7b96ce2ca96c96f40b4f95c679a11">01919</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcsplt__data.html#68e7b96ce2ca96c96f40b4f95c679a11">xactpos</a>:2;
+<a name="l01920"></a><a class="code" href="dwc__otg__regs_8h.html#2297a1a33f502bc705e5c450c9864c6c">01920</a> <span class="preprocessor">#define DWC_HCSPLIT_XACTPOS_MID 0</span>
+<a name="l01921"></a><a class="code" href="dwc__otg__regs_8h.html#fc237b3dd77c97276aa4bd50947117e2">01921</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_HCSPLIT_XACTPOS_END 1</span>
+<a name="l01922"></a><a class="code" href="dwc__otg__regs_8h.html#c0b856e1a71e0373153d986a3cb5b135">01922</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_HCSPLIT_XACTPOS_BEGIN 2</span>
+<a name="l01923"></a><a class="code" href="dwc__otg__regs_8h.html#b8a8f35d8fd73c955cc0403e87cea0c6">01923</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_HCSPLIT_XACTPOS_ALL 3</span>
+<a name="l01924"></a>01924 <span class="preprocessor"></span>
+<a name="l01926"></a><a class="code" href="unionhcsplt__data.html#0a4855eb44ec93ec47dcc218a8703e94">01926</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcsplt__data.html#0a4855eb44ec93ec47dcc218a8703e94">compsplt</a>:1;
+<a name="l01927"></a>01927 
+<a name="l01929"></a><a class="code" href="unionhcsplt__data.html#28e272ea89e4f9e7c2db05fb92927e74">01929</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcsplt__data.html#28e272ea89e4f9e7c2db05fb92927e74">reserved</a>:14;
+<a name="l01930"></a>01930 
+<a name="l01932"></a><a class="code" href="unionhcsplt__data.html#8b174930345ac0e5a8a6bd16794836d7">01932</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcsplt__data.html#8b174930345ac0e5a8a6bd16794836d7">spltena</a>:1;
+<a name="l01933"></a>01933         } <a class="code" href="unionhcsplt__data.html#b8bafe40eee4a9f598659d254be836e1">b</a>;
+<a name="l01934"></a>01934 } <a class="code" href="unionhcsplt__data.html">hcsplt_data_t</a>;
+<a name="l01935"></a>01935 
+<a name="l01940"></a><a class="code" href="unionhcint__data.html">01940</a> <span class="keyword">typedef</span> <span class="keyword">union </span><a class="code" href="unionhcint__data.html">hcint_data</a>
+<a name="l01941"></a>01941 {
+<a name="l01943"></a><a class="code" href="unionhcint__data.html#05a82fa7693f875622db744716d7f73e">01943</a>         uint32_t <a class="code" href="unionhcint__data.html#05a82fa7693f875622db744716d7f73e">d32</a>;
+<a name="l01945"></a>01945         <span class="keyword">struct </span>
+<a name="l01946"></a>01946 <span class="keyword">        </span>{
+<a name="l01948"></a><a class="code" href="unionhcint__data.html#49385cb90c4d8c003cfac91175a646e0">01948</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcint__data.html#49385cb90c4d8c003cfac91175a646e0">xfercomp</a>:1;
+<a name="l01950"></a><a class="code" href="unionhcint__data.html#b93ceab913a49e33c5bf4dde0e62d75a">01950</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcint__data.html#b93ceab913a49e33c5bf4dde0e62d75a">chhltd</a>:1;
+<a name="l01952"></a><a class="code" href="unionhcint__data.html#f953465ff02c518a52c48d4d6b1c09c7">01952</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcint__data.html#f953465ff02c518a52c48d4d6b1c09c7">ahberr</a>:1;
+<a name="l01954"></a><a class="code" href="unionhcint__data.html#cf2fb413e5758e9ebd8914b2f7605d73">01954</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcint__data.html#cf2fb413e5758e9ebd8914b2f7605d73">stall</a>:1;
+<a name="l01956"></a><a class="code" href="unionhcint__data.html#ce65c9d3f0c7d3e5b8f163a378051c6c">01956</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcint__data.html#ce65c9d3f0c7d3e5b8f163a378051c6c">nak</a>:1;
+<a name="l01958"></a><a class="code" href="unionhcint__data.html#729749d6d0b5a1d4c449287f9efdd5fe">01958</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcint__data.html#729749d6d0b5a1d4c449287f9efdd5fe">ack</a>:1;
+<a name="l01960"></a><a class="code" href="unionhcint__data.html#755e54c3dfded3653447dfdd63fd8b6a">01960</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcint__data.html#755e54c3dfded3653447dfdd63fd8b6a">nyet</a>:1;
+<a name="l01962"></a><a class="code" href="unionhcint__data.html#86ec2d311ef29228676781f9100d195a">01962</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcint__data.html#86ec2d311ef29228676781f9100d195a">xacterr</a>:1;
+<a name="l01964"></a><a class="code" href="unionhcint__data.html#b05adf33c7be609a2daf54478f884ec4">01964</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcint__data.html#b05adf33c7be609a2daf54478f884ec4">bblerr</a>:1;
+<a name="l01966"></a><a class="code" href="unionhcint__data.html#06f911d323d71f86639550507322dffb">01966</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcint__data.html#06f911d323d71f86639550507322dffb">frmovrun</a>:1;
+<a name="l01968"></a><a class="code" href="unionhcint__data.html#2fc8618d16e6908e99c8cca3ffb54736">01968</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcint__data.html#2fc8618d16e6908e99c8cca3ffb54736">datatglerr</a>:1;
+<a name="l01970"></a><a class="code" href="unionhcint__data.html#759d3d0d98bd7efe69d46cc975b81845">01970</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcint__data.html#759d3d0d98bd7efe69d46cc975b81845">bna</a> : 1;
+<a name="l01972"></a><a class="code" href="unionhcint__data.html#f13613b1a33edddb676d2bce8a35e447">01972</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcint__data.html#f13613b1a33edddb676d2bce8a35e447">xcs_xact</a> : 1;
+<a name="l01974"></a><a class="code" href="unionhcint__data.html#26f48c3ec302ac2e009be71733e068b7">01974</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcint__data.html#26f48c3ec302ac2e009be71733e068b7">frm_list_roll</a> : 1;
+<a name="l01976"></a><a class="code" href="unionhcint__data.html#1b7dcab0dbc45803be45b4d0b99eac49">01976</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcint__data.html#1b7dcab0dbc45803be45b4d0b99eac49">reserved14_31</a> : 18;
+<a name="l01977"></a>01977         } <a class="code" href="unionhcint__data.html#3ab6af507f45d91a7898dd711f4368ee">b</a>;
+<a name="l01978"></a>01978 } <a class="code" href="unionhcint__data.html">hcint_data_t</a>;
+<a name="l01979"></a>01979 
+<a name="l01986"></a><a class="code" href="unionhcintmsk__data.html">01986</a> <span class="keyword">typedef</span> <span class="keyword">union </span><a class="code" href="unionhcintmsk__data.html">hcintmsk_data</a>
+<a name="l01987"></a>01987 {
+<a name="l01989"></a><a class="code" href="unionhcintmsk__data.html#8868299fcc762e005b7f0bf67e5fbe30">01989</a>         uint32_t <a class="code" href="unionhcintmsk__data.html#8868299fcc762e005b7f0bf67e5fbe30">d32</a>;
+<a name="l01990"></a>01990 
+<a name="l01992"></a>01992         <span class="keyword">struct </span>
+<a name="l01993"></a>01993 <span class="keyword">        </span>{
+<a name="l01994"></a><a class="code" href="unionhcintmsk__data.html#4983a78156d96d9a0c16ca8ea2b09106">01994</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcintmsk__data.html#4983a78156d96d9a0c16ca8ea2b09106">xfercompl</a> : 1;
+<a name="l01995"></a><a class="code" href="unionhcintmsk__data.html#2549a84a06f4f6a7ad6fed50fcf7b068">01995</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcintmsk__data.html#2549a84a06f4f6a7ad6fed50fcf7b068">chhltd</a> : 1;
+<a name="l01996"></a><a class="code" href="unionhcintmsk__data.html#bd9e228b6cb8e60cdbefd4bb57bdcc33">01996</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcintmsk__data.html#bd9e228b6cb8e60cdbefd4bb57bdcc33">ahberr</a> : 1;
+<a name="l01997"></a><a class="code" href="unionhcintmsk__data.html#94dc82e231d28d16d21238809cb88f78">01997</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcintmsk__data.html#94dc82e231d28d16d21238809cb88f78">stall</a> : 1;
+<a name="l01998"></a><a class="code" href="unionhcintmsk__data.html#32ae7d92d0eb93ced42ac3773ddc3a2f">01998</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcintmsk__data.html#32ae7d92d0eb93ced42ac3773ddc3a2f">nak</a> : 1;
+<a name="l01999"></a><a class="code" href="unionhcintmsk__data.html#8d3388818a6dc098a1e1c64147d1ced9">01999</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcintmsk__data.html#8d3388818a6dc098a1e1c64147d1ced9">ack</a> : 1;
+<a name="l02000"></a><a class="code" href="unionhcintmsk__data.html#4274f9b730db0e390e5f3be4247ee45c">02000</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcintmsk__data.html#4274f9b730db0e390e5f3be4247ee45c">nyet</a> : 1;
+<a name="l02001"></a><a class="code" href="unionhcintmsk__data.html#29686b2c0b9502932327915d690a45d5">02001</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcintmsk__data.html#29686b2c0b9502932327915d690a45d5">xacterr</a> : 1;
+<a name="l02002"></a><a class="code" href="unionhcintmsk__data.html#5052c8737755083ee10105f36e839590">02002</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcintmsk__data.html#5052c8737755083ee10105f36e839590">bblerr</a> : 1;
+<a name="l02003"></a><a class="code" href="unionhcintmsk__data.html#2ba9f8dc5e946b28ac4169f75364e182">02003</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcintmsk__data.html#2ba9f8dc5e946b28ac4169f75364e182">frmovrun</a> : 1;
+<a name="l02004"></a><a class="code" href="unionhcintmsk__data.html#60bbf3878314aad41055137e348cc01d">02004</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcintmsk__data.html#60bbf3878314aad41055137e348cc01d">datatglerr</a> : 1;
+<a name="l02005"></a><a class="code" href="unionhcintmsk__data.html#dfbcaada980b7132f06667e0536b17da">02005</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcintmsk__data.html#dfbcaada980b7132f06667e0536b17da">bna</a> : 1;
+<a name="l02006"></a><a class="code" href="unionhcintmsk__data.html#ace04f1b0f78826b8d33b828d4e637c2">02006</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcintmsk__data.html#ace04f1b0f78826b8d33b828d4e637c2">xcs_xact</a> : 1;
+<a name="l02007"></a><a class="code" href="unionhcintmsk__data.html#da781977131daa2db51fee16900366ae">02007</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcintmsk__data.html#da781977131daa2db51fee16900366ae">frm_list_roll</a> : 1;
+<a name="l02008"></a><a class="code" href="unionhcintmsk__data.html#dcb3b9df0efa5f60db95dd09a7e4a083">02008</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcintmsk__data.html#dcb3b9df0efa5f60db95dd09a7e4a083">reserved14_31</a> : 18;
+<a name="l02009"></a>02009         } <a class="code" href="unionhcintmsk__data.html#6835f55069c94947b580c8f01f64a075">b</a>;
+<a name="l02010"></a>02010 } <a class="code" href="unionhcintmsk__data.html">hcintmsk_data_t</a>;
+<a name="l02011"></a>02011 
+<a name="l02019"></a><a class="code" href="unionhctsiz__data.html">02019</a> <span class="keyword">typedef</span> <span class="keyword">union </span><a class="code" href="unionhctsiz__data.html">hctsiz_data</a>
+<a name="l02020"></a>02020 {
+<a name="l02022"></a><a class="code" href="unionhctsiz__data.html#fb41950555c60c6015294bdefe9cd39d">02022</a>         uint32_t <a class="code" href="unionhctsiz__data.html#fb41950555c60c6015294bdefe9cd39d">d32</a>;
+<a name="l02023"></a>02023 
+<a name="l02025"></a>02025         <span class="keyword">struct </span>
+<a name="l02026"></a>02026 <span class="keyword">        </span>{
+<a name="l02028"></a><a class="code" href="unionhctsiz__data.html#6ad01d874d77aa4382f71fa68eaec12d">02028</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhctsiz__data.html#6ad01d874d77aa4382f71fa68eaec12d">xfersize</a>:19;
+<a name="l02029"></a>02029 
+<a name="l02031"></a><a class="code" href="unionhctsiz__data.html#3ea18df5a98d33a6f8fa786252a0205b">02031</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhctsiz__data.html#3ea18df5a98d33a6f8fa786252a0205b">pktcnt</a>:10;
+<a name="l02032"></a>02032 
+<a name="l02040"></a><a class="code" href="unionhctsiz__data.html#d8b17af02c244e47ca0c38f933a6b3f0">02040</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhctsiz__data.html#d8b17af02c244e47ca0c38f933a6b3f0">pid</a>:2;
+<a name="l02041"></a><a class="code" href="dwc__otg__regs_8h.html#ab429f705d8fb6db88a206968e438217">02041</a> <span class="preprocessor">#define DWC_HCTSIZ_DATA0 0</span>
+<a name="l02042"></a><a class="code" href="dwc__otg__regs_8h.html#8d9f79dc6ec3535659b6420115c8da80">02042</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_HCTSIZ_DATA1 2</span>
+<a name="l02043"></a><a class="code" href="dwc__otg__regs_8h.html#674f7277e9e0a30b9f169ecceccf45e0">02043</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_HCTSIZ_DATA2 1</span>
+<a name="l02044"></a><a class="code" href="dwc__otg__regs_8h.html#55e76fff4514ef727b2a1f6eead7a4e5">02044</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_HCTSIZ_MDATA 3</span>
+<a name="l02045"></a><a class="code" href="dwc__otg__regs_8h.html#3ce73700b1bd235f124e2a08e516aa88">02045</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_HCTSIZ_SETUP 3</span>
+<a name="l02046"></a>02046 <span class="preprocessor"></span>
+<a name="l02048"></a><a class="code" href="unionhctsiz__data.html#68625ebdd11afc0a026f41c94aedc161">02048</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhctsiz__data.html#68625ebdd11afc0a026f41c94aedc161">dopng</a>:1;
+<a name="l02049"></a>02049         } <a class="code" href="unionhctsiz__data.html#8967fa90c651bce44a3cbe90c44cf638">b</a>;
+<a name="l02050"></a>02050         
+<a name="l02052"></a>02052         <span class="keyword">struct </span>
+<a name="l02053"></a>02053 <span class="keyword">        </span>{
+<a name="l02055"></a><a class="code" href="unionhctsiz__data.html#0d1f05f3b24da2caa3acc1c3864bc29b">02055</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhctsiz__data.html#0d1f05f3b24da2caa3acc1c3864bc29b">schinfo</a> : 8;
+<a name="l02056"></a>02056                 
+<a name="l02062"></a><a class="code" href="unionhctsiz__data.html#ac1addd68951e1a6a25312d49be9895d">02062</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhctsiz__data.html#ac1addd68951e1a6a25312d49be9895d">ntd</a> : 8;
+<a name="l02063"></a>02063 
+<a name="l02065"></a><a class="code" href="unionhctsiz__data.html#30027b4cc28a3dd7930e48635a00488d">02065</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhctsiz__data.html#30027b4cc28a3dd7930e48635a00488d">reserved16_28</a> : 13;
+<a name="l02066"></a>02066 
+<a name="l02074"></a>02074                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhctsiz__data.html#d8b17af02c244e47ca0c38f933a6b3f0">pid</a> : 2;
+<a name="l02075"></a>02075 
+<a name="l02077"></a>02077                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhctsiz__data.html#68625ebdd11afc0a026f41c94aedc161">dopng</a> : 1;
+<a name="l02078"></a>02078         } <a class="code" href="unionhctsiz__data.html#6cc80c630201f29e4a43e0cd7030786b">b_ddma</a>;
+<a name="l02079"></a>02079 } <a class="code" href="unionhctsiz__data.html">hctsiz_data_t</a>;
+<a name="l02080"></a>02080 
+<a name="l02081"></a>02081 
+<a name="l02086"></a><a class="code" href="unionhcdma__data.html">02086</a> <span class="keyword">typedef</span> <span class="keyword">union </span><a class="code" href="unionhcdma__data.html">hcdma_data</a>
+<a name="l02087"></a>02087 {
+<a name="l02089"></a><a class="code" href="unionhcdma__data.html#27b804015f09ea7eb25f602cc6dbdda9">02089</a>         uint32_t <a class="code" href="unionhcdma__data.html#27b804015f09ea7eb25f602cc6dbdda9">d32</a>;
+<a name="l02091"></a>02091         <span class="keyword">struct </span>
+<a name="l02092"></a>02092 <span class="keyword">        </span>{
+<a name="l02093"></a><a class="code" href="unionhcdma__data.html#3d9002e33b12ccde29856f08db7be7bf">02093</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcdma__data.html#3d9002e33b12ccde29856f08db7be7bf">reserved0_2</a> : 3;
+<a name="l02095"></a><a class="code" href="unionhcdma__data.html#d1238e3a2f81540362765b3e6a29d7de">02095</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcdma__data.html#d1238e3a2f81540362765b3e6a29d7de">ctd</a> : 8;
+<a name="l02097"></a><a class="code" href="unionhcdma__data.html#8324b2ba8d18c5ecb1cbcb23874393db">02097</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhcdma__data.html#8324b2ba8d18c5ecb1cbcb23874393db">dma_addr</a> : 21;
+<a name="l02098"></a>02098         } <a class="code" href="unionhcdma__data.html#61ea7b926fcef1d4fe1a6c8a1a1be41a">b</a>;
+<a name="l02099"></a>02099 } <a class="code" href="unionhcdma__data.html">hcdma_data_t</a>;
+<a name="l02100"></a>02100 
+<a name="l02106"></a><a class="code" href="unionhost__dma__desc__sts.html">02106</a> <span class="keyword">typedef</span> <span class="keyword">union </span><a class="code" href="unionhost__dma__desc__sts.html">host_dma_desc_sts</a>
+<a name="l02107"></a>02107 {
+<a name="l02109"></a><a class="code" href="unionhost__dma__desc__sts.html#c8e191345883c19b7127e54479c75e4d">02109</a>         uint32_t <a class="code" href="unionhost__dma__desc__sts.html#c8e191345883c19b7127e54479c75e4d">d32</a>;
+<a name="l02112"></a>02112         <span class="comment">/* for non-isochronous  */</span>
+<a name="l02113"></a>02113         <span class="keyword">struct </span>{
+<a name="l02115"></a><a class="code" href="unionhost__dma__desc__sts.html#a8f68a8a5c22c3c1b530400c23083892">02115</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhost__dma__desc__sts.html#a8f68a8a5c22c3c1b530400c23083892">n_bytes</a> : 17;
+<a name="l02117"></a><a class="code" href="unionhost__dma__desc__sts.html#80be234e5bac143beca335ffe226eef6">02117</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhost__dma__desc__sts.html#80be234e5bac143beca335ffe226eef6">qtd_offset</a> : 6;
+<a name="l02122"></a><a class="code" href="unionhost__dma__desc__sts.html#c6ec29eb4bc0c9e165b3d09b951b4d13">02122</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhost__dma__desc__sts.html#c6ec29eb4bc0c9e165b3d09b951b4d13">a_qtd</a> : 1;
+<a name="l02127"></a><a class="code" href="unionhost__dma__desc__sts.html#634060a1b436857e15e8eb8f0d6d000a">02127</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhost__dma__desc__sts.html#634060a1b436857e15e8eb8f0d6d000a">sup</a> : 1;
+<a name="l02129"></a><a class="code" href="unionhost__dma__desc__sts.html#2efbb549924afd0deb402af9eda4a272">02129</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhost__dma__desc__sts.html#2efbb549924afd0deb402af9eda4a272">ioc</a> : 1;
+<a name="l02131"></a><a class="code" href="unionhost__dma__desc__sts.html#58d670cd305219a32f144a6705e649e3">02131</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhost__dma__desc__sts.html#58d670cd305219a32f144a6705e649e3">eol</a> : 1;
+<a name="l02132"></a><a class="code" href="unionhost__dma__desc__sts.html#a9cdbf7ba860112e98594c98483cc513">02132</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhost__dma__desc__sts.html#a9cdbf7ba860112e98594c98483cc513">reserved27</a> : 1;
+<a name="l02134"></a><a class="code" href="unionhost__dma__desc__sts.html#828b019082523c4637758bef38805420">02134</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhost__dma__desc__sts.html#828b019082523c4637758bef38805420">sts</a> : 2;
+<a name="l02135"></a><a class="code" href="dwc__otg__regs_8h.html#175767634e612a1e3dff3207a787d402">02135</a> <span class="preprocessor">        #define DMA_DESC_STS_PKTERR     1</span>
+<a name="l02136"></a><a class="code" href="unionhost__dma__desc__sts.html#8bdb2544b6e88225d2fc082110ea04bb">02136</a> <span class="preprocessor"></span>                <span class="keywordtype">unsigned</span> <a class="code" href="unionhost__dma__desc__sts.html#8bdb2544b6e88225d2fc082110ea04bb">reserved30</a> : 1;
+<a name="l02138"></a><a class="code" href="unionhost__dma__desc__sts.html#1c4cf70718c94a1a847e52d4dd65cbb0">02138</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhost__dma__desc__sts.html#1c4cf70718c94a1a847e52d4dd65cbb0">a</a> : 1;
+<a name="l02139"></a>02139         } <a class="code" href="unionhost__dma__desc__sts.html#a0e53895b927bfa9e322c3a3c0a08b3b">b</a>;
+<a name="l02140"></a>02140         <span class="comment">/* for isochronous */</span>
+<a name="l02141"></a>02141         <span class="keyword">struct </span>{
+<a name="l02143"></a>02143                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhost__dma__desc__sts.html#a8f68a8a5c22c3c1b530400c23083892">n_bytes</a> : 12;
+<a name="l02144"></a><a class="code" href="unionhost__dma__desc__sts.html#6b8b65f5037dd388cc2427f602ba0f8e">02144</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhost__dma__desc__sts.html#6b8b65f5037dd388cc2427f602ba0f8e">reserved12_24</a> : 13;
+<a name="l02146"></a>02146                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhost__dma__desc__sts.html#2efbb549924afd0deb402af9eda4a272">ioc</a> : 1;
+<a name="l02147"></a><a class="code" href="unionhost__dma__desc__sts.html#834971c4ec03a85654c8630ced715c8c">02147</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhost__dma__desc__sts.html#834971c4ec03a85654c8630ced715c8c">reserved26_27</a> : 2;
+<a name="l02149"></a>02149                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhost__dma__desc__sts.html#828b019082523c4637758bef38805420">sts</a> : 2;
+<a name="l02150"></a>02150                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhost__dma__desc__sts.html#8bdb2544b6e88225d2fc082110ea04bb">reserved30</a> : 1;
+<a name="l02152"></a>02152                 <span class="keywordtype">unsigned</span> <a class="code" href="unionhost__dma__desc__sts.html#1c4cf70718c94a1a847e52d4dd65cbb0">a</a> : 1;
+<a name="l02153"></a>02153         } b_isoc;
+<a name="l02154"></a>02154 } <a class="code" href="unionhost__dma__desc__sts.html">host_dma_desc_sts_t</a>;
+<a name="l02155"></a>02155 
+<a name="l02156"></a><a class="code" href="dwc__otg__regs_8h.html#000f3273fb3033d587107e7eff3c1ff6">02156</a> <span class="preprocessor">#define MAX_DMA_DESC_SIZE               131071</span>
+<a name="l02157"></a><a class="code" href="dwc__otg__regs_8h.html#7f241a3ed7bd5c0d4f1a496c77cbc225">02157</a> <span class="preprocessor"></span><span class="preprocessor">#define MAX_DMA_DESC_NUM_GENERIC        64</span>
+<a name="l02158"></a><a class="code" href="dwc__otg__regs_8h.html#b190810b3017403bd58b6346aad4e4ed">02158</a> <span class="preprocessor"></span><span class="preprocessor">#define MAX_DMA_DESC_NUM_HS_ISOC        256</span>
+<a name="l02159"></a><a class="code" href="dwc__otg__regs_8h.html#ff2c2ac58a30e050d647d0f9a256d0bd">02159</a> <span class="preprocessor"></span><span class="preprocessor">#define MAX_FRLIST_EN_NUM               64</span>
+<a name="l02160"></a>02160 <span class="preprocessor"></span>
+<a name="l02166"></a><a class="code" href="structdwc__otg__host__dma__desc.html">02166</a> <span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code" href="structdwc__otg__host__dma__desc.html">dwc_otg_host_dma_desc</a>
+<a name="l02167"></a>02167 {
+<a name="l02169"></a><a class="code" href="structdwc__otg__host__dma__desc.html#1b73b25e9fca51dd00fa0607d57d9e3f">02169</a>         <a class="code" href="unionhost__dma__desc__sts.html">host_dma_desc_sts_t</a>     <a class="code" href="structdwc__otg__host__dma__desc.html#1b73b25e9fca51dd00fa0607d57d9e3f">status</a>;
+<a name="l02171"></a><a class="code" href="structdwc__otg__host__dma__desc.html#fdc395094e1a1f9bb89c316a96d4b96b">02171</a>         uint32_t        <a class="code" href="structdwc__otg__host__dma__desc.html#fdc395094e1a1f9bb89c316a96d4b96b">buf</a>;
+<a name="l02172"></a>02172 } <a class="code" href="structdwc__otg__host__dma__desc.html">dwc_otg_host_dma_desc_t</a>;
+<a name="l02173"></a>02173 
+<a name="l02181"></a><a class="code" href="structdwc__otg__host__if.html">02181</a> <span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code" href="structdwc__otg__host__if.html">dwc_otg_host_if</a> {
+<a name="l02183"></a><a class="code" href="structdwc__otg__host__if.html#ff9692c2e10ca2bc7e24f981f25179c2">02183</a>         <a class="code" href="structdwc__otg__host__global__regs.html">dwc_otg_host_global_regs_t</a> *<a class="code" href="structdwc__otg__host__if.html#ff9692c2e10ca2bc7e24f981f25179c2">host_global_regs</a>;
+<a name="l02184"></a><a class="code" href="dwc__otg__regs_8h.html#b9ef775c8628a8f225e36729cf1be0c3">02184</a> <span class="preprocessor">#define DWC_OTG_HOST_GLOBAL_REG_OFFSET 0x400</span>
+<a name="l02185"></a>02185 <span class="preprocessor"></span>
+<a name="l02187"></a><a class="code" href="structdwc__otg__host__if.html#dc8fe33e0bb3829cafa884d5fc603c4d">02187</a>         <span class="keyword">volatile</span> uint32_t *<a class="code" href="structdwc__otg__host__if.html#dc8fe33e0bb3829cafa884d5fc603c4d">hprt0</a>;
+<a name="l02188"></a><a class="code" href="dwc__otg__regs_8h.html#d34097dedb09e076ae91cef4ab3b4b2a">02188</a> <span class="preprocessor">#define DWC_OTG_HOST_PORT_REGS_OFFSET 0x440</span>
+<a name="l02189"></a>02189 <span class="preprocessor"></span>
+<a name="l02191"></a><a class="code" href="structdwc__otg__host__if.html#7f7c107d4720641eb4141cd817211ac0">02191</a>         <a class="code" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *<a class="code" href="structdwc__otg__host__if.html#7f7c107d4720641eb4141cd817211ac0">hc_regs</a>[<a class="code" href="dwc__otg__core__if_8h.html#bfb88b45545f7685f668ac2f545674ec">MAX_EPS_CHANNELS</a>];
+<a name="l02192"></a><a class="code" href="dwc__otg__regs_8h.html#76dd0c82028245c6a217ad7ee366cf15">02192</a> <span class="preprocessor">#define DWC_OTG_HOST_CHAN_REGS_OFFSET 0x500</span>
+<a name="l02193"></a><a class="code" href="dwc__otg__regs_8h.html#850bdd3d5997cdf22bf69fe0a0df6be1">02193</a> <span class="preprocessor"></span><span class="preprocessor">#define DWC_OTG_CHAN_REGS_OFFSET 0x20</span>
+<a name="l02194"></a>02194 <span class="preprocessor"></span>
+<a name="l02195"></a>02195         <span class="comment">/* Host configuration information */</span>
+<a name="l02197"></a><a class="code" href="structdwc__otg__host__if.html#a7b144c7f83d79fdafd7cd0c8c06102d">02197</a>         uint8_t <a class="code" href="structdwc__otg__host__if.html#a7b144c7f83d79fdafd7cd0c8c06102d">num_host_channels</a>;
+<a name="l02199"></a><a class="code" href="structdwc__otg__host__if.html#23dedb1efa17aa1c199f1e3c6e2a9784">02199</a>         uint8_t <a class="code" href="structdwc__otg__host__if.html#23dedb1efa17aa1c199f1e3c6e2a9784">perio_eps_supported</a>;
+<a name="l02201"></a><a class="code" href="structdwc__otg__host__if.html#b208538c559719cd680ea4828429735e">02201</a>         uint16_t <a class="code" href="structdwc__otg__host__if.html#b208538c559719cd680ea4828429735e">perio_tx_fifo_size</a>;
+<a name="l02202"></a>02202 
+<a name="l02203"></a>02203 } <a class="code" href="structdwc__otg__host__if.html">dwc_otg_host_if_t</a>;
+<a name="l02204"></a>02204 
+<a name="l02210"></a><a class="code" href="unionpcgcctl__data.html">02210</a> <span class="keyword">typedef</span> <span class="keyword">union </span><a class="code" href="unionpcgcctl__data.html">pcgcctl_data</a> {
+<a name="l02212"></a><a class="code" href="unionpcgcctl__data.html#abe048ee884143501929b27d94c52db7">02212</a>         uint32_t <a class="code" href="unionpcgcctl__data.html#abe048ee884143501929b27d94c52db7">d32</a>;
+<a name="l02213"></a>02213 
+<a name="l02215"></a>02215         <span class="keyword">struct </span>{
+<a name="l02217"></a><a class="code" href="unionpcgcctl__data.html#bf40184845ef70be8e59b2672cb0bedf">02217</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionpcgcctl__data.html#bf40184845ef70be8e59b2672cb0bedf">stoppclk</a>:1;
+<a name="l02219"></a><a class="code" href="unionpcgcctl__data.html#a3ee36c0e5ea8ae5ac38829337120327">02219</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionpcgcctl__data.html#a3ee36c0e5ea8ae5ac38829337120327">gatehclk</a>:1;
+<a name="l02221"></a><a class="code" href="unionpcgcctl__data.html#02d7dff0f26c3ac50ad4b876f1853c17">02221</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionpcgcctl__data.html#02d7dff0f26c3ac50ad4b876f1853c17">pwrclmp</a>:1;
+<a name="l02223"></a><a class="code" href="unionpcgcctl__data.html#9708a50a6e42cd2372d65555edf5cf28">02223</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionpcgcctl__data.html#9708a50a6e42cd2372d65555edf5cf28">rstpdwnmodule</a>:1;
+<a name="l02225"></a><a class="code" href="unionpcgcctl__data.html#c39017c4715319d740b749d16401f26c">02225</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionpcgcctl__data.html#c39017c4715319d740b749d16401f26c">physuspended</a>:1;
+<a name="l02227"></a><a class="code" href="unionpcgcctl__data.html#6c18ad3b71ad92e548d0c6d64cc88734">02227</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionpcgcctl__data.html#6c18ad3b71ad92e548d0c6d64cc88734">enbl_sleep_gating</a>:1;
+<a name="l02229"></a><a class="code" href="unionpcgcctl__data.html#f8b4b268a4fd5094a9a43ec503455f6f">02229</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionpcgcctl__data.html#f8b4b268a4fd5094a9a43ec503455f6f">phy_in_sleep</a>:1;
+<a name="l02231"></a><a class="code" href="unionpcgcctl__data.html#07232b66695a6bcba4c89477ef13130f">02231</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionpcgcctl__data.html#07232b66695a6bcba4c89477ef13130f">deep_sleep</a>:1;
+<a name="l02232"></a>02232 
+<a name="l02233"></a><a class="code" href="unionpcgcctl__data.html#dc73a75e42509238eed388c3a8a30207">02233</a>                 <span class="keywordtype">unsigned</span> <a class="code" href="unionpcgcctl__data.html#dc73a75e42509238eed388c3a8a30207">reserved31_8</a>:24;
+<a name="l02234"></a>02234         } <a class="code" href="unionpcgcctl__data.html#f2bb76709d0ab9d08280eafb78a36279">b</a>;
+<a name="l02235"></a>02235 } <a class="code" href="unionpcgcctl__data.html">pcgcctl_data_t</a>;
+<a name="l02236"></a>02236 
+<a name="l02237"></a>02237 <span class="preprocessor">#endif</span>
+</pre></div><hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/dwc__otg__regs_8h.html b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__regs_8h.html
new file mode 100644
index 000000000000..b441305330a8
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/dwc__otg__regs_8h.html
@@ -0,0 +1,1468 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_regs.h File Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
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+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<h1>dwc_otg_regs.h File Reference</h1>This file contains the data structures for accessing the DWC_otg core registers. <a href="#_details">More...</a>
+<p>
+<code>#include &quot;<a class="el" href="dwc__otg__core__if_8h-source.html">dwc_otg_core_if.h</a>&quot;</code><br>
+
+<p>
+<a href="dwc__otg__regs_8h-source.html">Go to the source code of this file.</a><table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Structures</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__global__regs.html">dwc_otg_core_global_regs</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">DWC_otg Core registers .  <a href="structdwc__otg__core__global__regs.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">union &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniongotgctl__data.html">gotgctl_data</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields of the Core OTG Control and Status Register (GOTGCTL).  <a href="uniongotgctl__data.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">union &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniongotgint__data.html">gotgint_data</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields of the Core OTG Interrupt Register (GOTGINT).  <a href="uniongotgint__data.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">union &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniongahbcfg__data.html">gahbcfg_data</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields of the Core AHB Configuration Register (GAHBCFG).  <a href="uniongahbcfg__data.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">union &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniongusbcfg__data.html">gusbcfg_data</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields of the Core USB Configuration Register (GUSBCFG).  <a href="uniongusbcfg__data.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">union &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionglpmctl__data.html">glpmctl_data</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields of the Core LPM Configuration Register (GLPMCFG).  <a href="unionglpmctl__data.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">union &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniongrstctl__data.html">grstctl_data</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields of the Core Reset Register (GRSTCTL).  <a href="uniongrstctl__data.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">union &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniongintmsk__data.html">gintmsk_data</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields of the Core Interrupt Mask Register (GINTMSK).  <a href="uniongintmsk__data.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">union &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniongintsts__data.html">gintsts_data</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields of the Core Interrupt Register (GINTSTS).  <a href="uniongintsts__data.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">union &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniondevice__grxsts__data.html">device_grxsts_data</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the Device Receive Status Read and Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <em>d32</em> element then read out the bits using the <em>b</em>it elements.  <a href="uniondevice__grxsts__data.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">union &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhost__grxsts__data.html">host_grxsts_data</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the Host Receive Status Read and Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <em>d32</em> element then read out the bits using the <em>b</em>it elements.  <a href="unionhost__grxsts__data.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">union &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionfifosize__data.html">fifosize_data</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ, GNPTXFSIZ, DPTXFSIZn, DIEPTXFn).  <a href="unionfifosize__data.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">union &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniongnptxsts__data.html">gnptxsts_data</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the Non-Periodic Transmit FIFO/Queue Status Register (GNPTXSTS).  <a href="uniongnptxsts__data.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">union &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniondtxfsts__data.html">dtxfsts_data</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the Transmit FIFO Status Register (DTXFSTS).  <a href="uniondtxfsts__data.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">union &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniongi2cctl__data.html">gi2cctl_data</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the I2C Control Register (I2CCTL).  <a href="uniongi2cctl__data.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">union &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhwcfg1__data.html">hwcfg1_data</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the User HW Config1 Register.  <a href="unionhwcfg1__data.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">union &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhwcfg2__data.html">hwcfg2_data</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the User HW Config2 Register.  <a href="unionhwcfg2__data.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">union &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhwcfg3__data.html">hwcfg3_data</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the User HW Config3 Register.  <a href="unionhwcfg3__data.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">union &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhwcfg4__data.html">hwcfg4_data</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the User HW Config4 Register.  <a href="unionhwcfg4__data.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__global__regs.html">dwc_otg_dev_global_regs</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Device Global Registers.  <a href="structdwc__otg__dev__global__regs.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">union &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniondcfg__data.html">dcfg_data</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the Device Configuration Register.  <a href="uniondcfg__data.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">union &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniondctl__data.html">dctl_data</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the Device Control Register.  <a href="uniondctl__data.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">union &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniondsts__data.html">dsts_data</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the Device Status Register.  <a href="uniondsts__data.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">union &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniondiepint__data.html">diepint_data</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the Device IN EP Interrupt Register and the Device IN EP Common Mask Register.  <a href="uniondiepint__data.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">union &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniondoepint__data.html">doepint_data</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the Device OUT EP Interrupt Registerand Device OUT EP Common Interrupt Mask Register.  <a href="uniondoepint__data.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">union &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniondaint__data.html">daint_data</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the Device All EP Interrupt and Mask Registers.  <a href="uniondaint__data.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">union &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniondtknq1__data.html">dtknq1_data</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the Device IN Token Queue Read Registers.  <a href="uniondtknq1__data.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">union &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniondthrctl__data.html">dthrctl_data</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents Threshold control Register<ul>
+<li>Read and write the register into the <em>d32</em> member. </li></ul>
+ <a href="uniondthrctl__data.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__in__ep__regs.html">dwc_otg_dev_in_ep_regs</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Device Logical IN Endpoint-Specific Registers.  <a href="structdwc__otg__dev__in__ep__regs.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__out__ep__regs.html">dwc_otg_dev_out_ep_regs</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Device Logical OUT Endpoint-Specific Registers.  <a href="structdwc__otg__dev__out__ep__regs.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">union &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniondepctl__data.html">depctl_data</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the Device EP Control Register.  <a href="uniondepctl__data.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">union &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniondeptsiz__data.html">deptsiz_data</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the Device EP Transfer Size Register.  <a href="uniondeptsiz__data.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">union &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniondeptsiz0__data.html">deptsiz0_data</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the Device EP 0 Transfer Size Register.  <a href="uniondeptsiz0__data.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">union &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniondev__dma__desc__sts.html">dev_dma_desc_sts</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the DMA Descriptor status quadlet.  <a href="uniondev__dma__desc__sts.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__dma__desc.html">dwc_otg_dev_dma_desc</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">DMA Descriptor structure.  <a href="structdwc__otg__dev__dma__desc.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__if.html">dwc_otg_dev_if</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">The <a class="el" href="structdwc__otg__dev__if.html">dwc_otg_dev_if</a> structure contains information needed to manage the DWC_otg controller acting in device mode.  <a href="structdwc__otg__dev__if.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__host__global__regs.html">dwc_otg_host_global_regs</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">The Host Global Registers structure defines the size and relative field offsets for the Host Mode Global Registers.  <a href="structdwc__otg__host__global__regs.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">union &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhcfg__data.html">hcfg_data</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the Host Configuration Register.  <a href="unionhcfg__data.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">union &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhfir__data.html">hfir_data</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the Host Frame Remaing/Number Register.  <a href="unionhfir__data.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">union &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhfnum__data.html">hfnum_data</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the Host Frame Remaing/Number Register.  <a href="unionhfnum__data.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">union &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhptxsts__data.html">hptxsts_data</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">union &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhprt0__data.html">hprt0_data</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the Host Port Control and Status Register.  <a href="unionhprt0__data.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">union &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhaint__data.html">haint_data</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the Host All Interrupt Register.  <a href="unionhaint__data.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">union &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhaintmsk__data.html">haintmsk_data</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the Host All Interrupt Register.  <a href="unionhaintmsk__data.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Host Channel Specific Registers.  <a href="structdwc__otg__hc__regs.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">union &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhcchar__data.html">hcchar_data</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the Host Channel Characteristics Register.  <a href="unionhcchar__data.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">union &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhcsplt__data.html">hcsplt_data</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">union &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhcint__data.html">hcint_data</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the Host All Interrupt Register.  <a href="unionhcint__data.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">union &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhcintmsk__data.html">hcintmsk_data</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the Host Channel Interrupt Mask Register.  <a href="unionhcintmsk__data.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">union &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhctsiz__data.html">hctsiz_data</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the Host Channel Transfer Size Register.  <a href="unionhctsiz__data.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">union &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhcdma__data.html">hcdma_data</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the Host DMA Address Register used in Descriptor DMA mode.  <a href="unionhcdma__data.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">union &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhost__dma__desc__sts.html">host_dma_desc_sts</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the DMA Descriptor status quadlet for host mode.  <a href="unionhost__dma__desc__sts.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__host__dma__desc.html">dwc_otg_host_dma_desc</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Host-mode DMA Descriptor structure.  <a href="structdwc__otg__host__dma__desc.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__host__if.html">dwc_otg_host_if</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">OTG Host Interface Structure.  <a href="structdwc__otg__host__if.html#_details">More...</a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">union &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionpcgcctl__data.html">pcgcctl_data</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the Power and Clock Gating Control Register.  <a href="unionpcgcctl__data.html#_details">More...</a><br></td></tr>
+<tr><td colspan="2"><br><h2>Defines</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="d9d4b173bf321ff42fce0e9deff98e14"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_GLBINTRMASK" ref="d9d4b173bf321ff42fce0e9deff98e14" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#d9d4b173bf321ff42fce0e9deff98e14">DWC_GLBINTRMASK</a>&nbsp;&nbsp;&nbsp;0x0001</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="560957ddd2a723670ef56420c4180254"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_DMAENABLE" ref="560957ddd2a723670ef56420c4180254" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#560957ddd2a723670ef56420c4180254">DWC_DMAENABLE</a>&nbsp;&nbsp;&nbsp;0x0020</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7022f94899c9292fb3bbde4467c8b8f0"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_NPTXEMPTYLVL_EMPTY" ref="7022f94899c9292fb3bbde4467c8b8f0" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#7022f94899c9292fb3bbde4467c8b8f0">DWC_NPTXEMPTYLVL_EMPTY</a>&nbsp;&nbsp;&nbsp;0x0080</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="079b5cc58466a4e15679e69256084554"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_NPTXEMPTYLVL_HALFEMPTY" ref="079b5cc58466a4e15679e69256084554" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#079b5cc58466a4e15679e69256084554">DWC_NPTXEMPTYLVL_HALFEMPTY</a>&nbsp;&nbsp;&nbsp;0x0000</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="cf27d55f3aae7ee1a3b542bd0440be38"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_PTXEMPTYLVL_EMPTY" ref="cf27d55f3aae7ee1a3b542bd0440be38" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#cf27d55f3aae7ee1a3b542bd0440be38">DWC_PTXEMPTYLVL_EMPTY</a>&nbsp;&nbsp;&nbsp;0x0100</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="33e16da6d4da8316b50fdeb3c05c5930"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_PTXEMPTYLVL_HALFEMPTY" ref="33e16da6d4da8316b50fdeb3c05c5930" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#33e16da6d4da8316b50fdeb3c05c5930">DWC_PTXEMPTYLVL_HALFEMPTY</a>&nbsp;&nbsp;&nbsp;0x0000</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b06d547ae50b58fd46847daa34578122"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_SLAVE_ONLY_ARCH" ref="b06d547ae50b58fd46847daa34578122" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#b06d547ae50b58fd46847daa34578122">DWC_SLAVE_ONLY_ARCH</a>&nbsp;&nbsp;&nbsp;0</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="bc493e89caf2ae15aa2b306099b8a927"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_EXT_DMA_ARCH" ref="bc493e89caf2ae15aa2b306099b8a927" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#bc493e89caf2ae15aa2b306099b8a927">DWC_EXT_DMA_ARCH</a>&nbsp;&nbsp;&nbsp;1</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f91a3e3ec200595566b8df5e40485fda"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_INT_DMA_ARCH" ref="f91a3e3ec200595566b8df5e40485fda" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#f91a3e3ec200595566b8df5e40485fda">DWC_INT_DMA_ARCH</a>&nbsp;&nbsp;&nbsp;2</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="8d3140b85bae33e2d7955693c61fd490"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_MODE_HNP_SRP_CAPABLE" ref="8d3140b85bae33e2d7955693c61fd490" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#8d3140b85bae33e2d7955693c61fd490">DWC_MODE_HNP_SRP_CAPABLE</a>&nbsp;&nbsp;&nbsp;0</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ecd675d5698ebf873bad50c6d2241296"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_MODE_SRP_ONLY_CAPABLE" ref="ecd675d5698ebf873bad50c6d2241296" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#ecd675d5698ebf873bad50c6d2241296">DWC_MODE_SRP_ONLY_CAPABLE</a>&nbsp;&nbsp;&nbsp;1</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="42740812c78415753c76ea58e2dd6a50"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_MODE_NO_HNP_SRP_CAPABLE" ref="42740812c78415753c76ea58e2dd6a50" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#42740812c78415753c76ea58e2dd6a50">DWC_MODE_NO_HNP_SRP_CAPABLE</a>&nbsp;&nbsp;&nbsp;2</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="0e5bc465c451f7ce8402ce94c355398e"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_MODE_SRP_CAPABLE_DEVICE" ref="0e5bc465c451f7ce8402ce94c355398e" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#0e5bc465c451f7ce8402ce94c355398e">DWC_MODE_SRP_CAPABLE_DEVICE</a>&nbsp;&nbsp;&nbsp;3</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="74152fd1bf534e043a53efd98a982bb6"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_MODE_NO_SRP_CAPABLE_DEVICE" ref="74152fd1bf534e043a53efd98a982bb6" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#74152fd1bf534e043a53efd98a982bb6">DWC_MODE_NO_SRP_CAPABLE_DEVICE</a>&nbsp;&nbsp;&nbsp;4</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="bbca30221d8415bad1c254e5cb240eaa"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_MODE_SRP_CAPABLE_HOST" ref="bbca30221d8415bad1c254e5cb240eaa" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#bbca30221d8415bad1c254e5cb240eaa">DWC_MODE_SRP_CAPABLE_HOST</a>&nbsp;&nbsp;&nbsp;5</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="91a7255e685d172cfa7b6be0eaab5102"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_MODE_NO_SRP_CAPABLE_HOST" ref="91a7255e685d172cfa7b6be0eaab5102" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#91a7255e685d172cfa7b6be0eaab5102">DWC_MODE_NO_SRP_CAPABLE_HOST</a>&nbsp;&nbsp;&nbsp;6</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="a093dbf54151ef01db550174a2a4ad41"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_GAHBCFG_GLBINT_ENABLE" ref="a093dbf54151ef01db550174a2a4ad41" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#a093dbf54151ef01db550174a2a4ad41">DWC_GAHBCFG_GLBINT_ENABLE</a>&nbsp;&nbsp;&nbsp;1</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="8dceb2d2defa2395d00d9a41d2ce9c2b"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_GAHBCFG_INT_DMA_BURST_SINGLE" ref="8dceb2d2defa2395d00d9a41d2ce9c2b" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#8dceb2d2defa2395d00d9a41d2ce9c2b">DWC_GAHBCFG_INT_DMA_BURST_SINGLE</a>&nbsp;&nbsp;&nbsp;0</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e817b2bec10af4c5e95f10a78e031bcc"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_GAHBCFG_INT_DMA_BURST_INCR" ref="e817b2bec10af4c5e95f10a78e031bcc" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#e817b2bec10af4c5e95f10a78e031bcc">DWC_GAHBCFG_INT_DMA_BURST_INCR</a>&nbsp;&nbsp;&nbsp;1</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f3ed2114e59350a94162f596461c758f"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_GAHBCFG_INT_DMA_BURST_INCR4" ref="f3ed2114e59350a94162f596461c758f" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#f3ed2114e59350a94162f596461c758f">DWC_GAHBCFG_INT_DMA_BURST_INCR4</a>&nbsp;&nbsp;&nbsp;3</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7494f8fa74d6526d38867d7c8b254183"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_GAHBCFG_INT_DMA_BURST_INCR8" ref="7494f8fa74d6526d38867d7c8b254183" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#7494f8fa74d6526d38867d7c8b254183">DWC_GAHBCFG_INT_DMA_BURST_INCR8</a>&nbsp;&nbsp;&nbsp;5</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="07f5766941fd10e92ed221d37a758f4f"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_GAHBCFG_INT_DMA_BURST_INCR16" ref="07f5766941fd10e92ed221d37a758f4f" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#07f5766941fd10e92ed221d37a758f4f">DWC_GAHBCFG_INT_DMA_BURST_INCR16</a>&nbsp;&nbsp;&nbsp;7</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="15510bbfb4d9729c5b5a7dc9ff2ff741"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_GAHBCFG_DMAENABLE" ref="15510bbfb4d9729c5b5a7dc9ff2ff741" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#15510bbfb4d9729c5b5a7dc9ff2ff741">DWC_GAHBCFG_DMAENABLE</a>&nbsp;&nbsp;&nbsp;1</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="bed45675c271744db00ee5445383c1dd"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_GAHBCFG_TXFEMPTYLVL_EMPTY" ref="bed45675c271744db00ee5445383c1dd" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#bed45675c271744db00ee5445383c1dd">DWC_GAHBCFG_TXFEMPTYLVL_EMPTY</a>&nbsp;&nbsp;&nbsp;1</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="0ec8d38e3f85707561b300ae1b339b71"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY" ref="0ec8d38e3f85707561b300ae1b339b71" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#0ec8d38e3f85707561b300ae1b339b71">DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY</a>&nbsp;&nbsp;&nbsp;0</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="8cd1d59e0700e5b528deebdea7a7ac76"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_SOF_INTR_MASK" ref="8cd1d59e0700e5b528deebdea7a7ac76" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#8cd1d59e0700e5b528deebdea7a7ac76">DWC_SOF_INTR_MASK</a>&nbsp;&nbsp;&nbsp;0x0008</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="dc3fa334f676024ecd75f63f885d4ec3"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_HOST_MODE" ref="dc3fa334f676024ecd75f63f885d4ec3" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#dc3fa334f676024ecd75f63f885d4ec3">DWC_HOST_MODE</a>&nbsp;&nbsp;&nbsp;1</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="93cbb84c3631af89d282fb1b406594f5"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_STS_DATA_UPDT" ref="93cbb84c3631af89d282fb1b406594f5" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#93cbb84c3631af89d282fb1b406594f5">DWC_STS_DATA_UPDT</a>&nbsp;&nbsp;&nbsp;0x2</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="53a6a9dd332c8a15f505cd0027fb4c86"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_STS_XFER_COMP" ref="53a6a9dd332c8a15f505cd0027fb4c86" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#53a6a9dd332c8a15f505cd0027fb4c86">DWC_STS_XFER_COMP</a>&nbsp;&nbsp;&nbsp;0x3</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="de6ad4d62ad4debd7d97e27ea68bbe7f"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_DSTS_GOUT_NAK" ref="de6ad4d62ad4debd7d97e27ea68bbe7f" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#de6ad4d62ad4debd7d97e27ea68bbe7f">DWC_DSTS_GOUT_NAK</a>&nbsp;&nbsp;&nbsp;0x1</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="2f7181f56123a3d16d78e204ab6e5e96"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_DSTS_SETUP_COMP" ref="2f7181f56123a3d16d78e204ab6e5e96" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#2f7181f56123a3d16d78e204ab6e5e96">DWC_DSTS_SETUP_COMP</a>&nbsp;&nbsp;&nbsp;0x4</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="416a63dc7ef9b792d21b01cc257bba43"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_DSTS_SETUP_UPDT" ref="416a63dc7ef9b792d21b01cc257bba43" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#416a63dc7ef9b792d21b01cc257bba43">DWC_DSTS_SETUP_UPDT</a>&nbsp;&nbsp;&nbsp;0x6</td></tr>
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+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="d81c89ef7c3e40cfffe9ed08b7136e90"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_GRXSTS_PKTSTS_IN" ref="d81c89ef7c3e40cfffe9ed08b7136e90" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#d81c89ef7c3e40cfffe9ed08b7136e90">DWC_GRXSTS_PKTSTS_IN</a>&nbsp;&nbsp;&nbsp;0x2</td></tr>
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+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c5c019a36ea5cb66d3cb436292d8c3de"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_GRXSTS_PKTSTS_IN_XFER_COMP" ref="c5c019a36ea5cb66d3cb436292d8c3de" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#c5c019a36ea5cb66d3cb436292d8c3de">DWC_GRXSTS_PKTSTS_IN_XFER_COMP</a>&nbsp;&nbsp;&nbsp;0x3</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="63be63fa3258a785d81ded62ab27b30d"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR" ref="63be63fa3258a785d81ded62ab27b30d" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#63be63fa3258a785d81ded62ab27b30d">DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR</a>&nbsp;&nbsp;&nbsp;0x5</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="a6d1e988dc17e285244c4e587440cbef"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_GRXSTS_PKTSTS_CH_HALTED" ref="a6d1e988dc17e285244c4e587440cbef" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#a6d1e988dc17e285244c4e587440cbef">DWC_GRXSTS_PKTSTS_CH_HALTED</a>&nbsp;&nbsp;&nbsp;0x7</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="8af3c99831b24f4f12a6d5c8d738b5c1"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG" ref="8af3c99831b24f4f12a6d5c8d738b5c1" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#8af3c99831b24f4f12a6d5c8d738b5c1">DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG</a>&nbsp;&nbsp;&nbsp;0</td></tr>
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+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="184dedc2208935e427ec8d70f63acc03"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG" ref="184dedc2208935e427ec8d70f63acc03" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#184dedc2208935e427ec8d70f63acc03">DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG</a>&nbsp;&nbsp;&nbsp;1</td></tr>
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+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="9f259c90ff1115e85ad4ffc7dab0186b"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG" ref="9f259c90ff1115e85ad4ffc7dab0186b" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#9f259c90ff1115e85ad4ffc7dab0186b">DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG</a>&nbsp;&nbsp;&nbsp;2</td></tr>
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+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="1f8de01acf1cfba7684a6b541cdacc72"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE" ref="1f8de01acf1cfba7684a6b541cdacc72" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#1f8de01acf1cfba7684a6b541cdacc72">DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE</a>&nbsp;&nbsp;&nbsp;3</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f3d7ebd02f23f2520561832a4972d3c6"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE" ref="f3d7ebd02f23f2520561832a4972d3c6" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#f3d7ebd02f23f2520561832a4972d3c6">DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE</a>&nbsp;&nbsp;&nbsp;4</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="77eccf27fae160a4ad7f72b1b43864c3"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST" ref="77eccf27fae160a4ad7f72b1b43864c3" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#77eccf27fae160a4ad7f72b1b43864c3">DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST</a>&nbsp;&nbsp;&nbsp;5</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="dc5c9ee91aa1e0070aa05fd7d958ab8f"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST" ref="dc5c9ee91aa1e0070aa05fd7d958ab8f" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#dc5c9ee91aa1e0070aa05fd7d958ab8f">DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST</a>&nbsp;&nbsp;&nbsp;6</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7286edbddfc6b83cf2082a0ad88932ae"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED" ref="7286edbddfc6b83cf2082a0ad88932ae" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#7286edbddfc6b83cf2082a0ad88932ae">DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED</a>&nbsp;&nbsp;&nbsp;0</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e216917509a2f9a01493b5d9acc8717c"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_HWCFG2_HS_PHY_TYPE_UTMI" ref="e216917509a2f9a01493b5d9acc8717c" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#e216917509a2f9a01493b5d9acc8717c">DWC_HWCFG2_HS_PHY_TYPE_UTMI</a>&nbsp;&nbsp;&nbsp;1</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="0633e41edfacfabfb7ba32f972dc0479"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_HWCFG2_HS_PHY_TYPE_ULPI" ref="0633e41edfacfabfb7ba32f972dc0479" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#0633e41edfacfabfb7ba32f972dc0479">DWC_HWCFG2_HS_PHY_TYPE_ULPI</a>&nbsp;&nbsp;&nbsp;2</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="0a3e7ebf66c6ecde6d4fc4e6d5e14d5e"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI" ref="0a3e7ebf66c6ecde6d4fc4e6d5e14d5e" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#0a3e7ebf66c6ecde6d4fc4e6d5e14d5e">DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI</a>&nbsp;&nbsp;&nbsp;3</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="867bd5c96203c1cf32fbbe78ca893a72"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_DCFG_SEND_STALL" ref="867bd5c96203c1cf32fbbe78ca893a72" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#867bd5c96203c1cf32fbbe78ca893a72">DWC_DCFG_SEND_STALL</a>&nbsp;&nbsp;&nbsp;1</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="d5b5378a658017c4f9cbdd8e4462d4fc"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_DCFG_FRAME_INTERVAL_80" ref="d5b5378a658017c4f9cbdd8e4462d4fc" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#d5b5378a658017c4f9cbdd8e4462d4fc">DWC_DCFG_FRAME_INTERVAL_80</a>&nbsp;&nbsp;&nbsp;0</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="0724fae5fc15468eabad5dd76c39e74f"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_DCFG_FRAME_INTERVAL_85" ref="0724fae5fc15468eabad5dd76c39e74f" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#0724fae5fc15468eabad5dd76c39e74f">DWC_DCFG_FRAME_INTERVAL_85</a>&nbsp;&nbsp;&nbsp;1</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3652689417367e081e78a6cc0df59686"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_DCFG_FRAME_INTERVAL_90" ref="3652689417367e081e78a6cc0df59686" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#3652689417367e081e78a6cc0df59686">DWC_DCFG_FRAME_INTERVAL_90</a>&nbsp;&nbsp;&nbsp;2</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="12d2316f6beb751fca190b3865baeb50"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_DCFG_FRAME_INTERVAL_95" ref="12d2316f6beb751fca190b3865baeb50" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#12d2316f6beb751fca190b3865baeb50">DWC_DCFG_FRAME_INTERVAL_95</a>&nbsp;&nbsp;&nbsp;3</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="2c41cb64f1ba728146bece30a622044c"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ" ref="2c41cb64f1ba728146bece30a622044c" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#2c41cb64f1ba728146bece30a622044c">DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ</a>&nbsp;&nbsp;&nbsp;0</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="373742ad0a97af406169cc3ada63ca04"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ" ref="373742ad0a97af406169cc3ada63ca04" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#373742ad0a97af406169cc3ada63ca04">DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ</a>&nbsp;&nbsp;&nbsp;1</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7df682e9f37924c859657ff26fee5cbc"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_DSTS_ENUMSPD_LS_PHY_6MHZ" ref="7df682e9f37924c859657ff26fee5cbc" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#7df682e9f37924c859657ff26fee5cbc">DWC_DSTS_ENUMSPD_LS_PHY_6MHZ</a>&nbsp;&nbsp;&nbsp;2</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="81dafef32b78df31eb2eeac36fd0694a"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_DSTS_ENUMSPD_FS_PHY_48MHZ" ref="81dafef32b78df31eb2eeac36fd0694a" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#81dafef32b78df31eb2eeac36fd0694a">DWC_DSTS_ENUMSPD_FS_PHY_48MHZ</a>&nbsp;&nbsp;&nbsp;3</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="8ed30be9c5fc70ceb62f8e974ef5d58f"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_DEP0CTL_MPS_64" ref="8ed30be9c5fc70ceb62f8e974ef5d58f" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#8ed30be9c5fc70ceb62f8e974ef5d58f">DWC_DEP0CTL_MPS_64</a>&nbsp;&nbsp;&nbsp;0</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="1571f704fa9a27aed09f5bf9f1fee3cd"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_DEP0CTL_MPS_32" ref="1571f704fa9a27aed09f5bf9f1fee3cd" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#1571f704fa9a27aed09f5bf9f1fee3cd">DWC_DEP0CTL_MPS_32</a>&nbsp;&nbsp;&nbsp;1</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f5eb5941743a925692ca3008e795f0c9"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_DEP0CTL_MPS_16" ref="f5eb5941743a925692ca3008e795f0c9" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#f5eb5941743a925692ca3008e795f0c9">DWC_DEP0CTL_MPS_16</a>&nbsp;&nbsp;&nbsp;2</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3207e5140ff0395b34f637942ab5b191"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_DEP0CTL_MPS_8" ref="3207e5140ff0395b34f637942ab5b191" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#3207e5140ff0395b34f637942ab5b191">DWC_DEP0CTL_MPS_8</a>&nbsp;&nbsp;&nbsp;3</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c2cfc53da94087a90d21d3528b005bcf"></a><!-- doxytag: member="dwc_otg_regs.h::BS_HOST_READY" ref="c2cfc53da94087a90d21d3528b005bcf" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#c2cfc53da94087a90d21d3528b005bcf">BS_HOST_READY</a>&nbsp;&nbsp;&nbsp;0x0</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Buffer status definitions. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3110b1318d89fe11ee69f3ccbe219c4e"></a><!-- doxytag: member="dwc_otg_regs.h::BS_DMA_BUSY" ref="3110b1318d89fe11ee69f3ccbe219c4e" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#3110b1318d89fe11ee69f3ccbe219c4e">BS_DMA_BUSY</a>&nbsp;&nbsp;&nbsp;0x1</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b20f6432003d81072ed8b7cd66d6305b"></a><!-- doxytag: member="dwc_otg_regs.h::BS_DMA_DONE" ref="b20f6432003d81072ed8b7cd66d6305b" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#b20f6432003d81072ed8b7cd66d6305b">BS_DMA_DONE</a>&nbsp;&nbsp;&nbsp;0x2</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e6e96a79797557986256d1a1ff104ca1"></a><!-- doxytag: member="dwc_otg_regs.h::BS_HOST_BUSY" ref="e6e96a79797557986256d1a1ff104ca1" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#e6e96a79797557986256d1a1ff104ca1">BS_HOST_BUSY</a>&nbsp;&nbsp;&nbsp;0x3</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="cc9b21a293ad5a9103a64d76314a052e"></a><!-- doxytag: member="dwc_otg_regs.h::RTS_SUCCESS" ref="cc9b21a293ad5a9103a64d76314a052e" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#cc9b21a293ad5a9103a64d76314a052e">RTS_SUCCESS</a>&nbsp;&nbsp;&nbsp;0x0</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Receive/Transmit status definitions. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="46f9d43df5fef233f4f5415d4719c1da"></a><!-- doxytag: member="dwc_otg_regs.h::RTS_BUFFLUSH" ref="46f9d43df5fef233f4f5415d4719c1da" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#46f9d43df5fef233f4f5415d4719c1da">RTS_BUFFLUSH</a>&nbsp;&nbsp;&nbsp;0x1</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="1fa264096eca908e709d19b87a53f13f"></a><!-- doxytag: member="dwc_otg_regs.h::RTS_RESERVED" ref="1fa264096eca908e709d19b87a53f13f" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#1fa264096eca908e709d19b87a53f13f">RTS_RESERVED</a>&nbsp;&nbsp;&nbsp;0x2</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="55b69fa65e7d41448646c88fc0642408"></a><!-- doxytag: member="dwc_otg_regs.h::RTS_BUFERR" ref="55b69fa65e7d41448646c88fc0642408" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#55b69fa65e7d41448646c88fc0642408">RTS_BUFERR</a>&nbsp;&nbsp;&nbsp;0x3</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="4ea9445cbc89c8cc6bbf01c9dd7a9883"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_DEV_GLOBAL_REG_OFFSET" ref="4ea9445cbc89c8cc6bbf01c9dd7a9883" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#4ea9445cbc89c8cc6bbf01c9dd7a9883">DWC_DEV_GLOBAL_REG_OFFSET</a>&nbsp;&nbsp;&nbsp;0x800</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="57eeaae2d9cf530fbae00d3f462cc7da"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_DEV_IN_EP_REG_OFFSET" ref="57eeaae2d9cf530fbae00d3f462cc7da" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#57eeaae2d9cf530fbae00d3f462cc7da">DWC_DEV_IN_EP_REG_OFFSET</a>&nbsp;&nbsp;&nbsp;0x900</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c9c83030effbf067775d9111e4d90895"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_EP_REG_OFFSET" ref="c9c83030effbf067775d9111e4d90895" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#c9c83030effbf067775d9111e4d90895">DWC_EP_REG_OFFSET</a>&nbsp;&nbsp;&nbsp;0x20</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7234e42a2bcd47aca0d67a414eb0598e"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_DEV_OUT_EP_REG_OFFSET" ref="7234e42a2bcd47aca0d67a414eb0598e" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#7234e42a2bcd47aca0d67a414eb0598e">DWC_DEV_OUT_EP_REG_OFFSET</a>&nbsp;&nbsp;&nbsp;0xB00</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="398b117902d7a5594388a5086bb2de21"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_HCFG_30_60_MHZ" ref="398b117902d7a5594388a5086bb2de21" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#398b117902d7a5594388a5086bb2de21">DWC_HCFG_30_60_MHZ</a>&nbsp;&nbsp;&nbsp;0</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="556ba73fd9346d666a7c0a28fcf993a7"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_HCFG_48_MHZ" ref="556ba73fd9346d666a7c0a28fcf993a7" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#556ba73fd9346d666a7c0a28fcf993a7">DWC_HCFG_48_MHZ</a>&nbsp;&nbsp;&nbsp;1</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="40a20b71af7ff9f23a2241a2e4c3c819"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_HCFG_6_MHZ" ref="40a20b71af7ff9f23a2241a2e4c3c819" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#40a20b71af7ff9f23a2241a2e4c3c819">DWC_HCFG_6_MHZ</a>&nbsp;&nbsp;&nbsp;2</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="4903938414e67044883b7df5582d6eed"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_HFNUM_MAX_FRNUM" ref="4903938414e67044883b7df5582d6eed" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#4903938414e67044883b7df5582d6eed">DWC_HFNUM_MAX_FRNUM</a>&nbsp;&nbsp;&nbsp;0x3FFF</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="4556f79078df2164a8162fa8144142a0"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_HPRT0_PRTSPD_HIGH_SPEED" ref="4556f79078df2164a8162fa8144142a0" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#4556f79078df2164a8162fa8144142a0">DWC_HPRT0_PRTSPD_HIGH_SPEED</a>&nbsp;&nbsp;&nbsp;0</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="1d144361f6655bb79e7503e7159e6be5"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_HPRT0_PRTSPD_FULL_SPEED" ref="1d144361f6655bb79e7503e7159e6be5" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#1d144361f6655bb79e7503e7159e6be5">DWC_HPRT0_PRTSPD_FULL_SPEED</a>&nbsp;&nbsp;&nbsp;1</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="db9e36d1ab76c334f6e004ee270bd36f"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_HPRT0_PRTSPD_LOW_SPEED" ref="db9e36d1ab76c334f6e004ee270bd36f" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#db9e36d1ab76c334f6e004ee270bd36f">DWC_HPRT0_PRTSPD_LOW_SPEED</a>&nbsp;&nbsp;&nbsp;2</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="2297a1a33f502bc705e5c450c9864c6c"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_HCSPLIT_XACTPOS_MID" ref="2297a1a33f502bc705e5c450c9864c6c" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#2297a1a33f502bc705e5c450c9864c6c">DWC_HCSPLIT_XACTPOS_MID</a>&nbsp;&nbsp;&nbsp;0</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="fc237b3dd77c97276aa4bd50947117e2"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_HCSPLIT_XACTPOS_END" ref="fc237b3dd77c97276aa4bd50947117e2" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#fc237b3dd77c97276aa4bd50947117e2">DWC_HCSPLIT_XACTPOS_END</a>&nbsp;&nbsp;&nbsp;1</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c0b856e1a71e0373153d986a3cb5b135"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_HCSPLIT_XACTPOS_BEGIN" ref="c0b856e1a71e0373153d986a3cb5b135" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#c0b856e1a71e0373153d986a3cb5b135">DWC_HCSPLIT_XACTPOS_BEGIN</a>&nbsp;&nbsp;&nbsp;2</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b8a8f35d8fd73c955cc0403e87cea0c6"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_HCSPLIT_XACTPOS_ALL" ref="b8a8f35d8fd73c955cc0403e87cea0c6" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#b8a8f35d8fd73c955cc0403e87cea0c6">DWC_HCSPLIT_XACTPOS_ALL</a>&nbsp;&nbsp;&nbsp;3</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ab429f705d8fb6db88a206968e438217"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_HCTSIZ_DATA0" ref="ab429f705d8fb6db88a206968e438217" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#ab429f705d8fb6db88a206968e438217">DWC_HCTSIZ_DATA0</a>&nbsp;&nbsp;&nbsp;0</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="8d9f79dc6ec3535659b6420115c8da80"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_HCTSIZ_DATA1" ref="8d9f79dc6ec3535659b6420115c8da80" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#8d9f79dc6ec3535659b6420115c8da80">DWC_HCTSIZ_DATA1</a>&nbsp;&nbsp;&nbsp;2</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="674f7277e9e0a30b9f169ecceccf45e0"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_HCTSIZ_DATA2" ref="674f7277e9e0a30b9f169ecceccf45e0" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#674f7277e9e0a30b9f169ecceccf45e0">DWC_HCTSIZ_DATA2</a>&nbsp;&nbsp;&nbsp;1</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="55e76fff4514ef727b2a1f6eead7a4e5"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_HCTSIZ_MDATA" ref="55e76fff4514ef727b2a1f6eead7a4e5" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#55e76fff4514ef727b2a1f6eead7a4e5">DWC_HCTSIZ_MDATA</a>&nbsp;&nbsp;&nbsp;3</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3ce73700b1bd235f124e2a08e516aa88"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_HCTSIZ_SETUP" ref="3ce73700b1bd235f124e2a08e516aa88" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#3ce73700b1bd235f124e2a08e516aa88">DWC_HCTSIZ_SETUP</a>&nbsp;&nbsp;&nbsp;3</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="175767634e612a1e3dff3207a787d402"></a><!-- doxytag: member="dwc_otg_regs.h::DMA_DESC_STS_PKTERR" ref="175767634e612a1e3dff3207a787d402" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#175767634e612a1e3dff3207a787d402">DMA_DESC_STS_PKTERR</a>&nbsp;&nbsp;&nbsp;1</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="000f3273fb3033d587107e7eff3c1ff6"></a><!-- doxytag: member="dwc_otg_regs.h::MAX_DMA_DESC_SIZE" ref="000f3273fb3033d587107e7eff3c1ff6" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#000f3273fb3033d587107e7eff3c1ff6">MAX_DMA_DESC_SIZE</a>&nbsp;&nbsp;&nbsp;131071</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7f241a3ed7bd5c0d4f1a496c77cbc225"></a><!-- doxytag: member="dwc_otg_regs.h::MAX_DMA_DESC_NUM_GENERIC" ref="7f241a3ed7bd5c0d4f1a496c77cbc225" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#7f241a3ed7bd5c0d4f1a496c77cbc225">MAX_DMA_DESC_NUM_GENERIC</a>&nbsp;&nbsp;&nbsp;64</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b190810b3017403bd58b6346aad4e4ed"></a><!-- doxytag: member="dwc_otg_regs.h::MAX_DMA_DESC_NUM_HS_ISOC" ref="b190810b3017403bd58b6346aad4e4ed" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#b190810b3017403bd58b6346aad4e4ed">MAX_DMA_DESC_NUM_HS_ISOC</a>&nbsp;&nbsp;&nbsp;256</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ff2c2ac58a30e050d647d0f9a256d0bd"></a><!-- doxytag: member="dwc_otg_regs.h::MAX_FRLIST_EN_NUM" ref="ff2c2ac58a30e050d647d0f9a256d0bd" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#ff2c2ac58a30e050d647d0f9a256d0bd">MAX_FRLIST_EN_NUM</a>&nbsp;&nbsp;&nbsp;64</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b9ef775c8628a8f225e36729cf1be0c3"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_OTG_HOST_GLOBAL_REG_OFFSET" ref="b9ef775c8628a8f225e36729cf1be0c3" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#b9ef775c8628a8f225e36729cf1be0c3">DWC_OTG_HOST_GLOBAL_REG_OFFSET</a>&nbsp;&nbsp;&nbsp;0x400</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="d34097dedb09e076ae91cef4ab3b4b2a"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_OTG_HOST_PORT_REGS_OFFSET" ref="d34097dedb09e076ae91cef4ab3b4b2a" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#d34097dedb09e076ae91cef4ab3b4b2a">DWC_OTG_HOST_PORT_REGS_OFFSET</a>&nbsp;&nbsp;&nbsp;0x440</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="76dd0c82028245c6a217ad7ee366cf15"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_OTG_HOST_CHAN_REGS_OFFSET" ref="76dd0c82028245c6a217ad7ee366cf15" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#76dd0c82028245c6a217ad7ee366cf15">DWC_OTG_HOST_CHAN_REGS_OFFSET</a>&nbsp;&nbsp;&nbsp;0x500</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="850bdd3d5997cdf22bf69fe0a0df6be1"></a><!-- doxytag: member="dwc_otg_regs.h::DWC_OTG_CHAN_REGS_OFFSET" ref="850bdd3d5997cdf22bf69fe0a0df6be1" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#850bdd3d5997cdf22bf69fe0a0df6be1">DWC_OTG_CHAN_REGS_OFFSET</a>&nbsp;&nbsp;&nbsp;0x20</td></tr>
+
+<tr><td colspan="2"><br><h2>Typedefs</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef <a class="el" href="structdwc__otg__core__global__regs.html">dwc_otg_core_global_regs</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#4ba81f9e704c22b6ae0155dfb103b040">dwc_otg_core_global_regs_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">DWC_otg Core registers .  <a href="#4ba81f9e704c22b6ae0155dfb103b040"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef <a class="el" href="uniongotgctl__data.html">gotgctl_data</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#6a10de8c32943876bfc55ed308d3ff83">gotgctl_data_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields of the Core OTG Control and Status Register (GOTGCTL).  <a href="#6a10de8c32943876bfc55ed308d3ff83"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef <a class="el" href="uniongotgint__data.html">gotgint_data</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#9f95118956319102de69927308a2defd">gotgint_data_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields of the Core OTG Interrupt Register (GOTGINT).  <a href="#9f95118956319102de69927308a2defd"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef <a class="el" href="uniongahbcfg__data.html">gahbcfg_data</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#e1aca1c2d0abbb005545a17af3508291">gahbcfg_data_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields of the Core AHB Configuration Register (GAHBCFG).  <a href="#e1aca1c2d0abbb005545a17af3508291"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef <a class="el" href="uniongusbcfg__data.html">gusbcfg_data</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#176748792c6f7aedc1aacf6740c2b1dd">gusbcfg_data_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields of the Core USB Configuration Register (GUSBCFG).  <a href="#176748792c6f7aedc1aacf6740c2b1dd"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef <a class="el" href="unionglpmctl__data.html">glpmctl_data</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#ba73e60dacc956a6090a82188bb8fcfa">glpmcfg_data_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields of the Core LPM Configuration Register (GLPMCFG).  <a href="#ba73e60dacc956a6090a82188bb8fcfa"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef <a class="el" href="uniongrstctl__data.html">grstctl_data</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#ca690ce842cde2518004eefeedda7788">grstctl_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields of the Core Reset Register (GRSTCTL).  <a href="#ca690ce842cde2518004eefeedda7788"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef <a class="el" href="uniongintmsk__data.html">gintmsk_data</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#db54cb8baf5c7d970347192ad40662d3">gintmsk_data_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields of the Core Interrupt Mask Register (GINTMSK).  <a href="#db54cb8baf5c7d970347192ad40662d3"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef <a class="el" href="uniongintsts__data.html">gintsts_data</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#211ef100682c75981568527ed748dcfc">gintsts_data_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields of the Core Interrupt Register (GINTSTS).  <a href="#211ef100682c75981568527ed748dcfc"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="89dcb8224836ceda40e3584b3db51411"></a><!-- doxytag: member="dwc_otg_regs.h::device_grxsts_data_t" ref="89dcb8224836ceda40e3584b3db51411" args="" -->
+typedef <a class="el" href="uniondevice__grxsts__data.html">device_grxsts_data</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#89dcb8224836ceda40e3584b3db51411">device_grxsts_data_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the Device Receive Status Read and Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <em>d32</em> element then read out the bits using the <em>b</em>it elements. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="1d5d223eb9bab051464aca64efd707e1"></a><!-- doxytag: member="dwc_otg_regs.h::host_grxsts_data_t" ref="1d5d223eb9bab051464aca64efd707e1" args="" -->
+typedef <a class="el" href="unionhost__grxsts__data.html">host_grxsts_data</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#1d5d223eb9bab051464aca64efd707e1">host_grxsts_data_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the Host Receive Status Read and Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <em>d32</em> element then read out the bits using the <em>b</em>it elements. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef <a class="el" href="unionfifosize__data.html">fifosize_data</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#389bbcdb2f9b7b284631c4e3c6c05ca4">fifosize_data_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ, GNPTXFSIZ, DPTXFSIZn, DIEPTXFn).  <a href="#389bbcdb2f9b7b284631c4e3c6c05ca4"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef <a class="el" href="uniongnptxsts__data.html">gnptxsts_data</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#e00daff072291dd6e7af34701aad3138">gnptxsts_data_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the Non-Periodic Transmit FIFO/Queue Status Register (GNPTXSTS).  <a href="#e00daff072291dd6e7af34701aad3138"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef <a class="el" href="uniondtxfsts__data.html">dtxfsts_data</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#d3e24afd53e919e2cb6d436506248f75">dtxfsts_data_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the Transmit FIFO Status Register (DTXFSTS).  <a href="#d3e24afd53e919e2cb6d436506248f75"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef <a class="el" href="uniongi2cctl__data.html">gi2cctl_data</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#de10c5861b75d2f22b1a1b9e817a3098">gi2cctl_data_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the I2C Control Register (I2CCTL).  <a href="#de10c5861b75d2f22b1a1b9e817a3098"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef <a class="el" href="unionhwcfg1__data.html">hwcfg1_data</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#e3fd2e458471dcd8fec9fa09ff787ad5">hwcfg1_data_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the User HW Config1 Register.  <a href="#e3fd2e458471dcd8fec9fa09ff787ad5"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef <a class="el" href="unionhwcfg2__data.html">hwcfg2_data</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#a3044f8c36a47affba16a8abcebc2a33">hwcfg2_data_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the User HW Config2 Register.  <a href="#a3044f8c36a47affba16a8abcebc2a33"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef <a class="el" href="unionhwcfg3__data.html">hwcfg3_data</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#cec01b13bc8d56e9001801bb14a98857">hwcfg3_data_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the User HW Config3 Register.  <a href="#cec01b13bc8d56e9001801bb14a98857"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef <a class="el" href="unionhwcfg4__data.html">hwcfg4_data</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#d9159ac522a8a34be480e616a9df7ebe">hwcfg4_data_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the User HW Config4 Register.  <a href="#d9159ac522a8a34be480e616a9df7ebe"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef <a class="el" href="structdwc__otg__dev__global__regs.html">dwc_otg_dev_global_regs</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#c8e8458afafc8849b85f5b5fcf9b6d1b">dwc_otg_device_global_regs_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Device Global Registers.  <a href="#c8e8458afafc8849b85f5b5fcf9b6d1b"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef <a class="el" href="uniondcfg__data.html">dcfg_data</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#077228cd7e2acbd1e246bd9b0379c524">dcfg_data_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the Device Configuration Register.  <a href="#077228cd7e2acbd1e246bd9b0379c524"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef <a class="el" href="uniondctl__data.html">dctl_data</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#043805708857633a05ae076cf8c0a143">dctl_data_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the Device Control Register.  <a href="#043805708857633a05ae076cf8c0a143"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef <a class="el" href="uniondsts__data.html">dsts_data</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#2bd7f2043b7f4841e17b38edc406e06d">dsts_data_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the Device Status Register.  <a href="#2bd7f2043b7f4841e17b38edc406e06d"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef <a class="el" href="uniondiepint__data.html">diepint_data</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#0f4ab8ee4156c299665471b3a6f279ce">diepint_data_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the Device IN EP Interrupt Register and the Device IN EP Common Mask Register.  <a href="#0f4ab8ee4156c299665471b3a6f279ce"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="0a168a8839d24b08e39eebb131447531"></a><!-- doxytag: member="dwc_otg_regs.h::diepmsk_data_t" ref="0a168a8839d24b08e39eebb131447531" args="" -->
+typedef <a class="el" href="uniondiepint__data.html">diepint_data</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#0a168a8839d24b08e39eebb131447531">diepmsk_data_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the Device IN EP Common/Dedicated Interrupt Mask Register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef <a class="el" href="uniondoepint__data.html">doepint_data</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#692b7898b190ff12cca460bd0711db3f">doepint_data_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the Device OUT EP Interrupt Registerand Device OUT EP Common Interrupt Mask Register.  <a href="#692b7898b190ff12cca460bd0711db3f"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="722a9ff3c92f6c195b9ee3c3838b6bbb"></a><!-- doxytag: member="dwc_otg_regs.h::doepmsk_data_t" ref="722a9ff3c92f6c195b9ee3c3838b6bbb" args="" -->
+typedef <a class="el" href="uniondoepint__data.html">doepint_data</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#722a9ff3c92f6c195b9ee3c3838b6bbb">doepmsk_data_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the Device OUT EP Common/Dedicated Interrupt Mask Register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef <a class="el" href="uniondaint__data.html">daint_data</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#1effb8b11c6a62aacfcbea74c1be84f6">daint_data_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the Device All EP Interrupt and Mask Registers.  <a href="#1effb8b11c6a62aacfcbea74c1be84f6"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef <a class="el" href="uniondtknq1__data.html">dtknq1_data</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#61e9acc9f9165e3fb6c15ce96db21861">dtknq1_data_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the Device IN Token Queue Read Registers.  <a href="#61e9acc9f9165e3fb6c15ce96db21861"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef <a class="el" href="uniondthrctl__data.html">dthrctl_data</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#962414fc1e02940112ab0db4c53bcc6c">dthrctl_data_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents Threshold control Register<ul>
+<li>Read and write the register into the <em>d32</em> member. </li></ul>
+ <a href="#962414fc1e02940112ab0db4c53bcc6c"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef <a class="el" href="structdwc__otg__dev__in__ep__regs.html">dwc_otg_dev_in_ep_regs</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#f23afc1a2db189b69772170cbd68b509">dwc_otg_dev_in_ep_regs_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Device Logical IN Endpoint-Specific Registers.  <a href="#f23afc1a2db189b69772170cbd68b509"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef <a class="el" href="structdwc__otg__dev__out__ep__regs.html">dwc_otg_dev_out_ep_regs</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#67ce4d713bb26f1244377b55aec8035a">dwc_otg_dev_out_ep_regs_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Device Logical OUT Endpoint-Specific Registers.  <a href="#67ce4d713bb26f1244377b55aec8035a"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef <a class="el" href="uniondepctl__data.html">depctl_data</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#1d8ef2c3a67226833c01502c66bbd7a3">depctl_data_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the Device EP Control Register.  <a href="#1d8ef2c3a67226833c01502c66bbd7a3"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef <a class="el" href="uniondeptsiz__data.html">deptsiz_data</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#cb6f36bd93d869b9e61de914c8e2d222">deptsiz_data_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the Device EP Transfer Size Register.  <a href="#cb6f36bd93d869b9e61de914c8e2d222"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef <a class="el" href="uniondeptsiz0__data.html">deptsiz0_data</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#0c2941814d5219b96c19caac80d58a3e">deptsiz0_data_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the Device EP 0 Transfer Size Register.  <a href="#0c2941814d5219b96c19caac80d58a3e"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef <a class="el" href="uniondev__dma__desc__sts.html">dev_dma_desc_sts</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#5363ac57fa4401cb81be60414d9104fe">dev_dma_desc_sts_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the DMA Descriptor status quadlet.  <a href="#5363ac57fa4401cb81be60414d9104fe"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef <a class="el" href="structdwc__otg__dev__dma__desc.html">dwc_otg_dev_dma_desc</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#e10a2a455a645b5d69d3a078b82ffc75">dwc_otg_dev_dma_desc_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">DMA Descriptor structure.  <a href="#e10a2a455a645b5d69d3a078b82ffc75"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef <a class="el" href="structdwc__otg__dev__if.html">dwc_otg_dev_if</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#9cc9d3e0d8697163a63c07db365a8d72">dwc_otg_dev_if_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">The <a class="el" href="structdwc__otg__dev__if.html">dwc_otg_dev_if</a> structure contains information needed to manage the DWC_otg controller acting in device mode.  <a href="#9cc9d3e0d8697163a63c07db365a8d72"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef <a class="el" href="structdwc__otg__host__global__regs.html">dwc_otg_host_global_regs</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#9e250e84dc7eefacc94a0d9d9fd198df">dwc_otg_host_global_regs_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">The Host Global Registers structure defines the size and relative field offsets for the Host Mode Global Registers.  <a href="#9e250e84dc7eefacc94a0d9d9fd198df"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef <a class="el" href="unionhcfg__data.html">hcfg_data</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#26f6beffdddc3cbe5f7ec4f77824cca0">hcfg_data_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the Host Configuration Register.  <a href="#26f6beffdddc3cbe5f7ec4f77824cca0"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ff5539ea6d98c6725480b533c13dc652"></a><!-- doxytag: member="dwc_otg_regs.h::hfir_data_t" ref="ff5539ea6d98c6725480b533c13dc652" args="" -->
+typedef <a class="el" href="unionhfir__data.html">hfir_data</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#ff5539ea6d98c6725480b533c13dc652">hfir_data_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the Host Frame Remaing/Number Register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f5c22a704229989ff3435059ebe9fb10"></a><!-- doxytag: member="dwc_otg_regs.h::hfnum_data_t" ref="f5c22a704229989ff3435059ebe9fb10" args="" -->
+typedef <a class="el" href="unionhfnum__data.html">hfnum_data</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#f5c22a704229989ff3435059ebe9fb10">hfnum_data_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the Host Frame Remaing/Number Register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="d10f5283af2413d9f1e2cd565a67bc23"></a><!-- doxytag: member="dwc_otg_regs.h::hptxsts_data_t" ref="d10f5283af2413d9f1e2cd565a67bc23" args="" -->
+typedef <a class="el" href="unionhptxsts__data.html">hptxsts_data</a>&nbsp;</td><td class="memItemRight" valign="bottom"><b>hptxsts_data_t</b></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef <a class="el" href="unionhprt0__data.html">hprt0_data</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#b6962581d4be622894de1b523256f4f9">hprt0_data_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the Host Port Control and Status Register.  <a href="#b6962581d4be622894de1b523256f4f9"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="27de5d0beb5957eb126766a01fec40b2"></a><!-- doxytag: member="dwc_otg_regs.h::haint_data_t" ref="27de5d0beb5957eb126766a01fec40b2" args="" -->
+typedef <a class="el" href="unionhaint__data.html">haint_data</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#27de5d0beb5957eb126766a01fec40b2">haint_data_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the Host All Interrupt Register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f8363fbf7d3be043235c0bf6b057a637"></a><!-- doxytag: member="dwc_otg_regs.h::haintmsk_data_t" ref="f8363fbf7d3be043235c0bf6b057a637" args="" -->
+typedef <a class="el" href="unionhaintmsk__data.html">haintmsk_data</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#f8363fbf7d3be043235c0bf6b057a637">haintmsk_data_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the Host All Interrupt Register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef <a class="el" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#c64589846d616caf2a82a41be5dc359b">dwc_otg_hc_regs_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Host Channel Specific Registers.  <a href="#c64589846d616caf2a82a41be5dc359b"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef <a class="el" href="unionhcchar__data.html">hcchar_data</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#e3bd36607e63cd3181c877f329a6eff8">hcchar_data_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the Host Channel Characteristics Register.  <a href="#e3bd36607e63cd3181c877f329a6eff8"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="045816994a73b8521b6da78c3107213c"></a><!-- doxytag: member="dwc_otg_regs.h::hcsplt_data_t" ref="045816994a73b8521b6da78c3107213c" args="" -->
+typedef <a class="el" href="unionhcsplt__data.html">hcsplt_data</a>&nbsp;</td><td class="memItemRight" valign="bottom"><b>hcsplt_data_t</b></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c765ad9a2d3eff579f45362a2dcf39e3"></a><!-- doxytag: member="dwc_otg_regs.h::hcint_data_t" ref="c765ad9a2d3eff579f45362a2dcf39e3" args="" -->
+typedef <a class="el" href="unionhcint__data.html">hcint_data</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#c765ad9a2d3eff579f45362a2dcf39e3">hcint_data_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the Host All Interrupt Register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef <a class="el" href="unionhcintmsk__data.html">hcintmsk_data</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#eeffbd23c7de44b01363bf196b4a6a44">hcintmsk_data_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the Host Channel Interrupt Mask Register.  <a href="#eeffbd23c7de44b01363bf196b4a6a44"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef <a class="el" href="unionhctsiz__data.html">hctsiz_data</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#2f3d030c12693e0cf5876517856766b4">hctsiz_data_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the Host Channel Transfer Size Register.  <a href="#2f3d030c12693e0cf5876517856766b4"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="018c0b4c795e3d3c373348fd4dafecb4"></a><!-- doxytag: member="dwc_otg_regs.h::hcdma_data_t" ref="018c0b4c795e3d3c373348fd4dafecb4" args="" -->
+typedef <a class="el" href="unionhcdma__data.html">hcdma_data</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#018c0b4c795e3d3c373348fd4dafecb4">hcdma_data_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the Host DMA Address Register used in Descriptor DMA mode. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef <a class="el" href="unionhost__dma__desc__sts.html">host_dma_desc_sts</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#fbefbebde0abe3db88477ab0831d865a">host_dma_desc_sts_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the DMA Descriptor status quadlet for host mode.  <a href="#fbefbebde0abe3db88477ab0831d865a"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef <a class="el" href="structdwc__otg__host__dma__desc.html">dwc_otg_host_dma_desc</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#c4ddf8781cd4885c274d7964d3a32337">dwc_otg_host_dma_desc_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Host-mode DMA Descriptor structure.  <a href="#c4ddf8781cd4885c274d7964d3a32337"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef <a class="el" href="structdwc__otg__host__if.html">dwc_otg_host_if</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#3fce2e3cb951b38f1c6fec40637392c2">dwc_otg_host_if_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">OTG Host Interface Structure.  <a href="#3fce2e3cb951b38f1c6fec40637392c2"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">typedef <a class="el" href="unionpcgcctl__data.html">pcgcctl_data</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="dwc__otg__regs_8h.html#5efd1b5bf72987298cdf3d79bca37832">pcgcctl_data_t</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This union represents the bit fields in the Power and Clock Gating Control Register.  <a href="#5efd1b5bf72987298cdf3d79bca37832"></a><br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This file contains the data structures for accessing the DWC_otg core registers. 
+<p>
+The application interfaces with the HS OTG core by reading from and writing to the Control and Status Register (CSR) space through the AHB Slave interface. These registers are 32 bits wide, and the addresses are 32-bit-block aligned. CSRs are classified as follows:<ul>
+<li>Core Global Registers</li><li>Device Mode Registers</li><li>Device Global Registers</li><li>Device Endpoint Specific Registers</li><li>Host Mode Registers</li><li>Host Global Registers</li><li>Host Port CSRs</li><li>Host Channel Specific Registers</li></ul>
+<p>
+Only the Core Global registers can be accessed in both Device and Host modes. When the HS OTG core is operating in one mode, either Device or Host, the application must not access registers from the other mode. When the core switches from one mode to another, the registers in the new mode of operation must be reprogrammed as they would be after a power-on reset. 
+<p>
+Definition in file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr><h2>Typedef Documentation</h2>
+<a class="anchor" name="4ba81f9e704c22b6ae0155dfb103b040"></a><!-- doxytag: member="dwc_otg_regs.h::dwc_otg_core_global_regs_t" ref="4ba81f9e704c22b6ae0155dfb103b040" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef struct <a class="el" href="structdwc__otg__core__global__regs.html">dwc_otg_core_global_regs</a>  <a class="el" href="structdwc__otg__core__global__regs.html">dwc_otg_core_global_regs_t</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+DWC_otg Core registers . 
+<p>
+The <a class="el" href="structdwc__otg__core__global__regs.html">dwc_otg_core_global_regs</a> structure defines the size and relative field offsets for the Core Global registers. 
+</div>
+</div><p>
+<a class="anchor" name="6a10de8c32943876bfc55ed308d3ff83"></a><!-- doxytag: member="dwc_otg_regs.h::gotgctl_data_t" ref="6a10de8c32943876bfc55ed308d3ff83" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef union <a class="el" href="uniongotgctl__data.html">gotgctl_data</a>  <a class="el" href="uniongotgctl__data.html">gotgctl_data_t</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This union represents the bit fields of the Core OTG Control and Status Register (GOTGCTL). 
+<p>
+Set the bits using the bit fields then write the <em>d32</em> value to the register. 
+</div>
+</div><p>
+<a class="anchor" name="9f95118956319102de69927308a2defd"></a><!-- doxytag: member="dwc_otg_regs.h::gotgint_data_t" ref="9f95118956319102de69927308a2defd" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef union <a class="el" href="uniongotgint__data.html">gotgint_data</a>  <a class="el" href="uniongotgint__data.html">gotgint_data_t</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This union represents the bit fields of the Core OTG Interrupt Register (GOTGINT). 
+<p>
+Set/clear the bits using the bit fields then write the <em>d32</em> value to the register. 
+</div>
+</div><p>
+<a class="anchor" name="e1aca1c2d0abbb005545a17af3508291"></a><!-- doxytag: member="dwc_otg_regs.h::gahbcfg_data_t" ref="e1aca1c2d0abbb005545a17af3508291" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef union <a class="el" href="uniongahbcfg__data.html">gahbcfg_data</a>  <a class="el" href="uniongahbcfg__data.html">gahbcfg_data_t</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This union represents the bit fields of the Core AHB Configuration Register (GAHBCFG). 
+<p>
+Set/clear the bits using the bit fields then write the <em>d32</em> value to the register. 
+</div>
+</div><p>
+<a class="anchor" name="176748792c6f7aedc1aacf6740c2b1dd"></a><!-- doxytag: member="dwc_otg_regs.h::gusbcfg_data_t" ref="176748792c6f7aedc1aacf6740c2b1dd" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef union <a class="el" href="uniongusbcfg__data.html">gusbcfg_data</a>  <a class="el" href="uniongusbcfg__data.html">gusbcfg_data_t</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This union represents the bit fields of the Core USB Configuration Register (GUSBCFG). 
+<p>
+Set the bits using the bit fields then write the <em>d32</em> value to the register. 
+</div>
+</div><p>
+<a class="anchor" name="ba73e60dacc956a6090a82188bb8fcfa"></a><!-- doxytag: member="dwc_otg_regs.h::glpmcfg_data_t" ref="ba73e60dacc956a6090a82188bb8fcfa" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef union <a class="el" href="unionglpmctl__data.html">glpmctl_data</a>  <a class="el" href="unionglpmctl__data.html">glpmcfg_data_t</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This union represents the bit fields of the Core LPM Configuration Register (GLPMCFG). 
+<p>
+Set the bits using bit fields then write the <em>d32</em> value to the register. 
+</div>
+</div><p>
+<a class="anchor" name="ca690ce842cde2518004eefeedda7788"></a><!-- doxytag: member="dwc_otg_regs.h::grstctl_t" ref="ca690ce842cde2518004eefeedda7788" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef union <a class="el" href="uniongrstctl__data.html">grstctl_data</a>  <a class="el" href="uniongrstctl__data.html">grstctl_t</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This union represents the bit fields of the Core Reset Register (GRSTCTL). 
+<p>
+Set/clear the bits using the bit fields then write the <em>d32</em> value to the register. 
+</div>
+</div><p>
+<a class="anchor" name="db54cb8baf5c7d970347192ad40662d3"></a><!-- doxytag: member="dwc_otg_regs.h::gintmsk_data_t" ref="db54cb8baf5c7d970347192ad40662d3" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef union <a class="el" href="uniongintmsk__data.html">gintmsk_data</a>  <a class="el" href="uniongintmsk__data.html">gintmsk_data_t</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This union represents the bit fields of the Core Interrupt Mask Register (GINTMSK). 
+<p>
+Set/clear the bits using the bit fields then write the <em>d32</em> value to the register. 
+</div>
+</div><p>
+<a class="anchor" name="211ef100682c75981568527ed748dcfc"></a><!-- doxytag: member="dwc_otg_regs.h::gintsts_data_t" ref="211ef100682c75981568527ed748dcfc" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef union <a class="el" href="uniongintsts__data.html">gintsts_data</a>  <a class="el" href="uniongintsts__data.html">gintsts_data_t</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This union represents the bit fields of the Core Interrupt Register (GINTSTS). 
+<p>
+Set/clear the bits using the bit fields then write the <em>d32</em> value to the register. 
+</div>
+</div><p>
+<a class="anchor" name="389bbcdb2f9b7b284631c4e3c6c05ca4"></a><!-- doxytag: member="dwc_otg_regs.h::fifosize_data_t" ref="389bbcdb2f9b7b284631c4e3c6c05ca4" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef union <a class="el" href="unionfifosize__data.html">fifosize_data</a>  <a class="el" href="unionfifosize__data.html">fifosize_data_t</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ, GNPTXFSIZ, DPTXFSIZn, DIEPTXFn). 
+<p>
+Read the register into the <em>d32</em> element then read out the bits using the <em>b</em>it elements. 
+</div>
+</div><p>
+<a class="anchor" name="e00daff072291dd6e7af34701aad3138"></a><!-- doxytag: member="dwc_otg_regs.h::gnptxsts_data_t" ref="e00daff072291dd6e7af34701aad3138" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef union <a class="el" href="uniongnptxsts__data.html">gnptxsts_data</a>  <a class="el" href="uniongnptxsts__data.html">gnptxsts_data_t</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This union represents the bit fields in the Non-Periodic Transmit FIFO/Queue Status Register (GNPTXSTS). 
+<p>
+Read the register into the <em>d32</em> element then read out the bits using the <em>b</em>it elements. 
+</div>
+</div><p>
+<a class="anchor" name="d3e24afd53e919e2cb6d436506248f75"></a><!-- doxytag: member="dwc_otg_regs.h::dtxfsts_data_t" ref="d3e24afd53e919e2cb6d436506248f75" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef union <a class="el" href="uniondtxfsts__data.html">dtxfsts_data</a>  <a class="el" href="uniondtxfsts__data.html">dtxfsts_data_t</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This union represents the bit fields in the Transmit FIFO Status Register (DTXFSTS). 
+<p>
+Read the register into the <em>d32</em> element then read out the bits using the <em>b</em>it elements. 
+</div>
+</div><p>
+<a class="anchor" name="de10c5861b75d2f22b1a1b9e817a3098"></a><!-- doxytag: member="dwc_otg_regs.h::gi2cctl_data_t" ref="de10c5861b75d2f22b1a1b9e817a3098" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef union <a class="el" href="uniongi2cctl__data.html">gi2cctl_data</a>  <a class="el" href="uniongi2cctl__data.html">gi2cctl_data_t</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This union represents the bit fields in the I2C Control Register (I2CCTL). 
+<p>
+Read the register into the <em>d32</em> element then read out the bits using the <em>b</em>it elements. 
+</div>
+</div><p>
+<a class="anchor" name="e3fd2e458471dcd8fec9fa09ff787ad5"></a><!-- doxytag: member="dwc_otg_regs.h::hwcfg1_data_t" ref="e3fd2e458471dcd8fec9fa09ff787ad5" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef union <a class="el" href="unionhwcfg1__data.html">hwcfg1_data</a>  <a class="el" href="unionhwcfg1__data.html">hwcfg1_data_t</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This union represents the bit fields in the User HW Config1 Register. 
+<p>
+Read the register into the <em>d32</em> element then read out the bits using the <em>b</em>it elements. 
+</div>
+</div><p>
+<a class="anchor" name="a3044f8c36a47affba16a8abcebc2a33"></a><!-- doxytag: member="dwc_otg_regs.h::hwcfg2_data_t" ref="a3044f8c36a47affba16a8abcebc2a33" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef union <a class="el" href="unionhwcfg2__data.html">hwcfg2_data</a>  <a class="el" href="unionhwcfg2__data.html">hwcfg2_data_t</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This union represents the bit fields in the User HW Config2 Register. 
+<p>
+Read the register into the <em>d32</em> element then read out the bits using the <em>b</em>it elements. 
+</div>
+</div><p>
+<a class="anchor" name="cec01b13bc8d56e9001801bb14a98857"></a><!-- doxytag: member="dwc_otg_regs.h::hwcfg3_data_t" ref="cec01b13bc8d56e9001801bb14a98857" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef union <a class="el" href="unionhwcfg3__data.html">hwcfg3_data</a>  <a class="el" href="unionhwcfg3__data.html">hwcfg3_data_t</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This union represents the bit fields in the User HW Config3 Register. 
+<p>
+Read the register into the <em>d32</em> element then read out the bits using the <em>b</em>it elements. 
+</div>
+</div><p>
+<a class="anchor" name="d9159ac522a8a34be480e616a9df7ebe"></a><!-- doxytag: member="dwc_otg_regs.h::hwcfg4_data_t" ref="d9159ac522a8a34be480e616a9df7ebe" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef union <a class="el" href="unionhwcfg4__data.html">hwcfg4_data</a>  <a class="el" href="unionhwcfg4__data.html">hwcfg4_data_t</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This union represents the bit fields in the User HW Config4 Register. 
+<p>
+Read the register into the <em>d32</em> element then read out the bits using the <em>b</em>it elements. 
+</div>
+</div><p>
+<a class="anchor" name="c8e8458afafc8849b85f5b5fcf9b6d1b"></a><!-- doxytag: member="dwc_otg_regs.h::dwc_otg_device_global_regs_t" ref="c8e8458afafc8849b85f5b5fcf9b6d1b" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef struct <a class="el" href="structdwc__otg__dev__global__regs.html">dwc_otg_dev_global_regs</a>  <a class="el" href="structdwc__otg__dev__global__regs.html">dwc_otg_device_global_regs_t</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Device Global Registers. 
+<p>
+<em>Offsets 800h-BFFh</em><p>
+The following structures define the size and relative field offsets for the Device Mode Registers.<p>
+<em>These registers are visible only in Device mode and must not be accessed in Host mode, as the results are unknown.</em> 
+</div>
+</div><p>
+<a class="anchor" name="077228cd7e2acbd1e246bd9b0379c524"></a><!-- doxytag: member="dwc_otg_regs.h::dcfg_data_t" ref="077228cd7e2acbd1e246bd9b0379c524" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef union <a class="el" href="uniondcfg__data.html">dcfg_data</a>  <a class="el" href="uniondcfg__data.html">dcfg_data_t</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This union represents the bit fields in the Device Configuration Register. 
+<p>
+Read the register into the <em>d32</em> member then set/clear the bits using the <em>b</em>it elements. Write the <em>d32</em> member to the dcfg register. 
+</div>
+</div><p>
+<a class="anchor" name="043805708857633a05ae076cf8c0a143"></a><!-- doxytag: member="dwc_otg_regs.h::dctl_data_t" ref="043805708857633a05ae076cf8c0a143" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef union <a class="el" href="uniondctl__data.html">dctl_data</a>  <a class="el" href="uniondctl__data.html">dctl_data_t</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This union represents the bit fields in the Device Control Register. 
+<p>
+Read the register into the <em>d32</em> member then set/clear the bits using the <em>b</em>it elements. 
+</div>
+</div><p>
+<a class="anchor" name="2bd7f2043b7f4841e17b38edc406e06d"></a><!-- doxytag: member="dwc_otg_regs.h::dsts_data_t" ref="2bd7f2043b7f4841e17b38edc406e06d" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef union <a class="el" href="uniondsts__data.html">dsts_data</a>  <a class="el" href="uniondsts__data.html">dsts_data_t</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This union represents the bit fields in the Device Status Register. 
+<p>
+Read the register into the <em>d32</em> member then set/clear the bits using the <em>b</em>it elements. 
+</div>
+</div><p>
+<a class="anchor" name="0f4ab8ee4156c299665471b3a6f279ce"></a><!-- doxytag: member="dwc_otg_regs.h::diepint_data_t" ref="0f4ab8ee4156c299665471b3a6f279ce" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef union <a class="el" href="uniondiepint__data.html">diepint_data</a>  <a class="el" href="uniondiepint__data.html">diepint_data_t</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This union represents the bit fields in the Device IN EP Interrupt Register and the Device IN EP Common Mask Register. 
+<p>
+<ul>
+<li>Read the register into the <em>d32</em> member then set/clear the bits using the <em>b</em>it elements. </li></ul>
+
+</div>
+</div><p>
+<a class="anchor" name="692b7898b190ff12cca460bd0711db3f"></a><!-- doxytag: member="dwc_otg_regs.h::doepint_data_t" ref="692b7898b190ff12cca460bd0711db3f" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef union <a class="el" href="uniondoepint__data.html">doepint_data</a>  <a class="el" href="uniondoepint__data.html">doepint_data_t</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This union represents the bit fields in the Device OUT EP Interrupt Registerand Device OUT EP Common Interrupt Mask Register. 
+<p>
+<ul>
+<li>Read the register into the <em>d32</em> member then set/clear the bits using the <em>b</em>it elements. </li></ul>
+
+</div>
+</div><p>
+<a class="anchor" name="1effb8b11c6a62aacfcbea74c1be84f6"></a><!-- doxytag: member="dwc_otg_regs.h::daint_data_t" ref="1effb8b11c6a62aacfcbea74c1be84f6" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef union <a class="el" href="uniondaint__data.html">daint_data</a>  <a class="el" href="uniondaint__data.html">daint_data_t</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This union represents the bit fields in the Device All EP Interrupt and Mask Registers. 
+<p>
+<ul>
+<li>Read the register into the <em>d32</em> member then set/clear the bits using the <em>b</em>it elements. </li></ul>
+
+</div>
+</div><p>
+<a class="anchor" name="61e9acc9f9165e3fb6c15ce96db21861"></a><!-- doxytag: member="dwc_otg_regs.h::dtknq1_data_t" ref="61e9acc9f9165e3fb6c15ce96db21861" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef union <a class="el" href="uniondtknq1__data.html">dtknq1_data</a>  <a class="el" href="uniondtknq1__data.html">dtknq1_data_t</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This union represents the bit fields in the Device IN Token Queue Read Registers. 
+<p>
+<ul>
+<li>Read the register into the <em>d32</em> member.</li><li>READ-ONLY Register </li></ul>
+
+</div>
+</div><p>
+<a class="anchor" name="962414fc1e02940112ab0db4c53bcc6c"></a><!-- doxytag: member="dwc_otg_regs.h::dthrctl_data_t" ref="962414fc1e02940112ab0db4c53bcc6c" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef union <a class="el" href="uniondthrctl__data.html">dthrctl_data</a>  <a class="el" href="uniondthrctl__data.html">dthrctl_data_t</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This union represents Threshold control Register<ul>
+<li>Read and write the register into the <em>d32</em> member. </li></ul>
+
+<p>
+<ul>
+<li>READ-WRITABLE Register </li></ul>
+
+</div>
+</div><p>
+<a class="anchor" name="f23afc1a2db189b69772170cbd68b509"></a><!-- doxytag: member="dwc_otg_regs.h::dwc_otg_dev_in_ep_regs_t" ref="f23afc1a2db189b69772170cbd68b509" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef struct <a class="el" href="structdwc__otg__dev__in__ep__regs.html">dwc_otg_dev_in_ep_regs</a>  <a class="el" href="structdwc__otg__dev__in__ep__regs.html">dwc_otg_dev_in_ep_regs_t</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Device Logical IN Endpoint-Specific Registers. 
+<p>
+<em>Offsets 900h-AFCh</em><p>
+There will be one set of endpoint registers per logical endpoint implemented.<p>
+<em>These registers are visible only in Device mode and must not be accessed in Host mode, as the results are unknown.</em> 
+</div>
+</div><p>
+<a class="anchor" name="67ce4d713bb26f1244377b55aec8035a"></a><!-- doxytag: member="dwc_otg_regs.h::dwc_otg_dev_out_ep_regs_t" ref="67ce4d713bb26f1244377b55aec8035a" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef struct <a class="el" href="structdwc__otg__dev__out__ep__regs.html">dwc_otg_dev_out_ep_regs</a>  <a class="el" href="structdwc__otg__dev__out__ep__regs.html">dwc_otg_dev_out_ep_regs_t</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Device Logical OUT Endpoint-Specific Registers. 
+<p>
+<em>Offsets: B00h-CFCh</em><p>
+There will be one set of endpoint registers per logical endpoint implemented.<p>
+<em>These registers are visible only in Device mode and must not be accessed in Host mode, as the results are unknown.</em> 
+</div>
+</div><p>
+<a class="anchor" name="1d8ef2c3a67226833c01502c66bbd7a3"></a><!-- doxytag: member="dwc_otg_regs.h::depctl_data_t" ref="1d8ef2c3a67226833c01502c66bbd7a3" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef union <a class="el" href="uniondepctl__data.html">depctl_data</a>  <a class="el" href="uniondepctl__data.html">depctl_data_t</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This union represents the bit fields in the Device EP Control Register. 
+<p>
+Read the register into the <em>d32</em> member then set/clear the bits using the <em>b</em>it elements. 
+</div>
+</div><p>
+<a class="anchor" name="cb6f36bd93d869b9e61de914c8e2d222"></a><!-- doxytag: member="dwc_otg_regs.h::deptsiz_data_t" ref="cb6f36bd93d869b9e61de914c8e2d222" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef union <a class="el" href="uniondeptsiz__data.html">deptsiz_data</a>  <a class="el" href="uniondeptsiz__data.html">deptsiz_data_t</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This union represents the bit fields in the Device EP Transfer Size Register. 
+<p>
+Read the register into the <em>d32</em> member then set/clear the bits using the <em>b</em>it elements. 
+</div>
+</div><p>
+<a class="anchor" name="0c2941814d5219b96c19caac80d58a3e"></a><!-- doxytag: member="dwc_otg_regs.h::deptsiz0_data_t" ref="0c2941814d5219b96c19caac80d58a3e" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef union <a class="el" href="uniondeptsiz0__data.html">deptsiz0_data</a>  <a class="el" href="uniondeptsiz0__data.html">deptsiz0_data_t</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This union represents the bit fields in the Device EP 0 Transfer Size Register. 
+<p>
+Read the register into the <em>d32</em> member then set/clear the bits using the <em>b</em>it elements. 
+</div>
+</div><p>
+<a class="anchor" name="5363ac57fa4401cb81be60414d9104fe"></a><!-- doxytag: member="dwc_otg_regs.h::dev_dma_desc_sts_t" ref="5363ac57fa4401cb81be60414d9104fe" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef union <a class="el" href="uniondev__dma__desc__sts.html">dev_dma_desc_sts</a>  <a class="el" href="uniondev__dma__desc__sts.html">dev_dma_desc_sts_t</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This union represents the bit fields in the DMA Descriptor status quadlet. 
+<p>
+Read the quadlet into the <em>d32</em> member then set/clear the bits using the <em>b</em>it, <em>b_iso_out</em> and <em>b_iso_in</em> elements. 
+</div>
+</div><p>
+<a class="anchor" name="e10a2a455a645b5d69d3a078b82ffc75"></a><!-- doxytag: member="dwc_otg_regs.h::dwc_otg_dev_dma_desc_t" ref="e10a2a455a645b5d69d3a078b82ffc75" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef struct <a class="el" href="structdwc__otg__dev__dma__desc.html">dwc_otg_dev_dma_desc</a>  <a class="el" href="structdwc__otg__dev__dma__desc.html">dwc_otg_dev_dma_desc_t</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+DMA Descriptor structure. 
+<p>
+DMA Descriptor structure contains two quadlets: Status quadlet and Data buffer pointer. 
+</div>
+</div><p>
+<a class="anchor" name="9cc9d3e0d8697163a63c07db365a8d72"></a><!-- doxytag: member="dwc_otg_regs.h::dwc_otg_dev_if_t" ref="9cc9d3e0d8697163a63c07db365a8d72" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef struct <a class="el" href="structdwc__otg__dev__if.html">dwc_otg_dev_if</a>  <a class="el" href="structdwc__otg__dev__if.html">dwc_otg_dev_if_t</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+The <a class="el" href="structdwc__otg__dev__if.html">dwc_otg_dev_if</a> structure contains information needed to manage the DWC_otg controller acting in device mode. 
+<p>
+It represents the programming view of the device-specific aspects of the controller. 
+</div>
+</div><p>
+<a class="anchor" name="9e250e84dc7eefacc94a0d9d9fd198df"></a><!-- doxytag: member="dwc_otg_regs.h::dwc_otg_host_global_regs_t" ref="9e250e84dc7eefacc94a0d9d9fd198df" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef struct <a class="el" href="structdwc__otg__host__global__regs.html">dwc_otg_host_global_regs</a>  <a class="el" href="structdwc__otg__host__global__regs.html">dwc_otg_host_global_regs_t</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+The Host Global Registers structure defines the size and relative field offsets for the Host Mode Global Registers. 
+<p>
+Host Global Registers offsets 400h-7FFh. 
+</div>
+</div><p>
+<a class="anchor" name="26f6beffdddc3cbe5f7ec4f77824cca0"></a><!-- doxytag: member="dwc_otg_regs.h::hcfg_data_t" ref="26f6beffdddc3cbe5f7ec4f77824cca0" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef union <a class="el" href="unionhcfg__data.html">hcfg_data</a>  <a class="el" href="unionhcfg__data.html">hcfg_data_t</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This union represents the bit fields in the Host Configuration Register. 
+<p>
+Read the register into the <em>d32</em> member then set/clear the bits using the <em>b</em>it elements. Write the <em>d32</em> member to the hcfg register. 
+</div>
+</div><p>
+<a class="anchor" name="b6962581d4be622894de1b523256f4f9"></a><!-- doxytag: member="dwc_otg_regs.h::hprt0_data_t" ref="b6962581d4be622894de1b523256f4f9" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef union <a class="el" href="unionhprt0__data.html">hprt0_data</a>  <a class="el" href="unionhprt0__data.html">hprt0_data_t</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This union represents the bit fields in the Host Port Control and Status Register. 
+<p>
+Read the register into the <em>d32</em> member then set/clear the bits using the <em>b</em>it elements. Write the <em>d32</em> member to the hprt0 register. 
+</div>
+</div><p>
+<a class="anchor" name="c64589846d616caf2a82a41be5dc359b"></a><!-- doxytag: member="dwc_otg_regs.h::dwc_otg_hc_regs_t" ref="c64589846d616caf2a82a41be5dc359b" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef struct <a class="el" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs</a>  <a class="el" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Host Channel Specific Registers. 
+<p>
+<em>500h-5FCh</em> 
+</div>
+</div><p>
+<a class="anchor" name="e3bd36607e63cd3181c877f329a6eff8"></a><!-- doxytag: member="dwc_otg_regs.h::hcchar_data_t" ref="e3bd36607e63cd3181c877f329a6eff8" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef union <a class="el" href="unionhcchar__data.html">hcchar_data</a>  <a class="el" href="unionhcchar__data.html">hcchar_data_t</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This union represents the bit fields in the Host Channel Characteristics Register. 
+<p>
+Read the register into the <em>d32</em> member then set/clear the bits using the <em>b</em>it elements. Write the <em>d32</em> member to the hcchar register. 
+</div>
+</div><p>
+<a class="anchor" name="eeffbd23c7de44b01363bf196b4a6a44"></a><!-- doxytag: member="dwc_otg_regs.h::hcintmsk_data_t" ref="eeffbd23c7de44b01363bf196b4a6a44" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef union <a class="el" href="unionhcintmsk__data.html">hcintmsk_data</a>  <a class="el" href="unionhcintmsk__data.html">hcintmsk_data_t</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This union represents the bit fields in the Host Channel Interrupt Mask Register. 
+<p>
+Read the register into the <em>d32</em> member then set/clear the bits using the <em>b</em>it elements. Write the <em>d32</em> member to the hcintmsk register. 
+</div>
+</div><p>
+<a class="anchor" name="2f3d030c12693e0cf5876517856766b4"></a><!-- doxytag: member="dwc_otg_regs.h::hctsiz_data_t" ref="2f3d030c12693e0cf5876517856766b4" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef union <a class="el" href="unionhctsiz__data.html">hctsiz_data</a>  <a class="el" href="unionhctsiz__data.html">hctsiz_data_t</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This union represents the bit fields in the Host Channel Transfer Size Register. 
+<p>
+Read the register into the <em>d32</em> member then set/clear the bits using the <em>b</em>it elements. Write the <em>d32</em> member to the hcchar register. 
+</div>
+</div><p>
+<a class="anchor" name="fbefbebde0abe3db88477ab0831d865a"></a><!-- doxytag: member="dwc_otg_regs.h::host_dma_desc_sts_t" ref="fbefbebde0abe3db88477ab0831d865a" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef union <a class="el" href="unionhost__dma__desc__sts.html">host_dma_desc_sts</a>  <a class="el" href="unionhost__dma__desc__sts.html">host_dma_desc_sts_t</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This union represents the bit fields in the DMA Descriptor status quadlet for host mode. 
+<p>
+Read the quadlet into the <em>d32</em> member then set/clear the bits using the <em>b</em>it elements. 
+</div>
+</div><p>
+<a class="anchor" name="c4ddf8781cd4885c274d7964d3a32337"></a><!-- doxytag: member="dwc_otg_regs.h::dwc_otg_host_dma_desc_t" ref="c4ddf8781cd4885c274d7964d3a32337" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef struct <a class="el" href="structdwc__otg__host__dma__desc.html">dwc_otg_host_dma_desc</a>  <a class="el" href="structdwc__otg__host__dma__desc.html">dwc_otg_host_dma_desc_t</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Host-mode DMA Descriptor structure. 
+<p>
+DMA Descriptor structure contains two quadlets: Status quadlet and Data buffer pointer. 
+</div>
+</div><p>
+<a class="anchor" name="3fce2e3cb951b38f1c6fec40637392c2"></a><!-- doxytag: member="dwc_otg_regs.h::dwc_otg_host_if_t" ref="3fce2e3cb951b38f1c6fec40637392c2" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef struct <a class="el" href="structdwc__otg__host__if.html">dwc_otg_host_if</a>  <a class="el" href="structdwc__otg__host__if.html">dwc_otg_host_if_t</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+OTG Host Interface Structure. 
+<p>
+The OTG Host Interface Structure structure contains information needed to manage the DWC_otg controller acting in host mode. It represents the programming view of the host-specific aspects of the controller. 
+</div>
+</div><p>
+<a class="anchor" name="5efd1b5bf72987298cdf3d79bca37832"></a><!-- doxytag: member="dwc_otg_regs.h::pcgcctl_data_t" ref="5efd1b5bf72987298cdf3d79bca37832" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef union <a class="el" href="unionpcgcctl__data.html">pcgcctl_data</a>  <a class="el" href="unionpcgcctl__data.html">pcgcctl_data_t</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+This union represents the bit fields in the Power and Clock Gating Control Register. 
+<p>
+Read the register into the <em>d32</em> member then set/clear the bits using the <em>b</em>it elements. 
+</div>
+</div><p>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/files.html b/drivers/usb/host/dwc_otg/doc/html/files.html
new file mode 100644
index 000000000000..5784f074b8ae
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/files.html
@@ -0,0 +1,52 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: File Index</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li id="current"><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<h1>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver File List</h1>Here is a list of all documented files with brief descriptions:<table>
+  <tr><td class="indexkey"><b>dummy_audio.c</b> <a href="dummy__audio_8c-source.html">[code]</a></td><td class="indexvalue"></td></tr>
+  <tr><td class="indexkey"><a class="el" href="dwc__cfi__common_8h.html">dwc_cfi_common.h</a> <a href="dwc__cfi__common_8h-source.html">[code]</a></td><td class="indexvalue">This file contains the CFI specific common constants, interfaces (functions and macros) and structures for Linux </td></tr>
+  <tr><td class="indexkey"><a class="el" href="dwc__otg__attr_8c.html">dwc_otg_attr.c</a> <a href="dwc__otg__attr_8c-source.html">[code]</a></td><td class="indexvalue">The diagnostic interface will provide access to the controller for bringing up the hardware and testing </td></tr>
+  <tr><td class="indexkey"><a class="el" href="dwc__otg__attr_8h.html">dwc_otg_attr.h</a> <a href="dwc__otg__attr_8h-source.html">[code]</a></td><td class="indexvalue">This file contains the interface to the Linux device attributes </td></tr>
+  <tr><td class="indexkey"><a class="el" href="dwc__otg__cfi_8c.html">dwc_otg_cfi.c</a> <a href="dwc__otg__cfi_8c-source.html">[code]</a></td><td class="indexvalue">This file contains the most of the CFI implementation for the OTG </td></tr>
+  <tr><td class="indexkey"><a class="el" href="dwc__otg__cfi_8h.html">dwc_otg_cfi.h</a> <a href="dwc__otg__cfi_8h-source.html">[code]</a></td><td class="indexvalue">This file contains the CFI related OTG PCD specific common constants, interfaces (functions and macros) and data structures </td></tr>
+  <tr><td class="indexkey"><a class="el" href="dwc__otg__cil_8c.html">dwc_otg_cil.c</a> <a href="dwc__otg__cil_8c-source.html">[code]</a></td><td class="indexvalue">The Core Interface Layer provides basic services for accessing and managing the DWC_otg hardware </td></tr>
+  <tr><td class="indexkey"><a class="el" href="dwc__otg__cil_8h.html">dwc_otg_cil.h</a> <a href="dwc__otg__cil_8h-source.html">[code]</a></td><td class="indexvalue">This file contains the interface to the Core Interface Layer </td></tr>
+  <tr><td class="indexkey"><a class="el" href="dwc__otg__cil__intr_8c.html">dwc_otg_cil_intr.c</a> <a href="dwc__otg__cil__intr_8c-source.html">[code]</a></td><td class="indexvalue">The Core Interface Layer provides basic services for accessing and managing the DWC_otg hardware </td></tr>
+  <tr><td class="indexkey"><a class="el" href="dwc__otg__core__if_8h.html">dwc_otg_core_if.h</a> <a href="dwc__otg__core__if_8h-source.html">[code]</a></td><td class="indexvalue">This file defines DWC_OTG Core API </td></tr>
+  <tr><td class="indexkey"><a class="el" href="dwc__otg__dbg_8h.html">dwc_otg_dbg.h</a> <a href="dwc__otg__dbg_8h-source.html">[code]</a></td><td class="indexvalue">This file defines debug levels </td></tr>
+  <tr><td class="indexkey"><a class="el" href="dwc__otg__driver_8c.html">dwc_otg_driver.c</a> <a href="dwc__otg__driver_8c-source.html">[code]</a></td><td class="indexvalue">The dwc_otg_driver module provides the initialization and cleanup entry points for the DWC_otg driver </td></tr>
+  <tr><td class="indexkey"><a class="el" href="dwc__otg__driver_8h.html">dwc_otg_driver.h</a> <a href="dwc__otg__driver_8h-source.html">[code]</a></td><td class="indexvalue">This file contains the interface to the Linux driver </td></tr>
+  <tr><td class="indexkey"><a class="el" href="dwc__otg__hcd_8c.html">dwc_otg_hcd.c</a> <a href="dwc__otg__hcd_8c-source.html">[code]</a></td><td class="indexvalue">This file implements HCD Core </td></tr>
+  <tr><td class="indexkey"><a class="el" href="dwc__otg__hcd_8h.html">dwc_otg_hcd.h</a> <a href="dwc__otg__hcd_8h-source.html">[code]</a></td><td class="indexvalue">This file contains the structures, constants, and interfaces for the Host Contoller Driver (HCD) </td></tr>
+  <tr><td class="indexkey"><a class="el" href="dwc__otg__hcd__ddma_8c.html">dwc_otg_hcd_ddma.c</a> <a href="dwc__otg__hcd__ddma_8c-source.html">[code]</a></td><td class="indexvalue">This file contains Descriptor DMA support implementation for host mode </td></tr>
+  <tr><td class="indexkey"><a class="el" href="dwc__otg__hcd__if_8h.html">dwc_otg_hcd_if.h</a> <a href="dwc__otg__hcd__if_8h-source.html">[code]</a></td><td class="indexvalue">This file defines DWC_OTG HCD Core API </td></tr>
+  <tr><td class="indexkey"><a class="el" href="dwc__otg__hcd__intr_8c.html">dwc_otg_hcd_intr.c</a> <a href="dwc__otg__hcd__intr_8c-source.html">[code]</a></td><td class="indexvalue">This file contains the implementation of the HCD Interrupt handlers </td></tr>
+  <tr><td class="indexkey"><a class="el" href="dwc__otg__hcd__linux_8c.html">dwc_otg_hcd_linux.c</a> <a href="dwc__otg__hcd__linux_8c-source.html">[code]</a></td><td class="indexvalue">This file contains the implementation of the HCD </td></tr>
+  <tr><td class="indexkey"><a class="el" href="dwc__otg__hcd__queue_8c.html">dwc_otg_hcd_queue.c</a> <a href="dwc__otg__hcd__queue_8c-source.html">[code]</a></td><td class="indexvalue">This file contains the functions to manage Queue Heads and Queue Transfer Descriptors </td></tr>
+  <tr><td class="indexkey"><a class="el" href="dwc__otg__pcd_8c.html">dwc_otg_pcd.c</a> <a href="dwc__otg__pcd_8c-source.html">[code]</a></td><td class="indexvalue">This file implements PCD Core </td></tr>
+  <tr><td class="indexkey"><a class="el" href="dwc__otg__pcd_8h.html">dwc_otg_pcd.h</a> <a href="dwc__otg__pcd_8h-source.html">[code]</a></td><td class="indexvalue">This file contains the structures, constants, and interfaces for the Perpherial Contoller Driver (PCD) </td></tr>
+  <tr><td class="indexkey"><a class="el" href="dwc__otg__pcd__if_8h.html">dwc_otg_pcd_if.h</a> <a href="dwc__otg__pcd__if_8h-source.html">[code]</a></td><td class="indexvalue">This file defines DWC_OTG PCD Core API </td></tr>
+  <tr><td class="indexkey"><a class="el" href="dwc__otg__pcd__intr_8c.html">dwc_otg_pcd_intr.c</a> <a href="dwc__otg__pcd__intr_8c-source.html">[code]</a></td><td class="indexvalue">This file contains the implementation of the PCD Interrupt handlers </td></tr>
+  <tr><td class="indexkey"><a class="el" href="dwc__otg__pcd__linux_8c.html">dwc_otg_pcd_linux.c</a> <a href="dwc__otg__pcd__linux_8c-source.html">[code]</a></td><td class="indexvalue">This file implements the Peripheral Controller Driver </td></tr>
+  <tr><td class="indexkey"><a class="el" href="dwc__otg__regs_8h.html">dwc_otg_regs.h</a> <a href="dwc__otg__regs_8h-source.html">[code]</a></td><td class="indexvalue">This file contains the data structures for accessing the DWC_otg core registers </td></tr>
+</table>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/functions.html b/drivers/usb/host/dwc_otg/doc/html/functions.html
new file mode 100644
index 000000000000..bcabc5e7f1ae
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/functions.html
@@ -0,0 +1,82 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li id="current"><a href="functions.html"><span>All</span></a></li>
+    <li><a href="functions_func.html"><span>Functions</span></a></li>
+    <li><a href="functions_vars.html"><span>Variables</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li id="current"><a href="functions.html#index_a"><span>a</span></a></li>
+    <li><a href="functions_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="functions_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="functions_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="functions_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="functions_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="functions_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="functions_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="functions_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="functions_0x6c.html#index_l"><span>l</span></a></li>
+    <li><a href="functions_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="functions_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="functions_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="functions_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="functions_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="functions_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="functions_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="functions_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="functions_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="functions_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="functions_0x77.html#index_w"><span>w</span></a></li>
+    <li><a href="functions_0x78.html#index_x"><span>x</span></a></li>
+  </ul>
+</div>
+
+<p>
+Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:
+<p>
+<h3><a class="anchor" name="index_a">- a -</a></h3><ul>
+<li>a
+: <a class="el" href="unionhost__dma__desc__sts.html#1c4cf70718c94a1a847e52d4dd65cbb0">host_dma_desc_sts</a><li>a_alt_hnp_support
+: <a class="el" href="structdwc__otg__pcd.html#49f2d2b04a4c07a8d53643f7681b5405">dwc_otg_pcd</a><li>a_hnp_support
+: <a class="el" href="structdwc__otg__pcd.html#e8008719644bdc23040f1a1545b7117f">dwc_otg_pcd</a><li>a_qtd
+: <a class="el" href="unionhost__dma__desc__sts.html#c6ec29eb4bc0c9e165b3d09b951b4d13">host_dma_desc_sts</a><li>a_valid_filt_en
+: <a class="el" href="unionhwcfg4__data.html#109cd4df5b8b9035bf37aae2cbcbc15e">hwcfg4_data</a><li>ack
+: <a class="el" href="unionhcintmsk__data.html#8d3388818a6dc098a1e1c64147d1ced9">hcintmsk_data</a>, <a class="el" href="unionhcint__data.html#729749d6d0b5a1d4c449287f9efdd5fe">hcint_data</a>, <a class="el" href="uniongi2cctl__data.html#58c5fecd71f1bf68dc3e6939e5b56335">gi2cctl_data</a><li>active
+: <a class="el" href="structdwc__ep.html#63b7a1a3ee32df393ff10d8bfc5c8648">dwc_ep</a><li>active_eps
+: <a class="el" href="structcfiobject.html#82805f011abf3deace7faa159729229a">cfiobject</a><li>actual
+: <a class="el" href="structdwc__otg__pcd__request.html#0fd7d659f353273d8b2b22027306a2a2">dwc_otg_pcd_request</a><li>actual_length
+: <a class="el" href="structdwc__otg__hcd__urb.html#742c8a97d3867ab89148eae34e0c73a6">dwc_otg_hcd_urb</a>, <a class="el" href="structdwc__otg__hcd__iso__packet__desc.html#c00b967f4c613820b99efc0abda5178c">dwc_otg_hcd_iso_packet_desc</a><li>addr
+: <a class="el" href="uniongi2cctl__data.html#5641294f472040bc6c4f7e70e84500f0">gi2cctl_data</a>, <a class="el" href="structcfi__dma__buff.html#549d40f7e33056fc5a99d51d00714d97">cfi_dma_buff</a><li>adevtoutchng
+: <a class="el" href="uniongotgint__data.html#f216cb4939e1a348fbffaff87fc42772">gotgint_data</a><li>ahb_thr_ratio
+: <a class="el" href="uniondthrctl__data.html#00bbf39ee16616cc14410549c1e97c45">dthrctl_data</a>, <a class="el" href="structdwc__otg__driver__module__params.html#b450246efcbc087eb36b0979040162ca">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#8787af52f8d70a9100ab1fa2b0f69bfb">dwc_otg_core_params</a><li>ahberr
+: <a class="el" href="unionhcintmsk__data.html#bd9e228b6cb8e60cdbefd4bb57bdcc33">hcintmsk_data</a>, <a class="el" href="unionhcint__data.html#f953465ff02c518a52c48d4d6b1c09c7">hcint_data</a>, <a class="el" href="uniondoepint__data.html#cdfedbad6643d94271e91e135485a68d">doepint_data</a>, <a class="el" href="uniondiepint__data.html#6d57fa84f687bc4f05013c1e1a7edf29">diepint_data</a><li>ahbidle
+: <a class="el" href="uniongrstctl__data.html#587c5ec6713e2626db517105ab9aea3e">grstctl_data</a><li>align_buff
+: <a class="el" href="structdwc__hc.html#e0c3ba51a04b36656baa4e70fc63cf77">dwc_hc</a><li>appl_resp
+: <a class="el" href="unionglpmctl__data.html#1898203022af680f08036de89e86e4b0">glpmctl_data</a><li>architecture
+: <a class="el" href="unionhwcfg2__data.html#e5000f58c6a0f09c75375b4c912af0eb">hwcfg2_data</a><li>asesvld
+: <a class="el" href="uniongotgctl__data.html#e16505965a031d2e488a26378a14a834">gotgctl_data</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/functions_0x62.html b/drivers/usb/host/dwc_otg/doc/html/functions_0x62.html
new file mode 100644
index 000000000000..95f005631930
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/functions_0x62.html
@@ -0,0 +1,99 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li id="current"><a href="functions.html"><span>All</span></a></li>
+    <li><a href="functions_func.html"><span>Functions</span></a></li>
+    <li><a href="functions_vars.html"><span>Variables</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions.html#index_a"><span>a</span></a></li>
+    <li id="current"><a href="functions_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="functions_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="functions_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="functions_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="functions_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="functions_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="functions_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="functions_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="functions_0x6c.html#index_l"><span>l</span></a></li>
+    <li><a href="functions_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="functions_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="functions_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="functions_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="functions_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="functions_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="functions_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="functions_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="functions_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="functions_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="functions_0x77.html#index_w"><span>w</span></a></li>
+    <li><a href="functions_0x78.html#index_x"><span>x</span></a></li>
+  </ul>
+</div>
+
+<p>
+Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:
+<p>
+<h3><a class="anchor" name="index_b">- b -</a></h3><ul>
+<li>b
+: <a class="el" href="unionpcgcctl__data.html#f2bb76709d0ab9d08280eafb78a36279">pcgcctl_data</a>, <a class="el" href="unionhost__dma__desc__sts.html#a0e53895b927bfa9e322c3a3c0a08b3b">host_dma_desc_sts</a>, <a class="el" href="unionhcdma__data.html#61ea7b926fcef1d4fe1a6c8a1a1be41a">hcdma_data</a>, <a class="el" href="unionhctsiz__data.html#8967fa90c651bce44a3cbe90c44cf638">hctsiz_data</a>, <a class="el" href="unionhcintmsk__data.html#6835f55069c94947b580c8f01f64a075">hcintmsk_data</a>, <a class="el" href="unionhcint__data.html#3ab6af507f45d91a7898dd711f4368ee">hcint_data</a>, <a class="el" href="unionhcsplt__data.html#b8bafe40eee4a9f598659d254be836e1">hcsplt_data</a>, <a class="el" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">hcchar_data</a>, <a class="el" href="unionhaintmsk__data.html#03f75072e5548a4addea100a40e0ac89">haintmsk_data</a>, <a class="el" href="unionhaint__data.html#4ca1bd2581863c172fe667b226cfa2aa">haint_data</a>, <a class="el" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">hprt0_data</a>, <a class="el" href="unionhptxsts__data.html#a6839185cc4aeabf771f04f1b2a97ec3">hptxsts_data</a>, <a class="el" href="unionhfnum__data.html#81df6fbd20a454665803eb5790855c66">hfnum_data</a>, <a class="el" href="unionhfir__data.html#01ffc2aff6bf358564585c2ee7d513c8">hfir_data</a>, <a class="el" href="unionhcfg__data.html#45bbb24387d58961dd2b8f2f65689bd7">hcfg_data</a>, <a class="el" href="uniondev__dma__desc__sts.html#1876c32496f0067948f6282b7583aeab">dev_dma_desc_sts</a>, <a class="el" href="uniondeptsiz0__data.html#8e50594573fd774fc3e27404d8b1f59c">deptsiz0_data</a>, <a class="el" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">deptsiz_data</a>, <a class="el" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">depctl_data</a>, <a class="el" href="uniondthrctl__data.html#298be6991ca44e5e1ca558471789d33f">dthrctl_data</a>, <a class="el" href="uniondtknq1__data.html#fffe59f9a5f7cdf1ece03cf43caff69d">dtknq1_data</a>, <a class="el" href="uniondoepint__data.html#9e966d9f85589f278dc2c0d0c7833856">doepint_data</a>, <a class="el" href="uniondiepint__data.html#48d2a745e0ec983a47b35b0428b0437d">diepint_data</a>, <a class="el" href="uniondsts__data.html#4066fcedb7ac9a88e47aa1b2df0e89ee">dsts_data</a>, <a class="el" href="uniondctl__data.html#a3abfa6d609d9864f1f65712b409d4d3">dctl_data</a>, <a class="el" href="uniondcfg__data.html#242c1b463f445de3fc265e8c20fde50b">dcfg_data</a>, <a class="el" href="unionhwcfg4__data.html#9fb9175668e2381c568c5adbf6e5225d">hwcfg4_data</a>, <a class="el" href="unionhwcfg3__data.html#928c5de42f8af177ce34712123b5093c">hwcfg3_data</a>, <a class="el" href="unionhwcfg2__data.html#9dcc70e2dba617cbc6c12189be5c1d6a">hwcfg2_data</a>, <a class="el" href="unionhwcfg1__data.html#fc54d55ec3ffbba9312c1d0c7611f605">hwcfg1_data</a>, <a class="el" href="uniongi2cctl__data.html#5cd3b77fc770fc81b9cf9330cac214a8">gi2cctl_data</a>, <a class="el" href="uniondtxfsts__data.html#168f673549aad11d0d9fdc06ee6c5480">dtxfsts_data</a>, <a class="el" href="uniongnptxsts__data.html#be1d1adf7b827616ebbbf6bf564c0738">gnptxsts_data</a>, <a class="el" href="unionfifosize__data.html#4f0c71e88cc54c4efa4cd4ff43334c51">fifosize_data</a>, <a class="el" href="unionhost__grxsts__data.html#9d67ba193008dd6afa7fe613c665238d">host_grxsts_data</a>, <a class="el" href="uniondevice__grxsts__data.html#dbcda32a5bc5e5423bcf6e01d99c7686">device_grxsts_data</a>, <a class="el" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">gintsts_data</a>, <a class="el" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">gintmsk_data</a>, <a class="el" href="uniongrstctl__data.html#7907ac8831a2f72dec59592a093871e3">grstctl_data</a>, <a class="el" href="unionglpmctl__data.html#bd3cc34c338226ff1cd89448f7590ff1">glpmctl_data</a>, <a class="el" href="uniongusbcfg__data.html#1dab81bf7260b1e23f97298c34abea06">gusbcfg_data</a>, <a class="el" href="uniongahbcfg__data.html#aa9726048597c5bb54ea38eda976e1a4">gahbcfg_data</a>, <a class="el" href="uniongotgint__data.html#e48c5633608687c8895da201199c2a7c">gotgint_data</a>, <a class="el" href="uniongotgctl__data.html#212c81366266e906a188f4dbfadb6dd3">gotgctl_data</a><li>b_ddma
+: <a class="el" href="unionhctsiz__data.html#6cc80c630201f29e4a43e0cd7030786b">hctsiz_data</a><li>b_hnp_enable
+: <a class="el" href="structdwc__otg__pcd.html#e09fc5322ac0d7deec2772984c10ae90">dwc_otg_pcd</a><li>b_iso_in
+: <a class="el" href="uniondev__dma__desc__sts.html#324fdd57830243334b74e0579b4e9f96">dev_dma_desc_sts</a><li>b_iso_out
+: <a class="el" href="uniondev__dma__desc__sts.html#214ba099b6077c3393b179cf9a7909f7">dev_dma_desc_sts</a><li>b_valid_filt_en
+: <a class="el" href="unionhwcfg4__data.html#2f741788949e2fea24c129b1a4e10331">hwcfg4_data</a><li>babble
+: <a class="el" href="uniondoepint__data.html#c555371bda41092d89992523563dadbb">doepint_data</a><li>back2backsetup
+: <a class="el" href="uniondoepint__data.html#84e49d0a3324691b004bedc6af146747">doepint_data</a><li>bAlign
+: <a class="el" href="struct__ddma__align__buffer__setup.html#1cc0ba7e2c2a435cce1d502732ce07a1">_ddma_align_buffer_setup</a><li>base
+: <a class="el" href="structdwc__otg__device.html#ed96ed1109175f87fd83fa32a9c2c6fa">dwc_otg_device</a><li>bblerr
+: <a class="el" href="unionhcintmsk__data.html#5052c8737755083ee10105f36e839590">hcintmsk_data</a>, <a class="el" href="unionhcint__data.html#b05adf33c7be609a2daf54478f884ec4">hcint_data</a><li>bcnt
+: <a class="el" href="unionhost__grxsts__data.html#026fd4d8ab68825fab038c083b8e9c60">host_grxsts_data</a>, <a class="el" href="uniondevice__grxsts__data.html#6162a5f256d8041bc3d1d1071e999107">device_grxsts_data</a><li>bCount
+: <a class="el" href="struct__ddma__sg__buffer__setup.html#6287daf5a964bf1d09e8ffca29b88748">_ddma_sg_buffer_setup</a><li>bDescCount
+: <a class="el" href="struct__ddma__concat__buffer__setup__hdr.html#605becc1e8a681d6623343b28013b56a">_ddma_concat_buffer_setup_hdr</a><li>bEndpointAddress
+: <a class="el" href="struct__tx__fifo__size__setup.html#c04a19a9c0c93d385f7ea42ed38ba0a6">_tx_fifo_size_setup</a>, <a class="el" href="struct__ddma__align__buffer__setup.html#28008cbe6479b7473aa21ac2d3ceaf67">_ddma_align_buffer_setup</a>, <a class="el" href="struct__ddma__concat__buffer__setup__hdr.html#b6e4aab1ee8884a314ba38326ea85f24">_ddma_concat_buffer_setup_hdr</a><li>bInEndpointAddress
+: <a class="el" href="struct__ddma__sg__buffer__setup.html#bb435a2ac72bfd26384c9b5b1b0b35af">_ddma_sg_buffer_setup</a><li>bInterval
+: <a class="el" href="structdwc__ep.html#d9e9ffe348764ababc3165ed04f9ec6c">dwc_ep</a><li>bm_align
+: <a class="el" href="structcfi__ep.html#bb544b7938d0c62857fc3726988310d2">cfi_ep</a><li>bm_circ
+: <a class="el" href="structcfi__ep.html#3ab8ca6103c0483f2fefce0dc1684eaa">cfi_ep</a><li>bm_concat
+: <a class="el" href="structcfi__ep.html#4c83b9bb5a75e6b81fbfa86b51736164">cfi_ep</a><li>bm_sg
+: <a class="el" href="structcfi__ep.html#4010b0f12bf1cd37a2c0bf06b392570a">cfi_ep</a><li>bmAttributes
+: <a class="el" href="structcfi__feature__desc__header.html#556f5723d7ed0a9c6a1260b1f2a3fd30">cfi_feature_desc_header</a><li>bna
+: <a class="el" href="unionhcintmsk__data.html#dfbcaada980b7132f06667e0536b17da">hcintmsk_data</a>, <a class="el" href="unionhcint__data.html#759d3d0d98bd7efe69d46cc975b81845">hcint_data</a>, <a class="el" href="uniondoepint__data.html#e68e77d553158195b16a790012f9627d">doepint_data</a>, <a class="el" href="uniondiepint__data.html#2530c984ae3ebda73405d98080d8a57b">diepint_data</a><li>bNameLen
+: <a class="el" href="structcfi__feature__desc__header.html#4e90b7a616a2efc24937fc6d5cff1347">cfi_feature_desc_header</a><li>bOffset
+: <a class="el" href="struct__ddma__sg__buffer__setup.html#5ab16a208d20dd6940ecfd3244e2b9c0">_ddma_sg_buffer_setup</a><li>bOutEndpointAddress
+: <a class="el" href="struct__ddma__sg__buffer__setup.html#b61eaff3e4857fd6223d9fc678814786">_ddma_sg_buffer_setup</a><li>bRequest
+: <a class="el" href="structcfi__usb__ctrlrequest.html#b3083f525fa9bb97e41364418daee3fa">cfi_usb_ctrlrequest</a><li>bRequestType
+: <a class="el" href="structcfi__usb__ctrlrequest.html#6ba267845c2907b3908d3761c252b10c">cfi_usb_ctrlrequest</a><li>bs
+: <a class="el" href="uniondev__dma__desc__sts.html#05d1c1d8f6c5a1967c51c5d0e2e04261">dev_dma_desc_sts</a><li>bsesvld
+: <a class="el" href="uniongotgctl__data.html#69931c3759421d5eb6f91d4c9da4dddd">gotgctl_data</a><li>bsydne
+: <a class="el" href="uniongi2cctl__data.html#b28daedf73bcb4d651f8fbc03bb69778">gi2cctl_data</a><li>buf
+: <a class="el" href="structdwc__otg__host__dma__desc.html#fdc395094e1a1f9bb89c316a96d4b96b">dwc_otg_host_dma_desc</a>, <a class="el" href="structdwc__otg__dev__dma__desc.html#0454dad420ef536fe5eb7c38ef764430">dwc_otg_dev_dma_desc</a>, <a class="el" href="structdwc__otg__pcd__request.html#c46438f3d95146654a25cd219d7a1d5a">dwc_otg_pcd_request</a>, <a class="el" href="structdwc__otg__hcd__urb.html#99ae35ffcd6147ddb93b361ab3bcfe95">dwc_otg_hcd_urb</a>, <a class="el" href="structcfi__dma__buff.html#474851b3123373b8b30fa3637eb81b5b">cfi_dma_buff</a><li>buf_in
+: <a class="el" href="structcfiobject.html#f6548b2b8fbab90656c22eb5ca857643">cfiobject</a><li>buf_out
+: <a class="el" href="structcfiobject.html#adaa1cd0f88e639251f8dfbd65da7935">cfiobject</a><li>buf_proc_intrvl
+: <a class="el" href="structdwc__ep.html#4638b25387e59a5a4721a503b5279dfc">dwc_ep</a><li>bytes
+: <a class="el" href="uniondev__dma__desc__sts.html#9b6181d78984cb4d853945774f300ef0">dev_dma_desc_sts</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/functions_0x63.html b/drivers/usb/host/dwc_otg/doc/html/functions_0x63.html
new file mode 100644
index 000000000000..838fb7f2e579
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/functions_0x63.html
@@ -0,0 +1,110 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li id="current"><a href="functions.html"><span>All</span></a></li>
+    <li><a href="functions_func.html"><span>Functions</span></a></li>
+    <li><a href="functions_vars.html"><span>Variables</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions.html#index_a"><span>a</span></a></li>
+    <li><a href="functions_0x62.html#index_b"><span>b</span></a></li>
+    <li id="current"><a href="functions_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="functions_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="functions_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="functions_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="functions_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="functions_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="functions_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="functions_0x6c.html#index_l"><span>l</span></a></li>
+    <li><a href="functions_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="functions_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="functions_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="functions_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="functions_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="functions_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="functions_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="functions_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="functions_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="functions_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="functions_0x77.html#index_w"><span>w</span></a></li>
+    <li><a href="functions_0x78.html#index_x"><span>x</span></a></li>
+  </ul>
+</div>
+
+<p>
+Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:
+<p>
+<h3><a class="anchor" name="index_c">- c -</a></h3><ul>
+<li>cfi_setup
+: <a class="el" href="structdwc__otg__pcd__function__ops.html#e717e78fcf05e0de9c6d478fee1afa87">dwc_otg_pcd_function_ops</a><li>cgnpinnak
+: <a class="el" href="uniondctl__data.html#6feecf1184cd67b8b8ede2e2030a5dba">dctl_data</a><li>cgoutnak
+: <a class="el" href="uniondctl__data.html#7ffb7af3cfeb7efb811eb3c7fa7f3440">dctl_data</a><li>ch0
+: <a class="el" href="unionhaintmsk__data.html#dd096952e3d38ffa5db796e3a7334e7b">haintmsk_data</a>, <a class="el" href="unionhaint__data.html#4518de0451164b403fd446119606c798">haint_data</a><li>ch1
+: <a class="el" href="unionhaintmsk__data.html#c79960e27bba0c730936148272b14d3b">haintmsk_data</a>, <a class="el" href="unionhaint__data.html#111c951f2c033e42b8d341f968ccc387">haint_data</a><li>ch10
+: <a class="el" href="unionhaintmsk__data.html#e815617fd288b134798fa5e2dd23af67">haintmsk_data</a>, <a class="el" href="unionhaint__data.html#07c1c428e4e756aa65338659fc2f20d1">haint_data</a><li>ch11
+: <a class="el" href="unionhaintmsk__data.html#51e0430615e457c51a8f12f3c8c6246b">haintmsk_data</a>, <a class="el" href="unionhaint__data.html#5234dd8c3b0aa7d46154aa89f6fe2635">haint_data</a><li>ch12
+: <a class="el" href="unionhaintmsk__data.html#a7e151fe0676bde7a2ac43ee5b6f1b73">haintmsk_data</a>, <a class="el" href="unionhaint__data.html#43ab83f803054d0a5557471380186f8f">haint_data</a><li>ch13
+: <a class="el" href="unionhaintmsk__data.html#3ad05d0ef4e63250fc7b3af9f1654271">haintmsk_data</a>, <a class="el" href="unionhaint__data.html#7764f0ba6f46901a0c800dcc8c158643">haint_data</a><li>ch14
+: <a class="el" href="unionhaintmsk__data.html#3f0cf3851a6f6b74c33a71a3b255372b">haintmsk_data</a>, <a class="el" href="unionhaint__data.html#46a15c2faf17d049b71fcd46d1a58842">haint_data</a><li>ch15
+: <a class="el" href="unionhaintmsk__data.html#da69c5905fb9a16f50f9a0a8c0c9b125">haintmsk_data</a>, <a class="el" href="unionhaint__data.html#58435a2988a1d8a2dd11c64b8246bfcf">haint_data</a><li>ch2
+: <a class="el" href="unionhaintmsk__data.html#0ecac53d912d941c9139af6591f93261">haintmsk_data</a>, <a class="el" href="unionhaint__data.html#4f22391988e52ce0cf4c26114352d491">haint_data</a><li>ch3
+: <a class="el" href="unionhaintmsk__data.html#40feb12ac2af27dfb5772dcaec2c17c2">haintmsk_data</a>, <a class="el" href="unionhaint__data.html#595c465c0d89f2fc5b213436243f3301">haint_data</a><li>ch4
+: <a class="el" href="unionhaintmsk__data.html#5692699f367a57de45bab48856a35624">haintmsk_data</a>, <a class="el" href="unionhaint__data.html#daec53008bfef01a4eae6a287476be28">haint_data</a><li>ch5
+: <a class="el" href="unionhaintmsk__data.html#e49e1e6e4bea7ee8375c7e9da57d0217">haintmsk_data</a>, <a class="el" href="unionhaint__data.html#236e813b0d2c40105d98eabaaa83668a">haint_data</a><li>ch6
+: <a class="el" href="unionhaintmsk__data.html#df9d27f0be312e3c56cbd20736cb8e07">haintmsk_data</a>, <a class="el" href="unionhaint__data.html#4b32ecbff1ca92fb9a6ed7c85163b068">haint_data</a><li>ch7
+: <a class="el" href="unionhaintmsk__data.html#df61ec0f4ee97164b1a1aa1d8d0bd4b8">haintmsk_data</a>, <a class="el" href="unionhaint__data.html#858da0223b1c8c714704083fc3bb8716">haint_data</a><li>ch8
+: <a class="el" href="unionhaintmsk__data.html#1c05566d9af4c7401cc95ed613b62252">haintmsk_data</a>, <a class="el" href="unionhaint__data.html#a2b5aa5c0ad6f2ddd237f2fc4d5772f5">haint_data</a><li>ch9
+: <a class="el" href="unionhaintmsk__data.html#f12b0a59f2e663d15e9f69866c5bf701">haintmsk_data</a>, <a class="el" href="unionhaint__data.html#991c29e3cf0a85ef17178df828fd1474">haint_data</a><li>channel
+: <a class="el" href="structdwc__otg__qh.html#bbdb7d30b60b6c326301f33b35088bb4">dwc_otg_qh</a><li>chdis
+: <a class="el" href="unionhcchar__data.html#73c9f7f3cc4036c72ef341d1d1d9c388">hcchar_data</a><li>chen
+: <a class="el" href="unionhcchar__data.html#994a5305780edb0c4fe159b6cc7b14ae">hcchar_data</a><li>chhltd
+: <a class="el" href="unionhcintmsk__data.html#2549a84a06f4f6a7ad6fed50fcf7b068">hcintmsk_data</a>, <a class="el" href="unionhcint__data.html#b93ceab913a49e33c5bf4dde0e62d75a">hcint_data</a><li>chint
+: <a class="el" href="unionhaintmsk__data.html#80030e17495460223602afd3aad1287c">haintmsk_data</a>, <a class="el" href="unionhaint__data.html#6824b5b98c861cbc8efe3ba9f70cfea0">haint_data</a><li>chnum
+: <a class="el" href="unionhost__grxsts__data.html#684095394d11ec74a327f945c9e678bf">host_grxsts_data</a><li>cnak
+: <a class="el" href="uniondepctl__data.html#0b87d0914ceee7a20ffd2d7510b6a72e">depctl_data</a><li>common_irq_installed
+: <a class="el" href="structdwc__otg__device.html#80bfe5405d4146d3edca4e3eb2f9239b">dwc_otg_device</a><li>complete
+: <a class="el" href="structdwc__otg__pcd__function__ops.html#126db5e83cd3cc03f303eb3da668816f">dwc_otg_pcd_function_ops</a>, <a class="el" href="structdwc__otg__hcd__function__ops.html#09a989481103de7468cd46ef61ace0ce">dwc_otg_hcd_function_ops</a><li>complete_split
+: <a class="el" href="structdwc__otg__qtd.html#6355e968a4d36edce3e22c89ac7b5001">dwc_otg_qtd</a>, <a class="el" href="structdwc__hc.html#21e00df6fb9a555975879526118d599e">dwc_hc</a><li>compsplt
+: <a class="el" href="unionhcsplt__data.html#0a4855eb44ec93ec47dcc218a8703e94">hcsplt_data</a><li>config
+: <a class="el" href="structzero__dev.html#2481a8df9867ab54361cf4ffc7267484">zero_dev</a><li>conidsts
+: <a class="el" href="uniongotgctl__data.html#777151f3c8c1b3117493aee2cd7a2e5c">gotgctl_data</a><li>conidstschng
+: <a class="el" href="uniongintsts__data.html#86b8b53e53486db96a8faf6307c248df">gintsts_data</a>, <a class="el" href="uniongintmsk__data.html#ade723f4f136cfa884e5bf536d913f14">gintmsk_data</a><li>conn_timer
+: <a class="el" href="structdwc__otg__hcd.html#de7796a41bb7d1e45ed9dbc20c995342">dwc_otg_hcd</a><li>connect
+: <a class="el" href="structdwc__otg__pcd__function__ops.html#4d3df508947b8ba75c5537617227cf9c">dwc_otg_pcd_function_ops</a><li>control_phase
+: <a class="el" href="structdwc__otg__qtd.html#5189ec9c992974d20477481eaf96d0bb">dwc_otg_qtd</a><li>core_global_regs
+: <a class="el" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">dwc_otg_core_if</a><li>core_if
+: <a class="el" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">dwc_otg_pcd</a>, <a class="el" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">dwc_otg_hcd</a>, <a class="el" href="structdwc__otg__device.html#4cc7c9f6e473072c2ed0a5e6adb25ebe">dwc_otg_device</a><li>core_params
+: <a class="el" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">dwc_otg_core_if</a><li>csftrst
+: <a class="el" href="uniongrstctl__data.html#82df3462742f67d18b2964fafc0d9c02">grstctl_data</a><li>ctd
+: <a class="el" href="unionhcdma__data.html#d1238e3a2f81540362765b3e6a29d7de">hcdma_data</a><li>ctrl_req
+: <a class="el" href="structcfiobject.html#a86c33aef2a521a27ca515bb7397dd34">cfiobject</a><li>cur_pkt
+: <a class="el" href="structdwc__ep.html#d4e63c7d944c2b48260b4a75c2b58925">dwc_ep</a><li>cur_pkt_addr
+: <a class="el" href="structdwc__ep.html#d3bc23598a77d3cca52c70a28afc6b5e">dwc_ep</a><li>cur_pkt_dma_addr
+: <a class="el" href="structdwc__ep.html#ed4594c9f6c2bcbcf6f1bbe9e9c64061">dwc_ep</a><li>curmode
+: <a class="el" href="uniongintsts__data.html#f0815c8bea0a37c98b12a08481b2980c">gintsts_data</a><li>currmod
+: <a class="el" href="uniongotgctl__data.html#540a9022e5ff38c2a656b8ebd59070cb">gotgctl_data</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/functions_0x64.html b/drivers/usb/host/dwc_otg/doc/html/functions_0x64.html
new file mode 100644
index 000000000000..7d5406535b42
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/functions_0x64.html
@@ -0,0 +1,158 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li id="current"><a href="functions.html"><span>All</span></a></li>
+    <li><a href="functions_func.html"><span>Functions</span></a></li>
+    <li><a href="functions_vars.html"><span>Variables</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions.html#index_a"><span>a</span></a></li>
+    <li><a href="functions_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="functions_0x63.html#index_c"><span>c</span></a></li>
+    <li id="current"><a href="functions_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="functions_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="functions_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="functions_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="functions_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="functions_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="functions_0x6c.html#index_l"><span>l</span></a></li>
+    <li><a href="functions_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="functions_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="functions_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="functions_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="functions_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="functions_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="functions_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="functions_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="functions_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="functions_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="functions_0x77.html#index_w"><span>w</span></a></li>
+    <li><a href="functions_0x78.html#index_x"><span>x</span></a></li>
+  </ul>
+</div>
+
+<p>
+Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:
+<p>
+<h3><a class="anchor" name="index_d">- d -</a></h3><ul>
+<li>d32
+: <a class="el" href="unionpcgcctl__data.html#abe048ee884143501929b27d94c52db7">pcgcctl_data</a>, <a class="el" href="unionhost__dma__desc__sts.html#c8e191345883c19b7127e54479c75e4d">host_dma_desc_sts</a>, <a class="el" href="unionhcdma__data.html#27b804015f09ea7eb25f602cc6dbdda9">hcdma_data</a>, <a class="el" href="unionhctsiz__data.html#fb41950555c60c6015294bdefe9cd39d">hctsiz_data</a>, <a class="el" href="unionhcintmsk__data.html#8868299fcc762e005b7f0bf67e5fbe30">hcintmsk_data</a>, <a class="el" href="unionhcint__data.html#05a82fa7693f875622db744716d7f73e">hcint_data</a>, <a class="el" href="unionhcsplt__data.html#0cd235b445ff681b846f5dccf24fd644">hcsplt_data</a>, <a class="el" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">hcchar_data</a>, <a class="el" href="unionhaintmsk__data.html#65f3e5dbc7a62b6fb57426abaaffc6a2">haintmsk_data</a>, <a class="el" href="unionhaint__data.html#c83834650d2981b44274a89dda63a0f5">haint_data</a>, <a class="el" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">hprt0_data</a>, <a class="el" href="unionhptxsts__data.html#b48d41d449d8f71c0b184b38029c26bc">hptxsts_data</a>, <a class="el" href="unionhfnum__data.html#e5ccbed3af86ac88577ded328e6c9932">hfnum_data</a>, <a class="el" href="unionhfir__data.html#859d5325dbf422643fb86695328c206d">hfir_data</a>, <a class="el" href="unionhcfg__data.html#381a253b3a38a7f943dcbb42f7bf10be">hcfg_data</a>, <a class="el" href="uniondev__dma__desc__sts.html#fb77b9c4ab63304073542ed2b118a64b">dev_dma_desc_sts</a>, <a class="el" href="uniondeptsiz0__data.html#a06fa9b1dcaee47fba9cf869027ed6f1">deptsiz0_data</a>, <a class="el" href="uniondeptsiz__data.html#10c2b2ba8b419b0a766430a59befbbe0">deptsiz_data</a>, <a class="el" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">depctl_data</a>, <a class="el" href="uniondthrctl__data.html#f66c52fe9278bb6ed52c811ddbed16a5">dthrctl_data</a>, <a class="el" href="uniondtknq1__data.html#86015789f75da8cd507db3766fe93fef">dtknq1_data</a>, <a class="el" href="uniondaint__data.html#cf05e79bf751384bef904448a231bc41">daint_data</a>, <a class="el" href="uniondoepint__data.html#94f8c8fc116b430565f9322e3621b3a5">doepint_data</a>, <a class="el" href="uniondiepint__data.html#7d2c24507663bf96c280c57fbf544ef7">diepint_data</a>, <a class="el" href="uniondsts__data.html#0f126daef735b142b06dbc4cdbe13814">dsts_data</a>, <a class="el" href="uniondctl__data.html#f49aadfd7ad95b570115b3c245b1729e">dctl_data</a>, <a class="el" href="uniondcfg__data.html#efd84d3306db1b4370535a0e814612dc">dcfg_data</a>, <a class="el" href="unionhwcfg4__data.html#edcdf66b3add0e05ce0006b0b0de8dd0">hwcfg4_data</a>, <a class="el" href="unionhwcfg3__data.html#9daf160f3fc0cc8e4e68c037f6c2f9d7">hwcfg3_data</a>, <a class="el" href="unionhwcfg2__data.html#2a2482b24bbfa8cdd589e376184d1e3b">hwcfg2_data</a>, <a class="el" href="unionhwcfg1__data.html#9ca836052f9bd01e0b70902862ed09a4">hwcfg1_data</a>, <a class="el" href="uniongi2cctl__data.html#97e9ae4e52d9bd9370027b5da5f65787">gi2cctl_data</a>, <a class="el" href="uniondtxfsts__data.html#684b8a9ccf83a5807e9bb3491c662c39">dtxfsts_data</a>, <a class="el" href="uniongnptxsts__data.html#a58b5adbe6bd0344c4f585ef6aba4672">gnptxsts_data</a>, <a class="el" href="unionfifosize__data.html#937e01b91f0a60a5aa9f6a4eaf6ce661">fifosize_data</a>, <a class="el" href="unionhost__grxsts__data.html#993969735da9c3615652391aae76359a">host_grxsts_data</a>, <a class="el" href="uniondevice__grxsts__data.html#9d454f39c05e23d376dfb0069d933986">device_grxsts_data</a>, <a class="el" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">gintsts_data</a>, <a class="el" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">gintmsk_data</a>, <a class="el" href="uniongrstctl__data.html#d89d99c95bd5177fbd879d38963d3e62">grstctl_data</a>, <a class="el" href="unionglpmctl__data.html#cd41461734ff898209bfb64057ef2eb8">glpmctl_data</a>, <a class="el" href="uniongusbcfg__data.html#c3d8f2d95fd61a172eb108cb72a85b47">gusbcfg_data</a>, <a class="el" href="uniongahbcfg__data.html#2532b75f838946009af8806c924f0c08">gahbcfg_data</a>, <a class="el" href="uniongotgint__data.html#8a343df4fc4e68b802be7629864308e2">gotgint_data</a>, <a class="el" href="uniongotgctl__data.html#ebb591ab40ff41f0e06f03a795647d33">gotgctl_data</a>, <a class="el" href="structdwc__otg__pcd.html#e4fe210f7a18b9f0c393af9cdf282d56">dwc_otg_pcd</a>, <a class="el" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#95ad2033c30d79c28ffcfa6df44af1d5">dwc_otg_hcd::dwc_otg_hcd_internal_flags</a><li>daint
+: <a class="el" href="structdwc__otg__dev__global__regs.html#2e25df2fbec9d398742709524056cbd5">dwc_otg_dev_global_regs</a><li>daintmsk
+: <a class="el" href="structdwc__otg__dev__global__regs.html#5def6c3850c041928b9a662422ee0679">dwc_otg_dev_global_regs</a><li>data
+: <a class="el" href="structcfi__usb__ctrlrequest.html#5b3865e9cb2c0fcf373b1c862a63c180">cfi_usb_ctrlrequest</a><li>data_fifo
+: <a class="el" href="structdwc__otg__core__if.html#f99c868784a8269073bc251f88d92ee4">dwc_otg_core_if</a><li>data_fifo_size
+: <a class="el" href="structdwc__otg__driver__module__params.html#a9ae5039d88c52fab455235bf4f8696b">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#3d8dc206f54165f52c7f8599731d0f95">dwc_otg_core_params</a><li>data_pattern_frame
+: <a class="el" href="structdwc__ep.html#c505483882bd67a7b0076851f693f2cc">dwc_ep</a><li>data_per_frame
+: <a class="el" href="structdwc__ep.html#4672369f4724db642856d72d5048213e">dwc_ep</a><li>data_pid_start
+: <a class="el" href="structdwc__hc.html#513427c5e8c4603ba344d4e7f9191064">dwc_hc</a>, <a class="el" href="structdwc__ep.html#4ceafa9e067ba462ab38c20ffcf8d597">dwc_ep</a><li>data_toggle
+: <a class="el" href="structdwc__otg__qh.html#b0e001bfd76f5781926795ac47ef2c25">dwc_otg_qh</a>, <a class="el" href="structdwc__otg__qtd.html#e912f256e01165b573c26262247a5eff">dwc_otg_qtd</a><li>datatglerr
+: <a class="el" href="unionhcintmsk__data.html#60bbf3878314aad41055137e348cc01d">hcintmsk_data</a>, <a class="el" href="unionhcint__data.html#2fc8618d16e6908e99c8cca3ffb54736">hcint_data</a><li>dcfg
+: <a class="el" href="structdwc__otg__dev__global__regs.html#c0c24937bbd7184884f05343f56ef1da">dwc_otg_dev_global_regs</a>, <a class="el" href="structdwc__otg__core__if.html#fcce854acc5b4afca80bd5667ecc4ef2">dwc_otg_core_if</a><li>dctl
+: <a class="el" href="structdwc__otg__dev__global__regs.html#3779c2fc508920a831a59e696a8fa785">dwc_otg_dev_global_regs</a><li>ddrsel
+: <a class="el" href="uniongusbcfg__data.html#e6dc05942f880adfaee600bc9e0ba33b">gusbcfg_data</a><li>deachint
+: <a class="el" href="structdwc__otg__dev__global__regs.html#4795bc8eab569241a3f8e6aad5d99ac7">dwc_otg_dev_global_regs</a><li>deachintmsk
+: <a class="el" href="structdwc__otg__dev__global__regs.html#e64a153683f0e0cda14b56a163651825">dwc_otg_dev_global_regs</a><li>debdone
+: <a class="el" href="uniongotgint__data.html#7bac6821d07d401731213dc0e94852ca">gotgint_data</a><li>ded_fifo_en
+: <a class="el" href="unionhwcfg4__data.html#175e8897d6e3c8ef4026413943de503b">hwcfg4_data</a><li>deep_sleep
+: <a class="el" href="unionpcgcctl__data.html#07232b66695a6bcba4c89477ef13130f">pcgcctl_data</a><li>depth
+: <a class="el" href="unionfifosize__data.html#48c08d73da4d2d16d4320b93beb5ba8b">fifosize_data</a><li>desc
+: <a class="el" href="structdwc__otg__pcd__ep.html#86e27843c439dd0b1d12d9bf2dc6516f">dwc_otg_pcd_ep</a><li>desc_addr
+: <a class="el" href="structdwc__ep.html#57e934b26e76939912eaa76321075a0d">dwc_ep</a><li>desc_cnt
+: <a class="el" href="structdwc__ep.html#5e5bfcc93d41670bc0d29ad5f0f35871">dwc_ep</a><li>desc_count
+: <a class="el" href="structcfi__ep.html#73050a3011b918e8be6c2434db357514">cfi_ep</a><li>desc_dma
+: <a class="el" href="unionhwcfg4__data.html#988888a48e9088d0e9f889818eb63509">hwcfg4_data</a><li>desc_dma_dyn
+: <a class="el" href="unionhwcfg4__data.html#9562305cf5dd89816939792a66879542">hwcfg4_data</a><li>desc_list
+: <a class="el" href="structdwc__otg__qh.html#0e5f35688e54ba97054a1a7576e81150">dwc_otg_qh</a><li>desc_list_addr
+: <a class="el" href="structdwc__hc.html#f3001addf65df4d3c6a5c685d7637efd">dwc_hc</a><li>desc_list_dma
+: <a class="el" href="structdwc__otg__qh.html#c31412bb35362e77c697352fd4c3eeaf">dwc_otg_qh</a><li>descdma
+: <a class="el" href="unionhcfg__data.html#7ec04d77b1c0d3cc25165e77e9bce5f4">hcfg_data</a>, <a class="el" href="uniondcfg__data.html#d83666dcf5675453a387915ce1653d54">dcfg_data</a><li>dev_addr
+: <a class="el" href="structdwc__otg__hcd__pipe__info.html#3812ead0191c9b3bebf48fe8ea370d78">dwc_otg_hcd_pipe_info</a>, <a class="el" href="structdwc__hc.html#b2c7e8baff70104375f4916e9b76cef7">dwc_hc</a><li>dev_endpoints
+: <a class="el" href="structdwc__otg__driver__module__params.html#c1c36daec6af25fb425c85a696c445e4">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#17d0dda7fe2cd51726cd1dd34c57b94a">dwc_otg_core_params</a><li>dev_global_regs
+: <a class="el" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dwc_otg_dev_if</a><li>dev_if
+: <a class="el" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dwc_otg_core_if</a><li>dev_nperio_tx_fifo_size
+: <a class="el" href="structdwc__otg__driver__module__params.html#3172175dc8f08e96b63c7a8c162201f5">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#d08d9aee1fb4e6508089415d6150176e">dwc_otg_core_params</a><li>dev_perio_tx_fifo_size
+: <a class="el" href="structdwc__otg__driver__module__params.html#aada52f0668d5d52b8ac6281c8736283">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#2958d325289f4a77b6435cda729e5f6e">dwc_otg_core_params</a><li>dev_rx_fifo_size
+: <a class="el" href="structdwc__otg__driver__module__params.html#707eedd2d7794728c5188e5d5056316e">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#24ea6f9329f64ac0ad2d31dafe0d1d8c">dwc_otg_core_params</a><li>dev_speed
+: <a class="el" href="structdwc__otg__qh.html#42459dd91e199807783000b6dc358a7d">dwc_otg_qh</a><li>dev_token_q_depth
+: <a class="el" href="unionhwcfg2__data.html#ba242467585b60b4d3db9882e0f39b3f">hwcfg2_data</a><li>dev_tx_fifo_size
+: <a class="el" href="structdwc__otg__driver__module__params.html#d1c3fbc5325b13e1191388b76795b848">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#6e0c5d06467fbf3458f11f7eb8153a8b">dwc_otg_core_params</a><li>devaddr
+: <a class="el" href="unionhcchar__data.html#19326a679cb3507cf294d229834252a1">hcchar_data</a>, <a class="el" href="uniondcfg__data.html#71c70afb48dd124d12e43d86edd90f1e">dcfg_data</a><li>devhnpen
+: <a class="el" href="uniongotgctl__data.html#0058cbee8b53336c28746116301ea796">gotgctl_data</a><li>devspd
+: <a class="el" href="uniondcfg__data.html#28ffb9fb43686fe553fbe80f1ead62a4">dcfg_data</a><li>dfifo_depth
+: <a class="el" href="unionhwcfg3__data.html#f885715ddb953dbe95acc08e49264706">hwcfg3_data</a><li>diepctl
+: <a class="el" href="structdwc__otg__dev__in__ep__regs.html#53a5adb977e2aec66d4902c6ba293216">dwc_otg_dev_in_ep_regs</a><li>diepdma
+: <a class="el" href="structdwc__otg__dev__in__ep__regs.html#5f013840a15e0a310b8722646880a420">dwc_otg_dev_in_ep_regs</a><li>diepdmab
+: <a class="el" href="structdwc__otg__dev__in__ep__regs.html#aa24ec8b19877c7f2f20802afc6f9cef">dwc_otg_dev_in_ep_regs</a><li>diepeachintmsk
+: <a class="el" href="structdwc__otg__dev__global__regs.html#aaf2a5c6be4130d558c291f6aaeeca4f">dwc_otg_dev_global_regs</a><li>diepint
+: <a class="el" href="structdwc__otg__dev__in__ep__regs.html#4d6d6309ef5e09ad9048655ced6a2769">dwc_otg_dev_in_ep_regs</a><li>diepmsk
+: <a class="el" href="structdwc__otg__dev__global__regs.html#02e44cb182548d78c5b7d27929ca5f11">dwc_otg_dev_global_regs</a><li>dieptsiz
+: <a class="el" href="structdwc__otg__dev__in__ep__regs.html#88f637b5a4e8a0c6bc87d157072255dd">dwc_otg_dev_in_ep_regs</a><li>disabling
+: <a class="el" href="structdwc__otg__pcd__ep.html#510fcd32761716abec5a35594a3d3ad3">dwc_otg_pcd_ep</a><li>disconnect
+: <a class="el" href="uniongintsts__data.html#45d8d681263dcfc7c2b6cf30ee689f28">gintsts_data</a>, <a class="el" href="uniongintmsk__data.html#0ff313bfc712a2f3d71bc1a5f1a17ce2">gintmsk_data</a>, <a class="el" href="structdwc__otg__pcd__function__ops.html#51b0e7dcf19398bad4f0ec459b43077a">dwc_otg_pcd_function_ops</a>, <a class="el" href="structdwc__otg__hcd__function__ops.html#fb7650d10a745991479af978fb519651">dwc_otg_hcd_function_ops</a>, <a class="el" href="structdwc__otg__cil__callbacks.html#1a8ccad34a04f3e8b085aa5720bbcc70">dwc_otg_cil_callbacks</a><li>dma
+: <a class="el" href="structdwc__otg__pcd__ep.html#314db0fbde1d5eb9eae0cbe4fdef47a4">dwc_otg_pcd_ep</a>, <a class="el" href="structdwc__otg__pcd__request.html#df93c8905495816eb0327b192938a4a1">dwc_otg_pcd_request</a>, <a class="el" href="structdwc__otg__hcd__urb.html#4e177a55239e95ae2f6c8b6b913f67fc">dwc_otg_hcd_urb</a><li>dma_addr
+: <a class="el" href="unionhcdma__data.html#8324b2ba8d18c5ecb1cbcb23874393db">hcdma_data</a>, <a class="el" href="structdwc__ep.html#b40ce70422b6d105a855a8df4b33d45d">dwc_ep</a><li>dma_addr0
+: <a class="el" href="structdwc__ep.html#553936d1d003413d00a24330274887f9">dwc_ep</a><li>dma_addr1
+: <a class="el" href="structdwc__ep.html#02dc1be77d505b19f14651fe9805c97f">dwc_ep</a><li>dma_burst_size
+: <a class="el" href="structdwc__otg__driver__module__params.html#19c1567261677aa53120cfae53b90f8d">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#f9d2a8cd9b36d24de89121d19f693ccb">dwc_otg_core_params</a><li>dma_desc_addr
+: <a class="el" href="structdwc__ep.html#1a43e464429530e874472092e0e1af09">dwc_ep</a><li>dma_desc_enable
+: <a class="el" href="structdwc__otg__driver__module__params.html#cdceee2a19bb233c12893751f443c40d">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dwc_otg_core_if</a>, <a class="el" href="structdwc__otg__core__params.html#36c5bcf00d0f776b5c9e84e5d8ae408d">dwc_otg_core_params</a><li>dma_desc_last
+: <a class="el" href="structcfi__ep.html#3f4e5c42f279663ee0065ffce4f44783">cfi_ep</a><li>dma_enable
+: <a class="el" href="structdwc__otg__driver__module__params.html#fe4469605ca0460a3e309603d7c23e86">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dwc_otg_core_if</a>, <a class="el" href="structdwc__otg__core__params.html#3c791cb4898379d156acc47c5b9a84fc">dwc_otg_core_params</a><li>dma_in_desc_addr
+: <a class="el" href="structdwc__otg__dev__if.html#ba2f5eede8b3deaaec8882baeea6a35b">dwc_otg_dev_if</a><li>dma_out_desc_addr
+: <a class="el" href="structdwc__otg__dev__if.html#3829a415bbaf0f5c3e29b1a9f3cf546b">dwc_otg_dev_if</a><li>dma_setup_desc_addr
+: <a class="el" href="structdwc__otg__dev__if.html#fb3d3353afd5f9d08a8e49c48158cfb7">dwc_otg_dev_if</a><li>dmaenable
+: <a class="el" href="uniongahbcfg__data.html#f39c07c45326af38a267b0e308496b5c">gahbcfg_data</a><li>dmareq
+: <a class="el" href="uniongrstctl__data.html#13e11d4c86ca39b8edf3c1878708fad1">grstctl_data</a><li>do_ping
+: <a class="el" href="structdwc__hc.html#ae7184275dbb23b3a5d2af20ed224920">dwc_hc</a><li>do_split
+: <a class="el" href="structdwc__otg__qh.html#8708dd009988ce20b8a8d52a4a96c5a3">dwc_otg_qh</a>, <a class="el" href="structdwc__hc.html#4365ef67d517a621a626ac5392545c6d">dwc_hc</a><li>doepctl
+: <a class="el" href="structdwc__otg__dev__out__ep__regs.html#2a522b71fc97658c07debf3521f7d3e5">dwc_otg_dev_out_ep_regs</a><li>doepdma
+: <a class="el" href="structdwc__otg__dev__out__ep__regs.html#006071bf54bfa1c1f5e25cf4c9f65cb1">dwc_otg_dev_out_ep_regs</a><li>doepdmab
+: <a class="el" href="structdwc__otg__dev__out__ep__regs.html#baff3c1aea7aed57a42fa0015f15e0fa">dwc_otg_dev_out_ep_regs</a><li>doepeachintmsk
+: <a class="el" href="structdwc__otg__dev__global__regs.html#304e089ed2d36d9076228b8d7e1cc515">dwc_otg_dev_global_regs</a><li>doepfn
+: <a class="el" href="structdwc__otg__dev__out__ep__regs.html#f23e8e9750d99b1c4b5ac0c674e8733e">dwc_otg_dev_out_ep_regs</a><li>doepint
+: <a class="el" href="structdwc__otg__dev__out__ep__regs.html#81d837c801dcfa30f17b567419a86f62">dwc_otg_dev_out_ep_regs</a><li>doepmsk
+: <a class="el" href="structdwc__otg__dev__global__regs.html#d6947be9d84a1d87156f81a10ebb036b">dwc_otg_dev_global_regs</a><li>doeptsiz
+: <a class="el" href="structdwc__otg__dev__out__ep__regs.html#e756ec48787099f0a4e2ce353fce4f91">dwc_otg_dev_out_ep_regs</a><li>dopng
+: <a class="el" href="unionhctsiz__data.html#68625ebdd11afc0a026f41c94aedc161">hctsiz_data</a><li>dpid
+: <a class="el" href="uniondepctl__data.html#ea2f031d4f4dd0580caa5707d50dd0c1">depctl_data</a>, <a class="el" href="unionhost__grxsts__data.html#5c4ca6a6c4a85064dd024095607a634d">host_grxsts_data</a>, <a class="el" href="uniondevice__grxsts__data.html#d0f4716b612b04fde649a2f689ea5b88">device_grxsts_data</a><li>dptxfsiz_dieptxf
+: <a class="el" href="structdwc__otg__core__global__regs.html#efd9e780825f992dbc6cf46d2d72869e">dwc_otg_core_global_regs</a><li>driver
+: <a class="el" href="structgadget__wrapper.html#8997a3c90f9eb0a8f40f5762ffc5ce60">gadget_wrapper</a><li>dsts
+: <a class="el" href="structdwc__otg__dev__global__regs.html#1ed00edd20ce5db7d07666804101ec05">dwc_otg_dev_global_regs</a><li>dtknqr1
+: <a class="el" href="structdwc__otg__dev__global__regs.html#b130a76736e0e81d5a020651109352de">dwc_otg_dev_global_regs</a><li>dtknqr2
+: <a class="el" href="structdwc__otg__dev__global__regs.html#27968db886161264e7820bcf4a746e5d">dwc_otg_dev_global_regs</a><li>dtknqr3_dthrctl
+: <a class="el" href="structdwc__otg__dev__global__regs.html#c263c55a0bb752f8939731aa2f8f6cb8">dwc_otg_dev_global_regs</a><li>dtknqr4_fifoemptymsk
+: <a class="el" href="structdwc__otg__dev__global__regs.html#fbc2b776c2150842813e4681dd43bedc">dwc_otg_dev_global_regs</a><li>dtxfsts
+: <a class="el" href="structdwc__otg__dev__in__ep__regs.html#90db7d3ed2dd087e0a55a1465deb21c9">dwc_otg_dev_in_ep_regs</a><li>dvbusdis
+: <a class="el" href="structdwc__otg__dev__global__regs.html#95088e182c3ff164d1b331bb196eb95d">dwc_otg_dev_global_regs</a><li>dvbuspulse
+: <a class="el" href="structdwc__otg__dev__global__regs.html#8747dbe01b5a4cbd2c980bf39fdb4737">dwc_otg_dev_global_regs</a><li>dw_align_buf
+: <a class="el" href="structdwc__otg__qh.html#aac9f90a6afd9056dce79d013dd2168b">dwc_otg_qh</a><li>dw_align_buf_dma
+: <a class="el" href="structdwc__otg__qh.html#b0b008f9d25f5e3b6e285d2830cfdca1">dwc_otg_qh</a><li>DWC_CIRCLEQ_ENTRY()
+: <a class="el" href="structdwc__otg__qtd.html#aac18e92835ac0678a83d023660f1560">dwc_otg_qtd</a>, <a class="el" href="structdwc__hc.html#bf81e1a0c0ae06faf445a61b950e24f5">dwc_hc</a><li>dwc_ep
+: <a class="el" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_otg_pcd_ep</a><li>dwc_otg_hcd
+: <a class="el" href="structwrapper__priv__data.html#3a5cfdab2772597d857294972bb171c8">wrapper_priv_data</a><li>dynamic_fifo
+: <a class="el" href="unionhwcfg2__data.html#b6bfbfe650352dec82a02d15677fe88d">hwcfg2_data</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/functions_0x65.html b/drivers/usb/host/dwc_otg/doc/html/functions_0x65.html
new file mode 100644
index 000000000000..3016a51c9d86
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/functions_0x65.html
@@ -0,0 +1,109 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li id="current"><a href="functions.html"><span>All</span></a></li>
+    <li><a href="functions_func.html"><span>Functions</span></a></li>
+    <li><a href="functions_vars.html"><span>Variables</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions.html#index_a"><span>a</span></a></li>
+    <li><a href="functions_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="functions_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="functions_0x64.html#index_d"><span>d</span></a></li>
+    <li id="current"><a href="functions_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="functions_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="functions_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="functions_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="functions_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="functions_0x6c.html#index_l"><span>l</span></a></li>
+    <li><a href="functions_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="functions_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="functions_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="functions_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="functions_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="functions_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="functions_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="functions_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="functions_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="functions_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="functions_0x77.html#index_w"><span>w</span></a></li>
+    <li><a href="functions_0x78.html#index_x"><span>x</span></a></li>
+  </ul>
+</div>
+
+<p>
+Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:
+<p>
+<h3><a class="anchor" name="index_e">- e -</a></h3><ul>
+<li>emptyintr
+: <a class="el" href="uniondiepint__data.html#de84fb009990e97bfa46f825d5358429">diepint_data</a><li>en_multiple_tx_fifo
+: <a class="el" href="structdwc__otg__driver__module__params.html#13860bb2c8d23e40088703289e6ae835">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__if.html#31d08d1ebcd290b05139b0fcd24048ec">dwc_otg_core_if</a>, <a class="el" href="structdwc__otg__core__params.html#d61279dcea66973b2915e335efb07fe3">dwc_otg_core_params</a><li>en_utmi_sleep
+: <a class="el" href="unionglpmctl__data.html#63e912a05b8d29872b92263ca616fec8">glpmctl_data</a><li>enable_dynamic_fifo
+: <a class="el" href="structdwc__otg__driver__module__params.html#f448f6de6dcafca027bd2873b714b916">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#8c169633d4a6f28e964cef9f597c6e03">dwc_otg_core_params</a><li>enbl_sleep_gating
+: <a class="el" href="unionpcgcctl__data.html#6c18ad3b71ad92e548d0c6d64cc88734">pcgcctl_data</a><li>enumdone
+: <a class="el" href="uniongintsts__data.html#84e707787b50ee3867786c8e0995f41e">gintsts_data</a>, <a class="el" href="uniongintmsk__data.html#895f1c1537debec62da4fd248249859c">gintmsk_data</a><li>enumspd
+: <a class="el" href="uniondsts__data.html#f918f3d04b026687af3e1953f5c79fea">dsts_data</a><li>eol
+: <a class="el" href="unionhost__dma__desc__sts.html#58d670cd305219a32f144a6705e649e3">host_dma_desc_sts</a><li>eopframe
+: <a class="el" href="uniongintsts__data.html#a731c93eb9e131fadde92da363a85527">gintsts_data</a>, <a class="el" href="uniongintmsk__data.html#aeb61a24f3c50caacfb8fe523c85768a">gintmsk_data</a><li>ep
+: <a class="el" href="uniondaint__data.html#5d048f0d5695317b05317d3c5ec4f79d">daint_data</a>, <a class="el" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">cfi_ep</a><li>ep0
+: <a class="el" href="structgadget__wrapper.html#8f28c6610592157ecef50de726919162">gadget_wrapper</a>, <a class="el" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">dwc_otg_pcd</a><li>ep0_pending
+: <a class="el" href="structdwc__otg__pcd.html#2c8be11c3b9c7cd02684348eb028aeb5">dwc_otg_pcd</a><li>ep0state
+: <a class="el" href="structdwc__otg__pcd.html#8f6963b3fb9ab83048c4c0697c90382a">dwc_otg_pcd</a><li>ep_dir0
+: <a class="el" href="unionhwcfg1__data.html#b58699c49f54de158d6edc4e57716668">hwcfg1_data</a><li>ep_dir1
+: <a class="el" href="unionhwcfg1__data.html#a62adc1641ef86ed0967061fe0480197">hwcfg1_data</a><li>ep_dir10
+: <a class="el" href="unionhwcfg1__data.html#1dba400b1d532a89de3f2c4410e9ab4d">hwcfg1_data</a><li>ep_dir11
+: <a class="el" href="unionhwcfg1__data.html#c5b95969c9c9ffd9f641f7a495e90621">hwcfg1_data</a><li>ep_dir12
+: <a class="el" href="unionhwcfg1__data.html#a88f6d54f42966f47e77dddd015f5aad">hwcfg1_data</a><li>ep_dir13
+: <a class="el" href="unionhwcfg1__data.html#708fa9af8f43442846ed4a122cbf5610">hwcfg1_data</a><li>ep_dir14
+: <a class="el" href="unionhwcfg1__data.html#c930e82427e44ae78db85730665ed2a8">hwcfg1_data</a><li>ep_dir15
+: <a class="el" href="unionhwcfg1__data.html#cb596169ca88921f58ab84d0a38a4cc8">hwcfg1_data</a><li>ep_dir2
+: <a class="el" href="unionhwcfg1__data.html#03607d2fd2913d3bd20035bc66105e77">hwcfg1_data</a><li>ep_dir3
+: <a class="el" href="unionhwcfg1__data.html#9beabdd8094db63c0359a7ef22f2266d">hwcfg1_data</a><li>ep_dir4
+: <a class="el" href="unionhwcfg1__data.html#393899c7a69f9c36ab1b0ef15ab58568">hwcfg1_data</a><li>ep_dir5
+: <a class="el" href="unionhwcfg1__data.html#ef4cd3ba5b57ad791d1dfc237fcb7b2b">hwcfg1_data</a><li>ep_dir6
+: <a class="el" href="unionhwcfg1__data.html#1521515b71e5bb03b1102fb3333c1bbc">hwcfg1_data</a><li>ep_dir7
+: <a class="el" href="unionhwcfg1__data.html#ddc5b4c31dc56456bdca5660d4608f28">hwcfg1_data</a><li>ep_dir8
+: <a class="el" href="unionhwcfg1__data.html#a0d189caec30660152f1fd3abd1176f2">hwcfg1_data</a><li>ep_dir9
+: <a class="el" href="unionhwcfg1__data.html#0c21e8d57df291e8d3b2dbb67c52956e">hwcfg1_data</a><li>ep_is_in
+: <a class="el" href="structdwc__otg__qh.html#2dc622878a6617e5c803061804d5cf9f">dwc_otg_qh</a>, <a class="el" href="structdwc__hc.html#c5088d431f5efc382121f201f5d571aa">dwc_hc</a><li>ep_num
+: <a class="el" href="structdwc__otg__hcd__pipe__info.html#57b54466daa38c3a77f48e94c5e30f0d">dwc_otg_hcd_pipe_info</a>, <a class="el" href="structdwc__hc.html#70b755f76a00b81679aeb1e0db8b2e60">dwc_hc</a><li>ep_type
+: <a class="el" href="structdwc__otg__qh.html#98b78ffd8dbc01be44b302e873e73a82">dwc_otg_qh</a>, <a class="el" href="structdwc__hc.html#e6169fbc92e4d79686097742ad646f5c">dwc_hc</a><li>epdir
+: <a class="el" href="unionhcchar__data.html#11f1b16e50f90806f90953bb979d4e77">hcchar_data</a><li>epdis
+: <a class="el" href="uniondepctl__data.html#4d76ba4ebd506d3175ec5cdc0d811654">depctl_data</a><li>epdisabled
+: <a class="el" href="uniondoepint__data.html#8a263ddc3ab9080b8c2e02ccead0c983">doepint_data</a>, <a class="el" href="uniondiepint__data.html#3a649b75195fb5b26135d75b03cf561d">diepint_data</a><li>epena
+: <a class="el" href="uniondepctl__data.html#337ceb41a9e0735e144e684b1f9e5368">depctl_data</a><li>epmismatch
+: <a class="el" href="uniongintsts__data.html#c30e01457b826afc318e5d76e9dfdded">gintsts_data</a>, <a class="el" href="uniongintmsk__data.html#3a21d0006e144647b43ef910b9183da9">gintmsk_data</a><li>epmscnt
+: <a class="el" href="uniondcfg__data.html#9292b8ce264ebdb8a26c28883443a4df">dcfg_data</a><li>epnum
+: <a class="el" href="unionhcchar__data.html#1597f36b85006e643aaf6f4d503bebc9">hcchar_data</a>, <a class="el" href="uniondevice__grxsts__data.html#d91e207bb8fb6e20652e6ad2474aec8e">device_grxsts_data</a><li>epnums0_5
+: <a class="el" href="uniondtknq1__data.html#b35b4b7cfebfe54904ac0d74bb771825">dtknq1_data</a><li>eptype
+: <a class="el" href="unionhcchar__data.html#df4deee52d932ab29e5d077cde77cbfc">hcchar_data</a>, <a class="el" href="uniondepctl__data.html#f119782e7db731a3d4bf6c500b4ba5d2">depctl_data</a><li>erlysuspend
+: <a class="el" href="uniongintsts__data.html#2659c4ea7b295a089ee498b21b44992b">gintsts_data</a>, <a class="el" href="uniongintmsk__data.html#0c455b6461081720584a8acc4e0e18a5">gintmsk_data</a><li>error_count
+: <a class="el" href="structdwc__otg__qtd.html#18eeb9c647049aec468bf9a7861c873f">dwc_otg_qtd</a>, <a class="el" href="structdwc__otg__hcd__urb.html#58c7018042c94c436637ea80354e7e28">dwc_otg_hcd_urb</a><li>error_state
+: <a class="el" href="structdwc__hc.html#ab0855754930fdc74978fa71772982ed">dwc_hc</a><li>errticerr
+: <a class="el" href="uniondsts__data.html#fc57a31e440fcf11b233c8c208df83be">dsts_data</a><li>even_odd_frame
+: <a class="el" href="structdwc__ep.html#0692ad9970f4ff48b4210577a6bf86ee">dwc_ep</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/functions_0x66.html b/drivers/usb/host/dwc_otg/doc/html/functions_0x66.html
new file mode 100644
index 000000000000..3db0e3f1e7a3
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/functions_0x66.html
@@ -0,0 +1,81 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li id="current"><a href="functions.html"><span>All</span></a></li>
+    <li><a href="functions_func.html"><span>Functions</span></a></li>
+    <li><a href="functions_vars.html"><span>Variables</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions.html#index_a"><span>a</span></a></li>
+    <li><a href="functions_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="functions_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="functions_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="functions_0x65.html#index_e"><span>e</span></a></li>
+    <li id="current"><a href="functions_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="functions_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="functions_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="functions_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="functions_0x6c.html#index_l"><span>l</span></a></li>
+    <li><a href="functions_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="functions_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="functions_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="functions_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="functions_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="functions_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="functions_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="functions_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="functions_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="functions_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="functions_0x77.html#index_w"><span>w</span></a></li>
+    <li><a href="functions_0x78.html#index_x"><span>x</span></a></li>
+  </ul>
+</div>
+
+<p>
+Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:
+<p>
+<h3><a class="anchor" name="index_f">- f -</a></h3><ul>
+<li>flags
+: <a class="el" href="structdwc__otg__hcd.html#9aaf2a112f5794f92dedd826342bd637">dwc_otg_hcd</a>, <a class="el" href="structdwc__otg__hcd__urb.html#2f1d90765496d78d297b3e57ef4d781c">dwc_otg_hcd_urb</a><li>fn
+: <a class="el" href="uniondevice__grxsts__data.html#f535ee62a482ec97ca61dc4954e358c6">device_grxsts_data</a><li>fops
+: <a class="el" href="structdwc__otg__pcd.html#b7001dde5db2706707a860da0030d9e6">dwc_otg_pcd</a>, <a class="el" href="structdwc__otg__hcd.html#ffefbd33a59a14b8b46406f5aaeaa2f4">dwc_otg_hcd</a><li>frame_list
+: <a class="el" href="structdwc__otg__hcd.html#77f16d5530f50556ed01fe7f69a135fd">dwc_otg_hcd</a><li>frame_list_dma
+: <a class="el" href="structdwc__otg__hcd.html#3421063dcac9d4e200b5d9bbb0508f3d">dwc_otg_hcd</a><li>frame_number
+: <a class="el" href="structdwc__otg__hcd.html#f79fefeb7908c0ddf702331253acb292">dwc_otg_hcd</a><li>framenum
+: <a class="el" href="uniondev__dma__desc__sts.html#d9da3eccc6d247e2b5eccd4dfba7874e">dev_dma_desc_sts</a><li>free_hc_list
+: <a class="el" href="structdwc__otg__hcd.html#1761f2e6b8f6ba82c0e0c4e561813f0f">dwc_otg_hcd</a><li>frint
+: <a class="el" href="unionhfir__data.html#5302611bdf96e87f3a7f30319212bcc2">hfir_data</a><li>frlisten
+: <a class="el" href="unionhcfg__data.html#11340031265fce764f491b23ae42dda5">hcfg_data</a><li>frm_list_roll
+: <a class="el" href="unionhcintmsk__data.html#da781977131daa2db51fee16900366ae">hcintmsk_data</a>, <a class="el" href="unionhcint__data.html#26f48c3ec302ac2e009be71733e068b7">hcint_data</a><li>frmovrun
+: <a class="el" href="unionhcintmsk__data.html#2ba9f8dc5e946b28ac4169f75364e182">hcintmsk_data</a>, <a class="el" href="unionhcint__data.html#06f911d323d71f86639550507322dffb">hcint_data</a><li>frnum
+: <a class="el" href="unionhfnum__data.html#a64e8b6c4a1cd262dbc30e158f3cb8bc">hfnum_data</a><li>frrem
+: <a class="el" href="unionhfnum__data.html#2a2ce50ebd4c4da5347a2d93c4bbc996">hfnum_data</a><li>fs_phy_type
+: <a class="el" href="unionhwcfg2__data.html#e75417d7e2d1843abf6e48f67851326e">hwcfg2_data</a><li>fsintf
+: <a class="el" href="uniongusbcfg__data.html#8f23ebcf05c1bc48b4e406e98d828f78">gusbcfg_data</a><li>fslspclksel
+: <a class="el" href="unionhcfg__data.html#e048ad3775c6794c3ee07af86079fadf">hcfg_data</a><li>fslssupp
+: <a class="el" href="unionhcfg__data.html#c047f55e398b8a94aef27a66ed78f2de">hcfg_data</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/functions_0x67.html b/drivers/usb/host/dwc_otg/doc/html/functions_0x67.html
new file mode 100644
index 000000000000..adaebb4ea63b
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/functions_0x67.html
@@ -0,0 +1,95 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li id="current"><a href="functions.html"><span>All</span></a></li>
+    <li><a href="functions_func.html"><span>Functions</span></a></li>
+    <li><a href="functions_vars.html"><span>Variables</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions.html#index_a"><span>a</span></a></li>
+    <li><a href="functions_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="functions_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="functions_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="functions_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="functions_0x66.html#index_f"><span>f</span></a></li>
+    <li id="current"><a href="functions_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="functions_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="functions_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="functions_0x6c.html#index_l"><span>l</span></a></li>
+    <li><a href="functions_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="functions_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="functions_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="functions_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="functions_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="functions_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="functions_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="functions_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="functions_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="functions_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="functions_0x77.html#index_w"><span>w</span></a></li>
+    <li><a href="functions_0x78.html#index_x"><span>x</span></a></li>
+  </ul>
+</div>
+
+<p>
+Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:
+<p>
+<h3><a class="anchor" name="index_g">- g -</a></h3><ul>
+<li>gadget
+: <a class="el" href="structgadget__wrapper.html#a1f30b68c6b42bc728c45c329312d7b1">gadget_wrapper</a>, <a class="el" href="structcfiobject.html#fcb2ec62bedb38bb1e6a596ac778d4e6">cfiobject</a>, <a class="el" href="structzero__dev.html#e0d019d6177afd1efa101aed63f1a174">zero_dev</a><li>gahbcfg
+: <a class="el" href="structdwc__otg__core__global__regs.html#537c95e57269fabf29c6b36ad8e1ed45">dwc_otg_core_global_regs</a><li>gatehclk
+: <a class="el" href="unionpcgcctl__data.html#a3ee36c0e5ea8ae5ac38829337120327">pcgcctl_data</a><li>gcontbna
+: <a class="el" href="uniondctl__data.html#212c36aaab3763a6de5cca56999c0263">dctl_data</a><li>get_b_hnp_enable
+: <a class="el" href="structdwc__otg__hcd__function__ops.html#24a2ee2bad4dc517fed62417a2a542d3">dwc_otg_hcd_function_ops</a><li>ggpio
+: <a class="el" href="structdwc__otg__core__global__regs.html#694546400c443d41b449772c8573f3e8">dwc_otg_core_global_regs</a><li>ghwcfg1
+: <a class="el" href="structdwc__otg__core__global__regs.html#56d2988ff8fedbbde479ffe8d4e84b75">dwc_otg_core_global_regs</a><li>ghwcfg2
+: <a class="el" href="structdwc__otg__core__global__regs.html#b0f241f53ca7b3be1c94bd684ed61f79">dwc_otg_core_global_regs</a><li>ghwcfg3
+: <a class="el" href="structdwc__otg__core__global__regs.html#57ddcc14f581f5d6276122f9747aff72">dwc_otg_core_global_regs</a><li>ghwcfg4
+: <a class="el" href="structdwc__otg__core__global__regs.html#e1df73c776d3b31d5f0a501ccdeb1d2d">dwc_otg_core_global_regs</a><li>gi2cctl
+: <a class="el" href="structdwc__otg__core__global__regs.html#8ecf68262dbcdb6901f3011cfe35a144">dwc_otg_core_global_regs</a><li>ginnakeff
+: <a class="el" href="uniongintsts__data.html#15a2e362768704ab6143fea33fc8755b">gintsts_data</a>, <a class="el" href="uniongintmsk__data.html#83a6fb180ef8b18faf8d02ba8b50c841">gintmsk_data</a><li>gintmsk
+: <a class="el" href="structdwc__otg__core__global__regs.html#48827c76da2c6b18f369e2f2483cc4b6">dwc_otg_core_global_regs</a><li>gintsts
+: <a class="el" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">dwc_otg_core_global_regs</a><li>glblintrmsk
+: <a class="el" href="uniongahbcfg__data.html#f75957f35be7ecd70616f5d0bcfb1e51">gahbcfg_data</a><li>glpmcfg
+: <a class="el" href="structdwc__otg__core__global__regs.html#843cfb38ba366a9a46ad07ed11eb8396">dwc_otg_core_global_regs</a><li>gmc
+: <a class="el" href="uniondctl__data.html#6ceae1404558a4ffec4dab1c4702c7c8">dctl_data</a><li>gnpinnaksts
+: <a class="el" href="uniondctl__data.html#26ba184e018a813e96527822f9e26fde">dctl_data</a><li>gnptxfsiz
+: <a class="el" href="structdwc__otg__core__global__regs.html#20fb70fe34a1a65d085b1d4e5f8d9106">dwc_otg_core_global_regs</a><li>gnptxsts
+: <a class="el" href="structdwc__otg__core__global__regs.html#57dabea6f6e0bf9e1ee8e94f55b9e465">dwc_otg_core_global_regs</a><li>gotgctl
+: <a class="el" href="structdwc__otg__core__global__regs.html#54034d00bb6b47ada4e0c0baa87cbd8a">dwc_otg_core_global_regs</a><li>gotgint
+: <a class="el" href="structdwc__otg__core__global__regs.html#69cc290cfdfe6900890f7a5a16b3137c">dwc_otg_core_global_regs</a><li>goutnakeff
+: <a class="el" href="uniongintsts__data.html#5fd87ed0462f444df968567f310488f7">gintsts_data</a>, <a class="el" href="uniongintmsk__data.html#1a47902a93203910433a35fab3f5b8a1">gintmsk_data</a><li>goutnaksts
+: <a class="el" href="uniondctl__data.html#995d969d60e86b2ea662eb831c882b44">dctl_data</a><li>gpvndctl
+: <a class="el" href="structdwc__otg__core__global__regs.html#a12db668367caef8386d2ba20289e437">dwc_otg_core_global_regs</a><li>grstctl
+: <a class="el" href="structdwc__otg__core__global__regs.html#49d307957dbe53f20aa8f7a5409ee8ad">dwc_otg_core_global_regs</a><li>grxfsiz
+: <a class="el" href="structdwc__otg__core__global__regs.html#b1a8cc07a9541c9a73e864579602b79b">dwc_otg_core_global_regs</a><li>grxstsp
+: <a class="el" href="structdwc__otg__core__global__regs.html#763b05035799e1c16d34957fb62a2d17">dwc_otg_core_global_regs</a><li>grxstsr
+: <a class="el" href="structdwc__otg__core__global__regs.html#5e688c41f25ba8081f34cb1b2b052dbc">dwc_otg_core_global_regs</a><li>gsnpsid
+: <a class="el" href="structdwc__otg__core__global__regs.html#30798436df220217c3960ac4a46710dc">dwc_otg_core_global_regs</a><li>guid
+: <a class="el" href="structdwc__otg__core__global__regs.html#8735ca2e93c1e984ac2d5bcf0cda96d7">dwc_otg_core_global_regs</a><li>gusbcfg
+: <a class="el" href="structdwc__otg__core__global__regs.html#ef39e181e246447df47c56aa4e37cc42">dwc_otg_core_global_regs</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/functions_0x68.html b/drivers/usb/host/dwc_otg/doc/html/functions_0x68.html
new file mode 100644
index 000000000000..7e37e6b4e72a
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/functions_0x68.html
@@ -0,0 +1,119 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li id="current"><a href="functions.html"><span>All</span></a></li>
+    <li><a href="functions_func.html"><span>Functions</span></a></li>
+    <li><a href="functions_vars.html"><span>Variables</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions.html#index_a"><span>a</span></a></li>
+    <li><a href="functions_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="functions_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="functions_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="functions_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="functions_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="functions_0x67.html#index_g"><span>g</span></a></li>
+    <li id="current"><a href="functions_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="functions_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="functions_0x6c.html#index_l"><span>l</span></a></li>
+    <li><a href="functions_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="functions_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="functions_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="functions_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="functions_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="functions_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="functions_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="functions_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="functions_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="functions_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="functions_0x77.html#index_w"><span>w</span></a></li>
+    <li><a href="functions_0x78.html#index_x"><span>x</span></a></li>
+  </ul>
+</div>
+
+<p>
+Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:
+<p>
+<h3><a class="anchor" name="index_h">- h -</a></h3><ul>
+<li>haint
+: <a class="el" href="structdwc__otg__host__global__regs.html#7c41808b0a69ed7d2125eb3afbbf6c14">dwc_otg_host_global_regs</a><li>haintmsk
+: <a class="el" href="structdwc__otg__host__global__regs.html#317f5059d4c2dc91da041f5c0a4819fc">dwc_otg_host_global_regs</a><li>halt_on_queue
+: <a class="el" href="structdwc__hc.html#c3b27b33fae73aff43a9834a1ed585da">dwc_hc</a><li>halt_pending
+: <a class="el" href="structdwc__hc.html#2177dcde6dbb17b6bc7d0fb34e8ec95a">dwc_hc</a><li>halt_status
+: <a class="el" href="structdwc__hc.html#07eca0fa02105ddaa1719387f5558b23">dwc_hc</a><li>hburstlen
+: <a class="el" href="uniongahbcfg__data.html#b8f9a94aa77eb5abc379c438bf68f3d0">gahbcfg_data</a><li>hc_num
+: <a class="el" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">dwc_hc</a><li>hc_ptr_array
+: <a class="el" href="structdwc__otg__hcd.html#cb393f6a676fb106e0e3d35396fb97f9">dwc_otg_hcd</a><li>hc_regs
+: <a class="el" href="structdwc__otg__host__if.html#7f7c107d4720641eb4141cd817211ac0">dwc_otg_host_if</a><li>hcchar
+: <a class="el" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">dwc_otg_hc_regs</a><li>hcd
+: <a class="el" href="structdwc__otg__device.html#834ef28e884f0d7fcac68f3bdf5c4b33">dwc_otg_device</a><li>hcd_cb
+: <a class="el" href="structdwc__otg__core__if.html#9a8568a762af68c9b0d97e0278cc26ba">dwc_otg_core_if</a><li>hcdma
+: <a class="el" href="structdwc__otg__hc__regs.html#ab2148d4b5f1bf3a2ad438e497a8b4a3">dwc_otg_hc_regs</a><li>hcdmab
+: <a class="el" href="structdwc__otg__hc__regs.html#602f4c6eceb8e9d4fa61f35d4149f355">dwc_otg_hc_regs</a><li>hcfg
+: <a class="el" href="structdwc__otg__host__global__regs.html#fd7d93b5ffcb6c7c0a84ef656e6e68de">dwc_otg_host_global_regs</a>, <a class="el" href="structdwc__otg__core__if.html#447a626f22ad64a90c68a6f49e624eb8">dwc_otg_core_if</a><li>hcint
+: <a class="el" href="structdwc__otg__hc__regs.html#0dfd5bae537d58e13788508dc719480d">dwc_otg_hc_regs</a><li>hcintmsk
+: <a class="el" href="structdwc__otg__hc__regs.html#830aa61c1d4326823662168ea7359205">dwc_otg_hc_regs</a><li>hcintr
+: <a class="el" href="uniongintsts__data.html#e02f1a50b20ed1c4248fd76e155147e8">gintsts_data</a>, <a class="el" href="uniongintmsk__data.html#3a4c193d8ff48291809dcd3ccb7c0585">gintmsk_data</a><li>hcsplt
+: <a class="el" href="structdwc__otg__hc__regs.html#149053001a9ee21b692afde531a814de">dwc_otg_hc_regs</a><li>hctsiz
+: <a class="el" href="structdwc__otg__hc__regs.html#c6173f823ba754d9f9549422b6380ca2">dwc_otg_hc_regs</a><li>hdr
+: <a class="el" href="struct__ddma__concat__buffer__setup.html#512cdc8b5ef9053f514443b884ec4730">_ddma_concat_buffer_setup</a><li>hfir
+: <a class="el" href="structdwc__otg__host__global__regs.html#d5ad893315e7b0dde27a3c5867dc56d0">dwc_otg_host_global_regs</a><li>hflbaddr
+: <a class="el" href="structdwc__otg__host__global__regs.html#9a6af0a2c19d7b6228c7a40c9078907b">dwc_otg_host_global_regs</a><li>hfnum
+: <a class="el" href="structdwc__otg__host__global__regs.html#cebb0d86d0776473ef30eeac61e8692c">dwc_otg_host_global_regs</a><li>hird
+: <a class="el" href="unionglpmctl__data.html#176b788935d1952606f523f2718b3512">glpmctl_data</a><li>hird_thres
+: <a class="el" href="unionglpmctl__data.html#e2ceea4bfe468c7b3c800235d7ffd5d2">glpmctl_data</a><li>hnp_changed
+: <a class="el" href="structdwc__otg__pcd__function__ops.html#db190030830b55d72b36255980be08d7">dwc_otg_pcd_function_ops</a><li>hnpcap
+: <a class="el" href="uniongusbcfg__data.html#71b6330c5ccf1d21ebf79a0a829612b5">gusbcfg_data</a><li>hnpreq
+: <a class="el" href="uniongotgctl__data.html#08487ecb0860252b73815ee6e0f8eaa3">gotgctl_data</a><li>host_channels
+: <a class="el" href="structdwc__otg__driver__module__params.html#4727585082d86c52396adfde0cfffa17">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#c1b433c6965aa7d48f6ca6818c592039">dwc_otg_core_params</a><li>host_global_regs
+: <a class="el" href="structdwc__otg__host__if.html#ff9692c2e10ca2bc7e24f981f25179c2">dwc_otg_host_if</a><li>host_if
+: <a class="el" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">dwc_otg_core_if</a><li>host_ls_low_power_phy_clk
+: <a class="el" href="structdwc__otg__driver__module__params.html#91c46e96e070e983e3f91c756dd4aa64">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#98f413798f20dc40036a2ec527935a7d">dwc_otg_core_params</a><li>host_nperio_tx_fifo_size
+: <a class="el" href="structdwc__otg__driver__module__params.html#edf2038417f58acd8dab202a8ca19d2a">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#6ff00857d99f72c0cfd6198cbcfab9a7">dwc_otg_core_params</a><li>host_perio_tx_fifo_size
+: <a class="el" href="structdwc__otg__driver__module__params.html#bdc820350ca3b6aec5ac435c9712ccd5">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#5bc3cac5c81fd8d6fd291ca4b7de3e28">dwc_otg_core_params</a><li>host_perio_tx_q_depth
+: <a class="el" href="unionhwcfg2__data.html#857bb59069e203a94ffd32538c60058f">hwcfg2_data</a><li>host_rx_fifo_size
+: <a class="el" href="structdwc__otg__driver__module__params.html#1f490daab4c4e08d2773f46d51f1f5f7">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#2b2ab9c2fe16db70b136515b2e981f6b">dwc_otg_core_params</a><li>host_support_fs_ls_low_power
+: <a class="el" href="structdwc__otg__driver__module__params.html#6f3a0a2bf5c82d296fec31fec7b765ca">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#85cad588a450b8497347af9cf166bfde">dwc_otg_core_params</a><li>hprt0
+: <a class="el" href="structdwc__otg__host__if.html#dc8fe33e0bb3829cafa884d5fc603c4d">dwc_otg_host_if</a><li>hptxfsiz
+: <a class="el" href="structdwc__otg__core__global__regs.html#94ae41f04d5a4244a8ebc23e51187e96">dwc_otg_core_global_regs</a><li>hptxsts
+: <a class="el" href="structdwc__otg__host__global__regs.html#bf1a1528a2e479d86318d49ecd52ee40">dwc_otg_host_global_regs</a><li>hs_phy_type
+: <a class="el" href="unionhwcfg2__data.html#a248a2502e3c440d7b6e4ad61d396f4e">hwcfg2_data</a><li>hsftrst
+: <a class="el" href="uniongrstctl__data.html#7418a85aa4ffaa77c49f046202c97c01">grstctl_data</a><li>hsic_connect
+: <a class="el" href="unionglpmctl__data.html#76c64ead46647c39aa76edebf2f63444">glpmctl_data</a><li>hstfrm
+: <a class="el" href="uniongrstctl__data.html#6bf39518efe967ed4c7f9db6d3811a90">grstctl_data</a><li>hstnegdet
+: <a class="el" href="uniongotgint__data.html#7cd2a34cef45f168eb3ee197c101d164">gotgint_data</a><li>hstnegscs
+: <a class="el" href="uniongotgctl__data.html#20b17868fc09a12b163732d5bbc84d8d">gotgctl_data</a><li>hstnegsucstschng
+: <a class="el" href="uniongotgint__data.html#e41c62fee3da6113b23594cec6fb0c67">gotgint_data</a><li>hstsethnpen
+: <a class="el" href="uniongotgctl__data.html#7d45791d3622a59ff43ab248bbb1b2c1">gotgctl_data</a><li>hub_addr
+: <a class="el" href="structdwc__hc.html#19d0302b6e3769eada2466b8e5e0dd91">dwc_hc</a><li>hub_info
+: <a class="el" href="structdwc__otg__hcd__function__ops.html#71bff93886173700d26a8950e7ea82e1">dwc_otg_hcd_function_ops</a><li>hubaddr
+: <a class="el" href="unionhcsplt__data.html#2843e0a36458a9a4c2d5ed6da3027b36">hcsplt_data</a><li>hwcfg1
+: <a class="el" href="structdwc__otg__core__if.html#d7c6a00c6d7c157ff60a044a28ec8b95">dwc_otg_core_if</a><li>hwcfg2
+: <a class="el" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">dwc_otg_core_if</a><li>hwcfg3
+: <a class="el" href="structdwc__otg__core__if.html#91d0e0a5e8e048024c8846d12e00cecc">dwc_otg_core_if</a><li>hwcfg4
+: <a class="el" href="structdwc__otg__core__if.html#9c1394f3c46adde2fa7be79bf0237f9b">dwc_otg_core_if</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/functions_0x69.html b/drivers/usb/host/dwc_otg/doc/html/functions_0x69.html
new file mode 100644
index 000000000000..f6253f18de9e
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/functions_0x69.html
@@ -0,0 +1,121 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li id="current"><a href="functions.html"><span>All</span></a></li>
+    <li><a href="functions_func.html"><span>Functions</span></a></li>
+    <li><a href="functions_vars.html"><span>Variables</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions.html#index_a"><span>a</span></a></li>
+    <li><a href="functions_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="functions_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="functions_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="functions_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="functions_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="functions_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="functions_0x68.html#index_h"><span>h</span></a></li>
+    <li id="current"><a href="functions_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="functions_0x6c.html#index_l"><span>l</span></a></li>
+    <li><a href="functions_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="functions_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="functions_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="functions_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="functions_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="functions_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="functions_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="functions_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="functions_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="functions_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="functions_0x77.html#index_w"><span>w</span></a></li>
+    <li><a href="functions_0x78.html#index_x"><span>x</span></a></li>
+  </ul>
+</div>
+
+<p>
+Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:
+<p>
+<h3><a class="anchor" name="index_i">- i -</a></h3><ul>
+<li>i2c
+: <a class="el" href="unionhwcfg3__data.html#dd2115f4a4bfa47b2c9c9a7b5f42e203">hwcfg3_data</a><li>i2c_enable
+: <a class="el" href="structdwc__otg__driver__module__params.html#4e1d822cfcc6332fcaa0471bb1ca0d54">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#6b0a0ab15284a541ae079beecaf3e617">dwc_otg_core_params</a><li>i2cdevaddr
+: <a class="el" href="uniongi2cctl__data.html#78d1a33a0a81bbca4e89e2f578b27ca2">gi2cctl_data</a><li>i2cen
+: <a class="el" href="uniongi2cctl__data.html#6a14bacfd6c36d22071a79cb0fb53e77">gi2cctl_data</a><li>i2cintr
+: <a class="el" href="uniongintsts__data.html#2e8bd51ad285fd46db48f9fb5bbb7993">gintsts_data</a>, <a class="el" href="uniongintmsk__data.html#92dd84dd80b06e949668f85e6b6b7086">gintmsk_data</a><li>i2csuspctl
+: <a class="el" href="uniongi2cctl__data.html#96fcad9de22d851a74f900458c2ac325">gi2cctl_data</a><li>ic_traffic_pull_remove
+: <a class="el" href="uniongusbcfg__data.html#6805b1ea875bbb9cd31e877fd66c8559">gusbcfg_data</a><li>ic_usb_cap
+: <a class="el" href="uniongusbcfg__data.html#b729e853539aafb4bab1e4e9ac57916a">gusbcfg_data</a>, <a class="el" href="structdwc__otg__driver__module__params.html#ed3802eea4e62cd79ef7d8701d45b506">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#359a3cb3a7b4800a0c32750005c9fd1b">dwc_otg_core_params</a><li>id
+: <a class="el" href="structcfi__string.html#dc88ed81d4ff35c7a1c837708659afea">cfi_string</a><li>iddig_filt_en
+: <a class="el" href="unionhwcfg4__data.html#be353f75bb8cd8b14fc5f8db2d51da55">hwcfg4_data</a><li>ifrmnum
+: <a class="el" href="uniondctl__data.html#a817a529df5c5fc57135560014b90dcc">dctl_data</a><li>in
+: <a class="el" href="uniondaint__data.html#dbc4f689d070e6cbc112ec910f8bc36a">daint_data</a><li>in_desc_addr
+: <a class="el" href="structdwc__otg__dev__if.html#99f44e328bbb4401aabd8e2708853238">dwc_otg_dev_if</a><li>in_ep
+: <a class="el" href="structgadget__wrapper.html#9b57a0085afa3decabffc89943866931">gadget_wrapper</a>, <a class="el" href="structdwc__otg__pcd.html#dbfc8c424ea3add38db96fa87219caa8">dwc_otg_pcd</a>, <a class="el" href="structzero__dev.html#8b35a5b8ce497d55d7369a4635d891df">zero_dev</a><li>in_ep_regs
+: <a class="el" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">dwc_otg_dev_if</a><li>in_process
+: <a class="el" href="structdwc__otg__qtd.html#c1d73f1d48eeabbdc198ad28c0882bc1">dwc_otg_qtd</a><li>incomplisoin
+: <a class="el" href="uniongintsts__data.html#6a2b4a287af4632cec2207fe6fb91e86">gintsts_data</a>, <a class="el" href="uniongintmsk__data.html#3f9eeb4c73291b7943b7187ba34c90f4">gintmsk_data</a><li>incomplisoout
+: <a class="el" href="uniongintsts__data.html#519e2237cad3f43ebb7665e8d24c0180">gintsts_data</a>, <a class="el" href="uniongintmsk__data.html#c63c107070bd7623766e39cd06ec7c97">gintmsk_data</a><li>inep0
+: <a class="el" href="uniondaint__data.html#371eb39ddd249f984242ffc6bc2590ba">daint_data</a><li>inep1
+: <a class="el" href="uniondaint__data.html#af6849b786344ddee9cd7f884199434c">daint_data</a><li>inep10
+: <a class="el" href="uniondaint__data.html#f7560a6b186b5a690382e443b12feee8">daint_data</a><li>inep11
+: <a class="el" href="uniondaint__data.html#67745fd9faa3ca8d8da6e937d782cc3e">daint_data</a><li>inep12
+: <a class="el" href="uniondaint__data.html#bbae9ce28263f0973e46ed65367f898b">daint_data</a><li>inep13
+: <a class="el" href="uniondaint__data.html#dc51893893bfeddf1e842a89d778b6d8">daint_data</a><li>inep14
+: <a class="el" href="uniondaint__data.html#8235ebce9e66c2d0e76edf7a1a5cd877">daint_data</a><li>inep15
+: <a class="el" href="uniondaint__data.html#419952bb56b11f01e7f0995e138237de">daint_data</a><li>inep2
+: <a class="el" href="uniondaint__data.html#a52a2d17ef3dbea8fa25217629181a7c">daint_data</a><li>inep3
+: <a class="el" href="uniondaint__data.html#7152eb0ccf903be2810d1e25fef9bfb5">daint_data</a><li>inep4
+: <a class="el" href="uniondaint__data.html#f1e4c6eb79afda585c260a93c111aa12">daint_data</a><li>inep5
+: <a class="el" href="uniondaint__data.html#4175dc0a3f230773225f0971c31bc129">daint_data</a><li>inep6
+: <a class="el" href="uniondaint__data.html#40b670d2fc2b799a6278a16326441b1f">daint_data</a><li>inep7
+: <a class="el" href="uniondaint__data.html#8beeff7b54bd1902946425ab6a0d9d22">daint_data</a><li>inep8
+: <a class="el" href="uniondaint__data.html#baf8f1fe4bde7d02d61c93b5c7059f57">daint_data</a><li>inep9
+: <a class="el" href="uniondaint__data.html#ae119c728bcdf52e9504fedd16b0886b">daint_data</a><li>inepint
+: <a class="el" href="uniongintsts__data.html#e4e48a2a194cf95d934800a85c12784f">gintsts_data</a><li>inepintr
+: <a class="el" href="uniongintmsk__data.html#bcae4c9dd3d0f153b379dfbc6c830fc5">gintmsk_data</a><li>inepnakeff
+: <a class="el" href="uniondiepint__data.html#9186a1106fe57e01ce720a50ceb5864f">diepint_data</a><li>interval
+: <a class="el" href="structdwc__otg__qh.html#cdbce86d457f0ea08e2efedc47c9b315">dwc_otg_qh</a>, <a class="el" href="structdwc__otg__hcd__urb.html#49c5353377e2fb173f1b34ae7be7e257">dwc_otg_hcd_urb</a><li>intknepmis
+: <a class="el" href="uniondiepint__data.html#103fb29d954cf12d33f7ebe6009f9a46">diepint_data</a><li>intknqflsh
+: <a class="el" href="uniongrstctl__data.html#259049fa7991ecad9ca1595763b636f9">grstctl_data</a><li>intknwptr
+: <a class="el" href="uniondtknq1__data.html#33b25ddce8afe3ac2d8736f42133c284">dtknq1_data</a><li>intktxfemp
+: <a class="el" href="uniondiepint__data.html#7c9961f17328bbc25ca39e7ec1891e16">diepint_data</a><li>intokenrx
+: <a class="el" href="uniongintsts__data.html#912b165c3b774baedd294b678df9c2c0">gintsts_data</a><li>inv_sel_hsic
+: <a class="el" href="unionglpmctl__data.html#f664636955d9476647937d13d48f068e">glpmctl_data</a><li>ioc
+: <a class="el" href="unionhost__dma__desc__sts.html#2efbb549924afd0deb402af9eda4a272">host_dma_desc_sts</a>, <a class="el" href="uniondev__dma__desc__sts.html#02c8be72ef6258c25094478c7cac0b12">dev_dma_desc_sts</a><li>is_in
+: <a class="el" href="structdwc__ep.html#b882b6b7c857100ed20600e94ea37760">dwc_ep</a><li>iso_desc_addr
+: <a class="el" href="structdwc__ep.html#a4e11d12099ad64dd5048a3a210fc9f6">dwc_ep</a><li>iso_descs
+: <a class="el" href="structdwc__otg__hcd__urb.html#ed542f6a2d99dba2f6b71b0d8012ec8a">dwc_otg_hcd_urb</a><li>iso_dma_desc_addr
+: <a class="el" href="structdwc__ep.html#d571f49545171ea167193edac7984173">dwc_ep</a><li>iso_req_handle
+: <a class="el" href="structdwc__otg__pcd__ep.html#716d3c29adc54c6822935fc2ae9bef51">dwc_otg_pcd_ep</a><li>iso_thr_en
+: <a class="el" href="uniondthrctl__data.html#f69727f09d4443c01038ba7b163814f8">dthrctl_data</a><li>iso_tx_thr_en
+: <a class="el" href="structdwc__otg__dev__if.html#76af117a05ad95e5e5c534a1afcdae22">dwc_otg_dev_if</a><li>isoc_complete
+: <a class="el" href="structdwc__otg__pcd__function__ops.html#9714dfa4909221c0b937a9bcadf97339">dwc_otg_pcd_function_ops</a><li>isoc_frame_index
+: <a class="el" href="structdwc__otg__qtd.html#c67d5f885976d0698f20d113d32b4b30">dwc_otg_qtd</a><li>isoc_frame_index_last
+: <a class="el" href="structdwc__otg__qtd.html#c296d49e3615e35c06b83e7febc31943">dwc_otg_qtd</a><li>isoc_split_offset
+: <a class="el" href="structdwc__otg__qtd.html#839371940a7e34365e2272f3214b7e34">dwc_otg_qtd</a><li>isoc_split_pos
+: <a class="el" href="structdwc__otg__qtd.html#ab224d64d72f2ef4f10e722ebcfa29a6">dwc_otg_qtd</a><li>isooutdrop
+: <a class="el" href="uniongintsts__data.html#e6e931e1d6226dc110a98cd42c9a8e5f">gintsts_data</a>, <a class="el" href="uniongintmsk__data.html#3a0a75b129ccdaed6d98d1982b374d52">gintmsk_data</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/functions_0x6c.html b/drivers/usb/host/dwc_otg/doc/html/functions_0x6c.html
new file mode 100644
index 000000000000..9c194367fc1c
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/functions_0x6c.html
@@ -0,0 +1,74 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li id="current"><a href="functions.html"><span>All</span></a></li>
+    <li><a href="functions_func.html"><span>Functions</span></a></li>
+    <li><a href="functions_vars.html"><span>Variables</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions.html#index_a"><span>a</span></a></li>
+    <li><a href="functions_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="functions_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="functions_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="functions_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="functions_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="functions_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="functions_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="functions_0x69.html#index_i"><span>i</span></a></li>
+    <li id="current"><a href="functions_0x6c.html#index_l"><span>l</span></a></li>
+    <li><a href="functions_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="functions_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="functions_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="functions_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="functions_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="functions_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="functions_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="functions_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="functions_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="functions_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="functions_0x77.html#index_w"><span>w</span></a></li>
+    <li><a href="functions_0x78.html#index_x"><span>x</span></a></li>
+  </ul>
+</div>
+
+<p>
+Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:
+<p>
+<h3><a class="anchor" name="index_l">- l -</a></h3><ul>
+<li>l
+: <a class="el" href="uniondev__dma__desc__sts.html#b728a79d6a86a0d1b6426a1b2627f2c2">dev_dma_desc_sts</a><li>length
+: <a class="el" href="structdwc__otg__pcd__request.html#3dd3fcc889bf220b048023e8b05fab61">dwc_otg_pcd_request</a>, <a class="el" href="structdwc__otg__hcd__urb.html#dca57de4fdecd894241ce24167206a45">dwc_otg_hcd_urb</a>, <a class="el" href="structdwc__otg__hcd__iso__packet__desc.html#8392d21b820df0181f4e6dca91234543">dwc_otg_hcd_iso_packet_desc</a>, <a class="el" href="structiso__pkt__info.html#ced82142e81778345016841e15020eb8">iso_pkt_info</a><li>lh
+: <a class="el" href="structcfi__ep.html#18bff3370dc933cd374d458897dfbc2f">cfi_ep</a><li>lock
+: <a class="el" href="structdwc__otg__pcd.html#5d450e4d06659ab2f3b18e5c816776e4">dwc_otg_pcd</a>, <a class="el" href="structdwc__otg__hcd.html#34f29e9c035009476495f7701c1813fd">dwc_otg_hcd</a>, <a class="el" href="structzero__dev.html#712568d4b6a481845034ac6d87c0547d">zero_dev</a><li>lpm_cap_en
+: <a class="el" href="unionglpmctl__data.html#cf0a4cfcd158e41eb3811048e723890f">glpmctl_data</a><li>lpm_chan_index
+: <a class="el" href="unionglpmctl__data.html#7e6bb2a40d4e0bdfed6f868b1f670235">glpmctl_data</a><li>lpm_enable
+: <a class="el" href="structdwc__otg__driver__module__params.html#bb4e33c533d53de007814f0e5a70dd8a">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#8b906ba765a10dd9fcfa1c02dbc0184e">dwc_otg_core_params</a><li>lpm_resp
+: <a class="el" href="unionglpmctl__data.html#752c00118919fce173804931b058c5a8">glpmctl_data</a><li>lpmtranrcvd
+: <a class="el" href="uniongintsts__data.html#50e73e91df681c835de50f8276058829">gintsts_data</a>, <a class="el" href="uniongintmsk__data.html#24f9f89b33866c5dc7b16588bc94e103">gintmsk_data</a><li>lspddev
+: <a class="el" href="unionhcchar__data.html#ca469c8bda88761c4d9ef74b811d71f4">hcchar_data</a><li>lx_state
+: <a class="el" href="structdwc__otg__core__if.html#2b0701d814069ec69897e08374366c7b">dwc_otg_core_if</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/functions_0x6d.html b/drivers/usb/host/dwc_otg/doc/html/functions_0x6d.html
new file mode 100644
index 000000000000..e57901eed4b1
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/functions_0x6d.html
@@ -0,0 +1,79 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li id="current"><a href="functions.html"><span>All</span></a></li>
+    <li><a href="functions_func.html"><span>Functions</span></a></li>
+    <li><a href="functions_vars.html"><span>Variables</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions.html#index_a"><span>a</span></a></li>
+    <li><a href="functions_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="functions_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="functions_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="functions_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="functions_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="functions_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="functions_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="functions_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="functions_0x6c.html#index_l"><span>l</span></a></li>
+    <li id="current"><a href="functions_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="functions_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="functions_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="functions_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="functions_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="functions_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="functions_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="functions_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="functions_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="functions_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="functions_0x77.html#index_w"><span>w</span></a></li>
+    <li><a href="functions_0x78.html#index_x"><span>x</span></a></li>
+  </ul>
+</div>
+
+<p>
+Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:
+<p>
+<h3><a class="anchor" name="index_m">- m -</a></h3><ul>
+<li>max_packet
+: <a class="el" href="structdwc__hc.html#bd88f02eb286ba01d8d1b049e8975ccb">dwc_hc</a><li>max_packet_count
+: <a class="el" href="structdwc__otg__driver__module__params.html#bb7904edc790fce40ac04ed68a64217e">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#e17230afa013a15beda38565d19fa933">dwc_otg_core_params</a><li>max_transfer_size
+: <a class="el" href="structdwc__otg__driver__module__params.html#16cc5351ae1dfbcd81d56a7ec16e1748">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#e614d1d2ee740cd972ca76ed0dffec74">dwc_otg_core_params</a><li>maxp
+: <a class="el" href="structdwc__otg__qh.html#5975c2bede1ca0c6cfe9a66fe0a52567">dwc_otg_qh</a><li>maxpacket
+: <a class="el" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">dwc_ep</a><li>maxxfer
+: <a class="el" href="structdwc__ep.html#f60095e5ebedf7f98f3bfea77ce9a755">dwc_ep</a><li>mc
+: <a class="el" href="uniondeptsiz__data.html#45a97381fba9a7d9c3bde425334a60a5">deptsiz_data</a><li>min_ahb_freq
+: <a class="el" href="unionhwcfg4__data.html#0a12e214e53ded595dfa11157129ab8c">hwcfg4_data</a><li>modemismatch
+: <a class="el" href="uniongintsts__data.html#5fda463a80eb6927b2b875d64e8a0753">gintsts_data</a>, <a class="el" href="uniongintmsk__data.html#f62315fe9de8bb3bc371cb0a51927496">gintmsk_data</a><li>mpi_enable
+: <a class="el" href="structdwc__otg__driver__module__params.html#484412984c814a6298b05b58d94bd730">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#740e50199a75b3877b7db630d49c36aa">dwc_otg_core_params</a><li>mps
+: <a class="el" href="unionhcchar__data.html#47d11a5e62f69534d8ac0606aa7ffe7d">hcchar_data</a>, <a class="el" href="uniondepctl__data.html#5899d20333186341271c2d0b7781b98c">depctl_data</a>, <a class="el" href="structdwc__otg__hcd__pipe__info.html#b1d585e71a4e15bc79fc5f6d87bada6a">dwc_otg_hcd_pipe_info</a><li>mtrf
+: <a class="el" href="uniondev__dma__desc__sts.html#01c54383fd48fc31a3dd93ef54c417e8">dev_dma_desc_sts</a><li>multi_count
+: <a class="el" href="structdwc__hc.html#9a01b904f7ccc7178cdb80c20e8a9b0c">dwc_hc</a><li>multi_proc_int
+: <a class="el" href="unionhwcfg2__data.html#53c36944e5bd45e6f3ecbe933d7246eb">hwcfg2_data</a><li>multicnt
+: <a class="el" href="unionhcchar__data.html#9c0f515663251779e4960ec5613ce6fe">hcchar_data</a><li>multiproc_int_enable
+: <a class="el" href="structdwc__otg__core__if.html#5675c8d8dd7df746fda9157dc39ba5c2">dwc_otg_core_if</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/functions_0x6e.html b/drivers/usb/host/dwc_otg/doc/html/functions_0x6e.html
new file mode 100644
index 000000000000..b2c51c21a314
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/functions_0x6e.html
@@ -0,0 +1,99 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li id="current"><a href="functions.html"><span>All</span></a></li>
+    <li><a href="functions_func.html"><span>Functions</span></a></li>
+    <li><a href="functions_vars.html"><span>Variables</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions.html#index_a"><span>a</span></a></li>
+    <li><a href="functions_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="functions_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="functions_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="functions_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="functions_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="functions_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="functions_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="functions_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="functions_0x6c.html#index_l"><span>l</span></a></li>
+    <li><a href="functions_0x6d.html#index_m"><span>m</span></a></li>
+    <li id="current"><a href="functions_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="functions_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="functions_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="functions_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="functions_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="functions_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="functions_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="functions_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="functions_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="functions_0x77.html#index_w"><span>w</span></a></li>
+    <li><a href="functions_0x78.html#index_x"><span>x</span></a></li>
+  </ul>
+</div>
+
+<p>
+Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:
+<p>
+<h3><a class="anchor" name="index_n">- n -</a></h3><ul>
+<li>n_bytes
+: <a class="el" href="unionhost__dma__desc__sts.html#a8f68a8a5c22c3c1b530400c23083892">host_dma_desc_sts</a>, <a class="el" href="structdwc__otg__qh.html#6b625d870c7854ccaff5c28fad87482a">dwc_otg_qh</a><li>n_desc
+: <a class="el" href="structdwc__otg__qtd.html#ef3021e617cf1f448bd23b1f7ab3859b">dwc_otg_qtd</a><li>nak
+: <a class="el" href="unionhcintmsk__data.html#32ae7d92d0eb93ced42ac3773ddc3a2f">hcintmsk_data</a>, <a class="el" href="unionhcint__data.html#ce65c9d3f0c7d3e5b8f163a378051c6c">hcint_data</a>, <a class="el" href="uniondoepint__data.html#2ac99fbbb1bcf135d5db41e096e8b95b">doepint_data</a>, <a class="el" href="uniondiepint__data.html#3ade814b2bef3085bb6fa32e94ea1aac">diepint_data</a><li>nakonbble
+: <a class="el" href="uniondctl__data.html#422c27727aa788391b807b62011bd464">dctl_data</a><li>naksts
+: <a class="el" href="uniondepctl__data.html#98d3916b91f9d3d6c460d0ffaffd7b8b">depctl_data</a><li>need_gadget_att
+: <a class="el" href="structcfiobject.html#f103d681f78c43dc92dd4a85cdbdc27c">cfiobject</a><li>need_status_in_complete
+: <a class="el" href="structcfiobject.html#8d35a323dcd29a1c9d1a8568bd514c3b">cfiobject</a><li>next_frame
+: <a class="el" href="structdwc__ep.html#1e9f4d08454c973c17acb3e52a2c3689">dwc_ep</a><li>nextep
+: <a class="el" href="uniondepctl__data.html#3bdea97ec728985cbc4b9305f3ed8e96">depctl_data</a><li>non_iso_thr_en
+: <a class="el" href="uniondthrctl__data.html#9b9e309f454fb10621cbaeafe068af47">dthrctl_data</a><li>non_iso_tx_thr_en
+: <a class="el" href="structdwc__otg__dev__if.html#c4c1cdbb40f37e3403d62ae00b4819eb">dwc_otg_dev_if</a><li>non_periodic_channels
+: <a class="el" href="structdwc__otg__hcd.html#e7fff26b5cce7c6c520c89f9e3c75617">dwc_otg_hcd</a><li>non_periodic_qh_ptr
+: <a class="el" href="structdwc__otg__hcd.html#01ab5791d6269b6b5d506f2113b94231">dwc_otg_hcd</a><li>non_periodic_sched_active
+: <a class="el" href="structdwc__otg__hcd.html#ffa3041ad517da9519aa2159cdec3f61">dwc_otg_hcd</a><li>non_periodic_sched_inactive
+: <a class="el" href="structdwc__otg__hcd.html#64c96c47a36d71bad6e4360cec9d07ad">dwc_otg_hcd</a><li>nonperio_tx_q_depth
+: <a class="el" href="unionhwcfg2__data.html#1369a191c7bd2f717cef2bce7a97ee67">hwcfg2_data</a><li>nperio_tx_fifo_size
+: <a class="el" href="structdwc__otg__core__if.html#fb77b09f04a5687d2087726edd8dece6">dwc_otg_core_if</a><li>nptxfemplvl_txfemplvl
+: <a class="el" href="uniongahbcfg__data.html#00758ec639d12cc80fd98b1a6526c454">gahbcfg_data</a><li>nptxfempty
+: <a class="el" href="uniongintsts__data.html#adebf5ff5bdf69a2bcf0bd4b2ba55ef4">gintsts_data</a>, <a class="el" href="uniongintmsk__data.html#2c395e7bef31a4d9b2d1a3257c601be4">gintmsk_data</a><li>nptxfrwnden
+: <a class="el" href="uniongusbcfg__data.html#3ac9a67298febe31dc67c802a7f77f0a">gusbcfg_data</a><li>nptxfspcavail
+: <a class="el" href="uniongnptxsts__data.html#6c149be246bcf5ca5395f67e67648207">gnptxsts_data</a><li>nptxqspcavail
+: <a class="el" href="uniongnptxsts__data.html#634ffd5e84bc422ddef043574d8f0957">gnptxsts_data</a><li>nptxqtop_chnep
+: <a class="el" href="uniongnptxsts__data.html#6f593581592d2c904db11b39f8275ed9">gnptxsts_data</a><li>nptxqtop_terminate
+: <a class="el" href="uniongnptxsts__data.html#8aeca3e7350acc25b9c0623eea88bfc3">gnptxsts_data</a><li>nptxqtop_token
+: <a class="el" href="uniongnptxsts__data.html#7675d024cc57442bd67d63551cb5dfcc">gnptxsts_data</a><li>ntd
+: <a class="el" href="unionhctsiz__data.html#ac1addd68951e1a6a25312d49be9895d">hctsiz_data</a>, <a class="el" href="structdwc__otg__qh.html#6da0f75ffa49c8ffadde42e9618ed8c8">dwc_otg_qh</a>, <a class="el" href="structdwc__hc.html#9a3a483b9c4e45d1ec5f475beb6a10a3">dwc_hc</a><li>num
+: <a class="el" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">dwc_ep</a><li>num_dev_ep
+: <a class="el" href="unionhwcfg2__data.html#9f827f334b58643849598ce1fa314c5a">hwcfg2_data</a><li>num_dev_mode_ctrl_ep
+: <a class="el" href="unionhwcfg4__data.html#51130a20d8311e691ea8b8565bbe3080">hwcfg4_data</a><li>num_dev_perio_in_ep
+: <a class="el" href="unionhwcfg4__data.html#aee60fb196cf53b610df556744e4d317">hwcfg4_data</a><li>num_host_chan
+: <a class="el" href="unionhwcfg2__data.html#83708a4d45e8d019892367c5ae9f6fd0">hwcfg2_data</a><li>num_host_channels
+: <a class="el" href="structdwc__otg__host__if.html#a7b144c7f83d79fdafd7cd0c8c06102d">dwc_otg_host_if</a><li>num_in_eps
+: <a class="el" href="structdwc__otg__dev__if.html#4fae9bc1293bf2e58966c38fa5b98822">dwc_otg_dev_if</a>, <a class="el" href="unionhwcfg4__data.html#753b321350388c5e1307802ff968f9a8">hwcfg4_data</a><li>num_out_eps
+: <a class="el" href="structdwc__otg__dev__if.html#2f0e01cdc605623f591963fc83c8dc73">dwc_otg_dev_if</a><li>nyet
+: <a class="el" href="unionhcintmsk__data.html#4274f9b730db0e390e5f3be4247ee45c">hcintmsk_data</a>, <a class="el" href="unionhcint__data.html#755e54c3dfded3653447dfdd63fd8b6a">hcint_data</a>, <a class="el" href="uniondoepint__data.html#f35ad8ba20b8941b6ad00dc75586454f">doepint_data</a><li>nzstsouthshk
+: <a class="el" href="uniondcfg__data.html#bfe8fbad12896d96cbeb686243f9602e">dcfg_data</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/functions_0x6f.html b/drivers/usb/host/dwc_otg/doc/html/functions_0x6f.html
new file mode 100644
index 000000000000..5fcbf44959cd
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/functions_0x6f.html
@@ -0,0 +1,101 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li id="current"><a href="functions.html"><span>All</span></a></li>
+    <li><a href="functions_func.html"><span>Functions</span></a></li>
+    <li><a href="functions_vars.html"><span>Variables</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions.html#index_a"><span>a</span></a></li>
+    <li><a href="functions_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="functions_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="functions_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="functions_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="functions_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="functions_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="functions_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="functions_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="functions_0x6c.html#index_l"><span>l</span></a></li>
+    <li><a href="functions_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="functions_0x6e.html#index_n"><span>n</span></a></li>
+    <li id="current"><a href="functions_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="functions_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="functions_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="functions_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="functions_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="functions_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="functions_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="functions_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="functions_0x77.html#index_w"><span>w</span></a></li>
+    <li><a href="functions_0x78.html#index_x"><span>x</span></a></li>
+  </ul>
+</div>
+
+<p>
+Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:
+<p>
+<h3><a class="anchor" name="index_o">- o -</a></h3><ul>
+<li>oddfrm
+: <a class="el" href="unionhcchar__data.html#1eae01428cc22feed785eedff05c86da">hcchar_data</a><li>offset
+: <a class="el" href="structdwc__otg__hcd__iso__packet__desc.html#246f3d147a22cd295c534253593dca4a">dwc_otg_hcd_iso_packet_desc</a>, <a class="el" href="structiso__pkt__info.html#0c72a0585ccc93555da4db7e168f75f8">iso_pkt_info</a><li>op_mode
+: <a class="el" href="unionhwcfg2__data.html#592df9b97ff9342b839d2ed76d54c652">hwcfg2_data</a><li>op_state
+: <a class="el" href="structdwc__otg__core__if.html#5a5c5c1cf8d870101cc1fffac56d88c0">dwc_otg_core_if</a><li>ops
+: <a class="el" href="structcfiobject.html#324b7481af9ba7a97233b162bbe8301a">cfiobject</a><li>opt
+: <a class="el" href="structdwc__otg__driver__module__params.html#bccaf8d2ce8da6d5ef0d1c81caf9e518">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#6d67db1b1152d788bf2fc7fdc6363f78">dwc_otg_core_params</a><li>optional_features
+: <a class="el" href="unionhwcfg3__data.html#37ea87e07a63864a3b985df59fe98c8d">hwcfg3_data</a><li>otg_cap
+: <a class="el" href="structdwc__otg__driver__module__params.html#985f1849ab70919e756c86280a8f7ef0">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#b6960c28e9c7d82dca37645726c8f7ce">dwc_otg_core_params</a><li>otg_enable_hsic
+: <a class="el" href="unionhwcfg3__data.html#8c83b7ac3a4bb366119aeb3195126445">hwcfg3_data</a><li>otg_enable_ic_usb
+: <a class="el" href="unionhwcfg3__data.html#a01a48361a21cb9dfbbd555823b8531b">hwcfg3_data</a><li>otg_func
+: <a class="el" href="unionhwcfg3__data.html#dcd27bbcb3f0e0f5fbd6e7e8b7db1865">hwcfg3_data</a><li>otg_lpm_en
+: <a class="el" href="unionhwcfg3__data.html#2b9c39a4ce021bfd039729ccf2c2c503">hwcfg3_data</a><li>otg_port
+: <a class="el" href="structdwc__otg__hcd.html#9231b4c3dce89a1506a5e501ec5c7a39">dwc_otg_hcd</a><li>otgintr
+: <a class="el" href="uniongintsts__data.html#7934c11c40b0b60137edbdaa2be45542">gintsts_data</a>, <a class="el" href="uniongintmsk__data.html#6c9d578034af4f2ca08447fdac22ff88">gintmsk_data</a><li>otgutmifssel
+: <a class="el" href="uniongusbcfg__data.html#ef6e00f543156d1af19662c3ee86830d">gusbcfg_data</a><li>out
+: <a class="el" href="uniondaint__data.html#8462ad2dc1692f1253b769445382e2d4">daint_data</a><li>out_desc_addr
+: <a class="el" href="structdwc__otg__dev__if.html#8cc9be8ccaba2ef93b02b34ba7b26bad">dwc_otg_dev_if</a><li>out_ep
+: <a class="el" href="structgadget__wrapper.html#c420e5ba1a1c2d83d62471c423180d3c">gadget_wrapper</a>, <a class="el" href="structdwc__otg__pcd.html#b9e49a1d1fbca5ba9523e27c7108df30">dwc_otg_pcd</a>, <a class="el" href="structzero__dev.html#28a2079d55de6ac606cc69b79882223f">zero_dev</a><li>out_ep_regs
+: <a class="el" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">dwc_otg_dev_if</a><li>outep0
+: <a class="el" href="uniondaint__data.html#c7e9083edca852fb7f2f64e8671aee84">daint_data</a><li>outep1
+: <a class="el" href="uniondaint__data.html#32fab893aee2c30b343fcef45a2b663b">daint_data</a><li>outep10
+: <a class="el" href="uniondaint__data.html#1c2f136c1e7820cb09f31b7d7e8ddcf4">daint_data</a><li>outep11
+: <a class="el" href="uniondaint__data.html#f1df69d381a3a93148371edd890f375e">daint_data</a><li>outep12
+: <a class="el" href="uniondaint__data.html#fc51e98e345b027d0e015cebe87914a3">daint_data</a><li>outep13
+: <a class="el" href="uniondaint__data.html#fdb431a548b60ebf8ca6aea82c64b841">daint_data</a><li>outep14
+: <a class="el" href="uniondaint__data.html#14a49a0718676557899e5f121583778e">daint_data</a><li>outep15
+: <a class="el" href="uniondaint__data.html#f3223d420d13e35899760843900cc8ea">daint_data</a><li>outep2
+: <a class="el" href="uniondaint__data.html#ab37e9518e23799029192a422ca6a3ca">daint_data</a><li>outep3
+: <a class="el" href="uniondaint__data.html#db7e607293c77325f6940d33c56bc502">daint_data</a><li>outep4
+: <a class="el" href="uniondaint__data.html#17ad350597358b4795cf861409ba228c">daint_data</a><li>outep5
+: <a class="el" href="uniondaint__data.html#d50c4c8564d64cc4c176bcadd031b625">daint_data</a><li>outep6
+: <a class="el" href="uniondaint__data.html#d23b2e895318d194c683f2c6bb2ccbbe">daint_data</a><li>outep7
+: <a class="el" href="uniondaint__data.html#f8891bc2ff5fe8989c5119461e6ab126">daint_data</a><li>outep8
+: <a class="el" href="uniondaint__data.html#29c28a7d96343bfcc1f43faa72e83722">daint_data</a><li>outep9
+: <a class="el" href="uniondaint__data.html#8ad45fbc3efeb84ed83dc44b80e83c05">daint_data</a><li>outepintr
+: <a class="el" href="uniongintsts__data.html#58c08d29fa4b120748eb01b0d989facf">gintsts_data</a>, <a class="el" href="uniongintmsk__data.html#d48fe24e3e91bc1bcbc1c790c1b67f96">gintmsk_data</a><li>outpkterr
+: <a class="el" href="uniondoepint__data.html#dc9d4f243e80cd6796fcc334498fa4cc">doepint_data</a><li>outtknepdis
+: <a class="el" href="uniondoepint__data.html#3f02a0e998438229ec34bb1a8c1f4192">doepint_data</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/functions_0x70.html b/drivers/usb/host/dwc_otg/doc/html/functions_0x70.html
new file mode 100644
index 000000000000..935f5de3d930
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/functions_0x70.html
@@ -0,0 +1,144 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li id="current"><a href="functions.html"><span>All</span></a></li>
+    <li><a href="functions_func.html"><span>Functions</span></a></li>
+    <li><a href="functions_vars.html"><span>Variables</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions.html#index_a"><span>a</span></a></li>
+    <li><a href="functions_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="functions_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="functions_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="functions_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="functions_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="functions_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="functions_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="functions_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="functions_0x6c.html#index_l"><span>l</span></a></li>
+    <li><a href="functions_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="functions_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="functions_0x6f.html#index_o"><span>o</span></a></li>
+    <li id="current"><a href="functions_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="functions_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="functions_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="functions_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="functions_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="functions_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="functions_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="functions_0x77.html#index_w"><span>w</span></a></li>
+    <li><a href="functions_0x78.html#index_x"><span>x</span></a></li>
+  </ul>
+</div>
+
+<p>
+Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:
+<p>
+<h3><a class="anchor" name="index_p">- p -</a></h3><ul>
+<li>p
+: <a class="el" href="structdwc__otg__cil__callbacks.html#a486473d73fb104dc3a37e963a8ef8e5">dwc_otg_cil_callbacks</a><li>p_tx_msk
+: <a class="el" href="structdwc__otg__core__if.html#0683b28ebf5247a60247d27a1a714d27">dwc_otg_core_if</a><li>packet_count
+: <a class="el" href="structdwc__otg__hcd__urb.html#570583697e8c1e4398969630bc2562f8">dwc_otg_hcd_urb</a><li>packet_size_cntr_width
+: <a class="el" href="unionhwcfg3__data.html#a397ea503f5155d8e3a66cc82d7937f2">hwcfg3_data</a><li>pcd
+: <a class="el" href="structgadget__wrapper.html#cdc4a50b5415cc484f77c61a63db3e94">gadget_wrapper</a>, <a class="el" href="structdwc__otg__pcd__ep.html#234391334e48cbd72710d08655c9ed16">dwc_otg_pcd_ep</a>, <a class="el" href="structdwc__otg__device.html#2a8eefbd03790ea0bbb70e0ac14e4786">dwc_otg_device</a>, <a class="el" href="structcfiobject.html#bab38f9fb74c1332c70029000c7d3818">cfiobject</a><li>pcd_cb
+: <a class="el" href="structdwc__otg__core__if.html#83bca1e02fafc4bbfa9c1f2eeb19b245">dwc_otg_core_if</a><li>pcgcctl
+: <a class="el" href="structdwc__otg__core__if.html#348ed2c9aeae6fc608f1bb813978b3f9">dwc_otg_core_if</a><li>perfrint
+: <a class="el" href="uniondcfg__data.html#f4ed8f15f1716ff0f9366badac18fbb4">dcfg_data</a><li>perio_ep_supported
+: <a class="el" href="unionhwcfg2__data.html#d0d29d530b38b3dcd58c88a2ef9688bb">hwcfg2_data</a><li>perio_eps_supported
+: <a class="el" href="structdwc__otg__host__if.html#23dedb1efa17aa1c199f1e3c6e2a9784">dwc_otg_host_if</a><li>perio_tx_fifo_size
+: <a class="el" href="structdwc__otg__host__if.html#b208538c559719cd680ea4828429735e">dwc_otg_host_if</a>, <a class="el" href="structdwc__otg__dev__if.html#817a953b04c45cf346d7a7d6fc274150">dwc_otg_dev_if</a><li>periodic_channels
+: <a class="el" href="structdwc__otg__hcd.html#5754b87bd4644fbb7b90cf843c638f1c">dwc_otg_hcd</a><li>periodic_sched_assigned
+: <a class="el" href="structdwc__otg__hcd.html#4b8deae798f771135c4a99693b26873f">dwc_otg_hcd</a><li>periodic_sched_inactive
+: <a class="el" href="structdwc__otg__hcd.html#2a747cacd6bdbacbef86d4157c34a312">dwc_otg_hcd</a><li>periodic_sched_queued
+: <a class="el" href="structdwc__otg__hcd.html#e127912880eb487b3a2f38778c0de238">dwc_otg_hcd</a><li>periodic_sched_ready
+: <a class="el" href="structdwc__otg__hcd.html#74b089e094911a558f7b5f24681d3242">dwc_otg_hcd</a><li>periodic_usecs
+: <a class="el" href="structdwc__otg__hcd.html#1f2ce690c8ded506eff8d1b567747235">dwc_otg_hcd</a><li>perschedena
+: <a class="el" href="unionhcfg__data.html#b49be9c0cbc3df2bb917e1ea96c99c62">hcfg_data</a><li>perschedstat
+: <a class="el" href="unionhcfg__data.html#995a4d09381b8d6ce2c7ac0a6c7f364a">hcfg_data</a><li>phy_in_sleep
+: <a class="el" href="unionpcgcctl__data.html#f8b4b268a4fd5094a9a43ec503455f6f">pcgcctl_data</a><li>phy_init_done
+: <a class="el" href="structdwc__otg__core__if.html#24dd9dec510e5edac930538b81004b74">dwc_otg_core_if</a><li>phy_type
+: <a class="el" href="structdwc__otg__driver__module__params.html#77d1c10524440ed2e5189624157526ac">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#8b5d4e0c98c46d0d4e80b6faf66daf72">dwc_otg_core_params</a><li>phy_ulpi_ddr
+: <a class="el" href="structdwc__otg__driver__module__params.html#6a2b8c0c6298a7b1da23d5dd5abc4da8">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#6fc9a3fbe3c36cbbc231f1642ee96cfe">dwc_otg_core_params</a><li>phy_ulpi_ext_vbus
+: <a class="el" href="structdwc__otg__driver__module__params.html#8402de29e6ec24baa5881cb7d74914c2">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#3b6fa0a7fe7d7f87326894fdbe0aa375">dwc_otg_core_params</a><li>phy_utmi_width
+: <a class="el" href="structdwc__otg__driver__module__params.html#f6284c33f13fe2f02491fa1a0c479b25">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#41f5a03ab1b68564b240e03f33a09dde">dwc_otg_core_params</a><li>phyif
+: <a class="el" href="uniongusbcfg__data.html#f5e1a41cbdf6ae4b30a929ff3de8c99c">gusbcfg_data</a><li>phylpwrclksel
+: <a class="el" href="uniongusbcfg__data.html#9e4bac4a0ef0a045f97792f68c5f35df">gusbcfg_data</a><li>physel
+: <a class="el" href="uniongusbcfg__data.html#6680455bce7433ccec13377a20912e04">gusbcfg_data</a><li>physuspended
+: <a class="el" href="unionpcgcctl__data.html#c39017c4715319d740b749d16401f26c">pcgcctl_data</a><li>pid
+: <a class="el" href="unionhctsiz__data.html#d8b17af02c244e47ca0c38f933a6b3f0">hctsiz_data</a>, <a class="el" href="uniondev__dma__desc__sts.html#79bf5fe6d9949ddb671daa14b5ee298e">dev_dma_desc_sts</a><li>ping_state
+: <a class="el" href="structdwc__otg__qh.html#2c115474978a808c797c8975d72e419d">dwc_otg_qh</a><li>pipe_dir
+: <a class="el" href="structdwc__otg__hcd__pipe__info.html#8342fc4305ea957e2fa78f2bc9e707e4">dwc_otg_hcd_pipe_info</a><li>pipe_info
+: <a class="el" href="structdwc__otg__hcd__urb.html#34ee3ac5931687b41dd726f00c558369">dwc_otg_hcd_urb</a><li>pipe_type
+: <a class="el" href="structdwc__otg__hcd__pipe__info.html#0278c3069bc464cc4dbed8f6647f5856">dwc_otg_hcd_pipe_info</a><li>pkt_cnt
+: <a class="el" href="structdwc__ep.html#46349fb0608d8c6849ced211b0628c15">dwc_ep</a><li>pkt_info
+: <a class="el" href="structdwc__ep.html#a8ed15a24123a2dad6861da7d61dfb48">dwc_ep</a><li>pkt_per_frm
+: <a class="el" href="structdwc__ep.html#fe51420474de8a9d74fc9c4adc811c4b">dwc_ep</a><li>pktcnt
+: <a class="el" href="unionhctsiz__data.html#3ea18df5a98d33a6f8fa786252a0205b">hctsiz_data</a>, <a class="el" href="uniondeptsiz0__data.html#debb8f273e4480cde57bef7677697bd0">deptsiz0_data</a>, <a class="el" href="uniondeptsiz__data.html#bbd89e812371e5b555bb82373f3643d9">deptsiz_data</a><li>pktdrpsts
+: <a class="el" href="uniondoepint__data.html#0c8fc4f5245a9874c0c3b61d1c6f719d">doepint_data</a><li>pktsts
+: <a class="el" href="unionhost__grxsts__data.html#6dc2553475a56a445c6e6f319feffac8">host_grxsts_data</a>, <a class="el" href="uniondevice__grxsts__data.html#712eb005af256f84ebfc6f3083dd1ba8">device_grxsts_data</a><li>point2point
+: <a class="el" href="unionhwcfg2__data.html#6ef3a94368c53a22c222795bfc2306e3">hwcfg2_data</a><li>port_addr
+: <a class="el" href="structdwc__hc.html#9f597e05c37d7292f4c0d965c67ee3dd">dwc_hc</a><li>port_connect_status
+: <a class="el" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#9314ac02ed140807687793b512f78c63">dwc_otg_hcd::dwc_otg_hcd_internal_flags</a><li>port_connect_status_change
+: <a class="el" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#cd31ac4b9658265e90773448f354f0e1">dwc_otg_hcd::dwc_otg_hcd_internal_flags</a><li>port_enable_change
+: <a class="el" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#d222ae08372109a312f6649f77b650e8">dwc_otg_hcd::dwc_otg_hcd_internal_flags</a><li>port_l1_change
+: <a class="el" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#1900375ccea165f0efc40725f507a0bf">dwc_otg_hcd::dwc_otg_hcd_internal_flags</a><li>port_over_current_change
+: <a class="el" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#bc96cf12e2bc5b61ce05f15ae3297bd6">dwc_otg_hcd::dwc_otg_hcd_internal_flags</a><li>port_reset_change
+: <a class="el" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#d0d63f32ed35315e8a02549521fb386e">dwc_otg_hcd::dwc_otg_hcd_internal_flags</a><li>port_suspend_change
+: <a class="el" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#2a6e323cb4c01153aff1adc6269c74c7">dwc_otg_hcd::dwc_otg_hcd_internal_flags</a><li>portintr
+: <a class="el" href="uniongintsts__data.html#7490e48c2c93d20c182f00161f18b8e5">gintsts_data</a>, <a class="el" href="uniongintmsk__data.html#c907c60cbc7b157e730b053b40f4a2b3">gintmsk_data</a><li>power_optimiz
+: <a class="el" href="unionhwcfg4__data.html#3227ec0129191d0d099f0dce7f18c546">hwcfg4_data</a><li>priv
+: <a class="el" href="structdwc__otg__pcd__ep.html#8c8fad971c6c3b1c54d334c7f9b2d03e">dwc_otg_pcd_ep</a>, <a class="el" href="structdwc__otg__pcd__request.html#e0d93b64365968aa0dcf58535aecf40c">dwc_otg_pcd_request</a>, <a class="el" href="structdwc__otg__hcd.html#c019b908f209d577ccc19d29030926a1">dwc_otg_hcd</a>, <a class="el" href="structdwc__otg__hcd__urb.html#5ba0e393ef9768275db85c00e68be477">dwc_otg_hcd_urb</a><li>proc_buf_num
+: <a class="el" href="structdwc__ep.html#53033f174854701986545f05502e1cad">dwc_ep</a><li>prt_sleep_sts
+: <a class="el" href="unionglpmctl__data.html#241ff25a215f16ac29b3bb6d9f4943ed">glpmctl_data</a><li>prtaddr
+: <a class="el" href="unionhcsplt__data.html#e1c0812d6f655ea9915a6152c9f16cd6">hcsplt_data</a><li>prtconndet
+: <a class="el" href="unionhprt0__data.html#5124a40eeafd92c9632c91a2c3132937">hprt0_data</a><li>prtconnsts
+: <a class="el" href="unionhprt0__data.html#39b2dee944be8ec96857a3b43d203390">hprt0_data</a><li>prtena
+: <a class="el" href="unionhprt0__data.html#a964274b5d22e89ca4490f66dff3c763">hprt0_data</a><li>prtenchng
+: <a class="el" href="unionhprt0__data.html#75eae10eb537e49cc1ae2dc01c18aa47">hprt0_data</a><li>prtlnsts
+: <a class="el" href="unionhprt0__data.html#85a83fc17905d43dc604dce7f0869c63">hprt0_data</a><li>prtovrcurract
+: <a class="el" href="unionhprt0__data.html#4d8f8b654c26760791614ccbc43f180c">hprt0_data</a><li>prtovrcurrchng
+: <a class="el" href="unionhprt0__data.html#cc51da1d52cb824d419ef3feb6ba70b6">hprt0_data</a><li>prtpwr
+: <a class="el" href="unionhprt0__data.html#010bd8fb208ef4eeaa288b28f8f8c3a4">hprt0_data</a><li>prtres
+: <a class="el" href="unionhprt0__data.html#3f5961529636a3891a4ca9421dd535fa">hprt0_data</a><li>prtrst
+: <a class="el" href="unionhprt0__data.html#714a31048710164370292124795a9a9b">hprt0_data</a><li>prtspd
+: <a class="el" href="unionhprt0__data.html#59f1c27b8c912de0237d2d2974fc2a22">hprt0_data</a><li>prtsusp
+: <a class="el" href="unionhprt0__data.html#e7fe71d6c465ae002211c24a6ba359d2">hprt0_data</a><li>prttstctl
+: <a class="el" href="unionhprt0__data.html#c61d714ff8f0bc62767342523347ba66">hprt0_data</a><li>psetup
+: <a class="el" href="structdwc__otg__dev__if.html#ade28f08143342505c705db1fc0865a9">dwc_otg_dev_if</a><li>pti_enable
+: <a class="el" href="structdwc__otg__driver__module__params.html#2e17f84d9b07732a7fdf37b13832c54a">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#b601fde03b371b74deab1205e1329a7d">dwc_otg_core_params</a><li>pti_enh_enable
+: <a class="el" href="structdwc__otg__core__if.html#34540b79e9a14bfa234a52ac132c5cd1">dwc_otg_core_if</a><li>ptxfemplvl
+: <a class="el" href="uniongahbcfg__data.html#e45b68a6e6e681e58d70fd8e70f9542f">gahbcfg_data</a><li>ptxfempty
+: <a class="el" href="uniongintsts__data.html#54ed752629e9b8916507beca28d76162">gintsts_data</a>, <a class="el" href="uniongintmsk__data.html#3b52444894e041c660c146af2178272f">gintmsk_data</a><li>ptxfspcavail
+: <a class="el" href="unionhptxsts__data.html#0df6fb1f76396da626715d6ffc06dfa8">hptxsts_data</a><li>ptxqspcavail
+: <a class="el" href="unionhptxsts__data.html#8139e6eafb7b0bbb3cbafa125d5cd28f">hptxsts_data</a><li>ptxqtop_chnum
+: <a class="el" href="unionhptxsts__data.html#6fdf33c3add1fa286beaa252610b20ec">hptxsts_data</a><li>ptxqtop_odd
+: <a class="el" href="unionhptxsts__data.html#6b18b0bdf10050b08ac265e9143fdd63">hptxsts_data</a><li>ptxqtop_terminate
+: <a class="el" href="unionhptxsts__data.html#3c8a2ed8f4185130a28a452c0a9967f4">hptxsts_data</a><li>ptxqtop_token
+: <a class="el" href="unionhptxsts__data.html#e51712fd406526683b5c3311bd3dab8d">hptxsts_data</a><li>pwrclmp
+: <a class="el" href="unionpcgcctl__data.html#02d7dff0f26c3ac50ad4b876f1853c17">pcgcctl_data</a><li>pwronprgdone
+: <a class="el" href="uniondctl__data.html#216f929e4d24b0c3005cd0add0de7a27">dctl_data</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/functions_0x71.html b/drivers/usb/host/dwc_otg/doc/html/functions_0x71.html
new file mode 100644
index 000000000000..19bd972ed2dd
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/functions_0x71.html
@@ -0,0 +1,71 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li id="current"><a href="functions.html"><span>All</span></a></li>
+    <li><a href="functions_func.html"><span>Functions</span></a></li>
+    <li><a href="functions_vars.html"><span>Variables</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions.html#index_a"><span>a</span></a></li>
+    <li><a href="functions_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="functions_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="functions_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="functions_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="functions_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="functions_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="functions_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="functions_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="functions_0x6c.html#index_l"><span>l</span></a></li>
+    <li><a href="functions_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="functions_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="functions_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="functions_0x70.html#index_p"><span>p</span></a></li>
+    <li id="current"><a href="functions_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="functions_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="functions_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="functions_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="functions_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="functions_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="functions_0x77.html#index_w"><span>w</span></a></li>
+    <li><a href="functions_0x78.html#index_x"><span>x</span></a></li>
+  </ul>
+</div>
+
+<p>
+Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:
+<p>
+<h3><a class="anchor" name="index_q">- q -</a></h3><ul>
+<li>qh
+: <a class="el" href="structdwc__otg__qtd.html#f80ddcfb6edbe83a3991dd67c93a47e4">dwc_otg_qtd</a>, <a class="el" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">dwc_hc</a><li>qh_list_entry
+: <a class="el" href="structdwc__otg__qh.html#3e1cb9863dc72139e1832c04244c25ff">dwc_otg_qh</a><li>qtd
+: <a class="el" href="structdwc__otg__hcd__urb.html#68dc4d459bb70aed6083553653aadaad">dwc_otg_hcd_urb</a><li>qtd_list
+: <a class="el" href="structdwc__otg__qh.html#9567d266da8e796d3467fb16ae867f8e">dwc_otg_qh</a><li>qtd_offset
+: <a class="el" href="unionhost__dma__desc__sts.html#80be234e5bac143beca335ffe226eef6">host_dma_desc_sts</a><li>queue
+: <a class="el" href="structdwc__otg__pcd__ep.html#71f4fa571dfdc96f62fa4869e6add300">dwc_otg_pcd_ep</a><li>queue_sof
+: <a class="el" href="structdwc__otg__pcd__ep.html#bbec681b68f2f745d1cfecfedd4e64be">dwc_otg_pcd_ep</a><li>queuing_high_bandwidth
+: <a class="el" href="structdwc__otg__core__if.html#5a6a90b40bc80e71d40f107b68f1e84c">dwc_otg_core_if</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/functions_0x72.html b/drivers/usb/host/dwc_otg/doc/html/functions_0x72.html
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index 000000000000..96a63373e64c
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/functions_0x72.html
@@ -0,0 +1,141 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li id="current"><a href="functions.html"><span>All</span></a></li>
+    <li><a href="functions_func.html"><span>Functions</span></a></li>
+    <li><a href="functions_vars.html"><span>Variables</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions.html#index_a"><span>a</span></a></li>
+    <li><a href="functions_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="functions_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="functions_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="functions_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="functions_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="functions_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="functions_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="functions_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="functions_0x6c.html#index_l"><span>l</span></a></li>
+    <li><a href="functions_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="functions_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="functions_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="functions_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="functions_0x71.html#index_q"><span>q</span></a></li>
+    <li id="current"><a href="functions_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="functions_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="functions_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="functions_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="functions_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="functions_0x77.html#index_w"><span>w</span></a></li>
+    <li><a href="functions_0x78.html#index_x"><span>x</span></a></li>
+  </ul>
+</div>
+
+<p>
+Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:
+<p>
+<h3><a class="anchor" name="index_r">- r -</a></h3><ul>
+<li>reg_offset
+: <a class="el" href="structdwc__otg__device.html#d2701bc8589613bec5074968e57ce6ef">dwc_otg_device</a><li>regaddr
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+: <a class="el" href="structdwc__otg__hcd.html#4f2b2c551e4ac9f49afcbdbde1ddf55d">dwc_otg_hcd</a><li>restart_hcd_on_session_req
+: <a class="el" href="structdwc__otg__core__if.html#05b4c81b19338fc64090cf22d635517a">dwc_otg_core_if</a><li>resume
+: <a class="el" href="structdwc__otg__pcd__function__ops.html#654870eb85c5356b6a97a514645e5d8c">dwc_otg_pcd_function_ops</a>, <a class="el" href="structzero__dev.html#5fcacdfb9a6b069c866d44d66dd566a4">zero_dev</a><li>resume_wakeup
+: <a class="el" href="structdwc__otg__cil__callbacks.html#ad1895ddf4ad83622a514a725b4129d6">dwc_otg_cil_callbacks</a><li>retry_count
+: <a class="el" href="unionglpmctl__data.html#be75ed525bcfe231cd9bda6a1b8594f6">glpmctl_data</a><li>retry_count_sts
+: <a class="el" href="unionglpmctl__data.html#67ddd4b3576e04a06d5fff707c8bbf18">glpmctl_data</a><li>rmtwkupsig
+: <a class="el" href="uniondctl__data.html#dcae5af28dc159cd7ba85a9a2b8be51a">dctl_data</a><li>rstpdwnmodule
+: <a class="el" href="unionpcgcctl__data.html#9708a50a6e42cd2372d65555edf5cf28">pcgcctl_data</a><li>rw
+: <a class="el" href="uniongi2cctl__data.html#afc04461ec8ca28e870cb2374b862961">gi2cctl_data</a><li>rwdata
+: <a class="el" href="uniongi2cctl__data.html#7324a24ede0ab8ddcd9fbb1c5c558ff5">gi2cctl_data</a><li>rx_fifo_size
+: <a class="el" href="structdwc__otg__core__if.html#50bbb76c3818ada9ed2ea5527edabcd4">dwc_otg_core_if</a><li>rx_thr_en
+: <a class="el" href="structdwc__otg__dev__if.html#839ada1cbeff50af91f5db00f4b36ec4">dwc_otg_dev_if</a>, <a class="el" href="uniondthrctl__data.html#0a73132b4e481b250e1b5f533b807bcb">dthrctl_data</a><li>rx_thr_len
+: <a class="el" href="uniondthrctl__data.html#210370ba2134a296e1c1dcc8b2f05461">dthrctl_data</a><li>rx_thr_length
+: <a class="el" href="structdwc__otg__dev__if.html#e1ec98fc03446d7e172572a973107d62">dwc_otg_dev_if</a>, <a class="el" href="structdwc__otg__driver__module__params.html#eecdc71dde5ce0543a04d541a90f79bc">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#2cb1f83013e357828fbf55ac91971d44">dwc_otg_core_params</a><li>rxbytes
+: <a class="el" href="uniondev__dma__desc__sts.html#ede78801cd7bc514474fcbe1ef154e5a">dev_dma_desc_sts</a><li>rxfflsh
+: <a class="el" href="uniongrstctl__data.html#88467c1f0580f4837d229d85b35c97a7">grstctl_data</a><li>rxsts
+: <a class="el" href="uniondev__dma__desc__sts.html#a80809cda5b19b3e36f512effef795f0">dev_dma_desc_sts</a><li>rxstsqlvl
+: <a class="el" href="uniongintsts__data.html#7595576956c3a0ced9ea387880943012">gintsts_data</a>, <a class="el" href="uniongintmsk__data.html#83db45f92a3a692d79199e1a850c2a62">gintmsk_data</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/functions_0x73.html b/drivers/usb/host/dwc_otg/doc/html/functions_0x73.html
new file mode 100644
index 000000000000..6a80ff479c2a
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/functions_0x73.html
@@ -0,0 +1,128 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li id="current"><a href="functions.html"><span>All</span></a></li>
+    <li><a href="functions_func.html"><span>Functions</span></a></li>
+    <li><a href="functions_vars.html"><span>Variables</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions.html#index_a"><span>a</span></a></li>
+    <li><a href="functions_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="functions_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="functions_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="functions_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="functions_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="functions_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="functions_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="functions_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="functions_0x6c.html#index_l"><span>l</span></a></li>
+    <li><a href="functions_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="functions_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="functions_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="functions_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="functions_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="functions_0x72.html#index_r"><span>r</span></a></li>
+    <li id="current"><a href="functions_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="functions_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="functions_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="functions_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="functions_0x77.html#index_w"><span>w</span></a></li>
+    <li><a href="functions_0x78.html#index_x"><span>x</span></a></li>
+  </ul>
+</div>
+
+<p>
+Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:
+<p>
+<h3><a class="anchor" name="index_s">- s -</a></h3><ul>
+<li>s
+: <a class="el" href="structcfi__string.html#c852efd76029880787738fb474dd486e">cfi_string</a><li>sched_frame
+: <a class="el" href="structdwc__otg__qh.html#977a8032f08e45a9e9bdcd558a6965d3">dwc_otg_qh</a><li>schinfo
+: <a class="el" href="unionhctsiz__data.html#0d1f05f3b24da2caa3acc1c3864bc29b">hctsiz_data</a>, <a class="el" href="structdwc__hc.html#42c5f7b0264ee050df79dc1fe57464b7">dwc_hc</a><li>send_lpm
+: <a class="el" href="unionglpmctl__data.html#0651e486c5502489b2cac633bb00c78e">glpmctl_data</a><li>sent_zlp
+: <a class="el" href="structdwc__otg__pcd__request.html#c2c1832d46f417b63e41b5e23def6fc6">dwc_otg_pcd_request</a>, <a class="el" href="structdwc__ep.html#8c6340435beba0b8c025a4677602acab">dwc_ep</a><li>sesenddet
+: <a class="el" href="uniongotgint__data.html#58a04bef67e26229efe95f12938d18e8">gotgint_data</a><li>sesreq
+: <a class="el" href="uniongotgctl__data.html#c6b0b35d4366f74cf6fe268eda781f06">gotgctl_data</a><li>sesreqscs
+: <a class="el" href="uniongotgctl__data.html#5239dbbb4b31210a35a7104abb688801">gotgctl_data</a><li>sesreqsucstschng
+: <a class="el" href="uniongotgint__data.html#99a56305c7cc48086ef34c15bbc40ca6">gotgint_data</a><li>session_end_filt_en
+: <a class="el" href="unionhwcfg4__data.html#d5dc6949986ee9ac55ccf542b855fddf">hwcfg4_data</a><li>session_start
+: <a class="el" href="structdwc__otg__cil__callbacks.html#d4235cc3ff7705538ccafa408950d759">dwc_otg_cil_callbacks</a><li>sessreqintr
+: <a class="el" href="uniongintsts__data.html#c8b14c042daab677d0c4ae691d573995">gintsts_data</a>, <a class="el" href="uniongintmsk__data.html#aabb586a72e2a76982bfaa780e482212">gintmsk_data</a><li>setd0pid
+: <a class="el" href="uniondepctl__data.html#90d89b642aafd60a6c62db5bf8396de9">depctl_data</a><li>setd1pid
+: <a class="el" href="uniondepctl__data.html#9c0962acc0c23fe46a7738ad36634c25">depctl_data</a><li>setup
+: <a class="el" href="uniondoepint__data.html#b286d1b76f09a9122aca23e430b63dc8">doepint_data</a>, <a class="el" href="structdwc__otg__pcd__function__ops.html#e99e932440749d9464e008cef78e808d">dwc_otg_pcd_function_ops</a><li>setup_desc_addr
+: <a class="el" href="structdwc__otg__dev__if.html#f149a6cbedd5f180ff033caeee6f527e">dwc_otg_dev_if</a><li>setup_desc_index
+: <a class="el" href="structdwc__otg__dev__if.html#dd45f3935b2ebb171de8da70cddd6935">dwc_otg_dev_if</a><li>setup_dma
+: <a class="el" href="structdwc__otg__hcd__urb.html#497f61f9b3f6f77f6b844e31c047264d">dwc_otg_hcd_urb</a><li>setup_packet
+: <a class="el" href="structdwc__otg__hcd__urb.html#254afd954f3e24bb92841384183a317c">dwc_otg_hcd_urb</a><li>setup_pkt
+: <a class="el" href="structdwc__otg__pcd.html#5ea5c519e678fbb382c2ea7d128562c1">dwc_otg_pcd</a><li>setup_pkt_dma_handle
+: <a class="el" href="structdwc__otg__pcd.html#606d94ec61cca4c21e4dc9cb2e3b7064">dwc_otg_pcd</a><li>sftdiscon
+: <a class="el" href="uniondctl__data.html#3416d438405187a683c67f5006f7bfc8">dctl_data</a><li>sgnpinnak
+: <a class="el" href="uniondctl__data.html#2349dad5149cd3fcfd8fe3abcd77c32e">dctl_data</a><li>sgoutnak
+: <a class="el" href="uniondctl__data.html#28bd2f29264841207cd740ce9ec7fa91">dctl_data</a><li>short_read
+: <a class="el" href="structdwc__hc.html#83e9a3cc9075b1fe21a6fa5190fa78c1">dwc_hc</a><li>sleep
+: <a class="el" href="structdwc__otg__pcd__function__ops.html#9b7666c7835bd611f87095d43b104f68">dwc_otg_pcd_function_ops</a><li>sleep_state_resumeok
+: <a class="el" href="unionglpmctl__data.html#3b87473445c87d173f350828a60cacd8">glpmctl_data</a><li>snak
+: <a class="el" href="uniondepctl__data.html#ccf6e60ac8cabde8da36edb19504ba2b">depctl_data</a><li>snp
+: <a class="el" href="uniondepctl__data.html#27d9b0c9fa7b2c1a053d1ec7a1f69962">depctl_data</a><li>snpsid
+: <a class="el" href="structdwc__otg__core__if.html#afc495591efa54c74c1dd50278b57ffe">dwc_otg_core_if</a><li>soffn
+: <a class="el" href="uniondsts__data.html#5a81ac4848c859cbf7d494dc345a0ce8">dsts_data</a><li>sofintr
+: <a class="el" href="uniongintsts__data.html#3f6ba377d6b1449884bb4da1b155c61b">gintsts_data</a>, <a class="el" href="uniongintmsk__data.html#d9cb28e92090a5da3c00d35768d90c82">gintmsk_data</a><li>sp
+: <a class="el" href="uniondev__dma__desc__sts.html#a850ddfa13601227c05e0ae43a538a9d">dev_dma_desc_sts</a><li>spd
+: <a class="el" href="structdwc__otg__dev__if.html#aaabcd21be1be15804b0cf49119ce883">dwc_otg_dev_if</a><li>speed
+: <a class="el" href="structdwc__otg__dev__if.html#8a602da4cbdc4fc88c785471426ed63c">dwc_otg_dev_if</a>, <a class="el" href="structdwc__otg__hcd__function__ops.html#29f9b98c1a824637a5c8aec86649fdd4">dwc_otg_hcd_function_ops</a>, <a class="el" href="structdwc__otg__driver__module__params.html#e0002437cefb2b64dc92f40fd69ef29f">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#d2c4f622f1c14f68c6e60e2603acd09d">dwc_otg_core_params</a>, <a class="el" href="structdwc__hc.html#570b78178975193edb921af1ef36d37b">dwc_hc</a><li>spltena
+: <a class="el" href="unionhcsplt__data.html#8b174930345ac0e5a8a6bd16794836d7">hcsplt_data</a><li>sr
+: <a class="el" href="uniondev__dma__desc__sts.html#88d65d05f6561525543d09d0137c8967">dev_dma_desc_sts</a><li>srp_success
+: <a class="el" href="structdwc__otg__core__if.html#c2bb1913ed3fcc082a06d70242e9768a">dwc_otg_core_if</a><li>srp_timer
+: <a class="el" href="structdwc__otg__pcd.html#466fb6ae524fc970f164701db2e70246">dwc_otg_pcd</a><li>srp_timer_started
+: <a class="el" href="structdwc__otg__core__if.html#749cdeef193b7590b036a9b1d1442b73">dwc_otg_core_if</a><li>srpcap
+: <a class="el" href="uniongusbcfg__data.html#44485a787b8a386fadae801869ce7810">gusbcfg_data</a><li>ssplit_out_xfer_count
+: <a class="el" href="structdwc__otg__qtd.html#badffe465e850133c62c8f7e539f3fca">dwc_otg_qtd</a><li>stall
+: <a class="el" href="unionhcintmsk__data.html#94dc82e231d28d16d21238809cb88f78">hcintmsk_data</a>, <a class="el" href="unionhcint__data.html#cf2fb413e5758e9ebd8914b2f7605d73">hcint_data</a>, <a class="el" href="uniondepctl__data.html#f7ad1bcf91d28b8a4aa8d3a343dd83e4">depctl_data</a><li>stall_clear_flag
+: <a class="el" href="structdwc__ep.html#0d30d306e370810fc819f6ef735c7e67">dwc_ep</a><li>start
+: <a class="el" href="structdwc__otg__hcd__function__ops.html#d74a65269fe5712ac307bfd3230a29b4">dwc_otg_hcd_function_ops</a>, <a class="el" href="structdwc__otg__cil__callbacks.html#ebb662b2e0b4d187648b7f91b9d00713">dwc_otg_cil_callbacks</a><li>start_pkt_count
+: <a class="el" href="structdwc__hc.html#6c030bc725f43025d3046d17b4fbee4e">dwc_hc</a><li>start_split_frame
+: <a class="el" href="structdwc__otg__qh.html#a92b9ff45f0eca459b41ca20e4d8e99c">dwc_otg_qh</a><li>start_xfer_buff
+: <a class="el" href="structdwc__ep.html#d0cda8ded2e5142d9a1c9c17efc5812f">dwc_ep</a><li>start_xfer_tasklet
+: <a class="el" href="structdwc__otg__pcd.html#9b45cd00cd5835aba4236529a04b28f1">dwc_otg_pcd</a><li>startaddr
+: <a class="el" href="unionfifosize__data.html#26d78332a532cf9c0337c89edbff5f1b">fifosize_data</a><li>status
+: <a class="el" href="structdwc__otg__host__dma__desc.html#1b73b25e9fca51dd00fa0607d57d9e3f">dwc_otg_host_dma_desc</a>, <a class="el" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">dwc_otg_dev_dma_desc</a>, <a class="el" href="structdwc__otg__hcd__urb.html#101e4a6762b9911cdb85768890fa1210">dwc_otg_hcd_urb</a>, <a class="el" href="structdwc__otg__hcd__iso__packet__desc.html#d070772c24621c47b49ad21c6acadb94">dwc_otg_hcd_iso_packet_desc</a>, <a class="el" href="structiso__pkt__info.html#1317c3b425c0ef55dbde153b04c28dd4">iso_pkt_info</a><li>status_buf
+: <a class="el" href="structdwc__otg__pcd.html#ca247241f78970f27e5c964fc04d47c8">dwc_otg_pcd</a>, <a class="el" href="structdwc__otg__hcd.html#68627912f0d3672096e6a98be38f66ab">dwc_otg_hcd</a><li>status_buf_dma
+: <a class="el" href="structdwc__otg__hcd.html#3e752b2c5d632d848f3b1fadf543e7a4">dwc_otg_hcd</a><li>status_buf_dma_handle
+: <a class="el" href="structdwc__otg__pcd.html#c3880dd4ce15c515ba37b90b6e7fd293">dwc_otg_pcd</a><li>stop
+: <a class="el" href="structdwc__otg__cil__callbacks.html#cd604365bc84ceda780e10c2344870e4">dwc_otg_cil_callbacks</a><li>stoppclk
+: <a class="el" href="unionpcgcctl__data.html#bf40184845ef70be8e59b2672cb0bedf">pcgcctl_data</a><li>stopped
+: <a class="el" href="structdwc__otg__pcd__ep.html#cce0e089118d8bf7c6278c21ded70d5a">dwc_otg_pcd_ep</a><li>sts
+: <a class="el" href="unionhost__dma__desc__sts.html#828b019082523c4637758bef38805420">host_dma_desc_sts</a>, <a class="el" href="uniondev__dma__desc__sts.html#2be04f03ca64c3484260b2235aef3b9b">dev_dma_desc_sts</a><li>stsphsercvd
+: <a class="el" href="uniondoepint__data.html#038fca8f1c03d7cfe323caa4f8bda126">doepint_data</a><li>sup
+: <a class="el" href="unionhost__dma__desc__sts.html#634060a1b436857e15e8eb8f0d6d000a">host_dma_desc_sts</a><li>supcnt
+: <a class="el" href="uniondeptsiz0__data.html#60123707d51d7dfa22cd6b245402e49b">deptsiz0_data</a><li>suspend
+: <a class="el" href="structdwc__otg__pcd__function__ops.html#fef8ed359353cb84b7c5ac641d54d296">dwc_otg_pcd_function_ops</a>, <a class="el" href="structdwc__otg__cil__callbacks.html#a9e06ccc347fa446e2b131532e203d94">dwc_otg_cil_callbacks</a><li>suspsts
+: <a class="el" href="uniondsts__data.html#4c7cd8ee3877701268846b0b02ac3d97">dsts_data</a><li>sync_frame
+: <a class="el" href="structdwc__ep.html#1b9094ddfba3cddf397fd308cdbf4c81">dwc_ep</a><li>synch_reset_type
+: <a class="el" href="unionhwcfg3__data.html#2aee57ed6a1fb0c63830b9f3b3754373">hwcfg3_data</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/functions_0x74.html b/drivers/usb/host/dwc_otg/doc/html/functions_0x74.html
new file mode 100644
index 000000000000..47f3abe7ec4d
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/functions_0x74.html
@@ -0,0 +1,88 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li id="current"><a href="functions.html"><span>All</span></a></li>
+    <li><a href="functions_func.html"><span>Functions</span></a></li>
+    <li><a href="functions_vars.html"><span>Variables</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions.html#index_a"><span>a</span></a></li>
+    <li><a href="functions_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="functions_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="functions_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="functions_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="functions_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="functions_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="functions_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="functions_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="functions_0x6c.html#index_l"><span>l</span></a></li>
+    <li><a href="functions_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="functions_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="functions_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="functions_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="functions_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="functions_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="functions_0x73.html#index_s"><span>s</span></a></li>
+    <li id="current"><a href="functions_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="functions_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="functions_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="functions_0x77.html#index_w"><span>w</span></a></li>
+    <li><a href="functions_0x78.html#index_x"><span>x</span></a></li>
+  </ul>
+</div>
+
+<p>
+Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:
+<p>
+<h3><a class="anchor" name="index_t">- t -</a></h3><ul>
+<li>td_first
+: <a class="el" href="structdwc__otg__qh.html#3b20e91c00b1de8d42612a8b1250b403">dwc_otg_qh</a><li>td_last
+: <a class="el" href="structdwc__otg__qh.html#9bd6dc808af3f1cab76ae7819af479f9">dwc_otg_qh</a><li>term_sel_dl_pulse
+: <a class="el" href="uniongusbcfg__data.html#d075f50f1d962c57ff491291f66f1778">gusbcfg_data</a><li>test_mode
+: <a class="el" href="structdwc__otg__pcd.html#577c57ee60c2ef42dce7791c85d50394">dwc_otg_pcd</a><li>test_mode_tasklet
+: <a class="el" href="structdwc__otg__pcd.html#d1aed2eb03a93032a1ce80e3145bb81e">dwc_otg_pcd</a><li>thr_ctl
+: <a class="el" href="structdwc__otg__driver__module__params.html#7fe5c7ff692926fb5cbe3b10d4123594">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#1610a4b28bea581c46f251d995bf4a51">dwc_otg_core_params</a><li>timeout
+: <a class="el" href="uniondiepint__data.html#2513e8eef259c711e9a139cb2631b142">diepint_data</a><li>total_fifo_size
+: <a class="el" href="structdwc__otg__core__if.html#cae59008a554cb7de24bd4f2afea7532">dwc_otg_core_if</a><li>total_len
+: <a class="el" href="structdwc__ep.html#5a218f200cff0491b735f43fed5176bf">dwc_ep</a><li>toutcal
+: <a class="el" href="uniongusbcfg__data.html#5dd00ef14661fce822a6ece15cf16799">gusbcfg_data</a><li>ts_dline
+: <a class="el" href="structdwc__otg__driver__module__params.html#25f8f9c3558aa01fecf8bcd1527ee6cc">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#879afefd6e13233a78d74ee71d3ee75e">dwc_otg_core_params</a><li>tstctl
+: <a class="el" href="uniondctl__data.html#ef7a2687eef3086056f30b13f3588f9e">dctl_data</a><li>tx_end_delay
+: <a class="el" href="uniongusbcfg__data.html#581b301bfa1951e1bd8ee20aa7256dc2">gusbcfg_data</a><li>tx_fifo_num
+: <a class="el" href="structdwc__ep.html#ffa14f48094778143353b845b5d238cd">dwc_ep</a><li>tx_fifo_size
+: <a class="el" href="structdwc__otg__dev__if.html#ea32a81a3c0a752e6d6274f8fd6faef9">dwc_otg_dev_if</a><li>tx_msk
+: <a class="el" href="structdwc__otg__core__if.html#b558bae74403677f08e45c692a88d4e2">dwc_otg_core_if</a><li>tx_thr_len
+: <a class="el" href="uniondthrctl__data.html#75959c97b938bf99faa602c933938340">dthrctl_data</a><li>tx_thr_length
+: <a class="el" href="structdwc__otg__dev__if.html#55206f9ce7b0c2614e2c534d01acd6c4">dwc_otg_dev_if</a>, <a class="el" href="structdwc__otg__driver__module__params.html#04d15f44d06c291acfeef82812bd1c65">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#c92fc907d503f9b8bb3600164c520b0e">dwc_otg_core_params</a><li>txbytes
+: <a class="el" href="uniondev__dma__desc__sts.html#56cc3ad6b0e5704c6eb394f58f660eef">dev_dma_desc_sts</a><li>txfflsh
+: <a class="el" href="uniongrstctl__data.html#8a5fcfc953bd0ba61beb36739c70b0ef">grstctl_data</a><li>txfifoundrn
+: <a class="el" href="uniondiepint__data.html#90d0e6a99275eccd4a50f62644de9152">diepint_data</a><li>txfnum
+: <a class="el" href="uniondepctl__data.html#89fd2f9f2183a32181e9a04bf3251c43">depctl_data</a>, <a class="el" href="uniongrstctl__data.html#d074ddfa3331eeb6d088e35f4f627481">grstctl_data</a><li>txfspcavail
+: <a class="el" href="uniondtxfsts__data.html#83db0e2dbe071694f549a383b7037b3b">dtxfsts_data</a><li>txsts
+: <a class="el" href="uniondev__dma__desc__sts.html#30ebc024572822f0803d28c95914a44c">dev_dma_desc_sts</a><li>type
+: <a class="el" href="structdwc__ep.html#17b10677bd9b0a1d612dd4ce2fb0eb0f">dwc_ep</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/functions_0x75.html b/drivers/usb/host/dwc_otg/doc/html/functions_0x75.html
new file mode 100644
index 000000000000..83f1439bda82
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/functions_0x75.html
@@ -0,0 +1,78 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li id="current"><a href="functions.html"><span>All</span></a></li>
+    <li><a href="functions_func.html"><span>Functions</span></a></li>
+    <li><a href="functions_vars.html"><span>Variables</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions.html#index_a"><span>a</span></a></li>
+    <li><a href="functions_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="functions_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="functions_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="functions_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="functions_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="functions_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="functions_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="functions_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="functions_0x6c.html#index_l"><span>l</span></a></li>
+    <li><a href="functions_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="functions_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="functions_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="functions_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="functions_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="functions_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="functions_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="functions_0x74.html#index_t"><span>t</span></a></li>
+    <li id="current"><a href="functions_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="functions_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="functions_0x77.html#index_w"><span>w</span></a></li>
+    <li><a href="functions_0x78.html#index_x"><span>x</span></a></li>
+  </ul>
+</div>
+
+<p>
+Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:
+<p>
+<h3><a class="anchor" name="index_u">- u -</a></h3><ul>
+<li>ulpi_auto_res
+: <a class="el" href="uniongusbcfg__data.html#404cb37d84dd990f4df89fc904bb7a63">gusbcfg_data</a><li>ulpi_clk_sus_m
+: <a class="el" href="uniongusbcfg__data.html#017fa2eb1df13d0917ffc6b243e5064c">gusbcfg_data</a><li>ulpi_ext_vbus_drv
+: <a class="el" href="uniongusbcfg__data.html#f4784a3028f221e2aed6138ecef53048">gusbcfg_data</a><li>ulpi_fs_ls
+: <a class="el" href="structdwc__otg__driver__module__params.html#33489751a5cef9e462d26e92caae3031">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#3d7cfc3c416010102b2c671dfaa828d5">dwc_otg_core_params</a><li>ulpi_fsls
+: <a class="el" href="uniongusbcfg__data.html#de6d061bf2d0d8c909e6f7d701977b73">gusbcfg_data</a><li>ulpi_int_vbus_indicator
+: <a class="el" href="uniongusbcfg__data.html#b71576ecb647b9d81aa8c9b45c9fe14d">gusbcfg_data</a><li>ulpi_utmi_sel
+: <a class="el" href="uniongusbcfg__data.html#f86631568e6d3682cdba6482608bdcfe">gusbcfg_data</a><li>unused
+: <a class="el" href="structdwc__otg__dev__out__ep__regs.html#f78d72b82ee55e6a35cada1bd89d5659">dwc_otg_dev_out_ep_regs</a>, <a class="el" href="structdwc__otg__dev__global__regs.html#8d6452da1d0e266737d77e55fc15f72c">dwc_otg_dev_global_regs</a><li>urb
+: <a class="el" href="structdwc__otg__qtd.html#7e7767808e8eb9d71de0db00f57553f9">dwc_otg_qtd</a><li>usbactep
+: <a class="el" href="uniondepctl__data.html#2ddb1e68ac29dfc383dacd94f76b4710">depctl_data</a><li>usbreset
+: <a class="el" href="uniongintsts__data.html#76926be659d963c79dbcec91e25ce8ed">gintsts_data</a>, <a class="el" href="uniongintmsk__data.html#de79426e6a5436e34cf4b1ac42a72ee6">gintmsk_data</a><li>usbsuspend
+: <a class="el" href="uniongintsts__data.html#de67a7536cdb9305e24f05d771708bce">gintsts_data</a>, <a class="el" href="uniongintmsk__data.html#3b93f1ae00dcd1dcc4d6d19547f26b56">gintmsk_data</a><li>usbtrdtim
+: <a class="el" href="uniongusbcfg__data.html#d3e238db709189683bc41db2a67e9d61">gusbcfg_data</a><li>usecs
+: <a class="el" href="structdwc__otg__qh.html#401de6aadcfc2f99773f44c6731c4646">dwc_otg_qh</a><li>utmi_phy_data_width
+: <a class="el" href="unionhwcfg4__data.html#31e5336f64bdea1bb8e1e358375b20f0">hwcfg4_data</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/functions_0x76.html b/drivers/usb/host/dwc_otg/doc/html/functions_0x76.html
new file mode 100644
index 000000000000..190da71ada6d
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/functions_0x76.html
@@ -0,0 +1,65 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li id="current"><a href="functions.html"><span>All</span></a></li>
+    <li><a href="functions_func.html"><span>Functions</span></a></li>
+    <li><a href="functions_vars.html"><span>Variables</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions.html#index_a"><span>a</span></a></li>
+    <li><a href="functions_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="functions_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="functions_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="functions_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="functions_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="functions_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="functions_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="functions_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="functions_0x6c.html#index_l"><span>l</span></a></li>
+    <li><a href="functions_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="functions_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="functions_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="functions_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="functions_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="functions_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="functions_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="functions_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="functions_0x75.html#index_u"><span>u</span></a></li>
+    <li id="current"><a href="functions_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="functions_0x77.html#index_w"><span>w</span></a></li>
+    <li><a href="functions_0x78.html#index_x"><span>x</span></a></li>
+  </ul>
+</div>
+
+<p>
+Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:
+<p>
+<h3><a class="anchor" name="index_v">- v -</a></h3><ul>
+<li>vbus_valid_filt_en
+: <a class="el" href="unionhwcfg4__data.html#5cbe1c265b6623dff23460111142db7d">hwcfg4_data</a><li>vendor_ctrl_if
+: <a class="el" href="unionhwcfg3__data.html#5008cb6cf85beb23f391e8ccf7306884">hwcfg3_data</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/functions_0x77.html b/drivers/usb/host/dwc_otg/doc/html/functions_0x77.html
new file mode 100644
index 000000000000..e6ef4c8c11f8
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/functions_0x77.html
@@ -0,0 +1,79 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li id="current"><a href="functions.html"><span>All</span></a></li>
+    <li><a href="functions_func.html"><span>Functions</span></a></li>
+    <li><a href="functions_vars.html"><span>Variables</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions.html#index_a"><span>a</span></a></li>
+    <li><a href="functions_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="functions_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="functions_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="functions_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="functions_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="functions_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="functions_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="functions_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="functions_0x6c.html#index_l"><span>l</span></a></li>
+    <li><a href="functions_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="functions_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="functions_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="functions_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="functions_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="functions_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="functions_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="functions_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="functions_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="functions_0x76.html#index_v"><span>v</span></a></li>
+    <li id="current"><a href="functions_0x77.html#index_w"><span>w</span></a></li>
+    <li><a href="functions_0x78.html#index_x"><span>x</span></a></li>
+  </ul>
+</div>
+
+<p>
+Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:
+<p>
+<h3><a class="anchor" name="index_w">- w -</a></h3><ul>
+<li>wCoreID
+: <a class="el" href="structcfi__all__features__header.html#f6840858aad78617369b7decba6ef5e3">cfi_all_features_header</a><li>wDataLength
+: <a class="el" href="structcfi__feature__desc__header.html#0f33193eaf5853b1d3454adce81105d4">cfi_feature_desc_header</a><li>wDepth
+: <a class="el" href="struct__rx__fifo__size__setup.html#a05d30e9417ac8c2ec0fd2c1ec49be71">_rx_fifo_size_setup</a>, <a class="el" href="struct__tx__fifo__size__setup.html#70fb102a57e335dd8ee56096f3a9f99d">_tx_fifo_size_setup</a><li>wFeatureID
+: <a class="el" href="structcfi__feature__desc__header.html#f76e757383a5210368e599f872952170">cfi_feature_desc_header</a><li>wIndex
+: <a class="el" href="structcfi__usb__ctrlrequest.html#984c95bd61e8d1120cd935bcbc5d7134">cfi_usb_ctrlrequest</a><li>wkp_timer
+: <a class="el" href="structdwc__otg__core__if.html#c914461f460deacd426bea7a05ebb204">dwc_otg_core_if</a><li>wkupintr
+: <a class="el" href="uniongintsts__data.html#d2e845fd68f2e8abe6b7445dbde9d2a4">gintsts_data</a>, <a class="el" href="uniongintmsk__data.html#d3cde0fd62a006ec3f5db615f1e62da5">gintmsk_data</a><li>wLength
+: <a class="el" href="structcfi__usb__ctrlrequest.html#60d71d1239e46e787f0b4c626de7c769">cfi_usb_ctrlrequest</a>, <a class="el" href="structcfi__feature__desc__header.html#77769436c06687bdbe98c5e75e7641df">cfi_feature_desc_header</a><li>wNumFeatures
+: <a class="el" href="structcfi__all__features__header.html#e7abb90105e5cfd6ddfe8ba5dfaf8fa1">cfi_all_features_header</a><li>wq_otg
+: <a class="el" href="structdwc__otg__core__if.html#7e3716f6d6bc6f956a45efbe6e308386">dwc_otg_core_if</a><li>wrap_bit
+: <a class="el" href="uniondtknq1__data.html#9ae9021519e7fa501c86093c7718dbb4">dtknq1_data</a><li>wSize
+: <a class="el" href="struct__ddma__concat__buffer__setup__hdr.html#d59713609608ce8aab53c43332073ef7">_ddma_concat_buffer_setup_hdr</a>, <a class="el" href="struct__ddma__sg__buffer__setup.html#728db9bac2db62f7e7b2b9ccb0873546">_ddma_sg_buffer_setup</a><li>wTotalLen
+: <a class="el" href="structcfi__all__features__header.html#3973fa190311671de5bbd74a7b825f42">cfi_all_features_header</a><li>wTxBytes
+: <a class="el" href="struct__ddma__concat__buffer__setup.html#748241a5b55a514f4386498aceb1e505">_ddma_concat_buffer_setup</a><li>wValue
+: <a class="el" href="structcfi__usb__ctrlrequest.html#2f236bbf9450df1a3b5204c4570d883f">cfi_usb_ctrlrequest</a><li>wVersion
+: <a class="el" href="structcfi__all__features__header.html#3542d584c0c68a73351c7d2530f25c6d">cfi_all_features_header</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/functions_0x78.html b/drivers/usb/host/dwc_otg/doc/html/functions_0x78.html
new file mode 100644
index 000000000000..ff6493684113
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/functions_0x78.html
@@ -0,0 +1,77 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li id="current"><a href="functions.html"><span>All</span></a></li>
+    <li><a href="functions_func.html"><span>Functions</span></a></li>
+    <li><a href="functions_vars.html"><span>Variables</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions.html#index_a"><span>a</span></a></li>
+    <li><a href="functions_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="functions_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="functions_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="functions_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="functions_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="functions_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="functions_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="functions_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="functions_0x6c.html#index_l"><span>l</span></a></li>
+    <li><a href="functions_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="functions_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="functions_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="functions_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="functions_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="functions_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="functions_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="functions_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="functions_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="functions_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="functions_0x77.html#index_w"><span>w</span></a></li>
+    <li id="current"><a href="functions_0x78.html#index_x"><span>x</span></a></li>
+  </ul>
+</div>
+
+<p>
+Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:
+<p>
+<h3><a class="anchor" name="index_x">- x -</a></h3><ul>
+<li>xact_pos
+: <a class="el" href="structdwc__hc.html#3cde49a724756e16eb11a027360b2d4b">dwc_hc</a><li>xacterr
+: <a class="el" href="unionhcintmsk__data.html#29686b2c0b9502932327915d690a45d5">hcintmsk_data</a>, <a class="el" href="unionhcint__data.html#86ec2d311ef29228676781f9100d195a">hcint_data</a><li>xactpos
+: <a class="el" href="unionhcsplt__data.html#68e7b96ce2ca96c96f40b4f95c679a11">hcsplt_data</a><li>xcs_xact
+: <a class="el" href="unionhcintmsk__data.html#ace04f1b0f78826b8d33b828d4e637c2">hcintmsk_data</a>, <a class="el" href="unionhcint__data.html#f13613b1a33edddb676d2bce8a35e447">hcint_data</a><li>xfer_buff
+: <a class="el" href="structdwc__hc.html#9dc781cb9e4bc639765beee37ce76673">dwc_hc</a>, <a class="el" href="structdwc__ep.html#97fa9bf5c31ba734d54f70e6fe6ae8eb">dwc_ep</a><li>xfer_buff0
+: <a class="el" href="structdwc__ep.html#b6d727e366ac589d304256c758d2d44a">dwc_ep</a><li>xfer_buff1
+: <a class="el" href="structdwc__ep.html#36ff87362a0da5bce95eaf85522d49ff">dwc_ep</a><li>xfer_count
+: <a class="el" href="structdwc__hc.html#6199aaeab2d64954311c410b30270293">dwc_hc</a>, <a class="el" href="structdwc__ep.html#23d4871510b5bcb54fbf0674d8f122bd">dwc_ep</a><li>xfer_len
+: <a class="el" href="structdwc__hc.html#ce32fe93214f1686896e924fbf61cac7">dwc_hc</a>, <a class="el" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">dwc_ep</a>, <a class="el" href="structcfi__ep.html#f85903cb9e179124e42d98d557098011">cfi_ep</a><li>xfer_size_cntr_width
+: <a class="el" href="unionhwcfg3__data.html#66f311995decf2f11d620aa6a56fa26e">hwcfg3_data</a><li>xfer_started
+: <a class="el" href="structdwc__hc.html#78a1cf134604b24bfdedb4f4df9f2c1f">dwc_hc</a><li>xfercomp
+: <a class="el" href="unionhcint__data.html#49385cb90c4d8c003cfac91175a646e0">hcint_data</a><li>xfercompl
+: <a class="el" href="unionhcintmsk__data.html#4983a78156d96d9a0c16ca8ea2b09106">hcintmsk_data</a>, <a class="el" href="uniondoepint__data.html#341f7ffa5a9da7f6b1e09e9f4cc516a3">doepint_data</a>, <a class="el" href="uniondiepint__data.html#56e1252841323973e0ada12cc89059c9">diepint_data</a><li>xfersize
+: <a class="el" href="unionhctsiz__data.html#6ad01d874d77aa4382f71fa68eaec12d">hctsiz_data</a>, <a class="el" href="uniondeptsiz0__data.html#1792e672dde70ead19bd0f5e7642af03">deptsiz0_data</a>, <a class="el" href="uniondeptsiz__data.html#cf06327d851e7cfe5c442b29bf2d6fa4">deptsiz_data</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/functions_func.html b/drivers/usb/host/dwc_otg/doc/html/functions_func.html
new file mode 100644
index 000000000000..3689a322990a
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/functions_func.html
@@ -0,0 +1,36 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Functions</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions.html"><span>All</span></a></li>
+    <li id="current"><a href="functions_func.html"><span>Functions</span></a></li>
+    <li><a href="functions_vars.html"><span>Variables</span></a></li>
+  </ul>
+</div>
+&nbsp;
+<p>
+<ul>
+<li>DWC_CIRCLEQ_ENTRY()
+: <a class="el" href="structdwc__otg__qtd.html#aac18e92835ac0678a83d023660f1560">dwc_otg_qtd</a>, <a class="el" href="structdwc__hc.html#bf81e1a0c0ae06faf445a61b950e24f5">dwc_hc</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/functions_vars.html b/drivers/usb/host/dwc_otg/doc/html/functions_vars.html
new file mode 100644
index 000000000000..61581963e0f4
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/functions_vars.html
@@ -0,0 +1,82 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions.html"><span>All</span></a></li>
+    <li><a href="functions_func.html"><span>Functions</span></a></li>
+    <li id="current"><a href="functions_vars.html"><span>Variables</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li id="current"><a href="functions_vars.html#index_a"><span>a</span></a></li>
+    <li><a href="functions_vars_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="functions_vars_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="functions_vars_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="functions_vars_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="functions_vars_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="functions_vars_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="functions_vars_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="functions_vars_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="functions_vars_0x6c.html#index_l"><span>l</span></a></li>
+    <li><a href="functions_vars_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="functions_vars_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="functions_vars_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="functions_vars_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="functions_vars_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="functions_vars_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="functions_vars_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="functions_vars_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="functions_vars_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="functions_vars_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="functions_vars_0x77.html#index_w"><span>w</span></a></li>
+    <li><a href="functions_vars_0x78.html#index_x"><span>x</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_a">- a -</a></h3><ul>
+<li>a
+: <a class="el" href="unionhost__dma__desc__sts.html#1c4cf70718c94a1a847e52d4dd65cbb0">host_dma_desc_sts</a><li>a_alt_hnp_support
+: <a class="el" href="structdwc__otg__pcd.html#49f2d2b04a4c07a8d53643f7681b5405">dwc_otg_pcd</a><li>a_hnp_support
+: <a class="el" href="structdwc__otg__pcd.html#e8008719644bdc23040f1a1545b7117f">dwc_otg_pcd</a><li>a_qtd
+: <a class="el" href="unionhost__dma__desc__sts.html#c6ec29eb4bc0c9e165b3d09b951b4d13">host_dma_desc_sts</a><li>a_valid_filt_en
+: <a class="el" href="unionhwcfg4__data.html#109cd4df5b8b9035bf37aae2cbcbc15e">hwcfg4_data</a><li>ack
+: <a class="el" href="unionhcintmsk__data.html#8d3388818a6dc098a1e1c64147d1ced9">hcintmsk_data</a>, <a class="el" href="unionhcint__data.html#729749d6d0b5a1d4c449287f9efdd5fe">hcint_data</a>, <a class="el" href="uniongi2cctl__data.html#58c5fecd71f1bf68dc3e6939e5b56335">gi2cctl_data</a><li>active
+: <a class="el" href="structdwc__ep.html#63b7a1a3ee32df393ff10d8bfc5c8648">dwc_ep</a><li>active_eps
+: <a class="el" href="structcfiobject.html#82805f011abf3deace7faa159729229a">cfiobject</a><li>actual
+: <a class="el" href="structdwc__otg__pcd__request.html#0fd7d659f353273d8b2b22027306a2a2">dwc_otg_pcd_request</a><li>actual_length
+: <a class="el" href="structdwc__otg__hcd__urb.html#742c8a97d3867ab89148eae34e0c73a6">dwc_otg_hcd_urb</a>, <a class="el" href="structdwc__otg__hcd__iso__packet__desc.html#c00b967f4c613820b99efc0abda5178c">dwc_otg_hcd_iso_packet_desc</a><li>addr
+: <a class="el" href="uniongi2cctl__data.html#5641294f472040bc6c4f7e70e84500f0">gi2cctl_data</a>, <a class="el" href="structcfi__dma__buff.html#549d40f7e33056fc5a99d51d00714d97">cfi_dma_buff</a><li>adevtoutchng
+: <a class="el" href="uniongotgint__data.html#f216cb4939e1a348fbffaff87fc42772">gotgint_data</a><li>ahb_thr_ratio
+: <a class="el" href="uniondthrctl__data.html#00bbf39ee16616cc14410549c1e97c45">dthrctl_data</a>, <a class="el" href="structdwc__otg__driver__module__params.html#b450246efcbc087eb36b0979040162ca">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#8787af52f8d70a9100ab1fa2b0f69bfb">dwc_otg_core_params</a><li>ahberr
+: <a class="el" href="unionhcintmsk__data.html#bd9e228b6cb8e60cdbefd4bb57bdcc33">hcintmsk_data</a>, <a class="el" href="unionhcint__data.html#f953465ff02c518a52c48d4d6b1c09c7">hcint_data</a>, <a class="el" href="uniondoepint__data.html#cdfedbad6643d94271e91e135485a68d">doepint_data</a>, <a class="el" href="uniondiepint__data.html#6d57fa84f687bc4f05013c1e1a7edf29">diepint_data</a><li>ahbidle
+: <a class="el" href="uniongrstctl__data.html#587c5ec6713e2626db517105ab9aea3e">grstctl_data</a><li>align_buff
+: <a class="el" href="structdwc__hc.html#e0c3ba51a04b36656baa4e70fc63cf77">dwc_hc</a><li>appl_resp
+: <a class="el" href="unionglpmctl__data.html#1898203022af680f08036de89e86e4b0">glpmctl_data</a><li>architecture
+: <a class="el" href="unionhwcfg2__data.html#e5000f58c6a0f09c75375b4c912af0eb">hwcfg2_data</a><li>asesvld
+: <a class="el" href="uniongotgctl__data.html#e16505965a031d2e488a26378a14a834">gotgctl_data</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x62.html b/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x62.html
new file mode 100644
index 000000000000..a81951d30054
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x62.html
@@ -0,0 +1,99 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions.html"><span>All</span></a></li>
+    <li><a href="functions_func.html"><span>Functions</span></a></li>
+    <li id="current"><a href="functions_vars.html"><span>Variables</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions_vars.html#index_a"><span>a</span></a></li>
+    <li id="current"><a href="functions_vars_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="functions_vars_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="functions_vars_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="functions_vars_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="functions_vars_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="functions_vars_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="functions_vars_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="functions_vars_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="functions_vars_0x6c.html#index_l"><span>l</span></a></li>
+    <li><a href="functions_vars_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="functions_vars_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="functions_vars_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="functions_vars_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="functions_vars_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="functions_vars_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="functions_vars_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="functions_vars_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="functions_vars_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="functions_vars_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="functions_vars_0x77.html#index_w"><span>w</span></a></li>
+    <li><a href="functions_vars_0x78.html#index_x"><span>x</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_b">- b -</a></h3><ul>
+<li>b
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+: <a class="el" href="uniondev__dma__desc__sts.html#324fdd57830243334b74e0579b4e9f96">dev_dma_desc_sts</a><li>b_iso_out
+: <a class="el" href="uniondev__dma__desc__sts.html#214ba099b6077c3393b179cf9a7909f7">dev_dma_desc_sts</a><li>b_valid_filt_en
+: <a class="el" href="unionhwcfg4__data.html#2f741788949e2fea24c129b1a4e10331">hwcfg4_data</a><li>babble
+: <a class="el" href="uniondoepint__data.html#c555371bda41092d89992523563dadbb">doepint_data</a><li>back2backsetup
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+: <a class="el" href="struct__ddma__sg__buffer__setup.html#6287daf5a964bf1d09e8ffca29b88748">_ddma_sg_buffer_setup</a><li>bDescCount
+: <a class="el" href="struct__ddma__concat__buffer__setup__hdr.html#605becc1e8a681d6623343b28013b56a">_ddma_concat_buffer_setup_hdr</a><li>bEndpointAddress
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+: <a class="el" href="structdwc__ep.html#d9e9ffe348764ababc3165ed04f9ec6c">dwc_ep</a><li>bm_align
+: <a class="el" href="structcfi__ep.html#bb544b7938d0c62857fc3726988310d2">cfi_ep</a><li>bm_circ
+: <a class="el" href="structcfi__ep.html#3ab8ca6103c0483f2fefce0dc1684eaa">cfi_ep</a><li>bm_concat
+: <a class="el" href="structcfi__ep.html#4c83b9bb5a75e6b81fbfa86b51736164">cfi_ep</a><li>bm_sg
+: <a class="el" href="structcfi__ep.html#4010b0f12bf1cd37a2c0bf06b392570a">cfi_ep</a><li>bmAttributes
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+: <a class="el" href="structcfi__feature__desc__header.html#4e90b7a616a2efc24937fc6d5cff1347">cfi_feature_desc_header</a><li>bOffset
+: <a class="el" href="struct__ddma__sg__buffer__setup.html#5ab16a208d20dd6940ecfd3244e2b9c0">_ddma_sg_buffer_setup</a><li>bOutEndpointAddress
+: <a class="el" href="struct__ddma__sg__buffer__setup.html#b61eaff3e4857fd6223d9fc678814786">_ddma_sg_buffer_setup</a><li>bRequest
+: <a class="el" href="structcfi__usb__ctrlrequest.html#b3083f525fa9bb97e41364418daee3fa">cfi_usb_ctrlrequest</a><li>bRequestType
+: <a class="el" href="structcfi__usb__ctrlrequest.html#6ba267845c2907b3908d3761c252b10c">cfi_usb_ctrlrequest</a><li>bs
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+: <a class="el" href="uniongotgctl__data.html#69931c3759421d5eb6f91d4c9da4dddd">gotgctl_data</a><li>bsydne
+: <a class="el" href="uniongi2cctl__data.html#b28daedf73bcb4d651f8fbc03bb69778">gi2cctl_data</a><li>buf
+: <a class="el" href="structdwc__otg__host__dma__desc.html#fdc395094e1a1f9bb89c316a96d4b96b">dwc_otg_host_dma_desc</a>, <a class="el" href="structdwc__otg__dev__dma__desc.html#0454dad420ef536fe5eb7c38ef764430">dwc_otg_dev_dma_desc</a>, <a class="el" href="structdwc__otg__pcd__request.html#c46438f3d95146654a25cd219d7a1d5a">dwc_otg_pcd_request</a>, <a class="el" href="structdwc__otg__hcd__urb.html#99ae35ffcd6147ddb93b361ab3bcfe95">dwc_otg_hcd_urb</a>, <a class="el" href="structcfi__dma__buff.html#474851b3123373b8b30fa3637eb81b5b">cfi_dma_buff</a><li>buf_in
+: <a class="el" href="structcfiobject.html#f6548b2b8fbab90656c22eb5ca857643">cfiobject</a><li>buf_out
+: <a class="el" href="structcfiobject.html#adaa1cd0f88e639251f8dfbd65da7935">cfiobject</a><li>buf_proc_intrvl
+: <a class="el" href="structdwc__ep.html#4638b25387e59a5a4721a503b5279dfc">dwc_ep</a><li>bytes
+: <a class="el" href="uniondev__dma__desc__sts.html#9b6181d78984cb4d853945774f300ef0">dev_dma_desc_sts</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
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--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x63.html
@@ -0,0 +1,110 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions.html"><span>All</span></a></li>
+    <li><a href="functions_func.html"><span>Functions</span></a></li>
+    <li id="current"><a href="functions_vars.html"><span>Variables</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions_vars.html#index_a"><span>a</span></a></li>
+    <li><a href="functions_vars_0x62.html#index_b"><span>b</span></a></li>
+    <li id="current"><a href="functions_vars_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="functions_vars_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="functions_vars_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="functions_vars_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="functions_vars_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="functions_vars_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="functions_vars_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="functions_vars_0x6c.html#index_l"><span>l</span></a></li>
+    <li><a href="functions_vars_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="functions_vars_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="functions_vars_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="functions_vars_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="functions_vars_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="functions_vars_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="functions_vars_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="functions_vars_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="functions_vars_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="functions_vars_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="functions_vars_0x77.html#index_w"><span>w</span></a></li>
+    <li><a href="functions_vars_0x78.html#index_x"><span>x</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_c">- c -</a></h3><ul>
+<li>cfi_setup
+: <a class="el" href="structdwc__otg__pcd__function__ops.html#e717e78fcf05e0de9c6d478fee1afa87">dwc_otg_pcd_function_ops</a><li>cgnpinnak
+: <a class="el" href="uniondctl__data.html#6feecf1184cd67b8b8ede2e2030a5dba">dctl_data</a><li>cgoutnak
+: <a class="el" href="uniondctl__data.html#7ffb7af3cfeb7efb811eb3c7fa7f3440">dctl_data</a><li>ch0
+: <a class="el" href="unionhaintmsk__data.html#dd096952e3d38ffa5db796e3a7334e7b">haintmsk_data</a>, <a class="el" href="unionhaint__data.html#4518de0451164b403fd446119606c798">haint_data</a><li>ch1
+: <a class="el" href="unionhaintmsk__data.html#c79960e27bba0c730936148272b14d3b">haintmsk_data</a>, <a class="el" href="unionhaint__data.html#111c951f2c033e42b8d341f968ccc387">haint_data</a><li>ch10
+: <a class="el" href="unionhaintmsk__data.html#e815617fd288b134798fa5e2dd23af67">haintmsk_data</a>, <a class="el" href="unionhaint__data.html#07c1c428e4e756aa65338659fc2f20d1">haint_data</a><li>ch11
+: <a class="el" href="unionhaintmsk__data.html#51e0430615e457c51a8f12f3c8c6246b">haintmsk_data</a>, <a class="el" href="unionhaint__data.html#5234dd8c3b0aa7d46154aa89f6fe2635">haint_data</a><li>ch12
+: <a class="el" href="unionhaintmsk__data.html#a7e151fe0676bde7a2ac43ee5b6f1b73">haintmsk_data</a>, <a class="el" href="unionhaint__data.html#43ab83f803054d0a5557471380186f8f">haint_data</a><li>ch13
+: <a class="el" href="unionhaintmsk__data.html#3ad05d0ef4e63250fc7b3af9f1654271">haintmsk_data</a>, <a class="el" href="unionhaint__data.html#7764f0ba6f46901a0c800dcc8c158643">haint_data</a><li>ch14
+: <a class="el" href="unionhaintmsk__data.html#3f0cf3851a6f6b74c33a71a3b255372b">haintmsk_data</a>, <a class="el" href="unionhaint__data.html#46a15c2faf17d049b71fcd46d1a58842">haint_data</a><li>ch15
+: <a class="el" href="unionhaintmsk__data.html#da69c5905fb9a16f50f9a0a8c0c9b125">haintmsk_data</a>, <a class="el" href="unionhaint__data.html#58435a2988a1d8a2dd11c64b8246bfcf">haint_data</a><li>ch2
+: <a class="el" href="unionhaintmsk__data.html#0ecac53d912d941c9139af6591f93261">haintmsk_data</a>, <a class="el" href="unionhaint__data.html#4f22391988e52ce0cf4c26114352d491">haint_data</a><li>ch3
+: <a class="el" href="unionhaintmsk__data.html#40feb12ac2af27dfb5772dcaec2c17c2">haintmsk_data</a>, <a class="el" href="unionhaint__data.html#595c465c0d89f2fc5b213436243f3301">haint_data</a><li>ch4
+: <a class="el" href="unionhaintmsk__data.html#5692699f367a57de45bab48856a35624">haintmsk_data</a>, <a class="el" href="unionhaint__data.html#daec53008bfef01a4eae6a287476be28">haint_data</a><li>ch5
+: <a class="el" href="unionhaintmsk__data.html#e49e1e6e4bea7ee8375c7e9da57d0217">haintmsk_data</a>, <a class="el" href="unionhaint__data.html#236e813b0d2c40105d98eabaaa83668a">haint_data</a><li>ch6
+: <a class="el" href="unionhaintmsk__data.html#df9d27f0be312e3c56cbd20736cb8e07">haintmsk_data</a>, <a class="el" href="unionhaint__data.html#4b32ecbff1ca92fb9a6ed7c85163b068">haint_data</a><li>ch7
+: <a class="el" href="unionhaintmsk__data.html#df61ec0f4ee97164b1a1aa1d8d0bd4b8">haintmsk_data</a>, <a class="el" href="unionhaint__data.html#858da0223b1c8c714704083fc3bb8716">haint_data</a><li>ch8
+: <a class="el" href="unionhaintmsk__data.html#1c05566d9af4c7401cc95ed613b62252">haintmsk_data</a>, <a class="el" href="unionhaint__data.html#a2b5aa5c0ad6f2ddd237f2fc4d5772f5">haint_data</a><li>ch9
+: <a class="el" href="unionhaintmsk__data.html#f12b0a59f2e663d15e9f69866c5bf701">haintmsk_data</a>, <a class="el" href="unionhaint__data.html#991c29e3cf0a85ef17178df828fd1474">haint_data</a><li>channel
+: <a class="el" href="structdwc__otg__qh.html#bbdb7d30b60b6c326301f33b35088bb4">dwc_otg_qh</a><li>chdis
+: <a class="el" href="unionhcchar__data.html#73c9f7f3cc4036c72ef341d1d1d9c388">hcchar_data</a><li>chen
+: <a class="el" href="unionhcchar__data.html#994a5305780edb0c4fe159b6cc7b14ae">hcchar_data</a><li>chhltd
+: <a class="el" href="unionhcintmsk__data.html#2549a84a06f4f6a7ad6fed50fcf7b068">hcintmsk_data</a>, <a class="el" href="unionhcint__data.html#b93ceab913a49e33c5bf4dde0e62d75a">hcint_data</a><li>chint
+: <a class="el" href="unionhaintmsk__data.html#80030e17495460223602afd3aad1287c">haintmsk_data</a>, <a class="el" href="unionhaint__data.html#6824b5b98c861cbc8efe3ba9f70cfea0">haint_data</a><li>chnum
+: <a class="el" href="unionhost__grxsts__data.html#684095394d11ec74a327f945c9e678bf">host_grxsts_data</a><li>cnak
+: <a class="el" href="uniondepctl__data.html#0b87d0914ceee7a20ffd2d7510b6a72e">depctl_data</a><li>common_irq_installed
+: <a class="el" href="structdwc__otg__device.html#80bfe5405d4146d3edca4e3eb2f9239b">dwc_otg_device</a><li>complete
+: <a class="el" href="structdwc__otg__pcd__function__ops.html#126db5e83cd3cc03f303eb3da668816f">dwc_otg_pcd_function_ops</a>, <a class="el" href="structdwc__otg__hcd__function__ops.html#09a989481103de7468cd46ef61ace0ce">dwc_otg_hcd_function_ops</a><li>complete_split
+: <a class="el" href="structdwc__otg__qtd.html#6355e968a4d36edce3e22c89ac7b5001">dwc_otg_qtd</a>, <a class="el" href="structdwc__hc.html#21e00df6fb9a555975879526118d599e">dwc_hc</a><li>compsplt
+: <a class="el" href="unionhcsplt__data.html#0a4855eb44ec93ec47dcc218a8703e94">hcsplt_data</a><li>config
+: <a class="el" href="structzero__dev.html#2481a8df9867ab54361cf4ffc7267484">zero_dev</a><li>conidsts
+: <a class="el" href="uniongotgctl__data.html#777151f3c8c1b3117493aee2cd7a2e5c">gotgctl_data</a><li>conidstschng
+: <a class="el" href="uniongintsts__data.html#86b8b53e53486db96a8faf6307c248df">gintsts_data</a>, <a class="el" href="uniongintmsk__data.html#ade723f4f136cfa884e5bf536d913f14">gintmsk_data</a><li>conn_timer
+: <a class="el" href="structdwc__otg__hcd.html#de7796a41bb7d1e45ed9dbc20c995342">dwc_otg_hcd</a><li>connect
+: <a class="el" href="structdwc__otg__pcd__function__ops.html#4d3df508947b8ba75c5537617227cf9c">dwc_otg_pcd_function_ops</a><li>control_phase
+: <a class="el" href="structdwc__otg__qtd.html#5189ec9c992974d20477481eaf96d0bb">dwc_otg_qtd</a><li>core_global_regs
+: <a class="el" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">dwc_otg_core_if</a><li>core_if
+: <a class="el" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">dwc_otg_pcd</a>, <a class="el" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">dwc_otg_hcd</a>, <a class="el" href="structdwc__otg__device.html#4cc7c9f6e473072c2ed0a5e6adb25ebe">dwc_otg_device</a><li>core_params
+: <a class="el" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">dwc_otg_core_if</a><li>csftrst
+: <a class="el" href="uniongrstctl__data.html#82df3462742f67d18b2964fafc0d9c02">grstctl_data</a><li>ctd
+: <a class="el" href="unionhcdma__data.html#d1238e3a2f81540362765b3e6a29d7de">hcdma_data</a><li>ctrl_req
+: <a class="el" href="structcfiobject.html#a86c33aef2a521a27ca515bb7397dd34">cfiobject</a><li>cur_pkt
+: <a class="el" href="structdwc__ep.html#d4e63c7d944c2b48260b4a75c2b58925">dwc_ep</a><li>cur_pkt_addr
+: <a class="el" href="structdwc__ep.html#d3bc23598a77d3cca52c70a28afc6b5e">dwc_ep</a><li>cur_pkt_dma_addr
+: <a class="el" href="structdwc__ep.html#ed4594c9f6c2bcbcf6f1bbe9e9c64061">dwc_ep</a><li>curmode
+: <a class="el" href="uniongintsts__data.html#f0815c8bea0a37c98b12a08481b2980c">gintsts_data</a><li>currmod
+: <a class="el" href="uniongotgctl__data.html#540a9022e5ff38c2a656b8ebd59070cb">gotgctl_data</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x64.html b/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x64.html
new file mode 100644
index 000000000000..75410e1d972a
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x64.html
@@ -0,0 +1,157 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions.html"><span>All</span></a></li>
+    <li><a href="functions_func.html"><span>Functions</span></a></li>
+    <li id="current"><a href="functions_vars.html"><span>Variables</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions_vars.html#index_a"><span>a</span></a></li>
+    <li><a href="functions_vars_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="functions_vars_0x63.html#index_c"><span>c</span></a></li>
+    <li id="current"><a href="functions_vars_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="functions_vars_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="functions_vars_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="functions_vars_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="functions_vars_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="functions_vars_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="functions_vars_0x6c.html#index_l"><span>l</span></a></li>
+    <li><a href="functions_vars_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="functions_vars_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="functions_vars_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="functions_vars_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="functions_vars_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="functions_vars_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="functions_vars_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="functions_vars_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="functions_vars_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="functions_vars_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="functions_vars_0x77.html#index_w"><span>w</span></a></li>
+    <li><a href="functions_vars_0x78.html#index_x"><span>x</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_d">- d -</a></h3><ul>
+<li>d32
+: <a class="el" href="unionpcgcctl__data.html#abe048ee884143501929b27d94c52db7">pcgcctl_data</a>, <a class="el" href="unionhost__dma__desc__sts.html#c8e191345883c19b7127e54479c75e4d">host_dma_desc_sts</a>, <a class="el" href="unionhcdma__data.html#27b804015f09ea7eb25f602cc6dbdda9">hcdma_data</a>, <a class="el" href="unionhctsiz__data.html#fb41950555c60c6015294bdefe9cd39d">hctsiz_data</a>, <a class="el" href="unionhcintmsk__data.html#8868299fcc762e005b7f0bf67e5fbe30">hcintmsk_data</a>, <a class="el" href="unionhcint__data.html#05a82fa7693f875622db744716d7f73e">hcint_data</a>, <a class="el" href="unionhcsplt__data.html#0cd235b445ff681b846f5dccf24fd644">hcsplt_data</a>, <a class="el" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">hcchar_data</a>, <a class="el" href="unionhaintmsk__data.html#65f3e5dbc7a62b6fb57426abaaffc6a2">haintmsk_data</a>, <a class="el" href="unionhaint__data.html#c83834650d2981b44274a89dda63a0f5">haint_data</a>, <a class="el" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">hprt0_data</a>, <a class="el" href="unionhptxsts__data.html#b48d41d449d8f71c0b184b38029c26bc">hptxsts_data</a>, <a class="el" href="unionhfnum__data.html#e5ccbed3af86ac88577ded328e6c9932">hfnum_data</a>, <a class="el" href="unionhfir__data.html#859d5325dbf422643fb86695328c206d">hfir_data</a>, <a class="el" href="unionhcfg__data.html#381a253b3a38a7f943dcbb42f7bf10be">hcfg_data</a>, <a class="el" href="uniondev__dma__desc__sts.html#fb77b9c4ab63304073542ed2b118a64b">dev_dma_desc_sts</a>, <a class="el" href="uniondeptsiz0__data.html#a06fa9b1dcaee47fba9cf869027ed6f1">deptsiz0_data</a>, <a class="el" href="uniondeptsiz__data.html#10c2b2ba8b419b0a766430a59befbbe0">deptsiz_data</a>, <a class="el" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">depctl_data</a>, <a class="el" href="uniondthrctl__data.html#f66c52fe9278bb6ed52c811ddbed16a5">dthrctl_data</a>, <a class="el" href="uniondtknq1__data.html#86015789f75da8cd507db3766fe93fef">dtknq1_data</a>, <a class="el" href="uniondaint__data.html#cf05e79bf751384bef904448a231bc41">daint_data</a>, <a class="el" href="uniondoepint__data.html#94f8c8fc116b430565f9322e3621b3a5">doepint_data</a>, <a class="el" href="uniondiepint__data.html#7d2c24507663bf96c280c57fbf544ef7">diepint_data</a>, <a class="el" href="uniondsts__data.html#0f126daef735b142b06dbc4cdbe13814">dsts_data</a>, <a class="el" href="uniondctl__data.html#f49aadfd7ad95b570115b3c245b1729e">dctl_data</a>, <a class="el" href="uniondcfg__data.html#efd84d3306db1b4370535a0e814612dc">dcfg_data</a>, <a class="el" href="unionhwcfg4__data.html#edcdf66b3add0e05ce0006b0b0de8dd0">hwcfg4_data</a>, <a class="el" href="unionhwcfg3__data.html#9daf160f3fc0cc8e4e68c037f6c2f9d7">hwcfg3_data</a>, <a class="el" href="unionhwcfg2__data.html#2a2482b24bbfa8cdd589e376184d1e3b">hwcfg2_data</a>, <a class="el" href="unionhwcfg1__data.html#9ca836052f9bd01e0b70902862ed09a4">hwcfg1_data</a>, <a class="el" href="uniongi2cctl__data.html#97e9ae4e52d9bd9370027b5da5f65787">gi2cctl_data</a>, <a class="el" href="uniondtxfsts__data.html#684b8a9ccf83a5807e9bb3491c662c39">dtxfsts_data</a>, <a class="el" href="uniongnptxsts__data.html#a58b5adbe6bd0344c4f585ef6aba4672">gnptxsts_data</a>, <a class="el" href="unionfifosize__data.html#937e01b91f0a60a5aa9f6a4eaf6ce661">fifosize_data</a>, <a class="el" href="unionhost__grxsts__data.html#993969735da9c3615652391aae76359a">host_grxsts_data</a>, <a class="el" href="uniondevice__grxsts__data.html#9d454f39c05e23d376dfb0069d933986">device_grxsts_data</a>, <a class="el" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">gintsts_data</a>, <a class="el" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">gintmsk_data</a>, <a class="el" href="uniongrstctl__data.html#d89d99c95bd5177fbd879d38963d3e62">grstctl_data</a>, <a class="el" href="unionglpmctl__data.html#cd41461734ff898209bfb64057ef2eb8">glpmctl_data</a>, <a class="el" href="uniongusbcfg__data.html#c3d8f2d95fd61a172eb108cb72a85b47">gusbcfg_data</a>, <a class="el" href="uniongahbcfg__data.html#2532b75f838946009af8806c924f0c08">gahbcfg_data</a>, <a class="el" href="uniongotgint__data.html#8a343df4fc4e68b802be7629864308e2">gotgint_data</a>, <a class="el" href="uniongotgctl__data.html#ebb591ab40ff41f0e06f03a795647d33">gotgctl_data</a>, <a class="el" href="structdwc__otg__pcd.html#e4fe210f7a18b9f0c393af9cdf282d56">dwc_otg_pcd</a>, <a class="el" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#95ad2033c30d79c28ffcfa6df44af1d5">dwc_otg_hcd::dwc_otg_hcd_internal_flags</a><li>daint
+: <a class="el" href="structdwc__otg__dev__global__regs.html#2e25df2fbec9d398742709524056cbd5">dwc_otg_dev_global_regs</a><li>daintmsk
+: <a class="el" href="structdwc__otg__dev__global__regs.html#5def6c3850c041928b9a662422ee0679">dwc_otg_dev_global_regs</a><li>data
+: <a class="el" href="structcfi__usb__ctrlrequest.html#5b3865e9cb2c0fcf373b1c862a63c180">cfi_usb_ctrlrequest</a><li>data_fifo
+: <a class="el" href="structdwc__otg__core__if.html#f99c868784a8269073bc251f88d92ee4">dwc_otg_core_if</a><li>data_fifo_size
+: <a class="el" href="structdwc__otg__driver__module__params.html#a9ae5039d88c52fab455235bf4f8696b">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#3d8dc206f54165f52c7f8599731d0f95">dwc_otg_core_params</a><li>data_pattern_frame
+: <a class="el" href="structdwc__ep.html#c505483882bd67a7b0076851f693f2cc">dwc_ep</a><li>data_per_frame
+: <a class="el" href="structdwc__ep.html#4672369f4724db642856d72d5048213e">dwc_ep</a><li>data_pid_start
+: <a class="el" href="structdwc__hc.html#513427c5e8c4603ba344d4e7f9191064">dwc_hc</a>, <a class="el" href="structdwc__ep.html#4ceafa9e067ba462ab38c20ffcf8d597">dwc_ep</a><li>data_toggle
+: <a class="el" href="structdwc__otg__qh.html#b0e001bfd76f5781926795ac47ef2c25">dwc_otg_qh</a>, <a class="el" href="structdwc__otg__qtd.html#e912f256e01165b573c26262247a5eff">dwc_otg_qtd</a><li>datatglerr
+: <a class="el" href="unionhcintmsk__data.html#60bbf3878314aad41055137e348cc01d">hcintmsk_data</a>, <a class="el" href="unionhcint__data.html#2fc8618d16e6908e99c8cca3ffb54736">hcint_data</a><li>dcfg
+: <a class="el" href="structdwc__otg__dev__global__regs.html#c0c24937bbd7184884f05343f56ef1da">dwc_otg_dev_global_regs</a>, <a class="el" href="structdwc__otg__core__if.html#fcce854acc5b4afca80bd5667ecc4ef2">dwc_otg_core_if</a><li>dctl
+: <a class="el" href="structdwc__otg__dev__global__regs.html#3779c2fc508920a831a59e696a8fa785">dwc_otg_dev_global_regs</a><li>ddrsel
+: <a class="el" href="uniongusbcfg__data.html#e6dc05942f880adfaee600bc9e0ba33b">gusbcfg_data</a><li>deachint
+: <a class="el" href="structdwc__otg__dev__global__regs.html#4795bc8eab569241a3f8e6aad5d99ac7">dwc_otg_dev_global_regs</a><li>deachintmsk
+: <a class="el" href="structdwc__otg__dev__global__regs.html#e64a153683f0e0cda14b56a163651825">dwc_otg_dev_global_regs</a><li>debdone
+: <a class="el" href="uniongotgint__data.html#7bac6821d07d401731213dc0e94852ca">gotgint_data</a><li>ded_fifo_en
+: <a class="el" href="unionhwcfg4__data.html#175e8897d6e3c8ef4026413943de503b">hwcfg4_data</a><li>deep_sleep
+: <a class="el" href="unionpcgcctl__data.html#07232b66695a6bcba4c89477ef13130f">pcgcctl_data</a><li>depth
+: <a class="el" href="unionfifosize__data.html#48c08d73da4d2d16d4320b93beb5ba8b">fifosize_data</a><li>desc
+: <a class="el" href="structdwc__otg__pcd__ep.html#86e27843c439dd0b1d12d9bf2dc6516f">dwc_otg_pcd_ep</a><li>desc_addr
+: <a class="el" href="structdwc__ep.html#57e934b26e76939912eaa76321075a0d">dwc_ep</a><li>desc_cnt
+: <a class="el" href="structdwc__ep.html#5e5bfcc93d41670bc0d29ad5f0f35871">dwc_ep</a><li>desc_count
+: <a class="el" href="structcfi__ep.html#73050a3011b918e8be6c2434db357514">cfi_ep</a><li>desc_dma
+: <a class="el" href="unionhwcfg4__data.html#988888a48e9088d0e9f889818eb63509">hwcfg4_data</a><li>desc_dma_dyn
+: <a class="el" href="unionhwcfg4__data.html#9562305cf5dd89816939792a66879542">hwcfg4_data</a><li>desc_list
+: <a class="el" href="structdwc__otg__qh.html#0e5f35688e54ba97054a1a7576e81150">dwc_otg_qh</a><li>desc_list_addr
+: <a class="el" href="structdwc__hc.html#f3001addf65df4d3c6a5c685d7637efd">dwc_hc</a><li>desc_list_dma
+: <a class="el" href="structdwc__otg__qh.html#c31412bb35362e77c697352fd4c3eeaf">dwc_otg_qh</a><li>descdma
+: <a class="el" href="unionhcfg__data.html#7ec04d77b1c0d3cc25165e77e9bce5f4">hcfg_data</a>, <a class="el" href="uniondcfg__data.html#d83666dcf5675453a387915ce1653d54">dcfg_data</a><li>dev_addr
+: <a class="el" href="structdwc__otg__hcd__pipe__info.html#3812ead0191c9b3bebf48fe8ea370d78">dwc_otg_hcd_pipe_info</a>, <a class="el" href="structdwc__hc.html#b2c7e8baff70104375f4916e9b76cef7">dwc_hc</a><li>dev_endpoints
+: <a class="el" href="structdwc__otg__driver__module__params.html#c1c36daec6af25fb425c85a696c445e4">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#17d0dda7fe2cd51726cd1dd34c57b94a">dwc_otg_core_params</a><li>dev_global_regs
+: <a class="el" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dwc_otg_dev_if</a><li>dev_if
+: <a class="el" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dwc_otg_core_if</a><li>dev_nperio_tx_fifo_size
+: <a class="el" href="structdwc__otg__driver__module__params.html#3172175dc8f08e96b63c7a8c162201f5">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#d08d9aee1fb4e6508089415d6150176e">dwc_otg_core_params</a><li>dev_perio_tx_fifo_size
+: <a class="el" href="structdwc__otg__driver__module__params.html#aada52f0668d5d52b8ac6281c8736283">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#2958d325289f4a77b6435cda729e5f6e">dwc_otg_core_params</a><li>dev_rx_fifo_size
+: <a class="el" href="structdwc__otg__driver__module__params.html#707eedd2d7794728c5188e5d5056316e">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#24ea6f9329f64ac0ad2d31dafe0d1d8c">dwc_otg_core_params</a><li>dev_speed
+: <a class="el" href="structdwc__otg__qh.html#42459dd91e199807783000b6dc358a7d">dwc_otg_qh</a><li>dev_token_q_depth
+: <a class="el" href="unionhwcfg2__data.html#ba242467585b60b4d3db9882e0f39b3f">hwcfg2_data</a><li>dev_tx_fifo_size
+: <a class="el" href="structdwc__otg__driver__module__params.html#d1c3fbc5325b13e1191388b76795b848">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#6e0c5d06467fbf3458f11f7eb8153a8b">dwc_otg_core_params</a><li>devaddr
+: <a class="el" href="unionhcchar__data.html#19326a679cb3507cf294d229834252a1">hcchar_data</a>, <a class="el" href="uniondcfg__data.html#71c70afb48dd124d12e43d86edd90f1e">dcfg_data</a><li>devhnpen
+: <a class="el" href="uniongotgctl__data.html#0058cbee8b53336c28746116301ea796">gotgctl_data</a><li>devspd
+: <a class="el" href="uniondcfg__data.html#28ffb9fb43686fe553fbe80f1ead62a4">dcfg_data</a><li>dfifo_depth
+: <a class="el" href="unionhwcfg3__data.html#f885715ddb953dbe95acc08e49264706">hwcfg3_data</a><li>diepctl
+: <a class="el" href="structdwc__otg__dev__in__ep__regs.html#53a5adb977e2aec66d4902c6ba293216">dwc_otg_dev_in_ep_regs</a><li>diepdma
+: <a class="el" href="structdwc__otg__dev__in__ep__regs.html#5f013840a15e0a310b8722646880a420">dwc_otg_dev_in_ep_regs</a><li>diepdmab
+: <a class="el" href="structdwc__otg__dev__in__ep__regs.html#aa24ec8b19877c7f2f20802afc6f9cef">dwc_otg_dev_in_ep_regs</a><li>diepeachintmsk
+: <a class="el" href="structdwc__otg__dev__global__regs.html#aaf2a5c6be4130d558c291f6aaeeca4f">dwc_otg_dev_global_regs</a><li>diepint
+: <a class="el" href="structdwc__otg__dev__in__ep__regs.html#4d6d6309ef5e09ad9048655ced6a2769">dwc_otg_dev_in_ep_regs</a><li>diepmsk
+: <a class="el" href="structdwc__otg__dev__global__regs.html#02e44cb182548d78c5b7d27929ca5f11">dwc_otg_dev_global_regs</a><li>dieptsiz
+: <a class="el" href="structdwc__otg__dev__in__ep__regs.html#88f637b5a4e8a0c6bc87d157072255dd">dwc_otg_dev_in_ep_regs</a><li>disabling
+: <a class="el" href="structdwc__otg__pcd__ep.html#510fcd32761716abec5a35594a3d3ad3">dwc_otg_pcd_ep</a><li>disconnect
+: <a class="el" href="uniongintsts__data.html#45d8d681263dcfc7c2b6cf30ee689f28">gintsts_data</a>, <a class="el" href="uniongintmsk__data.html#0ff313bfc712a2f3d71bc1a5f1a17ce2">gintmsk_data</a>, <a class="el" href="structdwc__otg__pcd__function__ops.html#51b0e7dcf19398bad4f0ec459b43077a">dwc_otg_pcd_function_ops</a>, <a class="el" href="structdwc__otg__hcd__function__ops.html#fb7650d10a745991479af978fb519651">dwc_otg_hcd_function_ops</a>, <a class="el" href="structdwc__otg__cil__callbacks.html#1a8ccad34a04f3e8b085aa5720bbcc70">dwc_otg_cil_callbacks</a><li>dma
+: <a class="el" href="structdwc__otg__pcd__ep.html#314db0fbde1d5eb9eae0cbe4fdef47a4">dwc_otg_pcd_ep</a>, <a class="el" href="structdwc__otg__pcd__request.html#df93c8905495816eb0327b192938a4a1">dwc_otg_pcd_request</a>, <a class="el" href="structdwc__otg__hcd__urb.html#4e177a55239e95ae2f6c8b6b913f67fc">dwc_otg_hcd_urb</a><li>dma_addr
+: <a class="el" href="unionhcdma__data.html#8324b2ba8d18c5ecb1cbcb23874393db">hcdma_data</a>, <a class="el" href="structdwc__ep.html#b40ce70422b6d105a855a8df4b33d45d">dwc_ep</a><li>dma_addr0
+: <a class="el" href="structdwc__ep.html#553936d1d003413d00a24330274887f9">dwc_ep</a><li>dma_addr1
+: <a class="el" href="structdwc__ep.html#02dc1be77d505b19f14651fe9805c97f">dwc_ep</a><li>dma_burst_size
+: <a class="el" href="structdwc__otg__driver__module__params.html#19c1567261677aa53120cfae53b90f8d">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#f9d2a8cd9b36d24de89121d19f693ccb">dwc_otg_core_params</a><li>dma_desc_addr
+: <a class="el" href="structdwc__ep.html#1a43e464429530e874472092e0e1af09">dwc_ep</a><li>dma_desc_enable
+: <a class="el" href="structdwc__otg__driver__module__params.html#cdceee2a19bb233c12893751f443c40d">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dwc_otg_core_if</a>, <a class="el" href="structdwc__otg__core__params.html#36c5bcf00d0f776b5c9e84e5d8ae408d">dwc_otg_core_params</a><li>dma_desc_last
+: <a class="el" href="structcfi__ep.html#3f4e5c42f279663ee0065ffce4f44783">cfi_ep</a><li>dma_enable
+: <a class="el" href="structdwc__otg__driver__module__params.html#fe4469605ca0460a3e309603d7c23e86">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dwc_otg_core_if</a>, <a class="el" href="structdwc__otg__core__params.html#3c791cb4898379d156acc47c5b9a84fc">dwc_otg_core_params</a><li>dma_in_desc_addr
+: <a class="el" href="structdwc__otg__dev__if.html#ba2f5eede8b3deaaec8882baeea6a35b">dwc_otg_dev_if</a><li>dma_out_desc_addr
+: <a class="el" href="structdwc__otg__dev__if.html#3829a415bbaf0f5c3e29b1a9f3cf546b">dwc_otg_dev_if</a><li>dma_setup_desc_addr
+: <a class="el" href="structdwc__otg__dev__if.html#fb3d3353afd5f9d08a8e49c48158cfb7">dwc_otg_dev_if</a><li>dmaenable
+: <a class="el" href="uniongahbcfg__data.html#f39c07c45326af38a267b0e308496b5c">gahbcfg_data</a><li>dmareq
+: <a class="el" href="uniongrstctl__data.html#13e11d4c86ca39b8edf3c1878708fad1">grstctl_data</a><li>do_ping
+: <a class="el" href="structdwc__hc.html#ae7184275dbb23b3a5d2af20ed224920">dwc_hc</a><li>do_split
+: <a class="el" href="structdwc__otg__qh.html#8708dd009988ce20b8a8d52a4a96c5a3">dwc_otg_qh</a>, <a class="el" href="structdwc__hc.html#4365ef67d517a621a626ac5392545c6d">dwc_hc</a><li>doepctl
+: <a class="el" href="structdwc__otg__dev__out__ep__regs.html#2a522b71fc97658c07debf3521f7d3e5">dwc_otg_dev_out_ep_regs</a><li>doepdma
+: <a class="el" href="structdwc__otg__dev__out__ep__regs.html#006071bf54bfa1c1f5e25cf4c9f65cb1">dwc_otg_dev_out_ep_regs</a><li>doepdmab
+: <a class="el" href="structdwc__otg__dev__out__ep__regs.html#baff3c1aea7aed57a42fa0015f15e0fa">dwc_otg_dev_out_ep_regs</a><li>doepeachintmsk
+: <a class="el" href="structdwc__otg__dev__global__regs.html#304e089ed2d36d9076228b8d7e1cc515">dwc_otg_dev_global_regs</a><li>doepfn
+: <a class="el" href="structdwc__otg__dev__out__ep__regs.html#f23e8e9750d99b1c4b5ac0c674e8733e">dwc_otg_dev_out_ep_regs</a><li>doepint
+: <a class="el" href="structdwc__otg__dev__out__ep__regs.html#81d837c801dcfa30f17b567419a86f62">dwc_otg_dev_out_ep_regs</a><li>doepmsk
+: <a class="el" href="structdwc__otg__dev__global__regs.html#d6947be9d84a1d87156f81a10ebb036b">dwc_otg_dev_global_regs</a><li>doeptsiz
+: <a class="el" href="structdwc__otg__dev__out__ep__regs.html#e756ec48787099f0a4e2ce353fce4f91">dwc_otg_dev_out_ep_regs</a><li>dopng
+: <a class="el" href="unionhctsiz__data.html#68625ebdd11afc0a026f41c94aedc161">hctsiz_data</a><li>dpid
+: <a class="el" href="uniondepctl__data.html#ea2f031d4f4dd0580caa5707d50dd0c1">depctl_data</a>, <a class="el" href="unionhost__grxsts__data.html#5c4ca6a6c4a85064dd024095607a634d">host_grxsts_data</a>, <a class="el" href="uniondevice__grxsts__data.html#d0f4716b612b04fde649a2f689ea5b88">device_grxsts_data</a><li>dptxfsiz_dieptxf
+: <a class="el" href="structdwc__otg__core__global__regs.html#efd9e780825f992dbc6cf46d2d72869e">dwc_otg_core_global_regs</a><li>driver
+: <a class="el" href="structgadget__wrapper.html#8997a3c90f9eb0a8f40f5762ffc5ce60">gadget_wrapper</a><li>dsts
+: <a class="el" href="structdwc__otg__dev__global__regs.html#1ed00edd20ce5db7d07666804101ec05">dwc_otg_dev_global_regs</a><li>dtknqr1
+: <a class="el" href="structdwc__otg__dev__global__regs.html#b130a76736e0e81d5a020651109352de">dwc_otg_dev_global_regs</a><li>dtknqr2
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+: <a class="el" href="structdwc__otg__dev__global__regs.html#c263c55a0bb752f8939731aa2f8f6cb8">dwc_otg_dev_global_regs</a><li>dtknqr4_fifoemptymsk
+: <a class="el" href="structdwc__otg__dev__global__regs.html#fbc2b776c2150842813e4681dd43bedc">dwc_otg_dev_global_regs</a><li>dtxfsts
+: <a class="el" href="structdwc__otg__dev__in__ep__regs.html#90db7d3ed2dd087e0a55a1465deb21c9">dwc_otg_dev_in_ep_regs</a><li>dvbusdis
+: <a class="el" href="structdwc__otg__dev__global__regs.html#95088e182c3ff164d1b331bb196eb95d">dwc_otg_dev_global_regs</a><li>dvbuspulse
+: <a class="el" href="structdwc__otg__dev__global__regs.html#8747dbe01b5a4cbd2c980bf39fdb4737">dwc_otg_dev_global_regs</a><li>dw_align_buf
+: <a class="el" href="structdwc__otg__qh.html#aac9f90a6afd9056dce79d013dd2168b">dwc_otg_qh</a><li>dw_align_buf_dma
+: <a class="el" href="structdwc__otg__qh.html#b0b008f9d25f5e3b6e285d2830cfdca1">dwc_otg_qh</a><li>dwc_ep
+: <a class="el" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_otg_pcd_ep</a><li>dwc_otg_hcd
+: <a class="el" href="structwrapper__priv__data.html#3a5cfdab2772597d857294972bb171c8">wrapper_priv_data</a><li>dynamic_fifo
+: <a class="el" href="unionhwcfg2__data.html#b6bfbfe650352dec82a02d15677fe88d">hwcfg2_data</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x65.html b/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x65.html
new file mode 100644
index 000000000000..2d0c14362888
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x65.html
@@ -0,0 +1,109 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions.html"><span>All</span></a></li>
+    <li><a href="functions_func.html"><span>Functions</span></a></li>
+    <li id="current"><a href="functions_vars.html"><span>Variables</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions_vars.html#index_a"><span>a</span></a></li>
+    <li><a href="functions_vars_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="functions_vars_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="functions_vars_0x64.html#index_d"><span>d</span></a></li>
+    <li id="current"><a href="functions_vars_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="functions_vars_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="functions_vars_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="functions_vars_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="functions_vars_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="functions_vars_0x6c.html#index_l"><span>l</span></a></li>
+    <li><a href="functions_vars_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="functions_vars_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="functions_vars_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="functions_vars_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="functions_vars_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="functions_vars_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="functions_vars_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="functions_vars_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="functions_vars_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="functions_vars_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="functions_vars_0x77.html#index_w"><span>w</span></a></li>
+    <li><a href="functions_vars_0x78.html#index_x"><span>x</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_e">- e -</a></h3><ul>
+<li>emptyintr
+: <a class="el" href="uniondiepint__data.html#de84fb009990e97bfa46f825d5358429">diepint_data</a><li>en_multiple_tx_fifo
+: <a class="el" href="structdwc__otg__driver__module__params.html#13860bb2c8d23e40088703289e6ae835">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__if.html#31d08d1ebcd290b05139b0fcd24048ec">dwc_otg_core_if</a>, <a class="el" href="structdwc__otg__core__params.html#d61279dcea66973b2915e335efb07fe3">dwc_otg_core_params</a><li>en_utmi_sleep
+: <a class="el" href="unionglpmctl__data.html#63e912a05b8d29872b92263ca616fec8">glpmctl_data</a><li>enable_dynamic_fifo
+: <a class="el" href="structdwc__otg__driver__module__params.html#f448f6de6dcafca027bd2873b714b916">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#8c169633d4a6f28e964cef9f597c6e03">dwc_otg_core_params</a><li>enbl_sleep_gating
+: <a class="el" href="unionpcgcctl__data.html#6c18ad3b71ad92e548d0c6d64cc88734">pcgcctl_data</a><li>enumdone
+: <a class="el" href="uniongintsts__data.html#84e707787b50ee3867786c8e0995f41e">gintsts_data</a>, <a class="el" href="uniongintmsk__data.html#895f1c1537debec62da4fd248249859c">gintmsk_data</a><li>enumspd
+: <a class="el" href="uniondsts__data.html#f918f3d04b026687af3e1953f5c79fea">dsts_data</a><li>eol
+: <a class="el" href="unionhost__dma__desc__sts.html#58d670cd305219a32f144a6705e649e3">host_dma_desc_sts</a><li>eopframe
+: <a class="el" href="uniongintsts__data.html#a731c93eb9e131fadde92da363a85527">gintsts_data</a>, <a class="el" href="uniongintmsk__data.html#aeb61a24f3c50caacfb8fe523c85768a">gintmsk_data</a><li>ep
+: <a class="el" href="uniondaint__data.html#5d048f0d5695317b05317d3c5ec4f79d">daint_data</a>, <a class="el" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">cfi_ep</a><li>ep0
+: <a class="el" href="structgadget__wrapper.html#8f28c6610592157ecef50de726919162">gadget_wrapper</a>, <a class="el" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">dwc_otg_pcd</a><li>ep0_pending
+: <a class="el" href="structdwc__otg__pcd.html#2c8be11c3b9c7cd02684348eb028aeb5">dwc_otg_pcd</a><li>ep0state
+: <a class="el" href="structdwc__otg__pcd.html#8f6963b3fb9ab83048c4c0697c90382a">dwc_otg_pcd</a><li>ep_dir0
+: <a class="el" href="unionhwcfg1__data.html#b58699c49f54de158d6edc4e57716668">hwcfg1_data</a><li>ep_dir1
+: <a class="el" href="unionhwcfg1__data.html#a62adc1641ef86ed0967061fe0480197">hwcfg1_data</a><li>ep_dir10
+: <a class="el" href="unionhwcfg1__data.html#1dba400b1d532a89de3f2c4410e9ab4d">hwcfg1_data</a><li>ep_dir11
+: <a class="el" href="unionhwcfg1__data.html#c5b95969c9c9ffd9f641f7a495e90621">hwcfg1_data</a><li>ep_dir12
+: <a class="el" href="unionhwcfg1__data.html#a88f6d54f42966f47e77dddd015f5aad">hwcfg1_data</a><li>ep_dir13
+: <a class="el" href="unionhwcfg1__data.html#708fa9af8f43442846ed4a122cbf5610">hwcfg1_data</a><li>ep_dir14
+: <a class="el" href="unionhwcfg1__data.html#c930e82427e44ae78db85730665ed2a8">hwcfg1_data</a><li>ep_dir15
+: <a class="el" href="unionhwcfg1__data.html#cb596169ca88921f58ab84d0a38a4cc8">hwcfg1_data</a><li>ep_dir2
+: <a class="el" href="unionhwcfg1__data.html#03607d2fd2913d3bd20035bc66105e77">hwcfg1_data</a><li>ep_dir3
+: <a class="el" href="unionhwcfg1__data.html#9beabdd8094db63c0359a7ef22f2266d">hwcfg1_data</a><li>ep_dir4
+: <a class="el" href="unionhwcfg1__data.html#393899c7a69f9c36ab1b0ef15ab58568">hwcfg1_data</a><li>ep_dir5
+: <a class="el" href="unionhwcfg1__data.html#ef4cd3ba5b57ad791d1dfc237fcb7b2b">hwcfg1_data</a><li>ep_dir6
+: <a class="el" href="unionhwcfg1__data.html#1521515b71e5bb03b1102fb3333c1bbc">hwcfg1_data</a><li>ep_dir7
+: <a class="el" href="unionhwcfg1__data.html#ddc5b4c31dc56456bdca5660d4608f28">hwcfg1_data</a><li>ep_dir8
+: <a class="el" href="unionhwcfg1__data.html#a0d189caec30660152f1fd3abd1176f2">hwcfg1_data</a><li>ep_dir9
+: <a class="el" href="unionhwcfg1__data.html#0c21e8d57df291e8d3b2dbb67c52956e">hwcfg1_data</a><li>ep_is_in
+: <a class="el" href="structdwc__otg__qh.html#2dc622878a6617e5c803061804d5cf9f">dwc_otg_qh</a>, <a class="el" href="structdwc__hc.html#c5088d431f5efc382121f201f5d571aa">dwc_hc</a><li>ep_num
+: <a class="el" href="structdwc__otg__hcd__pipe__info.html#57b54466daa38c3a77f48e94c5e30f0d">dwc_otg_hcd_pipe_info</a>, <a class="el" href="structdwc__hc.html#70b755f76a00b81679aeb1e0db8b2e60">dwc_hc</a><li>ep_type
+: <a class="el" href="structdwc__otg__qh.html#98b78ffd8dbc01be44b302e873e73a82">dwc_otg_qh</a>, <a class="el" href="structdwc__hc.html#e6169fbc92e4d79686097742ad646f5c">dwc_hc</a><li>epdir
+: <a class="el" href="unionhcchar__data.html#11f1b16e50f90806f90953bb979d4e77">hcchar_data</a><li>epdis
+: <a class="el" href="uniondepctl__data.html#4d76ba4ebd506d3175ec5cdc0d811654">depctl_data</a><li>epdisabled
+: <a class="el" href="uniondoepint__data.html#8a263ddc3ab9080b8c2e02ccead0c983">doepint_data</a>, <a class="el" href="uniondiepint__data.html#3a649b75195fb5b26135d75b03cf561d">diepint_data</a><li>epena
+: <a class="el" href="uniondepctl__data.html#337ceb41a9e0735e144e684b1f9e5368">depctl_data</a><li>epmismatch
+: <a class="el" href="uniongintsts__data.html#c30e01457b826afc318e5d76e9dfdded">gintsts_data</a>, <a class="el" href="uniongintmsk__data.html#3a21d0006e144647b43ef910b9183da9">gintmsk_data</a><li>epmscnt
+: <a class="el" href="uniondcfg__data.html#9292b8ce264ebdb8a26c28883443a4df">dcfg_data</a><li>epnum
+: <a class="el" href="unionhcchar__data.html#1597f36b85006e643aaf6f4d503bebc9">hcchar_data</a>, <a class="el" href="uniondevice__grxsts__data.html#d91e207bb8fb6e20652e6ad2474aec8e">device_grxsts_data</a><li>epnums0_5
+: <a class="el" href="uniondtknq1__data.html#b35b4b7cfebfe54904ac0d74bb771825">dtknq1_data</a><li>eptype
+: <a class="el" href="unionhcchar__data.html#df4deee52d932ab29e5d077cde77cbfc">hcchar_data</a>, <a class="el" href="uniondepctl__data.html#f119782e7db731a3d4bf6c500b4ba5d2">depctl_data</a><li>erlysuspend
+: <a class="el" href="uniongintsts__data.html#2659c4ea7b295a089ee498b21b44992b">gintsts_data</a>, <a class="el" href="uniongintmsk__data.html#0c455b6461081720584a8acc4e0e18a5">gintmsk_data</a><li>error_count
+: <a class="el" href="structdwc__otg__qtd.html#18eeb9c647049aec468bf9a7861c873f">dwc_otg_qtd</a>, <a class="el" href="structdwc__otg__hcd__urb.html#58c7018042c94c436637ea80354e7e28">dwc_otg_hcd_urb</a><li>error_state
+: <a class="el" href="structdwc__hc.html#ab0855754930fdc74978fa71772982ed">dwc_hc</a><li>errticerr
+: <a class="el" href="uniondsts__data.html#fc57a31e440fcf11b233c8c208df83be">dsts_data</a><li>even_odd_frame
+: <a class="el" href="structdwc__ep.html#0692ad9970f4ff48b4210577a6bf86ee">dwc_ep</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x66.html b/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x66.html
new file mode 100644
index 000000000000..aca7433f7ef5
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x66.html
@@ -0,0 +1,81 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions.html"><span>All</span></a></li>
+    <li><a href="functions_func.html"><span>Functions</span></a></li>
+    <li id="current"><a href="functions_vars.html"><span>Variables</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions_vars.html#index_a"><span>a</span></a></li>
+    <li><a href="functions_vars_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="functions_vars_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="functions_vars_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="functions_vars_0x65.html#index_e"><span>e</span></a></li>
+    <li id="current"><a href="functions_vars_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="functions_vars_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="functions_vars_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="functions_vars_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="functions_vars_0x6c.html#index_l"><span>l</span></a></li>
+    <li><a href="functions_vars_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="functions_vars_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="functions_vars_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="functions_vars_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="functions_vars_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="functions_vars_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="functions_vars_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="functions_vars_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="functions_vars_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="functions_vars_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="functions_vars_0x77.html#index_w"><span>w</span></a></li>
+    <li><a href="functions_vars_0x78.html#index_x"><span>x</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_f">- f -</a></h3><ul>
+<li>flags
+: <a class="el" href="structdwc__otg__hcd.html#9aaf2a112f5794f92dedd826342bd637">dwc_otg_hcd</a>, <a class="el" href="structdwc__otg__hcd__urb.html#2f1d90765496d78d297b3e57ef4d781c">dwc_otg_hcd_urb</a><li>fn
+: <a class="el" href="uniondevice__grxsts__data.html#f535ee62a482ec97ca61dc4954e358c6">device_grxsts_data</a><li>fops
+: <a class="el" href="structdwc__otg__pcd.html#b7001dde5db2706707a860da0030d9e6">dwc_otg_pcd</a>, <a class="el" href="structdwc__otg__hcd.html#ffefbd33a59a14b8b46406f5aaeaa2f4">dwc_otg_hcd</a><li>frame_list
+: <a class="el" href="structdwc__otg__hcd.html#77f16d5530f50556ed01fe7f69a135fd">dwc_otg_hcd</a><li>frame_list_dma
+: <a class="el" href="structdwc__otg__hcd.html#3421063dcac9d4e200b5d9bbb0508f3d">dwc_otg_hcd</a><li>frame_number
+: <a class="el" href="structdwc__otg__hcd.html#f79fefeb7908c0ddf702331253acb292">dwc_otg_hcd</a><li>framenum
+: <a class="el" href="uniondev__dma__desc__sts.html#d9da3eccc6d247e2b5eccd4dfba7874e">dev_dma_desc_sts</a><li>free_hc_list
+: <a class="el" href="structdwc__otg__hcd.html#1761f2e6b8f6ba82c0e0c4e561813f0f">dwc_otg_hcd</a><li>frint
+: <a class="el" href="unionhfir__data.html#5302611bdf96e87f3a7f30319212bcc2">hfir_data</a><li>frlisten
+: <a class="el" href="unionhcfg__data.html#11340031265fce764f491b23ae42dda5">hcfg_data</a><li>frm_list_roll
+: <a class="el" href="unionhcintmsk__data.html#da781977131daa2db51fee16900366ae">hcintmsk_data</a>, <a class="el" href="unionhcint__data.html#26f48c3ec302ac2e009be71733e068b7">hcint_data</a><li>frmovrun
+: <a class="el" href="unionhcintmsk__data.html#2ba9f8dc5e946b28ac4169f75364e182">hcintmsk_data</a>, <a class="el" href="unionhcint__data.html#06f911d323d71f86639550507322dffb">hcint_data</a><li>frnum
+: <a class="el" href="unionhfnum__data.html#a64e8b6c4a1cd262dbc30e158f3cb8bc">hfnum_data</a><li>frrem
+: <a class="el" href="unionhfnum__data.html#2a2ce50ebd4c4da5347a2d93c4bbc996">hfnum_data</a><li>fs_phy_type
+: <a class="el" href="unionhwcfg2__data.html#e75417d7e2d1843abf6e48f67851326e">hwcfg2_data</a><li>fsintf
+: <a class="el" href="uniongusbcfg__data.html#8f23ebcf05c1bc48b4e406e98d828f78">gusbcfg_data</a><li>fslspclksel
+: <a class="el" href="unionhcfg__data.html#e048ad3775c6794c3ee07af86079fadf">hcfg_data</a><li>fslssupp
+: <a class="el" href="unionhcfg__data.html#c047f55e398b8a94aef27a66ed78f2de">hcfg_data</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x67.html b/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x67.html
new file mode 100644
index 000000000000..a74c80a385e8
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x67.html
@@ -0,0 +1,95 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions.html"><span>All</span></a></li>
+    <li><a href="functions_func.html"><span>Functions</span></a></li>
+    <li id="current"><a href="functions_vars.html"><span>Variables</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions_vars.html#index_a"><span>a</span></a></li>
+    <li><a href="functions_vars_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="functions_vars_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="functions_vars_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="functions_vars_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="functions_vars_0x66.html#index_f"><span>f</span></a></li>
+    <li id="current"><a href="functions_vars_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="functions_vars_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="functions_vars_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="functions_vars_0x6c.html#index_l"><span>l</span></a></li>
+    <li><a href="functions_vars_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="functions_vars_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="functions_vars_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="functions_vars_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="functions_vars_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="functions_vars_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="functions_vars_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="functions_vars_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="functions_vars_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="functions_vars_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="functions_vars_0x77.html#index_w"><span>w</span></a></li>
+    <li><a href="functions_vars_0x78.html#index_x"><span>x</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_g">- g -</a></h3><ul>
+<li>gadget
+: <a class="el" href="structgadget__wrapper.html#a1f30b68c6b42bc728c45c329312d7b1">gadget_wrapper</a>, <a class="el" href="structcfiobject.html#fcb2ec62bedb38bb1e6a596ac778d4e6">cfiobject</a>, <a class="el" href="structzero__dev.html#e0d019d6177afd1efa101aed63f1a174">zero_dev</a><li>gahbcfg
+: <a class="el" href="structdwc__otg__core__global__regs.html#537c95e57269fabf29c6b36ad8e1ed45">dwc_otg_core_global_regs</a><li>gatehclk
+: <a class="el" href="unionpcgcctl__data.html#a3ee36c0e5ea8ae5ac38829337120327">pcgcctl_data</a><li>gcontbna
+: <a class="el" href="uniondctl__data.html#212c36aaab3763a6de5cca56999c0263">dctl_data</a><li>get_b_hnp_enable
+: <a class="el" href="structdwc__otg__hcd__function__ops.html#24a2ee2bad4dc517fed62417a2a542d3">dwc_otg_hcd_function_ops</a><li>ggpio
+: <a class="el" href="structdwc__otg__core__global__regs.html#694546400c443d41b449772c8573f3e8">dwc_otg_core_global_regs</a><li>ghwcfg1
+: <a class="el" href="structdwc__otg__core__global__regs.html#56d2988ff8fedbbde479ffe8d4e84b75">dwc_otg_core_global_regs</a><li>ghwcfg2
+: <a class="el" href="structdwc__otg__core__global__regs.html#b0f241f53ca7b3be1c94bd684ed61f79">dwc_otg_core_global_regs</a><li>ghwcfg3
+: <a class="el" href="structdwc__otg__core__global__regs.html#57ddcc14f581f5d6276122f9747aff72">dwc_otg_core_global_regs</a><li>ghwcfg4
+: <a class="el" href="structdwc__otg__core__global__regs.html#e1df73c776d3b31d5f0a501ccdeb1d2d">dwc_otg_core_global_regs</a><li>gi2cctl
+: <a class="el" href="structdwc__otg__core__global__regs.html#8ecf68262dbcdb6901f3011cfe35a144">dwc_otg_core_global_regs</a><li>ginnakeff
+: <a class="el" href="uniongintsts__data.html#15a2e362768704ab6143fea33fc8755b">gintsts_data</a>, <a class="el" href="uniongintmsk__data.html#83a6fb180ef8b18faf8d02ba8b50c841">gintmsk_data</a><li>gintmsk
+: <a class="el" href="structdwc__otg__core__global__regs.html#48827c76da2c6b18f369e2f2483cc4b6">dwc_otg_core_global_regs</a><li>gintsts
+: <a class="el" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">dwc_otg_core_global_regs</a><li>glblintrmsk
+: <a class="el" href="uniongahbcfg__data.html#f75957f35be7ecd70616f5d0bcfb1e51">gahbcfg_data</a><li>glpmcfg
+: <a class="el" href="structdwc__otg__core__global__regs.html#843cfb38ba366a9a46ad07ed11eb8396">dwc_otg_core_global_regs</a><li>gmc
+: <a class="el" href="uniondctl__data.html#6ceae1404558a4ffec4dab1c4702c7c8">dctl_data</a><li>gnpinnaksts
+: <a class="el" href="uniondctl__data.html#26ba184e018a813e96527822f9e26fde">dctl_data</a><li>gnptxfsiz
+: <a class="el" href="structdwc__otg__core__global__regs.html#20fb70fe34a1a65d085b1d4e5f8d9106">dwc_otg_core_global_regs</a><li>gnptxsts
+: <a class="el" href="structdwc__otg__core__global__regs.html#57dabea6f6e0bf9e1ee8e94f55b9e465">dwc_otg_core_global_regs</a><li>gotgctl
+: <a class="el" href="structdwc__otg__core__global__regs.html#54034d00bb6b47ada4e0c0baa87cbd8a">dwc_otg_core_global_regs</a><li>gotgint
+: <a class="el" href="structdwc__otg__core__global__regs.html#69cc290cfdfe6900890f7a5a16b3137c">dwc_otg_core_global_regs</a><li>goutnakeff
+: <a class="el" href="uniongintsts__data.html#5fd87ed0462f444df968567f310488f7">gintsts_data</a>, <a class="el" href="uniongintmsk__data.html#1a47902a93203910433a35fab3f5b8a1">gintmsk_data</a><li>goutnaksts
+: <a class="el" href="uniondctl__data.html#995d969d60e86b2ea662eb831c882b44">dctl_data</a><li>gpvndctl
+: <a class="el" href="structdwc__otg__core__global__regs.html#a12db668367caef8386d2ba20289e437">dwc_otg_core_global_regs</a><li>grstctl
+: <a class="el" href="structdwc__otg__core__global__regs.html#49d307957dbe53f20aa8f7a5409ee8ad">dwc_otg_core_global_regs</a><li>grxfsiz
+: <a class="el" href="structdwc__otg__core__global__regs.html#b1a8cc07a9541c9a73e864579602b79b">dwc_otg_core_global_regs</a><li>grxstsp
+: <a class="el" href="structdwc__otg__core__global__regs.html#763b05035799e1c16d34957fb62a2d17">dwc_otg_core_global_regs</a><li>grxstsr
+: <a class="el" href="structdwc__otg__core__global__regs.html#5e688c41f25ba8081f34cb1b2b052dbc">dwc_otg_core_global_regs</a><li>gsnpsid
+: <a class="el" href="structdwc__otg__core__global__regs.html#30798436df220217c3960ac4a46710dc">dwc_otg_core_global_regs</a><li>guid
+: <a class="el" href="structdwc__otg__core__global__regs.html#8735ca2e93c1e984ac2d5bcf0cda96d7">dwc_otg_core_global_regs</a><li>gusbcfg
+: <a class="el" href="structdwc__otg__core__global__regs.html#ef39e181e246447df47c56aa4e37cc42">dwc_otg_core_global_regs</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x68.html b/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x68.html
new file mode 100644
index 000000000000..b89f32639656
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x68.html
@@ -0,0 +1,119 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions.html"><span>All</span></a></li>
+    <li><a href="functions_func.html"><span>Functions</span></a></li>
+    <li id="current"><a href="functions_vars.html"><span>Variables</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions_vars.html#index_a"><span>a</span></a></li>
+    <li><a href="functions_vars_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="functions_vars_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="functions_vars_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="functions_vars_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="functions_vars_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="functions_vars_0x67.html#index_g"><span>g</span></a></li>
+    <li id="current"><a href="functions_vars_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="functions_vars_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="functions_vars_0x6c.html#index_l"><span>l</span></a></li>
+    <li><a href="functions_vars_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="functions_vars_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="functions_vars_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="functions_vars_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="functions_vars_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="functions_vars_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="functions_vars_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="functions_vars_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="functions_vars_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="functions_vars_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="functions_vars_0x77.html#index_w"><span>w</span></a></li>
+    <li><a href="functions_vars_0x78.html#index_x"><span>x</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_h">- h -</a></h3><ul>
+<li>haint
+: <a class="el" href="structdwc__otg__host__global__regs.html#7c41808b0a69ed7d2125eb3afbbf6c14">dwc_otg_host_global_regs</a><li>haintmsk
+: <a class="el" href="structdwc__otg__host__global__regs.html#317f5059d4c2dc91da041f5c0a4819fc">dwc_otg_host_global_regs</a><li>halt_on_queue
+: <a class="el" href="structdwc__hc.html#c3b27b33fae73aff43a9834a1ed585da">dwc_hc</a><li>halt_pending
+: <a class="el" href="structdwc__hc.html#2177dcde6dbb17b6bc7d0fb34e8ec95a">dwc_hc</a><li>halt_status
+: <a class="el" href="structdwc__hc.html#07eca0fa02105ddaa1719387f5558b23">dwc_hc</a><li>hburstlen
+: <a class="el" href="uniongahbcfg__data.html#b8f9a94aa77eb5abc379c438bf68f3d0">gahbcfg_data</a><li>hc_num
+: <a class="el" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">dwc_hc</a><li>hc_ptr_array
+: <a class="el" href="structdwc__otg__hcd.html#cb393f6a676fb106e0e3d35396fb97f9">dwc_otg_hcd</a><li>hc_regs
+: <a class="el" href="structdwc__otg__host__if.html#7f7c107d4720641eb4141cd817211ac0">dwc_otg_host_if</a><li>hcchar
+: <a class="el" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">dwc_otg_hc_regs</a><li>hcd
+: <a class="el" href="structdwc__otg__device.html#834ef28e884f0d7fcac68f3bdf5c4b33">dwc_otg_device</a><li>hcd_cb
+: <a class="el" href="structdwc__otg__core__if.html#9a8568a762af68c9b0d97e0278cc26ba">dwc_otg_core_if</a><li>hcdma
+: <a class="el" href="structdwc__otg__hc__regs.html#ab2148d4b5f1bf3a2ad438e497a8b4a3">dwc_otg_hc_regs</a><li>hcdmab
+: <a class="el" href="structdwc__otg__hc__regs.html#602f4c6eceb8e9d4fa61f35d4149f355">dwc_otg_hc_regs</a><li>hcfg
+: <a class="el" href="structdwc__otg__host__global__regs.html#fd7d93b5ffcb6c7c0a84ef656e6e68de">dwc_otg_host_global_regs</a>, <a class="el" href="structdwc__otg__core__if.html#447a626f22ad64a90c68a6f49e624eb8">dwc_otg_core_if</a><li>hcint
+: <a class="el" href="structdwc__otg__hc__regs.html#0dfd5bae537d58e13788508dc719480d">dwc_otg_hc_regs</a><li>hcintmsk
+: <a class="el" href="structdwc__otg__hc__regs.html#830aa61c1d4326823662168ea7359205">dwc_otg_hc_regs</a><li>hcintr
+: <a class="el" href="uniongintsts__data.html#e02f1a50b20ed1c4248fd76e155147e8">gintsts_data</a>, <a class="el" href="uniongintmsk__data.html#3a4c193d8ff48291809dcd3ccb7c0585">gintmsk_data</a><li>hcsplt
+: <a class="el" href="structdwc__otg__hc__regs.html#149053001a9ee21b692afde531a814de">dwc_otg_hc_regs</a><li>hctsiz
+: <a class="el" href="structdwc__otg__hc__regs.html#c6173f823ba754d9f9549422b6380ca2">dwc_otg_hc_regs</a><li>hdr
+: <a class="el" href="struct__ddma__concat__buffer__setup.html#512cdc8b5ef9053f514443b884ec4730">_ddma_concat_buffer_setup</a><li>hfir
+: <a class="el" href="structdwc__otg__host__global__regs.html#d5ad893315e7b0dde27a3c5867dc56d0">dwc_otg_host_global_regs</a><li>hflbaddr
+: <a class="el" href="structdwc__otg__host__global__regs.html#9a6af0a2c19d7b6228c7a40c9078907b">dwc_otg_host_global_regs</a><li>hfnum
+: <a class="el" href="structdwc__otg__host__global__regs.html#cebb0d86d0776473ef30eeac61e8692c">dwc_otg_host_global_regs</a><li>hird
+: <a class="el" href="unionglpmctl__data.html#176b788935d1952606f523f2718b3512">glpmctl_data</a><li>hird_thres
+: <a class="el" href="unionglpmctl__data.html#e2ceea4bfe468c7b3c800235d7ffd5d2">glpmctl_data</a><li>hnp_changed
+: <a class="el" href="structdwc__otg__pcd__function__ops.html#db190030830b55d72b36255980be08d7">dwc_otg_pcd_function_ops</a><li>hnpcap
+: <a class="el" href="uniongusbcfg__data.html#71b6330c5ccf1d21ebf79a0a829612b5">gusbcfg_data</a><li>hnpreq
+: <a class="el" href="uniongotgctl__data.html#08487ecb0860252b73815ee6e0f8eaa3">gotgctl_data</a><li>host_channels
+: <a class="el" href="structdwc__otg__driver__module__params.html#4727585082d86c52396adfde0cfffa17">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#c1b433c6965aa7d48f6ca6818c592039">dwc_otg_core_params</a><li>host_global_regs
+: <a class="el" href="structdwc__otg__host__if.html#ff9692c2e10ca2bc7e24f981f25179c2">dwc_otg_host_if</a><li>host_if
+: <a class="el" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">dwc_otg_core_if</a><li>host_ls_low_power_phy_clk
+: <a class="el" href="structdwc__otg__driver__module__params.html#91c46e96e070e983e3f91c756dd4aa64">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#98f413798f20dc40036a2ec527935a7d">dwc_otg_core_params</a><li>host_nperio_tx_fifo_size
+: <a class="el" href="structdwc__otg__driver__module__params.html#edf2038417f58acd8dab202a8ca19d2a">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#6ff00857d99f72c0cfd6198cbcfab9a7">dwc_otg_core_params</a><li>host_perio_tx_fifo_size
+: <a class="el" href="structdwc__otg__driver__module__params.html#bdc820350ca3b6aec5ac435c9712ccd5">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#5bc3cac5c81fd8d6fd291ca4b7de3e28">dwc_otg_core_params</a><li>host_perio_tx_q_depth
+: <a class="el" href="unionhwcfg2__data.html#857bb59069e203a94ffd32538c60058f">hwcfg2_data</a><li>host_rx_fifo_size
+: <a class="el" href="structdwc__otg__driver__module__params.html#1f490daab4c4e08d2773f46d51f1f5f7">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#2b2ab9c2fe16db70b136515b2e981f6b">dwc_otg_core_params</a><li>host_support_fs_ls_low_power
+: <a class="el" href="structdwc__otg__driver__module__params.html#6f3a0a2bf5c82d296fec31fec7b765ca">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#85cad588a450b8497347af9cf166bfde">dwc_otg_core_params</a><li>hprt0
+: <a class="el" href="structdwc__otg__host__if.html#dc8fe33e0bb3829cafa884d5fc603c4d">dwc_otg_host_if</a><li>hptxfsiz
+: <a class="el" href="structdwc__otg__core__global__regs.html#94ae41f04d5a4244a8ebc23e51187e96">dwc_otg_core_global_regs</a><li>hptxsts
+: <a class="el" href="structdwc__otg__host__global__regs.html#bf1a1528a2e479d86318d49ecd52ee40">dwc_otg_host_global_regs</a><li>hs_phy_type
+: <a class="el" href="unionhwcfg2__data.html#a248a2502e3c440d7b6e4ad61d396f4e">hwcfg2_data</a><li>hsftrst
+: <a class="el" href="uniongrstctl__data.html#7418a85aa4ffaa77c49f046202c97c01">grstctl_data</a><li>hsic_connect
+: <a class="el" href="unionglpmctl__data.html#76c64ead46647c39aa76edebf2f63444">glpmctl_data</a><li>hstfrm
+: <a class="el" href="uniongrstctl__data.html#6bf39518efe967ed4c7f9db6d3811a90">grstctl_data</a><li>hstnegdet
+: <a class="el" href="uniongotgint__data.html#7cd2a34cef45f168eb3ee197c101d164">gotgint_data</a><li>hstnegscs
+: <a class="el" href="uniongotgctl__data.html#20b17868fc09a12b163732d5bbc84d8d">gotgctl_data</a><li>hstnegsucstschng
+: <a class="el" href="uniongotgint__data.html#e41c62fee3da6113b23594cec6fb0c67">gotgint_data</a><li>hstsethnpen
+: <a class="el" href="uniongotgctl__data.html#7d45791d3622a59ff43ab248bbb1b2c1">gotgctl_data</a><li>hub_addr
+: <a class="el" href="structdwc__hc.html#19d0302b6e3769eada2466b8e5e0dd91">dwc_hc</a><li>hub_info
+: <a class="el" href="structdwc__otg__hcd__function__ops.html#71bff93886173700d26a8950e7ea82e1">dwc_otg_hcd_function_ops</a><li>hubaddr
+: <a class="el" href="unionhcsplt__data.html#2843e0a36458a9a4c2d5ed6da3027b36">hcsplt_data</a><li>hwcfg1
+: <a class="el" href="structdwc__otg__core__if.html#d7c6a00c6d7c157ff60a044a28ec8b95">dwc_otg_core_if</a><li>hwcfg2
+: <a class="el" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">dwc_otg_core_if</a><li>hwcfg3
+: <a class="el" href="structdwc__otg__core__if.html#91d0e0a5e8e048024c8846d12e00cecc">dwc_otg_core_if</a><li>hwcfg4
+: <a class="el" href="structdwc__otg__core__if.html#9c1394f3c46adde2fa7be79bf0237f9b">dwc_otg_core_if</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x69.html b/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x69.html
new file mode 100644
index 000000000000..822d0d2742dd
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x69.html
@@ -0,0 +1,121 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions.html"><span>All</span></a></li>
+    <li><a href="functions_func.html"><span>Functions</span></a></li>
+    <li id="current"><a href="functions_vars.html"><span>Variables</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions_vars.html#index_a"><span>a</span></a></li>
+    <li><a href="functions_vars_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="functions_vars_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="functions_vars_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="functions_vars_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="functions_vars_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="functions_vars_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="functions_vars_0x68.html#index_h"><span>h</span></a></li>
+    <li id="current"><a href="functions_vars_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="functions_vars_0x6c.html#index_l"><span>l</span></a></li>
+    <li><a href="functions_vars_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="functions_vars_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="functions_vars_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="functions_vars_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="functions_vars_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="functions_vars_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="functions_vars_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="functions_vars_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="functions_vars_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="functions_vars_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="functions_vars_0x77.html#index_w"><span>w</span></a></li>
+    <li><a href="functions_vars_0x78.html#index_x"><span>x</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_i">- i -</a></h3><ul>
+<li>i2c
+: <a class="el" href="unionhwcfg3__data.html#dd2115f4a4bfa47b2c9c9a7b5f42e203">hwcfg3_data</a><li>i2c_enable
+: <a class="el" href="structdwc__otg__driver__module__params.html#4e1d822cfcc6332fcaa0471bb1ca0d54">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#6b0a0ab15284a541ae079beecaf3e617">dwc_otg_core_params</a><li>i2cdevaddr
+: <a class="el" href="uniongi2cctl__data.html#78d1a33a0a81bbca4e89e2f578b27ca2">gi2cctl_data</a><li>i2cen
+: <a class="el" href="uniongi2cctl__data.html#6a14bacfd6c36d22071a79cb0fb53e77">gi2cctl_data</a><li>i2cintr
+: <a class="el" href="uniongintsts__data.html#2e8bd51ad285fd46db48f9fb5bbb7993">gintsts_data</a>, <a class="el" href="uniongintmsk__data.html#92dd84dd80b06e949668f85e6b6b7086">gintmsk_data</a><li>i2csuspctl
+: <a class="el" href="uniongi2cctl__data.html#96fcad9de22d851a74f900458c2ac325">gi2cctl_data</a><li>ic_traffic_pull_remove
+: <a class="el" href="uniongusbcfg__data.html#6805b1ea875bbb9cd31e877fd66c8559">gusbcfg_data</a><li>ic_usb_cap
+: <a class="el" href="uniongusbcfg__data.html#b729e853539aafb4bab1e4e9ac57916a">gusbcfg_data</a>, <a class="el" href="structdwc__otg__driver__module__params.html#ed3802eea4e62cd79ef7d8701d45b506">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#359a3cb3a7b4800a0c32750005c9fd1b">dwc_otg_core_params</a><li>id
+: <a class="el" href="structcfi__string.html#dc88ed81d4ff35c7a1c837708659afea">cfi_string</a><li>iddig_filt_en
+: <a class="el" href="unionhwcfg4__data.html#be353f75bb8cd8b14fc5f8db2d51da55">hwcfg4_data</a><li>ifrmnum
+: <a class="el" href="uniondctl__data.html#a817a529df5c5fc57135560014b90dcc">dctl_data</a><li>in
+: <a class="el" href="uniondaint__data.html#dbc4f689d070e6cbc112ec910f8bc36a">daint_data</a><li>in_desc_addr
+: <a class="el" href="structdwc__otg__dev__if.html#99f44e328bbb4401aabd8e2708853238">dwc_otg_dev_if</a><li>in_ep
+: <a class="el" href="structgadget__wrapper.html#9b57a0085afa3decabffc89943866931">gadget_wrapper</a>, <a class="el" href="structdwc__otg__pcd.html#dbfc8c424ea3add38db96fa87219caa8">dwc_otg_pcd</a>, <a class="el" href="structzero__dev.html#8b35a5b8ce497d55d7369a4635d891df">zero_dev</a><li>in_ep_regs
+: <a class="el" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">dwc_otg_dev_if</a><li>in_process
+: <a class="el" href="structdwc__otg__qtd.html#c1d73f1d48eeabbdc198ad28c0882bc1">dwc_otg_qtd</a><li>incomplisoin
+: <a class="el" href="uniongintsts__data.html#6a2b4a287af4632cec2207fe6fb91e86">gintsts_data</a>, <a class="el" href="uniongintmsk__data.html#3f9eeb4c73291b7943b7187ba34c90f4">gintmsk_data</a><li>incomplisoout
+: <a class="el" href="uniongintsts__data.html#519e2237cad3f43ebb7665e8d24c0180">gintsts_data</a>, <a class="el" href="uniongintmsk__data.html#c63c107070bd7623766e39cd06ec7c97">gintmsk_data</a><li>inep0
+: <a class="el" href="uniondaint__data.html#371eb39ddd249f984242ffc6bc2590ba">daint_data</a><li>inep1
+: <a class="el" href="uniondaint__data.html#af6849b786344ddee9cd7f884199434c">daint_data</a><li>inep10
+: <a class="el" href="uniondaint__data.html#f7560a6b186b5a690382e443b12feee8">daint_data</a><li>inep11
+: <a class="el" href="uniondaint__data.html#67745fd9faa3ca8d8da6e937d782cc3e">daint_data</a><li>inep12
+: <a class="el" href="uniondaint__data.html#bbae9ce28263f0973e46ed65367f898b">daint_data</a><li>inep13
+: <a class="el" href="uniondaint__data.html#dc51893893bfeddf1e842a89d778b6d8">daint_data</a><li>inep14
+: <a class="el" href="uniondaint__data.html#8235ebce9e66c2d0e76edf7a1a5cd877">daint_data</a><li>inep15
+: <a class="el" href="uniondaint__data.html#419952bb56b11f01e7f0995e138237de">daint_data</a><li>inep2
+: <a class="el" href="uniondaint__data.html#a52a2d17ef3dbea8fa25217629181a7c">daint_data</a><li>inep3
+: <a class="el" href="uniondaint__data.html#7152eb0ccf903be2810d1e25fef9bfb5">daint_data</a><li>inep4
+: <a class="el" href="uniondaint__data.html#f1e4c6eb79afda585c260a93c111aa12">daint_data</a><li>inep5
+: <a class="el" href="uniondaint__data.html#4175dc0a3f230773225f0971c31bc129">daint_data</a><li>inep6
+: <a class="el" href="uniondaint__data.html#40b670d2fc2b799a6278a16326441b1f">daint_data</a><li>inep7
+: <a class="el" href="uniondaint__data.html#8beeff7b54bd1902946425ab6a0d9d22">daint_data</a><li>inep8
+: <a class="el" href="uniondaint__data.html#baf8f1fe4bde7d02d61c93b5c7059f57">daint_data</a><li>inep9
+: <a class="el" href="uniondaint__data.html#ae119c728bcdf52e9504fedd16b0886b">daint_data</a><li>inepint
+: <a class="el" href="uniongintsts__data.html#e4e48a2a194cf95d934800a85c12784f">gintsts_data</a><li>inepintr
+: <a class="el" href="uniongintmsk__data.html#bcae4c9dd3d0f153b379dfbc6c830fc5">gintmsk_data</a><li>inepnakeff
+: <a class="el" href="uniondiepint__data.html#9186a1106fe57e01ce720a50ceb5864f">diepint_data</a><li>interval
+: <a class="el" href="structdwc__otg__qh.html#cdbce86d457f0ea08e2efedc47c9b315">dwc_otg_qh</a>, <a class="el" href="structdwc__otg__hcd__urb.html#49c5353377e2fb173f1b34ae7be7e257">dwc_otg_hcd_urb</a><li>intknepmis
+: <a class="el" href="uniondiepint__data.html#103fb29d954cf12d33f7ebe6009f9a46">diepint_data</a><li>intknqflsh
+: <a class="el" href="uniongrstctl__data.html#259049fa7991ecad9ca1595763b636f9">grstctl_data</a><li>intknwptr
+: <a class="el" href="uniondtknq1__data.html#33b25ddce8afe3ac2d8736f42133c284">dtknq1_data</a><li>intktxfemp
+: <a class="el" href="uniondiepint__data.html#7c9961f17328bbc25ca39e7ec1891e16">diepint_data</a><li>intokenrx
+: <a class="el" href="uniongintsts__data.html#912b165c3b774baedd294b678df9c2c0">gintsts_data</a><li>inv_sel_hsic
+: <a class="el" href="unionglpmctl__data.html#f664636955d9476647937d13d48f068e">glpmctl_data</a><li>ioc
+: <a class="el" href="unionhost__dma__desc__sts.html#2efbb549924afd0deb402af9eda4a272">host_dma_desc_sts</a>, <a class="el" href="uniondev__dma__desc__sts.html#02c8be72ef6258c25094478c7cac0b12">dev_dma_desc_sts</a><li>is_in
+: <a class="el" href="structdwc__ep.html#b882b6b7c857100ed20600e94ea37760">dwc_ep</a><li>iso_desc_addr
+: <a class="el" href="structdwc__ep.html#a4e11d12099ad64dd5048a3a210fc9f6">dwc_ep</a><li>iso_descs
+: <a class="el" href="structdwc__otg__hcd__urb.html#ed542f6a2d99dba2f6b71b0d8012ec8a">dwc_otg_hcd_urb</a><li>iso_dma_desc_addr
+: <a class="el" href="structdwc__ep.html#d571f49545171ea167193edac7984173">dwc_ep</a><li>iso_req_handle
+: <a class="el" href="structdwc__otg__pcd__ep.html#716d3c29adc54c6822935fc2ae9bef51">dwc_otg_pcd_ep</a><li>iso_thr_en
+: <a class="el" href="uniondthrctl__data.html#f69727f09d4443c01038ba7b163814f8">dthrctl_data</a><li>iso_tx_thr_en
+: <a class="el" href="structdwc__otg__dev__if.html#76af117a05ad95e5e5c534a1afcdae22">dwc_otg_dev_if</a><li>isoc_complete
+: <a class="el" href="structdwc__otg__pcd__function__ops.html#9714dfa4909221c0b937a9bcadf97339">dwc_otg_pcd_function_ops</a><li>isoc_frame_index
+: <a class="el" href="structdwc__otg__qtd.html#c67d5f885976d0698f20d113d32b4b30">dwc_otg_qtd</a><li>isoc_frame_index_last
+: <a class="el" href="structdwc__otg__qtd.html#c296d49e3615e35c06b83e7febc31943">dwc_otg_qtd</a><li>isoc_split_offset
+: <a class="el" href="structdwc__otg__qtd.html#839371940a7e34365e2272f3214b7e34">dwc_otg_qtd</a><li>isoc_split_pos
+: <a class="el" href="structdwc__otg__qtd.html#ab224d64d72f2ef4f10e722ebcfa29a6">dwc_otg_qtd</a><li>isooutdrop
+: <a class="el" href="uniongintsts__data.html#e6e931e1d6226dc110a98cd42c9a8e5f">gintsts_data</a>, <a class="el" href="uniongintmsk__data.html#3a0a75b129ccdaed6d98d1982b374d52">gintmsk_data</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x6c.html b/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x6c.html
new file mode 100644
index 000000000000..eb4da462041a
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x6c.html
@@ -0,0 +1,74 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions.html"><span>All</span></a></li>
+    <li><a href="functions_func.html"><span>Functions</span></a></li>
+    <li id="current"><a href="functions_vars.html"><span>Variables</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions_vars.html#index_a"><span>a</span></a></li>
+    <li><a href="functions_vars_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="functions_vars_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="functions_vars_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="functions_vars_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="functions_vars_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="functions_vars_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="functions_vars_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="functions_vars_0x69.html#index_i"><span>i</span></a></li>
+    <li id="current"><a href="functions_vars_0x6c.html#index_l"><span>l</span></a></li>
+    <li><a href="functions_vars_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="functions_vars_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="functions_vars_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="functions_vars_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="functions_vars_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="functions_vars_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="functions_vars_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="functions_vars_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="functions_vars_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="functions_vars_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="functions_vars_0x77.html#index_w"><span>w</span></a></li>
+    <li><a href="functions_vars_0x78.html#index_x"><span>x</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_l">- l -</a></h3><ul>
+<li>l
+: <a class="el" href="uniondev__dma__desc__sts.html#b728a79d6a86a0d1b6426a1b2627f2c2">dev_dma_desc_sts</a><li>length
+: <a class="el" href="structdwc__otg__pcd__request.html#3dd3fcc889bf220b048023e8b05fab61">dwc_otg_pcd_request</a>, <a class="el" href="structdwc__otg__hcd__urb.html#dca57de4fdecd894241ce24167206a45">dwc_otg_hcd_urb</a>, <a class="el" href="structdwc__otg__hcd__iso__packet__desc.html#8392d21b820df0181f4e6dca91234543">dwc_otg_hcd_iso_packet_desc</a>, <a class="el" href="structiso__pkt__info.html#ced82142e81778345016841e15020eb8">iso_pkt_info</a><li>lh
+: <a class="el" href="structcfi__ep.html#18bff3370dc933cd374d458897dfbc2f">cfi_ep</a><li>lock
+: <a class="el" href="structdwc__otg__pcd.html#5d450e4d06659ab2f3b18e5c816776e4">dwc_otg_pcd</a>, <a class="el" href="structdwc__otg__hcd.html#34f29e9c035009476495f7701c1813fd">dwc_otg_hcd</a>, <a class="el" href="structzero__dev.html#712568d4b6a481845034ac6d87c0547d">zero_dev</a><li>lpm_cap_en
+: <a class="el" href="unionglpmctl__data.html#cf0a4cfcd158e41eb3811048e723890f">glpmctl_data</a><li>lpm_chan_index
+: <a class="el" href="unionglpmctl__data.html#7e6bb2a40d4e0bdfed6f868b1f670235">glpmctl_data</a><li>lpm_enable
+: <a class="el" href="structdwc__otg__driver__module__params.html#bb4e33c533d53de007814f0e5a70dd8a">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#8b906ba765a10dd9fcfa1c02dbc0184e">dwc_otg_core_params</a><li>lpm_resp
+: <a class="el" href="unionglpmctl__data.html#752c00118919fce173804931b058c5a8">glpmctl_data</a><li>lpmtranrcvd
+: <a class="el" href="uniongintsts__data.html#50e73e91df681c835de50f8276058829">gintsts_data</a>, <a class="el" href="uniongintmsk__data.html#24f9f89b33866c5dc7b16588bc94e103">gintmsk_data</a><li>lspddev
+: <a class="el" href="unionhcchar__data.html#ca469c8bda88761c4d9ef74b811d71f4">hcchar_data</a><li>lx_state
+: <a class="el" href="structdwc__otg__core__if.html#2b0701d814069ec69897e08374366c7b">dwc_otg_core_if</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x6d.html b/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x6d.html
new file mode 100644
index 000000000000..a97be16a88d7
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x6d.html
@@ -0,0 +1,79 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions.html"><span>All</span></a></li>
+    <li><a href="functions_func.html"><span>Functions</span></a></li>
+    <li id="current"><a href="functions_vars.html"><span>Variables</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions_vars.html#index_a"><span>a</span></a></li>
+    <li><a href="functions_vars_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="functions_vars_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="functions_vars_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="functions_vars_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="functions_vars_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="functions_vars_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="functions_vars_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="functions_vars_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="functions_vars_0x6c.html#index_l"><span>l</span></a></li>
+    <li id="current"><a href="functions_vars_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="functions_vars_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="functions_vars_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="functions_vars_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="functions_vars_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="functions_vars_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="functions_vars_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="functions_vars_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="functions_vars_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="functions_vars_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="functions_vars_0x77.html#index_w"><span>w</span></a></li>
+    <li><a href="functions_vars_0x78.html#index_x"><span>x</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_m">- m -</a></h3><ul>
+<li>max_packet
+: <a class="el" href="structdwc__hc.html#bd88f02eb286ba01d8d1b049e8975ccb">dwc_hc</a><li>max_packet_count
+: <a class="el" href="structdwc__otg__driver__module__params.html#bb7904edc790fce40ac04ed68a64217e">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#e17230afa013a15beda38565d19fa933">dwc_otg_core_params</a><li>max_transfer_size
+: <a class="el" href="structdwc__otg__driver__module__params.html#16cc5351ae1dfbcd81d56a7ec16e1748">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#e614d1d2ee740cd972ca76ed0dffec74">dwc_otg_core_params</a><li>maxp
+: <a class="el" href="structdwc__otg__qh.html#5975c2bede1ca0c6cfe9a66fe0a52567">dwc_otg_qh</a><li>maxpacket
+: <a class="el" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">dwc_ep</a><li>maxxfer
+: <a class="el" href="structdwc__ep.html#f60095e5ebedf7f98f3bfea77ce9a755">dwc_ep</a><li>mc
+: <a class="el" href="uniondeptsiz__data.html#45a97381fba9a7d9c3bde425334a60a5">deptsiz_data</a><li>min_ahb_freq
+: <a class="el" href="unionhwcfg4__data.html#0a12e214e53ded595dfa11157129ab8c">hwcfg4_data</a><li>modemismatch
+: <a class="el" href="uniongintsts__data.html#5fda463a80eb6927b2b875d64e8a0753">gintsts_data</a>, <a class="el" href="uniongintmsk__data.html#f62315fe9de8bb3bc371cb0a51927496">gintmsk_data</a><li>mpi_enable
+: <a class="el" href="structdwc__otg__driver__module__params.html#484412984c814a6298b05b58d94bd730">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#740e50199a75b3877b7db630d49c36aa">dwc_otg_core_params</a><li>mps
+: <a class="el" href="unionhcchar__data.html#47d11a5e62f69534d8ac0606aa7ffe7d">hcchar_data</a>, <a class="el" href="uniondepctl__data.html#5899d20333186341271c2d0b7781b98c">depctl_data</a>, <a class="el" href="structdwc__otg__hcd__pipe__info.html#b1d585e71a4e15bc79fc5f6d87bada6a">dwc_otg_hcd_pipe_info</a><li>mtrf
+: <a class="el" href="uniondev__dma__desc__sts.html#01c54383fd48fc31a3dd93ef54c417e8">dev_dma_desc_sts</a><li>multi_count
+: <a class="el" href="structdwc__hc.html#9a01b904f7ccc7178cdb80c20e8a9b0c">dwc_hc</a><li>multi_proc_int
+: <a class="el" href="unionhwcfg2__data.html#53c36944e5bd45e6f3ecbe933d7246eb">hwcfg2_data</a><li>multicnt
+: <a class="el" href="unionhcchar__data.html#9c0f515663251779e4960ec5613ce6fe">hcchar_data</a><li>multiproc_int_enable
+: <a class="el" href="structdwc__otg__core__if.html#5675c8d8dd7df746fda9157dc39ba5c2">dwc_otg_core_if</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x6e.html b/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x6e.html
new file mode 100644
index 000000000000..254c6c9e97d6
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x6e.html
@@ -0,0 +1,99 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions.html"><span>All</span></a></li>
+    <li><a href="functions_func.html"><span>Functions</span></a></li>
+    <li id="current"><a href="functions_vars.html"><span>Variables</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions_vars.html#index_a"><span>a</span></a></li>
+    <li><a href="functions_vars_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="functions_vars_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="functions_vars_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="functions_vars_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="functions_vars_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="functions_vars_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="functions_vars_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="functions_vars_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="functions_vars_0x6c.html#index_l"><span>l</span></a></li>
+    <li><a href="functions_vars_0x6d.html#index_m"><span>m</span></a></li>
+    <li id="current"><a href="functions_vars_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="functions_vars_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="functions_vars_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="functions_vars_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="functions_vars_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="functions_vars_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="functions_vars_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="functions_vars_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="functions_vars_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="functions_vars_0x77.html#index_w"><span>w</span></a></li>
+    <li><a href="functions_vars_0x78.html#index_x"><span>x</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_n">- n -</a></h3><ul>
+<li>n_bytes
+: <a class="el" href="unionhost__dma__desc__sts.html#a8f68a8a5c22c3c1b530400c23083892">host_dma_desc_sts</a>, <a class="el" href="structdwc__otg__qh.html#6b625d870c7854ccaff5c28fad87482a">dwc_otg_qh</a><li>n_desc
+: <a class="el" href="structdwc__otg__qtd.html#ef3021e617cf1f448bd23b1f7ab3859b">dwc_otg_qtd</a><li>nak
+: <a class="el" href="unionhcintmsk__data.html#32ae7d92d0eb93ced42ac3773ddc3a2f">hcintmsk_data</a>, <a class="el" href="unionhcint__data.html#ce65c9d3f0c7d3e5b8f163a378051c6c">hcint_data</a>, <a class="el" href="uniondoepint__data.html#2ac99fbbb1bcf135d5db41e096e8b95b">doepint_data</a>, <a class="el" href="uniondiepint__data.html#3ade814b2bef3085bb6fa32e94ea1aac">diepint_data</a><li>nakonbble
+: <a class="el" href="uniondctl__data.html#422c27727aa788391b807b62011bd464">dctl_data</a><li>naksts
+: <a class="el" href="uniondepctl__data.html#98d3916b91f9d3d6c460d0ffaffd7b8b">depctl_data</a><li>need_gadget_att
+: <a class="el" href="structcfiobject.html#f103d681f78c43dc92dd4a85cdbdc27c">cfiobject</a><li>need_status_in_complete
+: <a class="el" href="structcfiobject.html#8d35a323dcd29a1c9d1a8568bd514c3b">cfiobject</a><li>next_frame
+: <a class="el" href="structdwc__ep.html#1e9f4d08454c973c17acb3e52a2c3689">dwc_ep</a><li>nextep
+: <a class="el" href="uniondepctl__data.html#3bdea97ec728985cbc4b9305f3ed8e96">depctl_data</a><li>non_iso_thr_en
+: <a class="el" href="uniondthrctl__data.html#9b9e309f454fb10621cbaeafe068af47">dthrctl_data</a><li>non_iso_tx_thr_en
+: <a class="el" href="structdwc__otg__dev__if.html#c4c1cdbb40f37e3403d62ae00b4819eb">dwc_otg_dev_if</a><li>non_periodic_channels
+: <a class="el" href="structdwc__otg__hcd.html#e7fff26b5cce7c6c520c89f9e3c75617">dwc_otg_hcd</a><li>non_periodic_qh_ptr
+: <a class="el" href="structdwc__otg__hcd.html#01ab5791d6269b6b5d506f2113b94231">dwc_otg_hcd</a><li>non_periodic_sched_active
+: <a class="el" href="structdwc__otg__hcd.html#ffa3041ad517da9519aa2159cdec3f61">dwc_otg_hcd</a><li>non_periodic_sched_inactive
+: <a class="el" href="structdwc__otg__hcd.html#64c96c47a36d71bad6e4360cec9d07ad">dwc_otg_hcd</a><li>nonperio_tx_q_depth
+: <a class="el" href="unionhwcfg2__data.html#1369a191c7bd2f717cef2bce7a97ee67">hwcfg2_data</a><li>nperio_tx_fifo_size
+: <a class="el" href="structdwc__otg__core__if.html#fb77b09f04a5687d2087726edd8dece6">dwc_otg_core_if</a><li>nptxfemplvl_txfemplvl
+: <a class="el" href="uniongahbcfg__data.html#00758ec639d12cc80fd98b1a6526c454">gahbcfg_data</a><li>nptxfempty
+: <a class="el" href="uniongintsts__data.html#adebf5ff5bdf69a2bcf0bd4b2ba55ef4">gintsts_data</a>, <a class="el" href="uniongintmsk__data.html#2c395e7bef31a4d9b2d1a3257c601be4">gintmsk_data</a><li>nptxfrwnden
+: <a class="el" href="uniongusbcfg__data.html#3ac9a67298febe31dc67c802a7f77f0a">gusbcfg_data</a><li>nptxfspcavail
+: <a class="el" href="uniongnptxsts__data.html#6c149be246bcf5ca5395f67e67648207">gnptxsts_data</a><li>nptxqspcavail
+: <a class="el" href="uniongnptxsts__data.html#634ffd5e84bc422ddef043574d8f0957">gnptxsts_data</a><li>nptxqtop_chnep
+: <a class="el" href="uniongnptxsts__data.html#6f593581592d2c904db11b39f8275ed9">gnptxsts_data</a><li>nptxqtop_terminate
+: <a class="el" href="uniongnptxsts__data.html#8aeca3e7350acc25b9c0623eea88bfc3">gnptxsts_data</a><li>nptxqtop_token
+: <a class="el" href="uniongnptxsts__data.html#7675d024cc57442bd67d63551cb5dfcc">gnptxsts_data</a><li>ntd
+: <a class="el" href="unionhctsiz__data.html#ac1addd68951e1a6a25312d49be9895d">hctsiz_data</a>, <a class="el" href="structdwc__otg__qh.html#6da0f75ffa49c8ffadde42e9618ed8c8">dwc_otg_qh</a>, <a class="el" href="structdwc__hc.html#9a3a483b9c4e45d1ec5f475beb6a10a3">dwc_hc</a><li>num
+: <a class="el" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">dwc_ep</a><li>num_dev_ep
+: <a class="el" href="unionhwcfg2__data.html#9f827f334b58643849598ce1fa314c5a">hwcfg2_data</a><li>num_dev_mode_ctrl_ep
+: <a class="el" href="unionhwcfg4__data.html#51130a20d8311e691ea8b8565bbe3080">hwcfg4_data</a><li>num_dev_perio_in_ep
+: <a class="el" href="unionhwcfg4__data.html#aee60fb196cf53b610df556744e4d317">hwcfg4_data</a><li>num_host_chan
+: <a class="el" href="unionhwcfg2__data.html#83708a4d45e8d019892367c5ae9f6fd0">hwcfg2_data</a><li>num_host_channels
+: <a class="el" href="structdwc__otg__host__if.html#a7b144c7f83d79fdafd7cd0c8c06102d">dwc_otg_host_if</a><li>num_in_eps
+: <a class="el" href="structdwc__otg__dev__if.html#4fae9bc1293bf2e58966c38fa5b98822">dwc_otg_dev_if</a>, <a class="el" href="unionhwcfg4__data.html#753b321350388c5e1307802ff968f9a8">hwcfg4_data</a><li>num_out_eps
+: <a class="el" href="structdwc__otg__dev__if.html#2f0e01cdc605623f591963fc83c8dc73">dwc_otg_dev_if</a><li>nyet
+: <a class="el" href="unionhcintmsk__data.html#4274f9b730db0e390e5f3be4247ee45c">hcintmsk_data</a>, <a class="el" href="unionhcint__data.html#755e54c3dfded3653447dfdd63fd8b6a">hcint_data</a>, <a class="el" href="uniondoepint__data.html#f35ad8ba20b8941b6ad00dc75586454f">doepint_data</a><li>nzstsouthshk
+: <a class="el" href="uniondcfg__data.html#bfe8fbad12896d96cbeb686243f9602e">dcfg_data</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x6f.html b/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x6f.html
new file mode 100644
index 000000000000..42089793702c
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x6f.html
@@ -0,0 +1,101 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions.html"><span>All</span></a></li>
+    <li><a href="functions_func.html"><span>Functions</span></a></li>
+    <li id="current"><a href="functions_vars.html"><span>Variables</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions_vars.html#index_a"><span>a</span></a></li>
+    <li><a href="functions_vars_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="functions_vars_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="functions_vars_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="functions_vars_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="functions_vars_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="functions_vars_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="functions_vars_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="functions_vars_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="functions_vars_0x6c.html#index_l"><span>l</span></a></li>
+    <li><a href="functions_vars_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="functions_vars_0x6e.html#index_n"><span>n</span></a></li>
+    <li id="current"><a href="functions_vars_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="functions_vars_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="functions_vars_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="functions_vars_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="functions_vars_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="functions_vars_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="functions_vars_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="functions_vars_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="functions_vars_0x77.html#index_w"><span>w</span></a></li>
+    <li><a href="functions_vars_0x78.html#index_x"><span>x</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_o">- o -</a></h3><ul>
+<li>oddfrm
+: <a class="el" href="unionhcchar__data.html#1eae01428cc22feed785eedff05c86da">hcchar_data</a><li>offset
+: <a class="el" href="structdwc__otg__hcd__iso__packet__desc.html#246f3d147a22cd295c534253593dca4a">dwc_otg_hcd_iso_packet_desc</a>, <a class="el" href="structiso__pkt__info.html#0c72a0585ccc93555da4db7e168f75f8">iso_pkt_info</a><li>op_mode
+: <a class="el" href="unionhwcfg2__data.html#592df9b97ff9342b839d2ed76d54c652">hwcfg2_data</a><li>op_state
+: <a class="el" href="structdwc__otg__core__if.html#5a5c5c1cf8d870101cc1fffac56d88c0">dwc_otg_core_if</a><li>ops
+: <a class="el" href="structcfiobject.html#324b7481af9ba7a97233b162bbe8301a">cfiobject</a><li>opt
+: <a class="el" href="structdwc__otg__driver__module__params.html#bccaf8d2ce8da6d5ef0d1c81caf9e518">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#6d67db1b1152d788bf2fc7fdc6363f78">dwc_otg_core_params</a><li>optional_features
+: <a class="el" href="unionhwcfg3__data.html#37ea87e07a63864a3b985df59fe98c8d">hwcfg3_data</a><li>otg_cap
+: <a class="el" href="structdwc__otg__driver__module__params.html#985f1849ab70919e756c86280a8f7ef0">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#b6960c28e9c7d82dca37645726c8f7ce">dwc_otg_core_params</a><li>otg_enable_hsic
+: <a class="el" href="unionhwcfg3__data.html#8c83b7ac3a4bb366119aeb3195126445">hwcfg3_data</a><li>otg_enable_ic_usb
+: <a class="el" href="unionhwcfg3__data.html#a01a48361a21cb9dfbbd555823b8531b">hwcfg3_data</a><li>otg_func
+: <a class="el" href="unionhwcfg3__data.html#dcd27bbcb3f0e0f5fbd6e7e8b7db1865">hwcfg3_data</a><li>otg_lpm_en
+: <a class="el" href="unionhwcfg3__data.html#2b9c39a4ce021bfd039729ccf2c2c503">hwcfg3_data</a><li>otg_port
+: <a class="el" href="structdwc__otg__hcd.html#9231b4c3dce89a1506a5e501ec5c7a39">dwc_otg_hcd</a><li>otgintr
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+: <a class="el" href="uniongusbcfg__data.html#ef6e00f543156d1af19662c3ee86830d">gusbcfg_data</a><li>out
+: <a class="el" href="uniondaint__data.html#8462ad2dc1692f1253b769445382e2d4">daint_data</a><li>out_desc_addr
+: <a class="el" href="structdwc__otg__dev__if.html#8cc9be8ccaba2ef93b02b34ba7b26bad">dwc_otg_dev_if</a><li>out_ep
+: <a class="el" href="structgadget__wrapper.html#c420e5ba1a1c2d83d62471c423180d3c">gadget_wrapper</a>, <a class="el" href="structdwc__otg__pcd.html#b9e49a1d1fbca5ba9523e27c7108df30">dwc_otg_pcd</a>, <a class="el" href="structzero__dev.html#28a2079d55de6ac606cc69b79882223f">zero_dev</a><li>out_ep_regs
+: <a class="el" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">dwc_otg_dev_if</a><li>outep0
+: <a class="el" href="uniondaint__data.html#c7e9083edca852fb7f2f64e8671aee84">daint_data</a><li>outep1
+: <a class="el" href="uniondaint__data.html#32fab893aee2c30b343fcef45a2b663b">daint_data</a><li>outep10
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+: <a class="el" href="uniondaint__data.html#f8891bc2ff5fe8989c5119461e6ab126">daint_data</a><li>outep8
+: <a class="el" href="uniondaint__data.html#29c28a7d96343bfcc1f43faa72e83722">daint_data</a><li>outep9
+: <a class="el" href="uniondaint__data.html#8ad45fbc3efeb84ed83dc44b80e83c05">daint_data</a><li>outepintr
+: <a class="el" href="uniongintsts__data.html#58c08d29fa4b120748eb01b0d989facf">gintsts_data</a>, <a class="el" href="uniongintmsk__data.html#d48fe24e3e91bc1bcbc1c790c1b67f96">gintmsk_data</a><li>outpkterr
+: <a class="el" href="uniondoepint__data.html#dc9d4f243e80cd6796fcc334498fa4cc">doepint_data</a><li>outtknepdis
+: <a class="el" href="uniondoepint__data.html#3f02a0e998438229ec34bb1a8c1f4192">doepint_data</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x70.html b/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x70.html
new file mode 100644
index 000000000000..b6be1be98e7d
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x70.html
@@ -0,0 +1,144 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions.html"><span>All</span></a></li>
+    <li><a href="functions_func.html"><span>Functions</span></a></li>
+    <li id="current"><a href="functions_vars.html"><span>Variables</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions_vars.html#index_a"><span>a</span></a></li>
+    <li><a href="functions_vars_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="functions_vars_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="functions_vars_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="functions_vars_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="functions_vars_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="functions_vars_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="functions_vars_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="functions_vars_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="functions_vars_0x6c.html#index_l"><span>l</span></a></li>
+    <li><a href="functions_vars_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="functions_vars_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="functions_vars_0x6f.html#index_o"><span>o</span></a></li>
+    <li id="current"><a href="functions_vars_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="functions_vars_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="functions_vars_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="functions_vars_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="functions_vars_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="functions_vars_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="functions_vars_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="functions_vars_0x77.html#index_w"><span>w</span></a></li>
+    <li><a href="functions_vars_0x78.html#index_x"><span>x</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_p">- p -</a></h3><ul>
+<li>p
+: <a class="el" href="structdwc__otg__cil__callbacks.html#a486473d73fb104dc3a37e963a8ef8e5">dwc_otg_cil_callbacks</a><li>p_tx_msk
+: <a class="el" href="structdwc__otg__core__if.html#0683b28ebf5247a60247d27a1a714d27">dwc_otg_core_if</a><li>packet_count
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+: <a class="el" href="unionhwcfg3__data.html#a397ea503f5155d8e3a66cc82d7937f2">hwcfg3_data</a><li>pcd
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+: <a class="el" href="structdwc__otg__core__if.html#83bca1e02fafc4bbfa9c1f2eeb19b245">dwc_otg_core_if</a><li>pcgcctl
+: <a class="el" href="structdwc__otg__core__if.html#348ed2c9aeae6fc608f1bb813978b3f9">dwc_otg_core_if</a><li>perfrint
+: <a class="el" href="uniondcfg__data.html#f4ed8f15f1716ff0f9366badac18fbb4">dcfg_data</a><li>perio_ep_supported
+: <a class="el" href="unionhwcfg2__data.html#d0d29d530b38b3dcd58c88a2ef9688bb">hwcfg2_data</a><li>perio_eps_supported
+: <a class="el" href="structdwc__otg__host__if.html#23dedb1efa17aa1c199f1e3c6e2a9784">dwc_otg_host_if</a><li>perio_tx_fifo_size
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+: <a class="el" href="structdwc__otg__hcd.html#5754b87bd4644fbb7b90cf843c638f1c">dwc_otg_hcd</a><li>periodic_sched_assigned
+: <a class="el" href="structdwc__otg__hcd.html#4b8deae798f771135c4a99693b26873f">dwc_otg_hcd</a><li>periodic_sched_inactive
+: <a class="el" href="structdwc__otg__hcd.html#2a747cacd6bdbacbef86d4157c34a312">dwc_otg_hcd</a><li>periodic_sched_queued
+: <a class="el" href="structdwc__otg__hcd.html#e127912880eb487b3a2f38778c0de238">dwc_otg_hcd</a><li>periodic_sched_ready
+: <a class="el" href="structdwc__otg__hcd.html#74b089e094911a558f7b5f24681d3242">dwc_otg_hcd</a><li>periodic_usecs
+: <a class="el" href="structdwc__otg__hcd.html#1f2ce690c8ded506eff8d1b567747235">dwc_otg_hcd</a><li>perschedena
+: <a class="el" href="unionhcfg__data.html#b49be9c0cbc3df2bb917e1ea96c99c62">hcfg_data</a><li>perschedstat
+: <a class="el" href="unionhcfg__data.html#995a4d09381b8d6ce2c7ac0a6c7f364a">hcfg_data</a><li>phy_in_sleep
+: <a class="el" href="unionpcgcctl__data.html#f8b4b268a4fd5094a9a43ec503455f6f">pcgcctl_data</a><li>phy_init_done
+: <a class="el" href="structdwc__otg__core__if.html#24dd9dec510e5edac930538b81004b74">dwc_otg_core_if</a><li>phy_type
+: <a class="el" href="structdwc__otg__driver__module__params.html#77d1c10524440ed2e5189624157526ac">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#8b5d4e0c98c46d0d4e80b6faf66daf72">dwc_otg_core_params</a><li>phy_ulpi_ddr
+: <a class="el" href="structdwc__otg__driver__module__params.html#6a2b8c0c6298a7b1da23d5dd5abc4da8">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#6fc9a3fbe3c36cbbc231f1642ee96cfe">dwc_otg_core_params</a><li>phy_ulpi_ext_vbus
+: <a class="el" href="structdwc__otg__driver__module__params.html#8402de29e6ec24baa5881cb7d74914c2">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#3b6fa0a7fe7d7f87326894fdbe0aa375">dwc_otg_core_params</a><li>phy_utmi_width
+: <a class="el" href="structdwc__otg__driver__module__params.html#f6284c33f13fe2f02491fa1a0c479b25">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#41f5a03ab1b68564b240e03f33a09dde">dwc_otg_core_params</a><li>phyif
+: <a class="el" href="uniongusbcfg__data.html#f5e1a41cbdf6ae4b30a929ff3de8c99c">gusbcfg_data</a><li>phylpwrclksel
+: <a class="el" href="uniongusbcfg__data.html#9e4bac4a0ef0a045f97792f68c5f35df">gusbcfg_data</a><li>physel
+: <a class="el" href="uniongusbcfg__data.html#6680455bce7433ccec13377a20912e04">gusbcfg_data</a><li>physuspended
+: <a class="el" href="unionpcgcctl__data.html#c39017c4715319d740b749d16401f26c">pcgcctl_data</a><li>pid
+: <a class="el" href="unionhctsiz__data.html#d8b17af02c244e47ca0c38f933a6b3f0">hctsiz_data</a>, <a class="el" href="uniondev__dma__desc__sts.html#79bf5fe6d9949ddb671daa14b5ee298e">dev_dma_desc_sts</a><li>ping_state
+: <a class="el" href="structdwc__otg__qh.html#2c115474978a808c797c8975d72e419d">dwc_otg_qh</a><li>pipe_dir
+: <a class="el" href="structdwc__otg__hcd__pipe__info.html#8342fc4305ea957e2fa78f2bc9e707e4">dwc_otg_hcd_pipe_info</a><li>pipe_info
+: <a class="el" href="structdwc__otg__hcd__urb.html#34ee3ac5931687b41dd726f00c558369">dwc_otg_hcd_urb</a><li>pipe_type
+: <a class="el" href="structdwc__otg__hcd__pipe__info.html#0278c3069bc464cc4dbed8f6647f5856">dwc_otg_hcd_pipe_info</a><li>pkt_cnt
+: <a class="el" href="structdwc__ep.html#46349fb0608d8c6849ced211b0628c15">dwc_ep</a><li>pkt_info
+: <a class="el" href="structdwc__ep.html#a8ed15a24123a2dad6861da7d61dfb48">dwc_ep</a><li>pkt_per_frm
+: <a class="el" href="structdwc__ep.html#fe51420474de8a9d74fc9c4adc811c4b">dwc_ep</a><li>pktcnt
+: <a class="el" href="unionhctsiz__data.html#3ea18df5a98d33a6f8fa786252a0205b">hctsiz_data</a>, <a class="el" href="uniondeptsiz0__data.html#debb8f273e4480cde57bef7677697bd0">deptsiz0_data</a>, <a class="el" href="uniondeptsiz__data.html#bbd89e812371e5b555bb82373f3643d9">deptsiz_data</a><li>pktdrpsts
+: <a class="el" href="uniondoepint__data.html#0c8fc4f5245a9874c0c3b61d1c6f719d">doepint_data</a><li>pktsts
+: <a class="el" href="unionhost__grxsts__data.html#6dc2553475a56a445c6e6f319feffac8">host_grxsts_data</a>, <a class="el" href="uniondevice__grxsts__data.html#712eb005af256f84ebfc6f3083dd1ba8">device_grxsts_data</a><li>point2point
+: <a class="el" href="unionhwcfg2__data.html#6ef3a94368c53a22c222795bfc2306e3">hwcfg2_data</a><li>port_addr
+: <a class="el" href="structdwc__hc.html#9f597e05c37d7292f4c0d965c67ee3dd">dwc_hc</a><li>port_connect_status
+: <a class="el" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#9314ac02ed140807687793b512f78c63">dwc_otg_hcd::dwc_otg_hcd_internal_flags</a><li>port_connect_status_change
+: <a class="el" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#cd31ac4b9658265e90773448f354f0e1">dwc_otg_hcd::dwc_otg_hcd_internal_flags</a><li>port_enable_change
+: <a class="el" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#d222ae08372109a312f6649f77b650e8">dwc_otg_hcd::dwc_otg_hcd_internal_flags</a><li>port_l1_change
+: <a class="el" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#1900375ccea165f0efc40725f507a0bf">dwc_otg_hcd::dwc_otg_hcd_internal_flags</a><li>port_over_current_change
+: <a class="el" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#bc96cf12e2bc5b61ce05f15ae3297bd6">dwc_otg_hcd::dwc_otg_hcd_internal_flags</a><li>port_reset_change
+: <a class="el" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#d0d63f32ed35315e8a02549521fb386e">dwc_otg_hcd::dwc_otg_hcd_internal_flags</a><li>port_suspend_change
+: <a class="el" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#2a6e323cb4c01153aff1adc6269c74c7">dwc_otg_hcd::dwc_otg_hcd_internal_flags</a><li>portintr
+: <a class="el" href="uniongintsts__data.html#7490e48c2c93d20c182f00161f18b8e5">gintsts_data</a>, <a class="el" href="uniongintmsk__data.html#c907c60cbc7b157e730b053b40f4a2b3">gintmsk_data</a><li>power_optimiz
+: <a class="el" href="unionhwcfg4__data.html#3227ec0129191d0d099f0dce7f18c546">hwcfg4_data</a><li>priv
+: <a class="el" href="structdwc__otg__pcd__ep.html#8c8fad971c6c3b1c54d334c7f9b2d03e">dwc_otg_pcd_ep</a>, <a class="el" href="structdwc__otg__pcd__request.html#e0d93b64365968aa0dcf58535aecf40c">dwc_otg_pcd_request</a>, <a class="el" href="structdwc__otg__hcd.html#c019b908f209d577ccc19d29030926a1">dwc_otg_hcd</a>, <a class="el" href="structdwc__otg__hcd__urb.html#5ba0e393ef9768275db85c00e68be477">dwc_otg_hcd_urb</a><li>proc_buf_num
+: <a class="el" href="structdwc__ep.html#53033f174854701986545f05502e1cad">dwc_ep</a><li>prt_sleep_sts
+: <a class="el" href="unionglpmctl__data.html#241ff25a215f16ac29b3bb6d9f4943ed">glpmctl_data</a><li>prtaddr
+: <a class="el" href="unionhcsplt__data.html#e1c0812d6f655ea9915a6152c9f16cd6">hcsplt_data</a><li>prtconndet
+: <a class="el" href="unionhprt0__data.html#5124a40eeafd92c9632c91a2c3132937">hprt0_data</a><li>prtconnsts
+: <a class="el" href="unionhprt0__data.html#39b2dee944be8ec96857a3b43d203390">hprt0_data</a><li>prtena
+: <a class="el" href="unionhprt0__data.html#a964274b5d22e89ca4490f66dff3c763">hprt0_data</a><li>prtenchng
+: <a class="el" href="unionhprt0__data.html#75eae10eb537e49cc1ae2dc01c18aa47">hprt0_data</a><li>prtlnsts
+: <a class="el" href="unionhprt0__data.html#85a83fc17905d43dc604dce7f0869c63">hprt0_data</a><li>prtovrcurract
+: <a class="el" href="unionhprt0__data.html#4d8f8b654c26760791614ccbc43f180c">hprt0_data</a><li>prtovrcurrchng
+: <a class="el" href="unionhprt0__data.html#cc51da1d52cb824d419ef3feb6ba70b6">hprt0_data</a><li>prtpwr
+: <a class="el" href="unionhprt0__data.html#010bd8fb208ef4eeaa288b28f8f8c3a4">hprt0_data</a><li>prtres
+: <a class="el" href="unionhprt0__data.html#3f5961529636a3891a4ca9421dd535fa">hprt0_data</a><li>prtrst
+: <a class="el" href="unionhprt0__data.html#714a31048710164370292124795a9a9b">hprt0_data</a><li>prtspd
+: <a class="el" href="unionhprt0__data.html#59f1c27b8c912de0237d2d2974fc2a22">hprt0_data</a><li>prtsusp
+: <a class="el" href="unionhprt0__data.html#e7fe71d6c465ae002211c24a6ba359d2">hprt0_data</a><li>prttstctl
+: <a class="el" href="unionhprt0__data.html#c61d714ff8f0bc62767342523347ba66">hprt0_data</a><li>psetup
+: <a class="el" href="structdwc__otg__dev__if.html#ade28f08143342505c705db1fc0865a9">dwc_otg_dev_if</a><li>pti_enable
+: <a class="el" href="structdwc__otg__driver__module__params.html#2e17f84d9b07732a7fdf37b13832c54a">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#b601fde03b371b74deab1205e1329a7d">dwc_otg_core_params</a><li>pti_enh_enable
+: <a class="el" href="structdwc__otg__core__if.html#34540b79e9a14bfa234a52ac132c5cd1">dwc_otg_core_if</a><li>ptxfemplvl
+: <a class="el" href="uniongahbcfg__data.html#e45b68a6e6e681e58d70fd8e70f9542f">gahbcfg_data</a><li>ptxfempty
+: <a class="el" href="uniongintsts__data.html#54ed752629e9b8916507beca28d76162">gintsts_data</a>, <a class="el" href="uniongintmsk__data.html#3b52444894e041c660c146af2178272f">gintmsk_data</a><li>ptxfspcavail
+: <a class="el" href="unionhptxsts__data.html#0df6fb1f76396da626715d6ffc06dfa8">hptxsts_data</a><li>ptxqspcavail
+: <a class="el" href="unionhptxsts__data.html#8139e6eafb7b0bbb3cbafa125d5cd28f">hptxsts_data</a><li>ptxqtop_chnum
+: <a class="el" href="unionhptxsts__data.html#6fdf33c3add1fa286beaa252610b20ec">hptxsts_data</a><li>ptxqtop_odd
+: <a class="el" href="unionhptxsts__data.html#6b18b0bdf10050b08ac265e9143fdd63">hptxsts_data</a><li>ptxqtop_terminate
+: <a class="el" href="unionhptxsts__data.html#3c8a2ed8f4185130a28a452c0a9967f4">hptxsts_data</a><li>ptxqtop_token
+: <a class="el" href="unionhptxsts__data.html#e51712fd406526683b5c3311bd3dab8d">hptxsts_data</a><li>pwrclmp
+: <a class="el" href="unionpcgcctl__data.html#02d7dff0f26c3ac50ad4b876f1853c17">pcgcctl_data</a><li>pwronprgdone
+: <a class="el" href="uniondctl__data.html#216f929e4d24b0c3005cd0add0de7a27">dctl_data</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x71.html b/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x71.html
new file mode 100644
index 000000000000..65a9066faa80
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x71.html
@@ -0,0 +1,71 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions.html"><span>All</span></a></li>
+    <li><a href="functions_func.html"><span>Functions</span></a></li>
+    <li id="current"><a href="functions_vars.html"><span>Variables</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions_vars.html#index_a"><span>a</span></a></li>
+    <li><a href="functions_vars_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="functions_vars_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="functions_vars_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="functions_vars_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="functions_vars_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="functions_vars_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="functions_vars_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="functions_vars_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="functions_vars_0x6c.html#index_l"><span>l</span></a></li>
+    <li><a href="functions_vars_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="functions_vars_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="functions_vars_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="functions_vars_0x70.html#index_p"><span>p</span></a></li>
+    <li id="current"><a href="functions_vars_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="functions_vars_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="functions_vars_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="functions_vars_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="functions_vars_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="functions_vars_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="functions_vars_0x77.html#index_w"><span>w</span></a></li>
+    <li><a href="functions_vars_0x78.html#index_x"><span>x</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_q">- q -</a></h3><ul>
+<li>qh
+: <a class="el" href="structdwc__otg__qtd.html#f80ddcfb6edbe83a3991dd67c93a47e4">dwc_otg_qtd</a>, <a class="el" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">dwc_hc</a><li>qh_list_entry
+: <a class="el" href="structdwc__otg__qh.html#3e1cb9863dc72139e1832c04244c25ff">dwc_otg_qh</a><li>qtd
+: <a class="el" href="structdwc__otg__hcd__urb.html#68dc4d459bb70aed6083553653aadaad">dwc_otg_hcd_urb</a><li>qtd_list
+: <a class="el" href="structdwc__otg__qh.html#9567d266da8e796d3467fb16ae867f8e">dwc_otg_qh</a><li>qtd_offset
+: <a class="el" href="unionhost__dma__desc__sts.html#80be234e5bac143beca335ffe226eef6">host_dma_desc_sts</a><li>queue
+: <a class="el" href="structdwc__otg__pcd__ep.html#71f4fa571dfdc96f62fa4869e6add300">dwc_otg_pcd_ep</a><li>queue_sof
+: <a class="el" href="structdwc__otg__pcd__ep.html#bbec681b68f2f745d1cfecfedd4e64be">dwc_otg_pcd_ep</a><li>queuing_high_bandwidth
+: <a class="el" href="structdwc__otg__core__if.html#5a6a90b40bc80e71d40f107b68f1e84c">dwc_otg_core_if</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x72.html b/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x72.html
new file mode 100644
index 000000000000..2f53f8f64967
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x72.html
@@ -0,0 +1,141 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions.html"><span>All</span></a></li>
+    <li><a href="functions_func.html"><span>Functions</span></a></li>
+    <li id="current"><a href="functions_vars.html"><span>Variables</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions_vars.html#index_a"><span>a</span></a></li>
+    <li><a href="functions_vars_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="functions_vars_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="functions_vars_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="functions_vars_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="functions_vars_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="functions_vars_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="functions_vars_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="functions_vars_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="functions_vars_0x6c.html#index_l"><span>l</span></a></li>
+    <li><a href="functions_vars_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="functions_vars_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="functions_vars_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="functions_vars_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="functions_vars_0x71.html#index_q"><span>q</span></a></li>
+    <li id="current"><a href="functions_vars_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="functions_vars_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="functions_vars_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="functions_vars_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="functions_vars_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="functions_vars_0x77.html#index_w"><span>w</span></a></li>
+    <li><a href="functions_vars_0x78.html#index_x"><span>x</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_r">- r -</a></h3><ul>
+<li>reg_offset
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+: <a class="el" href="structdwc__otg__pcd.html#9d8e6d7f0ad10d580d467024e258f6f5">dwc_otg_pcd</a><li>req
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+: <a class="el" href="structdwc__otg__pcd.html#cbe5c4062e140ee88f51ee916c0db0ad">dwc_otg_pcd</a><li>request_pending
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+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x73.html b/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x73.html
new file mode 100644
index 000000000000..f7a0eb963c5d
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x73.html
@@ -0,0 +1,128 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions.html"><span>All</span></a></li>
+    <li><a href="functions_func.html"><span>Functions</span></a></li>
+    <li id="current"><a href="functions_vars.html"><span>Variables</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions_vars.html#index_a"><span>a</span></a></li>
+    <li><a href="functions_vars_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="functions_vars_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="functions_vars_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="functions_vars_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="functions_vars_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="functions_vars_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="functions_vars_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="functions_vars_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="functions_vars_0x6c.html#index_l"><span>l</span></a></li>
+    <li><a href="functions_vars_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="functions_vars_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="functions_vars_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="functions_vars_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="functions_vars_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="functions_vars_0x72.html#index_r"><span>r</span></a></li>
+    <li id="current"><a href="functions_vars_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="functions_vars_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="functions_vars_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="functions_vars_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="functions_vars_0x77.html#index_w"><span>w</span></a></li>
+    <li><a href="functions_vars_0x78.html#index_x"><span>x</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_s">- s -</a></h3><ul>
+<li>s
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+: <a class="el" href="uniondctl__data.html#2349dad5149cd3fcfd8fe3abcd77c32e">dctl_data</a><li>sgoutnak
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+: <a class="el" href="structdwc__hc.html#83e9a3cc9075b1fe21a6fa5190fa78c1">dwc_hc</a><li>sleep
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+: <a class="el" href="structdwc__otg__core__if.html#c2bb1913ed3fcc082a06d70242e9768a">dwc_otg_core_if</a><li>srp_timer
+: <a class="el" href="structdwc__otg__pcd.html#466fb6ae524fc970f164701db2e70246">dwc_otg_pcd</a><li>srp_timer_started
+: <a class="el" href="structdwc__otg__core__if.html#749cdeef193b7590b036a9b1d1442b73">dwc_otg_core_if</a><li>srpcap
+: <a class="el" href="uniongusbcfg__data.html#44485a787b8a386fadae801869ce7810">gusbcfg_data</a><li>ssplit_out_xfer_count
+: <a class="el" href="structdwc__otg__qtd.html#badffe465e850133c62c8f7e539f3fca">dwc_otg_qtd</a><li>stall
+: <a class="el" href="unionhcintmsk__data.html#94dc82e231d28d16d21238809cb88f78">hcintmsk_data</a>, <a class="el" href="unionhcint__data.html#cf2fb413e5758e9ebd8914b2f7605d73">hcint_data</a>, <a class="el" href="uniondepctl__data.html#f7ad1bcf91d28b8a4aa8d3a343dd83e4">depctl_data</a><li>stall_clear_flag
+: <a class="el" href="structdwc__ep.html#0d30d306e370810fc819f6ef735c7e67">dwc_ep</a><li>start
+: <a class="el" href="structdwc__otg__hcd__function__ops.html#d74a65269fe5712ac307bfd3230a29b4">dwc_otg_hcd_function_ops</a>, <a class="el" href="structdwc__otg__cil__callbacks.html#ebb662b2e0b4d187648b7f91b9d00713">dwc_otg_cil_callbacks</a><li>start_pkt_count
+: <a class="el" href="structdwc__hc.html#6c030bc725f43025d3046d17b4fbee4e">dwc_hc</a><li>start_split_frame
+: <a class="el" href="structdwc__otg__qh.html#a92b9ff45f0eca459b41ca20e4d8e99c">dwc_otg_qh</a><li>start_xfer_buff
+: <a class="el" href="structdwc__ep.html#d0cda8ded2e5142d9a1c9c17efc5812f">dwc_ep</a><li>start_xfer_tasklet
+: <a class="el" href="structdwc__otg__pcd.html#9b45cd00cd5835aba4236529a04b28f1">dwc_otg_pcd</a><li>startaddr
+: <a class="el" href="unionfifosize__data.html#26d78332a532cf9c0337c89edbff5f1b">fifosize_data</a><li>status
+: <a class="el" href="structdwc__otg__host__dma__desc.html#1b73b25e9fca51dd00fa0607d57d9e3f">dwc_otg_host_dma_desc</a>, <a class="el" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">dwc_otg_dev_dma_desc</a>, <a class="el" href="structdwc__otg__hcd__urb.html#101e4a6762b9911cdb85768890fa1210">dwc_otg_hcd_urb</a>, <a class="el" href="structdwc__otg__hcd__iso__packet__desc.html#d070772c24621c47b49ad21c6acadb94">dwc_otg_hcd_iso_packet_desc</a>, <a class="el" href="structiso__pkt__info.html#1317c3b425c0ef55dbde153b04c28dd4">iso_pkt_info</a><li>status_buf
+: <a class="el" href="structdwc__otg__pcd.html#ca247241f78970f27e5c964fc04d47c8">dwc_otg_pcd</a>, <a class="el" href="structdwc__otg__hcd.html#68627912f0d3672096e6a98be38f66ab">dwc_otg_hcd</a><li>status_buf_dma
+: <a class="el" href="structdwc__otg__hcd.html#3e752b2c5d632d848f3b1fadf543e7a4">dwc_otg_hcd</a><li>status_buf_dma_handle
+: <a class="el" href="structdwc__otg__pcd.html#c3880dd4ce15c515ba37b90b6e7fd293">dwc_otg_pcd</a><li>stop
+: <a class="el" href="structdwc__otg__cil__callbacks.html#cd604365bc84ceda780e10c2344870e4">dwc_otg_cil_callbacks</a><li>stoppclk
+: <a class="el" href="unionpcgcctl__data.html#bf40184845ef70be8e59b2672cb0bedf">pcgcctl_data</a><li>stopped
+: <a class="el" href="structdwc__otg__pcd__ep.html#cce0e089118d8bf7c6278c21ded70d5a">dwc_otg_pcd_ep</a><li>sts
+: <a class="el" href="unionhost__dma__desc__sts.html#828b019082523c4637758bef38805420">host_dma_desc_sts</a>, <a class="el" href="uniondev__dma__desc__sts.html#2be04f03ca64c3484260b2235aef3b9b">dev_dma_desc_sts</a><li>stsphsercvd
+: <a class="el" href="uniondoepint__data.html#038fca8f1c03d7cfe323caa4f8bda126">doepint_data</a><li>sup
+: <a class="el" href="unionhost__dma__desc__sts.html#634060a1b436857e15e8eb8f0d6d000a">host_dma_desc_sts</a><li>supcnt
+: <a class="el" href="uniondeptsiz0__data.html#60123707d51d7dfa22cd6b245402e49b">deptsiz0_data</a><li>suspend
+: <a class="el" href="structdwc__otg__pcd__function__ops.html#fef8ed359353cb84b7c5ac641d54d296">dwc_otg_pcd_function_ops</a>, <a class="el" href="structdwc__otg__cil__callbacks.html#a9e06ccc347fa446e2b131532e203d94">dwc_otg_cil_callbacks</a><li>suspsts
+: <a class="el" href="uniondsts__data.html#4c7cd8ee3877701268846b0b02ac3d97">dsts_data</a><li>sync_frame
+: <a class="el" href="structdwc__ep.html#1b9094ddfba3cddf397fd308cdbf4c81">dwc_ep</a><li>synch_reset_type
+: <a class="el" href="unionhwcfg3__data.html#2aee57ed6a1fb0c63830b9f3b3754373">hwcfg3_data</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x74.html b/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x74.html
new file mode 100644
index 000000000000..952cc30fd044
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x74.html
@@ -0,0 +1,88 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions.html"><span>All</span></a></li>
+    <li><a href="functions_func.html"><span>Functions</span></a></li>
+    <li id="current"><a href="functions_vars.html"><span>Variables</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions_vars.html#index_a"><span>a</span></a></li>
+    <li><a href="functions_vars_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="functions_vars_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="functions_vars_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="functions_vars_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="functions_vars_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="functions_vars_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="functions_vars_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="functions_vars_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="functions_vars_0x6c.html#index_l"><span>l</span></a></li>
+    <li><a href="functions_vars_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="functions_vars_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="functions_vars_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="functions_vars_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="functions_vars_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="functions_vars_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="functions_vars_0x73.html#index_s"><span>s</span></a></li>
+    <li id="current"><a href="functions_vars_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="functions_vars_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="functions_vars_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="functions_vars_0x77.html#index_w"><span>w</span></a></li>
+    <li><a href="functions_vars_0x78.html#index_x"><span>x</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_t">- t -</a></h3><ul>
+<li>td_first
+: <a class="el" href="structdwc__otg__qh.html#3b20e91c00b1de8d42612a8b1250b403">dwc_otg_qh</a><li>td_last
+: <a class="el" href="structdwc__otg__qh.html#9bd6dc808af3f1cab76ae7819af479f9">dwc_otg_qh</a><li>term_sel_dl_pulse
+: <a class="el" href="uniongusbcfg__data.html#d075f50f1d962c57ff491291f66f1778">gusbcfg_data</a><li>test_mode
+: <a class="el" href="structdwc__otg__pcd.html#577c57ee60c2ef42dce7791c85d50394">dwc_otg_pcd</a><li>test_mode_tasklet
+: <a class="el" href="structdwc__otg__pcd.html#d1aed2eb03a93032a1ce80e3145bb81e">dwc_otg_pcd</a><li>thr_ctl
+: <a class="el" href="structdwc__otg__driver__module__params.html#7fe5c7ff692926fb5cbe3b10d4123594">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#1610a4b28bea581c46f251d995bf4a51">dwc_otg_core_params</a><li>timeout
+: <a class="el" href="uniondiepint__data.html#2513e8eef259c711e9a139cb2631b142">diepint_data</a><li>total_fifo_size
+: <a class="el" href="structdwc__otg__core__if.html#cae59008a554cb7de24bd4f2afea7532">dwc_otg_core_if</a><li>total_len
+: <a class="el" href="structdwc__ep.html#5a218f200cff0491b735f43fed5176bf">dwc_ep</a><li>toutcal
+: <a class="el" href="uniongusbcfg__data.html#5dd00ef14661fce822a6ece15cf16799">gusbcfg_data</a><li>ts_dline
+: <a class="el" href="structdwc__otg__driver__module__params.html#25f8f9c3558aa01fecf8bcd1527ee6cc">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#879afefd6e13233a78d74ee71d3ee75e">dwc_otg_core_params</a><li>tstctl
+: <a class="el" href="uniondctl__data.html#ef7a2687eef3086056f30b13f3588f9e">dctl_data</a><li>tx_end_delay
+: <a class="el" href="uniongusbcfg__data.html#581b301bfa1951e1bd8ee20aa7256dc2">gusbcfg_data</a><li>tx_fifo_num
+: <a class="el" href="structdwc__ep.html#ffa14f48094778143353b845b5d238cd">dwc_ep</a><li>tx_fifo_size
+: <a class="el" href="structdwc__otg__dev__if.html#ea32a81a3c0a752e6d6274f8fd6faef9">dwc_otg_dev_if</a><li>tx_msk
+: <a class="el" href="structdwc__otg__core__if.html#b558bae74403677f08e45c692a88d4e2">dwc_otg_core_if</a><li>tx_thr_len
+: <a class="el" href="uniondthrctl__data.html#75959c97b938bf99faa602c933938340">dthrctl_data</a><li>tx_thr_length
+: <a class="el" href="structdwc__otg__dev__if.html#55206f9ce7b0c2614e2c534d01acd6c4">dwc_otg_dev_if</a>, <a class="el" href="structdwc__otg__driver__module__params.html#04d15f44d06c291acfeef82812bd1c65">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#c92fc907d503f9b8bb3600164c520b0e">dwc_otg_core_params</a><li>txbytes
+: <a class="el" href="uniondev__dma__desc__sts.html#56cc3ad6b0e5704c6eb394f58f660eef">dev_dma_desc_sts</a><li>txfflsh
+: <a class="el" href="uniongrstctl__data.html#8a5fcfc953bd0ba61beb36739c70b0ef">grstctl_data</a><li>txfifoundrn
+: <a class="el" href="uniondiepint__data.html#90d0e6a99275eccd4a50f62644de9152">diepint_data</a><li>txfnum
+: <a class="el" href="uniondepctl__data.html#89fd2f9f2183a32181e9a04bf3251c43">depctl_data</a>, <a class="el" href="uniongrstctl__data.html#d074ddfa3331eeb6d088e35f4f627481">grstctl_data</a><li>txfspcavail
+: <a class="el" href="uniondtxfsts__data.html#83db0e2dbe071694f549a383b7037b3b">dtxfsts_data</a><li>txsts
+: <a class="el" href="uniondev__dma__desc__sts.html#30ebc024572822f0803d28c95914a44c">dev_dma_desc_sts</a><li>type
+: <a class="el" href="structdwc__ep.html#17b10677bd9b0a1d612dd4ce2fb0eb0f">dwc_ep</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x75.html b/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x75.html
new file mode 100644
index 000000000000..54c5ed9727c4
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x75.html
@@ -0,0 +1,78 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions.html"><span>All</span></a></li>
+    <li><a href="functions_func.html"><span>Functions</span></a></li>
+    <li id="current"><a href="functions_vars.html"><span>Variables</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions_vars.html#index_a"><span>a</span></a></li>
+    <li><a href="functions_vars_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="functions_vars_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="functions_vars_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="functions_vars_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="functions_vars_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="functions_vars_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="functions_vars_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="functions_vars_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="functions_vars_0x6c.html#index_l"><span>l</span></a></li>
+    <li><a href="functions_vars_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="functions_vars_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="functions_vars_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="functions_vars_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="functions_vars_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="functions_vars_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="functions_vars_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="functions_vars_0x74.html#index_t"><span>t</span></a></li>
+    <li id="current"><a href="functions_vars_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="functions_vars_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="functions_vars_0x77.html#index_w"><span>w</span></a></li>
+    <li><a href="functions_vars_0x78.html#index_x"><span>x</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_u">- u -</a></h3><ul>
+<li>ulpi_auto_res
+: <a class="el" href="uniongusbcfg__data.html#404cb37d84dd990f4df89fc904bb7a63">gusbcfg_data</a><li>ulpi_clk_sus_m
+: <a class="el" href="uniongusbcfg__data.html#017fa2eb1df13d0917ffc6b243e5064c">gusbcfg_data</a><li>ulpi_ext_vbus_drv
+: <a class="el" href="uniongusbcfg__data.html#f4784a3028f221e2aed6138ecef53048">gusbcfg_data</a><li>ulpi_fs_ls
+: <a class="el" href="structdwc__otg__driver__module__params.html#33489751a5cef9e462d26e92caae3031">dwc_otg_driver_module_params</a>, <a class="el" href="structdwc__otg__core__params.html#3d7cfc3c416010102b2c671dfaa828d5">dwc_otg_core_params</a><li>ulpi_fsls
+: <a class="el" href="uniongusbcfg__data.html#de6d061bf2d0d8c909e6f7d701977b73">gusbcfg_data</a><li>ulpi_int_vbus_indicator
+: <a class="el" href="uniongusbcfg__data.html#b71576ecb647b9d81aa8c9b45c9fe14d">gusbcfg_data</a><li>ulpi_utmi_sel
+: <a class="el" href="uniongusbcfg__data.html#f86631568e6d3682cdba6482608bdcfe">gusbcfg_data</a><li>unused
+: <a class="el" href="structdwc__otg__dev__out__ep__regs.html#f78d72b82ee55e6a35cada1bd89d5659">dwc_otg_dev_out_ep_regs</a>, <a class="el" href="structdwc__otg__dev__global__regs.html#8d6452da1d0e266737d77e55fc15f72c">dwc_otg_dev_global_regs</a><li>urb
+: <a class="el" href="structdwc__otg__qtd.html#7e7767808e8eb9d71de0db00f57553f9">dwc_otg_qtd</a><li>usbactep
+: <a class="el" href="uniondepctl__data.html#2ddb1e68ac29dfc383dacd94f76b4710">depctl_data</a><li>usbreset
+: <a class="el" href="uniongintsts__data.html#76926be659d963c79dbcec91e25ce8ed">gintsts_data</a>, <a class="el" href="uniongintmsk__data.html#de79426e6a5436e34cf4b1ac42a72ee6">gintmsk_data</a><li>usbsuspend
+: <a class="el" href="uniongintsts__data.html#de67a7536cdb9305e24f05d771708bce">gintsts_data</a>, <a class="el" href="uniongintmsk__data.html#3b93f1ae00dcd1dcc4d6d19547f26b56">gintmsk_data</a><li>usbtrdtim
+: <a class="el" href="uniongusbcfg__data.html#d3e238db709189683bc41db2a67e9d61">gusbcfg_data</a><li>usecs
+: <a class="el" href="structdwc__otg__qh.html#401de6aadcfc2f99773f44c6731c4646">dwc_otg_qh</a><li>utmi_phy_data_width
+: <a class="el" href="unionhwcfg4__data.html#31e5336f64bdea1bb8e1e358375b20f0">hwcfg4_data</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x76.html b/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x76.html
new file mode 100644
index 000000000000..6bc749520fcc
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x76.html
@@ -0,0 +1,65 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions.html"><span>All</span></a></li>
+    <li><a href="functions_func.html"><span>Functions</span></a></li>
+    <li id="current"><a href="functions_vars.html"><span>Variables</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions_vars.html#index_a"><span>a</span></a></li>
+    <li><a href="functions_vars_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="functions_vars_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="functions_vars_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="functions_vars_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="functions_vars_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="functions_vars_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="functions_vars_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="functions_vars_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="functions_vars_0x6c.html#index_l"><span>l</span></a></li>
+    <li><a href="functions_vars_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="functions_vars_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="functions_vars_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="functions_vars_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="functions_vars_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="functions_vars_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="functions_vars_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="functions_vars_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="functions_vars_0x75.html#index_u"><span>u</span></a></li>
+    <li id="current"><a href="functions_vars_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="functions_vars_0x77.html#index_w"><span>w</span></a></li>
+    <li><a href="functions_vars_0x78.html#index_x"><span>x</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_v">- v -</a></h3><ul>
+<li>vbus_valid_filt_en
+: <a class="el" href="unionhwcfg4__data.html#5cbe1c265b6623dff23460111142db7d">hwcfg4_data</a><li>vendor_ctrl_if
+: <a class="el" href="unionhwcfg3__data.html#5008cb6cf85beb23f391e8ccf7306884">hwcfg3_data</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x77.html b/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x77.html
new file mode 100644
index 000000000000..973b698e6651
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x77.html
@@ -0,0 +1,79 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions.html"><span>All</span></a></li>
+    <li><a href="functions_func.html"><span>Functions</span></a></li>
+    <li id="current"><a href="functions_vars.html"><span>Variables</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions_vars.html#index_a"><span>a</span></a></li>
+    <li><a href="functions_vars_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="functions_vars_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="functions_vars_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="functions_vars_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="functions_vars_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="functions_vars_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="functions_vars_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="functions_vars_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="functions_vars_0x6c.html#index_l"><span>l</span></a></li>
+    <li><a href="functions_vars_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="functions_vars_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="functions_vars_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="functions_vars_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="functions_vars_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="functions_vars_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="functions_vars_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="functions_vars_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="functions_vars_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="functions_vars_0x76.html#index_v"><span>v</span></a></li>
+    <li id="current"><a href="functions_vars_0x77.html#index_w"><span>w</span></a></li>
+    <li><a href="functions_vars_0x78.html#index_x"><span>x</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_w">- w -</a></h3><ul>
+<li>wCoreID
+: <a class="el" href="structcfi__all__features__header.html#f6840858aad78617369b7decba6ef5e3">cfi_all_features_header</a><li>wDataLength
+: <a class="el" href="structcfi__feature__desc__header.html#0f33193eaf5853b1d3454adce81105d4">cfi_feature_desc_header</a><li>wDepth
+: <a class="el" href="struct__rx__fifo__size__setup.html#a05d30e9417ac8c2ec0fd2c1ec49be71">_rx_fifo_size_setup</a>, <a class="el" href="struct__tx__fifo__size__setup.html#70fb102a57e335dd8ee56096f3a9f99d">_tx_fifo_size_setup</a><li>wFeatureID
+: <a class="el" href="structcfi__feature__desc__header.html#f76e757383a5210368e599f872952170">cfi_feature_desc_header</a><li>wIndex
+: <a class="el" href="structcfi__usb__ctrlrequest.html#984c95bd61e8d1120cd935bcbc5d7134">cfi_usb_ctrlrequest</a><li>wkp_timer
+: <a class="el" href="structdwc__otg__core__if.html#c914461f460deacd426bea7a05ebb204">dwc_otg_core_if</a><li>wkupintr
+: <a class="el" href="uniongintsts__data.html#d2e845fd68f2e8abe6b7445dbde9d2a4">gintsts_data</a>, <a class="el" href="uniongintmsk__data.html#d3cde0fd62a006ec3f5db615f1e62da5">gintmsk_data</a><li>wLength
+: <a class="el" href="structcfi__usb__ctrlrequest.html#60d71d1239e46e787f0b4c626de7c769">cfi_usb_ctrlrequest</a>, <a class="el" href="structcfi__feature__desc__header.html#77769436c06687bdbe98c5e75e7641df">cfi_feature_desc_header</a><li>wNumFeatures
+: <a class="el" href="structcfi__all__features__header.html#e7abb90105e5cfd6ddfe8ba5dfaf8fa1">cfi_all_features_header</a><li>wq_otg
+: <a class="el" href="structdwc__otg__core__if.html#7e3716f6d6bc6f956a45efbe6e308386">dwc_otg_core_if</a><li>wrap_bit
+: <a class="el" href="uniondtknq1__data.html#9ae9021519e7fa501c86093c7718dbb4">dtknq1_data</a><li>wSize
+: <a class="el" href="struct__ddma__concat__buffer__setup__hdr.html#d59713609608ce8aab53c43332073ef7">_ddma_concat_buffer_setup_hdr</a>, <a class="el" href="struct__ddma__sg__buffer__setup.html#728db9bac2db62f7e7b2b9ccb0873546">_ddma_sg_buffer_setup</a><li>wTotalLen
+: <a class="el" href="structcfi__all__features__header.html#3973fa190311671de5bbd74a7b825f42">cfi_all_features_header</a><li>wTxBytes
+: <a class="el" href="struct__ddma__concat__buffer__setup.html#748241a5b55a514f4386498aceb1e505">_ddma_concat_buffer_setup</a><li>wValue
+: <a class="el" href="structcfi__usb__ctrlrequest.html#2f236bbf9450df1a3b5204c4570d883f">cfi_usb_ctrlrequest</a><li>wVersion
+: <a class="el" href="structcfi__all__features__header.html#3542d584c0c68a73351c7d2530f25c6d">cfi_all_features_header</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x78.html b/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x78.html
new file mode 100644
index 000000000000..a2e2b548dc6c
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x78.html
@@ -0,0 +1,77 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions.html"><span>All</span></a></li>
+    <li><a href="functions_func.html"><span>Functions</span></a></li>
+    <li id="current"><a href="functions_vars.html"><span>Variables</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="functions_vars.html#index_a"><span>a</span></a></li>
+    <li><a href="functions_vars_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="functions_vars_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="functions_vars_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="functions_vars_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="functions_vars_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="functions_vars_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="functions_vars_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="functions_vars_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="functions_vars_0x6c.html#index_l"><span>l</span></a></li>
+    <li><a href="functions_vars_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="functions_vars_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="functions_vars_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="functions_vars_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="functions_vars_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="functions_vars_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="functions_vars_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="functions_vars_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="functions_vars_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="functions_vars_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="functions_vars_0x77.html#index_w"><span>w</span></a></li>
+    <li id="current"><a href="functions_vars_0x78.html#index_x"><span>x</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_x">- x -</a></h3><ul>
+<li>xact_pos
+: <a class="el" href="structdwc__hc.html#3cde49a724756e16eb11a027360b2d4b">dwc_hc</a><li>xacterr
+: <a class="el" href="unionhcintmsk__data.html#29686b2c0b9502932327915d690a45d5">hcintmsk_data</a>, <a class="el" href="unionhcint__data.html#86ec2d311ef29228676781f9100d195a">hcint_data</a><li>xactpos
+: <a class="el" href="unionhcsplt__data.html#68e7b96ce2ca96c96f40b4f95c679a11">hcsplt_data</a><li>xcs_xact
+: <a class="el" href="unionhcintmsk__data.html#ace04f1b0f78826b8d33b828d4e637c2">hcintmsk_data</a>, <a class="el" href="unionhcint__data.html#f13613b1a33edddb676d2bce8a35e447">hcint_data</a><li>xfer_buff
+: <a class="el" href="structdwc__hc.html#9dc781cb9e4bc639765beee37ce76673">dwc_hc</a>, <a class="el" href="structdwc__ep.html#97fa9bf5c31ba734d54f70e6fe6ae8eb">dwc_ep</a><li>xfer_buff0
+: <a class="el" href="structdwc__ep.html#b6d727e366ac589d304256c758d2d44a">dwc_ep</a><li>xfer_buff1
+: <a class="el" href="structdwc__ep.html#36ff87362a0da5bce95eaf85522d49ff">dwc_ep</a><li>xfer_count
+: <a class="el" href="structdwc__hc.html#6199aaeab2d64954311c410b30270293">dwc_hc</a>, <a class="el" href="structdwc__ep.html#23d4871510b5bcb54fbf0674d8f122bd">dwc_ep</a><li>xfer_len
+: <a class="el" href="structdwc__hc.html#ce32fe93214f1686896e924fbf61cac7">dwc_hc</a>, <a class="el" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">dwc_ep</a>, <a class="el" href="structcfi__ep.html#f85903cb9e179124e42d98d557098011">cfi_ep</a><li>xfer_size_cntr_width
+: <a class="el" href="unionhwcfg3__data.html#66f311995decf2f11d620aa6a56fa26e">hwcfg3_data</a><li>xfer_started
+: <a class="el" href="structdwc__hc.html#78a1cf134604b24bfdedb4f4df9f2c1f">dwc_hc</a><li>xfercomp
+: <a class="el" href="unionhcint__data.html#49385cb90c4d8c003cfac91175a646e0">hcint_data</a><li>xfercompl
+: <a class="el" href="unionhcintmsk__data.html#4983a78156d96d9a0c16ca8ea2b09106">hcintmsk_data</a>, <a class="el" href="uniondoepint__data.html#341f7ffa5a9da7f6b1e09e9f4cc516a3">doepint_data</a>, <a class="el" href="uniondiepint__data.html#56e1252841323973e0ada12cc89059c9">diepint_data</a><li>xfersize
+: <a class="el" href="unionhctsiz__data.html#6ad01d874d77aa4382f71fa68eaec12d">hctsiz_data</a>, <a class="el" href="uniondeptsiz0__data.html#1792e672dde70ead19bd0f5e7642af03">deptsiz0_data</a>, <a class="el" href="uniondeptsiz__data.html#cf06327d851e7cfe5c442b29bf2d6fa4">deptsiz_data</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals.html b/drivers/usb/host/dwc_otg/doc/html/globals.html
new file mode 100644
index 000000000000..3074c2729010
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals.html
@@ -0,0 +1,87 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li id="current"><a href="globals.html"><span>All</span></a></li>
+    <li><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li id="current"><a href="globals.html#index__"><span>_</span></a></li>
+    <li><a href="globals_0x61.html#index_a"><span>a</span></a></li>
+    <li><a href="globals_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="globals_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="globals_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="globals_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="globals_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="globals_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="globals_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="globals_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="globals_0x6b.html#index_k"><span>k</span></a></li>
+    <li><a href="globals_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="globals_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="globals_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="globals_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="globals_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="globals_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="globals_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="globals_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="globals_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="globals_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="globals_0x77.html#index_w"><span>w</span></a></li>
+  </ul>
+</div>
+
+<p>
+Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:
+<p>
+<h3><a class="anchor" name="index__">- _ -</a></h3><ul>
+<li>__DWC_CFI_COMMON_H__
+: <a class="el" href="dwc__cfi__common_8h.html#50e76b6bdcb8e42b2b48aada9a1833e2">dwc_cfi_common.h</a><li>__DWC_CIL_H__
+: <a class="el" href="dwc__otg__cil_8h.html#c9555551bb7f2d0a51be23d54463f2ec">dwc_otg_cil.h</a><li>__DWC_CORE_IF_H__
+: <a class="el" href="dwc__otg__core__if_8h.html#5bae757850823a08f21d3c2156dcdb19">dwc_otg_core_if.h</a><li>__DWC_OTG_ATTR_H__
+: <a class="el" href="dwc__otg__attr_8h.html#338d875aceea377e37f82aa8fe743420">dwc_otg_attr.h</a><li>__DWC_OTG_CFI_H__
+: <a class="el" href="dwc__otg__cfi_8h.html#d4efa118a5f5c82587650944721a8dc1">dwc_otg_cfi.h</a><li>__DWC_PCD_H__
+: <a class="el" href="dwc__otg__pcd_8h.html#ed26bb67f5785dc6e70289976637a310">dwc_otg_pcd.h</a><li>__DWC_PCD_IF_H__
+: <a class="el" href="dwc__otg__pcd__if_8h.html#f647f1720e56adb91588a6e55179dec5">dwc_otg_pcd_if.h</a><li>_complete()
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#e1d629bc692aa1e42584459867b1aeaa">dwc_otg_pcd_linux.c</a>, <a class="el" href="dwc__otg__hcd__linux_8c.html#a0d18986574c384e98aa280e0475a9aa">dwc_otg_hcd_linux.c</a><li>_connect()
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#c7c1c4f8fe8e62f1d9e6f75de5563658">dwc_otg_pcd_linux.c</a><li>_disconnect()
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#682f9829330d06521a5d4c00702e4580">dwc_otg_pcd_linux.c</a>, <a class="el" href="dwc__otg__hcd__linux_8c.html#8011f9b662a7f4182e762de616bbc95e">dwc_otg_hcd_linux.c</a><li>_get_b_hnp_enable()
+: <a class="el" href="dwc__otg__hcd__linux_8c.html#578b76a201e8e722e31afdcd2c35dac9">dwc_otg_hcd_linux.c</a><li>_hnp_changed()
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#9e8595e1d36e6b1ffbc27c4862957a08">dwc_otg_pcd_linux.c</a><li>_hub_info()
+: <a class="el" href="dwc__otg__hcd__linux_8c.html#f4fe5a6082e7cce809f3e2a4cb71a7e4">dwc_otg_hcd_linux.c</a><li>_isoc_complete()
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#737e47386e05da8cf6cbf85a289f5454">dwc_otg_pcd_linux.c</a><li>_reset()
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#208cf9e0227e5f81e015ed3ac5bacec4">dwc_otg_pcd_linux.c</a><li>_resume()
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#86cdfe71d125da339e17e52049fc5ea0">dwc_otg_pcd_linux.c</a><li>_setup()
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#4a1481839b3d869d882f984a6c6ed9e5">dwc_otg_pcd_linux.c</a><li>_speed()
+: <a class="el" href="dwc__otg__hcd__linux_8c.html#22cff3e20b45ec02e81e54a1adacfa20">dwc_otg_hcd_linux.c</a><li>_start()
+: <a class="el" href="dwc__otg__hcd__linux_8c.html#e11ebd665a86e6ec3fd661965acca90e">dwc_otg_hcd_linux.c</a><li>_suspend()
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#7f479ecaee0801b55b4f0bd0f36f8b67">dwc_otg_pcd_linux.c</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_0x61.html b/drivers/usb/host/dwc_otg/doc/html/globals_0x61.html
new file mode 100644
index 000000000000..f9054d6cc06a
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_0x61.html
@@ -0,0 +1,76 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li id="current"><a href="globals.html"><span>All</span></a></li>
+    <li><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html#index__"><span>_</span></a></li>
+    <li id="current"><a href="globals_0x61.html#index_a"><span>a</span></a></li>
+    <li><a href="globals_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="globals_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="globals_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="globals_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="globals_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="globals_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="globals_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="globals_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="globals_0x6b.html#index_k"><span>k</span></a></li>
+    <li><a href="globals_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="globals_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="globals_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="globals_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="globals_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="globals_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="globals_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="globals_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="globals_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="globals_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="globals_0x77.html#index_w"><span>w</span></a></li>
+  </ul>
+</div>
+
+<p>
+Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:
+<p>
+<h3><a class="anchor" name="index_a">- a -</a></h3><ul>
+<li>A_HOST
+: <a class="el" href="dwc__otg__cil_8h.html#a0732b344b6571a4554968e4ee2214dd">dwc_otg_cil.h</a><li>A_PERIPHERAL
+: <a class="el" href="dwc__otg__cil_8h.html#7528970c03451cfc85e86ab92bbaf554">dwc_otg_cil.h</a><li>A_SUSPEND
+: <a class="el" href="dwc__otg__cil_8h.html#da9f5eb506da71435e8976ceb38bc14d">dwc_otg_cil.h</a><li>alloc_iso_request()
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#94fd50b5e9d41d1d38a503d819fc07c4">dwc_otg_pcd_linux.c</a><li>alloc_wrapper()
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#e0f94c48914d5f911f7623a53c5385a9">dwc_otg_pcd_linux.c</a><li>allocate_bus_bandwidth()
+: <a class="el" href="dwc__otg__hcd__linux_8c.html#e270a6a091a674ccf6f390fdcf746b87">dwc_otg_hcd_linux.c</a><li>assign_and_init_hc()
+: <a class="el" href="dwc__otg__hcd_8c.html#08cefee3729196462fe6a7608046652c">dwc_otg_hcd.c</a><li>assign_perio_tx_fifo()
+: <a class="el" href="dwc__otg__pcd_8c.html#1df421d3a1449ec3a927d0a006c57c38">dwc_otg_pcd.c</a><li>assign_tx_fifo()
+: <a class="el" href="dwc__otg__pcd_8c.html#5b3f2d055af51e556be50f3ada673e4a">dwc_otg_pcd.c</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_0x62.html b/drivers/usb/host/dwc_otg/doc/html/globals_0x62.html
new file mode 100644
index 000000000000..b9299fc63ac7
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_0x62.html
@@ -0,0 +1,83 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li id="current"><a href="globals.html"><span>All</span></a></li>
+    <li><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html#index__"><span>_</span></a></li>
+    <li><a href="globals_0x61.html#index_a"><span>a</span></a></li>
+    <li id="current"><a href="globals_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="globals_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="globals_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="globals_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="globals_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="globals_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="globals_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="globals_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="globals_0x6b.html#index_k"><span>k</span></a></li>
+    <li><a href="globals_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="globals_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="globals_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="globals_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="globals_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="globals_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="globals_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="globals_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="globals_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="globals_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="globals_0x77.html#index_w"><span>w</span></a></li>
+  </ul>
+</div>
+
+<p>
+Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:
+<p>
+<h3><a class="anchor" name="index_b">- b -</a></h3><ul>
+<li>B_HOST
+: <a class="el" href="dwc__otg__cil_8h.html#02d6d4d9a0fdcc4fc8c5cf8e6c8577aa">dwc_otg_cil.h</a><li>B_PERIPHERAL
+: <a class="el" href="dwc__otg__cil_8h.html#622c3b95c9a587f518a787c05c50ffb7">dwc_otg_cil.h</a><li>BitStuffTime
+: <a class="el" href="dwc__otg__hcd__queue_8c.html#e740bef95f7929a07065b699f6f087a2">dwc_otg_hcd_queue.c</a><li>BS_ALIGN_VAL_HDR_LEN
+: <a class="el" href="dwc__otg__cfi_8h.html#5495ec473ea2d7c8f805567416c559f0">dwc_otg_cfi.h</a><li>BS_CONCAT_VAL_HDR_LEN
+: <a class="el" href="dwc__otg__cfi_8h.html#c89955571b72df025126a1047bc53a00">dwc_otg_cfi.h</a><li>BS_DMA_BUSY
+: <a class="el" href="dwc__otg__regs_8h.html#3110b1318d89fe11ee69f3ccbe219c4e">dwc_otg_regs.h</a><li>BS_DMA_DONE
+: <a class="el" href="dwc__otg__regs_8h.html#b20f6432003d81072ed8b7cd66d6305b">dwc_otg_regs.h</a><li>BS_HOST_BUSY
+: <a class="el" href="dwc__otg__regs_8h.html#e6e96a79797557986256d1a1ff104ca1">dwc_otg_regs.h</a><li>BS_HOST_READY
+: <a class="el" href="dwc__otg__regs_8h.html#c2cfc53da94087a90d21d3528b005bcf">dwc_otg_regs.h</a><li>BS_SG_VAL_DESC_LEN
+: <a class="el" href="dwc__otg__cfi_8h.html#2332c8839256e2bb1aa1e0e8a9185ce2">dwc_otg_cfi.h</a><li>buspower
+: <a class="el" href="dwc__otg__attr_8c.html#1d54646ee79d4ce4f4acd08d7d4448ce">dwc_otg_attr.c</a><li>buspower_show
+: <a class="el" href="dwc__otg__attr_8c.html#6979f4909cde868d800dba13ef95aa8c">dwc_otg_attr.c</a><li>buspower_store
+: <a class="el" href="dwc__otg__attr_8c.html#4514a396df18dae15f7f03f640f52ac7">dwc_otg_attr.c</a><li>bussuspend
+: <a class="el" href="dwc__otg__attr_8c.html#e3c6534cdd3e1b7e83bf48e745d44c64">dwc_otg_attr.c</a><li>bussuspend_show
+: <a class="el" href="dwc__otg__attr_8c.html#ae1f7e3a17c5a0bcc5a93096aeb902d2">dwc_otg_attr.c</a><li>bussuspend_store
+: <a class="el" href="dwc__otg__attr_8c.html#f218d7c4c611b97dfaa1e03ac2daa353">dwc_otg_attr.c</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_0x63.html b/drivers/usb/host/dwc_otg/doc/html/globals_0x63.html
new file mode 100644
index 000000000000..edb5575bd7db
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_0x63.html
@@ -0,0 +1,100 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li id="current"><a href="globals.html"><span>All</span></a></li>
+    <li><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html#index__"><span>_</span></a></li>
+    <li><a href="globals_0x61.html#index_a"><span>a</span></a></li>
+    <li><a href="globals_0x62.html#index_b"><span>b</span></a></li>
+    <li id="current"><a href="globals_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="globals_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="globals_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="globals_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="globals_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="globals_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="globals_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="globals_0x6b.html#index_k"><span>k</span></a></li>
+    <li><a href="globals_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="globals_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="globals_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="globals_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="globals_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="globals_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="globals_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="globals_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="globals_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="globals_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="globals_0x77.html#index_w"><span>w</span></a></li>
+  </ul>
+</div>
+
+<p>
+Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:
+<p>
+<h3><a class="anchor" name="index_c">- c -</a></h3><ul>
+<li>calc_bus_time()
+: <a class="el" href="dwc__otg__hcd__queue_8c.html#49a9d4aa15e01fc07d68826bd05c0f4d">dwc_otg_hcd_queue.c</a><li>calc_num_in_eps()
+: <a class="el" href="dwc__otg__cil_8c.html#1cdde3ab3e53e93c5a42feed628aaf7d">dwc_otg_cil.c</a><li>calc_num_out_eps()
+: <a class="el" href="dwc__otg__cil_8c.html#e923d8ecfaf2957ef7d0a1379e0b5101">dwc_otg_cil.c</a><li>calc_starting_frame()
+: <a class="el" href="dwc__otg__hcd__ddma_8c.html#f9c8d06c646b374cf34925e659142709">dwc_otg_hcd_ddma.c</a><li>CFI_ALL_FEATURES_HDR_LEN
+: <a class="el" href="dwc__cfi__common_8h.html#b6c1d0a310ae1d0a89437b2cf92e57ba">dwc_cfi_common.h</a><li>cfi_all_features_header_t
+: <a class="el" href="dwc__cfi__common_8h.html#23298b60a6c427f08efe303c0bb332f8">dwc_cfi_common.h</a><li>CFI_CORE_ID_OTG
+: <a class="el" href="dwc__cfi__common_8h.html#4b0c4a003085148bef609d81fa3c1589">dwc_cfi_common.h</a><li>CFI_CORE_ID_UDC
+: <a class="el" href="dwc__cfi__common_8h.html#227fde38cd429d2ecaf3cd5bdd5d67d9">dwc_cfi_common.h</a><li>CFI_CORE_ID_WUDEV
+: <a class="el" href="dwc__cfi__common_8h.html#b885f7a00a119d048803beaf41a5dc30">dwc_cfi_common.h</a><li>cfi_ep_t
+: <a class="el" href="dwc__otg__cfi_8h.html#1c70b0d73323d138d4aac971e9998908">dwc_otg_cfi.h</a><li>CFI_FEATURE_ATTR_RO
+: <a class="el" href="dwc__cfi__common_8h.html#45ffc2183d956983ca297033f9e527af">dwc_cfi_common.h</a><li>CFI_FEATURE_ATTR_RW
+: <a class="el" href="dwc__cfi__common_8h.html#a4536fb9c1314c2f90a93cfcd082dbb9">dwc_cfi_common.h</a><li>CFI_FEATURE_DESC_HDR_LEN
+: <a class="el" href="dwc__cfi__common_8h.html#7ec5e43b7d52a39b553fdfa8fb17d889">dwc_cfi_common.h</a><li>cfi_feature_desc_header_t
+: <a class="el" href="dwc__cfi__common_8h.html#04466a29673dc59d190905db0db48266">dwc_cfi_common.h</a><li>CFI_IN_BUF_LEN
+: <a class="el" href="dwc__otg__cfi_8h.html#34582b9ef366f4c0e8ea24aa2388e829">dwc_otg_cfi.h</a><li>CFI_INFO
+: <a class="el" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">dwc_otg_cfi.h</a><li>CFI_INFO_DEF
+: <a class="el" href="dwc__otg__cfi_8h.html#7f62f8d1e9825c09b1f7d2badbe2527a">dwc_otg_cfi.h</a><li>cfi_ops_t
+: <a class="el" href="dwc__otg__cfi_8h.html#226b99dcff1992adefa086b6c7773eff">dwc_otg_cfi.h</a><li>CFI_OUT_BUF_LEN
+: <a class="el" href="dwc__otg__cfi_8h.html#739556affb10ce8a44b362b8ffa41a40">dwc_otg_cfi.h</a><li>cfi_setup_cb_t
+: <a class="el" href="dwc__otg__pcd__if_8h.html#7d75df2095c14a2d985df8027359e440">dwc_otg_pcd_if.h</a><li>cfi_string_t
+: <a class="el" href="dwc__cfi__common_8h.html#16bf31056d146243d486600ccbe8da85">dwc_cfi_common.h</a><li>cfiobject_t
+: <a class="el" href="dwc__otg__cfi_8h.html#4a1790f6f20555dd7cb9c8ae91c568a6">dwc_otg_cfi.h</a><li>cfiw_ep_alloc_buffer()
+: <a class="el" href="dwc__otg__pcd__if_8h.html#3951259aaef3df35d1955076a907f095">dwc_otg_pcd_if.h</a>, <a class="el" href="dwc__otg__pcd_8c.html#3951259aaef3df35d1955076a907f095">dwc_otg_pcd.c</a><li>check_max_xfer_size()
+: <a class="el" href="dwc__otg__hcd__queue_8c.html#4d3ef86a879b015bea87b02118aae4c9">dwc_otg_hcd_queue.c</a><li>check_periodic_bandwidth()
+: <a class="el" href="dwc__otg__hcd__queue_8c.html#fee6145ab0fe7782c587916160dedb11">dwc_otg_hcd_queue.c</a><li>CHK_DEBUG_LEVEL
+: <a class="el" href="dwc__otg__dbg_8h.html#7a96217c88a4d786f6cb3d4df09dee04">dwc_otg_dbg.h</a><li>clear_hc_int
+: <a class="el" href="dwc__otg__cil_8h.html#071cb1f3f29f9a52775e9fff270b1c7c">dwc_otg_cil.h</a><li>complete_ep()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#c77f277130ba55b19100bde598da7d85">dwc_otg_pcd_intr.c</a><li>complete_iso_ep()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#05965765a43225780ae08f2c3928f782">dwc_otg_pcd_intr.c</a><li>complete_isoc_xfer_ddma()
+: <a class="el" href="dwc__otg__hcd__ddma_8c.html#aad342d0a6056bbc5645809f24ac8507">dwc_otg_hcd_ddma.c</a><li>complete_non_isoc_xfer_ddma()
+: <a class="el" href="dwc__otg__hcd__ddma_8c.html#3551cf23294204324754fca2da9a99d1">dwc_otg_hcd_ddma.c</a><li>complete_non_periodic_xfer()
+: <a class="el" href="dwc__otg__hcd__intr_8c.html#2fa47944efef508dddcab00b0050ef0a">dwc_otg_hcd_intr.c</a><li>complete_periodic_xfer()
+: <a class="el" href="dwc__otg__hcd__intr_8c.html#a0fa0d4fa5f0af15860d685bb8fe3e50">dwc_otg_hcd_intr.c</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_0x64.html b/drivers/usb/host/dwc_otg/doc/html/globals_0x64.html
new file mode 100644
index 000000000000..6c33b3da5ecd
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_0x64.html
@@ -0,0 +1,686 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li id="current"><a href="globals.html"><span>All</span></a></li>
+    <li><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html#index__"><span>_</span></a></li>
+    <li><a href="globals_0x61.html#index_a"><span>a</span></a></li>
+    <li><a href="globals_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="globals_0x63.html#index_c"><span>c</span></a></li>
+    <li id="current"><a href="globals_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="globals_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="globals_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="globals_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="globals_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="globals_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="globals_0x6b.html#index_k"><span>k</span></a></li>
+    <li><a href="globals_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="globals_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="globals_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="globals_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="globals_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="globals_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="globals_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="globals_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="globals_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="globals_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="globals_0x77.html#index_w"><span>w</span></a></li>
+  </ul>
+</div>
+
+<p>
+Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:
+<p>
+<h3><a class="anchor" name="index_d">- d -</a></h3><ul>
+<li>daint_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#1effb8b11c6a62aacfcbea74c1be84f6">dwc_otg_regs.h</a><li>DBG_ANY
+: <a class="el" href="dwc__otg__dbg_8h.html#2bf62a567355d1ea38814714bd7b57ec">dwc_otg_dbg.h</a><li>DBG_CIL
+: <a class="el" href="dwc__otg__dbg_8h.html#57840e6b35e0e469296fd2db46227b13">dwc_otg_dbg.h</a><li>DBG_CILV
+: <a class="el" href="dwc__otg__dbg_8h.html#daab8e158c0c530486656ef52e5b0bbe">dwc_otg_dbg.h</a><li>DBG_HCD
+: <a class="el" href="dwc__otg__dbg_8h.html#e4a050e176c1c4f556da2b276a8c2b37">dwc_otg_dbg.h</a><li>DBG_HCD_URB
+: <a class="el" href="dwc__otg__dbg_8h.html#737e22e02729647d12db8e3059ad06c9">dwc_otg_dbg.h</a><li>DBG_HCDV
+: <a class="el" href="dwc__otg__dbg_8h.html#39931d908ba215b3d5d590e42d8408b5">dwc_otg_dbg.h</a><li>dbg_level_show()
+: <a class="el" href="dwc__otg__driver_8c.html#1e2b7516063b70cc1eaecc8d286b0689">dwc_otg_driver.c</a><li>dbg_level_store()
+: <a class="el" href="dwc__otg__driver_8c.html#e886456741506f66ce4adc5b843dc055">dwc_otg_driver.c</a><li>DBG_OFF
+: <a class="el" href="dwc__otg__dbg_8h.html#7d413cde1d2543d2c3447e890868f800">dwc_otg_dbg.h</a><li>DBG_PCD
+: <a class="el" href="dwc__otg__dbg_8h.html#b39e7fe4805812e8f65962134b45f48a">dwc_otg_dbg.h</a><li>DBG_PCDV
+: <a class="el" href="dwc__otg__dbg_8h.html#fe60e047aac272899de8f63b43df80e7">dwc_otg_dbg.h</a><li>dcfg_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#077228cd7e2acbd1e246bd9b0379c524">dwc_otg_regs.h</a><li>dctl_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#043805708857633a05ae076cf8c0a143">dwc_otg_regs.h</a><li>ddma_align_buffer_setup_t
+: <a class="el" href="dwc__otg__cfi_8h.html#f60b107e43f0edf8ac94f781803c8780">dwc_otg_cfi.h</a><li>ddma_concat_buffer_setup_hdr_t
+: <a class="el" href="dwc__otg__cfi_8h.html#a6fccd9def2a83408bdb10eb7964a4d6">dwc_otg_cfi.h</a><li>ddma_concat_buffer_setup_t
+: <a class="el" href="dwc__otg__cfi_8h.html#083bc35d34ae5489588bb581fc45ae73">dwc_otg_cfi.h</a><li>DDMA_MAX_TRANSFER_SIZE
+: <a class="el" href="dwc__otg__pcd_8h.html#6dad4d4462e9819753acfc601889faec">dwc_otg_pcd.h</a><li>ddma_sg_buffer_setup_t
+: <a class="el" href="dwc__otg__cfi_8h.html#1040b884c9adf08c1106ffdf9f191ad4">dwc_otg_cfi.h</a><li>deactivate_qh()
+: <a class="el" href="dwc__otg__hcd__intr_8c.html#57e9a29ec2dc8cd8d119acade0ae4ff1">dwc_otg_hcd_intr.c</a><li>DEBUG_EP0
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#1d4105869a3a5ce989afa5124218de0a">dwc_otg_pcd_intr.c</a><li>del_timers()
+: <a class="el" href="dwc__otg__hcd_8c.html#939a9c8afc75cbe47625e392a7c66a1a">dwc_otg_hcd.c</a><li>del_xfer_timers()
+: <a class="el" href="dwc__otg__hcd_8c.html#17f7272e6a2fe4515b3160ad4694ea55">dwc_otg_hcd.c</a><li>depctl_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#1d8ef2c3a67226833c01502c66bbd7a3">dwc_otg_regs.h</a><li>deptsiz0_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#0c2941814d5219b96c19caac80d58a3e">dwc_otg_regs.h</a><li>deptsiz_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#cb6f36bd93d869b9e61de914c8e2d222">dwc_otg_regs.h</a><li>desc_list_alloc()
+: <a class="el" href="dwc__otg__hcd__ddma_8c.html#12375cf094e35d9be3b78da6cf621d01">dwc_otg_hcd_ddma.c</a><li>desc_list_free()
+: <a class="el" href="dwc__otg__hcd__ddma_8c.html#c062f46629017bdeeebaf90aa65f610b">dwc_otg_hcd_ddma.c</a><li>deschedule_periodic()
+: <a class="el" href="dwc__otg__hcd__queue_8c.html#97dd97603c01db8288a735910b3b24a7">dwc_otg_hcd_queue.c</a><li>desclist_idx_dec()
+: <a class="el" href="dwc__otg__hcd__ddma_8c.html#13186d2e949bb38420a7a19a4530a5ad">dwc_otg_hcd_ddma.c</a><li>desclist_idx_inc()
+: <a class="el" href="dwc__otg__hcd__ddma_8c.html#c4d25855998839163827c8062bd6fb8b">dwc_otg_hcd_ddma.c</a><li>DESCNUM_THRESHOLD
+: <a class="el" href="dwc__otg__hcd__ddma_8c.html#1f389f323086b2c2697f2ab56062ead6">dwc_otg_hcd_ddma.c</a><li>dev_dma_desc_sts_t
+: <a class="el" href="dwc__otg__regs_8h.html#5363ac57fa4401cb81be60414d9104fe">dwc_otg_regs.h</a><li>device_grxsts_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#89dcb8224836ceda40e3584b3db51411">dwc_otg_regs.h</a><li>diepint_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#0f4ab8ee4156c299665471b3a6f279ce">dwc_otg_regs.h</a><li>diepmsk_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#0a168a8839d24b08e39eebb131447531">dwc_otg_regs.h</a><li>disable_hc_int
+: <a class="el" href="dwc__otg__cil_8h.html#e530fa4a6ed31f67cad65969355651ef">dwc_otg_cil.h</a><li>DMA_DESC_STS_PKTERR
+: <a class="el" href="dwc__otg__regs_8h.html#175767634e612a1e3dff3207a787d402">dwc_otg_regs.h</a><li>do_clear_feature()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#2198ea3f0136465fa325a189d4ba5140">dwc_otg_pcd_intr.c</a><li>do_gadget_setup()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#6c417c7d86bc9540e13ca4faeaf3dfbf">dwc_otg_pcd_intr.c</a><li>do_get_status()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#f449add2b4e8de7ced10fd1bb4c5b748">dwc_otg_pcd_intr.c</a><li>do_set_address()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#f653efb69491b3e293cab4a33940ac3d">dwc_otg_pcd_intr.c</a><li>do_set_feature()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#3754b29956ab3a85851dea376e046db9">dwc_otg_pcd_intr.c</a><li>do_setup_in_status_phase()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#39d3face14e49b0f1ad5c978f87665fe">dwc_otg_pcd_intr.c</a><li>do_setup_out_status_phase()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#cce0022b7577cda90a2d2e78e1f8171b">dwc_otg_pcd_intr.c</a><li>do_test_mode()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#9d6d6e24faab6478aef9e2217c9b5ab9">dwc_otg_pcd_intr.c</a>, <a class="el" href="dwc__otg__pcd_8h.html#9d6d6e24faab6478aef9e2217c9b5ab9">dwc_otg_pcd.h</a><li>doepint_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#692b7898b190ff12cca460bd0711db3f">dwc_otg_regs.h</a><li>doepmsk_data_t
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+: <a class="el" href="dwc__otg__pcd__if_8h.html#44d7ec17e6e087e44dd7c372e01fcfb2">dwc_otg_pcd_if.h</a><li>dwc_sample_frrem
+: <a class="el" href="dwc__otg__hcd_8h.html#7bdda6719cefc42f2302c5c34084ba69">dwc_otg_hcd.h</a><li>dwc_setup_cb_t
+: <a class="el" href="dwc__otg__pcd__if_8h.html#a9145aeaa27da4fa1befb424f927fde7">dwc_otg_pcd_if.h</a><li>DWC_SLAVE_ONLY_ARCH
+: <a class="el" href="dwc__otg__regs_8h.html#b06d547ae50b58fd46847daa34578122">dwc_otg_regs.h</a><li>dwc_sleep_cb_t
+: <a class="el" href="dwc__otg__pcd__if_8h.html#fc48d3df458c446cc0ace0a7d7755c67">dwc_otg_pcd_if.h</a><li>DWC_SOF_INTR_MASK
+: <a class="el" href="dwc__otg__regs_8h.html#8cd1d59e0700e5b528deebdea7a7ac76">dwc_otg_regs.h</a><li>DWC_SPEED_PARAM_FULL
+: <a class="el" href="dwc__otg__core__if_8h.html#353c64bfe6bbc9da8406528ad8220166">dwc_otg_core_if.h</a><li>DWC_SPEED_PARAM_HIGH
+: <a class="el" href="dwc__otg__core__if_8h.html#43c6bf01342fe06704016619c8d35fa7">dwc_otg_core_if.h</a><li>DWC_STS_DATA_UPDT
+: <a class="el" href="dwc__otg__regs_8h.html#93cbb84c3631af89d282fb1b406594f5">dwc_otg_regs.h</a><li>DWC_STS_XFER_COMP
+: <a class="el" href="dwc__otg__regs_8h.html#53a6a9dd332c8a15f505cd0027fb4c86">dwc_otg_regs.h</a><li>dwc_suspend_cb_t
+: <a class="el" href="dwc__otg__pcd__if_8h.html#ddcaadb93595803ca5f2ffb74cd88619">dwc_otg_pcd_if.h</a><li>dwc_urb_to_endpoint()
+: <a class="el" href="dwc__otg__hcd__linux_8c.html#99c594c1e3af2fa78b09c914cb334611">dwc_otg_hcd_linux.c</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_0x65.html b/drivers/usb/host/dwc_otg/doc/html/globals_0x65.html
new file mode 100644
index 000000000000..b8ce265b58a2
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_0x65.html
@@ -0,0 +1,78 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li id="current"><a href="globals.html"><span>All</span></a></li>
+    <li><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html#index__"><span>_</span></a></li>
+    <li><a href="globals_0x61.html#index_a"><span>a</span></a></li>
+    <li><a href="globals_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="globals_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="globals_0x64.html#index_d"><span>d</span></a></li>
+    <li id="current"><a href="globals_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="globals_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="globals_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="globals_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="globals_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="globals_0x6b.html#index_k"><span>k</span></a></li>
+    <li><a href="globals_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="globals_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="globals_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="globals_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="globals_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="globals_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="globals_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="globals_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="globals_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="globals_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="globals_0x77.html#index_w"><span>w</span></a></li>
+  </ul>
+</div>
+
+<p>
+Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:
+<p>
+<h3><a class="anchor" name="index_e">- e -</a></h3><ul>
+<li>endpoint_disable()
+: <a class="el" href="dwc__otg__hcd__linux_8c.html#0aefc084c4c334dac85c95a43e8942c6">dwc_otg_hcd_linux.c</a><li>ep0_complete_request()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#f64bfae20151c51d3b0a6d4e523f356e">dwc_otg_pcd_intr.c</a><li>ep0_do_stall()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#325b13e198ff56e9de2600ac7f28a57d">dwc_otg_pcd_intr.c</a><li>ep0_out_start()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#726b57833bb3ae4648ce7e7a7e125bf7">dwc_otg_pcd_intr.c</a><li>ep0_state
+: <a class="el" href="dwc__otg__pcd_8h.html#f286abbd9be76db05fee7aebfeb61865">dwc_otg_pcd.h</a><li>ep0state_e
+: <a class="el" href="dwc__otg__pcd_8h.html#70fcb6a989e5871e16f4c1c96ffe394a">dwc_otg_pcd.h</a><li>ep_dequeue()
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#e2e4913a926acc55f4e57c3ff8f97c08">dwc_otg_pcd_linux.c</a><li>ep_disable()
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#1708514cb93c5da43a8f634de1c0f5e7">dwc_otg_pcd_linux.c</a><li>ep_enable()
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#9761890d7f741f9421d82254c9846f31">dwc_otg_pcd_linux.c</a><li>ep_halt()
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#8ee99e0e68c8e50e94c242805b158cb2">dwc_otg_pcd_linux.c</a><li>ep_queue()
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#f97bea831037135af73c3c202e3e01dc">dwc_otg_pcd_linux.c</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_0x66.html b/drivers/usb/host/dwc_otg/doc/html/globals_0x66.html
new file mode 100644
index 000000000000..51aa44b0fdf1
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_0x66.html
@@ -0,0 +1,87 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li id="current"><a href="globals.html"><span>All</span></a></li>
+    <li><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html#index__"><span>_</span></a></li>
+    <li><a href="globals_0x61.html#index_a"><span>a</span></a></li>
+    <li><a href="globals_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="globals_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="globals_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="globals_0x65.html#index_e"><span>e</span></a></li>
+    <li id="current"><a href="globals_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="globals_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="globals_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="globals_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="globals_0x6b.html#index_k"><span>k</span></a></li>
+    <li><a href="globals_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="globals_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="globals_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="globals_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="globals_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="globals_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="globals_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="globals_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="globals_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="globals_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="globals_0x77.html#index_w"><span>w</span></a></li>
+  </ul>
+</div>
+
+<p>
+Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:
+<p>
+<h3><a class="anchor" name="index_f">- f -</a></h3><ul>
+<li>fifosize_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#389bbcdb2f9b7b284631c4e3c6c05ca4">dwc_otg_regs.h</a><li>fops
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#9ce9b5e49c60906c189bee157dd68acd">dwc_otg_pcd_linux.c</a><li>frame_incr_val()
+: <a class="el" href="dwc__otg__hcd__ddma_8c.html#357d9fe0cd782a9c88e79f47c3b58384">dwc_otg_hcd_ddma.c</a><li>frame_list_alloc()
+: <a class="el" href="dwc__otg__hcd__ddma_8c.html#35be74597b6abe7a7d077c2c00d64dc2">dwc_otg_hcd_ddma.c</a><li>frame_list_free()
+: <a class="el" href="dwc__otg__hcd__ddma_8c.html#01991072b147e11d3b7350a2ee9ee920">dwc_otg_hcd_ddma.c</a><li>frame_list_idx()
+: <a class="el" href="dwc__otg__hcd__ddma_8c.html#cc7af33964cf891f1448376c2a57b309">dwc_otg_hcd_ddma.c</a><li>frame_to_desc_idx()
+: <a class="el" href="dwc__otg__hcd__ddma_8c.html#42ed718bf245372d90fa8f92fcb69a99">dwc_otg_hcd_ddma.c</a><li>free_bus_bandwidth()
+: <a class="el" href="dwc__otg__hcd__linux_8c.html#53fcd6fb7b833323112e8856070e88d8">dwc_otg_hcd_linux.c</a><li>free_iso_request()
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#a9a7bc869bc7f3d05804059f3277d11a">dwc_otg_pcd_linux.c</a><li>free_wrapper()
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#8893dc41eae659439546d874c6e9977f">dwc_otg_pcd_linux.c</a><li>FS_LS_HOST_DELAY
+: <a class="el" href="dwc__otg__hcd__queue_8c.html#8f9875d35aace115a340d2cef9c66294">dwc_otg_hcd_queue.c</a><li>FT_ID_DFIFO_DEPTH
+: <a class="el" href="dwc__otg__cfi_8h.html#54b879727edcb06acdd11968ec60d249">dwc_otg_cfi.h</a><li>FT_ID_DMA_BUFF_ALIGN
+: <a class="el" href="dwc__otg__cfi_8h.html#9335284cd4dae01f4bc0da7cb89d5ef4">dwc_otg_cfi.h</a><li>FT_ID_DMA_BUFFER_SETUP
+: <a class="el" href="dwc__otg__cfi_8h.html#98840b45640251bfafa3481260aef889">dwc_otg_cfi.h</a><li>FT_ID_DMA_CIRCULAR
+: <a class="el" href="dwc__otg__cfi_8h.html#8db5bfce321e02d42b742e9deedfa665">dwc_otg_cfi.h</a><li>FT_ID_DMA_CONCAT_SETUP
+: <a class="el" href="dwc__otg__cfi_8h.html#779a11db5843dd058581d93c8232bd7c">dwc_otg_cfi.h</a><li>FT_ID_DMA_MODE
+: <a class="el" href="dwc__otg__cfi_8h.html#0e196868939f6bbf0d157868bfc90208">dwc_otg_cfi.h</a><li>FT_ID_RX_FIFO_DEPTH
+: <a class="el" href="dwc__otg__cfi_8h.html#42b7c98c105de1f9399786a3419e7e20">dwc_otg_cfi.h</a><li>FT_ID_THRESHOLD_SETUP
+: <a class="el" href="dwc__otg__cfi_8h.html#bcc99a9e5a0b15b4212d88bd9c610647">dwc_otg_cfi.h</a><li>FT_ID_TX_FIFO_DEPTH
+: <a class="el" href="dwc__otg__cfi_8h.html#a3a67b679a59c5279370bbf69f114cb6">dwc_otg_cfi.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_0x67.html b/drivers/usb/host/dwc_otg/doc/html/globals_0x67.html
new file mode 100644
index 000000000000..3ecaaf776555
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_0x67.html
@@ -0,0 +1,93 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li id="current"><a href="globals.html"><span>All</span></a></li>
+    <li><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html#index__"><span>_</span></a></li>
+    <li><a href="globals_0x61.html#index_a"><span>a</span></a></li>
+    <li><a href="globals_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="globals_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="globals_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="globals_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="globals_0x66.html#index_f"><span>f</span></a></li>
+    <li id="current"><a href="globals_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="globals_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="globals_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="globals_0x6b.html#index_k"><span>k</span></a></li>
+    <li><a href="globals_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="globals_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="globals_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="globals_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="globals_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="globals_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="globals_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="globals_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="globals_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="globals_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="globals_0x77.html#index_w"><span>w</span></a></li>
+  </ul>
+</div>
+
+<p>
+Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:
+<p>
+<h3><a class="anchor" name="index_g">- g -</a></h3><ul>
+<li>g_dbg_lvl
+: <a class="el" href="dwc__otg__driver_8c.html#7ef4ada2ebb5f1aadf3be4d7fbf8ce62">dwc_otg_driver.c</a>, <a class="el" href="dwc__otg__dbg_8h.html#7ef4ada2ebb5f1aadf3be4d7fbf8ce62">dwc_otg_dbg.h</a><li>gadget_add_eps()
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#647f81bc0edc9007af3ff2ba04e884f3">dwc_otg_pcd_linux.c</a><li>gahbcfg_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#e1aca1c2d0abbb005545a17af3508291">dwc_otg_regs.h</a><li>get_a_alt_hnp_support()
+: <a class="el" href="dwc__otg__pcd__if_8h.html#842709a4980bc78d49726fa880922dda">dwc_otg_pcd_if.h</a>, <a class="el" href="dwc__otg__pcd_8c.html#842709a4980bc78d49726fa880922dda">dwc_otg_pcd.c</a><li>get_a_hnp_support()
+: <a class="el" href="dwc__otg__pcd__if_8h.html#69d0bb469e15cb46f00c17398f76df99">dwc_otg_pcd_if.h</a>, <a class="el" href="dwc__otg__pcd_8c.html#69d0bb469e15cb46f00c17398f76df99">dwc_otg_pcd.c</a><li>get_actual_xfer_length()
+: <a class="el" href="dwc__otg__hcd__intr_8c.html#6cdb134cbb3cdf3501ca39761137baf0">dwc_otg_hcd_intr.c</a><li>get_b_hnp_enable()
+: <a class="el" href="dwc__otg__pcd__if_8h.html#777a6a4e250add9ba5f5f5d63d854031">dwc_otg_pcd_if.h</a>, <a class="el" href="dwc__otg__pcd_8c.html#777a6a4e250add9ba5f5f5d63d854031">dwc_otg_pcd.c</a><li>get_cfi_ep_by_addr()
+: <a class="el" href="dwc__otg__cfi_8h.html#5ece1e51b8534a5cc9a7dd5115bb01ca">dwc_otg_cfi.h</a><li>get_cfi_ep_by_pcd_ep()
+: <a class="el" href="dwc__otg__cfi_8h.html#c21284d5adf03032d094a36babf9b1e5">dwc_otg_cfi.h</a><li>GET_CORE_IF
+: <a class="el" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">dwc_otg_pcd.h</a><li>get_device_speed()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#6a3ddac8955990b9a63646c40c65446b">dwc_otg_pcd_intr.c</a><li>get_ep_by_addr()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#3c351d7f51d6242296d6ea3bb1a9775c">dwc_otg_pcd_intr.c</a><li>get_ep_from_handle()
+: <a class="el" href="dwc__otg__pcd_8c.html#4b46c226fa34cd7fc4ceec2c5e7f8ebe">dwc_otg_pcd.c</a><li>get_ep_of_last_in_token()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#fde237571d3aaa5d03376d3bee827075">dwc_otg_pcd_intr.c</a><li>get_frame_number()
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#7af23be44d3ad24c67cd1e22579dd90e">dwc_otg_pcd_linux.c</a>, <a class="el" href="dwc__otg__hcd__linux_8c.html#c78128edb8902dc96534c5bb253f99a3">dwc_otg_hcd_linux.c</a><li>get_in_ep()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#cc3f2f1ae0ab7d33903a1d0d9097c04e">dwc_otg_pcd_intr.c</a><li>get_out_ep()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#fbd54e53e1968d3b4798ea1b63b52f74">dwc_otg_pcd_intr.c</a><li>gi2cctl_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#de10c5861b75d2f22b1a1b9e817a3098">dwc_otg_regs.h</a><li>gintmsk_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#db54cb8baf5c7d970347192ad40662d3">dwc_otg_regs.h</a><li>gintsts_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#211ef100682c75981568527ed748dcfc">dwc_otg_regs.h</a><li>glpmcfg_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#ba73e60dacc956a6090a82188bb8fcfa">dwc_otg_regs.h</a><li>gnptxsts_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#e00daff072291dd6e7af34701aad3138">dwc_otg_regs.h</a><li>gotgctl_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#6a10de8c32943876bfc55ed308d3ff83">dwc_otg_regs.h</a><li>gotgint_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#9f95118956319102de69927308a2defd">dwc_otg_regs.h</a><li>grstctl_t
+: <a class="el" href="dwc__otg__regs_8h.html#ca690ce842cde2518004eefeedda7788">dwc_otg_regs.h</a><li>gusbcfg_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#176748792c6f7aedc1aacf6740c2b1dd">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_0x68.html b/drivers/usb/host/dwc_otg/doc/html/globals_0x68.html
new file mode 100644
index 000000000000..0790daa0ae99
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_0x68.html
@@ -0,0 +1,129 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li id="current"><a href="globals.html"><span>All</span></a></li>
+    <li><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html#index__"><span>_</span></a></li>
+    <li><a href="globals_0x61.html#index_a"><span>a</span></a></li>
+    <li><a href="globals_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="globals_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="globals_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="globals_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="globals_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="globals_0x67.html#index_g"><span>g</span></a></li>
+    <li id="current"><a href="globals_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="globals_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="globals_0x6b.html#index_k"><span>k</span></a></li>
+    <li><a href="globals_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="globals_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="globals_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="globals_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="globals_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="globals_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="globals_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="globals_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="globals_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="globals_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="globals_0x77.html#index_w"><span>w</span></a></li>
+  </ul>
+</div>
+
+<p>
+Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:
+<p>
+<h3><a class="anchor" name="index_h">- h -</a></h3><ul>
+<li>haint_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#27de5d0beb5957eb126766a01fec40b2">dwc_otg_regs.h</a><li>haintmsk_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#f8363fbf7d3be043235c0bf6b057a637">dwc_otg_regs.h</a><li>halt_channel()
+: <a class="el" href="dwc__otg__hcd__intr_8c.html#8b774e79e18861e9ad3ab1d0de00d47c">dwc_otg_hcd_intr.c</a><li>handle_ep0()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#4991119b51de03163a3677c36bc0ee3b">dwc_otg_pcd_intr.c</a><li>handle_hc_ack_intr()
+: <a class="el" href="dwc__otg__hcd__intr_8c.html#243b0fb4191e46127a6823c0b5e970bb">dwc_otg_hcd_intr.c</a><li>handle_hc_ahberr_intr()
+: <a class="el" href="dwc__otg__hcd__intr_8c.html#1edf7eebc0475898518e18dc12c1b4b9">dwc_otg_hcd_intr.c</a><li>handle_hc_babble_intr()
+: <a class="el" href="dwc__otg__hcd__intr_8c.html#ab5348f52aac4081a9c35d529c1fcd79">dwc_otg_hcd_intr.c</a><li>handle_hc_chhltd_intr()
+: <a class="el" href="dwc__otg__hcd__intr_8c.html#83541cd20d3297d7d7d24052834ef019">dwc_otg_hcd_intr.c</a><li>handle_hc_chhltd_intr_dma()
+: <a class="el" href="dwc__otg__hcd__intr_8c.html#d75ed153a90dbda39d4d8e6cde4358df">dwc_otg_hcd_intr.c</a><li>handle_hc_datatglerr_intr()
+: <a class="el" href="dwc__otg__hcd__intr_8c.html#f73e70f0e622267b6281e0cd6c1d89cf">dwc_otg_hcd_intr.c</a><li>handle_hc_frmovrun_intr()
+: <a class="el" href="dwc__otg__hcd__intr_8c.html#a30d61b2809dccf609bcf83cc61c9d63">dwc_otg_hcd_intr.c</a><li>handle_hc_nak_intr()
+: <a class="el" href="dwc__otg__hcd__intr_8c.html#19f718e1e8f7cded3bb7431008ee0309">dwc_otg_hcd_intr.c</a><li>handle_hc_nyet_intr()
+: <a class="el" href="dwc__otg__hcd__intr_8c.html#5093a2b94c1d5cd1988eb93d9def298f">dwc_otg_hcd_intr.c</a><li>handle_hc_stall_intr()
+: <a class="el" href="dwc__otg__hcd__intr_8c.html#e89fabf3023fa4f0279f312e5e9d4223">dwc_otg_hcd_intr.c</a><li>handle_hc_xacterr_intr()
+: <a class="el" href="dwc__otg__hcd__intr_8c.html#464af1671bd416d5db48a51fc93366ee">dwc_otg_hcd_intr.c</a><li>handle_hc_xfercomp_intr()
+: <a class="el" href="dwc__otg__hcd__intr_8c.html#e8bfcabff910322ef19eec9fc99fd097">dwc_otg_hcd_intr.c</a><li>handle_in_ep_disable_intr()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#6c9df42abc5cb6f676a44918207c91b7">dwc_otg_pcd_intr.c</a><li>handle_in_ep_nak_intr()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#273ccc8e8cdb9e2075844f2f922b53bf">dwc_otg_pcd_intr.c</a><li>handle_in_ep_timeout_intr()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#65d4f747d13e368916ee0e16d202119b">dwc_otg_pcd_intr.c</a><li>handle_iso_out_pkt_dropped()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#41cfc0d590740640795b350998bcc2c4">dwc_otg_pcd_intr.c</a><li>handle_out_ep_babble_intr()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#42aef7ea134cccf7cdb53e7e1428bc4a">dwc_otg_pcd_intr.c</a><li>handle_out_ep_nak_intr()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#252929e585c84eaf0485869cd7734244">dwc_otg_pcd_intr.c</a><li>handle_out_ep_nyet_intr()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#926d9068c1950cc406d50828e72a31db">dwc_otg_pcd_intr.c</a><li>handle_xfercomp_isoc_split_in()
+: <a class="el" href="dwc__otg__hcd__intr_8c.html#a56eb0602c101ab380581b164973fb33">dwc_otg_hcd_intr.c</a><li>hc_set_even_odd_frame()
+: <a class="el" href="dwc__otg__cil_8c.html#b2669551136671d3e4b6ad56bd947222">dwc_otg_cil.c</a><li>hcchar_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#e3bd36607e63cd3181c877f329a6eff8">dwc_otg_regs.h</a><li>hcd_cil_callbacks
+: <a class="el" href="dwc__otg__hcd_8c.html#106ff6cbb1499325ea75f2d97abb8e6a">dwc_otg_hcd.c</a><li>hcd_disconnect()
+: <a class="el" href="dwc__otg__cil__intr_8c.html#b208bc4537e7b26658edc642e407894b">dwc_otg_cil_intr.c</a><li>hcd_fops
+: <a class="el" href="dwc__otg__hcd__linux_8c.html#430ee3db85940ea34a1702a37fbfb942">dwc_otg_hcd_linux.c</a><li>hcd_frrem
+: <a class="el" href="dwc__otg__attr_8c.html#98c5b16a6162e4c9057aee72a7216efb">dwc_otg_attr.c</a><li>hcd_frrem_show
+: <a class="el" href="dwc__otg__attr_8c.html#d1d9d9abd2011c79fe7453c20e03e31a">dwc_otg_attr.c</a><li>hcd_init()
+: <a class="el" href="dwc__otg__hcd__linux_8c.html#ab12cdf65bf4ed68545a6c17cc31269f">dwc_otg_hcd_linux.c</a>, <a class="el" href="dwc__otg__driver_8c.html#ab12cdf65bf4ed68545a6c17cc31269f">dwc_otg_driver.c</a><li>hcd_remove()
+: <a class="el" href="dwc__otg__hcd__linux_8c.html#f36193b3ff33c0473956c8a15eee4f5b">dwc_otg_hcd_linux.c</a>, <a class="el" href="dwc__otg__driver_8c.html#f36193b3ff33c0473956c8a15eee4f5b">dwc_otg_driver.c</a><li>hcd_resume()
+: <a class="el" href="dwc__otg__cil__intr_8c.html#681e193a107c04b5005500ff35c59cd5">dwc_otg_cil_intr.c</a><li>hcd_session_start()
+: <a class="el" href="dwc__otg__cil__intr_8c.html#2ccec1f0c44ae8129f3012a519ecd5eb">dwc_otg_cil_intr.c</a><li>hcd_start()
+: <a class="el" href="dwc__otg__hcd__linux_8c.html#5d7f9da64cfeb32895d6c3d1366d45cf">dwc_otg_hcd_linux.c</a>, <a class="el" href="dwc__otg__cil__intr_8c.html#fc2d933cd662b3d060747004c79203a1">dwc_otg_cil_intr.c</a><li>hcd_start_func()
+: <a class="el" href="dwc__otg__hcd_8c.html#5a7a5af3b84b4af188fa3b60058a039c">dwc_otg_hcd.c</a><li>hcd_stop()
+: <a class="el" href="dwc__otg__hcd__linux_8c.html#cbb6a9e932a0baf80d1fdb013ac5d679">dwc_otg_hcd_linux.c</a>, <a class="el" href="dwc__otg__cil__intr_8c.html#b2721d01cc389181470095955b4e0994">dwc_otg_cil_intr.c</a><li>hcd_to_dwc_otg_hcd()
+: <a class="el" href="dwc__otg__hcd__linux_8c.html#bd8c86466ccd8ff8b94867d601e66116">dwc_otg_hcd_linux.c</a><li>hcddump
+: <a class="el" href="dwc__otg__attr_8c.html#eb95151b5afaea479812773b61c402b4">dwc_otg_attr.c</a><li>hcddump_show
+: <a class="el" href="dwc__otg__attr_8c.html#e16d4439b6b733715ecc1d06ed999aa4">dwc_otg_attr.c</a><li>hcdma_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#018c0b4c795e3d3c373348fd4dafecb4">dwc_otg_regs.h</a><li>hcfg_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#26f6beffdddc3cbe5f7ec4f77824cca0">dwc_otg_regs.h</a><li>hcint_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#c765ad9a2d3eff579f45362a2dcf39e3">dwc_otg_regs.h</a><li>hcintmsk_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#eeffbd23c7de44b01363bf196b4a6a44">dwc_otg_regs.h</a><li>hctsiz_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#2f3d030c12693e0cf5876517856766b4">dwc_otg_regs.h</a><li>hfir_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#ff5539ea6d98c6725480b533c13dc652">dwc_otg_regs.h</a><li>hfnum_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#f5c22a704229989ff3435059ebe9fb10">dwc_otg_regs.h</a><li>hnp
+: <a class="el" href="dwc__otg__attr_8c.html#2d1cf91c8e20bcdd4f552c410b0aa6ba">dwc_otg_attr.c</a><li>hnp_show
+: <a class="el" href="dwc__otg__attr_8c.html#5ed0f5e2094b1db679075adf2f81e10a">dwc_otg_attr.c</a><li>hnp_store
+: <a class="el" href="dwc__otg__attr_8c.html#14b1910d541301f5456e2a15a3b4f0b0">dwc_otg_attr.c</a><li>host_dma_desc_sts_t
+: <a class="el" href="dwc__otg__regs_8h.html#fbefbebde0abe3db88477ab0831d865a">dwc_otg_regs.h</a><li>host_grxsts_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#1d5d223eb9bab051464aca64efd707e1">dwc_otg_regs.h</a><li>hprt0_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#b6962581d4be622894de1b523256f4f9">dwc_otg_regs.h</a><li>HS_HOST_DELAY
+: <a class="el" href="dwc__otg__hcd__queue_8c.html#2a974c684e456c20cc2d9bceb2e71a11">dwc_otg_hcd_queue.c</a><li>hub_control()
+: <a class="el" href="dwc__otg__hcd__linux_8c.html#55d196cab99083dabdacdee78dc5e339">dwc_otg_hcd_linux.c</a><li>HUB_LS_SETUP
+: <a class="el" href="dwc__otg__hcd__queue_8c.html#d596163a6f24db7fb4ee092a933e03a2">dwc_otg_hcd_queue.c</a><li>hub_status_data()
+: <a class="el" href="dwc__otg__hcd__linux_8c.html#108442f4aa4dc4663d8659241ed04e9c">dwc_otg_hcd_linux.c</a><li>hwcfg1_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#e3fd2e458471dcd8fec9fa09ff787ad5">dwc_otg_regs.h</a><li>hwcfg2_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#a3044f8c36a47affba16a8abcebc2a33">dwc_otg_regs.h</a><li>hwcfg3_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#cec01b13bc8d56e9001801bb14a98857">dwc_otg_regs.h</a><li>hwcfg4_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#d9159ac522a8a34be480e616a9df7ebe">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_0x69.html b/drivers/usb/host/dwc_otg/doc/html/globals_0x69.html
new file mode 100644
index 000000000000..d9269ca0ed76
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_0x69.html
@@ -0,0 +1,76 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li id="current"><a href="globals.html"><span>All</span></a></li>
+    <li><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html#index__"><span>_</span></a></li>
+    <li><a href="globals_0x61.html#index_a"><span>a</span></a></li>
+    <li><a href="globals_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="globals_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="globals_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="globals_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="globals_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="globals_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="globals_0x68.html#index_h"><span>h</span></a></li>
+    <li id="current"><a href="globals_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="globals_0x6b.html#index_k"><span>k</span></a></li>
+    <li><a href="globals_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="globals_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="globals_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="globals_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="globals_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="globals_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="globals_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="globals_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="globals_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="globals_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="globals_0x77.html#index_w"><span>w</span></a></li>
+  </ul>
+</div>
+
+<p>
+Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:
+<p>
+<h3><a class="anchor" name="index_i">- i -</a></h3><ul>
+<li>init_devspd()
+: <a class="el" href="dwc__otg__cil_8c.html#6ef971c486eacd419d20e1bc545f9238">dwc_otg_cil.c</a><li>init_dma_desc_chain()
+: <a class="el" href="dwc__otg__cil_8c.html#50a39773d3477ca76a71787e27400d7a">dwc_otg_cil.c</a><li>init_fslspclksel()
+: <a class="el" href="dwc__otg__cil_8c.html#4550564b18dcd56bd2c4ec1ba91c6e13">dwc_otg_cil.c</a><li>init_isoc_dma_desc()
+: <a class="el" href="dwc__otg__hcd__ddma_8c.html#f2bad2e76275e230f83be94c21a0bd75">dwc_otg_hcd_ddma.c</a><li>init_non_isoc_dma_desc()
+: <a class="el" href="dwc__otg__hcd__ddma_8c.html#f3630ce7f8926de36873d78a1748134f">dwc_otg_hcd_ddma.c</a><li>iso_ep_start()
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#eb3df484c8c344613a2a9b23e24036a8">dwc_otg_pcd_linux.c</a><li>iso_ep_stop()
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#cecdcaa060d30ac09414419545a5d1c6">dwc_otg_pcd_linux.c</a><li>iso_pkt_info_t
+: <a class="el" href="dwc__otg__cil_8h.html#ef7ad72528599bd12fe954ce1899576e">dwc_otg_cil.h</a><li>ISOC_URB_GIVEBACK_ASAP
+: <a class="el" href="dwc__otg__hcd__ddma_8c.html#7aed1ace42f0421b376041d8831c9a74">dwc_otg_hcd_ddma.c</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_0x6b.html b/drivers/usb/host/dwc_otg/doc/html/globals_0x6b.html
new file mode 100644
index 000000000000..d75fa77030af
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_0x6b.html
@@ -0,0 +1,69 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li id="current"><a href="globals.html"><span>All</span></a></li>
+    <li><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html#index__"><span>_</span></a></li>
+    <li><a href="globals_0x61.html#index_a"><span>a</span></a></li>
+    <li><a href="globals_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="globals_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="globals_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="globals_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="globals_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="globals_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="globals_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="globals_0x69.html#index_i"><span>i</span></a></li>
+    <li id="current"><a href="globals_0x6b.html#index_k"><span>k</span></a></li>
+    <li><a href="globals_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="globals_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="globals_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="globals_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="globals_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="globals_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="globals_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="globals_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="globals_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="globals_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="globals_0x77.html#index_w"><span>w</span></a></li>
+  </ul>
+</div>
+
+<p>
+Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:
+<p>
+<h3><a class="anchor" name="index_k">- k -</a></h3><ul>
+<li>kill_all_urbs()
+: <a class="el" href="dwc__otg__hcd_8c.html#63f169b583c3818268def3614ac2fe0a">dwc_otg_hcd.c</a><li>kill_urbs_in_qh_list()
+: <a class="el" href="dwc__otg__hcd_8c.html#8fd9263ed86449c5440edd834cb4d766">dwc_otg_hcd.c</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_0x6d.html b/drivers/usb/host/dwc_otg/doc/html/globals_0x6d.html
new file mode 100644
index 000000000000..22cffaca45c1
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_0x6d.html
@@ -0,0 +1,84 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li id="current"><a href="globals.html"><span>All</span></a></li>
+    <li><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html#index__"><span>_</span></a></li>
+    <li><a href="globals_0x61.html#index_a"><span>a</span></a></li>
+    <li><a href="globals_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="globals_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="globals_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="globals_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="globals_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="globals_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="globals_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="globals_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="globals_0x6b.html#index_k"><span>k</span></a></li>
+    <li id="current"><a href="globals_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="globals_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="globals_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="globals_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="globals_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="globals_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="globals_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="globals_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="globals_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="globals_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="globals_0x77.html#index_w"><span>w</span></a></li>
+  </ul>
+</div>
+
+<p>
+Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:
+<p>
+<h3><a class="anchor" name="index_m">- m -</a></h3><ul>
+<li>max
+: <a class="el" href="dwc__otg__cfi_8h.html#4755d18ce5205f644e5cd02db7f4ada5">dwc_otg_cfi.h</a><li>max_desc_num()
+: <a class="el" href="dwc__otg__hcd__ddma_8c.html#b7563972b1dd332dde72911900756d92">dwc_otg_hcd_ddma.c</a><li>MAX_DMA_DESC_CNT
+: <a class="el" href="dwc__otg__pcd_8h.html#a1c5dc8973b5c039fd77b1e250ce29e2">dwc_otg_pcd.h</a><li>MAX_DMA_DESC_NUM_GENERIC
+: <a class="el" href="dwc__otg__regs_8h.html#7f241a3ed7bd5c0d4f1a496c77cbc225">dwc_otg_regs.h</a><li>MAX_DMA_DESC_NUM_HS_ISOC
+: <a class="el" href="dwc__otg__regs_8h.html#b190810b3017403bd58b6346aad4e4ed">dwc_otg_regs.h</a><li>MAX_DMA_DESC_SIZE
+: <a class="el" href="dwc__otg__regs_8h.html#000f3273fb3033d587107e7eff3c1ff6">dwc_otg_regs.h</a><li>MAX_EP0_SIZE
+: <a class="el" href="dwc__otg__pcd__if_8h.html#8fbbba66f80923843e99def6064a570f">dwc_otg_pcd_if.h</a><li>MAX_EPS_CHANNELS
+: <a class="el" href="dwc__otg__core__if_8h.html#bfb88b45545f7685f668ac2f545674ec">dwc_otg_core_if.h</a><li>MAX_FRLIST_EN_NUM
+: <a class="el" href="dwc__otg__regs_8h.html#ff2c2ac58a30e050d647d0f9a256d0bd">dwc_otg_regs.h</a><li>MAX_ISOC_XFER_SIZE_FS
+: <a class="el" href="dwc__otg__hcd__ddma_8c.html#cf56bce31ec5dfcc2a36047c0c648784">dwc_otg_hcd_ddma.c</a><li>MAX_ISOC_XFER_SIZE_HS
+: <a class="el" href="dwc__otg__hcd__ddma_8c.html#06012eeeca2d17ee7ea304b381928c4a">dwc_otg_hcd_ddma.c</a><li>MAX_PACKET_SIZE
+: <a class="el" href="dwc__otg__pcd__if_8h.html#cf2c48a3393f5ae43e8d88d01c2d204a">dwc_otg_pcd_if.h</a><li>MAX_PERIO_FIFOS
+: <a class="el" href="dwc__otg__core__if_8h.html#13bb22067644d357537c2905fe5ffb8c">dwc_otg_core_if.h</a><li>MAX_TX_FIFOS
+: <a class="el" href="dwc__otg__core__if_8h.html#050db6129005b993e573311dc42bc1a8">dwc_otg_core_if.h</a><li>min
+: <a class="el" href="dwc__otg__cfi_8h.html#7c9949b9e692a8360832aedfa1843657">dwc_otg_cfi.h</a><li>MODULE_PARM_DESC()
+: <a class="el" href="dwc__otg__driver_8c.html#e0dbd8f1a438746fa8ec7798ceb2bd50">dwc_otg_driver.c</a><li>MSEC_PER_JIFFIE
+: <a class="el" href="dwc__otg__attr_8c.html#4e04f10b5ae5b78f1bc8b3c2e8af8f92">dwc_otg_attr.c</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_0x6e.html b/drivers/usb/host/dwc_otg/doc/html/globals_0x6e.html
new file mode 100644
index 000000000000..c77753fed0f2
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_0x6e.html
@@ -0,0 +1,68 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li id="current"><a href="globals.html"><span>All</span></a></li>
+    <li><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html#index__"><span>_</span></a></li>
+    <li><a href="globals_0x61.html#index_a"><span>a</span></a></li>
+    <li><a href="globals_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="globals_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="globals_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="globals_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="globals_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="globals_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="globals_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="globals_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="globals_0x6b.html#index_k"><span>k</span></a></li>
+    <li><a href="globals_0x6d.html#index_m"><span>m</span></a></li>
+    <li id="current"><a href="globals_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="globals_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="globals_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="globals_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="globals_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="globals_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="globals_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="globals_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="globals_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="globals_0x77.html#index_w"><span>w</span></a></li>
+  </ul>
+</div>
+
+<p>
+Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:
+<p>
+<h3><a class="anchor" name="index_n">- n -</a></h3><ul>
+<li>NS_TO_US
+: <a class="el" href="dwc__otg__hcd__queue_8c.html#1df143acbaa5817cd09c8cca89851747">dwc_otg_hcd_queue.c</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_0x6f.html b/drivers/usb/host/dwc_otg/doc/html/globals_0x6f.html
new file mode 100644
index 000000000000..e0d373bcc3f8
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_0x6f.html
@@ -0,0 +1,73 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li id="current"><a href="globals.html"><span>All</span></a></li>
+    <li><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html#index__"><span>_</span></a></li>
+    <li><a href="globals_0x61.html#index_a"><span>a</span></a></li>
+    <li><a href="globals_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="globals_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="globals_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="globals_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="globals_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="globals_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="globals_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="globals_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="globals_0x6b.html#index_k"><span>k</span></a></li>
+    <li><a href="globals_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="globals_0x6e.html#index_n"><span>n</span></a></li>
+    <li id="current"><a href="globals_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="globals_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="globals_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="globals_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="globals_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="globals_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="globals_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="globals_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="globals_0x77.html#index_w"><span>w</span></a></li>
+  </ul>
+</div>
+
+<p>
+Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:
+<p>
+<h3><a class="anchor" name="index_o">- o -</a></h3><ul>
+<li>OTG_CORE_REV_2_60a
+: <a class="el" href="dwc__otg__cil_8h.html#51536e4844fe9022b60531eebca32a26">dwc_otg_cil.h</a><li>OTG_CORE_REV_2_71a
+: <a class="el" href="dwc__otg__cil_8h.html#aac1e3cc465029aa0a2965b7c6d9fc50">dwc_otg_cil.h</a><li>OTG_CORE_REV_2_72a
+: <a class="el" href="dwc__otg__cil_8h.html#3d25615a19f95042bcc3512b4855cebe">dwc_otg_cil.h</a><li>OTG_CORE_REV_2_80a
+: <a class="el" href="dwc__otg__cil_8h.html#02c75ff58b0b88ae59c89063478648dd">dwc_otg_cil.h</a><li>OTG_CORE_REV_2_81a
+: <a class="el" href="dwc__otg__cil_8h.html#ceb592db3a34e7435e6bd9fc4cf5627c">dwc_otg_cil.h</a><li>OTG_CORE_REV_2_90a
+: <a class="el" href="dwc__otg__cil_8h.html#c2f4aa7b1cfc164330925404c5029724">dwc_otg_cil.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_0x70.html b/drivers/usb/host/dwc_otg/doc/html/globals_0x70.html
new file mode 100644
index 000000000000..7b54408a42ca
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_0x70.html
@@ -0,0 +1,84 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li id="current"><a href="globals.html"><span>All</span></a></li>
+    <li><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html#index__"><span>_</span></a></li>
+    <li><a href="globals_0x61.html#index_a"><span>a</span></a></li>
+    <li><a href="globals_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="globals_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="globals_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="globals_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="globals_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="globals_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="globals_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="globals_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="globals_0x6b.html#index_k"><span>k</span></a></li>
+    <li><a href="globals_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="globals_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="globals_0x6f.html#index_o"><span>o</span></a></li>
+    <li id="current"><a href="globals_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="globals_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="globals_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="globals_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="globals_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="globals_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="globals_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="globals_0x77.html#index_w"><span>w</span></a></li>
+  </ul>
+</div>
+
+<p>
+Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:
+<p>
+<h3><a class="anchor" name="index_p">- p -</a></h3><ul>
+<li>packed
+: <a class="el" href="dwc__otg__cfi_8h.html#3e7b3a7aca62be5747bfe900e0a9e102">dwc_otg_cfi.h</a><li>pcd_callbacks
+: <a class="el" href="dwc__otg__pcd_8c.html#c360aaa36ba28b977284fd482e7bc5ca">dwc_otg_pcd.c</a><li>pcd_clear_halt()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#153d9a3b2162ef091dc24027379af19f">dwc_otg_pcd_intr.c</a><li>pcd_init()
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#9dbc565a7942db0adbf1ec341db22901">dwc_otg_pcd_linux.c</a>, <a class="el" href="dwc__otg__driver_8c.html#9dbc565a7942db0adbf1ec341db22901">dwc_otg_driver.c</a><li>pcd_remove()
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#03129ea5120095af86c98558792aeae8">dwc_otg_pcd_linux.c</a>, <a class="el" href="dwc__otg__driver_8c.html#7960b8e2c02d9ab89b65cb01ba08658b">dwc_otg_driver.c</a><li>pcd_resume()
+: <a class="el" href="dwc__otg__cil__intr_8c.html#7d70de843b2e147969d32f7a9b2aa9e3">dwc_otg_cil_intr.c</a><li>pcd_setup()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#856a520a378e4f6f274253227080cfa1">dwc_otg_pcd_intr.c</a><li>pcd_start()
+: <a class="el" href="dwc__otg__cil__intr_8c.html#a1de88a9a54457a0b828a8a2845a210c">dwc_otg_cil_intr.c</a><li>pcd_stop()
+: <a class="el" href="dwc__otg__cil__intr_8c.html#d8eff82b37ea044fd7621faedcb36570">dwc_otg_cil_intr.c</a><li>pcd_suspend()
+: <a class="el" href="dwc__otg__cil__intr_8c.html#d9ac0577152f65fe83a76cbbca4ea795">dwc_otg_cil_intr.c</a><li>pcgcctl_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#5efd1b5bf72987298cdf3d79bca37832">dwc_otg_regs.h</a><li>per_sched_disable()
+: <a class="el" href="dwc__otg__hcd__ddma_8c.html#693b9fdfeebc77b8132cfaf461b9c8fd">dwc_otg_hcd_ddma.c</a><li>per_sched_enable()
+: <a class="el" href="dwc__otg__hcd__ddma_8c.html#5b78d71512c6143d5a50e31dc3517f6a">dwc_otg_hcd_ddma.c</a><li>periodic_channel_available()
+: <a class="el" href="dwc__otg__hcd__queue_8c.html#debf9d35891234a74bc00832bba603bc">dwc_otg_hcd_queue.c</a><li>print_ep0_state()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#13cc45eef95b81189df890c10cf7ca66">dwc_otg_pcd_intr.c</a><li>process_non_periodic_channels()
+: <a class="el" href="dwc__otg__hcd_8c.html#a3f28e8605fd652c5177962e5dc8b95a">dwc_otg_hcd.c</a><li>process_periodic_channels()
+: <a class="el" href="dwc__otg__hcd_8c.html#00876268eb53e5ce91dbedcb026181ec">dwc_otg_hcd.c</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_0x71.html b/drivers/usb/host/dwc_otg/doc/html/globals_0x71.html
new file mode 100644
index 000000000000..3a79b908b60d
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_0x71.html
@@ -0,0 +1,70 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li id="current"><a href="globals.html"><span>All</span></a></li>
+    <li><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html#index__"><span>_</span></a></li>
+    <li><a href="globals_0x61.html#index_a"><span>a</span></a></li>
+    <li><a href="globals_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="globals_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="globals_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="globals_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="globals_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="globals_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="globals_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="globals_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="globals_0x6b.html#index_k"><span>k</span></a></li>
+    <li><a href="globals_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="globals_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="globals_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="globals_0x70.html#index_p"><span>p</span></a></li>
+    <li id="current"><a href="globals_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="globals_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="globals_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="globals_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="globals_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="globals_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="globals_0x77.html#index_w"><span>w</span></a></li>
+  </ul>
+</div>
+
+<p>
+Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:
+<p>
+<h3><a class="anchor" name="index_q">- q -</a></h3><ul>
+<li>qh_init()
+: <a class="el" href="dwc__otg__hcd__queue_8c.html#d32f8a4be67b758e9541e33746363677">dwc_otg_hcd_queue.c</a><li>qh_list_free()
+: <a class="el" href="dwc__otg__hcd_8c.html#d76881c1efea1a13be74ecfde85b4881">dwc_otg_hcd.c</a><li>queue_transaction()
+: <a class="el" href="dwc__otg__hcd_8c.html#8c7cd2f81cf41dbf3158f49b1d82a4f8">dwc_otg_hcd.c</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_0x72.html b/drivers/usb/host/dwc_otg/doc/html/globals_0x72.html
new file mode 100644
index 000000000000..fde6703e5202
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_0x72.html
@@ -0,0 +1,94 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li id="current"><a href="globals.html"><span>All</span></a></li>
+    <li><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html#index__"><span>_</span></a></li>
+    <li><a href="globals_0x61.html#index_a"><span>a</span></a></li>
+    <li><a href="globals_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="globals_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="globals_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="globals_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="globals_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="globals_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="globals_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="globals_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="globals_0x6b.html#index_k"><span>k</span></a></li>
+    <li><a href="globals_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="globals_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="globals_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="globals_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="globals_0x71.html#index_q"><span>q</span></a></li>
+    <li id="current"><a href="globals_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="globals_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="globals_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="globals_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="globals_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="globals_0x77.html#index_w"><span>w</span></a></li>
+  </ul>
+</div>
+
+<p>
+Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:
+<p>
+<h3><a class="anchor" name="index_r">- r -</a></h3><ul>
+<li>rd_reg_test
+: <a class="el" href="dwc__otg__attr_8c.html#829fa87e3e65ff4038b6bc0eb2a93fb7">dwc_otg_attr.c</a><li>rd_reg_test_show
+: <a class="el" href="dwc__otg__attr_8c.html#81946b90c6e16e9596d9b9ccd1d54476">dwc_otg_attr.c</a><li>recalc_initial_desc_idx()
+: <a class="el" href="dwc__otg__hcd__ddma_8c.html#fc5f584eb735a394a794a3022939638a">dwc_otg_hcd_ddma.c</a><li>regdump
+: <a class="el" href="dwc__otg__attr_8c.html#8db089dfccee4ac4de5f89814ddd42fc">dwc_otg_attr.c</a><li>regdump_show
+: <a class="el" href="dwc__otg__attr_8c.html#36728dcc762e9cbdbc9543c8b780df68">dwc_otg_attr.c</a><li>regoffset
+: <a class="el" href="dwc__otg__attr_8c.html#aeabf3d18b9b521d65b364cec3dcde45">dwc_otg_attr.c</a><li>regoffset_show
+: <a class="el" href="dwc__otg__attr_8c.html#ca58f009788e262a917c23784a84cb16">dwc_otg_attr.c</a><li>regoffset_store
+: <a class="el" href="dwc__otg__attr_8c.html#fc5be3dbcd075f5087ca1730661c5dc2">dwc_otg_attr.c</a><li>regvalue
+: <a class="el" href="dwc__otg__attr_8c.html#c246d9ba494611cb5b3054a71bf21d22">dwc_otg_attr.c</a><li>regvalue_show
+: <a class="el" href="dwc__otg__attr_8c.html#bb38eb60bd43b1de364db80fd1bcdbcf">dwc_otg_attr.c</a><li>regvalue_store
+: <a class="el" href="dwc__otg__attr_8c.html#7db6b85ac60be49f52987e615a01408b">dwc_otg_attr.c</a><li>reinit_ddma_iso_xfer()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#c3f6fb3131e0786ec75a9c4a29fea297">dwc_otg_pcd_intr.c</a><li>release_channel()
+: <a class="el" href="dwc__otg__hcd__intr_8c.html#4f6bf01b14a03eeed81d27bffa5e99fc">dwc_otg_hcd_intr.c</a><li>release_channel_ddma()
+: <a class="el" href="dwc__otg__hcd__ddma_8c.html#060f60ac2e210b5da3bbe379674d2012">dwc_otg_hcd_ddma.c</a><li>release_perio_tx_fifo()
+: <a class="el" href="dwc__otg__pcd_8c.html#1bd1933ef625beee77eb026c4b1acb15">dwc_otg_pcd.c</a><li>release_tx_fifo()
+: <a class="el" href="dwc__otg__pcd_8c.html#bde782d98282535dc0c29a468da11f02">dwc_otg_pcd.c</a><li>remote_wakeup
+: <a class="el" href="dwc__otg__attr_8c.html#f3afff970133d773b5414f1f0f2becfe">dwc_otg_attr.c</a><li>remote_wakeup_show
+: <a class="el" href="dwc__otg__attr_8c.html#3321551071eb0987630d501c377ff095">dwc_otg_attr.c</a><li>remote_wakeup_store
+: <a class="el" href="dwc__otg__attr_8c.html#e64972f2160646d9d707a97366eba56c">dwc_otg_attr.c</a><li>reset_tasklet_func()
+: <a class="el" href="dwc__otg__hcd_8c.html#ed4640393d701e9bbfd966d4006a60b8">dwc_otg_hcd.c</a><li>restart_transfer()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#ed405cebf67cd1a89efd15a2935c8cef">dwc_otg_pcd_intr.c</a><li>RTS_BUFERR
+: <a class="el" href="dwc__otg__regs_8h.html#55b69fa65e7d41448646c88fc0642408">dwc_otg_regs.h</a><li>RTS_BUFFLUSH
+: <a class="el" href="dwc__otg__regs_8h.html#46f9d43df5fef233f4f5415d4719c1da">dwc_otg_regs.h</a><li>RTS_RESERVED
+: <a class="el" href="dwc__otg__regs_8h.html#1fa264096eca908e709d19b87a53f13f">dwc_otg_regs.h</a><li>RTS_SUCCESS
+: <a class="el" href="dwc__otg__regs_8h.html#cc9b21a293ad5a9103a64d76314a052e">dwc_otg_regs.h</a><li>RW_REG_COUNT
+: <a class="el" href="dwc__otg__attr_8c.html#5f954c85228b04a896cab754ab56358e">dwc_otg_attr.c</a><li>rx_fifo_size_setup_t
+: <a class="el" href="dwc__otg__cfi_8h.html#0fbbd60333457c6667bd7757e4aac2f8">dwc_otg_cfi.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_0x73.html b/drivers/usb/host/dwc_otg/doc/html/globals_0x73.html
new file mode 100644
index 000000000000..33736a0a3407
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_0x73.html
@@ -0,0 +1,85 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li id="current"><a href="globals.html"><span>All</span></a></li>
+    <li><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html#index__"><span>_</span></a></li>
+    <li><a href="globals_0x61.html#index_a"><span>a</span></a></li>
+    <li><a href="globals_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="globals_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="globals_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="globals_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="globals_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="globals_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="globals_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="globals_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="globals_0x6b.html#index_k"><span>k</span></a></li>
+    <li><a href="globals_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="globals_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="globals_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="globals_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="globals_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="globals_0x72.html#index_r"><span>r</span></a></li>
+    <li id="current"><a href="globals_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="globals_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="globals_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="globals_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="globals_0x77.html#index_w"><span>w</span></a></li>
+  </ul>
+</div>
+
+<p>
+Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:
+<p>
+<h3><a class="anchor" name="index_s">- s -</a></h3><ul>
+<li>S3C2410X_CLEAR_EINTPEND
+: <a class="el" href="dwc__otg__driver_8h.html#3af7bafbb69f04a0fd36a27fae7e8497">dwc_otg_driver.h</a><li>S_IWUSR
+: <a class="el" href="dwc__otg__attr_8c.html#ac2308832629daf78cb9dd123551cd8a">dwc_otg_attr.c</a><li>schedule_periodic()
+: <a class="el" href="dwc__otg__hcd__queue_8c.html#06b5d4bb36612e7da15a3727b1396a0c">dwc_otg_hcd_queue.c</a><li>SCHEDULE_SLOP
+: <a class="el" href="dwc__otg__hcd__queue_8c.html#86d31a59a5f7c095cd183a06edeed5e1">dwc_otg_hcd_queue.c</a><li>set_current_pkt_info()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#17428b2360118cc59ab9d5cbcef8a14b">dwc_otg_pcd_intr.c</a><li>set_ddma_iso_pkts_info()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#e5ed26b3ab2380cb92773df1720ec752">dwc_otg_pcd_intr.c</a><li>SET_DEBUG_LEVEL()
+: <a class="el" href="dwc__otg__dbg_8h.html#68eadfdf7a6a3f2eed00492119b00bae">dwc_otg_dbg.h</a><li>set_iso_pkts_info()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#a356ecc4053e9700785a27dbfdd6b2db">dwc_otg_pcd_intr.c</a><li>set_parameters()
+: <a class="el" href="dwc__otg__driver_8c.html#fe3a3765da365671b36ba5e28dc4d38b">dwc_otg_driver.c</a><li>set_pid_isoc()
+: <a class="el" href="dwc__otg__cil_8c.html#bf1f2e3a039a78f9cc51c8223c40d8e1">dwc_otg_cil.c</a><li>spramdump
+: <a class="el" href="dwc__otg__attr_8c.html#d24c69237b2acf90968b763e467e9ec9">dwc_otg_attr.c</a><li>spramdump_show
+: <a class="el" href="dwc__otg__attr_8c.html#e98e139afbb50f9d989ddbef2f0dbd6e">dwc_otg_attr.c</a><li>srp
+: <a class="el" href="dwc__otg__attr_8c.html#0c2c4ba16770c40a82dbb1c33cbc2e4a">dwc_otg_attr.c</a><li>srp_show
+: <a class="el" href="dwc__otg__attr_8c.html#9e8313bb6a0f54484d279b2e28269712">dwc_otg_attr.c</a><li>srp_store
+: <a class="el" href="dwc__otg__attr_8c.html#80c785e24be4a8ce02d0b38a0ba5484a">dwc_otg_attr.c</a><li>srp_timeout()
+: <a class="el" href="dwc__otg__pcd_8c.html#e1e5a9264c2ad212d697d6be1110874f">dwc_otg_pcd.c</a><li>start_next_request()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#de7160b7e7b8fd622ba95392513e197c">dwc_otg_pcd_intr.c</a>, <a class="el" href="dwc__otg__pcd_8c.html#de7160b7e7b8fd622ba95392513e197c">dwc_otg_pcd.c</a><li>start_xfer_tasklet_func()
+: <a class="el" href="dwc__otg__pcd_8c.html#4d9d8f7fb8f74eb64176fba91b38cb35">dwc_otg_pcd.c</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_0x74.html b/drivers/usb/host/dwc_otg/doc/html/globals_0x74.html
new file mode 100644
index 000000000000..9884208a6b9a
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_0x74.html
@@ -0,0 +1,68 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li id="current"><a href="globals.html"><span>All</span></a></li>
+    <li><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html#index__"><span>_</span></a></li>
+    <li><a href="globals_0x61.html#index_a"><span>a</span></a></li>
+    <li><a href="globals_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="globals_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="globals_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="globals_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="globals_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="globals_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="globals_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="globals_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="globals_0x6b.html#index_k"><span>k</span></a></li>
+    <li><a href="globals_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="globals_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="globals_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="globals_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="globals_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="globals_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="globals_0x73.html#index_s"><span>s</span></a></li>
+    <li id="current"><a href="globals_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="globals_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="globals_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="globals_0x77.html#index_w"><span>w</span></a></li>
+  </ul>
+</div>
+
+<p>
+Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:
+<p>
+<h3><a class="anchor" name="index_t">- t -</a></h3><ul>
+<li>tx_fifo_size_setup_t
+: <a class="el" href="dwc__otg__cfi_8h.html#9da70e9326ec40c9f1bd9c487aabe4c1">dwc_otg_cfi.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_0x75.html b/drivers/usb/host/dwc_otg/doc/html/globals_0x75.html
new file mode 100644
index 000000000000..3e6fe31a76b9
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_0x75.html
@@ -0,0 +1,80 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li id="current"><a href="globals.html"><span>All</span></a></li>
+    <li><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html#index__"><span>_</span></a></li>
+    <li><a href="globals_0x61.html#index_a"><span>a</span></a></li>
+    <li><a href="globals_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="globals_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="globals_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="globals_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="globals_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="globals_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="globals_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="globals_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="globals_0x6b.html#index_k"><span>k</span></a></li>
+    <li><a href="globals_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="globals_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="globals_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="globals_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="globals_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="globals_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="globals_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="globals_0x74.html#index_t"><span>t</span></a></li>
+    <li id="current"><a href="globals_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="globals_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="globals_0x77.html#index_w"><span>w</span></a></li>
+  </ul>
+</div>
+
+<p>
+Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:
+<p>
+<h3><a class="anchor" name="index_u">- u -</a></h3><ul>
+<li>UPACKED
+: <a class="el" href="dwc__otg__cfi_8h.html#289004a802a0ba1d6ccaf6c6969f4e3f">dwc_otg_cfi.h</a>, <a class="el" href="dwc__cfi__common_8h.html#6c83e2952dc5636d5cfc5336217dcfcd">dwc_cfi_common.h</a><li>update_frame_list()
+: <a class="el" href="dwc__otg__hcd__ddma_8c.html#46c1ec7e2bd2f1177983f6676952cfdf">dwc_otg_hcd_ddma.c</a><li>update_isoc_urb_state()
+: <a class="el" href="dwc__otg__hcd__intr_8c.html#e93d54bdf873c5a31882660c2984458e">dwc_otg_hcd_intr.c</a><li>update_non_isoc_urb_state_ddma()
+: <a class="el" href="dwc__otg__hcd__ddma_8c.html#7a1a6af7f05278f5b7daa3b0a2d2fa4a">dwc_otg_hcd_ddma.c</a><li>update_urb_state_xfer_comp()
+: <a class="el" href="dwc__otg__hcd__intr_8c.html#ecb30a961e8d4831e8691d45a77162e3">dwc_otg_hcd_intr.c</a><li>update_urb_state_xfer_intr()
+: <a class="el" href="dwc__otg__hcd__intr_8c.html#0640c3606be7a8700ea4813e590ebf43">dwc_otg_hcd_intr.c</a><li>urb_dequeue()
+: <a class="el" href="dwc__otg__hcd__linux_8c.html#afc1f3d92fd7596140c0068bc96034f7">dwc_otg_hcd_linux.c</a><li>urb_enqueue()
+: <a class="el" href="dwc__otg__hcd__linux_8c.html#d9e9c76f2bc1c4f662d132c710a95a60">dwc_otg_hcd_linux.c</a><li>URB_GIVEBACK_ASAP
+: <a class="el" href="dwc__otg__hcd__if_8h.html#973a9deb7ee08e99abf7cb7adf6a5c72">dwc_otg_hcd_if.h</a><li>URB_SEND_ZERO_PACKET
+: <a class="el" href="dwc__otg__hcd__if_8h.html#14e576ea3b30c038f925e3e6c80c64fe">dwc_otg_hcd_if.h</a><li>USB_DWC
+: <a class="el" href="dwc__otg__dbg_8h.html#c1cdef6b622b17c7bb2d2574c6b66e0c">dwc_otg_dbg.h</a><li>usb_gadget_register_driver()
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#8c1ba129028b3b16909973eb30b85d2c">dwc_otg_pcd_linux.c</a><li>usb_gadget_unregister_driver()
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#fa4a24d0806fbb6e3135d27d24a6a00d">dwc_otg_pcd_linux.c</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_0x76.html b/drivers/usb/host/dwc_otg/doc/html/globals_0x76.html
new file mode 100644
index 000000000000..bf2c6342a389
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_0x76.html
@@ -0,0 +1,75 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li id="current"><a href="globals.html"><span>All</span></a></li>
+    <li><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html#index__"><span>_</span></a></li>
+    <li><a href="globals_0x61.html#index_a"><span>a</span></a></li>
+    <li><a href="globals_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="globals_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="globals_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="globals_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="globals_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="globals_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="globals_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="globals_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="globals_0x6b.html#index_k"><span>k</span></a></li>
+    <li><a href="globals_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="globals_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="globals_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="globals_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="globals_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="globals_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="globals_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="globals_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="globals_0x75.html#index_u"><span>u</span></a></li>
+    <li id="current"><a href="globals_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="globals_0x77.html#index_w"><span>w</span></a></li>
+  </ul>
+</div>
+
+<p>
+Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:
+<p>
+<h3><a class="anchor" name="index_v">- v -</a></h3><ul>
+<li>VEN_CORE_ACTIVATE_FEATURES
+: <a class="el" href="dwc__cfi__common_8h.html#1d1302d0d167f7c9580878fbfff847d4">dwc_cfi_common.h</a><li>VEN_CORE_GET_FEATURE
+: <a class="el" href="dwc__cfi__common_8h.html#22bf207e476d086391240b18aacc0314">dwc_cfi_common.h</a><li>VEN_CORE_GET_FEATURES
+: <a class="el" href="dwc__cfi__common_8h.html#b206fe3fb25aa96547a4bc0e47a864c6">dwc_cfi_common.h</a><li>VEN_CORE_READ_REGISTER
+: <a class="el" href="dwc__cfi__common_8h.html#8d4bf92524d3e5fd4b4b060fc1269ec6">dwc_cfi_common.h</a><li>VEN_CORE_RESET_FEATURES
+: <a class="el" href="dwc__cfi__common_8h.html#f7551c9e324871e8258dacc4f4467846">dwc_cfi_common.h</a><li>VEN_CORE_SET_FEATURE
+: <a class="el" href="dwc__cfi__common_8h.html#ee7fb610a7fb2437df3425e2330e9d39">dwc_cfi_common.h</a><li>VEN_CORE_WRITE_REGISTER
+: <a class="el" href="dwc__cfi__common_8h.html#d132d545f74a408b62d44a34ba51426c">dwc_cfi_common.h</a><li>version_show()
+: <a class="el" href="dwc__otg__driver_8c.html#6eaf4dedcf1df7eb80c48f1872212012">dwc_otg_driver.c</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_0x77.html b/drivers/usb/host/dwc_otg/doc/html/globals_0x77.html
new file mode 100644
index 000000000000..d1af4b37a7ac
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_0x77.html
@@ -0,0 +1,74 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li id="current"><a href="globals.html"><span>All</span></a></li>
+    <li><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html#index__"><span>_</span></a></li>
+    <li><a href="globals_0x61.html#index_a"><span>a</span></a></li>
+    <li><a href="globals_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="globals_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="globals_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="globals_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="globals_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="globals_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="globals_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="globals_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="globals_0x6b.html#index_k"><span>k</span></a></li>
+    <li><a href="globals_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="globals_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="globals_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="globals_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="globals_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="globals_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="globals_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="globals_0x74.html#index_t"><span>t</span></a></li>
+    <li><a href="globals_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="globals_0x76.html#index_v"><span>v</span></a></li>
+    <li id="current"><a href="globals_0x77.html#index_w"><span>w</span></a></li>
+  </ul>
+</div>
+
+<p>
+Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:
+<p>
+<h3><a class="anchor" name="index_w">- w -</a></h3><ul>
+<li>w_conn_id_status_change()
+: <a class="el" href="dwc__otg__cil__intr_8c.html#9ef061e0e79210e6c2a2c2b9cc45bd45">dwc_otg_cil_intr.c</a>, <a class="el" href="dwc__otg__cil_8h.html#9ef061e0e79210e6c2a2c2b9cc45bd45">dwc_otg_cil.h</a><li>w_wakeup_detected()
+: <a class="el" href="dwc__otg__cil__intr_8c.html#07f0b189448c71e7ea4c7b121320fb89">dwc_otg_cil_intr.c</a>, <a class="el" href="dwc__otg__cil_8h.html#07f0b189448c71e7ea4c7b121320fb89">dwc_otg_cil.h</a><li>wakeup()
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#6a6034564b7cc6d8cebfbe02a944cd2c">dwc_otg_pcd_linux.c</a><li>wr_reg_test
+: <a class="el" href="dwc__otg__attr_8c.html#b46682cc35d8ddece607cdf93c124575">dwc_otg_attr.c</a><li>wr_reg_test_show
+: <a class="el" href="dwc__otg__attr_8c.html#9dd7132e3f334eed0e27e11ab5f7b0c4">dwc_otg_attr.c</a><li>write_empty_tx_fifo()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#5e53962e63763aa9df6400981b7d5354">dwc_otg_pcd_intr.c</a><li>write_isoc_frame_data()
+: <a class="el" href="dwc__otg__cil_8c.html#e39d47d3aee9efcd525c13ce6a1f5f6a">dwc_otg_cil.c</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_defs.html b/drivers/usb/host/dwc_otg/doc/html/globals_defs.html
new file mode 100644
index 000000000000..d156f9318643
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_defs.html
@@ -0,0 +1,68 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html"><span>All</span></a></li>
+    <li><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li id="current"><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li id="current"><a href="globals_defs.html#index__"><span>_</span></a></li>
+    <li><a href="globals_defs_0x61.html#index_a"><span>a</span></a></li>
+    <li><a href="globals_defs_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="globals_defs_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="globals_defs_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="globals_defs_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="globals_defs_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="globals_defs_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="globals_defs_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="globals_defs_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="globals_defs_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="globals_defs_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="globals_defs_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="globals_defs_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="globals_defs_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="globals_defs_0x76.html#index_v"><span>v</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index__">- _ -</a></h3><ul>
+<li>__DWC_CFI_COMMON_H__
+: <a class="el" href="dwc__cfi__common_8h.html#50e76b6bdcb8e42b2b48aada9a1833e2">dwc_cfi_common.h</a><li>__DWC_CIL_H__
+: <a class="el" href="dwc__otg__cil_8h.html#c9555551bb7f2d0a51be23d54463f2ec">dwc_otg_cil.h</a><li>__DWC_CORE_IF_H__
+: <a class="el" href="dwc__otg__core__if_8h.html#5bae757850823a08f21d3c2156dcdb19">dwc_otg_core_if.h</a><li>__DWC_OTG_ATTR_H__
+: <a class="el" href="dwc__otg__attr_8h.html#338d875aceea377e37f82aa8fe743420">dwc_otg_attr.h</a><li>__DWC_OTG_CFI_H__
+: <a class="el" href="dwc__otg__cfi_8h.html#d4efa118a5f5c82587650944721a8dc1">dwc_otg_cfi.h</a><li>__DWC_PCD_H__
+: <a class="el" href="dwc__otg__pcd_8h.html#ed26bb67f5785dc6e70289976637a310">dwc_otg_pcd.h</a><li>__DWC_PCD_IF_H__
+: <a class="el" href="dwc__otg__pcd__if_8h.html#f647f1720e56adb91588a6e55179dec5">dwc_otg_pcd_if.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x61.html b/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x61.html
new file mode 100644
index 000000000000..54995e9f1976
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x61.html
@@ -0,0 +1,64 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html"><span>All</span></a></li>
+    <li><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li id="current"><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals_defs.html#index__"><span>_</span></a></li>
+    <li id="current"><a href="globals_defs_0x61.html#index_a"><span>a</span></a></li>
+    <li><a href="globals_defs_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="globals_defs_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="globals_defs_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="globals_defs_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="globals_defs_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="globals_defs_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="globals_defs_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="globals_defs_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="globals_defs_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="globals_defs_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="globals_defs_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="globals_defs_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="globals_defs_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="globals_defs_0x76.html#index_v"><span>v</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_a">- a -</a></h3><ul>
+<li>A_HOST
+: <a class="el" href="dwc__otg__cil_8h.html#a0732b344b6571a4554968e4ee2214dd">dwc_otg_cil.h</a><li>A_PERIPHERAL
+: <a class="el" href="dwc__otg__cil_8h.html#7528970c03451cfc85e86ab92bbaf554">dwc_otg_cil.h</a><li>A_SUSPEND
+: <a class="el" href="dwc__otg__cil_8h.html#da9f5eb506da71435e8976ceb38bc14d">dwc_otg_cil.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x62.html b/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x62.html
new file mode 100644
index 000000000000..7b3afdcf4340
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x62.html
@@ -0,0 +1,71 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html"><span>All</span></a></li>
+    <li><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li id="current"><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals_defs.html#index__"><span>_</span></a></li>
+    <li><a href="globals_defs_0x61.html#index_a"><span>a</span></a></li>
+    <li id="current"><a href="globals_defs_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="globals_defs_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="globals_defs_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="globals_defs_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="globals_defs_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="globals_defs_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="globals_defs_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="globals_defs_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="globals_defs_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="globals_defs_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="globals_defs_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="globals_defs_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="globals_defs_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="globals_defs_0x76.html#index_v"><span>v</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_b">- b -</a></h3><ul>
+<li>B_HOST
+: <a class="el" href="dwc__otg__cil_8h.html#02d6d4d9a0fdcc4fc8c5cf8e6c8577aa">dwc_otg_cil.h</a><li>B_PERIPHERAL
+: <a class="el" href="dwc__otg__cil_8h.html#622c3b95c9a587f518a787c05c50ffb7">dwc_otg_cil.h</a><li>BitStuffTime
+: <a class="el" href="dwc__otg__hcd__queue_8c.html#e740bef95f7929a07065b699f6f087a2">dwc_otg_hcd_queue.c</a><li>BS_ALIGN_VAL_HDR_LEN
+: <a class="el" href="dwc__otg__cfi_8h.html#5495ec473ea2d7c8f805567416c559f0">dwc_otg_cfi.h</a><li>BS_CONCAT_VAL_HDR_LEN
+: <a class="el" href="dwc__otg__cfi_8h.html#c89955571b72df025126a1047bc53a00">dwc_otg_cfi.h</a><li>BS_DMA_BUSY
+: <a class="el" href="dwc__otg__regs_8h.html#3110b1318d89fe11ee69f3ccbe219c4e">dwc_otg_regs.h</a><li>BS_DMA_DONE
+: <a class="el" href="dwc__otg__regs_8h.html#b20f6432003d81072ed8b7cd66d6305b">dwc_otg_regs.h</a><li>BS_HOST_BUSY
+: <a class="el" href="dwc__otg__regs_8h.html#e6e96a79797557986256d1a1ff104ca1">dwc_otg_regs.h</a><li>BS_HOST_READY
+: <a class="el" href="dwc__otg__regs_8h.html#c2cfc53da94087a90d21d3528b005bcf">dwc_otg_regs.h</a><li>BS_SG_VAL_DESC_LEN
+: <a class="el" href="dwc__otg__cfi_8h.html#2332c8839256e2bb1aa1e0e8a9185ce2">dwc_otg_cfi.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x63.html b/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x63.html
new file mode 100644
index 000000000000..ba1c6e53fa13
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x63.html
@@ -0,0 +1,74 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html"><span>All</span></a></li>
+    <li><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li id="current"><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals_defs.html#index__"><span>_</span></a></li>
+    <li><a href="globals_defs_0x61.html#index_a"><span>a</span></a></li>
+    <li><a href="globals_defs_0x62.html#index_b"><span>b</span></a></li>
+    <li id="current"><a href="globals_defs_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="globals_defs_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="globals_defs_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="globals_defs_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="globals_defs_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="globals_defs_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="globals_defs_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="globals_defs_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="globals_defs_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="globals_defs_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="globals_defs_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="globals_defs_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="globals_defs_0x76.html#index_v"><span>v</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_c">- c -</a></h3><ul>
+<li>CFI_ALL_FEATURES_HDR_LEN
+: <a class="el" href="dwc__cfi__common_8h.html#b6c1d0a310ae1d0a89437b2cf92e57ba">dwc_cfi_common.h</a><li>CFI_CORE_ID_OTG
+: <a class="el" href="dwc__cfi__common_8h.html#4b0c4a003085148bef609d81fa3c1589">dwc_cfi_common.h</a><li>CFI_CORE_ID_UDC
+: <a class="el" href="dwc__cfi__common_8h.html#227fde38cd429d2ecaf3cd5bdd5d67d9">dwc_cfi_common.h</a><li>CFI_CORE_ID_WUDEV
+: <a class="el" href="dwc__cfi__common_8h.html#b885f7a00a119d048803beaf41a5dc30">dwc_cfi_common.h</a><li>CFI_FEATURE_ATTR_RO
+: <a class="el" href="dwc__cfi__common_8h.html#45ffc2183d956983ca297033f9e527af">dwc_cfi_common.h</a><li>CFI_FEATURE_ATTR_RW
+: <a class="el" href="dwc__cfi__common_8h.html#a4536fb9c1314c2f90a93cfcd082dbb9">dwc_cfi_common.h</a><li>CFI_FEATURE_DESC_HDR_LEN
+: <a class="el" href="dwc__cfi__common_8h.html#7ec5e43b7d52a39b553fdfa8fb17d889">dwc_cfi_common.h</a><li>CFI_IN_BUF_LEN
+: <a class="el" href="dwc__otg__cfi_8h.html#34582b9ef366f4c0e8ea24aa2388e829">dwc_otg_cfi.h</a><li>CFI_INFO
+: <a class="el" href="dwc__otg__cfi_8h.html#f121e7b686ae7277b695f7209c41135f">dwc_otg_cfi.h</a><li>CFI_INFO_DEF
+: <a class="el" href="dwc__otg__cfi_8h.html#7f62f8d1e9825c09b1f7d2badbe2527a">dwc_otg_cfi.h</a><li>CFI_OUT_BUF_LEN
+: <a class="el" href="dwc__otg__cfi_8h.html#739556affb10ce8a44b362b8ffa41a40">dwc_otg_cfi.h</a><li>CHK_DEBUG_LEVEL
+: <a class="el" href="dwc__otg__dbg_8h.html#7a96217c88a4d786f6cb3d4df09dee04">dwc_otg_dbg.h</a><li>clear_hc_int
+: <a class="el" href="dwc__otg__cil_8h.html#071cb1f3f29f9a52775e9fff270b1c7c">dwc_otg_cil.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x64.html b/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x64.html
new file mode 100644
index 000000000000..874f082138e8
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x64.html
@@ -0,0 +1,241 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html"><span>All</span></a></li>
+    <li><a href="globals_func.html"><span>Functions</span></a></li>
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+  </ul>
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+    <li><a href="globals_defs_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="globals_defs_0x76.html#index_v"><span>v</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_d">- d -</a></h3><ul>
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+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x66.html b/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x66.html
new file mode 100644
index 000000000000..7c3a3e76903f
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x66.html
@@ -0,0 +1,71 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html"><span>All</span></a></li>
+    <li><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li id="current"><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals_defs.html#index__"><span>_</span></a></li>
+    <li><a href="globals_defs_0x61.html#index_a"><span>a</span></a></li>
+    <li><a href="globals_defs_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="globals_defs_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="globals_defs_0x64.html#index_d"><span>d</span></a></li>
+    <li id="current"><a href="globals_defs_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="globals_defs_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="globals_defs_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="globals_defs_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="globals_defs_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="globals_defs_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="globals_defs_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="globals_defs_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="globals_defs_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="globals_defs_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="globals_defs_0x76.html#index_v"><span>v</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_f">- f -</a></h3><ul>
+<li>FS_LS_HOST_DELAY
+: <a class="el" href="dwc__otg__hcd__queue_8c.html#8f9875d35aace115a340d2cef9c66294">dwc_otg_hcd_queue.c</a><li>FT_ID_DFIFO_DEPTH
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+: <a class="el" href="dwc__otg__cfi_8h.html#0e196868939f6bbf0d157868bfc90208">dwc_otg_cfi.h</a><li>FT_ID_RX_FIFO_DEPTH
+: <a class="el" href="dwc__otg__cfi_8h.html#42b7c98c105de1f9399786a3419e7e20">dwc_otg_cfi.h</a><li>FT_ID_THRESHOLD_SETUP
+: <a class="el" href="dwc__otg__cfi_8h.html#bcc99a9e5a0b15b4212d88bd9c610647">dwc_otg_cfi.h</a><li>FT_ID_TX_FIFO_DEPTH
+: <a class="el" href="dwc__otg__cfi_8h.html#a3a67b679a59c5279370bbf69f114cb6">dwc_otg_cfi.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x67.html b/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x67.html
new file mode 100644
index 000000000000..0f983adc21b7
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x67.html
@@ -0,0 +1,62 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html"><span>All</span></a></li>
+    <li><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li id="current"><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals_defs.html#index__"><span>_</span></a></li>
+    <li><a href="globals_defs_0x61.html#index_a"><span>a</span></a></li>
+    <li><a href="globals_defs_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="globals_defs_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="globals_defs_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="globals_defs_0x66.html#index_f"><span>f</span></a></li>
+    <li id="current"><a href="globals_defs_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="globals_defs_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="globals_defs_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="globals_defs_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="globals_defs_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="globals_defs_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="globals_defs_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="globals_defs_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="globals_defs_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="globals_defs_0x76.html#index_v"><span>v</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_g">- g -</a></h3><ul>
+<li>GET_CORE_IF
+: <a class="el" href="dwc__otg__pcd_8h.html#464549f9f4484651efe25b1a03692d72">dwc_otg_pcd.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x68.html b/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x68.html
new file mode 100644
index 000000000000..824fbd79b396
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x68.html
@@ -0,0 +1,63 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html"><span>All</span></a></li>
+    <li><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li id="current"><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals_defs.html#index__"><span>_</span></a></li>
+    <li><a href="globals_defs_0x61.html#index_a"><span>a</span></a></li>
+    <li><a href="globals_defs_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="globals_defs_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="globals_defs_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="globals_defs_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="globals_defs_0x67.html#index_g"><span>g</span></a></li>
+    <li id="current"><a href="globals_defs_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="globals_defs_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="globals_defs_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="globals_defs_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="globals_defs_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="globals_defs_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="globals_defs_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="globals_defs_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="globals_defs_0x76.html#index_v"><span>v</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_h">- h -</a></h3><ul>
+<li>HS_HOST_DELAY
+: <a class="el" href="dwc__otg__hcd__queue_8c.html#2a974c684e456c20cc2d9bceb2e71a11">dwc_otg_hcd_queue.c</a><li>HUB_LS_SETUP
+: <a class="el" href="dwc__otg__hcd__queue_8c.html#d596163a6f24db7fb4ee092a933e03a2">dwc_otg_hcd_queue.c</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x69.html b/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x69.html
new file mode 100644
index 000000000000..bf04bb8059ad
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x69.html
@@ -0,0 +1,62 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html"><span>All</span></a></li>
+    <li><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li id="current"><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals_defs.html#index__"><span>_</span></a></li>
+    <li><a href="globals_defs_0x61.html#index_a"><span>a</span></a></li>
+    <li><a href="globals_defs_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="globals_defs_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="globals_defs_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="globals_defs_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="globals_defs_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="globals_defs_0x68.html#index_h"><span>h</span></a></li>
+    <li id="current"><a href="globals_defs_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="globals_defs_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="globals_defs_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="globals_defs_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="globals_defs_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="globals_defs_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="globals_defs_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="globals_defs_0x76.html#index_v"><span>v</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_i">- i -</a></h3><ul>
+<li>ISOC_URB_GIVEBACK_ASAP
+: <a class="el" href="dwc__otg__hcd__ddma_8c.html#7aed1ace42f0421b376041d8831c9a74">dwc_otg_hcd_ddma.c</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:50 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x6d.html b/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x6d.html
new file mode 100644
index 000000000000..140812f099ec
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x6d.html
@@ -0,0 +1,76 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html"><span>All</span></a></li>
+    <li><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li id="current"><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals_defs.html#index__"><span>_</span></a></li>
+    <li><a href="globals_defs_0x61.html#index_a"><span>a</span></a></li>
+    <li><a href="globals_defs_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="globals_defs_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="globals_defs_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="globals_defs_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="globals_defs_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="globals_defs_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="globals_defs_0x69.html#index_i"><span>i</span></a></li>
+    <li id="current"><a href="globals_defs_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="globals_defs_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="globals_defs_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="globals_defs_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="globals_defs_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="globals_defs_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="globals_defs_0x76.html#index_v"><span>v</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_m">- m -</a></h3><ul>
+<li>max
+: <a class="el" href="dwc__otg__cfi_8h.html#4755d18ce5205f644e5cd02db7f4ada5">dwc_otg_cfi.h</a><li>MAX_DMA_DESC_CNT
+: <a class="el" href="dwc__otg__pcd_8h.html#a1c5dc8973b5c039fd77b1e250ce29e2">dwc_otg_pcd.h</a><li>MAX_DMA_DESC_NUM_GENERIC
+: <a class="el" href="dwc__otg__regs_8h.html#7f241a3ed7bd5c0d4f1a496c77cbc225">dwc_otg_regs.h</a><li>MAX_DMA_DESC_NUM_HS_ISOC
+: <a class="el" href="dwc__otg__regs_8h.html#b190810b3017403bd58b6346aad4e4ed">dwc_otg_regs.h</a><li>MAX_DMA_DESC_SIZE
+: <a class="el" href="dwc__otg__regs_8h.html#000f3273fb3033d587107e7eff3c1ff6">dwc_otg_regs.h</a><li>MAX_EP0_SIZE
+: <a class="el" href="dwc__otg__pcd__if_8h.html#8fbbba66f80923843e99def6064a570f">dwc_otg_pcd_if.h</a><li>MAX_EPS_CHANNELS
+: <a class="el" href="dwc__otg__core__if_8h.html#bfb88b45545f7685f668ac2f545674ec">dwc_otg_core_if.h</a><li>MAX_FRLIST_EN_NUM
+: <a class="el" href="dwc__otg__regs_8h.html#ff2c2ac58a30e050d647d0f9a256d0bd">dwc_otg_regs.h</a><li>MAX_ISOC_XFER_SIZE_FS
+: <a class="el" href="dwc__otg__hcd__ddma_8c.html#cf56bce31ec5dfcc2a36047c0c648784">dwc_otg_hcd_ddma.c</a><li>MAX_ISOC_XFER_SIZE_HS
+: <a class="el" href="dwc__otg__hcd__ddma_8c.html#06012eeeca2d17ee7ea304b381928c4a">dwc_otg_hcd_ddma.c</a><li>MAX_PACKET_SIZE
+: <a class="el" href="dwc__otg__pcd__if_8h.html#cf2c48a3393f5ae43e8d88d01c2d204a">dwc_otg_pcd_if.h</a><li>MAX_PERIO_FIFOS
+: <a class="el" href="dwc__otg__core__if_8h.html#13bb22067644d357537c2905fe5ffb8c">dwc_otg_core_if.h</a><li>MAX_TX_FIFOS
+: <a class="el" href="dwc__otg__core__if_8h.html#050db6129005b993e573311dc42bc1a8">dwc_otg_core_if.h</a><li>min
+: <a class="el" href="dwc__otg__cfi_8h.html#7c9949b9e692a8360832aedfa1843657">dwc_otg_cfi.h</a><li>MSEC_PER_JIFFIE
+: <a class="el" href="dwc__otg__attr_8c.html#4e04f10b5ae5b78f1bc8b3c2e8af8f92">dwc_otg_attr.c</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:50 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x6e.html b/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x6e.html
new file mode 100644
index 000000000000..0413b016eeef
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x6e.html
@@ -0,0 +1,62 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html"><span>All</span></a></li>
+    <li><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li id="current"><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals_defs.html#index__"><span>_</span></a></li>
+    <li><a href="globals_defs_0x61.html#index_a"><span>a</span></a></li>
+    <li><a href="globals_defs_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="globals_defs_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="globals_defs_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="globals_defs_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="globals_defs_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="globals_defs_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="globals_defs_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="globals_defs_0x6d.html#index_m"><span>m</span></a></li>
+    <li id="current"><a href="globals_defs_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="globals_defs_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="globals_defs_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="globals_defs_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="globals_defs_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="globals_defs_0x76.html#index_v"><span>v</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_n">- n -</a></h3><ul>
+<li>NS_TO_US
+: <a class="el" href="dwc__otg__hcd__queue_8c.html#1df143acbaa5817cd09c8cca89851747">dwc_otg_hcd_queue.c</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:50 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x6f.html b/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x6f.html
new file mode 100644
index 000000000000..d938dc81ed93
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x6f.html
@@ -0,0 +1,67 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html"><span>All</span></a></li>
+    <li><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li id="current"><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals_defs.html#index__"><span>_</span></a></li>
+    <li><a href="globals_defs_0x61.html#index_a"><span>a</span></a></li>
+    <li><a href="globals_defs_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="globals_defs_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="globals_defs_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="globals_defs_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="globals_defs_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="globals_defs_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="globals_defs_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="globals_defs_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="globals_defs_0x6e.html#index_n"><span>n</span></a></li>
+    <li id="current"><a href="globals_defs_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="globals_defs_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="globals_defs_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="globals_defs_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="globals_defs_0x76.html#index_v"><span>v</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_o">- o -</a></h3><ul>
+<li>OTG_CORE_REV_2_60a
+: <a class="el" href="dwc__otg__cil_8h.html#51536e4844fe9022b60531eebca32a26">dwc_otg_cil.h</a><li>OTG_CORE_REV_2_71a
+: <a class="el" href="dwc__otg__cil_8h.html#aac1e3cc465029aa0a2965b7c6d9fc50">dwc_otg_cil.h</a><li>OTG_CORE_REV_2_72a
+: <a class="el" href="dwc__otg__cil_8h.html#3d25615a19f95042bcc3512b4855cebe">dwc_otg_cil.h</a><li>OTG_CORE_REV_2_80a
+: <a class="el" href="dwc__otg__cil_8h.html#02c75ff58b0b88ae59c89063478648dd">dwc_otg_cil.h</a><li>OTG_CORE_REV_2_81a
+: <a class="el" href="dwc__otg__cil_8h.html#ceb592db3a34e7435e6bd9fc4cf5627c">dwc_otg_cil.h</a><li>OTG_CORE_REV_2_90a
+: <a class="el" href="dwc__otg__cil_8h.html#c2f4aa7b1cfc164330925404c5029724">dwc_otg_cil.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:50 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x72.html b/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x72.html
new file mode 100644
index 000000000000..84a22460d842
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x72.html
@@ -0,0 +1,66 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html"><span>All</span></a></li>
+    <li><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li id="current"><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals_defs.html#index__"><span>_</span></a></li>
+    <li><a href="globals_defs_0x61.html#index_a"><span>a</span></a></li>
+    <li><a href="globals_defs_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="globals_defs_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="globals_defs_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="globals_defs_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="globals_defs_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="globals_defs_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="globals_defs_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="globals_defs_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="globals_defs_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="globals_defs_0x6f.html#index_o"><span>o</span></a></li>
+    <li id="current"><a href="globals_defs_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="globals_defs_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="globals_defs_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="globals_defs_0x76.html#index_v"><span>v</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_r">- r -</a></h3><ul>
+<li>RTS_BUFERR
+: <a class="el" href="dwc__otg__regs_8h.html#55b69fa65e7d41448646c88fc0642408">dwc_otg_regs.h</a><li>RTS_BUFFLUSH
+: <a class="el" href="dwc__otg__regs_8h.html#46f9d43df5fef233f4f5415d4719c1da">dwc_otg_regs.h</a><li>RTS_RESERVED
+: <a class="el" href="dwc__otg__regs_8h.html#1fa264096eca908e709d19b87a53f13f">dwc_otg_regs.h</a><li>RTS_SUCCESS
+: <a class="el" href="dwc__otg__regs_8h.html#cc9b21a293ad5a9103a64d76314a052e">dwc_otg_regs.h</a><li>RW_REG_COUNT
+: <a class="el" href="dwc__otg__attr_8c.html#5f954c85228b04a896cab754ab56358e">dwc_otg_attr.c</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:50 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x73.html b/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x73.html
new file mode 100644
index 000000000000..402040a76f0b
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x73.html
@@ -0,0 +1,63 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html"><span>All</span></a></li>
+    <li><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li id="current"><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals_defs.html#index__"><span>_</span></a></li>
+    <li><a href="globals_defs_0x61.html#index_a"><span>a</span></a></li>
+    <li><a href="globals_defs_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="globals_defs_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="globals_defs_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="globals_defs_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="globals_defs_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="globals_defs_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="globals_defs_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="globals_defs_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="globals_defs_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="globals_defs_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="globals_defs_0x72.html#index_r"><span>r</span></a></li>
+    <li id="current"><a href="globals_defs_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="globals_defs_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="globals_defs_0x76.html#index_v"><span>v</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_s">- s -</a></h3><ul>
+<li>S3C2410X_CLEAR_EINTPEND
+: <a class="el" href="dwc__otg__driver_8h.html#3af7bafbb69f04a0fd36a27fae7e8497">dwc_otg_driver.h</a><li>SCHEDULE_SLOP
+: <a class="el" href="dwc__otg__hcd__queue_8c.html#86d31a59a5f7c095cd183a06edeed5e1">dwc_otg_hcd_queue.c</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:50 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x75.html b/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x75.html
new file mode 100644
index 000000000000..6f98f7c21a97
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x75.html
@@ -0,0 +1,64 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html"><span>All</span></a></li>
+    <li><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li id="current"><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals_defs.html#index__"><span>_</span></a></li>
+    <li><a href="globals_defs_0x61.html#index_a"><span>a</span></a></li>
+    <li><a href="globals_defs_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="globals_defs_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="globals_defs_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="globals_defs_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="globals_defs_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="globals_defs_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="globals_defs_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="globals_defs_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="globals_defs_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="globals_defs_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="globals_defs_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="globals_defs_0x73.html#index_s"><span>s</span></a></li>
+    <li id="current"><a href="globals_defs_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="globals_defs_0x76.html#index_v"><span>v</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_u">- u -</a></h3><ul>
+<li>URB_GIVEBACK_ASAP
+: <a class="el" href="dwc__otg__hcd__if_8h.html#973a9deb7ee08e99abf7cb7adf6a5c72">dwc_otg_hcd_if.h</a><li>URB_SEND_ZERO_PACKET
+: <a class="el" href="dwc__otg__hcd__if_8h.html#14e576ea3b30c038f925e3e6c80c64fe">dwc_otg_hcd_if.h</a><li>USB_DWC
+: <a class="el" href="dwc__otg__dbg_8h.html#c1cdef6b622b17c7bb2d2574c6b66e0c">dwc_otg_dbg.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:50 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x76.html b/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x76.html
new file mode 100644
index 000000000000..013c59a78f99
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x76.html
@@ -0,0 +1,68 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html"><span>All</span></a></li>
+    <li><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li id="current"><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals_defs.html#index__"><span>_</span></a></li>
+    <li><a href="globals_defs_0x61.html#index_a"><span>a</span></a></li>
+    <li><a href="globals_defs_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="globals_defs_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="globals_defs_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="globals_defs_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="globals_defs_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="globals_defs_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="globals_defs_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="globals_defs_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="globals_defs_0x6e.html#index_n"><span>n</span></a></li>
+    <li><a href="globals_defs_0x6f.html#index_o"><span>o</span></a></li>
+    <li><a href="globals_defs_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="globals_defs_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="globals_defs_0x75.html#index_u"><span>u</span></a></li>
+    <li id="current"><a href="globals_defs_0x76.html#index_v"><span>v</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_v">- v -</a></h3><ul>
+<li>VEN_CORE_ACTIVATE_FEATURES
+: <a class="el" href="dwc__cfi__common_8h.html#1d1302d0d167f7c9580878fbfff847d4">dwc_cfi_common.h</a><li>VEN_CORE_GET_FEATURE
+: <a class="el" href="dwc__cfi__common_8h.html#22bf207e476d086391240b18aacc0314">dwc_cfi_common.h</a><li>VEN_CORE_GET_FEATURES
+: <a class="el" href="dwc__cfi__common_8h.html#b206fe3fb25aa96547a4bc0e47a864c6">dwc_cfi_common.h</a><li>VEN_CORE_READ_REGISTER
+: <a class="el" href="dwc__cfi__common_8h.html#8d4bf92524d3e5fd4b4b060fc1269ec6">dwc_cfi_common.h</a><li>VEN_CORE_RESET_FEATURES
+: <a class="el" href="dwc__cfi__common_8h.html#f7551c9e324871e8258dacc4f4467846">dwc_cfi_common.h</a><li>VEN_CORE_SET_FEATURE
+: <a class="el" href="dwc__cfi__common_8h.html#ee7fb610a7fb2437df3425e2330e9d39">dwc_cfi_common.h</a><li>VEN_CORE_WRITE_REGISTER
+: <a class="el" href="dwc__cfi__common_8h.html#d132d545f74a408b62d44a34ba51426c">dwc_cfi_common.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:50 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_enum.html b/drivers/usb/host/dwc_otg/doc/html/globals_enum.html
new file mode 100644
index 000000000000..6ae2433e6eec
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_enum.html
@@ -0,0 +1,44 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html"><span>All</span></a></li>
+    <li><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li id="current"><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+&nbsp;
+<p>
+<ul>
+<li>dwc_otg_control_phase
+: <a class="el" href="dwc__otg__hcd_8h.html#4ec934997af9e24c8eede108d399c140">dwc_otg_hcd.h</a><li>dwc_otg_halt_status
+: <a class="el" href="dwc__otg__cil_8h.html#5535f5641e4293d3ecca5c863863d60d">dwc_otg_cil.h</a><li>dwc_otg_lx_state
+: <a class="el" href="dwc__otg__cil_8h.html#8442e49b7c783099ac17bda4f8b3bc3c">dwc_otg_cil.h</a><li>dwc_otg_transaction_type
+: <a class="el" href="dwc__otg__hcd_8h.html#0ab043da15526ddcd3f3698505d52d83">dwc_otg_hcd.h</a><li>ep0_state
+: <a class="el" href="dwc__otg__pcd_8h.html#f286abbd9be76db05fee7aebfeb61865">dwc_otg_pcd.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_eval.html b/drivers/usb/host/dwc_otg/doc/html/globals_eval.html
new file mode 100644
index 000000000000..1778d4e69d48
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_eval.html
@@ -0,0 +1,43 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html"><span>All</span></a></li>
+    <li><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li id="current"><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+&nbsp;
+<p>
+<ul>
+<li>DWC_OTG_L0
+: <a class="el" href="dwc__otg__cil_8h.html#8442e49b7c783099ac17bda4f8b3bc3c9743a36d9b0b8c66a11a0714fdd27fb5">dwc_otg_cil.h</a><li>DWC_OTG_L1
+: <a class="el" href="dwc__otg__cil_8h.html#8442e49b7c783099ac17bda4f8b3bc3cf5b112742a8103f3489107ad26c0ff58">dwc_otg_cil.h</a><li>DWC_OTG_L2
+: <a class="el" href="dwc__otg__cil_8h.html#8442e49b7c783099ac17bda4f8b3bc3cd1fadb6fa31de73e8176316a0e0ba905">dwc_otg_cil.h</a><li>DWC_OTG_L3
+: <a class="el" href="dwc__otg__cil_8h.html#8442e49b7c783099ac17bda4f8b3bc3c86715d528a59b114b95aaafa8f2142f6">dwc_otg_cil.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_func.html b/drivers/usb/host/dwc_otg/doc/html/globals_func.html
new file mode 100644
index 000000000000..8e2b1ee72399
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_func.html
@@ -0,0 +1,77 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html"><span>All</span></a></li>
+    <li id="current"><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li id="current"><a href="globals_func.html#index__"><span>_</span></a></li>
+    <li><a href="globals_func_0x61.html#index_a"><span>a</span></a></li>
+    <li><a href="globals_func_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="globals_func_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="globals_func_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="globals_func_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="globals_func_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="globals_func_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="globals_func_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="globals_func_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="globals_func_0x6b.html#index_k"><span>k</span></a></li>
+    <li><a href="globals_func_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="globals_func_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="globals_func_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="globals_func_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="globals_func_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="globals_func_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="globals_func_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="globals_func_0x77.html#index_w"><span>w</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index__">- _ -</a></h3><ul>
+<li>_complete()
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#e1d629bc692aa1e42584459867b1aeaa">dwc_otg_pcd_linux.c</a>, <a class="el" href="dwc__otg__hcd__linux_8c.html#a0d18986574c384e98aa280e0475a9aa">dwc_otg_hcd_linux.c</a><li>_connect()
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#c7c1c4f8fe8e62f1d9e6f75de5563658">dwc_otg_pcd_linux.c</a><li>_disconnect()
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#682f9829330d06521a5d4c00702e4580">dwc_otg_pcd_linux.c</a>, <a class="el" href="dwc__otg__hcd__linux_8c.html#8011f9b662a7f4182e762de616bbc95e">dwc_otg_hcd_linux.c</a><li>_get_b_hnp_enable()
+: <a class="el" href="dwc__otg__hcd__linux_8c.html#578b76a201e8e722e31afdcd2c35dac9">dwc_otg_hcd_linux.c</a><li>_hnp_changed()
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#9e8595e1d36e6b1ffbc27c4862957a08">dwc_otg_pcd_linux.c</a><li>_hub_info()
+: <a class="el" href="dwc__otg__hcd__linux_8c.html#f4fe5a6082e7cce809f3e2a4cb71a7e4">dwc_otg_hcd_linux.c</a><li>_isoc_complete()
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#737e47386e05da8cf6cbf85a289f5454">dwc_otg_pcd_linux.c</a><li>_reset()
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#208cf9e0227e5f81e015ed3ac5bacec4">dwc_otg_pcd_linux.c</a><li>_resume()
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#86cdfe71d125da339e17e52049fc5ea0">dwc_otg_pcd_linux.c</a><li>_setup()
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#4a1481839b3d869d882f984a6c6ed9e5">dwc_otg_pcd_linux.c</a><li>_speed()
+: <a class="el" href="dwc__otg__hcd__linux_8c.html#22cff3e20b45ec02e81e54a1adacfa20">dwc_otg_hcd_linux.c</a><li>_start()
+: <a class="el" href="dwc__otg__hcd__linux_8c.html#e11ebd665a86e6ec3fd661965acca90e">dwc_otg_hcd_linux.c</a><li>_suspend()
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#7f479ecaee0801b55b4f0bd0f36f8b67">dwc_otg_pcd_linux.c</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_func_0x61.html b/drivers/usb/host/dwc_otg/doc/html/globals_func_0x61.html
new file mode 100644
index 000000000000..1d512d609224
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_func_0x61.html
@@ -0,0 +1,70 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html"><span>All</span></a></li>
+    <li id="current"><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals_func.html#index__"><span>_</span></a></li>
+    <li id="current"><a href="globals_func_0x61.html#index_a"><span>a</span></a></li>
+    <li><a href="globals_func_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="globals_func_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="globals_func_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="globals_func_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="globals_func_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="globals_func_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="globals_func_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="globals_func_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="globals_func_0x6b.html#index_k"><span>k</span></a></li>
+    <li><a href="globals_func_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="globals_func_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="globals_func_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="globals_func_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="globals_func_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="globals_func_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="globals_func_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="globals_func_0x77.html#index_w"><span>w</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_a">- a -</a></h3><ul>
+<li>alloc_iso_request()
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#94fd50b5e9d41d1d38a503d819fc07c4">dwc_otg_pcd_linux.c</a><li>alloc_wrapper()
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#e0f94c48914d5f911f7623a53c5385a9">dwc_otg_pcd_linux.c</a><li>allocate_bus_bandwidth()
+: <a class="el" href="dwc__otg__hcd__linux_8c.html#e270a6a091a674ccf6f390fdcf746b87">dwc_otg_hcd_linux.c</a><li>assign_and_init_hc()
+: <a class="el" href="dwc__otg__hcd_8c.html#08cefee3729196462fe6a7608046652c">dwc_otg_hcd.c</a><li>assign_perio_tx_fifo()
+: <a class="el" href="dwc__otg__pcd_8c.html#1df421d3a1449ec3a927d0a006c57c38">dwc_otg_pcd.c</a><li>assign_tx_fifo()
+: <a class="el" href="dwc__otg__pcd_8c.html#5b3f2d055af51e556be50f3ada673e4a">dwc_otg_pcd.c</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_func_0x62.html b/drivers/usb/host/dwc_otg/doc/html/globals_func_0x62.html
new file mode 100644
index 000000000000..59786f6bd95e
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_func_0x62.html
@@ -0,0 +1,68 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html"><span>All</span></a></li>
+    <li id="current"><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals_func.html#index__"><span>_</span></a></li>
+    <li><a href="globals_func_0x61.html#index_a"><span>a</span></a></li>
+    <li id="current"><a href="globals_func_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="globals_func_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="globals_func_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="globals_func_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="globals_func_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="globals_func_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="globals_func_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="globals_func_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="globals_func_0x6b.html#index_k"><span>k</span></a></li>
+    <li><a href="globals_func_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="globals_func_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="globals_func_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="globals_func_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="globals_func_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="globals_func_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="globals_func_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="globals_func_0x77.html#index_w"><span>w</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_b">- b -</a></h3><ul>
+<li>buspower_show()
+: <a class="el" href="dwc__otg__attr_8c.html#6979f4909cde868d800dba13ef95aa8c">dwc_otg_attr.c</a><li>buspower_store()
+: <a class="el" href="dwc__otg__attr_8c.html#4514a396df18dae15f7f03f640f52ac7">dwc_otg_attr.c</a><li>bussuspend_show()
+: <a class="el" href="dwc__otg__attr_8c.html#ae1f7e3a17c5a0bcc5a93096aeb902d2">dwc_otg_attr.c</a><li>bussuspend_store()
+: <a class="el" href="dwc__otg__attr_8c.html#f218d7c4c611b97dfaa1e03ac2daa353">dwc_otg_attr.c</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_func_0x63.html b/drivers/usb/host/dwc_otg/doc/html/globals_func_0x63.html
new file mode 100644
index 000000000000..21e3050cee1f
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_func_0x63.html
@@ -0,0 +1,77 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html"><span>All</span></a></li>
+    <li id="current"><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals_func.html#index__"><span>_</span></a></li>
+    <li><a href="globals_func_0x61.html#index_a"><span>a</span></a></li>
+    <li><a href="globals_func_0x62.html#index_b"><span>b</span></a></li>
+    <li id="current"><a href="globals_func_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="globals_func_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="globals_func_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="globals_func_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="globals_func_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="globals_func_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="globals_func_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="globals_func_0x6b.html#index_k"><span>k</span></a></li>
+    <li><a href="globals_func_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="globals_func_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="globals_func_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="globals_func_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="globals_func_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="globals_func_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="globals_func_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="globals_func_0x77.html#index_w"><span>w</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_c">- c -</a></h3><ul>
+<li>calc_bus_time()
+: <a class="el" href="dwc__otg__hcd__queue_8c.html#49a9d4aa15e01fc07d68826bd05c0f4d">dwc_otg_hcd_queue.c</a><li>calc_num_in_eps()
+: <a class="el" href="dwc__otg__cil_8c.html#1cdde3ab3e53e93c5a42feed628aaf7d">dwc_otg_cil.c</a><li>calc_num_out_eps()
+: <a class="el" href="dwc__otg__cil_8c.html#e923d8ecfaf2957ef7d0a1379e0b5101">dwc_otg_cil.c</a><li>calc_starting_frame()
+: <a class="el" href="dwc__otg__hcd__ddma_8c.html#f9c8d06c646b374cf34925e659142709">dwc_otg_hcd_ddma.c</a><li>cfiw_ep_alloc_buffer()
+: <a class="el" href="dwc__otg__pcd__if_8h.html#3951259aaef3df35d1955076a907f095">dwc_otg_pcd_if.h</a>, <a class="el" href="dwc__otg__pcd_8c.html#3951259aaef3df35d1955076a907f095">dwc_otg_pcd.c</a><li>check_max_xfer_size()
+: <a class="el" href="dwc__otg__hcd__queue_8c.html#4d3ef86a879b015bea87b02118aae4c9">dwc_otg_hcd_queue.c</a><li>check_periodic_bandwidth()
+: <a class="el" href="dwc__otg__hcd__queue_8c.html#fee6145ab0fe7782c587916160dedb11">dwc_otg_hcd_queue.c</a><li>complete_ep()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#c77f277130ba55b19100bde598da7d85">dwc_otg_pcd_intr.c</a><li>complete_iso_ep()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#05965765a43225780ae08f2c3928f782">dwc_otg_pcd_intr.c</a><li>complete_isoc_xfer_ddma()
+: <a class="el" href="dwc__otg__hcd__ddma_8c.html#aad342d0a6056bbc5645809f24ac8507">dwc_otg_hcd_ddma.c</a><li>complete_non_isoc_xfer_ddma()
+: <a class="el" href="dwc__otg__hcd__ddma_8c.html#3551cf23294204324754fca2da9a99d1">dwc_otg_hcd_ddma.c</a><li>complete_non_periodic_xfer()
+: <a class="el" href="dwc__otg__hcd__intr_8c.html#2fa47944efef508dddcab00b0050ef0a">dwc_otg_hcd_intr.c</a><li>complete_periodic_xfer()
+: <a class="el" href="dwc__otg__hcd__intr_8c.html#a0fa0d4fa5f0af15860d685bb8fe3e50">dwc_otg_hcd_intr.c</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_func_0x64.html b/drivers/usb/host/dwc_otg/doc/html/globals_func_0x64.html
new file mode 100644
index 000000000000..b9c4b1c839bd
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_func_0x64.html
@@ -0,0 +1,427 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html"><span>All</span></a></li>
+    <li id="current"><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals_func.html#index__"><span>_</span></a></li>
+    <li><a href="globals_func_0x61.html#index_a"><span>a</span></a></li>
+    <li><a href="globals_func_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="globals_func_0x63.html#index_c"><span>c</span></a></li>
+    <li id="current"><a href="globals_func_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="globals_func_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="globals_func_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="globals_func_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="globals_func_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="globals_func_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="globals_func_0x6b.html#index_k"><span>k</span></a></li>
+    <li><a href="globals_func_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="globals_func_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="globals_func_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="globals_func_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="globals_func_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="globals_func_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="globals_func_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="globals_func_0x77.html#index_w"><span>w</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_d">- d -</a></h3><ul>
+<li>dbg_level_show()
+: <a class="el" href="dwc__otg__driver_8c.html#1e2b7516063b70cc1eaecc8d286b0689">dwc_otg_driver.c</a><li>dbg_level_store()
+: <a class="el" href="dwc__otg__driver_8c.html#e886456741506f66ce4adc5b843dc055">dwc_otg_driver.c</a><li>deactivate_qh()
+: <a class="el" href="dwc__otg__hcd__intr_8c.html#57e9a29ec2dc8cd8d119acade0ae4ff1">dwc_otg_hcd_intr.c</a><li>del_timers()
+: <a class="el" href="dwc__otg__hcd_8c.html#939a9c8afc75cbe47625e392a7c66a1a">dwc_otg_hcd.c</a><li>del_xfer_timers()
+: <a class="el" href="dwc__otg__hcd_8c.html#17f7272e6a2fe4515b3160ad4694ea55">dwc_otg_hcd.c</a><li>desc_list_alloc()
+: <a class="el" href="dwc__otg__hcd__ddma_8c.html#12375cf094e35d9be3b78da6cf621d01">dwc_otg_hcd_ddma.c</a><li>desc_list_free()
+: <a class="el" href="dwc__otg__hcd__ddma_8c.html#c062f46629017bdeeebaf90aa65f610b">dwc_otg_hcd_ddma.c</a><li>deschedule_periodic()
+: <a class="el" href="dwc__otg__hcd__queue_8c.html#97dd97603c01db8288a735910b3b24a7">dwc_otg_hcd_queue.c</a><li>desclist_idx_dec()
+: <a class="el" href="dwc__otg__hcd__ddma_8c.html#13186d2e949bb38420a7a19a4530a5ad">dwc_otg_hcd_ddma.c</a><li>desclist_idx_inc()
+: <a class="el" href="dwc__otg__hcd__ddma_8c.html#c4d25855998839163827c8062bd6fb8b">dwc_otg_hcd_ddma.c</a><li>do_clear_feature()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#2198ea3f0136465fa325a189d4ba5140">dwc_otg_pcd_intr.c</a><li>do_gadget_setup()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#6c417c7d86bc9540e13ca4faeaf3dfbf">dwc_otg_pcd_intr.c</a><li>do_get_status()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#f449add2b4e8de7ced10fd1bb4c5b748">dwc_otg_pcd_intr.c</a><li>do_set_address()
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+: <a class="el" href="dwc__otg__core__if_8h.html#c072cef5b7d3c5566ad3be010c6d49ed">dwc_otg_core_if.h</a>, <a class="el" href="dwc__otg__cil_8c.html#c072cef5b7d3c5566ad3be010c6d49ed">dwc_otg_cil.c</a><li>dwc_otg_set_srpcapable()
+: <a class="el" href="dwc__otg__core__if_8h.html#e75a4faa49ac70c19e9bc8a039d6e37f">dwc_otg_core_if.h</a>, <a class="el" href="dwc__otg__cil_8c.html#e75a4faa49ac70c19e9bc8a039d6e37f">dwc_otg_cil.c</a><li>dwc_otg_set_uninitialized()
+: <a class="el" href="dwc__otg__cil_8c.html#322ac38f3a85f48410ed6e91adce3955">dwc_otg_cil.c</a><li>dwc_otg_setup_params()
+: <a class="el" href="dwc__otg__cil_8c.html#2be12d7b5990c6eaac2f1a5fb688f2f8">dwc_otg_cil.c</a><li>dwc_urb_to_endpoint()
+: <a class="el" href="dwc__otg__hcd__linux_8c.html#99c594c1e3af2fa78b09c914cb334611">dwc_otg_hcd_linux.c</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_func_0x65.html b/drivers/usb/host/dwc_otg/doc/html/globals_func_0x65.html
new file mode 100644
index 000000000000..5e5869d5d246
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_func_0x65.html
@@ -0,0 +1,73 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html"><span>All</span></a></li>
+    <li id="current"><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals_func.html#index__"><span>_</span></a></li>
+    <li><a href="globals_func_0x61.html#index_a"><span>a</span></a></li>
+    <li><a href="globals_func_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="globals_func_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="globals_func_0x64.html#index_d"><span>d</span></a></li>
+    <li id="current"><a href="globals_func_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="globals_func_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="globals_func_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="globals_func_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="globals_func_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="globals_func_0x6b.html#index_k"><span>k</span></a></li>
+    <li><a href="globals_func_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="globals_func_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="globals_func_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="globals_func_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="globals_func_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="globals_func_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="globals_func_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="globals_func_0x77.html#index_w"><span>w</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_e">- e -</a></h3><ul>
+<li>endpoint_disable()
+: <a class="el" href="dwc__otg__hcd__linux_8c.html#0aefc084c4c334dac85c95a43e8942c6">dwc_otg_hcd_linux.c</a><li>ep0_complete_request()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#f64bfae20151c51d3b0a6d4e523f356e">dwc_otg_pcd_intr.c</a><li>ep0_do_stall()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#325b13e198ff56e9de2600ac7f28a57d">dwc_otg_pcd_intr.c</a><li>ep0_out_start()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#726b57833bb3ae4648ce7e7a7e125bf7">dwc_otg_pcd_intr.c</a><li>ep_dequeue()
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#e2e4913a926acc55f4e57c3ff8f97c08">dwc_otg_pcd_linux.c</a><li>ep_disable()
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#1708514cb93c5da43a8f634de1c0f5e7">dwc_otg_pcd_linux.c</a><li>ep_enable()
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#9761890d7f741f9421d82254c9846f31">dwc_otg_pcd_linux.c</a><li>ep_halt()
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#8ee99e0e68c8e50e94c242805b158cb2">dwc_otg_pcd_linux.c</a><li>ep_queue()
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#f97bea831037135af73c3c202e3e01dc">dwc_otg_pcd_linux.c</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_func_0x66.html b/drivers/usb/host/dwc_otg/doc/html/globals_func_0x66.html
new file mode 100644
index 000000000000..0dd4c50199c7
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_func_0x66.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html"><span>All</span></a></li>
+    <li id="current"><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals_func.html#index__"><span>_</span></a></li>
+    <li><a href="globals_func_0x61.html#index_a"><span>a</span></a></li>
+    <li><a href="globals_func_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="globals_func_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="globals_func_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="globals_func_0x65.html#index_e"><span>e</span></a></li>
+    <li id="current"><a href="globals_func_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="globals_func_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="globals_func_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="globals_func_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="globals_func_0x6b.html#index_k"><span>k</span></a></li>
+    <li><a href="globals_func_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="globals_func_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="globals_func_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="globals_func_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="globals_func_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="globals_func_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="globals_func_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="globals_func_0x77.html#index_w"><span>w</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_f">- f -</a></h3><ul>
+<li>frame_incr_val()
+: <a class="el" href="dwc__otg__hcd__ddma_8c.html#357d9fe0cd782a9c88e79f47c3b58384">dwc_otg_hcd_ddma.c</a><li>frame_list_alloc()
+: <a class="el" href="dwc__otg__hcd__ddma_8c.html#35be74597b6abe7a7d077c2c00d64dc2">dwc_otg_hcd_ddma.c</a><li>frame_list_free()
+: <a class="el" href="dwc__otg__hcd__ddma_8c.html#01991072b147e11d3b7350a2ee9ee920">dwc_otg_hcd_ddma.c</a><li>frame_list_idx()
+: <a class="el" href="dwc__otg__hcd__ddma_8c.html#cc7af33964cf891f1448376c2a57b309">dwc_otg_hcd_ddma.c</a><li>frame_to_desc_idx()
+: <a class="el" href="dwc__otg__hcd__ddma_8c.html#42ed718bf245372d90fa8f92fcb69a99">dwc_otg_hcd_ddma.c</a><li>free_bus_bandwidth()
+: <a class="el" href="dwc__otg__hcd__linux_8c.html#53fcd6fb7b833323112e8856070e88d8">dwc_otg_hcd_linux.c</a><li>free_iso_request()
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#a9a7bc869bc7f3d05804059f3277d11a">dwc_otg_pcd_linux.c</a><li>free_wrapper()
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#8893dc41eae659439546d874c6e9977f">dwc_otg_pcd_linux.c</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_func_0x67.html b/drivers/usb/host/dwc_otg/doc/html/globals_func_0x67.html
new file mode 100644
index 000000000000..aeaef34e49d3
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_func_0x67.html
@@ -0,0 +1,78 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html"><span>All</span></a></li>
+    <li id="current"><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals_func.html#index__"><span>_</span></a></li>
+    <li><a href="globals_func_0x61.html#index_a"><span>a</span></a></li>
+    <li><a href="globals_func_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="globals_func_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="globals_func_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="globals_func_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="globals_func_0x66.html#index_f"><span>f</span></a></li>
+    <li id="current"><a href="globals_func_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="globals_func_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="globals_func_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="globals_func_0x6b.html#index_k"><span>k</span></a></li>
+    <li><a href="globals_func_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="globals_func_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="globals_func_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="globals_func_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="globals_func_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="globals_func_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="globals_func_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="globals_func_0x77.html#index_w"><span>w</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_g">- g -</a></h3><ul>
+<li>gadget_add_eps()
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#647f81bc0edc9007af3ff2ba04e884f3">dwc_otg_pcd_linux.c</a><li>get_a_alt_hnp_support()
+: <a class="el" href="dwc__otg__pcd__if_8h.html#842709a4980bc78d49726fa880922dda">dwc_otg_pcd_if.h</a>, <a class="el" href="dwc__otg__pcd_8c.html#842709a4980bc78d49726fa880922dda">dwc_otg_pcd.c</a><li>get_a_hnp_support()
+: <a class="el" href="dwc__otg__pcd__if_8h.html#69d0bb469e15cb46f00c17398f76df99">dwc_otg_pcd_if.h</a>, <a class="el" href="dwc__otg__pcd_8c.html#69d0bb469e15cb46f00c17398f76df99">dwc_otg_pcd.c</a><li>get_actual_xfer_length()
+: <a class="el" href="dwc__otg__hcd__intr_8c.html#6cdb134cbb3cdf3501ca39761137baf0">dwc_otg_hcd_intr.c</a><li>get_b_hnp_enable()
+: <a class="el" href="dwc__otg__pcd__if_8h.html#777a6a4e250add9ba5f5f5d63d854031">dwc_otg_pcd_if.h</a>, <a class="el" href="dwc__otg__pcd_8c.html#777a6a4e250add9ba5f5f5d63d854031">dwc_otg_pcd.c</a><li>get_cfi_ep_by_addr()
+: <a class="el" href="dwc__otg__cfi_8h.html#5ece1e51b8534a5cc9a7dd5115bb01ca">dwc_otg_cfi.h</a><li>get_cfi_ep_by_pcd_ep()
+: <a class="el" href="dwc__otg__cfi_8h.html#c21284d5adf03032d094a36babf9b1e5">dwc_otg_cfi.h</a><li>get_device_speed()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#6a3ddac8955990b9a63646c40c65446b">dwc_otg_pcd_intr.c</a><li>get_ep_by_addr()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#3c351d7f51d6242296d6ea3bb1a9775c">dwc_otg_pcd_intr.c</a><li>get_ep_from_handle()
+: <a class="el" href="dwc__otg__pcd_8c.html#4b46c226fa34cd7fc4ceec2c5e7f8ebe">dwc_otg_pcd.c</a><li>get_ep_of_last_in_token()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#fde237571d3aaa5d03376d3bee827075">dwc_otg_pcd_intr.c</a><li>get_frame_number()
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#7af23be44d3ad24c67cd1e22579dd90e">dwc_otg_pcd_linux.c</a>, <a class="el" href="dwc__otg__hcd__linux_8c.html#c78128edb8902dc96534c5bb253f99a3">dwc_otg_hcd_linux.c</a><li>get_in_ep()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#cc3f2f1ae0ab7d33903a1d0d9097c04e">dwc_otg_pcd_intr.c</a><li>get_out_ep()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#fbd54e53e1968d3b4798ea1b63b52f74">dwc_otg_pcd_intr.c</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_func_0x68.html b/drivers/usb/host/dwc_otg/doc/html/globals_func_0x68.html
new file mode 100644
index 000000000000..ddc79466a640
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_func_0x68.html
@@ -0,0 +1,101 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html"><span>All</span></a></li>
+    <li id="current"><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals_func.html#index__"><span>_</span></a></li>
+    <li><a href="globals_func_0x61.html#index_a"><span>a</span></a></li>
+    <li><a href="globals_func_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="globals_func_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="globals_func_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="globals_func_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="globals_func_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="globals_func_0x67.html#index_g"><span>g</span></a></li>
+    <li id="current"><a href="globals_func_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="globals_func_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="globals_func_0x6b.html#index_k"><span>k</span></a></li>
+    <li><a href="globals_func_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="globals_func_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="globals_func_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="globals_func_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="globals_func_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="globals_func_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="globals_func_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="globals_func_0x77.html#index_w"><span>w</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_h">- h -</a></h3><ul>
+<li>halt_channel()
+: <a class="el" href="dwc__otg__hcd__intr_8c.html#8b774e79e18861e9ad3ab1d0de00d47c">dwc_otg_hcd_intr.c</a><li>handle_ep0()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#4991119b51de03163a3677c36bc0ee3b">dwc_otg_pcd_intr.c</a><li>handle_hc_ack_intr()
+: <a class="el" href="dwc__otg__hcd__intr_8c.html#243b0fb4191e46127a6823c0b5e970bb">dwc_otg_hcd_intr.c</a><li>handle_hc_ahberr_intr()
+: <a class="el" href="dwc__otg__hcd__intr_8c.html#1edf7eebc0475898518e18dc12c1b4b9">dwc_otg_hcd_intr.c</a><li>handle_hc_babble_intr()
+: <a class="el" href="dwc__otg__hcd__intr_8c.html#ab5348f52aac4081a9c35d529c1fcd79">dwc_otg_hcd_intr.c</a><li>handle_hc_chhltd_intr()
+: <a class="el" href="dwc__otg__hcd__intr_8c.html#83541cd20d3297d7d7d24052834ef019">dwc_otg_hcd_intr.c</a><li>handle_hc_chhltd_intr_dma()
+: <a class="el" href="dwc__otg__hcd__intr_8c.html#d75ed153a90dbda39d4d8e6cde4358df">dwc_otg_hcd_intr.c</a><li>handle_hc_datatglerr_intr()
+: <a class="el" href="dwc__otg__hcd__intr_8c.html#f73e70f0e622267b6281e0cd6c1d89cf">dwc_otg_hcd_intr.c</a><li>handle_hc_frmovrun_intr()
+: <a class="el" href="dwc__otg__hcd__intr_8c.html#a30d61b2809dccf609bcf83cc61c9d63">dwc_otg_hcd_intr.c</a><li>handle_hc_nak_intr()
+: <a class="el" href="dwc__otg__hcd__intr_8c.html#19f718e1e8f7cded3bb7431008ee0309">dwc_otg_hcd_intr.c</a><li>handle_hc_nyet_intr()
+: <a class="el" href="dwc__otg__hcd__intr_8c.html#5093a2b94c1d5cd1988eb93d9def298f">dwc_otg_hcd_intr.c</a><li>handle_hc_stall_intr()
+: <a class="el" href="dwc__otg__hcd__intr_8c.html#e89fabf3023fa4f0279f312e5e9d4223">dwc_otg_hcd_intr.c</a><li>handle_hc_xacterr_intr()
+: <a class="el" href="dwc__otg__hcd__intr_8c.html#464af1671bd416d5db48a51fc93366ee">dwc_otg_hcd_intr.c</a><li>handle_hc_xfercomp_intr()
+: <a class="el" href="dwc__otg__hcd__intr_8c.html#e8bfcabff910322ef19eec9fc99fd097">dwc_otg_hcd_intr.c</a><li>handle_in_ep_disable_intr()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#6c9df42abc5cb6f676a44918207c91b7">dwc_otg_pcd_intr.c</a><li>handle_in_ep_nak_intr()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#273ccc8e8cdb9e2075844f2f922b53bf">dwc_otg_pcd_intr.c</a><li>handle_in_ep_timeout_intr()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#65d4f747d13e368916ee0e16d202119b">dwc_otg_pcd_intr.c</a><li>handle_iso_out_pkt_dropped()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#41cfc0d590740640795b350998bcc2c4">dwc_otg_pcd_intr.c</a><li>handle_out_ep_babble_intr()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#42aef7ea134cccf7cdb53e7e1428bc4a">dwc_otg_pcd_intr.c</a><li>handle_out_ep_nak_intr()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#252929e585c84eaf0485869cd7734244">dwc_otg_pcd_intr.c</a><li>handle_out_ep_nyet_intr()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#926d9068c1950cc406d50828e72a31db">dwc_otg_pcd_intr.c</a><li>handle_xfercomp_isoc_split_in()
+: <a class="el" href="dwc__otg__hcd__intr_8c.html#a56eb0602c101ab380581b164973fb33">dwc_otg_hcd_intr.c</a><li>hc_set_even_odd_frame()
+: <a class="el" href="dwc__otg__cil_8c.html#b2669551136671d3e4b6ad56bd947222">dwc_otg_cil.c</a><li>hcd_disconnect()
+: <a class="el" href="dwc__otg__cil__intr_8c.html#b208bc4537e7b26658edc642e407894b">dwc_otg_cil_intr.c</a><li>hcd_frrem_show()
+: <a class="el" href="dwc__otg__attr_8c.html#d1d9d9abd2011c79fe7453c20e03e31a">dwc_otg_attr.c</a><li>hcd_init()
+: <a class="el" href="dwc__otg__hcd__linux_8c.html#ab12cdf65bf4ed68545a6c17cc31269f">dwc_otg_hcd_linux.c</a>, <a class="el" href="dwc__otg__driver_8c.html#ab12cdf65bf4ed68545a6c17cc31269f">dwc_otg_driver.c</a><li>hcd_remove()
+: <a class="el" href="dwc__otg__hcd__linux_8c.html#f36193b3ff33c0473956c8a15eee4f5b">dwc_otg_hcd_linux.c</a>, <a class="el" href="dwc__otg__driver_8c.html#f36193b3ff33c0473956c8a15eee4f5b">dwc_otg_driver.c</a><li>hcd_resume()
+: <a class="el" href="dwc__otg__cil__intr_8c.html#681e193a107c04b5005500ff35c59cd5">dwc_otg_cil_intr.c</a><li>hcd_session_start()
+: <a class="el" href="dwc__otg__cil__intr_8c.html#2ccec1f0c44ae8129f3012a519ecd5eb">dwc_otg_cil_intr.c</a><li>hcd_start()
+: <a class="el" href="dwc__otg__hcd__linux_8c.html#5d7f9da64cfeb32895d6c3d1366d45cf">dwc_otg_hcd_linux.c</a>, <a class="el" href="dwc__otg__cil__intr_8c.html#fc2d933cd662b3d060747004c79203a1">dwc_otg_cil_intr.c</a><li>hcd_start_func()
+: <a class="el" href="dwc__otg__hcd_8c.html#5a7a5af3b84b4af188fa3b60058a039c">dwc_otg_hcd.c</a><li>hcd_stop()
+: <a class="el" href="dwc__otg__hcd__linux_8c.html#cbb6a9e932a0baf80d1fdb013ac5d679">dwc_otg_hcd_linux.c</a>, <a class="el" href="dwc__otg__cil__intr_8c.html#b2721d01cc389181470095955b4e0994">dwc_otg_cil_intr.c</a><li>hcd_to_dwc_otg_hcd()
+: <a class="el" href="dwc__otg__hcd__linux_8c.html#bd8c86466ccd8ff8b94867d601e66116">dwc_otg_hcd_linux.c</a><li>hcddump_show()
+: <a class="el" href="dwc__otg__attr_8c.html#e16d4439b6b733715ecc1d06ed999aa4">dwc_otg_attr.c</a><li>hnp_store()
+: <a class="el" href="dwc__otg__attr_8c.html#14b1910d541301f5456e2a15a3b4f0b0">dwc_otg_attr.c</a><li>hub_control()
+: <a class="el" href="dwc__otg__hcd__linux_8c.html#55d196cab99083dabdacdee78dc5e339">dwc_otg_hcd_linux.c</a><li>hub_status_data()
+: <a class="el" href="dwc__otg__hcd__linux_8c.html#108442f4aa4dc4663d8659241ed04e9c">dwc_otg_hcd_linux.c</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_func_0x69.html b/drivers/usb/host/dwc_otg/doc/html/globals_func_0x69.html
new file mode 100644
index 000000000000..4b5ff4a45b56
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_func_0x69.html
@@ -0,0 +1,71 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html"><span>All</span></a></li>
+    <li id="current"><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals_func.html#index__"><span>_</span></a></li>
+    <li><a href="globals_func_0x61.html#index_a"><span>a</span></a></li>
+    <li><a href="globals_func_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="globals_func_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="globals_func_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="globals_func_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="globals_func_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="globals_func_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="globals_func_0x68.html#index_h"><span>h</span></a></li>
+    <li id="current"><a href="globals_func_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="globals_func_0x6b.html#index_k"><span>k</span></a></li>
+    <li><a href="globals_func_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="globals_func_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="globals_func_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="globals_func_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="globals_func_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="globals_func_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="globals_func_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="globals_func_0x77.html#index_w"><span>w</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_i">- i -</a></h3><ul>
+<li>init_devspd()
+: <a class="el" href="dwc__otg__cil_8c.html#6ef971c486eacd419d20e1bc545f9238">dwc_otg_cil.c</a><li>init_dma_desc_chain()
+: <a class="el" href="dwc__otg__cil_8c.html#50a39773d3477ca76a71787e27400d7a">dwc_otg_cil.c</a><li>init_fslspclksel()
+: <a class="el" href="dwc__otg__cil_8c.html#4550564b18dcd56bd2c4ec1ba91c6e13">dwc_otg_cil.c</a><li>init_isoc_dma_desc()
+: <a class="el" href="dwc__otg__hcd__ddma_8c.html#f2bad2e76275e230f83be94c21a0bd75">dwc_otg_hcd_ddma.c</a><li>init_non_isoc_dma_desc()
+: <a class="el" href="dwc__otg__hcd__ddma_8c.html#f3630ce7f8926de36873d78a1748134f">dwc_otg_hcd_ddma.c</a><li>iso_ep_start()
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#eb3df484c8c344613a2a9b23e24036a8">dwc_otg_pcd_linux.c</a><li>iso_ep_stop()
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#cecdcaa060d30ac09414419545a5d1c6">dwc_otg_pcd_linux.c</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_func_0x6b.html b/drivers/usb/host/dwc_otg/doc/html/globals_func_0x6b.html
new file mode 100644
index 000000000000..854a72c4f615
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_func_0x6b.html
@@ -0,0 +1,66 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html"><span>All</span></a></li>
+    <li id="current"><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals_func.html#index__"><span>_</span></a></li>
+    <li><a href="globals_func_0x61.html#index_a"><span>a</span></a></li>
+    <li><a href="globals_func_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="globals_func_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="globals_func_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="globals_func_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="globals_func_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="globals_func_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="globals_func_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="globals_func_0x69.html#index_i"><span>i</span></a></li>
+    <li id="current"><a href="globals_func_0x6b.html#index_k"><span>k</span></a></li>
+    <li><a href="globals_func_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="globals_func_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="globals_func_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="globals_func_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="globals_func_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="globals_func_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="globals_func_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="globals_func_0x77.html#index_w"><span>w</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_k">- k -</a></h3><ul>
+<li>kill_all_urbs()
+: <a class="el" href="dwc__otg__hcd_8c.html#63f169b583c3818268def3614ac2fe0a">dwc_otg_hcd.c</a><li>kill_urbs_in_qh_list()
+: <a class="el" href="dwc__otg__hcd_8c.html#8fd9263ed86449c5440edd834cb4d766">dwc_otg_hcd.c</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_func_0x6d.html b/drivers/usb/host/dwc_otg/doc/html/globals_func_0x6d.html
new file mode 100644
index 000000000000..e45997a4161c
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_func_0x6d.html
@@ -0,0 +1,66 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html"><span>All</span></a></li>
+    <li id="current"><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals_func.html#index__"><span>_</span></a></li>
+    <li><a href="globals_func_0x61.html#index_a"><span>a</span></a></li>
+    <li><a href="globals_func_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="globals_func_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="globals_func_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="globals_func_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="globals_func_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="globals_func_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="globals_func_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="globals_func_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="globals_func_0x6b.html#index_k"><span>k</span></a></li>
+    <li id="current"><a href="globals_func_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="globals_func_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="globals_func_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="globals_func_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="globals_func_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="globals_func_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="globals_func_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="globals_func_0x77.html#index_w"><span>w</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_m">- m -</a></h3><ul>
+<li>max_desc_num()
+: <a class="el" href="dwc__otg__hcd__ddma_8c.html#b7563972b1dd332dde72911900756d92">dwc_otg_hcd_ddma.c</a><li>MODULE_PARM_DESC()
+: <a class="el" href="dwc__otg__driver_8c.html#e0dbd8f1a438746fa8ec7798ceb2bd50">dwc_otg_driver.c</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_func_0x70.html b/drivers/usb/host/dwc_otg/doc/html/globals_func_0x70.html
new file mode 100644
index 000000000000..d4b3d4c6d309
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_func_0x70.html
@@ -0,0 +1,78 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html"><span>All</span></a></li>
+    <li id="current"><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals_func.html#index__"><span>_</span></a></li>
+    <li><a href="globals_func_0x61.html#index_a"><span>a</span></a></li>
+    <li><a href="globals_func_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="globals_func_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="globals_func_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="globals_func_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="globals_func_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="globals_func_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="globals_func_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="globals_func_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="globals_func_0x6b.html#index_k"><span>k</span></a></li>
+    <li><a href="globals_func_0x6d.html#index_m"><span>m</span></a></li>
+    <li id="current"><a href="globals_func_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="globals_func_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="globals_func_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="globals_func_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="globals_func_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="globals_func_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="globals_func_0x77.html#index_w"><span>w</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_p">- p -</a></h3><ul>
+<li>pcd_clear_halt()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#153d9a3b2162ef091dc24027379af19f">dwc_otg_pcd_intr.c</a><li>pcd_init()
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#9dbc565a7942db0adbf1ec341db22901">dwc_otg_pcd_linux.c</a>, <a class="el" href="dwc__otg__driver_8c.html#9dbc565a7942db0adbf1ec341db22901">dwc_otg_driver.c</a><li>pcd_remove()
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#03129ea5120095af86c98558792aeae8">dwc_otg_pcd_linux.c</a>, <a class="el" href="dwc__otg__driver_8c.html#7960b8e2c02d9ab89b65cb01ba08658b">dwc_otg_driver.c</a><li>pcd_resume()
+: <a class="el" href="dwc__otg__cil__intr_8c.html#7d70de843b2e147969d32f7a9b2aa9e3">dwc_otg_cil_intr.c</a><li>pcd_setup()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#856a520a378e4f6f274253227080cfa1">dwc_otg_pcd_intr.c</a><li>pcd_start()
+: <a class="el" href="dwc__otg__cil__intr_8c.html#a1de88a9a54457a0b828a8a2845a210c">dwc_otg_cil_intr.c</a><li>pcd_stop()
+: <a class="el" href="dwc__otg__cil__intr_8c.html#d8eff82b37ea044fd7621faedcb36570">dwc_otg_cil_intr.c</a><li>pcd_suspend()
+: <a class="el" href="dwc__otg__cil__intr_8c.html#d9ac0577152f65fe83a76cbbca4ea795">dwc_otg_cil_intr.c</a><li>per_sched_disable()
+: <a class="el" href="dwc__otg__hcd__ddma_8c.html#693b9fdfeebc77b8132cfaf461b9c8fd">dwc_otg_hcd_ddma.c</a><li>per_sched_enable()
+: <a class="el" href="dwc__otg__hcd__ddma_8c.html#5b78d71512c6143d5a50e31dc3517f6a">dwc_otg_hcd_ddma.c</a><li>periodic_channel_available()
+: <a class="el" href="dwc__otg__hcd__queue_8c.html#debf9d35891234a74bc00832bba603bc">dwc_otg_hcd_queue.c</a><li>print_ep0_state()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#13cc45eef95b81189df890c10cf7ca66">dwc_otg_pcd_intr.c</a><li>process_non_periodic_channels()
+: <a class="el" href="dwc__otg__hcd_8c.html#a3f28e8605fd652c5177962e5dc8b95a">dwc_otg_hcd.c</a><li>process_periodic_channels()
+: <a class="el" href="dwc__otg__hcd_8c.html#00876268eb53e5ce91dbedcb026181ec">dwc_otg_hcd.c</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_func_0x71.html b/drivers/usb/host/dwc_otg/doc/html/globals_func_0x71.html
new file mode 100644
index 000000000000..41e644520441
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_func_0x71.html
@@ -0,0 +1,67 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html"><span>All</span></a></li>
+    <li id="current"><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals_func.html#index__"><span>_</span></a></li>
+    <li><a href="globals_func_0x61.html#index_a"><span>a</span></a></li>
+    <li><a href="globals_func_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="globals_func_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="globals_func_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="globals_func_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="globals_func_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="globals_func_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="globals_func_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="globals_func_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="globals_func_0x6b.html#index_k"><span>k</span></a></li>
+    <li><a href="globals_func_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="globals_func_0x70.html#index_p"><span>p</span></a></li>
+    <li id="current"><a href="globals_func_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="globals_func_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="globals_func_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="globals_func_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="globals_func_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="globals_func_0x77.html#index_w"><span>w</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_q">- q -</a></h3><ul>
+<li>qh_init()
+: <a class="el" href="dwc__otg__hcd__queue_8c.html#d32f8a4be67b758e9541e33746363677">dwc_otg_hcd_queue.c</a><li>qh_list_free()
+: <a class="el" href="dwc__otg__hcd_8c.html#d76881c1efea1a13be74ecfde85b4881">dwc_otg_hcd.c</a><li>queue_transaction()
+: <a class="el" href="dwc__otg__hcd_8c.html#8c7cd2f81cf41dbf3158f49b1d82a4f8">dwc_otg_hcd.c</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_func_0x72.html b/drivers/usb/host/dwc_otg/doc/html/globals_func_0x72.html
new file mode 100644
index 000000000000..7cfd7bcf8c89
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_func_0x72.html
@@ -0,0 +1,80 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html"><span>All</span></a></li>
+    <li id="current"><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals_func.html#index__"><span>_</span></a></li>
+    <li><a href="globals_func_0x61.html#index_a"><span>a</span></a></li>
+    <li><a href="globals_func_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="globals_func_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="globals_func_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="globals_func_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="globals_func_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="globals_func_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="globals_func_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="globals_func_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="globals_func_0x6b.html#index_k"><span>k</span></a></li>
+    <li><a href="globals_func_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="globals_func_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="globals_func_0x71.html#index_q"><span>q</span></a></li>
+    <li id="current"><a href="globals_func_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="globals_func_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="globals_func_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="globals_func_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="globals_func_0x77.html#index_w"><span>w</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_r">- r -</a></h3><ul>
+<li>rd_reg_test_show()
+: <a class="el" href="dwc__otg__attr_8c.html#81946b90c6e16e9596d9b9ccd1d54476">dwc_otg_attr.c</a><li>recalc_initial_desc_idx()
+: <a class="el" href="dwc__otg__hcd__ddma_8c.html#fc5f584eb735a394a794a3022939638a">dwc_otg_hcd_ddma.c</a><li>regdump_show()
+: <a class="el" href="dwc__otg__attr_8c.html#36728dcc762e9cbdbc9543c8b780df68">dwc_otg_attr.c</a><li>regoffset_show()
+: <a class="el" href="dwc__otg__attr_8c.html#ca58f009788e262a917c23784a84cb16">dwc_otg_attr.c</a><li>regoffset_store()
+: <a class="el" href="dwc__otg__attr_8c.html#fc5be3dbcd075f5087ca1730661c5dc2">dwc_otg_attr.c</a><li>regvalue_show()
+: <a class="el" href="dwc__otg__attr_8c.html#bb38eb60bd43b1de364db80fd1bcdbcf">dwc_otg_attr.c</a><li>regvalue_store()
+: <a class="el" href="dwc__otg__attr_8c.html#7db6b85ac60be49f52987e615a01408b">dwc_otg_attr.c</a><li>reinit_ddma_iso_xfer()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#c3f6fb3131e0786ec75a9c4a29fea297">dwc_otg_pcd_intr.c</a><li>release_channel()
+: <a class="el" href="dwc__otg__hcd__intr_8c.html#4f6bf01b14a03eeed81d27bffa5e99fc">dwc_otg_hcd_intr.c</a><li>release_channel_ddma()
+: <a class="el" href="dwc__otg__hcd__ddma_8c.html#060f60ac2e210b5da3bbe379674d2012">dwc_otg_hcd_ddma.c</a><li>release_perio_tx_fifo()
+: <a class="el" href="dwc__otg__pcd_8c.html#1bd1933ef625beee77eb026c4b1acb15">dwc_otg_pcd.c</a><li>release_tx_fifo()
+: <a class="el" href="dwc__otg__pcd_8c.html#bde782d98282535dc0c29a468da11f02">dwc_otg_pcd.c</a><li>remote_wakeup_show()
+: <a class="el" href="dwc__otg__attr_8c.html#3321551071eb0987630d501c377ff095">dwc_otg_attr.c</a><li>remote_wakeup_store()
+: <a class="el" href="dwc__otg__attr_8c.html#e64972f2160646d9d707a97366eba56c">dwc_otg_attr.c</a><li>reset_tasklet_func()
+: <a class="el" href="dwc__otg__hcd_8c.html#ed4640393d701e9bbfd966d4006a60b8">dwc_otg_hcd.c</a><li>restart_transfer()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#ed405cebf67cd1a89efd15a2935c8cef">dwc_otg_pcd_intr.c</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_func_0x73.html b/drivers/usb/host/dwc_otg/doc/html/globals_func_0x73.html
new file mode 100644
index 000000000000..72e2957a74ba
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_func_0x73.html
@@ -0,0 +1,77 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html"><span>All</span></a></li>
+    <li id="current"><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals_func.html#index__"><span>_</span></a></li>
+    <li><a href="globals_func_0x61.html#index_a"><span>a</span></a></li>
+    <li><a href="globals_func_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="globals_func_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="globals_func_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="globals_func_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="globals_func_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="globals_func_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="globals_func_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="globals_func_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="globals_func_0x6b.html#index_k"><span>k</span></a></li>
+    <li><a href="globals_func_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="globals_func_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="globals_func_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="globals_func_0x72.html#index_r"><span>r</span></a></li>
+    <li id="current"><a href="globals_func_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="globals_func_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="globals_func_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="globals_func_0x77.html#index_w"><span>w</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_s">- s -</a></h3><ul>
+<li>schedule_periodic()
+: <a class="el" href="dwc__otg__hcd__queue_8c.html#06b5d4bb36612e7da15a3727b1396a0c">dwc_otg_hcd_queue.c</a><li>set_current_pkt_info()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#17428b2360118cc59ab9d5cbcef8a14b">dwc_otg_pcd_intr.c</a><li>set_ddma_iso_pkts_info()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#e5ed26b3ab2380cb92773df1720ec752">dwc_otg_pcd_intr.c</a><li>SET_DEBUG_LEVEL()
+: <a class="el" href="dwc__otg__dbg_8h.html#68eadfdf7a6a3f2eed00492119b00bae">dwc_otg_dbg.h</a><li>set_iso_pkts_info()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#a356ecc4053e9700785a27dbfdd6b2db">dwc_otg_pcd_intr.c</a><li>set_parameters()
+: <a class="el" href="dwc__otg__driver_8c.html#fe3a3765da365671b36ba5e28dc4d38b">dwc_otg_driver.c</a><li>set_pid_isoc()
+: <a class="el" href="dwc__otg__cil_8c.html#bf1f2e3a039a78f9cc51c8223c40d8e1">dwc_otg_cil.c</a><li>spramdump_show()
+: <a class="el" href="dwc__otg__attr_8c.html#e98e139afbb50f9d989ddbef2f0dbd6e">dwc_otg_attr.c</a><li>srp_show()
+: <a class="el" href="dwc__otg__attr_8c.html#9e8313bb6a0f54484d279b2e28269712">dwc_otg_attr.c</a><li>srp_store()
+: <a class="el" href="dwc__otg__attr_8c.html#80c785e24be4a8ce02d0b38a0ba5484a">dwc_otg_attr.c</a><li>srp_timeout()
+: <a class="el" href="dwc__otg__pcd_8c.html#e1e5a9264c2ad212d697d6be1110874f">dwc_otg_pcd.c</a><li>start_next_request()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#de7160b7e7b8fd622ba95392513e197c">dwc_otg_pcd_intr.c</a>, <a class="el" href="dwc__otg__pcd_8c.html#de7160b7e7b8fd622ba95392513e197c">dwc_otg_pcd.c</a><li>start_xfer_tasklet_func()
+: <a class="el" href="dwc__otg__pcd_8c.html#4d9d8f7fb8f74eb64176fba91b38cb35">dwc_otg_pcd.c</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_func_0x75.html b/drivers/usb/host/dwc_otg/doc/html/globals_func_0x75.html
new file mode 100644
index 000000000000..0999b3e2f28c
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_func_0x75.html
@@ -0,0 +1,73 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html"><span>All</span></a></li>
+    <li id="current"><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals_func.html#index__"><span>_</span></a></li>
+    <li><a href="globals_func_0x61.html#index_a"><span>a</span></a></li>
+    <li><a href="globals_func_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="globals_func_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="globals_func_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="globals_func_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="globals_func_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="globals_func_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="globals_func_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="globals_func_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="globals_func_0x6b.html#index_k"><span>k</span></a></li>
+    <li><a href="globals_func_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="globals_func_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="globals_func_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="globals_func_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="globals_func_0x73.html#index_s"><span>s</span></a></li>
+    <li id="current"><a href="globals_func_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="globals_func_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="globals_func_0x77.html#index_w"><span>w</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_u">- u -</a></h3><ul>
+<li>update_frame_list()
+: <a class="el" href="dwc__otg__hcd__ddma_8c.html#46c1ec7e2bd2f1177983f6676952cfdf">dwc_otg_hcd_ddma.c</a><li>update_isoc_urb_state()
+: <a class="el" href="dwc__otg__hcd__intr_8c.html#e93d54bdf873c5a31882660c2984458e">dwc_otg_hcd_intr.c</a><li>update_non_isoc_urb_state_ddma()
+: <a class="el" href="dwc__otg__hcd__ddma_8c.html#7a1a6af7f05278f5b7daa3b0a2d2fa4a">dwc_otg_hcd_ddma.c</a><li>update_urb_state_xfer_comp()
+: <a class="el" href="dwc__otg__hcd__intr_8c.html#ecb30a961e8d4831e8691d45a77162e3">dwc_otg_hcd_intr.c</a><li>update_urb_state_xfer_intr()
+: <a class="el" href="dwc__otg__hcd__intr_8c.html#0640c3606be7a8700ea4813e590ebf43">dwc_otg_hcd_intr.c</a><li>urb_dequeue()
+: <a class="el" href="dwc__otg__hcd__linux_8c.html#afc1f3d92fd7596140c0068bc96034f7">dwc_otg_hcd_linux.c</a><li>urb_enqueue()
+: <a class="el" href="dwc__otg__hcd__linux_8c.html#d9e9c76f2bc1c4f662d132c710a95a60">dwc_otg_hcd_linux.c</a><li>usb_gadget_register_driver()
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#8c1ba129028b3b16909973eb30b85d2c">dwc_otg_pcd_linux.c</a><li>usb_gadget_unregister_driver()
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#fa4a24d0806fbb6e3135d27d24a6a00d">dwc_otg_pcd_linux.c</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_func_0x76.html b/drivers/usb/host/dwc_otg/doc/html/globals_func_0x76.html
new file mode 100644
index 000000000000..91caeb0e9de2
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_func_0x76.html
@@ -0,0 +1,65 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html"><span>All</span></a></li>
+    <li id="current"><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals_func.html#index__"><span>_</span></a></li>
+    <li><a href="globals_func_0x61.html#index_a"><span>a</span></a></li>
+    <li><a href="globals_func_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="globals_func_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="globals_func_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="globals_func_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="globals_func_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="globals_func_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="globals_func_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="globals_func_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="globals_func_0x6b.html#index_k"><span>k</span></a></li>
+    <li><a href="globals_func_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="globals_func_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="globals_func_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="globals_func_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="globals_func_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="globals_func_0x75.html#index_u"><span>u</span></a></li>
+    <li id="current"><a href="globals_func_0x76.html#index_v"><span>v</span></a></li>
+    <li><a href="globals_func_0x77.html#index_w"><span>w</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_v">- v -</a></h3><ul>
+<li>version_show()
+: <a class="el" href="dwc__otg__driver_8c.html#6eaf4dedcf1df7eb80c48f1872212012">dwc_otg_driver.c</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_func_0x77.html b/drivers/usb/host/dwc_otg/doc/html/globals_func_0x77.html
new file mode 100644
index 000000000000..7934bcd6ff76
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_func_0x77.html
@@ -0,0 +1,70 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html"><span>All</span></a></li>
+    <li id="current"><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals_func.html#index__"><span>_</span></a></li>
+    <li><a href="globals_func_0x61.html#index_a"><span>a</span></a></li>
+    <li><a href="globals_func_0x62.html#index_b"><span>b</span></a></li>
+    <li><a href="globals_func_0x63.html#index_c"><span>c</span></a></li>
+    <li><a href="globals_func_0x64.html#index_d"><span>d</span></a></li>
+    <li><a href="globals_func_0x65.html#index_e"><span>e</span></a></li>
+    <li><a href="globals_func_0x66.html#index_f"><span>f</span></a></li>
+    <li><a href="globals_func_0x67.html#index_g"><span>g</span></a></li>
+    <li><a href="globals_func_0x68.html#index_h"><span>h</span></a></li>
+    <li><a href="globals_func_0x69.html#index_i"><span>i</span></a></li>
+    <li><a href="globals_func_0x6b.html#index_k"><span>k</span></a></li>
+    <li><a href="globals_func_0x6d.html#index_m"><span>m</span></a></li>
+    <li><a href="globals_func_0x70.html#index_p"><span>p</span></a></li>
+    <li><a href="globals_func_0x71.html#index_q"><span>q</span></a></li>
+    <li><a href="globals_func_0x72.html#index_r"><span>r</span></a></li>
+    <li><a href="globals_func_0x73.html#index_s"><span>s</span></a></li>
+    <li><a href="globals_func_0x75.html#index_u"><span>u</span></a></li>
+    <li><a href="globals_func_0x76.html#index_v"><span>v</span></a></li>
+    <li id="current"><a href="globals_func_0x77.html#index_w"><span>w</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_w">- w -</a></h3><ul>
+<li>w_conn_id_status_change()
+: <a class="el" href="dwc__otg__cil__intr_8c.html#9ef061e0e79210e6c2a2c2b9cc45bd45">dwc_otg_cil_intr.c</a>, <a class="el" href="dwc__otg__cil_8h.html#9ef061e0e79210e6c2a2c2b9cc45bd45">dwc_otg_cil.h</a><li>w_wakeup_detected()
+: <a class="el" href="dwc__otg__cil__intr_8c.html#07f0b189448c71e7ea4c7b121320fb89">dwc_otg_cil_intr.c</a>, <a class="el" href="dwc__otg__cil_8h.html#07f0b189448c71e7ea4c7b121320fb89">dwc_otg_cil.h</a><li>wakeup()
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#6a6034564b7cc6d8cebfbe02a944cd2c">dwc_otg_pcd_linux.c</a><li>wr_reg_test_show()
+: <a class="el" href="dwc__otg__attr_8c.html#9dd7132e3f334eed0e27e11ab5f7b0c4">dwc_otg_attr.c</a><li>write_empty_tx_fifo()
+: <a class="el" href="dwc__otg__pcd__intr_8c.html#5e53962e63763aa9df6400981b7d5354">dwc_otg_pcd_intr.c</a><li>write_isoc_frame_data()
+: <a class="el" href="dwc__otg__cil_8c.html#e39d47d3aee9efcd525c13ce6a1f5f6a">dwc_otg_cil.c</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_type.html b/drivers/usb/host/dwc_otg/doc/html/globals_type.html
new file mode 100644
index 000000000000..a9b8400ce988
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_type.html
@@ -0,0 +1,175 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html"><span>All</span></a></li>
+    <li><a href="globals_func.html"><span>Functions</span></a></li>
+    <li><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li id="current"><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="#index_c"><span>c</span></a></li>
+    <li><a href="#index_d"><span>d</span></a></li>
+    <li><a href="#index_e"><span>e</span></a></li>
+    <li><a href="#index_f"><span>f</span></a></li>
+    <li><a href="#index_g"><span>g</span></a></li>
+    <li><a href="#index_h"><span>h</span></a></li>
+    <li><a href="#index_i"><span>i</span></a></li>
+    <li><a href="#index_p"><span>p</span></a></li>
+    <li><a href="#index_r"><span>r</span></a></li>
+    <li><a href="#index_t"><span>t</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_c">- c -</a></h3><ul>
+<li>cfi_all_features_header_t
+: <a class="el" href="dwc__cfi__common_8h.html#23298b60a6c427f08efe303c0bb332f8">dwc_cfi_common.h</a><li>cfi_ep_t
+: <a class="el" href="dwc__otg__cfi_8h.html#1c70b0d73323d138d4aac971e9998908">dwc_otg_cfi.h</a><li>cfi_feature_desc_header_t
+: <a class="el" href="dwc__cfi__common_8h.html#04466a29673dc59d190905db0db48266">dwc_cfi_common.h</a><li>cfi_ops_t
+: <a class="el" href="dwc__otg__cfi_8h.html#226b99dcff1992adefa086b6c7773eff">dwc_otg_cfi.h</a><li>cfi_setup_cb_t
+: <a class="el" href="dwc__otg__pcd__if_8h.html#7d75df2095c14a2d985df8027359e440">dwc_otg_pcd_if.h</a><li>cfi_string_t
+: <a class="el" href="dwc__cfi__common_8h.html#16bf31056d146243d486600ccbe8da85">dwc_cfi_common.h</a><li>cfiobject_t
+: <a class="el" href="dwc__otg__cfi_8h.html#4a1790f6f20555dd7cb9c8ae91c568a6">dwc_otg_cfi.h</a></ul>
+<h3><a class="anchor" name="index_d">- d -</a></h3><ul>
+<li>daint_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#1effb8b11c6a62aacfcbea74c1be84f6">dwc_otg_regs.h</a><li>dcfg_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#077228cd7e2acbd1e246bd9b0379c524">dwc_otg_regs.h</a><li>dctl_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#043805708857633a05ae076cf8c0a143">dwc_otg_regs.h</a><li>ddma_align_buffer_setup_t
+: <a class="el" href="dwc__otg__cfi_8h.html#f60b107e43f0edf8ac94f781803c8780">dwc_otg_cfi.h</a><li>ddma_concat_buffer_setup_hdr_t
+: <a class="el" href="dwc__otg__cfi_8h.html#a6fccd9def2a83408bdb10eb7964a4d6">dwc_otg_cfi.h</a><li>ddma_concat_buffer_setup_t
+: <a class="el" href="dwc__otg__cfi_8h.html#083bc35d34ae5489588bb581fc45ae73">dwc_otg_cfi.h</a><li>ddma_sg_buffer_setup_t
+: <a class="el" href="dwc__otg__cfi_8h.html#1040b884c9adf08c1106ffdf9f191ad4">dwc_otg_cfi.h</a><li>depctl_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#1d8ef2c3a67226833c01502c66bbd7a3">dwc_otg_regs.h</a><li>deptsiz0_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#0c2941814d5219b96c19caac80d58a3e">dwc_otg_regs.h</a><li>deptsiz_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#cb6f36bd93d869b9e61de914c8e2d222">dwc_otg_regs.h</a><li>dev_dma_desc_sts_t
+: <a class="el" href="dwc__otg__regs_8h.html#5363ac57fa4401cb81be60414d9104fe">dwc_otg_regs.h</a><li>device_grxsts_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#89dcb8224836ceda40e3584b3db51411">dwc_otg_regs.h</a><li>diepint_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#0f4ab8ee4156c299665471b3a6f279ce">dwc_otg_regs.h</a><li>diepmsk_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#0a168a8839d24b08e39eebb131447531">dwc_otg_regs.h</a><li>doepint_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#692b7898b190ff12cca460bd0711db3f">dwc_otg_regs.h</a><li>doepmsk_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#722a9ff3c92f6c195b9ee3c3838b6bbb">dwc_otg_regs.h</a><li>dsts_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#2bd7f2043b7f4841e17b38edc406e06d">dwc_otg_regs.h</a><li>dthrctl_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#962414fc1e02940112ab0db4c53bcc6c">dwc_otg_regs.h</a><li>dtknq1_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#61e9acc9f9165e3fb6c15ce96db21861">dwc_otg_regs.h</a><li>dtxfsts_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#d3e24afd53e919e2cb6d436506248f75">dwc_otg_regs.h</a><li>dwc_completion_cb_t
+: <a class="el" href="dwc__otg__pcd__if_8h.html#9c448e9fa004f873c281f46f5e5a597d">dwc_otg_pcd_if.h</a><li>dwc_connect_cb_t
+: <a class="el" href="dwc__otg__pcd__if_8h.html#4808152d074c472f4fb1aa7b662e3004">dwc_otg_pcd_if.h</a><li>dwc_disconnect_cb_t
+: <a class="el" href="dwc__otg__pcd__if_8h.html#959f051498d2957d47cb0d27b42546aa">dwc_otg_pcd_if.h</a><li>dwc_ep_t
+: <a class="el" href="dwc__otg__cil_8h.html#974bc77a560995de85c414ac44799443">dwc_otg_cil.h</a><li>dwc_hc_t
+: <a class="el" href="dwc__otg__cil_8h.html#fc0170955f6bcf84c1b8d02ec94a5826">dwc_otg_cil.h</a><li>dwc_hnp_params_changed_cb_t
+: <a class="el" href="dwc__otg__pcd__if_8h.html#eef0b7f44036d8164121ed079710058b">dwc_otg_pcd_if.h</a><li>dwc_isoc_completion_cb_t
+: <a class="el" href="dwc__otg__pcd__if_8h.html#a6f91e357c7c7782afa7db03e95a52ed">dwc_otg_pcd_if.h</a><li>dwc_otg_cil_callbacks_t
+: <a class="el" href="dwc__otg__cil_8h.html#b54889e4f4d9fd42235411c317645280">dwc_otg_cil.h</a><li>dwc_otg_control_phase_e
+: <a class="el" href="dwc__otg__hcd_8h.html#be7c5653ee5e9d33855d2513f31b56a5">dwc_otg_hcd.h</a><li>dwc_otg_core_global_regs_t
+: <a class="el" href="dwc__otg__regs_8h.html#4ba81f9e704c22b6ae0155dfb103b040">dwc_otg_regs.h</a><li>dwc_otg_core_if_t
+: <a class="el" href="dwc__otg__core__if_8h.html#645ef0682256d1b3dbd576fe9dfaf487">dwc_otg_core_if.h</a><li>dwc_otg_core_params_t
+: <a class="el" href="dwc__otg__cil_8h.html#b277e9a981ab1d2769a32f6610a52f51">dwc_otg_cil.h</a><li>dwc_otg_dev_dma_desc_t
+: <a class="el" href="dwc__otg__regs_8h.html#e10a2a455a645b5d69d3a078b82ffc75">dwc_otg_regs.h</a><li>dwc_otg_dev_if_t
+: <a class="el" href="dwc__otg__regs_8h.html#9cc9d3e0d8697163a63c07db365a8d72">dwc_otg_regs.h</a><li>dwc_otg_dev_in_ep_regs_t
+: <a class="el" href="dwc__otg__regs_8h.html#f23afc1a2db189b69772170cbd68b509">dwc_otg_regs.h</a><li>dwc_otg_dev_out_ep_regs_t
+: <a class="el" href="dwc__otg__regs_8h.html#67ce4d713bb26f1244377b55aec8035a">dwc_otg_regs.h</a><li>dwc_otg_device_global_regs_t
+: <a class="el" href="dwc__otg__regs_8h.html#c8e8458afafc8849b85f5b5fcf9b6d1b">dwc_otg_regs.h</a><li>dwc_otg_device_t
+: <a class="el" href="dwc__otg__driver_8h.html#70dce40f5a55fe7acee5343d998d5074">dwc_otg_driver.h</a><li>dwc_otg_hc_regs_t
+: <a class="el" href="dwc__otg__regs_8h.html#c64589846d616caf2a82a41be5dc359b">dwc_otg_regs.h</a><li>dwc_otg_hcd_complete_urb_cb_t
+: <a class="el" href="dwc__otg__hcd__if_8h.html#87b0daec8c90b013f81b4854b64dec2e">dwc_otg_hcd_if.h</a><li>dwc_otg_hcd_disconnect_cb_t
+: <a class="el" href="dwc__otg__hcd__if_8h.html#8190c45625905c85a22565524abcf192">dwc_otg_hcd_if.h</a><li>dwc_otg_hcd_get_b_hnp_enable
+: <a class="el" href="dwc__otg__hcd__if_8h.html#23db00d75e435cb0cb13d1e914dfd672">dwc_otg_hcd_if.h</a><li>dwc_otg_hcd_hub_info_from_urb_cb_t
+: <a class="el" href="dwc__otg__hcd__if_8h.html#7893b4f0c0c2116e6cd8ba82659d7b65">dwc_otg_hcd_if.h</a><li>dwc_otg_hcd_speed_from_urb_cb_t
+: <a class="el" href="dwc__otg__hcd__if_8h.html#d85b6d5afa41eb5b0d1365b14642e77c">dwc_otg_hcd_if.h</a><li>dwc_otg_hcd_start_cb_t
+: <a class="el" href="dwc__otg__hcd__if_8h.html#76658d35c49c5594bdb795fddf8252a8">dwc_otg_hcd_if.h</a><li>dwc_otg_hcd_t
+: <a class="el" href="dwc__otg__hcd__if_8h.html#c60760d19c9d069e3bf00b4b97b74cd3">dwc_otg_hcd_if.h</a><li>dwc_otg_hcd_urb_t
+: <a class="el" href="dwc__otg__hcd__if_8h.html#0e7bca23553c3dfc493b44a01454a2c4">dwc_otg_hcd_if.h</a><li>dwc_otg_host_dma_desc_t
+: <a class="el" href="dwc__otg__regs_8h.html#c4ddf8781cd4885c274d7964d3a32337">dwc_otg_regs.h</a><li>dwc_otg_host_global_regs_t
+: <a class="el" href="dwc__otg__regs_8h.html#9e250e84dc7eefacc94a0d9d9fd198df">dwc_otg_regs.h</a><li>dwc_otg_host_if_t
+: <a class="el" href="dwc__otg__regs_8h.html#3fce2e3cb951b38f1c6fec40637392c2">dwc_otg_regs.h</a><li>dwc_otg_pcd_ep_t
+: <a class="el" href="dwc__otg__pcd_8h.html#fa97bfbab3706fa510ecff969ce39756">dwc_otg_pcd.h</a><li>dwc_otg_pcd_iso_request_t
+: <a class="el" href="dwc__otg__pcd_8h.html#050b65dd6f6dfd9d8527f94bdf88a937">dwc_otg_pcd.h</a><li>dwc_otg_pcd_request_t
+: <a class="el" href="dwc__otg__pcd_8h.html#1253ddf26039ef0a68df3eb5423f65da">dwc_otg_pcd.h</a><li>dwc_otg_pcd_t
+: <a class="el" href="dwc__otg__pcd__if_8h.html#f6503e2b4469b327ae64f650bb5721cb">dwc_otg_pcd_if.h</a><li>dwc_otg_qh_t
+: <a class="el" href="dwc__otg__hcd_8h.html#7d1300eb1d7683e646af1094fe418c0b">dwc_otg_hcd.h</a><li>dwc_otg_qtd_t
+: <a class="el" href="dwc__otg__hcd_8h.html#05542225d8dd075a2b981fa565bdfccc">dwc_otg_hcd.h</a><li>dwc_otg_transaction_type_e
+: <a class="el" href="dwc__otg__hcd_8h.html#92c49783eebc5bcffa8b8a51c2127be9">dwc_otg_hcd.h</a><li>dwc_reset_cb_t
+: <a class="el" href="dwc__otg__pcd__if_8h.html#f6bba5b7b3d3ad67fbf2161717281fdd">dwc_otg_pcd_if.h</a><li>dwc_resume_cb_t
+: <a class="el" href="dwc__otg__pcd__if_8h.html#44d7ec17e6e087e44dd7c372e01fcfb2">dwc_otg_pcd_if.h</a><li>dwc_setup_cb_t
+: <a class="el" href="dwc__otg__pcd__if_8h.html#a9145aeaa27da4fa1befb424f927fde7">dwc_otg_pcd_if.h</a><li>dwc_sleep_cb_t
+: <a class="el" href="dwc__otg__pcd__if_8h.html#fc48d3df458c446cc0ace0a7d7755c67">dwc_otg_pcd_if.h</a><li>dwc_suspend_cb_t
+: <a class="el" href="dwc__otg__pcd__if_8h.html#ddcaadb93595803ca5f2ffb74cd88619">dwc_otg_pcd_if.h</a></ul>
+<h3><a class="anchor" name="index_e">- e -</a></h3><ul>
+<li>ep0state_e
+: <a class="el" href="dwc__otg__pcd_8h.html#70fcb6a989e5871e16f4c1c96ffe394a">dwc_otg_pcd.h</a></ul>
+<h3><a class="anchor" name="index_f">- f -</a></h3><ul>
+<li>fifosize_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#389bbcdb2f9b7b284631c4e3c6c05ca4">dwc_otg_regs.h</a></ul>
+<h3><a class="anchor" name="index_g">- g -</a></h3><ul>
+<li>gahbcfg_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#e1aca1c2d0abbb005545a17af3508291">dwc_otg_regs.h</a><li>gi2cctl_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#de10c5861b75d2f22b1a1b9e817a3098">dwc_otg_regs.h</a><li>gintmsk_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#db54cb8baf5c7d970347192ad40662d3">dwc_otg_regs.h</a><li>gintsts_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#211ef100682c75981568527ed748dcfc">dwc_otg_regs.h</a><li>glpmcfg_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#ba73e60dacc956a6090a82188bb8fcfa">dwc_otg_regs.h</a><li>gnptxsts_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#e00daff072291dd6e7af34701aad3138">dwc_otg_regs.h</a><li>gotgctl_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#6a10de8c32943876bfc55ed308d3ff83">dwc_otg_regs.h</a><li>gotgint_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#9f95118956319102de69927308a2defd">dwc_otg_regs.h</a><li>grstctl_t
+: <a class="el" href="dwc__otg__regs_8h.html#ca690ce842cde2518004eefeedda7788">dwc_otg_regs.h</a><li>gusbcfg_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#176748792c6f7aedc1aacf6740c2b1dd">dwc_otg_regs.h</a></ul>
+<h3><a class="anchor" name="index_h">- h -</a></h3><ul>
+<li>haint_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#27de5d0beb5957eb126766a01fec40b2">dwc_otg_regs.h</a><li>haintmsk_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#f8363fbf7d3be043235c0bf6b057a637">dwc_otg_regs.h</a><li>hcchar_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#e3bd36607e63cd3181c877f329a6eff8">dwc_otg_regs.h</a><li>hcdma_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#018c0b4c795e3d3c373348fd4dafecb4">dwc_otg_regs.h</a><li>hcfg_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#26f6beffdddc3cbe5f7ec4f77824cca0">dwc_otg_regs.h</a><li>hcint_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#c765ad9a2d3eff579f45362a2dcf39e3">dwc_otg_regs.h</a><li>hcintmsk_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#eeffbd23c7de44b01363bf196b4a6a44">dwc_otg_regs.h</a><li>hctsiz_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#2f3d030c12693e0cf5876517856766b4">dwc_otg_regs.h</a><li>hfir_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#ff5539ea6d98c6725480b533c13dc652">dwc_otg_regs.h</a><li>hfnum_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#f5c22a704229989ff3435059ebe9fb10">dwc_otg_regs.h</a><li>host_dma_desc_sts_t
+: <a class="el" href="dwc__otg__regs_8h.html#fbefbebde0abe3db88477ab0831d865a">dwc_otg_regs.h</a><li>host_grxsts_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#1d5d223eb9bab051464aca64efd707e1">dwc_otg_regs.h</a><li>hprt0_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#b6962581d4be622894de1b523256f4f9">dwc_otg_regs.h</a><li>hwcfg1_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#e3fd2e458471dcd8fec9fa09ff787ad5">dwc_otg_regs.h</a><li>hwcfg2_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#a3044f8c36a47affba16a8abcebc2a33">dwc_otg_regs.h</a><li>hwcfg3_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#cec01b13bc8d56e9001801bb14a98857">dwc_otg_regs.h</a><li>hwcfg4_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#d9159ac522a8a34be480e616a9df7ebe">dwc_otg_regs.h</a></ul>
+<h3><a class="anchor" name="index_i">- i -</a></h3><ul>
+<li>iso_pkt_info_t
+: <a class="el" href="dwc__otg__cil_8h.html#ef7ad72528599bd12fe954ce1899576e">dwc_otg_cil.h</a></ul>
+<h3><a class="anchor" name="index_p">- p -</a></h3><ul>
+<li>pcgcctl_data_t
+: <a class="el" href="dwc__otg__regs_8h.html#5efd1b5bf72987298cdf3d79bca37832">dwc_otg_regs.h</a></ul>
+<h3><a class="anchor" name="index_r">- r -</a></h3><ul>
+<li>rx_fifo_size_setup_t
+: <a class="el" href="dwc__otg__cfi_8h.html#0fbbd60333457c6667bd7757e4aac2f8">dwc_otg_cfi.h</a></ul>
+<h3><a class="anchor" name="index_t">- t -</a></h3><ul>
+<li>tx_fifo_size_setup_t
+: <a class="el" href="dwc__otg__cfi_8h.html#9da70e9326ec40c9f1bd9c487aabe4c1">dwc_otg_cfi.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/globals_vars.html b/drivers/usb/host/dwc_otg/doc/html/globals_vars.html
new file mode 100644
index 000000000000..3f862ed8a24a
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/globals_vars.html
@@ -0,0 +1,120 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li id="current"><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="files.html"><span>File&nbsp;List</span></a></li>
+    <li id="current"><a href="globals.html"><span>Globals</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="globals.html"><span>All</span></a></li>
+    <li><a href="globals_func.html"><span>Functions</span></a></li>
+    <li id="current"><a href="globals_vars.html"><span>Variables</span></a></li>
+    <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+    <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+    <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    <li><a href="globals_defs.html"><span>Defines</span></a></li>
+  </ul>
+</div>
+<div class="tabs">
+  <ul>
+    <li><a href="#index_b"><span>b</span></a></li>
+    <li><a href="#index_d"><span>d</span></a></li>
+    <li><a href="#index_f"><span>f</span></a></li>
+    <li><a href="#index_g"><span>g</span></a></li>
+    <li><a href="#index_h"><span>h</span></a></li>
+    <li><a href="#index_p"><span>p</span></a></li>
+    <li><a href="#index_r"><span>r</span></a></li>
+    <li><a href="#index_s"><span>s</span></a></li>
+    <li><a href="#index_u"><span>u</span></a></li>
+    <li><a href="#index_w"><span>w</span></a></li>
+  </ul>
+</div>
+
+<p>
+&nbsp;
+<p>
+<h3><a class="anchor" name="index_b">- b -</a></h3><ul>
+<li>buspower
+: <a class="el" href="dwc__otg__attr_8c.html#1d54646ee79d4ce4f4acd08d7d4448ce">dwc_otg_attr.c</a><li>buspower_show
+: <a class="el" href="dwc__otg__attr_8c.html#6979f4909cde868d800dba13ef95aa8c">dwc_otg_attr.c</a><li>buspower_store
+: <a class="el" href="dwc__otg__attr_8c.html#4514a396df18dae15f7f03f640f52ac7">dwc_otg_attr.c</a><li>bussuspend
+: <a class="el" href="dwc__otg__attr_8c.html#e3c6534cdd3e1b7e83bf48e745d44c64">dwc_otg_attr.c</a><li>bussuspend_show
+: <a class="el" href="dwc__otg__attr_8c.html#ae1f7e3a17c5a0bcc5a93096aeb902d2">dwc_otg_attr.c</a><li>bussuspend_store
+: <a class="el" href="dwc__otg__attr_8c.html#f218d7c4c611b97dfaa1e03ac2daa353">dwc_otg_attr.c</a></ul>
+<h3><a class="anchor" name="index_d">- d -</a></h3><ul>
+<li>dwc_driver_name
+: <a class="el" href="dwc__otg__driver_8c.html#3f7932dcd77bb7b05f92f759e6569fe2">dwc_otg_driver.c</a><li>dwc_otg_hc_driver
+: <a class="el" href="dwc__otg__hcd__linux_8c.html#ab1d492c360b963d179798f2641c02a5">dwc_otg_hcd_linux.c</a><li>dwc_otg_hcd_name
+: <a class="el" href="dwc__otg__hcd__linux_8c.html#41b49c86957a3835934c2f26fee377df">dwc_otg_hcd_linux.c</a><li>dwc_otg_module_params
+: <a class="el" href="dwc__otg__driver_8c.html#887d74166238890f65ffb620e39c759b">dwc_otg_driver.c</a><li>dwc_otg_pcd_ep_ops
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#8d23bf781df0ba0fb4a0133d08c09dc1">dwc_otg_pcd_linux.c</a><li>dwc_otg_pcd_ops
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#592a942ef237021f608d03dd8b57bc54">dwc_otg_pcd_linux.c</a></ul>
+<h3><a class="anchor" name="index_f">- f -</a></h3><ul>
+<li>fops
+: <a class="el" href="dwc__otg__pcd__linux_8c.html#9ce9b5e49c60906c189bee157dd68acd">dwc_otg_pcd_linux.c</a></ul>
+<h3><a class="anchor" name="index_g">- g -</a></h3><ul>
+<li>g_dbg_lvl
+: <a class="el" href="dwc__otg__driver_8c.html#7ef4ada2ebb5f1aadf3be4d7fbf8ce62">dwc_otg_driver.c</a>, <a class="el" href="dwc__otg__dbg_8h.html#7ef4ada2ebb5f1aadf3be4d7fbf8ce62">dwc_otg_dbg.h</a></ul>
+<h3><a class="anchor" name="index_h">- h -</a></h3><ul>
+<li>hcd_cil_callbacks
+: <a class="el" href="dwc__otg__hcd_8c.html#106ff6cbb1499325ea75f2d97abb8e6a">dwc_otg_hcd.c</a><li>hcd_fops
+: <a class="el" href="dwc__otg__hcd__linux_8c.html#430ee3db85940ea34a1702a37fbfb942">dwc_otg_hcd_linux.c</a><li>hcd_frrem
+: <a class="el" href="dwc__otg__attr_8c.html#98c5b16a6162e4c9057aee72a7216efb">dwc_otg_attr.c</a><li>hcd_frrem_show
+: <a class="el" href="dwc__otg__attr_8c.html#d1d9d9abd2011c79fe7453c20e03e31a">dwc_otg_attr.c</a><li>hcddump
+: <a class="el" href="dwc__otg__attr_8c.html#eb95151b5afaea479812773b61c402b4">dwc_otg_attr.c</a><li>hcddump_show
+: <a class="el" href="dwc__otg__attr_8c.html#e16d4439b6b733715ecc1d06ed999aa4">dwc_otg_attr.c</a><li>hnp
+: <a class="el" href="dwc__otg__attr_8c.html#2d1cf91c8e20bcdd4f552c410b0aa6ba">dwc_otg_attr.c</a><li>hnp_show
+: <a class="el" href="dwc__otg__attr_8c.html#5ed0f5e2094b1db679075adf2f81e10a">dwc_otg_attr.c</a><li>hnp_store
+: <a class="el" href="dwc__otg__attr_8c.html#14b1910d541301f5456e2a15a3b4f0b0">dwc_otg_attr.c</a></ul>
+<h3><a class="anchor" name="index_p">- p -</a></h3><ul>
+<li>packed
+: <a class="el" href="dwc__otg__cfi_8h.html#3e7b3a7aca62be5747bfe900e0a9e102">dwc_otg_cfi.h</a><li>pcd_callbacks
+: <a class="el" href="dwc__otg__pcd_8c.html#c360aaa36ba28b977284fd482e7bc5ca">dwc_otg_pcd.c</a></ul>
+<h3><a class="anchor" name="index_r">- r -</a></h3><ul>
+<li>rd_reg_test
+: <a class="el" href="dwc__otg__attr_8c.html#829fa87e3e65ff4038b6bc0eb2a93fb7">dwc_otg_attr.c</a><li>rd_reg_test_show
+: <a class="el" href="dwc__otg__attr_8c.html#81946b90c6e16e9596d9b9ccd1d54476">dwc_otg_attr.c</a><li>regdump
+: <a class="el" href="dwc__otg__attr_8c.html#8db089dfccee4ac4de5f89814ddd42fc">dwc_otg_attr.c</a><li>regdump_show
+: <a class="el" href="dwc__otg__attr_8c.html#36728dcc762e9cbdbc9543c8b780df68">dwc_otg_attr.c</a><li>regoffset
+: <a class="el" href="dwc__otg__attr_8c.html#aeabf3d18b9b521d65b364cec3dcde45">dwc_otg_attr.c</a><li>regoffset_show
+: <a class="el" href="dwc__otg__attr_8c.html#ca58f009788e262a917c23784a84cb16">dwc_otg_attr.c</a><li>regoffset_store
+: <a class="el" href="dwc__otg__attr_8c.html#fc5be3dbcd075f5087ca1730661c5dc2">dwc_otg_attr.c</a><li>regvalue
+: <a class="el" href="dwc__otg__attr_8c.html#c246d9ba494611cb5b3054a71bf21d22">dwc_otg_attr.c</a><li>regvalue_show
+: <a class="el" href="dwc__otg__attr_8c.html#bb38eb60bd43b1de364db80fd1bcdbcf">dwc_otg_attr.c</a><li>regvalue_store
+: <a class="el" href="dwc__otg__attr_8c.html#7db6b85ac60be49f52987e615a01408b">dwc_otg_attr.c</a><li>remote_wakeup
+: <a class="el" href="dwc__otg__attr_8c.html#f3afff970133d773b5414f1f0f2becfe">dwc_otg_attr.c</a><li>remote_wakeup_show
+: <a class="el" href="dwc__otg__attr_8c.html#3321551071eb0987630d501c377ff095">dwc_otg_attr.c</a><li>remote_wakeup_store
+: <a class="el" href="dwc__otg__attr_8c.html#e64972f2160646d9d707a97366eba56c">dwc_otg_attr.c</a></ul>
+<h3><a class="anchor" name="index_s">- s -</a></h3><ul>
+<li>S_IWUSR
+: <a class="el" href="dwc__otg__attr_8c.html#ac2308832629daf78cb9dd123551cd8a">dwc_otg_attr.c</a><li>spramdump
+: <a class="el" href="dwc__otg__attr_8c.html#d24c69237b2acf90968b763e467e9ec9">dwc_otg_attr.c</a><li>spramdump_show
+: <a class="el" href="dwc__otg__attr_8c.html#e98e139afbb50f9d989ddbef2f0dbd6e">dwc_otg_attr.c</a><li>srp
+: <a class="el" href="dwc__otg__attr_8c.html#0c2c4ba16770c40a82dbb1c33cbc2e4a">dwc_otg_attr.c</a><li>srp_show
+: <a class="el" href="dwc__otg__attr_8c.html#9e8313bb6a0f54484d279b2e28269712">dwc_otg_attr.c</a><li>srp_store
+: <a class="el" href="dwc__otg__attr_8c.html#80c785e24be4a8ce02d0b38a0ba5484a">dwc_otg_attr.c</a></ul>
+<h3><a class="anchor" name="index_u">- u -</a></h3><ul>
+<li>UPACKED
+: <a class="el" href="dwc__otg__cfi_8h.html#289004a802a0ba1d6ccaf6c6969f4e3f">dwc_otg_cfi.h</a>, <a class="el" href="dwc__cfi__common_8h.html#6c83e2952dc5636d5cfc5336217dcfcd">dwc_cfi_common.h</a></ul>
+<h3><a class="anchor" name="index_w">- w -</a></h3><ul>
+<li>wr_reg_test
+: <a class="el" href="dwc__otg__attr_8c.html#b46682cc35d8ddece607cdf93c124575">dwc_otg_attr.c</a><li>wr_reg_test_show
+: <a class="el" href="dwc__otg__attr_8c.html#9dd7132e3f334eed0e27e11ab5f7b0c4">dwc_otg_attr.c</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/index.html b/drivers/usb/host/dwc_otg/doc/html/index.html
new file mode 100644
index 000000000000..97a0b4709533
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/index.html
@@ -0,0 +1,8 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver</title></head>
+<frameset cols="250,*">
+  <frame src="tree.html" name="treefrm">
+  <frame src="main.html" name="basefrm">
+</frameset>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/linux module attributes.html b/drivers/usb/host/dwc_otg/doc/html/linux module attributes.html
new file mode 100644
index 000000000000..662d114c5b0e
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/linux module attributes.html	
@@ -0,0 +1,130 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: </title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+The Linux module attributes feature is used to provide the Linux Diagnostic Interface.<p>
+These attributes are accessed through sysfs. The diagnostic interface will provide access to the controller for bringing up the hardware and testing.<p>
+The following table shows the attributes. <table border="1" cellspacing="3" cellpadding="3">
+<tr>
+<td><b> Name</b> </td><td><b> Description</b> </td><td><b> Access</b> <p>
+</td></tr>
+<tr>
+<td>mode  </td><td>Returns the current mode: 0 for device mode, 1 for host mode </td><td>Read <p>
+</td></tr>
+<tr>
+<td>hnpcapable  </td><td>Gets or sets the "HNP-capable" bit in the Core USB Configuraton Register. Read returns the current value. </td><td>Read/Write <p>
+</td></tr>
+<tr>
+<td>srpcapable  </td><td>Gets or sets the "SRP-capable" bit in the Core USB Configuraton Register. Read returns the current value. </td><td>Read/Write <p>
+</td></tr>
+<tr>
+<td>hsic_connect  </td><td>Gets or sets the "HSIC-Connect" bit in the GLPMCFG Register. Read returns the current value. </td><td>Read/Write <p>
+</td></tr>
+<tr>
+<td>inv_sel_hsic  </td><td>Gets or sets the "Invert Select HSIC" bit in the GLPMFG Register. Read returns the current value. </td><td>Read/Write <p>
+</td></tr>
+<tr>
+<td>hnp  </td><td>Initiates the Host Negotiation Protocol. Read returns the status. </td><td>Read/Write <p>
+</td></tr>
+<tr>
+<td>srp  </td><td>Initiates the Session Request Protocol. Read returns the status. </td><td>Read/Write <p>
+</td></tr>
+<tr>
+<td>buspower  </td><td>Gets or sets the Power State of the bus (0 - Off or 1 - On) </td><td>Read/Write <p>
+</td></tr>
+<tr>
+<td>bussuspend  </td><td>Suspends the USB bus. </td><td>Read/Write <p>
+</td></tr>
+<tr>
+<td>busconnected  </td><td>Gets the connection status of the bus </td><td>Read <p>
+</td></tr>
+<tr>
+<td>gotgctl  </td><td>Gets or sets the Core Control Status Register. </td><td>Read/Write <p>
+</td></tr>
+<tr>
+<td>gusbcfg  </td><td>Gets or sets the Core USB Configuration Register </td><td>Read/Write <p>
+</td></tr>
+<tr>
+<td>grxfsiz  </td><td>Gets or sets the Receive FIFO Size Register </td><td>Read/Write <p>
+</td></tr>
+<tr>
+<td>gnptxfsiz  </td><td>Gets or sets the non-periodic Transmit Size Register </td><td>Read/Write <p>
+</td></tr>
+<tr>
+<td>gpvndctl  </td><td>Gets or sets the PHY Vendor Control Register </td><td>Read/Write <p>
+</td></tr>
+<tr>
+<td>ggpio  </td><td>Gets the value in the lower 16-bits of the General Purpose IO Register or sets the upper 16 bits. </td><td>Read/Write <p>
+</td></tr>
+<tr>
+<td>guid  </td><td>Gets or sets the value of the User ID Register </td><td>Read/Write <p>
+</td></tr>
+<tr>
+<td>gsnpsid  </td><td>Gets the value of the Synopsys ID Regester </td><td>Read <p>
+</td></tr>
+<tr>
+<td>devspeed  </td><td>Gets or sets the device speed setting in the DCFG register </td><td>Read/Write <p>
+</td></tr>
+<tr>
+<td>enumspeed  </td><td>Gets the device enumeration Speed. </td><td>Read <p>
+</td></tr>
+<tr>
+<td>hptxfsiz  </td><td>Gets the value of the Host Periodic Transmit FIFO </td><td>Read <p>
+</td></tr>
+<tr>
+<td>hprt0  </td><td>Gets or sets the value in the Host Port Control and Status Register </td><td>Read/Write <p>
+</td></tr>
+<tr>
+<td>regoffset  </td><td>Sets the register offset for the next Register Access </td><td>Read/Write <p>
+</td></tr>
+<tr>
+<td>regvalue  </td><td>Gets or sets the value of the register at the offset in the regoffset attribute. </td><td>Read/Write <p>
+</td></tr>
+<tr>
+<td>remote_wakeup  </td><td>On read, shows the status of Remote Wakeup. On write, initiates a remote wakeup of the host. When bit 0 is 1 and Remote Wakeup is enabled, the Remote Wakeup signalling bit in the Device Control Register is set for 1 milli-second. </td><td>Read/Write <p>
+</td></tr>
+<tr>
+<td>regdump  </td><td>Dumps the contents of core registers. </td><td>Read <p>
+</td></tr>
+<tr>
+<td>spramdump  </td><td>Dumps the contents of core registers. </td><td>Read <p>
+</td></tr>
+<tr>
+<td>hcddump  </td><td>Dumps the current HCD state. </td><td>Read <p>
+</td></tr>
+<tr>
+<td>hcd_frrem  </td><td>Shows the average value of the Frame Remaining field in the Host Frame Number/Frame Remaining register when an SOF interrupt occurs. This can be used to determine the average interrupt latency. Also shows the average Frame Remaining value for start_transfer and the "a" and "b" sample points. The "a" and "b" sample points may be used during debugging bto determine how long it takes to execute a section of the HCD code. </td><td>Read <p>
+</td></tr>
+<tr>
+<td>rd_reg_test  </td><td>Displays the time required to read the GNPTXFSIZ register many times (the output shows the number of times the register is read). </td><td>Read <p>
+</td></tr>
+<tr>
+<td>wr_reg_test  </td><td>Displays the time required to write the GNPTXFSIZ register many times (the output shows the number of times the register is written). </td><td>Read <p>
+</td></tr>
+<tr>
+<td>lpm_response  </td><td>Gets or sets lpm_response mode. Applicable only in device mode. </td><td>Write <p>
+</td></tr>
+<tr>
+<td>sleep_local_dev  </td><td>Generetates sleep signaling. Applicable only in host mode. </td><td>Write <p>
+</td></tr>
+<tr>
+<td>sleep_status  </td><td>Shows sleep status of device. </td><td>Read <p>
+</td></tr>
+</table>
+<p>
+Example usage: To get the current mode: cat /sys/devices/lm0/mode<p>
+To power down the USB: echo 0 &gt; /sys/devices/lm0/buspower <hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/main.html b/drivers/usb/host/dwc_otg/doc/html/main.html
new file mode 100644
index 000000000000..aa55c25ed77e
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/main.html
@@ -0,0 +1,21 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Main Page</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li id="current"><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<h1>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver Documentation</h1>
+<p>
+<h3 align="center">v2.90a </h3><hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/module parameters.html b/drivers/usb/host/dwc_otg/doc/html/module parameters.html
new file mode 100644
index 000000000000..871a210e4fd3
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/module parameters.html	
@@ -0,0 +1,189 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: </title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+The following parameters may be specified when starting the module.<p>
+These parameters define how the DWC_otg controller should be configured. Parameter values are passed to the CIL initialization function dwc_otg_cil_init<p>
+Example: <code>modprobe dwc_otg speed=1 otg_cap=1</code><p>
+<table border="1" cellspacing="3" cellpadding="3">
+<tr>
+<td>Parameter Name</td><td>Meaning<p>
+</td></tr>
+<tr>
+<td>otg_cap </td><td>Specifies the OTG capabilities. The driver will automatically detect the value for this parameter if none is specified.<ul>
+<li>0: HNP and SRP capable (default, if available)</li><li>1: SRP Only capable</li><li>2: No HNP/SRP capable </li></ul>
+<p>
+</td></tr>
+<tr>
+<td>dma_enable </td><td>Specifies whether to use slave or DMA mode for accessing the data FIFOs. The driver will automatically detect the value for this parameter if none is specified.<ul>
+<li>0: Slave</li><li>1: DMA (default, if available) </li></ul>
+<p>
+</td></tr>
+<tr>
+<td>dma_burst_size </td><td>The DMA Burst size (applicable only for External DMA Mode).<ul>
+<li>Values: 1, 4, 8 16, 32, 64, 128, 256 (default 32) </li></ul>
+<p>
+</td></tr>
+<tr>
+<td>speed </td><td>Specifies the maximum speed of operation in host and device mode. The actual speed depends on the speed of the attached device and the value of phy_type.<ul>
+<li>0: High Speed (default)</li><li>1: Full Speed </li></ul>
+<p>
+</td></tr>
+<tr>
+<td>host_support_fs_ls_low_power </td><td>Specifies whether low power mode is supported when attached to a Full Speed or Low Speed device in host mode.<ul>
+<li>0: Don't support low power mode (default)</li><li>1: Support low power mode </li></ul>
+<p>
+</td></tr>
+<tr>
+<td>host_ls_low_power_phy_clk </td><td>Specifies the PHY clock rate in low power mode when connected to a Low Speed device in host mode. This parameter is applicable only if HOST_SUPPORT_FS_LS_LOW_POWER is enabled.<ul>
+<li>0: 48 MHz (default)</li><li>1: 6 MHz </li></ul>
+<p>
+</td></tr>
+<tr>
+<td>enable_dynamic_fifo </td><td>Specifies whether FIFOs may be resized by the driver software.<ul>
+<li>0: Use cC FIFO size parameters</li><li>1: Allow dynamic FIFO sizing (default) </li></ul>
+<p>
+</td></tr>
+<tr>
+<td>data_fifo_size </td><td>Total number of 4-byte words in the data FIFO memory. This memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs.<ul>
+<li>Values: 32 to 32768 (default 8192)</li></ul>
+<p>
+Note: The total FIFO memory depth in the FPGA configuration is 8192. <p>
+</td></tr>
+<tr>
+<td>dev_rx_fifo_size </td><td>Number of 4-byte words in the Rx FIFO in device mode when dynamic FIFO sizing is enabled.<ul>
+<li>Values: 16 to 32768 (default 1064) </li></ul>
+<p>
+</td></tr>
+<tr>
+<td>dev_nperio_tx_fifo_size </td><td>Number of 4-byte words in the non-periodic Tx FIFO in device mode when dynamic FIFO sizing is enabled.<ul>
+<li>Values: 16 to 32768 (default 1024) </li></ul>
+<p>
+</td></tr>
+<tr>
+<td>dev_perio_tx_fifo_size_n (n = 1 to 15) </td><td>Number of 4-byte words in each of the periodic Tx FIFOs in device mode when dynamic FIFO sizing is enabled.<ul>
+<li>Values: 4 to 768 (default 256) </li></ul>
+<p>
+</td></tr>
+<tr>
+<td>host_rx_fifo_size </td><td>Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO sizing is enabled.<ul>
+<li>Values: 16 to 32768 (default 1024) </li></ul>
+<p>
+</td></tr>
+<tr>
+<td>host_nperio_tx_fifo_size </td><td>Number of 4-byte words in the non-periodic Tx FIFO in host mode when dynamic FIFO sizing is enabled in the core.<ul>
+<li>Values: 16 to 32768 (default 1024) </li></ul>
+<p>
+</td></tr>
+<tr>
+<td>host_perio_tx_fifo_size </td><td>Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO sizing is enabled.<ul>
+<li>Values: 16 to 32768 (default 1024) </li></ul>
+<p>
+</td></tr>
+<tr>
+<td>max_transfer_size </td><td>The maximum transfer size supported in bytes.<ul>
+<li>Values: 2047 to 65,535 (default 65,535) </li></ul>
+<p>
+</td></tr>
+<tr>
+<td>max_packet_count </td><td>The maximum number of packets in a transfer.<ul>
+<li>Values: 15 to 511 (default 511) </li></ul>
+<p>
+</td></tr>
+<tr>
+<td>host_channels </td><td>The number of host channel registers to use.<ul>
+<li>Values: 1 to 16 (default 12)</li></ul>
+<p>
+Note: The FPGA configuration supports a maximum of 12 host channels. <p>
+</td></tr>
+<tr>
+<td>dev_endpoints </td><td>The number of endpoints in addition to EP0 available for device mode operations.<ul>
+<li>Values: 1 to 15 (default 6 IN and OUT)</li></ul>
+<p>
+Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in addition to EP0. <p>
+</td></tr>
+<tr>
+<td>phy_type </td><td>Specifies the type of PHY interface to use. By default, the driver will automatically detect the phy_type.<ul>
+<li>0: Full Speed</li><li>1: UTMI+ (default, if available)</li><li>2: ULPI </li></ul>
+<p>
+</td></tr>
+<tr>
+<td>phy_utmi_width </td><td>Specifies the UTMI+ Data Width. This parameter is applicable for a phy_type of UTMI+. Also, this parameter is applicable only if the OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the core has been configured to work at either data path width.<ul>
+<li>Values: 8 or 16 bits (default 16) </li></ul>
+<p>
+</td></tr>
+<tr>
+<td>phy_ulpi_ddr </td><td>Specifies whether the ULPI operates at double or single data rate. This parameter is only applicable if phy_type is ULPI.<ul>
+<li>0: single data rate ULPI interface with 8 bit wide data bus (default)</li><li>1: double data rate ULPI interface with 4 bit wide data bus </li></ul>
+<p>
+</td></tr>
+<tr>
+<td>i2c_enable </td><td>Specifies whether to use the I2C interface for full speed PHY. This parameter is only applicable if PHY_TYPE is FS.<ul>
+<li>0: Disabled (default)</li><li>1: Enabled </li></ul>
+<p>
+</td></tr>
+<tr>
+<td>otg_en_multiple_tx_fifo </td><td>Specifies whether dedicatedto tx fifos are enabled for non periodic IN EPs. The driver will automatically detect the value for this parameter if none is specified.<ul>
+<li>0: Disabled</li><li>1: Enabled (default, if available) </li></ul>
+<p>
+</td></tr>
+<tr>
+<td>dev_tx_fifo_size_n (n = 1 to 15) </td><td>Number of 4-byte words in each of the Tx FIFOs in device mode when dynamic FIFO sizing is enabled.<ul>
+<li>Values: 4 to 768 (default 256) </li></ul>
+<p>
+</td></tr>
+<tr>
+<td>tx_thr_length </td><td>Transmit Threshold length in 32 bit double words<ul>
+<li>Values: 8 to 128 (default 64) </li></ul>
+<p>
+</td></tr>
+<tr>
+<td>rx_thr_length </td><td>Receive Threshold length in 32 bit double words<ul>
+<li>Values: 8 to 128 (default 64) </li></ul>
+<p>
+</td></tr>
+<tr>
+<td>thr_ctl </td><td>Specifies whether to enable Thresholding for Device mode. Bits 0, 1, 2 of this parmater specifies if thresholding is enabled for non-Iso Tx, Iso Tx and Rx transfers accordingly. The driver will automatically detect the value for this parameter if none is specified.<ul>
+<li>Values: 0 to 7 (default 0) Bit values indicate:</li><li>0: Thresholding disabled</li><li>1: Thresholding enabled </li></ul>
+<p>
+</td></tr>
+<tr>
+<td>dma_desc_enable </td><td>Specifies whether to enable Descriptor DMA mode. The driver will automatically detect the value for this parameter if none is specified.<ul>
+<li>0: Descriptor DMA disabled</li><li>1: Descriptor DMA (default, if available) </li></ul>
+<p>
+</td></tr>
+<tr>
+<td>mpi_enable </td><td>Specifies whether to enable MPI enhancement mode. The driver will automatically detect the value for this parameter if none is specified.<ul>
+<li>0: MPI disabled (default)</li><li>1: MPI enable </li></ul>
+<p>
+</td></tr>
+<tr>
+<td>pti_enable </td><td>Specifies whether to enable PTI enhancement support. The driver will automatically detect the value for this parameter if none is specified.<ul>
+<li>0: PTI disabled (default)</li><li>1: PTI enable </li></ul>
+<p>
+</td></tr>
+<tr>
+<td>lpm_enable </td><td>Specifies whether to enable LPM support. The driver will automatically detect the value for this parameter if none is specified.<ul>
+<li>0: LPM disabled</li><li>1: LPM enable (default, if available) </li></ul>
+<p>
+</td></tr>
+<tr>
+<td>ahb_thr_ratio </td><td>Specifies AHB Threshold ratio.<ul>
+<li>Values: 0 to 3 (default 0)  </li></ul>
+</td></tr>
+</table>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/pages.html b/drivers/usb/host/dwc_otg/doc/html/pages.html
new file mode 100644
index 000000000000..5442a60ef243
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/pages.html
@@ -0,0 +1,27 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Page Index</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li id="current"><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<h1>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver Related Pages</h1>Here is a list of all related documentation pages:<ul>
+<li><a class="el" href="linux module attributes.html">Linux Module Attributes</a>
+
+<li><a class="el" href="module parameters.html">Module Parameters</a>
+
+<li><a class="el" href="todo.html">Todo List</a>
+
+</ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:50 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/struct__ddma__align__buffer__setup.html b/drivers/usb/host/dwc_otg/doc/html/struct__ddma__align__buffer__setup.html
new file mode 100644
index 000000000000..d640bc24801b
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/struct__ddma__align__buffer__setup.html
@@ -0,0 +1,46 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: _ddma_align_buffer_setup Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>_ddma_align_buffer_setup Struct Reference</h1><!-- doxytag: class="_ddma_align_buffer_setup" -->Descriptor DMA Alignment Buffer setup structure.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__cfi_8h-source.html">dwc_otg_cfi.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="28008cbe6479b7473aa21ac2d3ceaf67"></a><!-- doxytag: member="_ddma_align_buffer_setup::bEndpointAddress" ref="28008cbe6479b7473aa21ac2d3ceaf67" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct__ddma__align__buffer__setup.html#28008cbe6479b7473aa21ac2d3ceaf67">bEndpointAddress</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="1cc0ba7e2c2a435cce1d502732ce07a1"></a><!-- doxytag: member="_ddma_align_buffer_setup::bAlign" ref="1cc0ba7e2c2a435cce1d502732ce07a1" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct__ddma__align__buffer__setup.html#1cc0ba7e2c2a435cce1d502732ce07a1">bAlign</a></td></tr>
+
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+Descriptor DMA Alignment Buffer setup structure. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cfi_8h-source.html#l00115">115</a> of file <a class="el" href="dwc__otg__cfi_8h-source.html">dwc_otg_cfi.h</a>.<hr>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__cfi_8h-source.html">dwc_otg_cfi.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/struct__ddma__concat__buffer__setup.html b/drivers/usb/host/dwc_otg/doc/html/struct__ddma__concat__buffer__setup.html
new file mode 100644
index 000000000000..b8ec739cf78b
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/struct__ddma__concat__buffer__setup.html
@@ -0,0 +1,46 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: _ddma_concat_buffer_setup Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>_ddma_concat_buffer_setup Struct Reference</h1><!-- doxytag: class="_ddma_concat_buffer_setup" -->Descriptor DMA Concatenation Buffer setup structure.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__cfi_8h-source.html">dwc_otg_cfi.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="512cdc8b5ef9053f514443b884ec4730"></a><!-- doxytag: member="_ddma_concat_buffer_setup::hdr" ref="512cdc8b5ef9053f514443b884ec4730" args="" -->
+<a class="el" href="struct__ddma__concat__buffer__setup__hdr.html">ddma_concat_buffer_setup_hdr_t</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct__ddma__concat__buffer__setup.html#512cdc8b5ef9053f514443b884ec4730">hdr</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="748241a5b55a514f4386498aceb1e505"></a><!-- doxytag: member="_ddma_concat_buffer_setup::wTxBytes" ref="748241a5b55a514f4386498aceb1e505" args="" -->
+uint16_t *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct__ddma__concat__buffer__setup.html#748241a5b55a514f4386498aceb1e505">wTxBytes</a></td></tr>
+
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+Descriptor DMA Concatenation Buffer setup structure. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cfi_8h-source.html#l00105">105</a> of file <a class="el" href="dwc__otg__cfi_8h-source.html">dwc_otg_cfi.h</a>.<hr>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__cfi_8h-source.html">dwc_otg_cfi.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/struct__ddma__concat__buffer__setup__hdr.html b/drivers/usb/host/dwc_otg/doc/html/struct__ddma__concat__buffer__setup__hdr.html
new file mode 100644
index 000000000000..969f0b9ee9d2
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/struct__ddma__concat__buffer__setup__hdr.html
@@ -0,0 +1,49 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: _ddma_concat_buffer_setup_hdr Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>_ddma_concat_buffer_setup_hdr Struct Reference</h1><!-- doxytag: class="_ddma_concat_buffer_setup_hdr" -->Descriptor DMA Concatenation Buffer setup structure.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__cfi_8h-source.html">dwc_otg_cfi.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b6e4aab1ee8884a314ba38326ea85f24"></a><!-- doxytag: member="_ddma_concat_buffer_setup_hdr::bEndpointAddress" ref="b6e4aab1ee8884a314ba38326ea85f24" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct__ddma__concat__buffer__setup__hdr.html#b6e4aab1ee8884a314ba38326ea85f24">bEndpointAddress</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="605becc1e8a681d6623343b28013b56a"></a><!-- doxytag: member="_ddma_concat_buffer_setup_hdr::bDescCount" ref="605becc1e8a681d6623343b28013b56a" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct__ddma__concat__buffer__setup__hdr.html#605becc1e8a681d6623343b28013b56a">bDescCount</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="d59713609608ce8aab53c43332073ef7"></a><!-- doxytag: member="_ddma_concat_buffer_setup_hdr::wSize" ref="d59713609608ce8aab53c43332073ef7" args="" -->
+uint16_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct__ddma__concat__buffer__setup__hdr.html#d59713609608ce8aab53c43332073ef7">wSize</a></td></tr>
+
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+Descriptor DMA Concatenation Buffer setup structure. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cfi_8h-source.html#l00093">93</a> of file <a class="el" href="dwc__otg__cfi_8h-source.html">dwc_otg_cfi.h</a>.<hr>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__cfi_8h-source.html">dwc_otg_cfi.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/struct__ddma__sg__buffer__setup.html b/drivers/usb/host/dwc_otg/doc/html/struct__ddma__sg__buffer__setup.html
new file mode 100644
index 000000000000..f650509c785a
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/struct__ddma__sg__buffer__setup.html
@@ -0,0 +1,57 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: _ddma_sg_buffer_setup Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>_ddma_sg_buffer_setup Struct Reference</h1><!-- doxytag: class="_ddma_sg_buffer_setup" -->Descriptor DMA SG Buffer setup structure (SG buffer).  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__cfi_8h-source.html">dwc_otg_cfi.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b61eaff3e4857fd6223d9fc678814786"></a><!-- doxytag: member="_ddma_sg_buffer_setup::bOutEndpointAddress" ref="b61eaff3e4857fd6223d9fc678814786" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct__ddma__sg__buffer__setup.html#b61eaff3e4857fd6223d9fc678814786">bOutEndpointAddress</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="bb435a2ac72bfd26384c9b5b1b0b35af"></a><!-- doxytag: member="_ddma_sg_buffer_setup::bInEndpointAddress" ref="bb435a2ac72bfd26384c9b5b1b0b35af" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct__ddma__sg__buffer__setup.html#bb435a2ac72bfd26384c9b5b1b0b35af">bInEndpointAddress</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="5ab16a208d20dd6940ecfd3244e2b9c0"></a><!-- doxytag: member="_ddma_sg_buffer_setup::bOffset" ref="5ab16a208d20dd6940ecfd3244e2b9c0" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct__ddma__sg__buffer__setup.html#5ab16a208d20dd6940ecfd3244e2b9c0">bOffset</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="6287daf5a964bf1d09e8ffca29b88748"></a><!-- doxytag: member="_ddma_sg_buffer_setup::bCount" ref="6287daf5a964bf1d09e8ffca29b88748" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct__ddma__sg__buffer__setup.html#6287daf5a964bf1d09e8ffca29b88748">bCount</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="728db9bac2db62f7e7b2b9ccb0873546"></a><!-- doxytag: member="_ddma_sg_buffer_setup::wSize" ref="728db9bac2db62f7e7b2b9ccb0873546" args="" -->
+uint16_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct__ddma__sg__buffer__setup.html#728db9bac2db62f7e7b2b9ccb0873546">wSize</a></td></tr>
+
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+Descriptor DMA SG Buffer setup structure (SG buffer). 
+<p>
+This structure is also used for setting up a buffer for Circular DDMA. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cfi_8h-source.html#l00077">77</a> of file <a class="el" href="dwc__otg__cfi_8h-source.html">dwc_otg_cfi.h</a>.<hr>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__cfi_8h-source.html">dwc_otg_cfi.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/struct__rx__fifo__size__setup.html b/drivers/usb/host/dwc_otg/doc/html/struct__rx__fifo__size__setup.html
new file mode 100644
index 000000000000..6c8b1e69b128
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/struct__rx__fifo__size__setup.html
@@ -0,0 +1,43 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: _rx_fifo_size_setup Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>_rx_fifo_size_setup Struct Reference</h1><!-- doxytag: class="_rx_fifo_size_setup" -->Transmit FIFO Size setup structure.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__cfi_8h-source.html">dwc_otg_cfi.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="a05d30e9417ac8c2ec0fd2c1ec49be71"></a><!-- doxytag: member="_rx_fifo_size_setup::wDepth" ref="a05d30e9417ac8c2ec0fd2c1ec49be71" args="" -->
+uint16_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct__rx__fifo__size__setup.html#a05d30e9417ac8c2ec0fd2c1ec49be71">wDepth</a></td></tr>
+
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+Transmit FIFO Size setup structure. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cfi_8h-source.html#l00130">130</a> of file <a class="el" href="dwc__otg__cfi_8h-source.html">dwc_otg_cfi.h</a>.<hr>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__cfi_8h-source.html">dwc_otg_cfi.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/struct__tx__fifo__size__setup.html b/drivers/usb/host/dwc_otg/doc/html/struct__tx__fifo__size__setup.html
new file mode 100644
index 000000000000..1a4bd244a753
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/struct__tx__fifo__size__setup.html
@@ -0,0 +1,46 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: _tx_fifo_size_setup Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>_tx_fifo_size_setup Struct Reference</h1><!-- doxytag: class="_tx_fifo_size_setup" -->Transmit FIFO Size setup structure.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__cfi_8h-source.html">dwc_otg_cfi.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c04a19a9c0c93d385f7ea42ed38ba0a6"></a><!-- doxytag: member="_tx_fifo_size_setup::bEndpointAddress" ref="c04a19a9c0c93d385f7ea42ed38ba0a6" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct__tx__fifo__size__setup.html#c04a19a9c0c93d385f7ea42ed38ba0a6">bEndpointAddress</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="70fb102a57e335dd8ee56096f3a9f99d"></a><!-- doxytag: member="_tx_fifo_size_setup::wDepth" ref="70fb102a57e335dd8ee56096f3a9f99d" args="" -->
+uint16_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct__tx__fifo__size__setup.html#70fb102a57e335dd8ee56096f3a9f99d">wDepth</a></td></tr>
+
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+Transmit FIFO Size setup structure. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cfi_8h-source.html#l00123">123</a> of file <a class="el" href="dwc__otg__cfi_8h-source.html">dwc_otg_cfi.h</a>.<hr>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__cfi_8h-source.html">dwc_otg_cfi.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/structcfi__all__features__header.html b/drivers/usb/host/dwc_otg/doc/html/structcfi__all__features__header.html
new file mode 100644
index 000000000000..c1ed3606d2cd
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/structcfi__all__features__header.html
@@ -0,0 +1,75 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: cfi_all_features_header Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>cfi_all_features_header Struct Reference</h1><!-- doxytag: class="cfi_all_features_header" -->This structure is the header of the Core Features dataset returned to the Host.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__cfi__common_8h-source.html">dwc_cfi_common.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3973fa190311671de5bbd74a7b825f42"></a><!-- doxytag: member="cfi_all_features_header::wTotalLen" ref="3973fa190311671de5bbd74a7b825f42" args="" -->
+uint16_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcfi__all__features__header.html#3973fa190311671de5bbd74a7b825f42">wTotalLen</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">The total length of the features dataset returned to the Host. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint16_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcfi__all__features__header.html#3542d584c0c68a73351c7d2530f25c6d">wVersion</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">CFI version number inBinary-Coded Decimal (i.e., 1.00 is 100H).  <a href="#3542d584c0c68a73351c7d2530f25c6d"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f6840858aad78617369b7decba6ef5e3"></a><!-- doxytag: member="cfi_all_features_header::wCoreID" ref="f6840858aad78617369b7decba6ef5e3" args="" -->
+uint16_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcfi__all__features__header.html#f6840858aad78617369b7decba6ef5e3">wCoreID</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">The ID of the Core. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e7abb90105e5cfd6ddfe8ba5dfaf8fa1"></a><!-- doxytag: member="cfi_all_features_header::wNumFeatures" ref="e7abb90105e5cfd6ddfe8ba5dfaf8fa1" args="" -->
+uint16_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcfi__all__features__header.html#e7abb90105e5cfd6ddfe8ba5dfaf8fa1">wNumFeatures</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Number of features returned by VEN_CORE_GET_FEATURES request. <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This structure is the header of the Core Features dataset returned to the Host. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__cfi__common_8h-source.html#l00069">69</a> of file <a class="el" href="dwc__cfi__common_8h-source.html">dwc_cfi_common.h</a>.<hr><h2>Field Documentation</h2>
+<a class="anchor" name="3542d584c0c68a73351c7d2530f25c6d"></a><!-- doxytag: member="cfi_all_features_header::wVersion" ref="3542d584c0c68a73351c7d2530f25c6d" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint16_t <a class="el" href="structcfi__all__features__header.html#3542d584c0c68a73351c7d2530f25c6d">cfi_all_features_header::wVersion</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+CFI version number inBinary-Coded Decimal (i.e., 1.00 is 100H). 
+<p>
+This field identifies the version of the CFI Specification with which the device is compliant. 
+<p>
+Definition at line <a class="el" href="dwc__cfi__common_8h-source.html#l00082">82</a> of file <a class="el" href="dwc__cfi__common_8h-source.html">dwc_cfi_common.h</a>.
+</div>
+</div><p>
+<hr>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dwc__cfi__common_8h-source.html">dwc_cfi_common.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/structcfi__dma__buff.html b/drivers/usb/host/dwc_otg/doc/html/structcfi__dma__buff.html
new file mode 100644
index 000000000000..866833db3b19
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/structcfi__dma__buff.html
@@ -0,0 +1,41 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: cfi_dma_buff Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>cfi_dma_buff Struct Reference</h1><!-- doxytag: class="cfi_dma_buff" --><table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="549d40f7e33056fc5a99d51d00714d97"></a><!-- doxytag: member="cfi_dma_buff::addr" ref="549d40f7e33056fc5a99d51d00714d97" args="" -->
+dma_addr_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcfi__dma__buff.html#549d40f7e33056fc5a99d51d00714d97">addr</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="474851b3123373b8b30fa3637eb81b5b"></a><!-- doxytag: member="cfi_dma_buff::buf" ref="474851b3123373b8b30fa3637eb81b5b" args="" -->
+uint8_t *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcfi__dma__buff.html#474851b3123373b8b30fa3637eb81b5b">buf</a></td></tr>
+
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cfi_8h-source.html#l00182">182</a> of file <a class="el" href="dwc__otg__cfi_8h-source.html">dwc_otg_cfi.h</a>.<hr>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__cfi_8h-source.html">dwc_otg_cfi.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/structcfi__ep.html b/drivers/usb/host/dwc_otg/doc/html/structcfi__ep.html
new file mode 100644
index 000000000000..cdf155909a0b
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/structcfi__ep.html
@@ -0,0 +1,69 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: cfi_ep Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>cfi_ep Struct Reference</h1><!-- doxytag: class="cfi_ep" -->The CFI wrapper of the enabled and activated <a class="el" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep</a> structures.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__cfi_8h-source.html">dwc_otg_cfi.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="18bff3370dc933cd374d458897dfbc2f"></a><!-- doxytag: member="cfi_ep::lh" ref="18bff3370dc933cd374d458897dfbc2f" args="" -->
+dwc_list_link_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcfi__ep.html#18bff3370dc933cd374d458897dfbc2f">lh</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="07c11a23c68b5ce8d546819211b2fa4b"></a><!-- doxytag: member="cfi_ep::ep" ref="07c11a23c68b5ce8d546819211b2fa4b" args="" -->
+<a class="el" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcfi__ep.html#07c11a23c68b5ce8d546819211b2fa4b">ep</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3f4e5c42f279663ee0065ffce4f44783"></a><!-- doxytag: member="cfi_ep::dma_desc_last" ref="3f4e5c42f279663ee0065ffce4f44783" args="" -->
+dwc_otg_dma_desc *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcfi__ep.html#3f4e5c42f279663ee0065ffce4f44783">dma_desc_last</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="4010b0f12bf1cd37a2c0bf06b392570a"></a><!-- doxytag: member="cfi_ep::bm_sg" ref="4010b0f12bf1cd37a2c0bf06b392570a" args="" -->
+<a class="el" href="struct__ddma__sg__buffer__setup.html">ddma_sg_buffer_setup_t</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcfi__ep.html#4010b0f12bf1cd37a2c0bf06b392570a">bm_sg</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3ab8ca6103c0483f2fefce0dc1684eaa"></a><!-- doxytag: member="cfi_ep::bm_circ" ref="3ab8ca6103c0483f2fefce0dc1684eaa" args="" -->
+<a class="el" href="struct__ddma__sg__buffer__setup.html">ddma_sg_buffer_setup_t</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcfi__ep.html#3ab8ca6103c0483f2fefce0dc1684eaa">bm_circ</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="4c83b9bb5a75e6b81fbfa86b51736164"></a><!-- doxytag: member="cfi_ep::bm_concat" ref="4c83b9bb5a75e6b81fbfa86b51736164" args="" -->
+<a class="el" href="struct__ddma__concat__buffer__setup.html">ddma_concat_buffer_setup_t</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcfi__ep.html#4c83b9bb5a75e6b81fbfa86b51736164">bm_concat</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="bb544b7938d0c62857fc3726988310d2"></a><!-- doxytag: member="cfi_ep::bm_align" ref="bb544b7938d0c62857fc3726988310d2" args="" -->
+<a class="el" href="struct__ddma__align__buffer__setup.html">ddma_align_buffer_setup_t</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcfi__ep.html#bb544b7938d0c62857fc3726988310d2">bm_align</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f85903cb9e179124e42d98d557098011"></a><!-- doxytag: member="cfi_ep::xfer_len" ref="f85903cb9e179124e42d98d557098011" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcfi__ep.html#f85903cb9e179124e42d98d557098011">xfer_len</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="73050a3011b918e8be6c2434db357514"></a><!-- doxytag: member="cfi_ep::desc_count" ref="73050a3011b918e8be6c2434db357514" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcfi__ep.html#73050a3011b918e8be6c2434db357514">desc_count</a></td></tr>
+
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+The CFI wrapper of the enabled and activated <a class="el" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep</a> structures. 
+<p>
+This structure is used to store the buffer setup data for any enabled endpoint in the PCD. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cfi_8h-source.html#l00156">156</a> of file <a class="el" href="dwc__otg__cfi_8h-source.html">dwc_otg_cfi.h</a>.<hr>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__cfi_8h-source.html">dwc_otg_cfi.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/structcfi__feature__desc__header.html b/drivers/usb/host/dwc_otg/doc/html/structcfi__feature__desc__header.html
new file mode 100644
index 000000000000..557f335cb07d
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/structcfi__feature__desc__header.html
@@ -0,0 +1,60 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: cfi_feature_desc_header Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>cfi_feature_desc_header Struct Reference</h1><!-- doxytag: class="cfi_feature_desc_header" -->This structure is a header of the Core Feature descriptor dataset returned to the Host after the VEN_CORE_GET_FEATURES request.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__cfi__common_8h-source.html">dwc_cfi_common.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f76e757383a5210368e599f872952170"></a><!-- doxytag: member="cfi_feature_desc_header::wFeatureID" ref="f76e757383a5210368e599f872952170" args="" -->
+uint16_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcfi__feature__desc__header.html#f76e757383a5210368e599f872952170">wFeatureID</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">The feature ID. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="77769436c06687bdbe98c5e75e7641df"></a><!-- doxytag: member="cfi_feature_desc_header::wLength" ref="77769436c06687bdbe98c5e75e7641df" args="" -->
+uint16_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcfi__feature__desc__header.html#77769436c06687bdbe98c5e75e7641df">wLength</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Length of this feature descriptor in bytes - including the length of the feature name string. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="0f33193eaf5853b1d3454adce81105d4"></a><!-- doxytag: member="cfi_feature_desc_header::wDataLength" ref="0f33193eaf5853b1d3454adce81105d4" args="" -->
+uint16_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcfi__feature__desc__header.html#0f33193eaf5853b1d3454adce81105d4">wDataLength</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">The data length of this feature in bytes. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="556f5723d7ed0a9c6a1260b1f2a3fd30"></a><!-- doxytag: member="cfi_feature_desc_header::bmAttributes" ref="556f5723d7ed0a9c6a1260b1f2a3fd30" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcfi__feature__desc__header.html#556f5723d7ed0a9c6a1260b1f2a3fd30">bmAttributes</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Attributes of this features D0: Access rights 0 - Read/Write 1 - Read only. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="4e90b7a616a2efc24937fc6d5cff1347"></a><!-- doxytag: member="cfi_feature_desc_header::bNameLen" ref="4e90b7a616a2efc24937fc6d5cff1347" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcfi__feature__desc__header.html#4e90b7a616a2efc24937fc6d5cff1347">bNameLen</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Length of the feature name in bytes. <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This structure is a header of the Core Feature descriptor dataset returned to the Host after the VEN_CORE_GET_FEATURES request. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__cfi__common_8h-source.html#l00099">99</a> of file <a class="el" href="dwc__cfi__common_8h-source.html">dwc_cfi_common.h</a>.<hr>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dwc__cfi__common_8h-source.html">dwc_cfi_common.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/structcfi__ops.html b/drivers/usb/host/dwc_otg/doc/html/structcfi__ops.html
new file mode 100644
index 000000000000..734204644f81
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/structcfi__ops.html
@@ -0,0 +1,64 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: cfi_ops Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>cfi_ops Struct Reference</h1><!-- doxytag: class="cfi_ops" -->This is the interface for the CFI operations.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__cfi_8h-source.html">dwc_otg_cfi.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="1da60799de5a3a4ab53c63e1778e08af"></a><!-- doxytag: member="cfi_ops::ep_enable" ref="1da60799de5a3a4ab53c63e1778e08af" args=")(struct cfiobject *cfi, struct dwc_otg_pcd *pcd, struct dwc_otg_pcd_ep *ep)" -->
+int(*&nbsp;</td><td class="memItemRight" valign="bottom"><b>ep_enable</b> )(struct <a class="el" href="structcfiobject.html">cfiobject</a> *cfi, struct <a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd</a> *pcd, struct <a class="el" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep</a> *ep)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="0f57d061a80c9e04eeff9c960637595f"></a><!-- doxytag: member="cfi_ops::ep_alloc_buf" ref="0f57d061a80c9e04eeff9c960637595f" args=")(struct cfiobject *cfi, struct dwc_otg_pcd *pcd, struct dwc_otg_pcd_ep *ep, dma_addr_t *dma, unsigned size, gfp_t flags)" -->
+void *(*&nbsp;</td><td class="memItemRight" valign="bottom"><b>ep_alloc_buf</b> )(struct <a class="el" href="structcfiobject.html">cfiobject</a> *cfi, struct <a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd</a> *pcd, struct <a class="el" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep</a> *ep, dma_addr_t *dma, unsigned size, gfp_t flags)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="132fd4871260083bbd9945e121dc1819"></a><!-- doxytag: member="cfi_ops::release" ref="132fd4871260083bbd9945e121dc1819" args=")(struct cfiobject *cfi)" -->
+void(*&nbsp;</td><td class="memItemRight" valign="bottom"><b>release</b> )(struct <a class="el" href="structcfiobject.html">cfiobject</a> *cfi)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="a46d61a3e78632ab9ca2787b1025fee7"></a><!-- doxytag: member="cfi_ops::ctrl_write_complete" ref="a46d61a3e78632ab9ca2787b1025fee7" args=")(struct cfiobject *cfi, struct dwc_otg_pcd *pcd)" -->
+int(*&nbsp;</td><td class="memItemRight" valign="bottom"><b>ctrl_write_complete</b> )(struct <a class="el" href="structcfiobject.html">cfiobject</a> *cfi, struct <a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd</a> *pcd)</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="a3e763247b8fbedc46ddfa624408ab11"></a><!-- doxytag: member="cfi_ops::build_descriptors" ref="a3e763247b8fbedc46ddfa624408ab11" args=")(struct cfiobject *cfi, struct dwc_otg_pcd *pcd, struct dwc_otg_pcd_ep *ep, dwc_otg_pcd_request_t *req)" -->
+void(*&nbsp;</td><td class="memItemRight" valign="bottom"><b>build_descriptors</b> )(struct <a class="el" href="structcfiobject.html">cfiobject</a> *cfi, struct <a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd</a> *pcd, struct <a class="el" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep</a> *ep, <a class="el" href="structdwc__otg__pcd__request.html">dwc_otg_pcd_request_t</a> *req)</td></tr>
+
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This is the interface for the CFI operations. 
+<p>
+<dl compact><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>ep_enable</em>&nbsp;</td><td>Called when any endpoint is enabled and activated. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>release</em>&nbsp;</td><td>Called when the CFI object is released and it needs to correctly deallocate the dynamic memory </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>ctrl_write_complete</em>&nbsp;</td><td>Called when the data stage of the request is complete </td></tr>
+  </table>
+</dl>
+
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cfi_8h-source.html#l00199">199</a> of file <a class="el" href="dwc__otg__cfi_8h-source.html">dwc_otg_cfi.h</a>.<hr>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__cfi_8h-source.html">dwc_otg_cfi.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/structcfi__string.html b/drivers/usb/host/dwc_otg/doc/html/structcfi__string.html
new file mode 100644
index 000000000000..3b79640c5253
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/structcfi__string.html
@@ -0,0 +1,48 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: cfi_string Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>cfi_string Struct Reference</h1><!-- doxytag: class="cfi_string" -->This structure describes a NULL terminated string referenced by its id field.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__cfi__common_8h-source.html">dwc_cfi_common.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="dc88ed81d4ff35c7a1c837708659afea"></a><!-- doxytag: member="cfi_string::id" ref="dc88ed81d4ff35c7a1c837708659afea" args="" -->
+uint16_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcfi__string.html#dc88ed81d4ff35c7a1c837708659afea">id</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c852efd76029880787738fb474dd486e"></a><!-- doxytag: member="cfi_string::s" ref="c852efd76029880787738fb474dd486e" args="" -->
+const uint8_t *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcfi__string.html#c852efd76029880787738fb474dd486e">s</a></td></tr>
+
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This structure describes a NULL terminated string referenced by its id field. 
+<p>
+It is very similar to usb_string structure but has the id field type set to 16-bit. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__cfi__common_8h-source.html#l00136">136</a> of file <a class="el" href="dwc__cfi__common_8h-source.html">dwc_cfi_common.h</a>.<hr>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dwc__cfi__common_8h-source.html">dwc_cfi_common.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/structcfi__usb__ctrlrequest.html b/drivers/usb/host/dwc_otg/doc/html/structcfi__usb__ctrlrequest.html
new file mode 100644
index 000000000000..467657e84711
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/structcfi__usb__ctrlrequest.html
@@ -0,0 +1,58 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: cfi_usb_ctrlrequest Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>cfi_usb_ctrlrequest Struct Reference</h1><!-- doxytag: class="cfi_usb_ctrlrequest" -->struct <a class="el" href="structcfi__usb__ctrlrequest.html">cfi_usb_ctrlrequest</a> - the CFI implementation of the struct usb_ctrlrequest This structure encapsulates the standard usb_ctrlrequest and adds a pointer to the data returned in the data stage of a 3-stage Control Write requests.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__cfi_8h-source.html">dwc_otg_cfi.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="6ba267845c2907b3908d3761c252b10c"></a><!-- doxytag: member="cfi_usb_ctrlrequest::bRequestType" ref="6ba267845c2907b3908d3761c252b10c" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcfi__usb__ctrlrequest.html#6ba267845c2907b3908d3761c252b10c">bRequestType</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b3083f525fa9bb97e41364418daee3fa"></a><!-- doxytag: member="cfi_usb_ctrlrequest::bRequest" ref="b3083f525fa9bb97e41364418daee3fa" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcfi__usb__ctrlrequest.html#b3083f525fa9bb97e41364418daee3fa">bRequest</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="2f236bbf9450df1a3b5204c4570d883f"></a><!-- doxytag: member="cfi_usb_ctrlrequest::wValue" ref="2f236bbf9450df1a3b5204c4570d883f" args="" -->
+uint16_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcfi__usb__ctrlrequest.html#2f236bbf9450df1a3b5204c4570d883f">wValue</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="984c95bd61e8d1120cd935bcbc5d7134"></a><!-- doxytag: member="cfi_usb_ctrlrequest::wIndex" ref="984c95bd61e8d1120cd935bcbc5d7134" args="" -->
+uint16_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcfi__usb__ctrlrequest.html#984c95bd61e8d1120cd935bcbc5d7134">wIndex</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="60d71d1239e46e787f0b4c626de7c769"></a><!-- doxytag: member="cfi_usb_ctrlrequest::wLength" ref="60d71d1239e46e787f0b4c626de7c769" args="" -->
+uint16_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcfi__usb__ctrlrequest.html#60d71d1239e46e787f0b4c626de7c769">wLength</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="5b3865e9cb2c0fcf373b1c862a63c180"></a><!-- doxytag: member="cfi_usb_ctrlrequest::data" ref="5b3865e9cb2c0fcf373b1c862a63c180" args="" -->
+uint8_t *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcfi__usb__ctrlrequest.html#5b3865e9cb2c0fcf373b1c862a63c180">data</a></td></tr>
+
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+struct <a class="el" href="structcfi__usb__ctrlrequest.html">cfi_usb_ctrlrequest</a> - the CFI implementation of the struct usb_ctrlrequest This structure encapsulates the standard usb_ctrlrequest and adds a pointer to the data returned in the data stage of a 3-stage Control Write requests. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cfi_8h-source.html#l00140">140</a> of file <a class="el" href="dwc__otg__cfi_8h-source.html">dwc_otg_cfi.h</a>.<hr>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__cfi_8h-source.html">dwc_otg_cfi.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/structcfiobject.html b/drivers/usb/host/dwc_otg/doc/html/structcfiobject.html
new file mode 100644
index 000000000000..7e63c2286045
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/structcfiobject.html
@@ -0,0 +1,62 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: cfiobject Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>cfiobject Struct Reference</h1><!-- doxytag: class="cfiobject" --><table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="324b7481af9ba7a97233b162bbe8301a"></a><!-- doxytag: member="cfiobject::ops" ref="324b7481af9ba7a97233b162bbe8301a" args="" -->
+<a class="el" href="structcfi__ops.html">cfi_ops_t</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcfiobject.html#324b7481af9ba7a97233b162bbe8301a">ops</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="bab38f9fb74c1332c70029000c7d3818"></a><!-- doxytag: member="cfiobject::pcd" ref="bab38f9fb74c1332c70029000c7d3818" args="" -->
+<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcfiobject.html#bab38f9fb74c1332c70029000c7d3818">pcd</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="fcb2ec62bedb38bb1e6a596ac778d4e6"></a><!-- doxytag: member="cfiobject::gadget" ref="fcb2ec62bedb38bb1e6a596ac778d4e6" args="" -->
+usb_gadget *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcfiobject.html#fcb2ec62bedb38bb1e6a596ac778d4e6">gadget</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f6548b2b8fbab90656c22eb5ca857643"></a><!-- doxytag: member="cfiobject::buf_in" ref="f6548b2b8fbab90656c22eb5ca857643" args="" -->
+<a class="el" href="structcfi__dma__buff.html">cfi_dma_buff_t</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcfiobject.html#f6548b2b8fbab90656c22eb5ca857643">buf_in</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="adaa1cd0f88e639251f8dfbd65da7935"></a><!-- doxytag: member="cfiobject::buf_out" ref="adaa1cd0f88e639251f8dfbd65da7935" args="" -->
+<a class="el" href="structcfi__dma__buff.html">cfi_dma_buff_t</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcfiobject.html#adaa1cd0f88e639251f8dfbd65da7935">buf_out</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="a86c33aef2a521a27ca515bb7397dd34"></a><!-- doxytag: member="cfiobject::ctrl_req" ref="a86c33aef2a521a27ca515bb7397dd34" args="" -->
+<a class="el" href="structcfi__usb__ctrlrequest.html">cfi_usb_ctrlrequest</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcfiobject.html#a86c33aef2a521a27ca515bb7397dd34">ctrl_req</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="82805f011abf3deace7faa159729229a"></a><!-- doxytag: member="cfiobject::active_eps" ref="82805f011abf3deace7faa159729229a" args="" -->
+dwc_list_link_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcfiobject.html#82805f011abf3deace7faa159729229a">active_eps</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f103d681f78c43dc92dd4a85cdbdc27c"></a><!-- doxytag: member="cfiobject::need_gadget_att" ref="f103d681f78c43dc92dd4a85cdbdc27c" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcfiobject.html#f103d681f78c43dc92dd4a85cdbdc27c">need_gadget_att</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="8d35a323dcd29a1c9d1a8568bd514c3b"></a><!-- doxytag: member="cfiobject::need_status_in_complete" ref="8d35a323dcd29a1c9d1a8568bd514c3b" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcfiobject.html#8d35a323dcd29a1c9d1a8568bd514c3b">need_status_in_complete</a></td></tr>
+
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cfi_8h-source.html#l00214">214</a> of file <a class="el" href="dwc__otg__cfi_8h-source.html">dwc_otg_cfi.h</a>.<hr>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__cfi_8h-source.html">dwc_otg_cfi.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/structdwc__ep.html b/drivers/usb/host/dwc_otg/doc/html/structdwc__ep.html
new file mode 100644
index 000000000000..893fb76fce63
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/structdwc__ep.html
@@ -0,0 +1,192 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
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+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_ep Struct Reference</title>
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+<h1>dwc_ep Struct Reference</h1><!-- doxytag: class="dwc_ep" -->The <code><a class="el" href="structdwc__ep.html">dwc_ep</a></code> structure represents the state of a single endpoint when acting in device mode.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="1dd76dafde9ac2a466d64a5acbc35214"></a><!-- doxytag: member="dwc_ep::num" ref="1dd76dafde9ac2a466d64a5acbc35214" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__ep.html#1dd76dafde9ac2a466d64a5acbc35214">num</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">EP number used for register address lookup. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b882b6b7c857100ed20600e94ea37760"></a><!-- doxytag: member="dwc_ep::is_in" ref="b882b6b7c857100ed20600e94ea37760" args="" -->
+unsigned&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__ep.html#b882b6b7c857100ed20600e94ea37760">is_in</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">EP direction 0 = OUT. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="63b7a1a3ee32df393ff10d8bfc5c8648"></a><!-- doxytag: member="dwc_ep::active" ref="63b7a1a3ee32df393ff10d8bfc5c8648" args="" -->
+unsigned&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__ep.html#63b7a1a3ee32df393ff10d8bfc5c8648">active</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">EP active. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ffa14f48094778143353b845b5d238cd"></a><!-- doxytag: member="dwc_ep::tx_fifo_num" ref="ffa14f48094778143353b845b5d238cd" args="" -->
+unsigned&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__ep.html#ffa14f48094778143353b845b5d238cd">tx_fifo_num</a>:4</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Periodic Tx FIFO # for IN EPs For INTR EP set to 0 to use non-periodic Tx FIFO If dedicated Tx FIFOs are enabled for all IN Eps - Tx FIFO # FOR IN EPs. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="17b10677bd9b0a1d612dd4ce2fb0eb0f"></a><!-- doxytag: member="dwc_ep::type" ref="17b10677bd9b0a1d612dd4ce2fb0eb0f" args="" -->
+unsigned&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__ep.html#17b10677bd9b0a1d612dd4ce2fb0eb0f">type</a>:2</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">EP type: 0 - Control, 1 - ISOC, 2 - BULK, 3 - INTR. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="4ceafa9e067ba462ab38c20ffcf8d597"></a><!-- doxytag: member="dwc_ep::data_pid_start" ref="4ceafa9e067ba462ab38c20ffcf8d597" args="" -->
+unsigned&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__ep.html#4ceafa9e067ba462ab38c20ffcf8d597">data_pid_start</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">DATA start PID for INTR and BULK EP. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="0692ad9970f4ff48b4210577a6bf86ee"></a><!-- doxytag: member="dwc_ep::even_odd_frame" ref="0692ad9970f4ff48b4210577a6bf86ee" args="" -->
+unsigned&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__ep.html#0692ad9970f4ff48b4210577a6bf86ee">even_odd_frame</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Frame (even/odd) for ISOC EP. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="d17473ece3c9a34f5e7a230d3315de94"></a><!-- doxytag: member="dwc_ep::maxpacket" ref="d17473ece3c9a34f5e7a230d3315de94" args="" -->
+unsigned&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__ep.html#d17473ece3c9a34f5e7a230d3315de94">maxpacket</a>:11</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Max Packet bytes. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f60095e5ebedf7f98f3bfea77ce9a755"></a><!-- doxytag: member="dwc_ep::maxxfer" ref="f60095e5ebedf7f98f3bfea77ce9a755" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__ep.html#f60095e5ebedf7f98f3bfea77ce9a755">maxxfer</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Max Transfer size. <br></td></tr>
+<tr><td colspan="2"><div class="groupHeader">Transfer state</div></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b40ce70422b6d105a855a8df4b33d45d"></a><!-- doxytag: member="dwc_ep::dma_addr" ref="b40ce70422b6d105a855a8df4b33d45d" args="" -->
+dwc_dma_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__ep.html#b40ce70422b6d105a855a8df4b33d45d">dma_addr</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Pointer to the beginning of the transfer buffer -- do not modify during transfer. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="1a43e464429530e874472092e0e1af09"></a><!-- doxytag: member="dwc_ep::dma_desc_addr" ref="1a43e464429530e874472092e0e1af09" args="" -->
+dwc_dma_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__ep.html#1a43e464429530e874472092e0e1af09">dma_desc_addr</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="57e934b26e76939912eaa76321075a0d"></a><!-- doxytag: member="dwc_ep::desc_addr" ref="57e934b26e76939912eaa76321075a0d" args="" -->
+<a class="el" href="structdwc__otg__dev__dma__desc.html">dwc_otg_dev_dma_desc_t</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__ep.html#57e934b26e76939912eaa76321075a0d">desc_addr</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="d0cda8ded2e5142d9a1c9c17efc5812f"></a><!-- doxytag: member="dwc_ep::start_xfer_buff" ref="d0cda8ded2e5142d9a1c9c17efc5812f" args="" -->
+uint8_t *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__ep.html#d0cda8ded2e5142d9a1c9c17efc5812f">start_xfer_buff</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="97fa9bf5c31ba734d54f70e6fe6ae8eb"></a><!-- doxytag: member="dwc_ep::xfer_buff" ref="97fa9bf5c31ba734d54f70e6fe6ae8eb" args="" -->
+uint8_t *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__ep.html#97fa9bf5c31ba734d54f70e6fe6ae8eb">xfer_buff</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">pointer to the transfer buffer <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="36d4010478ceb27479c0b12b376a7924"></a><!-- doxytag: member="dwc_ep::xfer_len" ref="36d4010478ceb27479c0b12b376a7924" args="" -->
+unsigned&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__ep.html#36d4010478ceb27479c0b12b376a7924">xfer_len</a>:19</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Number of bytes to transfer. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="23d4871510b5bcb54fbf0674d8f122bd"></a><!-- doxytag: member="dwc_ep::xfer_count" ref="23d4871510b5bcb54fbf0674d8f122bd" args="" -->
+unsigned&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__ep.html#23d4871510b5bcb54fbf0674d8f122bd">xfer_count</a>:19</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Number of bytes transferred. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="8c6340435beba0b8c025a4677602acab"></a><!-- doxytag: member="dwc_ep::sent_zlp" ref="8c6340435beba0b8c025a4677602acab" args="" -->
+unsigned&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__ep.html#8c6340435beba0b8c025a4677602acab">sent_zlp</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Sent ZLP. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="5a218f200cff0491b735f43fed5176bf"></a><!-- doxytag: member="dwc_ep::total_len" ref="5a218f200cff0491b735f43fed5176bf" args="" -->
+unsigned&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__ep.html#5a218f200cff0491b735f43fed5176bf">total_len</a>:19</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Total len for control transfer. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="0d30d306e370810fc819f6ef735c7e67"></a><!-- doxytag: member="dwc_ep::stall_clear_flag" ref="0d30d306e370810fc819f6ef735c7e67" args="" -->
+unsigned&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__ep.html#0d30d306e370810fc819f6ef735c7e67">stall_clear_flag</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">stall clear flag <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="5e5bfcc93d41670bc0d29ad5f0f35871"></a><!-- doxytag: member="dwc_ep::desc_cnt" ref="5e5bfcc93d41670bc0d29ad5f0f35871" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__ep.html#5e5bfcc93d41670bc0d29ad5f0f35871">desc_cnt</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Allocated DMA Desc count. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="553936d1d003413d00a24330274887f9"></a><!-- doxytag: member="dwc_ep::dma_addr0" ref="553936d1d003413d00a24330274887f9" args="" -->
+dwc_dma_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__ep.html#553936d1d003413d00a24330274887f9">dma_addr0</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">DMA addresses of ISOC buffers. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="02dc1be77d505b19f14651fe9805c97f"></a><!-- doxytag: member="dwc_ep::dma_addr1" ref="02dc1be77d505b19f14651fe9805c97f" args="" -->
+dwc_dma_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__ep.html#02dc1be77d505b19f14651fe9805c97f">dma_addr1</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="d571f49545171ea167193edac7984173"></a><!-- doxytag: member="dwc_ep::iso_dma_desc_addr" ref="d571f49545171ea167193edac7984173" args="" -->
+dwc_dma_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__ep.html#d571f49545171ea167193edac7984173">iso_dma_desc_addr</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="a4e11d12099ad64dd5048a3a210fc9f6"></a><!-- doxytag: member="dwc_ep::iso_desc_addr" ref="a4e11d12099ad64dd5048a3a210fc9f6" args="" -->
+<a class="el" href="structdwc__otg__dev__dma__desc.html">dwc_otg_dev_dma_desc_t</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__ep.html#a4e11d12099ad64dd5048a3a210fc9f6">iso_desc_addr</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b6d727e366ac589d304256c758d2d44a"></a><!-- doxytag: member="dwc_ep::xfer_buff0" ref="b6d727e366ac589d304256c758d2d44a" args="" -->
+uint8_t *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__ep.html#b6d727e366ac589d304256c758d2d44a">xfer_buff0</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">pointer to the transfer buffers <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="36ff87362a0da5bce95eaf85522d49ff"></a><!-- doxytag: member="dwc_ep::xfer_buff1" ref="36ff87362a0da5bce95eaf85522d49ff" args="" -->
+uint8_t *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__ep.html#36ff87362a0da5bce95eaf85522d49ff">xfer_buff1</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="53033f174854701986545f05502e1cad"></a><!-- doxytag: member="dwc_ep::proc_buf_num" ref="53033f174854701986545f05502e1cad" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__ep.html#53033f174854701986545f05502e1cad">proc_buf_num</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">number of ISOC Buffer is processing <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="4638b25387e59a5a4721a503b5279dfc"></a><!-- doxytag: member="dwc_ep::buf_proc_intrvl" ref="4638b25387e59a5a4721a503b5279dfc" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__ep.html#4638b25387e59a5a4721a503b5279dfc">buf_proc_intrvl</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Interval of ISOC Buffer processing. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="4672369f4724db642856d72d5048213e"></a><!-- doxytag: member="dwc_ep::data_per_frame" ref="4672369f4724db642856d72d5048213e" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__ep.html#4672369f4724db642856d72d5048213e">data_per_frame</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Data size for regular frame. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c505483882bd67a7b0076851f693f2cc"></a><!-- doxytag: member="dwc_ep::data_pattern_frame" ref="c505483882bd67a7b0076851f693f2cc" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__ep.html#c505483882bd67a7b0076851f693f2cc">data_pattern_frame</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Data size for pattern frame. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="1b9094ddfba3cddf397fd308cdbf4c81"></a><!-- doxytag: member="dwc_ep::sync_frame" ref="1b9094ddfba3cddf397fd308cdbf4c81" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__ep.html#1b9094ddfba3cddf397fd308cdbf4c81">sync_frame</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Frame number of pattern data. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="d9e9ffe348764ababc3165ed04f9ec6c"></a><!-- doxytag: member="dwc_ep::bInterval" ref="d9e9ffe348764ababc3165ed04f9ec6c" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__ep.html#d9e9ffe348764ababc3165ed04f9ec6c">bInterval</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">bInterval <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="fe51420474de8a9d74fc9c4adc811c4b"></a><!-- doxytag: member="dwc_ep::pkt_per_frm" ref="fe51420474de8a9d74fc9c4adc811c4b" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__ep.html#fe51420474de8a9d74fc9c4adc811c4b">pkt_per_frm</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">ISO Packet number per frame. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="1e9f4d08454c973c17acb3e52a2c3689"></a><!-- doxytag: member="dwc_ep::next_frame" ref="1e9f4d08454c973c17acb3e52a2c3689" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__ep.html#1e9f4d08454c973c17acb3e52a2c3689">next_frame</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Next frame num for which will be setup DMA Desc. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="46349fb0608d8c6849ced211b0628c15"></a><!-- doxytag: member="dwc_ep::pkt_cnt" ref="46349fb0608d8c6849ced211b0628c15" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__ep.html#46349fb0608d8c6849ced211b0628c15">pkt_cnt</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Number of packets per buffer processing. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="a8ed15a24123a2dad6861da7d61dfb48"></a><!-- doxytag: member="dwc_ep::pkt_info" ref="a8ed15a24123a2dad6861da7d61dfb48" args="" -->
+<a class="el" href="structiso__pkt__info.html">iso_pkt_info_t</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__ep.html#a8ed15a24123a2dad6861da7d61dfb48">pkt_info</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Info for all isoc packets. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="d4e63c7d944c2b48260b4a75c2b58925"></a><!-- doxytag: member="dwc_ep::cur_pkt" ref="d4e63c7d944c2b48260b4a75c2b58925" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__ep.html#d4e63c7d944c2b48260b4a75c2b58925">cur_pkt</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">current pkt number <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="d3bc23598a77d3cca52c70a28afc6b5e"></a><!-- doxytag: member="dwc_ep::cur_pkt_addr" ref="d3bc23598a77d3cca52c70a28afc6b5e" args="" -->
+uint8_t *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__ep.html#d3bc23598a77d3cca52c70a28afc6b5e">cur_pkt_addr</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">current pkt number <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ed4594c9f6c2bcbcf6f1bbe9e9c64061"></a><!-- doxytag: member="dwc_ep::cur_pkt_dma_addr" ref="ed4594c9f6c2bcbcf6f1bbe9e9c64061" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__ep.html#ed4594c9f6c2bcbcf6f1bbe9e9c64061">cur_pkt_dma_addr</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">current pkt number <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+The <code><a class="el" href="structdwc__ep.html">dwc_ep</a></code> structure represents the state of a single endpoint when acting in device mode. 
+<p>
+It contains the data items needed for an endpoint to be activated and transfer packets. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8h-source.html#l00088">88</a> of file <a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a>.<hr>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/structdwc__hc.html b/drivers/usb/host/dwc_otg/doc/html/structdwc__hc.html
new file mode 100644
index 000000000000..b23fc5c64785
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/structdwc__hc.html
@@ -0,0 +1,345 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_hc Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>dwc_hc Struct Reference</h1><!-- doxytag: class="dwc_hc" -->Host channel descriptor.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Public Member Functions</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="bf81e1a0c0ae06faf445a61b950e24f5"></a><!-- doxytag: member="dwc_hc::DWC_CIRCLEQ_ENTRY" ref="bf81e1a0c0ae06faf445a61b950e24f5" args="(dwc_hc) hc_list_entry" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__hc.html#bf81e1a0c0ae06faf445a61b950e24f5">DWC_CIRCLEQ_ENTRY</a> (<a class="el" href="structdwc__hc.html">dwc_hc</a>) hc_list_entry</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Entry in list of host channels. <br></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="df0c2b93e5c84cfaba6f06eaeaece5a1"></a><!-- doxytag: member="dwc_hc::hc_num" ref="df0c2b93e5c84cfaba6f06eaeaece5a1" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__hc.html#df0c2b93e5c84cfaba6f06eaeaece5a1">hc_num</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Host channel number used for register address lookup. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b2c7e8baff70104375f4916e9b76cef7"></a><!-- doxytag: member="dwc_hc::dev_addr" ref="b2c7e8baff70104375f4916e9b76cef7" args="" -->
+unsigned&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__hc.html#b2c7e8baff70104375f4916e9b76cef7">dev_addr</a>:7</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Device to access. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="70b755f76a00b81679aeb1e0db8b2e60"></a><!-- doxytag: member="dwc_hc::ep_num" ref="70b755f76a00b81679aeb1e0db8b2e60" args="" -->
+unsigned&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__hc.html#70b755f76a00b81679aeb1e0db8b2e60">ep_num</a>:4</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">EP to access. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">unsigned&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__hc.html#c5088d431f5efc382121f201f5d571aa">ep_is_in</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">EP direction.  <a href="#c5088d431f5efc382121f201f5d571aa"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">unsigned&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__hc.html#570b78178975193edb921af1ef36d37b">speed</a>:2</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">EP speed.  <a href="#570b78178975193edb921af1ef36d37b"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">unsigned&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__hc.html#e6169fbc92e4d79686097742ad646f5c">ep_type</a>:2</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Endpoint type.  <a href="#e6169fbc92e4d79686097742ad646f5c"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="bd88f02eb286ba01d8d1b049e8975ccb"></a><!-- doxytag: member="dwc_hc::max_packet" ref="bd88f02eb286ba01d8d1b049e8975ccb" args="" -->
+unsigned&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__hc.html#bd88f02eb286ba01d8d1b049e8975ccb">max_packet</a>:11</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Max packet size in bytes. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">unsigned&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__hc.html#513427c5e8c4603ba344d4e7f9191064">data_pid_start</a>:2</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">PID for initial transaction.  <a href="#513427c5e8c4603ba344d4e7f9191064"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="9a01b904f7ccc7178cdb80c20e8a9b0c"></a><!-- doxytag: member="dwc_hc::multi_count" ref="9a01b904f7ccc7178cdb80c20e8a9b0c" args="" -->
+unsigned&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__hc.html#9a01b904f7ccc7178cdb80c20e8a9b0c">multi_count</a>:2</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Number of periodic transactions per (micro)frame. <br></td></tr>
+<tr><td colspan="2"><div class="groupHeader">Transfer State</div></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="9dc781cb9e4bc639765beee37ce76673"></a><!-- doxytag: member="dwc_hc::xfer_buff" ref="9dc781cb9e4bc639765beee37ce76673" args="" -->
+uint8_t *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__hc.html#9dc781cb9e4bc639765beee37ce76673">xfer_buff</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Pointer to the current transfer buffer position. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e0c3ba51a04b36656baa4e70fc63cf77"></a><!-- doxytag: member="dwc_hc::align_buff" ref="e0c3ba51a04b36656baa4e70fc63cf77" args="" -->
+dwc_dma_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__hc.html#e0c3ba51a04b36656baa4e70fc63cf77">align_buff</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">In Buffer DMA mode this buffer will be used if xfer_buff is not DWORD aligned. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ce32fe93214f1686896e924fbf61cac7"></a><!-- doxytag: member="dwc_hc::xfer_len" ref="ce32fe93214f1686896e924fbf61cac7" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__hc.html#ce32fe93214f1686896e924fbf61cac7">xfer_len</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Total number of bytes to transfer. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="6199aaeab2d64954311c410b30270293"></a><!-- doxytag: member="dwc_hc::xfer_count" ref="6199aaeab2d64954311c410b30270293" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__hc.html#6199aaeab2d64954311c410b30270293">xfer_count</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Number of bytes transferred so far. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="6c030bc725f43025d3046d17b4fbee4e"></a><!-- doxytag: member="dwc_hc::start_pkt_count" ref="6c030bc725f43025d3046d17b4fbee4e" args="" -->
+uint16_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__hc.html#6c030bc725f43025d3046d17b4fbee4e">start_pkt_count</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Packet count at start of transfer. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__hc.html#78a1cf134604b24bfdedb4f4df9f2c1f">xfer_started</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Flag to indicate whether the transfer has been started.  <a href="#78a1cf134604b24bfdedb4f4df9f2c1f"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__hc.html#ae7184275dbb23b3a5d2af20ed224920">do_ping</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Set to 1 to indicate that a PING request should be issued on this channel.  <a href="#ae7184275dbb23b3a5d2af20ed224920"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__hc.html#ab0855754930fdc74978fa71772982ed">error_state</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Set to 1 to indicate that the error count for this transaction is non-zero.  <a href="#ab0855754930fdc74978fa71772982ed"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__hc.html#c3b27b33fae73aff43a9834a1ed585da">halt_on_queue</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Set to 1 to indicate that this channel should be halted the next time a request is queued for the channel.  <a href="#c3b27b33fae73aff43a9834a1ed585da"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__hc.html#2177dcde6dbb17b6bc7d0fb34e8ec95a">halt_pending</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Set to 1 if the host channel has been halted, but the core is not finished flushing queued requests.  <a href="#2177dcde6dbb17b6bc7d0fb34e8ec95a"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="07eca0fa02105ddaa1719387f5558b23"></a><!-- doxytag: member="dwc_hc::halt_status" ref="07eca0fa02105ddaa1719387f5558b23" args="" -->
+dwc_otg_halt_status_e&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__hc.html#07eca0fa02105ddaa1719387f5558b23">halt_status</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Reason for halting the host channel. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="4365ef67d517a621a626ac5392545c6d"></a><!-- doxytag: member="dwc_hc::do_split" ref="4365ef67d517a621a626ac5392545c6d" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__hc.html#4365ef67d517a621a626ac5392545c6d">do_split</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Enable split for the channel. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="21e00df6fb9a555975879526118d599e"></a><!-- doxytag: member="dwc_hc::complete_split" ref="21e00df6fb9a555975879526118d599e" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__hc.html#21e00df6fb9a555975879526118d599e">complete_split</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Enable complete split. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="19d0302b6e3769eada2466b8e5e0dd91"></a><!-- doxytag: member="dwc_hc::hub_addr" ref="19d0302b6e3769eada2466b8e5e0dd91" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__hc.html#19d0302b6e3769eada2466b8e5e0dd91">hub_addr</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Address of high speed hub. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="9f597e05c37d7292f4c0d965c67ee3dd"></a><!-- doxytag: member="dwc_hc::port_addr" ref="9f597e05c37d7292f4c0d965c67ee3dd" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__hc.html#9f597e05c37d7292f4c0d965c67ee3dd">port_addr</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Port of the low/full speed device. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3cde49a724756e16eb11a027360b2d4b"></a><!-- doxytag: member="dwc_hc::xact_pos" ref="3cde49a724756e16eb11a027360b2d4b" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__hc.html#3cde49a724756e16eb11a027360b2d4b">xact_pos</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Split transaction position One of the following values:<ul>
+<li>DWC_HCSPLIT_XACTPOS_MID</li><li>DWC_HCSPLIT_XACTPOS_BEGIN</li><li>DWC_HCSPLIT_XACTPOS_END</li><li>DWC_HCSPLIT_XACTPOS_ALL. </li></ul>
+<br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="83e9a3cc9075b1fe21a6fa5190fa78c1"></a><!-- doxytag: member="dwc_hc::short_read" ref="83e9a3cc9075b1fe21a6fa5190fa78c1" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__hc.html#83e9a3cc9075b1fe21a6fa5190fa78c1">short_read</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Set when the host channel does a short read. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="961e8eae7a18c503e370c4bc513d3e55"></a><!-- doxytag: member="dwc_hc::requests" ref="961e8eae7a18c503e370c4bc513d3e55" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__hc.html#961e8eae7a18c503e370c4bc513d3e55">requests</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Number of requests issued for this channel since it was assigned to the current transfer (not counting PINGs). <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="d338f8db131745d9921f51c30f26cd3c"></a><!-- doxytag: member="dwc_hc::qh" ref="d338f8db131745d9921f51c30f26cd3c" args="" -->
+<a class="el" href="structdwc__otg__qh.html">dwc_otg_qh</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__hc.html#d338f8db131745d9921f51c30f26cd3c">qh</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Queue Head for the transfer being processed by this channel. <br></td></tr>
+<tr><td colspan="2"><div class="groupHeader">Descriptor DMA support</div></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="9a3a483b9c4e45d1ec5f475beb6a10a3"></a><!-- doxytag: member="dwc_hc::ntd" ref="9a3a483b9c4e45d1ec5f475beb6a10a3" args="" -->
+uint16_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__hc.html#9a3a483b9c4e45d1ec5f475beb6a10a3">ntd</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Number of Transfer Descriptors. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f3001addf65df4d3c6a5c685d7637efd"></a><!-- doxytag: member="dwc_hc::desc_list_addr" ref="f3001addf65df4d3c6a5c685d7637efd" args="" -->
+dwc_dma_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__hc.html#f3001addf65df4d3c6a5c685d7637efd">desc_list_addr</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Descriptor List DMA address. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="42c5f7b0264ee050df79dc1fe57464b7"></a><!-- doxytag: member="dwc_hc::schinfo" ref="42c5f7b0264ee050df79dc1fe57464b7" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__hc.html#42c5f7b0264ee050df79dc1fe57464b7">schinfo</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Scheduling micro-frame bitmap. <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+Host channel descriptor. 
+<p>
+This structure represents the state of a single host channel when acting in host mode. It contains the data items needed to transfer packets to an endpoint via a host channel. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8h-source.html#l00237">237</a> of file <a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a>.<hr><h2>Field Documentation</h2>
+<a class="anchor" name="c5088d431f5efc382121f201f5d571aa"></a><!-- doxytag: member="dwc_hc::ep_is_in" ref="c5088d431f5efc382121f201f5d571aa" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">unsigned <a class="el" href="structdwc__hc.html#c5088d431f5efc382121f201f5d571aa">dwc_hc::ep_is_in</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+EP direction. 
+<p>
+0: OUT, 1: IN 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8h-source.html#l00248">248</a> of file <a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="570b78178975193edb921af1ef36d37b"></a><!-- doxytag: member="dwc_hc::speed" ref="570b78178975193edb921af1ef36d37b" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">unsigned <a class="el" href="structdwc__hc.html#570b78178975193edb921af1ef36d37b">dwc_hc::speed</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+EP speed. 
+<p>
+One of the following values:<ul>
+<li>DWC_OTG_EP_SPEED_LOW</li><li>DWC_OTG_EP_SPEED_FULL</li><li>DWC_OTG_EP_SPEED_HIGH </li></ul>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8h-source.html#l00257">257</a> of file <a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="e6169fbc92e4d79686097742ad646f5c"></a><!-- doxytag: member="dwc_hc::ep_type" ref="e6169fbc92e4d79686097742ad646f5c" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">unsigned <a class="el" href="structdwc__hc.html#e6169fbc92e4d79686097742ad646f5c">dwc_hc::ep_type</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Endpoint type. 
+<p>
+One of the following values:<ul>
+<li>DWC_OTG_EP_TYPE_CONTROL: 0</li><li>DWC_OTG_EP_TYPE_ISOC: 1</li><li>DWC_OTG_EP_TYPE_BULK: 2</li><li>DWC_OTG_EP_TYPE_INTR: 3 </li></ul>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8h-source.html#l00270">270</a> of file <a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="513427c5e8c4603ba344d4e7f9191064"></a><!-- doxytag: member="dwc_hc::data_pid_start" ref="513427c5e8c4603ba344d4e7f9191064" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">unsigned <a class="el" href="structdwc__hc.html#513427c5e8c4603ba344d4e7f9191064">dwc_hc::data_pid_start</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+PID for initial transaction. 
+<p>
+0: DATA0,<br>
+ 1: DATA2,<br>
+ 2: DATA1,<br>
+ 3: MDATA (non-Control EP), SETUP (Control EP) 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8h-source.html#l00283">283</a> of file <a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="78a1cf134604b24bfdedb4f4df9f2c1f"></a><!-- doxytag: member="dwc_hc::xfer_started" ref="78a1cf134604b24bfdedb4f4df9f2c1f" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint8_t <a class="el" href="structdwc__hc.html#78a1cf134604b24bfdedb4f4df9f2c1f">dwc_hc::xfer_started</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Flag to indicate whether the transfer has been started. 
+<p>
+Set to 1 if it has been started, 0 otherwise. 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8h-source.html#l00314">314</a> of file <a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="ae7184275dbb23b3a5d2af20ed224920"></a><!-- doxytag: member="dwc_hc::do_ping" ref="ae7184275dbb23b3a5d2af20ed224920" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint8_t <a class="el" href="structdwc__hc.html#ae7184275dbb23b3a5d2af20ed224920">dwc_hc::do_ping</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Set to 1 to indicate that a PING request should be issued on this channel. 
+<p>
+If 0, process normally. 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8h-source.html#l00320">320</a> of file <a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="ab0855754930fdc74978fa71772982ed"></a><!-- doxytag: member="dwc_hc::error_state" ref="ab0855754930fdc74978fa71772982ed" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint8_t <a class="el" href="structdwc__hc.html#ab0855754930fdc74978fa71772982ed">dwc_hc::error_state</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Set to 1 to indicate that the error count for this transaction is non-zero. 
+<p>
+Set to 0 if the error count is 0. 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8h-source.html#l00326">326</a> of file <a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="c3b27b33fae73aff43a9834a1ed585da"></a><!-- doxytag: member="dwc_hc::halt_on_queue" ref="c3b27b33fae73aff43a9834a1ed585da" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint8_t <a class="el" href="structdwc__hc.html#c3b27b33fae73aff43a9834a1ed585da">dwc_hc::halt_on_queue</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Set to 1 to indicate that this channel should be halted the next time a request is queued for the channel. 
+<p>
+This is necessary in slave mode if no request queue space is available when an attempt is made to halt the channel. 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8h-source.html#l00334">334</a> of file <a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="2177dcde6dbb17b6bc7d0fb34e8ec95a"></a><!-- doxytag: member="dwc_hc::halt_pending" ref="2177dcde6dbb17b6bc7d0fb34e8ec95a" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint8_t <a class="el" href="structdwc__hc.html#2177dcde6dbb17b6bc7d0fb34e8ec95a">dwc_hc::halt_pending</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Set to 1 if the host channel has been halted, but the core is not finished flushing queued requests. 
+<p>
+Otherwise 0. 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8h-source.html#l00340">340</a> of file <a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a>.
+</div>
+</div><p>
+<hr>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__cil__callbacks.html b/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__cil__callbacks.html
new file mode 100644
index 000000000000..ac0cc0733026
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__cil__callbacks.html
@@ -0,0 +1,70 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_cil_callbacks Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>dwc_otg_cil_callbacks Struct Reference</h1><!-- doxytag: class="dwc_otg_cil_callbacks" -->DWC_otg CIL callback structure.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ebb662b2e0b4d187648b7f91b9d00713"></a><!-- doxytag: member="dwc_otg_cil_callbacks::start" ref="ebb662b2e0b4d187648b7f91b9d00713" args=")(void *_p)" -->
+int(*&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__cil__callbacks.html#ebb662b2e0b4d187648b7f91b9d00713">start</a> )(void *_p)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Start function for role change. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="cd604365bc84ceda780e10c2344870e4"></a><!-- doxytag: member="dwc_otg_cil_callbacks::stop" ref="cd604365bc84ceda780e10c2344870e4" args=")(void *_p)" -->
+int(*&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__cil__callbacks.html#cd604365bc84ceda780e10c2344870e4">stop</a> )(void *_p)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Stop Function for role change. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="1a8ccad34a04f3e8b085aa5720bbcc70"></a><!-- doxytag: member="dwc_otg_cil_callbacks::disconnect" ref="1a8ccad34a04f3e8b085aa5720bbcc70" args=")(void *_p)" -->
+int(*&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__cil__callbacks.html#1a8ccad34a04f3e8b085aa5720bbcc70">disconnect</a> )(void *_p)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Disconnect Function for role change. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ad1895ddf4ad83622a514a725b4129d6"></a><!-- doxytag: member="dwc_otg_cil_callbacks::resume_wakeup" ref="ad1895ddf4ad83622a514a725b4129d6" args=")(void *_p)" -->
+int(*&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__cil__callbacks.html#ad1895ddf4ad83622a514a725b4129d6">resume_wakeup</a> )(void *_p)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Resume/Remote wakeup Function. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="a9e06ccc347fa446e2b131532e203d94"></a><!-- doxytag: member="dwc_otg_cil_callbacks::suspend" ref="a9e06ccc347fa446e2b131532e203d94" args=")(void *_p)" -->
+int(*&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__cil__callbacks.html#a9e06ccc347fa446e2b131532e203d94">suspend</a> )(void *_p)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Suspend function. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="d4235cc3ff7705538ccafa408950d759"></a><!-- doxytag: member="dwc_otg_cil_callbacks::session_start" ref="d4235cc3ff7705538ccafa408950d759" args=")(void *_p)" -->
+int(*&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__cil__callbacks.html#d4235cc3ff7705538ccafa408950d759">session_start</a> )(void *_p)</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Session Start (SRP). <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="a486473d73fb104dc3a37e963a8ef8e5"></a><!-- doxytag: member="dwc_otg_cil_callbacks::p" ref="a486473d73fb104dc3a37e963a8ef8e5" args="" -->
+void *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__cil__callbacks.html#a486473d73fb104dc3a37e963a8ef8e5">p</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Pointer passed to <a class="el" href="structdwc__otg__cil__callbacks.html#ebb662b2e0b4d187648b7f91b9d00713">start()</a> and <a class="el" href="structdwc__otg__cil__callbacks.html#cd604365bc84ceda780e10c2344870e4">stop()</a>. <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+DWC_otg CIL callback structure. 
+<p>
+This structure allows the HCD and PCD to register functions used for starting and stopping the PCD and HCD for role change on for a DRD. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8h-source.html#l01109">1109</a> of file <a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a>.<hr>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__core__global__regs.html b/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__core__global__regs.html
new file mode 100644
index 000000000000..eb4401415ff8
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__core__global__regs.html
@@ -0,0 +1,557 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_core_global_regs Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>dwc_otg_core_global_regs Struct Reference</h1><!-- doxytag: class="dwc_otg_core_global_regs" -->DWC_otg Core registers .  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__global__regs.html#54034d00bb6b47ada4e0c0baa87cbd8a">gotgctl</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">OTG Control and Status Register.  <a href="#54034d00bb6b47ada4e0c0baa87cbd8a"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__global__regs.html#69cc290cfdfe6900890f7a5a16b3137c">gotgint</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">OTG Interrupt Register.  <a href="#69cc290cfdfe6900890f7a5a16b3137c"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__global__regs.html#537c95e57269fabf29c6b36ad8e1ed45">gahbcfg</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Core AHB Configuration Register.  <a href="#537c95e57269fabf29c6b36ad8e1ed45"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__global__regs.html#ef39e181e246447df47c56aa4e37cc42">gusbcfg</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Core USB Configuration Register.  <a href="#ef39e181e246447df47c56aa4e37cc42"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__global__regs.html#49d307957dbe53f20aa8f7a5409ee8ad">grstctl</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Core Reset Register.  <a href="#49d307957dbe53f20aa8f7a5409ee8ad"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">gintsts</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Core Interrupt Register.  <a href="#aa1d909e3b0a60a56bf612968ff09019"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__global__regs.html#48827c76da2c6b18f369e2f2483cc4b6">gintmsk</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Core Interrupt Mask Register.  <a href="#48827c76da2c6b18f369e2f2483cc4b6"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__global__regs.html#5e688c41f25ba8081f34cb1b2b052dbc">grxstsr</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Receive Status Queue Read Register (Read Only).  <a href="#5e688c41f25ba8081f34cb1b2b052dbc"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__global__regs.html#763b05035799e1c16d34957fb62a2d17">grxstsp</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Receive Status Queue Read &amp; POP Register (Read Only).  <a href="#763b05035799e1c16d34957fb62a2d17"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__global__regs.html#b1a8cc07a9541c9a73e864579602b79b">grxfsiz</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Receive FIFO Size Register.  <a href="#b1a8cc07a9541c9a73e864579602b79b"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__global__regs.html#20fb70fe34a1a65d085b1d4e5f8d9106">gnptxfsiz</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Non Periodic Transmit FIFO Size Register.  <a href="#20fb70fe34a1a65d085b1d4e5f8d9106"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__global__regs.html#57dabea6f6e0bf9e1ee8e94f55b9e465">gnptxsts</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Non Periodic Transmit FIFO/Queue Status Register (Read Only).  <a href="#57dabea6f6e0bf9e1ee8e94f55b9e465"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__global__regs.html#8ecf68262dbcdb6901f3011cfe35a144">gi2cctl</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">I2C Access Register.  <a href="#8ecf68262dbcdb6901f3011cfe35a144"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__global__regs.html#a12db668367caef8386d2ba20289e437">gpvndctl</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">PHY Vendor Control Register.  <a href="#a12db668367caef8386d2ba20289e437"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__global__regs.html#694546400c443d41b449772c8573f3e8">ggpio</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">General Purpose Input/Output Register.  <a href="#694546400c443d41b449772c8573f3e8"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__global__regs.html#8735ca2e93c1e984ac2d5bcf0cda96d7">guid</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">User ID Register.  <a href="#8735ca2e93c1e984ac2d5bcf0cda96d7"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__global__regs.html#30798436df220217c3960ac4a46710dc">gsnpsid</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Synopsys ID Register (Read Only).  <a href="#30798436df220217c3960ac4a46710dc"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__global__regs.html#56d2988ff8fedbbde479ffe8d4e84b75">ghwcfg1</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">User HW Config1 Register (Read Only).  <a href="#56d2988ff8fedbbde479ffe8d4e84b75"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__global__regs.html#b0f241f53ca7b3be1c94bd684ed61f79">ghwcfg2</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">User HW Config2 Register (Read Only).  <a href="#b0f241f53ca7b3be1c94bd684ed61f79"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__global__regs.html#57ddcc14f581f5d6276122f9747aff72">ghwcfg3</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">User HW Config3 Register (Read Only).  <a href="#57ddcc14f581f5d6276122f9747aff72"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__global__regs.html#e1df73c776d3b31d5f0a501ccdeb1d2d">ghwcfg4</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">User HW Config4 Register (Read Only).  <a href="#e1df73c776d3b31d5f0a501ccdeb1d2d"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="843cfb38ba366a9a46ad07ed11eb8396"></a><!-- doxytag: member="dwc_otg_core_global_regs::glpmcfg" ref="843cfb38ba366a9a46ad07ed11eb8396" args="" -->
+volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__global__regs.html#843cfb38ba366a9a46ad07ed11eb8396">glpmcfg</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Core LPM Configuration register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="61b9a23f780477ed03ef8236a393fb2e"></a><!-- doxytag: member="dwc_otg_core_global_regs::reserved" ref="61b9a23f780477ed03ef8236a393fb2e" args="[42]" -->
+volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__global__regs.html#61b9a23f780477ed03ef8236a393fb2e">reserved</a> [42]</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Reserved <em>Offset: 058h-0FFh</em>. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__global__regs.html#94ae41f04d5a4244a8ebc23e51187e96">hptxfsiz</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Host Periodic Transmit FIFO Size Register.  <a href="#94ae41f04d5a4244a8ebc23e51187e96"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__global__regs.html#efd9e780825f992dbc6cf46d2d72869e">dptxfsiz_dieptxf</a> [15]</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Device Periodic Transmit FIFO::n Register if dedicated fifos are disabled, otherwise Device Transmit FIFO::n Register.  <a href="#efd9e780825f992dbc6cf46d2d72869e"></a><br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+DWC_otg Core registers . 
+<p>
+The <a class="el" href="structdwc__otg__core__global__regs.html">dwc_otg_core_global_regs</a> structure defines the size and relative field offsets for the Core Global registers. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00071">71</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr><h2>Field Documentation</h2>
+<a class="anchor" name="54034d00bb6b47ada4e0c0baa87cbd8a"></a><!-- doxytag: member="dwc_otg_core_global_regs::gotgctl" ref="54034d00bb6b47ada4e0c0baa87cbd8a" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__core__global__regs.html#54034d00bb6b47ada4e0c0baa87cbd8a">dwc_otg_core_global_regs::gotgctl</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+OTG Control and Status Register. 
+<p>
+<em>Offset: 000h</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00073">73</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="69cc290cfdfe6900890f7a5a16b3137c"></a><!-- doxytag: member="dwc_otg_core_global_regs::gotgint" ref="69cc290cfdfe6900890f7a5a16b3137c" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__core__global__regs.html#69cc290cfdfe6900890f7a5a16b3137c">dwc_otg_core_global_regs::gotgint</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+OTG Interrupt Register. 
+<p>
+<em>Offset: 004h</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00075">75</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="537c95e57269fabf29c6b36ad8e1ed45"></a><!-- doxytag: member="dwc_otg_core_global_regs::gahbcfg" ref="537c95e57269fabf29c6b36ad8e1ed45" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__core__global__regs.html#537c95e57269fabf29c6b36ad8e1ed45">dwc_otg_core_global_regs::gahbcfg</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Core AHB Configuration Register. 
+<p>
+<em>Offset: 008h</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00077">77</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="ef39e181e246447df47c56aa4e37cc42"></a><!-- doxytag: member="dwc_otg_core_global_regs::gusbcfg" ref="ef39e181e246447df47c56aa4e37cc42" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__core__global__regs.html#ef39e181e246447df47c56aa4e37cc42">dwc_otg_core_global_regs::gusbcfg</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Core USB Configuration Register. 
+<p>
+<em>Offset: 00Ch</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00087">87</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="49d307957dbe53f20aa8f7a5409ee8ad"></a><!-- doxytag: member="dwc_otg_core_global_regs::grstctl" ref="49d307957dbe53f20aa8f7a5409ee8ad" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__core__global__regs.html#49d307957dbe53f20aa8f7a5409ee8ad">dwc_otg_core_global_regs::grstctl</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Core Reset Register. 
+<p>
+<em>Offset: 010h</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00089">89</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="aa1d909e3b0a60a56bf612968ff09019"></a><!-- doxytag: member="dwc_otg_core_global_regs::gintsts" ref="aa1d909e3b0a60a56bf612968ff09019" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__core__global__regs.html#aa1d909e3b0a60a56bf612968ff09019">dwc_otg_core_global_regs::gintsts</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Core Interrupt Register. 
+<p>
+<em>Offset: 014h</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00091">91</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="48827c76da2c6b18f369e2f2483cc4b6"></a><!-- doxytag: member="dwc_otg_core_global_regs::gintmsk" ref="48827c76da2c6b18f369e2f2483cc4b6" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__core__global__regs.html#48827c76da2c6b18f369e2f2483cc4b6">dwc_otg_core_global_regs::gintmsk</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Core Interrupt Mask Register. 
+<p>
+<em>Offset: 018h</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00093">93</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="5e688c41f25ba8081f34cb1b2b052dbc"></a><!-- doxytag: member="dwc_otg_core_global_regs::grxstsr" ref="5e688c41f25ba8081f34cb1b2b052dbc" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__core__global__regs.html#5e688c41f25ba8081f34cb1b2b052dbc">dwc_otg_core_global_regs::grxstsr</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Receive Status Queue Read Register (Read Only). 
+<p>
+<em>Offset: 01Ch</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00095">95</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="763b05035799e1c16d34957fb62a2d17"></a><!-- doxytag: member="dwc_otg_core_global_regs::grxstsp" ref="763b05035799e1c16d34957fb62a2d17" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__core__global__regs.html#763b05035799e1c16d34957fb62a2d17">dwc_otg_core_global_regs::grxstsp</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Receive Status Queue Read &amp; POP Register (Read Only). 
+<p>
+<em>Offset: 020h</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00097">97</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="b1a8cc07a9541c9a73e864579602b79b"></a><!-- doxytag: member="dwc_otg_core_global_regs::grxfsiz" ref="b1a8cc07a9541c9a73e864579602b79b" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__core__global__regs.html#b1a8cc07a9541c9a73e864579602b79b">dwc_otg_core_global_regs::grxfsiz</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Receive FIFO Size Register. 
+<p>
+<em>Offset: 024h</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00099">99</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="20fb70fe34a1a65d085b1d4e5f8d9106"></a><!-- doxytag: member="dwc_otg_core_global_regs::gnptxfsiz" ref="20fb70fe34a1a65d085b1d4e5f8d9106" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__core__global__regs.html#20fb70fe34a1a65d085b1d4e5f8d9106">dwc_otg_core_global_regs::gnptxfsiz</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Non Periodic Transmit FIFO Size Register. 
+<p>
+<em>Offset: 028h</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00101">101</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="57dabea6f6e0bf9e1ee8e94f55b9e465"></a><!-- doxytag: member="dwc_otg_core_global_regs::gnptxsts" ref="57dabea6f6e0bf9e1ee8e94f55b9e465" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__core__global__regs.html#57dabea6f6e0bf9e1ee8e94f55b9e465">dwc_otg_core_global_regs::gnptxsts</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Non Periodic Transmit FIFO/Queue Status Register (Read Only). 
+<p>
+<em>Offset: 02Ch</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00104">104</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="8ecf68262dbcdb6901f3011cfe35a144"></a><!-- doxytag: member="dwc_otg_core_global_regs::gi2cctl" ref="8ecf68262dbcdb6901f3011cfe35a144" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__core__global__regs.html#8ecf68262dbcdb6901f3011cfe35a144">dwc_otg_core_global_regs::gi2cctl</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+I2C Access Register. 
+<p>
+<em>Offset: 030h</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00106">106</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="a12db668367caef8386d2ba20289e437"></a><!-- doxytag: member="dwc_otg_core_global_regs::gpvndctl" ref="a12db668367caef8386d2ba20289e437" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__core__global__regs.html#a12db668367caef8386d2ba20289e437">dwc_otg_core_global_regs::gpvndctl</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+PHY Vendor Control Register. 
+<p>
+<em>Offset: 034h</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00108">108</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="694546400c443d41b449772c8573f3e8"></a><!-- doxytag: member="dwc_otg_core_global_regs::ggpio" ref="694546400c443d41b449772c8573f3e8" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__core__global__regs.html#694546400c443d41b449772c8573f3e8">dwc_otg_core_global_regs::ggpio</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+General Purpose Input/Output Register. 
+<p>
+<em>Offset: 038h</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00110">110</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="8735ca2e93c1e984ac2d5bcf0cda96d7"></a><!-- doxytag: member="dwc_otg_core_global_regs::guid" ref="8735ca2e93c1e984ac2d5bcf0cda96d7" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__core__global__regs.html#8735ca2e93c1e984ac2d5bcf0cda96d7">dwc_otg_core_global_regs::guid</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+User ID Register. 
+<p>
+<em>Offset: 03Ch</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00112">112</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="30798436df220217c3960ac4a46710dc"></a><!-- doxytag: member="dwc_otg_core_global_regs::gsnpsid" ref="30798436df220217c3960ac4a46710dc" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__core__global__regs.html#30798436df220217c3960ac4a46710dc">dwc_otg_core_global_regs::gsnpsid</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Synopsys ID Register (Read Only). 
+<p>
+<em>Offset: 040h</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00114">114</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="56d2988ff8fedbbde479ffe8d4e84b75"></a><!-- doxytag: member="dwc_otg_core_global_regs::ghwcfg1" ref="56d2988ff8fedbbde479ffe8d4e84b75" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__core__global__regs.html#56d2988ff8fedbbde479ffe8d4e84b75">dwc_otg_core_global_regs::ghwcfg1</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+User HW Config1 Register (Read Only). 
+<p>
+<em>Offset: 044h</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00116">116</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="b0f241f53ca7b3be1c94bd684ed61f79"></a><!-- doxytag: member="dwc_otg_core_global_regs::ghwcfg2" ref="b0f241f53ca7b3be1c94bd684ed61f79" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__core__global__regs.html#b0f241f53ca7b3be1c94bd684ed61f79">dwc_otg_core_global_regs::ghwcfg2</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+User HW Config2 Register (Read Only). 
+<p>
+<em>Offset: 048h</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00118">118</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="57ddcc14f581f5d6276122f9747aff72"></a><!-- doxytag: member="dwc_otg_core_global_regs::ghwcfg3" ref="57ddcc14f581f5d6276122f9747aff72" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__core__global__regs.html#57ddcc14f581f5d6276122f9747aff72">dwc_otg_core_global_regs::ghwcfg3</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+User HW Config3 Register (Read Only). 
+<p>
+<em>Offset: 04Ch</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00132">132</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="e1df73c776d3b31d5f0a501ccdeb1d2d"></a><!-- doxytag: member="dwc_otg_core_global_regs::ghwcfg4" ref="e1df73c776d3b31d5f0a501ccdeb1d2d" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__core__global__regs.html#e1df73c776d3b31d5f0a501ccdeb1d2d">dwc_otg_core_global_regs::ghwcfg4</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+User HW Config4 Register (Read Only). 
+<p>
+<em>Offset: 050h</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00134">134</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="94ae41f04d5a4244a8ebc23e51187e96"></a><!-- doxytag: member="dwc_otg_core_global_regs::hptxfsiz" ref="94ae41f04d5a4244a8ebc23e51187e96" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__core__global__regs.html#94ae41f04d5a4244a8ebc23e51187e96">dwc_otg_core_global_regs::hptxfsiz</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Host Periodic Transmit FIFO Size Register. 
+<p>
+<em>Offset: 100h</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00140">140</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="efd9e780825f992dbc6cf46d2d72869e"></a><!-- doxytag: member="dwc_otg_core_global_regs::dptxfsiz_dieptxf" ref="efd9e780825f992dbc6cf46d2d72869e" args="[15]" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__core__global__regs.html#efd9e780825f992dbc6cf46d2d72869e">dwc_otg_core_global_regs::dptxfsiz_dieptxf</a>[15]          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Device Periodic Transmit FIFO::n Register if dedicated fifos are disabled, otherwise Device Transmit FIFO::n Register. 
+<p>
+<em>Offset: 104h + (FIFO_Number-1)*04h, 1 &lt;= FIFO Number &lt;= 15 (1&lt;=n&lt;=15).</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00144">144</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<hr>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__core__if.html b/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__core__if.html
new file mode 100644
index 000000000000..8f48162beefc
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__core__if.html
@@ -0,0 +1,190 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_core_if Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>dwc_otg_core_if Struct Reference</h1><!-- doxytag: class="dwc_otg_core_if" -->The <code><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if</a></code> structure contains information needed to manage the DWC_otg controller acting in either host or device mode.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="63ffc9b8e36340bd59bf1fab9ca490ad"></a><!-- doxytag: member="dwc_otg_core_if::core_params" ref="63ffc9b8e36340bd59bf1fab9ca490ad" args="" -->
+<a class="el" href="structdwc__otg__core__params.html">dwc_otg_core_params_t</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__if.html#63ffc9b8e36340bd59bf1fab9ca490ad">core_params</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Parameters that define how the core should be configured. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="909eae7e3b9432ca1e278b99f7811f52"></a><!-- doxytag: member="dwc_otg_core_if::core_global_regs" ref="909eae7e3b9432ca1e278b99f7811f52" args="" -->
+<a class="el" href="structdwc__otg__core__global__regs.html">dwc_otg_core_global_regs_t</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__if.html#909eae7e3b9432ca1e278b99f7811f52">core_global_regs</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Core Global registers starting at offset 000h. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="a0ed84d057445e2acd4c793f10f91078"></a><!-- doxytag: member="dwc_otg_core_if::dev_if" ref="a0ed84d057445e2acd4c793f10f91078" args="" -->
+<a class="el" href="structdwc__otg__dev__if.html">dwc_otg_dev_if_t</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__if.html#a0ed84d057445e2acd4c793f10f91078">dev_if</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Device-specific information. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="51bac71891b5f6f435d7fc4582b974c1"></a><!-- doxytag: member="dwc_otg_core_if::host_if" ref="51bac71891b5f6f435d7fc4582b974c1" args="" -->
+<a class="el" href="structdwc__otg__host__if.html">dwc_otg_host_if_t</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__if.html#51bac71891b5f6f435d7fc4582b974c1">host_if</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Host-specific information. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="afc495591efa54c74c1dd50278b57ffe"></a><!-- doxytag: member="dwc_otg_core_if::snpsid" ref="afc495591efa54c74c1dd50278b57ffe" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__if.html#afc495591efa54c74c1dd50278b57ffe">snpsid</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Value from SNPSID register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="24dd9dec510e5edac930538b81004b74"></a><!-- doxytag: member="dwc_otg_core_if::phy_init_done" ref="24dd9dec510e5edac930538b81004b74" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__if.html#24dd9dec510e5edac930538b81004b74">phy_init_done</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c2bb1913ed3fcc082a06d70242e9768a"></a><!-- doxytag: member="dwc_otg_core_if::srp_success" ref="c2bb1913ed3fcc082a06d70242e9768a" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__if.html#c2bb1913ed3fcc082a06d70242e9768a">srp_success</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="749cdeef193b7590b036a9b1d1442b73"></a><!-- doxytag: member="dwc_otg_core_if::srp_timer_started" ref="749cdeef193b7590b036a9b1d1442b73" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__if.html#749cdeef193b7590b036a9b1d1442b73">srp_timer_started</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="348ed2c9aeae6fc608f1bb813978b3f9"></a><!-- doxytag: member="dwc_otg_core_if::pcgcctl" ref="348ed2c9aeae6fc608f1bb813978b3f9" args="" -->
+volatile uint32_t *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__if.html#348ed2c9aeae6fc608f1bb813978b3f9">pcgcctl</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Power and Clock Gating Control Register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f99c868784a8269073bc251f88d92ee4"></a><!-- doxytag: member="dwc_otg_core_if::data_fifo" ref="f99c868784a8269073bc251f88d92ee4" args="[MAX_EPS_CHANNELS]" -->
+uint32_t *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__if.html#f99c868784a8269073bc251f88d92ee4">data_fifo</a> [MAX_EPS_CHANNELS]</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Push/pop addresses for endpoints or host channels. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="cae59008a554cb7de24bd4f2afea7532"></a><!-- doxytag: member="dwc_otg_core_if::total_fifo_size" ref="cae59008a554cb7de24bd4f2afea7532" args="" -->
+uint16_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__if.html#cae59008a554cb7de24bd4f2afea7532">total_fifo_size</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Total RAM for FIFOs (Bytes). <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="50bbb76c3818ada9ed2ea5527edabcd4"></a><!-- doxytag: member="dwc_otg_core_if::rx_fifo_size" ref="50bbb76c3818ada9ed2ea5527edabcd4" args="" -->
+uint16_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__if.html#50bbb76c3818ada9ed2ea5527edabcd4">rx_fifo_size</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Size of Rx FIFO (Bytes). <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="fb77b09f04a5687d2087726edd8dece6"></a><!-- doxytag: member="dwc_otg_core_if::nperio_tx_fifo_size" ref="fb77b09f04a5687d2087726edd8dece6" args="" -->
+uint16_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__if.html#fb77b09f04a5687d2087726edd8dece6">nperio_tx_fifo_size</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Size of Non-periodic Tx FIFO (Bytes). <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="5ade18c62c5101c603247691d3047a19"></a><!-- doxytag: member="dwc_otg_core_if::dma_enable" ref="5ade18c62c5101c603247691d3047a19" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__if.html#5ade18c62c5101c603247691d3047a19">dma_enable</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">1 if DMA is enabled, 0 otherwise. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7e3b96c6167eceeeb1090798f8297f1f"></a><!-- doxytag: member="dwc_otg_core_if::dma_desc_enable" ref="7e3b96c6167eceeeb1090798f8297f1f" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__if.html#7e3b96c6167eceeeb1090798f8297f1f">dma_desc_enable</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">1 if DMA descriptor is enabled, 0 otherwise. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="34540b79e9a14bfa234a52ac132c5cd1"></a><!-- doxytag: member="dwc_otg_core_if::pti_enh_enable" ref="34540b79e9a14bfa234a52ac132c5cd1" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__if.html#34540b79e9a14bfa234a52ac132c5cd1">pti_enh_enable</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">1 if PTI Enhancement mode is enabled, 0 otherwise. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="5675c8d8dd7df746fda9157dc39ba5c2"></a><!-- doxytag: member="dwc_otg_core_if::multiproc_int_enable" ref="5675c8d8dd7df746fda9157dc39ba5c2" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__if.html#5675c8d8dd7df746fda9157dc39ba5c2">multiproc_int_enable</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">1 if MPI Enhancement mode is enabled, 0 otherwise. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="31d08d1ebcd290b05139b0fcd24048ec"></a><!-- doxytag: member="dwc_otg_core_if::en_multiple_tx_fifo" ref="31d08d1ebcd290b05139b0fcd24048ec" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__if.html#31d08d1ebcd290b05139b0fcd24048ec">en_multiple_tx_fifo</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">1 if dedicated Tx FIFOs are enabled, 0 otherwise. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="5a6a90b40bc80e71d40f107b68f1e84c"></a><!-- doxytag: member="dwc_otg_core_if::queuing_high_bandwidth" ref="5a6a90b40bc80e71d40f107b68f1e84c" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__if.html#5a6a90b40bc80e71d40f107b68f1e84c">queuing_high_bandwidth</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Set to 1 if multiple packets of a high-bandwidth transfer is in process of being queued. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="d7c6a00c6d7c157ff60a044a28ec8b95"></a><!-- doxytag: member="dwc_otg_core_if::hwcfg1" ref="d7c6a00c6d7c157ff60a044a28ec8b95" args="" -->
+<a class="el" href="unionhwcfg1__data.html">hwcfg1_data_t</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__if.html#d7c6a00c6d7c157ff60a044a28ec8b95">hwcfg1</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Hardware Configuration -- stored here for convenience. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e5782c3dc6b5b7a25dfebd4b9bf258c5"></a><!-- doxytag: member="dwc_otg_core_if::hwcfg2" ref="e5782c3dc6b5b7a25dfebd4b9bf258c5" args="" -->
+<a class="el" href="unionhwcfg2__data.html">hwcfg2_data_t</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__if.html#e5782c3dc6b5b7a25dfebd4b9bf258c5">hwcfg2</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="91d0e0a5e8e048024c8846d12e00cecc"></a><!-- doxytag: member="dwc_otg_core_if::hwcfg3" ref="91d0e0a5e8e048024c8846d12e00cecc" args="" -->
+<a class="el" href="unionhwcfg3__data.html">hwcfg3_data_t</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__if.html#91d0e0a5e8e048024c8846d12e00cecc">hwcfg3</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="9c1394f3c46adde2fa7be79bf0237f9b"></a><!-- doxytag: member="dwc_otg_core_if::hwcfg4" ref="9c1394f3c46adde2fa7be79bf0237f9b" args="" -->
+<a class="el" href="unionhwcfg4__data.html">hwcfg4_data_t</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__if.html#9c1394f3c46adde2fa7be79bf0237f9b">hwcfg4</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="447a626f22ad64a90c68a6f49e624eb8"></a><!-- doxytag: member="dwc_otg_core_if::hcfg" ref="447a626f22ad64a90c68a6f49e624eb8" args="" -->
+<a class="el" href="unionhcfg__data.html">hcfg_data_t</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__if.html#447a626f22ad64a90c68a6f49e624eb8">hcfg</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Host and Device Configuration -- stored here for convenience. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="fcce854acc5b4afca80bd5667ecc4ef2"></a><!-- doxytag: member="dwc_otg_core_if::dcfg" ref="fcce854acc5b4afca80bd5667ecc4ef2" args="" -->
+<a class="el" href="uniondcfg__data.html">dcfg_data_t</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__if.html#fcce854acc5b4afca80bd5667ecc4ef2">dcfg</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="5a5c5c1cf8d870101cc1fffac56d88c0"></a><!-- doxytag: member="dwc_otg_core_if::op_state" ref="5a5c5c1cf8d870101cc1fffac56d88c0" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__if.html#5a5c5c1cf8d870101cc1fffac56d88c0">op_state</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">The operational State, during transations (a_host&gt;&gt;a_peripherial and b_device=&gt;b_host) this may not match the core but allows the software to determine transitions. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__if.html#05b4c81b19338fc64090cf22d635517a">restart_hcd_on_session_req</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Set to 1 if the HCD needs to be restarted on a session request interrupt.  <a href="#05b4c81b19338fc64090cf22d635517a"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="9a8568a762af68c9b0d97e0278cc26ba"></a><!-- doxytag: member="dwc_otg_core_if::hcd_cb" ref="9a8568a762af68c9b0d97e0278cc26ba" args="" -->
+<a class="el" href="structdwc__otg__cil__callbacks.html">dwc_otg_cil_callbacks</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__if.html#9a8568a762af68c9b0d97e0278cc26ba">hcd_cb</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">HCD callbacks. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="83bca1e02fafc4bbfa9c1f2eeb19b245"></a><!-- doxytag: member="dwc_otg_core_if::pcd_cb" ref="83bca1e02fafc4bbfa9c1f2eeb19b245" args="" -->
+<a class="el" href="structdwc__otg__cil__callbacks.html">dwc_otg_cil_callbacks</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__if.html#83bca1e02fafc4bbfa9c1f2eeb19b245">pcd_cb</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">PCD callbacks. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="0683b28ebf5247a60247d27a1a714d27"></a><!-- doxytag: member="dwc_otg_core_if::p_tx_msk" ref="0683b28ebf5247a60247d27a1a714d27" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__if.html#0683b28ebf5247a60247d27a1a714d27">p_tx_msk</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Device mode Periodic Tx FIFO Mask. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b558bae74403677f08e45c692a88d4e2"></a><!-- doxytag: member="dwc_otg_core_if::tx_msk" ref="b558bae74403677f08e45c692a88d4e2" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__if.html#b558bae74403677f08e45c692a88d4e2">tx_msk</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Device mode Periodic Tx FIFO Mask. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7e3716f6d6bc6f956a45efbe6e308386"></a><!-- doxytag: member="dwc_otg_core_if::wq_otg" ref="7e3716f6d6bc6f956a45efbe6e308386" args="" -->
+dwc_workq_t *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__if.html#7e3716f6d6bc6f956a45efbe6e308386">wq_otg</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Workqueue object used for handling several interrupts. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c914461f460deacd426bea7a05ebb204"></a><!-- doxytag: member="dwc_otg_core_if::wkp_timer" ref="c914461f460deacd426bea7a05ebb204" args="" -->
+dwc_timer_t *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__if.html#c914461f460deacd426bea7a05ebb204">wkp_timer</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Timer object used for handling "Wakeup Detected" Interrupt. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="2b0701d814069ec69897e08374366c7b"></a><!-- doxytag: member="dwc_otg_core_if::lx_state" ref="2b0701d814069ec69897e08374366c7b" args="" -->
+dwc_otg_lx_state_e&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__if.html#2b0701d814069ec69897e08374366c7b">lx_state</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Lx state of device. <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+The <code><a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if</a></code> structure contains information needed to manage the DWC_otg controller acting in either host or device mode. 
+<p>
+It represents the programming view of the controller as a whole. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8h-source.html#l00680">680</a> of file <a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a>.<hr><h2>Field Documentation</h2>
+<a class="anchor" name="05b4c81b19338fc64090cf22d635517a"></a><!-- doxytag: member="dwc_otg_core_if::restart_hcd_on_session_req" ref="05b4c81b19338fc64090cf22d635517a" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint8_t <a class="el" href="structdwc__otg__core__if.html#05b4c81b19338fc64090cf22d635517a">dwc_otg_core_if::restart_hcd_on_session_req</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Set to 1 if the HCD needs to be restarted on a session request interrupt. 
+<p>
+This is required if no connector ID status change has occurred since the HCD was last disconnected. 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8h-source.html#l00765">765</a> of file <a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a>.
+</div>
+</div><p>
+<hr>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__core__params.html b/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__core__params.html
new file mode 100644
index 000000000000..1782671ddf3d
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__core__params.html
@@ -0,0 +1,606 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_core_params Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>dwc_otg_core_params Struct Reference</h1><!-- doxytag: class="dwc_otg_core_params" -->The following parameters may be specified when starting the module.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="6d67db1b1152d788bf2fc7fdc6363f78"></a><!-- doxytag: member="dwc_otg_core_params::opt" ref="6d67db1b1152d788bf2fc7fdc6363f78" args="" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__params.html#6d67db1b1152d788bf2fc7fdc6363f78">opt</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__params.html#b6960c28e9c7d82dca37645726c8f7ce">otg_cap</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Specifies the OTG capabilities.  <a href="#b6960c28e9c7d82dca37645726c8f7ce"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__params.html#3c791cb4898379d156acc47c5b9a84fc">dma_enable</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Specifies whether to use slave or DMA mode for accessing the data FIFOs.  <a href="#3c791cb4898379d156acc47c5b9a84fc"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__params.html#36c5bcf00d0f776b5c9e84e5d8ae408d">dma_desc_enable</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">When DMA mode is enabled specifies whether to use address DMA or DMA Descritor mode for accessing the data FIFOs in device mode.  <a href="#36c5bcf00d0f776b5c9e84e5d8ae408d"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__params.html#f9d2a8cd9b36d24de89121d19f693ccb">dma_burst_size</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">The DMA Burst size (applicable only for External DMA Mode).  <a href="#f9d2a8cd9b36d24de89121d19f693ccb"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__params.html#d2c4f622f1c14f68c6e60e2603acd09d">speed</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Specifies the maximum speed of operation in host and device mode.  <a href="#d2c4f622f1c14f68c6e60e2603acd09d"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__params.html#85cad588a450b8497347af9cf166bfde">host_support_fs_ls_low_power</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Specifies whether low power mode is supported when attached to a Full Speed or Low Speed device in host mode.  <a href="#85cad588a450b8497347af9cf166bfde"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__params.html#98f413798f20dc40036a2ec527935a7d">host_ls_low_power_phy_clk</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Specifies the PHY clock rate in low power mode when connected to a Low Speed device in host mode.  <a href="#98f413798f20dc40036a2ec527935a7d"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="8c169633d4a6f28e964cef9f597c6e03"></a><!-- doxytag: member="dwc_otg_core_params::enable_dynamic_fifo" ref="8c169633d4a6f28e964cef9f597c6e03" args="" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__params.html#8c169633d4a6f28e964cef9f597c6e03">enable_dynamic_fifo</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">0 - Use cC FIFO size parameters 1 - Allow dynamic FIFO sizing (default) <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__params.html#3d8dc206f54165f52c7f8599731d0f95">data_fifo_size</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Total number of 4-byte words in the data FIFO memory.  <a href="#3d8dc206f54165f52c7f8599731d0f95"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__params.html#24ea6f9329f64ac0ad2d31dafe0d1d8c">dev_rx_fifo_size</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Number of 4-byte words in the Rx FIFO in device mode when dynamic FIFO sizing is enabled.  <a href="#24ea6f9329f64ac0ad2d31dafe0d1d8c"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__params.html#d08d9aee1fb4e6508089415d6150176e">dev_nperio_tx_fifo_size</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Number of 4-byte words in the non-periodic Tx FIFO in device mode when dynamic FIFO sizing is enabled.  <a href="#d08d9aee1fb4e6508089415d6150176e"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__params.html#2958d325289f4a77b6435cda729e5f6e">dev_perio_tx_fifo_size</a> [MAX_PERIO_FIFOS]</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Number of 4-byte words in each of the periodic Tx FIFOs in device mode when dynamic FIFO sizing is enabled.  <a href="#2958d325289f4a77b6435cda729e5f6e"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__params.html#2b2ab9c2fe16db70b136515b2e981f6b">host_rx_fifo_size</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO sizing is enabled.  <a href="#2b2ab9c2fe16db70b136515b2e981f6b"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__params.html#6ff00857d99f72c0cfd6198cbcfab9a7">host_nperio_tx_fifo_size</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Number of 4-byte words in the non-periodic Tx FIFO in host mode when Dynamic FIFO sizing is enabled in the core.  <a href="#6ff00857d99f72c0cfd6198cbcfab9a7"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__params.html#5bc3cac5c81fd8d6fd291ca4b7de3e28">host_perio_tx_fifo_size</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO sizing is enabled.  <a href="#5bc3cac5c81fd8d6fd291ca4b7de3e28"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__params.html#e614d1d2ee740cd972ca76ed0dffec74">max_transfer_size</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">The maximum transfer size supported in bytes.  <a href="#e614d1d2ee740cd972ca76ed0dffec74"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__params.html#e17230afa013a15beda38565d19fa933">max_packet_count</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">The maximum number of packets in a transfer.  <a href="#e17230afa013a15beda38565d19fa933"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__params.html#c1b433c6965aa7d48f6ca6818c592039">host_channels</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">The number of host channel registers to use.  <a href="#c1b433c6965aa7d48f6ca6818c592039"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__params.html#17d0dda7fe2cd51726cd1dd34c57b94a">dev_endpoints</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">The number of endpoints in addition to EP0 available for device mode operations.  <a href="#17d0dda7fe2cd51726cd1dd34c57b94a"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__params.html#8b5d4e0c98c46d0d4e80b6faf66daf72">phy_type</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Specifies the type of PHY interface to use.  <a href="#8b5d4e0c98c46d0d4e80b6faf66daf72"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__params.html#41f5a03ab1b68564b240e03f33a09dde">phy_utmi_width</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Specifies the UTMI+ Data Width.  <a href="#41f5a03ab1b68564b240e03f33a09dde"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__params.html#6fc9a3fbe3c36cbbc231f1642ee96cfe">phy_ulpi_ddr</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Specifies whether the ULPI operates at double or single data rate.  <a href="#6fc9a3fbe3c36cbbc231f1642ee96cfe"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3b6fa0a7fe7d7f87326894fdbe0aa375"></a><!-- doxytag: member="dwc_otg_core_params::phy_ulpi_ext_vbus" ref="3b6fa0a7fe7d7f87326894fdbe0aa375" args="" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__params.html#3b6fa0a7fe7d7f87326894fdbe0aa375">phy_ulpi_ext_vbus</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Specifies whether to use the internal or external supply to drive the vbus with a ULPI phy. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__params.html#6b0a0ab15284a541ae079beecaf3e617">i2c_enable</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Specifies whether to use the I2Cinterface for full speed PHY.  <a href="#6b0a0ab15284a541ae079beecaf3e617"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3d7cfc3c416010102b2c671dfaa828d5"></a><!-- doxytag: member="dwc_otg_core_params::ulpi_fs_ls" ref="3d7cfc3c416010102b2c671dfaa828d5" args="" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__params.html#3d7cfc3c416010102b2c671dfaa828d5">ulpi_fs_ls</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="879afefd6e13233a78d74ee71d3ee75e"></a><!-- doxytag: member="dwc_otg_core_params::ts_dline" ref="879afefd6e13233a78d74ee71d3ee75e" args="" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__params.html#879afefd6e13233a78d74ee71d3ee75e">ts_dline</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="d61279dcea66973b2915e335efb07fe3"></a><!-- doxytag: member="dwc_otg_core_params::en_multiple_tx_fifo" ref="d61279dcea66973b2915e335efb07fe3" args="" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__params.html#d61279dcea66973b2915e335efb07fe3">en_multiple_tx_fifo</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Specifies whether dedicated transmit FIFOs are enabled for non periodic IN endpoints in device mode 0 - No 1 - Yes. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__params.html#6e0c5d06467fbf3458f11f7eb8153a8b">dev_tx_fifo_size</a> [MAX_TX_FIFOS]</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Number of 4-byte words in each of the Tx FIFOs in device mode when dynamic FIFO sizing is enabled.  <a href="#6e0c5d06467fbf3458f11f7eb8153a8b"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="1610a4b28bea581c46f251d995bf4a51"></a><!-- doxytag: member="dwc_otg_core_params::thr_ctl" ref="1610a4b28bea581c46f251d995bf4a51" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__params.html#1610a4b28bea581c46f251d995bf4a51">thr_ctl</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Thresholding enable flag- bit 0 - enable non-ISO Tx thresholding bit 1 - enable ISO Tx thresholding bit 2 - enable Rx thresholding. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c92fc907d503f9b8bb3600164c520b0e"></a><!-- doxytag: member="dwc_otg_core_params::tx_thr_length" ref="c92fc907d503f9b8bb3600164c520b0e" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__params.html#c92fc907d503f9b8bb3600164c520b0e">tx_thr_length</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Thresholding length for Tx FIFOs in 32 bit DWORDs. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="2cb1f83013e357828fbf55ac91971d44"></a><!-- doxytag: member="dwc_otg_core_params::rx_thr_length" ref="2cb1f83013e357828fbf55ac91971d44" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__params.html#2cb1f83013e357828fbf55ac91971d44">rx_thr_length</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Thresholding length for Rx FIFOs in 32 bit DWORDs. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="8b906ba765a10dd9fcfa1c02dbc0184e"></a><!-- doxytag: member="dwc_otg_core_params::lpm_enable" ref="8b906ba765a10dd9fcfa1c02dbc0184e" args="" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__params.html#8b906ba765a10dd9fcfa1c02dbc0184e">lpm_enable</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Specifies whether LPM (Link Power Management) support is enabled. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b601fde03b371b74deab1205e1329a7d"></a><!-- doxytag: member="dwc_otg_core_params::pti_enable" ref="b601fde03b371b74deab1205e1329a7d" args="" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__params.html#b601fde03b371b74deab1205e1329a7d">pti_enable</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Per Transfer Interrupt mode enable flag 1 - Enabled 0 - Disabled. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="740e50199a75b3877b7db630d49c36aa"></a><!-- doxytag: member="dwc_otg_core_params::mpi_enable" ref="740e50199a75b3877b7db630d49c36aa" args="" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__params.html#740e50199a75b3877b7db630d49c36aa">mpi_enable</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Multi Processor Interrupt mode enable flag 1 - Enabled 0 - Disabled. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="359a3cb3a7b4800a0c32750005c9fd1b"></a><!-- doxytag: member="dwc_otg_core_params::ic_usb_cap" ref="359a3cb3a7b4800a0c32750005c9fd1b" args="" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__params.html#359a3cb3a7b4800a0c32750005c9fd1b">ic_usb_cap</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">IS_USB Capability 1 - Enabled 0 - Disabled. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="8787af52f8d70a9100ab1fa2b0f69bfb"></a><!-- doxytag: member="dwc_otg_core_params::ahb_thr_ratio" ref="8787af52f8d70a9100ab1fa2b0f69bfb" args="" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__core__params.html#8787af52f8d70a9100ab1fa2b0f69bfb">ahb_thr_ratio</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">AHB Threshold Ratio 2'b00 AHB Threshold = MAC Threshold 2'b01 AHB Threshold = 1/2 MAC Threshold 2'b10 AHB Threshold = 1/4 MAC Threshold 2'b11 AHB Threshold = 1/8 MAC Threshold. <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+The following parameters may be specified when starting the module. 
+<p>
+These parameters define how the DWC_otg controller should be configured. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8h-source.html#l00401">401</a> of file <a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a>.<hr><h2>Field Documentation</h2>
+<a class="anchor" name="b6960c28e9c7d82dca37645726c8f7ce"></a><!-- doxytag: member="dwc_otg_core_params::otg_cap" ref="b6960c28e9c7d82dca37645726c8f7ce" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t <a class="el" href="structdwc__otg__core__params.html#b6960c28e9c7d82dca37645726c8f7ce">dwc_otg_core_params::otg_cap</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Specifies the OTG capabilities. 
+<p>
+The driver will automatically detect the value for this parameter if none is specified. 0 - HNP and SRP capable (default) 1 - SRP Only capable 2 - No HNP/SRP capable 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8h-source.html#l00411">411</a> of file <a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="3c791cb4898379d156acc47c5b9a84fc"></a><!-- doxytag: member="dwc_otg_core_params::dma_enable" ref="3c791cb4898379d156acc47c5b9a84fc" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t <a class="el" href="structdwc__otg__core__params.html#3c791cb4898379d156acc47c5b9a84fc">dwc_otg_core_params::dma_enable</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Specifies whether to use slave or DMA mode for accessing the data FIFOs. 
+<p>
+The driver will automatically detect the value for this parameter if none is specified. 0 - Slave 1 - DMA (default, if available) 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8h-source.html#l00420">420</a> of file <a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="36c5bcf00d0f776b5c9e84e5d8ae408d"></a><!-- doxytag: member="dwc_otg_core_params::dma_desc_enable" ref="36c5bcf00d0f776b5c9e84e5d8ae408d" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t <a class="el" href="structdwc__otg__core__params.html#36c5bcf00d0f776b5c9e84e5d8ae408d">dwc_otg_core_params::dma_desc_enable</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+When DMA mode is enabled specifies whether to use address DMA or DMA Descritor mode for accessing the data FIFOs in device mode. 
+<p>
+The driver will automatically detect the value for this parameter if none is specified. 0 - address DMA 1 - DMA Descriptor(default, if available) 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8h-source.html#l00429">429</a> of file <a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="f9d2a8cd9b36d24de89121d19f693ccb"></a><!-- doxytag: member="dwc_otg_core_params::dma_burst_size" ref="f9d2a8cd9b36d24de89121d19f693ccb" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t <a class="el" href="structdwc__otg__core__params.html#f9d2a8cd9b36d24de89121d19f693ccb">dwc_otg_core_params::dma_burst_size</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+The DMA Burst size (applicable only for External DMA Mode). 
+<p>
+1, 4, 8 16, 32, 64, 128, 256 (default 32) 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8h-source.html#l00433">433</a> of file <a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="d2c4f622f1c14f68c6e60e2603acd09d"></a><!-- doxytag: member="dwc_otg_core_params::speed" ref="d2c4f622f1c14f68c6e60e2603acd09d" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t <a class="el" href="structdwc__otg__core__params.html#d2c4f622f1c14f68c6e60e2603acd09d">dwc_otg_core_params::speed</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Specifies the maximum speed of operation in host and device mode. 
+<p>
+The actual speed depends on the speed of the attached device and the value of phy_type. The actual speed depends on the speed of the attached device. 0 - High Speed (default) 1 - Full Speed 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8h-source.html#l00443">443</a> of file <a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="85cad588a450b8497347af9cf166bfde"></a><!-- doxytag: member="dwc_otg_core_params::host_support_fs_ls_low_power" ref="85cad588a450b8497347af9cf166bfde" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t <a class="el" href="structdwc__otg__core__params.html#85cad588a450b8497347af9cf166bfde">dwc_otg_core_params::host_support_fs_ls_low_power</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Specifies whether low power mode is supported when attached to a Full Speed or Low Speed device in host mode. 
+<p>
+0 - Don't support low power mode (default) 1 - Support low power mode 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8h-source.html#l00449">449</a> of file <a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="98f413798f20dc40036a2ec527935a7d"></a><!-- doxytag: member="dwc_otg_core_params::host_ls_low_power_phy_clk" ref="98f413798f20dc40036a2ec527935a7d" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t <a class="el" href="structdwc__otg__core__params.html#98f413798f20dc40036a2ec527935a7d">dwc_otg_core_params::host_ls_low_power_phy_clk</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Specifies the PHY clock rate in low power mode when connected to a Low Speed device in host mode. 
+<p>
+This parameter is applicable only if HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS then defaults to 6 MHZ otherwise 48 MHZ.<p>
+0 - 48 MHz 1 - 6 MHz 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8h-source.html#l00459">459</a> of file <a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="3d8dc206f54165f52c7f8599731d0f95"></a><!-- doxytag: member="dwc_otg_core_params::data_fifo_size" ref="3d8dc206f54165f52c7f8599731d0f95" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t <a class="el" href="structdwc__otg__core__params.html#3d8dc206f54165f52c7f8599731d0f95">dwc_otg_core_params::data_fifo_size</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Total number of 4-byte words in the data FIFO memory. 
+<p>
+This memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs. 32 to 32768 (default 8192) Note: The total FIFO memory depth in the FPGA configuration is 8192. 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8h-source.html#l00473">473</a> of file <a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="24ea6f9329f64ac0ad2d31dafe0d1d8c"></a><!-- doxytag: member="dwc_otg_core_params::dev_rx_fifo_size" ref="24ea6f9329f64ac0ad2d31dafe0d1d8c" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t <a class="el" href="structdwc__otg__core__params.html#24ea6f9329f64ac0ad2d31dafe0d1d8c">dwc_otg_core_params::dev_rx_fifo_size</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Number of 4-byte words in the Rx FIFO in device mode when dynamic FIFO sizing is enabled. 
+<p>
+16 to 32768 (default 1064) 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8h-source.html#l00479">479</a> of file <a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="d08d9aee1fb4e6508089415d6150176e"></a><!-- doxytag: member="dwc_otg_core_params::dev_nperio_tx_fifo_size" ref="d08d9aee1fb4e6508089415d6150176e" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t <a class="el" href="structdwc__otg__core__params.html#d08d9aee1fb4e6508089415d6150176e">dwc_otg_core_params::dev_nperio_tx_fifo_size</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Number of 4-byte words in the non-periodic Tx FIFO in device mode when dynamic FIFO sizing is enabled. 
+<p>
+16 to 32768 (default 1024) 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8h-source.html#l00485">485</a> of file <a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="2958d325289f4a77b6435cda729e5f6e"></a><!-- doxytag: member="dwc_otg_core_params::dev_perio_tx_fifo_size" ref="2958d325289f4a77b6435cda729e5f6e" args="[MAX_PERIO_FIFOS]" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t <a class="el" href="structdwc__otg__core__params.html#2958d325289f4a77b6435cda729e5f6e">dwc_otg_core_params::dev_perio_tx_fifo_size</a>[MAX_PERIO_FIFOS]          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Number of 4-byte words in each of the periodic Tx FIFOs in device mode when dynamic FIFO sizing is enabled. 
+<p>
+4 to 768 (default 256) 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8h-source.html#l00491">491</a> of file <a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="2b2ab9c2fe16db70b136515b2e981f6b"></a><!-- doxytag: member="dwc_otg_core_params::host_rx_fifo_size" ref="2b2ab9c2fe16db70b136515b2e981f6b" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t <a class="el" href="structdwc__otg__core__params.html#2b2ab9c2fe16db70b136515b2e981f6b">dwc_otg_core_params::host_rx_fifo_size</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO sizing is enabled. 
+<p>
+16 to 32768 (default 1024) 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8h-source.html#l00497">497</a> of file <a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="6ff00857d99f72c0cfd6198cbcfab9a7"></a><!-- doxytag: member="dwc_otg_core_params::host_nperio_tx_fifo_size" ref="6ff00857d99f72c0cfd6198cbcfab9a7" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t <a class="el" href="structdwc__otg__core__params.html#6ff00857d99f72c0cfd6198cbcfab9a7">dwc_otg_core_params::host_nperio_tx_fifo_size</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Number of 4-byte words in the non-periodic Tx FIFO in host mode when Dynamic FIFO sizing is enabled in the core. 
+<p>
+16 to 32768 (default 1024) 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8h-source.html#l00503">503</a> of file <a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="5bc3cac5c81fd8d6fd291ca4b7de3e28"></a><!-- doxytag: member="dwc_otg_core_params::host_perio_tx_fifo_size" ref="5bc3cac5c81fd8d6fd291ca4b7de3e28" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t <a class="el" href="structdwc__otg__core__params.html#5bc3cac5c81fd8d6fd291ca4b7de3e28">dwc_otg_core_params::host_perio_tx_fifo_size</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO sizing is enabled. 
+<p>
+16 to 32768 (default 1024) 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8h-source.html#l00509">509</a> of file <a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="e614d1d2ee740cd972ca76ed0dffec74"></a><!-- doxytag: member="dwc_otg_core_params::max_transfer_size" ref="e614d1d2ee740cd972ca76ed0dffec74" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t <a class="el" href="structdwc__otg__core__params.html#e614d1d2ee740cd972ca76ed0dffec74">dwc_otg_core_params::max_transfer_size</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+The maximum transfer size supported in bytes. 
+<p>
+2047 to 65,535 (default 65,535) 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8h-source.html#l00514">514</a> of file <a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="e17230afa013a15beda38565d19fa933"></a><!-- doxytag: member="dwc_otg_core_params::max_packet_count" ref="e17230afa013a15beda38565d19fa933" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t <a class="el" href="structdwc__otg__core__params.html#e17230afa013a15beda38565d19fa933">dwc_otg_core_params::max_packet_count</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+The maximum number of packets in a transfer. 
+<p>
+15 to 511 (default 511) 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8h-source.html#l00519">519</a> of file <a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="c1b433c6965aa7d48f6ca6818c592039"></a><!-- doxytag: member="dwc_otg_core_params::host_channels" ref="c1b433c6965aa7d48f6ca6818c592039" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t <a class="el" href="structdwc__otg__core__params.html#c1b433c6965aa7d48f6ca6818c592039">dwc_otg_core_params::host_channels</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+The number of host channel registers to use. 
+<p>
+1 to 16 (default 12) Note: The FPGA configuration supports a maximum of 12 host channels. 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8h-source.html#l00525">525</a> of file <a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="17d0dda7fe2cd51726cd1dd34c57b94a"></a><!-- doxytag: member="dwc_otg_core_params::dev_endpoints" ref="17d0dda7fe2cd51726cd1dd34c57b94a" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t <a class="el" href="structdwc__otg__core__params.html#17d0dda7fe2cd51726cd1dd34c57b94a">dwc_otg_core_params::dev_endpoints</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+The number of endpoints in addition to EP0 available for device mode operations. 
+<p>
+1 to 15 (default 6 IN and OUT) Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in addition to EP0. 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8h-source.html#l00533">533</a> of file <a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="8b5d4e0c98c46d0d4e80b6faf66daf72"></a><!-- doxytag: member="dwc_otg_core_params::phy_type" ref="8b5d4e0c98c46d0d4e80b6faf66daf72" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t <a class="el" href="structdwc__otg__core__params.html#8b5d4e0c98c46d0d4e80b6faf66daf72">dwc_otg_core_params::phy_type</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Specifies the type of PHY interface to use. 
+<p>
+By default, the driver will automatically detect the phy_type.<p>
+0 - Full Speed PHY 1 - UTMI+ (default) 2 - ULPI 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8h-source.html#l00543">543</a> of file <a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="41f5a03ab1b68564b240e03f33a09dde"></a><!-- doxytag: member="dwc_otg_core_params::phy_utmi_width" ref="41f5a03ab1b68564b240e03f33a09dde" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t <a class="el" href="structdwc__otg__core__params.html#41f5a03ab1b68564b240e03f33a09dde">dwc_otg_core_params::phy_utmi_width</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Specifies the UTMI+ Data Width. 
+<p>
+This parameter is applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI PHY_TYPE, this parameter indicates the data width between the MAC and the ULPI Wrapper.) Also, this parameter is applicable only if the OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the core has been configured to work at either data path width.<p>
+8 or 16 bits (default 16) 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8h-source.html#l00556">556</a> of file <a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="6fc9a3fbe3c36cbbc231f1642ee96cfe"></a><!-- doxytag: member="dwc_otg_core_params::phy_ulpi_ddr" ref="6fc9a3fbe3c36cbbc231f1642ee96cfe" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t <a class="el" href="structdwc__otg__core__params.html#6fc9a3fbe3c36cbbc231f1642ee96cfe">dwc_otg_core_params::phy_ulpi_ddr</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Specifies whether the ULPI operates at double or single data rate. 
+<p>
+This parameter is only applicable if PHY_TYPE is ULPI.<p>
+0 - single data rate ULPI interface with 8 bit wide data bus (default) 1 - double data rate ULPI interface with 4 bit wide data bus 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8h-source.html#l00568">568</a> of file <a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="6b0a0ab15284a541ae079beecaf3e617"></a><!-- doxytag: member="dwc_otg_core_params::i2c_enable" ref="6b0a0ab15284a541ae079beecaf3e617" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t <a class="el" href="structdwc__otg__core__params.html#6b0a0ab15284a541ae079beecaf3e617">dwc_otg_core_params::i2c_enable</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Specifies whether to use the I2Cinterface for full speed PHY. 
+<p>
+This parameter is only applicable if PHY_TYPE is FS. 0 - No (default) 1 - Yes 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8h-source.html#l00582">582</a> of file <a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="6e0c5d06467fbf3458f11f7eb8153a8b"></a><!-- doxytag: member="dwc_otg_core_params::dev_tx_fifo_size" ref="6e0c5d06467fbf3458f11f7eb8153a8b" args="[MAX_TX_FIFOS]" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t <a class="el" href="structdwc__otg__core__params.html#6e0c5d06467fbf3458f11f7eb8153a8b">dwc_otg_core_params::dev_tx_fifo_size</a>[MAX_TX_FIFOS]          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Number of 4-byte words in each of the Tx FIFOs in device mode when dynamic FIFO sizing is enabled. 
+<p>
+4 to 768 (default 256) 
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8h-source.html#l00600">600</a> of file <a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a>.
+</div>
+</div><p>
+<hr>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__dev__dma__desc.html b/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__dev__dma__desc.html
new file mode 100644
index 000000000000..7c9468d6f4ee
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__dev__dma__desc.html
@@ -0,0 +1,50 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_dev_dma_desc Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>dwc_otg_dev_dma_desc Struct Reference</h1><!-- doxytag: class="dwc_otg_dev_dma_desc" -->DMA Descriptor structure.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ab81bc9b2bca330e2dda8941b17c85ba"></a><!-- doxytag: member="dwc_otg_dev_dma_desc::status" ref="ab81bc9b2bca330e2dda8941b17c85ba" args="" -->
+<a class="el" href="uniondev__dma__desc__sts.html">dev_dma_desc_sts_t</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__dma__desc.html#ab81bc9b2bca330e2dda8941b17c85ba">status</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">DMA Descriptor status quadlet. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="0454dad420ef536fe5eb7c38ef764430"></a><!-- doxytag: member="dwc_otg_dev_dma_desc::buf" ref="0454dad420ef536fe5eb7c38ef764430" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__dma__desc.html#0454dad420ef536fe5eb7c38ef764430">buf</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">DMA Descriptor data buffer pointer. <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+DMA Descriptor structure. 
+<p>
+DMA Descriptor structure contains two quadlets: Status quadlet and Data buffer pointer. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01542">1542</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__dev__global__regs.html b/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__dev__global__regs.html
new file mode 100644
index 000000000000..ba941d9847e8
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__dev__global__regs.html
@@ -0,0 +1,441 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_dev_global_regs Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>dwc_otg_dev_global_regs Struct Reference</h1><!-- doxytag: class="dwc_otg_dev_global_regs" -->Device Global Registers.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__global__regs.html#c0c24937bbd7184884f05343f56ef1da">dcfg</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Device Configuration Register.  <a href="#c0c24937bbd7184884f05343f56ef1da"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__global__regs.html#3779c2fc508920a831a59e696a8fa785">dctl</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Device Control Register.  <a href="#3779c2fc508920a831a59e696a8fa785"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__global__regs.html#1ed00edd20ce5db7d07666804101ec05">dsts</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Device Status Register (Read Only).  <a href="#1ed00edd20ce5db7d07666804101ec05"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__global__regs.html#8d6452da1d0e266737d77e55fc15f72c">unused</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Reserved.  <a href="#8d6452da1d0e266737d77e55fc15f72c"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__global__regs.html#02e44cb182548d78c5b7d27929ca5f11">diepmsk</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Device IN Endpoint Common Interrupt Mask Register.  <a href="#02e44cb182548d78c5b7d27929ca5f11"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__global__regs.html#d6947be9d84a1d87156f81a10ebb036b">doepmsk</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Device OUT Endpoint Common Interrupt Mask Register.  <a href="#d6947be9d84a1d87156f81a10ebb036b"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__global__regs.html#2e25df2fbec9d398742709524056cbd5">daint</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Device All Endpoints Interrupt Register.  <a href="#2e25df2fbec9d398742709524056cbd5"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__global__regs.html#5def6c3850c041928b9a662422ee0679">daintmsk</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Device All Endpoints Interrupt Mask Register.  <a href="#5def6c3850c041928b9a662422ee0679"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__global__regs.html#b130a76736e0e81d5a020651109352de">dtknqr1</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Device IN Token Queue Read Register-1 (Read Only).  <a href="#b130a76736e0e81d5a020651109352de"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__global__regs.html#27968db886161264e7820bcf4a746e5d">dtknqr2</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Device IN Token Queue Read Register-2 (Read Only).  <a href="#27968db886161264e7820bcf4a746e5d"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__global__regs.html#95088e182c3ff164d1b331bb196eb95d">dvbusdis</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Device VBUS discharge Register.  <a href="#95088e182c3ff164d1b331bb196eb95d"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__global__regs.html#8747dbe01b5a4cbd2c980bf39fdb4737">dvbuspulse</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Device VBUS Pulse Register.  <a href="#8747dbe01b5a4cbd2c980bf39fdb4737"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__global__regs.html#c263c55a0bb752f8939731aa2f8f6cb8">dtknqr3_dthrctl</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Device IN Token Queue Read Register-3 (Read Only).  <a href="#c263c55a0bb752f8939731aa2f8f6cb8"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__global__regs.html#fbc2b776c2150842813e4681dd43bedc">dtknqr4_fifoemptymsk</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Device IN Token Queue Read Register-4 (Read Only).  <a href="#fbc2b776c2150842813e4681dd43bedc"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__global__regs.html#4795bc8eab569241a3f8e6aad5d99ac7">deachint</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Device Each Endpoint Interrupt Register (Read Only).  <a href="#4795bc8eab569241a3f8e6aad5d99ac7"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__global__regs.html#e64a153683f0e0cda14b56a163651825">deachintmsk</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Device Each Endpoint Interrupt mask Register (Read/Write).  <a href="#e64a153683f0e0cda14b56a163651825"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__global__regs.html#aaf2a5c6be4130d558c291f6aaeeca4f">diepeachintmsk</a> [MAX_EPS_CHANNELS]</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Device Each In Endpoint Interrupt mask Register (Read/Write).  <a href="#aaf2a5c6be4130d558c291f6aaeeca4f"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__global__regs.html#304e089ed2d36d9076228b8d7e1cc515">doepeachintmsk</a> [MAX_EPS_CHANNELS]</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Device Each Out Endpoint Interrupt mask Register (Read/Write).  <a href="#304e089ed2d36d9076228b8d7e1cc515"></a><br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+Device Global Registers. 
+<p>
+<em>Offsets 800h-BFFh</em><p>
+The following structures define the size and relative field offsets for the Device Mode Registers.<p>
+<em>These registers are visible only in Device mode and must not be accessed in Host mode, as the results are unknown.</em> 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00865">865</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr><h2>Field Documentation</h2>
+<a class="anchor" name="c0c24937bbd7184884f05343f56ef1da"></a><!-- doxytag: member="dwc_otg_dev_global_regs::dcfg" ref="c0c24937bbd7184884f05343f56ef1da" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__dev__global__regs.html#c0c24937bbd7184884f05343f56ef1da">dwc_otg_dev_global_regs::dcfg</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Device Configuration Register. 
+<p>
+<em>Offset 800h</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00867">867</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="3779c2fc508920a831a59e696a8fa785"></a><!-- doxytag: member="dwc_otg_dev_global_regs::dctl" ref="3779c2fc508920a831a59e696a8fa785" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__dev__global__regs.html#3779c2fc508920a831a59e696a8fa785">dwc_otg_dev_global_regs::dctl</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Device Control Register. 
+<p>
+<em>Offset: 804h</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00869">869</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="1ed00edd20ce5db7d07666804101ec05"></a><!-- doxytag: member="dwc_otg_dev_global_regs::dsts" ref="1ed00edd20ce5db7d07666804101ec05" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__dev__global__regs.html#1ed00edd20ce5db7d07666804101ec05">dwc_otg_dev_global_regs::dsts</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Device Status Register (Read Only). 
+<p>
+<em>Offset: 808h</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00871">871</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="8d6452da1d0e266737d77e55fc15f72c"></a><!-- doxytag: member="dwc_otg_dev_global_regs::unused" ref="8d6452da1d0e266737d77e55fc15f72c" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t <a class="el" href="structdwc__otg__dev__global__regs.html#8d6452da1d0e266737d77e55fc15f72c">dwc_otg_dev_global_regs::unused</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Reserved. 
+<p>
+<em>Offset: 80Ch</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00873">873</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="02e44cb182548d78c5b7d27929ca5f11"></a><!-- doxytag: member="dwc_otg_dev_global_regs::diepmsk" ref="02e44cb182548d78c5b7d27929ca5f11" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__dev__global__regs.html#02e44cb182548d78c5b7d27929ca5f11">dwc_otg_dev_global_regs::diepmsk</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Device IN Endpoint Common Interrupt Mask Register. 
+<p>
+<em>Offset: 810h</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00876">876</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="d6947be9d84a1d87156f81a10ebb036b"></a><!-- doxytag: member="dwc_otg_dev_global_regs::doepmsk" ref="d6947be9d84a1d87156f81a10ebb036b" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__dev__global__regs.html#d6947be9d84a1d87156f81a10ebb036b">dwc_otg_dev_global_regs::doepmsk</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Device OUT Endpoint Common Interrupt Mask Register. 
+<p>
+<em>Offset: 814h</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00879">879</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="2e25df2fbec9d398742709524056cbd5"></a><!-- doxytag: member="dwc_otg_dev_global_regs::daint" ref="2e25df2fbec9d398742709524056cbd5" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__dev__global__regs.html#2e25df2fbec9d398742709524056cbd5">dwc_otg_dev_global_regs::daint</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Device All Endpoints Interrupt Register. 
+<p>
+<em>Offset: 818h</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00881">881</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="5def6c3850c041928b9a662422ee0679"></a><!-- doxytag: member="dwc_otg_dev_global_regs::daintmsk" ref="5def6c3850c041928b9a662422ee0679" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__dev__global__regs.html#5def6c3850c041928b9a662422ee0679">dwc_otg_dev_global_regs::daintmsk</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Device All Endpoints Interrupt Mask Register. 
+<p>
+<em>Offset: 81Ch</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00884">884</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="b130a76736e0e81d5a020651109352de"></a><!-- doxytag: member="dwc_otg_dev_global_regs::dtknqr1" ref="b130a76736e0e81d5a020651109352de" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__dev__global__regs.html#b130a76736e0e81d5a020651109352de">dwc_otg_dev_global_regs::dtknqr1</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Device IN Token Queue Read Register-1 (Read Only). 
+<p>
+<em>Offset: 820h</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00887">887</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="27968db886161264e7820bcf4a746e5d"></a><!-- doxytag: member="dwc_otg_dev_global_regs::dtknqr2" ref="27968db886161264e7820bcf4a746e5d" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__dev__global__regs.html#27968db886161264e7820bcf4a746e5d">dwc_otg_dev_global_regs::dtknqr2</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Device IN Token Queue Read Register-2 (Read Only). 
+<p>
+<em>Offset: 824h</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00890">890</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="95088e182c3ff164d1b331bb196eb95d"></a><!-- doxytag: member="dwc_otg_dev_global_regs::dvbusdis" ref="95088e182c3ff164d1b331bb196eb95d" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__dev__global__regs.html#95088e182c3ff164d1b331bb196eb95d">dwc_otg_dev_global_regs::dvbusdis</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Device VBUS discharge Register. 
+<p>
+<em>Offset: 828h</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00892">892</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="8747dbe01b5a4cbd2c980bf39fdb4737"></a><!-- doxytag: member="dwc_otg_dev_global_regs::dvbuspulse" ref="8747dbe01b5a4cbd2c980bf39fdb4737" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__dev__global__regs.html#8747dbe01b5a4cbd2c980bf39fdb4737">dwc_otg_dev_global_regs::dvbuspulse</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Device VBUS Pulse Register. 
+<p>
+<em>Offset: 82Ch</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00894">894</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="c263c55a0bb752f8939731aa2f8f6cb8"></a><!-- doxytag: member="dwc_otg_dev_global_regs::dtknqr3_dthrctl" ref="c263c55a0bb752f8939731aa2f8f6cb8" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__dev__global__regs.html#c263c55a0bb752f8939731aa2f8f6cb8">dwc_otg_dev_global_regs::dtknqr3_dthrctl</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Device IN Token Queue Read Register-3 (Read Only). 
+<p>
+/ Device Thresholding control register (Read/Write) <em>Offset: 830h</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00898">898</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="fbc2b776c2150842813e4681dd43bedc"></a><!-- doxytag: member="dwc_otg_dev_global_regs::dtknqr4_fifoemptymsk" ref="fbc2b776c2150842813e4681dd43bedc" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__dev__global__regs.html#fbc2b776c2150842813e4681dd43bedc">dwc_otg_dev_global_regs::dtknqr4_fifoemptymsk</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Device IN Token Queue Read Register-4 (Read Only). 
+<p>
+/ Device IN EPs empty Inr. Mask Register (Read/Write) <em>Offset: 834h</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00902">902</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="4795bc8eab569241a3f8e6aad5d99ac7"></a><!-- doxytag: member="dwc_otg_dev_global_regs::deachint" ref="4795bc8eab569241a3f8e6aad5d99ac7" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__dev__global__regs.html#4795bc8eab569241a3f8e6aad5d99ac7">dwc_otg_dev_global_regs::deachint</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Device Each Endpoint Interrupt Register (Read Only). 
+<p>
+/ <em>Offset: 838h</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00905">905</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="e64a153683f0e0cda14b56a163651825"></a><!-- doxytag: member="dwc_otg_dev_global_regs::deachintmsk" ref="e64a153683f0e0cda14b56a163651825" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__dev__global__regs.html#e64a153683f0e0cda14b56a163651825">dwc_otg_dev_global_regs::deachintmsk</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Device Each Endpoint Interrupt mask Register (Read/Write). 
+<p>
+/ <em>Offset: 83Ch</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00908">908</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="aaf2a5c6be4130d558c291f6aaeeca4f"></a><!-- doxytag: member="dwc_otg_dev_global_regs::diepeachintmsk" ref="aaf2a5c6be4130d558c291f6aaeeca4f" args="[MAX_EPS_CHANNELS]" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__dev__global__regs.html#aaf2a5c6be4130d558c291f6aaeeca4f">dwc_otg_dev_global_regs::diepeachintmsk</a>[MAX_EPS_CHANNELS]          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Device Each In Endpoint Interrupt mask Register (Read/Write). 
+<p>
+/ <em>Offset: 840h</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00911">911</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="304e089ed2d36d9076228b8d7e1cc515"></a><!-- doxytag: member="dwc_otg_dev_global_regs::doepeachintmsk" ref="304e089ed2d36d9076228b8d7e1cc515" args="[MAX_EPS_CHANNELS]" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__dev__global__regs.html#304e089ed2d36d9076228b8d7e1cc515">dwc_otg_dev_global_regs::doepeachintmsk</a>[MAX_EPS_CHANNELS]          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Device Each Out Endpoint Interrupt mask Register (Read/Write). 
+<p>
+/ <em>Offset: 880h</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00914">914</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<hr>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__dev__if.html b/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__dev__if.html
new file mode 100644
index 000000000000..730e5a4acb80
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__dev__if.html
@@ -0,0 +1,142 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_dev_if Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>dwc_otg_dev_if Struct Reference</h1><!-- doxytag: class="dwc_otg_dev_if" -->The <a class="el" href="structdwc__otg__dev__if.html">dwc_otg_dev_if</a> structure contains information needed to manage the DWC_otg controller acting in device mode.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="el" href="structdwc__otg__dev__global__regs.html">dwc_otg_device_global_regs_t</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dev_global_regs</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Pointer to device Global registers.  <a href="#e261921bab2e67ccc69007fc485d7f82"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7329ead96344810d718f63738b54a4ca"></a><!-- doxytag: member="dwc_otg_dev_if::in_ep_regs" ref="7329ead96344810d718f63738b54a4ca" args="[MAX_EPS_CHANNELS]" -->
+<a class="el" href="structdwc__otg__dev__in__ep__regs.html">dwc_otg_dev_in_ep_regs_t</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__if.html#7329ead96344810d718f63738b54a4ca">in_ep_regs</a> [MAX_EPS_CHANNELS]</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Device Logical IN Endpoint-Specific Registers 900h-AFCh. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="9cc0e6b18b00e44c5d4b46a8ff460384"></a><!-- doxytag: member="dwc_otg_dev_if::out_ep_regs" ref="9cc0e6b18b00e44c5d4b46a8ff460384" args="[MAX_EPS_CHANNELS]" -->
+<a class="el" href="structdwc__otg__dev__out__ep__regs.html">dwc_otg_dev_out_ep_regs_t</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__if.html#9cc0e6b18b00e44c5d4b46a8ff460384">out_ep_regs</a> [MAX_EPS_CHANNELS]</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Device Logical OUT Endpoint-Specific Registers B00h-CFCh. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="8a602da4cbdc4fc88c785471426ed63c"></a><!-- doxytag: member="dwc_otg_dev_if::speed" ref="8a602da4cbdc4fc88c785471426ed63c" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__if.html#8a602da4cbdc4fc88c785471426ed63c">speed</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Device Speed 0: Unknown, 1: LS, 2:FS, 3: HS. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="4fae9bc1293bf2e58966c38fa5b98822"></a><!-- doxytag: member="dwc_otg_dev_if::num_in_eps" ref="4fae9bc1293bf2e58966c38fa5b98822" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__if.html#4fae9bc1293bf2e58966c38fa5b98822">num_in_eps</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Number # of Tx EP range: 0-15 exept ep0. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="2f0e01cdc605623f591963fc83c8dc73"></a><!-- doxytag: member="dwc_otg_dev_if::num_out_eps" ref="2f0e01cdc605623f591963fc83c8dc73" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__if.html#2f0e01cdc605623f591963fc83c8dc73">num_out_eps</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Number # of Rx EP range: 0-15 exept ep 0. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="817a953b04c45cf346d7a7d6fc274150"></a><!-- doxytag: member="dwc_otg_dev_if::perio_tx_fifo_size" ref="817a953b04c45cf346d7a7d6fc274150" args="[MAX_PERIO_FIFOS]" -->
+uint16_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__if.html#817a953b04c45cf346d7a7d6fc274150">perio_tx_fifo_size</a> [MAX_PERIO_FIFOS]</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Size of periodic FIFOs (Bytes). <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ea32a81a3c0a752e6d6274f8fd6faef9"></a><!-- doxytag: member="dwc_otg_dev_if::tx_fifo_size" ref="ea32a81a3c0a752e6d6274f8fd6faef9" args="[MAX_TX_FIFOS]" -->
+uint16_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__if.html#ea32a81a3c0a752e6d6274f8fd6faef9">tx_fifo_size</a> [MAX_TX_FIFOS]</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Size of Tx FIFOs (Bytes). <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="839ada1cbeff50af91f5db00f4b36ec4"></a><!-- doxytag: member="dwc_otg_dev_if::rx_thr_en" ref="839ada1cbeff50af91f5db00f4b36ec4" args="" -->
+uint16_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__if.html#839ada1cbeff50af91f5db00f4b36ec4">rx_thr_en</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Thresholding enable flags and length varaiables. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="76af117a05ad95e5e5c534a1afcdae22"></a><!-- doxytag: member="dwc_otg_dev_if::iso_tx_thr_en" ref="76af117a05ad95e5e5c534a1afcdae22" args="" -->
+uint16_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__if.html#76af117a05ad95e5e5c534a1afcdae22">iso_tx_thr_en</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c4c1cdbb40f37e3403d62ae00b4819eb"></a><!-- doxytag: member="dwc_otg_dev_if::non_iso_tx_thr_en" ref="c4c1cdbb40f37e3403d62ae00b4819eb" args="" -->
+uint16_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__if.html#c4c1cdbb40f37e3403d62ae00b4819eb">non_iso_tx_thr_en</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e1ec98fc03446d7e172572a973107d62"></a><!-- doxytag: member="dwc_otg_dev_if::rx_thr_length" ref="e1ec98fc03446d7e172572a973107d62" args="" -->
+uint16_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__if.html#e1ec98fc03446d7e172572a973107d62">rx_thr_length</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="55206f9ce7b0c2614e2c534d01acd6c4"></a><!-- doxytag: member="dwc_otg_dev_if::tx_thr_length" ref="55206f9ce7b0c2614e2c534d01acd6c4" args="" -->
+uint16_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__if.html#55206f9ce7b0c2614e2c534d01acd6c4">tx_thr_length</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="fb3d3353afd5f9d08a8e49c48158cfb7"></a><!-- doxytag: member="dwc_otg_dev_if::dma_setup_desc_addr" ref="fb3d3353afd5f9d08a8e49c48158cfb7" args="[2]" -->
+dwc_dma_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__if.html#fb3d3353afd5f9d08a8e49c48158cfb7">dma_setup_desc_addr</a> [2]</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">2 descriptors for SETUP packets <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f149a6cbedd5f180ff033caeee6f527e"></a><!-- doxytag: member="dwc_otg_dev_if::setup_desc_addr" ref="f149a6cbedd5f180ff033caeee6f527e" args="[2]" -->
+<a class="el" href="structdwc__otg__dev__dma__desc.html">dwc_otg_dev_dma_desc_t</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__if.html#f149a6cbedd5f180ff033caeee6f527e">setup_desc_addr</a> [2]</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ade28f08143342505c705db1fc0865a9"></a><!-- doxytag: member="dwc_otg_dev_if::psetup" ref="ade28f08143342505c705db1fc0865a9" args="" -->
+<a class="el" href="structdwc__otg__dev__dma__desc.html">dwc_otg_dev_dma_desc_t</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__if.html#ade28f08143342505c705db1fc0865a9">psetup</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Pointer to Descriptor with latest SETUP packet. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="dd45f3935b2ebb171de8da70cddd6935"></a><!-- doxytag: member="dwc_otg_dev_if::setup_desc_index" ref="dd45f3935b2ebb171de8da70cddd6935" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__if.html#dd45f3935b2ebb171de8da70cddd6935">setup_desc_index</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Index of current SETUP handler descriptor. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ba2f5eede8b3deaaec8882baeea6a35b"></a><!-- doxytag: member="dwc_otg_dev_if::dma_in_desc_addr" ref="ba2f5eede8b3deaaec8882baeea6a35b" args="" -->
+dwc_dma_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__if.html#ba2f5eede8b3deaaec8882baeea6a35b">dma_in_desc_addr</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Descriptor for Data In or Status In phases. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="99f44e328bbb4401aabd8e2708853238"></a><!-- doxytag: member="dwc_otg_dev_if::in_desc_addr" ref="99f44e328bbb4401aabd8e2708853238" args="" -->
+<a class="el" href="structdwc__otg__dev__dma__desc.html">dwc_otg_dev_dma_desc_t</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__if.html#99f44e328bbb4401aabd8e2708853238">in_desc_addr</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3829a415bbaf0f5c3e29b1a9f3cf546b"></a><!-- doxytag: member="dwc_otg_dev_if::dma_out_desc_addr" ref="3829a415bbaf0f5c3e29b1a9f3cf546b" args="" -->
+dwc_dma_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__if.html#3829a415bbaf0f5c3e29b1a9f3cf546b">dma_out_desc_addr</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Descriptor for Data Out or Status Out phases. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="8cc9be8ccaba2ef93b02b34ba7b26bad"></a><!-- doxytag: member="dwc_otg_dev_if::out_desc_addr" ref="8cc9be8ccaba2ef93b02b34ba7b26bad" args="" -->
+<a class="el" href="structdwc__otg__dev__dma__desc.html">dwc_otg_dev_dma_desc_t</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__if.html#8cc9be8ccaba2ef93b02b34ba7b26bad">out_desc_addr</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="aaabcd21be1be15804b0cf49119ce883"></a><!-- doxytag: member="dwc_otg_dev_if::spd" ref="aaabcd21be1be15804b0cf49119ce883" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__if.html#aaabcd21be1be15804b0cf49119ce883">spd</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Setup Packet Detected - if set clear NAK when queueing. <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+The <a class="el" href="structdwc__otg__dev__if.html">dwc_otg_dev_if</a> structure contains information needed to manage the DWC_otg controller acting in device mode. 
+<p>
+It represents the programming view of the device-specific aspects of the controller. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01554">1554</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr><h2>Field Documentation</h2>
+<a class="anchor" name="e261921bab2e67ccc69007fc485d7f82"></a><!-- doxytag: member="dwc_otg_dev_if::dev_global_regs" ref="e261921bab2e67ccc69007fc485d7f82" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="structdwc__otg__dev__global__regs.html">dwc_otg_device_global_regs_t</a>* <a class="el" href="structdwc__otg__dev__if.html#e261921bab2e67ccc69007fc485d7f82">dwc_otg_dev_if::dev_global_regs</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Pointer to device Global registers. 
+<p>
+Device Global Registers starting at offset 800h 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01558">1558</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<hr>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__dev__in__ep__regs.html b/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__dev__in__ep__regs.html
new file mode 100644
index 000000000000..62f3a60f2d1e
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__dev__in__ep__regs.html
@@ -0,0 +1,221 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_dev_in_ep_regs Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>dwc_otg_dev_in_ep_regs Struct Reference</h1><!-- doxytag: class="dwc_otg_dev_in_ep_regs" -->Device Logical IN Endpoint-Specific Registers.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__in__ep__regs.html#53a5adb977e2aec66d4902c6ba293216">diepctl</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Device IN Endpoint Control Register.  <a href="#53a5adb977e2aec66d4902c6ba293216"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__in__ep__regs.html#4a6af6187ad26a0059b4b2b4706aaa6d">reserved04</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Reserved.  <a href="#4a6af6187ad26a0059b4b2b4706aaa6d"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__in__ep__regs.html#4d6d6309ef5e09ad9048655ced6a2769">diepint</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Device IN Endpoint Interrupt Register.  <a href="#4d6d6309ef5e09ad9048655ced6a2769"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__in__ep__regs.html#6d896f525592c1e1d12d33dba999ccd6">reserved0C</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Reserved.  <a href="#6d896f525592c1e1d12d33dba999ccd6"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__in__ep__regs.html#88f637b5a4e8a0c6bc87d157072255dd">dieptsiz</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Device IN Endpoint Transfer Size Register.  <a href="#88f637b5a4e8a0c6bc87d157072255dd"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__in__ep__regs.html#5f013840a15e0a310b8722646880a420">diepdma</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Device IN Endpoint DMA Address Register.  <a href="#5f013840a15e0a310b8722646880a420"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__in__ep__regs.html#90db7d3ed2dd087e0a55a1465deb21c9">dtxfsts</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Device IN Endpoint Transmit FIFO Status Register.  <a href="#90db7d3ed2dd087e0a55a1465deb21c9"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__in__ep__regs.html#aa24ec8b19877c7f2f20802afc6f9cef">diepdmab</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Device IN Endpoint DMA Buffer Register.  <a href="#aa24ec8b19877c7f2f20802afc6f9cef"></a><br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+Device Logical IN Endpoint-Specific Registers. 
+<p>
+<em>Offsets 900h-AFCh</em><p>
+There will be one set of endpoint registers per logical endpoint implemented.<p>
+<em>These registers are visible only in Device mode and must not be accessed in Host mode, as the results are unknown.</em> 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01239">1239</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr><h2>Field Documentation</h2>
+<a class="anchor" name="53a5adb977e2aec66d4902c6ba293216"></a><!-- doxytag: member="dwc_otg_dev_in_ep_regs::diepctl" ref="53a5adb977e2aec66d4902c6ba293216" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__dev__in__ep__regs.html#53a5adb977e2aec66d4902c6ba293216">dwc_otg_dev_in_ep_regs::diepctl</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Device IN Endpoint Control Register. 
+<p>
+<em>Offset:900h + (ep_num * 20h) + 00h</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01242">1242</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="4a6af6187ad26a0059b4b2b4706aaa6d"></a><!-- doxytag: member="dwc_otg_dev_in_ep_regs::reserved04" ref="4a6af6187ad26a0059b4b2b4706aaa6d" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t <a class="el" href="structdwc__otg__dev__in__ep__regs.html#4a6af6187ad26a0059b4b2b4706aaa6d">dwc_otg_dev_in_ep_regs::reserved04</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Reserved. 
+<p>
+<em>Offset:900h + (ep_num * 20h) + 04h</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01244">1244</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="4d6d6309ef5e09ad9048655ced6a2769"></a><!-- doxytag: member="dwc_otg_dev_in_ep_regs::diepint" ref="4d6d6309ef5e09ad9048655ced6a2769" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__dev__in__ep__regs.html#4d6d6309ef5e09ad9048655ced6a2769">dwc_otg_dev_in_ep_regs::diepint</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Device IN Endpoint Interrupt Register. 
+<p>
+<em>Offset:900h + (ep_num * 20h) + 08h</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01247">1247</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="6d896f525592c1e1d12d33dba999ccd6"></a><!-- doxytag: member="dwc_otg_dev_in_ep_regs::reserved0C" ref="6d896f525592c1e1d12d33dba999ccd6" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t <a class="el" href="structdwc__otg__dev__in__ep__regs.html#6d896f525592c1e1d12d33dba999ccd6">dwc_otg_dev_in_ep_regs::reserved0C</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Reserved. 
+<p>
+<em>Offset:900h + (ep_num * 20h) + 0Ch</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01249">1249</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="88f637b5a4e8a0c6bc87d157072255dd"></a><!-- doxytag: member="dwc_otg_dev_in_ep_regs::dieptsiz" ref="88f637b5a4e8a0c6bc87d157072255dd" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__dev__in__ep__regs.html#88f637b5a4e8a0c6bc87d157072255dd">dwc_otg_dev_in_ep_regs::dieptsiz</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Device IN Endpoint Transfer Size Register. 
+<p>
+<em>Offset:900h + (ep_num * 20h) + 10h</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01252">1252</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="5f013840a15e0a310b8722646880a420"></a><!-- doxytag: member="dwc_otg_dev_in_ep_regs::diepdma" ref="5f013840a15e0a310b8722646880a420" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__dev__in__ep__regs.html#5f013840a15e0a310b8722646880a420">dwc_otg_dev_in_ep_regs::diepdma</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Device IN Endpoint DMA Address Register. 
+<p>
+<em>Offset:900h + (ep_num * 20h) + 14h</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01255">1255</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="90db7d3ed2dd087e0a55a1465deb21c9"></a><!-- doxytag: member="dwc_otg_dev_in_ep_regs::dtxfsts" ref="90db7d3ed2dd087e0a55a1465deb21c9" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__dev__in__ep__regs.html#90db7d3ed2dd087e0a55a1465deb21c9">dwc_otg_dev_in_ep_regs::dtxfsts</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Device IN Endpoint Transmit FIFO Status Register. 
+<p>
+<em>Offset:900h + (ep_num * 20h) + 18h</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01258">1258</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="aa24ec8b19877c7f2f20802afc6f9cef"></a><!-- doxytag: member="dwc_otg_dev_in_ep_regs::diepdmab" ref="aa24ec8b19877c7f2f20802afc6f9cef" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__dev__in__ep__regs.html#aa24ec8b19877c7f2f20802afc6f9cef">dwc_otg_dev_in_ep_regs::diepdmab</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Device IN Endpoint DMA Buffer Register. 
+<p>
+<em>Offset:900h + (ep_num * 20h) + 1Ch</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01261">1261</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<hr>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__dev__out__ep__regs.html b/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__dev__out__ep__regs.html
new file mode 100644
index 000000000000..32d4bee93344
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__dev__out__ep__regs.html
@@ -0,0 +1,221 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_dev_out_ep_regs Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>dwc_otg_dev_out_ep_regs Struct Reference</h1><!-- doxytag: class="dwc_otg_dev_out_ep_regs" -->Device Logical OUT Endpoint-Specific Registers.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__out__ep__regs.html#2a522b71fc97658c07debf3521f7d3e5">doepctl</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Device OUT Endpoint Control Register.  <a href="#2a522b71fc97658c07debf3521f7d3e5"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__out__ep__regs.html#f23e8e9750d99b1c4b5ac0c674e8733e">doepfn</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Device OUT Endpoint Frame number Register.  <a href="#f23e8e9750d99b1c4b5ac0c674e8733e"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__out__ep__regs.html#81d837c801dcfa30f17b567419a86f62">doepint</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Device OUT Endpoint Interrupt Register.  <a href="#81d837c801dcfa30f17b567419a86f62"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__out__ep__regs.html#9e4014081779b42d9da9a59b2361fe9b">reserved0C</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Reserved.  <a href="#9e4014081779b42d9da9a59b2361fe9b"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__out__ep__regs.html#e756ec48787099f0a4e2ce353fce4f91">doeptsiz</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Device OUT Endpoint Transfer Size Register.  <a href="#e756ec48787099f0a4e2ce353fce4f91"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__out__ep__regs.html#006071bf54bfa1c1f5e25cf4c9f65cb1">doepdma</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Device OUT Endpoint DMA Address Register.  <a href="#006071bf54bfa1c1f5e25cf4c9f65cb1"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__out__ep__regs.html#f78d72b82ee55e6a35cada1bd89d5659">unused</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Reserved.  <a href="#f78d72b82ee55e6a35cada1bd89d5659"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__dev__out__ep__regs.html#baff3c1aea7aed57a42fa0015f15e0fa">doepdmab</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Device OUT Endpoint DMA Buffer Register.  <a href="#baff3c1aea7aed57a42fa0015f15e0fa"></a><br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+Device Logical OUT Endpoint-Specific Registers. 
+<p>
+<em>Offsets: B00h-CFCh</em><p>
+There will be one set of endpoint registers per logical endpoint implemented.<p>
+<em>These registers are visible only in Device mode and must not be accessed in Host mode, as the results are unknown.</em> 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01274">1274</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr><h2>Field Documentation</h2>
+<a class="anchor" name="2a522b71fc97658c07debf3521f7d3e5"></a><!-- doxytag: member="dwc_otg_dev_out_ep_regs::doepctl" ref="2a522b71fc97658c07debf3521f7d3e5" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__dev__out__ep__regs.html#2a522b71fc97658c07debf3521f7d3e5">dwc_otg_dev_out_ep_regs::doepctl</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Device OUT Endpoint Control Register. 
+<p>
+<em>Offset:B00h + (ep_num * 20h) + 00h</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01277">1277</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="f23e8e9750d99b1c4b5ac0c674e8733e"></a><!-- doxytag: member="dwc_otg_dev_out_ep_regs::doepfn" ref="f23e8e9750d99b1c4b5ac0c674e8733e" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__dev__out__ep__regs.html#f23e8e9750d99b1c4b5ac0c674e8733e">dwc_otg_dev_out_ep_regs::doepfn</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Device OUT Endpoint Frame number Register. 
+<p>
+<em>Offset: B00h + (ep_num * 20h) + 04h</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01280">1280</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="81d837c801dcfa30f17b567419a86f62"></a><!-- doxytag: member="dwc_otg_dev_out_ep_regs::doepint" ref="81d837c801dcfa30f17b567419a86f62" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__dev__out__ep__regs.html#81d837c801dcfa30f17b567419a86f62">dwc_otg_dev_out_ep_regs::doepint</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Device OUT Endpoint Interrupt Register. 
+<p>
+<em>Offset:B00h + (ep_num * 20h) + 08h</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01283">1283</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="9e4014081779b42d9da9a59b2361fe9b"></a><!-- doxytag: member="dwc_otg_dev_out_ep_regs::reserved0C" ref="9e4014081779b42d9da9a59b2361fe9b" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t <a class="el" href="structdwc__otg__dev__out__ep__regs.html#9e4014081779b42d9da9a59b2361fe9b">dwc_otg_dev_out_ep_regs::reserved0C</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Reserved. 
+<p>
+<em>Offset:B00h + (ep_num * 20h) + 0Ch</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01285">1285</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="e756ec48787099f0a4e2ce353fce4f91"></a><!-- doxytag: member="dwc_otg_dev_out_ep_regs::doeptsiz" ref="e756ec48787099f0a4e2ce353fce4f91" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__dev__out__ep__regs.html#e756ec48787099f0a4e2ce353fce4f91">dwc_otg_dev_out_ep_regs::doeptsiz</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Device OUT Endpoint Transfer Size Register. 
+<p>
+<em>Offset: B00h + (ep_num * 20h) + 10h</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01288">1288</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="006071bf54bfa1c1f5e25cf4c9f65cb1"></a><!-- doxytag: member="dwc_otg_dev_out_ep_regs::doepdma" ref="006071bf54bfa1c1f5e25cf4c9f65cb1" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__dev__out__ep__regs.html#006071bf54bfa1c1f5e25cf4c9f65cb1">dwc_otg_dev_out_ep_regs::doepdma</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Device OUT Endpoint DMA Address Register. 
+<p>
+<em>Offset:B00h + (ep_num * 20h) + 14h</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01291">1291</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="f78d72b82ee55e6a35cada1bd89d5659"></a><!-- doxytag: member="dwc_otg_dev_out_ep_regs::unused" ref="f78d72b82ee55e6a35cada1bd89d5659" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t <a class="el" href="structdwc__otg__dev__out__ep__regs.html#f78d72b82ee55e6a35cada1bd89d5659">dwc_otg_dev_out_ep_regs::unused</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Reserved. 
+<p>
+<em>Offset:B00h + * (ep_num * 20h) + 18h</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01293">1293</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="baff3c1aea7aed57a42fa0015f15e0fa"></a><!-- doxytag: member="dwc_otg_dev_out_ep_regs::doepdmab" ref="baff3c1aea7aed57a42fa0015f15e0fa" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t <a class="el" href="structdwc__otg__dev__out__ep__regs.html#baff3c1aea7aed57a42fa0015f15e0fa">dwc_otg_dev_out_ep_regs::doepdmab</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Device OUT Endpoint DMA Buffer Register. 
+<p>
+<em>Offset:B00h + (ep_num * 20h) + 1Ch</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01296">1296</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<hr>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__device.html b/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__device.html
new file mode 100644
index 000000000000..2a9a04a383ce
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__device.html
@@ -0,0 +1,64 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_device Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>dwc_otg_device Struct Reference</h1><!-- doxytag: class="dwc_otg_device" -->This structure is a wrapper that encapsulates the driver components used to manage a single DWC_otg controller.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__driver_8h-source.html">dwc_otg_driver.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ed96ed1109175f87fd83fa32a9c2c6fa"></a><!-- doxytag: member="dwc_otg_device::base" ref="ed96ed1109175f87fd83fa32a9c2c6fa" args="" -->
+void *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__device.html#ed96ed1109175f87fd83fa32a9c2c6fa">base</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Base address returned from ioremap(). <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="4cc7c9f6e473072c2ed0a5e6adb25ebe"></a><!-- doxytag: member="dwc_otg_device::core_if" ref="4cc7c9f6e473072c2ed0a5e6adb25ebe" args="" -->
+<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__device.html#4cc7c9f6e473072c2ed0a5e6adb25ebe">core_if</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Pointer to the core interface structure. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="d2701bc8589613bec5074968e57ce6ef"></a><!-- doxytag: member="dwc_otg_device::reg_offset" ref="d2701bc8589613bec5074968e57ce6ef" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__device.html#d2701bc8589613bec5074968e57ce6ef">reg_offset</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Register offset for Diagnostic API. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="2a8eefbd03790ea0bbb70e0ac14e4786"></a><!-- doxytag: member="dwc_otg_device::pcd" ref="2a8eefbd03790ea0bbb70e0ac14e4786" args="" -->
+<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__device.html#2a8eefbd03790ea0bbb70e0ac14e4786">pcd</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Pointer to the PCD structure. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="834ef28e884f0d7fcac68f3bdf5c4b33"></a><!-- doxytag: member="dwc_otg_device::hcd" ref="834ef28e884f0d7fcac68f3bdf5c4b33" args="" -->
+<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__device.html#834ef28e884f0d7fcac68f3bdf5c4b33">hcd</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Pointer to the HCD structure. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="80bfe5405d4146d3edca4e3eb2f9239b"></a><!-- doxytag: member="dwc_otg_device::common_irq_installed" ref="80bfe5405d4146d3edca4e3eb2f9239b" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__device.html#80bfe5405d4146d3edca4e3eb2f9239b">common_irq_installed</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Flag to indicate whether the common IRQ handler is installed. <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This structure is a wrapper that encapsulates the driver components used to manage a single DWC_otg controller. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__driver_8h-source.html#l00056">56</a> of file <a class="el" href="dwc__otg__driver_8h-source.html">dwc_otg_driver.h</a>.<hr>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__driver_8h-source.html">dwc_otg_driver.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__driver__module__params.html b/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__driver__module__params.html
new file mode 100644
index 000000000000..bf9eb57a0d8c
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__driver__module__params.html
@@ -0,0 +1,146 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_driver_module_params Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>dwc_otg_driver_module_params Struct Reference</h1><!-- doxytag: class="dwc_otg_driver_module_params" --><table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="bccaf8d2ce8da6d5ef0d1c81caf9e518"></a><!-- doxytag: member="dwc_otg_driver_module_params::opt" ref="bccaf8d2ce8da6d5ef0d1c81caf9e518" args="" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__driver__module__params.html#bccaf8d2ce8da6d5ef0d1c81caf9e518">opt</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="985f1849ab70919e756c86280a8f7ef0"></a><!-- doxytag: member="dwc_otg_driver_module_params::otg_cap" ref="985f1849ab70919e756c86280a8f7ef0" args="" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__driver__module__params.html#985f1849ab70919e756c86280a8f7ef0">otg_cap</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="fe4469605ca0460a3e309603d7c23e86"></a><!-- doxytag: member="dwc_otg_driver_module_params::dma_enable" ref="fe4469605ca0460a3e309603d7c23e86" args="" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__driver__module__params.html#fe4469605ca0460a3e309603d7c23e86">dma_enable</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="cdceee2a19bb233c12893751f443c40d"></a><!-- doxytag: member="dwc_otg_driver_module_params::dma_desc_enable" ref="cdceee2a19bb233c12893751f443c40d" args="" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__driver__module__params.html#cdceee2a19bb233c12893751f443c40d">dma_desc_enable</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="19c1567261677aa53120cfae53b90f8d"></a><!-- doxytag: member="dwc_otg_driver_module_params::dma_burst_size" ref="19c1567261677aa53120cfae53b90f8d" args="" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__driver__module__params.html#19c1567261677aa53120cfae53b90f8d">dma_burst_size</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e0002437cefb2b64dc92f40fd69ef29f"></a><!-- doxytag: member="dwc_otg_driver_module_params::speed" ref="e0002437cefb2b64dc92f40fd69ef29f" args="" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__driver__module__params.html#e0002437cefb2b64dc92f40fd69ef29f">speed</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="6f3a0a2bf5c82d296fec31fec7b765ca"></a><!-- doxytag: member="dwc_otg_driver_module_params::host_support_fs_ls_low_power" ref="6f3a0a2bf5c82d296fec31fec7b765ca" args="" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__driver__module__params.html#6f3a0a2bf5c82d296fec31fec7b765ca">host_support_fs_ls_low_power</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="91c46e96e070e983e3f91c756dd4aa64"></a><!-- doxytag: member="dwc_otg_driver_module_params::host_ls_low_power_phy_clk" ref="91c46e96e070e983e3f91c756dd4aa64" args="" -->
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+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ed3802eea4e62cd79ef7d8701d45b506"></a><!-- doxytag: member="dwc_otg_driver_module_params::ic_usb_cap" ref="ed3802eea4e62cd79ef7d8701d45b506" args="" -->
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+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b450246efcbc087eb36b0979040162ca"></a><!-- doxytag: member="dwc_otg_driver_module_params::ahb_thr_ratio" ref="b450246efcbc087eb36b0979040162ca" args="" -->
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+
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__driver_8c-source.html#l00120">120</a> of file <a class="el" href="dwc__otg__driver_8c-source.html">dwc_otg_driver.c</a>.<hr>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__driver_8c-source.html">dwc_otg_driver.c</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__hc__regs.html b/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__hc__regs.html
new file mode 100644
index 000000000000..eaaf3527f89d
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__hc__regs.html
@@ -0,0 +1,200 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hc_regs Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>dwc_otg_hc_regs Struct Reference</h1><!-- doxytag: class="dwc_otg_hc_regs" -->Host Channel Specific Registers.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">hcchar</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Host Channel 0 Characteristic Register.  <a href="#3d8bdf7979ea6dd5ba01858aca7a1c02"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hc__regs.html#149053001a9ee21b692afde531a814de">hcsplt</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Host Channel 0 Split Control Register.  <a href="#149053001a9ee21b692afde531a814de"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hc__regs.html#0dfd5bae537d58e13788508dc719480d">hcint</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Host Channel 0 Interrupt Register.  <a href="#0dfd5bae537d58e13788508dc719480d"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hc__regs.html#830aa61c1d4326823662168ea7359205">hcintmsk</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Host Channel 0 Interrupt Mask Register.  <a href="#830aa61c1d4326823662168ea7359205"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hc__regs.html#c6173f823ba754d9f9549422b6380ca2">hctsiz</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Host Channel 0 Transfer Size Register.  <a href="#c6173f823ba754d9f9549422b6380ca2"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hc__regs.html#ab2148d4b5f1bf3a2ad438e497a8b4a3">hcdma</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Host Channel 0 DMA Address Register.  <a href="#ab2148d4b5f1bf3a2ad438e497a8b4a3"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="a0a3f7d7424594783afc83c7e8b22a69"></a><!-- doxytag: member="dwc_otg_hc_regs::reserved" ref="a0a3f7d7424594783afc83c7e8b22a69" args="" -->
+volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hc__regs.html#a0a3f7d7424594783afc83c7e8b22a69">reserved</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hc__regs.html#602f4c6eceb8e9d4fa61f35d4149f355">hcdmab</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Host Channel 0 DMA Buffer Address Register.  <a href="#602f4c6eceb8e9d4fa61f35d4149f355"></a><br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+Host Channel Specific Registers. 
+<p>
+<em>500h-5FCh</em> 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01838">1838</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr><h2>Field Documentation</h2>
+<a class="anchor" name="3d8bdf7979ea6dd5ba01858aca7a1c02"></a><!-- doxytag: member="dwc_otg_hc_regs::hcchar" ref="3d8bdf7979ea6dd5ba01858aca7a1c02" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__hc__regs.html#3d8bdf7979ea6dd5ba01858aca7a1c02">dwc_otg_hc_regs::hcchar</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Host Channel 0 Characteristic Register. 
+<p>
+<em>Offset: 500h + (chan_num * 20h) + 00h</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01841">1841</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="149053001a9ee21b692afde531a814de"></a><!-- doxytag: member="dwc_otg_hc_regs::hcsplt" ref="149053001a9ee21b692afde531a814de" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__hc__regs.html#149053001a9ee21b692afde531a814de">dwc_otg_hc_regs::hcsplt</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Host Channel 0 Split Control Register. 
+<p>
+<em>Offset: 500h + (chan_num * 20h) + 04h</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01843">1843</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="0dfd5bae537d58e13788508dc719480d"></a><!-- doxytag: member="dwc_otg_hc_regs::hcint" ref="0dfd5bae537d58e13788508dc719480d" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__hc__regs.html#0dfd5bae537d58e13788508dc719480d">dwc_otg_hc_regs::hcint</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Host Channel 0 Interrupt Register. 
+<p>
+<em>Offset: 500h + (chan_num * 20h) + 08h</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01845">1845</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="830aa61c1d4326823662168ea7359205"></a><!-- doxytag: member="dwc_otg_hc_regs::hcintmsk" ref="830aa61c1d4326823662168ea7359205" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__hc__regs.html#830aa61c1d4326823662168ea7359205">dwc_otg_hc_regs::hcintmsk</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Host Channel 0 Interrupt Mask Register. 
+<p>
+<em>Offset: 500h + (chan_num * 20h) + 0Ch</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01847">1847</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="c6173f823ba754d9f9549422b6380ca2"></a><!-- doxytag: member="dwc_otg_hc_regs::hctsiz" ref="c6173f823ba754d9f9549422b6380ca2" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__hc__regs.html#c6173f823ba754d9f9549422b6380ca2">dwc_otg_hc_regs::hctsiz</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Host Channel 0 Transfer Size Register. 
+<p>
+<em>Offset: 500h + (chan_num * 20h) + 10h</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01849">1849</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="ab2148d4b5f1bf3a2ad438e497a8b4a3"></a><!-- doxytag: member="dwc_otg_hc_regs::hcdma" ref="ab2148d4b5f1bf3a2ad438e497a8b4a3" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__hc__regs.html#ab2148d4b5f1bf3a2ad438e497a8b4a3">dwc_otg_hc_regs::hcdma</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Host Channel 0 DMA Address Register. 
+<p>
+<em>Offset: 500h + (chan_num * 20h) + 14h</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01851">1851</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="602f4c6eceb8e9d4fa61f35d4149f355"></a><!-- doxytag: member="dwc_otg_hc_regs::hcdmab" ref="602f4c6eceb8e9d4fa61f35d4149f355" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__hc__regs.html#602f4c6eceb8e9d4fa61f35d4149f355">dwc_otg_hc_regs::hcdmab</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Host Channel 0 DMA Buffer Address Register. 
+<p>
+<em>Offset: 500h + (chan_num * 20h) + 1Ch</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01854">1854</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<hr>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__hcd.html b/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__hcd.html
new file mode 100644
index 000000000000..eee25ed84a04
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__hcd.html
@@ -0,0 +1,377 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>dwc_otg_hcd Struct Reference</h1><!-- doxytag: class="dwc_otg_hcd" -->This structure holds the state of the HCD, including the non-periodic and periodic schedules.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__hcd_8h-source.html">dwc_otg_hcd.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e36b9560ce538a7d2ea9bd266d4041f0"></a><!-- doxytag: member="dwc_otg_hcd::core_if" ref="e36b9560ce538a7d2ea9bd266d4041f0" args="" -->
+<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd.html#e36b9560ce538a7d2ea9bd266d4041f0">core_if</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">DWC OTG Core Interface Layer. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ffefbd33a59a14b8b46406f5aaeaa2f4"></a><!-- doxytag: member="dwc_otg_hcd::fops" ref="ffefbd33a59a14b8b46406f5aaeaa2f4" args="" -->
+<a class="el" href="structdwc__otg__hcd__function__ops.html">dwc_otg_hcd_function_ops</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd.html#ffefbd33a59a14b8b46406f5aaeaa2f4">fops</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Function HCD driver callbacks. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="9aaf2a112f5794f92dedd826342bd637"></a><!-- doxytag: member="dwc_otg_hcd::flags" ref="9aaf2a112f5794f92dedd826342bd637" args="" -->
+<a class="el" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html">dwc_otg_hcd::dwc_otg_hcd_internal_flags</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd.html#9aaf2a112f5794f92dedd826342bd637">flags</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Internal DWC HCD Flags. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">dwc_list_link_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd.html#64c96c47a36d71bad6e4360cec9d07ad">non_periodic_sched_inactive</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Inactive items in the non-periodic schedule.  <a href="#64c96c47a36d71bad6e4360cec9d07ad"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">dwc_list_link_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd.html#ffa3041ad517da9519aa2159cdec3f61">non_periodic_sched_active</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Active items in the non-periodic schedule.  <a href="#ffa3041ad517da9519aa2159cdec3f61"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="01ab5791d6269b6b5d506f2113b94231"></a><!-- doxytag: member="dwc_otg_hcd::non_periodic_qh_ptr" ref="01ab5791d6269b6b5d506f2113b94231" args="" -->
+dwc_list_link_t *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd.html#01ab5791d6269b6b5d506f2113b94231">non_periodic_qh_ptr</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Pointer to the next Queue Head to process in the active non-periodic schedule. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">dwc_list_link_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd.html#2a747cacd6bdbacbef86d4157c34a312">periodic_sched_inactive</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Inactive items in the periodic schedule.  <a href="#2a747cacd6bdbacbef86d4157c34a312"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">dwc_list_link_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd.html#74b089e094911a558f7b5f24681d3242">periodic_sched_ready</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">List of periodic QHs that are ready for execution in the next frame, but have not yet been assigned to host channels.  <a href="#74b089e094911a558f7b5f24681d3242"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">dwc_list_link_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd.html#4b8deae798f771135c4a99693b26873f">periodic_sched_assigned</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">List of periodic QHs to be executed in the next frame that are assigned to host channels.  <a href="#4b8deae798f771135c4a99693b26873f"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">dwc_list_link_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd.html#e127912880eb487b3a2f38778c0de238">periodic_sched_queued</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">List of periodic QHs that have been queued for execution.  <a href="#e127912880eb487b3a2f38778c0de238"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint16_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd.html#1f2ce690c8ded506eff8d1b567747235">periodic_usecs</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Total bandwidth claimed so far for periodic transfers.  <a href="#1f2ce690c8ded506eff8d1b567747235"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint16_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd.html#f79fefeb7908c0ddf702331253acb292">frame_number</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Frame number read from the core at SOF.  <a href="#f79fefeb7908c0ddf702331253acb292"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">hc_list&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd.html#1761f2e6b8f6ba82c0e0c4e561813f0f">free_hc_list</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Free host channels in the controller.  <a href="#1761f2e6b8f6ba82c0e0c4e561813f0f"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd.html#5754b87bd4644fbb7b90cf843c638f1c">periodic_channels</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Number of host channels assigned to periodic transfers.  <a href="#5754b87bd4644fbb7b90cf843c638f1c"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e7fff26b5cce7c6c520c89f9e3c75617"></a><!-- doxytag: member="dwc_otg_hcd::non_periodic_channels" ref="e7fff26b5cce7c6c520c89f9e3c75617" args="" -->
+int&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd.html#e7fff26b5cce7c6c520c89f9e3c75617">non_periodic_channels</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Number of host channels assigned to non-periodic transfers. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="el" href="structdwc__hc.html">dwc_hc</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd.html#cb393f6a676fb106e0e3d35396fb97f9">hc_ptr_array</a> [MAX_EPS_CHANNELS]</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Array of pointers to the host channel descriptors.  <a href="#cb393f6a676fb106e0e3d35396fb97f9"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint8_t *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd.html#68627912f0d3672096e6a98be38f66ab">status_buf</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Buffer to use for any data received during the status phase of a control transfer.  <a href="#68627912f0d3672096e6a98be38f66ab"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3e752b2c5d632d848f3b1fadf543e7a4"></a><!-- doxytag: member="dwc_otg_hcd::status_buf_dma" ref="3e752b2c5d632d848f3b1fadf543e7a4" args="" -->
+dma_addr_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd.html#3e752b2c5d632d848f3b1fadf543e7a4">status_buf_dma</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">DMA address for status_buf. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">dwc_timer_t *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd.html#de7796a41bb7d1e45ed9dbc20c995342">conn_timer</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Connection timer.  <a href="#de7796a41bb7d1e45ed9dbc20c995342"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="4f2b2c551e4ac9f49afcbdbde1ddf55d"></a><!-- doxytag: member="dwc_otg_hcd::reset_tasklet" ref="4f2b2c551e4ac9f49afcbdbde1ddf55d" args="" -->
+dwc_tasklet_t *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd.html#4f2b2c551e4ac9f49afcbdbde1ddf55d">reset_tasklet</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="34f29e9c035009476495f7701c1813fd"></a><!-- doxytag: member="dwc_otg_hcd::lock" ref="34f29e9c035009476495f7701c1813fd" args="" -->
+dwc_spinlock_t *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd.html#34f29e9c035009476495f7701c1813fd">lock</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c019b908f209d577ccc19d29030926a1"></a><!-- doxytag: member="dwc_otg_hcd::priv" ref="c019b908f209d577ccc19d29030926a1" args="" -->
+void *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd.html#c019b908f209d577ccc19d29030926a1">priv</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Private data that could be used by OS wrapper. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="9231b4c3dce89a1506a5e501ec5c7a39"></a><!-- doxytag: member="dwc_otg_hcd::otg_port" ref="9231b4c3dce89a1506a5e501ec5c7a39" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd.html#9231b4c3dce89a1506a5e501ec5c7a39">otg_port</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="77f16d5530f50556ed01fe7f69a135fd"></a><!-- doxytag: member="dwc_otg_hcd::frame_list" ref="77f16d5530f50556ed01fe7f69a135fd" args="" -->
+uint32_t *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd.html#77f16d5530f50556ed01fe7f69a135fd">frame_list</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Frame List. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3421063dcac9d4e200b5d9bbb0508f3d"></a><!-- doxytag: member="dwc_otg_hcd::frame_list_dma" ref="3421063dcac9d4e200b5d9bbb0508f3d" args="" -->
+dma_addr_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd.html#3421063dcac9d4e200b5d9bbb0508f3d">frame_list_dma</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Frame List DMA address. <br></td></tr>
+<tr><td colspan="2"><br><h2>Data Structures</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">union &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html">dwc_otg_hcd_internal_flags</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Internal DWC HCD Flags.  <a href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#_details">More...</a><br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This structure holds the state of the HCD, including the non-periodic and periodic schedules. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8h-source.html#l00372">372</a> of file <a class="el" href="dwc__otg__hcd_8h-source.html">dwc_otg_hcd.h</a>.<hr><h2>Field Documentation</h2>
+<a class="anchor" name="64c96c47a36d71bad6e4360cec9d07ad"></a><!-- doxytag: member="dwc_otg_hcd::non_periodic_sched_inactive" ref="64c96c47a36d71bad6e4360cec9d07ad" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">dwc_list_link_t <a class="el" href="structdwc__otg__hcd.html#64c96c47a36d71bad6e4360cec9d07ad">dwc_otg_hcd::non_periodic_sched_inactive</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Inactive items in the non-periodic schedule. 
+<p>
+This is a list of Queue Heads. Transfers associated with these Queue Heads are not currently assigned to a host channel. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8h-source.html#l00399">399</a> of file <a class="el" href="dwc__otg__hcd_8h-source.html">dwc_otg_hcd.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="ffa3041ad517da9519aa2159cdec3f61"></a><!-- doxytag: member="dwc_otg_hcd::non_periodic_sched_active" ref="ffa3041ad517da9519aa2159cdec3f61" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">dwc_list_link_t <a class="el" href="structdwc__otg__hcd.html#ffa3041ad517da9519aa2159cdec3f61">dwc_otg_hcd::non_periodic_sched_active</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Active items in the non-periodic schedule. 
+<p>
+This is a list of Queue Heads. Transfers associated with these Queue Heads are currently assigned to a host channel. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8h-source.html#l00406">406</a> of file <a class="el" href="dwc__otg__hcd_8h-source.html">dwc_otg_hcd.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="2a747cacd6bdbacbef86d4157c34a312"></a><!-- doxytag: member="dwc_otg_hcd::periodic_sched_inactive" ref="2a747cacd6bdbacbef86d4157c34a312" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">dwc_list_link_t <a class="el" href="structdwc__otg__hcd.html#2a747cacd6bdbacbef86d4157c34a312">dwc_otg_hcd::periodic_sched_inactive</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Inactive items in the periodic schedule. 
+<p>
+This is a list of QHs for periodic transfers that are _not_ scheduled for the next frame. Each QH in the list has an interval counter that determines when it needs to be scheduled for execution. This scheduling mechanism allows only a simple calculation for periodic bandwidth used (i.e. must assume that all periodic transfers may need to execute in the same frame). However, it greatly simplifies scheduling and should be sufficient for the vast majority of OTG hosts, which need to connect to a small number of peripherals at one time.<p>
+Items move from this list to periodic_sched_ready when the QH interval counter is 0 at SOF. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8h-source.html#l00428">428</a> of file <a class="el" href="dwc__otg__hcd_8h-source.html">dwc_otg_hcd.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="74b089e094911a558f7b5f24681d3242"></a><!-- doxytag: member="dwc_otg_hcd::periodic_sched_ready" ref="74b089e094911a558f7b5f24681d3242" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">dwc_list_link_t <a class="el" href="structdwc__otg__hcd.html#74b089e094911a558f7b5f24681d3242">dwc_otg_hcd::periodic_sched_ready</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+List of periodic QHs that are ready for execution in the next frame, but have not yet been assigned to host channels. 
+<p>
+Items move from this list to periodic_sched_assigned as host channels become available during the current frame. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8h-source.html#l00437">437</a> of file <a class="el" href="dwc__otg__hcd_8h-source.html">dwc_otg_hcd.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="4b8deae798f771135c4a99693b26873f"></a><!-- doxytag: member="dwc_otg_hcd::periodic_sched_assigned" ref="4b8deae798f771135c4a99693b26873f" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">dwc_list_link_t <a class="el" href="structdwc__otg__hcd.html#4b8deae798f771135c4a99693b26873f">dwc_otg_hcd::periodic_sched_assigned</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+List of periodic QHs to be executed in the next frame that are assigned to host channels. 
+<p>
+Items move from this list to periodic_sched_queued as the transactions for the QH are queued to the DWC_otg controller. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8h-source.html#l00446">446</a> of file <a class="el" href="dwc__otg__hcd_8h-source.html">dwc_otg_hcd.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="e127912880eb487b3a2f38778c0de238"></a><!-- doxytag: member="dwc_otg_hcd::periodic_sched_queued" ref="e127912880eb487b3a2f38778c0de238" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">dwc_list_link_t <a class="el" href="structdwc__otg__hcd.html#e127912880eb487b3a2f38778c0de238">dwc_otg_hcd::periodic_sched_queued</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+List of periodic QHs that have been queued for execution. 
+<p>
+Items move from this list to either periodic_sched_inactive or periodic_sched_ready when the channel associated with the transfer is released. If the interval for the QH is 1, the item moves to periodic_sched_ready because it must be rescheduled for the next frame. Otherwise, the item moves to periodic_sched_inactive. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8h-source.html#l00457">457</a> of file <a class="el" href="dwc__otg__hcd_8h-source.html">dwc_otg_hcd.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="1f2ce690c8ded506eff8d1b567747235"></a><!-- doxytag: member="dwc_otg_hcd::periodic_usecs" ref="1f2ce690c8ded506eff8d1b567747235" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint16_t <a class="el" href="structdwc__otg__hcd.html#1f2ce690c8ded506eff8d1b567747235">dwc_otg_hcd::periodic_usecs</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Total bandwidth claimed so far for periodic transfers. 
+<p>
+This value is in microseconds per (micro)frame. The assumption is that all periodic transfers may occur in the same (micro)frame. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8h-source.html#l00464">464</a> of file <a class="el" href="dwc__otg__hcd_8h-source.html">dwc_otg_hcd.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="f79fefeb7908c0ddf702331253acb292"></a><!-- doxytag: member="dwc_otg_hcd::frame_number" ref="f79fefeb7908c0ddf702331253acb292" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint16_t <a class="el" href="structdwc__otg__hcd.html#f79fefeb7908c0ddf702331253acb292">dwc_otg_hcd::frame_number</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Frame number read from the core at SOF. 
+<p>
+The value ranges from 0 to DWC_HFNUM_MAX_FRNUM. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8h-source.html#l00470">470</a> of file <a class="el" href="dwc__otg__hcd_8h-source.html">dwc_otg_hcd.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="1761f2e6b8f6ba82c0e0c4e561813f0f"></a><!-- doxytag: member="dwc_otg_hcd::free_hc_list" ref="1761f2e6b8f6ba82c0e0c4e561813f0f" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">struct hc_list <a class="el" href="structdwc__otg__hcd.html#1761f2e6b8f6ba82c0e0c4e561813f0f">dwc_otg_hcd::free_hc_list</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Free host channels in the controller. 
+<p>
+This is a list of dwc_hc_t items. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8h-source.html#l00476">476</a> of file <a class="el" href="dwc__otg__hcd_8h-source.html">dwc_otg_hcd.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="5754b87bd4644fbb7b90cf843c638f1c"></a><!-- doxytag: member="dwc_otg_hcd::periodic_channels" ref="5754b87bd4644fbb7b90cf843c638f1c" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int <a class="el" href="structdwc__otg__hcd.html#5754b87bd4644fbb7b90cf843c638f1c">dwc_otg_hcd::periodic_channels</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Number of host channels assigned to periodic transfers. 
+<p>
+Currently assuming that there is a dedicated host channel for each periodic transaction and at least one host channel available for non-periodic transactions. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8h-source.html#l00483">483</a> of file <a class="el" href="dwc__otg__hcd_8h-source.html">dwc_otg_hcd.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="cb393f6a676fb106e0e3d35396fb97f9"></a><!-- doxytag: member="dwc_otg_hcd::hc_ptr_array" ref="cb393f6a676fb106e0e3d35396fb97f9" args="[MAX_EPS_CHANNELS]" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">struct <a class="el" href="structdwc__hc.html">dwc_hc</a>* <a class="el" href="structdwc__otg__hcd.html#cb393f6a676fb106e0e3d35396fb97f9">dwc_otg_hcd::hc_ptr_array</a>[MAX_EPS_CHANNELS]          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Array of pointers to the host channel descriptors. 
+<p>
+Allows accessing a host channel descriptor given the host channel number. This is useful in interrupt handlers. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8h-source.html#l00495">495</a> of file <a class="el" href="dwc__otg__hcd_8h-source.html">dwc_otg_hcd.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="68627912f0d3672096e6a98be38f66ab"></a><!-- doxytag: member="dwc_otg_hcd::status_buf" ref="68627912f0d3672096e6a98be38f66ab" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint8_t* <a class="el" href="structdwc__otg__hcd.html#68627912f0d3672096e6a98be38f66ab">dwc_otg_hcd::status_buf</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Buffer to use for any data received during the status phase of a control transfer. 
+<p>
+Normally no data is transferred during the status phase. This buffer is used as a bit bucket. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8h-source.html#l00502">502</a> of file <a class="el" href="dwc__otg__hcd_8h-source.html">dwc_otg_hcd.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="de7796a41bb7d1e45ed9dbc20c995342"></a><!-- doxytag: member="dwc_otg_hcd::conn_timer" ref="de7796a41bb7d1e45ed9dbc20c995342" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">dwc_timer_t* <a class="el" href="structdwc__otg__hcd.html#de7796a41bb7d1e45ed9dbc20c995342">dwc_otg_hcd::conn_timer</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Connection timer. 
+<p>
+An OTG host must display a message if the device does not connect. Started when the VBus power is turned on via sysfs attribute "buspower". 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8h-source.html#l00515">515</a> of file <a class="el" href="dwc__otg__hcd_8h-source.html">dwc_otg_hcd.h</a>.
+</div>
+</div><p>
+<hr>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__hcd_8h-source.html">dwc_otg_hcd.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__hcd__function__ops.html b/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__hcd__function__ops.html
new file mode 100644
index 000000000000..587487ebb0da
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__hcd__function__ops.html
@@ -0,0 +1,53 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd_function_ops Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>dwc_otg_hcd_function_ops Struct Reference</h1><!-- doxytag: class="dwc_otg_hcd_function_ops" --><table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="d74a65269fe5712ac307bfd3230a29b4"></a><!-- doxytag: member="dwc_otg_hcd_function_ops::start" ref="d74a65269fe5712ac307bfd3230a29b4" args="" -->
+<a class="el" href="dwc__otg__hcd__if_8h.html#76658d35c49c5594bdb795fddf8252a8">dwc_otg_hcd_start_cb_t</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd__function__ops.html#d74a65269fe5712ac307bfd3230a29b4">start</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="fb7650d10a745991479af978fb519651"></a><!-- doxytag: member="dwc_otg_hcd_function_ops::disconnect" ref="fb7650d10a745991479af978fb519651" args="" -->
+<a class="el" href="dwc__otg__hcd__if_8h.html#8190c45625905c85a22565524abcf192">dwc_otg_hcd_disconnect_cb_t</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd__function__ops.html#fb7650d10a745991479af978fb519651">disconnect</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="71bff93886173700d26a8950e7ea82e1"></a><!-- doxytag: member="dwc_otg_hcd_function_ops::hub_info" ref="71bff93886173700d26a8950e7ea82e1" args="" -->
+<a class="el" href="dwc__otg__hcd__if_8h.html#7893b4f0c0c2116e6cd8ba82659d7b65">dwc_otg_hcd_hub_info_from_urb_cb_t</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd__function__ops.html#71bff93886173700d26a8950e7ea82e1">hub_info</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="29f9b98c1a824637a5c8aec86649fdd4"></a><!-- doxytag: member="dwc_otg_hcd_function_ops::speed" ref="29f9b98c1a824637a5c8aec86649fdd4" args="" -->
+<a class="el" href="dwc__otg__hcd__if_8h.html#d85b6d5afa41eb5b0d1365b14642e77c">dwc_otg_hcd_speed_from_urb_cb_t</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd__function__ops.html#29f9b98c1a824637a5c8aec86649fdd4">speed</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="09a989481103de7468cd46ef61ace0ce"></a><!-- doxytag: member="dwc_otg_hcd_function_ops::complete" ref="09a989481103de7468cd46ef61ace0ce" args="" -->
+<a class="el" href="dwc__otg__hcd__if_8h.html#87b0daec8c90b013f81b4854b64dec2e">dwc_otg_hcd_complete_urb_cb_t</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd__function__ops.html#09a989481103de7468cd46ef61ace0ce">complete</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="24a2ee2bad4dc517fed62417a2a542d3"></a><!-- doxytag: member="dwc_otg_hcd_function_ops::get_b_hnp_enable" ref="24a2ee2bad4dc517fed62417a2a542d3" args="" -->
+<a class="el" href="dwc__otg__hcd__if_8h.html#23db00d75e435cb0cb13d1e914dfd672">dwc_otg_hcd_get_b_hnp_enable</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd__function__ops.html#24a2ee2bad4dc517fed62417a2a542d3">get_b_hnp_enable</a></td></tr>
+
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__if_8h-source.html#l00076">76</a> of file <a class="el" href="dwc__otg__hcd__if_8h-source.html">dwc_otg_hcd_if.h</a>.<hr>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__hcd__if_8h-source.html">dwc_otg_hcd_if.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__hcd__iso__packet__desc.html b/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__hcd__iso__packet__desc.html
new file mode 100644
index 000000000000..6067aef325e1
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__hcd__iso__packet__desc.html
@@ -0,0 +1,47 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd_iso_packet_desc Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>dwc_otg_hcd_iso_packet_desc Struct Reference</h1><!-- doxytag: class="dwc_otg_hcd_iso_packet_desc" --><table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="246f3d147a22cd295c534253593dca4a"></a><!-- doxytag: member="dwc_otg_hcd_iso_packet_desc::offset" ref="246f3d147a22cd295c534253593dca4a" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd__iso__packet__desc.html#246f3d147a22cd295c534253593dca4a">offset</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="8392d21b820df0181f4e6dca91234543"></a><!-- doxytag: member="dwc_otg_hcd_iso_packet_desc::length" ref="8392d21b820df0181f4e6dca91234543" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd__iso__packet__desc.html#8392d21b820df0181f4e6dca91234543">length</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c00b967f4c613820b99efc0abda5178c"></a><!-- doxytag: member="dwc_otg_hcd_iso_packet_desc::actual_length" ref="c00b967f4c613820b99efc0abda5178c" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd__iso__packet__desc.html#c00b967f4c613820b99efc0abda5178c">actual_length</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="d070772c24621c47b49ad21c6acadb94"></a><!-- doxytag: member="dwc_otg_hcd_iso_packet_desc::status" ref="d070772c24621c47b49ad21c6acadb94" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd__iso__packet__desc.html#d070772c24621c47b49ad21c6acadb94">status</a></td></tr>
+
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8h-source.html#l00063">63</a> of file <a class="el" href="dwc__otg__hcd_8h-source.html">dwc_otg_hcd.h</a>.<hr>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__hcd_8h-source.html">dwc_otg_hcd.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__hcd__pipe__info.html b/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__hcd__pipe__info.html
new file mode 100644
index 000000000000..dd40bdad440b
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__hcd__pipe__info.html
@@ -0,0 +1,50 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd_pipe_info Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>dwc_otg_hcd_pipe_info Struct Reference</h1><!-- doxytag: class="dwc_otg_hcd_pipe_info" --><table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3812ead0191c9b3bebf48fe8ea370d78"></a><!-- doxytag: member="dwc_otg_hcd_pipe_info::dev_addr" ref="3812ead0191c9b3bebf48fe8ea370d78" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd__pipe__info.html#3812ead0191c9b3bebf48fe8ea370d78">dev_addr</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="57b54466daa38c3a77f48e94c5e30f0d"></a><!-- doxytag: member="dwc_otg_hcd_pipe_info::ep_num" ref="57b54466daa38c3a77f48e94c5e30f0d" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd__pipe__info.html#57b54466daa38c3a77f48e94c5e30f0d">ep_num</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="0278c3069bc464cc4dbed8f6647f5856"></a><!-- doxytag: member="dwc_otg_hcd_pipe_info::pipe_type" ref="0278c3069bc464cc4dbed8f6647f5856" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd__pipe__info.html#0278c3069bc464cc4dbed8f6647f5856">pipe_type</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="8342fc4305ea957e2fa78f2bc9e707e4"></a><!-- doxytag: member="dwc_otg_hcd_pipe_info::pipe_dir" ref="8342fc4305ea957e2fa78f2bc9e707e4" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd__pipe__info.html#8342fc4305ea957e2fa78f2bc9e707e4">pipe_dir</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b1d585e71a4e15bc79fc5f6d87bada6a"></a><!-- doxytag: member="dwc_otg_hcd_pipe_info::mps" ref="b1d585e71a4e15bc79fc5f6d87bada6a" args="" -->
+uint16_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd__pipe__info.html#b1d585e71a4e15bc79fc5f6d87bada6a">mps</a></td></tr>
+
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8h-source.html#l00055">55</a> of file <a class="el" href="dwc__otg__hcd_8h-source.html">dwc_otg_hcd.h</a>.<hr>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__hcd_8h-source.html">dwc_otg_hcd.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__hcd__urb.html b/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__hcd__urb.html
new file mode 100644
index 000000000000..3cb4d1a44351
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__hcd__urb.html
@@ -0,0 +1,80 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd_urb Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>dwc_otg_hcd_urb Struct Reference</h1><!-- doxytag: class="dwc_otg_hcd_urb" --><table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="5ba0e393ef9768275db85c00e68be477"></a><!-- doxytag: member="dwc_otg_hcd_urb::priv" ref="5ba0e393ef9768275db85c00e68be477" args="" -->
+void *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd__urb.html#5ba0e393ef9768275db85c00e68be477">priv</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="68dc4d459bb70aed6083553653aadaad"></a><!-- doxytag: member="dwc_otg_hcd_urb::qtd" ref="68dc4d459bb70aed6083553653aadaad" args="" -->
+<a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd__urb.html#68dc4d459bb70aed6083553653aadaad">qtd</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="99ae35ffcd6147ddb93b361ab3bcfe95"></a><!-- doxytag: member="dwc_otg_hcd_urb::buf" ref="99ae35ffcd6147ddb93b361ab3bcfe95" args="" -->
+void *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd__urb.html#99ae35ffcd6147ddb93b361ab3bcfe95">buf</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="4e177a55239e95ae2f6c8b6b913f67fc"></a><!-- doxytag: member="dwc_otg_hcd_urb::dma" ref="4e177a55239e95ae2f6c8b6b913f67fc" args="" -->
+dwc_dma_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd__urb.html#4e177a55239e95ae2f6c8b6b913f67fc">dma</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="254afd954f3e24bb92841384183a317c"></a><!-- doxytag: member="dwc_otg_hcd_urb::setup_packet" ref="254afd954f3e24bb92841384183a317c" args="" -->
+void *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd__urb.html#254afd954f3e24bb92841384183a317c">setup_packet</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="497f61f9b3f6f77f6b844e31c047264d"></a><!-- doxytag: member="dwc_otg_hcd_urb::setup_dma" ref="497f61f9b3f6f77f6b844e31c047264d" args="" -->
+dwc_dma_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd__urb.html#497f61f9b3f6f77f6b844e31c047264d">setup_dma</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="dca57de4fdecd894241ce24167206a45"></a><!-- doxytag: member="dwc_otg_hcd_urb::length" ref="dca57de4fdecd894241ce24167206a45" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd__urb.html#dca57de4fdecd894241ce24167206a45">length</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="742c8a97d3867ab89148eae34e0c73a6"></a><!-- doxytag: member="dwc_otg_hcd_urb::actual_length" ref="742c8a97d3867ab89148eae34e0c73a6" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd__urb.html#742c8a97d3867ab89148eae34e0c73a6">actual_length</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="101e4a6762b9911cdb85768890fa1210"></a><!-- doxytag: member="dwc_otg_hcd_urb::status" ref="101e4a6762b9911cdb85768890fa1210" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd__urb.html#101e4a6762b9911cdb85768890fa1210">status</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="58c7018042c94c436637ea80354e7e28"></a><!-- doxytag: member="dwc_otg_hcd_urb::error_count" ref="58c7018042c94c436637ea80354e7e28" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd__urb.html#58c7018042c94c436637ea80354e7e28">error_count</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="570583697e8c1e4398969630bc2562f8"></a><!-- doxytag: member="dwc_otg_hcd_urb::packet_count" ref="570583697e8c1e4398969630bc2562f8" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd__urb.html#570583697e8c1e4398969630bc2562f8">packet_count</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="2f1d90765496d78d297b3e57ef4d781c"></a><!-- doxytag: member="dwc_otg_hcd_urb::flags" ref="2f1d90765496d78d297b3e57ef4d781c" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd__urb.html#2f1d90765496d78d297b3e57ef4d781c">flags</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="49c5353377e2fb173f1b34ae7be7e257"></a><!-- doxytag: member="dwc_otg_hcd_urb::interval" ref="49c5353377e2fb173f1b34ae7be7e257" args="" -->
+uint16_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd__urb.html#49c5353377e2fb173f1b34ae7be7e257">interval</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="34ee3ac5931687b41dd726f00c558369"></a><!-- doxytag: member="dwc_otg_hcd_urb::pipe_info" ref="34ee3ac5931687b41dd726f00c558369" args="" -->
+<a class="el" href="structdwc__otg__hcd__pipe__info.html">dwc_otg_hcd_pipe_info</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd__urb.html#34ee3ac5931687b41dd726f00c558369">pipe_info</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ed542f6a2d99dba2f6b71b0d8012ec8a"></a><!-- doxytag: member="dwc_otg_hcd_urb::iso_descs" ref="ed542f6a2d99dba2f6b71b0d8012ec8a" args="[0]" -->
+<a class="el" href="structdwc__otg__hcd__iso__packet__desc.html">dwc_otg_hcd_iso_packet_desc</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__hcd__urb.html#ed542f6a2d99dba2f6b71b0d8012ec8a">iso_descs</a> [0]</td></tr>
+
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8h-source.html#l00072">72</a> of file <a class="el" href="dwc__otg__hcd_8h-source.html">dwc_otg_hcd.h</a>.<hr>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__hcd_8h-source.html">dwc_otg_hcd.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__host__dma__desc.html b/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__host__dma__desc.html
new file mode 100644
index 000000000000..e888f0af510c
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__host__dma__desc.html
@@ -0,0 +1,50 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_host_dma_desc Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>dwc_otg_host_dma_desc Struct Reference</h1><!-- doxytag: class="dwc_otg_host_dma_desc" -->Host-mode DMA Descriptor structure.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="1b73b25e9fca51dd00fa0607d57d9e3f"></a><!-- doxytag: member="dwc_otg_host_dma_desc::status" ref="1b73b25e9fca51dd00fa0607d57d9e3f" args="" -->
+<a class="el" href="unionhost__dma__desc__sts.html">host_dma_desc_sts_t</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__host__dma__desc.html#1b73b25e9fca51dd00fa0607d57d9e3f">status</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">DMA Descriptor status quadlet. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="fdc395094e1a1f9bb89c316a96d4b96b"></a><!-- doxytag: member="dwc_otg_host_dma_desc::buf" ref="fdc395094e1a1f9bb89c316a96d4b96b" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__host__dma__desc.html#fdc395094e1a1f9bb89c316a96d4b96b">buf</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">DMA Descriptor data buffer pointer. <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+Host-mode DMA Descriptor structure. 
+<p>
+DMA Descriptor structure contains two quadlets: Status quadlet and Data buffer pointer. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l02166">2166</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__host__global__regs.html b/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__host__global__regs.html
new file mode 100644
index 000000000000..498888c9f71b
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__host__global__regs.html
@@ -0,0 +1,219 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_host_global_regs Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>dwc_otg_host_global_regs Struct Reference</h1><!-- doxytag: class="dwc_otg_host_global_regs" -->The Host Global Registers structure defines the size and relative field offsets for the Host Mode Global Registers.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__host__global__regs.html#fd7d93b5ffcb6c7c0a84ef656e6e68de">hcfg</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Host Configuration Register.  <a href="#fd7d93b5ffcb6c7c0a84ef656e6e68de"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__host__global__regs.html#d5ad893315e7b0dde27a3c5867dc56d0">hfir</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Host Frame Interval Register.  <a href="#d5ad893315e7b0dde27a3c5867dc56d0"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__host__global__regs.html#cebb0d86d0776473ef30eeac61e8692c">hfnum</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Host Frame Number / Frame Remaining Register.  <a href="#cebb0d86d0776473ef30eeac61e8692c"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__host__global__regs.html#fa21568e8b2f87538105f7109a9d1719">reserved40C</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Reserved.  <a href="#fa21568e8b2f87538105f7109a9d1719"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__host__global__regs.html#bf1a1528a2e479d86318d49ecd52ee40">hptxsts</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Host Periodic Transmit FIFO/ Queue Status Register.  <a href="#bf1a1528a2e479d86318d49ecd52ee40"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__host__global__regs.html#7c41808b0a69ed7d2125eb3afbbf6c14">haint</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Host All Channels Interrupt Register.  <a href="#7c41808b0a69ed7d2125eb3afbbf6c14"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__host__global__regs.html#317f5059d4c2dc91da041f5c0a4819fc">haintmsk</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Host All Channels Interrupt Mask Register.  <a href="#317f5059d4c2dc91da041f5c0a4819fc"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">volatile uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__host__global__regs.html#9a6af0a2c19d7b6228c7a40c9078907b">hflbaddr</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Host Frame List Base Address Register .  <a href="#9a6af0a2c19d7b6228c7a40c9078907b"></a><br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+The Host Global Registers structure defines the size and relative field offsets for the Host Mode Global Registers. 
+<p>
+Host Global Registers offsets 400h-7FFh. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01627">1627</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr><h2>Field Documentation</h2>
+<a class="anchor" name="fd7d93b5ffcb6c7c0a84ef656e6e68de"></a><!-- doxytag: member="dwc_otg_host_global_regs::hcfg" ref="fd7d93b5ffcb6c7c0a84ef656e6e68de" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__host__global__regs.html#fd7d93b5ffcb6c7c0a84ef656e6e68de">dwc_otg_host_global_regs::hcfg</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Host Configuration Register. 
+<p>
+<em>Offset: 400h</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01629">1629</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="d5ad893315e7b0dde27a3c5867dc56d0"></a><!-- doxytag: member="dwc_otg_host_global_regs::hfir" ref="d5ad893315e7b0dde27a3c5867dc56d0" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__host__global__regs.html#d5ad893315e7b0dde27a3c5867dc56d0">dwc_otg_host_global_regs::hfir</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Host Frame Interval Register. 
+<p>
+<em>Offset: 404h</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01631">1631</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="cebb0d86d0776473ef30eeac61e8692c"></a><!-- doxytag: member="dwc_otg_host_global_regs::hfnum" ref="cebb0d86d0776473ef30eeac61e8692c" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__host__global__regs.html#cebb0d86d0776473ef30eeac61e8692c">dwc_otg_host_global_regs::hfnum</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Host Frame Number / Frame Remaining Register. 
+<p>
+<em>Offset: 408h</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01633">1633</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="fa21568e8b2f87538105f7109a9d1719"></a><!-- doxytag: member="dwc_otg_host_global_regs::reserved40C" ref="fa21568e8b2f87538105f7109a9d1719" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t <a class="el" href="structdwc__otg__host__global__regs.html#fa21568e8b2f87538105f7109a9d1719">dwc_otg_host_global_regs::reserved40C</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Reserved. 
+<p>
+<em>Offset: 40Ch</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01635">1635</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="bf1a1528a2e479d86318d49ecd52ee40"></a><!-- doxytag: member="dwc_otg_host_global_regs::hptxsts" ref="bf1a1528a2e479d86318d49ecd52ee40" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__host__global__regs.html#bf1a1528a2e479d86318d49ecd52ee40">dwc_otg_host_global_regs::hptxsts</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Host Periodic Transmit FIFO/ Queue Status Register. 
+<p>
+<em>Offset: 410h</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01637">1637</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="7c41808b0a69ed7d2125eb3afbbf6c14"></a><!-- doxytag: member="dwc_otg_host_global_regs::haint" ref="7c41808b0a69ed7d2125eb3afbbf6c14" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__host__global__regs.html#7c41808b0a69ed7d2125eb3afbbf6c14">dwc_otg_host_global_regs::haint</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Host All Channels Interrupt Register. 
+<p>
+<em>Offset: 414h</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01639">1639</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="317f5059d4c2dc91da041f5c0a4819fc"></a><!-- doxytag: member="dwc_otg_host_global_regs::haintmsk" ref="317f5059d4c2dc91da041f5c0a4819fc" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__host__global__regs.html#317f5059d4c2dc91da041f5c0a4819fc">dwc_otg_host_global_regs::haintmsk</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Host All Channels Interrupt Mask Register. 
+<p>
+<em>Offset: 418h</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01641">1641</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="9a6af0a2c19d7b6228c7a40c9078907b"></a><!-- doxytag: member="dwc_otg_host_global_regs::hflbaddr" ref="9a6af0a2c19d7b6228c7a40c9078907b" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">volatile uint32_t <a class="el" href="structdwc__otg__host__global__regs.html#9a6af0a2c19d7b6228c7a40c9078907b">dwc_otg_host_global_regs::hflbaddr</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Host Frame List Base Address Register . 
+<p>
+<em>Offset: 41Ch</em> 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01643">1643</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<hr>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__host__if.html b/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__host__if.html
new file mode 100644
index 000000000000..83ca3eccf246
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__host__if.html
@@ -0,0 +1,66 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_host_if Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>dwc_otg_host_if Struct Reference</h1><!-- doxytag: class="dwc_otg_host_if" -->OTG Host Interface Structure.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ff9692c2e10ca2bc7e24f981f25179c2"></a><!-- doxytag: member="dwc_otg_host_if::host_global_regs" ref="ff9692c2e10ca2bc7e24f981f25179c2" args="" -->
+<a class="el" href="structdwc__otg__host__global__regs.html">dwc_otg_host_global_regs_t</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__host__if.html#ff9692c2e10ca2bc7e24f981f25179c2">host_global_regs</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Host Global Registers starting at offset 400h. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="dc8fe33e0bb3829cafa884d5fc603c4d"></a><!-- doxytag: member="dwc_otg_host_if::hprt0" ref="dc8fe33e0bb3829cafa884d5fc603c4d" args="" -->
+volatile uint32_t *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__host__if.html#dc8fe33e0bb3829cafa884d5fc603c4d">hprt0</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Host Port 0 Control and Status Register. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7f7c107d4720641eb4141cd817211ac0"></a><!-- doxytag: member="dwc_otg_host_if::hc_regs" ref="7f7c107d4720641eb4141cd817211ac0" args="[MAX_EPS_CHANNELS]" -->
+<a class="el" href="structdwc__otg__hc__regs.html">dwc_otg_hc_regs_t</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__host__if.html#7f7c107d4720641eb4141cd817211ac0">hc_regs</a> [MAX_EPS_CHANNELS]</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Host Channel Specific Registers at offsets 500h-5FCh. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="a7b144c7f83d79fdafd7cd0c8c06102d"></a><!-- doxytag: member="dwc_otg_host_if::num_host_channels" ref="a7b144c7f83d79fdafd7cd0c8c06102d" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__host__if.html#a7b144c7f83d79fdafd7cd0c8c06102d">num_host_channels</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Number of Host Channels (range: 1-16). <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="23dedb1efa17aa1c199f1e3c6e2a9784"></a><!-- doxytag: member="dwc_otg_host_if::perio_eps_supported" ref="23dedb1efa17aa1c199f1e3c6e2a9784" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__host__if.html#23dedb1efa17aa1c199f1e3c6e2a9784">perio_eps_supported</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Periodic EPs supported (0: no, 1: yes). <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b208538c559719cd680ea4828429735e"></a><!-- doxytag: member="dwc_otg_host_if::perio_tx_fifo_size" ref="b208538c559719cd680ea4828429735e" args="" -->
+uint16_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__host__if.html#b208538c559719cd680ea4828429735e">perio_tx_fifo_size</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Periodic Tx FIFO Size (Only 1 host periodic Tx FIFO). <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+OTG Host Interface Structure. 
+<p>
+The OTG Host Interface Structure structure contains information needed to manage the DWC_otg controller acting in host mode. It represents the programming view of the host-specific aspects of the controller. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l02181">2181</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__pcd.html b/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__pcd.html
new file mode 100644
index 000000000000..996688e5db3e
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__pcd.html
@@ -0,0 +1,152 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>dwc_otg_pcd Struct Reference</h1><!-- doxytag: class="dwc_otg_pcd" -->DWC_otg PCD Structure.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__pcd_8h-source.html">dwc_otg_pcd.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b7001dde5db2706707a860da0030d9e6"></a><!-- doxytag: member="dwc_otg_pcd::fops" ref="b7001dde5db2706707a860da0030d9e6" args="" -->
+<a class="el" href="structdwc__otg__pcd__function__ops.html">dwc_otg_pcd_function_ops</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__pcd.html#b7001dde5db2706707a860da0030d9e6">fops</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="995be0b313ab6aefc095c598528bbd4c"></a><!-- doxytag: member="dwc_otg_pcd::core_if" ref="995be0b313ab6aefc095c598528bbd4c" args="" -->
+<a class="el" href="structdwc__otg__core__if.html">dwc_otg_core_if_t</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__pcd.html#995be0b313ab6aefc095c598528bbd4c">core_if</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Core Interface. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="8f6963b3fb9ab83048c4c0697c90382a"></a><!-- doxytag: member="dwc_otg_pcd::ep0state" ref="8f6963b3fb9ab83048c4c0697c90382a" args="" -->
+<a class="el" href="dwc__otg__pcd_8h.html#70fcb6a989e5871e16f4c1c96ffe394a">ep0state_e</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__pcd.html#8f6963b3fb9ab83048c4c0697c90382a">ep0state</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">State of EP0. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="2c8be11c3b9c7cd02684348eb028aeb5"></a><!-- doxytag: member="dwc_otg_pcd::ep0_pending" ref="2c8be11c3b9c7cd02684348eb028aeb5" args="" -->
+unsigned&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__pcd.html#2c8be11c3b9c7cd02684348eb028aeb5">ep0_pending</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">EP0 Request is pending. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="cbe5c4062e140ee88f51ee916c0db0ad"></a><!-- doxytag: member="dwc_otg_pcd::request_config" ref="cbe5c4062e140ee88f51ee916c0db0ad" args="" -->
+unsigned&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__pcd.html#cbe5c4062e140ee88f51ee916c0db0ad">request_config</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Indicates when SET CONFIGURATION Request is in process. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="9d8e6d7f0ad10d580d467024e258f6f5"></a><!-- doxytag: member="dwc_otg_pcd::remote_wakeup_enable" ref="9d8e6d7f0ad10d580d467024e258f6f5" args="" -->
+unsigned&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__pcd.html#9d8e6d7f0ad10d580d467024e258f6f5">remote_wakeup_enable</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">The state of the Remote Wakeup Enable. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e09fc5322ac0d7deec2772984c10ae90"></a><!-- doxytag: member="dwc_otg_pcd::b_hnp_enable" ref="e09fc5322ac0d7deec2772984c10ae90" args="" -->
+unsigned&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__pcd.html#e09fc5322ac0d7deec2772984c10ae90">b_hnp_enable</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">The state of the B-Device HNP Enable. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e8008719644bdc23040f1a1545b7117f"></a><!-- doxytag: member="dwc_otg_pcd::a_hnp_support" ref="e8008719644bdc23040f1a1545b7117f" args="" -->
+unsigned&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__pcd.html#e8008719644bdc23040f1a1545b7117f">a_hnp_support</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">The state of A-Device HNP Support. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="49f2d2b04a4c07a8d53643f7681b5405"></a><!-- doxytag: member="dwc_otg_pcd::a_alt_hnp_support" ref="49f2d2b04a4c07a8d53643f7681b5405" args="" -->
+unsigned&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__pcd.html#49f2d2b04a4c07a8d53643f7681b5405">a_alt_hnp_support</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">The state of the A-Device Alt HNP support. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3a0464b4ac677a7742e9b7c0c820414c"></a><!-- doxytag: member="dwc_otg_pcd::request_pending" ref="3a0464b4ac677a7742e9b7c0c820414c" args="" -->
+unsigned&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__pcd.html#3a0464b4ac677a7742e9b7c0c820414c">request_pending</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Count of pending Requests. <br></td></tr>
+<tr><td class="memItemLeft" nowrap><a class="anchor" name="5ea5c519e678fbb382c2ea7d128562c1"></a><!-- doxytag: member="dwc_otg_pcd::setup_pkt" ref="5ea5c519e678fbb382c2ea7d128562c1" args="" -->
+union {</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;usb_device_request_t&nbsp;&nbsp;&nbsp;<a class="el" href="structdwc__otg__pcd.html#af0345bc2c877d96863ef440c923204c">req</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;uint32_t&nbsp;&nbsp;&nbsp;<a class="el" href="structdwc__otg__pcd.html#e4fe210f7a18b9f0c393af9cdf282d56">d32</a> [2]</td></tr>
+
+<tr><td class="memItemLeft" nowrap valign="top">}&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__pcd.html#5ea5c519e678fbb382c2ea7d128562c1">setup_pkt</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">SETUP packet for EP0 This structure is allocated as a DMA buffer on PCD initialization with enough space for up to 3 setup packets. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="606d94ec61cca4c21e4dc9cb2e3b7064"></a><!-- doxytag: member="dwc_otg_pcd::setup_pkt_dma_handle" ref="606d94ec61cca4c21e4dc9cb2e3b7064" args="" -->
+dwc_dma_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__pcd.html#606d94ec61cca4c21e4dc9cb2e3b7064">setup_pkt_dma_handle</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ca247241f78970f27e5c964fc04d47c8"></a><!-- doxytag: member="dwc_otg_pcd::status_buf" ref="ca247241f78970f27e5c964fc04d47c8" args="" -->
+uint16_t *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__pcd.html#ca247241f78970f27e5c964fc04d47c8">status_buf</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">2-byte dma buffer used to return status from GET_STATUS <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c3880dd4ce15c515ba37b90b6e7fd293"></a><!-- doxytag: member="dwc_otg_pcd::status_buf_dma_handle" ref="c3880dd4ce15c515ba37b90b6e7fd293" args="" -->
+dwc_dma_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__pcd.html#c3880dd4ce15c515ba37b90b6e7fd293">status_buf_dma_handle</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="14f4f2a41d1305fdc0ec1806d119da89"></a><!-- doxytag: member="dwc_otg_pcd::ep0" ref="14f4f2a41d1305fdc0ec1806d119da89" args="" -->
+<a class="el" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__pcd.html#14f4f2a41d1305fdc0ec1806d119da89">ep0</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">EP0. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="dbfc8c424ea3add38db96fa87219caa8"></a><!-- doxytag: member="dwc_otg_pcd::in_ep" ref="dbfc8c424ea3add38db96fa87219caa8" args="[MAX_EPS_CHANNELS-1]" -->
+<a class="el" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__pcd.html#dbfc8c424ea3add38db96fa87219caa8">in_ep</a> [MAX_EPS_CHANNELS-1]</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Array of IN EPs. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b9e49a1d1fbca5ba9523e27c7108df30"></a><!-- doxytag: member="dwc_otg_pcd::out_ep" ref="b9e49a1d1fbca5ba9523e27c7108df30" args="[MAX_EPS_CHANNELS-1]" -->
+<a class="el" href="structdwc__otg__pcd__ep.html">dwc_otg_pcd_ep_t</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__pcd.html#b9e49a1d1fbca5ba9523e27c7108df30">out_ep</a> [MAX_EPS_CHANNELS-1]</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Array of OUT EPs. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="5d450e4d06659ab2f3b18e5c816776e4"></a><!-- doxytag: member="dwc_otg_pcd::lock" ref="5d450e4d06659ab2f3b18e5c816776e4" args="" -->
+dwc_spinlock_t *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__pcd.html#5d450e4d06659ab2f3b18e5c816776e4">lock</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">number of valid EPs in the above array. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">dwc_timer_t *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__pcd.html#466fb6ae524fc970f164701db2e70246">srp_timer</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Timer for SRP.  <a href="#466fb6ae524fc970f164701db2e70246"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="d1aed2eb03a93032a1ce80e3145bb81e"></a><!-- doxytag: member="dwc_otg_pcd::test_mode_tasklet" ref="d1aed2eb03a93032a1ce80e3145bb81e" args="" -->
+dwc_tasklet_t *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__pcd.html#d1aed2eb03a93032a1ce80e3145bb81e">test_mode_tasklet</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Tasklet to defer starting of TEST mode transmissions until Status Phase has been completed. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="9b45cd00cd5835aba4236529a04b28f1"></a><!-- doxytag: member="dwc_otg_pcd::start_xfer_tasklet" ref="9b45cd00cd5835aba4236529a04b28f1" args="" -->
+dwc_tasklet_t *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__pcd.html#9b45cd00cd5835aba4236529a04b28f1">start_xfer_tasklet</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Tasklet to delay starting of xfer in DMA mode. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="577c57ee60c2ef42dce7791c85d50394"></a><!-- doxytag: member="dwc_otg_pcd::test_mode" ref="577c57ee60c2ef42dce7791c85d50394" args="" -->
+unsigned&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__pcd.html#577c57ee60c2ef42dce7791c85d50394">test_mode</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">The test mode to enter when the tasklet is executed. <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+DWC_otg PCD Structure. 
+<p>
+This structure encapsulates the data for the dwc_otg PCD. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd_8h-source.html#l00137">137</a> of file <a class="el" href="dwc__otg__pcd_8h-source.html">dwc_otg_pcd.h</a>.<hr><h2>Field Documentation</h2>
+<a class="anchor" name="466fb6ae524fc970f164701db2e70246"></a><!-- doxytag: member="dwc_otg_pcd::srp_timer" ref="466fb6ae524fc970f164701db2e70246" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">dwc_timer_t* <a class="el" href="structdwc__otg__pcd.html#466fb6ae524fc970f164701db2e70246">dwc_otg_pcd::srp_timer</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Timer for SRP. 
+<p>
+If it expires before SRP is successful clear the SRP. 
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd_8h-source.html#l00185">185</a> of file <a class="el" href="dwc__otg__pcd_8h-source.html">dwc_otg_pcd.h</a>.
+</div>
+</div><p>
+<hr>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__pcd_8h-source.html">dwc_otg_pcd.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__pcd__ep.html b/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__pcd__ep.html
new file mode 100644
index 000000000000..fed4ce3043fb
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__pcd__ep.html
@@ -0,0 +1,77 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd_ep Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>dwc_otg_pcd_ep Struct Reference</h1><!-- doxytag: class="dwc_otg_pcd_ep" -->PCD EP structure.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__pcd_8h-source.html">dwc_otg_pcd.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="86e27843c439dd0b1d12d9bf2dc6516f"></a><!-- doxytag: member="dwc_otg_pcd_ep::desc" ref="86e27843c439dd0b1d12d9bf2dc6516f" args="" -->
+const usb_endpoint_descriptor_t *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__pcd__ep.html#86e27843c439dd0b1d12d9bf2dc6516f">desc</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">USB EP Descriptor. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="71f4fa571dfdc96f62fa4869e6add300"></a><!-- doxytag: member="dwc_otg_pcd_ep::queue" ref="71f4fa571dfdc96f62fa4869e6add300" args="" -->
+req_list&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__pcd__ep.html#71f4fa571dfdc96f62fa4869e6add300">queue</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">queue of dwc_otg_pcd_requests. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="cce0e089118d8bf7c6278c21ded70d5a"></a><!-- doxytag: member="dwc_otg_pcd_ep::stopped" ref="cce0e089118d8bf7c6278c21ded70d5a" args="" -->
+unsigned&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__pcd__ep.html#cce0e089118d8bf7c6278c21ded70d5a">stopped</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="510fcd32761716abec5a35594a3d3ad3"></a><!-- doxytag: member="dwc_otg_pcd_ep::disabling" ref="510fcd32761716abec5a35594a3d3ad3" args="" -->
+unsigned&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__pcd__ep.html#510fcd32761716abec5a35594a3d3ad3">disabling</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="314db0fbde1d5eb9eae0cbe4fdef47a4"></a><!-- doxytag: member="dwc_otg_pcd_ep::dma" ref="314db0fbde1d5eb9eae0cbe4fdef47a4" args="" -->
+unsigned&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__pcd__ep.html#314db0fbde1d5eb9eae0cbe4fdef47a4">dma</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="bbec681b68f2f745d1cfecfedd4e64be"></a><!-- doxytag: member="dwc_otg_pcd_ep::queue_sof" ref="bbec681b68f2f745d1cfecfedd4e64be" args="" -->
+unsigned&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__pcd__ep.html#bbec681b68f2f745d1cfecfedd4e64be">queue_sof</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="716d3c29adc54c6822935fc2ae9bef51"></a><!-- doxytag: member="dwc_otg_pcd_ep::iso_req_handle" ref="716d3c29adc54c6822935fc2ae9bef51" args="" -->
+void *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__pcd__ep.html#716d3c29adc54c6822935fc2ae9bef51">iso_req_handle</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">ISOC req handle passed. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="6e43754ce0f3a4fe29e4d70fd58d4f8f"></a><!-- doxytag: member="dwc_otg_pcd_ep::dwc_ep" ref="6e43754ce0f3a4fe29e4d70fd58d4f8f" args="" -->
+<a class="el" href="structdwc__ep.html">dwc_ep_t</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__pcd__ep.html#6e43754ce0f3a4fe29e4d70fd58d4f8f">dwc_ep</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">DWC_otg ep data. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="234391334e48cbd72710d08655c9ed16"></a><!-- doxytag: member="dwc_otg_pcd_ep::pcd" ref="234391334e48cbd72710d08655c9ed16" args="" -->
+<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__pcd__ep.html#234391334e48cbd72710d08655c9ed16">pcd</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Pointer to PCD. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="8c8fad971c6c3b1c54d334c7f9b2d03e"></a><!-- doxytag: member="dwc_otg_pcd_ep::priv" ref="8c8fad971c6c3b1c54d334c7f9b2d03e" args="" -->
+void *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__pcd__ep.html#8c8fad971c6c3b1c54d334c7f9b2d03e">priv</a></td></tr>
+
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+PCD EP structure. 
+<p>
+This structure describes an EP, there is an array of EPs in the PCD structure. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd_8h-source.html#l00109">109</a> of file <a class="el" href="dwc__otg__pcd_8h-source.html">dwc_otg_pcd.h</a>.<hr>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__pcd_8h-source.html">dwc_otg_pcd.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__pcd__function__ops.html b/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__pcd__function__ops.html
new file mode 100644
index 000000000000..711d0e5cd39f
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__pcd__function__ops.html
@@ -0,0 +1,73 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd_function_ops Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>dwc_otg_pcd_function_ops Struct Reference</h1><!-- doxytag: class="dwc_otg_pcd_function_ops" -->Function Driver Ops Data Structure.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__pcd__if_8h-source.html">dwc_otg_pcd_if.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="4d3df508947b8ba75c5537617227cf9c"></a><!-- doxytag: member="dwc_otg_pcd_function_ops::connect" ref="4d3df508947b8ba75c5537617227cf9c" args="" -->
+<a class="el" href="dwc__otg__pcd__if_8h.html#4808152d074c472f4fb1aa7b662e3004">dwc_connect_cb_t</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__pcd__function__ops.html#4d3df508947b8ba75c5537617227cf9c">connect</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="51b0e7dcf19398bad4f0ec459b43077a"></a><!-- doxytag: member="dwc_otg_pcd_function_ops::disconnect" ref="51b0e7dcf19398bad4f0ec459b43077a" args="" -->
+<a class="el" href="dwc__otg__pcd__if_8h.html#959f051498d2957d47cb0d27b42546aa">dwc_disconnect_cb_t</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__pcd__function__ops.html#51b0e7dcf19398bad4f0ec459b43077a">disconnect</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e99e932440749d9464e008cef78e808d"></a><!-- doxytag: member="dwc_otg_pcd_function_ops::setup" ref="e99e932440749d9464e008cef78e808d" args="" -->
+<a class="el" href="dwc__otg__pcd__if_8h.html#a9145aeaa27da4fa1befb424f927fde7">dwc_setup_cb_t</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__pcd__function__ops.html#e99e932440749d9464e008cef78e808d">setup</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="126db5e83cd3cc03f303eb3da668816f"></a><!-- doxytag: member="dwc_otg_pcd_function_ops::complete" ref="126db5e83cd3cc03f303eb3da668816f" args="" -->
+<a class="el" href="dwc__otg__pcd__if_8h.html#9c448e9fa004f873c281f46f5e5a597d">dwc_completion_cb_t</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__pcd__function__ops.html#126db5e83cd3cc03f303eb3da668816f">complete</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="9714dfa4909221c0b937a9bcadf97339"></a><!-- doxytag: member="dwc_otg_pcd_function_ops::isoc_complete" ref="9714dfa4909221c0b937a9bcadf97339" args="" -->
+<a class="el" href="dwc__otg__pcd__if_8h.html#a6f91e357c7c7782afa7db03e95a52ed">dwc_isoc_completion_cb_t</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__pcd__function__ops.html#9714dfa4909221c0b937a9bcadf97339">isoc_complete</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="fef8ed359353cb84b7c5ac641d54d296"></a><!-- doxytag: member="dwc_otg_pcd_function_ops::suspend" ref="fef8ed359353cb84b7c5ac641d54d296" args="" -->
+<a class="el" href="dwc__otg__pcd__if_8h.html#ddcaadb93595803ca5f2ffb74cd88619">dwc_suspend_cb_t</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__pcd__function__ops.html#fef8ed359353cb84b7c5ac641d54d296">suspend</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="9b7666c7835bd611f87095d43b104f68"></a><!-- doxytag: member="dwc_otg_pcd_function_ops::sleep" ref="9b7666c7835bd611f87095d43b104f68" args="" -->
+<a class="el" href="dwc__otg__pcd__if_8h.html#fc48d3df458c446cc0ace0a7d7755c67">dwc_sleep_cb_t</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__pcd__function__ops.html#9b7666c7835bd611f87095d43b104f68">sleep</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="654870eb85c5356b6a97a514645e5d8c"></a><!-- doxytag: member="dwc_otg_pcd_function_ops::resume" ref="654870eb85c5356b6a97a514645e5d8c" args="" -->
+<a class="el" href="dwc__otg__pcd__if_8h.html#44d7ec17e6e087e44dd7c372e01fcfb2">dwc_resume_cb_t</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__pcd__function__ops.html#654870eb85c5356b6a97a514645e5d8c">resume</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="781da247a225731f7e8367e843081fe0"></a><!-- doxytag: member="dwc_otg_pcd_function_ops::reset" ref="781da247a225731f7e8367e843081fe0" args="" -->
+<a class="el" href="dwc__otg__pcd__if_8h.html#f6bba5b7b3d3ad67fbf2161717281fdd">dwc_reset_cb_t</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__pcd__function__ops.html#781da247a225731f7e8367e843081fe0">reset</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="db190030830b55d72b36255980be08d7"></a><!-- doxytag: member="dwc_otg_pcd_function_ops::hnp_changed" ref="db190030830b55d72b36255980be08d7" args="" -->
+<a class="el" href="dwc__otg__pcd__if_8h.html#eef0b7f44036d8164121ed079710058b">dwc_hnp_params_changed_cb_t</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__pcd__function__ops.html#db190030830b55d72b36255980be08d7">hnp_changed</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e717e78fcf05e0de9c6d478fee1afa87"></a><!-- doxytag: member="dwc_otg_pcd_function_ops::cfi_setup" ref="e717e78fcf05e0de9c6d478fee1afa87" args="" -->
+<a class="el" href="dwc__otg__pcd__if_8h.html#7d75df2095c14a2d985df8027359e440">cfi_setup_cb_t</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__pcd__function__ops.html#e717e78fcf05e0de9c6d478fee1afa87">cfi_setup</a></td></tr>
+
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+Function Driver Ops Data Structure. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__if_8h-source.html#l00107">107</a> of file <a class="el" href="dwc__otg__pcd__if_8h-source.html">dwc_otg_pcd_if.h</a>.<hr>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__pcd__if_8h-source.html">dwc_otg_pcd_if.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__pcd__request.html b/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__pcd__request.html
new file mode 100644
index 000000000000..d09628179ff4
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__pcd__request.html
@@ -0,0 +1,64 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd_request Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>dwc_otg_pcd_request Struct Reference</h1><!-- doxytag: class="dwc_otg_pcd_request" -->DWC_otg request structure.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__pcd_8h-source.html">dwc_otg_pcd.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Public Member Functions</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="8fec1facd3e67642d6c57c8912f7d632"></a><!-- doxytag: member="dwc_otg_pcd_request::DWC_CIRCLEQ_ENTRY" ref="8fec1facd3e67642d6c57c8912f7d632" args="(dwc_otg_pcd_request) queue_entry" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><b>DWC_CIRCLEQ_ENTRY</b> (<a class="el" href="structdwc__otg__pcd__request.html">dwc_otg_pcd_request</a>) queue_entry</td></tr>
+
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e0d93b64365968aa0dcf58535aecf40c"></a><!-- doxytag: member="dwc_otg_pcd_request::priv" ref="e0d93b64365968aa0dcf58535aecf40c" args="" -->
+void *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__pcd__request.html#e0d93b64365968aa0dcf58535aecf40c">priv</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c46438f3d95146654a25cd219d7a1d5a"></a><!-- doxytag: member="dwc_otg_pcd_request::buf" ref="c46438f3d95146654a25cd219d7a1d5a" args="" -->
+void *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__pcd__request.html#c46438f3d95146654a25cd219d7a1d5a">buf</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="df93c8905495816eb0327b192938a4a1"></a><!-- doxytag: member="dwc_otg_pcd_request::dma" ref="df93c8905495816eb0327b192938a4a1" args="" -->
+dwc_dma_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__pcd__request.html#df93c8905495816eb0327b192938a4a1">dma</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3dd3fcc889bf220b048023e8b05fab61"></a><!-- doxytag: member="dwc_otg_pcd_request::length" ref="3dd3fcc889bf220b048023e8b05fab61" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__pcd__request.html#3dd3fcc889bf220b048023e8b05fab61">length</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="0fd7d659f353273d8b2b22027306a2a2"></a><!-- doxytag: member="dwc_otg_pcd_request::actual" ref="0fd7d659f353273d8b2b22027306a2a2" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__pcd__request.html#0fd7d659f353273d8b2b22027306a2a2">actual</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c2c1832d46f417b63e41b5e23def6fc6"></a><!-- doxytag: member="dwc_otg_pcd_request::sent_zlp" ref="c2c1832d46f417b63e41b5e23def6fc6" args="" -->
+unsigned&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__pcd__request.html#c2c1832d46f417b63e41b5e23def6fc6">sent_zlp</a>:1</td></tr>
+
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+DWC_otg request structure. 
+<p>
+This structure is a list of requests. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd_8h-source.html#l00092">92</a> of file <a class="el" href="dwc__otg__pcd_8h-source.html">dwc_otg_pcd.h</a>.<hr>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__pcd_8h-source.html">dwc_otg_pcd.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__qh.html b/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__qh.html
new file mode 100644
index 000000000000..0e4c1697887c
--- /dev/null
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@@ -0,0 +1,228 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_qh Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>dwc_otg_qh Struct Reference</h1><!-- doxytag: class="dwc_otg_qh" -->A Queue Head (QH) holds the static characteristics of an endpoint and maintains a list of transfers (QTDs) for that endpoint.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__hcd_8h-source.html">dwc_otg_hcd.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__qh.html#98b78ffd8dbc01be44b302e873e73a82">ep_type</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Endpoint type.  <a href="#98b78ffd8dbc01be44b302e873e73a82"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="2dc622878a6617e5c803061804d5cf9f"></a><!-- doxytag: member="dwc_otg_qh::ep_is_in" ref="2dc622878a6617e5c803061804d5cf9f" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__qh.html#2dc622878a6617e5c803061804d5cf9f">ep_is_in</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="5975c2bede1ca0c6cfe9a66fe0a52567"></a><!-- doxytag: member="dwc_otg_qh::maxp" ref="5975c2bede1ca0c6cfe9a66fe0a52567" args="" -->
+uint16_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__qh.html#5975c2bede1ca0c6cfe9a66fe0a52567">maxp</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">wMaxPacketSize Field of Endpoint Descriptor. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__qh.html#42459dd91e199807783000b6dc358a7d">dev_speed</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Device speed.  <a href="#42459dd91e199807783000b6dc358a7d"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__qh.html#b0e001bfd76f5781926795ac47ef2c25">data_toggle</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Determines the PID of the next data packet for non-control transfers.  <a href="#b0e001bfd76f5781926795ac47ef2c25"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="2c115474978a808c797c8975d72e419d"></a><!-- doxytag: member="dwc_otg_qh::ping_state" ref="2c115474978a808c797c8975d72e419d" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__qh.html#2c115474978a808c797c8975d72e419d">ping_state</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Ping state if 1. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="9567d266da8e796d3467fb16ae867f8e"></a><!-- doxytag: member="dwc_otg_qh::qtd_list" ref="9567d266da8e796d3467fb16ae867f8e" args="" -->
+dwc_otg_qtd_list&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__qh.html#9567d266da8e796d3467fb16ae867f8e">qtd_list</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">List of QTDs for this QH. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="bbdb7d30b60b6c326301f33b35088bb4"></a><!-- doxytag: member="dwc_otg_qh::channel" ref="bbdb7d30b60b6c326301f33b35088bb4" args="" -->
+<a class="el" href="structdwc__hc.html">dwc_hc</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__qh.html#bbdb7d30b60b6c326301f33b35088bb4">channel</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Host channel currently processing transfers for this QH. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="8708dd009988ce20b8a8d52a4a96c5a3"></a><!-- doxytag: member="dwc_otg_qh::do_split" ref="8708dd009988ce20b8a8d52a4a96c5a3" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__qh.html#8708dd009988ce20b8a8d52a4a96c5a3">do_split</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Full/low speed endpoint on high-speed hub requires split. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="aac9f90a6afd9056dce79d013dd2168b"></a><!-- doxytag: member="dwc_otg_qh::dw_align_buf" ref="aac9f90a6afd9056dce79d013dd2168b" args="" -->
+uint8_t *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__qh.html#aac9f90a6afd9056dce79d013dd2168b">dw_align_buf</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Used instead of original buffer if it(physical address) is not dword-aligned. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b0b008f9d25f5e3b6e285d2830cfdca1"></a><!-- doxytag: member="dwc_otg_qh::dw_align_buf_dma" ref="b0b008f9d25f5e3b6e285d2830cfdca1" args="" -->
+dwc_dma_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__qh.html#b0b008f9d25f5e3b6e285d2830cfdca1">dw_align_buf_dma</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3e1cb9863dc72139e1832c04244c25ff"></a><!-- doxytag: member="dwc_otg_qh::qh_list_entry" ref="3e1cb9863dc72139e1832c04244c25ff" args="" -->
+dwc_list_link_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__qh.html#3e1cb9863dc72139e1832c04244c25ff">qh_list_entry</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Entry for QH in either the periodic or non-periodic schedule. <br></td></tr>
+<tr><td colspan="2"><div class="groupHeader">Periodic schedule information</div></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="401de6aadcfc2f99773f44c6731c4646"></a><!-- doxytag: member="dwc_otg_qh::usecs" ref="401de6aadcfc2f99773f44c6731c4646" args="" -->
+uint16_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__qh.html#401de6aadcfc2f99773f44c6731c4646">usecs</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Bandwidth in microseconds per (micro)frame. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="cdbce86d457f0ea08e2efedc47c9b315"></a><!-- doxytag: member="dwc_otg_qh::interval" ref="cdbce86d457f0ea08e2efedc47c9b315" args="" -->
+uint16_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__qh.html#cdbce86d457f0ea08e2efedc47c9b315">interval</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Interval between transfers in (micro)frames. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint16_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__qh.html#977a8032f08e45a9e9bdcd558a6965d3">sched_frame</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">(micro)frame to initialize a periodic transfer.  <a href="#977a8032f08e45a9e9bdcd558a6965d3"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="a92b9ff45f0eca459b41ca20e4d8e99c"></a><!-- doxytag: member="dwc_otg_qh::start_split_frame" ref="a92b9ff45f0eca459b41ca20e4d8e99c" args="" -->
+uint16_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__qh.html#a92b9ff45f0eca459b41ca20e4d8e99c">start_split_frame</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">(micro)frame at which last start split was initialized. <br></td></tr>
+<tr><td colspan="2"><div class="groupHeader">Descriptor DMA support</div></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="0e5f35688e54ba97054a1a7576e81150"></a><!-- doxytag: member="dwc_otg_qh::desc_list" ref="0e5f35688e54ba97054a1a7576e81150" args="" -->
+<a class="el" href="structdwc__otg__host__dma__desc.html">dwc_otg_host_dma_desc_t</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__qh.html#0e5f35688e54ba97054a1a7576e81150">desc_list</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Descriptor List. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c31412bb35362e77c697352fd4c3eeaf"></a><!-- doxytag: member="dwc_otg_qh::desc_list_dma" ref="c31412bb35362e77c697352fd4c3eeaf" args="" -->
+dwc_dma_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__qh.html#c31412bb35362e77c697352fd4c3eeaf">desc_list_dma</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Descriptor List physical address. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint32_t *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__qh.html#6b625d870c7854ccaff5c28fad87482a">n_bytes</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Xfer Bytes array.  <a href="#6b625d870c7854ccaff5c28fad87482a"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="6da0f75ffa49c8ffadde42e9618ed8c8"></a><!-- doxytag: member="dwc_otg_qh::ntd" ref="6da0f75ffa49c8ffadde42e9618ed8c8" args="" -->
+uint16_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__qh.html#6da0f75ffa49c8ffadde42e9618ed8c8">ntd</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Actual number of transfer descriptors in a list. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3b20e91c00b1de8d42612a8b1250b403"></a><!-- doxytag: member="dwc_otg_qh::td_first" ref="3b20e91c00b1de8d42612a8b1250b403" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__qh.html#3b20e91c00b1de8d42612a8b1250b403">td_first</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">First activated isochronous transfer descriptor index. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="9bd6dc808af3f1cab76ae7819af479f9"></a><!-- doxytag: member="dwc_otg_qh::td_last" ref="9bd6dc808af3f1cab76ae7819af479f9" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__qh.html#9bd6dc808af3f1cab76ae7819af479f9">td_last</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Last activated isochronous transfer descriptor index. <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+A Queue Head (QH) holds the static characteristics of an endpoint and maintains a list of transfers (QTDs) for that endpoint. 
+<p>
+A QH structure may be entered in either the non-periodic or periodic schedule. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8h-source.html#l00261">261</a> of file <a class="el" href="dwc__otg__hcd_8h-source.html">dwc_otg_hcd.h</a>.<hr><h2>Field Documentation</h2>
+<a class="anchor" name="98b78ffd8dbc01be44b302e873e73a82"></a><!-- doxytag: member="dwc_otg_qh::ep_type" ref="98b78ffd8dbc01be44b302e873e73a82" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint8_t <a class="el" href="structdwc__otg__qh.html#98b78ffd8dbc01be44b302e873e73a82">dwc_otg_qh::ep_type</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Endpoint type. 
+<p>
+One of the following values:<ul>
+<li>UE_CONTROL</li><li>UE_BULK</li><li>UE_INTERRUPT</li><li>UE_ISOCHRONOUS </li></ul>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8h-source.html#l00270">270</a> of file <a class="el" href="dwc__otg__hcd_8h-source.html">dwc_otg_hcd.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="42459dd91e199807783000b6dc358a7d"></a><!-- doxytag: member="dwc_otg_qh::dev_speed" ref="42459dd91e199807783000b6dc358a7d" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint8_t <a class="el" href="structdwc__otg__qh.html#42459dd91e199807783000b6dc358a7d">dwc_otg_qh::dev_speed</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Device speed. 
+<p>
+One of the following values:<ul>
+<li>DWC_OTG_EP_SPEED_LOW</li><li>DWC_OTG_EP_SPEED_FULL</li><li>DWC_OTG_EP_SPEED_HIGH </li></ul>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8h-source.html#l00283">283</a> of file <a class="el" href="dwc__otg__hcd_8h-source.html">dwc_otg_hcd.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="b0e001bfd76f5781926795ac47ef2c25"></a><!-- doxytag: member="dwc_otg_qh::data_toggle" ref="b0e001bfd76f5781926795ac47ef2c25" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint8_t <a class="el" href="structdwc__otg__qh.html#b0e001bfd76f5781926795ac47ef2c25">dwc_otg_qh::data_toggle</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Determines the PID of the next data packet for non-control transfers. 
+<p>
+Ignored for control transfers.<br>
+ One of the following values:<ul>
+<li>DWC_OTG_HC_PID_DATA0</li><li>DWC_OTG_HC_PID_DATA1 </li></ul>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8h-source.html#l00292">292</a> of file <a class="el" href="dwc__otg__hcd_8h-source.html">dwc_otg_hcd.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="977a8032f08e45a9e9bdcd558a6965d3"></a><!-- doxytag: member="dwc_otg_qh::sched_frame" ref="977a8032f08e45a9e9bdcd558a6965d3" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint16_t <a class="el" href="structdwc__otg__qh.html#977a8032f08e45a9e9bdcd558a6965d3">dwc_otg_qh::sched_frame</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+(micro)frame to initialize a periodic transfer. 
+<p>
+The transfer executes in the following (micro)frame. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8h-source.html#l00321">321</a> of file <a class="el" href="dwc__otg__hcd_8h-source.html">dwc_otg_hcd.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="6b625d870c7854ccaff5c28fad87482a"></a><!-- doxytag: member="dwc_otg_qh::n_bytes" ref="6b625d870c7854ccaff5c28fad87482a" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t* <a class="el" href="structdwc__otg__qh.html#6b625d870c7854ccaff5c28fad87482a">dwc_otg_qh::n_bytes</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Xfer Bytes array. 
+<p>
+Each element corresponds to a descriptor and indicates original XferSize size value for the descriptor. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8h-source.html#l00352">352</a> of file <a class="el" href="dwc__otg__hcd_8h-source.html">dwc_otg_hcd.h</a>.
+</div>
+</div><p>
+<hr>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__hcd_8h-source.html">dwc_otg_hcd.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__qtd.html b/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__qtd.html
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--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__qtd.html
@@ -0,0 +1,157 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_qtd Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>dwc_otg_qtd Struct Reference</h1><!-- doxytag: class="dwc_otg_qtd" -->A Queue Transfer Descriptor (QTD) holds the state of a bulk, control, interrupt, or isochronous transfer.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__hcd_8h-source.html">dwc_otg_hcd.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Public Member Functions</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="aac18e92835ac0678a83d023660f1560"></a><!-- doxytag: member="dwc_otg_qtd::DWC_CIRCLEQ_ENTRY" ref="aac18e92835ac0678a83d023660f1560" args="(dwc_otg_qtd) qtd_list_entry" -->
+&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__qtd.html#aac18e92835ac0678a83d023660f1560">DWC_CIRCLEQ_ENTRY</a> (<a class="el" href="structdwc__otg__qtd.html">dwc_otg_qtd</a>) qtd_list_entry</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This list of QTDs. <br></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__qtd.html#e912f256e01165b573c26262247a5eff">data_toggle</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Determines the PID of the next data packet for the data phase of control transfers.  <a href="#e912f256e01165b573c26262247a5eff"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="5189ec9c992974d20477481eaf96d0bb"></a><!-- doxytag: member="dwc_otg_qtd::control_phase" ref="5189ec9c992974d20477481eaf96d0bb" args="" -->
+<a class="el" href="dwc__otg__hcd_8h.html#be7c5653ee5e9d33855d2513f31b56a5">dwc_otg_control_phase_e</a>&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__qtd.html#5189ec9c992974d20477481eaf96d0bb">control_phase</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Current phase for control transfers (Setup, Data, or Status). <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="6355e968a4d36edce3e22c89ac7b5001"></a><!-- doxytag: member="dwc_otg_qtd::complete_split" ref="6355e968a4d36edce3e22c89ac7b5001" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__qtd.html#6355e968a4d36edce3e22c89ac7b5001">complete_split</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Keep track of the current split type for FS/LS endpoints on a HS Hub. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="badffe465e850133c62c8f7e539f3fca"></a><!-- doxytag: member="dwc_otg_qtd::ssplit_out_xfer_count" ref="badffe465e850133c62c8f7e539f3fca" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__qtd.html#badffe465e850133c62c8f7e539f3fca">ssplit_out_xfer_count</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">How many bytes transferred during SSPLIT OUT. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="18eeb9c647049aec468bf9a7861c873f"></a><!-- doxytag: member="dwc_otg_qtd::error_count" ref="18eeb9c647049aec468bf9a7861c873f" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__qtd.html#18eeb9c647049aec468bf9a7861c873f">error_count</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Holds the number of bus errors that have occurred for a transaction within this transfer. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint16_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__qtd.html#c67d5f885976d0698f20d113d32b4b30">isoc_frame_index</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Index of the next frame descriptor for an isochronous transfer.  <a href="#c67d5f885976d0698f20d113d32b4b30"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ab224d64d72f2ef4f10e722ebcfa29a6"></a><!-- doxytag: member="dwc_otg_qtd::isoc_split_pos" ref="ab224d64d72f2ef4f10e722ebcfa29a6" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__qtd.html#ab224d64d72f2ef4f10e722ebcfa29a6">isoc_split_pos</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Position of the ISOC split on full/low speed. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="839371940a7e34365e2272f3214b7e34"></a><!-- doxytag: member="dwc_otg_qtd::isoc_split_offset" ref="839371940a7e34365e2272f3214b7e34" args="" -->
+uint16_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__qtd.html#839371940a7e34365e2272f3214b7e34">isoc_split_offset</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Position of the ISOC split in the buffer for the current frame. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7e7767808e8eb9d71de0db00f57553f9"></a><!-- doxytag: member="dwc_otg_qtd::urb" ref="7e7767808e8eb9d71de0db00f57553f9" args="" -->
+<a class="el" href="structdwc__otg__hcd__urb.html">dwc_otg_hcd_urb</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__qtd.html#7e7767808e8eb9d71de0db00f57553f9">urb</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">URB for this transfer. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f80ddcfb6edbe83a3991dd67c93a47e4"></a><!-- doxytag: member="dwc_otg_qtd::qh" ref="f80ddcfb6edbe83a3991dd67c93a47e4" args="" -->
+<a class="el" href="structdwc__otg__qh.html">dwc_otg_qh</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__qtd.html#f80ddcfb6edbe83a3991dd67c93a47e4">qh</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c1d73f1d48eeabbdc198ad28c0882bc1"></a><!-- doxytag: member="dwc_otg_qtd::in_process" ref="c1d73f1d48eeabbdc198ad28c0882bc1" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__qtd.html#c1d73f1d48eeabbdc198ad28c0882bc1">in_process</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Indicates if this QTD is currently processed by HW. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ef3021e617cf1f448bd23b1f7ab3859b"></a><!-- doxytag: member="dwc_otg_qtd::n_desc" ref="ef3021e617cf1f448bd23b1f7ab3859b" args="" -->
+uint8_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__qtd.html#ef3021e617cf1f448bd23b1f7ab3859b">n_desc</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Number of DMA descriptors for this QTD. <br></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top">uint16_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structdwc__otg__qtd.html#c296d49e3615e35c06b83e7febc31943">isoc_frame_index_last</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Last activated frame(packet) index.  <a href="#c296d49e3615e35c06b83e7febc31943"></a><br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+A Queue Transfer Descriptor (QTD) holds the state of a bulk, control, interrupt, or isochronous transfer. 
+<p>
+A single QTD is created for each URB (of one of these types) submitted to the HCD. The transfer associated with a QTD may require one or multiple transactions.<p>
+A QTD is linked to a Queue Head, which is entered in either the non-periodic or periodic schedule for execution. When a QTD is chosen for execution, some or all of its transactions may be executed. After execution, the state of the QTD is updated. The QTD may be retired if all its transactions are complete or if an error occurred. Otherwise, it remains in the schedule so more transactions can be executed later. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8h-source.html#l00191">191</a> of file <a class="el" href="dwc__otg__hcd_8h-source.html">dwc_otg_hcd.h</a>.<hr><h2>Field Documentation</h2>
+<a class="anchor" name="e912f256e01165b573c26262247a5eff"></a><!-- doxytag: member="dwc_otg_qtd::data_toggle" ref="e912f256e01165b573c26262247a5eff" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint8_t <a class="el" href="structdwc__otg__qtd.html#e912f256e01165b573c26262247a5eff">dwc_otg_qtd::data_toggle</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Determines the PID of the next data packet for the data phase of control transfers. 
+<p>
+Ignored for other transfer types.<br>
+ One of the following values:<ul>
+<li>DWC_OTG_HC_PID_DATA0</li><li>DWC_OTG_HC_PID_DATA1 </li></ul>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8h-source.html#l00199">199</a> of file <a class="el" href="dwc__otg__hcd_8h-source.html">dwc_otg_hcd.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="c67d5f885976d0698f20d113d32b4b30"></a><!-- doxytag: member="dwc_otg_qtd::isoc_frame_index" ref="c67d5f885976d0698f20d113d32b4b30" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint16_t <a class="el" href="structdwc__otg__qtd.html#c67d5f885976d0698f20d113d32b4b30">dwc_otg_qtd::isoc_frame_index</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Index of the next frame descriptor for an isochronous transfer. 
+<p>
+A frame descriptor describes the buffer position and length of the data to be transferred in the next scheduled (micro)frame of an isochronous transfer. It also holds status for that transaction. The frame index starts at 0. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8h-source.html#l00224">224</a> of file <a class="el" href="dwc__otg__hcd_8h-source.html">dwc_otg_hcd.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="c296d49e3615e35c06b83e7febc31943"></a><!-- doxytag: member="dwc_otg_qtd::isoc_frame_index_last" ref="c296d49e3615e35c06b83e7febc31943" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint16_t <a class="el" href="structdwc__otg__qtd.html#c296d49e3615e35c06b83e7febc31943">dwc_otg_qtd::isoc_frame_index_last</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Last activated frame(packet) index. 
+<p>
+Used in Descriptor DMA mode only. 
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8h-source.html#l00250">250</a> of file <a class="el" href="dwc__otg__hcd_8h-source.html">dwc_otg_hcd.h</a>.
+</div>
+</div><p>
+<hr>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__hcd_8h-source.html">dwc_otg_hcd.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/structgadget__wrapper.html b/drivers/usb/host/dwc_otg/doc/html/structgadget__wrapper.html
new file mode 100644
index 000000000000..fbb5e8bc7943
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/structgadget__wrapper.html
@@ -0,0 +1,53 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: gadget_wrapper Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>gadget_wrapper Struct Reference</h1><!-- doxytag: class="gadget_wrapper" --><table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="cdc4a50b5415cc484f77c61a63db3e94"></a><!-- doxytag: member="gadget_wrapper::pcd" ref="cdc4a50b5415cc484f77c61a63db3e94" args="" -->
+<a class="el" href="structdwc__otg__pcd.html">dwc_otg_pcd_t</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structgadget__wrapper.html#cdc4a50b5415cc484f77c61a63db3e94">pcd</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="a1f30b68c6b42bc728c45c329312d7b1"></a><!-- doxytag: member="gadget_wrapper::gadget" ref="a1f30b68c6b42bc728c45c329312d7b1" args="" -->
+usb_gadget&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structgadget__wrapper.html#a1f30b68c6b42bc728c45c329312d7b1">gadget</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="8997a3c90f9eb0a8f40f5762ffc5ce60"></a><!-- doxytag: member="gadget_wrapper::driver" ref="8997a3c90f9eb0a8f40f5762ffc5ce60" args="" -->
+usb_gadget_driver *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structgadget__wrapper.html#8997a3c90f9eb0a8f40f5762ffc5ce60">driver</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="8f28c6610592157ecef50de726919162"></a><!-- doxytag: member="gadget_wrapper::ep0" ref="8f28c6610592157ecef50de726919162" args="" -->
+usb_ep&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structgadget__wrapper.html#8f28c6610592157ecef50de726919162">ep0</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="9b57a0085afa3decabffc89943866931"></a><!-- doxytag: member="gadget_wrapper::in_ep" ref="9b57a0085afa3decabffc89943866931" args="[16]" -->
+usb_ep&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structgadget__wrapper.html#9b57a0085afa3decabffc89943866931">in_ep</a> [16]</td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c420e5ba1a1c2d83d62471c423180d3c"></a><!-- doxytag: member="gadget_wrapper::out_ep" ref="c420e5ba1a1c2d83d62471c423180d3c" args="[16]" -->
+usb_ep&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structgadget__wrapper.html#c420e5ba1a1c2d83d62471c423180d3c">out_ep</a> [16]</td></tr>
+
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__pcd__linux_8c-source.html#l00082">82</a> of file <a class="el" href="dwc__otg__pcd__linux_8c-source.html">dwc_otg_pcd_linux.c</a>.<hr>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__pcd__linux_8c-source.html">dwc_otg_pcd_linux.c</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/structiso__pkt__info.html b/drivers/usb/host/dwc_otg/doc/html/structiso__pkt__info.html
new file mode 100644
index 000000000000..5cf3c97f3787
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/structiso__pkt__info.html
@@ -0,0 +1,49 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: iso_pkt_info Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>iso_pkt_info Struct Reference</h1><!-- doxytag: class="iso_pkt_info" -->Information for each ISOC packet.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="0c72a0585ccc93555da4db7e168f75f8"></a><!-- doxytag: member="iso_pkt_info::offset" ref="0c72a0585ccc93555da4db7e168f75f8" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structiso__pkt__info.html#0c72a0585ccc93555da4db7e168f75f8">offset</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ced82142e81778345016841e15020eb8"></a><!-- doxytag: member="iso_pkt_info::length" ref="ced82142e81778345016841e15020eb8" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structiso__pkt__info.html#ced82142e81778345016841e15020eb8">length</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="1317c3b425c0ef55dbde153b04c28dd4"></a><!-- doxytag: member="iso_pkt_info::status" ref="1317c3b425c0ef55dbde153b04c28dd4" args="" -->
+int32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structiso__pkt__info.html#1317c3b425c0ef55dbde153b04c28dd4">status</a></td></tr>
+
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+Information for each ISOC packet. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__cil_8h-source.html#l00077">77</a> of file <a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a>.<hr>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__cil_8h-source.html">dwc_otg_cil.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/structwrapper__priv__data.html b/drivers/usb/host/dwc_otg/doc/html/structwrapper__priv__data.html
new file mode 100644
index 000000000000..4bb779e0e304
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/structwrapper__priv__data.html
@@ -0,0 +1,38 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: wrapper_priv_data Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>wrapper_priv_data Struct Reference</h1><!-- doxytag: class="wrapper_priv_data" --><table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="3a5cfdab2772597d857294972bb171c8"></a><!-- doxytag: member="wrapper_priv_data::dwc_otg_hcd" ref="3a5cfdab2772597d857294972bb171c8" args="" -->
+<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd_t</a> *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structwrapper__priv__data.html#3a5cfdab2772597d857294972bb171c8">dwc_otg_hcd</a></td></tr>
+
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd__linux_8c-source.html#l00095">95</a> of file <a class="el" href="dwc__otg__hcd__linux_8c-source.html">dwc_otg_hcd_linux.c</a>.<hr>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__hcd__linux_8c-source.html">dwc_otg_hcd_linux.c</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/structzero__dev.html b/drivers/usb/host/dwc_otg/doc/html/structzero__dev.html
new file mode 100644
index 000000000000..3c565be289a4
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/structzero__dev.html
@@ -0,0 +1,56 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: zero_dev Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>zero_dev Struct Reference</h1><!-- doxytag: class="zero_dev" --><table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="712568d4b6a481845034ac6d87c0547d"></a><!-- doxytag: member="zero_dev::lock" ref="712568d4b6a481845034ac6d87c0547d" args="" -->
+spinlock_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structzero__dev.html#712568d4b6a481845034ac6d87c0547d">lock</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e0d019d6177afd1efa101aed63f1a174"></a><!-- doxytag: member="zero_dev::gadget" ref="e0d019d6177afd1efa101aed63f1a174" args="" -->
+usb_gadget *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structzero__dev.html#e0d019d6177afd1efa101aed63f1a174">gadget</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7dad5245ef3701a5521638e2499ebfe9"></a><!-- doxytag: member="zero_dev::req" ref="7dad5245ef3701a5521638e2499ebfe9" args="" -->
+usb_request *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structzero__dev.html#7dad5245ef3701a5521638e2499ebfe9">req</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="2481a8df9867ab54361cf4ffc7267484"></a><!-- doxytag: member="zero_dev::config" ref="2481a8df9867ab54361cf4ffc7267484" args="" -->
+u8&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structzero__dev.html#2481a8df9867ab54361cf4ffc7267484">config</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="8b35a5b8ce497d55d7369a4635d891df"></a><!-- doxytag: member="zero_dev::in_ep" ref="8b35a5b8ce497d55d7369a4635d891df" args="" -->
+usb_ep *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structzero__dev.html#8b35a5b8ce497d55d7369a4635d891df">in_ep</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="28a2079d55de6ac606cc69b79882223f"></a><!-- doxytag: member="zero_dev::out_ep" ref="28a2079d55de6ac606cc69b79882223f" args="" -->
+usb_ep *&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structzero__dev.html#28a2079d55de6ac606cc69b79882223f">out_ep</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="5fcacdfb9a6b069c866d44d66dd566a4"></a><!-- doxytag: member="zero_dev::resume" ref="5fcacdfb9a6b069c866d44d66dd566a4" args="" -->
+timer_list&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="structzero__dev.html#5fcacdfb9a6b069c866d44d66dd566a4">resume</a></td></tr>
+
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+
+<p>
+
+<p>
+Definition at line <a class="el" href="dummy__audio_8c-source.html#l00342">342</a> of file <a class="el" href="dummy__audio_8c-source.html">dummy_audio.c</a>.<hr>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dummy__audio_8c-source.html">dummy_audio.c</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/tabs.css b/drivers/usb/host/dwc_otg/doc/html/tabs.css
new file mode 100644
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+++ b/drivers/usb/host/dwc_otg/doc/html/tabs.css
@@ -0,0 +1,102 @@
+/* tabs styles, based on http://www.alistapart.com/articles/slidingdoors */
+
+DIV.tabs
+{
+   float            : left;
+   width            : 100%;
+   background       : url("tab_b.gif") repeat-x bottom;
+   margin-bottom    : 4px;
+}
+
+DIV.tabs UL
+{
+   margin           : 0px;
+   padding-left     : 10px;
+   list-style       : none;
+}
+
+DIV.tabs LI, DIV.tabs FORM
+{
+   display          : inline;
+   margin           : 0px;
+   padding          : 0px;
+}
+
+DIV.tabs FORM
+{
+   float            : right;
+}
+
+DIV.tabs A
+{
+   float            : left;
+   background       : url("tab_r.gif") no-repeat right top;
+   border-bottom    : 1px solid #84B0C7;
+   font-size        : x-small;
+   font-weight      : bold;
+   text-decoration  : none;
+}
+
+DIV.tabs A:hover
+{
+   background-position: 100% -150px;
+}
+
+DIV.tabs A:link, DIV.tabs A:visited,
+DIV.tabs A:active, DIV.tabs A:hover
+{
+       color: #1A419D;
+}
+
+DIV.tabs SPAN
+{
+   float            : left;
+   display          : block;
+   background       : url("tab_l.gif") no-repeat left top;
+   padding          : 5px 9px;
+   white-space      : nowrap;
+}
+
+DIV.tabs INPUT
+{
+   float            : right;
+   display          : inline;
+   font-size        : 1em;
+}
+
+DIV.tabs TD
+{
+   font-size        : x-small;
+   font-weight      : bold;
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+
+
+
+/* Commented Backslash Hack hides rule from IE5-Mac \*/
+DIV.tabs SPAN {float : none;}
+/* End IE5-Mac hack */
+
+DIV.tabs A:hover SPAN
+{
+   background-position: 0% -150px;
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+
+DIV.tabs LI#current A
+{
+   background-position: 100% -150px;
+   border-width     : 0px;
+}
+
+DIV.tabs LI#current SPAN
+{
+   background-position: 0% -150px;
+   padding-bottom   : 6px;
+}
+
+DIV.nav
+{
+   background       : none;
+   border           : none;
+   border-bottom    : 1px solid #84B0C7;
+}
diff --git a/drivers/usb/host/dwc_otg/doc/html/todo.html b/drivers/usb/host/dwc_otg/doc/html/todo.html
new file mode 100644
index 000000000000..88706b0729ed
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/todo.html
@@ -0,0 +1,262 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Todo List</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<h1><a class="anchor" name="todo">Todo List</a></h1><a class="anchor" name="_todo000001"></a> <dl>
+<dt>Global <a class="el" href="dwc__otg__attr_8c.html#a6ede17e817a37b1207d7a82147a8e57">DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW</a>  </dt>
+<dd>Add code to initiate the HNP. </dd>
+</dl>
+<p>
+<a class="anchor" name="_todo000002"></a> <dl>
+<dt>Global <a class="el" href="dwc__otg__attr_8c.html#9e8313bb6a0f54484d279b2e28269712">srp_show</a>  </dt>
+<dd>Add code to initiate the SRP. </dd>
+</dl>
+<p>
+<a class="anchor" name="_todo000003"></a> <dl>
+<dt>Global <a class="el" href="dwc__otg__attr_8c.html#6979f4909cde868d800dba13ef95aa8c">buspower_show</a>  </dt>
+<dd>Need to do more for power on/off? </dd>
+</dl>
+<p>
+<a class="anchor" name="_todo000004"></a> <dl>
+<dt>Global <a class="el" href="dwc__otg__attr_8c.html#ae1f7e3a17c5a0bcc5a93096aeb902d2">bussuspend_show</a>  </dt>
+<dd>Need to do more for suspend? </dd>
+</dl>
+<p>
+<a class="anchor" name="_todo000005"></a> <dl>
+<dt>Global <a class="el" href="dwc__otg__cil_8c.html#3d60e58f32be881047ac61bc852f60f7">dwc_otg_enable_device_interrupts</a>  </dt>
+<dd>NGS: Should this be a module parameter? </dd>
+</dl>
+<p>
+<a class="anchor" name="_todo000006"></a> <dl>
+<dt>Global <a class="el" href="dwc__otg__cil_8c.html#f79b0f3b5b96b0535e33627ee3a66eba">dwc_otg_core_dev_init</a>  </dt>
+<dd>NGS: Fix Periodic FIFO Sizing! </dd>
+</dl>
+<p>
+<a class="anchor" name="_todo000006"></a> <dl>
+<dt>Global <a class="el" href="dwc__otg__cil_8c.html#f79b0f3b5b96b0535e33627ee3a66eba">dwc_otg_core_dev_init</a>  </dt>
+<dd>Finish debug of this </dd>
+</dl>
+<p>
+<a class="anchor" name="_todo000006"></a> <dl>
+<dt>Global <a class="el" href="dwc__otg__cil_8c.html#f79b0f3b5b96b0535e33627ee3a66eba">dwc_otg_core_dev_init</a>  </dt>
+<dd>- if the condition needed to be checked or in any case all pending interrutps should be cleared? </dd>
+</dl>
+<p>
+<a class="anchor" name="_todo000009"></a> <dl>
+<dt>Global <a class="el" href="dwc__otg__cil_8c.html#d8c1e6f7860c482df84db003b52c369c">dwc_otg_ep0_continue_transfer</a>  </dt>
+<dd>Should there be check for room in the Tx Status Queue. If not remove the code above this comment. </dd>
+</dl>
+<p>
+<a class="anchor" name="_todo000010"></a> <dl>
+<dt>Global <a class="el" href="dwc__otg__cil_8c.html#97a11808b8b12a365a91f02b6d686d0c">dwc_otg_ep_write_packet</a>  </dt>
+<dd>NGS Where are the Periodic Tx FIFO addresses intialized? What should this be? </dd>
+</dl>
+<p>
+<a class="anchor" name="_todo000011"></a> <dl>
+<dt>Global <a class="el" href="dwc__otg__cil_8c.html#68f59dd23ccfffa9aa1dc590e99b7668">dwc_otg_read_packet</a>  </dt>
+<dd>Account for the case where _dest is not dword aligned. This requires reading data from the FIFO into a uint32_t temp buffer, then moving it into the data buffer. </dd>
+</dl>
+<p>
+<a class="anchor" name="_todo000012"></a> <dl>
+<dt>Global <a class="el" href="dwc__otg__cil__intr_8c.html#93001a1a9717b7e0491f5a2548fce1b6">dwc_otg_handle_disconnect_intr</a>  </dt>
+<dd>Consolidate this if statement. </dd>
+</dl>
+<p>
+<a class="anchor" name="_todo000013"></a> <dl>
+<dt>Global <a class="el" href="dwc__otg__cil__intr_8c.html#b86f8c4806bdc1f78ea438263c9f6c67">dwc_otg_read_common_intr</a>  </dt>
+<dd>: The port interrupt occurs while in device mode. Added code to CIL to clear the interrupt for now! </dd>
+</dl>
+<p>
+<a class="anchor" name="_todo000014"></a> <dl>
+<dt>Global <a class="el" href="dwc__otg__driver_8c.html#e0dbd8f1a438746fa8ec7798ceb2bd50">MODULE_PARM_DESC</a>  </dt>
+<dd>Set the max to 512K, modify checks </dd>
+</dl>
+<p>
+<a class="anchor" name="_todo000016"></a> <dl>
+<dt>Global <a class="el" href="dwc__otg__hcd_8h.html#b9dde24773f2741b9ff67e2d46760dc0">dwc_otg_hcd_handle_intr</a>  </dt>
+<dd>Implement i2cintr handler. </dd>
+</dl>
+<p>
+<a class="anchor" name="_todo000020"></a> <dl>
+<dt>Global <a class="el" href="dwc__otg__hcd_8h.html#187194b7a9f28e7f7a09ac3e345c7253">dwc_otg_hcd_qh_create</a>  </dt>
+<dd>add memflags argument </dd>
+</dl>
+<p>
+<a class="anchor" name="_todo000015"></a> <dl>
+<dt>Global <a class="el" href="dwc__otg__hcd_8h.html#ca94cde3142ff1121bb0ff9bd44fa762">dwc_otg_hcd_complete_xfer_ddma</a>  </dt>
+<dd>Consider the case when period exceeds FrameList size. Frame Rollover interrupt should be used. </dd>
+</dl>
+<p>
+<a class="anchor" name="_todo000017"></a> <dl>
+<dt>Global <a class="el" href="dwc__otg__hcd__intr_8c.html#5093a2b94c1d5cd1988eb93d9def298f">handle_hc_nyet_intr</a>  </dt>
+<dd>add support for isoc release </dd>
+</dl>
+<p>
+<a class="anchor" name="_todo000018"></a> <dl>
+<dt>Global <a class="el" href="dwc__otg__hcd__intr_8c.html#d75ed153a90dbda39d4d8e6cde4358df">handle_hc_chhltd_intr_dma</a>  </dt>
+<dd>This is here because of a possible hardware bug. Spec says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT interrupt w/ACK bit set should occur, but I only see the XFERCOMP bit, even with it masked out. This is a workaround for that behavior. Should fix this when hardware is fixed. </dd>
+</dl>
+<p>
+<a class="anchor" name="_todo000019"></a> <dl>
+<dt>Global <a class="el" href="dwc__otg__hcd__queue_8c.html#d32f8a4be67b758e9541e33746363677">qh_init</a>  </dt>
+<dd>Account for split transfers in the bus time. </dd>
+</dl>
+<p>
+<a class="anchor" name="_todo000021"></a> <dl>
+<dt>File <a class="el" href="dwc__otg__pcd_8c.html">dwc_otg_pcd.c</a>  </dt>
+<dd>Add Device Mode test modes (Test J mode, Test K mode, etc). <p>
+Does it work when the request size is greater than DEPTSIZ transfer size<p>
+</dd>
+</dl>
+<p>
+<a class="anchor" name="_todo000022"></a> <dl>
+<dt>Global <a class="el" href="dwc__otg__pcd_8c.html#e0a690ac031f8f06c2e7fb10b4633b05">dwc_otg_pcd_iso_ep_start</a>  </dt>
+<dd>- pattern data support is to be implemented in the future </dd>
+</dl>
+<p>
+<a class="anchor" name="_todo000023"></a> <dl>
+<dt>Global <a class="el" href="dwc__otg__pcd_8c.html#b6506996bd4b93ef4f80092a64384fae">dwc_otg_pcd_reinit</a>  </dt>
+<dd>NGS: Add direction to EP, based on contents of HWCFG1. Need a copy of HWCFG1 in pcd structure? sprintf(";r </dd>
+</dl>
+<p>
+<a class="anchor" name="_todo000023"></a> <dl>
+<dt>Global <a class="el" href="dwc__otg__pcd_8c.html#b6506996bd4b93ef4f80092a64384fae">dwc_otg_pcd_reinit</a>  </dt>
+<dd>NGS: Add direction to EP, based on contents of HWCFG1. Need a copy of HWCFG1 in pcd structure? sprintf(";r </dd>
+</dl>
+<p>
+<a class="anchor" name="_todo000025"></a> <dl>
+<dt>Global <a class="el" href="dwc__otg__pcd_8c.html#09f3d77397aa7d22a1ca32e26c8aedea">dwc_otg_pcd_ep_queue</a>  </dt>
+<dd>NGS Create a function for this. </dd>
+</dl>
+<p>
+<a class="anchor" name="_todo000033"></a> <dl>
+<dt>Global <a class="el" href="dwc__otg__pcd_8h.html#9d6d6e24faab6478aef9e2217c9b5ab9">do_test_mode</a>  </dt>
+<dd>This has not been tested since the tasklet struct was put into the PCD struct!<p>
+</dd>
+</dl>
+<p>
+<a class="anchor" name="_todo000026"></a> <dl>
+<dt>Global <a class="el" href="dwc__otg__pcd__intr_8c.html#99560d3941c21dedd1fb1fc846cea24f">dwc_otg_pcd_handle_rx_status_q_level_intr</a>  </dt>
+<dd>NGS Check for buffer overflow? </dd>
+</dl>
+<p>
+<a class="anchor" name="_todo000027"></a> <dl>
+<dt>Global <a class="el" href="dwc__otg__pcd__intr_8c.html#fde237571d3aaa5d03376d3bee827075">get_ep_of_last_in_token</a>  </dt>
+<dd>Find a simpler way to calculate the max queue position. </dd>
+</dl>
+<p>
+<a class="anchor" name="_todo000028"></a> <dl>
+<dt>Global <a class="el" href="dwc__otg__pcd__intr_8c.html#19e17d6a73d8a3ebf00a1d11999a5ff9">dwc_otg_pcd_stop</a>  </dt>
+<dd>NGS Flush Periodic FIFOs </dd>
+</dl>
+<p>
+<a class="anchor" name="_todo000029"></a> <dl>
+<dt>Global <a class="el" href="dwc__otg__pcd__intr_8c.html#726b57833bb3ae4648ce7e7a7e125bf7">ep0_out_start</a>  </dt>
+<dd>NGS: Update the comments from the HW FS.<p>
+</dd>
+</dl>
+<p>
+<a class="anchor" name="_todo000029"></a> <dl>
+<dt>Global <a class="el" href="dwc__otg__pcd__intr_8c.html#726b57833bb3ae4648ce7e7a7e125bf7">ep0_out_start</a>  </dt>
+<dd>dma needs to handle multiple setup packets (up to 3) </dd>
+</dl>
+<p>
+<a class="anchor" name="_todo000031"></a> <dl>
+<dt>Global <a class="el" href="dwc__otg__pcd__intr_8c.html#6c417c7d86bc9540e13ca4faeaf3dfbf">do_gadget_setup</a>  </dt>
+<dd>This is a g_file_storage gadget driver specific workaround: a DELAYED_STATUS result from the fsg_setup routine will result in the gadget queueing a EP0 IN status phase for a two-stage control transfer. Exactly the same as a SET_CONFIGURATION/SET_INTERFACE except that this is a class specific request. Need a generic way to know when the gadget driver will queue the status phase. Can we assume when we call the gadget driver setup() function that it will always queue and require the following flag? Need to look into this. </dd>
+</dl>
+<p>
+<a class="anchor" name="_todo000032"></a> <dl>
+<dt>Global <a class="el" href="dwc__otg__pcd__intr_8c.html#153d9a3b2162ef091dc24027379af19f">pcd_clear_halt</a>  </dt>
+<dd>FIXME: this causes an EP mismatch in DMA mode. epmismatch not yet implemented. </dd>
+</dl>
+<p>
+<a class="anchor" name="_todo000034"></a> <dl>
+<dt>Global <a class="el" href="dwc__otg__pcd__intr_8c.html#f449add2b4e8de7ced10fd1bb4c5b748">do_get_status</a>  </dt>
+<dd>check for EP stall </dd>
+</dl>
+<p>
+<a class="anchor" name="_todo000035"></a> <dl>
+<dt>Global <a class="el" href="dwc__otg__pcd__intr_8c.html#3754b29956ab3a85851dea376e046db9">do_set_feature</a>  </dt>
+<dd>This has not been tested since the tasklet struct was put into the PCD struct! </dd>
+</dl>
+<p>
+<a class="anchor" name="_todo000035"></a> <dl>
+<dt>Global <a class="el" href="dwc__otg__pcd__intr_8c.html#3754b29956ab3a85851dea376e046db9">do_set_feature</a>  </dt>
+<dd>Is the gotgctl.devhnpen cleared by a USB Reset? </dd>
+</dl>
+<p>
+<a class="anchor" name="_todo000037"></a> <dl>
+<dt>Global <a class="el" href="dwc__otg__pcd__intr_8c.html#2198ea3f0136465fa325a189d4ba5140">do_clear_feature</a>  </dt>
+<dd>Add CLEAR_FEATURE for TEST modes. </dd>
+</dl>
+<p>
+<a class="anchor" name="_todo000038"></a> <dl>
+<dt>Global <a class="el" href="dwc__otg__pcd__intr_8c.html#856a520a378e4f6f274253227080cfa1">pcd_setup</a>  </dt>
+<dd>handle &gt; 1 setup packet , assert error for now </dd>
+</dl>
+<p>
+<a class="anchor" name="_todo000038"></a> <dl>
+<dt>Global <a class="el" href="dwc__otg__pcd__intr_8c.html#856a520a378e4f6f274253227080cfa1">pcd_setup</a>  </dt>
+<dd>NGS: Handle bad setup packet? </dd>
+</dl>
+<p>
+<a class="anchor" name="_todo000040"></a> <dl>
+<dt>Global <a class="el" href="dwc__otg__pcd__intr_8c.html#65d4f747d13e368916ee0e16d202119b">handle_in_ep_timeout_intr</a>  </dt>
+<dd>NGS Check EP type. Implement for Periodic EPs </dd>
+</dl>
+<p>
+<a class="anchor" name="_todo000041"></a> <dl>
+<dt>Global <a class="el" href="dwc__otg__pcd__intr_8c.html#273ccc8e8cdb9e2075844f2f922b53bf">handle_in_ep_nak_intr</a>  </dt>
+<dd>implement ISR </dd>
+</dl>
+<p>
+<a class="anchor" name="_todo000042"></a> <dl>
+<dt>Global <a class="el" href="dwc__otg__pcd__intr_8c.html#42aef7ea134cccf7cdb53e7e1428bc4a">handle_out_ep_babble_intr</a>  </dt>
+<dd>implement ISR </dd>
+</dl>
+<p>
+<a class="anchor" name="_todo000043"></a> <dl>
+<dt>Global <a class="el" href="dwc__otg__pcd__intr_8c.html#252929e585c84eaf0485869cd7734244">handle_out_ep_nak_intr</a>  </dt>
+<dd>implement ISR </dd>
+</dl>
+<p>
+<a class="anchor" name="_todo000044"></a> <dl>
+<dt>Global <a class="el" href="dwc__otg__pcd__intr_8c.html#926d9068c1950cc406d50828e72a31db">handle_out_ep_nyet_intr</a>  </dt>
+<dd>implement ISR </dd>
+</dl>
+<p>
+<a class="anchor" name="_todo000045"></a> <dl>
+<dt>Global <a class="el" href="dwc__otg__pcd__linux_8c.html#647f81bc0edc9007af3ff2ba04e884f3">gadget_add_eps</a>  </dt>
+<dd>NGS: What should the max packet size be set to here? Before EP type is set? </dd>
+</dl>
+<p>
+<a class="anchor" name="_todo000045"></a> <dl>
+<dt>Global <a class="el" href="dwc__otg__pcd__linux_8c.html#647f81bc0edc9007af3ff2ba04e884f3">gadget_add_eps</a>  </dt>
+<dd>NGS: What should the max packet size be set to here? Before EP type is set? </dd>
+</dl>
+<p>
+<a class="anchor" name="_todo000045"></a> <dl>
+<dt>Global <a class="el" href="dwc__otg__pcd__linux_8c.html#647f81bc0edc9007af3ff2ba04e884f3">gadget_add_eps</a>  </dt>
+<dd>NGS: What should the max packet size be set to here? Before EP type is set? </dd>
+</dl>
+<p>
+<a class="anchor" name="_todo000048"></a> <dl>
+<dt>Global <a class="el" href="dwc__otg__pcd__linux_8c.html#6cbde69780790137d41fd45558236000">dwc_otg_pcd_gadget_release</a>  </dt>
+<dd>Should this do something? Should it free the PCD? </dd>
+</dl>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
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+  <body class="ftvtree">
+    <div class="directory">
+      <h3>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver</h3>
+      <div style="display: block;">
+        <p><img src="ftv2pnode.png" alt="o" width=16 height=22 onclick="toggleFolder('folder1', this)"/><img src="ftv2folderclosed.png" alt="+" width=24 height=22 onclick="toggleFolder('folder1', this)"/><a class="el" href="annotated.html" target="basefrm">Data Structures</a></p>
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+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="uniondtxfsts__data.html" target="basefrm">dtxfsts_data</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="structdwc__ep.html" target="basefrm">dwc_ep</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="structdwc__hc.html" target="basefrm">dwc_hc</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="structdwc__otg__cil__callbacks.html" target="basefrm">dwc_otg_cil_callbacks</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="structdwc__otg__core__global__regs.html" target="basefrm">dwc_otg_core_global_regs</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="structdwc__otg__core__if.html" target="basefrm">dwc_otg_core_if</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="structdwc__otg__core__params.html" target="basefrm">dwc_otg_core_params</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="structdwc__otg__dev__dma__desc.html" target="basefrm">dwc_otg_dev_dma_desc</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="structdwc__otg__dev__global__regs.html" target="basefrm">dwc_otg_dev_global_regs</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="structdwc__otg__dev__if.html" target="basefrm">dwc_otg_dev_if</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="structdwc__otg__dev__in__ep__regs.html" target="basefrm">dwc_otg_dev_in_ep_regs</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="structdwc__otg__dev__out__ep__regs.html" target="basefrm">dwc_otg_dev_out_ep_regs</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="structdwc__otg__device.html" target="basefrm">dwc_otg_device</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="structdwc__otg__driver__module__params.html" target="basefrm">dwc_otg_driver_module_params</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="structdwc__otg__hc__regs.html" target="basefrm">dwc_otg_hc_regs</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="structdwc__otg__hcd.html" target="basefrm">dwc_otg_hcd</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html" target="basefrm">dwc_otg_hcd::dwc_otg_hcd_internal_flags</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="structdwc__otg__hcd__function__ops.html" target="basefrm">dwc_otg_hcd_function_ops</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="structdwc__otg__hcd__iso__packet__desc.html" target="basefrm">dwc_otg_hcd_iso_packet_desc</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="structdwc__otg__hcd__pipe__info.html" target="basefrm">dwc_otg_hcd_pipe_info</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="structdwc__otg__hcd__urb.html" target="basefrm">dwc_otg_hcd_urb</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="structdwc__otg__host__dma__desc.html" target="basefrm">dwc_otg_host_dma_desc</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="structdwc__otg__host__global__regs.html" target="basefrm">dwc_otg_host_global_regs</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="structdwc__otg__host__if.html" target="basefrm">dwc_otg_host_if</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="structdwc__otg__pcd.html" target="basefrm">dwc_otg_pcd</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="structdwc__otg__pcd__ep.html" target="basefrm">dwc_otg_pcd_ep</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="structdwc__otg__pcd__function__ops.html" target="basefrm">dwc_otg_pcd_function_ops</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="structdwc__otg__pcd__request.html" target="basefrm">dwc_otg_pcd_request</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="structdwc__otg__qh.html" target="basefrm">dwc_otg_qh</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="structdwc__otg__qtd.html" target="basefrm">dwc_otg_qtd</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="unionfifosize__data.html" target="basefrm">fifosize_data</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="structgadget__wrapper.html" target="basefrm">gadget_wrapper</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="uniongahbcfg__data.html" target="basefrm">gahbcfg_data</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="uniongi2cctl__data.html" target="basefrm">gi2cctl_data</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="uniongintmsk__data.html" target="basefrm">gintmsk_data</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="uniongintsts__data.html" target="basefrm">gintsts_data</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="unionglpmctl__data.html" target="basefrm">glpmctl_data</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="uniongnptxsts__data.html" target="basefrm">gnptxsts_data</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="uniongotgctl__data.html" target="basefrm">gotgctl_data</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="uniongotgint__data.html" target="basefrm">gotgint_data</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="uniongrstctl__data.html" target="basefrm">grstctl_data</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="uniongusbcfg__data.html" target="basefrm">gusbcfg_data</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="unionhaint__data.html" target="basefrm">haint_data</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="unionhaintmsk__data.html" target="basefrm">haintmsk_data</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="unionhcchar__data.html" target="basefrm">hcchar_data</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="unionhcdma__data.html" target="basefrm">hcdma_data</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="unionhcfg__data.html" target="basefrm">hcfg_data</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="unionhcint__data.html" target="basefrm">hcint_data</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="unionhcintmsk__data.html" target="basefrm">hcintmsk_data</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="unionhcsplt__data.html" target="basefrm">hcsplt_data</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="unionhctsiz__data.html" target="basefrm">hctsiz_data</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="unionhfir__data.html" target="basefrm">hfir_data</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="unionhfnum__data.html" target="basefrm">hfnum_data</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="unionhost__dma__desc__sts.html" target="basefrm">host_dma_desc_sts</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="unionhost__grxsts__data.html" target="basefrm">host_grxsts_data</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="unionhprt0__data.html" target="basefrm">hprt0_data</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="unionhptxsts__data.html" target="basefrm">hptxsts_data</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="unionhwcfg1__data.html" target="basefrm">hwcfg1_data</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="unionhwcfg2__data.html" target="basefrm">hwcfg2_data</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="unionhwcfg3__data.html" target="basefrm">hwcfg3_data</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="unionhwcfg4__data.html" target="basefrm">hwcfg4_data</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="structiso__pkt__info.html" target="basefrm">iso_pkt_info</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="unionpcgcctl__data.html" target="basefrm">pcgcctl_data</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="structwrapper__priv__data.html" target="basefrm">wrapper_priv_data</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2lastnode.png" alt="\" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="structzero__dev.html" target="basefrm">zero_dev</a></p>
+        </div>
+        <p><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="functions.html" target="basefrm">Data Fields</a></p>
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+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="dwc__cfi__common_8h.html" target="basefrm">dwc_cfi_common.h</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="dwc__otg__attr_8c.html" target="basefrm">dwc_otg_attr.c</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="dwc__otg__attr_8h.html" target="basefrm">dwc_otg_attr.h</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="dwc__otg__cfi_8c.html" target="basefrm">dwc_otg_cfi.c</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="dwc__otg__cfi_8h.html" target="basefrm">dwc_otg_cfi.h</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="dwc__otg__cil_8c.html" target="basefrm">dwc_otg_cil.c</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="dwc__otg__cil_8h.html" target="basefrm">dwc_otg_cil.h</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="dwc__otg__cil__intr_8c.html" target="basefrm">dwc_otg_cil_intr.c</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="dwc__otg__core__if_8h.html" target="basefrm">dwc_otg_core_if.h</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="dwc__otg__dbg_8h.html" target="basefrm">dwc_otg_dbg.h</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="dwc__otg__driver_8c.html" target="basefrm">dwc_otg_driver.c</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="dwc__otg__driver_8h.html" target="basefrm">dwc_otg_driver.h</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="dwc__otg__hcd_8c.html" target="basefrm">dwc_otg_hcd.c</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="dwc__otg__hcd_8h.html" target="basefrm">dwc_otg_hcd.h</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="dwc__otg__hcd__ddma_8c.html" target="basefrm">dwc_otg_hcd_ddma.c</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="dwc__otg__hcd__if_8h.html" target="basefrm">dwc_otg_hcd_if.h</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="dwc__otg__hcd__intr_8c.html" target="basefrm">dwc_otg_hcd_intr.c</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="dwc__otg__hcd__linux_8c.html" target="basefrm">dwc_otg_hcd_linux.c</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="dwc__otg__hcd__queue_8c.html" target="basefrm">dwc_otg_hcd_queue.c</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="dwc__otg__pcd_8c.html" target="basefrm">dwc_otg_pcd.c</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="dwc__otg__pcd_8h.html" target="basefrm">dwc_otg_pcd.h</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="dwc__otg__pcd__if_8h.html" target="basefrm">dwc_otg_pcd_if.h</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="dwc__otg__pcd__intr_8c.html" target="basefrm">dwc_otg_pcd_intr.c</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="dwc__otg__pcd__linux_8c.html" target="basefrm">dwc_otg_pcd_linux.c</a></p>
+          <p><img src="ftv2vertline.png" alt="|" width=16 height=22 /><img src="ftv2lastnode.png" alt="\" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="dwc__otg__regs_8h.html" target="basefrm">dwc_otg_regs.h</a></p>
+        </div>
+        <p><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="globals.html" target="basefrm">Globals</a></p>
+        <p><img src="ftv2plastnode.png" alt="\" width=16 height=22 onclick="toggleFolder('folder3', this)"/><img src="ftv2folderclosed.png" alt="+" width=24 height=22 onclick="toggleFolder('folder3', this)"/><a class="el" href="pages.html" target="basefrm">Related Pages</a></p>
+        <div id="folder3">
+          <p><img src="ftv2blank.png" alt="&nbsp;" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="linux module attributes.html" target="basefrm">Linux Module Attributes</a></p>
+          <p><img src="ftv2blank.png" alt="&nbsp;" width=16 height=22 /><img src="ftv2node.png" alt="o" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="module parameters.html" target="basefrm">Module Parameters</a></p>
+          <p><img src="ftv2blank.png" alt="&nbsp;" width=16 height=22 /><img src="ftv2lastnode.png" alt="\" width=16 height=22 /><img src="ftv2doc.png" alt="*" width=24 height=22 /><a class="el" href="todo.html" target="basefrm">Todo List</a></p>
+        </div>
+      </div>
+    </div>
+  </body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/uniondaint__data.html b/drivers/usb/host/dwc_otg/doc/html/uniondaint__data.html
new file mode 100644
index 000000000000..f83b15f309b9
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/uniondaint__data.html
@@ -0,0 +1,131 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: daint_data Union Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>daint_data Union Reference</h1><!-- doxytag: class="daint_data" -->This union represents the bit fields in the Device All EP Interrupt and Mask Registers.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="cf05e79bf751384bef904448a231bc41"></a><!-- doxytag: member="daint_data::d32" ref="cf05e79bf751384bef904448a231bc41" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniondaint__data.html#cf05e79bf751384bef904448a231bc41">d32</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">raw register data <br></td></tr>
+<tr><td class="memItemLeft" nowrap><a class="anchor" name="5d048f0d5695317b05317d3c5ec4f79d"></a><!-- doxytag: member="daint_data::ep" ref="5d048f0d5695317b05317d3c5ec4f79d" args="" -->
+struct {</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondaint__data.html#dbc4f689d070e6cbc112ec910f8bc36a">in</a>:16</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">IN Endpoint bits. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondaint__data.html#8462ad2dc1692f1253b769445382e2d4">out</a>:16</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">OUT Endpoint bits. <br></td></tr>
+<tr><td class="memItemLeft" nowrap valign="top">}&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniondaint__data.html#5d048f0d5695317b05317d3c5ec4f79d">ep</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">register bits <br></td></tr>
+<tr><td class="memItemLeft" nowrap><a class="anchor" name="a75e47f1eb750ddd9b8213086fd49317"></a><!-- doxytag: member="daint_data::b" ref="a75e47f1eb750ddd9b8213086fd49317" args="" -->
+struct {</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondaint__data.html#371eb39ddd249f984242ffc6bc2590ba">inep0</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">IN Endpoint bits. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondaint__data.html#af6849b786344ddee9cd7f884199434c">inep1</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondaint__data.html#a52a2d17ef3dbea8fa25217629181a7c">inep2</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondaint__data.html#7152eb0ccf903be2810d1e25fef9bfb5">inep3</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondaint__data.html#f1e4c6eb79afda585c260a93c111aa12">inep4</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondaint__data.html#4175dc0a3f230773225f0971c31bc129">inep5</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondaint__data.html#40b670d2fc2b799a6278a16326441b1f">inep6</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondaint__data.html#8beeff7b54bd1902946425ab6a0d9d22">inep7</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondaint__data.html#baf8f1fe4bde7d02d61c93b5c7059f57">inep8</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondaint__data.html#ae119c728bcdf52e9504fedd16b0886b">inep9</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondaint__data.html#f7560a6b186b5a690382e443b12feee8">inep10</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondaint__data.html#67745fd9faa3ca8d8da6e937d782cc3e">inep11</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondaint__data.html#bbae9ce28263f0973e46ed65367f898b">inep12</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondaint__data.html#dc51893893bfeddf1e842a89d778b6d8">inep13</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondaint__data.html#8235ebce9e66c2d0e76edf7a1a5cd877">inep14</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondaint__data.html#419952bb56b11f01e7f0995e138237de">inep15</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondaint__data.html#c7e9083edca852fb7f2f64e8671aee84">outep0</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">OUT Endpoint bits. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondaint__data.html#32fab893aee2c30b343fcef45a2b663b">outep1</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondaint__data.html#ab37e9518e23799029192a422ca6a3ca">outep2</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondaint__data.html#db7e607293c77325f6940d33c56bc502">outep3</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondaint__data.html#17ad350597358b4795cf861409ba228c">outep4</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondaint__data.html#d50c4c8564d64cc4c176bcadd031b625">outep5</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondaint__data.html#d23b2e895318d194c683f2c6bb2ccbbe">outep6</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondaint__data.html#f8891bc2ff5fe8989c5119461e6ab126">outep7</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondaint__data.html#29c28a7d96343bfcc1f43faa72e83722">outep8</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondaint__data.html#8ad45fbc3efeb84ed83dc44b80e83c05">outep9</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondaint__data.html#1c2f136c1e7820cb09f31b7d7e8ddcf4">outep10</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondaint__data.html#f1df69d381a3a93148371edd890f375e">outep11</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondaint__data.html#fc51e98e345b027d0e015cebe87914a3">outep12</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondaint__data.html#fdb431a548b60ebf8ca6aea82c64b841">outep13</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondaint__data.html#14a49a0718676557899e5f121583778e">outep14</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondaint__data.html#f3223d420d13e35899760843900cc8ea">outep15</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap valign="top">}&nbsp;</td><td class="memItemRight" valign="bottom"><b>b</b></td></tr>
+
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This union represents the bit fields in the Device All EP Interrupt and Mask Registers. 
+<p>
+<ul>
+<li>Read the register into the <em>d32</em> member then set/clear the bits using the <em>b</em>it elements. </li></ul>
+
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01130">1130</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr>The documentation for this union was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/uniondcfg__data.html b/drivers/usb/host/dwc_otg/doc/html/uniondcfg__data.html
new file mode 100644
index 000000000000..42d30f27c13b
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/uniondcfg__data.html
@@ -0,0 +1,74 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dcfg_data Union Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>dcfg_data Union Reference</h1><!-- doxytag: class="dcfg_data" -->This union represents the bit fields in the Device Configuration Register.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="efd84d3306db1b4370535a0e814612dc"></a><!-- doxytag: member="dcfg_data::d32" ref="efd84d3306db1b4370535a0e814612dc" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniondcfg__data.html#efd84d3306db1b4370535a0e814612dc">d32</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">raw register data <br></td></tr>
+<tr><td class="memItemLeft" nowrap><a class="anchor" name="242c1b463f445de3fc265e8c20fde50b"></a><!-- doxytag: member="dcfg_data::b" ref="242c1b463f445de3fc265e8c20fde50b" args="" -->
+struct {</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondcfg__data.html#28ffb9fb43686fe553fbe80f1ead62a4">devspd</a>:2</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Device Speed. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondcfg__data.html#bfe8fbad12896d96cbeb686243f9602e">nzstsouthshk</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Non Zero Length Status OUT Handshake. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondcfg__data.html#34ff0184038007f588650f208026ef1a">reserved3</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondcfg__data.html#71c70afb48dd124d12e43d86edd90f1e">devaddr</a>:7</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Device Addresses. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondcfg__data.html#f4ed8f15f1716ff0f9366badac18fbb4">perfrint</a>:2</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Periodic Frame Interval. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondcfg__data.html#b6b4268d55a7dd952a0406c94abc8be0">reserved13_17</a>:5</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondcfg__data.html#9292b8ce264ebdb8a26c28883443a4df">epmscnt</a>:5</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">In Endpoint Mis-match count. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondcfg__data.html#d83666dcf5675453a387915ce1653d54">descdma</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Enable Descriptor DMA in Device mode. <br></td></tr>
+<tr><td class="memItemLeft" nowrap valign="top">}&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniondcfg__data.html#242c1b463f445de3fc265e8c20fde50b">b</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">register bits <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This union represents the bit fields in the Device Configuration Register. 
+<p>
+Read the register into the <em>d32</em> member then set/clear the bits using the <em>b</em>it elements. Write the <em>d32</em> member to the dcfg register. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00923">923</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr>The documentation for this union was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/uniondctl__data.html b/drivers/usb/host/dwc_otg/doc/html/uniondctl__data.html
new file mode 100644
index 000000000000..c403ec030668
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/uniondctl__data.html
@@ -0,0 +1,96 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dctl_data Union Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>dctl_data Union Reference</h1><!-- doxytag: class="dctl_data" -->This union represents the bit fields in the Device Control Register.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f49aadfd7ad95b570115b3c245b1729e"></a><!-- doxytag: member="dctl_data::d32" ref="f49aadfd7ad95b570115b3c245b1729e" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniondctl__data.html#f49aadfd7ad95b570115b3c245b1729e">d32</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">raw register data <br></td></tr>
+<tr><td class="memItemLeft" nowrap><a class="anchor" name="a3abfa6d609d9864f1f65712b409d4d3"></a><!-- doxytag: member="dctl_data::b" ref="a3abfa6d609d9864f1f65712b409d4d3" args="" -->
+struct {</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondctl__data.html#dcae5af28dc159cd7ba85a9a2b8be51a">rmtwkupsig</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Remote Wakeup. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondctl__data.html#3416d438405187a683c67f5006f7bfc8">sftdiscon</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Soft Disconnect. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondctl__data.html#26ba184e018a813e96527822f9e26fde">gnpinnaksts</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Global Non-Periodic IN NAK Status. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondctl__data.html#995d969d60e86b2ea662eb831c882b44">goutnaksts</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Global OUT NAK Status. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondctl__data.html#ef7a2687eef3086056f30b13f3588f9e">tstctl</a>:3</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Test Control. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondctl__data.html#2349dad5149cd3fcfd8fe3abcd77c32e">sgnpinnak</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Set Global Non-Periodic IN NAK. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondctl__data.html#6feecf1184cd67b8b8ede2e2030a5dba">cgnpinnak</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Clear Global Non-Periodic IN NAK. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondctl__data.html#28bd2f29264841207cd740ce9ec7fa91">sgoutnak</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Set Global OUT NAK. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondctl__data.html#7ffb7af3cfeb7efb811eb3c7fa7f3440">cgoutnak</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Clear Global OUT NAK. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondctl__data.html#216f929e4d24b0c3005cd0add0de7a27">pwronprgdone</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Power-On Programming Done. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondctl__data.html#212c36aaab3763a6de5cca56999c0263">gcontbna</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Global Continue on BNA. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondctl__data.html#6ceae1404558a4ffec4dab1c4702c7c8">gmc</a>:2</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Global Multi Count. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondctl__data.html#a817a529df5c5fc57135560014b90dcc">ifrmnum</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Ignore Frame Number for ISOC EPs. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondctl__data.html#422c27727aa788391b807b62011bd464">nakonbble</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">NAK on Babble. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondctl__data.html#dccb4bb22e6b46b3b92f495e8bdcd857">reserved17_31</a>:15</td></tr>
+
+<tr><td class="memItemLeft" nowrap valign="top">}&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniondctl__data.html#a3abfa6d609d9864f1f65712b409d4d3">b</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">register bits <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This union represents the bit fields in the Device Control Register. 
+<p>
+Read the register into the <em>d32</em> member then set/clear the bits using the <em>b</em>it elements. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00957">957</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr>The documentation for this union was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/uniondepctl__data.html b/drivers/usb/host/dwc_otg/doc/html/uniondepctl__data.html
new file mode 100644
index 000000000000..78a42437ce0a
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/uniondepctl__data.html
@@ -0,0 +1,139 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: depctl_data Union Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>depctl_data Union Reference</h1><!-- doxytag: class="depctl_data" -->This union represents the bit fields in the Device EP Control Register.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c3d4448663382417e50e23c05ff11a09"></a><!-- doxytag: member="depctl_data::d32" ref="c3d4448663382417e50e23c05ff11a09" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniondepctl__data.html#c3d4448663382417e50e23c05ff11a09">d32</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">raw register data <br></td></tr>
+<tr><td class="memItemLeft" nowrap><a class="anchor" name="92b47fc74de50f45d781d16e33176766"></a><!-- doxytag: member="depctl_data::b" ref="92b47fc74de50f45d781d16e33176766" args="" -->
+struct {</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondepctl__data.html#5899d20333186341271c2d0b7781b98c">mps</a>:11</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Maximum Packet Size IN/OUT EPn IN/OUT EP0 - 2 bits 2'b00: 64 Bytes 2'b01: 32 2'b10: 16 2'b11: 8. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondepctl__data.html#3bdea97ec728985cbc4b9305f3ed8e96">nextep</a>:4</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Next Endpoint IN EPn/IN EP0 OUT EPn/OUT EP0 - reserved. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondepctl__data.html#2ddb1e68ac29dfc383dacd94f76b4710">usbactep</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">USB Active Endpoint. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondepctl__data.html#ea2f031d4f4dd0580caa5707d50dd0c1">dpid</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Endpoint DPID (INTR/Bulk IN and OUT endpoints) This field contains the PID of the packet going to be received or transmitted on this endpoint.  <a href="#af1a491d20a3fa5c391bb7068c9a359e"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondepctl__data.html#98d3916b91f9d3d6c460d0ffaffd7b8b">naksts</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">NAK Status. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondepctl__data.html#f119782e7db731a3d4bf6c500b4ba5d2">eptype</a>:2</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Endpoint Type 2'b00: Control 2'b01: Isochronous 2'b10: Bulk 2'b11: Interrupt. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondepctl__data.html#27d9b0c9fa7b2c1a053d1ec7a1f69962">snp</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Snoop Mode OUT EPn/OUT EP0 IN EPn/IN EP0 - reserved. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondepctl__data.html#f7ad1bcf91d28b8a4aa8d3a343dd83e4">stall</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Stall Handshake. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondepctl__data.html#89fd2f9f2183a32181e9a04bf3251c43">txfnum</a>:4</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Tx Fifo Number IN EPn/IN EP0 OUT EPn/OUT EP0 - reserved. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondepctl__data.html#0b87d0914ceee7a20ffd2d7510b6a72e">cnak</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Clear NAK. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondepctl__data.html#ccf6e60ac8cabde8da36edb19504ba2b">snak</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Set NAK. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondepctl__data.html#90d89b642aafd60a6c62db5bf8396de9">setd0pid</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Set DATA0 PID (INTR/Bulk IN and OUT endpoints) Writing to this field sets the Endpoint DPID (DPID) field in this register to DATA0.  <a href="#190e93e7f574508e8e09c1bf1f6f6d47"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondepctl__data.html#9c0962acc0c23fe46a7738ad36634c25">setd1pid</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Set DATA1 PID (INTR/Bulk IN and OUT endpoints) Writing to this field sets the Endpoint DPID (DPID) field in this register to DATA1 Set Odd (micro)frame (SetOddFr) (ISO IN and OUT Endpoints) Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd (micro) frame. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondepctl__data.html#4d76ba4ebd506d3175ec5cdc0d811654">epdis</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Endpoint Disable. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondepctl__data.html#337ceb41a9e0735e144e684b1f9e5368">epena</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Endpoint Enable. <br></td></tr>
+<tr><td class="memItemLeft" nowrap valign="top">}&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniondepctl__data.html#92b47fc74de50f45d781d16e33176766">b</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">register bits <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This union represents the bit fields in the Device EP Control Register. 
+<p>
+Read the register into the <em>d32</em> member then set/clear the bits using the <em>b</em>it elements. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01304">1304</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr><h2>Field Documentation</h2>
+<a class="anchor" name="ea2f031d4f4dd0580caa5707d50dd0c1"></a><!-- doxytag: member="depctl_data::dpid" ref="ea2f031d4f4dd0580caa5707d50dd0c1" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">unsigned <a class="el" href="uniondepctl__data.html#ea2f031d4f4dd0580caa5707d50dd0c1">depctl_data::dpid</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Endpoint DPID (INTR/Bulk IN and OUT endpoints) This field contains the PID of the packet going to be received or transmitted on this endpoint. 
+<p>
+The application should program the PID of the first packet going to be received or transmitted on this endpoint , after the endpoint is activated. Application use the SetD1PID and SetD0PID fields of this register to program either D0 or D1 PID.<p>
+The encoding for this field is<ul>
+<li>0: D0</li><li>1: D1 </li></ul>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01344">1344</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="90d89b642aafd60a6c62db5bf8396de9"></a><!-- doxytag: member="depctl_data::setd0pid" ref="90d89b642aafd60a6c62db5bf8396de9" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">unsigned <a class="el" href="uniondepctl__data.html#90d89b642aafd60a6c62db5bf8396de9">depctl_data::setd0pid</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Set DATA0 PID (INTR/Bulk IN and OUT endpoints) Writing to this field sets the Endpoint DPID (DPID) field in this register to DATA0. 
+<p>
+Set Even (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints) Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even (micro) frame. 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01381">1381</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<hr>The documentation for this union was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/uniondeptsiz0__data.html b/drivers/usb/host/dwc_otg/doc/html/uniondeptsiz0__data.html
new file mode 100644
index 000000000000..e937961410b1
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/uniondeptsiz0__data.html
@@ -0,0 +1,69 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: deptsiz0_data Union Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>deptsiz0_data Union Reference</h1><!-- doxytag: class="deptsiz0_data" -->This union represents the bit fields in the Device EP 0 Transfer Size Register.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="a06fa9b1dcaee47fba9cf869027ed6f1"></a><!-- doxytag: member="deptsiz0_data::d32" ref="a06fa9b1dcaee47fba9cf869027ed6f1" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniondeptsiz0__data.html#a06fa9b1dcaee47fba9cf869027ed6f1">d32</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">raw register data <br></td></tr>
+<tr><td class="memItemLeft" nowrap><a class="anchor" name="8e50594573fd774fc3e27404d8b1f59c"></a><!-- doxytag: member="deptsiz0_data::b" ref="8e50594573fd774fc3e27404d8b1f59c" args="" -->
+struct {</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondeptsiz0__data.html#1792e672dde70ead19bd0f5e7642af03">xfersize</a>:7</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Transfer size. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondeptsiz0__data.html#c7fc04a01e440f0ed58541fd64a1b9be">reserved7_18</a>:12</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Reserved. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondeptsiz0__data.html#debb8f273e4480cde57bef7677697bd0">pktcnt</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Packet Count. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondeptsiz0__data.html#6a0d46284aeed1dd01b301ec503cc5c4">reserved20_28</a>:9</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Reserved. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondeptsiz0__data.html#60123707d51d7dfa22cd6b245402e49b">supcnt</a>:2</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Setup Packet Count (DOEPTSIZ0 Only). <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondeptsiz0__data.html#54b64c3a39b487b090048869c4a237e1">reserved31</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap valign="top">}&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniondeptsiz0__data.html#8e50594573fd774fc3e27404d8b1f59c">b</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">register bits <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This union represents the bit fields in the Device EP 0 Transfer Size Register. 
+<p>
+Read the register into the <em>d32</em> member then set/clear the bits using the <em>b</em>it elements. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01423">1423</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr>The documentation for this union was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/uniondeptsiz__data.html b/drivers/usb/host/dwc_otg/doc/html/uniondeptsiz__data.html
new file mode 100644
index 000000000000..1e89a244fc75
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/uniondeptsiz__data.html
@@ -0,0 +1,63 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: deptsiz_data Union Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>deptsiz_data Union Reference</h1><!-- doxytag: class="deptsiz_data" -->This union represents the bit fields in the Device EP Transfer Size Register.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="10c2b2ba8b419b0a766430a59befbbe0"></a><!-- doxytag: member="deptsiz_data::d32" ref="10c2b2ba8b419b0a766430a59befbbe0" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniondeptsiz__data.html#10c2b2ba8b419b0a766430a59befbbe0">d32</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">raw register data <br></td></tr>
+<tr><td class="memItemLeft" nowrap><a class="anchor" name="4ef5a09d8918c8ec2769c5b67f8b6d32"></a><!-- doxytag: member="deptsiz_data::b" ref="4ef5a09d8918c8ec2769c5b67f8b6d32" args="" -->
+struct {</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondeptsiz__data.html#cf06327d851e7cfe5c442b29bf2d6fa4">xfersize</a>:19</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Transfer size. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondeptsiz__data.html#bbd89e812371e5b555bb82373f3643d9">pktcnt</a>:10</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Packet Count. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondeptsiz__data.html#45a97381fba9a7d9c3bde425334a60a5">mc</a>:2</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Multi Count - Periodic IN endpoints. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondeptsiz__data.html#19515de87199335d65ebbd0e04a13f87">reserved</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap valign="top">}&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniondeptsiz__data.html#4ef5a09d8918c8ec2769c5b67f8b6d32">b</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">register bits <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This union represents the bit fields in the Device EP Transfer Size Register. 
+<p>
+Read the register into the <em>d32</em> member then set/clear the bits using the <em>b</em>it elements. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01403">1403</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr>The documentation for this union was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/uniondev__dma__desc__sts.html b/drivers/usb/host/dwc_otg/doc/html/uniondev__dma__desc__sts.html
new file mode 100644
index 000000000000..ba4db0f3b0f4
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/uniondev__dma__desc__sts.html
@@ -0,0 +1,140 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dev_dma_desc_sts Union Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>dev_dma_desc_sts Union Reference</h1><!-- doxytag: class="dev_dma_desc_sts" -->This union represents the bit fields in the DMA Descriptor status quadlet.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="fb77b9c4ab63304073542ed2b118a64b"></a><!-- doxytag: member="dev_dma_desc_sts::d32" ref="fb77b9c4ab63304073542ed2b118a64b" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniondev__dma__desc__sts.html#fb77b9c4ab63304073542ed2b118a64b">d32</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">raw register data <br></td></tr>
+<tr><td class="memItemLeft" nowrap><a class="anchor" name="1876c32496f0067948f6282b7583aeab"></a><!-- doxytag: member="dev_dma_desc_sts::b" ref="1876c32496f0067948f6282b7583aeab" args="" -->
+struct {</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondev__dma__desc__sts.html#9b6181d78984cb4d853945774f300ef0">bytes</a>:16</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Received number of bytes. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondev__dma__desc__sts.html#a87eecf4647accc23a4e409c6c2ad47c">reserved16_22</a>:7</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondev__dma__desc__sts.html#01c54383fd48fc31a3dd93ef54c417e8">mtrf</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Multiple Transfer - only for OUT EPs. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondev__dma__desc__sts.html#88d65d05f6561525543d09d0137c8967">sr</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Setup Packet received - only for OUT EPs. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondev__dma__desc__sts.html#02c8be72ef6258c25094478c7cac0b12">ioc</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Interrupt On Complete. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondev__dma__desc__sts.html#a850ddfa13601227c05e0ae43a538a9d">sp</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Short Packet. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondev__dma__desc__sts.html#b728a79d6a86a0d1b6426a1b2627f2c2">l</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Last. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondev__dma__desc__sts.html#2be04f03ca64c3484260b2235aef3b9b">sts</a>:2</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Receive Status. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondev__dma__desc__sts.html#05d1c1d8f6c5a1967c51c5d0e2e04261">bs</a>:2</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Buffer Status. <br></td></tr>
+<tr><td class="memItemLeft" nowrap valign="top">}&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniondev__dma__desc__sts.html#1876c32496f0067948f6282b7583aeab">b</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">quadlet bits <br></td></tr>
+<tr><td class="memItemLeft" nowrap><a class="anchor" name="214ba099b6077c3393b179cf9a7909f7"></a><!-- doxytag: member="dev_dma_desc_sts::b_iso_out" ref="214ba099b6077c3393b179cf9a7909f7" args="" -->
+struct {</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondev__dma__desc__sts.html#ede78801cd7bc514474fcbe1ef154e5a">rxbytes</a>:11</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Received number of bytes. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondev__dma__desc__sts.html#268998cfefef876150fff80a33ba70a6">reserved11</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondev__dma__desc__sts.html#d9da3eccc6d247e2b5eccd4dfba7874e">framenum</a>:11</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Frame Number. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondev__dma__desc__sts.html#79bf5fe6d9949ddb671daa14b5ee298e">pid</a>:2</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Received ISO Data PID. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondev__dma__desc__sts.html#02c8be72ef6258c25094478c7cac0b12">ioc</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Interrupt On Complete. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondev__dma__desc__sts.html#a850ddfa13601227c05e0ae43a538a9d">sp</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Short Packet. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondev__dma__desc__sts.html#b728a79d6a86a0d1b6426a1b2627f2c2">l</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Last. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondev__dma__desc__sts.html#a80809cda5b19b3e36f512effef795f0">rxsts</a>:2</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Receive Status. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondev__dma__desc__sts.html#05d1c1d8f6c5a1967c51c5d0e2e04261">bs</a>:2</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Buffer Status. <br></td></tr>
+<tr><td class="memItemLeft" nowrap valign="top">}&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniondev__dma__desc__sts.html#214ba099b6077c3393b179cf9a7909f7">b_iso_out</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">iso out quadlet bits <br></td></tr>
+<tr><td class="memItemLeft" nowrap><a class="anchor" name="324fdd57830243334b74e0579b4e9f96"></a><!-- doxytag: member="dev_dma_desc_sts::b_iso_in" ref="324fdd57830243334b74e0579b4e9f96" args="" -->
+struct {</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondev__dma__desc__sts.html#56cc3ad6b0e5704c6eb394f58f660eef">txbytes</a>:12</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Transmited number of bytes. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondev__dma__desc__sts.html#d9da3eccc6d247e2b5eccd4dfba7874e">framenum</a>:11</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Frame Number. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondev__dma__desc__sts.html#79bf5fe6d9949ddb671daa14b5ee298e">pid</a>:2</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Transmited ISO Data PID. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondev__dma__desc__sts.html#02c8be72ef6258c25094478c7cac0b12">ioc</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Interrupt On Complete. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondev__dma__desc__sts.html#a850ddfa13601227c05e0ae43a538a9d">sp</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Short Packet. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondev__dma__desc__sts.html#b728a79d6a86a0d1b6426a1b2627f2c2">l</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Last. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondev__dma__desc__sts.html#30ebc024572822f0803d28c95914a44c">txsts</a>:2</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Transmit Status. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondev__dma__desc__sts.html#05d1c1d8f6c5a1967c51c5d0e2e04261">bs</a>:2</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Buffer Status. <br></td></tr>
+<tr><td class="memItemLeft" nowrap valign="top">}&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniondev__dma__desc__sts.html#324fdd57830243334b74e0579b4e9f96">b_iso_in</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">iso in quadlet bits <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This union represents the bit fields in the DMA Descriptor status quadlet. 
+<p>
+Read the quadlet into the <em>d32</em> member then set/clear the bits using the <em>b</em>it, <em>b_iso_out</em> and <em>b_iso_in</em> elements. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01466">1466</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr>The documentation for this union was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/uniondevice__grxsts__data.html b/drivers/usb/host/dwc_otg/doc/html/uniondevice__grxsts__data.html
new file mode 100644
index 000000000000..14c82c90fa0c
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/uniondevice__grxsts__data.html
@@ -0,0 +1,62 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: device_grxsts_data Union Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>device_grxsts_data Union Reference</h1><!-- doxytag: class="device_grxsts_data" -->This union represents the bit fields in the Device Receive Status Read and Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <em>d32</em> element then read out the bits using the <em>b</em>it elements.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="9d454f39c05e23d376dfb0069d933986"></a><!-- doxytag: member="device_grxsts_data::d32" ref="9d454f39c05e23d376dfb0069d933986" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniondevice__grxsts__data.html#9d454f39c05e23d376dfb0069d933986">d32</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">raw register data <br></td></tr>
+<tr><td class="memItemLeft" nowrap><a class="anchor" name="dbcda32a5bc5e5423bcf6e01d99c7686"></a><!-- doxytag: member="device_grxsts_data::b" ref="dbcda32a5bc5e5423bcf6e01d99c7686" args="" -->
+struct {</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondevice__grxsts__data.html#d91e207bb8fb6e20652e6ad2474aec8e">epnum</a>:4</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondevice__grxsts__data.html#6162a5f256d8041bc3d1d1071e999107">bcnt</a>:11</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondevice__grxsts__data.html#d0f4716b612b04fde649a2f689ea5b88">dpid</a>:2</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondevice__grxsts__data.html#712eb005af256f84ebfc6f3083dd1ba8">pktsts</a>:4</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondevice__grxsts__data.html#f535ee62a482ec97ca61dc4954e358c6">fn</a>:4</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondevice__grxsts__data.html#95064e007a2dd525524d59af9f27eb36">reserved</a>:7</td></tr>
+
+<tr><td class="memItemLeft" nowrap valign="top">}&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniondevice__grxsts__data.html#dbcda32a5bc5e5423bcf6e01d99c7686">b</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">register bits <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This union represents the bit fields in the Device Receive Status Read and Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <em>d32</em> element then read out the bits using the <em>b</em>it elements. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00601">601</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr>The documentation for this union was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/uniondiepint__data.html b/drivers/usb/host/dwc_otg/doc/html/uniondiepint__data.html
new file mode 100644
index 000000000000..d905ea08253f
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/uniondiepint__data.html
@@ -0,0 +1,90 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: diepint_data Union Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>diepint_data Union Reference</h1><!-- doxytag: class="diepint_data" -->This union represents the bit fields in the Device IN EP Interrupt Register and the Device IN EP Common Mask Register.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="7d2c24507663bf96c280c57fbf544ef7"></a><!-- doxytag: member="diepint_data::d32" ref="7d2c24507663bf96c280c57fbf544ef7" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniondiepint__data.html#7d2c24507663bf96c280c57fbf544ef7">d32</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">raw register data <br></td></tr>
+<tr><td class="memItemLeft" nowrap><a class="anchor" name="48d2a745e0ec983a47b35b0428b0437d"></a><!-- doxytag: member="diepint_data::b" ref="48d2a745e0ec983a47b35b0428b0437d" args="" -->
+struct {</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondiepint__data.html#56e1252841323973e0ada12cc89059c9">xfercompl</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Transfer complete mask. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondiepint__data.html#3a649b75195fb5b26135d75b03cf561d">epdisabled</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Endpoint disable mask. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondiepint__data.html#6d57fa84f687bc4f05013c1e1a7edf29">ahberr</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">AHB Error mask. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondiepint__data.html#2513e8eef259c711e9a139cb2631b142">timeout</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">TimeOUT Handshake mask (non-ISOC EPs). <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondiepint__data.html#7c9961f17328bbc25ca39e7ec1891e16">intktxfemp</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">IN Token received with TxF Empty mask. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondiepint__data.html#103fb29d954cf12d33f7ebe6009f9a46">intknepmis</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">IN Token Received with EP mismatch mask. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondiepint__data.html#9186a1106fe57e01ce720a50ceb5864f">inepnakeff</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">IN Endpoint HAK Effective mask. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondiepint__data.html#de84fb009990e97bfa46f825d5358429">emptyintr</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">IN Endpoint HAK Effective mask. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondiepint__data.html#90d0e6a99275eccd4a50f62644de9152">txfifoundrn</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondiepint__data.html#2530c984ae3ebda73405d98080d8a57b">bna</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">BNA Interrupt mask. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondiepint__data.html#ba6d7c79905ec53a74a9db0bac336986">reserved10_12</a>:3</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondiepint__data.html#3ade814b2bef3085bb6fa32e94ea1aac">nak</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">BNA Interrupt mask. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondiepint__data.html#6fcd49001dc57506b9b1bbd74b4cb360">reserved14_31</a>:18</td></tr>
+
+<tr><td class="memItemLeft" nowrap valign="top">}&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniondiepint__data.html#48d2a745e0ec983a47b35b0428b0437d">b</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">register bits <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This union represents the bit fields in the Device IN EP Interrupt Register and the Device IN EP Common Mask Register. 
+<p>
+<ul>
+<li>Read the register into the <em>d32</em> member then set/clear the bits using the <em>b</em>it elements. </li></ul>
+
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01030">1030</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr>The documentation for this union was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/uniondoepint__data.html b/drivers/usb/host/dwc_otg/doc/html/uniondoepint__data.html
new file mode 100644
index 000000000000..cfa88a4d89c9
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/uniondoepint__data.html
@@ -0,0 +1,98 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: doepint_data Union Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>doepint_data Union Reference</h1><!-- doxytag: class="doepint_data" -->This union represents the bit fields in the Device OUT EP Interrupt Registerand Device OUT EP Common Interrupt Mask Register.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="94f8c8fc116b430565f9322e3621b3a5"></a><!-- doxytag: member="doepint_data::d32" ref="94f8c8fc116b430565f9322e3621b3a5" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniondoepint__data.html#94f8c8fc116b430565f9322e3621b3a5">d32</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">raw register data <br></td></tr>
+<tr><td class="memItemLeft" nowrap><a class="anchor" name="9e966d9f85589f278dc2c0d0c7833856"></a><!-- doxytag: member="doepint_data::b" ref="9e966d9f85589f278dc2c0d0c7833856" args="" -->
+struct {</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondoepint__data.html#341f7ffa5a9da7f6b1e09e9f4cc516a3">xfercompl</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Transfer complete. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondoepint__data.html#8a263ddc3ab9080b8c2e02ccead0c983">epdisabled</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Endpoint disable. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondoepint__data.html#cdfedbad6643d94271e91e135485a68d">ahberr</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">AHB Error. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondoepint__data.html#b286d1b76f09a9122aca23e430b63dc8">setup</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Setup Phase Done (contorl EPs). <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondoepint__data.html#3f02a0e998438229ec34bb1a8c1f4192">outtknepdis</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">OUT Token Received when Endpoint Disabled. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondoepint__data.html#038fca8f1c03d7cfe323caa4f8bda126">stsphsercvd</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondoepint__data.html#84e49d0a3324691b004bedc6af146747">back2backsetup</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Back-to-Back SETUP Packets Received. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondoepint__data.html#97829cea3541ebb1fb07dd5b24f0d415">reserved7</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondoepint__data.html#dc9d4f243e80cd6796fcc334498fa4cc">outpkterr</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">OUT packet Error. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondoepint__data.html#e68e77d553158195b16a790012f9627d">bna</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">BNA Interrupt. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondoepint__data.html#f01b0c085f14ead4c6fd5b1eafdcd497">reserved10</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondoepint__data.html#0c8fc4f5245a9874c0c3b61d1c6f719d">pktdrpsts</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Packet Drop Status. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondoepint__data.html#c555371bda41092d89992523563dadbb">babble</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Babble Interrupt. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondoepint__data.html#2ac99fbbb1bcf135d5db41e096e8b95b">nak</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">NAK Interrupt. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondoepint__data.html#f35ad8ba20b8941b6ad00dc75586454f">nyet</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">NYET Interrupt. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondoepint__data.html#d5fb6ae977f62553cdc355128399468a">reserved15_31</a>:17</td></tr>
+
+<tr><td class="memItemLeft" nowrap valign="top">}&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniondoepint__data.html#9e966d9f85589f278dc2c0d0c7833856">b</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">register bits <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This union represents the bit fields in the Device OUT EP Interrupt Registerand Device OUT EP Common Interrupt Mask Register. 
+<p>
+<ul>
+<li>Read the register into the <em>d32</em> member then set/clear the bits using the <em>b</em>it elements. </li></ul>
+
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01078">1078</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr>The documentation for this union was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/uniondsts__data.html b/drivers/usb/host/dwc_otg/doc/html/uniondsts__data.html
new file mode 100644
index 000000000000..f2ac7549c180
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/uniondsts__data.html
@@ -0,0 +1,68 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dsts_data Union Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>dsts_data Union Reference</h1><!-- doxytag: class="dsts_data" -->This union represents the bit fields in the Device Status Register.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="0f126daef735b142b06dbc4cdbe13814"></a><!-- doxytag: member="dsts_data::d32" ref="0f126daef735b142b06dbc4cdbe13814" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniondsts__data.html#0f126daef735b142b06dbc4cdbe13814">d32</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">raw register data <br></td></tr>
+<tr><td class="memItemLeft" nowrap><a class="anchor" name="4066fcedb7ac9a88e47aa1b2df0e89ee"></a><!-- doxytag: member="dsts_data::b" ref="4066fcedb7ac9a88e47aa1b2df0e89ee" args="" -->
+struct {</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondsts__data.html#4c7cd8ee3877701268846b0b02ac3d97">suspsts</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Suspend Status. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondsts__data.html#f918f3d04b026687af3e1953f5c79fea">enumspd</a>:2</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Enumerated Speed. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondsts__data.html#fc57a31e440fcf11b233c8c208df83be">errticerr</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Erratic Error. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondsts__data.html#5d3df4c5b52ea3e0cf3311d64ae6a05d">reserved4_7</a>:4</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondsts__data.html#5a81ac4848c859cbf7d494dc345a0ce8">soffn</a>:14</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Frame or Microframe Number of the received SOF. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondsts__data.html#6cf6e0bdb54164703f46ac1ac7258c38">reserved22_31</a>:10</td></tr>
+
+<tr><td class="memItemLeft" nowrap valign="top">}&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniondsts__data.html#4066fcedb7ac9a88e47aa1b2df0e89ee">b</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">register bits <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This union represents the bit fields in the Device Status Register. 
+<p>
+Read the register into the <em>d32</em> member then set/clear the bits using the <em>b</em>it elements. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01001">1001</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr>The documentation for this union was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/uniondthrctl__data.html b/drivers/usb/host/dwc_otg/doc/html/uniondthrctl__data.html
new file mode 100644
index 000000000000..5c7730a715cf
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/uniondthrctl__data.html
@@ -0,0 +1,178 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dthrctl_data Union Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>dthrctl_data Union Reference</h1><!-- doxytag: class="dthrctl_data" -->This union represents Threshold control Register<ul>
+<li>Read and write the register into the <em>d32</em> member. </li></ul>
+ 
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="f66c52fe9278bb6ed52c811ddbed16a5"></a><!-- doxytag: member="dthrctl_data::d32" ref="f66c52fe9278bb6ed52c811ddbed16a5" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniondthrctl__data.html#f66c52fe9278bb6ed52c811ddbed16a5">d32</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">raw register data <br></td></tr>
+<tr><td class="memItemLeft" nowrap><a class="anchor" name="298be6991ca44e5e1ca558471789d33f"></a><!-- doxytag: member="dthrctl_data::b" ref="298be6991ca44e5e1ca558471789d33f" args="" -->
+struct {</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondthrctl__data.html#9b9e309f454fb10621cbaeafe068af47">non_iso_thr_en</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">non ISO Tx Thr.  <a href="#2452ada2f389647f30e51c517323f509"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondthrctl__data.html#f69727f09d4443c01038ba7b163814f8">iso_thr_en</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">ISO Tx Thr.  <a href="#321e3dfd9ab0967a6ea4152efe4c29a6"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondthrctl__data.html#75959c97b938bf99faa602c933938340">tx_thr_len</a>:9</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Tx Thr.  <a href="#242f2cc3f63a55d7f1db69a47ccf082c"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondthrctl__data.html#00bbf39ee16616cc14410549c1e97c45">ahb_thr_ratio</a>:2</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">AHB Threshold ratio. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondthrctl__data.html#a9f51dc49f7e07a49dc8fad22699fa6c">reserved13_15</a>:3</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Reserved. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondthrctl__data.html#0a73132b4e481b250e1b5f533b807bcb">rx_thr_en</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Rx Thr.  <a href="#d90f4495ca8364ebff6667b6ed16113a"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondthrctl__data.html#210370ba2134a296e1c1dcc8b2f05461">rx_thr_len</a>:9</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Rx Thr.  <a href="#7e94fbb83bd3fa7cd87ae94728a46461"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondthrctl__data.html#79c053fcb32c8fdceffebf8dda9f3785">reserved26_31</a>:6</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Reserved. <br></td></tr>
+<tr><td class="memItemLeft" nowrap valign="top">}&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniondthrctl__data.html#298be6991ca44e5e1ca558471789d33f">b</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">register bits <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This union represents Threshold control Register<ul>
+<li>Read and write the register into the <em>d32</em> member. </li></ul>
+
+<p>
+<ul>
+<li>READ-WRITABLE Register </li></ul>
+
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01205">1205</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr><h2>Field Documentation</h2>
+<a class="anchor" name="9b9e309f454fb10621cbaeafe068af47"></a><!-- doxytag: member="dthrctl_data::non_iso_thr_en" ref="9b9e309f454fb10621cbaeafe068af47" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">unsigned <a class="el" href="uniondthrctl__data.html#9b9e309f454fb10621cbaeafe068af47">dthrctl_data::non_iso_thr_en</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+non ISO Tx Thr. 
+<p>
+Enable 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01211">1211</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="f69727f09d4443c01038ba7b163814f8"></a><!-- doxytag: member="dthrctl_data::iso_thr_en" ref="f69727f09d4443c01038ba7b163814f8" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">unsigned <a class="el" href="uniondthrctl__data.html#f69727f09d4443c01038ba7b163814f8">dthrctl_data::iso_thr_en</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+ISO Tx Thr. 
+<p>
+Enable 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01213">1213</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="75959c97b938bf99faa602c933938340"></a><!-- doxytag: member="dthrctl_data::tx_thr_len" ref="75959c97b938bf99faa602c933938340" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">unsigned <a class="el" href="uniondthrctl__data.html#75959c97b938bf99faa602c933938340">dthrctl_data::tx_thr_len</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Tx Thr. 
+<p>
+Length 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01215">1215</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="0a73132b4e481b250e1b5f533b807bcb"></a><!-- doxytag: member="dthrctl_data::rx_thr_en" ref="0a73132b4e481b250e1b5f533b807bcb" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">unsigned <a class="el" href="uniondthrctl__data.html#0a73132b4e481b250e1b5f533b807bcb">dthrctl_data::rx_thr_en</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Rx Thr. 
+<p>
+Enable 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01221">1221</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="210370ba2134a296e1c1dcc8b2f05461"></a><!-- doxytag: member="dthrctl_data::rx_thr_len" ref="210370ba2134a296e1c1dcc8b2f05461" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">unsigned <a class="el" href="uniondthrctl__data.html#210370ba2134a296e1c1dcc8b2f05461">dthrctl_data::rx_thr_len</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Rx Thr. 
+<p>
+Length 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01223">1223</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<hr>The documentation for this union was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/uniondtknq1__data.html b/drivers/usb/host/dwc_otg/doc/html/uniondtknq1__data.html
new file mode 100644
index 000000000000..781f04f516e9
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/uniondtknq1__data.html
@@ -0,0 +1,86 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dtknq1_data Union Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>dtknq1_data Union Reference</h1><!-- doxytag: class="dtknq1_data" -->This union represents the bit fields in the Device IN Token Queue Read Registers.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="86015789f75da8cd507db3766fe93fef"></a><!-- doxytag: member="dtknq1_data::d32" ref="86015789f75da8cd507db3766fe93fef" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniondtknq1__data.html#86015789f75da8cd507db3766fe93fef">d32</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">raw register data <br></td></tr>
+<tr><td class="memItemLeft" nowrap><a class="anchor" name="fffe59f9a5f7cdf1ece03cf43caff69d"></a><!-- doxytag: member="dtknq1_data::b" ref="fffe59f9a5f7cdf1ece03cf43caff69d" args="" -->
+struct {</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondtknq1__data.html#33b25ddce8afe3ac2d8736f42133c284">intknwptr</a>:5</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">In Token Queue Write Pointer. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondtknq1__data.html#08d3442422c47ce894571c92470195c9">reserved05_06</a>:2</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Reserved. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondtknq1__data.html#9ae9021519e7fa501c86093c7718dbb4">wrap_bit</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">write pointer has wrapped. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondtknq1__data.html#b35b4b7cfebfe54904ac0d74bb771825">epnums0_5</a>:24</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">EP Numbers of IN Tokens 0 .  <a href="#d966ef428333fc35a7cc22df975c9ce7"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap valign="top">}&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniondtknq1__data.html#fffe59f9a5f7cdf1ece03cf43caff69d">b</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">register bits <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This union represents the bit fields in the Device IN Token Queue Read Registers. 
+<p>
+<ul>
+<li>Read the register into the <em>d32</em> member.</li><li>READ-ONLY Register </li></ul>
+
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01184">1184</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr><h2>Field Documentation</h2>
+<a class="anchor" name="b35b4b7cfebfe54904ac0d74bb771825"></a><!-- doxytag: member="dtknq1_data::epnums0_5" ref="b35b4b7cfebfe54904ac0d74bb771825" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">unsigned <a class="el" href="uniondtknq1__data.html#b35b4b7cfebfe54904ac0d74bb771825">dtknq1_data::epnums0_5</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+EP Numbers of IN Tokens 0 . 
+<p>
+.. 4 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01196">1196</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<hr>The documentation for this union was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/uniondtxfsts__data.html b/drivers/usb/host/dwc_otg/doc/html/uniondtxfsts__data.html
new file mode 100644
index 000000000000..28f2157bf056
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/uniondtxfsts__data.html
@@ -0,0 +1,56 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dtxfsts_data Union Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>dtxfsts_data Union Reference</h1><!-- doxytag: class="dtxfsts_data" -->This union represents the bit fields in the Transmit FIFO Status Register (DTXFSTS).  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="684b8a9ccf83a5807e9bb3491c662c39"></a><!-- doxytag: member="dtxfsts_data::d32" ref="684b8a9ccf83a5807e9bb3491c662c39" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniondtxfsts__data.html#684b8a9ccf83a5807e9bb3491c662c39">d32</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">raw register data <br></td></tr>
+<tr><td class="memItemLeft" nowrap><a class="anchor" name="168f673549aad11d0d9fdc06ee6c5480"></a><!-- doxytag: member="dtxfsts_data::b" ref="168f673549aad11d0d9fdc06ee6c5480" args="" -->
+struct {</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondtxfsts__data.html#83db0e2dbe071694f549a383b7037b3b">txfspcavail</a>:16</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondtxfsts__data.html#7bf9687e9efb791c8d3da9e50fde6096">reserved</a>:16</td></tr>
+
+<tr><td class="memItemLeft" nowrap valign="top">}&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniondtxfsts__data.html#168f673549aad11d0d9fdc06ee6c5480">b</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">register bits <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This union represents the bit fields in the Transmit FIFO Status Register (DTXFSTS). 
+<p>
+Read the register into the <em>d32</em> element then read out the bits using the <em>b</em>it elements. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00697">697</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr>The documentation for this union was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html b/drivers/usb/host/dwc_otg/doc/html/uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html
new file mode 100644
index 000000000000..b04986e7aae1
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html
@@ -0,0 +1,66 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd::dwc_otg_hcd_internal_flags Union Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<div class="nav">
+<a class="el" href="structdwc__otg__hcd.html">dwc_otg_hcd</a>::<a class="el" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html">dwc_otg_hcd_internal_flags</a></div>
+<h1>dwc_otg_hcd::dwc_otg_hcd_internal_flags Union Reference</h1><!-- doxytag: class="dwc_otg_hcd::dwc_otg_hcd_internal_flags" -->Internal DWC HCD Flags.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__hcd_8h-source.html">dwc_otg_hcd.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="95ad2033c30d79c28ffcfa6df44af1d5"></a><!-- doxytag: member="dwc_otg_hcd::dwc_otg_hcd_internal_flags::d32" ref="95ad2033c30d79c28ffcfa6df44af1d5" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#95ad2033c30d79c28ffcfa6df44af1d5">d32</a></td></tr>
+
+<tr><td class="memItemLeft" nowrap><a class="anchor" name="76f573861d9316238ded198c58c228c7"></a><!-- doxytag: member="dwc_otg_hcd::dwc_otg_hcd_internal_flags::b" ref="76f573861d9316238ded198c58c228c7" args="" -->
+struct {</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#cd31ac4b9658265e90773448f354f0e1">port_connect_status_change</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#9314ac02ed140807687793b512f78c63">port_connect_status</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#d0d63f32ed35315e8a02549521fb386e">port_reset_change</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#d222ae08372109a312f6649f77b650e8">port_enable_change</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#2a6e323cb4c01153aff1adc6269c74c7">port_suspend_change</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#bc96cf12e2bc5b61ce05f15ae3297bd6">port_over_current_change</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#1900375ccea165f0efc40725f507a0bf">port_l1_change</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html#763f58f20d7103f86b4f40f37f501f33">reserved</a>:26</td></tr>
+
+<tr><td class="memItemLeft" nowrap valign="top">}&nbsp;</td><td class="memItemRight" valign="bottom"><b>b</b></td></tr>
+
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+Internal DWC HCD Flags. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__hcd_8h-source.html#l00380">380</a> of file <a class="el" href="dwc__otg__hcd_8h-source.html">dwc_otg_hcd.h</a>.<hr>The documentation for this union was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__hcd_8h-source.html">dwc_otg_hcd.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/unionfifosize__data.html b/drivers/usb/host/dwc_otg/doc/html/unionfifosize__data.html
new file mode 100644
index 000000000000..ea7c6bb1ed81
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/unionfifosize__data.html
@@ -0,0 +1,56 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: fifosize_data Union Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>fifosize_data Union Reference</h1><!-- doxytag: class="fifosize_data" -->This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ, GNPTXFSIZ, DPTXFSIZn, DIEPTXFn).  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="937e01b91f0a60a5aa9f6a4eaf6ce661"></a><!-- doxytag: member="fifosize_data::d32" ref="937e01b91f0a60a5aa9f6a4eaf6ce661" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionfifosize__data.html#937e01b91f0a60a5aa9f6a4eaf6ce661">d32</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">raw register data <br></td></tr>
+<tr><td class="memItemLeft" nowrap><a class="anchor" name="4f0c71e88cc54c4efa4cd4ff43334c51"></a><!-- doxytag: member="fifosize_data::b" ref="4f0c71e88cc54c4efa4cd4ff43334c51" args="" -->
+struct {</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionfifosize__data.html#26d78332a532cf9c0337c89edbff5f1b">startaddr</a>:16</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionfifosize__data.html#48c08d73da4d2d16d4320b93beb5ba8b">depth</a>:16</td></tr>
+
+<tr><td class="memItemLeft" nowrap valign="top">}&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionfifosize__data.html#4f0c71e88cc54c4efa4cd4ff43334c51">b</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">register bits <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ, GNPTXFSIZ, DPTXFSIZn, DIEPTXFn). 
+<p>
+Read the register into the <em>d32</em> element then read out the bits using the <em>b</em>it elements. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00651">651</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr>The documentation for this union was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/uniongahbcfg__data.html b/drivers/usb/host/dwc_otg/doc/html/uniongahbcfg__data.html
new file mode 100644
index 000000000000..2582c0c5c9c0
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/uniongahbcfg__data.html
@@ -0,0 +1,66 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: gahbcfg_data Union Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>gahbcfg_data Union Reference</h1><!-- doxytag: class="gahbcfg_data" -->This union represents the bit fields of the Core AHB Configuration Register (GAHBCFG).  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="2532b75f838946009af8806c924f0c08"></a><!-- doxytag: member="gahbcfg_data::d32" ref="2532b75f838946009af8806c924f0c08" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniongahbcfg__data.html#2532b75f838946009af8806c924f0c08">d32</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">raw register data <br></td></tr>
+<tr><td class="memItemLeft" nowrap><a class="anchor" name="aa9726048597c5bb54ea38eda976e1a4"></a><!-- doxytag: member="gahbcfg_data::b" ref="aa9726048597c5bb54ea38eda976e1a4" args="" -->
+struct {</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongahbcfg__data.html#f75957f35be7ecd70616f5d0bcfb1e51">glblintrmsk</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongahbcfg__data.html#b8f9a94aa77eb5abc379c438bf68f3d0">hburstlen</a>:4</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongahbcfg__data.html#f39c07c45326af38a267b0e308496b5c">dmaenable</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongahbcfg__data.html#dbd9a753c076249c2d9e1c6d917194e4">reserved</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongahbcfg__data.html#00758ec639d12cc80fd98b1a6526c454">nptxfemplvl_txfemplvl</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongahbcfg__data.html#e45b68a6e6e681e58d70fd8e70f9542f">ptxfemplvl</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongahbcfg__data.html#f5fcb22471add360aa70f3512dab7ecd">reserved9_31</a>:23</td></tr>
+
+<tr><td class="memItemLeft" nowrap valign="top">}&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniongahbcfg__data.html#aa9726048597c5bb54ea38eda976e1a4">b</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">register bits <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This union represents the bit fields of the Core AHB Configuration Register (GAHBCFG). 
+<p>
+Set/clear the bits using the bit fields then write the <em>d32</em> value to the register. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00216">216</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr>The documentation for this union was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/uniongi2cctl__data.html b/drivers/usb/host/dwc_otg/doc/html/uniongi2cctl__data.html
new file mode 100644
index 000000000000..6a4150c84d2b
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/uniongi2cctl__data.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: gi2cctl_data Union Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>gi2cctl_data Union Reference</h1><!-- doxytag: class="gi2cctl_data" -->This union represents the bit fields in the I2C Control Register (I2CCTL).  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="97e9ae4e52d9bd9370027b5da5f65787"></a><!-- doxytag: member="gi2cctl_data::d32" ref="97e9ae4e52d9bd9370027b5da5f65787" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniongi2cctl__data.html#97e9ae4e52d9bd9370027b5da5f65787">d32</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">raw register data <br></td></tr>
+<tr><td class="memItemLeft" nowrap><a class="anchor" name="5cd3b77fc770fc81b9cf9330cac214a8"></a><!-- doxytag: member="gi2cctl_data::b" ref="5cd3b77fc770fc81b9cf9330cac214a8" args="" -->
+struct {</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongi2cctl__data.html#7324a24ede0ab8ddcd9fbb1c5c558ff5">rwdata</a>:8</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongi2cctl__data.html#9c6113a7da88fc158f2ffabe4b0bfcb6">regaddr</a>:8</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongi2cctl__data.html#5641294f472040bc6c4f7e70e84500f0">addr</a>:7</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongi2cctl__data.html#6a14bacfd6c36d22071a79cb0fb53e77">i2cen</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongi2cctl__data.html#58c5fecd71f1bf68dc3e6939e5b56335">ack</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongi2cctl__data.html#96fcad9de22d851a74f900458c2ac325">i2csuspctl</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongi2cctl__data.html#78d1a33a0a81bbca4e89e2f578b27ca2">i2cdevaddr</a>:2</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongi2cctl__data.html#208c2f1fe8cff50b174028b7573ae03f">reserved</a>:2</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongi2cctl__data.html#afc04461ec8ca28e870cb2374b862961">rw</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongi2cctl__data.html#b28daedf73bcb4d651f8fbc03bb69778">bsydne</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap valign="top">}&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniongi2cctl__data.html#5cd3b77fc770fc81b9cf9330cac214a8">b</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">register bits <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This union represents the bit fields in the I2C Control Register (I2CCTL). 
+<p>
+Read the register into the <em>d32</em> element then read out the bits using the <em>b</em>it elements. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00712">712</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr>The documentation for this union was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/uniongintmsk__data.html b/drivers/usb/host/dwc_otg/doc/html/uniongintmsk__data.html
new file mode 100644
index 000000000000..fbabbb9d3538
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/uniongintmsk__data.html
@@ -0,0 +1,114 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: gintmsk_data Union Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>gintmsk_data Union Reference</h1><!-- doxytag: class="gintmsk_data" -->This union represents the bit fields of the Core Interrupt Mask Register (GINTMSK).  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="9c007bd53320f30b3cb06eb56b96673d"></a><!-- doxytag: member="gintmsk_data::d32" ref="9c007bd53320f30b3cb06eb56b96673d" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniongintmsk__data.html#9c007bd53320f30b3cb06eb56b96673d">d32</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">raw register data <br></td></tr>
+<tr><td class="memItemLeft" nowrap><a class="anchor" name="6f9ac3edb378165675a3203f555aa8d6"></a><!-- doxytag: member="gintmsk_data::b" ref="6f9ac3edb378165675a3203f555aa8d6" args="" -->
+struct {</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintmsk__data.html#74efe8733ca57d2b6147f8d42178c95c">reserved0</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintmsk__data.html#f62315fe9de8bb3bc371cb0a51927496">modemismatch</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintmsk__data.html#6c9d578034af4f2ca08447fdac22ff88">otgintr</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintmsk__data.html#d9cb28e92090a5da3c00d35768d90c82">sofintr</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintmsk__data.html#83db45f92a3a692d79199e1a850c2a62">rxstsqlvl</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintmsk__data.html#2c395e7bef31a4d9b2d1a3257c601be4">nptxfempty</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintmsk__data.html#83a6fb180ef8b18faf8d02ba8b50c841">ginnakeff</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintmsk__data.html#1a47902a93203910433a35fab3f5b8a1">goutnakeff</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintmsk__data.html#b82d0335e1b637612cc3d8442d9e52cc">reserved8</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintmsk__data.html#92dd84dd80b06e949668f85e6b6b7086">i2cintr</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintmsk__data.html#0c455b6461081720584a8acc4e0e18a5">erlysuspend</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintmsk__data.html#3b93f1ae00dcd1dcc4d6d19547f26b56">usbsuspend</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintmsk__data.html#de79426e6a5436e34cf4b1ac42a72ee6">usbreset</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintmsk__data.html#895f1c1537debec62da4fd248249859c">enumdone</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintmsk__data.html#3a0a75b129ccdaed6d98d1982b374d52">isooutdrop</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintmsk__data.html#aeb61a24f3c50caacfb8fe523c85768a">eopframe</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintmsk__data.html#e5f7668978b7c4898dccda363be492ae">reserved16</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintmsk__data.html#3a21d0006e144647b43ef910b9183da9">epmismatch</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintmsk__data.html#bcae4c9dd3d0f153b379dfbc6c830fc5">inepintr</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintmsk__data.html#d48fe24e3e91bc1bcbc1c790c1b67f96">outepintr</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintmsk__data.html#3f9eeb4c73291b7943b7187ba34c90f4">incomplisoin</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintmsk__data.html#c63c107070bd7623766e39cd06ec7c97">incomplisoout</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintmsk__data.html#1cc5065ff41bfe410b53631392f0e2a7">reserved22_23</a>:2</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintmsk__data.html#c907c60cbc7b157e730b053b40f4a2b3">portintr</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintmsk__data.html#3a4c193d8ff48291809dcd3ccb7c0585">hcintr</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintmsk__data.html#3b52444894e041c660c146af2178272f">ptxfempty</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintmsk__data.html#24f9f89b33866c5dc7b16588bc94e103">lpmtranrcvd</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintmsk__data.html#ade723f4f136cfa884e5bf536d913f14">conidstschng</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintmsk__data.html#0ff313bfc712a2f3d71bc1a5f1a17ce2">disconnect</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintmsk__data.html#aabb586a72e2a76982bfaa780e482212">sessreqintr</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintmsk__data.html#d3cde0fd62a006ec3f5db615f1e62da5">wkupintr</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap valign="top">}&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniongintmsk__data.html#6f9ac3edb378165675a3203f555aa8d6">b</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">register bits <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This union represents the bit fields of the Core Interrupt Mask Register (GINTMSK). 
+<p>
+Set/clear the bits using the bit fields then write the <em>d32</em> value to the register. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00512">512</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr>The documentation for this union was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/uniongintsts__data.html b/drivers/usb/host/dwc_otg/doc/html/uniongintsts__data.html
new file mode 100644
index 000000000000..059b029df50e
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/uniongintsts__data.html
@@ -0,0 +1,114 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: gintsts_data Union Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>gintsts_data Union Reference</h1><!-- doxytag: class="gintsts_data" -->This union represents the bit fields of the Core Interrupt Register (GINTSTS).  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="379f34f5a95628b735e3a965f9cea12d"></a><!-- doxytag: member="gintsts_data::d32" ref="379f34f5a95628b735e3a965f9cea12d" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniongintsts__data.html#379f34f5a95628b735e3a965f9cea12d">d32</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">raw register data <br></td></tr>
+<tr><td class="memItemLeft" nowrap><a class="anchor" name="781da5558468e5dbdc93ae95e4cb872e"></a><!-- doxytag: member="gintsts_data::b" ref="781da5558468e5dbdc93ae95e4cb872e" args="" -->
+struct {</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintsts__data.html#f0815c8bea0a37c98b12a08481b2980c">curmode</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintsts__data.html#5fda463a80eb6927b2b875d64e8a0753">modemismatch</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintsts__data.html#7934c11c40b0b60137edbdaa2be45542">otgintr</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintsts__data.html#3f6ba377d6b1449884bb4da1b155c61b">sofintr</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintsts__data.html#7595576956c3a0ced9ea387880943012">rxstsqlvl</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintsts__data.html#adebf5ff5bdf69a2bcf0bd4b2ba55ef4">nptxfempty</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintsts__data.html#15a2e362768704ab6143fea33fc8755b">ginnakeff</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintsts__data.html#5fd87ed0462f444df968567f310488f7">goutnakeff</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintsts__data.html#704fa166643640f4c9b6c6de037d860a">reserved8</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintsts__data.html#2e8bd51ad285fd46db48f9fb5bbb7993">i2cintr</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintsts__data.html#2659c4ea7b295a089ee498b21b44992b">erlysuspend</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintsts__data.html#de67a7536cdb9305e24f05d771708bce">usbsuspend</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintsts__data.html#76926be659d963c79dbcec91e25ce8ed">usbreset</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintsts__data.html#84e707787b50ee3867786c8e0995f41e">enumdone</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintsts__data.html#e6e931e1d6226dc110a98cd42c9a8e5f">isooutdrop</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintsts__data.html#a731c93eb9e131fadde92da363a85527">eopframe</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintsts__data.html#912b165c3b774baedd294b678df9c2c0">intokenrx</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintsts__data.html#c30e01457b826afc318e5d76e9dfdded">epmismatch</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintsts__data.html#e4e48a2a194cf95d934800a85c12784f">inepint</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintsts__data.html#58c08d29fa4b120748eb01b0d989facf">outepintr</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintsts__data.html#6a2b4a287af4632cec2207fe6fb91e86">incomplisoin</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintsts__data.html#519e2237cad3f43ebb7665e8d24c0180">incomplisoout</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintsts__data.html#dbb68c65fa6a899acf2bf74dac94790e">reserved22_23</a>:2</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintsts__data.html#7490e48c2c93d20c182f00161f18b8e5">portintr</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintsts__data.html#e02f1a50b20ed1c4248fd76e155147e8">hcintr</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintsts__data.html#54ed752629e9b8916507beca28d76162">ptxfempty</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintsts__data.html#50e73e91df681c835de50f8276058829">lpmtranrcvd</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintsts__data.html#86b8b53e53486db96a8faf6307c248df">conidstschng</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintsts__data.html#45d8d681263dcfc7c2b6cf30ee689f28">disconnect</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintsts__data.html#c8b14c042daab677d0c4ae691d573995">sessreqintr</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongintsts__data.html#d2e845fd68f2e8abe6b7445dbde9d2a4">wkupintr</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap valign="top">}&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniongintsts__data.html#781da5558468e5dbdc93ae95e4cb872e">b</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">register bits <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This union represents the bit fields of the Core Interrupt Register (GINTSTS). 
+<p>
+Set/clear the bits using the bit fields then write the <em>d32</em> value to the register. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00555">555</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr>The documentation for this union was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/unionglpmctl__data.html b/drivers/usb/host/dwc_otg/doc/html/unionglpmctl__data.html
new file mode 100644
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--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/unionglpmctl__data.html
@@ -0,0 +1,178 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: glpmctl_data Union Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>glpmctl_data Union Reference</h1><!-- doxytag: class="glpmctl_data" -->This union represents the bit fields of the Core LPM Configuration Register (GLPMCFG).  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="cd41461734ff898209bfb64057ef2eb8"></a><!-- doxytag: member="glpmctl_data::d32" ref="cd41461734ff898209bfb64057ef2eb8" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionglpmctl__data.html#cd41461734ff898209bfb64057ef2eb8">d32</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">raw register data <br></td></tr>
+<tr><td class="memItemLeft" nowrap><a class="anchor" name="bd3cc34c338226ff1cd89448f7590ff1"></a><!-- doxytag: member="glpmctl_data::b" ref="bd3cc34c338226ff1cd89448f7590ff1" args="" -->
+struct {</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionglpmctl__data.html#cf0a4cfcd158e41eb3811048e723890f">lpm_cap_en</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">LPM-Capable (LPMCap) (Device and Host) The application uses this bit to control the DWC_otg core LPM capabilities. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionglpmctl__data.html#1898203022af680f08036de89e86e4b0">appl_resp</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">LPM response programmed by application (AppL1Res) (Device) Handshake response to LPM token pre-programmed by device application software. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionglpmctl__data.html#176b788935d1952606f523f2718b3512">hird</a>:4</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Host Initiated Resume Duration (HIRD) (Device and Host) In Host mode this field indicates the value of HIRD to be sent in an LPM transaction.  <a href="#84f99e6824e244a528210f671a0889e8"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionglpmctl__data.html#60a9c2e233e3ee15a80ae80b27d09f8b">rem_wkup_en</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">RemoteWakeEnable (bRemoteWake) (Device and Host) In Host mode this bit indicates the value of remote wake up to be sent in wIndex field of LPM transaction.  <a href="#e47b43fe162aa51e6dc6940f9689308c"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionglpmctl__data.html#63e912a05b8d29872b92263ca616fec8">en_utmi_sleep</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Enable utmi_sleep_n (EnblSlpM) (Device and Host) The application uses this bit to control the utmi_sleep_n assertion to the PHY when in L1 state. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionglpmctl__data.html#e2ceea4bfe468c7b3c800235d7ffd5d2">hird_thres</a>:5</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">HIRD Threshold (HIRD_Thres) (Device and Host). <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionglpmctl__data.html#752c00118919fce173804931b058c5a8">lpm_resp</a>:2</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">LPM Response (CoreL1Res) (Device and Host) In Host mode this bit contains handsake response to LPM transaction.  <a href="#0ca5be418312e033a5efe1e463ce895c"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionglpmctl__data.html#241ff25a215f16ac29b3bb6d9f4943ed">prt_sleep_sts</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Port Sleep Status (SlpSts) (Device and Host) This bit is set as long as a Sleep condition is present on the USB bus. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionglpmctl__data.html#3b87473445c87d173f350828a60cacd8">sleep_state_resumeok</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Sleep State Resume OK (L1ResumeOK) (Device and Host) Indicates that the application or host can start resume from Sleep state. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionglpmctl__data.html#7e6bb2a40d4e0bdfed6f868b1f670235">lpm_chan_index</a>:4</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">LPM channel Index (LPM_Chnl_Indx) (Host) The channel number on which the LPM transaction has to be applied while sending an LPM transaction to the local device. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionglpmctl__data.html#be75ed525bcfe231cd9bda6a1b8594f6">retry_count</a>:3</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">LPM Retry Count (LPM_Retry_Cnt) (Host) Number host retries that would be performed if the device response was not valid response. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionglpmctl__data.html#0651e486c5502489b2cac633bb00c78e">send_lpm</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Send LPM Transaction (SndLPM) (Host) When set by application software, an LPM transaction containing two tokens is sent. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionglpmctl__data.html#67ddd4b3576e04a06d5fff707c8bbf18">retry_count_sts</a>:3</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">LPM Retry status (LPM_RetryCnt_Sts) (Host) Number of LPM Host Retries still remaining to be transmitted for the current LPM sequence. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionglpmctl__data.html#b0b1d669c4161e9ffb1454d85bd243d2">reserved28_29</a>:2</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionglpmctl__data.html#76c64ead46647c39aa76edebf2f63444">hsic_connect</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">In host mode once this bit is set, the host configures to drive the HSIC Idle state on the bus.  <a href="#15102bf1c6f3725c7bd6ec19d5fb6593"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionglpmctl__data.html#f664636955d9476647937d13d48f068e">inv_sel_hsic</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">This bit overrides and functionally inverts the if_select_hsic input port signal. <br></td></tr>
+<tr><td class="memItemLeft" nowrap valign="top">}&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionglpmctl__data.html#bd3cc34c338226ff1cd89448f7590ff1">b</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">register bits <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This union represents the bit fields of the Core LPM Configuration Register (GLPMCFG). 
+<p>
+Set the bits using bit fields then write the <em>d32</em> value to the register. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00283">283</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr><h2>Field Documentation</h2>
+<a class="anchor" name="176b788935d1952606f523f2718b3512"></a><!-- doxytag: member="glpmctl_data::hird" ref="176b788935d1952606f523f2718b3512" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">unsigned <a class="el" href="unionglpmctl__data.html#176b788935d1952606f523f2718b3512">glpmctl_data::hird</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Host Initiated Resume Duration (HIRD) (Device and Host) In Host mode this field indicates the value of HIRD to be sent in an LPM transaction. 
+<p>
+In Device mode this field is updated with the Received LPM Token HIRD bmAttribute when an ACK/NYET/STALL response is sent to an LPM transaction. 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00306">306</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="60a9c2e233e3ee15a80ae80b27d09f8b"></a><!-- doxytag: member="glpmctl_data::rem_wkup_en" ref="60a9c2e233e3ee15a80ae80b27d09f8b" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">unsigned <a class="el" href="unionglpmctl__data.html#60a9c2e233e3ee15a80ae80b27d09f8b">glpmctl_data::rem_wkup_en</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+RemoteWakeEnable (bRemoteWake) (Device and Host) In Host mode this bit indicates the value of remote wake up to be sent in wIndex field of LPM transaction. 
+<p>
+In Device mode this field is updated with the Received LPM Token bRemoteWake bmAttribute when an ACK/NYET/STALL response is sent to an LPM transaction. 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00315">315</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="752c00118919fce173804931b058c5a8"></a><!-- doxytag: member="glpmctl_data::lpm_resp" ref="752c00118919fce173804931b058c5a8" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">unsigned <a class="el" href="unionglpmctl__data.html#752c00118919fce173804931b058c5a8">glpmctl_data::lpm_resp</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+LPM Response (CoreL1Res) (Device and Host) In Host mode this bit contains handsake response to LPM transaction. 
+<p>
+In Device mode the response of the core to LPM transaction received is reflected in these two bits.<ul>
+<li>0x0 : ERROR (No handshake response)</li><li>0x1 : STALL</li><li>0x2 : NYET</li><li>0x3 : ACK </li></ul>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00334">334</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="76c64ead46647c39aa76edebf2f63444"></a><!-- doxytag: member="glpmctl_data::hsic_connect" ref="76c64ead46647c39aa76edebf2f63444" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">unsigned <a class="el" href="unionglpmctl__data.html#76c64ead46647c39aa76edebf2f63444">glpmctl_data::hsic_connect</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+In host mode once this bit is set, the host configures to drive the HSIC Idle state on the bus. 
+<p>
+It then waits for the device to initiate the Connect sequence. In device mode once this bit is set, the device waits for the HSIC Idle line state on the bus. Upon receving the Idle line state, it initiates the HSIC Connect sequence. 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00375">375</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<hr>The documentation for this union was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/uniongnptxsts__data.html b/drivers/usb/host/dwc_otg/doc/html/uniongnptxsts__data.html
new file mode 100644
index 000000000000..fb3adeed2070
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/uniongnptxsts__data.html
@@ -0,0 +1,69 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: gnptxsts_data Union Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>gnptxsts_data Union Reference</h1><!-- doxytag: class="gnptxsts_data" -->This union represents the bit fields in the Non-Periodic Transmit FIFO/Queue Status Register (GNPTXSTS).  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="a58b5adbe6bd0344c4f585ef6aba4672"></a><!-- doxytag: member="gnptxsts_data::d32" ref="a58b5adbe6bd0344c4f585ef6aba4672" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniongnptxsts__data.html#a58b5adbe6bd0344c4f585ef6aba4672">d32</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">raw register data <br></td></tr>
+<tr><td class="memItemLeft" nowrap><a class="anchor" name="be1d1adf7b827616ebbbf6bf564c0738"></a><!-- doxytag: member="gnptxsts_data::b" ref="be1d1adf7b827616ebbbf6bf564c0738" args="" -->
+struct {</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongnptxsts__data.html#6c149be246bcf5ca5395f67e67648207">nptxfspcavail</a>:16</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongnptxsts__data.html#634ffd5e84bc422ddef043574d8f0957">nptxqspcavail</a>:8</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongnptxsts__data.html#8aeca3e7350acc25b9c0623eea88bfc3">nptxqtop_terminate</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Top of the Non-Periodic Transmit Request Queue<ul>
+<li>bit 24 - Terminate (Last entry for the selected channel/EP)</li><li>bits 26:25 - Token Type<ul>
+<li>2'b00 - IN/OUT</li><li>2'b01 - Zero Length OUT</li><li>2'b10 - PING/Complete Split</li><li>2'b11 - Channel Halt</li></ul>
+</li><li>bits 30:27 - Channel/EP Number. </li></ul>
+<br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongnptxsts__data.html#7675d024cc57442bd67d63551cb5dfcc">nptxqtop_token</a>:2</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongnptxsts__data.html#6f593581592d2c904db11b39f8275ed9">nptxqtop_chnep</a>:4</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongnptxsts__data.html#035aa5b790dd66e425a77291b849920f">reserved</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap valign="top">}&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniongnptxsts__data.html#be1d1adf7b827616ebbbf6bf564c0738">b</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">register bits <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This union represents the bit fields in the Non-Periodic Transmit FIFO/Queue Status Register (GNPTXSTS). 
+<p>
+Read the register into the <em>d32</em> element then read out the bits using the <em>b</em>it elements. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00667">667</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr>The documentation for this union was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/uniongotgctl__data.html b/drivers/usb/host/dwc_otg/doc/html/uniongotgctl__data.html
new file mode 100644
index 000000000000..d2d4d35497b7
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/uniongotgctl__data.html
@@ -0,0 +1,80 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: gotgctl_data Union Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>gotgctl_data Union Reference</h1><!-- doxytag: class="gotgctl_data" -->This union represents the bit fields of the Core OTG Control and Status Register (GOTGCTL).  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="ebb591ab40ff41f0e06f03a795647d33"></a><!-- doxytag: member="gotgctl_data::d32" ref="ebb591ab40ff41f0e06f03a795647d33" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniongotgctl__data.html#ebb591ab40ff41f0e06f03a795647d33">d32</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">raw register data <br></td></tr>
+<tr><td class="memItemLeft" nowrap><a class="anchor" name="212c81366266e906a188f4dbfadb6dd3"></a><!-- doxytag: member="gotgctl_data::b" ref="212c81366266e906a188f4dbfadb6dd3" args="" -->
+struct {</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongotgctl__data.html#5239dbbb4b31210a35a7104abb688801">sesreqscs</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongotgctl__data.html#c6b0b35d4366f74cf6fe268eda781f06">sesreq</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongotgctl__data.html#8a1159d33534011e702124f11e32346a">reserved2_7</a>:6</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongotgctl__data.html#20b17868fc09a12b163732d5bbc84d8d">hstnegscs</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongotgctl__data.html#08487ecb0860252b73815ee6e0f8eaa3">hnpreq</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongotgctl__data.html#7d45791d3622a59ff43ab248bbb1b2c1">hstsethnpen</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongotgctl__data.html#0058cbee8b53336c28746116301ea796">devhnpen</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongotgctl__data.html#8cdb9c356cb2bd7c08fd03277d018abe">reserved12_15</a>:4</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongotgctl__data.html#777151f3c8c1b3117493aee2cd7a2e5c">conidsts</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongotgctl__data.html#10d4ca93b77030eb791dba2486d337d8">reserved17</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongotgctl__data.html#e16505965a031d2e488a26378a14a834">asesvld</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongotgctl__data.html#69931c3759421d5eb6f91d4c9da4dddd">bsesvld</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongotgctl__data.html#540a9022e5ff38c2a656b8ebd59070cb">currmod</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongotgctl__data.html#c4e3970718da78ebc91f6cf46a2944ae">reserved21_31</a>:11</td></tr>
+
+<tr><td class="memItemLeft" nowrap valign="top">}&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniongotgctl__data.html#212c81366266e906a188f4dbfadb6dd3">b</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">register bits <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This union represents the bit fields of the Core OTG Control and Status Register (GOTGCTL). 
+<p>
+Set the bits using the bit fields then write the <em>d32</em> value to the register. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00152">152</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr>The documentation for this union was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/uniongotgint__data.html b/drivers/usb/host/dwc_otg/doc/html/uniongotgint__data.html
new file mode 100644
index 000000000000..d79e3e1b087c
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/uniongotgint__data.html
@@ -0,0 +1,79 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: gotgint_data Union Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>gotgint_data Union Reference</h1><!-- doxytag: class="gotgint_data" -->This union represents the bit fields of the Core OTG Interrupt Register (GOTGINT).  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="8a343df4fc4e68b802be7629864308e2"></a><!-- doxytag: member="gotgint_data::d32" ref="8a343df4fc4e68b802be7629864308e2" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniongotgint__data.html#8a343df4fc4e68b802be7629864308e2">d32</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">raw register data <br></td></tr>
+<tr><td class="memItemLeft" nowrap><a class="anchor" name="e48c5633608687c8895da201199c2a7c"></a><!-- doxytag: member="gotgint_data::b" ref="e48c5633608687c8895da201199c2a7c" args="" -->
+struct {</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongotgint__data.html#8da0f04fa16cee7d0446e47e9e459df8">reserved0_1</a>:2</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Current Mode. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongotgint__data.html#58a04bef67e26229efe95f12938d18e8">sesenddet</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Session End Detected. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongotgint__data.html#55e5d90b1cbab85d6928246c45d5a14c">reserved3_7</a>:5</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongotgint__data.html#99a56305c7cc48086ef34c15bbc40ca6">sesreqsucstschng</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Session Request Success Status Change. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongotgint__data.html#e41c62fee3da6113b23594cec6fb0c67">hstnegsucstschng</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Host Negotiation Success Status Change. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongotgint__data.html#0bbecd636a8dcdc464880f70de8b8dec">reserver10_16</a>:7</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongotgint__data.html#7cd2a34cef45f168eb3ee197c101d164">hstnegdet</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Host Negotiation Detected. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongotgint__data.html#f216cb4939e1a348fbffaff87fc42772">adevtoutchng</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">A-Device Timeout Change. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongotgint__data.html#7bac6821d07d401731213dc0e94852ca">debdone</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Debounce Done. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongotgint__data.html#7ef91e2737b9a29324c79310e94a0bca">reserved31_20</a>:12</td></tr>
+
+<tr><td class="memItemLeft" nowrap valign="top">}&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniongotgint__data.html#e48c5633608687c8895da201199c2a7c">b</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">register bits <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This union represents the bit fields of the Core OTG Interrupt Register (GOTGINT). 
+<p>
+Set/clear the bits using the bit fields then write the <em>d32</em> value to the register. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00179">179</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr>The documentation for this union was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/uniongrstctl__data.html b/drivers/usb/host/dwc_otg/doc/html/uniongrstctl__data.html
new file mode 100644
index 000000000000..b5df93cfc76f
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/uniongrstctl__data.html
@@ -0,0 +1,249 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: grstctl_data Union Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>grstctl_data Union Reference</h1><!-- doxytag: class="grstctl_data" -->This union represents the bit fields of the Core Reset Register (GRSTCTL).  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="d89d99c95bd5177fbd879d38963d3e62"></a><!-- doxytag: member="grstctl_data::d32" ref="d89d99c95bd5177fbd879d38963d3e62" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniongrstctl__data.html#d89d99c95bd5177fbd879d38963d3e62">d32</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">raw register data <br></td></tr>
+<tr><td class="memItemLeft" nowrap><a class="anchor" name="7907ac8831a2f72dec59592a093871e3"></a><!-- doxytag: member="grstctl_data::b" ref="7907ac8831a2f72dec59592a093871e3" args="" -->
+struct {</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongrstctl__data.html#82df3462742f67d18b2964fafc0d9c02">csftrst</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Core Soft Reset (CSftRst) (Device and Host).  <a href="#904bb870a89d76fe699f6cb0d539e54f"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongrstctl__data.html#7418a85aa4ffaa77c49f046202c97c01">hsftrst</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Hclk Soft Reset.  <a href="#0a829bab6848f2129fb302cc879f8453"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongrstctl__data.html#6bf39518efe967ed4c7f9db6d3811a90">hstfrm</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Host Frame Counter Reset (Host Only)<br>
+.  <a href="#58e8d4fd07e1861d4d4b14d8cd778fa4"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongrstctl__data.html#259049fa7991ecad9ca1595763b636f9">intknqflsh</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">In Token Sequence Learning Queue Flush (INTknQFlsh) (Device Only). <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongrstctl__data.html#88467c1f0580f4837d229d85b35c97a7">rxfflsh</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">RxFIFO Flush (RxFFlsh) (Device and Host).  <a href="#84d734965d4f110023c1389b0ff3f99c"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongrstctl__data.html#8a5fcfc953bd0ba61beb36739c70b0ef">txfflsh</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">TxFIFO Flush (TxFFlsh) (Device and Host).  <a href="#9a92b033c5509cafff50b5c45932478a"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongrstctl__data.html#d074ddfa3331eeb6d088e35f4f627481">txfnum</a>:5</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">TxFIFO Number (TxFNum) (Device and Host).  <a href="#c339afc8688300cb67c67b75d891f370"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongrstctl__data.html#8c0515740955d128e3c8dd51ca5417ea">reserved11_29</a>:19</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Reserved. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongrstctl__data.html#13e11d4c86ca39b8edf3c1878708fad1">dmareq</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">DMA Request Signal.  <a href="#4b13d18d381ad1547693fc9e6e3b7616"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongrstctl__data.html#587c5ec6713e2626db517105ab9aea3e">ahbidle</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">AHB Master Idle.  <a href="#ffe750972d34958b0354a13428d935ba"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap valign="top">}&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniongrstctl__data.html#7907ac8831a2f72dec59592a093871e3">b</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">register bits <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This union represents the bit fields of the Core Reset Register (GRSTCTL). 
+<p>
+Set/clear the bits using the bit fields then write the <em>d32</em> value to the register. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00388">388</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr><h2>Field Documentation</h2>
+<a class="anchor" name="82df3462742f67d18b2964fafc0d9c02"></a><!-- doxytag: member="grstctl_data::csftrst" ref="82df3462742f67d18b2964fafc0d9c02" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">unsigned <a class="el" href="uniongrstctl__data.html#82df3462742f67d18b2964fafc0d9c02">grstctl_data::csftrst</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Core Soft Reset (CSftRst) (Device and Host). 
+<p>
+The application can flush the control logic in the entire core using this bit. This bit resets the pipelines in the AHB Clock domain as well as the PHY Clock domain.<p>
+The state machines are reset to an IDLE state, the control bits in the CSRs are cleared, all the transmit FIFOs and the receive FIFO are flushed.<p>
+The status mask bits that control the generation of the interrupt, are cleared, to clear the interrupt. The interrupt status bits are not cleared, so the application can get the status of any events that occurred in the core after it has set this bit.<p>
+Any transactions on the AHB are terminated as soon as possible following the protocol. Any transactions on the USB are terminated immediately.<p>
+The configuration settings in the CSRs are unchanged, so the software doesn't have to reprogram these registers (Device Configuration/Host Configuration/Core System Configuration/Core PHY Configuration).<p>
+The application can write to this bit, any time it wants to reset the core. This is a self clearing bit and the core clears this bit after all the necessary logic is reset in the core, which may take several clocks, depending on the current state of the core. 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00428">428</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="7418a85aa4ffaa77c49f046202c97c01"></a><!-- doxytag: member="grstctl_data::hsftrst" ref="7418a85aa4ffaa77c49f046202c97c01" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">unsigned <a class="el" href="uniongrstctl__data.html#7418a85aa4ffaa77c49f046202c97c01">grstctl_data::hsftrst</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Hclk Soft Reset. 
+<p>
+The application uses this bit to reset the control logic in the AHB clock domain. Only AHB clock domain pipelines are reset. 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00435">435</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="6bf39518efe967ed4c7f9db6d3811a90"></a><!-- doxytag: member="grstctl_data::hstfrm" ref="6bf39518efe967ed4c7f9db6d3811a90" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">unsigned <a class="el" href="uniongrstctl__data.html#6bf39518efe967ed4c7f9db6d3811a90">grstctl_data::hstfrm</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Host Frame Counter Reset (Host Only)<br>
+. 
+<p>
+The application can reset the (micro)frame number counter inside the core, using this bit. When the (micro)frame counter is reset, the subsequent SOF sent out by the core, will have a (micro)frame number of 0. 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00444">444</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="88467c1f0580f4837d229d85b35c97a7"></a><!-- doxytag: member="grstctl_data::rxfflsh" ref="88467c1f0580f4837d229d85b35c97a7" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">unsigned <a class="el" href="uniongrstctl__data.html#88467c1f0580f4837d229d85b35c97a7">grstctl_data::rxfflsh</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+RxFIFO Flush (RxFFlsh) (Device and Host). 
+<p>
+The application can flush the entire Receive FIFO using this bit.<p>
+The application must first ensure that the core is not in the middle of a transaction.<p>
+The application should write into this bit, only after making sure that neither the DMA engine is reading from the RxFIFO nor the MAC is writing the data in to the FIFO.<p>
+The application should wait until the bit is cleared before performing any other operations. This bit will takes 8 clocks (slowest of PHY or AHB clock) to clear. 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00463">463</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="8a5fcfc953bd0ba61beb36739c70b0ef"></a><!-- doxytag: member="grstctl_data::txfflsh" ref="8a5fcfc953bd0ba61beb36739c70b0ef" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">unsigned <a class="el" href="uniongrstctl__data.html#8a5fcfc953bd0ba61beb36739c70b0ef">grstctl_data::txfflsh</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+TxFIFO Flush (TxFFlsh) (Device and Host). 
+<p>
+This bit is used to selectively flush a single or all transmit FIFOs. The application must first ensure that the core is not in the middle of a transaction.<p>
+The application should write into this bit, only after making sure that neither the DMA engine is writing into the TxFIFO nor the MAC is reading the data out of the FIFO.<p>
+The application should wait until the core clears this bit, before performing any operations. This bit will takes 8 clocks (slowest of PHY or AHB clock) to clear. 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00478">478</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="d074ddfa3331eeb6d088e35f4f627481"></a><!-- doxytag: member="grstctl_data::txfnum" ref="d074ddfa3331eeb6d088e35f4f627481" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">unsigned <a class="el" href="uniongrstctl__data.html#d074ddfa3331eeb6d088e35f4f627481">grstctl_data::txfnum</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+TxFIFO Number (TxFNum) (Device and Host). 
+<p>
+This is the FIFO number which needs to be flushed, using the TxFIFO Flush bit. This field should not be changed until the TxFIFO Flush bit is cleared by the core.<ul>
+<li>0x0 : Non Periodic TxFIFO Flush</li><li>0x1 : Periodic TxFIFO #1 Flush in device mode or Periodic TxFIFO in host mode</li><li>0x2 : Periodic TxFIFO #2 Flush in device mode.</li><li>...</li><li>0xF : Periodic TxFIFO #15 Flush in device mode</li><li>0x10: Flush all the Transmit NonPeriodic and Transmit Periodic FIFOs in the core </li></ul>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00495">495</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="13e11d4c86ca39b8edf3c1878708fad1"></a><!-- doxytag: member="grstctl_data::dmareq" ref="13e11d4c86ca39b8edf3c1878708fad1" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">unsigned <a class="el" href="uniongrstctl__data.html#13e11d4c86ca39b8edf3c1878708fad1">grstctl_data::dmareq</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+DMA Request Signal. 
+<p>
+Indicated DMA request is in probress. Used for debug purpose. 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00500">500</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="587c5ec6713e2626db517105ab9aea3e"></a><!-- doxytag: member="grstctl_data::ahbidle" ref="587c5ec6713e2626db517105ab9aea3e" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">unsigned <a class="el" href="uniongrstctl__data.html#587c5ec6713e2626db517105ab9aea3e">grstctl_data::ahbidle</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+AHB Master Idle. 
+<p>
+Indicates the AHB Master State Machine is in IDLE condition. 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00503">503</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<hr>The documentation for this union was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/uniongusbcfg__data.html b/drivers/usb/host/dwc_otg/doc/html/uniongusbcfg__data.html
new file mode 100644
index 000000000000..970fe47e683d
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/uniongusbcfg__data.html
@@ -0,0 +1,98 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: gusbcfg_data Union Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>gusbcfg_data Union Reference</h1><!-- doxytag: class="gusbcfg_data" -->This union represents the bit fields of the Core USB Configuration Register (GUSBCFG).  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c3d8f2d95fd61a172eb108cb72a85b47"></a><!-- doxytag: member="gusbcfg_data::d32" ref="c3d8f2d95fd61a172eb108cb72a85b47" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniongusbcfg__data.html#c3d8f2d95fd61a172eb108cb72a85b47">d32</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">raw register data <br></td></tr>
+<tr><td class="memItemLeft" nowrap><a class="anchor" name="1dab81bf7260b1e23f97298c34abea06"></a><!-- doxytag: member="gusbcfg_data::b" ref="1dab81bf7260b1e23f97298c34abea06" args="" -->
+struct {</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongusbcfg__data.html#5dd00ef14661fce822a6ece15cf16799">toutcal</a>:3</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongusbcfg__data.html#f5e1a41cbdf6ae4b30a929ff3de8c99c">phyif</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongusbcfg__data.html#f86631568e6d3682cdba6482608bdcfe">ulpi_utmi_sel</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongusbcfg__data.html#8f23ebcf05c1bc48b4e406e98d828f78">fsintf</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongusbcfg__data.html#6680455bce7433ccec13377a20912e04">physel</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongusbcfg__data.html#e6dc05942f880adfaee600bc9e0ba33b">ddrsel</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongusbcfg__data.html#44485a787b8a386fadae801869ce7810">srpcap</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongusbcfg__data.html#71b6330c5ccf1d21ebf79a0a829612b5">hnpcap</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongusbcfg__data.html#d3e238db709189683bc41db2a67e9d61">usbtrdtim</a>:4</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongusbcfg__data.html#3ac9a67298febe31dc67c802a7f77f0a">nptxfrwnden</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongusbcfg__data.html#9e4bac4a0ef0a045f97792f68c5f35df">phylpwrclksel</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongusbcfg__data.html#ef6e00f543156d1af19662c3ee86830d">otgutmifssel</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongusbcfg__data.html#de6d061bf2d0d8c909e6f7d701977b73">ulpi_fsls</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongusbcfg__data.html#404cb37d84dd990f4df89fc904bb7a63">ulpi_auto_res</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongusbcfg__data.html#017fa2eb1df13d0917ffc6b243e5064c">ulpi_clk_sus_m</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongusbcfg__data.html#f4784a3028f221e2aed6138ecef53048">ulpi_ext_vbus_drv</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongusbcfg__data.html#b71576ecb647b9d81aa8c9b45c9fe14d">ulpi_int_vbus_indicator</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongusbcfg__data.html#d075f50f1d962c57ff491291f66f1778">term_sel_dl_pulse</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongusbcfg__data.html#b6472dd64884f1b91bb5e7f27cfff97e">reserved23_25</a>:3</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongusbcfg__data.html#b729e853539aafb4bab1e4e9ac57916a">ic_usb_cap</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongusbcfg__data.html#6805b1ea875bbb9cd31e877fd66c8559">ic_traffic_pull_remove</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongusbcfg__data.html#581b301bfa1951e1bd8ee20aa7256dc2">tx_end_delay</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="uniongusbcfg__data.html#eccc976f536ce6742e0df01df7d8b095">reserved29_31</a>:3</td></tr>
+
+<tr><td class="memItemLeft" nowrap valign="top">}&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="uniongusbcfg__data.html#1dab81bf7260b1e23f97298c34abea06">b</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">register bits <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This union represents the bit fields of the Core USB Configuration Register (GUSBCFG). 
+<p>
+Set the bits using the bit fields then write the <em>d32</em> value to the register. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00247">247</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr>The documentation for this union was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/unionhaint__data.html b/drivers/usb/host/dwc_otg/doc/html/unionhaint__data.html
new file mode 100644
index 000000000000..55773ff0b89a
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/unionhaint__data.html
@@ -0,0 +1,93 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: haint_data Union Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>haint_data Union Reference</h1><!-- doxytag: class="haint_data" -->This union represents the bit fields in the Host All Interrupt Register.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c83834650d2981b44274a89dda63a0f5"></a><!-- doxytag: member="haint_data::d32" ref="c83834650d2981b44274a89dda63a0f5" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhaint__data.html#c83834650d2981b44274a89dda63a0f5">d32</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">raw register data <br></td></tr>
+<tr><td class="memItemLeft" nowrap><a class="anchor" name="4ca1bd2581863c172fe667b226cfa2aa"></a><!-- doxytag: member="haint_data::b" ref="4ca1bd2581863c172fe667b226cfa2aa" args="" -->
+struct {</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhaint__data.html#4518de0451164b403fd446119606c798">ch0</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhaint__data.html#111c951f2c033e42b8d341f968ccc387">ch1</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhaint__data.html#4f22391988e52ce0cf4c26114352d491">ch2</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhaint__data.html#595c465c0d89f2fc5b213436243f3301">ch3</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhaint__data.html#daec53008bfef01a4eae6a287476be28">ch4</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhaint__data.html#236e813b0d2c40105d98eabaaa83668a">ch5</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhaint__data.html#4b32ecbff1ca92fb9a6ed7c85163b068">ch6</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhaint__data.html#858da0223b1c8c714704083fc3bb8716">ch7</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhaint__data.html#a2b5aa5c0ad6f2ddd237f2fc4d5772f5">ch8</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhaint__data.html#991c29e3cf0a85ef17178df828fd1474">ch9</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhaint__data.html#07c1c428e4e756aa65338659fc2f20d1">ch10</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhaint__data.html#5234dd8c3b0aa7d46154aa89f6fe2635">ch11</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhaint__data.html#43ab83f803054d0a5557471380186f8f">ch12</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhaint__data.html#7764f0ba6f46901a0c800dcc8c158643">ch13</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhaint__data.html#46a15c2faf17d049b71fcd46d1a58842">ch14</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhaint__data.html#58435a2988a1d8a2dd11c64b8246bfcf">ch15</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhaint__data.html#08adf6a68f6ae5051eb461477afbe2cf">reserved</a>:16</td></tr>
+
+<tr><td class="memItemLeft" nowrap valign="top">}&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhaint__data.html#4ca1bd2581863c172fe667b226cfa2aa">b</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">register bits <br></td></tr>
+<tr><td class="memItemLeft" nowrap><a class="anchor" name="9317187b895abebbca64c364b6c3c322"></a><!-- doxytag: member="haint_data::b2" ref="9317187b895abebbca64c364b6c3c322" args="" -->
+struct {</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhaint__data.html#6824b5b98c861cbc8efe3ba9f70cfea0">chint</a>:16</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhaint__data.html#08adf6a68f6ae5051eb461477afbe2cf">reserved</a>:16</td></tr>
+
+<tr><td class="memItemLeft" nowrap valign="top">}&nbsp;</td><td class="memItemRight" valign="bottom"><b>b2</b></td></tr>
+
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This union represents the bit fields in the Host All Interrupt Register. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01771">1771</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr>The documentation for this union was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/unionhaintmsk__data.html b/drivers/usb/host/dwc_otg/doc/html/unionhaintmsk__data.html
new file mode 100644
index 000000000000..175595875429
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/unionhaintmsk__data.html
@@ -0,0 +1,93 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: haintmsk_data Union Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>haintmsk_data Union Reference</h1><!-- doxytag: class="haintmsk_data" -->This union represents the bit fields in the Host All Interrupt Register.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="65f3e5dbc7a62b6fb57426abaaffc6a2"></a><!-- doxytag: member="haintmsk_data::d32" ref="65f3e5dbc7a62b6fb57426abaaffc6a2" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhaintmsk__data.html#65f3e5dbc7a62b6fb57426abaaffc6a2">d32</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">raw register data <br></td></tr>
+<tr><td class="memItemLeft" nowrap><a class="anchor" name="03f75072e5548a4addea100a40e0ac89"></a><!-- doxytag: member="haintmsk_data::b" ref="03f75072e5548a4addea100a40e0ac89" args="" -->
+struct {</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhaintmsk__data.html#dd096952e3d38ffa5db796e3a7334e7b">ch0</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhaintmsk__data.html#c79960e27bba0c730936148272b14d3b">ch1</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhaintmsk__data.html#0ecac53d912d941c9139af6591f93261">ch2</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhaintmsk__data.html#40feb12ac2af27dfb5772dcaec2c17c2">ch3</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhaintmsk__data.html#5692699f367a57de45bab48856a35624">ch4</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhaintmsk__data.html#e49e1e6e4bea7ee8375c7e9da57d0217">ch5</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhaintmsk__data.html#df9d27f0be312e3c56cbd20736cb8e07">ch6</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhaintmsk__data.html#df61ec0f4ee97164b1a1aa1d8d0bd4b8">ch7</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhaintmsk__data.html#1c05566d9af4c7401cc95ed613b62252">ch8</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhaintmsk__data.html#f12b0a59f2e663d15e9f69866c5bf701">ch9</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhaintmsk__data.html#e815617fd288b134798fa5e2dd23af67">ch10</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhaintmsk__data.html#51e0430615e457c51a8f12f3c8c6246b">ch11</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhaintmsk__data.html#a7e151fe0676bde7a2ac43ee5b6f1b73">ch12</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhaintmsk__data.html#3ad05d0ef4e63250fc7b3af9f1654271">ch13</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhaintmsk__data.html#3f0cf3851a6f6b74c33a71a3b255372b">ch14</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhaintmsk__data.html#da69c5905fb9a16f50f9a0a8c0c9b125">ch15</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhaintmsk__data.html#b538c489375d2ca28e852a1b0366a532">reserved</a>:16</td></tr>
+
+<tr><td class="memItemLeft" nowrap valign="top">}&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhaintmsk__data.html#03f75072e5548a4addea100a40e0ac89">b</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">register bits <br></td></tr>
+<tr><td class="memItemLeft" nowrap><a class="anchor" name="59b2dc1e77bcf9b638f72776f494a77f"></a><!-- doxytag: member="haintmsk_data::b2" ref="59b2dc1e77bcf9b638f72776f494a77f" args="" -->
+struct {</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhaintmsk__data.html#80030e17495460223602afd3aad1287c">chint</a>:16</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhaintmsk__data.html#b538c489375d2ca28e852a1b0366a532">reserved</a>:16</td></tr>
+
+<tr><td class="memItemLeft" nowrap valign="top">}&nbsp;</td><td class="memItemRight" valign="bottom"><b>b2</b></td></tr>
+
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This union represents the bit fields in the Host All Interrupt Register. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01805">1805</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr>The documentation for this union was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/unionhcchar__data.html b/drivers/usb/host/dwc_otg/doc/html/unionhcchar__data.html
new file mode 100644
index 000000000000..14a5823f3b5f
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/unionhcchar__data.html
@@ -0,0 +1,123 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hcchar_data Union Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>hcchar_data Union Reference</h1><!-- doxytag: class="hcchar_data" -->This union represents the bit fields in the Host Channel Characteristics Register.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="03d352fb421ab5c11bf9afaae4933ba4"></a><!-- doxytag: member="hcchar_data::d32" ref="03d352fb421ab5c11bf9afaae4933ba4" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhcchar__data.html#03d352fb421ab5c11bf9afaae4933ba4">d32</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">raw register data <br></td></tr>
+<tr><td class="memItemLeft" nowrap><a class="anchor" name="231c3638b02200c477e402d977c31e51"></a><!-- doxytag: member="hcchar_data::b" ref="231c3638b02200c477e402d977c31e51" args="" -->
+struct {</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcchar__data.html#47d11a5e62f69534d8ac0606aa7ffe7d">mps</a>:11</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Maximum packet size in bytes. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcchar__data.html#1597f36b85006e643aaf6f4d503bebc9">epnum</a>:4</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Endpoint number. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcchar__data.html#11f1b16e50f90806f90953bb979d4e77">epdir</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">0: OUT, 1: IN <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcchar__data.html#40e9041243226810913a7f227fd84c9a">reserved</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcchar__data.html#ca469c8bda88761c4d9ef74b811d71f4">lspddev</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">0: Full/high speed device, 1: Low speed device <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcchar__data.html#df4deee52d932ab29e5d077cde77cbfc">eptype</a>:2</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">0: Control, 1: Isoc, 2: Bulk, 3: Intr <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcchar__data.html#9c0f515663251779e4960ec5613ce6fe">multicnt</a>:2</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Packets per frame for periodic transfers.  <a href="#ce2238ba96fbda574a72c4834a2a810a"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcchar__data.html#19326a679cb3507cf294d229834252a1">devaddr</a>:7</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Device address. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcchar__data.html#1eae01428cc22feed785eedff05c86da">oddfrm</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Frame to transmit periodic transaction.  <a href="#e7bc71fa9c5691332221255fd2e61d63"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcchar__data.html#73c9f7f3cc4036c72ef341d1d1d9c388">chdis</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Channel disable. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcchar__data.html#994a5305780edb0c4fe159b6cc7b14ae">chen</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Channel enable. <br></td></tr>
+<tr><td class="memItemLeft" nowrap valign="top">}&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhcchar__data.html#231c3638b02200c477e402d977c31e51">b</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">register bits <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This union represents the bit fields in the Host Channel Characteristics Register. 
+<p>
+Read the register into the <em>d32</em> member then set/clear the bits using the <em>b</em>it elements. Write the <em>d32</em> member to the hcchar register. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01863">1863</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr><h2>Field Documentation</h2>
+<a class="anchor" name="9c0f515663251779e4960ec5613ce6fe"></a><!-- doxytag: member="hcchar_data::multicnt" ref="9c0f515663251779e4960ec5613ce6fe" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">unsigned <a class="el" href="unionhcchar__data.html#9c0f515663251779e4960ec5613ce6fe">hcchar_data::multicnt</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Packets per frame for periodic transfers. 
+<p>
+0 is reserved. 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01887">1887</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<a class="anchor" name="1eae01428cc22feed785eedff05c86da"></a><!-- doxytag: member="hcchar_data::oddfrm" ref="1eae01428cc22feed785eedff05c86da" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">unsigned <a class="el" href="unionhcchar__data.html#1eae01428cc22feed785eedff05c86da">hcchar_data::oddfrm</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Frame to transmit periodic transaction. 
+<p>
+0: even, 1: odd 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01896">1896</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<hr>The documentation for this union was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/unionhcdma__data.html b/drivers/usb/host/dwc_otg/doc/html/unionhcdma__data.html
new file mode 100644
index 000000000000..4508ac2f7645
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/unionhcdma__data.html
@@ -0,0 +1,78 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hcdma_data Union Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>hcdma_data Union Reference</h1><!-- doxytag: class="hcdma_data" -->This union represents the bit fields in the Host DMA Address Register used in Descriptor DMA mode.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="27b804015f09ea7eb25f602cc6dbdda9"></a><!-- doxytag: member="hcdma_data::d32" ref="27b804015f09ea7eb25f602cc6dbdda9" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhcdma__data.html#27b804015f09ea7eb25f602cc6dbdda9">d32</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">raw register data <br></td></tr>
+<tr><td class="memItemLeft" nowrap><a class="anchor" name="61ea7b926fcef1d4fe1a6c8a1a1be41a"></a><!-- doxytag: member="hcdma_data::b" ref="61ea7b926fcef1d4fe1a6c8a1a1be41a" args="" -->
+struct {</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcdma__data.html#3d9002e33b12ccde29856f08db7be7bf">reserved0_2</a>: 3</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcdma__data.html#d1238e3a2f81540362765b3e6a29d7de">ctd</a>: 8</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Current Transfer Descriptor.  <a href="#b44d4a2e227aaf21169a9dce2e683794"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcdma__data.html#8324b2ba8d18c5ecb1cbcb23874393db">dma_addr</a>: 21</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Start Address of Descriptor List. <br></td></tr>
+<tr><td class="memItemLeft" nowrap valign="top">}&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhcdma__data.html#61ea7b926fcef1d4fe1a6c8a1a1be41a">b</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">register bits <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This union represents the bit fields in the Host DMA Address Register used in Descriptor DMA mode. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l02086">2086</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr><h2>Field Documentation</h2>
+<a class="anchor" name="d1238e3a2f81540362765b3e6a29d7de"></a><!-- doxytag: member="hcdma_data::ctd" ref="d1238e3a2f81540362765b3e6a29d7de" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">unsigned <a class="el" href="unionhcdma__data.html#d1238e3a2f81540362765b3e6a29d7de">hcdma_data::ctd</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Current Transfer Descriptor. 
+<p>
+Not used for ISOC 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l02095">2095</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<hr>The documentation for this union was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/unionhcfg__data.html b/drivers/usb/host/dwc_otg/doc/html/unionhcfg__data.html
new file mode 100644
index 000000000000..56846ebf514a
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/unionhcfg__data.html
@@ -0,0 +1,72 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hcfg_data Union Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>hcfg_data Union Reference</h1><!-- doxytag: class="hcfg_data" -->This union represents the bit fields in the Host Configuration Register.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="381a253b3a38a7f943dcbb42f7bf10be"></a><!-- doxytag: member="hcfg_data::d32" ref="381a253b3a38a7f943dcbb42f7bf10be" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhcfg__data.html#381a253b3a38a7f943dcbb42f7bf10be">d32</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">raw register data <br></td></tr>
+<tr><td class="memItemLeft" nowrap><a class="anchor" name="45bbb24387d58961dd2b8f2f65689bd7"></a><!-- doxytag: member="hcfg_data::b" ref="45bbb24387d58961dd2b8f2f65689bd7" args="" -->
+struct {</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcfg__data.html#e048ad3775c6794c3ee07af86079fadf">fslspclksel</a>:2</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">FS/LS Phy Clock Select. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcfg__data.html#c047f55e398b8a94aef27a66ed78f2de">fslssupp</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">FS/LS Only Support. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcfg__data.html#fcbdeb7668bb4e9f6cf150052ae2d014">reserved3_22</a>: 20</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcfg__data.html#7ec04d77b1c0d3cc25165e77e9bce5f4">descdma</a>: 1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Enable Scatter/gather DMA in Host mode. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcfg__data.html#11340031265fce764f491b23ae42dda5">frlisten</a>: 2</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Frame List Entries. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcfg__data.html#b49be9c0cbc3df2bb917e1ea96c99c62">perschedena</a>: 1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Enable Periodic Scheduling. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcfg__data.html#995a4d09381b8d6ce2c7ac0a6c7f364a">perschedstat</a>: 1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Periodic Scheduling Enabled Status. <br></td></tr>
+<tr><td class="memItemLeft" nowrap valign="top">}&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhcfg__data.html#45bbb24387d58961dd2b8f2f65689bd7">b</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">register bits <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This union represents the bit fields in the Host Configuration Register. 
+<p>
+Read the register into the <em>d32</em> member then set/clear the bits using the <em>b</em>it elements. Write the <em>d32</em> member to the hcfg register. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01652">1652</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr>The documentation for this union was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/unionhcint__data.html b/drivers/usb/host/dwc_otg/doc/html/unionhcint__data.html
new file mode 100644
index 000000000000..0bdb8de26d33
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/unionhcint__data.html
@@ -0,0 +1,95 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hcint_data Union Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>hcint_data Union Reference</h1><!-- doxytag: class="hcint_data" -->This union represents the bit fields in the Host All Interrupt Register.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="05a82fa7693f875622db744716d7f73e"></a><!-- doxytag: member="hcint_data::d32" ref="05a82fa7693f875622db744716d7f73e" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhcint__data.html#05a82fa7693f875622db744716d7f73e">d32</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">raw register data <br></td></tr>
+<tr><td class="memItemLeft" nowrap><a class="anchor" name="3ab6af507f45d91a7898dd711f4368ee"></a><!-- doxytag: member="hcint_data::b" ref="3ab6af507f45d91a7898dd711f4368ee" args="" -->
+struct {</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcint__data.html#49385cb90c4d8c003cfac91175a646e0">xfercomp</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Transfer Complete. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcint__data.html#b93ceab913a49e33c5bf4dde0e62d75a">chhltd</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Channel Halted. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcint__data.html#f953465ff02c518a52c48d4d6b1c09c7">ahberr</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">AHB Error. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcint__data.html#cf2fb413e5758e9ebd8914b2f7605d73">stall</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">STALL Response Received. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcint__data.html#ce65c9d3f0c7d3e5b8f163a378051c6c">nak</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">NAK Response Received. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcint__data.html#729749d6d0b5a1d4c449287f9efdd5fe">ack</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">ACK Response Received. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcint__data.html#755e54c3dfded3653447dfdd63fd8b6a">nyet</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">NYET Response Received. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcint__data.html#86ec2d311ef29228676781f9100d195a">xacterr</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Transaction Err. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcint__data.html#b05adf33c7be609a2daf54478f884ec4">bblerr</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Babble Error. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcint__data.html#06f911d323d71f86639550507322dffb">frmovrun</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Frame Overrun. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcint__data.html#2fc8618d16e6908e99c8cca3ffb54736">datatglerr</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Data Toggle Error. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcint__data.html#759d3d0d98bd7efe69d46cc975b81845">bna</a>: 1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Buffer Not Available (only for DDMA mode). <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcint__data.html#f13613b1a33edddb676d2bce8a35e447">xcs_xact</a>: 1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Exessive transaction error (only for DDMA mode). <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcint__data.html#26f48c3ec302ac2e009be71733e068b7">frm_list_roll</a>: 1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Frame List Rollover interrupt. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcint__data.html#1b7dcab0dbc45803be45b4d0b99eac49">reserved14_31</a>: 18</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Reserved. <br></td></tr>
+<tr><td class="memItemLeft" nowrap valign="top">}&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhcint__data.html#3ab6af507f45d91a7898dd711f4368ee">b</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">register bits <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This union represents the bit fields in the Host All Interrupt Register. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01940">1940</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr>The documentation for this union was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/unionhcintmsk__data.html b/drivers/usb/host/dwc_otg/doc/html/unionhcintmsk__data.html
new file mode 100644
index 000000000000..06321b1e288b
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/unionhcintmsk__data.html
@@ -0,0 +1,82 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hcintmsk_data Union Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>hcintmsk_data Union Reference</h1><!-- doxytag: class="hcintmsk_data" -->This union represents the bit fields in the Host Channel Interrupt Mask Register.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="8868299fcc762e005b7f0bf67e5fbe30"></a><!-- doxytag: member="hcintmsk_data::d32" ref="8868299fcc762e005b7f0bf67e5fbe30" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhcintmsk__data.html#8868299fcc762e005b7f0bf67e5fbe30">d32</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">raw register data <br></td></tr>
+<tr><td class="memItemLeft" nowrap><a class="anchor" name="6835f55069c94947b580c8f01f64a075"></a><!-- doxytag: member="hcintmsk_data::b" ref="6835f55069c94947b580c8f01f64a075" args="" -->
+struct {</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcintmsk__data.html#4983a78156d96d9a0c16ca8ea2b09106">xfercompl</a>: 1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcintmsk__data.html#2549a84a06f4f6a7ad6fed50fcf7b068">chhltd</a>: 1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcintmsk__data.html#bd9e228b6cb8e60cdbefd4bb57bdcc33">ahberr</a>: 1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcintmsk__data.html#94dc82e231d28d16d21238809cb88f78">stall</a>: 1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcintmsk__data.html#32ae7d92d0eb93ced42ac3773ddc3a2f">nak</a>: 1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcintmsk__data.html#8d3388818a6dc098a1e1c64147d1ced9">ack</a>: 1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcintmsk__data.html#4274f9b730db0e390e5f3be4247ee45c">nyet</a>: 1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcintmsk__data.html#29686b2c0b9502932327915d690a45d5">xacterr</a>: 1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcintmsk__data.html#5052c8737755083ee10105f36e839590">bblerr</a>: 1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcintmsk__data.html#2ba9f8dc5e946b28ac4169f75364e182">frmovrun</a>: 1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcintmsk__data.html#60bbf3878314aad41055137e348cc01d">datatglerr</a>: 1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcintmsk__data.html#dfbcaada980b7132f06667e0536b17da">bna</a>: 1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcintmsk__data.html#ace04f1b0f78826b8d33b828d4e637c2">xcs_xact</a>: 1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcintmsk__data.html#da781977131daa2db51fee16900366ae">frm_list_roll</a>: 1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcintmsk__data.html#dcb3b9df0efa5f60db95dd09a7e4a083">reserved14_31</a>: 18</td></tr>
+
+<tr><td class="memItemLeft" nowrap valign="top">}&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhcintmsk__data.html#6835f55069c94947b580c8f01f64a075">b</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">register bits <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This union represents the bit fields in the Host Channel Interrupt Mask Register. 
+<p>
+Read the register into the <em>d32</em> member then set/clear the bits using the <em>b</em>it elements. Write the <em>d32</em> member to the hcintmsk register. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01986">1986</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr>The documentation for this union was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/unionhcsplt__data.html b/drivers/usb/host/dwc_otg/doc/html/unionhcsplt__data.html
new file mode 100644
index 000000000000..713a5b584f18
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/unionhcsplt__data.html
@@ -0,0 +1,63 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hcsplt_data Union Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>hcsplt_data Union Reference</h1><!-- doxytag: class="hcsplt_data" --><table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="0cd235b445ff681b846f5dccf24fd644"></a><!-- doxytag: member="hcsplt_data::d32" ref="0cd235b445ff681b846f5dccf24fd644" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhcsplt__data.html#0cd235b445ff681b846f5dccf24fd644">d32</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">raw register data <br></td></tr>
+<tr><td class="memItemLeft" nowrap><a class="anchor" name="b8bafe40eee4a9f598659d254be836e1"></a><!-- doxytag: member="hcsplt_data::b" ref="b8bafe40eee4a9f598659d254be836e1" args="" -->
+struct {</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcsplt__data.html#e1c0812d6f655ea9915a6152c9f16cd6">prtaddr</a>:7</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Port Address. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcsplt__data.html#2843e0a36458a9a4c2d5ed6da3027b36">hubaddr</a>:7</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Hub Address. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcsplt__data.html#68e7b96ce2ca96c96f40b4f95c679a11">xactpos</a>:2</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Transaction Position. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcsplt__data.html#0a4855eb44ec93ec47dcc218a8703e94">compsplt</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Do Complete Split. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcsplt__data.html#28e272ea89e4f9e7c2db05fb92927e74">reserved</a>:14</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Reserved. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhcsplt__data.html#8b174930345ac0e5a8a6bd16794836d7">spltena</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Split Enble. <br></td></tr>
+<tr><td class="memItemLeft" nowrap valign="top">}&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhcsplt__data.html#b8bafe40eee4a9f598659d254be836e1">b</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">register bits <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01906">1906</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr>The documentation for this union was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/unionhctsiz__data.html b/drivers/usb/host/dwc_otg/doc/html/unionhctsiz__data.html
new file mode 100644
index 000000000000..36928a1ba356
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/unionhctsiz__data.html
@@ -0,0 +1,105 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hctsiz_data Union Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>hctsiz_data Union Reference</h1><!-- doxytag: class="hctsiz_data" -->This union represents the bit fields in the Host Channel Transfer Size Register.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="fb41950555c60c6015294bdefe9cd39d"></a><!-- doxytag: member="hctsiz_data::d32" ref="fb41950555c60c6015294bdefe9cd39d" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhctsiz__data.html#fb41950555c60c6015294bdefe9cd39d">d32</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">raw register data <br></td></tr>
+<tr><td class="memItemLeft" nowrap><a class="anchor" name="8967fa90c651bce44a3cbe90c44cf638"></a><!-- doxytag: member="hctsiz_data::b" ref="8967fa90c651bce44a3cbe90c44cf638" args="" -->
+struct {</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhctsiz__data.html#6ad01d874d77aa4382f71fa68eaec12d">xfersize</a>:19</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Total transfer size in bytes. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhctsiz__data.html#3ea18df5a98d33a6f8fa786252a0205b">pktcnt</a>:10</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Data packets to transfer. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhctsiz__data.html#d8b17af02c244e47ca0c38f933a6b3f0">pid</a>:2</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Packet ID for next data packet 0: DATA0 1: DATA2 2: DATA1 3: MDATA (non-Control), SETUP (Control). <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhctsiz__data.html#68625ebdd11afc0a026f41c94aedc161">dopng</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Do PING protocol when 1. <br></td></tr>
+<tr><td class="memItemLeft" nowrap valign="top">}&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhctsiz__data.html#8967fa90c651bce44a3cbe90c44cf638">b</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">register bits <br></td></tr>
+<tr><td class="memItemLeft" nowrap><a class="anchor" name="6cc80c630201f29e4a43e0cd7030786b"></a><!-- doxytag: member="hctsiz_data::b_ddma" ref="6cc80c630201f29e4a43e0cd7030786b" args="" -->
+struct {</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhctsiz__data.html#0d1f05f3b24da2caa3acc1c3864bc29b">schinfo</a>: 8</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Scheduling information. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhctsiz__data.html#ac1addd68951e1a6a25312d49be9895d">ntd</a>: 8</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Number of transfer descriptors.  <a href="#580c58735ef4e4a9f71fad9bc4b1ec13"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhctsiz__data.html#30027b4cc28a3dd7930e48635a00488d">reserved16_28</a>: 13</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Data packets to transfer. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhctsiz__data.html#d8b17af02c244e47ca0c38f933a6b3f0">pid</a>: 2</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Packet ID for next data packet 0: DATA0 1: DATA2 2: DATA1 3: MDATA (non-Control). <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhctsiz__data.html#68625ebdd11afc0a026f41c94aedc161">dopng</a>: 1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Do PING protocol when 1. <br></td></tr>
+<tr><td class="memItemLeft" nowrap valign="top">}&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhctsiz__data.html#6cc80c630201f29e4a43e0cd7030786b">b_ddma</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">register bits <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This union represents the bit fields in the Host Channel Transfer Size Register. 
+<p>
+Read the register into the <em>d32</em> member then set/clear the bits using the <em>b</em>it elements. Write the <em>d32</em> member to the hcchar register. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l02019">2019</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr><h2>Field Documentation</h2>
+<a class="anchor" name="ac1addd68951e1a6a25312d49be9895d"></a><!-- doxytag: member="hctsiz_data::ntd" ref="ac1addd68951e1a6a25312d49be9895d" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">unsigned <a class="el" href="unionhctsiz__data.html#ac1addd68951e1a6a25312d49be9895d">hctsiz_data::ntd</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Number of transfer descriptors. 
+<p>
+Max value: 64 in general, 256 only for HS isochronous endpoint. 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l02062">2062</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<hr>The documentation for this union was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/unionhfir__data.html b/drivers/usb/host/dwc_otg/doc/html/unionhfir__data.html
new file mode 100644
index 000000000000..a29b19fd29f9
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/unionhfir__data.html
@@ -0,0 +1,54 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hfir_data Union Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>hfir_data Union Reference</h1><!-- doxytag: class="hfir_data" -->This union represents the bit fields in the Host Frame Remaing/Number Register.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="859d5325dbf422643fb86695328c206d"></a><!-- doxytag: member="hfir_data::d32" ref="859d5325dbf422643fb86695328c206d" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhfir__data.html#859d5325dbf422643fb86695328c206d">d32</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">raw register data <br></td></tr>
+<tr><td class="memItemLeft" nowrap><a class="anchor" name="01ffc2aff6bf358564585c2ee7d513c8"></a><!-- doxytag: member="hfir_data::b" ref="01ffc2aff6bf358564585c2ee7d513c8" args="" -->
+struct {</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhfir__data.html#5302611bdf96e87f3a7f30319212bcc2">frint</a>:16</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhfir__data.html#ea1f95b5e0c86d531a8d76a2784efe1d">reserved</a>:16</td></tr>
+
+<tr><td class="memItemLeft" nowrap valign="top">}&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhfir__data.html#01ffc2aff6bf358564585c2ee7d513c8">b</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">register bits <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This union represents the bit fields in the Host Frame Remaing/Number Register. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01684">1684</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr>The documentation for this union was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/unionhfnum__data.html b/drivers/usb/host/dwc_otg/doc/html/unionhfnum__data.html
new file mode 100644
index 000000000000..0dbdb8917935
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/unionhfnum__data.html
@@ -0,0 +1,54 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hfnum_data Union Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>hfnum_data Union Reference</h1><!-- doxytag: class="hfnum_data" -->This union represents the bit fields in the Host Frame Remaing/Number Register.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="e5ccbed3af86ac88577ded328e6c9932"></a><!-- doxytag: member="hfnum_data::d32" ref="e5ccbed3af86ac88577ded328e6c9932" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhfnum__data.html#e5ccbed3af86ac88577ded328e6c9932">d32</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">raw register data <br></td></tr>
+<tr><td class="memItemLeft" nowrap><a class="anchor" name="81df6fbd20a454665803eb5790855c66"></a><!-- doxytag: member="hfnum_data::b" ref="81df6fbd20a454665803eb5790855c66" args="" -->
+struct {</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhfnum__data.html#a64e8b6c4a1cd262dbc30e158f3cb8bc">frnum</a>:16</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhfnum__data.html#2a2ce50ebd4c4da5347a2d93c4bbc996">frrem</a>:16</td></tr>
+
+<tr><td class="memItemLeft" nowrap valign="top">}&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhfnum__data.html#81df6fbd20a454665803eb5790855c66">b</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">register bits <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This union represents the bit fields in the Host Frame Remaing/Number Register. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01699">1699</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr>The documentation for this union was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/unionhost__dma__desc__sts.html b/drivers/usb/host/dwc_otg/doc/html/unionhost__dma__desc__sts.html
new file mode 100644
index 000000000000..487cb1ce9839
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/unionhost__dma__desc__sts.html
@@ -0,0 +1,123 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: host_dma_desc_sts Union Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>host_dma_desc_sts Union Reference</h1><!-- doxytag: class="host_dma_desc_sts" -->This union represents the bit fields in the DMA Descriptor status quadlet for host mode.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="c8e191345883c19b7127e54479c75e4d"></a><!-- doxytag: member="host_dma_desc_sts::d32" ref="c8e191345883c19b7127e54479c75e4d" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhost__dma__desc__sts.html#c8e191345883c19b7127e54479c75e4d">d32</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">raw register data <br></td></tr>
+<tr><td class="memItemLeft" nowrap><a class="anchor" name="a0e53895b927bfa9e322c3a3c0a08b3b"></a><!-- doxytag: member="host_dma_desc_sts::b" ref="a0e53895b927bfa9e322c3a3c0a08b3b" args="" -->
+struct {</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhost__dma__desc__sts.html#a8f68a8a5c22c3c1b530400c23083892">n_bytes</a>: 17</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Number of bytes. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhost__dma__desc__sts.html#80be234e5bac143beca335ffe226eef6">qtd_offset</a>: 6</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">QTD offset to jump when Short Packet received - only for IN EPs. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhost__dma__desc__sts.html#c6ec29eb4bc0c9e165b3d09b951b4d13">a_qtd</a>: 1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Set to request the core to jump to alternate QTD if Short Packet received - only for IN EPs. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhost__dma__desc__sts.html#634060a1b436857e15e8eb8f0d6d000a">sup</a>: 1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Setup Packet bit.  <a href="#bc5be7dc40019bf6af55d3af26334e6b"></a><br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhost__dma__desc__sts.html#2efbb549924afd0deb402af9eda4a272">ioc</a>: 1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Interrupt On Complete. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhost__dma__desc__sts.html#58d670cd305219a32f144a6705e649e3">eol</a>: 1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">End of List. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhost__dma__desc__sts.html#a9cdbf7ba860112e98594c98483cc513">reserved27</a>: 1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhost__dma__desc__sts.html#828b019082523c4637758bef38805420">sts</a>: 2</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Rx/Tx Status. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhost__dma__desc__sts.html#8bdb2544b6e88225d2fc082110ea04bb">reserved30</a>: 1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhost__dma__desc__sts.html#1c4cf70718c94a1a847e52d4dd65cbb0">a</a>: 1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Active Bit. <br></td></tr>
+<tr><td class="memItemLeft" nowrap valign="top">}&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhost__dma__desc__sts.html#a0e53895b927bfa9e322c3a3c0a08b3b">b</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">quadlet bits <br></td></tr>
+<tr><td class="memItemLeft" nowrap><a class="anchor" name="e16a70bba7e2e196189573323c2dbe1c"></a><!-- doxytag: member="host_dma_desc_sts::b_isoc" ref="e16a70bba7e2e196189573323c2dbe1c" args="" -->
+struct {</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhost__dma__desc__sts.html#a8f68a8a5c22c3c1b530400c23083892">n_bytes</a>: 12</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Number of bytes. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhost__dma__desc__sts.html#6b8b65f5037dd388cc2427f602ba0f8e">reserved12_24</a>: 13</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhost__dma__desc__sts.html#2efbb549924afd0deb402af9eda4a272">ioc</a>: 1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Interrupt On Complete. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhost__dma__desc__sts.html#834971c4ec03a85654c8630ced715c8c">reserved26_27</a>: 2</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhost__dma__desc__sts.html#828b019082523c4637758bef38805420">sts</a>: 2</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Rx/Tx Status. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhost__dma__desc__sts.html#8bdb2544b6e88225d2fc082110ea04bb">reserved30</a>: 1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhost__dma__desc__sts.html#1c4cf70718c94a1a847e52d4dd65cbb0">a</a>: 1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Active Bit. <br></td></tr>
+<tr><td class="memItemLeft" nowrap valign="top">}&nbsp;</td><td class="memItemRight" valign="bottom"><b>b_isoc</b></td></tr>
+
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This union represents the bit fields in the DMA Descriptor status quadlet for host mode. 
+<p>
+Read the quadlet into the <em>d32</em> member then set/clear the bits using the <em>b</em>it elements. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l02106">2106</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr><h2>Field Documentation</h2>
+<a class="anchor" name="634060a1b436857e15e8eb8f0d6d000a"></a><!-- doxytag: member="host_dma_desc_sts::sup" ref="634060a1b436857e15e8eb8f0d6d000a" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">unsigned <a class="el" href="unionhost__dma__desc__sts.html#634060a1b436857e15e8eb8f0d6d000a">host_dma_desc_sts::sup</a>          </td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>
+Setup Packet bit. 
+<p>
+When set indicates that buffer contains setup packet. 
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l02127">2127</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.
+</div>
+</div><p>
+<hr>The documentation for this union was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/unionhost__grxsts__data.html b/drivers/usb/host/dwc_otg/doc/html/unionhost__grxsts__data.html
new file mode 100644
index 000000000000..12927484d523
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/unionhost__grxsts__data.html
@@ -0,0 +1,60 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: host_grxsts_data Union Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>host_grxsts_data Union Reference</h1><!-- doxytag: class="host_grxsts_data" -->This union represents the bit fields in the Host Receive Status Read and Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <em>d32</em> element then read out the bits using the <em>b</em>it elements.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="993969735da9c3615652391aae76359a"></a><!-- doxytag: member="host_grxsts_data::d32" ref="993969735da9c3615652391aae76359a" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhost__grxsts__data.html#993969735da9c3615652391aae76359a">d32</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">raw register data <br></td></tr>
+<tr><td class="memItemLeft" nowrap><a class="anchor" name="9d67ba193008dd6afa7fe613c665238d"></a><!-- doxytag: member="host_grxsts_data::b" ref="9d67ba193008dd6afa7fe613c665238d" args="" -->
+struct {</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhost__grxsts__data.html#684095394d11ec74a327f945c9e678bf">chnum</a>:4</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhost__grxsts__data.html#026fd4d8ab68825fab038c083b8e9c60">bcnt</a>:11</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhost__grxsts__data.html#5c4ca6a6c4a85064dd024095607a634d">dpid</a>:2</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhost__grxsts__data.html#6dc2553475a56a445c6e6f319feffac8">pktsts</a>:4</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhost__grxsts__data.html#36fd3990562635838b4fce804de87d38">reserved</a>:11</td></tr>
+
+<tr><td class="memItemLeft" nowrap valign="top">}&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhost__grxsts__data.html#9d67ba193008dd6afa7fe613c665238d">b</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">register bits <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This union represents the bit fields in the Host Receive Status Read and Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <em>d32</em> element then read out the bits using the <em>b</em>it elements. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00627">627</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr>The documentation for this union was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/unionhprt0__data.html b/drivers/usb/host/dwc_otg/doc/html/unionhprt0__data.html
new file mode 100644
index 000000000000..084592c880cd
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/unionhprt0__data.html
@@ -0,0 +1,82 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hprt0_data Union Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>hprt0_data Union Reference</h1><!-- doxytag: class="hprt0_data" -->This union represents the bit fields in the Host Port Control and Status Register.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="88e9271f697d2ec209fc6a6da67fe216"></a><!-- doxytag: member="hprt0_data::d32" ref="88e9271f697d2ec209fc6a6da67fe216" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhprt0__data.html#88e9271f697d2ec209fc6a6da67fe216">d32</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">raw register data <br></td></tr>
+<tr><td class="memItemLeft" nowrap><a class="anchor" name="08cd86ce6da6462fc53601db7e2b73f3"></a><!-- doxytag: member="hprt0_data::b" ref="08cd86ce6da6462fc53601db7e2b73f3" args="" -->
+struct {</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhprt0__data.html#39b2dee944be8ec96857a3b43d203390">prtconnsts</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhprt0__data.html#5124a40eeafd92c9632c91a2c3132937">prtconndet</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhprt0__data.html#a964274b5d22e89ca4490f66dff3c763">prtena</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhprt0__data.html#75eae10eb537e49cc1ae2dc01c18aa47">prtenchng</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhprt0__data.html#4d8f8b654c26760791614ccbc43f180c">prtovrcurract</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhprt0__data.html#cc51da1d52cb824d419ef3feb6ba70b6">prtovrcurrchng</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhprt0__data.html#3f5961529636a3891a4ca9421dd535fa">prtres</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhprt0__data.html#e7fe71d6c465ae002211c24a6ba359d2">prtsusp</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhprt0__data.html#714a31048710164370292124795a9a9b">prtrst</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhprt0__data.html#dda1ec89253bbfe9a1592a133fe2c392">reserved9</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhprt0__data.html#85a83fc17905d43dc604dce7f0869c63">prtlnsts</a>:2</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhprt0__data.html#010bd8fb208ef4eeaa288b28f8f8c3a4">prtpwr</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhprt0__data.html#c61d714ff8f0bc62767342523347ba66">prttstctl</a>:4</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhprt0__data.html#59f1c27b8c912de0237d2d2974fc2a22">prtspd</a>:2</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhprt0__data.html#cfabc8a060c6d404c883186ec6bc9508">reserved19_31</a>:13</td></tr>
+
+<tr><td class="memItemLeft" nowrap valign="top">}&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhprt0__data.html#08cd86ce6da6462fc53601db7e2b73f3">b</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">register bits <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This union represents the bit fields in the Host Port Control and Status Register. 
+<p>
+Read the register into the <em>d32</em> member then set/clear the bits using the <em>b</em>it elements. Write the <em>d32</em> member to the hprt0 register. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01741">1741</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr>The documentation for this union was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/unionhptxsts__data.html b/drivers/usb/host/dwc_otg/doc/html/unionhptxsts__data.html
new file mode 100644
index 000000000000..584cb23cbde3
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/unionhptxsts__data.html
@@ -0,0 +1,62 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hptxsts_data Union Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>hptxsts_data Union Reference</h1><!-- doxytag: class="hptxsts_data" --><table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="b48d41d449d8f71c0b184b38029c26bc"></a><!-- doxytag: member="hptxsts_data::d32" ref="b48d41d449d8f71c0b184b38029c26bc" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhptxsts__data.html#b48d41d449d8f71c0b184b38029c26bc">d32</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">raw register data <br></td></tr>
+<tr><td class="memItemLeft" nowrap><a class="anchor" name="a6839185cc4aeabf771f04f1b2a97ec3"></a><!-- doxytag: member="hptxsts_data::b" ref="a6839185cc4aeabf771f04f1b2a97ec3" args="" -->
+struct {</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhptxsts__data.html#0df6fb1f76396da626715d6ffc06dfa8">ptxfspcavail</a>:16</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhptxsts__data.html#8139e6eafb7b0bbb3cbafa125d5cd28f">ptxqspcavail</a>:8</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhptxsts__data.html#3c8a2ed8f4185130a28a452c0a9967f4">ptxqtop_terminate</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Top of the Periodic Transmit Request Queue<ul>
+<li>bit 24 - Terminate (last entry for the selected channel)</li><li>bits 26:25 - Token Type<ul>
+<li>2'b00 - Zero length</li><li>2'b01 - Ping</li><li>2'b10 - Disable</li></ul>
+</li><li>bits 30:27 - Channel Number</li><li>bit 31 - Odd/even microframe. </li></ul>
+<br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhptxsts__data.html#e51712fd406526683b5c3311bd3dab8d">ptxqtop_token</a>:2</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhptxsts__data.html#6fdf33c3add1fa286beaa252610b20ec">ptxqtop_chnum</a>:4</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhptxsts__data.html#6b18b0bdf10050b08ac265e9143fdd63">ptxqtop_odd</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap valign="top">}&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhptxsts__data.html#a6839185cc4aeabf771f04f1b2a97ec3">b</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">register bits <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l01711">1711</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr>The documentation for this union was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/unionhwcfg1__data.html b/drivers/usb/host/dwc_otg/doc/html/unionhwcfg1__data.html
new file mode 100644
index 000000000000..33ce67eb32fa
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/unionhwcfg1__data.html
@@ -0,0 +1,84 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hwcfg1_data Union Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>hwcfg1_data Union Reference</h1><!-- doxytag: class="hwcfg1_data" -->This union represents the bit fields in the User HW Config1 Register.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="9ca836052f9bd01e0b70902862ed09a4"></a><!-- doxytag: member="hwcfg1_data::d32" ref="9ca836052f9bd01e0b70902862ed09a4" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhwcfg1__data.html#9ca836052f9bd01e0b70902862ed09a4">d32</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">raw register data <br></td></tr>
+<tr><td class="memItemLeft" nowrap><a class="anchor" name="fc54d55ec3ffbba9312c1d0c7611f605"></a><!-- doxytag: member="hwcfg1_data::b" ref="fc54d55ec3ffbba9312c1d0c7611f605" args="" -->
+struct {</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg1__data.html#b58699c49f54de158d6edc4e57716668">ep_dir0</a>:2</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg1__data.html#a62adc1641ef86ed0967061fe0480197">ep_dir1</a>:2</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg1__data.html#03607d2fd2913d3bd20035bc66105e77">ep_dir2</a>:2</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg1__data.html#9beabdd8094db63c0359a7ef22f2266d">ep_dir3</a>:2</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg1__data.html#393899c7a69f9c36ab1b0ef15ab58568">ep_dir4</a>:2</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg1__data.html#ef4cd3ba5b57ad791d1dfc237fcb7b2b">ep_dir5</a>:2</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg1__data.html#1521515b71e5bb03b1102fb3333c1bbc">ep_dir6</a>:2</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg1__data.html#ddc5b4c31dc56456bdca5660d4608f28">ep_dir7</a>:2</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg1__data.html#a0d189caec30660152f1fd3abd1176f2">ep_dir8</a>:2</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg1__data.html#0c21e8d57df291e8d3b2dbb67c52956e">ep_dir9</a>:2</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg1__data.html#1dba400b1d532a89de3f2c4410e9ab4d">ep_dir10</a>:2</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg1__data.html#c5b95969c9c9ffd9f641f7a495e90621">ep_dir11</a>:2</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg1__data.html#a88f6d54f42966f47e77dddd015f5aad">ep_dir12</a>:2</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg1__data.html#708fa9af8f43442846ed4a122cbf5610">ep_dir13</a>:2</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg1__data.html#c930e82427e44ae78db85730665ed2a8">ep_dir14</a>:2</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg1__data.html#cb596169ca88921f58ab84d0a38a4cc8">ep_dir15</a>:2</td></tr>
+
+<tr><td class="memItemLeft" nowrap valign="top">}&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhwcfg1__data.html#fc54d55ec3ffbba9312c1d0c7611f605">b</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">register bits <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This union represents the bit fields in the User HW Config1 Register. 
+<p>
+Read the register into the <em>d32</em> element then read out the bits using the <em>b</em>it elements. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00735">735</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr>The documentation for this union was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/unionhwcfg2__data.html b/drivers/usb/host/dwc_otg/doc/html/unionhwcfg2__data.html
new file mode 100644
index 000000000000..4053c1238783
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/unionhwcfg2__data.html
@@ -0,0 +1,82 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hwcfg2_data Union Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>hwcfg2_data Union Reference</h1><!-- doxytag: class="hwcfg2_data" -->This union represents the bit fields in the User HW Config2 Register.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="2a2482b24bbfa8cdd589e376184d1e3b"></a><!-- doxytag: member="hwcfg2_data::d32" ref="2a2482b24bbfa8cdd589e376184d1e3b" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhwcfg2__data.html#2a2482b24bbfa8cdd589e376184d1e3b">d32</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">raw register data <br></td></tr>
+<tr><td class="memItemLeft" nowrap><a class="anchor" name="9dcc70e2dba617cbc6c12189be5c1d6a"></a><!-- doxytag: member="hwcfg2_data::b" ref="9dcc70e2dba617cbc6c12189be5c1d6a" args="" -->
+struct {</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg2__data.html#592df9b97ff9342b839d2ed76d54c652">op_mode</a>:3</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg2__data.html#e5000f58c6a0f09c75375b4c912af0eb">architecture</a>:2</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg2__data.html#6ef3a94368c53a22c222795bfc2306e3">point2point</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg2__data.html#a248a2502e3c440d7b6e4ad61d396f4e">hs_phy_type</a>:2</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg2__data.html#e75417d7e2d1843abf6e48f67851326e">fs_phy_type</a>:2</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg2__data.html#9f827f334b58643849598ce1fa314c5a">num_dev_ep</a>:4</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg2__data.html#83708a4d45e8d019892367c5ae9f6fd0">num_host_chan</a>:4</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg2__data.html#d0d29d530b38b3dcd58c88a2ef9688bb">perio_ep_supported</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg2__data.html#b6bfbfe650352dec82a02d15677fe88d">dynamic_fifo</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg2__data.html#53c36944e5bd45e6f3ecbe933d7246eb">multi_proc_int</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg2__data.html#a46116164804fe814867f833d03080ac">reserved21</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg2__data.html#1369a191c7bd2f717cef2bce7a97ee67">nonperio_tx_q_depth</a>:2</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg2__data.html#857bb59069e203a94ffd32538c60058f">host_perio_tx_q_depth</a>:2</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg2__data.html#ba242467585b60b4d3db9882e0f39b3f">dev_token_q_depth</a>:5</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg2__data.html#097d9eac7baa9ff9b49198cdd9896885">reserved31</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap valign="top">}&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhwcfg2__data.html#9dcc70e2dba617cbc6c12189be5c1d6a">b</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">register bits <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This union represents the bit fields in the User HW Config2 Register. 
+<p>
+Read the register into the <em>d32</em> element then read out the bits using the <em>b</em>it elements. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00764">764</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr>The documentation for this union was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/unionhwcfg3__data.html b/drivers/usb/host/dwc_otg/doc/html/unionhwcfg3__data.html
new file mode 100644
index 000000000000..cdde7e2d6305
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/unionhwcfg3__data.html
@@ -0,0 +1,76 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hwcfg3_data Union Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>hwcfg3_data Union Reference</h1><!-- doxytag: class="hwcfg3_data" -->This union represents the bit fields in the User HW Config3 Register.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="9daf160f3fc0cc8e4e68c037f6c2f9d7"></a><!-- doxytag: member="hwcfg3_data::d32" ref="9daf160f3fc0cc8e4e68c037f6c2f9d7" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhwcfg3__data.html#9daf160f3fc0cc8e4e68c037f6c2f9d7">d32</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">raw register data <br></td></tr>
+<tr><td class="memItemLeft" nowrap><a class="anchor" name="928c5de42f8af177ce34712123b5093c"></a><!-- doxytag: member="hwcfg3_data::b" ref="928c5de42f8af177ce34712123b5093c" args="" -->
+struct {</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg3__data.html#66f311995decf2f11d620aa6a56fa26e">xfer_size_cntr_width</a>:4</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg3__data.html#a397ea503f5155d8e3a66cc82d7937f2">packet_size_cntr_width</a>:3</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg3__data.html#dcd27bbcb3f0e0f5fbd6e7e8b7db1865">otg_func</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg3__data.html#dd2115f4a4bfa47b2c9c9a7b5f42e203">i2c</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg3__data.html#5008cb6cf85beb23f391e8ccf7306884">vendor_ctrl_if</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg3__data.html#37ea87e07a63864a3b985df59fe98c8d">optional_features</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg3__data.html#2aee57ed6a1fb0c63830b9f3b3754373">synch_reset_type</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg3__data.html#a01a48361a21cb9dfbbd555823b8531b">otg_enable_ic_usb</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg3__data.html#8c83b7ac3a4bb366119aeb3195126445">otg_enable_hsic</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg3__data.html#7ef81a007358254606fa96f0c620f8a8">reserved14</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg3__data.html#2b9c39a4ce021bfd039729ccf2c2c503">otg_lpm_en</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg3__data.html#f885715ddb953dbe95acc08e49264706">dfifo_depth</a>:16</td></tr>
+
+<tr><td class="memItemLeft" nowrap valign="top">}&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhwcfg3__data.html#928c5de42f8af177ce34712123b5093c">b</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">register bits <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This union represents the bit fields in the User HW Config3 Register. 
+<p>
+Read the register into the <em>d32</em> element then read out the bits using the <em>b</em>it elements. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00806">806</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr>The documentation for this union was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/unionhwcfg4__data.html b/drivers/usb/host/dwc_otg/doc/html/unionhwcfg4__data.html
new file mode 100644
index 000000000000..a0e27f721cda
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/unionhwcfg4__data.html
@@ -0,0 +1,80 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hwcfg4_data Union Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>hwcfg4_data Union Reference</h1><!-- doxytag: class="hwcfg4_data" -->This union represents the bit fields in the User HW Config4 Register.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="edcdf66b3add0e05ce0006b0b0de8dd0"></a><!-- doxytag: member="hwcfg4_data::d32" ref="edcdf66b3add0e05ce0006b0b0de8dd0" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhwcfg4__data.html#edcdf66b3add0e05ce0006b0b0de8dd0">d32</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">raw register data <br></td></tr>
+<tr><td class="memItemLeft" nowrap><a class="anchor" name="9fb9175668e2381c568c5adbf6e5225d"></a><!-- doxytag: member="hwcfg4_data::b" ref="9fb9175668e2381c568c5adbf6e5225d" args="" -->
+struct {</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg4__data.html#aee60fb196cf53b610df556744e4d317">num_dev_perio_in_ep</a>:4</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg4__data.html#3227ec0129191d0d099f0dce7f18c546">power_optimiz</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg4__data.html#0a12e214e53ded595dfa11157129ab8c">min_ahb_freq</a>:9</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg4__data.html#31e5336f64bdea1bb8e1e358375b20f0">utmi_phy_data_width</a>:2</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg4__data.html#51130a20d8311e691ea8b8565bbe3080">num_dev_mode_ctrl_ep</a>:4</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg4__data.html#be353f75bb8cd8b14fc5f8db2d51da55">iddig_filt_en</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg4__data.html#5cbe1c265b6623dff23460111142db7d">vbus_valid_filt_en</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg4__data.html#109cd4df5b8b9035bf37aae2cbcbc15e">a_valid_filt_en</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg4__data.html#2f741788949e2fea24c129b1a4e10331">b_valid_filt_en</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg4__data.html#d5dc6949986ee9ac55ccf542b855fddf">session_end_filt_en</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg4__data.html#175e8897d6e3c8ef4026413943de503b">ded_fifo_en</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg4__data.html#753b321350388c5e1307802ff968f9a8">num_in_eps</a>:4</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg4__data.html#988888a48e9088d0e9f889818eb63509">desc_dma</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionhwcfg4__data.html#9562305cf5dd89816939792a66879542">desc_dma_dyn</a>:1</td></tr>
+
+<tr><td class="memItemLeft" nowrap valign="top">}&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionhwcfg4__data.html#9fb9175668e2381c568c5adbf6e5225d">b</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">register bits <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This union represents the bit fields in the User HW Config4 Register. 
+<p>
+Read the register into the <em>d32</em> element then read out the bits using the <em>b</em>it elements. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l00832">832</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr>The documentation for this union was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/doc/html/unionpcgcctl__data.html b/drivers/usb/host/dwc_otg/doc/html/unionpcgcctl__data.html
new file mode 100644
index 000000000000..dc9d6583ede8
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/doc/html/unionpcgcctl__data.html
@@ -0,0 +1,78 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: pcgcctl_data Union Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<!-- Generated by Doxygen 1.4.7 -->
+<div class="tabs">
+  <ul>
+    <li><a href="main.html"><span>Main&nbsp;Page</span></a></li>
+    <li id="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="files.html"><span>Files</span></a></li>
+    <li><a href="pages.html"><span>Related&nbsp;Pages</span></a></li>
+  </ul></div>
+<div class="tabs">
+  <ul>
+    <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+    <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
+  </ul></div>
+<h1>pcgcctl_data Union Reference</h1><!-- doxytag: class="pcgcctl_data" -->This union represents the bit fields in the Power and Clock Gating Control Register.  
+<a href="#_details">More...</a>
+<p>
+<code>#include &lt;<a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>&gt;</code>
+<p>
+<table border="0" cellpadding="0" cellspacing="0">
+<tr><td></td></tr>
+<tr><td colspan="2"><br><h2>Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="abe048ee884143501929b27d94c52db7"></a><!-- doxytag: member="pcgcctl_data::d32" ref="abe048ee884143501929b27d94c52db7" args="" -->
+uint32_t&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionpcgcctl__data.html#abe048ee884143501929b27d94c52db7">d32</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">raw register data <br></td></tr>
+<tr><td class="memItemLeft" nowrap><a class="anchor" name="f2bb76709d0ab9d08280eafb78a36279"></a><!-- doxytag: member="pcgcctl_data::b" ref="f2bb76709d0ab9d08280eafb78a36279" args="" -->
+struct {</td></tr>
+
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionpcgcctl__data.html#bf40184845ef70be8e59b2672cb0bedf">stoppclk</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Stop Pclk. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionpcgcctl__data.html#a3ee36c0e5ea8ae5ac38829337120327">gatehclk</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Gate Hclk. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionpcgcctl__data.html#02d7dff0f26c3ac50ad4b876f1853c17">pwrclmp</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Power Clamp. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionpcgcctl__data.html#9708a50a6e42cd2372d65555edf5cf28">rstpdwnmodule</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Reset Power Down Modules. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionpcgcctl__data.html#c39017c4715319d740b749d16401f26c">physuspended</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">PHY Suspended. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionpcgcctl__data.html#6c18ad3b71ad92e548d0c6d64cc88734">enbl_sleep_gating</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Enable Sleep Clock Gating (Enbl_L1Gating). <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionpcgcctl__data.html#f8b4b268a4fd5094a9a43ec503455f6f">phy_in_sleep</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">PHY In Sleep (PhySleep). <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionpcgcctl__data.html#07232b66695a6bcba4c89477ef13130f">deep_sleep</a>:1</td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Deep Sleep. <br></td></tr>
+<tr><td class="memItemLeft" nowrap>&nbsp;&nbsp;&nbsp;unsigned&nbsp;&nbsp;&nbsp;<a class="el" href="unionpcgcctl__data.html#dc73a75e42509238eed388c3a8a30207">reserved31_8</a>:24</td></tr>
+
+<tr><td class="memItemLeft" nowrap valign="top">}&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionpcgcctl__data.html#f2bb76709d0ab9d08280eafb78a36279">b</a></td></tr>
+
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">register bits <br></td></tr>
+</table>
+<hr><a name="_details"></a><h2>Detailed Description</h2>
+This union represents the bit fields in the Power and Clock Gating Control Register. 
+<p>
+Read the register into the <em>d32</em> member then set/clear the bits using the <em>b</em>it elements. 
+<p>
+
+<p>
+Definition at line <a class="el" href="dwc__otg__regs_8h-source.html#l02210">2210</a> of file <a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a>.<hr>The documentation for this union was generated from the following file:<ul>
+<li><a class="el" href="dwc__otg__regs_8h-source.html">dwc_otg_regs.h</a></ul>
+<hr size="1"><address style="align: right;"><small>Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by&nbsp;
+<a href="http://www.doxygen.org/index.html">
+<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.7 </small></address>
+</body>
+</html>
diff --git a/drivers/usb/host/dwc_otg/dummy_audio.c b/drivers/usb/host/dwc_otg/dummy_audio.c
new file mode 100644
index 000000000000..530ac8bafb82
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/dummy_audio.c
@@ -0,0 +1,1575 @@
+/*
+ * zero.c -- Gadget Zero, for USB development
+ *
+ * Copyright (C) 2003-2004 David Brownell
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions, and the following disclaimer,
+ *    without modification.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The names of the above-listed copyright holders may not be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/*
+ * Gadget Zero only needs two bulk endpoints, and is an example of how you
+ * can write a hardware-agnostic gadget driver running inside a USB device.
+ *
+ * Hardware details are visible (see CONFIG_USB_ZERO_* below) but don't
+ * affect most of the driver.
+ *
+ * Use it with the Linux host/master side "usbtest" driver to get a basic
+ * functional test of your device-side usb stack, or with "usb-skeleton".
+ *
+ * It supports two similar configurations.  One sinks whatever the usb host
+ * writes, and in return sources zeroes.  The other loops whatever the host
+ * writes back, so the host can read it.  Module options include:
+ *
+ *   buflen=N		default N=4096, buffer size used
+ *   qlen=N		default N=32, how many buffers in the loopback queue
+ *   loopdefault	default false, list loopback config first
+ *
+ * Many drivers will only have one configuration, letting them be much
+ * simpler if they also don't support high speed operation (like this
+ * driver does).
+ */
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/ioport.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/smp_lock.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/timer.h>
+#include <linux/list.h>
+#include <linux/interrupt.h>
+#include <linux/uts.h>
+#include <linux/version.h>
+#include <linux/device.h>
+#include <linux/moduleparam.h>
+#include <linux/proc_fs.h>
+
+#include <asm/byteorder.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/system.h>
+#include <asm/unaligned.h>
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)
+# include <linux/usb/ch9.h>
+#else
+# include <linux/usb_ch9.h>
+#endif
+
+#include <linux/usb_gadget.h>
+
+
+/*-------------------------------------------------------------------------*/
+/*-------------------------------------------------------------------------*/
+
+
+static int utf8_to_utf16le(const char *s, u16 *cp, unsigned len)
+{
+	int	count = 0;
+	u8	c;
+	u16	uchar;
+
+	/* this insists on correct encodings, though not minimal ones.
+	 * BUT it currently rejects legit 4-byte UTF-8 code points,
+	 * which need surrogate pairs.  (Unicode 3.1 can use them.)
+	 */
+	while (len != 0 && (c = (u8) *s++) != 0) {
+		if (unlikely(c & 0x80)) {
+			// 2-byte sequence:
+			// 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx
+			if ((c & 0xe0) == 0xc0) {
+				uchar = (c & 0x1f) << 6;
+
+				c = (u8) *s++;
+				if ((c & 0xc0) != 0xc0)
+					goto fail;
+				c &= 0x3f;
+				uchar |= c;
+
+			// 3-byte sequence (most CJKV characters):
+			// zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx
+			} else if ((c & 0xf0) == 0xe0) {
+				uchar = (c & 0x0f) << 12;
+
+				c = (u8) *s++;
+				if ((c & 0xc0) != 0xc0)
+					goto fail;
+				c &= 0x3f;
+				uchar |= c << 6;
+
+				c = (u8) *s++;
+				if ((c & 0xc0) != 0xc0)
+					goto fail;
+				c &= 0x3f;
+				uchar |= c;
+
+				/* no bogus surrogates */
+				if (0xd800 <= uchar && uchar <= 0xdfff)
+					goto fail;
+
+			// 4-byte sequence (surrogate pairs, currently rare):
+			// 11101110wwwwzzzzyy + 110111yyyyxxxxxx
+			//     = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx
+			// (uuuuu = wwww + 1)
+			// FIXME accept the surrogate code points (only)
+
+			} else
+				goto fail;
+		} else
+			uchar = c;
+		put_unaligned (cpu_to_le16 (uchar), cp++);
+		count++;
+		len--;
+	}
+	return count;
+fail:
+	return -1;
+}
+
+
+/**
+ * usb_gadget_get_string - fill out a string descriptor 
+ * @table: of c strings encoded using UTF-8
+ * @id: string id, from low byte of wValue in get string descriptor
+ * @buf: at least 256 bytes
+ *
+ * Finds the UTF-8 string matching the ID, and converts it into a
+ * string descriptor in utf16-le.
+ * Returns length of descriptor (always even) or negative errno
+ *
+ * If your driver needs stings in multiple languages, you'll probably
+ * "switch (wIndex) { ... }"  in your ep0 string descriptor logic,
+ * using this routine after choosing which set of UTF-8 strings to use.
+ * Note that US-ASCII is a strict subset of UTF-8; any string bytes with
+ * the eighth bit set will be multibyte UTF-8 characters, not ISO-8859/1
+ * characters (which are also widely used in C strings).
+ */
+int
+usb_gadget_get_string (struct usb_gadget_strings *table, int id, u8 *buf)
+{
+	struct usb_string	*s;
+	int			len;
+
+	/* descriptor 0 has the language id */
+	if (id == 0) {
+		buf [0] = 4;
+		buf [1] = USB_DT_STRING;
+		buf [2] = (u8) table->language;
+		buf [3] = (u8) (table->language >> 8);
+		return 4;
+	}
+	for (s = table->strings; s && s->s; s++)
+		if (s->id == id)
+			break;
+
+	/* unrecognized: stall. */
+	if (!s || !s->s)
+		return -EINVAL;
+
+	/* string descriptors have length, tag, then UTF16-LE text */
+	len = min ((size_t) 126, strlen (s->s));
+	memset (buf + 2, 0, 2 * len);	/* zero all the bytes */
+	len = utf8_to_utf16le(s->s, (u16 *)&buf[2], len);
+	if (len < 0)
+		return -EINVAL;
+	buf [0] = (len + 1) * 2;
+	buf [1] = USB_DT_STRING;
+	return buf [0];
+}
+
+
+/*-------------------------------------------------------------------------*/
+/*-------------------------------------------------------------------------*/
+
+
+/**
+ * usb_descriptor_fillbuf - fill buffer with descriptors
+ * @buf: Buffer to be filled
+ * @buflen: Size of buf
+ * @src: Array of descriptor pointers, terminated by null pointer.
+ *
+ * Copies descriptors into the buffer, returning the length or a
+ * negative error code if they can't all be copied.  Useful when
+ * assembling descriptors for an associated set of interfaces used
+ * as part of configuring a composite device; or in other cases where
+ * sets of descriptors need to be marshaled.
+ */
+int
+usb_descriptor_fillbuf(void *buf, unsigned buflen,
+		const struct usb_descriptor_header **src)
+{
+	u8	*dest = buf;
+
+	if (!src)
+		return -EINVAL;
+
+	/* fill buffer from src[] until null descriptor ptr */
+	for (; 0 != *src; src++) {
+		unsigned		len = (*src)->bLength;
+
+		if (len > buflen)
+			return -EINVAL;
+		memcpy(dest, *src, len);
+		buflen -= len;
+		dest += len;
+	}
+	return dest - (u8 *)buf;
+}
+
+
+/**
+ * usb_gadget_config_buf - builts a complete configuration descriptor
+ * @config: Header for the descriptor, including characteristics such
+ *	as power requirements and number of interfaces.
+ * @desc: Null-terminated vector of pointers to the descriptors (interface,
+ *	endpoint, etc) defining all functions in this device configuration.
+ * @buf: Buffer for the resulting configuration descriptor.
+ * @length: Length of buffer.  If this is not big enough to hold the
+ *	entire configuration descriptor, an error code will be returned.
+ *
+ * This copies descriptors into the response buffer, building a descriptor
+ * for that configuration.  It returns the buffer length or a negative
+ * status code.  The config.wTotalLength field is set to match the length
+ * of the result, but other descriptor fields (including power usage and
+ * interface count) must be set by the caller.
+ *
+ * Gadget drivers could use this when constructing a config descriptor
+ * in response to USB_REQ_GET_DESCRIPTOR.  They will need to patch the
+ * resulting bDescriptorType value if USB_DT_OTHER_SPEED_CONFIG is needed.
+ */
+int usb_gadget_config_buf(
+	const struct usb_config_descriptor	*config,
+	void					*buf,
+	unsigned				length,
+	const struct usb_descriptor_header	**desc
+)
+{
+	struct usb_config_descriptor		*cp = buf;
+	int					len;
+
+	/* config descriptor first */
+	if (length < USB_DT_CONFIG_SIZE || !desc)
+		return -EINVAL;
+	*cp = *config; 
+
+	/* then interface/endpoint/class/vendor/... */
+	len = usb_descriptor_fillbuf(USB_DT_CONFIG_SIZE + (u8*)buf,
+			length - USB_DT_CONFIG_SIZE, desc);
+	if (len < 0)
+		return len;
+	len += USB_DT_CONFIG_SIZE;
+	if (len > 0xffff)
+		return -EINVAL;
+
+	/* patch up the config descriptor */
+	cp->bLength = USB_DT_CONFIG_SIZE;
+	cp->bDescriptorType = USB_DT_CONFIG;
+	cp->wTotalLength = cpu_to_le16(len);
+	cp->bmAttributes |= USB_CONFIG_ATT_ONE;
+	return len;
+}
+
+/*-------------------------------------------------------------------------*/
+/*-------------------------------------------------------------------------*/
+
+
+#define RBUF_LEN (1024*1024)
+static int rbuf_start;
+static int rbuf_len;
+static __u8 rbuf[RBUF_LEN];
+
+/*-------------------------------------------------------------------------*/
+
+#define DRIVER_VERSION		"St Patrick's Day 2004"
+
+static const char shortname [] = "zero";
+static const char longname [] = "YAMAHA YST-MS35D USB Speaker  ";
+
+static const char source_sink [] = "source and sink data";
+static const char loopback [] = "loop input to output";
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * driver assumes self-powered hardware, and
+ * has no way for users to trigger remote wakeup.
+ *
+ * this version autoconfigures as much as possible,
+ * which is reasonable for most "bulk-only" drivers.
+ */
+static const char *EP_IN_NAME;		/* source */
+static const char *EP_OUT_NAME;		/* sink */
+
+/*-------------------------------------------------------------------------*/
+
+/* big enough to hold our biggest descriptor */
+#define USB_BUFSIZ	512
+
+struct zero_dev {
+	spinlock_t		lock;
+	struct usb_gadget	*gadget;
+	struct usb_request	*req;		/* for control responses */
+
+	/* when configured, we have one of two configs:
+	 * - source data (in to host) and sink it (out from host)
+	 * - or loop it back (out from host back in to host)
+	 */
+	u8			config;
+	struct usb_ep		*in_ep, *out_ep;
+
+	/* autoresume timer */
+	struct timer_list	resume;
+};
+
+#define xprintk(d,level,fmt,args...) \
+	dev_printk(level , &(d)->gadget->dev , fmt , ## args)
+
+#ifdef DEBUG
+#define DBG(dev,fmt,args...) \
+	xprintk(dev , KERN_DEBUG , fmt , ## args)
+#else
+#define DBG(dev,fmt,args...) \
+	do { } while (0)
+#endif /* DEBUG */
+
+#ifdef VERBOSE
+#define VDBG	DBG
+#else
+#define VDBG(dev,fmt,args...) \
+	do { } while (0)
+#endif /* VERBOSE */
+
+#define ERROR(dev,fmt,args...) \
+	xprintk(dev , KERN_ERR , fmt , ## args)
+#define WARN(dev,fmt,args...) \
+	xprintk(dev , KERN_WARNING , fmt , ## args)
+#define INFO(dev,fmt,args...) \
+	xprintk(dev , KERN_INFO , fmt , ## args)
+
+/*-------------------------------------------------------------------------*/
+
+static unsigned buflen = 4096;
+static unsigned qlen = 32;
+static unsigned pattern = 0;
+
+module_param (buflen, uint, S_IRUGO|S_IWUSR);
+module_param (qlen, uint, S_IRUGO|S_IWUSR);
+module_param (pattern, uint, S_IRUGO|S_IWUSR);
+
+/*
+ * if it's nonzero, autoresume says how many seconds to wait
+ * before trying to wake up the host after suspend.
+ */
+static unsigned autoresume = 0;
+module_param (autoresume, uint, 0);
+
+/*
+ * Normally the "loopback" configuration is second (index 1) so
+ * it's not the default.  Here's where to change that order, to
+ * work better with hosts where config changes are problematic.
+ * Or controllers (like superh) that only support one config.
+ */
+static int loopdefault = 0;
+
+module_param (loopdefault, bool, S_IRUGO|S_IWUSR);
+
+/*-------------------------------------------------------------------------*/
+
+/* Thanks to NetChip Technologies for donating this product ID.
+ *
+ * DO NOT REUSE THESE IDs with a protocol-incompatible driver!!  Ever!!
+ * Instead:  allocate your own, using normal USB-IF procedures.
+ */
+#ifndef	CONFIG_USB_ZERO_HNPTEST
+#define DRIVER_VENDOR_NUM	0x0525		/* NetChip */
+#define DRIVER_PRODUCT_NUM	0xa4a0		/* Linux-USB "Gadget Zero" */
+#else
+#define DRIVER_VENDOR_NUM	0x1a0a		/* OTG test device IDs */
+#define DRIVER_PRODUCT_NUM	0xbadd
+#endif
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * DESCRIPTORS ... most are static, but strings and (full)
+ * configuration descriptors are built on demand.
+ */
+
+/*
+#define STRING_MANUFACTURER		25
+#define STRING_PRODUCT			42
+#define STRING_SERIAL			101
+*/
+#define STRING_MANUFACTURER		1
+#define STRING_PRODUCT			2
+#define STRING_SERIAL			3
+
+#define STRING_SOURCE_SINK		250
+#define STRING_LOOPBACK			251
+
+/*
+ * This device advertises two configurations; these numbers work
+ * on a pxa250 as well as more flexible hardware.
+ */
+#define	CONFIG_SOURCE_SINK	3
+#define	CONFIG_LOOPBACK		2
+
+/*
+static struct usb_device_descriptor
+device_desc = {
+	.bLength =		sizeof device_desc,
+	.bDescriptorType =	USB_DT_DEVICE,
+
+	.bcdUSB =		__constant_cpu_to_le16 (0x0200),
+	.bDeviceClass =		USB_CLASS_VENDOR_SPEC,
+
+	.idVendor =		__constant_cpu_to_le16 (DRIVER_VENDOR_NUM),
+	.idProduct =		__constant_cpu_to_le16 (DRIVER_PRODUCT_NUM),
+	.iManufacturer =	STRING_MANUFACTURER,
+	.iProduct =		STRING_PRODUCT,
+	.iSerialNumber =	STRING_SERIAL,
+	.bNumConfigurations =	2,
+};
+*/
+static struct usb_device_descriptor
+device_desc = {
+	.bLength =		sizeof device_desc,
+	.bDescriptorType =	USB_DT_DEVICE,
+	.bcdUSB =		__constant_cpu_to_le16 (0x0100),
+	.bDeviceClass =		USB_CLASS_PER_INTERFACE,
+	.bDeviceSubClass =      0,
+	.bDeviceProtocol =      0,
+	.bMaxPacketSize0 =      64,
+	.bcdDevice =            __constant_cpu_to_le16 (0x0100),
+	.idVendor =		__constant_cpu_to_le16 (0x0499),
+	.idProduct =		__constant_cpu_to_le16 (0x3002),
+	.iManufacturer =	STRING_MANUFACTURER,
+	.iProduct =		STRING_PRODUCT,
+	.iSerialNumber =	STRING_SERIAL,
+	.bNumConfigurations =	1,
+};
+
+static struct usb_config_descriptor
+z_config = {
+	.bLength =		sizeof z_config,
+	.bDescriptorType =	USB_DT_CONFIG,
+
+	/* compute wTotalLength on the fly */
+	.bNumInterfaces =	2,
+	.bConfigurationValue =	1,
+	.iConfiguration =	0,
+	.bmAttributes =		0x40,
+	.bMaxPower =		0,	/* self-powered */
+};
+
+
+static struct usb_otg_descriptor
+otg_descriptor = {
+	.bLength =		sizeof otg_descriptor,
+	.bDescriptorType =	USB_DT_OTG,
+
+	.bmAttributes =		USB_OTG_SRP,
+};
+
+/* one interface in each configuration */
+#ifdef	CONFIG_USB_GADGET_DUALSPEED
+
+/*
+ * usb 2.0 devices need to expose both high speed and full speed
+ * descriptors, unless they only run at full speed.
+ *
+ * that means alternate endpoint descriptors (bigger packets)
+ * and a "device qualifier" ... plus more construction options
+ * for the config descriptor.
+ */
+
+static struct usb_qualifier_descriptor
+dev_qualifier = {
+	.bLength =		sizeof dev_qualifier,
+	.bDescriptorType =	USB_DT_DEVICE_QUALIFIER,
+
+	.bcdUSB =		__constant_cpu_to_le16 (0x0200),
+	.bDeviceClass =		USB_CLASS_VENDOR_SPEC,
+
+	.bNumConfigurations =	2,
+};
+
+
+struct usb_cs_as_general_descriptor {
+	__u8  bLength;
+	__u8  bDescriptorType;
+
+	__u8  bDescriptorSubType;
+	__u8  bTerminalLink;
+	__u8  bDelay;
+	__u16  wFormatTag;
+} __attribute__ ((packed));
+
+struct usb_cs_as_format_descriptor {
+	__u8  bLength;
+	__u8  bDescriptorType;
+
+	__u8  bDescriptorSubType;
+	__u8  bFormatType;
+	__u8  bNrChannels;
+	__u8  bSubframeSize;
+	__u8  bBitResolution;
+	__u8  bSamfreqType;
+	__u8  tLowerSamFreq[3];
+	__u8  tUpperSamFreq[3];
+} __attribute__ ((packed));
+
+static const struct usb_interface_descriptor
+z_audio_control_if_desc = {
+	.bLength =		sizeof z_audio_control_if_desc,
+	.bDescriptorType =	USB_DT_INTERFACE,
+	.bInterfaceNumber = 0,
+	.bAlternateSetting = 0,
+	.bNumEndpoints = 0,
+	.bInterfaceClass = USB_CLASS_AUDIO,
+	.bInterfaceSubClass = 0x1,
+	.bInterfaceProtocol = 0,
+	.iInterface = 0,
+};
+
+static const struct usb_interface_descriptor
+z_audio_if_desc = {
+	.bLength =		sizeof z_audio_if_desc,
+	.bDescriptorType =	USB_DT_INTERFACE,
+	.bInterfaceNumber = 1,
+	.bAlternateSetting = 0,
+	.bNumEndpoints = 0,
+	.bInterfaceClass = USB_CLASS_AUDIO,
+	.bInterfaceSubClass = 0x2,
+	.bInterfaceProtocol = 0,
+	.iInterface = 0,
+};
+
+static const struct usb_interface_descriptor
+z_audio_if_desc2 = {
+	.bLength =		sizeof z_audio_if_desc,
+	.bDescriptorType =	USB_DT_INTERFACE,
+	.bInterfaceNumber = 1,
+	.bAlternateSetting = 1,
+	.bNumEndpoints = 1,
+	.bInterfaceClass = USB_CLASS_AUDIO,
+	.bInterfaceSubClass = 0x2,
+	.bInterfaceProtocol = 0,
+	.iInterface = 0,
+};
+
+static const struct usb_cs_as_general_descriptor
+z_audio_cs_as_if_desc = {
+	.bLength = 7,
+	.bDescriptorType = 0x24,
+	
+	.bDescriptorSubType = 0x01,
+	.bTerminalLink = 0x01,
+	.bDelay = 0x0,
+	.wFormatTag = __constant_cpu_to_le16 (0x0001)
+};
+
+
+static const struct usb_cs_as_format_descriptor 
+z_audio_cs_as_format_desc = {
+	.bLength = 0xe,
+	.bDescriptorType = 0x24,
+	
+	.bDescriptorSubType = 2,
+	.bFormatType = 1,
+	.bNrChannels = 1,
+	.bSubframeSize = 1,
+	.bBitResolution = 8,
+	.bSamfreqType = 0,
+	.tLowerSamFreq = {0x7e, 0x13, 0x00},
+	.tUpperSamFreq = {0xe2, 0xd6, 0x00},
+};
+
+static const struct usb_endpoint_descriptor 
+z_iso_ep = {
+	.bLength = 0x09,
+	.bDescriptorType = 0x05,
+	.bEndpointAddress = 0x04,
+	.bmAttributes = 0x09,
+	.wMaxPacketSize = 0x0038,
+	.bInterval = 0x01,
+	.bRefresh = 0x00,
+	.bSynchAddress = 0x00,	
+};
+
+static char z_iso_ep2[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
+
+// 9 bytes
+static char z_ac_interface_header_desc[] = 
+{ 0x09, 0x24, 0x01, 0x00, 0x01, 0x2b, 0x00, 0x01, 0x01 };
+
+// 12 bytes
+static char z_0[] = {0x0c, 0x24, 0x02, 0x01, 0x01, 0x01, 0x00, 0x02, 
+		     0x03, 0x00, 0x00, 0x00};
+// 13 bytes
+static char z_1[] = {0x0d, 0x24, 0x06, 0x02, 0x01, 0x02, 0x15, 0x00, 
+		     0x02, 0x00, 0x02, 0x00, 0x00};
+// 9 bytes
+static char z_2[] = {0x09, 0x24, 0x03, 0x03, 0x01, 0x03, 0x00, 0x02, 
+		     0x00};
+
+static char za_0[] = {0x09, 0x04, 0x01, 0x02, 0x01, 0x01, 0x02, 0x00, 
+		      0x00};
+
+static char za_1[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
+
+static char za_2[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x01, 0x08, 0x00, 
+		      0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
+
+static char za_3[] = {0x09, 0x05, 0x04, 0x09, 0x70, 0x00, 0x01, 0x00,
+		      0x00};
+
+static char za_4[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
+
+static char za_5[] = {0x09, 0x04, 0x01, 0x03, 0x01, 0x01, 0x02, 0x00,
+		      0x00};
+
+static char za_6[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
+
+static char za_7[] = {0x0e, 0x24, 0x02, 0x01, 0x01, 0x02, 0x10, 0x00,
+		      0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
+
+static char za_8[] = {0x09, 0x05, 0x04, 0x09, 0x70, 0x00, 0x01, 0x00,
+		      0x00};
+
+static char za_9[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
+
+static char za_10[] = {0x09, 0x04, 0x01, 0x04, 0x01, 0x01, 0x02, 0x00,
+		       0x00};
+
+static char za_11[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
+
+static char za_12[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x02, 0x10, 0x00,
+		       0x73, 0x13, 0x00, 0xe2, 0xd6, 0x00};
+
+static char za_13[] = {0x09, 0x05, 0x04, 0x09, 0xe0, 0x00, 0x01, 0x00,
+		       0x00};
+
+static char za_14[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
+
+static char za_15[] = {0x09, 0x04, 0x01, 0x05, 0x01, 0x01, 0x02, 0x00, 
+		       0x00};
+
+static char za_16[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
+
+static char za_17[] = {0x0e, 0x24, 0x02, 0x01, 0x01, 0x03, 0x14, 0x00, 
+		       0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
+
+static char za_18[] = {0x09, 0x05, 0x04, 0x09, 0xa8, 0x00, 0x01, 0x00,
+		       0x00};
+
+static char za_19[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
+
+static char za_20[] = {0x09, 0x04, 0x01, 0x06, 0x01, 0x01, 0x02, 0x00,
+		       0x00};
+
+static char za_21[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
+
+static char za_22[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x03, 0x14, 0x00, 
+		       0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
+
+static char za_23[] = {0x09, 0x05, 0x04, 0x09, 0x50, 0x01, 0x01, 0x00,
+		       0x00};
+
+static char za_24[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
+
+
+
+static const struct usb_descriptor_header *z_function [] = {
+	(struct usb_descriptor_header *) &z_audio_control_if_desc,
+	(struct usb_descriptor_header *) &z_ac_interface_header_desc,
+	(struct usb_descriptor_header *) &z_0,
+	(struct usb_descriptor_header *) &z_1,
+	(struct usb_descriptor_header *) &z_2,
+	(struct usb_descriptor_header *) &z_audio_if_desc,
+	(struct usb_descriptor_header *) &z_audio_if_desc2,
+	(struct usb_descriptor_header *) &z_audio_cs_as_if_desc,
+	(struct usb_descriptor_header *) &z_audio_cs_as_format_desc,
+	(struct usb_descriptor_header *) &z_iso_ep,
+	(struct usb_descriptor_header *) &z_iso_ep2,
+	(struct usb_descriptor_header *) &za_0,
+	(struct usb_descriptor_header *) &za_1,
+	(struct usb_descriptor_header *) &za_2,
+	(struct usb_descriptor_header *) &za_3,
+	(struct usb_descriptor_header *) &za_4,
+	(struct usb_descriptor_header *) &za_5,
+	(struct usb_descriptor_header *) &za_6,
+	(struct usb_descriptor_header *) &za_7,
+	(struct usb_descriptor_header *) &za_8,
+	(struct usb_descriptor_header *) &za_9,
+	(struct usb_descriptor_header *) &za_10,
+	(struct usb_descriptor_header *) &za_11,
+	(struct usb_descriptor_header *) &za_12,
+	(struct usb_descriptor_header *) &za_13,
+	(struct usb_descriptor_header *) &za_14,
+	(struct usb_descriptor_header *) &za_15,
+	(struct usb_descriptor_header *) &za_16,
+	(struct usb_descriptor_header *) &za_17,
+	(struct usb_descriptor_header *) &za_18,
+	(struct usb_descriptor_header *) &za_19,
+	(struct usb_descriptor_header *) &za_20,
+	(struct usb_descriptor_header *) &za_21,
+	(struct usb_descriptor_header *) &za_22,
+	(struct usb_descriptor_header *) &za_23,
+	(struct usb_descriptor_header *) &za_24,
+	NULL,
+};
+
+/* maxpacket and other transfer characteristics vary by speed. */
+#define ep_desc(g,hs,fs) (((g)->speed==USB_SPEED_HIGH)?(hs):(fs))
+
+#else
+
+/* if there's no high speed support, maxpacket doesn't change. */
+#define ep_desc(g,hs,fs) fs
+
+#endif	/* !CONFIG_USB_GADGET_DUALSPEED */
+
+static char				manufacturer [40];
+//static char				serial [40];
+static char				serial [] = "Ser 00 em";
+
+/* static strings, in UTF-8 */
+static struct usb_string		strings [] = {
+	{ STRING_MANUFACTURER, manufacturer, },
+	{ STRING_PRODUCT, longname, },
+	{ STRING_SERIAL, serial, },
+	{ STRING_LOOPBACK, loopback, },
+	{ STRING_SOURCE_SINK, source_sink, },
+	{  }			/* end of list */
+};
+
+static struct usb_gadget_strings	stringtab = {
+	.language	= 0x0409,	/* en-us */
+	.strings	= strings,
+};
+
+/*
+ * config descriptors are also handcrafted.  these must agree with code
+ * that sets configurations, and with code managing interfaces and their
+ * altsettings.  other complexity may come from:
+ *
+ *  - high speed support, including "other speed config" rules
+ *  - multiple configurations
+ *  - interfaces with alternate settings
+ *  - embedded class or vendor-specific descriptors
+ *
+ * this handles high speed, and has a second config that could as easily
+ * have been an alternate interface setting (on most hardware).
+ *
+ * NOTE:  to demonstrate (and test) more USB capabilities, this driver
+ * should include an altsetting to test interrupt transfers, including
+ * high bandwidth modes at high speed.  (Maybe work like Intel's test
+ * device?)
+ */
+static int
+config_buf (struct usb_gadget *gadget, u8 *buf, u8 type, unsigned index)
+{
+	int len;
+	const struct usb_descriptor_header **function;
+	
+	function = z_function;
+	len = usb_gadget_config_buf (&z_config, buf, USB_BUFSIZ, function);
+	if (len < 0)
+		return len;
+	((struct usb_config_descriptor *) buf)->bDescriptorType = type;
+	return len;
+}
+
+/*-------------------------------------------------------------------------*/
+
+static struct usb_request *
+alloc_ep_req (struct usb_ep *ep, unsigned length)
+{
+	struct usb_request	*req;
+
+	req = usb_ep_alloc_request (ep, GFP_ATOMIC);
+	if (req) {
+		req->length = length;
+		req->buf = usb_ep_alloc_buffer (ep, length,
+				&req->dma, GFP_ATOMIC);
+		if (!req->buf) {
+			usb_ep_free_request (ep, req);
+			req = NULL;
+		}
+	}
+	return req;
+}
+
+static void free_ep_req (struct usb_ep *ep, struct usb_request *req)
+{
+	if (req->buf)
+		usb_ep_free_buffer (ep, req->buf, req->dma, req->length);
+	usb_ep_free_request (ep, req);
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* optionally require specific source/sink data patterns  */
+
+static int
+check_read_data (
+	struct zero_dev		*dev,
+	struct usb_ep		*ep,
+	struct usb_request	*req
+)
+{
+	unsigned	i;
+	u8		*buf = req->buf;
+
+	for (i = 0; i < req->actual; i++, buf++) {
+		switch (pattern) {
+		/* all-zeroes has no synchronization issues */
+		case 0:
+			if (*buf == 0)
+				continue;
+			break;
+		/* mod63 stays in sync with short-terminated transfers,
+		 * or otherwise when host and gadget agree on how large
+		 * each usb transfer request should be.  resync is done
+		 * with set_interface or set_config.
+		 */
+		case 1:
+			if (*buf == (u8)(i % 63))
+				continue;
+			break;
+		}
+		ERROR (dev, "bad OUT byte, buf [%d] = %d\n", i, *buf);
+		usb_ep_set_halt (ep);
+		return -EINVAL;
+	}
+	return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+static void zero_reset_config (struct zero_dev *dev)
+{
+	if (dev->config == 0)
+		return;
+
+	DBG (dev, "reset config\n");
+
+	/* just disable endpoints, forcing completion of pending i/o.
+	 * all our completion handlers free their requests in this case.
+	 */
+	if (dev->in_ep) {
+		usb_ep_disable (dev->in_ep);
+		dev->in_ep = NULL;
+	}
+	if (dev->out_ep) {
+		usb_ep_disable (dev->out_ep);
+		dev->out_ep = NULL;
+	}
+	dev->config = 0;
+	del_timer (&dev->resume);
+}
+
+#define _write(f, buf, sz) (f->f_op->write(f, buf, sz, &f->f_pos))
+
+static void 
+zero_isoc_complete (struct usb_ep *ep, struct usb_request *req)
+{
+	struct zero_dev	*dev = ep->driver_data;
+	int		status = req->status;
+	int i, j;
+
+	switch (status) {
+
+	case 0: 			/* normal completion? */
+		//printk ("\nzero ---------------> isoc normal completion %d bytes\n", req->actual);
+		for (i=0, j=rbuf_start; i<req->actual; i++) {
+			//printk ("%02x ", ((__u8*)req->buf)[i]);
+			rbuf[j] = ((__u8*)req->buf)[i];
+			j++;
+			if (j >= RBUF_LEN) j=0;
+		}
+		rbuf_start = j;
+		//printk ("\n\n");
+
+		if (rbuf_len < RBUF_LEN) {
+			rbuf_len += req->actual;
+			if (rbuf_len > RBUF_LEN) {
+				rbuf_len = RBUF_LEN;
+			}
+		}
+
+		break;
+
+	/* this endpoint is normally active while we're configured */
+	case -ECONNABORTED: 		/* hardware forced ep reset */
+	case -ECONNRESET:		/* request dequeued */
+	case -ESHUTDOWN:		/* disconnect from host */
+		VDBG (dev, "%s gone (%d), %d/%d\n", ep->name, status,
+				req->actual, req->length);
+		if (ep == dev->out_ep)
+			check_read_data (dev, ep, req);
+		free_ep_req (ep, req);
+		return;
+
+	case -EOVERFLOW:		/* buffer overrun on read means that
+					 * we didn't provide a big enough
+					 * buffer.
+					 */
+	default:
+#if 1
+		DBG (dev, "%s complete --> %d, %d/%d\n", ep->name,
+				status, req->actual, req->length);
+#endif
+	case -EREMOTEIO:		/* short read */
+		break;
+	}
+
+	status = usb_ep_queue (ep, req, GFP_ATOMIC);
+	if (status) {
+		ERROR (dev, "kill %s:  resubmit %d bytes --> %d\n",
+				ep->name, req->length, status);
+		usb_ep_set_halt (ep);
+		/* FIXME recover later ... somehow */
+	}
+}
+
+static struct usb_request *
+zero_start_isoc_ep (struct usb_ep *ep, int gfp_flags)
+{
+	struct usb_request	*req;
+	int			status;
+
+	req = alloc_ep_req (ep, 512);
+	if (!req)
+		return NULL;
+
+	req->complete = zero_isoc_complete;
+
+	status = usb_ep_queue (ep, req, gfp_flags);
+	if (status) {
+		struct zero_dev	*dev = ep->driver_data;
+
+		ERROR (dev, "start %s --> %d\n", ep->name, status);
+		free_ep_req (ep, req);
+		req = NULL;
+	}
+
+	return req;
+}
+
+/* change our operational config.  this code must agree with the code
+ * that returns config descriptors, and altsetting code.
+ *
+ * it's also responsible for power management interactions. some
+ * configurations might not work with our current power sources.
+ *
+ * note that some device controller hardware will constrain what this
+ * code can do, perhaps by disallowing more than one configuration or
+ * by limiting configuration choices (like the pxa2xx).
+ */
+static int
+zero_set_config (struct zero_dev *dev, unsigned number, int gfp_flags)
+{
+	int			result = 0;
+	struct usb_gadget	*gadget = dev->gadget;
+	const struct usb_endpoint_descriptor	*d;
+	struct usb_ep		*ep;
+
+	if (number == dev->config)
+		return 0;
+
+	zero_reset_config (dev);
+
+	gadget_for_each_ep (ep, gadget) {
+
+		if (strcmp (ep->name, "ep4") == 0) {
+
+			d = (struct usb_endpoint_descripter *)&za_23; // isoc ep desc for audio i/f alt setting 6
+			result = usb_ep_enable (ep, d);
+
+			if (result == 0) {
+				ep->driver_data = dev;
+				dev->in_ep = ep;
+
+				if (zero_start_isoc_ep (ep, gfp_flags) != 0) {
+
+					dev->in_ep = ep;
+					continue;
+				}
+
+				usb_ep_disable (ep);
+				result = -EIO;
+			}
+		}
+
+	}
+
+	dev->config = number;
+	return result;
+}
+
+/*-------------------------------------------------------------------------*/
+
+static void zero_setup_complete (struct usb_ep *ep, struct usb_request *req)
+{
+	if (req->status || req->actual != req->length)
+		DBG ((struct zero_dev *) ep->driver_data,
+				"setup complete --> %d, %d/%d\n",
+				req->status, req->actual, req->length);
+}
+
+/*
+ * The setup() callback implements all the ep0 functionality that's
+ * not handled lower down, in hardware or the hardware driver (like
+ * device and endpoint feature flags, and their status).  It's all
+ * housekeeping for the gadget function we're implementing.  Most of
+ * the work is in config-specific setup.
+ */
+static int
+zero_setup (struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl)
+{
+	struct zero_dev		*dev = get_gadget_data (gadget);
+	struct usb_request	*req = dev->req;
+	int			value = -EOPNOTSUPP;
+
+	/* usually this stores reply data in the pre-allocated ep0 buffer,
+	 * but config change events will reconfigure hardware.
+	 */
+	req->zero = 0;
+	switch (ctrl->bRequest) {
+
+	case USB_REQ_GET_DESCRIPTOR:
+
+		switch (ctrl->wValue >> 8) {
+
+		case USB_DT_DEVICE:
+			value = min (ctrl->wLength, (u16) sizeof device_desc);
+			memcpy (req->buf, &device_desc, value);
+			break;
+#ifdef CONFIG_USB_GADGET_DUALSPEED
+		case USB_DT_DEVICE_QUALIFIER:
+			if (!gadget->is_dualspeed)
+				break;
+			value = min (ctrl->wLength, (u16) sizeof dev_qualifier);
+			memcpy (req->buf, &dev_qualifier, value);
+			break;
+
+		case USB_DT_OTHER_SPEED_CONFIG:
+			if (!gadget->is_dualspeed)
+				break;
+			// FALLTHROUGH
+#endif /* CONFIG_USB_GADGET_DUALSPEED */
+		case USB_DT_CONFIG:
+			value = config_buf (gadget, req->buf,
+					ctrl->wValue >> 8,
+					ctrl->wValue & 0xff);
+			if (value >= 0)
+				value = min (ctrl->wLength, (u16) value);
+			break;
+
+		case USB_DT_STRING:
+			/* wIndex == language code.
+			 * this driver only handles one language, you can
+			 * add string tables for other languages, using
+			 * any UTF-8 characters
+			 */
+			value = usb_gadget_get_string (&stringtab,
+					ctrl->wValue & 0xff, req->buf);
+			if (value >= 0) {
+				value = min (ctrl->wLength, (u16) value);
+			}
+			break;
+		}
+		break;
+
+	/* currently two configs, two speeds */
+	case USB_REQ_SET_CONFIGURATION:
+		if (ctrl->bRequestType != 0)
+			goto unknown;
+
+		spin_lock (&dev->lock);
+		value = zero_set_config (dev, ctrl->wValue, GFP_ATOMIC);
+		spin_unlock (&dev->lock);
+		break;
+	case USB_REQ_GET_CONFIGURATION:
+		if (ctrl->bRequestType != USB_DIR_IN)
+			goto unknown;
+		*(u8 *)req->buf = dev->config;
+		value = min (ctrl->wLength, (u16) 1);
+		break;
+
+	/* until we add altsetting support, or other interfaces,
+	 * only 0/0 are possible.  pxa2xx only supports 0/0 (poorly)
+	 * and already killed pending endpoint I/O.
+	 */
+	case USB_REQ_SET_INTERFACE:
+
+		if (ctrl->bRequestType != USB_RECIP_INTERFACE)
+			goto unknown;
+		spin_lock (&dev->lock);
+		if (dev->config) {
+			u8		config = dev->config;
+
+			/* resets interface configuration, forgets about
+			 * previous transaction state (queued bufs, etc)
+			 * and re-inits endpoint state (toggle etc)
+			 * no response queued, just zero status == success.
+			 * if we had more than one interface we couldn't
+			 * use this "reset the config" shortcut.
+			 */
+			zero_reset_config (dev);
+			zero_set_config (dev, config, GFP_ATOMIC);
+			value = 0;
+		}
+		spin_unlock (&dev->lock);
+		break;
+	case USB_REQ_GET_INTERFACE:
+		if ((ctrl->bRequestType == 0x21) && (ctrl->wIndex == 0x02)) {
+			value = ctrl->wLength;
+			break;
+		}
+		else {
+			if (ctrl->bRequestType != (USB_DIR_IN|USB_RECIP_INTERFACE))
+				goto unknown;
+			if (!dev->config)
+				break;
+			if (ctrl->wIndex != 0) {
+				value = -EDOM;
+				break;
+			}
+			*(u8 *)req->buf = 0;
+			value = min (ctrl->wLength, (u16) 1);
+		}
+		break;
+
+	/*
+	 * These are the same vendor-specific requests supported by
+	 * Intel's USB 2.0 compliance test devices.  We exceed that
+	 * device spec by allowing multiple-packet requests.
+	 */
+	case 0x5b:	/* control WRITE test -- fill the buffer */
+		if (ctrl->bRequestType != (USB_DIR_OUT|USB_TYPE_VENDOR))
+			goto unknown;
+		if (ctrl->wValue || ctrl->wIndex)
+			break;
+		/* just read that many bytes into the buffer */
+		if (ctrl->wLength > USB_BUFSIZ)
+			break;
+		value = ctrl->wLength;
+		break;
+	case 0x5c:	/* control READ test -- return the buffer */
+		if (ctrl->bRequestType != (USB_DIR_IN|USB_TYPE_VENDOR))
+			goto unknown;
+		if (ctrl->wValue || ctrl->wIndex)
+			break;
+		/* expect those bytes are still in the buffer; send back */
+		if (ctrl->wLength > USB_BUFSIZ
+				|| ctrl->wLength != req->length)
+			break;
+		value = ctrl->wLength;
+		break;
+
+	case 0x01: // SET_CUR
+	case 0x02:
+	case 0x03:
+	case 0x04:
+	case 0x05:
+		value = ctrl->wLength;
+		break;
+	case 0x81:
+		switch (ctrl->wValue) {
+		case 0x0201:
+		case 0x0202:
+			((u8*)req->buf)[0] = 0x00;
+			((u8*)req->buf)[1] = 0xe3;
+			break;
+		case 0x0300:
+		case 0x0500:
+			((u8*)req->buf)[0] = 0x00;
+			break;
+		}
+		//((u8*)req->buf)[0] = 0x81;
+		//((u8*)req->buf)[1] = 0x81;
+		value = ctrl->wLength;
+		break;
+	case 0x82:
+		switch (ctrl->wValue) {
+		case 0x0201:
+		case 0x0202:
+			((u8*)req->buf)[0] = 0x00;
+			((u8*)req->buf)[1] = 0xc3;
+			break;
+		case 0x0300:
+		case 0x0500:
+			((u8*)req->buf)[0] = 0x00;
+			break;
+		}
+		//((u8*)req->buf)[0] = 0x82;
+		//((u8*)req->buf)[1] = 0x82;
+		value = ctrl->wLength;
+		break;
+	case 0x83:
+		switch (ctrl->wValue) {
+		case 0x0201:
+		case 0x0202:
+			((u8*)req->buf)[0] = 0x00;
+			((u8*)req->buf)[1] = 0x00;
+			break;
+		case 0x0300:
+			((u8*)req->buf)[0] = 0x60;
+			break;
+		case 0x0500:	
+			((u8*)req->buf)[0] = 0x18;
+			break;
+		}
+		//((u8*)req->buf)[0] = 0x83;
+		//((u8*)req->buf)[1] = 0x83;
+		value = ctrl->wLength;
+		break;
+	case 0x84:
+		switch (ctrl->wValue) {
+		case 0x0201:
+		case 0x0202:
+			((u8*)req->buf)[0] = 0x00;
+			((u8*)req->buf)[1] = 0x01;
+			break;
+		case 0x0300:
+		case 0x0500:
+			((u8*)req->buf)[0] = 0x08;
+			break;
+		}
+		//((u8*)req->buf)[0] = 0x84;
+		//((u8*)req->buf)[1] = 0x84;
+		value = ctrl->wLength;
+		break;
+	case 0x85:
+		((u8*)req->buf)[0] = 0x85;
+		((u8*)req->buf)[1] = 0x85;
+		value = ctrl->wLength;
+		break;
+
+	
+	default:
+unknown:
+		printk("unknown control req%02x.%02x v%04x i%04x l%d\n",
+			ctrl->bRequestType, ctrl->bRequest,
+			ctrl->wValue, ctrl->wIndex, ctrl->wLength);
+	}
+
+	/* respond with data transfer before status phase? */
+	if (value >= 0) {
+		req->length = value;
+		req->zero = value < ctrl->wLength
+				&& (value % gadget->ep0->maxpacket) == 0;
+		value = usb_ep_queue (gadget->ep0, req, GFP_ATOMIC);
+		if (value < 0) {
+			DBG (dev, "ep_queue < 0 --> %d\n", value);
+			req->status = 0;
+			zero_setup_complete (gadget->ep0, req);
+		}
+	}
+
+	/* device either stalls (value < 0) or reports success */
+	return value;
+}
+
+static void
+zero_disconnect (struct usb_gadget *gadget)
+{
+	struct zero_dev		*dev = get_gadget_data (gadget);
+	unsigned long		flags;
+
+	spin_lock_irqsave (&dev->lock, flags);
+	zero_reset_config (dev);
+
+	/* a more significant application might have some non-usb
+	 * activities to quiesce here, saving resources like power
+	 * or pushing the notification up a network stack.
+	 */
+	spin_unlock_irqrestore (&dev->lock, flags);
+
+	/* next we may get setup() calls to enumerate new connections;
+	 * or an unbind() during shutdown (including removing module).
+	 */
+}
+
+static void
+zero_autoresume (unsigned long _dev)
+{
+	struct zero_dev	*dev = (struct zero_dev *) _dev;
+	int		status;
+
+	/* normally the host would be woken up for something
+	 * more significant than just a timer firing...
+	 */
+	if (dev->gadget->speed != USB_SPEED_UNKNOWN) {
+		status = usb_gadget_wakeup (dev->gadget);
+		DBG (dev, "wakeup --> %d\n", status);
+	}
+}
+
+/*-------------------------------------------------------------------------*/
+
+static void
+zero_unbind (struct usb_gadget *gadget)
+{
+	struct zero_dev		*dev = get_gadget_data (gadget);
+
+	DBG (dev, "unbind\n");
+
+	/* we've already been disconnected ... no i/o is active */
+	if (dev->req)
+		free_ep_req (gadget->ep0, dev->req);
+	del_timer_sync (&dev->resume);
+	kfree (dev);
+	set_gadget_data (gadget, NULL);
+}
+
+static int
+zero_bind (struct usb_gadget *gadget)
+{
+	struct zero_dev		*dev;
+	//struct usb_ep		*ep;
+
+	printk("binding\n");
+	/*
+	 * DRIVER POLICY CHOICE:  you may want to do this differently.
+	 * One thing to avoid is reusing a bcdDevice revision code
+	 * with different host-visible configurations or behavior
+	 * restrictions -- using ep1in/ep2out vs ep1out/ep3in, etc
+	 */
+	//device_desc.bcdDevice = __constant_cpu_to_le16 (0x0201);
+
+
+	/* ok, we made sense of the hardware ... */
+	dev = kmalloc (sizeof *dev, SLAB_KERNEL);
+	if (!dev)
+		return -ENOMEM;
+	memset (dev, 0, sizeof *dev);
+	spin_lock_init (&dev->lock);
+	dev->gadget = gadget;
+	set_gadget_data (gadget, dev);
+
+	/* preallocate control response and buffer */
+	dev->req = usb_ep_alloc_request (gadget->ep0, GFP_KERNEL);
+	if (!dev->req)
+		goto enomem;
+	dev->req->buf = usb_ep_alloc_buffer (gadget->ep0, USB_BUFSIZ,
+				&dev->req->dma, GFP_KERNEL);
+	if (!dev->req->buf)
+		goto enomem;
+
+	dev->req->complete = zero_setup_complete;
+
+	device_desc.bMaxPacketSize0 = gadget->ep0->maxpacket;
+
+#ifdef CONFIG_USB_GADGET_DUALSPEED
+	/* assume ep0 uses the same value for both speeds ... */
+	dev_qualifier.bMaxPacketSize0 = device_desc.bMaxPacketSize0;
+
+	/* and that all endpoints are dual-speed */
+	//hs_source_desc.bEndpointAddress = fs_source_desc.bEndpointAddress;
+	//hs_sink_desc.bEndpointAddress = fs_sink_desc.bEndpointAddress;
+#endif
+
+	usb_gadget_set_selfpowered (gadget);
+
+	init_timer (&dev->resume);
+	dev->resume.function = zero_autoresume;
+	dev->resume.data = (unsigned long) dev;
+
+	gadget->ep0->driver_data = dev;
+
+	INFO (dev, "%s, version: " DRIVER_VERSION "\n", longname);
+	INFO (dev, "using %s, OUT %s IN %s\n", gadget->name,
+		EP_OUT_NAME, EP_IN_NAME);
+
+	snprintf (manufacturer, sizeof manufacturer,
+		UTS_SYSNAME " " UTS_RELEASE " with %s",
+		gadget->name);
+
+	return 0;
+
+enomem:
+	zero_unbind (gadget);
+	return -ENOMEM;
+}
+
+/*-------------------------------------------------------------------------*/
+
+static void
+zero_suspend (struct usb_gadget *gadget)
+{
+	struct zero_dev		*dev = get_gadget_data (gadget);
+
+	if (gadget->speed == USB_SPEED_UNKNOWN)
+		return;
+
+	if (autoresume) {
+		mod_timer (&dev->resume, jiffies + (HZ * autoresume));
+		DBG (dev, "suspend, wakeup in %d seconds\n", autoresume);
+	} else
+		DBG (dev, "suspend\n");
+}
+
+static void
+zero_resume (struct usb_gadget *gadget)
+{
+	struct zero_dev		*dev = get_gadget_data (gadget);
+
+	DBG (dev, "resume\n");
+	del_timer (&dev->resume);
+}
+
+
+/*-------------------------------------------------------------------------*/
+
+static struct usb_gadget_driver zero_driver = {
+#ifdef CONFIG_USB_GADGET_DUALSPEED
+	.speed		= USB_SPEED_HIGH,
+#else
+	.speed		= USB_SPEED_FULL,
+#endif
+	.function	= (char *) longname,
+	.bind		= zero_bind,
+	.unbind		= zero_unbind,
+
+	.setup		= zero_setup,
+	.disconnect	= zero_disconnect,
+
+	.suspend	= zero_suspend,
+	.resume		= zero_resume,
+
+	.driver 	= {
+		.name		= (char *) shortname,
+		// .shutdown = ...
+		// .suspend = ...
+		// .resume = ...
+	},
+};
+
+MODULE_AUTHOR ("David Brownell");
+MODULE_LICENSE ("Dual BSD/GPL");
+
+static struct proc_dir_entry *pdir, *pfile;
+
+static int isoc_read_data (char *page, char **start,
+			   off_t off, int count,
+			   int *eof, void *data)
+{
+	int i;
+	static int c = 0;
+	static int done = 0;
+	static int s = 0;
+
+/*
+	printk ("\ncount: %d\n", count);
+	printk ("rbuf_start: %d\n", rbuf_start);
+	printk ("rbuf_len: %d\n", rbuf_len);
+	printk ("off: %d\n", off);
+	printk ("start: %p\n\n", *start);
+*/
+	if (done) {
+		c = 0;
+		done = 0;
+		*eof = 1;
+		return 0;
+	}
+
+	if (c == 0) {
+		if (rbuf_len == RBUF_LEN)
+			s = rbuf_start;
+		else s = 0;
+	}
+
+	for (i=0; i<count && c<rbuf_len; i++, c++) {
+		page[i] = rbuf[(c+s) % RBUF_LEN];
+	}
+	*start = page;
+	
+	if (c >= rbuf_len) {
+		*eof = 1;
+		done = 1;
+	}
+
+
+	return i;
+}
+
+static int __init init (void)
+{
+
+	int retval = 0;
+
+	pdir = proc_mkdir("isoc_test", NULL);
+	if(pdir == NULL) {
+		retval = -ENOMEM;
+		printk("Error creating dir\n");
+		goto done;
+	}
+	pdir->owner = THIS_MODULE;
+
+	pfile = create_proc_read_entry("isoc_data",
+				       0444, pdir,
+				       isoc_read_data,
+				       NULL);
+	if (pfile == NULL) {
+		retval = -ENOMEM;
+		printk("Error creating file\n");
+		goto no_file;
+	}
+	pfile->owner = THIS_MODULE;
+
+	return usb_gadget_register_driver (&zero_driver);
+
+ no_file:
+	remove_proc_entry("isoc_data", NULL);
+ done:
+	return retval;
+}
+module_init (init);
+
+static void __exit cleanup (void)
+{
+
+	usb_gadget_unregister_driver (&zero_driver);
+	
+	remove_proc_entry("isoc_data", pdir);
+	remove_proc_entry("isoc_test", NULL);
+}
+module_exit (cleanup);
diff --git a/drivers/usb/host/dwc_otg/dwc_cfi_common.h b/drivers/usb/host/dwc_otg/dwc_cfi_common.h
new file mode 100644
index 000000000000..be56af4d2223
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/dwc_cfi_common.h
@@ -0,0 +1,142 @@
+/* ==========================================================================
+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+ * otherwise expressly agreed to in writing between Synopsys and you.
+ * 
+ * The Software IS NOT an item of Licensed Software or Licensed Product under
+ * any End User Software License Agreement or Agreement for Licensed Product
+ * with Synopsys or any supplement thereto. You are permitted to use and
+ * redistribute this Software in source and binary forms, with or without
+ * modification, provided that redistributions of source code must retain this
+ * notice. You may not view, use, disclose, copy or distribute this file or
+ * any information contained herein except pursuant to this license grant from
+ * Synopsys. If you do not agree with this notice, including the disclaimer
+ * below, then you are not authorized to use the Software.
+ * 
+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ * ========================================================================== */
+
+#if !defined(__DWC_CFI_COMMON_H__)
+#define __DWC_CFI_COMMON_H__
+
+//#include <linux/types.h>
+
+/**
+ * @file 
+ *
+ * This file contains the CFI specific common constants, interfaces
+ * (functions and macros) and structures for Linux. No PCD specific
+ * data structure or definition is to be included in this file.
+ *
+ */
+
+/** This is a request for all Core Features */
+#define VEN_CORE_GET_FEATURES		0xB1
+
+/** This is a request to get the value of a specific Core Feature */
+#define VEN_CORE_GET_FEATURE		0xB2
+
+/** This command allows the host to set the value of a specific Core Feature */
+#define VEN_CORE_SET_FEATURE		0xB3
+
+/** This command allows the host to set the default values of 
+ * either all or any specific Core Feature 
+ */
+#define VEN_CORE_RESET_FEATURES		0xB4
+
+/** This command forces the PCD to write the deferred values of a Core Features */
+#define VEN_CORE_ACTIVATE_FEATURES	0xB5
+
+/** This request reads a DWORD value from a register at the specified offset */
+#define VEN_CORE_READ_REGISTER		0xB6
+
+/** This request writes a DWORD value into a register at the specified offset */
+#define VEN_CORE_WRITE_REGISTER		0xB7
+
+/** This structure is the header of the Core Features dataset returned to 
+ *  the Host
+ */
+struct cfi_all_features_header {
+/** The features header structure length is */
+#define CFI_ALL_FEATURES_HDR_LEN		8
+	/**
+	 * The total length of the features dataset returned to the Host 
+	 */
+	uint16_t wTotalLen;
+
+	/**
+	 * CFI version number inBinary-Coded Decimal (i.e., 1.00 is 100H).
+	 * This field identifies the version of the CFI Specification with which 
+	 * the device is compliant.
+	 */
+	uint16_t wVersion;
+
+	/** The ID of the Core */
+	uint16_t wCoreID;
+#define CFI_CORE_ID_UDC		1
+#define CFI_CORE_ID_OTG		2
+#define CFI_CORE_ID_WUDEV	3
+
+	/** Number of features returned by VEN_CORE_GET_FEATURES request */
+	uint16_t wNumFeatures;
+} UPACKED;
+
+typedef struct cfi_all_features_header cfi_all_features_header_t;
+
+/** This structure is a header of the Core Feature descriptor dataset returned to 
+ *  the Host after the VEN_CORE_GET_FEATURES request
+ */
+struct cfi_feature_desc_header {
+#define CFI_FEATURE_DESC_HDR_LEN	8
+
+	/** The feature ID */
+	uint16_t wFeatureID;
+
+	/** Length of this feature descriptor in bytes - including the
+	 * length of the feature name string
+	 */
+	uint16_t wLength;
+
+	/** The data length of this feature in bytes */
+	uint16_t wDataLength;
+
+	/** 
+	 * Attributes of this features 
+	 * D0: Access rights
+	 * 0 - Read/Write
+	 * 1 - Read only
+	 */
+	uint8_t bmAttributes;
+#define CFI_FEATURE_ATTR_RO		1
+#define CFI_FEATURE_ATTR_RW		0
+
+	/** Length of the feature name in bytes */
+	uint8_t bNameLen;
+
+	/** The feature name buffer */
+	//uint8_t *name;
+} UPACKED;
+
+typedef struct cfi_feature_desc_header cfi_feature_desc_header_t;
+
+/**
+ * This structure describes a NULL terminated string referenced by its id field.
+ * It is very similar to usb_string structure but has the id field type set to 16-bit.
+ */
+struct cfi_string {
+	uint16_t id;
+	const uint8_t *s;
+};
+typedef struct cfi_string cfi_string_t;
+
+#endif
diff --git a/drivers/usb/host/dwc_otg/dwc_otg_attr.c b/drivers/usb/host/dwc_otg/dwc_otg_attr.c
new file mode 100644
index 000000000000..26ff76f1c774
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/dwc_otg_attr.c
@@ -0,0 +1,1316 @@
+/* ==========================================================================
+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.c $
+ * $Revision: #35 $
+ * $Date: 2009/04/03 $
+ * $Change: 1225160 $
+ *
+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+ * otherwise expressly agreed to in writing between Synopsys and you.
+ *
+ * The Software IS NOT an item of Licensed Software or Licensed Product under
+ * any End User Software License Agreement or Agreement for Licensed Product
+ * with Synopsys or any supplement thereto. You are permitted to use and
+ * redistribute this Software in source and binary forms, with or without
+ * modification, provided that redistributions of source code must retain this
+ * notice. You may not view, use, disclose, copy or distribute this file or
+ * any information contained herein except pursuant to this license grant from
+ * Synopsys. If you do not agree with this notice, including the disclaimer
+ * below, then you are not authorized to use the Software.
+ *
+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ * ========================================================================== */
+
+/** @file
+ *
+ * The diagnostic interface will provide access to the controller for
+ * bringing up the hardware and testing.  The Linux driver attributes
+ * feature will be used to provide the Linux Diagnostic
+ * Interface. These attributes are accessed through sysfs.
+ */
+
+/** @page "Linux Module Attributes"
+ *
+ * The Linux module attributes feature is used to provide the Linux
+ * Diagnostic Interface.  These attributes are accessed through sysfs.
+ * The diagnostic interface will provide access to the controller for
+ * bringing up the hardware and testing.
+
+ The following table shows the attributes.
+ <table>
+ <tr>
+ <td><b> Name</b></td>
+ <td><b> Description</b></td>
+ <td><b> Access</b></td>
+ </tr>
+
+ <tr>
+ <td> mode </td>
+ <td> Returns the current mode: 0 for device mode, 1 for host mode</td>
+ <td> Read</td>
+ </tr>
+
+ <tr>
+ <td> hnpcapable </td>
+ <td> Gets or sets the "HNP-capable" bit in the Core USB Configuraton Register.
+ Read returns the current value.</td>
+ <td> Read/Write</td>
+ </tr>
+
+ <tr>
+ <td> srpcapable </td>
+ <td> Gets or sets the "SRP-capable" bit in the Core USB Configuraton Register.
+ Read returns the current value.</td>
+ <td> Read/Write</td>
+ </tr>
+
+ <tr>
+ <td> hsic_connect </td>
+ <td> Gets or sets the "HSIC-Connect" bit in the GLPMCFG Register.
+ Read returns the current value.</td>
+ <td> Read/Write</td>
+ </tr>
+
+ <tr>
+ <td> inv_sel_hsic </td>
+ <td> Gets or sets the "Invert Select HSIC" bit in the GLPMFG Register.
+ Read returns the current value.</td>
+ <td> Read/Write</td>
+ </tr>
+
+ <tr>
+ <td> hnp </td>
+ <td> Initiates the Host Negotiation Protocol.  Read returns the status.</td>
+ <td> Read/Write</td>
+ </tr>
+
+ <tr>
+ <td> srp </td>
+ <td> Initiates the Session Request Protocol.  Read returns the status.</td>
+ <td> Read/Write</td>
+ </tr>
+
+ <tr>
+ <td> buspower </td>
+ <td> Gets or sets the Power State of the bus (0 - Off or 1 - On)</td>
+ <td> Read/Write</td>
+ </tr>
+
+ <tr>
+ <td> bussuspend </td>
+ <td> Suspends the USB bus.</td>
+ <td> Read/Write</td>
+ </tr>
+
+ <tr>
+ <td> busconnected </td>
+ <td> Gets the connection status of the bus</td>
+ <td> Read</td>
+ </tr>
+
+ <tr>
+ <td> gotgctl </td>
+ <td> Gets or sets the Core Control Status Register.</td>
+ <td> Read/Write</td>
+ </tr>
+
+ <tr>
+ <td> gusbcfg </td>
+ <td> Gets or sets the Core USB Configuration Register</td>
+ <td> Read/Write</td>
+ </tr>
+
+ <tr>
+ <td> grxfsiz </td>
+ <td> Gets or sets the Receive FIFO Size Register</td>
+ <td> Read/Write</td>
+ </tr>
+
+ <tr>
+ <td> gnptxfsiz </td>
+ <td> Gets or sets the non-periodic Transmit Size Register</td>
+ <td> Read/Write</td>
+ </tr>
+
+ <tr>
+ <td> gpvndctl </td>
+ <td> Gets or sets the PHY Vendor Control Register</td>
+ <td> Read/Write</td>
+ </tr>
+
+ <tr>
+ <td> ggpio </td>
+ <td> Gets the value in the lower 16-bits of the General Purpose IO Register
+ or sets the upper 16 bits.</td>
+ <td> Read/Write</td>
+ </tr>
+
+ <tr>
+ <td> guid </td>
+ <td> Gets or sets the value of the User ID Register</td>
+ <td> Read/Write</td>
+ </tr>
+
+ <tr>
+ <td> gsnpsid </td>
+ <td> Gets the value of the Synopsys ID Regester</td>
+ <td> Read</td>
+ </tr>
+
+ <tr>
+ <td> devspeed </td>
+ <td> Gets or sets the device speed setting in the DCFG register</td>
+ <td> Read/Write</td>
+ </tr>
+
+ <tr>
+ <td> enumspeed </td>
+ <td> Gets the device enumeration Speed.</td>
+ <td> Read</td>
+ </tr>
+
+ <tr>
+ <td> hptxfsiz </td>
+ <td> Gets the value of the Host Periodic Transmit FIFO</td>
+ <td> Read</td>
+ </tr>
+
+ <tr>
+ <td> hprt0 </td>
+ <td> Gets or sets the value in the Host Port Control and Status Register</td>
+ <td> Read/Write</td>
+ </tr>
+
+ <tr>
+ <td> regoffset </td>
+ <td> Sets the register offset for the next Register Access</td>
+ <td> Read/Write</td>
+ </tr>
+
+ <tr>
+ <td> regvalue </td>
+ <td> Gets or sets the value of the register at the offset in the regoffset attribute.</td>
+ <td> Read/Write</td>
+ </tr>
+
+ <tr>
+ <td> remote_wakeup </td>
+ <td> On read, shows the status of Remote Wakeup. On write, initiates a remote
+ wakeup of the host. When bit 0 is 1 and Remote Wakeup is enabled, the Remote
+ Wakeup signalling bit in the Device Control Register is set for 1
+ milli-second.</td>
+ <td> Read/Write</td>
+ </tr>
+
+ <tr>
+ <td> regdump </td>
+ <td> Dumps the contents of core registers.</td>
+ <td> Read</td>
+ </tr>
+
+ <tr>
+ <td> spramdump </td>
+ <td> Dumps the contents of core registers.</td>
+ <td> Read</td>
+ </tr>
+
+ <tr>
+ <td> hcddump </td>
+ <td> Dumps the current HCD state.</td>
+ <td> Read</td>
+ </tr>
+
+ <tr>
+ <td> hcd_frrem </td>
+ <td> Shows the average value of the Frame Remaining
+ field in the Host Frame Number/Frame Remaining register when an SOF interrupt
+ occurs. This can be used to determine the average interrupt latency. Also
+ shows the average Frame Remaining value for start_transfer and the "a" and
+ "b" sample points. The "a" and "b" sample points may be used during debugging
+ bto determine how long it takes to execute a section of the HCD code.</td>
+ <td> Read</td>
+ </tr>
+
+ <tr>
+ <td> rd_reg_test </td>
+ <td> Displays the time required to read the GNPTXFSIZ register many times
+ (the output shows the number of times the register is read).
+ <td> Read</td>
+ </tr>
+
+ <tr>
+ <td> wr_reg_test </td>
+ <td> Displays the time required to write the GNPTXFSIZ register many times
+ (the output shows the number of times the register is written).
+ <td> Read</td>
+ </tr>
+
+ <tr>
+ <td> lpm_response </td>
+ <td> Gets or sets lpm_response mode. Applicable only in device mode.
+ <td> Write</td>
+ </tr>
+
+ <tr>
+ <td> sleep_local_dev </td>
+ <td> Generetates sleep signaling. Applicable only in host mode.
+ <td> Write</td>
+ </tr>
+
+ <tr>
+ <td> sleep_status </td>
+ <td> Shows sleep status of device.
+ <td> Read</td>
+ </tr>
+
+ </table>
+
+ Example usage:
+ To get the current mode:
+ cat /sys/devices/lm0/mode
+
+ To power down the USB:
+ echo 0 > /sys/devices/lm0/buspower
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/types.h>
+#include <linux/stat.h>		/* permission constants */
+#include <linux/version.h>
+#include <linux/param.h>
+#include <linux/delay.h>
+#include <linux/jiffies.h>
+
+
+#ifdef LM_INTERFACE
+#include <asm/sizes.h>
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30))
+#include <asm/arch/lm.h>
+#else
+/* in 2.6.31, at least, we seem to have lost the generic LM infrastructure -
+   here we use definitions stolen from arm-integrator headers
+*/
+#include <mach/lm.h>
+#endif
+#elif defined(PLATFORM_INTERFACE)
+#include <linux/platform_device.h>
+#endif
+
+#include <asm/io.h>
+
+#include "dwc_os.h"
+#include "dwc_otg_driver.h"
+#include "dwc_otg_attr.h"
+#include "dwc_otg_core_if.h"
+#include "dwc_otg_pcd_if.h"
+#include "dwc_otg_hcd_if.h"
+
+/*
+ * MACROs for defining sysfs attribute
+ */
+#ifdef LM_INTERFACE
+
+#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
+static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
+{ \
+	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
+	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);		\
+	uint32_t val; \
+	val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
+	return sprintf (buf, "%s = 0x%x\n", _string_, val); \
+}
+#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \
+static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
+					const char *buf, size_t count) \
+{ \
+	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
+	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \
+	uint32_t set = simple_strtoul(buf, NULL, 16); \
+	dwc_otg_set_##_otg_attr_name_(otg_dev->core_if, set);\
+	return count; \
+}
+
+#elif defined(PCI_INTERFACE)
+
+#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
+static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
+{ \
+	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);	\
+	uint32_t val; \
+	val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
+	return sprintf (buf, "%s = 0x%x\n", _string_, val); \
+}
+#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \
+static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
+					const char *buf, size_t count) \
+{ \
+	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);  \
+	uint32_t set = simple_strtoul(buf, NULL, 16); \
+	dwc_otg_set_##_otg_attr_name_(otg_dev->core_if, set);\
+	return count; \
+}
+
+#elif defined(PLATFORM_INTERFACE)
+
+#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
+static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
+{ \
+        struct platform_device *platform_dev = \
+                container_of(_dev, struct platform_device, dev); \
+        dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);  \
+	uint32_t val; \
+	DWC_PRINTF("%s(%p) -> platform_dev %p, otg_dev %p\n", \
+                    __func__, _dev, platform_dev, otg_dev); \
+	val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
+	return sprintf (buf, "%s = 0x%x\n", _string_, val); \
+}
+#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \
+static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
+					const char *buf, size_t count) \
+{ \
+        struct platform_device *platform_dev = container_of(_dev, struct platform_device, dev); \
+        dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); \
+	uint32_t set = simple_strtoul(buf, NULL, 16); \
+	dwc_otg_set_##_otg_attr_name_(otg_dev->core_if, set);\
+	return count; \
+}
+#endif
+
+/*
+ * MACROs for defining sysfs attribute for 32-bit registers
+ */
+#ifdef LM_INTERFACE
+#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
+static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
+{ \
+	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
+	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \
+	uint32_t val; \
+	val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
+	return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
+}
+#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \
+static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
+					const char *buf, size_t count) \
+{ \
+	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
+	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \
+	uint32_t val = simple_strtoul(buf, NULL, 16); \
+	dwc_otg_set_##_otg_attr_name_ (otg_dev->core_if, val); \
+	return count; \
+}
+#elif defined(PCI_INTERFACE)
+#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
+static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
+{ \
+	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);  \
+	uint32_t val; \
+	val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
+	return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
+}
+#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \
+static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
+					const char *buf, size_t count) \
+{ \
+	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);  \
+	uint32_t val = simple_strtoul(buf, NULL, 16); \
+	dwc_otg_set_##_otg_attr_name_ (otg_dev->core_if, val); \
+	return count; \
+}
+
+#elif defined(PLATFORM_INTERFACE)
+#include "dwc_otg_dbg.h"
+#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
+static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
+{ \
+	struct platform_device *platform_dev = container_of(_dev, struct platform_device, dev); \
+	dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); \
+	uint32_t val; \
+	DWC_PRINTF("%s(%p) -> platform_dev %p, otg_dev %p\n", \
+                    __func__, _dev, platform_dev, otg_dev); \
+	val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
+	return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
+}
+#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \
+static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
+					const char *buf, size_t count) \
+{ \
+	struct platform_device *platform_dev = container_of(_dev, struct platform_device, dev); \
+	dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); \
+	uint32_t val = simple_strtoul(buf, NULL, 16); \
+	dwc_otg_set_##_otg_attr_name_ (otg_dev->core_if, val); \
+	return count; \
+}
+
+#endif
+
+#define DWC_OTG_DEVICE_ATTR_BITFIELD_RW(_otg_attr_name_,_string_) \
+DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
+DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \
+DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
+
+#define DWC_OTG_DEVICE_ATTR_BITFIELD_RO(_otg_attr_name_,_string_) \
+DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
+DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
+
+#define DWC_OTG_DEVICE_ATTR_REG32_RW(_otg_attr_name_,_addr_,_string_) \
+DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
+DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \
+DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
+
+#define DWC_OTG_DEVICE_ATTR_REG32_RO(_otg_attr_name_,_addr_,_string_) \
+DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
+DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
+
+/** @name Functions for Show/Store of Attributes */
+/**@{*/
+
+/**
+ * Show the register offset of the Register Access.
+ */
+static ssize_t regoffset_show(struct device *_dev,
+			      struct device_attribute *attr, char *buf)
+{
+#ifdef LM_INTERFACE
+	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+#elif defined(PCI_INTERFACE)
+	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+#elif defined(PLATFORM_INTERFACE)
+	struct platform_device *platform_dev = container_of(_dev,
+                                                    struct platform_device, dev);
+	dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
+#endif
+
+	return snprintf(buf, sizeof("0xFFFFFFFF\n") + 1, "0x%08x\n",
+			otg_dev->reg_offset);
+}
+
+/**
+ * Set the register offset for the next Register Access 	Read/Write
+ */
+static ssize_t regoffset_store(struct device *_dev,
+			       struct device_attribute *attr,
+			       const char *buf, size_t count)
+{
+#ifdef LM_INTERFACE
+	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+#elif defined(PCI_INTERFACE)
+	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+#elif defined(PLATFORM_INTERFACE)
+	struct platform_device *platform_dev = container_of(_dev,
+                                                    struct platform_device, dev);
+	dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
+#endif
+
+	uint32_t offset = simple_strtoul(buf, NULL, 16);
+        if (offset < SZ_256K) {
+		otg_dev->reg_offset = offset;
+	} else {
+		dev_err(_dev, "invalid offset\n");
+	}
+
+	return count;
+}
+
+DEVICE_ATTR(regoffset, S_IRUGO | S_IWUSR, regoffset_show, regoffset_store);
+
+/**
+ * Show the value of the register at the offset in the reg_offset
+ * attribute.
+ */
+static ssize_t regvalue_show(struct device *_dev,
+			     struct device_attribute *attr, char *buf)
+{
+#ifdef LM_INTERFACE
+	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+#elif defined(PCI_INTERFACE)
+	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+#elif defined(PLATFORM_INTERFACE)
+	struct platform_device *platform_dev =
+           container_of(_dev, struct platform_device, dev);
+	dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
+#endif
+
+	uint32_t val;
+	volatile uint32_t *addr;
+
+	if (otg_dev->reg_offset != 0xFFFFFFFF && 0 != otg_dev->base) {
+		/* Calculate the address */
+		addr = (uint32_t *) (otg_dev->reg_offset +
+				     (uint8_t *) otg_dev->base);
+		val = dwc_read_reg32(addr);
+		return snprintf(buf,
+				sizeof("Reg@0xFFFFFFFF = 0xFFFFFFFF\n") + 1,
+				"Reg@0x%06x = 0x%08x\n", otg_dev->reg_offset,
+				val);
+	} else {
+		dev_err(_dev, "Invalid offset (0x%0x)\n", otg_dev->reg_offset);
+		return sprintf(buf, "invalid offset\n");
+	}
+}
+
+/**
+ * Store the value in the register at the offset in the reg_offset
+ * attribute.
+ *
+ */
+static ssize_t regvalue_store(struct device *_dev,
+			      struct device_attribute *attr,
+			      const char *buf, size_t count)
+{
+#ifdef LM_INTERFACE
+	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+#elif defined(PCI_INTERFACE)
+	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+#elif defined(PLATFORM_INTERFACE)
+	struct platform_device *platform_dev =
+           container_of(_dev, struct platform_device, dev);
+	dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
+#endif
+
+	volatile uint32_t *addr;
+	uint32_t val = simple_strtoul(buf, NULL, 16);
+	//dev_dbg(_dev, "Offset=0x%08x Val=0x%08x\n", otg_dev->reg_offset, val);
+	if (otg_dev->reg_offset != 0xFFFFFFFF && 0 != otg_dev->base) {
+		/* Calculate the address */
+		addr = (uint32_t *) (otg_dev->reg_offset +
+				     (uint8_t *) otg_dev->base);
+		dwc_write_reg32(addr, val);
+	} else {
+		dev_err(_dev, "Invalid Register Offset (0x%08x)\n",
+			otg_dev->reg_offset);
+	}
+	return count;
+}
+
+DEVICE_ATTR(regvalue, S_IRUGO | S_IWUSR, regvalue_show, regvalue_store);
+
+/*
+ * Attributes
+ */
+DWC_OTG_DEVICE_ATTR_BITFIELD_RO(mode, "Mode");
+DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hnpcapable, "HNPCapable");
+DWC_OTG_DEVICE_ATTR_BITFIELD_RW(srpcapable, "Mode");
+DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hsic_connect, "HSIC Connect");
+DWC_OTG_DEVICE_ATTR_BITFIELD_RW(inv_sel_hsic, "Invert Select HSIC");
+
+//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(buspower,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode");
+//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(bussuspend,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode");
+DWC_OTG_DEVICE_ATTR_BITFIELD_RO(busconnected, "Bus Connected");
+
+DWC_OTG_DEVICE_ATTR_REG32_RW(gotgctl, 0, "GOTGCTL");
+DWC_OTG_DEVICE_ATTR_REG32_RW(gusbcfg,
+			     &(otg_dev->core_if->core_global_regs->gusbcfg),
+			     "GUSBCFG");
+DWC_OTG_DEVICE_ATTR_REG32_RW(grxfsiz,
+			     &(otg_dev->core_if->core_global_regs->grxfsiz),
+			     "GRXFSIZ");
+DWC_OTG_DEVICE_ATTR_REG32_RW(gnptxfsiz,
+			     &(otg_dev->core_if->core_global_regs->gnptxfsiz),
+			     "GNPTXFSIZ");
+DWC_OTG_DEVICE_ATTR_REG32_RW(gpvndctl,
+			     &(otg_dev->core_if->core_global_regs->gpvndctl),
+			     "GPVNDCTL");
+DWC_OTG_DEVICE_ATTR_REG32_RW(ggpio,
+			     &(otg_dev->core_if->core_global_regs->ggpio),
+			     "GGPIO");
+DWC_OTG_DEVICE_ATTR_REG32_RW(guid, &(otg_dev->core_if->core_global_regs->guid),
+			     "GUID");
+DWC_OTG_DEVICE_ATTR_REG32_RO(gsnpsid,
+			     &(otg_dev->core_if->core_global_regs->gsnpsid),
+			     "GSNPSID");
+DWC_OTG_DEVICE_ATTR_BITFIELD_RW(devspeed, "Device Speed");
+DWC_OTG_DEVICE_ATTR_BITFIELD_RO(enumspeed, "Device Enumeration Speed");
+
+DWC_OTG_DEVICE_ATTR_REG32_RO(hptxfsiz,
+			     &(otg_dev->core_if->core_global_regs->hptxfsiz),
+			     "HPTXFSIZ");
+DWC_OTG_DEVICE_ATTR_REG32_RW(hprt0, otg_dev->core_if->host_if->hprt0, "HPRT0");
+
+/**
+ * @todo Add code to initiate the HNP.
+ */
+/**
+ * Show the HNP status bit
+ */
+static ssize_t hnp_show(struct device *_dev,
+			struct device_attribute *attr, char *buf)
+{
+#ifdef LM_INTERFACE
+	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+#elif defined(PCI_INTERFACE)
+	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+#elif defined(PLATFORM_INTERFACE)
+	struct platform_device *platform_dev =
+           container_of(_dev, struct platform_device, dev);
+	dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
+#endif
+	return sprintf(buf, "HstNegScs = 0x%x\n",
+		       dwc_otg_get_hnpstatus(otg_dev->core_if));
+}
+
+/**
+ * Set the HNP Request bit
+ */
+static ssize_t hnp_store(struct device *_dev,
+			 struct device_attribute *attr,
+			 const char *buf, size_t count)
+{
+#ifdef LM_INTERFACE
+	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+#elif defined(PCI_INTERFACE)
+	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+#elif defined(PLATFORM_INTERFACE)
+	struct platform_device *platform_dev =
+           container_of(_dev, struct platform_device, dev);
+	dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
+#endif
+	uint32_t in = simple_strtoul(buf, NULL, 16);
+	dwc_otg_set_hnpreq(otg_dev->core_if, in);
+	return count;
+}
+
+DEVICE_ATTR(hnp, 0644, hnp_show, hnp_store);
+
+/**
+ * @todo Add code to initiate the SRP.
+ */
+/**
+ * Show the SRP status bit
+ */
+static ssize_t srp_show(struct device *_dev,
+			struct device_attribute *attr, char *buf)
+{
+#ifndef DWC_HOST_ONLY
+#ifdef LM_INTERFACE
+	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+#elif defined(PCI_INTERFACE)
+	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+#elif defined(PLATFORM_INTERFACE)
+	struct platform_device *platform_dev =
+           container_of(_dev, struct platform_device, dev);
+	dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
+#endif
+	return sprintf(buf, "SesReqScs = 0x%x\n",
+		       dwc_otg_get_srpstatus(otg_dev->core_if));
+#else
+	return sprintf(buf, "Host Only Mode!\n");
+#endif
+}
+
+/**
+ * Set the SRP Request bit
+ */
+static ssize_t srp_store(struct device *_dev,
+			 struct device_attribute *attr,
+			 const char *buf, size_t count)
+{
+#ifndef DWC_HOST_ONLY
+#ifdef LM_INTERFACE
+	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+#elif defined(PCI_INTERFACE)
+	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+#elif defined(PLATFORM_INTERFACE)
+	struct platform_device *platform_dev =
+           container_of(_dev, struct platform_device, dev);
+	dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
+#endif
+	dwc_otg_pcd_initiate_srp(otg_dev->pcd);
+#endif
+	return count;
+}
+
+DEVICE_ATTR(srp, 0644, srp_show, srp_store);
+
+/**
+ * @todo Need to do more for power on/off?
+ */
+/**
+ * Show the Bus Power status
+ */
+static ssize_t buspower_show(struct device *_dev,
+			     struct device_attribute *attr, char *buf)
+{
+#ifdef LM_INTERFACE
+	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+#elif defined(PCI_INTERFACE)
+	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+#elif defined(PLATFORM_INTERFACE)
+	struct platform_device *platform_dev =
+           container_of(_dev, struct platform_device, dev);
+	dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
+#endif
+	return sprintf(buf, "Bus Power = 0x%x\n",
+		       dwc_otg_get_prtpower(otg_dev->core_if));
+}
+
+/**
+ * Set the Bus Power status
+ */
+static ssize_t buspower_store(struct device *_dev,
+			      struct device_attribute *attr,
+			      const char *buf, size_t count)
+{
+#ifdef LM_INTERFACE
+	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+#elif defined(PCI_INTERFACE)
+	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+#elif defined(PLATFORM_INTERFACE)
+	struct platform_device *platform_dev =
+           container_of(_dev, struct platform_device, dev);
+	dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
+#endif
+	uint32_t on = simple_strtoul(buf, NULL, 16);
+	dwc_otg_set_prtpower(otg_dev->core_if, on);
+	return count;
+}
+
+DEVICE_ATTR(buspower, 0644, buspower_show, buspower_store);
+
+/**
+ * @todo Need to do more for suspend?
+ */
+/**
+ * Show the Bus Suspend status
+ */
+static ssize_t bussuspend_show(struct device *_dev,
+			       struct device_attribute *attr, char *buf)
+{
+#ifdef LM_INTERFACE
+	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+#elif defined(PCI_INTERFACE)
+	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+#elif defined(PLATFORM_INTERFACE)
+	struct platform_device *platform_dev =
+           container_of(_dev, struct platform_device, dev);
+	dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
+#endif
+
+	return sprintf(buf, "Bus Suspend = 0x%x\n",
+		       dwc_otg_get_prtsuspend(otg_dev->core_if));
+}
+
+/**
+ * Set the Bus Suspend status
+ */
+static ssize_t bussuspend_store(struct device *_dev,
+				struct device_attribute *attr,
+				const char *buf, size_t count)
+{
+#ifdef LM_INTERFACE
+	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+#elif defined(PCI_INTERFACE)
+	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+#elif defined(PLATFORM_INTERFACE)
+	struct platform_device *platform_dev =
+           container_of(_dev, struct platform_device, dev);
+	dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
+#endif
+
+	uint32_t in = simple_strtoul(buf, NULL, 16);
+	dwc_otg_set_prtsuspend(otg_dev->core_if, in);
+	return count;
+}
+
+DEVICE_ATTR(bussuspend, 0644, bussuspend_show, bussuspend_store);
+
+/**
+ * Show the status of Remote Wakeup.
+ */
+static ssize_t remote_wakeup_show(struct device *_dev,
+				  struct device_attribute *attr, char *buf)
+{
+#ifndef DWC_HOST_ONLY
+#ifdef LM_INTERFACE
+	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+#elif defined(PCI_INTERFACE)
+	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+#elif defined(PLATFORM_INTERFACE)
+	struct platform_device *platform_dev =
+           container_of(_dev, struct platform_device, dev);
+	dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
+#endif
+
+	return sprintf(buf,
+		       "Remote Wakeup Sig = %d Enabled = %d LPM Remote Wakeup = %d\n",
+		       dwc_otg_get_remotewakesig(otg_dev->core_if),
+		       dwc_otg_pcd_get_rmwkup_enable(otg_dev->pcd),
+		       dwc_otg_get_lpm_remotewakeenabled(otg_dev->core_if));
+#else
+	return sprintf(buf, "Host Only Mode!\n");
+#endif /* DWC_HOST_ONLY */
+}
+
+/**
+ * Initiate a remote wakeup of the host.  The Device control register
+ * Remote Wakeup Signal bit is written if the PCD Remote wakeup enable
+ * flag is set.
+ *
+ */
+static ssize_t remote_wakeup_store(struct device *_dev,
+				   struct device_attribute *attr,
+				   const char *buf, size_t count)
+{
+#ifndef DWC_HOST_ONLY
+#ifdef LM_INTERFACE
+	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+#elif defined(PCI_INTERFACE)
+	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+#elif defined(PLATFORM_INTERFACE)
+	struct platform_device *platform_dev =
+           container_of(_dev, struct platform_device, dev);
+	dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
+#endif
+
+	uint32_t val = simple_strtoul(buf, NULL, 16);
+
+	if (val & 1) {
+		dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 1);
+	} else {
+		dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 0);
+	}
+#endif /* DWC_HOST_ONLY */
+	return count;
+}
+
+DEVICE_ATTR(remote_wakeup, S_IRUGO | S_IWUSR, remote_wakeup_show,
+	    remote_wakeup_store);
+
+/**
+ * Dump global registers and either host or device registers (depending on the
+ * current mode of the core).
+ */
+static ssize_t regdump_show(struct device *_dev,
+			    struct device_attribute *attr, char *buf)
+{
+#ifdef LM_INTERFACE
+	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+#elif defined(PCI_INTERFACE)
+	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+#elif defined(PLATFORM_INTERFACE)
+	struct platform_device *platform_dev =
+           container_of(_dev, struct platform_device, dev);
+	dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
+#endif
+
+	dwc_otg_dump_global_registers(otg_dev->core_if);
+	if (dwc_otg_is_host_mode(otg_dev->core_if)) {
+		dwc_otg_dump_host_registers(otg_dev->core_if);
+	} else {
+		dwc_otg_dump_dev_registers(otg_dev->core_if);
+
+	}
+	return sprintf(buf, "Register Dump\n");
+}
+
+DEVICE_ATTR(regdump, S_IRUGO | S_IWUSR, regdump_show, 0);
+
+/**
+ * Dump global registers and either host or device registers (depending on the
+ * current mode of the core).
+ */
+static ssize_t spramdump_show(struct device *_dev,
+			      struct device_attribute *attr, char *buf)
+{
+#ifdef LM_INTERFACE
+	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+#elif defined(PCI_INTERFACE)
+	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+#elif defined(PLATFORM_INTERFACE)
+	struct platform_device *platform_dev =
+           container_of(_dev, struct platform_device, dev);
+	dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
+#endif
+
+	dwc_otg_dump_spram(otg_dev->core_if);
+
+	return sprintf(buf, "SPRAM Dump\n");
+}
+
+DEVICE_ATTR(spramdump, S_IRUGO | S_IWUSR, spramdump_show, 0);
+
+/**
+ * Dump the current hcd state.
+ */
+static ssize_t hcddump_show(struct device *_dev,
+			    struct device_attribute *attr, char *buf)
+{
+#ifndef DWC_DEVICE_ONLY
+#ifdef LM_INTERFACE
+	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+#elif defined(PCI_INTERFACE)
+	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+#elif defined(PLATFORM_INTERFACE)
+	struct platform_device *platform_dev =
+           container_of(_dev, struct platform_device, dev);
+	dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
+#endif
+
+	dwc_otg_hcd_dump_state(otg_dev->hcd);
+#endif /* DWC_DEVICE_ONLY */
+	return sprintf(buf, "HCD Dump\n");
+}
+
+DEVICE_ATTR(hcddump, S_IRUGO | S_IWUSR, hcddump_show, 0);
+
+/**
+ * Dump the average frame remaining at SOF. This can be used to
+ * determine average interrupt latency. Frame remaining is also shown for
+ * start transfer and two additional sample points.
+ */
+static ssize_t hcd_frrem_show(struct device *_dev,
+			      struct device_attribute *attr, char *buf)
+{
+#ifndef DWC_DEVICE_ONLY
+#ifdef LM_INTERFACE
+	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+#elif defined(PCI_INTERFACE)
+	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+#elif defined(PLATFORM_INTERFACE)
+	struct platform_device *platform_dev =
+           container_of(_dev, struct platform_device, dev);
+	dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
+#endif
+
+	dwc_otg_hcd_dump_frrem(otg_dev->hcd);
+#endif /* DWC_DEVICE_ONLY */
+	return sprintf(buf, "HCD Dump Frame Remaining\n");
+}
+
+DEVICE_ATTR(hcd_frrem, S_IRUGO | S_IWUSR, hcd_frrem_show, 0);
+
+/**
+ * Displays the time required to read the GNPTXFSIZ register many times (the
+ * output shows the number of times the register is read).
+ */
+#define RW_REG_COUNT 10000000
+#define MSEC_PER_JIFFIE 1000/HZ
+static ssize_t rd_reg_test_show(struct device *_dev,
+				struct device_attribute *attr, char *buf)
+{
+#ifdef LM_INTERFACE
+	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+#elif defined(PCI_INTERFACE)
+	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+#elif defined(PLATFORM_INTERFACE)
+	struct platform_device *platform_dev =
+           container_of(_dev, struct platform_device, dev);
+	dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
+#endif
+
+	int i;
+	int time;
+	int start_jiffies;
+
+	printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
+	       HZ, MSEC_PER_JIFFIE, loops_per_jiffy);
+	start_jiffies = jiffies;
+	for (i = 0; i < RW_REG_COUNT; i++) {
+		dwc_otg_get_gnptxfsiz(otg_dev->core_if);
+	}
+	time = jiffies - start_jiffies;
+	return sprintf(buf,
+		       "Time to read GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n",
+		       RW_REG_COUNT, time * MSEC_PER_JIFFIE, time);
+}
+
+DEVICE_ATTR(rd_reg_test, S_IRUGO | S_IWUSR, rd_reg_test_show, 0);
+
+/**
+ * Displays the time required to write the GNPTXFSIZ register many times (the
+ * output shows the number of times the register is written).
+ */
+static ssize_t wr_reg_test_show(struct device *_dev,
+				struct device_attribute *attr, char *buf)
+{
+#ifdef LM_INTERFACE
+	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+#elif defined(PCI_INTERFACE)
+	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+#elif defined(PLATFORM_INTERFACE)
+	struct platform_device *platform_dev =
+           container_of(_dev, struct platform_device, dev);
+	dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
+#endif
+
+	uint32_t reg_val;
+	int i;
+	int time;
+	int start_jiffies;
+
+	printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
+	       HZ, MSEC_PER_JIFFIE, loops_per_jiffy);
+	reg_val = dwc_otg_get_gnptxfsiz(otg_dev->core_if);
+	start_jiffies = jiffies;
+	for (i = 0; i < RW_REG_COUNT; i++) {
+		dwc_otg_set_gnptxfsiz(otg_dev->core_if, reg_val);
+	}
+	time = jiffies - start_jiffies;
+	return sprintf(buf,
+		       "Time to write GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n",
+		       RW_REG_COUNT, time * MSEC_PER_JIFFIE, time);
+}
+
+DEVICE_ATTR(wr_reg_test, S_IRUGO | S_IWUSR, wr_reg_test_show, 0);
+
+#ifdef CONFIG_USB_DWC_OTG_LPM
+
+/**
+* Show the lpm_response attribute.
+*/
+static ssize_t lpmresp_show(struct device *_dev,
+			    struct device_attribute *attr, char *buf)
+{
+#ifdef LM_INTERFACE
+	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+#elif defined(PCI_INTERFACE)
+	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+#elif defined(PLATFORM_INTERFACE)
+	struct platform_device *platform_dev =
+           container_of(_dev, struct platform_device, dev);
+	dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
+#endif
+
+	if (!dwc_otg_get_param_lpm_enable(otg_dev->core_if))
+		return sprintf(buf, "** LPM is DISABLED **\n");
+
+	if (!dwc_otg_is_device_mode(otg_dev->core_if)) {
+		return sprintf(buf, "** Current mode is not device mode\n");
+	}
+	return sprintf(buf, "lpm_response = %d\n",
+		       dwc_otg_get_lpmresponse(otg_dev->core_if));
+}
+
+/**
+* Store the lpm_response attribute.
+*/
+static ssize_t lpmresp_store(struct device *_dev,
+			     struct device_attribute *attr,
+			     const char *buf, size_t count)
+{
+#ifdef LM_INTERFACE
+	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+#elif defined(PCI_INTERFACE)
+	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+#elif defined(PLATFORM_INTERFACE)
+	struct platform_device *platform_dev =
+           container_of(_dev, struct platform_device, dev);
+	dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
+#endif
+
+	uint32_t val = simple_strtoul(buf, NULL, 16);
+
+	if (!dwc_otg_get_param_lpm_enable(otg_dev->core_if)) {
+		return 0;
+	}
+
+	if (!dwc_otg_is_device_mode(otg_dev->core_if)) {
+		return 0;
+	}
+
+	dwc_otg_set_lpmresponse(otg_dev->core_if, val);
+	return count;
+}
+
+DEVICE_ATTR(lpm_response, S_IRUGO | S_IWUSR, lpmresp_show, lpmresp_store);
+
+/**
+* Show the sleep_status attribute.
+*/
+static ssize_t sleepstatus_show(struct device *_dev,
+				struct device_attribute *attr, char *buf)
+{
+#ifdef LM_INTERFACE
+	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+#elif defined(PCI_INTERFACE)
+	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+#elif defined(PLATFORM_INTERFACE)
+	struct platform_device *platform_dev =
+           container_of(_dev, struct platform_device, dev);
+	dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
+#endif
+
+
+	return sprintf(buf, "Sleep Status = %d\n",
+		       dwc_otg_get_lpm_portsleepstatus(otg_dev->core_if));
+}
+
+/**
+ * Store the sleep_status attribure.
+ */
+static ssize_t sleepstatus_store(struct device *_dev,
+				 struct device_attribute *attr,
+				 const char *buf, size_t count)
+{
+#ifdef LM_INTERFACE
+	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+#elif defined(PCI_INTERFACE)
+	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+#elif defined(PLATFORM_INTERFACE)
+	struct platform_device *platform_dev =
+           container_of(_dev, struct platform_device, dev);
+	dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);
+#endif
+
+	dwc_otg_core_if_t *core_if = otg_dev->core_if;
+
+	if (dwc_otg_get_lpm_portsleepstatus(otg_dev->core_if)) {
+		if (dwc_otg_is_host_mode(core_if)) {
+
+			DWC_PRINTF("Host initiated resume\n");
+			dwc_otg_set_prtresume(otg_dev->core_if, 1);
+		}
+	}
+
+	return count;
+}
+
+DEVICE_ATTR(sleep_status, S_IRUGO | S_IWUSR, sleepstatus_show,
+	    sleepstatus_store);
+
+#endif				/* CONFIG_USB_DWC_OTG_LPM_ENABLE */
+
+/**@}*/
+
+/**
+ * Create the device files
+ */
+void dwc_otg_attr_create (
+#ifdef LM_INTERFACE
+	struct lm_device *dev
+#elif  defined(PCI_INTERFACE)
+	struct pci_dev *dev
+#elif  defined(PLATFORM_INTERFACE)
+	struct platform_device *dev
+#endif
+	)
+
+{
+	int error;
+
+	error = device_create_file(&dev->dev, &dev_attr_regoffset);
+	error = device_create_file(&dev->dev, &dev_attr_regvalue);
+	error = device_create_file(&dev->dev, &dev_attr_mode);
+	error = device_create_file(&dev->dev, &dev_attr_hnpcapable);
+	error = device_create_file(&dev->dev, &dev_attr_srpcapable);
+	error = device_create_file(&dev->dev, &dev_attr_hsic_connect);
+	error = device_create_file(&dev->dev, &dev_attr_inv_sel_hsic);
+	error = device_create_file(&dev->dev, &dev_attr_hnp);
+	error = device_create_file(&dev->dev, &dev_attr_srp);
+	error = device_create_file(&dev->dev, &dev_attr_buspower);
+	error = device_create_file(&dev->dev, &dev_attr_bussuspend);
+	error = device_create_file(&dev->dev, &dev_attr_busconnected);
+	error = device_create_file(&dev->dev, &dev_attr_gotgctl);
+	error = device_create_file(&dev->dev, &dev_attr_gusbcfg);
+	error = device_create_file(&dev->dev, &dev_attr_grxfsiz);
+	error = device_create_file(&dev->dev, &dev_attr_gnptxfsiz);
+	error = device_create_file(&dev->dev, &dev_attr_gpvndctl);
+	error = device_create_file(&dev->dev, &dev_attr_ggpio);
+	error = device_create_file(&dev->dev, &dev_attr_guid);
+	error = device_create_file(&dev->dev, &dev_attr_gsnpsid);
+	error = device_create_file(&dev->dev, &dev_attr_devspeed);
+	error = device_create_file(&dev->dev, &dev_attr_enumspeed);
+	error = device_create_file(&dev->dev, &dev_attr_hptxfsiz);
+	error = device_create_file(&dev->dev, &dev_attr_hprt0);
+	error = device_create_file(&dev->dev, &dev_attr_remote_wakeup);
+	error = device_create_file(&dev->dev, &dev_attr_regdump);
+	error = device_create_file(&dev->dev, &dev_attr_spramdump);
+	error = device_create_file(&dev->dev, &dev_attr_hcddump);
+	error = device_create_file(&dev->dev, &dev_attr_hcd_frrem);
+	error = device_create_file(&dev->dev, &dev_attr_rd_reg_test);
+	error = device_create_file(&dev->dev, &dev_attr_wr_reg_test);
+#ifdef CONFIG_USB_DWC_OTG_LPM
+	error = device_create_file(&dev->dev, &dev_attr_lpm_response);
+	error = device_create_file(&dev->dev, &dev_attr_sleep_status);
+#endif
+}
+
+/**
+ * Remove the device files
+ */
+void dwc_otg_attr_remove (
+#ifdef LM_INTERFACE
+	struct lm_device *dev
+#elif  defined(PCI_INTERFACE)
+	struct pci_dev *dev
+#elif  defined(PLATFORM_INTERFACE)
+	struct platform_device *dev
+#endif
+       )
+
+{
+	device_remove_file(&dev->dev, &dev_attr_regoffset);
+	device_remove_file(&dev->dev, &dev_attr_regvalue);
+	device_remove_file(&dev->dev, &dev_attr_mode);
+	device_remove_file(&dev->dev, &dev_attr_hnpcapable);
+	device_remove_file(&dev->dev, &dev_attr_srpcapable);
+	device_remove_file(&dev->dev, &dev_attr_hsic_connect);
+	device_remove_file(&dev->dev, &dev_attr_inv_sel_hsic);
+	device_remove_file(&dev->dev, &dev_attr_hnp);
+	device_remove_file(&dev->dev, &dev_attr_srp);
+	device_remove_file(&dev->dev, &dev_attr_buspower);
+	device_remove_file(&dev->dev, &dev_attr_bussuspend);
+	device_remove_file(&dev->dev, &dev_attr_busconnected);
+	device_remove_file(&dev->dev, &dev_attr_gotgctl);
+	device_remove_file(&dev->dev, &dev_attr_gusbcfg);
+	device_remove_file(&dev->dev, &dev_attr_grxfsiz);
+	device_remove_file(&dev->dev, &dev_attr_gnptxfsiz);
+	device_remove_file(&dev->dev, &dev_attr_gpvndctl);
+	device_remove_file(&dev->dev, &dev_attr_ggpio);
+	device_remove_file(&dev->dev, &dev_attr_guid);
+	device_remove_file(&dev->dev, &dev_attr_gsnpsid);
+	device_remove_file(&dev->dev, &dev_attr_devspeed);
+	device_remove_file(&dev->dev, &dev_attr_enumspeed);
+	device_remove_file(&dev->dev, &dev_attr_hptxfsiz);
+	device_remove_file(&dev->dev, &dev_attr_hprt0);
+	device_remove_file(&dev->dev, &dev_attr_remote_wakeup);
+	device_remove_file(&dev->dev, &dev_attr_regdump);
+	device_remove_file(&dev->dev, &dev_attr_spramdump);
+	device_remove_file(&dev->dev, &dev_attr_hcddump);
+	device_remove_file(&dev->dev, &dev_attr_hcd_frrem);
+	device_remove_file(&dev->dev, &dev_attr_rd_reg_test);
+	device_remove_file(&dev->dev, &dev_attr_wr_reg_test);
+#ifdef CONFIG_USB_DWC_OTG_LPM
+	device_remove_file(&dev->dev, &dev_attr_lpm_response);
+	device_remove_file(&dev->dev, &dev_attr_sleep_status);
+#endif
+}
diff --git a/drivers/usb/host/dwc_otg/dwc_otg_attr.h b/drivers/usb/host/dwc_otg/dwc_otg_attr.h
new file mode 100644
index 000000000000..b59651d50875
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/dwc_otg_attr.h
@@ -0,0 +1,88 @@
+/* ==========================================================================
+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.h $
+ * $Revision: #11 $
+ * $Date: 2009/04/03 $
+ * $Change: 1225160 $
+ *
+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+ * otherwise expressly agreed to in writing between Synopsys and you.
+ * 
+ * The Software IS NOT an item of Licensed Software or Licensed Product under
+ * any End User Software License Agreement or Agreement for Licensed Product
+ * with Synopsys or any supplement thereto. You are permitted to use and
+ * redistribute this Software in source and binary forms, with or without
+ * modification, provided that redistributions of source code must retain this
+ * notice. You may not view, use, disclose, copy or distribute this file or
+ * any information contained herein except pursuant to this license grant from
+ * Synopsys. If you do not agree with this notice, including the disclaimer
+ * below, then you are not authorized to use the Software.
+ * 
+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ * ========================================================================== */
+
+#if !defined(__DWC_OTG_ATTR_H__)
+#define __DWC_OTG_ATTR_H__
+
+/** @file
+ * This file contains the interface to the Linux device attributes.
+ */
+extern struct device_attribute dev_attr_regoffset;
+extern struct device_attribute dev_attr_regvalue;
+
+extern struct device_attribute dev_attr_mode;
+extern struct device_attribute dev_attr_hnpcapable;
+extern struct device_attribute dev_attr_srpcapable;
+extern struct device_attribute dev_attr_hnp;
+extern struct device_attribute dev_attr_srp;
+extern struct device_attribute dev_attr_buspower;
+extern struct device_attribute dev_attr_bussuspend;
+extern struct device_attribute dev_attr_busconnected;
+extern struct device_attribute dev_attr_gotgctl;
+extern struct device_attribute dev_attr_gusbcfg;
+extern struct device_attribute dev_attr_grxfsiz;
+extern struct device_attribute dev_attr_gnptxfsiz;
+extern struct device_attribute dev_attr_gpvndctl;
+extern struct device_attribute dev_attr_ggpio;
+extern struct device_attribute dev_attr_guid;
+extern struct device_attribute dev_attr_gsnpsid;
+extern struct device_attribute dev_attr_devspeed;
+extern struct device_attribute dev_attr_enumspeed;
+extern struct device_attribute dev_attr_hptxfsiz;
+extern struct device_attribute dev_attr_hprt0;
+#ifdef CONFIG_USB_DWC_OTG_LPM
+extern struct device_attribute dev_attr_lpm_response;
+extern struct device_attribute dev_attr_sleep_local_dev;
+extern struct device_attribute devi_attr_sleep_status;
+#endif
+
+void dwc_otg_attr_create (
+#ifdef LM_INTERFACE
+	struct lm_device *dev
+#elif  defined(PCI_INTERFACE)
+	struct pci_dev *dev
+#elif  defined(PLATFORM_INTERFACE)
+	struct platform_device *dev
+#endif
+	);
+
+void dwc_otg_attr_remove (
+#ifdef LM_INTERFACE
+	struct lm_device *dev
+#elif  defined(PCI_INTERFACE)
+	struct pci_dev *dev
+#elif  defined(PLATFORM_INTERFACE)
+	struct platform_device *dev
+#endif
+	);
+#endif
diff --git a/drivers/usb/host/dwc_otg/dwc_otg_cfi.c b/drivers/usb/host/dwc_otg/dwc_otg_cfi.c
new file mode 100644
index 000000000000..7fe725545b48
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/dwc_otg_cfi.c
@@ -0,0 +1,1876 @@
+/* ==========================================================================
+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+ * otherwise expressly agreed to in writing between Synopsys and you.
+ * 
+ * The Software IS NOT an item of Licensed Software or Licensed Product under
+ * any End User Software License Agreement or Agreement for Licensed Product
+ * with Synopsys or any supplement thereto. You are permitted to use and
+ * redistribute this Software in source and binary forms, with or without
+ * modification, provided that redistributions of source code must retain this
+ * notice. You may not view, use, disclose, copy or distribute this file or
+ * any information contained herein except pursuant to this license grant from
+ * Synopsys. If you do not agree with this notice, including the disclaimer
+ * below, then you are not authorized to use the Software.
+ * 
+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ * ========================================================================== */
+
+/** @file 
+ *
+ * This file contains the most of the CFI implementation for the OTG.
+ */
+
+#ifdef DWC_UTE_CFI
+
+#include "dwc_otg_pcd.h"
+#include "dwc_otg_cfi.h"
+
+/** This definition should actually migrate to the Portability Library */
+#define DWC_CONSTANT_CPU_TO_LE16(x) (x)
+
+extern dwc_otg_pcd_ep_t *get_ep_by_addr(dwc_otg_pcd_t * pcd, u16 wIndex);
+
+static int cfi_core_features_buf(uint8_t * buf, uint16_t buflen);
+static int cfi_get_feature_value(uint8_t * buf, uint16_t buflen,
+				 struct dwc_otg_pcd *pcd,
+				 struct cfi_usb_ctrlrequest *ctrl_req);
+static int cfi_set_feature_value(struct dwc_otg_pcd *pcd);
+static int cfi_ep_get_sg_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
+			     struct cfi_usb_ctrlrequest *req);
+static int cfi_ep_get_concat_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
+				 struct cfi_usb_ctrlrequest *req);
+static int cfi_ep_get_align_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
+				struct cfi_usb_ctrlrequest *req);
+static int cfi_preproc_reset(struct dwc_otg_pcd *pcd,
+			     struct cfi_usb_ctrlrequest *req);
+static void cfi_free_ep_bs_dyn_data(cfi_ep_t * cfiep);
+
+static uint16_t get_dfifo_size(dwc_otg_core_if_t * core_if);
+static int32_t get_rxfifo_size(dwc_otg_core_if_t * core_if, uint16_t wValue);
+static int32_t get_txfifo_size(struct dwc_otg_pcd *pcd, uint16_t wValue);
+
+static uint8_t resize_fifos(dwc_otg_core_if_t * core_if);
+
+/** This is the header of the all features descriptor */
+static cfi_all_features_header_t all_props_desc_header = {
+	.wVersion = DWC_CONSTANT_CPU_TO_LE16(0x100),
+	.wCoreID = DWC_CONSTANT_CPU_TO_LE16(CFI_CORE_ID_OTG),
+	.wNumFeatures = DWC_CONSTANT_CPU_TO_LE16(9),
+};
+
+/** This is an array of statically allocated feature descriptors */
+static cfi_feature_desc_header_t prop_descs[] = {
+
+	/* FT_ID_DMA_MODE */
+	{
+	 .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_MODE),
+	 .bmAttributes = CFI_FEATURE_ATTR_RW,
+	 .wDataLength = DWC_CONSTANT_CPU_TO_LE16(1),
+	 },
+
+	/* FT_ID_DMA_BUFFER_SETUP */
+	{
+	 .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_BUFFER_SETUP),
+	 .bmAttributes = CFI_FEATURE_ATTR_RW,
+	 .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6),
+	 },
+
+	/* FT_ID_DMA_BUFF_ALIGN */
+	{
+	 .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_BUFF_ALIGN),
+	 .bmAttributes = CFI_FEATURE_ATTR_RW,
+	 .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
+	 },
+
+	/* FT_ID_DMA_CONCAT_SETUP */
+	{
+	 .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_CONCAT_SETUP),
+	 .bmAttributes = CFI_FEATURE_ATTR_RW,
+	 //.wDataLength  = DWC_CONSTANT_CPU_TO_LE16(6),
+	 },
+
+	/* FT_ID_DMA_CIRCULAR */
+	{
+	 .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_CIRCULAR),
+	 .bmAttributes = CFI_FEATURE_ATTR_RW,
+	 .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6),
+	 },
+
+	/* FT_ID_THRESHOLD_SETUP */
+	{
+	 .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_THRESHOLD_SETUP),
+	 .bmAttributes = CFI_FEATURE_ATTR_RW,
+	 .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6),
+	 },
+
+	/* FT_ID_DFIFO_DEPTH */
+	{
+	 .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DFIFO_DEPTH),
+	 .bmAttributes = CFI_FEATURE_ATTR_RO,
+	 .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
+	 },
+
+	/* FT_ID_TX_FIFO_DEPTH */
+	{
+	 .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_TX_FIFO_DEPTH),
+	 .bmAttributes = CFI_FEATURE_ATTR_RW,
+	 .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
+	 },
+
+	/* FT_ID_RX_FIFO_DEPTH */
+	{
+	 .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_RX_FIFO_DEPTH),
+	 .bmAttributes = CFI_FEATURE_ATTR_RW,
+	 .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
+	 }
+};
+
+/** The table of feature names */
+cfi_string_t prop_name_table[] = {
+	{FT_ID_DMA_MODE, "dma_mode"},
+	{FT_ID_DMA_BUFFER_SETUP, "buffer_setup"},
+	{FT_ID_DMA_BUFF_ALIGN, "buffer_align"},
+	{FT_ID_DMA_CONCAT_SETUP, "concat_setup"},
+	{FT_ID_DMA_CIRCULAR, "buffer_circular"},
+	{FT_ID_THRESHOLD_SETUP, "threshold_setup"},
+	{FT_ID_DFIFO_DEPTH, "dfifo_depth"},
+	{FT_ID_TX_FIFO_DEPTH, "txfifo_depth"},
+	{FT_ID_RX_FIFO_DEPTH, "rxfifo_depth"},
+	{}
+};
+
+/************************************************************************/
+
+/** 
+ * Returns the name of the feature by its ID 
+ * or NULL if no featute ID matches.
+ * 
+ */
+const uint8_t *get_prop_name(uint16_t prop_id, int *len)
+{
+	cfi_string_t *pstr;
+	*len = 0;
+
+	for (pstr = prop_name_table; pstr && pstr->s; pstr++) {
+		if (pstr->id == prop_id) {
+			*len = DWC_STRLEN(pstr->s);
+			return pstr->s;
+		}
+	}
+	return NULL;
+}
+
+/**
+ * This function handles all CFI specific control requests.
+ * 
+ * Return a negative value to stall the DCE.
+ */
+int cfi_setup(struct dwc_otg_pcd *pcd, struct cfi_usb_ctrlrequest *ctrl)
+{
+	int retval = 0;
+	dwc_otg_pcd_ep_t *ep = NULL;
+	cfiobject_t *cfi = pcd->cfi;
+	struct dwc_otg_core_if *coreif = GET_CORE_IF(pcd);
+	uint16_t wLen = DWC_LE16_TO_CPU(&ctrl->wLength);
+	uint16_t wValue = DWC_LE16_TO_CPU(&ctrl->wValue);
+	uint16_t wIndex = DWC_LE16_TO_CPU(&ctrl->wIndex);
+	uint32_t regaddr = 0;
+	uint32_t regval = 0;
+
+	/* Save this Control Request in the CFI object. 
+	 * The data field will be assigned in the data stage completion CB function.
+	 */
+	cfi->ctrl_req = *ctrl;
+	cfi->ctrl_req.data = NULL;
+
+	cfi->need_gadget_att = 0;
+	cfi->need_status_in_complete = 0;
+
+	switch (ctrl->bRequest) {
+	case VEN_CORE_GET_FEATURES:
+		retval = cfi_core_features_buf(cfi->buf_in.buf, CFI_IN_BUF_LEN);
+		if (retval >= 0) {
+			//dump_msg(cfi->buf_in.buf, retval);
+			ep = &pcd->ep0;
+
+			retval = min((uint16_t) retval, wLen);
+			/* Transfer this buffer to the host through the EP0-IN EP */
+			ep->dwc_ep.dma_addr = cfi->buf_in.addr;
+			ep->dwc_ep.start_xfer_buff = cfi->buf_in.buf;
+			ep->dwc_ep.xfer_buff = cfi->buf_in.buf;
+			ep->dwc_ep.xfer_len = retval;
+			ep->dwc_ep.xfer_count = 0;
+			ep->dwc_ep.sent_zlp = 0;
+			ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
+
+			pcd->ep0_pending = 1;
+			dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
+		}
+		retval = 0;
+		break;
+
+	case VEN_CORE_GET_FEATURE:
+		CFI_INFO("VEN_CORE_GET_FEATURE\n");
+		retval = cfi_get_feature_value(cfi->buf_in.buf, CFI_IN_BUF_LEN,
+					       pcd, ctrl);
+		if (retval >= 0) {
+			ep = &pcd->ep0;
+
+			retval = min((uint16_t) retval, wLen);
+			/* Transfer this buffer to the host through the EP0-IN EP */
+			ep->dwc_ep.dma_addr = cfi->buf_in.addr;
+			ep->dwc_ep.start_xfer_buff = cfi->buf_in.buf;
+			ep->dwc_ep.xfer_buff = cfi->buf_in.buf;
+			ep->dwc_ep.xfer_len = retval;
+			ep->dwc_ep.xfer_count = 0;
+			ep->dwc_ep.sent_zlp = 0;
+			ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
+
+			pcd->ep0_pending = 1;
+			dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
+		}
+		CFI_INFO("VEN_CORE_GET_FEATURE=%d\n", retval);
+		dump_msg(cfi->buf_in.buf, retval);
+		break;
+
+	case VEN_CORE_SET_FEATURE:
+		CFI_INFO("VEN_CORE_SET_FEATURE\n");
+		/* Set up an XFER to get the data stage of the control request,
+		 * which is the new value of the feature to be modified.
+		 */
+		ep = &pcd->ep0;
+		ep->dwc_ep.is_in = 0;
+		ep->dwc_ep.dma_addr = cfi->buf_out.addr;
+		ep->dwc_ep.start_xfer_buff = cfi->buf_out.buf;
+		ep->dwc_ep.xfer_buff = cfi->buf_out.buf;
+		ep->dwc_ep.xfer_len = wLen;
+		ep->dwc_ep.xfer_count = 0;
+		ep->dwc_ep.sent_zlp = 0;
+		ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
+
+		pcd->ep0_pending = 1;
+		/* Read the control write's data stage */
+		dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
+		retval = 0;
+		break;
+
+	case VEN_CORE_RESET_FEATURES:
+		CFI_INFO("VEN_CORE_RESET_FEATURES\n");
+		cfi->need_gadget_att = 1;
+		cfi->need_status_in_complete = 1;
+		retval = cfi_preproc_reset(pcd, ctrl);
+		CFI_INFO("VEN_CORE_RESET_FEATURES = (%d)\n", retval);
+		break;
+
+	case VEN_CORE_ACTIVATE_FEATURES:
+		CFI_INFO("VEN_CORE_ACTIVATE_FEATURES\n");
+		break;
+
+	case VEN_CORE_READ_REGISTER:
+		CFI_INFO("VEN_CORE_READ_REGISTER\n");
+		/* wValue optionally contains the HI WORD of the register offset and
+		 * wIndex contains the LOW WORD of the register offset 
+		 */
+		if (wValue == 0) {
+			/* @TODO - MAS - fix the access to the base field */
+			regaddr = 0;
+			//regaddr = (uint32_t) pcd->otg_dev->base;
+			//GET_CORE_IF(pcd)->co
+			regaddr |= wIndex;
+		} else {
+			regaddr = (wValue << 16) | wIndex;
+		}
+
+		/* Read a 32-bit value of the memory at the regaddr */
+		regval = dwc_read_reg32((uint32_t *) regaddr);
+
+		ep = &pcd->ep0;
+		dwc_memcpy(cfi->buf_in.buf, &regval, sizeof(uint32_t));
+		ep->dwc_ep.is_in = 1;
+		ep->dwc_ep.dma_addr = cfi->buf_in.addr;
+		ep->dwc_ep.start_xfer_buff = cfi->buf_in.buf;
+		ep->dwc_ep.xfer_buff = cfi->buf_in.buf;
+		ep->dwc_ep.xfer_len = wLen;
+		ep->dwc_ep.xfer_count = 0;
+		ep->dwc_ep.sent_zlp = 0;
+		ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
+
+		pcd->ep0_pending = 1;
+		dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
+		cfi->need_gadget_att = 0;
+		retval = 0;
+		break;
+
+	case VEN_CORE_WRITE_REGISTER:
+		CFI_INFO("VEN_CORE_WRITE_REGISTER\n");
+		/* Set up an XFER to get the data stage of the control request,
+		 * which is the new value of the register to be modified.
+		 */
+		ep = &pcd->ep0;
+		ep->dwc_ep.is_in = 0;
+		ep->dwc_ep.dma_addr = cfi->buf_out.addr;
+		ep->dwc_ep.start_xfer_buff = cfi->buf_out.buf;
+		ep->dwc_ep.xfer_buff = cfi->buf_out.buf;
+		ep->dwc_ep.xfer_len = wLen;
+		ep->dwc_ep.xfer_count = 0;
+		ep->dwc_ep.sent_zlp = 0;
+		ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
+
+		pcd->ep0_pending = 1;
+		/* Read the control write's data stage */
+		dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
+		retval = 0;
+		break;
+
+	default:
+		retval = -DWC_E_NOT_SUPPORTED;
+		break;
+	}
+
+	return retval;
+}
+
+/**
+ * This function prepares the core features descriptors and copies its
+ * raw representation into the buffer <buf>.
+ * 
+ * The buffer structure is as follows:
+ *	all_features_header (8 bytes)
+ *	features_#1 (8 bytes + feature name string length)
+ *	features_#2 (8 bytes + feature name string length)
+ *	.....
+ *	features_#n - where n=the total count of feature descriptors
+ */
+static int cfi_core_features_buf(uint8_t * buf, uint16_t buflen)
+{
+	cfi_feature_desc_header_t *prop_hdr = prop_descs;
+	cfi_feature_desc_header_t *prop;
+	cfi_all_features_header_t *all_props_hdr = &all_props_desc_header;
+	cfi_all_features_header_t *tmp;
+	uint8_t *tmpbuf = buf;
+	const uint8_t *pname = NULL;
+	int i, j, namelen = 0, totlen;
+
+	/* Prepare and copy the core features into the buffer */
+	CFI_INFO("%s:\n", __func__);
+
+	tmp = (cfi_all_features_header_t *) tmpbuf;
+	*tmp = *all_props_hdr;
+	tmpbuf += CFI_ALL_FEATURES_HDR_LEN;
+
+	j = sizeof(prop_descs) / sizeof(cfi_all_features_header_t);
+	for (i = 0; i < j; i++, prop_hdr++) {
+		pname = get_prop_name(prop_hdr->wFeatureID, &namelen);
+		prop = (cfi_feature_desc_header_t *) tmpbuf;
+		*prop = *prop_hdr;
+
+		prop->bNameLen = namelen;
+		prop->wLength =
+		    DWC_CONSTANT_CPU_TO_LE16(CFI_FEATURE_DESC_HDR_LEN +
+					     namelen);
+
+		tmpbuf += CFI_FEATURE_DESC_HDR_LEN;
+		dwc_memcpy(tmpbuf, pname, namelen);
+		tmpbuf += namelen;
+	}
+
+	totlen = tmpbuf - buf;
+
+	if (totlen > 0) {
+		tmp = (cfi_all_features_header_t *) buf;
+		tmp->wTotalLen = DWC_CONSTANT_CPU_TO_LE16(totlen);
+	}
+
+	return totlen;
+}
+
+/**
+ * This function releases all the dynamic memory in the CFI object.
+ */
+static void cfi_release(cfiobject_t * cfiobj)
+{
+	cfi_ep_t *cfiep;
+	dwc_list_link_t *tmp;
+
+	CFI_INFO("%s\n", __func__);
+
+	if (cfiobj->buf_in.buf) {
+		dwc_dma_free(CFI_IN_BUF_LEN, cfiobj->buf_in.buf,
+			     cfiobj->buf_in.addr);
+		cfiobj->buf_in.buf = NULL;
+	}
+
+	if (cfiobj->buf_out.buf) {
+		dwc_dma_free(CFI_OUT_BUF_LEN, cfiobj->buf_out.buf,
+			     cfiobj->buf_out.addr);
+		cfiobj->buf_out.buf = NULL;
+	}
+
+	/* Free the Buffer Setup values for each EP */
+	//list_for_each_entry(cfiep, &cfiobj->active_eps, lh) {
+	DWC_LIST_FOREACH(tmp, &cfiobj->active_eps) {
+		cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
+		cfi_free_ep_bs_dyn_data(cfiep);
+	}
+}
+
+/**
+ * This function frees the dynamically allocated EP buffer setup data.
+ */
+static void cfi_free_ep_bs_dyn_data(cfi_ep_t * cfiep)
+{
+	if (cfiep->bm_sg) {
+		dwc_free(cfiep->bm_sg);
+		cfiep->bm_sg = NULL;
+	}
+
+	if (cfiep->bm_align) {
+		dwc_free(cfiep->bm_align);
+		cfiep->bm_align = NULL;
+	}
+
+	if (cfiep->bm_concat) {
+		if (NULL != cfiep->bm_concat->wTxBytes) {
+			dwc_free(cfiep->bm_concat->wTxBytes);
+			cfiep->bm_concat->wTxBytes = NULL;
+		}
+		dwc_free(cfiep->bm_concat);
+		cfiep->bm_concat = NULL;
+	}
+}
+
+/**
+ * This function initializes the default values of the features
+ * for a specific endpoint and should be called only once when
+ * the EP is enabled first time.
+ */
+static int cfi_ep_init_defaults(struct dwc_otg_pcd *pcd, cfi_ep_t * cfiep)
+{
+	int retval = 0;
+
+	cfiep->bm_sg = dwc_alloc(sizeof(ddma_sg_buffer_setup_t));
+	if (NULL == cfiep->bm_sg) {
+		CFI_INFO("Failed to allocate memory for SG feature value\n");
+		return -DWC_E_NO_MEMORY;
+	}
+	dwc_memset(cfiep->bm_sg, 0, sizeof(ddma_sg_buffer_setup_t));
+
+	/* For the Concatenation feature's default value we do not allocate
+	 * memory for the wTxBytes field - it will be done in the set_feature_value
+	 * request handler.
+	 */
+	cfiep->bm_concat = dwc_alloc(sizeof(ddma_concat_buffer_setup_t));
+	if (NULL == cfiep->bm_concat) {
+		CFI_INFO
+		    ("Failed to allocate memory for CONCATENATION feature value\n");
+		dwc_free(cfiep->bm_sg);
+		return -DWC_E_NO_MEMORY;
+	}
+	dwc_memset(cfiep->bm_concat, 0, sizeof(ddma_concat_buffer_setup_t));
+
+	cfiep->bm_align = dwc_alloc(sizeof(ddma_align_buffer_setup_t));
+	if (NULL == cfiep->bm_align) {
+		CFI_INFO
+		    ("Failed to allocate memory for Alignment feature value\n");
+		dwc_free(cfiep->bm_sg);
+		dwc_free(cfiep->bm_concat);
+		return -DWC_E_NO_MEMORY;
+	}
+	dwc_memset(cfiep->bm_align, 0, sizeof(ddma_align_buffer_setup_t));
+
+	return retval;
+}
+
+/**
+ * The callback function that notifies the CFI on the activation of
+ * an endpoint in the PCD. The following steps are done in this function:
+ *
+ *	Create a dynamically allocated cfi_ep_t object (a CFI wrapper to the PCD's 
+ *		active endpoint)
+ *	Create MAX_DMA_DESCS_PER_EP count DMA Descriptors for the EP
+ *	Set the Buffer Mode to standard
+ *	Initialize the default values for all EP modes (SG, Circular, Concat, Align)
+ *	Add the cfi_ep_t object to the list of active endpoints in the CFI object
+ */
+static int cfi_ep_enable(struct cfiobject *cfi, struct dwc_otg_pcd *pcd,
+			 struct dwc_otg_pcd_ep *ep)
+{
+	cfi_ep_t *cfiep;
+	int retval = -DWC_E_NOT_SUPPORTED;
+
+	CFI_INFO("%s: epname=%s; epnum=0x%02x\n", __func__,
+		 "EP_" /*ep->ep.name */ , ep->desc->bEndpointAddress);
+	/* MAS - Check whether this endpoint already is in the list */
+	cfiep = get_cfi_ep_by_pcd_ep(cfi, ep);
+
+	if (NULL == cfiep) {
+		/* Allocate a cfi_ep_t object */
+		cfiep = dwc_alloc(sizeof(cfi_ep_t));
+		if (NULL == cfiep) {
+			CFI_INFO
+			    ("Unable to allocate memory for <cfiep> in function %s\n",
+			     __func__);
+			return -DWC_E_NO_MEMORY;
+		}
+		dwc_memset(cfiep, 0, sizeof(cfi_ep_t));
+
+		/* Save the dwc_otg_pcd_ep pointer in the cfiep object */
+		cfiep->ep = ep;
+
+		/* Allocate the DMA Descriptors chain of MAX_DMA_DESCS_PER_EP count */
+		ep->dwc_ep.descs =
+		    dwc_dma_alloc(MAX_DMA_DESCS_PER_EP *
+				  sizeof(dwc_otg_dma_desc_t),
+				  &ep->dwc_ep.descs_dma_addr);
+
+		if (NULL == ep->dwc_ep.descs) {
+			dwc_free(cfiep);
+			return -DWC_E_NO_MEMORY;
+		}
+
+		DWC_LIST_INIT(&cfiep->lh);
+
+		/* Set the buffer mode to BM_STANDARD. It will be modified 
+		 * when building descriptors for a specific buffer mode */
+		ep->dwc_ep.buff_mode = BM_STANDARD;
+
+		/* Create and initialize the default values for this EP's Buffer modes */
+		if ((retval = cfi_ep_init_defaults(pcd, cfiep)) < 0)
+			return retval;
+
+		/* Add the cfi_ep_t object to the CFI object's list of active endpoints */
+		DWC_LIST_INSERT_TAIL(&cfi->active_eps, &cfiep->lh);
+		retval = 0;
+	} else {		/* The sought EP already is in the list */
+		CFI_INFO("%s: The sought EP already is in the list\n",
+			 __func__);
+	}
+
+	return retval;
+}
+
+/**
+ * This function is called when the data stage of a 3-stage Control Write request
+ * is complete.
+ * 
+ */
+static int cfi_ctrl_write_complete(struct cfiobject *cfi,
+				   struct dwc_otg_pcd *pcd)
+{
+	uint32_t addr, reg_value;
+	uint16_t wIndex, wValue;
+	uint8_t bRequest;
+	uint8_t *buf = cfi->buf_out.buf;
+	//struct usb_ctrlrequest *ctrl_req = &cfi->ctrl_req_saved;
+	struct cfi_usb_ctrlrequest *ctrl_req = &cfi->ctrl_req;
+	int retval = -DWC_E_NOT_SUPPORTED;
+
+	CFI_INFO("%s\n", __func__);
+
+	bRequest = ctrl_req->bRequest;
+	wIndex = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wIndex);
+	wValue = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wValue);
+
+	/* 
+	 * Save the pointer to the data stage in the ctrl_req's <data> field.
+	 * The request should be already saved in the command stage by now.
+	 */
+	ctrl_req->data = cfi->buf_out.buf;
+	cfi->need_status_in_complete = 0;
+	cfi->need_gadget_att = 0;
+
+	switch (bRequest) {
+	case VEN_CORE_WRITE_REGISTER:
+		/* The buffer contains raw data of the new value for the register */
+		reg_value = *((uint32_t *) buf);
+		if (wValue == 0) {
+			addr = 0;
+			//addr = (uint32_t) pcd->otg_dev->base;
+			addr += wIndex;
+		} else {
+			addr = (wValue << 16) | wIndex;
+		}
+
+		//writel(reg_value, addr);
+
+		retval = 0;
+		cfi->need_status_in_complete = 1;
+		break;
+
+	case VEN_CORE_SET_FEATURE:
+		/* The buffer contains raw data of the new value of the feature */
+		retval = cfi_set_feature_value(pcd);
+		if (retval < 0)
+			return retval;
+
+		cfi->need_status_in_complete = 1;
+		break;
+
+	default:
+		break;
+	}
+
+	return retval;
+}
+
+/**
+ * This function builds the DMA descriptors for the SG buffer mode.
+ */
+static void cfi_build_sg_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,
+			       dwc_otg_pcd_request_t * req)
+{
+	struct dwc_otg_pcd_ep *ep = cfiep->ep;
+	ddma_sg_buffer_setup_t *sgval = cfiep->bm_sg;
+	struct dwc_otg_dma_desc *desc = cfiep->ep->dwc_ep.descs;
+	struct dwc_otg_dma_desc *desc_last = cfiep->ep->dwc_ep.descs;
+	dma_addr_t buff_addr = req->dma;
+	int i;
+	uint32_t txsize, off;
+
+	txsize = sgval->wSize;
+	off = sgval->bOffset;
+
+//      CFI_INFO("%s: %s TXSIZE=0x%08x; OFFSET=0x%08x\n", 
+//              __func__, cfiep->ep->ep.name, txsize, off);
+
+	for (i = 0; i < sgval->bCount; i++) {
+		desc->status.b.bs = BS_HOST_BUSY;
+		desc->buf = buff_addr;
+		desc->status.b.l = 0;
+		desc->status.b.ioc = 0;
+		desc->status.b.sp = 0;
+		desc->status.b.bytes = txsize;
+		desc->status.b.bs = BS_HOST_READY;
+
+		/* Set the next address of the buffer */
+		buff_addr += txsize + off;
+		desc_last = desc;
+		desc++;
+	}
+
+	/* Set the last, ioc and sp bits on the Last DMA Descriptor */
+	desc_last->status.b.l = 1;
+	desc_last->status.b.ioc = 1;
+	desc_last->status.b.sp = ep->dwc_ep.sent_zlp;
+	/* Save the last DMA descriptor pointer */
+	cfiep->dma_desc_last = desc_last;
+	cfiep->desc_count = sgval->bCount;
+}
+
+/**
+ * This function builds the DMA descriptors for the Concatenation buffer mode.
+ */
+static void cfi_build_concat_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,
+				   dwc_otg_pcd_request_t * req)
+{
+	struct dwc_otg_pcd_ep *ep = cfiep->ep;
+	ddma_concat_buffer_setup_t *concatval = cfiep->bm_concat;
+	struct dwc_otg_dma_desc *desc = cfiep->ep->dwc_ep.descs;
+	struct dwc_otg_dma_desc *desc_last = cfiep->ep->dwc_ep.descs;
+	dma_addr_t buff_addr = req->dma;
+	int i;
+	uint16_t *txsize;
+
+	txsize = concatval->wTxBytes;
+
+	for (i = 0; i < concatval->hdr.bDescCount; i++) {
+		desc->buf = buff_addr;
+		desc->status.b.bs = BS_HOST_BUSY;
+		desc->status.b.l = 0;
+		desc->status.b.ioc = 0;
+		desc->status.b.sp = 0;
+		desc->status.b.bytes = *txsize;
+		desc->status.b.bs = BS_HOST_READY;
+
+		txsize++;
+		/* Set the next address of the buffer */
+		buff_addr += UGETW(ep->desc->wMaxPacketSize);
+		desc_last = desc;
+		desc++;
+	}
+
+	/* Set the last, ioc and sp bits on the Last DMA Descriptor */
+	desc_last->status.b.l = 1;
+	desc_last->status.b.ioc = 1;
+	desc_last->status.b.sp = ep->dwc_ep.sent_zlp;
+	cfiep->dma_desc_last = desc_last;
+	cfiep->desc_count = concatval->hdr.bDescCount;
+}
+
+/**
+ * This function builds the DMA descriptors for the Circular buffer mode
+ */
+static void cfi_build_circ_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,
+				 dwc_otg_pcd_request_t * req)
+{
+	/* @todo: MAS - add implementation when this feature needs to be tested */
+}
+
+/**
+ * This function builds the DMA descriptors for the Alignment buffer mode
+ */
+static void cfi_build_align_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,
+				  dwc_otg_pcd_request_t * req)
+{
+	struct dwc_otg_pcd_ep *ep = cfiep->ep;
+	ddma_align_buffer_setup_t *alignval = cfiep->bm_align;
+	struct dwc_otg_dma_desc *desc = cfiep->ep->dwc_ep.descs;
+	dma_addr_t buff_addr = req->dma;
+
+	desc->status.b.bs = BS_HOST_BUSY;
+	desc->status.b.l = 1;
+	desc->status.b.ioc = 1;
+	desc->status.b.sp = ep->dwc_ep.sent_zlp;
+	desc->status.b.bytes = req->length;
+	/* Adjust the buffer alignment */
+	desc->buf = (buff_addr + alignval->bAlign);
+	desc->status.b.bs = BS_HOST_READY;
+	cfiep->dma_desc_last = desc;
+	cfiep->desc_count = 1;
+}
+
+/**
+ * This function builds the DMA descriptors chain for different modes of the
+ * buffer setup of an endpoint.
+ */
+static void cfi_build_descriptors(struct cfiobject *cfi,
+				  struct dwc_otg_pcd *pcd,
+				  struct dwc_otg_pcd_ep *ep,
+				  dwc_otg_pcd_request_t * req)
+{
+	cfi_ep_t *cfiep;
+
+	/* Get the cfiep by the dwc_otg_pcd_ep */
+	cfiep = get_cfi_ep_by_pcd_ep(cfi, ep);
+	if (NULL == cfiep) {
+		CFI_INFO("%s: Unable to find a matching active endpoint\n",
+			 __func__);
+		return;
+	}
+
+	cfiep->xfer_len = req->length;
+
+	/* Iterate through all the DMA descriptors */
+	switch (cfiep->ep->dwc_ep.buff_mode) {
+	case BM_SG:
+		cfi_build_sg_descs(cfi, cfiep, req);
+		break;
+
+	case BM_CONCAT:
+		cfi_build_concat_descs(cfi, cfiep, req);
+		break;
+
+	case BM_CIRCULAR:
+		cfi_build_circ_descs(cfi, cfiep, req);
+		break;
+
+	case BM_ALIGN:
+		cfi_build_align_descs(cfi, cfiep, req);
+		break;
+
+	default:
+		break;
+	}
+}
+
+/**
+ * Allocate DMA buffer for different Buffer modes.
+ */
+static void *cfi_ep_alloc_buf(struct cfiobject *cfi, struct dwc_otg_pcd *pcd,
+			      struct dwc_otg_pcd_ep *ep, dma_addr_t * dma,
+			      unsigned size, gfp_t flags)
+{
+	return dwc_dma_alloc(size, dma);
+}
+
+/**
+ * This function initializes the CFI object.
+ */
+int init_cfi(cfiobject_t * cfiobj)
+{
+	CFI_INFO("%s\n", __func__);
+
+	/* Allocate a buffer for IN XFERs */
+	cfiobj->buf_in.buf =
+	    dwc_dma_alloc(CFI_IN_BUF_LEN, &cfiobj->buf_in.addr);
+	if (NULL == cfiobj->buf_in.buf) {
+		CFI_INFO("Unable to allocate buffer for INs\n");
+		return -DWC_E_NO_MEMORY;
+	}
+
+	/* Allocate a buffer for OUT XFERs */
+	cfiobj->buf_out.buf =
+	    dwc_dma_alloc(CFI_OUT_BUF_LEN, &cfiobj->buf_out.addr);
+	if (NULL == cfiobj->buf_out.buf) {
+		CFI_INFO("Unable to allocate buffer for OUT\n");
+		return -DWC_E_NO_MEMORY;
+	}
+
+	/* Initialize the callback function pointers */
+	cfiobj->ops.release = cfi_release;
+	cfiobj->ops.ep_enable = cfi_ep_enable;
+	cfiobj->ops.ctrl_write_complete = cfi_ctrl_write_complete;
+	cfiobj->ops.build_descriptors = cfi_build_descriptors;
+	cfiobj->ops.ep_alloc_buf = cfi_ep_alloc_buf;
+
+	/* Initialize the list of active endpoints in the CFI object */
+	DWC_LIST_INIT(&cfiobj->active_eps);
+
+	return 0;
+}
+
+/**
+ * This function reads the required feature's current value into the buffer
+ *
+ * @retval: Returns negative as error, or the data length of the feature  
+ */
+static int cfi_get_feature_value(uint8_t * buf, uint16_t buflen,
+				 struct dwc_otg_pcd *pcd,
+				 struct cfi_usb_ctrlrequest *ctrl_req)
+{
+	int retval = -DWC_E_NOT_SUPPORTED;
+	struct dwc_otg_core_if *coreif = GET_CORE_IF(pcd);
+	uint16_t dfifo, rxfifo, txfifo;
+
+	switch (ctrl_req->wIndex) {
+		/* Whether the DDMA is enabled or not */
+	case FT_ID_DMA_MODE:
+		*buf = (coreif->dma_enable && coreif->dma_desc_enable) ? 1 : 0;
+		retval = 1;
+		break;
+
+	case FT_ID_DMA_BUFFER_SETUP:
+		retval = cfi_ep_get_sg_val(buf, pcd, ctrl_req);
+		break;
+
+	case FT_ID_DMA_BUFF_ALIGN:
+		retval = cfi_ep_get_align_val(buf, pcd, ctrl_req);
+		break;
+
+	case FT_ID_DMA_CONCAT_SETUP:
+		retval = cfi_ep_get_concat_val(buf, pcd, ctrl_req);
+		break;
+
+	case FT_ID_DMA_CIRCULAR:
+		CFI_INFO("GetFeature value (FT_ID_DMA_CIRCULAR)\n");
+		break;
+
+	case FT_ID_THRESHOLD_SETUP:
+		CFI_INFO("GetFeature value (FT_ID_THRESHOLD_SETUP)\n");
+		break;
+
+	case FT_ID_DFIFO_DEPTH:
+		dfifo = get_dfifo_size(coreif);
+		*((uint16_t *) buf) = dfifo;
+		retval = sizeof(uint16_t);
+		break;
+
+	case FT_ID_TX_FIFO_DEPTH:
+		retval = get_txfifo_size(pcd, ctrl_req->wValue);
+		if (retval >= 0) {
+			txfifo = retval;
+			*((uint16_t *) buf) = txfifo;
+			retval = sizeof(uint16_t);
+		}
+		break;
+
+	case FT_ID_RX_FIFO_DEPTH:
+		retval = get_rxfifo_size(coreif, ctrl_req->wValue);
+		if (retval >= 0) {
+			rxfifo = retval;
+			*((uint16_t *) buf) = rxfifo;
+			retval = sizeof(uint16_t);
+		}
+		break;
+	}
+
+	return retval;
+}
+
+/**
+ * This function resets the SG for the specified EP to its default value
+ */
+static int cfi_reset_sg_val(cfi_ep_t * cfiep)
+{
+	dwc_memset(cfiep->bm_sg, 0, sizeof(ddma_sg_buffer_setup_t));
+	return 0;
+}
+
+/**
+ * This function resets the Alignment for the specified EP to its default value
+ */
+static int cfi_reset_align_val(cfi_ep_t * cfiep)
+{
+	dwc_memset(cfiep->bm_sg, 0, sizeof(ddma_sg_buffer_setup_t));
+	return 0;
+}
+
+/**
+ * This function resets the Concatenation for the specified EP to its default value
+ * This function will also set the value of the wTxBytes field to NULL after 
+ * freeing the memory previously allocated for this field.
+ */
+static int cfi_reset_concat_val(cfi_ep_t * cfiep)
+{
+	/* First we need to free the wTxBytes field */
+	if (cfiep->bm_concat->wTxBytes) {
+		dwc_free(cfiep->bm_concat->wTxBytes);
+		cfiep->bm_concat->wTxBytes = NULL;
+	}
+
+	dwc_memset(cfiep->bm_concat, 0, sizeof(ddma_concat_buffer_setup_t));
+	return 0;
+}
+
+/**
+ * This function resets all the buffer setups of the specified endpoint
+ */
+static int cfi_ep_reset_all_setup_vals(cfi_ep_t * cfiep)
+{
+	cfi_reset_sg_val(cfiep);
+	cfi_reset_align_val(cfiep);
+	cfi_reset_concat_val(cfiep);
+	return 0;
+}
+
+static int cfi_handle_reset_fifo_val(struct dwc_otg_pcd *pcd, uint8_t ep_addr,
+				     uint8_t rx_rst, uint8_t tx_rst)
+{
+	int retval = -DWC_E_INVALID;
+	uint16_t tx_siz[15];
+	uint16_t rx_siz = 0;
+	dwc_otg_pcd_ep_t *ep = NULL;
+	dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+	dwc_otg_core_params_t *params = GET_CORE_IF(pcd)->core_params;
+
+	if (rx_rst) {
+		rx_siz = params->dev_rx_fifo_size;
+		params->dev_rx_fifo_size = GET_CORE_IF(pcd)->init_rxfsiz;
+	}
+
+	if (tx_rst) {
+		if (ep_addr == 0) {
+			int i;
+
+			for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
+				tx_siz[i] =
+				    core_if->core_params->dev_tx_fifo_size[i];
+				core_if->core_params->dev_tx_fifo_size[i] =
+				    core_if->init_txfsiz[i];
+			}
+		} else {
+
+			ep = get_ep_by_addr(pcd, ep_addr);
+
+			if (NULL == ep) {
+				CFI_INFO
+				    ("%s: Unable to get the endpoint addr=0x%02x\n",
+				     __func__, ep_addr);
+				return -DWC_E_INVALID;
+			}
+
+			tx_siz[0] =
+			    params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num -
+						     1];
+			params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1] =
+			    GET_CORE_IF(pcd)->init_txfsiz[ep->dwc_ep.
+							  tx_fifo_num - 1];
+		}
+	}
+
+	if (resize_fifos(GET_CORE_IF(pcd))) {
+		retval = 0;
+	} else {
+		CFI_INFO
+		    ("%s: Error resetting the feature Reset All(FIFO size)\n",
+		     __func__);
+		if (rx_rst) {
+			params->dev_rx_fifo_size = rx_siz;
+		}
+
+		if (tx_rst) {
+			if (ep_addr == 0) {
+				int i;
+				for (i = 0; i < core_if->hwcfg4.b.num_in_eps;
+				     i++) {
+					core_if->core_params->
+					    dev_tx_fifo_size[i] = tx_siz[i];
+				}
+			} else {
+				params->dev_tx_fifo_size[ep->dwc_ep.
+							 tx_fifo_num - 1] =
+				    tx_siz[0];
+			}
+		}
+		retval = -DWC_E_INVALID;
+	}
+	return retval;
+}
+
+static int cfi_handle_reset_all(struct dwc_otg_pcd *pcd, uint8_t addr)
+{
+	int retval = 0;
+	cfi_ep_t *cfiep;
+	cfiobject_t *cfi = pcd->cfi;
+	dwc_list_link_t *tmp;
+
+	retval = cfi_handle_reset_fifo_val(pcd, addr, 1, 1);
+	if (retval < 0) {
+		return retval;
+	}
+
+	/* If the EP address is known then reset the features for only that EP */
+	if (addr) {
+		cfiep = get_cfi_ep_by_addr(pcd->cfi, addr);
+		if (NULL == cfiep) {
+			CFI_INFO("%s: Error getting the EP address 0x%02x\n",
+				 __func__, addr);
+			return -DWC_E_INVALID;
+		}
+		retval = cfi_ep_reset_all_setup_vals(cfiep);
+		cfiep->ep->dwc_ep.buff_mode = BM_STANDARD;
+	}
+	/* Otherwise (wValue == 0), reset all features of all EP's */
+	else {
+		/* Traverse all the active EP's and reset the feature(s) value(s) */
+		//list_for_each_entry(cfiep, &cfi->active_eps, lh) {
+		DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
+			cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
+			retval = cfi_ep_reset_all_setup_vals(cfiep);
+			cfiep->ep->dwc_ep.buff_mode = BM_STANDARD;
+			if (retval < 0) {
+				CFI_INFO
+				    ("%s: Error resetting the feature Reset All\n",
+				     __func__);
+				return retval;
+			}
+		}
+	}
+	return retval;
+}
+
+static int cfi_handle_reset_dma_buff_setup(struct dwc_otg_pcd *pcd,
+					   uint8_t addr)
+{
+	int retval = 0;
+	cfi_ep_t *cfiep;
+	cfiobject_t *cfi = pcd->cfi;
+	dwc_list_link_t *tmp;
+
+	/* If the EP address is known then reset the features for only that EP */
+	if (addr) {
+		cfiep = get_cfi_ep_by_addr(pcd->cfi, addr);
+		if (NULL == cfiep) {
+			CFI_INFO("%s: Error getting the EP address 0x%02x\n",
+				 __func__, addr);
+			return -DWC_E_INVALID;
+		}
+		retval = cfi_reset_sg_val(cfiep);
+	}
+	/* Otherwise (wValue == 0), reset all features of all EP's */
+	else {
+		/* Traverse all the active EP's and reset the feature(s) value(s) */
+		//list_for_each_entry(cfiep, &cfi->active_eps, lh) {
+		DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
+			cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
+			retval = cfi_reset_sg_val(cfiep);
+			if (retval < 0) {
+				CFI_INFO
+				    ("%s: Error resetting the feature Buffer Setup\n",
+				     __func__);
+				return retval;
+			}
+		}
+	}
+	return retval;
+}
+
+static int cfi_handle_reset_concat_val(struct dwc_otg_pcd *pcd, uint8_t addr)
+{
+	int retval = 0;
+	cfi_ep_t *cfiep;
+	cfiobject_t *cfi = pcd->cfi;
+	dwc_list_link_t *tmp;
+
+	/* If the EP address is known then reset the features for only that EP */
+	if (addr) {
+		cfiep = get_cfi_ep_by_addr(pcd->cfi, addr);
+		if (NULL == cfiep) {
+			CFI_INFO("%s: Error getting the EP address 0x%02x\n",
+				 __func__, addr);
+			return -DWC_E_INVALID;
+		}
+		retval = cfi_reset_concat_val(cfiep);
+	}
+	/* Otherwise (wValue == 0), reset all features of all EP's */
+	else {
+		/* Traverse all the active EP's and reset the feature(s) value(s) */
+		//list_for_each_entry(cfiep, &cfi->active_eps, lh) {
+		DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
+			cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
+			retval = cfi_reset_concat_val(cfiep);
+			if (retval < 0) {
+				CFI_INFO
+				    ("%s: Error resetting the feature Concatenation Value\n",
+				     __func__);
+				return retval;
+			}
+		}
+	}
+	return retval;
+}
+
+static int cfi_handle_reset_align_val(struct dwc_otg_pcd *pcd, uint8_t addr)
+{
+	int retval = 0;
+	cfi_ep_t *cfiep;
+	cfiobject_t *cfi = pcd->cfi;
+	dwc_list_link_t *tmp;
+
+	/* If the EP address is known then reset the features for only that EP */
+	if (addr) {
+		cfiep = get_cfi_ep_by_addr(pcd->cfi, addr);
+		if (NULL == cfiep) {
+			CFI_INFO("%s: Error getting the EP address 0x%02x\n",
+				 __func__, addr);
+			return -DWC_E_INVALID;
+		}
+		retval = cfi_reset_align_val(cfiep);
+	}
+	/* Otherwise (wValue == 0), reset all features of all EP's */
+	else {
+		/* Traverse all the active EP's and reset the feature(s) value(s) */
+		//list_for_each_entry(cfiep, &cfi->active_eps, lh) {
+		DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
+			cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
+			retval = cfi_reset_align_val(cfiep);
+			if (retval < 0) {
+				CFI_INFO
+				    ("%s: Error resetting the feature Aliignment Value\n",
+				     __func__);
+				return retval;
+			}
+		}
+	}
+	return retval;
+
+}
+
+static int cfi_preproc_reset(struct dwc_otg_pcd *pcd,
+			     struct cfi_usb_ctrlrequest *req)
+{
+	int retval = 0;
+
+	switch (req->wIndex) {
+	case 0:
+		/* Reset all features */
+		retval = cfi_handle_reset_all(pcd, req->wValue & 0xff);
+		break;
+
+	case FT_ID_DMA_BUFFER_SETUP:
+		/* Reset the SG buffer setup */
+		retval =
+		    cfi_handle_reset_dma_buff_setup(pcd, req->wValue & 0xff);
+		break;
+
+	case FT_ID_DMA_CONCAT_SETUP:
+		/* Reset the Concatenation buffer setup */
+		retval = cfi_handle_reset_concat_val(pcd, req->wValue & 0xff);
+		break;
+
+	case FT_ID_DMA_BUFF_ALIGN:
+		/* Reset the Alignment buffer setup */
+		retval = cfi_handle_reset_align_val(pcd, req->wValue & 0xff);
+		break;
+
+	case FT_ID_TX_FIFO_DEPTH:
+		retval =
+		    cfi_handle_reset_fifo_val(pcd, req->wValue & 0xff, 0, 1);
+		pcd->cfi->need_gadget_att = 0;
+		break;
+
+	case FT_ID_RX_FIFO_DEPTH:
+		retval = cfi_handle_reset_fifo_val(pcd, 0, 1, 0);
+		pcd->cfi->need_gadget_att = 0;
+		break;
+	default:
+		break;
+	}
+	return retval;
+}
+
+/**
+ * This function sets a new value for the SG buffer setup.
+ */
+static int cfi_ep_set_sg_val(uint8_t * buf, struct dwc_otg_pcd *pcd)
+{
+	uint8_t inaddr, outaddr;
+	cfi_ep_t *epin, *epout;
+	ddma_sg_buffer_setup_t *psgval;
+	uint32_t desccount, size;
+
+	CFI_INFO("%s\n", __func__);
+
+	psgval = (ddma_sg_buffer_setup_t *) buf;
+	desccount = (uint32_t) psgval->bCount;
+	size = (uint32_t) psgval->wSize;
+
+	/* Check the DMA descriptor count */
+	if ((desccount > MAX_DMA_DESCS_PER_EP) || (desccount == 0)) {
+		CFI_INFO
+		    ("%s: The count of DMA Descriptors should be between 1 and %d\n",
+		     __func__, MAX_DMA_DESCS_PER_EP);
+		return -DWC_E_INVALID;
+	}
+
+	/* Check the DMA descriptor count */
+
+	if (size == 0) {
+
+		CFI_INFO("%s: The transfer size should be at least 1 byte\n",
+			 __func__);
+
+		return -DWC_E_INVALID;
+
+	}
+
+	inaddr = psgval->bInEndpointAddress;
+	outaddr = psgval->bOutEndpointAddress;
+
+	epin = get_cfi_ep_by_addr(pcd->cfi, inaddr);
+	epout = get_cfi_ep_by_addr(pcd->cfi, outaddr);
+
+	if (NULL == epin || NULL == epout) {
+		CFI_INFO
+		    ("%s: Unable to get the endpoints inaddr=0x%02x outaddr=0x%02x\n",
+		     __func__, inaddr, outaddr);
+		return -DWC_E_INVALID;
+	}
+
+	epin->ep->dwc_ep.buff_mode = BM_SG;
+	dwc_memcpy(epin->bm_sg, psgval, sizeof(ddma_sg_buffer_setup_t));
+
+	epout->ep->dwc_ep.buff_mode = BM_SG;
+	dwc_memcpy(epout->bm_sg, psgval, sizeof(ddma_sg_buffer_setup_t));
+
+	return 0;
+}
+
+/**
+ * This function sets a new value for the buffer Alignment setup.
+ */
+static int cfi_ep_set_alignment_val(uint8_t * buf, struct dwc_otg_pcd *pcd)
+{
+	cfi_ep_t *ep;
+	uint8_t addr;
+	ddma_align_buffer_setup_t *palignval;
+
+	palignval = (ddma_align_buffer_setup_t *) buf;
+	addr = palignval->bEndpointAddress;
+
+	ep = get_cfi_ep_by_addr(pcd->cfi, addr);
+
+	if (NULL == ep) {
+		CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n",
+			 __func__, addr);
+		return -DWC_E_INVALID;
+	}
+
+	ep->ep->dwc_ep.buff_mode = BM_ALIGN;
+	dwc_memcpy(ep->bm_align, palignval, sizeof(ddma_align_buffer_setup_t));
+
+	return 0;
+}
+
+/**
+ * This function sets a new value for the Concatenation buffer setup.
+ */
+static int cfi_ep_set_concat_val(uint8_t * buf, struct dwc_otg_pcd *pcd)
+{
+	uint8_t addr;
+	cfi_ep_t *ep;
+	struct _ddma_concat_buffer_setup_hdr *pConcatValHdr;
+	uint16_t *pVals;
+	uint32_t desccount;
+	int i;
+	uint16_t mps;
+
+	pConcatValHdr = (struct _ddma_concat_buffer_setup_hdr *)buf;
+	desccount = (uint32_t) pConcatValHdr->bDescCount;
+	pVals = (uint16_t *) (buf + BS_CONCAT_VAL_HDR_LEN);
+
+	/* Check the DMA descriptor count */
+	if (desccount > MAX_DMA_DESCS_PER_EP) {
+		CFI_INFO("%s: Maximum DMA Descriptor count should be %d\n",
+			 __func__, MAX_DMA_DESCS_PER_EP);
+		return -DWC_E_INVALID;
+	}
+
+	addr = pConcatValHdr->bEndpointAddress;
+	ep = get_cfi_ep_by_addr(pcd->cfi, addr);
+	if (NULL == ep) {
+		CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n",
+			 __func__, addr);
+		return -DWC_E_INVALID;
+	}
+
+	mps = UGETW(ep->ep->desc->wMaxPacketSize);
+
+#if 0
+	for (i = 0; i < desccount; i++) {
+		CFI_INFO("%s: wTxSize[%d]=0x%04x\n", __func__, i, pVals[i]);
+	}
+	CFI_INFO("%s: epname=%s; mps=%d\n", __func__, ep->ep->ep.name, mps);
+#endif
+
+	/* Check the wTxSizes to be less than or equal to the mps */
+	for (i = 0; i < desccount; i++) {
+		if (pVals[i] > mps) {
+			CFI_INFO
+			    ("%s: ERROR - the wTxSize[%d] should be <= MPS (wTxSize=%d)\n",
+			     __func__, i, pVals[i]);
+			return -DWC_E_INVALID;
+		}
+	}
+
+	ep->ep->dwc_ep.buff_mode = BM_CONCAT;
+	dwc_memcpy(ep->bm_concat, pConcatValHdr, BS_CONCAT_VAL_HDR_LEN);
+
+	/* Free the previously allocated storage for the wTxBytes */
+	if (ep->bm_concat->wTxBytes) {
+		dwc_free(ep->bm_concat->wTxBytes);
+	}
+
+	/* Allocate a new storage for the wTxBytes field */
+	ep->bm_concat->wTxBytes =
+	    dwc_alloc(sizeof(uint16_t) * pConcatValHdr->bDescCount);
+	if (NULL == ep->bm_concat->wTxBytes) {
+		CFI_INFO("%s: Unable to allocate memory\n", __func__);
+		return -DWC_E_NO_MEMORY;
+	}
+
+	/* Copy the new values into the wTxBytes filed */
+	dwc_memcpy(ep->bm_concat->wTxBytes, buf + BS_CONCAT_VAL_HDR_LEN,
+		   sizeof(uint16_t) * pConcatValHdr->bDescCount);
+
+	return 0;
+}
+
+/**
+ * This function calculates the total of all FIFO sizes
+ * 
+ * @param core_if Programming view of DWC_otg controller
+ *
+ * @return The total of data FIFO sizes.
+ *
+ */
+static uint16_t get_dfifo_size(dwc_otg_core_if_t * core_if)
+{
+	dwc_otg_core_params_t *params = core_if->core_params;
+	uint16_t dfifo_total = 0;
+	int i;
+
+	/* The shared RxFIFO size */
+	dfifo_total =
+	    params->dev_rx_fifo_size + params->dev_nperio_tx_fifo_size;
+
+	/* Add up each TxFIFO size to the total */
+	for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
+		dfifo_total += params->dev_tx_fifo_size[i];
+	}
+
+	return dfifo_total;
+}
+
+/**
+ * This function returns Rx FIFO size
+ * 
+ * @param core_if Programming view of DWC_otg controller
+ *
+ * @return The total of data FIFO sizes.
+ *
+ */
+static int32_t get_rxfifo_size(dwc_otg_core_if_t * core_if, uint16_t wValue)
+{
+	switch (wValue >> 8) {
+	case 0:
+		return (core_if->pwron_rxfsiz <
+			32768) ? core_if->pwron_rxfsiz : 32768;
+		break;
+	case 1:
+		return core_if->core_params->dev_rx_fifo_size;
+		break;
+	default:
+		return -DWC_E_INVALID;
+		break;
+	}
+}
+
+/**
+ * This function returns Tx FIFO size for IN EP
+ * 
+ * @param core_if Programming view of DWC_otg controller
+ *
+ * @return The total of data FIFO sizes.
+ *
+ */
+static int32_t get_txfifo_size(struct dwc_otg_pcd *pcd, uint16_t wValue)
+{
+	dwc_otg_pcd_ep_t *ep;
+
+	ep = get_ep_by_addr(pcd, wValue & 0xff);
+
+	if (NULL == ep) {
+		CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n",
+			 __func__, wValue & 0xff);
+		return -DWC_E_INVALID;
+	}
+
+	if (!ep->dwc_ep.is_in) {
+		CFI_INFO
+		    ("%s: No Tx FIFO assingned to the Out endpoint addr=0x%02x\n",
+		     __func__, wValue & 0xff);
+		return -DWC_E_INVALID;
+	}
+
+	switch (wValue >> 8) {
+	case 0:
+		return (GET_CORE_IF(pcd)->
+			pwron_txfsiz[ep->dwc_ep.tx_fifo_num - 1] <
+			768) ? GET_CORE_IF(pcd)->pwron_txfsiz[ep->dwc_ep.
+							      tx_fifo_num -
+							      1] : 32768;
+		break;
+	case 1:
+		return GET_CORE_IF(pcd)->core_params->dev_tx_fifo_size[ep->
+								       dwc_ep.
+								       num - 1];
+		break;
+	default:
+		return -DWC_E_INVALID;
+		break;
+	}
+}
+
+/**
+ * This function checks if the submitted combination of 
+ * device mode FIFO sizes is possible or not.
+ * 
+ * @param core_if Programming view of DWC_otg controller
+ *
+ * @return 1 if possible, 0 otherwise.
+ *
+ */
+static uint8_t check_fifo_sizes(dwc_otg_core_if_t * core_if)
+{
+	uint16_t dfifo_actual = 0;
+	dwc_otg_core_params_t *params = core_if->core_params;
+	uint16_t start_addr = 0;
+	int i;
+
+	dfifo_actual =
+	    params->dev_rx_fifo_size + params->dev_nperio_tx_fifo_size;
+
+	for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
+		dfifo_actual += params->dev_tx_fifo_size[i];
+	}
+
+	if (dfifo_actual > core_if->total_fifo_size) {
+		return 0;
+	}
+
+	if (params->dev_rx_fifo_size > 32768 || params->dev_rx_fifo_size < 16)
+		return 0;
+
+	if (params->dev_nperio_tx_fifo_size > 32768
+	    || params->dev_nperio_tx_fifo_size < 16)
+		return 0;
+
+	for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
+
+		if (params->dev_tx_fifo_size[i] > 768
+		    || params->dev_tx_fifo_size[i] < 4)
+			return 0;
+	}
+
+	if (params->dev_rx_fifo_size > core_if->pwron_rxfsiz)
+		return 0;
+	start_addr = params->dev_rx_fifo_size;
+
+	if (params->dev_nperio_tx_fifo_size > core_if->pwron_gnptxfsiz)
+		return 0;
+	start_addr += params->dev_nperio_tx_fifo_size;
+
+	for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
+
+		if (params->dev_tx_fifo_size[i] > core_if->pwron_txfsiz[i])
+			return 0;
+		start_addr += params->dev_tx_fifo_size[i];
+	}
+
+	return 1;
+}
+
+/**
+ * This function resizes Device mode FIFOs
+ * 
+ * @param core_if Programming view of DWC_otg controller
+ *
+ * @return 1 if successful, 0 otherwise
+ *
+ */
+static uint8_t resize_fifos(dwc_otg_core_if_t * core_if)
+{
+	int i = 0;
+	dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
+	dwc_otg_core_params_t *params = core_if->core_params;
+	uint32_t rx_fifo_size;
+	fifosize_data_t nptxfifosize;
+	fifosize_data_t txfifosize[15];
+
+	uint32_t rx_fsz_bak;
+	uint32_t nptxfsz_bak;
+	uint32_t txfsz_bak[15];
+
+	uint16_t start_address;
+	uint8_t retval = 1;
+
+	if (!check_fifo_sizes(core_if)) {
+		return 0;
+	}
+
+	/* Configure data FIFO sizes */
+	if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
+		rx_fsz_bak = dwc_read_reg32(&global_regs->grxfsiz);
+		rx_fifo_size = params->dev_rx_fifo_size;
+		dwc_write_reg32(&global_regs->grxfsiz, rx_fifo_size);
+
+		/*
+		 * Tx FIFOs These FIFOs are numbered from 1 to 15.
+		 * Indexes of the FIFO size module parameters in the
+		 * dev_tx_fifo_size array and the FIFO size registers in
+		 * the dptxfsiz_dieptxf array run from 0 to 14.
+		 */
+
+		/* Non-periodic Tx FIFO */
+		nptxfsz_bak = dwc_read_reg32(&global_regs->gnptxfsiz);
+		nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
+		start_address = params->dev_rx_fifo_size;
+		nptxfifosize.b.startaddr = start_address;
+
+		dwc_write_reg32(&global_regs->gnptxfsiz, nptxfifosize.d32);
+
+		start_address += nptxfifosize.b.depth;
+
+		for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
+			txfsz_bak[i] =
+			    dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]);
+
+			txfifosize[i].b.depth = params->dev_tx_fifo_size[i];
+			txfifosize[i].b.startaddr = start_address;
+			dwc_write_reg32(&global_regs->dptxfsiz_dieptxf[i],
+					txfifosize[i].d32);
+
+			start_address += txfifosize[i].b.depth;
+		}
+
+		/** Check if register values are set correctly */
+		if (rx_fifo_size != dwc_read_reg32(&global_regs->grxfsiz)) {
+			retval = 0;
+		}
+
+		if (nptxfifosize.d32 != dwc_read_reg32(&global_regs->gnptxfsiz)) {
+			retval = 0;
+		}
+
+		for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
+			if (txfifosize[i].d32 !=
+			    dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i])) {
+				retval = 0;
+			}
+		}
+
+		/** If register values are not set correctly, reset old values */
+		if (retval == 0) {
+			dwc_write_reg32(&global_regs->grxfsiz, rx_fsz_bak);
+
+			/* Non-periodic Tx FIFO */
+			dwc_write_reg32(&global_regs->gnptxfsiz, nptxfsz_bak);
+
+			for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
+				dwc_write_reg32(&global_regs->
+						dptxfsiz_dieptxf[i],
+						txfsz_bak[i]);
+			}
+		}
+	} else {
+		return 0;
+	}
+
+	/* Flush the FIFOs */
+	dwc_otg_flush_tx_fifo(core_if, 0x10);	/* all Tx FIFOs */
+	dwc_otg_flush_rx_fifo(core_if);
+
+	return retval;
+}
+
+/**
+ * This function sets a new value for the buffer Alignment setup.
+ */
+static int cfi_ep_set_tx_fifo_val(uint8_t * buf, dwc_otg_pcd_t * pcd)
+{
+	int retval;
+	uint32_t fsiz;
+	uint16_t size;
+	uint16_t ep_addr;
+	dwc_otg_pcd_ep_t *ep;
+	dwc_otg_core_params_t *params = GET_CORE_IF(pcd)->core_params;
+	tx_fifo_size_setup_t *ptxfifoval;
+
+	ptxfifoval = (tx_fifo_size_setup_t *) buf;
+	ep_addr = ptxfifoval->bEndpointAddress;
+	size = ptxfifoval->wDepth;
+
+	ep = get_ep_by_addr(pcd, ep_addr);
+
+	CFI_INFO
+	    ("%s: Set Tx FIFO size: endpoint addr=0x%02x, depth=%d, FIFO Num=%d\n",
+	     __func__, ep_addr, size, ep->dwc_ep.tx_fifo_num);
+
+	if (NULL == ep) {
+		CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n",
+			 __func__, ep_addr);
+		return -DWC_E_INVALID;
+	}
+
+	fsiz = params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1];
+	params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1] = size;
+
+	if (resize_fifos(GET_CORE_IF(pcd))) {
+		retval = 0;
+	} else {
+		CFI_INFO
+		    ("%s: Error setting the feature Tx FIFO Size for EP%d\n",
+		     __func__, ep_addr);
+		params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1] = fsiz;
+		retval = -DWC_E_INVALID;
+	}
+
+	return retval;
+}
+
+/**
+ * This function sets a new value for the buffer Alignment setup.
+ */
+static int cfi_set_rx_fifo_val(uint8_t * buf, dwc_otg_pcd_t * pcd)
+{
+	int retval;
+	uint32_t fsiz;
+	uint16_t size;
+	dwc_otg_core_params_t *params = GET_CORE_IF(pcd)->core_params;
+	rx_fifo_size_setup_t *prxfifoval;
+
+	prxfifoval = (rx_fifo_size_setup_t *) buf;
+	size = prxfifoval->wDepth;
+
+	fsiz = params->dev_rx_fifo_size;
+	params->dev_rx_fifo_size = size;
+
+	if (resize_fifos(GET_CORE_IF(pcd))) {
+		retval = 0;
+	} else {
+		CFI_INFO("%s: Error setting the feature Rx FIFO Size\n",
+			 __func__);
+		params->dev_rx_fifo_size = fsiz;
+		retval = -DWC_E_INVALID;
+	}
+
+	return retval;
+}
+
+/**
+ * This function reads the SG of an EP's buffer setup into the buffer buf
+ */
+static int cfi_ep_get_sg_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
+			     struct cfi_usb_ctrlrequest *req)
+{
+	int retval = -DWC_E_INVALID;
+	uint8_t addr;
+	cfi_ep_t *ep;
+
+	/* The Low Byte of the wValue contains a non-zero address of the endpoint */
+	addr = req->wValue & 0xFF;
+	if (addr == 0)		/* The address should be non-zero */
+		return retval;
+
+	ep = get_cfi_ep_by_addr(pcd->cfi, addr);
+	if (NULL == ep) {
+		CFI_INFO("%s: Unable to get the endpoint address(0x%02x)\n",
+			 __func__, addr);
+		return retval;
+	}
+
+	dwc_memcpy(buf, ep->bm_sg, BS_SG_VAL_DESC_LEN);
+	retval = BS_SG_VAL_DESC_LEN;
+	return retval;
+}
+
+/**
+ * This function reads the Concatenation value of an EP's buffer mode into 
+ * the buffer buf
+ */
+static int cfi_ep_get_concat_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
+				 struct cfi_usb_ctrlrequest *req)
+{
+	int retval = -DWC_E_INVALID;
+	uint8_t addr;
+	cfi_ep_t *ep;
+	uint8_t desc_count;
+
+	/* The Low Byte of the wValue contains a non-zero address of the endpoint */
+	addr = req->wValue & 0xFF;
+	if (addr == 0)		/* The address should be non-zero */
+		return retval;
+
+	ep = get_cfi_ep_by_addr(pcd->cfi, addr);
+	if (NULL == ep) {
+		CFI_INFO("%s: Unable to get the endpoint address(0x%02x)\n",
+			 __func__, addr);
+		return retval;
+	}
+
+	/* Copy the header to the buffer */
+	dwc_memcpy(buf, ep->bm_concat, BS_CONCAT_VAL_HDR_LEN);
+	/* Advance the buffer pointer by the header size */
+	buf += BS_CONCAT_VAL_HDR_LEN;
+
+	desc_count = ep->bm_concat->hdr.bDescCount;
+	/* Copy alll the wTxBytes to the buffer */
+	dwc_memcpy(buf, ep->bm_concat->wTxBytes, sizeof(uid16_t) * desc_count);
+
+	retval = BS_CONCAT_VAL_HDR_LEN + sizeof(uid16_t) * desc_count;
+	return retval;
+}
+
+/**
+ * This function reads the buffer Alignment value of an EP's buffer mode into 
+ * the buffer buf
+ *
+ * @return The total number of bytes copied to the buffer or negative error code.
+ */
+static int cfi_ep_get_align_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
+				struct cfi_usb_ctrlrequest *req)
+{
+	int retval = -DWC_E_INVALID;
+	uint8_t addr;
+	cfi_ep_t *ep;
+
+	/* The Low Byte of the wValue contains a non-zero address of the endpoint */
+	addr = req->wValue & 0xFF;
+	if (addr == 0)		/* The address should be non-zero */
+		return retval;
+
+	ep = get_cfi_ep_by_addr(pcd->cfi, addr);
+	if (NULL == ep) {
+		CFI_INFO("%s: Unable to get the endpoint address(0x%02x)\n",
+			 __func__, addr);
+		return retval;
+	}
+
+	dwc_memcpy(buf, ep->bm_align, BS_ALIGN_VAL_HDR_LEN);
+	retval = BS_ALIGN_VAL_HDR_LEN;
+
+	return retval;
+}
+
+/**
+ * This function sets a new value for the specified feature
+ * 
+ * @param	pcd	A pointer to the PCD object
+ * 
+ * @return 0 if successful, negative error code otherwise to stall the DCE.
+ */
+static int cfi_set_feature_value(struct dwc_otg_pcd *pcd)
+{
+	int retval = -DWC_E_NOT_SUPPORTED;
+	uint16_t wIndex, wValue;
+	uint8_t bRequest;
+	struct dwc_otg_core_if *coreif;
+	cfiobject_t *cfi = pcd->cfi;
+	struct cfi_usb_ctrlrequest *ctrl_req;
+	uint8_t *buf;
+	ctrl_req = &cfi->ctrl_req;
+
+	buf = pcd->cfi->ctrl_req.data;
+
+	coreif = GET_CORE_IF(pcd);
+	bRequest = ctrl_req->bRequest;
+	wIndex = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wIndex);
+	wValue = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wValue);
+
+	/* See which feature is to be modified */
+	switch (wIndex) {
+	case FT_ID_DMA_BUFFER_SETUP:
+		/* Modify the feature */
+		if ((retval = cfi_ep_set_sg_val(buf, pcd)) < 0)
+			return retval;
+
+		/* And send this request to the gadget */
+		cfi->need_gadget_att = 1;
+		break;
+
+	case FT_ID_DMA_BUFF_ALIGN:
+		if ((retval = cfi_ep_set_alignment_val(buf, pcd)) < 0)
+			return retval;
+		cfi->need_gadget_att = 1;
+		break;
+
+	case FT_ID_DMA_CONCAT_SETUP:
+		/* Modify the feature */
+		if ((retval = cfi_ep_set_concat_val(buf, pcd)) < 0)
+			return retval;
+		cfi->need_gadget_att = 1;
+		break;
+
+	case FT_ID_DMA_CIRCULAR:
+		CFI_INFO("FT_ID_DMA_CIRCULAR\n");
+		break;
+
+	case FT_ID_THRESHOLD_SETUP:
+		CFI_INFO("FT_ID_THRESHOLD_SETUP\n");
+		break;
+
+	case FT_ID_DFIFO_DEPTH:
+		CFI_INFO("FT_ID_DFIFO_DEPTH\n");
+		break;
+
+	case FT_ID_TX_FIFO_DEPTH:
+		CFI_INFO("FT_ID_TX_FIFO_DEPTH\n");
+		if ((retval = cfi_ep_set_tx_fifo_val(buf, pcd)) < 0)
+			return retval;
+		cfi->need_gadget_att = 0;
+		break;
+
+	case FT_ID_RX_FIFO_DEPTH:
+		CFI_INFO("FT_ID_RX_FIFO_DEPTH\n");
+		if ((retval = cfi_set_rx_fifo_val(buf, pcd)) < 0)
+			return retval;
+		cfi->need_gadget_att = 0;
+		break;
+	}
+
+	return retval;
+}
+
+#endif				//DWC_UTE_CFI
diff --git a/drivers/usb/host/dwc_otg/dwc_otg_cfi.h b/drivers/usb/host/dwc_otg/dwc_otg_cfi.h
new file mode 100644
index 000000000000..0215224b5124
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/dwc_otg_cfi.h
@@ -0,0 +1,319 @@
+/* ==========================================================================
+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+ * otherwise expressly agreed to in writing between Synopsys and you.
+ * 
+ * The Software IS NOT an item of Licensed Software or Licensed Product under
+ * any End User Software License Agreement or Agreement for Licensed Product
+ * with Synopsys or any supplement thereto. You are permitted to use and
+ * redistribute this Software in source and binary forms, with or without
+ * modification, provided that redistributions of source code must retain this
+ * notice. You may not view, use, disclose, copy or distribute this file or
+ * any information contained herein except pursuant to this license grant from
+ * Synopsys. If you do not agree with this notice, including the disclaimer
+ * below, then you are not authorized to use the Software.
+ * 
+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ * ========================================================================== */
+
+#if !defined(__DWC_OTG_CFI_H__)
+#define __DWC_OTG_CFI_H__
+
+#include "dwc_otg_pcd.h"
+#include "dwc_cfi_common.h"
+
+/**
+ * @file 
+ *
+ * This file contains the CFI related OTG PCD specific common constants, interfaces
+ * (functions and macros) and data structures.
+ *
+ */
+
+struct dwc_otg_pcd;
+struct dwc_otg_pcd_ep;
+
+/** OTG CFI Features (properties) ID constants */
+/** This is a request for all Core Features */
+#define FT_ID_DMA_MODE					0x0001
+#define FT_ID_DMA_BUFFER_SETUP			0x0002
+#define FT_ID_DMA_BUFF_ALIGN			0x0003
+#define FT_ID_DMA_CONCAT_SETUP			0x0004
+#define FT_ID_DMA_CIRCULAR				0x0005
+#define FT_ID_THRESHOLD_SETUP			0x0006
+#define FT_ID_DFIFO_DEPTH				0x0007
+#define FT_ID_TX_FIFO_DEPTH				0x0008
+#define FT_ID_RX_FIFO_DEPTH				0x0009
+
+/**********************************************************/
+#define CFI_INFO_DEF
+
+#ifdef CFI_INFO_DEF
+#define CFI_INFO(fmt...)	DWC_PRINTF("CFI: " fmt);
+#else
+#define CFI_INFO(fmt...)
+#endif
+
+#define min(x,y) ({ \
+	x < y ? x : y; })
+
+#define max(x,y) ({ \
+	x > y ? x : y; })
+
+/** 
+ * Descriptor DMA SG Buffer setup structure (SG buffer). This structure is
+ * also used for setting up a buffer for Circular DDMA.
+ */
+struct _ddma_sg_buffer_setup {
+#define BS_SG_VAL_DESC_LEN	6
+	/* The OUT EP address */
+	uint8_t bOutEndpointAddress;
+	/* The IN EP address */
+	uint8_t bInEndpointAddress;
+	/* Number of bytes to put between transfer segments (must be DWORD boundaries) */
+	uint8_t bOffset;
+	/* The number of transfer segments (a DMA descriptors per each segment) */
+	uint8_t bCount;
+	/* Size (in byte) of each transfer segment */
+	uint16_t wSize;
+} __attribute__ ((packed));
+typedef struct _ddma_sg_buffer_setup ddma_sg_buffer_setup_t;
+
+/** Descriptor DMA Concatenation Buffer setup structure */
+struct _ddma_concat_buffer_setup_hdr {
+#define BS_CONCAT_VAL_HDR_LEN	4
+	/* The endpoint for which the buffer is to be set up */
+	uint8_t bEndpointAddress;
+	/* The count of descriptors to be used */
+	uint8_t bDescCount;
+	/* The total size of the transfer */
+	uint16_t wSize;
+} __attribute__ ((packed));
+typedef struct _ddma_concat_buffer_setup_hdr ddma_concat_buffer_setup_hdr_t;
+
+/** Descriptor DMA Concatenation Buffer setup structure */
+struct _ddma_concat_buffer_setup {
+	/* The SG header */
+	ddma_concat_buffer_setup_hdr_t hdr;
+
+	/* The XFER sizes pointer (allocated dynamically) */
+	uint16_t *wTxBytes;
+} __attribute__ ((packed));
+typedef struct _ddma_concat_buffer_setup ddma_concat_buffer_setup_t;
+
+/** Descriptor DMA Alignment Buffer setup structure */
+struct _ddma_align_buffer_setup {
+#define BS_ALIGN_VAL_HDR_LEN	2
+	uint8_t bEndpointAddress;
+	uint8_t bAlign;
+} __attribute__ ((packed));
+typedef struct _ddma_align_buffer_setup ddma_align_buffer_setup_t;
+
+/** Transmit FIFO Size setup structure */
+struct _tx_fifo_size_setup {
+	uint8_t bEndpointAddress;
+	uint16_t wDepth;
+} __attribute__ ((packed));
+typedef struct _tx_fifo_size_setup tx_fifo_size_setup_t;
+
+/** Transmit FIFO Size setup structure */
+struct _rx_fifo_size_setup {
+	uint16_t wDepth;
+} __attribute__ ((packed));
+typedef struct _rx_fifo_size_setup rx_fifo_size_setup_t;
+
+/**
+ * struct cfi_usb_ctrlrequest - the CFI implementation of the struct usb_ctrlrequest
+ * This structure encapsulates the standard usb_ctrlrequest and adds a pointer 
+ * to the data returned in the data stage of a 3-stage Control Write requests.
+ */
+struct cfi_usb_ctrlrequest {
+	uint8_t bRequestType;
+	uint8_t bRequest;
+	uint16_t wValue;
+	uint16_t wIndex;
+	uint16_t wLength;
+	uint8_t *data;
+} UPACKED;
+
+/*---------------------------------------------------------------------------*/
+
+/**
+ * The CFI wrapper of the enabled and activated dwc_otg_pcd_ep structures.
+ * This structure is used to store the buffer setup data for any 
+ * enabled endpoint in the PCD.
+ */
+struct cfi_ep {
+	/* Entry for the list container */
+	dwc_list_link_t lh;
+	/* Pointer to the active PCD endpoint structure */
+	struct dwc_otg_pcd_ep *ep;
+	/* The last descriptor in the chain of DMA descriptors of the endpoint */
+	struct dwc_otg_dma_desc *dma_desc_last;
+	/* The SG feature value */
+	ddma_sg_buffer_setup_t *bm_sg;
+	/* The Circular feature value */
+	ddma_sg_buffer_setup_t *bm_circ;
+	/* The Concatenation feature value */
+	ddma_concat_buffer_setup_t *bm_concat;
+	/* The Alignment feature value */
+	ddma_align_buffer_setup_t *bm_align;
+	/* XFER length */
+	uint32_t xfer_len;
+	/* 
+	 * Count of DMA descriptors currently used.
+	 * The total should not exceed the MAX_DMA_DESCS_PER_EP value
+	 * defined in the dwc_otg_cil.h
+	 */
+	uint32_t desc_count;
+};
+typedef struct cfi_ep cfi_ep_t;
+
+typedef struct cfi_dma_buff {
+#define CFI_IN_BUF_LEN	1024
+#define CFI_OUT_BUF_LEN	1024
+	dma_addr_t addr;
+	uint8_t *buf;
+} cfi_dma_buff_t;
+
+struct cfiobject;
+
+/**
+ * This is the interface for the CFI operations.
+ * 
+ * @param	ep_enable			Called when any endpoint is enabled and activated.
+ * @param	release				Called when the CFI object is released and it needs to correctly
+ *								deallocate the dynamic memory
+ * @param	ctrl_write_complete	Called when the data stage of the request is complete
+ */
+typedef struct cfi_ops {
+	int (*ep_enable) (struct cfiobject * cfi, struct dwc_otg_pcd * pcd,
+			  struct dwc_otg_pcd_ep * ep);
+	void *(*ep_alloc_buf) (struct cfiobject * cfi, struct dwc_otg_pcd * pcd,
+			       struct dwc_otg_pcd_ep * ep, dma_addr_t * dma,
+			       unsigned size, gfp_t flags);
+	void (*release) (struct cfiobject * cfi);
+	int (*ctrl_write_complete) (struct cfiobject * cfi,
+				    struct dwc_otg_pcd * pcd);
+	void (*build_descriptors) (struct cfiobject * cfi,
+				   struct dwc_otg_pcd * pcd,
+				   struct dwc_otg_pcd_ep * ep,
+				   dwc_otg_pcd_request_t * req);
+} cfi_ops_t;
+
+struct cfiobject {
+	cfi_ops_t ops;
+	struct dwc_otg_pcd *pcd;
+	struct usb_gadget *gadget;
+
+	/* Buffers used to send/receive CFI-related request data */
+	cfi_dma_buff_t buf_in;
+	cfi_dma_buff_t buf_out;
+
+	/* CFI specific Control request wrapper */
+	struct cfi_usb_ctrlrequest ctrl_req;
+
+	/* The list of active EP's in the PCD of type cfi_ep_t */
+	dwc_list_link_t active_eps;
+
+	/* This flag shall control the propagation of a specific request
+	 * to the gadget's processing routines.
+	 * 0 - no gadget handling
+	 * 1 - the gadget needs to know about this request (w/o completing a status 
+	 * phase - just return a 0 to the _setup callback)
+	 */
+	uint8_t need_gadget_att;
+
+	/* Flag indicating whether the status IN phase needs to be 
+	 * completed by the PCD
+	 */
+	uint8_t need_status_in_complete;
+};
+typedef struct cfiobject cfiobject_t;
+
+#define DUMP_MSG
+
+#if defined(DUMP_MSG)
+static inline void dump_msg(const u8 * buf, unsigned int length)
+{
+	unsigned int start, num, i;
+	char line[52], *p;
+
+	if (length >= 512)
+		return;
+
+	start = 0;
+	while (length > 0) {
+		num = min(length, 16u);
+		p = line;
+		for (i = 0; i < num; ++i) {
+			if (i == 8)
+				*p++ = ' ';
+			DWC_SPRINTF(p, " %02x", buf[i]);
+			p += 3;
+		}
+		*p = 0;
+		DWC_DEBUG("%6x: %s\n", start, line);
+		buf += num;
+		start += num;
+		length -= num;
+	}
+}
+#else
+static inline void dump_msg(const u8 * buf, unsigned int length)
+{
+}
+#endif
+
+/**
+ * This function returns a pointer to cfi_ep_t object with the addr address.
+ */
+static inline struct cfi_ep *get_cfi_ep_by_addr(struct cfiobject *cfi,
+						uint8_t addr)
+{
+	struct cfi_ep *pcfiep;
+	dwc_list_link_t *tmp;
+
+	DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
+		pcfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
+
+		if (pcfiep->ep->desc->bEndpointAddress == addr) {
+			return pcfiep;
+		}
+	}
+
+	return NULL;
+}
+
+/**
+ * This function returns a pointer to cfi_ep_t object that matches
+ * the dwc_otg_pcd_ep object.
+ */
+static inline struct cfi_ep *get_cfi_ep_by_pcd_ep(struct cfiobject *cfi,
+						  struct dwc_otg_pcd_ep *ep)
+{
+	struct cfi_ep *pcfiep = NULL;
+	dwc_list_link_t *tmp;
+
+	DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
+		pcfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
+		if (pcfiep->ep == ep) {
+			return pcfiep;
+		}
+	}
+	return NULL;
+}
+
+int cfi_setup(struct dwc_otg_pcd *pcd, struct cfi_usb_ctrlrequest *ctrl);
+
+#endif				/* (__DWC_OTG_CFI_H__) */
diff --git a/drivers/usb/host/dwc_otg/dwc_otg_cil.c b/drivers/usb/host/dwc_otg/dwc_otg_cil.c
new file mode 100644
index 000000000000..ccfe6b5292bf
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/dwc_otg_cil.c
@@ -0,0 +1,5410 @@
+/* ==========================================================================
+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.c $
+ * $Revision: #159 $
+ * $Date: 2009/04/21 $
+ * $Change: 1237465 $
+ *
+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+ * otherwise expressly agreed to in writing between Synopsys and you.
+ * 
+ * The Software IS NOT an item of Licensed Software or Licensed Product under
+ * any End User Software License Agreement or Agreement for Licensed Product
+ * with Synopsys or any supplement thereto. You are permitted to use and
+ * redistribute this Software in source and binary forms, with or without
+ * modification, provided that redistributions of source code must retain this
+ * notice. You may not view, use, disclose, copy or distribute this file or
+ * any information contained herein except pursuant to this license grant from
+ * Synopsys. If you do not agree with this notice, including the disclaimer
+ * below, then you are not authorized to use the Software.
+ * 
+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ * ========================================================================== */
+
+/** @file 
+ *
+ * The Core Interface Layer provides basic services for accessing and
+ * managing the DWC_otg hardware. These services are used by both the
+ * Host Controller Driver and the Peripheral Controller Driver.
+ *
+ * The CIL manages the memory map for the core so that the HCD and PCD
+ * don't have to do this separately. It also handles basic tasks like
+ * reading/writing the registers and data FIFOs in the controller.
+ * Some of the data access functions provide encapsulation of several
+ * operations required to perform a task, such as writing multiple
+ * registers to start a transfer. Finally, the CIL performs basic
+ * services that are not specific to either the host or device modes
+ * of operation. These services include management of the OTG Host
+ * Negotiation Protocol (HNP) and Session Request Protocol (SRP). A
+ * Diagnostic API is also provided to allow testing of the controller
+ * hardware.
+ *
+ * The Core Interface Layer has the following requirements:
+ * - Provides basic controller operations.
+ * - Minimal use of OS services.  
+ * - The OS services used will be abstracted by using inline functions
+ *	 or macros.
+ *
+ */
+
+#include "dwc_os.h"
+#include "dwc_otg_regs.h"
+#include "dwc_otg_cil.h"
+
+static int dwc_otg_setup_params(dwc_otg_core_if_t * core_if);
+
+/** 
+ * This function is called to initialize the DWC_otg CSR data
+ * structures.	The register addresses in the device and host
+ * structures are initialized from the base address supplied by the
+ * caller.	The calling function must make the OS calls to get the
+ * base address of the DWC_otg controller registers.  The core_params
+ * argument holds the parameters that specify how the core should be
+ * configured.
+ *
+ * @param reg_base_addr Base address of DWC_otg core registers
+ *
+ */
+dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t * reg_base_addr)
+{
+	dwc_otg_core_if_t *core_if = 0;
+	dwc_otg_dev_if_t *dev_if = 0;
+	dwc_otg_host_if_t *host_if = 0;
+	uint8_t *reg_base = (uint8_t *) reg_base_addr;
+	int i = 0;
+
+	DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, reg_base_addr);
+
+	core_if = dwc_alloc(sizeof(dwc_otg_core_if_t));
+
+	if (core_if == 0) {
+		DWC_DEBUGPL(DBG_CIL,
+			    "Allocation of dwc_otg_core_if_t failed\n");
+		return 0;
+	}
+	core_if->core_global_regs = (dwc_otg_core_global_regs_t *) reg_base;
+
+	/*
+	 * Allocate the Device Mode structures.
+	 */
+	dev_if = dwc_alloc(sizeof(dwc_otg_dev_if_t));
+
+	if (dev_if == 0) {
+		DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_dev_if_t failed\n");
+		dwc_free(core_if);
+		return 0;
+	}
+
+	dev_if->dev_global_regs =
+	    (dwc_otg_device_global_regs_t *) (reg_base +
+					      DWC_DEV_GLOBAL_REG_OFFSET);
+
+	for (i = 0; i < MAX_EPS_CHANNELS; i++) {
+		dev_if->in_ep_regs[i] = (dwc_otg_dev_in_ep_regs_t *)
+		    (reg_base + DWC_DEV_IN_EP_REG_OFFSET +
+		     (i * DWC_EP_REG_OFFSET));
+
+		dev_if->out_ep_regs[i] = (dwc_otg_dev_out_ep_regs_t *)
+		    (reg_base + DWC_DEV_OUT_EP_REG_OFFSET +
+		     (i * DWC_EP_REG_OFFSET));
+		DWC_DEBUGPL(DBG_CILV, "in_ep_regs[%d]->diepctl=%p\n",
+			    i, &dev_if->in_ep_regs[i]->diepctl);
+		DWC_DEBUGPL(DBG_CILV, "out_ep_regs[%d]->doepctl=%p\n",
+			    i, &dev_if->out_ep_regs[i]->doepctl);
+	}
+
+	dev_if->speed = 0;	// unknown
+
+	core_if->dev_if = dev_if;
+
+	/*
+	 * Allocate the Host Mode structures.
+	 */
+	host_if = dwc_alloc(sizeof(dwc_otg_host_if_t));
+
+	if (host_if == 0) {
+		DWC_DEBUGPL(DBG_CIL,
+			    "Allocation of dwc_otg_host_if_t failed\n");
+		dwc_free(dev_if);
+		dwc_free(core_if);
+		return 0;
+	}
+
+	host_if->host_global_regs = (dwc_otg_host_global_regs_t *)
+	    (reg_base + DWC_OTG_HOST_GLOBAL_REG_OFFSET);
+
+	host_if->hprt0 =
+	    (uint32_t *) (reg_base + DWC_OTG_HOST_PORT_REGS_OFFSET);
+
+	for (i = 0; i < MAX_EPS_CHANNELS; i++) {
+		host_if->hc_regs[i] = (dwc_otg_hc_regs_t *)
+		    (reg_base + DWC_OTG_HOST_CHAN_REGS_OFFSET +
+		     (i * DWC_OTG_CHAN_REGS_OFFSET));
+		DWC_DEBUGPL(DBG_CILV, "hc_reg[%d]->hcchar=%p\n",
+			    i, &host_if->hc_regs[i]->hcchar);
+	}
+
+	host_if->num_host_channels = MAX_EPS_CHANNELS;
+	core_if->host_if = host_if;
+
+	for (i = 0; i < MAX_EPS_CHANNELS; i++) {
+		core_if->data_fifo[i] =
+		    (uint32_t *) (reg_base + DWC_OTG_DATA_FIFO_OFFSET +
+				  (i * DWC_OTG_DATA_FIFO_SIZE));
+		DWC_DEBUGPL(DBG_CILV, "data_fifo[%d]=0x%08x\n",
+			    i, (unsigned)core_if->data_fifo[i]);
+	}
+
+	core_if->pcgcctl = (uint32_t *) (reg_base + DWC_OTG_PCGCCTL_OFFSET);
+
+	/* Initiate lx_state to L3 disconnected state */
+	core_if->lx_state = DWC_OTG_L3;
+	/*
+	 * Store the contents of the hardware configuration registers here for
+	 * easy access later.
+	 */
+	core_if->hwcfg1.d32 =
+	    dwc_read_reg32(&core_if->core_global_regs->ghwcfg1);
+	core_if->hwcfg2.d32 =
+	    dwc_read_reg32(&core_if->core_global_regs->ghwcfg2);
+	core_if->hwcfg3.d32 =
+	    dwc_read_reg32(&core_if->core_global_regs->ghwcfg3);
+	core_if->hwcfg4.d32 =
+	    dwc_read_reg32(&core_if->core_global_regs->ghwcfg4);
+
+	DWC_DEBUGPL(DBG_CILV, "hwcfg1=%08x\n", core_if->hwcfg1.d32);
+	DWC_DEBUGPL(DBG_CILV, "hwcfg2=%08x\n", core_if->hwcfg2.d32);
+	DWC_DEBUGPL(DBG_CILV, "hwcfg3=%08x\n", core_if->hwcfg3.d32);
+	DWC_DEBUGPL(DBG_CILV, "hwcfg4=%08x\n", core_if->hwcfg4.d32);
+
+	core_if->hcfg.d32 =
+	    dwc_read_reg32(&core_if->host_if->host_global_regs->hcfg);
+	core_if->dcfg.d32 =
+	    dwc_read_reg32(&core_if->dev_if->dev_global_regs->dcfg);
+
+	DWC_DEBUGPL(DBG_CILV, "hcfg=%08x\n", core_if->hcfg.d32);
+	DWC_DEBUGPL(DBG_CILV, "dcfg=%08x\n", core_if->dcfg.d32);
+
+	DWC_DEBUGPL(DBG_CILV, "op_mode=%0x\n", core_if->hwcfg2.b.op_mode);
+	DWC_DEBUGPL(DBG_CILV, "arch=%0x\n", core_if->hwcfg2.b.architecture);
+	DWC_DEBUGPL(DBG_CILV, "num_dev_ep=%d\n", core_if->hwcfg2.b.num_dev_ep);
+	DWC_DEBUGPL(DBG_CILV, "num_host_chan=%d\n",
+		    core_if->hwcfg2.b.num_host_chan);
+	DWC_DEBUGPL(DBG_CILV, "nonperio_tx_q_depth=0x%0x\n",
+		    core_if->hwcfg2.b.nonperio_tx_q_depth);
+	DWC_DEBUGPL(DBG_CILV, "host_perio_tx_q_depth=0x%0x\n",
+		    core_if->hwcfg2.b.host_perio_tx_q_depth);
+	DWC_DEBUGPL(DBG_CILV, "dev_token_q_depth=0x%0x\n",
+		    core_if->hwcfg2.b.dev_token_q_depth);
+
+	DWC_DEBUGPL(DBG_CILV, "Total FIFO SZ=%d\n",
+		    core_if->hwcfg3.b.dfifo_depth);
+	DWC_DEBUGPL(DBG_CILV, "xfer_size_cntr_width=%0x\n",
+		    core_if->hwcfg3.b.xfer_size_cntr_width);
+
+	/*
+	 * Set the SRP sucess bit for FS-I2c
+	 */
+	core_if->srp_success = 0;
+	core_if->srp_timer_started = 0;
+
+	/*
+	 * Create new workqueue and init works
+	 */
+	core_if->wq_otg = DWC_WORKQ_ALLOC("dwc_otg");
+	if (core_if->wq_otg == 0) {
+		DWC_WARN("DWC_WORKQ_ALLOC failed\n");
+		dwc_free(host_if);
+		dwc_free(dev_if);
+		dwc_free(core_if);
+		return 0;
+	}
+
+	core_if->snpsid = dwc_read_reg32(&core_if->core_global_regs->gsnpsid);
+
+	DWC_PRINTF("Core Release: %x.%x%x%x\n",
+		   (core_if->snpsid >> 12 & 0xF),
+		   (core_if->snpsid >> 8 & 0xF),
+		   (core_if->snpsid >> 4 & 0xF), (core_if->snpsid & 0xF));
+
+	core_if->wkp_timer = DWC_TIMER_ALLOC("Wake Up Timer",
+					     w_wakeup_detected, core_if);
+	if (core_if->wkp_timer == 0) {
+		DWC_WARN("DWC_TIMER_ALLOC failed\n");
+		dwc_free(host_if);
+		dwc_free(dev_if);
+		DWC_WORKQ_FREE(core_if->wq_otg);
+		dwc_free(core_if);
+		return 0;
+	}
+
+	if (dwc_otg_setup_params(core_if)) {
+		DWC_WARN("Error while setting core params\n");
+	}
+
+	return core_if;
+}
+
+/**
+ * This function frees the structures allocated by dwc_otg_cil_init().
+ * 
+ * @param core_if The core interface pointer returned from
+ * 		  dwc_otg_cil_init().
+ *
+ */
+void dwc_otg_cil_remove(dwc_otg_core_if_t * core_if)
+{
+	DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, core_if);
+
+	/* Disable all interrupts */
+	dwc_modify_reg32(&core_if->core_global_regs->gahbcfg, 1, 0);
+	dwc_write_reg32(&core_if->core_global_regs->gintmsk, 0);
+
+	if (core_if->wq_otg) {
+		DWC_WORKQ_WAIT_WORK_DONE(core_if->wq_otg, 500);
+		DWC_WORKQ_FREE(core_if->wq_otg);
+	}
+	if (core_if->dev_if) {
+		dwc_free(core_if->dev_if);
+	}
+	if (core_if->host_if) {
+		dwc_free(core_if->host_if);
+	}
+	dwc_free(core_if);
+	DWC_TIMER_FREE(core_if->wkp_timer);
+	DWC_FREE(core_if->core_params);
+}
+
+/**
+ * This function enables the controller's Global Interrupt in the AHB Config
+ * register.
+ *
+ * @param core_if Programming view of DWC_otg controller.
+ */
+void dwc_otg_enable_global_interrupts(dwc_otg_core_if_t * core_if)
+{
+	gahbcfg_data_t ahbcfg = {.d32 = 0 };
+	ahbcfg.b.glblintrmsk = 1;	/* Enable interrupts */
+	dwc_modify_reg32(&core_if->core_global_regs->gahbcfg, 0, ahbcfg.d32);
+}
+
+/**
+ * This function disables the controller's Global Interrupt in the AHB Config
+ * register.
+ *
+ * @param core_if Programming view of DWC_otg controller.
+ */
+void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t * core_if)
+{
+	gahbcfg_data_t ahbcfg = {.d32 = 0 };
+	ahbcfg.b.glblintrmsk = 1;	/* Enable interrupts */
+	DWC_PRINTF("%x -> %x\n", (unsigned int)&core_if->core_global_regs->gahbcfg, ahbcfg.d32);
+	dwc_modify_reg32(&core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0);
+}
+
+/**
+ * This function initializes the commmon interrupts, used in both
+ * device and host modes.
+ *
+ * @param core_if Programming view of the DWC_otg controller
+ *
+ */
+static void dwc_otg_enable_common_interrupts(dwc_otg_core_if_t * core_if)
+{
+	dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
+	gintmsk_data_t intr_mask = {.d32 = 0 };
+
+	/* Clear any pending OTG Interrupts */
+	dwc_write_reg32(&global_regs->gotgint, 0xFFFFFFFF);
+
+	/* Clear any pending interrupts */
+	dwc_write_reg32(&global_regs->gintsts, 0xFFFFFFFF);
+
+	/* 
+	 * Enable the interrupts in the GINTMSK. 
+	 */
+	intr_mask.b.modemismatch = 1;
+	intr_mask.b.otgintr = 1;
+
+	if (!core_if->dma_enable) {
+		intr_mask.b.rxstsqlvl = 1;
+	}
+
+	intr_mask.b.conidstschng = 1;
+	intr_mask.b.wkupintr = 1;
+	intr_mask.b.disconnect = 1;
+	intr_mask.b.usbsuspend = 1;
+	intr_mask.b.sessreqintr = 1;
+#ifdef CONFIG_USB_DWC_OTG_LPM
+	if (core_if->core_params->lpm_enable) {
+		intr_mask.b.lpmtranrcvd = 1;
+	}
+#endif
+	dwc_write_reg32(&global_regs->gintmsk, intr_mask.d32);
+}
+
+/**
+ * Initializes the FSLSPClkSel field of the HCFG register depending on the PHY
+ * type.
+ */
+static void init_fslspclksel(dwc_otg_core_if_t * core_if)
+{
+	uint32_t val;
+	hcfg_data_t hcfg;
+
+	if (((core_if->hwcfg2.b.hs_phy_type == 2) &&
+	     (core_if->hwcfg2.b.fs_phy_type == 1) &&
+	     (core_if->core_params->ulpi_fs_ls)) ||
+	    (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
+		/* Full speed PHY */
+		val = DWC_HCFG_48_MHZ;
+	} else {
+		/* High speed PHY running at full speed or high speed */
+		val = DWC_HCFG_30_60_MHZ;
+	}
+
+	DWC_DEBUGPL(DBG_CIL, "Initializing HCFG.FSLSPClkSel to 0x%1x\n", val);
+	hcfg.d32 = dwc_read_reg32(&core_if->host_if->host_global_regs->hcfg);
+	hcfg.b.fslspclksel = val;
+	dwc_write_reg32(&core_if->host_if->host_global_regs->hcfg, hcfg.d32);
+}
+
+/**
+ * Initializes the DevSpd field of the DCFG register depending on the PHY type
+ * and the enumeration speed of the device.
+ */
+static void init_devspd(dwc_otg_core_if_t * core_if)
+{
+	uint32_t val;
+	dcfg_data_t dcfg;
+
+	if (((core_if->hwcfg2.b.hs_phy_type == 2) &&
+	     (core_if->hwcfg2.b.fs_phy_type == 1) &&
+	     (core_if->core_params->ulpi_fs_ls)) ||
+	    (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
+		/* Full speed PHY */
+		val = 0x3;
+	} else if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL) {
+		/* High speed PHY running at full speed */
+		val = 0x1;
+	} else {
+		/* High speed PHY running at high speed */
+		val = 0x0;
+	}
+
+	DWC_DEBUGPL(DBG_CIL, "Initializing DCFG.DevSpd to 0x%1x\n", val);
+
+	dcfg.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dcfg);
+	dcfg.b.devspd = val;
+	dwc_write_reg32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
+}
+
+/**
+ * This function calculates the number of IN EPS
+ * using GHWCFG1 and GHWCFG2 registers values 
+ *
+ * @param core_if Programming view of the DWC_otg controller
+ */
+static uint32_t calc_num_in_eps(dwc_otg_core_if_t * core_if)
+{
+	uint32_t num_in_eps = 0;
+	uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep;
+	uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 3;
+	uint32_t num_tx_fifos = core_if->hwcfg4.b.num_in_eps;
+	int i;
+
+	for (i = 0; i < num_eps; ++i) {
+		if (!(hwcfg1 & 0x1))
+			num_in_eps++;
+
+		hwcfg1 >>= 2;
+	}
+
+	if (core_if->hwcfg4.b.ded_fifo_en) {
+		num_in_eps =
+		    (num_in_eps > num_tx_fifos) ? num_tx_fifos : num_in_eps;
+	}
+
+	return num_in_eps;
+}
+
+/**
+ * This function calculates the number of OUT EPS
+ * using GHWCFG1 and GHWCFG2 registers values 
+ *
+ * @param core_if Programming view of the DWC_otg controller
+ */
+static uint32_t calc_num_out_eps(dwc_otg_core_if_t * core_if)
+{
+	uint32_t num_out_eps = 0;
+	uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep;
+	uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 2;
+	int i;
+
+	for (i = 0; i < num_eps; ++i) {
+		if (!(hwcfg1 & 0x1))
+			num_out_eps++;
+
+		hwcfg1 >>= 2;
+	}
+	return num_out_eps;
+}
+
+/**
+ * This function initializes the DWC_otg controller registers and
+ * prepares the core for device mode or host mode operation.
+ *
+ * @param core_if Programming view of the DWC_otg controller
+ *
+ */
+void dwc_otg_core_init(dwc_otg_core_if_t * core_if)
+{
+	int i = 0;
+	dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
+	dwc_otg_dev_if_t *dev_if = core_if->dev_if;
+	gahbcfg_data_t ahbcfg = {.d32 = 0 };
+	gusbcfg_data_t usbcfg = {.d32 = 0 };
+	gi2cctl_data_t i2cctl = {.d32 = 0 };
+
+	DWC_DEBUGPL(DBG_CILV, "dwc_otg_core_init(%p) regs at %p\n",
+                    core_if, global_regs);
+
+	/* Common Initialization */
+
+	usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
+
+	/* Program the ULPI External VBUS bit if needed */
+	usbcfg.b.ulpi_ext_vbus_drv =
+	    (core_if->core_params->phy_ulpi_ext_vbus ==
+	     DWC_PHY_ULPI_EXTERNAL_VBUS) ? 1 : 0;
+
+	/* Set external TS Dline pulsing */
+	usbcfg.b.term_sel_dl_pulse =
+	    (core_if->core_params->ts_dline == 1) ? 1 : 0;
+	dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
+
+	/* Reset the Controller */
+	dwc_otg_core_reset(core_if);
+
+	/* Initialize parameters from Hardware configuration registers. */
+	dev_if->num_in_eps = calc_num_in_eps(core_if);
+	dev_if->num_out_eps = calc_num_out_eps(core_if);
+
+	DWC_DEBUGPL(DBG_CIL, "num_dev_perio_in_ep=%d\n",
+		    core_if->hwcfg4.b.num_dev_perio_in_ep);
+
+	for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++) {
+		dev_if->perio_tx_fifo_size[i] =
+		    dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]) >> 16;
+		DWC_DEBUGPL(DBG_CIL, "Periodic Tx FIFO SZ #%d=0x%0x\n",
+			    i, dev_if->perio_tx_fifo_size[i]);
+	}
+
+	for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
+		dev_if->tx_fifo_size[i] =
+		    dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]) >> 16;
+		DWC_DEBUGPL(DBG_CIL, "Tx FIFO SZ #%d=0x%0x\n",
+			    i, dev_if->perio_tx_fifo_size[i]);
+	}
+
+	core_if->total_fifo_size = core_if->hwcfg3.b.dfifo_depth;
+	core_if->rx_fifo_size = dwc_read_reg32(&global_regs->grxfsiz);
+	core_if->nperio_tx_fifo_size =
+	    dwc_read_reg32(&global_regs->gnptxfsiz) >> 16;
+
+	DWC_DEBUGPL(DBG_CIL, "Total FIFO SZ=%d\n", core_if->total_fifo_size);
+	DWC_DEBUGPL(DBG_CIL, "Rx FIFO SZ=%d\n", core_if->rx_fifo_size);
+	DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO SZ=%d\n",
+		    core_if->nperio_tx_fifo_size);
+
+	/* This programming sequence needs to happen in FS mode before any other
+	 * programming occurs */
+	if ((core_if->core_params->speed == DWC_SPEED_PARAM_FULL) &&
+	    (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
+		/* If FS mode with FS PHY */
+
+		/* core_init() is now called on every switch so only call the
+		 * following for the first time through. */
+		if (!core_if->phy_init_done) {
+			core_if->phy_init_done = 1;
+			DWC_DEBUGPL(DBG_CIL, "FS_PHY detected\n");
+			usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
+			usbcfg.b.physel = 1;
+			dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
+
+			/* Reset after a PHY select */
+			dwc_otg_core_reset(core_if);
+		}
+
+		/* Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.      Also
+		 * do this on HNP Dev/Host mode switches (done in dev_init and
+		 * host_init). */
+		if (dwc_otg_is_host_mode(core_if)) {
+			init_fslspclksel(core_if);
+		} else {
+			init_devspd(core_if);
+		}
+
+		if (core_if->core_params->i2c_enable) {
+			DWC_DEBUGPL(DBG_CIL, "FS_PHY Enabling I2c\n");
+			/* Program GUSBCFG.OtgUtmifsSel to I2C */
+			usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
+			usbcfg.b.otgutmifssel = 1;
+			dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
+
+			/* Program GI2CCTL.I2CEn */
+			i2cctl.d32 = dwc_read_reg32(&global_regs->gi2cctl);
+			i2cctl.b.i2cdevaddr = 1;
+			i2cctl.b.i2cen = 0;
+			dwc_write_reg32(&global_regs->gi2cctl, i2cctl.d32);
+			i2cctl.b.i2cen = 1;
+			dwc_write_reg32(&global_regs->gi2cctl, i2cctl.d32);
+		}
+
+	} /* endif speed == DWC_SPEED_PARAM_FULL */
+	else {
+		/* High speed PHY. */
+		if (!core_if->phy_init_done) {
+			core_if->phy_init_done = 1;
+			/* HS PHY parameters.  These parameters are preserved
+			 * during soft reset so only program the first time.  Do
+			 * a soft reset immediately after setting phyif.  */
+			usbcfg.b.ulpi_utmi_sel = core_if->core_params->phy_type;
+			if (usbcfg.b.ulpi_utmi_sel == 1) {
+				/* ULPI interface */
+				usbcfg.b.phyif = 0;
+				usbcfg.b.ddrsel =
+				    core_if->core_params->phy_ulpi_ddr;
+			} else {
+				/* UTMI+ interface */
+				if (core_if->core_params->phy_utmi_width == 16) {
+					usbcfg.b.phyif = 1;
+
+				} else {
+					usbcfg.b.phyif = 0;
+				}
+
+			}
+
+			dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
+			/* Reset after setting the PHY parameters */
+			dwc_otg_core_reset(core_if);
+		}
+	}
+
+	if ((core_if->hwcfg2.b.hs_phy_type == 2) &&
+	    (core_if->hwcfg2.b.fs_phy_type == 1) &&
+	    (core_if->core_params->ulpi_fs_ls)) {
+		DWC_DEBUGPL(DBG_CIL, "Setting ULPI FSLS\n");
+		usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
+		usbcfg.b.ulpi_fsls = 1;
+		usbcfg.b.ulpi_clk_sus_m = 1;
+		dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
+	} else {
+		usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
+		usbcfg.b.ulpi_fsls = 0;
+		usbcfg.b.ulpi_clk_sus_m = 0;
+		dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
+	}
+
+	/* Program the GAHBCFG Register. */
+	switch (core_if->hwcfg2.b.architecture) {
+
+	case DWC_SLAVE_ONLY_ARCH:
+		DWC_DEBUGPL(DBG_CIL, "Slave Only Mode\n");
+		ahbcfg.b.nptxfemplvl_txfemplvl =
+		    DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
+		ahbcfg.b.ptxfemplvl = DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
+		core_if->dma_enable = 0;
+		core_if->dma_desc_enable = 0;
+		break;
+
+	case DWC_EXT_DMA_ARCH:
+		DWC_DEBUGPL(DBG_CIL, "External DMA Mode\n");
+		{
+			uint8_t brst_sz = core_if->core_params->dma_burst_size;
+			ahbcfg.b.hburstlen = 0;
+			while (brst_sz > 1) {
+				ahbcfg.b.hburstlen++;
+				brst_sz >>= 1;
+			}
+		}
+		core_if->dma_enable = (core_if->core_params->dma_enable != 0);
+		core_if->dma_desc_enable =
+		    (core_if->core_params->dma_desc_enable != 0);
+		break;
+
+	case DWC_INT_DMA_ARCH:
+		DWC_DEBUGPL(DBG_CIL, "Internal DMA Mode\n");
+		/*ahbcfg.b.hburstlen = DWC_GAHBCFG_INT_DMA_BURST_INCR; */
+		ahbcfg.b.hburstlen = (1<<3)|(0<<0); /* WRESP=1, max 4 beats */
+		core_if->dma_enable = (core_if->core_params->dma_enable != 0);
+		core_if->dma_desc_enable =
+		    (core_if->core_params->dma_desc_enable != 0);
+		break;
+
+	}
+	if (core_if->dma_enable) {
+		if (core_if->dma_desc_enable) {
+			DWC_PRINTF("Using Descriptor DMA mode\n");
+		} else {
+			DWC_PRINTF("Using Buffer DMA mode\n");
+
+		}
+	} else {
+		DWC_PRINTF("Using Slave mode\n");
+		core_if->dma_desc_enable = 0;
+	}
+	
+	ahbcfg.b.dmaenable = core_if->dma_enable;
+	dwc_write_reg32(&global_regs->gahbcfg, ahbcfg.d32);
+
+	core_if->en_multiple_tx_fifo = core_if->hwcfg4.b.ded_fifo_en;
+
+	core_if->pti_enh_enable = core_if->core_params->pti_enable != 0;
+	core_if->multiproc_int_enable = core_if->core_params->mpi_enable;
+	DWC_PRINTF("Periodic Transfer Interrupt Enhancement - %s\n",
+		   ((core_if->pti_enh_enable) ? "enabled" : "disabled"));
+	DWC_PRINTF("Multiprocessor Interrupt Enhancement - %s\n",
+		   ((core_if->multiproc_int_enable) ? "enabled" : "disabled"));
+
+	/* 
+	 * Program the GUSBCFG register. 
+	 */
+	usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
+
+	switch (core_if->hwcfg2.b.op_mode) {
+	case DWC_MODE_HNP_SRP_CAPABLE:
+		usbcfg.b.hnpcap = (core_if->core_params->otg_cap ==
+				   DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE);
+		usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
+				   DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
+		break;
+
+	case DWC_MODE_SRP_ONLY_CAPABLE:
+		usbcfg.b.hnpcap = 0;
+		usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
+				   DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
+		break;
+
+	case DWC_MODE_NO_HNP_SRP_CAPABLE:
+		usbcfg.b.hnpcap = 0;
+		usbcfg.b.srpcap = 0;
+		break;
+
+	case DWC_MODE_SRP_CAPABLE_DEVICE:
+		usbcfg.b.hnpcap = 0;
+		usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
+				   DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
+		break;
+
+	case DWC_MODE_NO_SRP_CAPABLE_DEVICE:
+		usbcfg.b.hnpcap = 0;
+		usbcfg.b.srpcap = 0;
+		break;
+
+	case DWC_MODE_SRP_CAPABLE_HOST:
+		usbcfg.b.hnpcap = 0;
+		usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
+				   DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
+		break;
+
+	case DWC_MODE_NO_SRP_CAPABLE_HOST:
+		usbcfg.b.hnpcap = 0;
+		usbcfg.b.srpcap = 0;
+		break;
+	}
+
+	dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
+
+#ifdef CONFIG_USB_DWC_OTG_LPM
+	if (core_if->core_params->lpm_enable) {
+		glpmcfg_data_t lpmcfg = {.d32 = 0 };
+
+		/* To enable LPM support set lpm_cap_en bit */
+		lpmcfg.b.lpm_cap_en = 1;
+
+		/* Make AppL1Res ACK */
+		lpmcfg.b.appl_resp = 1;
+
+		/* Retry 3 times */
+		lpmcfg.b.retry_count = 3;
+
+		dwc_modify_reg32(&core_if->core_global_regs->glpmcfg,
+				 0, lpmcfg.d32);
+
+	}
+#endif
+	if (core_if->core_params->ic_usb_cap) {
+		gusbcfg_data_t gusbcfg = {.d32 = 0 };
+		gusbcfg.b.ic_usb_cap = 1;
+		dwc_modify_reg32(&core_if->core_global_regs->gusbcfg,
+				 0, gusbcfg.d32);
+	}
+
+	/* Enable common interrupts */
+	dwc_otg_enable_common_interrupts(core_if);
+
+	/* Do device or host intialization based on mode during PCD
+	 * and HCD initialization  */
+	if (dwc_otg_is_host_mode(core_if)) {
+		DWC_DEBUGPL(DBG_ANY, "Host Mode\n");
+		core_if->op_state = A_HOST;
+	} else {
+		DWC_DEBUGPL(DBG_ANY, "Device Mode\n");
+		core_if->op_state = B_PERIPHERAL;
+#ifdef DWC_DEVICE_ONLY
+		dwc_otg_core_dev_init(core_if);
+#endif
+	}
+}
+
+/** 
+ * This function enables the Device mode interrupts.
+ *
+ * @param core_if Programming view of DWC_otg controller
+ */
+void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t * core_if)
+{
+	gintmsk_data_t intr_mask = {.d32 = 0 };
+	dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
+
+	DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__);
+
+	/* Disable all interrupts. */
+	dwc_write_reg32(&global_regs->gintmsk, 0);
+
+	/* Clear any pending interrupts */
+	dwc_write_reg32(&global_regs->gintsts, 0xFFFFFFFF);
+
+	/* Enable the common interrupts */
+	dwc_otg_enable_common_interrupts(core_if);
+
+	/* Enable interrupts */
+	intr_mask.b.usbreset = 1;
+	intr_mask.b.enumdone = 1;
+
+	if (!core_if->multiproc_int_enable) {
+		intr_mask.b.inepintr = 1;
+		intr_mask.b.outepintr = 1;
+	}
+
+	intr_mask.b.erlysuspend = 1;
+
+	if (core_if->en_multiple_tx_fifo == 0) {
+		intr_mask.b.epmismatch = 1;
+	}
+#ifdef DWC_EN_ISOC
+	if (core_if->dma_enable) {
+		if (core_if->dma_desc_enable == 0) {
+			if (core_if->pti_enh_enable) {
+				dctl_data_t dctl = {.d32 = 0 };
+				dctl.b.ifrmnum = 1;
+				dwc_modify_reg32(&core_if->dev_if->
+						 dev_global_regs->dctl, 0,
+						 dctl.d32);
+			} else {
+				intr_mask.b.incomplisoin = 1;
+				intr_mask.b.incomplisoout = 1;
+			}
+		}
+	} else {
+		intr_mask.b.incomplisoin = 1;
+		intr_mask.b.incomplisoout = 1;
+	}
+#endif				/* DWC_EN_ISOC */
+
+	/** @todo NGS: Should this be a module parameter? */
+#ifdef USE_PERIODIC_EP
+	intr_mask.b.isooutdrop = 1;
+	intr_mask.b.eopframe = 1;
+	intr_mask.b.incomplisoin = 1;
+	intr_mask.b.incomplisoout = 1;
+#endif
+
+	dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
+
+	DWC_DEBUGPL(DBG_CIL, "%s() gintmsk=%0x\n", __func__,
+		    dwc_read_reg32(&global_regs->gintmsk));
+}
+
+/**
+ * This function initializes the DWC_otg controller registers for
+ * device mode.
+ * 
+ * @param core_if Programming view of DWC_otg controller
+ *
+ */
+void dwc_otg_core_dev_init(dwc_otg_core_if_t * core_if)
+{
+	int i;
+	dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
+	dwc_otg_dev_if_t *dev_if = core_if->dev_if;
+	dwc_otg_core_params_t *params = core_if->core_params;
+	dcfg_data_t dcfg = {.d32 = 0 };
+	grstctl_t resetctl = {.d32 = 0 };
+	uint32_t rx_fifo_size;
+	fifosize_data_t nptxfifosize;
+	fifosize_data_t txfifosize;
+	dthrctl_data_t dthrctl;
+	fifosize_data_t ptxfifosize;
+
+	/* Restart the Phy Clock */
+	dwc_write_reg32(core_if->pcgcctl, 0);
+
+	/* Device configuration register */
+	init_devspd(core_if);
+	dcfg.d32 = dwc_read_reg32(&dev_if->dev_global_regs->dcfg);
+	dcfg.b.descdma = (core_if->dma_desc_enable) ? 1 : 0;
+	dcfg.b.perfrint = DWC_DCFG_FRAME_INTERVAL_80;
+
+	dwc_write_reg32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
+
+	/* Configure data FIFO sizes */
+	if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
+		DWC_DEBUGPL(DBG_CIL, "Total FIFO Size=%d\n",
+			    core_if->total_fifo_size);
+		DWC_DEBUGPL(DBG_CIL, "Rx FIFO Size=%d\n",
+			    params->dev_rx_fifo_size);
+		DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO Size=%d\n",
+			    params->dev_nperio_tx_fifo_size);
+
+		/* Rx FIFO */
+		DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n",
+			    dwc_read_reg32(&global_regs->grxfsiz));
+
+#ifdef DWC_UTE_CFI
+		core_if->pwron_rxfsiz = dwc_read_reg32(&global_regs->grxfsiz);
+		core_if->init_rxfsiz = params->dev_rx_fifo_size;
+#endif
+		rx_fifo_size = params->dev_rx_fifo_size;
+		dwc_write_reg32(&global_regs->grxfsiz, rx_fifo_size);
+
+		DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n",
+			    dwc_read_reg32(&global_regs->grxfsiz));
+
+		/** Set Periodic Tx FIFO Mask all bits 0 */
+		core_if->p_tx_msk = 0;
+
+		/** Set Tx FIFO Mask all bits 0 */
+		core_if->tx_msk = 0;
+
+		if (core_if->en_multiple_tx_fifo == 0) {
+			/* Non-periodic Tx FIFO */
+			DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
+				    dwc_read_reg32(&global_regs->gnptxfsiz));
+
+			nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
+			nptxfifosize.b.startaddr = params->dev_rx_fifo_size;
+
+			dwc_write_reg32(&global_regs->gnptxfsiz,
+					nptxfifosize.d32);
+
+			DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
+				    dwc_read_reg32(&global_regs->gnptxfsiz));
+
+			/**@todo NGS: Fix Periodic FIFO Sizing! */
+			/*
+			 * Periodic Tx FIFOs These FIFOs are numbered from 1 to 15.
+			 * Indexes of the FIFO size module parameters in the
+			 * dev_perio_tx_fifo_size array and the FIFO size registers in
+			 * the dptxfsiz array run from 0 to 14.
+			 */
+			/** @todo Finish debug of this */
+			ptxfifosize.b.startaddr =
+			    nptxfifosize.b.startaddr + nptxfifosize.b.depth;
+			for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep;
+			     i++) {
+				ptxfifosize.b.depth =
+				    params->dev_perio_tx_fifo_size[i];
+				DWC_DEBUGPL(DBG_CIL,
+					    "initial dptxfsiz_dieptxf[%d]=%08x\n",
+					    i,
+					    dwc_read_reg32(&global_regs->
+							   dptxfsiz_dieptxf
+							   [i]));
+				dwc_write_reg32(&global_regs->
+						dptxfsiz_dieptxf[i],
+						ptxfifosize.d32);
+				DWC_DEBUGPL(DBG_CIL,
+					    "new dptxfsiz_dieptxf[%d]=%08x\n",
+					    i,
+					    dwc_read_reg32(&global_regs->
+							   dptxfsiz_dieptxf
+							   [i]));
+				ptxfifosize.b.startaddr += ptxfifosize.b.depth;
+			}
+		} else {
+			/*
+			 * Tx FIFOs These FIFOs are numbered from 1 to 15.
+			 * Indexes of the FIFO size module parameters in the
+			 * dev_tx_fifo_size array and the FIFO size registers in
+			 * the dptxfsiz_dieptxf array run from 0 to 14.
+			 */
+
+			/* Non-periodic Tx FIFO */
+			DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
+				    dwc_read_reg32(&global_regs->gnptxfsiz));
+
+#ifdef DWC_UTE_CFI
+			core_if->pwron_gnptxfsiz =
+			    (dwc_read_reg32(&global_regs->gnptxfsiz) >> 16);
+			core_if->init_gnptxfsiz =
+			    params->dev_nperio_tx_fifo_size;
+#endif
+			nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
+			nptxfifosize.b.startaddr = params->dev_rx_fifo_size;
+
+			dwc_write_reg32(&global_regs->gnptxfsiz,
+					nptxfifosize.d32);
+
+			DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
+				    dwc_read_reg32(&global_regs->gnptxfsiz));
+
+			txfifosize.b.startaddr =
+			    nptxfifosize.b.startaddr + nptxfifosize.b.depth;
+
+			for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
+
+				txfifosize.b.depth =
+				    params->dev_tx_fifo_size[i];
+
+				DWC_DEBUGPL(DBG_CIL,
+					    "initial dptxfsiz_dieptxf[%d]=%08x\n",
+					    i,
+					    dwc_read_reg32(&global_regs->
+							   dptxfsiz_dieptxf
+							   [i]));
+
+#ifdef DWC_UTE_CFI
+				core_if->pwron_txfsiz[i] =
+				    (dwc_read_reg32
+				     (&global_regs->dptxfsiz_dieptxf[i]) >> 16);
+				core_if->init_txfsiz[i] =
+				    params->dev_tx_fifo_size[i];
+#endif
+				dwc_write_reg32(&global_regs->
+						dptxfsiz_dieptxf[i],
+						txfifosize.d32);
+
+				DWC_DEBUGPL(DBG_CIL,
+					    "new dptxfsiz_dieptxf[%d]=%08x\n",
+					    i,
+					    dwc_read_reg32(&global_regs->
+							   dptxfsiz_dieptxf
+							   [i]));
+
+				txfifosize.b.startaddr += txfifosize.b.depth;
+			}
+		}
+	}
+	/* Flush the FIFOs */
+	dwc_otg_flush_tx_fifo(core_if, 0x10);	/* all Tx FIFOs */
+	dwc_otg_flush_rx_fifo(core_if);
+
+	/* Flush the Learning Queue. */
+	resetctl.b.intknqflsh = 1;
+	dwc_write_reg32(&core_if->core_global_regs->grstctl, resetctl.d32);
+
+	/* Clear all pending Device Interrupts */
+	/** @todo - if the condition needed to be checked 
+	 *  or in any case all pending interrutps should be cleared? 
+         */
+	if (core_if->multiproc_int_enable) {
+		for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
+			dwc_write_reg32(&dev_if->dev_global_regs->
+					diepeachintmsk[i], 0);
+		}
+
+		for (i = 0; i < core_if->dev_if->num_out_eps; ++i) {
+			dwc_write_reg32(&dev_if->dev_global_regs->
+					doepeachintmsk[i], 0);
+		}
+
+		dwc_write_reg32(&dev_if->dev_global_regs->deachint, 0xFFFFFFFF);
+		dwc_write_reg32(&dev_if->dev_global_regs->deachintmsk, 0);
+	} else {
+		dwc_write_reg32(&dev_if->dev_global_regs->diepmsk, 0);
+		dwc_write_reg32(&dev_if->dev_global_regs->doepmsk, 0);
+		dwc_write_reg32(&dev_if->dev_global_regs->daint, 0xFFFFFFFF);
+		dwc_write_reg32(&dev_if->dev_global_regs->daintmsk, 0);
+	}
+
+	for (i = 0; i <= dev_if->num_in_eps; i++) {
+		depctl_data_t depctl;
+		depctl.d32 = dwc_read_reg32(&dev_if->in_ep_regs[i]->diepctl);
+		if (depctl.b.epena) {
+			depctl.d32 = 0;
+			depctl.b.epdis = 1;
+			depctl.b.snak = 1;
+		} else {
+			depctl.d32 = 0;
+		}
+
+		dwc_write_reg32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32);
+
+		dwc_write_reg32(&dev_if->in_ep_regs[i]->dieptsiz, 0);
+		dwc_write_reg32(&dev_if->in_ep_regs[i]->diepdma, 0);
+		dwc_write_reg32(&dev_if->in_ep_regs[i]->diepint, 0xFF);
+	}
+
+	for (i = 0; i <= dev_if->num_out_eps; i++) {
+		depctl_data_t depctl;
+		depctl.d32 = dwc_read_reg32(&dev_if->out_ep_regs[i]->doepctl);
+		if (depctl.b.epena) {
+			depctl.d32 = 0;
+			depctl.b.epdis = 1;
+			depctl.b.snak = 1;
+		} else {
+			depctl.d32 = 0;
+		}
+
+		dwc_write_reg32(&dev_if->out_ep_regs[i]->doepctl, depctl.d32);
+
+		dwc_write_reg32(&dev_if->out_ep_regs[i]->doeptsiz, 0);
+		dwc_write_reg32(&dev_if->out_ep_regs[i]->doepdma, 0);
+		dwc_write_reg32(&dev_if->out_ep_regs[i]->doepint, 0xFF);
+	}
+
+	if (core_if->en_multiple_tx_fifo && core_if->dma_enable) {
+		dev_if->non_iso_tx_thr_en = params->thr_ctl & 0x1;
+		dev_if->iso_tx_thr_en = (params->thr_ctl >> 1) & 0x1;
+		dev_if->rx_thr_en = (params->thr_ctl >> 2) & 0x1;
+
+		dev_if->rx_thr_length = params->rx_thr_length;
+		dev_if->tx_thr_length = params->tx_thr_length;
+
+		dev_if->setup_desc_index = 0;
+
+		dthrctl.d32 = 0;
+		dthrctl.b.non_iso_thr_en = dev_if->non_iso_tx_thr_en;
+		dthrctl.b.iso_thr_en = dev_if->iso_tx_thr_en;
+		dthrctl.b.tx_thr_len = dev_if->tx_thr_length;
+		dthrctl.b.rx_thr_en = dev_if->rx_thr_en;
+		dthrctl.b.rx_thr_len = dev_if->rx_thr_length;
+		dthrctl.b.ahb_thr_ratio = params->ahb_thr_ratio;
+
+		dwc_write_reg32(&dev_if->dev_global_regs->dtknqr3_dthrctl,
+				dthrctl.d32);
+
+		DWC_DEBUGPL(DBG_CIL,
+			    "Non ISO Tx Thr - %d\nISO Tx Thr - %d\nRx Thr - %d\nTx Thr Len - %d\nRx Thr Len - %d\n",
+			    dthrctl.b.non_iso_thr_en, dthrctl.b.iso_thr_en,
+			    dthrctl.b.rx_thr_en, dthrctl.b.tx_thr_len,
+			    dthrctl.b.rx_thr_len);
+
+	}
+
+	dwc_otg_enable_device_interrupts(core_if);
+
+	{
+		diepmsk_data_t msk = {.d32 = 0 };
+		msk.b.txfifoundrn = 1;
+		if (core_if->multiproc_int_enable) {
+			dwc_modify_reg32(&dev_if->dev_global_regs->
+					 diepeachintmsk[0], msk.d32, msk.d32);
+		} else {
+			dwc_modify_reg32(&dev_if->dev_global_regs->diepmsk,
+					 msk.d32, msk.d32);
+		}
+	}
+
+	if (core_if->multiproc_int_enable) {
+		/* Set NAK on Babble */
+		dctl_data_t dctl = {.d32 = 0 };
+		dctl.b.nakonbble = 1;
+		dwc_modify_reg32(&dev_if->dev_global_regs->dctl, 0, dctl.d32);
+	}
+}
+
+/** 
+ * This function enables the Host mode interrupts.
+ *
+ * @param core_if Programming view of DWC_otg controller
+ */
+void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t * core_if)
+{
+	dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
+	gintmsk_data_t intr_mask = {.d32 = 0 };
+
+	DWC_DEBUGPL(DBG_CIL, "%s(%p)\n", __func__, core_if);
+
+	/* Disable all interrupts. */
+	dwc_write_reg32(&global_regs->gintmsk, 0);
+
+	/* Clear any pending interrupts. */
+	dwc_write_reg32(&global_regs->gintsts, 0xFFFFFFFF);
+
+	/* Enable the common interrupts */
+	dwc_otg_enable_common_interrupts(core_if);
+
+	/*
+	 * Enable host mode interrupts without disturbing common
+	 * interrupts.
+	 */
+	 
+	/* Do not need sof interrupt for Descriptor DMA*/ 
+	if (!core_if->dma_desc_enable) 
+	intr_mask.b.sofintr = 1;
+	intr_mask.b.portintr = 1;
+	intr_mask.b.hcintr = 1;
+
+	dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
+}
+
+/** 
+ * This function disables the Host Mode interrupts.
+ *
+ * @param core_if Programming view of DWC_otg controller
+ */
+void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t * core_if)
+{
+	dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
+	gintmsk_data_t intr_mask = {.d32 = 0 };
+
+	DWC_DEBUGPL(DBG_CILV, "%s()\n", __func__);
+
+	/*
+	 * Disable host mode interrupts without disturbing common
+	 * interrupts.
+	 */
+	intr_mask.b.sofintr = 1;
+	intr_mask.b.portintr = 1;
+	intr_mask.b.hcintr = 1;
+	intr_mask.b.ptxfempty = 1;
+	intr_mask.b.nptxfempty = 1;
+
+	dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0);
+}
+
+/**
+ * This function initializes the DWC_otg controller registers for
+ * host mode.
+ *
+ * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
+ * request queues. Host channels are reset to ensure that they are ready for
+ * performing transfers.
+ *
+ * @param core_if Programming view of DWC_otg controller
+ *
+ */
+void dwc_otg_core_host_init(dwc_otg_core_if_t * core_if)
+{
+	dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
+	dwc_otg_host_if_t *host_if = core_if->host_if;
+	dwc_otg_core_params_t *params = core_if->core_params;
+	hprt0_data_t hprt0 = {.d32 = 0 };
+	fifosize_data_t nptxfifosize;
+	fifosize_data_t ptxfifosize;
+	int i;
+	hcchar_data_t hcchar;
+	hcfg_data_t hcfg;
+	dwc_otg_hc_regs_t *hc_regs;
+	int num_channels;
+	gotgctl_data_t gotgctl = {.d32 = 0 };
+
+	DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, core_if);
+
+	/* Restart the Phy Clock */
+	dwc_write_reg32(core_if->pcgcctl, 0);
+
+	/* Initialize Host Configuration Register */
+	init_fslspclksel(core_if);
+	if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL) {
+		hcfg.d32 = dwc_read_reg32(&host_if->host_global_regs->hcfg);
+		hcfg.b.fslssupp = 1;
+		dwc_write_reg32(&host_if->host_global_regs->hcfg, hcfg.d32);
+		
+	}
+
+	if (core_if->core_params->dma_desc_enable) {
+		uint8_t op_mode = core_if->hwcfg2.b.op_mode;	
+		if (!(core_if->hwcfg4.b.desc_dma && (core_if->snpsid >= OTG_CORE_REV_2_90a) &&
+				((op_mode == DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) ||
+				(op_mode == DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) || 
+				(op_mode == DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG) ||
+				(op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST) ||
+				(op_mode == DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST)))) {
+				
+				DWC_ERROR("Host can't operate in Descriptor DMA mode.\n"
+					  "Either core version is below 2.90a or "
+					  "GHWCFG2, GHWCFG4 registers' values do not allow Descriptor DMA in host mode.\n"
+					  "To run the driver in Buffer DMA host mode set dma_desc_enable "
+					  "module parameter to 0.\n");
+				return;
+		}		
+		hcfg.d32 = dwc_read_reg32(&host_if->host_global_regs->hcfg);
+		hcfg.b.descdma = 1;
+		dwc_write_reg32(&host_if->host_global_regs->hcfg, hcfg.d32);
+	}
+	
+	/* Configure data FIFO sizes */
+	if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
+		DWC_DEBUGPL(DBG_CIL, "Total FIFO Size=%d\n",
+			    core_if->total_fifo_size);
+		DWC_DEBUGPL(DBG_CIL, "Rx FIFO Size=%d\n",
+			    params->host_rx_fifo_size);
+		DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO Size=%d\n",
+			    params->host_nperio_tx_fifo_size);
+		DWC_DEBUGPL(DBG_CIL, "P Tx FIFO Size=%d\n",
+			    params->host_perio_tx_fifo_size);
+
+		/* Rx FIFO */
+		DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n",
+			    dwc_read_reg32(&global_regs->grxfsiz));
+		dwc_write_reg32(&global_regs->grxfsiz,
+				params->host_rx_fifo_size);
+		DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n",
+			    dwc_read_reg32(&global_regs->grxfsiz));
+
+		/* Non-periodic Tx FIFO */
+		DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
+			    dwc_read_reg32(&global_regs->gnptxfsiz));
+		nptxfifosize.b.depth = params->host_nperio_tx_fifo_size;
+		nptxfifosize.b.startaddr = params->host_rx_fifo_size;
+		dwc_write_reg32(&global_regs->gnptxfsiz, nptxfifosize.d32);
+		DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
+			    dwc_read_reg32(&global_regs->gnptxfsiz));
+
+		/* Periodic Tx FIFO */
+		DWC_DEBUGPL(DBG_CIL, "initial hptxfsiz=%08x\n",
+			    dwc_read_reg32(&global_regs->hptxfsiz));
+		ptxfifosize.b.depth = params->host_perio_tx_fifo_size;
+		ptxfifosize.b.startaddr =
+		    nptxfifosize.b.startaddr + nptxfifosize.b.depth;
+		dwc_write_reg32(&global_regs->hptxfsiz, ptxfifosize.d32);
+		DWC_DEBUGPL(DBG_CIL, "new hptxfsiz=%08x\n",
+			    dwc_read_reg32(&global_regs->hptxfsiz));
+	}
+
+	/* Clear Host Set HNP Enable in the OTG Control Register */
+	gotgctl.b.hstsethnpen = 1;
+	dwc_modify_reg32(&global_regs->gotgctl, gotgctl.d32, 0);
+
+	/* Make sure the FIFOs are flushed. */
+	dwc_otg_flush_tx_fifo(core_if, 0x10 /* all Tx FIFOs */ );
+	dwc_otg_flush_rx_fifo(core_if);
+
+	if(!core_if->core_params->dma_desc_enable) {
+		/* Flush out any leftover queued requests. */
+		num_channels = core_if->core_params->host_channels;
+	
+		for (i = 0; i < num_channels; i++) {
+			hc_regs = core_if->host_if->hc_regs[i];
+			hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+			hcchar.b.chen = 0;
+			hcchar.b.chdis = 1;
+			hcchar.b.epdir = 0;
+			dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
+		}
+
+		/* Halt all channels to put them into a known state. */
+		for (i = 0; i < num_channels; i++) {
+			int count = 0;
+			hc_regs = core_if->host_if->hc_regs[i];
+			hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+			hcchar.b.chen = 1;
+			hcchar.b.chdis = 1;
+			hcchar.b.epdir = 0;
+			dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
+			DWC_DEBUGPL(DBG_HCDV, "%s: Halt channel %d regs %p\n", __func__, i, hc_regs);
+			do {
+				hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+				if (++count > 1000) {
+					DWC_ERROR
+					    ("%s: Unable to clear halt on channel %d (timeout HCCHAR 0x%X @%p)\n",
+					     __func__, i, hcchar.d32, &hc_regs->hcchar);
+					break;
+				}
+				dwc_udelay(1);
+			} while (hcchar.b.chen);
+		}
+	}
+	
+	/* Turn on the vbus power. */
+	DWC_PRINTF("Init: Port Power? op_state=%d\n", core_if->op_state);
+	if (core_if->op_state == A_HOST) {
+		hprt0.d32 = dwc_otg_read_hprt0(core_if);
+		DWC_PRINTF("Init: Power Port (%d)\n", hprt0.b.prtpwr);
+		if (hprt0.b.prtpwr == 0) {
+			hprt0.b.prtpwr = 1;
+			dwc_write_reg32(host_if->hprt0, hprt0.d32);
+		}
+	}
+
+	dwc_otg_enable_host_interrupts(core_if);
+}
+
+/**
+ * Prepares a host channel for transferring packets to/from a specific
+ * endpoint. The HCCHARn register is set up with the characteristics specified
+ * in _hc. Host channel interrupts that may need to be serviced while this
+ * transfer is in progress are enabled.
+ *
+ * @param core_if Programming view of DWC_otg controller
+ * @param hc Information needed to initialize the host channel
+ */
+void dwc_otg_hc_init(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
+{
+	uint32_t intr_enable;
+	hcintmsk_data_t hc_intr_mask;
+	gintmsk_data_t gintmsk = {.d32 = 0 };
+	hcchar_data_t hcchar;
+	hcsplt_data_t hcsplt;
+
+	uint8_t hc_num = hc->hc_num;
+	dwc_otg_host_if_t *host_if = core_if->host_if;
+	dwc_otg_hc_regs_t *hc_regs = host_if->hc_regs[hc_num];
+
+	/* Clear old interrupt conditions for this host channel. */
+	hc_intr_mask.d32 = 0xFFFFFFFF;
+	hc_intr_mask.b.reserved14_31 = 0;
+	dwc_write_reg32(&hc_regs->hcint, hc_intr_mask.d32);
+
+	/* Enable channel interrupts required for this transfer. */
+	hc_intr_mask.d32 = 0;
+	hc_intr_mask.b.chhltd = 1;
+	if (core_if->dma_enable) {
+		/* For Descriptor DMA mode core halts the channel on AHB error. Interrupt is not required */
+		if (!core_if->dma_desc_enable)
+			hc_intr_mask.b.ahberr = 1;
+		else {
+			if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) 
+				hc_intr_mask.b.xfercompl = 1;
+		}
+		
+		if (hc->error_state && !hc->do_split &&
+		    hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
+			hc_intr_mask.b.ack = 1;
+			if (hc->ep_is_in) {
+				hc_intr_mask.b.datatglerr = 1;
+				if (hc->ep_type != DWC_OTG_EP_TYPE_INTR) {
+					hc_intr_mask.b.nak = 1;
+				}
+			}
+		}
+	} else {
+		switch (hc->ep_type) {
+		case DWC_OTG_EP_TYPE_CONTROL:
+		case DWC_OTG_EP_TYPE_BULK:
+			hc_intr_mask.b.xfercompl = 1;
+			hc_intr_mask.b.stall = 1;
+			hc_intr_mask.b.xacterr = 1;
+			hc_intr_mask.b.datatglerr = 1;
+			if (hc->ep_is_in) {
+				hc_intr_mask.b.bblerr = 1;
+			} else {
+				hc_intr_mask.b.nak = 1;
+				hc_intr_mask.b.nyet = 1;
+				if (hc->do_ping) {
+					hc_intr_mask.b.ack = 1;
+				}
+			}
+
+			if (hc->do_split) {
+				hc_intr_mask.b.nak = 1;
+				if (hc->complete_split) {
+					hc_intr_mask.b.nyet = 1;
+				} else {
+					hc_intr_mask.b.ack = 1;
+				}
+			}
+
+			if (hc->error_state) {
+				hc_intr_mask.b.ack = 1;
+			}
+			break;
+		case DWC_OTG_EP_TYPE_INTR:
+			hc_intr_mask.b.xfercompl = 1;
+			hc_intr_mask.b.nak = 1;
+			hc_intr_mask.b.stall = 1;
+			hc_intr_mask.b.xacterr = 1;
+			hc_intr_mask.b.datatglerr = 1;
+			hc_intr_mask.b.frmovrun = 1;
+
+			if (hc->ep_is_in) {
+				hc_intr_mask.b.bblerr = 1;
+			}
+			if (hc->error_state) {
+				hc_intr_mask.b.ack = 1;
+			}
+			if (hc->do_split) {
+				if (hc->complete_split) {
+					hc_intr_mask.b.nyet = 1;
+				} else {
+					hc_intr_mask.b.ack = 1;
+				}
+			}
+			break;
+		case DWC_OTG_EP_TYPE_ISOC:
+			hc_intr_mask.b.xfercompl = 1;
+			hc_intr_mask.b.frmovrun = 1;
+			hc_intr_mask.b.ack = 1;
+
+			if (hc->ep_is_in) {
+				hc_intr_mask.b.xacterr = 1;
+				hc_intr_mask.b.bblerr = 1;
+			}
+			break;
+		}
+	}
+	dwc_write_reg32(&hc_regs->hcintmsk, hc_intr_mask.d32);
+
+	/* Enable the top level host channel interrupt. */
+	intr_enable = (1 << hc_num);
+	dwc_modify_reg32(&host_if->host_global_regs->haintmsk, 0, intr_enable);
+
+	/* Make sure host channel interrupts are enabled. */
+	gintmsk.b.hcintr = 1;
+	dwc_modify_reg32(&core_if->core_global_regs->gintmsk, 0, gintmsk.d32);
+
+	/*
+	 * Program the HCCHARn register with the endpoint characteristics for
+	 * the current transfer.
+	 */
+	hcchar.d32 = 0;
+	hcchar.b.devaddr = hc->dev_addr;
+	hcchar.b.epnum = hc->ep_num;
+	hcchar.b.epdir = hc->ep_is_in;
+	hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW);
+	hcchar.b.eptype = hc->ep_type;
+	hcchar.b.mps = hc->max_packet;
+
+	dwc_write_reg32(&host_if->hc_regs[hc_num]->hcchar, hcchar.d32);
+
+	DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
+	DWC_DEBUGPL(DBG_HCDV, "	 Dev Addr: %d\n", hcchar.b.devaddr);
+	DWC_DEBUGPL(DBG_HCDV, "	 Ep Num: %d\n", hcchar.b.epnum);
+	DWC_DEBUGPL(DBG_HCDV, "	 Is In: %d\n", hcchar.b.epdir);
+	DWC_DEBUGPL(DBG_HCDV, "	 Is Low Speed: %d\n", hcchar.b.lspddev);
+	DWC_DEBUGPL(DBG_HCDV, "	 Ep Type: %d\n", hcchar.b.eptype);
+	DWC_DEBUGPL(DBG_HCDV, "	 Max Pkt: %d\n", hcchar.b.mps);
+	DWC_DEBUGPL(DBG_HCDV, "	 Multi Cnt: %d\n", hcchar.b.multicnt);
+
+	/*
+	 * Program the HCSPLIT register for SPLITs
+	 */
+	hcsplt.d32 = 0;
+	if (hc->do_split) {
+		DWC_DEBUGPL(DBG_HCDV, "Programming HC %d with split --> %s\n",
+			    hc->hc_num,
+			    hc->complete_split ? "CSPLIT" : "SSPLIT");
+		hcsplt.b.compsplt = hc->complete_split;
+		hcsplt.b.xactpos = hc->xact_pos;
+		hcsplt.b.hubaddr = hc->hub_addr;
+		hcsplt.b.prtaddr = hc->port_addr;
+		DWC_DEBUGPL(DBG_HCDV, "	  comp split %d\n", hc->complete_split);
+		DWC_DEBUGPL(DBG_HCDV, "	  xact pos %d\n", hc->xact_pos);
+		DWC_DEBUGPL(DBG_HCDV, "	  hub addr %d\n", hc->hub_addr);
+		DWC_DEBUGPL(DBG_HCDV, "	  port addr %d\n", hc->port_addr);
+		DWC_DEBUGPL(DBG_HCDV, "	  is_in %d\n", hc->ep_is_in);
+		DWC_DEBUGPL(DBG_HCDV, "	  Max Pkt: %d\n", hcchar.b.mps);
+		DWC_DEBUGPL(DBG_HCDV, "	  xferlen: %d\n", hc->xfer_len);
+	}
+	dwc_write_reg32(&host_if->hc_regs[hc_num]->hcsplt, hcsplt.d32);
+
+}
+
+/**
+ * Attempts to halt a host channel. This function should only be called in
+ * Slave mode or to abort a transfer in either Slave mode or DMA mode. Under
+ * normal circumstances in DMA mode, the controller halts the channel when the
+ * transfer is complete or a condition occurs that requires application
+ * intervention.
+ *
+ * In slave mode, checks for a free request queue entry, then sets the Channel
+ * Enable and Channel Disable bits of the Host Channel Characteristics
+ * register of the specified channel to intiate the halt. If there is no free
+ * request queue entry, sets only the Channel Disable bit of the HCCHARn
+ * register to flush requests for this channel. In the latter case, sets a
+ * flag to indicate that the host channel needs to be halted when a request
+ * queue slot is open.
+ *
+ * In DMA mode, always sets the Channel Enable and Channel Disable bits of the
+ * HCCHARn register. The controller ensures there is space in the request
+ * queue before submitting the halt request.
+ *
+ * Some time may elapse before the core flushes any posted requests for this
+ * host channel and halts. The Channel Halted interrupt handler completes the
+ * deactivation of the host channel.
+ *
+ * @param core_if Controller register interface.
+ * @param hc Host channel to halt.
+ * @param halt_status Reason for halting the channel.
+ */
+void dwc_otg_hc_halt(dwc_otg_core_if_t * core_if,
+		     dwc_hc_t * hc, dwc_otg_halt_status_e halt_status)
+{
+	gnptxsts_data_t nptxsts;
+	hptxsts_data_t hptxsts;
+	hcchar_data_t hcchar;
+	dwc_otg_hc_regs_t *hc_regs;
+	dwc_otg_core_global_regs_t *global_regs;
+	dwc_otg_host_global_regs_t *host_global_regs;
+
+	DWC_DEBUGPL(DBG_HW2937, "  dwc_otg_hc_halt(%d)\n", hc->hc_num);
+	hc_regs = core_if->host_if->hc_regs[hc->hc_num];
+	global_regs = core_if->core_global_regs;
+	host_global_regs = core_if->host_if->host_global_regs;
+
+	DWC_ASSERT(!(halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS),
+		   "halt_status = %d\n", halt_status);
+
+	if (halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
+	    halt_status == DWC_OTG_HC_XFER_AHB_ERR) {
+		/*
+		 * Disable all channel interrupts except Ch Halted. The QTD
+		 * and QH state associated with this transfer has been cleared
+		 * (in the case of URB_DEQUEUE), so the channel needs to be
+		 * shut down carefully to prevent crashes.
+		 */
+		hcintmsk_data_t hcintmsk;
+		hcintmsk.d32 = 0;
+		hcintmsk.b.chhltd = 1;
+		dwc_write_reg32(&hc_regs->hcintmsk, hcintmsk.d32);
+
+		/*
+		 * Make sure no other interrupts besides halt are currently
+		 * pending. Handling another interrupt could cause a crash due
+		 * to the QTD and QH state.
+		 */
+		dwc_write_reg32(&hc_regs->hcint, ~hcintmsk.d32);
+
+		/*
+		 * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
+		 * even if the channel was already halted for some other
+		 * reason.
+		 */
+		hc->halt_status = halt_status;
+
+		hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+		if (hcchar.b.chen == 0) {
+			/*
+			 * The channel is either already halted or it hasn't
+			 * started yet. In DMA mode, the transfer may halt if
+			 * it finishes normally or a condition occurs that
+			 * requires driver intervention. Don't want to halt
+			 * the channel again. In either Slave or DMA mode,
+			 * it's possible that the transfer has been assigned
+			 * to a channel, but not started yet when an URB is
+			 * dequeued. Don't want to halt a channel that hasn't
+			 * started yet.
+			 */
+			return;
+		}
+	}
+	if (hc->halt_pending) {
+		/*
+		 * A halt has already been issued for this channel. This might
+		 * happen when a transfer is aborted by a higher level in
+		 * the stack.
+		 */
+#ifdef DEBUG
+		DWC_PRINTF
+		    ("*** %s: Channel %d, _hc->halt_pending already set ***\n",
+		     __func__, hc->hc_num);
+
+#endif
+		return;
+	}
+
+	hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+	
+	/* No need to set the bit in DDMA for disabling the channel */
+	//TODO check it everywhere channel is disabled		
+	if(!core_if->core_params->dma_desc_enable)
+		hcchar.b.chen = 1;
+	hcchar.b.chdis = 1;
+	
+	if (!core_if->dma_enable) {
+		/* Check for space in the request queue to issue the halt. */
+		if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
+		    hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
+			nptxsts.d32 = dwc_read_reg32(&global_regs->gnptxsts);
+			if (nptxsts.b.nptxqspcavail == 0) {
+				hcchar.b.chen = 0;
+			}
+		} else {
+			hptxsts.d32 =
+			    dwc_read_reg32(&host_global_regs->hptxsts);
+			if ((hptxsts.b.ptxqspcavail == 0)
+			    || (core_if->queuing_high_bandwidth)) {
+				hcchar.b.chen = 0;
+			}
+		}
+	}
+	dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
+
+	hc->halt_status = halt_status;
+
+	if (hcchar.b.chen) {
+		hc->halt_pending = 1;
+		hc->halt_on_queue = 0;
+	} else {
+		hc->halt_on_queue = 1;
+	}
+
+	DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
+	DWC_DEBUGPL(DBG_HCDV, "	 hcchar: 0x%08x\n", hcchar.d32);
+	DWC_DEBUGPL(DBG_HCDV, "	 halt_pending: %d\n", hc->halt_pending);
+	DWC_DEBUGPL(DBG_HCDV, "	 halt_on_queue: %d\n", hc->halt_on_queue);
+	DWC_DEBUGPL(DBG_HCDV, "	 halt_status: %d\n", hc->halt_status);
+
+	return;
+}
+
+/**
+ * Clears the transfer state for a host channel. This function is normally
+ * called after a transfer is done and the host channel is being released.
+ *
+ * @param core_if Programming view of DWC_otg controller.
+ * @param hc Identifies the host channel to clean up.
+ */
+void dwc_otg_hc_cleanup(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
+{
+	dwc_otg_hc_regs_t *hc_regs;
+
+	hc->xfer_started = 0;
+
+	/*
+	 * Clear channel interrupt enables and any unhandled channel interrupt
+	 * conditions.
+	 */
+	hc_regs = core_if->host_if->hc_regs[hc->hc_num];
+	dwc_write_reg32(&hc_regs->hcintmsk, 0);
+	dwc_write_reg32(&hc_regs->hcint, 0xFFFFFFFF);
+#ifdef DEBUG
+	DWC_TIMER_CANCEL(core_if->hc_xfer_timer[hc->hc_num]);
+#endif
+}
+
+/**
+ * Sets the channel property that indicates in which frame a periodic transfer
+ * should occur. This is always set to the _next_ frame. This function has no
+ * effect on non-periodic transfers.
+ *
+ * @param core_if Programming view of DWC_otg controller.
+ * @param hc Identifies the host channel to set up and its properties.
+ * @param hcchar Current value of the HCCHAR register for the specified host
+ * channel.
+ */
+static inline void hc_set_even_odd_frame(dwc_otg_core_if_t * core_if,
+					 dwc_hc_t * hc, hcchar_data_t * hcchar)
+{
+	if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
+	    hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
+		hfnum_data_t hfnum;
+		hfnum.d32 =
+		    dwc_read_reg32(&core_if->host_if->host_global_regs->hfnum);
+
+		/* 1 if _next_ frame is odd, 0 if it's even */
+		hcchar->b.oddfrm = (hfnum.b.frnum & 0x1) ? 0 : 1;
+#ifdef DEBUG
+		if (hc->ep_type == DWC_OTG_EP_TYPE_INTR && hc->do_split
+		    && !hc->complete_split) {
+			switch (hfnum.b.frnum & 0x7) {
+			case 7:
+				core_if->hfnum_7_samples++;
+				core_if->hfnum_7_frrem_accum += hfnum.b.frrem;
+				break;
+			case 0:
+				core_if->hfnum_0_samples++;
+				core_if->hfnum_0_frrem_accum += hfnum.b.frrem;
+				break;
+			default:
+				core_if->hfnum_other_samples++;
+				core_if->hfnum_other_frrem_accum +=
+				    hfnum.b.frrem;
+				break;
+			}
+		}
+#endif
+	}
+}
+
+#ifdef DEBUG
+void hc_xfer_timeout(void *ptr)
+{
+	hc_xfer_info_t *xfer_info = (hc_xfer_info_t *) ptr;
+	int hc_num = xfer_info->hc->hc_num;
+	DWC_WARN("%s: timeout on channel %d\n", __func__, hc_num);
+	DWC_WARN("	start_hcchar_val 0x%08x\n",
+		 xfer_info->core_if->start_hcchar_val[hc_num]);
+}
+#endif
+
+void set_pid_isoc(dwc_hc_t * hc)
+{
+	/* Set up the initial PID for the transfer. */
+	if (hc->speed == DWC_OTG_EP_SPEED_HIGH) {
+		if (hc->ep_is_in) {
+			if (hc->multi_count == 1) {
+				hc->data_pid_start =
+				    DWC_OTG_HC_PID_DATA0;
+			} else if (hc->multi_count == 2) {
+				hc->data_pid_start =
+				    DWC_OTG_HC_PID_DATA1;
+			} else {
+				hc->data_pid_start =
+				    DWC_OTG_HC_PID_DATA2;
+			}
+		} else {
+			if (hc->multi_count == 1) {
+				hc->data_pid_start =
+				    DWC_OTG_HC_PID_DATA0;
+			} else {
+				hc->data_pid_start =
+				    DWC_OTG_HC_PID_MDATA;
+			}
+		}
+	} else {
+		hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
+	}
+}
+
+/**
+ * This function does the setup for a data transfer for a host channel and
+ * starts the transfer. May be called in either Slave mode or DMA mode. In
+ * Slave mode, the caller must ensure that there is sufficient space in the
+ * request queue and Tx Data FIFO.
+ *
+ * For an OUT transfer in Slave mode, it loads a data packet into the
+ * appropriate FIFO. If necessary, additional data packets will be loaded in
+ * the Host ISR.
+ *
+ * For an IN transfer in Slave mode, a data packet is requested. The data
+ * packets are unloaded from the Rx FIFO in the Host ISR. If necessary,
+ * additional data packets are requested in the Host ISR.
+ *
+ * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ
+ * register along with a packet count of 1 and the channel is enabled. This
+ * causes a single PING transaction to occur. Other fields in HCTSIZ are
+ * simply set to 0 since no data transfer occurs in this case.
+ *
+ * For a PING transfer in DMA mode, the HCTSIZ register is initialized with
+ * all the information required to perform the subsequent data transfer. In
+ * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the
+ * controller performs the entire PING protocol, then starts the data
+ * transfer.
+ *
+ * @param core_if Programming view of DWC_otg controller.
+ * @param hc Information needed to initialize the host channel. The xfer_len
+ * value may be reduced to accommodate the max widths of the XferSize and
+ * PktCnt fields in the HCTSIZn register. The multi_count value may be changed
+ * to reflect the final xfer_len value.
+ */
+void dwc_otg_hc_start_transfer(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
+{
+	hcchar_data_t hcchar;
+	hctsiz_data_t hctsiz;
+	uint16_t num_packets;
+	uint32_t max_hc_xfer_size = core_if->core_params->max_transfer_size;
+	uint16_t max_hc_pkt_count = core_if->core_params->max_packet_count;
+	dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
+
+	hctsiz.d32 = 0;
+
+	if (hc->do_ping) {
+		if (!core_if->dma_enable) {
+			dwc_otg_hc_do_ping(core_if, hc);
+			hc->xfer_started = 1;
+			return;
+		} else {
+			hctsiz.b.dopng = 1;
+		}
+	}
+
+	if (hc->do_split) {
+		num_packets = 1;
+
+		if (hc->complete_split && !hc->ep_is_in) {
+			/* For CSPLIT OUT Transfer, set the size to 0 so the
+			 * core doesn't expect any data written to the FIFO */
+			hc->xfer_len = 0;
+		} else if (hc->ep_is_in || (hc->xfer_len > hc->max_packet)) {
+			hc->xfer_len = hc->max_packet;
+		} else if (!hc->ep_is_in && (hc->xfer_len > 188)) {
+			hc->xfer_len = 188;
+		}
+
+		hctsiz.b.xfersize = hc->xfer_len;
+	} else {
+		/*
+		 * Ensure that the transfer length and packet count will fit
+		 * in the widths allocated for them in the HCTSIZn register.
+		 */
+		if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
+		    hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
+			/*
+			 * Make sure the transfer size is no larger than one
+			 * (micro)frame's worth of data. (A check was done
+			 * when the periodic transfer was accepted to ensure
+			 * that a (micro)frame's worth of data can be
+			 * programmed into a channel.)
+			 */
+			uint32_t max_periodic_len =
+			    hc->multi_count * hc->max_packet;
+			if (hc->xfer_len > max_periodic_len) {
+				hc->xfer_len = max_periodic_len;
+			} else {
+			}
+		} else if (hc->xfer_len > max_hc_xfer_size) {
+			/* Make sure that xfer_len is a multiple of max packet size. */
+			hc->xfer_len = max_hc_xfer_size - hc->max_packet + 1;
+		}
+
+		if (hc->xfer_len > 0) {
+			num_packets =
+			    (hc->xfer_len + hc->max_packet -
+			     1) / hc->max_packet;
+			if (num_packets > max_hc_pkt_count) {
+				num_packets = max_hc_pkt_count;
+				hc->xfer_len = num_packets * hc->max_packet;
+			}
+		} else {
+			/* Need 1 packet for transfer length of 0. */
+			num_packets = 1;
+		}
+
+		if (hc->ep_is_in) {
+			/* Always program an integral # of max packets for IN transfers. */
+			hc->xfer_len = num_packets * hc->max_packet;
+		}
+
+		if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
+		    hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
+			/*
+			 * Make sure that the multi_count field matches the
+			 * actual transfer length.
+			 */
+			hc->multi_count = num_packets;
+		}
+
+		if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
+			set_pid_isoc(hc);
+
+		hctsiz.b.xfersize = hc->xfer_len;
+	}
+
+	hc->start_pkt_count = num_packets;
+	hctsiz.b.pktcnt = num_packets;
+	hctsiz.b.pid = hc->data_pid_start;
+	dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
+
+	DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
+	DWC_DEBUGPL(DBG_HCDV, "	 Xfer Size: %d\n", hctsiz.b.xfersize);
+	DWC_DEBUGPL(DBG_HCDV, "	 Num Pkts: %d\n", hctsiz.b.pktcnt);
+	DWC_DEBUGPL(DBG_HCDV, "	 Start PID: %d\n", hctsiz.b.pid);
+
+	if (core_if->dma_enable) {
+		dwc_dma_t dma_addr;
+		if (hc->align_buff) {
+			dma_addr = hc->align_buff;
+		} else {
+			dma_addr = (uint32_t)hc->xfer_buff;
+		}
+		dwc_write_reg32(&hc_regs->hcdma, dma_addr);
+	}
+
+	/* Start the split */
+	if (hc->do_split) {
+		hcsplt_data_t hcsplt;
+		hcsplt.d32 = dwc_read_reg32(&hc_regs->hcsplt);
+		hcsplt.b.spltena = 1;
+		dwc_write_reg32(&hc_regs->hcsplt, hcsplt.d32);
+	}
+
+	hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+	hcchar.b.multicnt = hc->multi_count;
+	hc_set_even_odd_frame(core_if, hc, &hcchar);
+#ifdef DEBUG
+	core_if->start_hcchar_val[hc->hc_num] = hcchar.d32;
+	if (hcchar.b.chdis) {
+		DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n",
+			 __func__, hc->hc_num, hcchar.d32);
+	}
+#endif
+
+	/* Set host channel enable after all other setup is complete. */
+	hcchar.b.chen = 1;
+	hcchar.b.chdis = 0;
+	dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
+
+	hc->xfer_started = 1;
+	hc->requests++;
+
+	if (!core_if->dma_enable && !hc->ep_is_in && hc->xfer_len > 0) {
+		/* Load OUT packet into the appropriate Tx FIFO. */
+		dwc_otg_hc_write_packet(core_if, hc);
+	}
+#ifdef DEBUG
+	if (hc->ep_type != DWC_OTG_EP_TYPE_INTR) {
+                DWC_DEBUGPL(DBG_HCDV, "transfer %d from core_if %p\n",
+                            hc->hc_num, core_if);//GRAYG
+		core_if->hc_xfer_info[hc->hc_num].core_if = core_if;
+		core_if->hc_xfer_info[hc->hc_num].hc = hc;
+		/* Start a timer for this transfer. */
+		DWC_TIMER_SCHEDULE(core_if->hc_xfer_timer[hc->hc_num], 10000);
+	}
+#endif
+}
+
+/**
+ * This function does the setup for a data transfer for a host channel 
+ * and starts the transfer in Descriptor DMA mode.
+ *
+ * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set.
+ * Sets PID and NTD values. For periodic transfers
+ * initializes SCHED_INFO field with micro-frame bitmap.
+ *
+ * Initializes HCDMA register with descriptor list address and CTD value
+ * then starts the transfer via enabling the channel.
+ *
+ * @param core_if Programming view of DWC_otg controller.
+ * @param hc Information needed to initialize the host channel.
+ */
+void dwc_otg_hc_start_transfer_ddma(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
+{
+	dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];	
+	hcchar_data_t hcchar;
+	hctsiz_data_t hctsiz;
+	hcdma_data_t  hcdma;
+	
+	hctsiz.d32 = 0;
+
+	if (hc->do_ping && !hc->ep_is_in)
+		hctsiz.b_ddma.dopng = 1;
+
+	if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
+		set_pid_isoc(hc);
+	
+	/* Packet Count and Xfer Size are not used in Descriptor DMA mode */
+	hctsiz.b_ddma.pid = hc->data_pid_start;
+	hctsiz.b_ddma.ntd = hc->ntd - 1; /* 0 - 1 descriptor, 1 - 2 descriptors, etc. */
+	hctsiz.b_ddma.schinfo = hc->schinfo; /* Non-zero only for high-speed interrupt endpoints */
+	
+	DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
+	DWC_DEBUGPL(DBG_HCDV, "	 Start PID: %d\n", hctsiz.b.pid);
+	DWC_DEBUGPL(DBG_HCDV, "	 NTD: %d\n", hctsiz.b_ddma.ntd);	
+
+	dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
+
+	hcdma.d32 = 0;
+	hcdma.b.dma_addr = ((uint32_t)hc->desc_list_addr) >> 11;
+		
+	/* Always start from first descriptor. */
+	hcdma.b.ctd = 0;
+	dwc_write_reg32(&hc_regs->hcdma, hcdma.d32);
+
+	hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+	hcchar.b.multicnt = hc->multi_count;
+	
+#ifdef DEBUG
+	core_if->start_hcchar_val[hc->hc_num] = hcchar.d32;
+	if (hcchar.b.chdis) {
+		DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n",
+			 __func__, hc->hc_num, hcchar.d32);
+	}
+#endif
+
+	/* Set host channel enable after all other setup is complete. */
+	hcchar.b.chen = 1;
+	hcchar.b.chdis = 0;
+	
+	dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
+
+	hc->xfer_started = 1;
+	hc->requests++;
+	
+#ifdef DEBUG
+	if ((hc->ep_type != DWC_OTG_EP_TYPE_INTR) && (hc->ep_type != DWC_OTG_EP_TYPE_ISOC)) {
+                DWC_DEBUGPL(DBG_HCDV, "DMA transfer %d from core_if %p\n",
+                            hc->hc_num, core_if);//GRAYG
+		core_if->hc_xfer_info[hc->hc_num].core_if = core_if;
+		core_if->hc_xfer_info[hc->hc_num].hc = hc;
+		/* Start a timer for this transfer. */
+		DWC_TIMER_SCHEDULE(core_if->hc_xfer_timer[hc->hc_num], 10000);
+	}
+
+#endif
+	
+}
+	
+/**
+ * This function continues a data transfer that was started by previous call
+ * to <code>dwc_otg_hc_start_transfer</code>. The caller must ensure there is
+ * sufficient space in the request queue and Tx Data FIFO. This function
+ * should only be called in Slave mode. In DMA mode, the controller acts
+ * autonomously to complete transfers programmed to a host channel.
+ *
+ * For an OUT transfer, a new data packet is loaded into the appropriate FIFO
+ * if there is any data remaining to be queued. For an IN transfer, another
+ * data packet is always requested. For the SETUP phase of a control transfer,
+ * this function does nothing.
+ *
+ * @return 1 if a new request is queued, 0 if no more requests are required
+ * for this transfer.
+ */
+int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
+{
+	DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
+
+	if (hc->do_split) {
+		/* SPLITs always queue just once per channel */
+		return 0;
+	} else if (hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
+		/* SETUPs are queued only once since they can't be NAKed. */
+		return 0;
+	} else if (hc->ep_is_in) {
+		/*
+		 * Always queue another request for other IN transfers. If
+		 * back-to-back INs are issued and NAKs are received for both,
+		 * the driver may still be processing the first NAK when the
+		 * second NAK is received. When the interrupt handler clears
+		 * the NAK interrupt for the first NAK, the second NAK will
+		 * not be seen. So we can't depend on the NAK interrupt
+		 * handler to requeue a NAKed request. Instead, IN requests
+		 * are issued each time this function is called. When the
+		 * transfer completes, the extra requests for the channel will
+		 * be flushed.
+		 */
+		hcchar_data_t hcchar;
+		dwc_otg_hc_regs_t *hc_regs =
+		    core_if->host_if->hc_regs[hc->hc_num];
+
+		hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+		hc_set_even_odd_frame(core_if, hc, &hcchar);
+		hcchar.b.chen = 1;
+		hcchar.b.chdis = 0;
+		DWC_DEBUGPL(DBG_HCDV, "	 IN xfer: hcchar = 0x%08x\n",
+			    hcchar.d32);
+		dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
+		hc->requests++;
+		return 1;
+	} else {
+		/* OUT transfers. */
+		if (hc->xfer_count < hc->xfer_len) {
+			if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
+			    hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
+				hcchar_data_t hcchar;
+				dwc_otg_hc_regs_t *hc_regs;
+				hc_regs = core_if->host_if->hc_regs[hc->hc_num];
+				hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+				hc_set_even_odd_frame(core_if, hc, &hcchar);
+			}
+
+			/* Load OUT packet into the appropriate Tx FIFO. */
+			dwc_otg_hc_write_packet(core_if, hc);
+			hc->requests++;
+			return 1;
+		} else {
+			return 0;
+		}
+	}
+}
+
+/**
+ * Starts a PING transfer. This function should only be called in Slave mode.
+ * The Do Ping bit is set in the HCTSIZ register, then the channel is enabled.
+ */
+void dwc_otg_hc_do_ping(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
+{
+	hcchar_data_t hcchar;
+	hctsiz_data_t hctsiz;
+	dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
+
+	DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
+
+	hctsiz.d32 = 0;
+	hctsiz.b.dopng = 1;
+	hctsiz.b.pktcnt = 1;
+	dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
+
+	hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+	hcchar.b.chen = 1;
+	hcchar.b.chdis = 0;
+	dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
+}
+
+/*
+ * This function writes a packet into the Tx FIFO associated with the Host
+ * Channel. For a channel associated with a non-periodic EP, the non-periodic
+ * Tx FIFO is written. For a channel associated with a periodic EP, the
+ * periodic Tx FIFO is written. This function should only be called in Slave
+ * mode.
+ *
+ * Upon return the xfer_buff and xfer_count fields in _hc are incremented by
+ * then number of bytes written to the Tx FIFO.
+ */
+void dwc_otg_hc_write_packet(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
+{
+	uint32_t i;
+	uint32_t remaining_count;
+	uint32_t byte_count;
+	uint32_t dword_count;
+
+	uint32_t *data_buff = (uint32_t *) (hc->xfer_buff);
+	uint32_t *data_fifo = core_if->data_fifo[hc->hc_num];
+
+	remaining_count = hc->xfer_len - hc->xfer_count;
+	if (remaining_count > hc->max_packet) {
+		byte_count = hc->max_packet;
+	} else {
+		byte_count = remaining_count;
+	}
+
+	dword_count = (byte_count + 3) / 4;
+
+	if ((((unsigned long)data_buff) & 0x3) == 0) {
+		/* xfer_buff is DWORD aligned. */
+		for (i = 0; i < dword_count; i++, data_buff++) {
+			dwc_write_reg32(data_fifo, *data_buff);
+		}
+	} else {
+		/* xfer_buff is not DWORD aligned. */
+		for (i = 0; i < dword_count; i++, data_buff++) {
+			uint32_t data;
+			data =
+			    (data_buff[0] | data_buff[1] << 8 | data_buff[2] <<
+			     16 | data_buff[3] << 24);
+			dwc_write_reg32(data_fifo, data);
+		}
+	}
+
+	hc->xfer_count += byte_count;
+	hc->xfer_buff += byte_count;
+}
+
+/**
+ * Gets the current USB frame number. This is the frame number from the last 
+ * SOF packet.	
+ */
+uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t * core_if)
+{
+	dsts_data_t dsts;
+	dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
+
+	/* read current frame/microframe number from DSTS register */
+	return dsts.b.soffn;
+}
+
+/**
+ * This function reads a setup packet from the Rx FIFO into the destination 
+ * buffer.	This function is called from the Rx Status Queue Level (RxStsQLvl)
+ * Interrupt routine when a SETUP packet has been received in Slave mode.
+ *
+ * @param core_if Programming view of DWC_otg controller.
+ * @param dest Destination buffer for packet data.
+ */
+void dwc_otg_read_setup_packet(dwc_otg_core_if_t * core_if, uint32_t * dest)
+{
+	/* Get the 8 bytes of a setup transaction data */
+
+	/* Pop 2 DWORDS off the receive data FIFO into memory */
+	dest[0] = dwc_read_reg32(core_if->data_fifo[0]);
+	dest[1] = dwc_read_reg32(core_if->data_fifo[0]);
+}
+
+/**
+ * This function enables EP0 OUT to receive SETUP packets and configures EP0 
+ * IN for transmitting packets.	 It is normally called when the
+ * "Enumeration Done" interrupt occurs.
+ *
+ * @param core_if Programming view of DWC_otg controller.
+ * @param ep The EP0 data.
+ */
+void dwc_otg_ep0_activate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
+{
+	dwc_otg_dev_if_t *dev_if = core_if->dev_if;
+	dsts_data_t dsts;
+	depctl_data_t diepctl;
+	depctl_data_t doepctl;
+	dctl_data_t dctl = {.d32 = 0 };
+
+	/* Read the Device Status and Endpoint 0 Control registers */
+	dsts.d32 = dwc_read_reg32(&dev_if->dev_global_regs->dsts);
+	diepctl.d32 = dwc_read_reg32(&dev_if->in_ep_regs[0]->diepctl);
+	doepctl.d32 = dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl);
+
+	/* Set the MPS of the IN EP based on the enumeration speed */
+	switch (dsts.b.enumspd) {
+	case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
+	case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
+	case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ:
+		diepctl.b.mps = DWC_DEP0CTL_MPS_64;
+		break;
+	case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ:
+		diepctl.b.mps = DWC_DEP0CTL_MPS_8;
+		break;
+	}
+
+	dwc_write_reg32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32);
+
+	/* Enable OUT EP for receive */
+	doepctl.b.epena = 1;
+	dwc_write_reg32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32);
+
+#ifdef VERBOSE
+	DWC_DEBUGPL(DBG_PCDV, "doepctl0=%0x\n",
+		    dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl));
+	DWC_DEBUGPL(DBG_PCDV, "diepctl0=%0x\n",
+		    dwc_read_reg32(&dev_if->in_ep_regs[0]->diepctl));
+#endif
+	dctl.b.cgnpinnak = 1;
+
+	dwc_modify_reg32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
+	DWC_DEBUGPL(DBG_PCDV, "dctl=%0x\n",
+		    dwc_read_reg32(&dev_if->dev_global_regs->dctl));
+}
+
+/**
+ * This function activates an EP.  The Device EP control register for
+ * the EP is configured as defined in the ep structure.	 Note: This
+ * function is not used for EP0.
+ *
+ * @param core_if Programming view of DWC_otg controller.
+ * @param ep The EP to activate.
+ */
+void dwc_otg_ep_activate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
+{
+	dwc_otg_dev_if_t *dev_if = core_if->dev_if;
+	depctl_data_t depctl;
+	volatile uint32_t *addr;
+	daint_data_t daintmsk = {.d32 = 0 };
+
+	DWC_DEBUGPL(DBG_PCDV, "%s() EP%d-%s\n", __func__, ep->num,
+		    (ep->is_in ? "IN" : "OUT"));
+
+	/* Read DEPCTLn register */
+	if (ep->is_in == 1) {
+		addr = &dev_if->in_ep_regs[ep->num]->diepctl;
+		daintmsk.ep.in = 1 << ep->num;
+	} else {
+		addr = &dev_if->out_ep_regs[ep->num]->doepctl;
+		daintmsk.ep.out = 1 << ep->num;
+	}
+
+	/* If the EP is already active don't change the EP Control
+	 * register. */
+	depctl.d32 = dwc_read_reg32(addr);
+	if (!depctl.b.usbactep) {
+		depctl.b.mps = ep->maxpacket;
+		depctl.b.eptype = ep->type;
+		depctl.b.txfnum = ep->tx_fifo_num;
+
+		if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
+			depctl.b.setd0pid = 1;	// ??? 
+		} else {
+			depctl.b.setd0pid = 1;
+		}
+		depctl.b.usbactep = 1;
+
+		dwc_write_reg32(addr, depctl.d32);
+		DWC_DEBUGPL(DBG_PCDV, "DEPCTL=%08x\n", dwc_read_reg32(addr));
+	}
+
+	/* Enable the Interrupt for this EP */
+	if (core_if->multiproc_int_enable) {
+		if (ep->is_in == 1) {
+			diepmsk_data_t diepmsk = {.d32 = 0 };
+			diepmsk.b.xfercompl = 1;
+			diepmsk.b.timeout = 1;
+			diepmsk.b.epdisabled = 1;
+			diepmsk.b.ahberr = 1;
+			diepmsk.b.intknepmis = 1;
+			diepmsk.b.txfifoundrn = 1;	//?????
+
+			if (core_if->dma_desc_enable) {
+				diepmsk.b.bna = 1;
+			}
+/*			
+			if(core_if->dma_enable) {
+				doepmsk.b.nak = 1;
+			}
+*/
+			dwc_write_reg32(&dev_if->dev_global_regs->
+					diepeachintmsk[ep->num], diepmsk.d32);
+
+		} else {
+			doepmsk_data_t doepmsk = {.d32 = 0 };
+			doepmsk.b.xfercompl = 1;
+			doepmsk.b.ahberr = 1;
+			doepmsk.b.epdisabled = 1;
+
+			if (core_if->dma_desc_enable) {
+				doepmsk.b.bna = 1;
+			}
+/*			
+			doepmsk.b.babble = 1;
+			doepmsk.b.nyet = 1;
+			doepmsk.b.nak = 1;
+*/
+			dwc_write_reg32(&dev_if->dev_global_regs->
+					doepeachintmsk[ep->num], doepmsk.d32);
+		}
+		dwc_modify_reg32(&dev_if->dev_global_regs->deachintmsk,
+				 0, daintmsk.d32);
+	} else {
+		dwc_modify_reg32(&dev_if->dev_global_regs->daintmsk,
+				 0, daintmsk.d32);
+	}
+
+	DWC_DEBUGPL(DBG_PCDV, "DAINTMSK=%0x\n",
+		    dwc_read_reg32(&dev_if->dev_global_regs->daintmsk));
+
+	ep->stall_clear_flag = 0;
+	return;
+}
+
+/**
+ * This function deactivates an EP. This is done by clearing the USB Active 
+ * EP bit in the Device EP control register. Note: This function is not used 
+ * for EP0. EP0 cannot be deactivated.
+ *
+ * @param core_if Programming view of DWC_otg controller.
+ * @param ep The EP to deactivate.
+ */
+void dwc_otg_ep_deactivate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
+{
+	depctl_data_t depctl = {.d32 = 0 };
+	volatile uint32_t *addr;
+	daint_data_t daintmsk = {.d32 = 0 };
+
+	/* Read DEPCTLn register */
+	if (ep->is_in == 1) {
+		addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
+		daintmsk.ep.in = 1 << ep->num;
+	} else {
+		addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
+		daintmsk.ep.out = 1 << ep->num;
+	}
+
+	depctl.d32 = dwc_read_reg32(addr);
+
+	depctl.b.usbactep = 0;
+
+	if (core_if->dma_desc_enable)
+		depctl.b.epdis = 1;
+
+	dwc_write_reg32(addr, depctl.d32);
+
+	/* Disable the Interrupt for this EP */
+	if (core_if->multiproc_int_enable) {
+		dwc_modify_reg32(&core_if->dev_if->dev_global_regs->deachintmsk,
+				 daintmsk.d32, 0);
+
+		if (ep->is_in == 1) {
+			dwc_write_reg32(&core_if->dev_if->dev_global_regs->
+					diepeachintmsk[ep->num], 0);
+		} else {
+			dwc_write_reg32(&core_if->dev_if->dev_global_regs->
+					doepeachintmsk[ep->num], 0);
+		}
+	} else {
+		dwc_modify_reg32(&core_if->dev_if->dev_global_regs->daintmsk,
+				 daintmsk.d32, 0);
+	}
+}
+
+/**
+ * This function initializes dma descriptor chain.
+ *
+ * @param core_if Programming view of DWC_otg controller.
+ * @param ep The EP to start the transfer on.
+ */
+static void init_dma_desc_chain(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
+{
+	dwc_otg_dev_dma_desc_t *dma_desc;
+	uint32_t offset;
+	uint32_t xfer_est;
+	int i;
+
+	ep->desc_cnt = (ep->total_len / ep->maxxfer) +
+	    ((ep->total_len % ep->maxxfer) ? 1 : 0);
+	if (!ep->desc_cnt)
+		ep->desc_cnt = 1;
+
+	dma_desc = ep->desc_addr;
+	xfer_est = ep->total_len;
+	offset = 0;
+	for (i = 0; i < ep->desc_cnt; ++i) {
+		/** DMA Descriptor Setup */
+		if (xfer_est > ep->maxxfer) {
+			dma_desc->status.b.bs = BS_HOST_BUSY;
+			dma_desc->status.b.l = 0;
+			dma_desc->status.b.ioc = 0;
+			dma_desc->status.b.sp = 0;
+			dma_desc->status.b.bytes = ep->maxxfer;
+			dma_desc->buf = ep->dma_addr + offset;
+			dma_desc->status.b.bs = BS_HOST_READY;
+
+			xfer_est -= ep->maxxfer;
+			offset += ep->maxxfer;
+		} else {
+			dma_desc->status.b.bs = BS_HOST_BUSY;
+			dma_desc->status.b.l = 1;
+			dma_desc->status.b.ioc = 1;
+			if (ep->is_in) {
+				dma_desc->status.b.sp =
+				    (xfer_est %
+				     ep->maxpacket) ? 1 : ((ep->
+							    sent_zlp) ? 1 : 0);
+				dma_desc->status.b.bytes = xfer_est;
+			} else {
+				dma_desc->status.b.bytes =
+				    xfer_est + ((4 - (xfer_est & 0x3)) & 0x3);
+			}
+
+			dma_desc->buf = ep->dma_addr + offset;
+			dma_desc->status.b.bs = BS_HOST_READY;
+		}
+		dma_desc++;
+	}
+}
+
+/**
+ * This function does the setup for a data transfer for an EP and
+ * starts the transfer.	 For an IN transfer, the packets will be
+ * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers,
+ * the packets are unloaded from the Rx FIFO in the ISR.  the ISR.
+ *
+ * @param core_if Programming view of DWC_otg controller.
+ * @param ep The EP to start the transfer on.
+ */
+
+void dwc_otg_ep_start_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
+{
+	depctl_data_t depctl;
+	deptsiz_data_t deptsiz;
+	gintmsk_data_t intr_mask = {.d32 = 0 };
+
+	DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__);
+	DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d "
+		    "xfer_buff=%p start_xfer_buff=%p, total_len = %d\n",
+		    ep->num, (ep->is_in ? "IN" : "OUT"), ep->xfer_len,
+		    ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff,
+		    ep->total_len);
+	/* IN endpoint */
+	if (ep->is_in == 1) {
+		dwc_otg_dev_in_ep_regs_t *in_regs =
+		    core_if->dev_if->in_ep_regs[ep->num];
+
+		gnptxsts_data_t gtxstatus;
+
+		gtxstatus.d32 =
+		    dwc_read_reg32(&core_if->core_global_regs->gnptxsts);
+
+		if (core_if->en_multiple_tx_fifo == 0
+		    && gtxstatus.b.nptxqspcavail == 0) {
+#ifdef DEBUG
+			DWC_PRINTF("TX Queue Full (0x%0x)\n", gtxstatus.d32);
+#endif
+			return;
+		}
+
+		depctl.d32 = dwc_read_reg32(&(in_regs->diepctl));
+		deptsiz.d32 = dwc_read_reg32(&(in_regs->dieptsiz));
+
+		ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ?
+		    ep->maxxfer : (ep->total_len - ep->xfer_len);
+
+		/* Zero Length Packet? */
+		if ((ep->xfer_len - ep->xfer_count) == 0) {
+			deptsiz.b.xfersize = 0;
+			deptsiz.b.pktcnt = 1;
+		} else {
+			/* Program the transfer size and packet count
+			 *      as follows: xfersize = N * maxpacket +
+			 *      short_packet pktcnt = N + (short_packet
+			 *      exist ? 1 : 0)  
+			 */
+			deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count;
+			deptsiz.b.pktcnt =
+			    (ep->xfer_len - ep->xfer_count - 1 +
+			     ep->maxpacket) / ep->maxpacket;
+		}
+
+		/* Write the DMA register */
+		if (core_if->dma_enable) {
+			if (core_if->dma_desc_enable == 0) {
+				dwc_write_reg32(&in_regs->dieptsiz,
+						deptsiz.d32);
+				dwc_write_reg32(&(in_regs->diepdma),
+						(uint32_t) ep->dma_addr);
+			} else {
+#ifdef DWC_UTE_CFI
+				/* The descriptor chain should be already initialized by now */
+				if (ep->buff_mode != BM_STANDARD) {
+					dwc_write_reg32(&in_regs->diepdma,
+							ep->descs_dma_addr);
+				} else {
+#endif
+				init_dma_desc_chain(core_if, ep);
+				/** DIEPDMAn Register write */
+				dwc_write_reg32(&in_regs->diepdma,
+						ep->dma_desc_addr);
+#ifdef DWC_UTE_CFI
+			}
+#endif
+			}
+		} else {
+			dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
+			if (ep->type != DWC_OTG_EP_TYPE_ISOC) {
+				/** 
+				 * Enable the Non-Periodic Tx FIFO empty interrupt,
+				 * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode,
+				 * the data will be written into the fifo by the ISR.
+				 */
+				if (core_if->en_multiple_tx_fifo == 0) {
+					intr_mask.b.nptxfempty = 1;
+					dwc_modify_reg32(&core_if->
+							 core_global_regs->
+							 gintmsk, intr_mask.d32,
+							 intr_mask.d32);
+				} else {
+					/* Enable the Tx FIFO Empty Interrupt for this EP */
+					if (ep->xfer_len > 0) {
+						uint32_t fifoemptymsk = 0;
+						fifoemptymsk = 1 << ep->num;
+						dwc_modify_reg32(&core_if->
+								 dev_if->
+								 dev_global_regs->
+								 dtknqr4_fifoemptymsk,
+								 0,
+								 fifoemptymsk);
+
+					}
+				}
+			}
+		}
+
+		/* EP enable, IN data in FIFO */
+		depctl.b.cnak = 1;
+		depctl.b.epena = 1;
+		dwc_write_reg32(&in_regs->diepctl, depctl.d32);
+
+		depctl.d32 =
+		    dwc_read_reg32(&core_if->dev_if->in_ep_regs[0]->diepctl);
+		depctl.b.nextep = ep->num;
+		dwc_write_reg32(&core_if->dev_if->in_ep_regs[0]->diepctl,
+				depctl.d32);
+
+	} else {
+		/* OUT endpoint */
+		dwc_otg_dev_out_ep_regs_t *out_regs =
+		    core_if->dev_if->out_ep_regs[ep->num];
+
+		depctl.d32 = dwc_read_reg32(&(out_regs->doepctl));
+		deptsiz.d32 = dwc_read_reg32(&(out_regs->doeptsiz));
+
+		ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ?
+		    ep->maxxfer : (ep->total_len - ep->xfer_len);
+
+		/* Program the transfer size and packet count as follows:
+		 * 
+		 *      pktcnt = N                                                                                 
+		 *      xfersize = N * maxpacket
+		 */
+		if ((ep->xfer_len - ep->xfer_count) == 0) {
+			/* Zero Length Packet */
+			deptsiz.b.xfersize = ep->maxpacket;
+			deptsiz.b.pktcnt = 1;
+		} else {
+			deptsiz.b.pktcnt =
+			    (ep->xfer_len - ep->xfer_count +
+			     (ep->maxpacket - 1)) / ep->maxpacket;
+			ep->xfer_len =
+			    deptsiz.b.pktcnt * ep->maxpacket + ep->xfer_count;
+			deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count;
+		}
+
+		DWC_DEBUGPL(DBG_PCDV, "ep%d xfersize=%d pktcnt=%d\n",
+			    ep->num, deptsiz.b.xfersize, deptsiz.b.pktcnt);
+
+		if (core_if->dma_enable) {
+			if (!core_if->dma_desc_enable) {
+				dwc_write_reg32(&out_regs->doeptsiz,
+						deptsiz.d32);
+
+				dwc_write_reg32(&(out_regs->doepdma),
+						(uint32_t) ep->dma_addr);
+			} else {
+#ifdef DWC_UTE_CFI
+				/* The descriptor chain should be already initialized by now */
+				if (ep->buff_mode != BM_STANDARD) {
+					dwc_write_reg32(&out_regs->doepdma,
+							ep->descs_dma_addr);
+				} else {
+#endif
+
+				init_dma_desc_chain(core_if, ep);
+
+				/** DOEPDMAn Register write */
+				dwc_write_reg32(&out_regs->doepdma,
+						ep->dma_desc_addr);
+#ifdef DWC_UTE_CFI
+				}
+#endif
+			}
+		} else {
+			dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
+		}
+
+		/* EP enable */
+		depctl.b.cnak = 1;
+		depctl.b.epena = 1;
+
+		dwc_write_reg32(&out_regs->doepctl, depctl.d32);
+
+		DWC_DEBUGPL(DBG_PCD, "DOEPCTL=%08x DOEPTSIZ=%08x\n",
+			    dwc_read_reg32(&out_regs->doepctl),
+			    dwc_read_reg32(&out_regs->doeptsiz));
+		DWC_DEBUGPL(DBG_PCD, "DAINTMSK=%08x GINTMSK=%08x\n",
+			    dwc_read_reg32(&core_if->dev_if->dev_global_regs->
+					   daintmsk),
+			    dwc_read_reg32(&core_if->core_global_regs->
+					   gintmsk));
+	}
+}
+
+/**
+ * This function setup a zero length transfer in Buffer DMA and
+ * Slave modes for usb requests with zero field set
+ *
+ * @param core_if Programming view of DWC_otg controller.
+ * @param ep The EP to start the transfer on.
+ *
+ */
+void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
+{
+
+	depctl_data_t depctl;
+	deptsiz_data_t deptsiz;
+	gintmsk_data_t intr_mask = {.d32 = 0 };
+
+	DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__);
+	DWC_PRINTF("zero length transfer is called\n");
+
+	/* IN endpoint */
+	if (ep->is_in == 1) {
+		dwc_otg_dev_in_ep_regs_t *in_regs =
+		    core_if->dev_if->in_ep_regs[ep->num];
+
+		depctl.d32 = dwc_read_reg32(&(in_regs->diepctl));
+		deptsiz.d32 = dwc_read_reg32(&(in_regs->dieptsiz));
+
+		deptsiz.b.xfersize = 0;
+		deptsiz.b.pktcnt = 1;
+
+		/* Write the DMA register */
+		if (core_if->dma_enable) {
+			if (core_if->dma_desc_enable == 0) {
+				dwc_write_reg32(&in_regs->dieptsiz,
+						deptsiz.d32);
+				dwc_write_reg32(&(in_regs->diepdma),
+						(uint32_t) ep->dma_addr);
+			}
+		} else {
+			dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
+			/** 
+			 * Enable the Non-Periodic Tx FIFO empty interrupt,
+			 * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode,
+			 * the data will be written into the fifo by the ISR.
+			 */
+			if (core_if->en_multiple_tx_fifo == 0) {
+				intr_mask.b.nptxfempty = 1;
+				dwc_modify_reg32(&core_if->core_global_regs->
+						 gintmsk, intr_mask.d32,
+						 intr_mask.d32);
+			} else {
+				/* Enable the Tx FIFO Empty Interrupt for this EP */
+				if (ep->xfer_len > 0) {
+					uint32_t fifoemptymsk = 0;
+					fifoemptymsk = 1 << ep->num;
+					dwc_modify_reg32(&core_if->dev_if->
+							 dev_global_regs->
+							 dtknqr4_fifoemptymsk,
+							 0, fifoemptymsk);
+				}
+			}
+		}
+
+		/* EP enable, IN data in FIFO */
+		depctl.b.cnak = 1;
+		depctl.b.epena = 1;
+		dwc_write_reg32(&in_regs->diepctl, depctl.d32);
+
+		depctl.d32 =
+		    dwc_read_reg32(&core_if->dev_if->in_ep_regs[0]->diepctl);
+		depctl.b.nextep = ep->num;
+		dwc_write_reg32(&core_if->dev_if->in_ep_regs[0]->diepctl,
+				depctl.d32);
+
+	} else {
+		/* OUT endpoint */
+		dwc_otg_dev_out_ep_regs_t *out_regs =
+		    core_if->dev_if->out_ep_regs[ep->num];
+
+		depctl.d32 = dwc_read_reg32(&(out_regs->doepctl));
+		deptsiz.d32 = dwc_read_reg32(&(out_regs->doeptsiz));
+
+		/* Zero Length Packet */
+		deptsiz.b.xfersize = ep->maxpacket;
+		deptsiz.b.pktcnt = 1;
+
+		if (core_if->dma_enable) {
+			if (!core_if->dma_desc_enable) {
+				dwc_write_reg32(&out_regs->doeptsiz,
+						deptsiz.d32);
+
+				dwc_write_reg32(&(out_regs->doepdma),
+						(uint32_t) ep->dma_addr);
+			}
+		} else {
+			dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
+		}
+
+		/* EP enable */
+		depctl.b.cnak = 1;
+		depctl.b.epena = 1;
+
+		dwc_write_reg32(&out_regs->doepctl, depctl.d32);
+
+	}
+}
+
+/**
+ * This function does the setup for a data transfer for EP0 and starts
+ * the transfer.  For an IN transfer, the packets will be loaded into
+ * the appropriate Tx FIFO in the ISR. For OUT transfers, the packets are
+ * unloaded from the Rx FIFO in the ISR.
+ *
+ * @param core_if Programming view of DWC_otg controller.
+ * @param ep The EP0 data.
+ */
+void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
+{
+	depctl_data_t depctl;
+	deptsiz0_data_t deptsiz;
+	gintmsk_data_t intr_mask = {.d32 = 0 };
+	dwc_otg_dev_dma_desc_t *dma_desc;
+
+	DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d "
+		    "xfer_buff=%p start_xfer_buff=%p \n",
+		    ep->num, (ep->is_in ? "IN" : "OUT"), ep->xfer_len,
+		    ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff);
+
+	ep->total_len = ep->xfer_len;
+
+	/* IN endpoint */
+	if (ep->is_in == 1) {
+		dwc_otg_dev_in_ep_regs_t *in_regs =
+		    core_if->dev_if->in_ep_regs[0];
+
+		gnptxsts_data_t gtxstatus;
+
+		gtxstatus.d32 =
+		    dwc_read_reg32(&core_if->core_global_regs->gnptxsts);
+
+		if (core_if->en_multiple_tx_fifo == 0
+		    && gtxstatus.b.nptxqspcavail == 0) {
+#ifdef DEBUG
+			deptsiz.d32 = dwc_read_reg32(&in_regs->dieptsiz);
+			DWC_DEBUGPL(DBG_PCD, "DIEPCTL0=%0x\n",
+				    dwc_read_reg32(&in_regs->diepctl));
+			DWC_DEBUGPL(DBG_PCD, "DIEPTSIZ0=%0x (sz=%d, pcnt=%d)\n",
+				    deptsiz.d32,
+				    deptsiz.b.xfersize, deptsiz.b.pktcnt);
+			DWC_PRINTF("TX Queue or FIFO Full (0x%0x)\n",
+				   gtxstatus.d32);
+#endif
+			return;
+		}
+
+		depctl.d32 = dwc_read_reg32(&in_regs->diepctl);
+		deptsiz.d32 = dwc_read_reg32(&in_regs->dieptsiz);
+
+		/* Zero Length Packet? */
+		if (ep->xfer_len == 0) {
+			deptsiz.b.xfersize = 0;
+			deptsiz.b.pktcnt = 1;
+		} else {
+			/* Program the transfer size and packet count
+			 *      as follows: xfersize = N * maxpacket +
+			 *      short_packet pktcnt = N + (short_packet
+			 *      exist ? 1 : 0)  
+			 */
+			if (ep->xfer_len > ep->maxpacket) {
+				ep->xfer_len = ep->maxpacket;
+				deptsiz.b.xfersize = ep->maxpacket;
+			} else {
+				deptsiz.b.xfersize = ep->xfer_len;
+			}
+			deptsiz.b.pktcnt = 1;
+
+		}
+		DWC_DEBUGPL(DBG_PCDV,
+			    "IN len=%d  xfersize=%d pktcnt=%d [%08x]\n",
+			    ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt,
+			    deptsiz.d32);
+
+		/* Write the DMA register */
+		if (core_if->dma_enable) {
+			if (core_if->dma_desc_enable == 0) {
+				dwc_write_reg32(&in_regs->dieptsiz,
+						deptsiz.d32);
+
+				dwc_write_reg32(&(in_regs->diepdma),
+						(uint32_t) ep->dma_addr);
+			} else {
+				dma_desc = core_if->dev_if->in_desc_addr;
+
+				/** DMA Descriptor Setup */
+				dma_desc->status.b.bs = BS_HOST_BUSY;
+				dma_desc->status.b.l = 1;
+				dma_desc->status.b.ioc = 1;
+				dma_desc->status.b.sp =
+				    (ep->xfer_len == ep->maxpacket) ? 0 : 1;
+				dma_desc->status.b.bytes = ep->xfer_len;
+				dma_desc->buf = ep->dma_addr;
+				dma_desc->status.b.bs = BS_HOST_READY;
+
+				/** DIEPDMA0 Register write */
+				dwc_write_reg32(&in_regs->diepdma,
+						core_if->dev_if->
+						dma_in_desc_addr);
+			}
+		} else {
+			dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
+		}
+
+		/* EP enable, IN data in FIFO */
+		depctl.b.cnak = 1;
+		depctl.b.epena = 1;
+		dwc_write_reg32(&in_regs->diepctl, depctl.d32);
+
+		/** 
+		 * Enable the Non-Periodic Tx FIFO empty interrupt, the
+		 * data will be written into the fifo by the ISR.
+		 */
+		if (!core_if->dma_enable) {
+			if (core_if->en_multiple_tx_fifo == 0) {
+				intr_mask.b.nptxfempty = 1;
+				dwc_modify_reg32(&core_if->core_global_regs->
+						 gintmsk, intr_mask.d32,
+						 intr_mask.d32);
+			} else {
+				/* Enable the Tx FIFO Empty Interrupt for this EP */
+				if (ep->xfer_len > 0) {
+					uint32_t fifoemptymsk = 0;
+					fifoemptymsk |= 1 << ep->num;
+					dwc_modify_reg32(&core_if->dev_if->
+							 dev_global_regs->
+							 dtknqr4_fifoemptymsk,
+							 0, fifoemptymsk);
+				}
+			}
+		}
+	} else {
+		/* OUT endpoint */
+		dwc_otg_dev_out_ep_regs_t *out_regs =
+		    core_if->dev_if->out_ep_regs[0];
+
+		depctl.d32 = dwc_read_reg32(&out_regs->doepctl);
+		deptsiz.d32 = dwc_read_reg32(&out_regs->doeptsiz);
+
+		/* Program the transfer size and packet count as follows:
+		 *      xfersize = N * (maxpacket + 4 - (maxpacket % 4))
+		 *      pktcnt = N                                                                                      */
+		/* Zero Length Packet */
+		deptsiz.b.xfersize = ep->maxpacket;
+		deptsiz.b.pktcnt = 1;
+
+		DWC_DEBUGPL(DBG_PCDV, "len=%d  xfersize=%d pktcnt=%d\n",
+			    ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt);
+
+		if (core_if->dma_enable) {
+			if (!core_if->dma_desc_enable) {
+				dwc_write_reg32(&out_regs->doeptsiz,
+						deptsiz.d32);
+
+				dwc_write_reg32(&(out_regs->doepdma),
+						(uint32_t) ep->dma_addr);
+			} else {
+				dma_desc = core_if->dev_if->out_desc_addr;
+
+				/** DMA Descriptor Setup */
+				dma_desc->status.b.bs = BS_HOST_BUSY;
+				dma_desc->status.b.l = 1;
+				dma_desc->status.b.ioc = 1;
+				dma_desc->status.b.bytes = ep->maxpacket;
+				dma_desc->buf = ep->dma_addr;
+				dma_desc->status.b.bs = BS_HOST_READY;
+
+				/** DOEPDMA0 Register write */
+				dwc_write_reg32(&out_regs->doepdma,
+						core_if->dev_if->
+						dma_out_desc_addr);
+			}
+		} else {
+			dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
+		}
+
+		/* EP enable */
+		depctl.b.cnak = 1;
+		depctl.b.epena = 1;
+		dwc_write_reg32(&(out_regs->doepctl), depctl.d32);
+	}
+}
+
+/**
+ * This function continues control IN transfers started by
+ * dwc_otg_ep0_start_transfer, when the transfer does not fit in a
+ * single packet.  NOTE: The DIEPCTL0/DOEPCTL0 registers only have one
+ * bit for the packet count.
+ *
+ * @param core_if Programming view of DWC_otg controller.
+ * @param ep The EP0 data.
+ */
+void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
+{
+	depctl_data_t depctl;
+	deptsiz0_data_t deptsiz;
+	gintmsk_data_t intr_mask = {.d32 = 0 };
+	dwc_otg_dev_dma_desc_t *dma_desc;
+
+	if (ep->is_in == 1) {
+		dwc_otg_dev_in_ep_regs_t *in_regs =
+		    core_if->dev_if->in_ep_regs[0];
+		gnptxsts_data_t tx_status = {.d32 = 0 };
+
+		tx_status.d32 =
+		    dwc_read_reg32(&core_if->core_global_regs->gnptxsts);
+		/** @todo Should there be check for room in the Tx
+		 * Status Queue.  If not remove the code above this comment. */
+
+		depctl.d32 = dwc_read_reg32(&in_regs->diepctl);
+		deptsiz.d32 = dwc_read_reg32(&in_regs->dieptsiz);
+
+		/* Program the transfer size and packet count
+		 *      as follows: xfersize = N * maxpacket +
+		 *      short_packet pktcnt = N + (short_packet
+		 *      exist ? 1 : 0)  
+		 */
+
+		if (core_if->dma_desc_enable == 0) {
+			deptsiz.b.xfersize =
+			    (ep->total_len - ep->xfer_count) >
+			    ep->maxpacket ? ep->maxpacket : (ep->total_len -
+							     ep->xfer_count);
+			deptsiz.b.pktcnt = 1;
+			if (core_if->dma_enable == 0) {
+				ep->xfer_len += deptsiz.b.xfersize;
+			} else {
+				ep->xfer_len = deptsiz.b.xfersize;
+			}
+			dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
+		} else {
+			ep->xfer_len =
+			    (ep->total_len - ep->xfer_count) >
+			    ep->maxpacket ? ep->maxpacket : (ep->total_len -
+							     ep->xfer_count);
+
+			dma_desc = core_if->dev_if->in_desc_addr;
+
+			/** DMA Descriptor Setup */
+			dma_desc->status.b.bs = BS_HOST_BUSY;
+			dma_desc->status.b.l = 1;
+			dma_desc->status.b.ioc = 1;
+			dma_desc->status.b.sp =
+			    (ep->xfer_len == ep->maxpacket) ? 0 : 1;
+			dma_desc->status.b.bytes = ep->xfer_len;
+			dma_desc->buf = ep->dma_addr;
+			dma_desc->status.b.bs = BS_HOST_READY;
+
+			/** DIEPDMA0 Register write */
+			dwc_write_reg32(&in_regs->diepdma,
+					core_if->dev_if->dma_in_desc_addr);
+		}
+
+		DWC_DEBUGPL(DBG_PCDV,
+			    "IN len=%d  xfersize=%d pktcnt=%d [%08x]\n",
+			    ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt,
+			    deptsiz.d32);
+
+		/* Write the DMA register */
+		if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) {
+			if (core_if->dma_desc_enable == 0)
+				dwc_write_reg32(&(in_regs->diepdma),
+						(uint32_t) ep->dma_addr);
+		}
+
+		/* EP enable, IN data in FIFO */
+		depctl.b.cnak = 1;
+		depctl.b.epena = 1;
+		dwc_write_reg32(&in_regs->diepctl, depctl.d32);
+
+		/** 
+		 * Enable the Non-Periodic Tx FIFO empty interrupt, the
+		 * data will be written into the fifo by the ISR.
+		 */
+		if (!core_if->dma_enable) {
+			if (core_if->en_multiple_tx_fifo == 0) {
+				/* First clear it from GINTSTS */
+				intr_mask.b.nptxfempty = 1;
+				dwc_modify_reg32(&core_if->core_global_regs->
+						 gintmsk, intr_mask.d32,
+						 intr_mask.d32);
+
+			} else {
+				/* Enable the Tx FIFO Empty Interrupt for this EP */
+				if (ep->xfer_len > 0) {
+					uint32_t fifoemptymsk = 0;
+					fifoemptymsk |= 1 << ep->num;
+					dwc_modify_reg32(&core_if->dev_if->
+							 dev_global_regs->
+							 dtknqr4_fifoemptymsk,
+							 0, fifoemptymsk);
+				}
+			}
+		}
+	} else {
+		dwc_otg_dev_out_ep_regs_t *out_regs =
+		    core_if->dev_if->out_ep_regs[0];
+
+		depctl.d32 = dwc_read_reg32(&out_regs->doepctl);
+		deptsiz.d32 = dwc_read_reg32(&out_regs->doeptsiz);
+
+		/* Program the transfer size and packet count
+		 *      as follows: xfersize = N * maxpacket +
+		 *      short_packet pktcnt = N + (short_packet
+		 *      exist ? 1 : 0)  
+		 */
+		deptsiz.b.xfersize = ep->maxpacket;
+		deptsiz.b.pktcnt = 1;
+
+		if (core_if->dma_desc_enable == 0) {
+			dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
+		} else {
+			dma_desc = core_if->dev_if->out_desc_addr;
+
+			/** DMA Descriptor Setup */
+			dma_desc->status.b.bs = BS_HOST_BUSY;
+			dma_desc->status.b.l = 1;
+			dma_desc->status.b.ioc = 1;
+			dma_desc->status.b.bytes = ep->maxpacket;
+			dma_desc->buf = ep->dma_addr;
+			dma_desc->status.b.bs = BS_HOST_READY;
+
+			/** DOEPDMA0 Register write */
+			dwc_write_reg32(&out_regs->doepdma,
+					core_if->dev_if->dma_out_desc_addr);
+		}
+
+		DWC_DEBUGPL(DBG_PCDV,
+			    "IN len=%d  xfersize=%d pktcnt=%d [%08x]\n",
+			    ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt,
+			    deptsiz.d32);
+
+		/* Write the DMA register */
+		if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) {
+			if (core_if->dma_desc_enable == 0)
+				dwc_write_reg32(&(out_regs->doepdma),
+						(uint32_t) ep->dma_addr);
+		}
+
+		/* EP enable, IN data in FIFO */
+		depctl.b.cnak = 1;
+		depctl.b.epena = 1;
+		dwc_write_reg32(&out_regs->doepctl, depctl.d32);
+
+	}
+}
+
+#ifdef DEBUG
+void dump_msg(const u8 * buf, unsigned int length)
+{
+	unsigned int start, num, i;
+	char line[52], *p;
+
+	if (length >= 512)
+		return;
+	start = 0;
+	while (length > 0) {
+		num = length < 16u ? length : 16u;
+		p = line;
+		for (i = 0; i < num; ++i) {
+			if (i == 8)
+				*p++ = ' ';
+			DWC_SPRINTF(p, " %02x", buf[i]);
+			p += 3;
+		}
+		*p = 0;
+		DWC_PRINTF("%6x: %s\n", start, line);
+		buf += num;
+		start += num;
+		length -= num;
+	}
+}
+#else
+static inline void dump_msg(const u8 * buf, unsigned int length)
+{
+}
+#endif
+
+/**
+ * This function writes a packet into the Tx FIFO associated with the
+ * EP.	For non-periodic EPs the non-periodic Tx FIFO is written.  For
+ * periodic EPs the periodic Tx FIFO associated with the EP is written
+ * with all packets for the next micro-frame.
+ *
+ * @param core_if Programming view of DWC_otg controller.
+ * @param ep The EP to write packet for.
+ * @param dma Indicates if DMA is being used.
+ */
+void dwc_otg_ep_write_packet(dwc_otg_core_if_t * core_if, dwc_ep_t * ep,
+			     int dma)
+{
+	/**
+	 * The buffer is padded to DWORD on a per packet basis in
+	 * slave/dma mode if the MPS is not DWORD aligned.	The last
+	 * packet, if short, is also padded to a multiple of DWORD.
+	 *
+	 * ep->xfer_buff always starts DWORD aligned in memory and is a 
+	 * multiple of DWORD in length
+	 *
+	 * ep->xfer_len can be any number of bytes
+	 *
+	 * ep->xfer_count is a multiple of ep->maxpacket until the last 
+	 *	packet
+	 *
+	 * FIFO access is DWORD */
+
+	uint32_t i;
+	uint32_t byte_count;
+	uint32_t dword_count;
+	uint32_t *fifo;
+	uint32_t *data_buff = (uint32_t *) ep->xfer_buff;
+
+	DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p)\n", __func__, core_if,
+		    ep);
+	if (ep->xfer_count >= ep->xfer_len) {
+		DWC_WARN("%s() No data for EP%d!!!\n", __func__, ep->num);
+		return;
+	}
+
+	/* Find the byte length of the packet either short packet or MPS */
+	if ((ep->xfer_len - ep->xfer_count) < ep->maxpacket) {
+		byte_count = ep->xfer_len - ep->xfer_count;
+	} else {
+		byte_count = ep->maxpacket;
+	}
+
+	/* Find the DWORD length, padded by extra bytes as neccessary if MPS
+	 * is not a multiple of DWORD */
+	dword_count = (byte_count + 3) / 4;
+
+#ifdef VERBOSE
+	dump_msg(ep->xfer_buff, byte_count);
+#endif
+
+	/**@todo NGS Where are the Periodic Tx FIFO addresses
+	 * intialized?	What should this be? */
+
+	fifo = core_if->data_fifo[ep->num];
+
+	DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "fifo=%p buff=%p *p=%08x bc=%d\n",
+		    fifo, data_buff, *data_buff, byte_count);
+
+	if (!dma) {
+		for (i = 0; i < dword_count; i++, data_buff++) {
+			dwc_write_reg32(fifo, *data_buff);
+		}
+	}
+
+	ep->xfer_count += byte_count;
+	ep->xfer_buff += byte_count;
+	ep->dma_addr += byte_count;
+}
+
+/** 
+ * Set the EP STALL.
+ *
+ * @param core_if Programming view of DWC_otg controller.
+ * @param ep The EP to set the stall on.
+ */
+void dwc_otg_ep_set_stall(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
+{
+	depctl_data_t depctl;
+	volatile uint32_t *depctl_addr;
+
+	DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, ep->num,
+		    (ep->is_in ? "IN" : "OUT"));
+
+	if (ep->is_in == 1) {
+		depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl);
+		depctl.d32 = dwc_read_reg32(depctl_addr);
+
+		/* set the disable and stall bits */
+		if (depctl.b.epena) {
+			depctl.b.epdis = 1;
+		}
+		depctl.b.stall = 1;
+		dwc_write_reg32(depctl_addr, depctl.d32);
+	} else {
+		depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl);
+		depctl.d32 = dwc_read_reg32(depctl_addr);
+
+		/* set the stall bit */
+		depctl.b.stall = 1;
+		dwc_write_reg32(depctl_addr, depctl.d32);
+	}
+
+	DWC_DEBUGPL(DBG_PCD, "DEPCTL=%0x\n", dwc_read_reg32(depctl_addr));
+
+	return;
+}
+
+/** 
+ * Clear the EP STALL.
+ *
+ * @param core_if Programming view of DWC_otg controller.
+ * @param ep The EP to clear stall from.
+ */
+void dwc_otg_ep_clear_stall(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
+{
+	depctl_data_t depctl;
+	volatile uint32_t *depctl_addr;
+
+	DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, ep->num,
+		    (ep->is_in ? "IN" : "OUT"));
+
+	if (ep->is_in == 1) {
+		depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl);
+	} else {
+		depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl);
+	}
+
+	depctl.d32 = dwc_read_reg32(depctl_addr);
+
+	/* clear the stall bits */
+	depctl.b.stall = 0;
+
+	/* 
+	 * USB Spec 9.4.5: For endpoints using data toggle, regardless
+	 * of whether an endpoint has the Halt feature set, a
+	 * ClearFeature(ENDPOINT_HALT) request always results in the
+	 * data toggle being reinitialized to DATA0.
+	 */
+	if (ep->type == DWC_OTG_EP_TYPE_INTR ||
+	    ep->type == DWC_OTG_EP_TYPE_BULK) {
+		depctl.b.setd0pid = 1;	/* DATA0 */
+	}
+
+	dwc_write_reg32(depctl_addr, depctl.d32);
+	DWC_DEBUGPL(DBG_PCD, "DEPCTL=%0x\n", dwc_read_reg32(depctl_addr));
+	return;
+}
+
+/** 
+ * This function reads a packet from the Rx FIFO into the destination
+ * buffer.	To read SETUP data use dwc_otg_read_setup_packet.
+ *
+ * @param core_if Programming view of DWC_otg controller.
+ * @param dest	  Destination buffer for the packet.
+ * @param bytes  Number of bytes to copy to the destination.
+ */
+void dwc_otg_read_packet(dwc_otg_core_if_t * core_if,
+			 uint8_t * dest, uint16_t bytes)
+{
+	int i;
+	int word_count = (bytes + 3) / 4;
+
+	volatile uint32_t *fifo = core_if->data_fifo[0];
+	uint32_t *data_buff = (uint32_t *) dest;
+
+	/**
+	 * @todo Account for the case where _dest is not dword aligned. This
+	 * requires reading data from the FIFO into a uint32_t temp buffer,
+	 * then moving it into the data buffer.
+	 */
+
+	DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p,%d)\n", __func__,
+		    core_if, dest, bytes);
+
+	for (i = 0; i < word_count; i++, data_buff++) {
+		*data_buff = dwc_read_reg32(fifo);
+	}
+
+	return;
+}
+
+/**
+ * This functions reads the device registers and prints them
+ *
+ * @param core_if Programming view of DWC_otg controller.
+ */
+void dwc_otg_dump_dev_registers(dwc_otg_core_if_t * core_if)
+{
+	int i;
+	volatile uint32_t *addr;
+
+	DWC_PRINTF("Device Global Registers\n");
+	addr = &core_if->dev_if->dev_global_regs->dcfg;
+	DWC_PRINTF("DCFG		 @0x%08X : 0x%08X\n", (uint32_t) addr,
+		   dwc_read_reg32(addr));
+	addr = &core_if->dev_if->dev_global_regs->dctl;
+	DWC_PRINTF("DCTL		 @0x%08X : 0x%08X\n", (uint32_t) addr,
+		   dwc_read_reg32(addr));
+	addr = &core_if->dev_if->dev_global_regs->dsts;
+	DWC_PRINTF("DSTS		 @0x%08X : 0x%08X\n", (uint32_t) addr,
+		   dwc_read_reg32(addr));
+	addr = &core_if->dev_if->dev_global_regs->diepmsk;
+	DWC_PRINTF("DIEPMSK	 @0x%08X : 0x%08X\n", (uint32_t) addr,
+		   dwc_read_reg32(addr));
+	addr = &core_if->dev_if->dev_global_regs->doepmsk;
+	DWC_PRINTF("DOEPMSK	 @0x%08X : 0x%08X\n", (uint32_t) addr,
+		   dwc_read_reg32(addr));
+	addr = &core_if->dev_if->dev_global_regs->daint;
+	DWC_PRINTF("DAINT	 @0x%08X : 0x%08X\n", (uint32_t) addr,
+		   dwc_read_reg32(addr));
+	addr = &core_if->dev_if->dev_global_regs->daintmsk;
+	DWC_PRINTF("DAINTMSK	 @0x%08X : 0x%08X\n", (uint32_t) addr,
+		   dwc_read_reg32(addr));
+	addr = &core_if->dev_if->dev_global_regs->dtknqr1;
+	DWC_PRINTF("DTKNQR1	 @0x%08X : 0x%08X\n", (uint32_t) addr,
+		   dwc_read_reg32(addr));
+	if (core_if->hwcfg2.b.dev_token_q_depth > 6) {
+		addr = &core_if->dev_if->dev_global_regs->dtknqr2;
+		DWC_PRINTF("DTKNQR2	 @0x%08X : 0x%08X\n",
+			   (uint32_t) addr, dwc_read_reg32(addr));
+	}
+
+	addr = &core_if->dev_if->dev_global_regs->dvbusdis;
+	DWC_PRINTF("DVBUSID	 @0x%08X : 0x%08X\n", (uint32_t) addr,
+		   dwc_read_reg32(addr));
+
+	addr = &core_if->dev_if->dev_global_regs->dvbuspulse;
+	DWC_PRINTF("DVBUSPULSE	@0x%08X : 0x%08X\n",
+		   (uint32_t) addr, dwc_read_reg32(addr));
+
+		addr = &core_if->dev_if->dev_global_regs->dtknqr3_dthrctl;
+		DWC_PRINTF("DTKNQR3_DTHRCTL	 @0x%08X : 0x%08X\n",
+			   (uint32_t) addr, dwc_read_reg32(addr));
+
+	if (core_if->hwcfg2.b.dev_token_q_depth > 22) {
+		addr = &core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk;
+		DWC_PRINTF("DTKNQR4	 @0x%08X : 0x%08X\n",
+			   (uint32_t) addr, dwc_read_reg32(addr));
+	}
+
+	addr = &core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk;
+	DWC_PRINTF("FIFOEMPMSK	 @0x%08X : 0x%08X\n", (uint32_t) addr,
+		   dwc_read_reg32(addr));
+
+	addr = &core_if->dev_if->dev_global_regs->deachint;
+	DWC_PRINTF("DEACHINT	 @0x%08X : 0x%08X\n", (uint32_t) addr,
+		   dwc_read_reg32(addr));
+	addr = &core_if->dev_if->dev_global_regs->deachintmsk;
+	DWC_PRINTF("DEACHINTMSK	 @0x%08X : 0x%08X\n", (uint32_t) addr,
+		   dwc_read_reg32(addr));
+
+	for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
+		addr = &core_if->dev_if->dev_global_regs->diepeachintmsk[i];
+		DWC_PRINTF("DIEPEACHINTMSK[%d]	 @0x%08X : 0x%08X\n", i,
+			   (uint32_t) addr, dwc_read_reg32(addr));
+	}
+
+	for (i = 0; i <= core_if->dev_if->num_out_eps; i++) {
+		addr = &core_if->dev_if->dev_global_regs->doepeachintmsk[i];
+		DWC_PRINTF("DOEPEACHINTMSK[%d]	 @0x%08X : 0x%08X\n", i,
+			   (uint32_t) addr, dwc_read_reg32(addr));
+	}
+
+	for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
+		DWC_PRINTF("Device IN EP %d Registers\n", i);
+		addr = &core_if->dev_if->in_ep_regs[i]->diepctl;
+		DWC_PRINTF("DIEPCTL	 @0x%08X : 0x%08X\n", (uint32_t) addr,
+			   dwc_read_reg32(addr));
+		addr = &core_if->dev_if->in_ep_regs[i]->diepint;
+		DWC_PRINTF("DIEPINT	 @0x%08X : 0x%08X\n", (uint32_t) addr,
+			   dwc_read_reg32(addr));
+		addr = &core_if->dev_if->in_ep_regs[i]->dieptsiz;
+		DWC_PRINTF("DIETSIZ	 @0x%08X : 0x%08X\n", (uint32_t) addr,
+			   dwc_read_reg32(addr));
+		addr = &core_if->dev_if->in_ep_regs[i]->diepdma;
+		DWC_PRINTF("DIEPDMA	 @0x%08X : 0x%08X\n", (uint32_t) addr,
+			   dwc_read_reg32(addr));
+		addr = &core_if->dev_if->in_ep_regs[i]->dtxfsts;
+		DWC_PRINTF("DTXFSTS	 @0x%08X : 0x%08X\n", (uint32_t) addr,
+			   dwc_read_reg32(addr));
+		addr = &core_if->dev_if->in_ep_regs[i]->diepdmab;
+		DWC_PRINTF("DIEPDMAB	 @0x%08X : 0x%08X\n", (uint32_t) addr,
+			   0 /*dwc_read_reg32(addr) */ );
+	}
+
+	for (i = 0; i <= core_if->dev_if->num_out_eps; i++) {
+		DWC_PRINTF("Device OUT EP %d Registers\n", i);
+		addr = &core_if->dev_if->out_ep_regs[i]->doepctl;
+		DWC_PRINTF("DOEPCTL	 @0x%08X : 0x%08X\n", (uint32_t) addr,
+			   dwc_read_reg32(addr));
+		addr = &core_if->dev_if->out_ep_regs[i]->doepfn;
+		DWC_PRINTF("DOEPFN	 @0x%08X : 0x%08X\n", (uint32_t) addr,
+			   dwc_read_reg32(addr));
+		addr = &core_if->dev_if->out_ep_regs[i]->doepint;
+		DWC_PRINTF("DOEPINT	 @0x%08X : 0x%08X\n", (uint32_t) addr,
+			   dwc_read_reg32(addr));
+		addr = &core_if->dev_if->out_ep_regs[i]->doeptsiz;
+		DWC_PRINTF("DOETSIZ	 @0x%08X : 0x%08X\n", (uint32_t) addr,
+			   dwc_read_reg32(addr));
+		addr = &core_if->dev_if->out_ep_regs[i]->doepdma;
+		DWC_PRINTF("DOEPDMA	 @0x%08X : 0x%08X\n", (uint32_t) addr,
+			   dwc_read_reg32(addr));
+		if (core_if->dma_enable) {	/* Don't access this register in SLAVE mode */
+			addr = &core_if->dev_if->out_ep_regs[i]->doepdmab;
+			DWC_PRINTF("DOEPDMAB	 @0x%08X : 0x%08X\n",
+				   (uint32_t) addr, dwc_read_reg32(addr));
+		}
+
+	}
+}
+
+/**
+ * This functions reads the SPRAM and prints its content
+ *
+ * @param core_if Programming view of DWC_otg controller.
+ */
+void dwc_otg_dump_spram(dwc_otg_core_if_t * core_if)
+{
+	volatile uint8_t *addr, *start_addr, *end_addr;
+
+	DWC_PRINTF("SPRAM Data:\n");
+	start_addr = (void *)core_if->core_global_regs;
+	DWC_PRINTF("Base Address: 0x%8X\n", (uint32_t) start_addr);
+	start_addr += 0x00028000;
+	end_addr = (void *)core_if->core_global_regs;
+	end_addr += 0x000280e0;
+
+	for (addr = start_addr; addr < end_addr; addr += 16) {
+		DWC_PRINTF
+		    ("0x%8X:\t%2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X\n",
+		     (uint32_t) addr, addr[0], addr[1], addr[2], addr[3],
+		     addr[4], addr[5], addr[6], addr[7], addr[8], addr[9],
+		     addr[10], addr[11], addr[12], addr[13], addr[14], addr[15]
+		    );
+	}
+
+	return;
+}
+
+/**
+ * This function reads the host registers and prints them
+ *
+ * @param core_if Programming view of DWC_otg controller.
+ */
+void dwc_otg_dump_host_registers(dwc_otg_core_if_t * core_if)
+{
+	int i;
+	volatile uint32_t *addr;
+
+	DWC_PRINTF("Host Global Registers\n");
+	addr = &core_if->host_if->host_global_regs->hcfg;
+	DWC_PRINTF("HCFG		 @0x%08X : 0x%08X\n", (uint32_t) addr,
+		   dwc_read_reg32(addr));
+	addr = &core_if->host_if->host_global_regs->hfir;
+	DWC_PRINTF("HFIR		 @0x%08X : 0x%08X\n", (uint32_t) addr,
+		   dwc_read_reg32(addr));
+	addr = &core_if->host_if->host_global_regs->hfnum;
+	DWC_PRINTF("HFNUM	 @0x%08X : 0x%08X\n", (uint32_t) addr,
+		   dwc_read_reg32(addr));
+	addr = &core_if->host_if->host_global_regs->hptxsts;
+	DWC_PRINTF("HPTXSTS	 @0x%08X : 0x%08X\n", (uint32_t) addr,
+		   dwc_read_reg32(addr));
+	addr = &core_if->host_if->host_global_regs->haint;
+	DWC_PRINTF("HAINT	 @0x%08X : 0x%08X\n", (uint32_t) addr,
+		   dwc_read_reg32(addr));
+	addr = &core_if->host_if->host_global_regs->haintmsk;
+	DWC_PRINTF("HAINTMSK	 @0x%08X : 0x%08X\n", (uint32_t) addr,
+		   dwc_read_reg32(addr));
+	if (core_if->dma_desc_enable) {
+		addr = &core_if->host_if->host_global_regs->hflbaddr;
+		DWC_PRINTF("HFLBADDR	 @0x%08X : 0x%08X\n",(uint32_t) addr,
+			   dwc_read_reg32(addr));
+	}
+	
+	addr = core_if->host_if->hprt0;
+	DWC_PRINTF("HPRT0	 @0x%08X : 0x%08X\n", (uint32_t) addr,
+		   dwc_read_reg32(addr));
+
+	for (i = 0; i < core_if->core_params->host_channels; i++) {
+		DWC_PRINTF("Host Channel %d Specific Registers\n", i);
+		addr = &core_if->host_if->hc_regs[i]->hcchar;
+		DWC_PRINTF("HCCHAR	 @0x%08X : 0x%08X\n", (uint32_t) addr,
+			   dwc_read_reg32(addr));
+		addr = &core_if->host_if->hc_regs[i]->hcsplt;
+		DWC_PRINTF("HCSPLT	 @0x%08X : 0x%08X\n", (uint32_t) addr,
+			   dwc_read_reg32(addr));
+		addr = &core_if->host_if->hc_regs[i]->hcint;
+		DWC_PRINTF("HCINT	 @0x%08X : 0x%08X\n", (uint32_t) addr,
+			   dwc_read_reg32(addr));
+		addr = &core_if->host_if->hc_regs[i]->hcintmsk;
+		DWC_PRINTF("HCINTMSK	 @0x%08X : 0x%08X\n", (uint32_t) addr,
+			   dwc_read_reg32(addr));
+		addr = &core_if->host_if->hc_regs[i]->hctsiz;
+		DWC_PRINTF("HCTSIZ	 @0x%08X : 0x%08X\n", (uint32_t) addr,
+			   dwc_read_reg32(addr));
+		addr = &core_if->host_if->hc_regs[i]->hcdma;
+		DWC_PRINTF("HCDMA	 @0x%08X : 0x%08X\n", (uint32_t) addr,
+			   dwc_read_reg32(addr));
+		if (core_if->dma_desc_enable) {
+			addr=&core_if->host_if->hc_regs[i]->hcdmab;
+			DWC_PRINTF("HCDMAB	 @0x%08X : 0x%08X\n",(uint32_t) addr, dwc_read_reg32(addr));
+	}
+
+	}
+	return;
+}
+
+/**
+ * This function reads the core global registers and prints them
+ *
+ * @param core_if Programming view of DWC_otg controller.
+ */
+void dwc_otg_dump_global_registers(dwc_otg_core_if_t * core_if)
+{
+	int i;
+	volatile uint32_t *addr;
+
+	DWC_PRINTF("Core Global Registers\n");
+	addr = &core_if->core_global_regs->gotgctl;
+	DWC_PRINTF("GOTGCTL	 @0x%08X : 0x%08X\n", (uint32_t) addr,
+		   dwc_read_reg32(addr));
+	addr = &core_if->core_global_regs->gotgint;
+	DWC_PRINTF("GOTGINT	 @0x%08X : 0x%08X\n", (uint32_t) addr,
+		   dwc_read_reg32(addr));
+	addr = &core_if->core_global_regs->gahbcfg;
+	DWC_PRINTF("GAHBCFG	 @0x%08X : 0x%08X\n", (uint32_t) addr,
+		   dwc_read_reg32(addr));
+	addr = &core_if->core_global_regs->gusbcfg;
+	DWC_PRINTF("GUSBCFG	 @0x%08X : 0x%08X\n", (uint32_t) addr,
+		   dwc_read_reg32(addr));
+	addr = &core_if->core_global_regs->grstctl;
+	DWC_PRINTF("GRSTCTL	 @0x%08X : 0x%08X\n", (uint32_t) addr,
+		   dwc_read_reg32(addr));
+	addr = &core_if->core_global_regs->gintsts;
+	DWC_PRINTF("GINTSTS	 @0x%08X : 0x%08X\n", (uint32_t) addr,
+		   dwc_read_reg32(addr));
+	addr = &core_if->core_global_regs->gintmsk;
+	DWC_PRINTF("GINTMSK	 @0x%08X : 0x%08X\n", (uint32_t) addr,
+		   dwc_read_reg32(addr));
+	addr = &core_if->core_global_regs->grxstsr;
+	DWC_PRINTF("GRXSTSR	 @0x%08X : 0x%08X\n", (uint32_t) addr,
+		   dwc_read_reg32(addr));
+	addr = &core_if->core_global_regs->grxfsiz;
+	DWC_PRINTF("GRXFSIZ	 @0x%08X : 0x%08X\n", (uint32_t) addr,
+		   dwc_read_reg32(addr));
+	addr = &core_if->core_global_regs->gnptxfsiz;
+	DWC_PRINTF("GNPTXFSIZ @0x%08X : 0x%08X\n", (uint32_t) addr,
+		   dwc_read_reg32(addr));
+	addr = &core_if->core_global_regs->gnptxsts;
+	DWC_PRINTF("GNPTXSTS	 @0x%08X : 0x%08X\n", (uint32_t) addr,
+		   dwc_read_reg32(addr));
+	addr = &core_if->core_global_regs->gi2cctl;
+	DWC_PRINTF("GI2CCTL	 @0x%08X : 0x%08X\n", (uint32_t) addr,
+		   dwc_read_reg32(addr));
+	addr = &core_if->core_global_regs->gpvndctl;
+	DWC_PRINTF("GPVNDCTL	 @0x%08X : 0x%08X\n", (uint32_t) addr,
+		   dwc_read_reg32(addr));
+	addr = &core_if->core_global_regs->ggpio;
+	DWC_PRINTF("GGPIO	 @0x%08X : 0x%08X\n", (uint32_t) addr,
+		   dwc_read_reg32(addr));
+	addr = &core_if->core_global_regs->guid;
+	DWC_PRINTF("GUID		 @0x%08X : 0x%08X\n", (uint32_t) addr,
+		   dwc_read_reg32(addr));
+	addr = &core_if->core_global_regs->gsnpsid;
+	DWC_PRINTF("GSNPSID	 @0x%08X : 0x%08X\n", (uint32_t) addr,
+		   dwc_read_reg32(addr));
+	addr = &core_if->core_global_regs->ghwcfg1;
+	DWC_PRINTF("GHWCFG1	 @0x%08X : 0x%08X\n", (uint32_t) addr,
+		   dwc_read_reg32(addr));
+	addr = &core_if->core_global_regs->ghwcfg2;
+	DWC_PRINTF("GHWCFG2	 @0x%08X : 0x%08X\n", (uint32_t) addr,
+		   dwc_read_reg32(addr));
+	addr = &core_if->core_global_regs->ghwcfg3;
+	DWC_PRINTF("GHWCFG3	 @0x%08X : 0x%08X\n", (uint32_t) addr,
+		   dwc_read_reg32(addr));
+	addr = &core_if->core_global_regs->ghwcfg4;
+	DWC_PRINTF("GHWCFG4	 @0x%08X : 0x%08X\n", (uint32_t) addr,
+		   dwc_read_reg32(addr));
+	addr = &core_if->core_global_regs->glpmcfg;
+	DWC_PRINTF("GLPMCFG	 @0x%08X : 0x%08X\n", (uint32_t) addr,
+		   dwc_read_reg32(addr));
+	addr = &core_if->core_global_regs->hptxfsiz;
+	DWC_PRINTF("HPTXFSIZ	 @0x%08X : 0x%08X\n", (uint32_t) addr,
+		   dwc_read_reg32(addr));
+
+	for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++) {
+		addr = &core_if->core_global_regs->dptxfsiz_dieptxf[i];
+		DWC_PRINTF("DPTXFSIZ[%d] @0x%08X : 0x%08X\n", i,
+			   (uint32_t) addr, dwc_read_reg32(addr));
+	}
+	addr = core_if->pcgcctl;
+	DWC_PRINTF("PCGCCTL	 @0x%08X : 0x%08X\n", (uint32_t) addr,
+		   dwc_read_reg32(addr));
+}
+
+/**
+ * Flush a Tx FIFO.
+ *
+ * @param core_if Programming view of DWC_otg controller.
+ * @param num Tx FIFO to flush.
+ */
+void dwc_otg_flush_tx_fifo(dwc_otg_core_if_t * core_if, const int num)
+{
+	dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
+	volatile grstctl_t greset = {.d32 = 0 };
+	int count = 0;
+
+	DWC_DEBUGPL((DBG_CIL | DBG_PCDV), "Flush Tx FIFO %d\n", num);
+
+	greset.b.txfflsh = 1;
+	greset.b.txfnum = num;
+	dwc_write_reg32(&global_regs->grstctl, greset.d32);
+
+	do {
+		greset.d32 = dwc_read_reg32(&global_regs->grstctl);
+		if (++count > 10000) {
+			DWC_WARN("%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n",
+				 __func__, greset.d32,
+				 dwc_read_reg32(&global_regs->gnptxsts));
+			break;
+		}
+		dwc_udelay(1);
+	} while (greset.b.txfflsh == 1);
+
+	/* Wait for 3 PHY Clocks */
+	dwc_udelay(1);
+}
+
+/**
+ * Flush Rx FIFO.
+ *
+ * @param core_if Programming view of DWC_otg controller.
+ */
+void dwc_otg_flush_rx_fifo(dwc_otg_core_if_t * core_if)
+{
+	dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
+	volatile grstctl_t greset = {.d32 = 0 };
+	int count = 0;
+
+	DWC_DEBUGPL((DBG_CIL | DBG_PCDV), "%s\n", __func__);
+	/*
+	 * 
+	 */
+	greset.b.rxfflsh = 1;
+	dwc_write_reg32(&global_regs->grstctl, greset.d32);
+
+	do {
+		greset.d32 = dwc_read_reg32(&global_regs->grstctl);
+		if (++count > 10000) {
+			DWC_WARN("%s() HANG! GRSTCTL=%0x\n", __func__,
+				 greset.d32);
+			break;
+		}
+		dwc_udelay(1);
+	} while (greset.b.rxfflsh == 1);
+
+	/* Wait for 3 PHY Clocks */
+	dwc_udelay(1);
+}
+
+/**
+ * Do core a soft reset of the core.  Be careful with this because it
+ * resets all the internal state machines of the core.
+ */
+void dwc_otg_core_reset(dwc_otg_core_if_t * core_if)
+{
+	dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
+	volatile grstctl_t greset = {.d32 = 0 };
+	int count = 0;
+
+	DWC_DEBUGPL(DBG_CILV, "%s\n", __func__);
+	/* Wait for AHB master IDLE state. */
+	do {
+		dwc_udelay(10);
+		greset.d32 = dwc_read_reg32(&global_regs->grstctl);
+		if (++count > 100000) {
+			DWC_WARN("%s() HANG! AHB Idle GRSTCTL=%0x\n", __func__,
+				 greset.d32);
+			return;
+		}
+	}
+	while (greset.b.ahbidle == 0);
+
+	/* Core Soft Reset */
+	count = 0;
+	greset.b.csftrst = 1;
+	dwc_write_reg32(&global_regs->grstctl, greset.d32);
+	do {
+		greset.d32 = dwc_read_reg32(&global_regs->grstctl);
+		if (++count > 10000) {
+			DWC_WARN("%s() HANG! Soft Reset GRSTCTL=%0x\n",
+				 __func__, greset.d32);
+			break;
+		}
+		dwc_udelay(1);
+	}
+	while (greset.b.csftrst == 1);
+
+	/* Wait for 3 PHY Clocks */
+	dwc_mdelay(100);
+}
+
+uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t * _core_if)
+{
+	return (dwc_otg_mode(_core_if) != DWC_HOST_MODE);
+}
+
+uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t * _core_if)
+{
+	return (dwc_otg_mode(_core_if) == DWC_HOST_MODE);
+}
+
+/**
+ * Register HCD callbacks.	The callbacks are used to start and stop
+ * the HCD for interrupt processing.
+ *
+ * @param core_if Programming view of DWC_otg controller.
+ * @param cb the HCD callback structure.
+ * @param p pointer to be passed to callback function (usb_hcd*).
+ */
+void dwc_otg_cil_register_hcd_callbacks(dwc_otg_core_if_t * core_if,
+					dwc_otg_cil_callbacks_t * cb, void *p)
+{
+	core_if->hcd_cb = cb;
+	cb->p = p;
+}
+
+/**
+ * Register PCD callbacks.	The callbacks are used to start and stop
+ * the PCD for interrupt processing.
+ *
+ * @param core_if Programming view of DWC_otg controller.
+ * @param cb the PCD callback structure.
+ * @param p pointer to be passed to callback function (pcd*).
+ */
+void dwc_otg_cil_register_pcd_callbacks(dwc_otg_core_if_t * core_if,
+					dwc_otg_cil_callbacks_t * cb, void *p)
+{
+	core_if->pcd_cb = cb;
+	cb->p = p;
+}
+
+#ifdef DWC_EN_ISOC
+
+/**
+ * This function writes isoc data per 1 (micro)frame into tx fifo
+ *
+ * @param core_if Programming view of DWC_otg controller.
+ * @param ep The EP to start the transfer on.
+ *
+ */
+void write_isoc_frame_data(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
+{
+	dwc_otg_dev_in_ep_regs_t *ep_regs;
+	dtxfsts_data_t txstatus = {.d32 = 0 };
+	uint32_t len = 0;
+	uint32_t dwords;
+
+	ep->xfer_len = ep->data_per_frame;
+	ep->xfer_count = 0;
+
+	ep_regs = core_if->dev_if->in_ep_regs[ep->num];
+
+	len = ep->xfer_len - ep->xfer_count;
+
+	if (len > ep->maxpacket) {
+		len = ep->maxpacket;
+	}
+
+	dwords = (len + 3) / 4;
+
+	/* While there is space in the queue and space in the FIFO and
+	 * More data to tranfer, Write packets to the Tx FIFO */
+	txstatus.d32 =
+	    dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]->dtxfsts);
+	DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", ep->num, txstatus.d32);
+
+	while (txstatus.b.txfspcavail > dwords &&
+	       ep->xfer_count < ep->xfer_len && ep->xfer_len != 0) {
+		/* Write the FIFO */
+		dwc_otg_ep_write_packet(core_if, ep, 0);
+
+		len = ep->xfer_len - ep->xfer_count;
+		if (len > ep->maxpacket) {
+			len = ep->maxpacket;
+		}
+
+		dwords = (len + 3) / 4;
+		txstatus.d32 =
+		    dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]->
+				   dtxfsts);
+		DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", ep->num,
+			    txstatus.d32);
+	}
+}
+
+/**
+ * This function initializes a descriptor chain for Isochronous transfer
+ *
+ * @param core_if Programming view of DWC_otg controller.
+ * @param ep The EP to start the transfer on.
+ *
+ */
+void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t * core_if,
+				       dwc_ep_t * ep)
+{
+	deptsiz_data_t deptsiz = {.d32 = 0 };
+	depctl_data_t depctl = {.d32 = 0 };
+	dsts_data_t dsts = {.d32 = 0 };
+	volatile uint32_t *addr;
+
+	if (ep->is_in) {
+		addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
+	} else {
+		addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
+	}
+
+	ep->xfer_len = ep->data_per_frame;
+	ep->xfer_count = 0;
+	ep->xfer_buff = ep->cur_pkt_addr;
+	ep->dma_addr = ep->cur_pkt_dma_addr;
+
+	if (ep->is_in) {
+		/* Program the transfer size and packet count
+		 *      as follows: xfersize = N * maxpacket +
+		 *      short_packet pktcnt = N + (short_packet
+		 *      exist ? 1 : 0)  
+		 */
+		deptsiz.b.xfersize = ep->xfer_len;
+		deptsiz.b.pktcnt =
+		    (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket;
+		deptsiz.b.mc = deptsiz.b.pktcnt;
+		dwc_write_reg32(&core_if->dev_if->in_ep_regs[ep->num]->dieptsiz,
+				deptsiz.d32);
+
+		/* Write the DMA register */
+		if (core_if->dma_enable) {
+			dwc_write_reg32(&
+					(core_if->dev_if->in_ep_regs[ep->num]->
+					 diepdma), (uint32_t) ep->dma_addr);
+		}
+	} else {
+		deptsiz.b.pktcnt =
+		    (ep->xfer_len + (ep->maxpacket - 1)) / ep->maxpacket;
+		deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
+
+		dwc_write_reg32(&core_if->dev_if->out_ep_regs[ep->num]->
+				doeptsiz, deptsiz.d32);
+
+		if (core_if->dma_enable) {
+			dwc_write_reg32(&
+					(core_if->dev_if->out_ep_regs[ep->num]->
+					 doepdma), (uint32_t) ep->dma_addr);
+		}
+	}
+
+	/** Enable endpoint, clear nak  */
+
+	depctl.d32 = 0;
+	if (ep->bInterval == 1) {
+		dsts.d32 =
+		    dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
+		ep->next_frame = dsts.b.soffn + ep->bInterval;
+
+		if (ep->next_frame & 0x1) {
+			depctl.b.setd1pid = 1;
+		} else {
+			depctl.b.setd0pid = 1;
+		}
+	} else {
+		ep->next_frame += ep->bInterval;
+
+		if (ep->next_frame & 0x1) {
+			depctl.b.setd1pid = 1;
+		} else {
+			depctl.b.setd0pid = 1;
+		}
+	}
+	depctl.b.epena = 1;
+	depctl.b.cnak = 1;
+
+	dwc_modify_reg32(addr, 0, depctl.d32);
+	depctl.d32 = dwc_read_reg32(addr);
+
+	if (ep->is_in && core_if->dma_enable == 0) {
+		write_isoc_frame_data(core_if, ep);
+	}
+
+}
+#endif				/* DWC_EN_ISOC */
+
+static void dwc_otg_set_uninitialized(int32_t * p, int size)
+{
+	int i;
+	for (i = 0; i < size; i++) {
+		p[i] = -1;
+	}
+}
+
+static int dwc_otg_param_initialized(int32_t val)
+{
+	return val != -1;
+}
+
+static int dwc_otg_setup_params(dwc_otg_core_if_t * core_if)
+{
+	int i;
+	core_if->core_params = DWC_ALLOC(sizeof(*core_if->core_params));
+	if (!core_if->core_params) {
+		return -DWC_E_NO_MEMORY;
+	}
+	dwc_otg_set_uninitialized((int32_t *) core_if->core_params,
+				  sizeof(*core_if->core_params) /
+				  sizeof(int32_t));
+	DWC_PRINTF("Setting default values for core params\n");
+	dwc_otg_set_param_otg_cap(core_if, dwc_param_otg_cap_default);
+	dwc_otg_set_param_dma_enable(core_if, dwc_param_dma_enable_default);
+	dwc_otg_set_param_dma_desc_enable(core_if,
+					  dwc_param_dma_desc_enable_default);
+	dwc_otg_set_param_opt(core_if, dwc_param_opt_default);
+	dwc_otg_set_param_dma_burst_size(core_if,
+					 dwc_param_dma_burst_size_default);
+	dwc_otg_set_param_host_support_fs_ls_low_power(core_if,
+						       dwc_param_host_support_fs_ls_low_power_default);
+	dwc_otg_set_param_enable_dynamic_fifo(core_if,
+					      dwc_param_enable_dynamic_fifo_default);
+	dwc_otg_set_param_data_fifo_size(core_if,
+					 dwc_param_data_fifo_size_default);
+	dwc_otg_set_param_dev_rx_fifo_size(core_if,
+					   dwc_param_dev_rx_fifo_size_default);
+	dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if,
+						  dwc_param_dev_nperio_tx_fifo_size_default);
+	dwc_otg_set_param_host_rx_fifo_size(core_if,
+					    dwc_param_host_rx_fifo_size_default);
+	dwc_otg_set_param_host_nperio_tx_fifo_size(core_if,
+						   dwc_param_host_nperio_tx_fifo_size_default);
+	dwc_otg_set_param_host_perio_tx_fifo_size(core_if,
+						  dwc_param_host_perio_tx_fifo_size_default);
+	dwc_otg_set_param_max_transfer_size(core_if,
+					    dwc_param_max_transfer_size_default);
+	dwc_otg_set_param_max_packet_count(core_if,
+					   dwc_param_max_packet_count_default);
+	dwc_otg_set_param_host_channels(core_if,
+					dwc_param_host_channels_default);
+	dwc_otg_set_param_dev_endpoints(core_if,
+					dwc_param_dev_endpoints_default);
+	dwc_otg_set_param_phy_type(core_if, dwc_param_phy_type_default);
+	dwc_otg_set_param_speed(core_if, dwc_param_speed_default);
+	dwc_otg_set_param_host_ls_low_power_phy_clk(core_if,
+						    dwc_param_host_ls_low_power_phy_clk_default);
+	dwc_otg_set_param_phy_ulpi_ddr(core_if, dwc_param_phy_ulpi_ddr_default);
+	dwc_otg_set_param_phy_ulpi_ext_vbus(core_if,
+					    dwc_param_phy_ulpi_ext_vbus_default);
+	dwc_otg_set_param_phy_utmi_width(core_if,
+					 dwc_param_phy_utmi_width_default);
+	dwc_otg_set_param_ts_dline(core_if, dwc_param_ts_dline_default);
+	dwc_otg_set_param_i2c_enable(core_if, dwc_param_i2c_enable_default);
+	dwc_otg_set_param_ulpi_fs_ls(core_if, dwc_param_ulpi_fs_ls_default);
+	dwc_otg_set_param_en_multiple_tx_fifo(core_if,
+					      dwc_param_en_multiple_tx_fifo_default);
+	for (i = 0; i < 15; i++) {
+		dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
+							 dwc_param_dev_perio_tx_fifo_size_default,
+							 i);
+	}
+
+	for (i = 0; i < 15; i++) {
+		dwc_otg_set_param_dev_tx_fifo_size(core_if,
+						   dwc_param_dev_tx_fifo_size_default,
+						   i);
+	}
+	dwc_otg_set_param_thr_ctl(core_if, dwc_param_thr_ctl_default);
+	dwc_otg_set_param_mpi_enable(core_if, dwc_param_mpi_enable_default);
+	dwc_otg_set_param_pti_enable(core_if, dwc_param_pti_enable_default);
+	dwc_otg_set_param_lpm_enable(core_if, dwc_param_lpm_enable_default);
+	dwc_otg_set_param_ic_usb_cap(core_if, dwc_param_ic_usb_cap_default);
+	dwc_otg_set_param_tx_thr_length(core_if,
+					dwc_param_tx_thr_length_default);
+	dwc_otg_set_param_rx_thr_length(core_if,
+					dwc_param_rx_thr_length_default);
+	dwc_otg_set_param_ahb_thr_ratio(core_if, dwc_param_ahb_thr_ratio_default);
+	DWC_PRINTF("Finished setting default values for core params\n");
+	return 0;
+}
+
+uint8_t dwc_otg_is_dma_enable(dwc_otg_core_if_t * core_if)
+{
+	return core_if->dma_enable;
+}
+
+/* Checks if the parameter is outside of its valid range of values */
+#define DWC_OTG_PARAM_TEST(_param_, _low_, _high_) \
+		(((_param_) < (_low_)) || \
+		((_param_) > (_high_)))
+
+/* Parameter access functions */
+int dwc_otg_set_param_otg_cap(dwc_otg_core_if_t * core_if, int32_t val)
+{
+	int valid;
+	int retval = 0;
+	if (DWC_OTG_PARAM_TEST(val, 0, 2)) {
+		DWC_WARN("Wrong value for otg_cap parameter\n");
+		DWC_WARN("otg_cap parameter must be 0,1 or 2\n");
+		retval = -DWC_E_INVALID;
+		goto out;
+	}
+
+	valid = 1;
+	switch (val) {
+	case DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE:
+		if (core_if->hwcfg2.b.op_mode !=
+		    DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
+			valid = 0;
+		break;
+	case DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE:
+		if ((core_if->hwcfg2.b.op_mode !=
+		     DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
+		    && (core_if->hwcfg2.b.op_mode !=
+			DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG)
+		    && (core_if->hwcfg2.b.op_mode !=
+			DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE)
+		    && (core_if->hwcfg2.b.op_mode !=
+		      DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) {
+			valid = 0;
+		}
+		break;
+	case DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE:
+		/* always valid */
+		break;
+	}
+	if (!valid) {
+		if (dwc_otg_param_initialized(core_if->core_params->otg_cap)) {
+			DWC_ERROR
+			    ("%d invalid for otg_cap paremter. Check HW configuration.\n",
+			     val);
+		}
+		val =
+		    (((core_if->hwcfg2.b.op_mode ==
+		       DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
+		      || (core_if->hwcfg2.b.op_mode ==
+			  DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG)
+		      || (core_if->hwcfg2.b.op_mode ==
+			  DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE)
+		      || (core_if->hwcfg2.b.op_mode ==
+			  DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) ?
+		     DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE :
+		     DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
+		retval = -DWC_E_INVALID;
+	}
+
+	core_if->core_params->otg_cap = val;
+      out:
+	return retval;
+}
+
+int32_t dwc_otg_get_param_otg_cap(dwc_otg_core_if_t * core_if)
+{
+	return core_if->core_params->otg_cap;
+}
+
+int dwc_otg_set_param_opt(dwc_otg_core_if_t * core_if, int32_t val)
+{
+	if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+		DWC_WARN("Wrong value for opt parameter\n");
+		return -DWC_E_INVALID;
+	}
+	core_if->core_params->opt = val;
+	return 0;
+}
+
+int32_t dwc_otg_get_param_opt(dwc_otg_core_if_t * core_if)
+{
+	return core_if->core_params->opt;
+}
+
+int dwc_otg_set_param_dma_enable(dwc_otg_core_if_t * core_if, int32_t val)
+{
+	int retval = 0;
+	if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+		DWC_WARN("Wrong value for dma enable\n");
+		return -DWC_E_INVALID;
+	}
+
+	if ((val == 1) && (core_if->hwcfg2.b.architecture == 0)) {
+		if (dwc_otg_param_initialized(core_if->core_params->dma_enable)) {
+			DWC_ERROR
+			    ("%d invalid for dma_enable paremter. Check HW configuration.\n",
+			     val);
+		}
+		val = 0;
+		retval = -DWC_E_INVALID;
+	}
+
+	core_if->core_params->dma_enable = val;
+	if (val == 0) {
+		dwc_otg_set_param_dma_desc_enable(core_if, 0);
+	}
+	return retval;
+}
+
+int32_t dwc_otg_get_param_dma_enable(dwc_otg_core_if_t * core_if)
+{
+	return core_if->core_params->dma_enable;
+}
+
+int dwc_otg_set_param_dma_desc_enable(dwc_otg_core_if_t * core_if, int32_t val)
+{
+	int retval = 0;
+	if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+		DWC_WARN("Wrong value for dma_enable\n");
+		DWC_WARN("dma_desc_enable must be 0 or 1\n");
+		return -DWC_E_INVALID;
+	}
+
+	if ((val == 1)
+	    && ((dwc_otg_get_param_dma_enable(core_if) == 0)
+		|| (core_if->hwcfg4.b.desc_dma == 0))) {
+		if (dwc_otg_param_initialized
+		    (core_if->core_params->dma_desc_enable)) {
+			DWC_ERROR
+			    ("%d invalid for dma_desc_enable paremter. Check HW configuration.\n",
+			     val);
+		}
+		val = 0;
+		retval = -DWC_E_INVALID;
+	}
+	core_if->core_params->dma_desc_enable = val;
+	return retval;
+}
+
+int32_t dwc_otg_get_param_dma_desc_enable(dwc_otg_core_if_t * core_if)
+{
+	return core_if->core_params->dma_desc_enable;
+}
+
+int dwc_otg_set_param_host_support_fs_ls_low_power(dwc_otg_core_if_t * core_if,
+						   int32_t val)
+{
+	if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+		DWC_WARN("Wrong value for host_support_fs_low_power\n");
+		DWC_WARN("host_support_fs_low_power must be 0 or 1\n");
+		return -DWC_E_INVALID;
+	}
+	core_if->core_params->host_support_fs_ls_low_power = val;
+	return 0;
+}
+
+int32_t dwc_otg_get_param_host_support_fs_ls_low_power(dwc_otg_core_if_t *
+						       core_if)
+{
+	return core_if->core_params->host_support_fs_ls_low_power;
+}
+
+int dwc_otg_set_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if,
+					  int32_t val)
+{
+	int retval = 0;
+	if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+		DWC_WARN("Wrong value for enable_dynamic_fifo\n");
+		DWC_WARN("enable_dynamic_fifo must be 0 or 1\n");
+		return -DWC_E_INVALID;
+	}
+
+	if ((val == 1) && (core_if->hwcfg2.b.dynamic_fifo == 0)) {
+		if (dwc_otg_param_initialized
+		    (core_if->core_params->enable_dynamic_fifo)) {
+			DWC_ERROR
+			    ("%d invalid for enable_dynamic_fifo paremter. Check HW configuration.\n",
+			     val);
+		}
+		val = 0;
+		retval = -DWC_E_INVALID;
+	}
+	core_if->core_params->enable_dynamic_fifo = val;
+	return retval;
+}
+
+int32_t dwc_otg_get_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if)
+{
+	return core_if->core_params->enable_dynamic_fifo;
+}
+
+int dwc_otg_set_param_data_fifo_size(dwc_otg_core_if_t * core_if, int32_t val)
+{
+	int retval = 0;
+	if (DWC_OTG_PARAM_TEST(val, 32, 32768)) {
+		DWC_WARN("Wrong value for data_fifo_size\n");
+		DWC_WARN("data_fifo_size must be 32-32768\n");
+		return -DWC_E_INVALID;
+	}
+
+	if (val > core_if->hwcfg3.b.dfifo_depth) {
+		if (dwc_otg_param_initialized
+		    (core_if->core_params->data_fifo_size)) {
+			DWC_ERROR
+			    ("%d invalid for data_fifo_size parameter. Check HW configuration.\n",
+			     val);
+		}
+		val = core_if->hwcfg3.b.dfifo_depth;
+		retval = -DWC_E_INVALID;
+	}
+
+	core_if->core_params->data_fifo_size = val;
+	return retval;
+}
+
+int32_t dwc_otg_get_param_data_fifo_size(dwc_otg_core_if_t * core_if)
+{
+	return core_if->core_params->data_fifo_size;
+}
+
+int dwc_otg_set_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if, int32_t val)
+{
+	int retval = 0;
+	if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
+		DWC_WARN("Wrong value for dev_rx_fifo_size\n");
+		DWC_WARN("dev_rx_fifo_size must be 16-32768\n");
+		return -DWC_E_INVALID;
+	}
+
+	if (val > dwc_read_reg32(&core_if->core_global_regs->grxfsiz)) {
+		if(dwc_otg_param_initialized(core_if->core_params->dev_rx_fifo_size)) {
+		DWC_WARN("%d invalid for dev_rx_fifo_size parameter\n", val);
+		}
+		val = dwc_read_reg32(&core_if->core_global_regs->grxfsiz);
+		retval = -DWC_E_INVALID;
+	}
+
+	core_if->core_params->dev_rx_fifo_size = val;
+	return retval;
+}
+
+int32_t dwc_otg_get_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if)
+{
+	return core_if->core_params->dev_rx_fifo_size;
+}
+
+int dwc_otg_set_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if,
+					      int32_t val)
+{
+	int retval = 0;
+
+	if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
+		DWC_WARN("Wrong value for dev_nperio_tx_fifo\n");
+		DWC_WARN("dev_nperio_tx_fifo must be 16-32768\n");
+		return -DWC_E_INVALID;
+	}
+
+	if (val > (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)) {
+		if (dwc_otg_param_initialized
+		    (core_if->core_params->dev_nperio_tx_fifo_size)) {
+			DWC_ERROR
+			    ("%d invalid for dev_nperio_tx_fifo_size. Check HW configuration.\n",
+			     val);
+		}
+		val =
+		    (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >>
+		     16);
+		retval = -DWC_E_INVALID;
+	}
+
+	core_if->core_params->dev_nperio_tx_fifo_size = val;
+	return retval;
+}
+
+int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if)
+{
+	return core_if->core_params->dev_nperio_tx_fifo_size;
+}
+
+int dwc_otg_set_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if,
+					int32_t val)
+{
+	int retval = 0;
+
+	if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
+		DWC_WARN("Wrong value for host_rx_fifo_size\n");
+		DWC_WARN("host_rx_fifo_size must be 16-32768\n");
+		return -DWC_E_INVALID;
+	}
+
+	if (val > dwc_read_reg32(&core_if->core_global_regs->grxfsiz)) {
+		if (dwc_otg_param_initialized
+		    (core_if->core_params->host_rx_fifo_size)) {
+			DWC_ERROR
+			    ("%d invalid for host_rx_fifo_size. Check HW configuration.\n",
+			     val);
+		}
+		val = dwc_read_reg32(&core_if->core_global_regs->grxfsiz);
+		retval = -DWC_E_INVALID;
+	}
+
+	core_if->core_params->host_rx_fifo_size = val;
+	return retval;
+
+}
+
+int32_t dwc_otg_get_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if)
+{
+	return core_if->core_params->host_rx_fifo_size;
+}
+
+int dwc_otg_set_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if,
+					       int32_t val)
+{
+	int retval = 0;
+
+	if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
+		DWC_WARN("Wrong value for host_nperio_tx_fifo_size\n");
+		DWC_WARN("host_nperio_tx_fifo_size must be 16-32768\n");
+		return -DWC_E_INVALID;
+	}
+
+	if (val > (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)) {
+		if (dwc_otg_param_initialized
+		    (core_if->core_params->host_nperio_tx_fifo_size)) {
+			DWC_ERROR
+			    ("%d invalid for host_nperio_tx_fifo_size. Check HW configuration.\n",
+			     val);
+		}
+		val =
+		    (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >>
+		     16);
+		retval = -DWC_E_INVALID;
+	}
+
+	core_if->core_params->host_nperio_tx_fifo_size = val;
+	return retval;
+}
+
+int32_t dwc_otg_get_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if)
+{
+	return core_if->core_params->host_nperio_tx_fifo_size;
+}
+
+int dwc_otg_set_param_host_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
+					      int32_t val)
+{
+	int retval = 0;
+	if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
+		DWC_WARN("Wrong value for host_perio_tx_fifo_size\n");
+		DWC_WARN("host_perio_tx_fifo_size must be 16-32768\n");
+		return -DWC_E_INVALID;
+	}
+
+	if (val >
+	    ((dwc_read_reg32(&core_if->core_global_regs->hptxfsiz) >> 16))) {
+		if (dwc_otg_param_initialized
+		    (core_if->core_params->host_perio_tx_fifo_size)) {
+			DWC_ERROR
+			    ("%d invalid for host_perio_tx_fifo_size. Check HW configuration.\n",
+			     val);
+		}
+		val =
+		    (dwc_read_reg32(&core_if->core_global_regs->hptxfsiz) >>
+		     16);
+		retval = -DWC_E_INVALID;
+	}
+
+	core_if->core_params->host_perio_tx_fifo_size = val;
+	return retval;
+}
+
+int32_t dwc_otg_get_param_host_perio_tx_fifo_size(dwc_otg_core_if_t * core_if)
+{
+	return core_if->core_params->host_perio_tx_fifo_size;
+}
+
+int dwc_otg_set_param_max_transfer_size(dwc_otg_core_if_t * core_if,
+					int32_t val)
+{
+	int retval = 0;
+
+	if (DWC_OTG_PARAM_TEST(val, 2047, 524288)) {
+		DWC_WARN("Wrong value for max_transfer_size\n");
+		DWC_WARN("max_transfer_size must be 2047-524288\n");
+		return -DWC_E_INVALID;
+	}
+
+	if (val >= (1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11))) {
+		if (dwc_otg_param_initialized
+		    (core_if->core_params->max_transfer_size)) {
+			DWC_ERROR
+			    ("%d invalid for max_transfer_size. Check HW configuration.\n",
+			     val);
+		}
+		val =
+		    ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 11)) -
+		     1);
+		retval = -DWC_E_INVALID;
+	}
+
+	core_if->core_params->max_transfer_size = val;
+	return retval;
+}
+
+int32_t dwc_otg_get_param_max_transfer_size(dwc_otg_core_if_t * core_if)
+{
+	return core_if->core_params->max_transfer_size;
+}
+
+int dwc_otg_set_param_max_packet_count(dwc_otg_core_if_t * core_if, int32_t val)
+{
+	int retval = 0;
+
+	if (DWC_OTG_PARAM_TEST(val, 15, 511)) {
+		DWC_WARN("Wrong value for max_packet_count\n");
+		DWC_WARN("max_packet_count must be 15-511\n");
+		return -DWC_E_INVALID;
+	}
+
+	if (val > (1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4))) {
+		if (dwc_otg_param_initialized
+		    (core_if->core_params->max_packet_count)) {
+			DWC_ERROR
+			    ("%d invalid for max_packet_count. Check HW configuration.\n",
+			     val);
+		}
+		val =
+		    ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1);
+		retval = -DWC_E_INVALID;
+	}
+
+	core_if->core_params->max_packet_count = val;
+	return retval;
+}
+
+int32_t dwc_otg_get_param_max_packet_count(dwc_otg_core_if_t * core_if)
+{
+	return core_if->core_params->max_packet_count;
+}
+
+int dwc_otg_set_param_host_channels(dwc_otg_core_if_t * core_if, int32_t val)
+{
+	int retval = 0;
+
+	if (DWC_OTG_PARAM_TEST(val, 1, 16)) {
+		DWC_WARN("Wrong value for host_channels\n");
+		DWC_WARN("host_channels must be 1-16\n");
+		return -DWC_E_INVALID;
+	}
+
+	if (val > (core_if->hwcfg2.b.num_host_chan + 1)) {
+		if (dwc_otg_param_initialized
+		    (core_if->core_params->host_channels)) {
+			DWC_ERROR
+			    ("%d invalid for host_channels. Check HW configurations.\n",
+			     val);
+		}
+		val = (core_if->hwcfg2.b.num_host_chan + 1);
+		retval = -DWC_E_INVALID;
+	}
+
+	core_if->core_params->host_channels = val;
+	return retval;
+}
+
+int32_t dwc_otg_get_param_host_channels(dwc_otg_core_if_t * core_if)
+{
+	return core_if->core_params->host_channels;
+}
+
+int dwc_otg_set_param_dev_endpoints(dwc_otg_core_if_t * core_if, int32_t val)
+{
+	int retval = 0;
+
+	if (DWC_OTG_PARAM_TEST(val, 1, 15)) {
+		DWC_WARN("Wrong value for dev_endpoints\n");
+		DWC_WARN("dev_endpoints must be 1-15\n");
+		return -DWC_E_INVALID;
+	}
+
+	if (val > (core_if->hwcfg2.b.num_dev_ep)) {
+		if (dwc_otg_param_initialized
+		    (core_if->core_params->dev_endpoints)) {
+			DWC_ERROR
+			    ("%d invalid for dev_endpoints. Check HW configurations.\n",
+			     val);
+		}
+		val = core_if->hwcfg2.b.num_dev_ep;
+		retval = -DWC_E_INVALID;
+	}
+
+	core_if->core_params->dev_endpoints = val;
+	return retval;
+}
+
+int32_t dwc_otg_get_param_dev_endpoints(dwc_otg_core_if_t * core_if)
+{
+	return core_if->core_params->dev_endpoints;
+}
+
+int dwc_otg_set_param_phy_type(dwc_otg_core_if_t * core_if, int32_t val)
+{
+	int retval = 0;
+	int valid = 0;
+
+	if (DWC_OTG_PARAM_TEST(val, 0, 2)) {
+		DWC_WARN("Wrong value for phy_type\n");
+		DWC_WARN("phy_type must be 0,1 or 2\n");
+		return -DWC_E_INVALID;
+	}
+#ifndef NO_FS_PHY_HW_CHECKS
+	if ((val == DWC_PHY_TYPE_PARAM_UTMI) &&
+	    ((core_if->hwcfg2.b.hs_phy_type == 1) ||
+	     (core_if->hwcfg2.b.hs_phy_type == 3))) {
+		valid = 1;
+	} else if ((val == DWC_PHY_TYPE_PARAM_ULPI) &&
+		   ((core_if->hwcfg2.b.hs_phy_type == 2) ||
+		    (core_if->hwcfg2.b.hs_phy_type == 3))) {
+		valid = 1;
+	} else if ((val == DWC_PHY_TYPE_PARAM_FS) &&
+		   (core_if->hwcfg2.b.fs_phy_type == 1)) {
+		valid = 1;
+	}
+	if (!valid) {
+		if (dwc_otg_param_initialized(core_if->core_params->phy_type)) {
+			DWC_ERROR
+			    ("%d invalid for phy_type. Check HW configurations.\n",
+			     val);
+		}
+		if (core_if->hwcfg2.b.hs_phy_type) {
+			if ((core_if->hwcfg2.b.hs_phy_type == 3) ||
+			    (core_if->hwcfg2.b.hs_phy_type == 1)) {
+				val = DWC_PHY_TYPE_PARAM_UTMI;
+			} else {
+				val = DWC_PHY_TYPE_PARAM_ULPI;
+			}
+		}
+		retval = -DWC_E_INVALID;
+	}
+#endif
+	core_if->core_params->phy_type = val;
+	return retval;
+}
+
+int32_t dwc_otg_get_param_phy_type(dwc_otg_core_if_t * core_if)
+{
+	return core_if->core_params->phy_type;
+}
+
+int dwc_otg_set_param_speed(dwc_otg_core_if_t * core_if, int32_t val)
+{
+	int retval = 0;
+	if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+		DWC_WARN("Wrong value for speed parameter\n");
+		DWC_WARN("max_speed parameter must be 0 or 1\n");
+		return -DWC_E_INVALID;
+	}
+	if ((val == 0)
+	    && dwc_otg_get_param_phy_type(core_if) == DWC_PHY_TYPE_PARAM_FS) {
+		if (dwc_otg_param_initialized(core_if->core_params->speed)) {
+			DWC_ERROR
+			    ("%d invalid for speed paremter. Check HW configuration.\n",
+			     val);
+		}
+		val =
+		    (dwc_otg_get_param_phy_type(core_if) ==
+		     DWC_PHY_TYPE_PARAM_FS ? 1 : 0);
+		retval = -DWC_E_INVALID;
+	}
+	core_if->core_params->speed = val;
+	return retval;
+}
+
+int32_t dwc_otg_get_param_speed(dwc_otg_core_if_t * core_if)
+{
+	return core_if->core_params->speed;
+}
+
+int dwc_otg_set_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t * core_if,
+						int32_t val)
+{
+	int retval = 0;
+
+	if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+		DWC_WARN
+		    ("Wrong value for host_ls_low_power_phy_clk parameter\n");
+		DWC_WARN("host_ls_low_power_phy_clk must be 0 or 1\n");
+		return -DWC_E_INVALID;
+	}
+
+	if ((val == DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ)
+	    && (dwc_otg_get_param_phy_type(core_if) == DWC_PHY_TYPE_PARAM_FS)) {
+		if(dwc_otg_param_initialized(core_if->core_params->host_ls_low_power_phy_clk)) {
+			DWC_ERROR("%d invalid for host_ls_low_power_phy_clk. Check HW configuration.\n",
+		     val);
+		}
+		val =
+		    (dwc_otg_get_param_phy_type(core_if) ==
+		     DWC_PHY_TYPE_PARAM_FS) ?
+		    DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ :
+		    DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ;
+		retval = -DWC_E_INVALID;
+	}
+
+	core_if->core_params->host_ls_low_power_phy_clk = val;
+	return retval;
+}
+
+int32_t dwc_otg_get_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t * core_if)
+{
+	return core_if->core_params->host_ls_low_power_phy_clk;
+}
+
+int dwc_otg_set_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if, int32_t val)
+{
+	if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+		DWC_WARN("Wrong value for phy_ulpi_ddr\n");
+		DWC_WARN("phy_upli_ddr must be 0 or 1\n");
+		return -DWC_E_INVALID;
+	}
+
+	core_if->core_params->phy_ulpi_ddr = val;
+	return 0;
+}
+
+int32_t dwc_otg_get_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if)
+{
+	return core_if->core_params->phy_ulpi_ddr;
+}
+
+int dwc_otg_set_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if,
+					int32_t val)
+{
+	if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+		DWC_WARN("Wrong valaue for phy_ulpi_ext_vbus\n");
+		DWC_WARN("phy_ulpi_ext_vbus must be 0 or 1\n");
+		return -DWC_E_INVALID;
+	}
+
+	core_if->core_params->phy_ulpi_ext_vbus = val;
+	return 0;
+}
+
+int32_t dwc_otg_get_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if)
+{
+	return core_if->core_params->phy_ulpi_ext_vbus;
+}
+
+int dwc_otg_set_param_phy_utmi_width(dwc_otg_core_if_t * core_if, int32_t val)
+{
+	if (DWC_OTG_PARAM_TEST(val, 8, 8) && DWC_OTG_PARAM_TEST(val, 16, 16)) {
+		DWC_WARN("Wrong valaue for phy_utmi_width\n");
+		DWC_WARN("phy_utmi_width must be 8 or 16\n");
+		return -DWC_E_INVALID;
+	}
+
+	core_if->core_params->phy_utmi_width = val;
+	return 0;
+}
+
+int32_t dwc_otg_get_param_phy_utmi_width(dwc_otg_core_if_t * core_if)
+{
+	return core_if->core_params->phy_utmi_width;
+}
+
+int dwc_otg_set_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if, int32_t val)
+{
+	if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+		DWC_WARN("Wrong valaue for ulpi_fs_ls\n");
+		DWC_WARN("ulpi_fs_ls must be 0 or 1\n");
+		return -DWC_E_INVALID;
+	}
+
+	core_if->core_params->ulpi_fs_ls = val;
+	return 0;
+}
+
+int32_t dwc_otg_get_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if)
+{
+	return core_if->core_params->ulpi_fs_ls;
+}
+
+int dwc_otg_set_param_ts_dline(dwc_otg_core_if_t * core_if, int32_t val)
+{
+	if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+		DWC_WARN("Wrong valaue for ts_dline\n");
+		DWC_WARN("ts_dline must be 0 or 1\n");
+		return -DWC_E_INVALID;
+	}
+
+	core_if->core_params->ts_dline = val;
+	return 0;
+}
+
+int32_t dwc_otg_get_param_ts_dline(dwc_otg_core_if_t * core_if)
+{
+	return core_if->core_params->ts_dline;
+}
+
+int dwc_otg_set_param_i2c_enable(dwc_otg_core_if_t * core_if, int32_t val)
+{
+	int retval = 0;
+	if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+		DWC_WARN("Wrong valaue for i2c_enable\n");
+		DWC_WARN("i2c_enable must be 0 or 1\n");
+		return -DWC_E_INVALID;
+	}
+#ifndef NO_FS_PHY_HW_CHECK
+	if (val == 1 && core_if->hwcfg3.b.i2c == 0) {
+		if(dwc_otg_param_initialized(core_if->core_params->i2c_enable)) {
+			DWC_ERROR("%d invalid for i2c_enable. Check HW configuration.\n",
+		     val);
+		}
+		val = 0;
+		retval = -DWC_E_INVALID;
+	}
+#endif
+
+	core_if->core_params->i2c_enable = val;
+	return retval;
+}
+
+int32_t dwc_otg_get_param_i2c_enable(dwc_otg_core_if_t * core_if)
+{
+	return core_if->core_params->i2c_enable;
+}
+
+int dwc_otg_set_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
+					     int32_t val, int fifo_num)
+{
+	int retval = 0;
+
+	if (DWC_OTG_PARAM_TEST(val, 4, 768)) {
+		DWC_WARN("Wrong value for dev_perio_tx_fifo_size\n");
+		DWC_WARN("dev_perio_tx_fifo_size must be 4-768\n");
+		return -DWC_E_INVALID;
+	}
+
+	if (val > (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[fifo_num]))) {
+		if(dwc_otg_param_initialized(core_if->core_params->dev_perio_tx_fifo_size[fifo_num])) {
+			DWC_ERROR("`%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n",
+		     val, fifo_num);
+		}
+		val = (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[fifo_num]));
+		retval = -DWC_E_INVALID;
+	}
+
+	core_if->core_params->dev_perio_tx_fifo_size[fifo_num] = val;
+	return retval;
+}
+
+int32_t dwc_otg_get_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
+						 int fifo_num)
+{
+	return core_if->core_params->dev_perio_tx_fifo_size[fifo_num];
+}
+
+int dwc_otg_set_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if,
+					  int32_t val)
+{
+	int retval = 0;
+	if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+		DWC_WARN("Wrong valaue for en_multiple_tx_fifo,\n");
+		DWC_WARN("en_multiple_tx_fifo must be 0 or 1\n");
+		return -DWC_E_INVALID;
+	}
+
+	if (val == 1 && core_if->hwcfg4.b.ded_fifo_en == 0) {
+		if(dwc_otg_param_initialized(core_if->core_params->en_multiple_tx_fifo)) {
+			DWC_ERROR("%d invalid for parameter en_multiple_tx_fifo. Check HW configuration.\n",
+		     val);
+		}
+		val = 0;
+		retval = -DWC_E_INVALID;
+	}
+
+	core_if->core_params->en_multiple_tx_fifo = val;
+	return retval;
+}
+
+int32_t dwc_otg_get_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if)
+{
+	return core_if->core_params->en_multiple_tx_fifo;
+}
+
+int dwc_otg_set_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if, int32_t val,
+				       int fifo_num)
+{
+	int retval = 0;
+
+	if (DWC_OTG_PARAM_TEST(val, 4, 768)) {
+		DWC_WARN("Wrong value for dev_tx_fifo_size\n");
+		DWC_WARN("dev_tx_fifo_size must be 4-768\n");
+		return -DWC_E_INVALID;
+	}
+
+	if (val > (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[fifo_num]))) {
+		if(dwc_otg_param_initialized(core_if->core_params->dev_tx_fifo_size[fifo_num])) {
+			DWC_ERROR("`%d' invalid for parameter `dev_tx_fifo_size_%d'. Check HW configuration.\n",
+		     val, fifo_num);
+		}
+		val = (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[fifo_num]));
+		retval = -DWC_E_INVALID;
+	}
+
+	core_if->core_params->dev_tx_fifo_size[fifo_num] = val;
+	return retval;
+}
+
+int32_t dwc_otg_get_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if,
+					   int fifo_num)
+{
+	return core_if->core_params->dev_tx_fifo_size[fifo_num];
+}
+
+int dwc_otg_set_param_thr_ctl(dwc_otg_core_if_t * core_if, int32_t val)
+{
+	int retval = 0;
+
+	if (DWC_OTG_PARAM_TEST(val, 0, 7)) {
+		DWC_WARN("Wrong value for thr_ctl\n");
+		DWC_WARN("thr_ctl must be 0-7\n");
+		return -DWC_E_INVALID;
+	}
+
+	if ((val != 0) &&
+	    (!dwc_otg_get_param_dma_enable(core_if) ||
+	     !core_if->hwcfg4.b.ded_fifo_en)) {
+		if(dwc_otg_param_initialized(core_if->core_params->thr_ctl)) {
+			DWC_ERROR("%d invalid for parameter thr_ctl. Check HW configuration.\n",
+		     val);
+		}
+		val = 0;
+		retval = -DWC_E_INVALID;
+	}
+
+	core_if->core_params->thr_ctl = val;
+	return retval;
+}
+
+int32_t dwc_otg_get_param_thr_ctl(dwc_otg_core_if_t * core_if)
+{
+	return core_if->core_params->thr_ctl;
+}
+
+int dwc_otg_set_param_lpm_enable(dwc_otg_core_if_t * core_if, int32_t val)
+{
+	int retval = 0;
+
+	if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+		DWC_WARN("Wrong value for lpm_enable\n");
+		DWC_WARN("lpm_enable must be 0 or 1\n");
+		return -DWC_E_INVALID;
+	}
+
+	if (val && !core_if->hwcfg3.b.otg_lpm_en) {
+		if(dwc_otg_param_initialized(core_if->core_params->lpm_enable)) {
+			DWC_ERROR("%d invalid for parameter lpm_enable. Check HW configuration.\n",
+		     val);
+		}
+		val = 0;
+		retval = -DWC_E_INVALID;
+	}
+
+	core_if->core_params->lpm_enable = val;
+	return retval;
+}
+
+int32_t dwc_otg_get_param_lpm_enable(dwc_otg_core_if_t * core_if)
+{
+	return core_if->core_params->lpm_enable;
+}
+
+int dwc_otg_set_param_tx_thr_length(dwc_otg_core_if_t * core_if, int32_t val)
+{
+	if (DWC_OTG_PARAM_TEST(val, 8, 128)) {
+		DWC_WARN("Wrong valaue for tx_thr_length\n");
+		DWC_WARN("tx_thr_length must be 8 - 128\n");
+		return -DWC_E_INVALID;
+	}
+
+	core_if->core_params->tx_thr_length = val;
+	return 0;
+}
+
+int32_t dwc_otg_get_param_tx_thr_length(dwc_otg_core_if_t * core_if)
+{
+	return core_if->core_params->tx_thr_length;
+}
+
+int dwc_otg_set_param_rx_thr_length(dwc_otg_core_if_t * core_if, int32_t val)
+{
+	if (DWC_OTG_PARAM_TEST(val, 8, 128)) {
+		DWC_WARN("Wrong valaue for rx_thr_length\n");
+		DWC_WARN("rx_thr_length must be 8 - 128\n");
+		return -DWC_E_INVALID;
+	}
+
+	core_if->core_params->rx_thr_length = val;
+	return 0;
+}
+
+int32_t dwc_otg_get_param_rx_thr_length(dwc_otg_core_if_t * core_if)
+{
+	return core_if->core_params->rx_thr_length;
+}
+
+int dwc_otg_set_param_dma_burst_size(dwc_otg_core_if_t * core_if, int32_t val)
+{
+	if (DWC_OTG_PARAM_TEST(val, 1, 1) &&
+	    DWC_OTG_PARAM_TEST(val, 4, 4) &&
+	    DWC_OTG_PARAM_TEST(val, 8, 8) &&
+	    DWC_OTG_PARAM_TEST(val, 16, 16) &&
+	    DWC_OTG_PARAM_TEST(val, 32, 32) &&
+	    DWC_OTG_PARAM_TEST(val, 64, 64) &&
+	    DWC_OTG_PARAM_TEST(val, 128, 128) &&
+	    DWC_OTG_PARAM_TEST(val, 256, 256)) {
+		DWC_WARN("`%d' invalid for parameter `dma_burst_size'\n", val);
+		return -DWC_E_INVALID;
+	}
+	core_if->core_params->dma_burst_size = val;
+	return 0;
+}
+
+int32_t dwc_otg_get_param_dma_burst_size(dwc_otg_core_if_t * core_if)
+{
+	return core_if->core_params->dma_burst_size;
+}
+
+int dwc_otg_set_param_pti_enable(dwc_otg_core_if_t * core_if, int32_t val)
+{
+	int retval = 0;
+	if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+		DWC_WARN("`%d' invalid for parameter `pti_enable'\n", val);
+		return -DWC_E_INVALID;
+	}
+	if (val && (core_if->snpsid < OTG_CORE_REV_2_72a)) {
+		if (dwc_otg_param_initialized(core_if->core_params->pti_enable)) {
+			DWC_ERROR("%d invalid for parameter pti_enable. Check HW configuration.\n",
+			     val);
+		}
+		retval = -DWC_E_INVALID;
+		val = 0;
+	}
+	core_if->core_params->pti_enable = val;
+	return retval;
+}
+
+int32_t dwc_otg_get_param_pti_enable(dwc_otg_core_if_t * core_if)
+{
+	return core_if->core_params->pti_enable;
+}
+
+int dwc_otg_set_param_mpi_enable(dwc_otg_core_if_t * core_if, int32_t val)
+{
+	int retval = 0;
+	if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+		DWC_WARN("`%d' invalid for parameter `mpi_enable'\n", val);
+		return -DWC_E_INVALID;
+	}
+	if (val && (core_if->hwcfg2.b.multi_proc_int == 0)) {
+		if (dwc_otg_param_initialized(core_if->core_params->mpi_enable)) {
+			DWC_ERROR("%d invalid for parameter mpi_enable. Check HW configuration.\n",
+			     val);
+		}
+		retval = -DWC_E_INVALID;
+		val = 0;
+	}
+	core_if->core_params->mpi_enable = val;
+	return retval;
+}
+
+int32_t dwc_otg_get_param_mpi_enable(dwc_otg_core_if_t * core_if)
+{
+	return core_if->core_params->mpi_enable;
+}
+
+int dwc_otg_set_param_ic_usb_cap(dwc_otg_core_if_t * core_if,
+					int32_t val)
+{
+	int retval = 0;
+	if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+		DWC_WARN("`%d' invalid for parameter `ic_usb_cap'\n", val);
+		DWC_WARN("ic_usb_cap must be 0 or 1\n");
+		return -DWC_E_INVALID;
+	}
+
+	if (val && (core_if->hwcfg3.b.otg_enable_ic_usb == 0)) {
+		if (dwc_otg_param_initialized(core_if->core_params->ic_usb_cap)) {
+			DWC_ERROR("%d invalid for parameter ic_usb_cap. Check HW configuration.\n",
+			     val);
+		}
+		retval = -DWC_E_INVALID;
+		val = 0;
+	}
+	core_if->core_params->ic_usb_cap = val;
+	return retval;
+}
+int32_t dwc_otg_get_param_ic_usb_cap(dwc_otg_core_if_t * core_if)
+{
+	return core_if->core_params->ic_usb_cap;
+}
+
+int dwc_otg_set_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if, int32_t val)
+{
+	int retval = 0;
+	int valid = 1;
+
+	if(DWC_OTG_PARAM_TEST(val, 0, 3)) {
+		DWC_WARN("`%d' invalid for parameter `ahb_thr_ratio'\n", val);
+		DWC_WARN("ahb_thr_ratio must be 0 - 3\n");
+		return -DWC_E_INVALID;
+	}
+
+	if(val && (core_if->snpsid < OTG_CORE_REV_2_81a || !dwc_otg_get_param_thr_ctl(core_if))) {
+		valid = 0;
+	} else if(val && ((dwc_otg_get_param_tx_thr_length(core_if) / (1 << val)) < 4)) {
+		valid = 0;
+	}
+	if(valid == 0) {
+		if(dwc_otg_param_initialized(core_if->core_params->ahb_thr_ratio)) {
+			DWC_ERROR("%d invalid for parameter ahb_thr_ratio. Chack HW configuration.\n", val);
+		}
+		retval = -DWC_E_INVALID;
+		val = 0;
+	}
+
+	core_if->core_params->ahb_thr_ratio = val;
+	return retval;
+}
+int32_t dwc_otg_get_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if)
+{
+	return core_if->core_params->ahb_thr_ratio;
+}
+
+
+uint32_t dwc_otg_get_hnpstatus(dwc_otg_core_if_t * core_if)
+{
+	gotgctl_data_t otgctl;
+	otgctl.d32 = dwc_read_reg32(&core_if->core_global_regs->gotgctl);
+	return otgctl.b.hstnegscs;
+}
+
+uint32_t dwc_otg_get_srpstatus(dwc_otg_core_if_t * core_if)
+{
+	gotgctl_data_t otgctl;
+	otgctl.d32 = dwc_read_reg32(&core_if->core_global_regs->gotgctl);
+	return otgctl.b.sesreqscs;
+}
+
+void dwc_otg_set_hnpreq(dwc_otg_core_if_t * core_if, uint32_t val)
+{
+	gotgctl_data_t otgctl;
+	otgctl.d32 = dwc_read_reg32(&core_if->core_global_regs->gotgctl);
+	otgctl.b.hnpreq = val;
+	dwc_write_reg32(&core_if->core_global_regs->gotgctl, otgctl.d32);
+}
+
+uint32_t dwc_otg_get_gsnpsid(dwc_otg_core_if_t * core_if)
+{
+	return core_if->snpsid;
+}
+
+uint32_t dwc_otg_get_mode(dwc_otg_core_if_t * core_if)
+{
+	gotgctl_data_t otgctl;
+	otgctl.d32 = dwc_read_reg32(&core_if->core_global_regs->gotgctl);
+	return otgctl.b.currmod;
+}
+
+uint32_t dwc_otg_get_hnpcapable(dwc_otg_core_if_t * core_if)
+{
+	gusbcfg_data_t usbcfg;
+	usbcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->gusbcfg);
+	return usbcfg.b.hnpcap;
+}
+
+void dwc_otg_set_hnpcapable(dwc_otg_core_if_t * core_if, uint32_t val)
+{
+	gusbcfg_data_t usbcfg;
+	usbcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->gusbcfg);
+	usbcfg.b.hnpcap = val;
+	dwc_write_reg32(&core_if->core_global_regs->gusbcfg, usbcfg.d32);
+}
+
+uint32_t dwc_otg_get_srpcapable(dwc_otg_core_if_t * core_if)
+{
+	gusbcfg_data_t usbcfg;
+	usbcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->gusbcfg);
+	return usbcfg.b.srpcap;
+}
+
+void dwc_otg_set_srpcapable(dwc_otg_core_if_t * core_if, uint32_t val)
+{
+	gusbcfg_data_t usbcfg;
+	usbcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->gusbcfg);
+	usbcfg.b.srpcap = val;
+	dwc_write_reg32(&core_if->core_global_regs->gusbcfg, usbcfg.d32);
+}
+
+uint32_t dwc_otg_get_devspeed(dwc_otg_core_if_t * core_if)
+{
+	dcfg_data_t dcfg;
+        dcfg.d32 = -1; //GRAYG
+        DWC_DEBUGPL(DBG_CILV, "%s - core_if(%p)\n", __func__, core_if);
+        if (NULL == core_if)
+                DWC_ERROR("reg request with NULL core_if\n");
+        DWC_DEBUGPL(DBG_CILV, "%s - core_if(%p)->dev_if(%p)\n", __func__,
+                    core_if, core_if->dev_if);
+        if (NULL == core_if->dev_if)
+                DWC_ERROR("reg request with NULL dev_if\n");
+        DWC_DEBUGPL(DBG_CILV, "%s - core_if(%p)->dev_if(%p)->"
+                    "dev_global_regs(%p)\n", __func__,
+                    core_if, core_if->dev_if,
+                    core_if->dev_if->dev_global_regs);
+        if (NULL == core_if->dev_if->dev_global_regs)
+                DWC_ERROR("reg request with NULL dev_global_regs\n");
+        else {
+                DWC_DEBUGPL(DBG_CILV, "%s - &core_if(%p)->dev_if(%p)->"
+                            "dev_global_regs(%p)->dcfg = %p\n", __func__,
+                            core_if, core_if->dev_if,
+                            core_if->dev_if->dev_global_regs,
+                            &core_if->dev_if->dev_global_regs->dcfg);
+        	dcfg.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dcfg);
+        }
+	return dcfg.b.devspd;
+}
+
+void dwc_otg_set_devspeed(dwc_otg_core_if_t * core_if, uint32_t val)
+{
+	dcfg_data_t dcfg;
+	dcfg.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dcfg);
+	dcfg.b.devspd = val;
+	dwc_write_reg32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
+}
+
+uint32_t dwc_otg_get_busconnected(dwc_otg_core_if_t * core_if)
+{
+	hprt0_data_t hprt0;
+	hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
+	return hprt0.b.prtconnsts;
+}
+
+uint32_t dwc_otg_get_enumspeed(dwc_otg_core_if_t * core_if)
+{
+	dsts_data_t dsts;
+	dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
+	return dsts.b.enumspd;
+}
+
+uint32_t dwc_otg_get_prtpower(dwc_otg_core_if_t * core_if)
+{
+	hprt0_data_t hprt0;
+	hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
+	return hprt0.b.prtpwr;
+
+}
+
+void dwc_otg_set_prtpower(dwc_otg_core_if_t * core_if, uint32_t val)
+{
+	hprt0_data_t hprt0;
+	hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
+	hprt0.b.prtpwr = val;
+	dwc_write_reg32(core_if->host_if->hprt0, val);
+}
+
+uint32_t dwc_otg_get_prtsuspend(dwc_otg_core_if_t * core_if)
+{
+	hprt0_data_t hprt0;
+	hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
+	return hprt0.b.prtsusp;
+
+}
+
+void dwc_otg_set_prtsuspend(dwc_otg_core_if_t * core_if, uint32_t val)
+{
+	hprt0_data_t hprt0;
+	hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
+	hprt0.b.prtsusp = val;
+	dwc_write_reg32(core_if->host_if->hprt0, val);
+}
+
+void dwc_otg_set_prtresume(dwc_otg_core_if_t * core_if, uint32_t val)
+{
+	hprt0_data_t hprt0;
+	hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
+	hprt0.b.prtres = val;
+	dwc_write_reg32(core_if->host_if->hprt0, val);
+}
+
+uint32_t dwc_otg_get_remotewakesig(dwc_otg_core_if_t * core_if)
+{
+	dctl_data_t dctl;
+	dctl.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dctl);
+	return dctl.b.rmtwkupsig;
+}
+
+uint32_t dwc_otg_get_lpm_portsleepstatus(dwc_otg_core_if_t * core_if)
+{
+	glpmcfg_data_t lpmcfg;
+	lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg);
+
+	DWC_ASSERT(!
+		   ((core_if->lx_state == DWC_OTG_L1) ^ lpmcfg.b.prt_sleep_sts),
+		   "lx_state = %d, lmpcfg.prt_sleep_sts = %d\n",
+		   core_if->lx_state, lpmcfg.b.prt_sleep_sts);
+
+	return lpmcfg.b.prt_sleep_sts;
+}
+
+uint32_t dwc_otg_get_lpm_remotewakeenabled(dwc_otg_core_if_t * core_if)
+{
+	glpmcfg_data_t lpmcfg;
+	lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg);
+	return lpmcfg.b.rem_wkup_en;
+}
+
+uint32_t dwc_otg_get_lpmresponse(dwc_otg_core_if_t * core_if)
+{
+	glpmcfg_data_t lpmcfg;
+	lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg);
+	return lpmcfg.b.appl_resp;
+}
+
+void dwc_otg_set_lpmresponse(dwc_otg_core_if_t * core_if, uint32_t val)
+{
+	glpmcfg_data_t lpmcfg;
+	lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg);
+	lpmcfg.b.appl_resp = val;
+	dwc_write_reg32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
+}
+
+uint32_t dwc_otg_get_hsic_connect(dwc_otg_core_if_t * core_if)
+{
+	glpmcfg_data_t lpmcfg;
+	lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg);
+	return lpmcfg.b.hsic_connect;
+}
+
+void dwc_otg_set_hsic_connect(dwc_otg_core_if_t * core_if, uint32_t val)
+{
+	glpmcfg_data_t lpmcfg;
+	lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg);
+	lpmcfg.b.hsic_connect = val;
+	dwc_write_reg32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
+}
+
+uint32_t dwc_otg_get_inv_sel_hsic(dwc_otg_core_if_t * core_if)
+{
+	glpmcfg_data_t lpmcfg;
+	lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg);
+	return lpmcfg.b.inv_sel_hsic;
+
+}
+
+void dwc_otg_set_inv_sel_hsic(dwc_otg_core_if_t * core_if, uint32_t val)
+{
+	glpmcfg_data_t lpmcfg;
+	lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg);
+	lpmcfg.b.inv_sel_hsic = val;
+	dwc_write_reg32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
+}
+
+uint32_t dwc_otg_get_gotgctl(dwc_otg_core_if_t * core_if)
+{
+	return dwc_read_reg32(&core_if->core_global_regs->gotgctl);
+}
+
+void dwc_otg_set_gotgctl(dwc_otg_core_if_t * core_if, uint32_t val)
+{
+	dwc_write_reg32(&core_if->core_global_regs->gotgctl, val);
+}
+
+uint32_t dwc_otg_get_gusbcfg(dwc_otg_core_if_t * core_if)
+{
+	return dwc_read_reg32(&core_if->core_global_regs->gusbcfg);
+}
+
+void dwc_otg_set_gusbcfg(dwc_otg_core_if_t * core_if, uint32_t val)
+{
+	dwc_write_reg32(&core_if->core_global_regs->gusbcfg, val);
+}
+
+uint32_t dwc_otg_get_grxfsiz(dwc_otg_core_if_t * core_if)
+{
+	return dwc_read_reg32(&core_if->core_global_regs->grxfsiz);
+}
+
+void dwc_otg_set_grxfsiz(dwc_otg_core_if_t * core_if, uint32_t val)
+{
+	dwc_write_reg32(&core_if->core_global_regs->grxfsiz, val);
+}
+
+uint32_t dwc_otg_get_gnptxfsiz(dwc_otg_core_if_t * core_if)
+{
+	return dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz);
+}
+
+void dwc_otg_set_gnptxfsiz(dwc_otg_core_if_t * core_if, uint32_t val)
+{
+	dwc_write_reg32(&core_if->core_global_regs->gnptxfsiz, val);
+}
+
+uint32_t dwc_otg_get_gpvndctl(dwc_otg_core_if_t * core_if)
+{
+	return dwc_read_reg32(&core_if->core_global_regs->gpvndctl);
+}
+
+void dwc_otg_set_gpvndctl(dwc_otg_core_if_t * core_if, uint32_t val)
+{
+	dwc_write_reg32(&core_if->core_global_regs->gpvndctl, val);
+}
+
+uint32_t dwc_otg_get_ggpio(dwc_otg_core_if_t * core_if)
+{
+	return dwc_read_reg32(&core_if->core_global_regs->ggpio);
+}
+
+void dwc_otg_set_ggpio(dwc_otg_core_if_t * core_if, uint32_t val)
+{
+	dwc_write_reg32(&core_if->core_global_regs->ggpio, val);
+}
+
+uint32_t dwc_otg_get_hprt0(dwc_otg_core_if_t * core_if)
+{
+	return dwc_read_reg32(core_if->host_if->hprt0);
+
+}
+
+void dwc_otg_set_hprt0(dwc_otg_core_if_t * core_if, uint32_t val)
+{
+	dwc_write_reg32(core_if->host_if->hprt0, val);
+}
+
+uint32_t dwc_otg_get_guid(dwc_otg_core_if_t * core_if)
+{
+	return dwc_read_reg32(&core_if->core_global_regs->guid);
+}
+
+void dwc_otg_set_guid(dwc_otg_core_if_t * core_if, uint32_t val)
+{
+	dwc_write_reg32(&core_if->core_global_regs->guid, val);
+}
+
+uint32_t dwc_otg_get_hptxfsiz(dwc_otg_core_if_t * core_if)
+{
+	return dwc_read_reg32(&core_if->core_global_regs->hptxfsiz);
+}
diff --git a/drivers/usb/host/dwc_otg/dwc_otg_cil.h b/drivers/usb/host/dwc_otg/dwc_otg_cil.h
new file mode 100644
index 000000000000..11761664dbfd
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/dwc_otg_cil.h
@@ -0,0 +1,1143 @@
+/* ==========================================================================
+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.h $
+ * $Revision: #99 $
+ * $Date: 2009/04/21 $
+ * $Change: 1237466 $
+ *
+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+ * otherwise expressly agreed to in writing between Synopsys and you.
+ * 
+ * The Software IS NOT an item of Licensed Software or Licensed Product under
+ * any End User Software License Agreement or Agreement for Licensed Product
+ * with Synopsys or any supplement thereto. You are permitted to use and
+ * redistribute this Software in source and binary forms, with or without
+ * modification, provided that redistributions of source code must retain this
+ * notice. You may not view, use, disclose, copy or distribute this file or
+ * any information contained herein except pursuant to this license grant from
+ * Synopsys. If you do not agree with this notice, including the disclaimer
+ * below, then you are not authorized to use the Software.
+ * 
+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ * ========================================================================== */
+
+#if !defined(__DWC_CIL_H__)
+#define __DWC_CIL_H__
+
+//#define HW2937_WORKAROUND
+#define DBG_HW2937 0x400
+
+#include "dwc_os.h"
+#include "dwc_list.h"
+#include "dwc_otg_dbg.h"
+#include "dwc_otg_regs.h"
+
+#include "dwc_otg_core_if.h"
+
+/**
+ * @file
+ * This file contains the interface to the Core Interface Layer.
+ */
+
+#ifdef DWC_UTE_CFI
+
+#define MAX_DMA_DESCS_PER_EP	256
+
+/**
+ * Enumeration for the data buffer mode
+ */
+typedef enum _data_buffer_mode {
+	BM_STANDARD = 0,	/* data buffer is in normal mode */
+	BM_SG = 1,		/* data buffer uses the scatter/gather mode */
+	BM_CONCAT = 2,		/* data buffer uses the concatenation mode */
+	BM_CIRCULAR = 3,	/* data buffer uses the circular DMA mode */
+	BM_ALIGN = 4		/* data buffer is in buffer alignment mode */
+} data_buffer_mode_e;
+#endif				//DWC_UTE_CFI
+
+/** Macros defined for DWC OTG HW Release verison */
+
+#define OTG_CORE_REV_2_60a	0x4F54260A
+#define OTG_CORE_REV_2_71a	0x4F54271A
+#define OTG_CORE_REV_2_72a	0x4F54272A
+#define OTG_CORE_REV_2_80a	0x4F54280A
+#define OTG_CORE_REV_2_81a	0x4F54281A
+#define OTG_CORE_REV_2_90a	0x4F54290A		
+
+/**
+ * Information for each ISOC packet.
+ */
+typedef struct iso_pkt_info {
+	uint32_t offset;
+	uint32_t length;
+	int32_t status;
+} iso_pkt_info_t;
+
+/**
+ * The <code>dwc_ep</code> structure represents the state of a single
+ * endpoint when acting in device mode. It contains the data items
+ * needed for an endpoint to be activated and transfer packets.
+ */
+typedef struct dwc_ep {
+	/** EP number used for register address lookup */
+	uint8_t num;
+	/** EP direction 0 = OUT */
+	unsigned is_in:1;
+	/** EP active. */
+	unsigned active:1;
+
+	/** Periodic Tx FIFO # for IN EPs For INTR EP set to 0 to use non-periodic Tx FIFO 
+		If dedicated Tx FIFOs are enabled for all IN Eps - Tx FIFO # FOR IN EPs*/
+	unsigned tx_fifo_num:4;
+	/** EP type: 0 - Control, 1 - ISOC,	 2 - BULK,	3 - INTR */
+	unsigned type:2;
+#define DWC_OTG_EP_TYPE_CONTROL	   0
+#define DWC_OTG_EP_TYPE_ISOC	   1
+#define DWC_OTG_EP_TYPE_BULK	   2
+#define DWC_OTG_EP_TYPE_INTR	   3
+
+	/** DATA start PID for INTR and BULK EP */
+	unsigned data_pid_start:1;
+	/** Frame (even/odd) for ISOC EP */
+	unsigned even_odd_frame:1;
+	/** Max Packet bytes */
+	unsigned maxpacket:11;
+
+	/** Max Transfer size */
+	uint32_t maxxfer;
+
+	/** @name Transfer state */
+	/** @{ */
+
+	/**
+	 * Pointer to the beginning of the transfer buffer -- do not modify
+	 * during transfer.
+	 */
+
+	dwc_dma_t dma_addr;
+
+	dwc_dma_t dma_desc_addr;
+	dwc_otg_dev_dma_desc_t *desc_addr;
+
+	uint8_t *start_xfer_buff;
+	/** pointer to the transfer buffer */
+	uint8_t *xfer_buff;
+	/** Number of bytes to transfer */
+	unsigned xfer_len:19;
+	/** Number of bytes transferred. */
+	unsigned xfer_count:19;
+	/** Sent ZLP */
+	unsigned sent_zlp:1;
+	/** Total len for control transfer */
+	unsigned total_len:19;
+
+	/** stall clear flag */
+	unsigned stall_clear_flag:1;
+
+#ifdef DWC_UTE_CFI
+	/* The buffer mode */
+	data_buffer_mode_e buff_mode;
+
+	/* The chain of DMA descriptors.
+	 * MAX_DMA_DESCS_PER_EP will be allocated for each active EP.
+	 */
+	dwc_otg_dma_desc_t *descs;
+
+	/* The DMA address of the descriptors chain start */
+	dma_addr_t descs_dma_addr;
+	/** This variable stores the length of the last enqueued request */
+	uint32_t cfi_req_len;
+#endif				//DWC_UTE_CFI
+
+	/** Allocated DMA Desc count */
+	uint32_t desc_cnt;
+
+#ifdef DWC_EN_ISOC
+	/**
+	 * Variables specific for ISOC EPs
+	 *
+	 */
+	/** DMA addresses of ISOC buffers */
+	dwc_dma_t dma_addr0;
+	dwc_dma_t dma_addr1;
+
+	dwc_dma_t iso_dma_desc_addr;
+	dwc_otg_dev_dma_desc_t *iso_desc_addr;
+
+	/** pointer to the transfer buffers */
+	uint8_t *xfer_buff0;
+	uint8_t *xfer_buff1;
+
+	/** number of ISOC Buffer is processing */
+	uint32_t proc_buf_num;
+	/** Interval of ISOC Buffer processing */
+	uint32_t buf_proc_intrvl;
+	/** Data size for regular frame */
+	uint32_t data_per_frame;
+
+	/* todo - pattern data support is to be implemented in the future */
+	/** Data size for pattern frame */
+	uint32_t data_pattern_frame;
+	/** Frame number of pattern data */
+	uint32_t sync_frame;
+
+	/** bInterval */
+	uint32_t bInterval;
+	/** ISO Packet number per frame */
+	uint32_t pkt_per_frm;
+	/** Next frame num for which will be setup DMA Desc */
+	uint32_t next_frame;
+	/** Number of packets per buffer processing */
+	uint32_t pkt_cnt;
+	/** Info for all isoc packets */
+	iso_pkt_info_t *pkt_info;
+	/** current pkt number */
+	uint32_t cur_pkt;
+	/** current pkt number */
+	uint8_t *cur_pkt_addr;
+	/** current pkt number */
+	uint32_t cur_pkt_dma_addr;
+#endif				/* DWC_EN_ISOC */
+
+/** @} */
+} dwc_ep_t;
+
+/*
+ * Reasons for halting a host channel.
+ */
+typedef enum dwc_otg_halt_status {
+	DWC_OTG_HC_XFER_NO_HALT_STATUS,
+	DWC_OTG_HC_XFER_COMPLETE,
+	DWC_OTG_HC_XFER_URB_COMPLETE,
+	DWC_OTG_HC_XFER_ACK,
+	DWC_OTG_HC_XFER_NAK,
+	DWC_OTG_HC_XFER_NYET,
+	DWC_OTG_HC_XFER_STALL,
+	DWC_OTG_HC_XFER_XACT_ERR,
+	DWC_OTG_HC_XFER_FRAME_OVERRUN,
+	DWC_OTG_HC_XFER_BABBLE_ERR,
+	DWC_OTG_HC_XFER_DATA_TOGGLE_ERR,
+	DWC_OTG_HC_XFER_AHB_ERR,
+	DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE,
+	DWC_OTG_HC_XFER_URB_DEQUEUE
+#ifdef HW2937_WORKAROUND
+	, DWC_OTG_HC_XFER_PAUSE_IN
+#endif
+} dwc_otg_halt_status_e;
+
+/**
+ * Host channel descriptor. This structure represents the state of a single
+ * host channel when acting in host mode. It contains the data items needed to
+ * transfer packets to an endpoint via a host channel.
+ */
+typedef struct dwc_hc {
+	/** Host channel number used for register address lookup */
+	uint8_t hc_num;
+
+	/** Device to access */
+	unsigned dev_addr:7;
+
+	/** EP to access */
+	unsigned ep_num:4;
+
+	/** EP direction. 0: OUT, 1: IN */
+	unsigned ep_is_in:1;
+
+	/**
+	 * EP speed.
+	 * One of the following values:
+	 *	- DWC_OTG_EP_SPEED_LOW
+	 *	- DWC_OTG_EP_SPEED_FULL
+	 *	- DWC_OTG_EP_SPEED_HIGH
+	 */
+	unsigned speed:2;
+#define DWC_OTG_EP_SPEED_LOW	0
+#define DWC_OTG_EP_SPEED_FULL	1
+#define DWC_OTG_EP_SPEED_HIGH	2
+
+	/**
+	 * Endpoint type.
+	 * One of the following values:
+	 *	- DWC_OTG_EP_TYPE_CONTROL: 0
+	 *	- DWC_OTG_EP_TYPE_ISOC: 1
+	 *	- DWC_OTG_EP_TYPE_BULK: 2
+	 *	- DWC_OTG_EP_TYPE_INTR: 3
+	 */
+	unsigned ep_type:2;
+
+	/** Max packet size in bytes */
+	unsigned max_packet:11;
+
+	/**
+	 * PID for initial transaction.
+	 * 0: DATA0,<br>
+	 * 1: DATA2,<br>
+	 * 2: DATA1,<br>
+	 * 3: MDATA (non-Control EP),
+	 *	  SETUP (Control EP)
+	 */
+	unsigned data_pid_start:2;
+#define DWC_OTG_HC_PID_DATA0 0
+#define DWC_OTG_HC_PID_DATA2 1
+#define DWC_OTG_HC_PID_DATA1 2
+#define DWC_OTG_HC_PID_MDATA 3
+#define DWC_OTG_HC_PID_SETUP 3
+
+	/** Number of periodic transactions per (micro)frame */
+	unsigned multi_count:2;
+
+	/** @name Transfer State */
+	/** @{ */
+
+	/** Pointer to the current transfer buffer position. */
+	uint8_t *xfer_buff;
+	/**	 
+	 * In Buffer DMA mode this buffer will be used
+	 * if xfer_buff is not DWORD aligned.
+	 */
+	dwc_dma_t align_buff;
+	/** Total number of bytes to transfer. */
+	uint32_t xfer_len;
+	/** Number of bytes transferred so far. */
+	uint32_t xfer_count;
+	/** Packet count at start of transfer.*/
+	uint16_t start_pkt_count;
+
+	/**
+	 * Flag to indicate whether the transfer has been started. Set to 1 if
+	 * it has been started, 0 otherwise.
+	 */
+	uint8_t xfer_started;
+
+	/**
+	 * Set to 1 to indicate that a PING request should be issued on this
+	 * channel. If 0, process normally.
+	 */
+	uint8_t do_ping;
+
+	/**
+	 * Set to 1 to indicate that the error count for this transaction is
+	 * non-zero. Set to 0 if the error count is 0.
+	 */
+	uint8_t error_state;
+
+	/**
+	 * Set to 1 to indicate that this channel should be halted the next
+	 * time a request is queued for the channel. This is necessary in
+	 * slave mode if no request queue space is available when an attempt
+	 * is made to halt the channel.
+	 */
+	uint8_t halt_on_queue;
+
+	/**
+	 * Set to 1 if the host channel has been halted, but the core is not
+	 * finished flushing queued requests. Otherwise 0.
+	 */
+	uint8_t halt_pending;
+
+	/**
+	 * Reason for halting the host channel.
+	 */
+	dwc_otg_halt_status_e halt_status;
+
+	/*
+	 * Split settings for the host channel
+	 */
+	uint8_t do_split;		   /**< Enable split for the channel */
+	uint8_t complete_split;	   /**< Enable complete split */
+	uint8_t hub_addr;		   /**< Address of high speed hub */
+
+	uint8_t port_addr;		   /**< Port of the low/full speed device */
+	/** Split transaction position 
+	 * One of the following values:
+	 *	  - DWC_HCSPLIT_XACTPOS_MID 
+	 *	  - DWC_HCSPLIT_XACTPOS_BEGIN
+	 *	  - DWC_HCSPLIT_XACTPOS_END
+	 *	  - DWC_HCSPLIT_XACTPOS_ALL */
+	uint8_t xact_pos;
+
+	/** Set when the host channel does a short read. */
+	uint8_t short_read;
+
+	/**
+	 * Number of requests issued for this channel since it was assigned to
+	 * the current transfer (not counting PINGs).
+	 */
+	uint8_t requests;
+
+	/**
+	 * Queue Head for the transfer being processed by this channel.
+	 */
+	struct dwc_otg_qh *qh;
+
+	/** @} */
+
+	/** Entry in list of host channels. */
+	 DWC_CIRCLEQ_ENTRY(dwc_hc) hc_list_entry;
+	
+	/** @name Descriptor DMA support */
+	/** @{ */
+			
+	/** Number of Transfer Descriptors */
+	uint16_t ntd;
+	
+	/** Descriptor List DMA address */
+	dwc_dma_t desc_list_addr;
+	
+	/** Scheduling micro-frame bitmap. */
+	uint8_t schinfo;
+	
+	/** @} */
+} dwc_hc_t;
+
+/**
+ * The following parameters may be specified when starting the module. These
+ * parameters define how the DWC_otg controller should be configured.
+ */
+typedef struct dwc_otg_core_params {
+	int32_t opt;
+
+	/**
+	 * Specifies the OTG capabilities. The driver will automatically
+	 * detect the value for this parameter if none is specified.
+	 * 0 - HNP and SRP capable (default)
+	 * 1 - SRP Only capable
+	 * 2 - No HNP/SRP capable
+	 */
+	int32_t otg_cap;
+
+	/**
+	 * Specifies whether to use slave or DMA mode for accessing the data
+	 * FIFOs. The driver will automatically detect the value for this
+	 * parameter if none is specified.
+	 * 0 - Slave
+	 * 1 - DMA (default, if available)
+	 */
+	int32_t dma_enable;
+
+	/**
+	 * When DMA mode is enabled specifies whether to use address DMA or DMA Descritor mode for accessing the data
+	 * FIFOs in device mode. The driver will automatically detect the value for this
+	 * parameter if none is specified.
+	 * 0 - address DMA
+	 * 1 - DMA Descriptor(default, if available)
+	 */
+	int32_t dma_desc_enable;
+	/** The DMA Burst size (applicable only for External DMA
+	 * Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32)
+	 */
+	int32_t dma_burst_size;	/* Translate this to GAHBCFG values */
+
+	/**
+	 * Specifies the maximum speed of operation in host and device mode.
+	 * The actual speed depends on the speed of the attached device and
+	 * the value of phy_type. The actual speed depends on the speed of the
+	 * attached device.
+	 * 0 - High Speed (default)
+	 * 1 - Full Speed
+	 */
+	int32_t speed;
+	/** Specifies whether low power mode is supported when attached 
+	 *	to a Full Speed or Low Speed device in host mode.
+	 * 0 - Don't support low power mode (default)
+	 * 1 - Support low power mode
+	 */
+	int32_t host_support_fs_ls_low_power;
+
+	/** Specifies the PHY clock rate in low power mode when connected to a
+	 * Low Speed device in host mode. This parameter is applicable only if
+	 * HOST_SUPPORT_FS_LS_LOW_POWER is enabled.	 If PHY_TYPE is set to FS
+	 * then defaults to 6 MHZ otherwise 48 MHZ.
+	 *
+	 * 0 - 48 MHz
+	 * 1 - 6 MHz
+	 */
+	int32_t host_ls_low_power_phy_clk;
+
+	/**
+	 * 0 - Use cC FIFO size parameters
+	 * 1 - Allow dynamic FIFO sizing (default)
+	 */
+	int32_t enable_dynamic_fifo;
+
+	/** Total number of 4-byte words in the data FIFO memory. This 
+	 * memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic 
+	 * Tx FIFOs.
+	 * 32 to 32768 (default 8192)
+	 * Note: The total FIFO memory depth in the FPGA configuration is 8192.
+	 */
+	int32_t data_fifo_size;
+
+	/** Number of 4-byte words in the Rx FIFO in device mode when dynamic 
+	 * FIFO sizing is enabled.
+	 * 16 to 32768 (default 1064)
+	 */
+	int32_t dev_rx_fifo_size;
+
+	/** Number of 4-byte words in the non-periodic Tx FIFO in device mode 
+	 * when dynamic FIFO sizing is enabled.
+	 * 16 to 32768 (default 1024)
+	 */
+	int32_t dev_nperio_tx_fifo_size;
+
+	/** Number of 4-byte words in each of the periodic Tx FIFOs in device
+	 * mode when dynamic FIFO sizing is enabled.
+	 * 4 to 768 (default 256)
+	 */
+	uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
+
+	/** Number of 4-byte words in the Rx FIFO in host mode when dynamic 
+	 * FIFO sizing is enabled.
+	 * 16 to 32768 (default 1024)  
+	 */
+	int32_t host_rx_fifo_size;
+
+		/** Number of 4-byte words in the non-periodic Tx FIFO in host mode 
+	 * when Dynamic FIFO sizing is enabled in the core. 
+	 * 16 to 32768 (default 1024)
+	 */
+	int32_t host_nperio_tx_fifo_size;
+
+	/** Number of 4-byte words in the host periodic Tx FIFO when dynamic 
+	 * FIFO sizing is enabled. 
+	 * 16 to 32768 (default 1024)
+	 */
+	int32_t host_perio_tx_fifo_size;
+
+	/** The maximum transfer size supported in bytes.  
+	 * 2047 to 65,535  (default 65,535)
+	 */
+	int32_t max_transfer_size;
+
+	/** The maximum number of packets in a transfer.  
+	 * 15 to 511  (default 511)
+	 */
+	int32_t max_packet_count;
+
+	/** The number of host channel registers to use.  
+	 * 1 to 16 (default 12) 
+	 * Note: The FPGA configuration supports a maximum of 12 host channels.
+	 */
+	int32_t host_channels;
+
+	/** The number of endpoints in addition to EP0 available for device 
+	 * mode operations. 
+	 * 1 to 15 (default 6 IN and OUT) 
+	 * Note: The FPGA configuration supports a maximum of 6 IN and OUT 
+	 * endpoints in addition to EP0.
+	 */
+	int32_t dev_endpoints;
+
+		/** 
+		 * Specifies the type of PHY interface to use. By default, the driver
+		 * will automatically detect the phy_type.
+		 * 
+		 * 0 - Full Speed PHY
+		 * 1 - UTMI+ (default)
+		 * 2 - ULPI
+		 */
+	int32_t phy_type;
+
+	/**
+	 * Specifies the UTMI+ Data Width.	This parameter is
+	 * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI
+	 * PHY_TYPE, this parameter indicates the data width between
+	 * the MAC and the ULPI Wrapper.) Also, this parameter is
+	 * applicable only if the OTG_HSPHY_WIDTH cC parameter was set
+	 * to "8 and 16 bits", meaning that the core has been
+	 * configured to work at either data path width. 
+	 *
+	 * 8 or 16 bits (default 16)
+	 */
+	int32_t phy_utmi_width;
+
+	/**
+	 * Specifies whether the ULPI operates at double or single
+	 * data rate. This parameter is only applicable if PHY_TYPE is
+	 * ULPI.
+	 * 
+	 * 0 - single data rate ULPI interface with 8 bit wide data
+	 * bus (default)
+	 * 1 - double data rate ULPI interface with 4 bit wide data
+	 * bus
+	 */
+	int32_t phy_ulpi_ddr;
+
+	/**
+	 * Specifies whether to use the internal or external supply to 
+	 * drive the vbus with a ULPI phy.
+	 */
+	int32_t phy_ulpi_ext_vbus;
+
+	/**
+	 * Specifies whether to use the I2Cinterface for full speed PHY. This
+	 * parameter is only applicable if PHY_TYPE is FS.
+	 * 0 - No (default)
+	 * 1 - Yes
+	 */
+	int32_t i2c_enable;
+
+	int32_t ulpi_fs_ls;
+
+	int32_t ts_dline;
+
+	/**
+	 * Specifies whether dedicated transmit FIFOs are 
+	 * enabled for non periodic IN endpoints in device mode
+	 * 0 - No 
+	 * 1 - Yes
+	 */
+	int32_t en_multiple_tx_fifo;
+
+	/** Number of 4-byte words in each of the Tx FIFOs in device
+	 * mode when dynamic FIFO sizing is enabled.
+	 * 4 to 768 (default 256)
+	 */
+	uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
+
+	/** Thresholding enable flag- 
+	 * bit 0 - enable non-ISO Tx thresholding
+	 * bit 1 - enable ISO Tx thresholding
+	 * bit 2 - enable Rx thresholding
+	 */
+	uint32_t thr_ctl;
+
+	/** Thresholding length for Tx 
+	 *	FIFOs in 32 bit DWORDs
+	 */
+	uint32_t tx_thr_length;
+
+	/** Thresholding length for Rx 
+	 *	FIFOs in 32 bit DWORDs
+	 */
+	uint32_t rx_thr_length;
+
+	/**
+	 * Specifies whether LPM (Link Power Management) support is enabled
+	 */
+	int32_t lpm_enable;
+
+	/** Per Transfer Interrupt 
+	 *	mode enable flag
+	 * 1 - Enabled
+	 * 0 - Disabled
+	 */
+	int32_t pti_enable;
+
+	/** Multi Processor Interrupt 
+	 *	mode enable flag
+	 * 1 - Enabled
+	 * 0 - Disabled
+	 */
+	int32_t mpi_enable;
+
+	/** IS_USB Capability
+	 * 1 - Enabled
+	 * 0 - Disabled
+	 */
+	int32_t ic_usb_cap;
+
+	/** AHB Threshold Ratio
+	 * 2'b00 AHB Threshold = 	MAC Threshold
+	 * 2'b01 AHB Threshold = 1/2 	MAC Threshold
+	 * 2'b10 AHB Threshold = 1/4	MAC Threshold
+	 * 2'b11 AHB Threshold = 1/8	MAC Threshold
+	 */
+	int32_t ahb_thr_ratio;
+
+} dwc_otg_core_params_t;
+
+#ifdef DEBUG
+struct dwc_otg_core_if;
+typedef struct hc_xfer_info {
+	struct dwc_otg_core_if *core_if;
+	dwc_hc_t *hc;
+} hc_xfer_info_t;
+#endif
+/*
+ * Device States
+ */
+typedef enum dwc_otg_lx_state {
+	/** On state */
+	DWC_OTG_L0,
+	/** LPM sleep state*/
+	DWC_OTG_L1,
+	/** USB suspend state*/
+	DWC_OTG_L2,
+	/** Off state*/
+	DWC_OTG_L3
+} dwc_otg_lx_state_e;
+
+/**
+ * The <code>dwc_otg_core_if</code> structure contains information needed to manage
+ * the DWC_otg controller acting in either host or device mode. It
+ * represents the programming view of the controller as a whole.
+ */
+struct dwc_otg_core_if {
+	/** Parameters that define how the core should be configured.*/
+	dwc_otg_core_params_t *core_params;
+
+	/** Core Global registers starting at offset 000h. */
+	dwc_otg_core_global_regs_t *core_global_regs;
+
+	/** Device-specific information */
+	dwc_otg_dev_if_t *dev_if;
+	/** Host-specific information */
+	dwc_otg_host_if_t *host_if;
+
+	/** Value from SNPSID register */
+	uint32_t snpsid;
+
+	/*
+	 * Set to 1 if the core PHY interface bits in USBCFG have been
+	 * initialized.
+	 */
+	uint8_t phy_init_done;
+
+	/*
+	 * SRP Success flag, set by srp success interrupt in FS I2C mode
+	 */
+	uint8_t srp_success;
+	uint8_t srp_timer_started;
+
+	/* Common configuration information */
+	/** Power and Clock Gating Control Register */
+	volatile uint32_t *pcgcctl;
+#define DWC_OTG_PCGCCTL_OFFSET 0xE00
+
+	/** Push/pop addresses for endpoints or host channels.*/
+	uint32_t *data_fifo[MAX_EPS_CHANNELS];
+#define DWC_OTG_DATA_FIFO_OFFSET 0x1000
+#define DWC_OTG_DATA_FIFO_SIZE 0x1000
+
+	/** Total RAM for FIFOs (Bytes) */
+	uint16_t total_fifo_size;
+	/** Size of Rx FIFO (Bytes) */
+	uint16_t rx_fifo_size;
+	/** Size of Non-periodic Tx FIFO (Bytes) */
+	uint16_t nperio_tx_fifo_size;
+
+	/** 1 if DMA is enabled, 0 otherwise. */
+	uint8_t dma_enable;
+
+	/** 1 if DMA descriptor is enabled, 0 otherwise. */
+	uint8_t dma_desc_enable;
+
+	/** 1 if PTI Enhancement mode is enabled, 0 otherwise. */
+	uint8_t pti_enh_enable;
+
+	/** 1 if MPI Enhancement mode is enabled, 0 otherwise. */
+	uint8_t multiproc_int_enable;
+
+	/** 1 if dedicated Tx FIFOs are enabled, 0 otherwise. */
+	uint8_t en_multiple_tx_fifo;
+
+	/** Set to 1 if multiple packets of a high-bandwidth transfer is in
+	 * process of being queued */
+	uint8_t queuing_high_bandwidth;
+
+	/** Hardware Configuration -- stored here for convenience.*/
+	hwcfg1_data_t hwcfg1;
+	hwcfg2_data_t hwcfg2;
+	hwcfg3_data_t hwcfg3;
+	hwcfg4_data_t hwcfg4;
+
+	/** Host and Device Configuration -- stored here for convenience.*/
+	hcfg_data_t hcfg;
+	dcfg_data_t dcfg;
+
+	/** The operational State, during transations
+	 * (a_host>>a_peripherial and b_device=>b_host) this may not
+	 * match the core but allows the software to determine
+	 * transitions.
+	 */
+	uint8_t op_state;
+
+	/**
+	 * Set to 1 if the HCD needs to be restarted on a session request
+	 * interrupt. This is required if no connector ID status change has
+	 * occurred since the HCD was last disconnected.
+	 */
+	uint8_t restart_hcd_on_session_req;
+
+	/** HCD callbacks */
+	/** A-Device is a_host */
+#define A_HOST		(1)
+	/** A-Device is a_suspend */
+#define A_SUSPEND	(2)
+	/** A-Device is a_peripherial */
+#define A_PERIPHERAL	(3)
+	/** B-Device is operating as a Peripheral. */
+#define B_PERIPHERAL	(4)
+	/** B-Device is operating as a Host. */
+#define B_HOST		(5)
+
+	/** HCD callbacks */
+	struct dwc_otg_cil_callbacks *hcd_cb;
+	/** PCD callbacks */
+	struct dwc_otg_cil_callbacks *pcd_cb;
+
+	/** Device mode Periodic Tx FIFO Mask */
+	uint32_t p_tx_msk;
+	/** Device mode Periodic Tx FIFO Mask */
+	uint32_t tx_msk;
+
+	/** Workqueue object used for handling several interrupts */
+	dwc_workq_t *wq_otg;
+
+	/** Timer object used for handling "Wakeup Detected" Interrupt */
+	dwc_timer_t *wkp_timer;
+
+#ifdef DEBUG
+	uint32_t start_hcchar_val[MAX_EPS_CHANNELS];
+
+	hc_xfer_info_t hc_xfer_info[MAX_EPS_CHANNELS];
+	dwc_timer_t *hc_xfer_timer[MAX_EPS_CHANNELS];
+
+	uint32_t hfnum_7_samples;
+	uint64_t hfnum_7_frrem_accum;
+	uint32_t hfnum_0_samples;
+	uint64_t hfnum_0_frrem_accum;
+	uint32_t hfnum_other_samples;
+	uint64_t hfnum_other_frrem_accum;
+#endif
+
+#ifdef DWC_UTE_CFI
+	uint16_t pwron_rxfsiz;
+	uint16_t pwron_gnptxfsiz;
+	uint16_t pwron_txfsiz[15];
+
+	uint16_t init_rxfsiz;
+	uint16_t init_gnptxfsiz;
+	uint16_t init_txfsiz[15];
+#endif
+
+	/** Lx state of device */
+	dwc_otg_lx_state_e lx_state;
+
+};
+
+#ifdef DEBUG
+/*
+ * This function is called when transfer is timed out.
+ */
+extern void hc_xfer_timeout(void *ptr);
+#endif
+
+/*
+ * The following functions are functions for works 
+ * using during handling some interrupts
+ */
+extern void w_conn_id_status_change(void *p);
+
+extern void w_wakeup_detected(void *p);
+
+/*
+ * The following functions support initialization of the CIL driver component
+ * and the DWC_otg controller.
+ */
+extern void dwc_otg_core_host_init(dwc_otg_core_if_t * _core_if);
+extern void dwc_otg_core_dev_init(dwc_otg_core_if_t * _core_if);
+
+/** @name Device CIL Functions
+ * The following functions support managing the DWC_otg controller in device
+ * mode.
+ */
+/**@{*/
+extern void dwc_otg_wakeup(dwc_otg_core_if_t * _core_if);
+extern void dwc_otg_read_setup_packet(dwc_otg_core_if_t * _core_if,
+				      uint32_t * _dest);
+extern uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t * _core_if);
+extern void dwc_otg_ep0_activate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
+extern void dwc_otg_ep_activate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
+extern void dwc_otg_ep_deactivate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
+extern void dwc_otg_ep_start_transfer(dwc_otg_core_if_t * _core_if,
+				      dwc_ep_t * _ep);
+extern void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t * _core_if,
+					 dwc_ep_t * _ep);
+extern void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t * _core_if,
+				       dwc_ep_t * _ep);
+extern void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t * _core_if,
+					  dwc_ep_t * _ep);
+extern void dwc_otg_ep_write_packet(dwc_otg_core_if_t * _core_if,
+				    dwc_ep_t * _ep, int _dma);
+extern void dwc_otg_ep_set_stall(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
+extern void dwc_otg_ep_clear_stall(dwc_otg_core_if_t * _core_if,
+				   dwc_ep_t * _ep);
+extern void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t * _core_if);
+
+#ifdef DWC_EN_ISOC
+extern void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t * core_if,
+					      dwc_ep_t * ep);
+extern void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t * core_if,
+					      dwc_ep_t * ep);
+#endif				/* DWC_EN_ISOC */
+/**@}*/
+
+/** @name Host CIL Functions
+ * The following functions support managing the DWC_otg controller in host
+ * mode.
+ */
+/**@{*/
+extern void dwc_otg_hc_init(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc);
+extern void dwc_otg_hc_halt(dwc_otg_core_if_t * _core_if,
+			    dwc_hc_t * _hc, dwc_otg_halt_status_e _halt_status);
+extern void dwc_otg_hc_cleanup(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc);
+extern void dwc_otg_hc_start_transfer(dwc_otg_core_if_t * _core_if,
+				      dwc_hc_t * _hc);
+extern int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t * _core_if,
+					dwc_hc_t * _hc);
+extern void dwc_otg_hc_do_ping(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc);
+extern void dwc_otg_hc_write_packet(dwc_otg_core_if_t * _core_if,
+				    dwc_hc_t * _hc);
+extern void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t * _core_if);
+extern void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t * _core_if);
+
+extern void dwc_otg_hc_start_transfer_ddma(dwc_otg_core_if_t * core_if, dwc_hc_t * hc);
+
+/* Macro used to clear one channel interrupt */
+#define clear_hc_int(_hc_regs_, _intr_) \
+do { \
+	hcint_data_t hcint_clear = {.d32 = 0}; \
+	hcint_clear.b._intr_ = 1; \
+	dwc_write_reg32(&(_hc_regs_)->hcint, hcint_clear.d32); \
+} while (0)
+
+/*
+ * Macro used to disable one channel interrupt. Channel interrupts are
+ * disabled when the channel is halted or released by the interrupt handler.
+ * There is no need to handle further interrupts of that type until the
+ * channel is re-assigned. In fact, subsequent handling may cause crashes
+ * because the channel structures are cleaned up when the channel is released.
+ */
+#define disable_hc_int(_hc_regs_, _intr_) \
+do { \
+	hcintmsk_data_t hcintmsk = {.d32 = 0}; \
+	hcintmsk.b._intr_ = 1; \
+	dwc_modify_reg32(&(_hc_regs_)->hcintmsk, hcintmsk.d32, 0); \
+} while (0)
+		
+/**
+ * This function Reads HPRT0 in preparation to modify.	It keeps the
+ * WC bits 0 so that if they are read as 1, they won't clear when you
+ * write it back 
+ */
+static inline uint32_t dwc_otg_read_hprt0(dwc_otg_core_if_t * _core_if)
+{
+	hprt0_data_t hprt0;
+	hprt0.d32 = dwc_read_reg32(_core_if->host_if->hprt0);
+	hprt0.b.prtena = 0;
+	hprt0.b.prtconndet = 0;
+	hprt0.b.prtenchng = 0;
+	hprt0.b.prtovrcurrchng = 0;
+	return hprt0.d32;
+}
+
+/**@}*/
+
+/** @name Common CIL Functions
+ * The following functions support managing the DWC_otg controller in either
+ * device or host mode.
+ */
+/**@{*/
+
+extern void dwc_otg_read_packet(dwc_otg_core_if_t * core_if,
+				uint8_t * dest, uint16_t bytes);
+
+extern void dwc_otg_flush_tx_fifo(dwc_otg_core_if_t * _core_if, const int _num);
+extern void dwc_otg_flush_rx_fifo(dwc_otg_core_if_t * _core_if);
+extern void dwc_otg_core_reset(dwc_otg_core_if_t * _core_if);
+
+/**
+ * This function returns the Core Interrupt register.
+ */
+static inline uint32_t dwc_otg_read_core_intr(dwc_otg_core_if_t * core_if)
+{
+	return (dwc_read_reg32(&core_if->core_global_regs->gintsts) &
+		dwc_read_reg32(&core_if->core_global_regs->gintmsk));
+}
+
+/**
+ * This function returns the OTG Interrupt register.
+ */
+static inline uint32_t dwc_otg_read_otg_intr(dwc_otg_core_if_t * core_if)
+{
+	return (dwc_read_reg32(&core_if->core_global_regs->gotgint));
+}
+
+/**
+ * This function reads the Device All Endpoints Interrupt register and
+ * returns the IN endpoint interrupt bits.
+ */
+static inline uint32_t dwc_otg_read_dev_all_in_ep_intr(dwc_otg_core_if_t *
+						       core_if)
+{
+
+	uint32_t v;
+
+	if (core_if->multiproc_int_enable) {
+		v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->
+				   deachint) & dwc_read_reg32(&core_if->dev_if->
+							      dev_global_regs->
+							      deachintmsk);
+	} else {
+		v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->daint) &
+		    dwc_read_reg32(&core_if->dev_if->dev_global_regs->daintmsk);
+	}
+	return (v & 0xffff);
+}
+
+/**
+ * This function reads the Device All Endpoints Interrupt register and
+ * returns the OUT endpoint interrupt bits.
+ */
+static inline uint32_t dwc_otg_read_dev_all_out_ep_intr(dwc_otg_core_if_t *
+							core_if)
+{
+	uint32_t v;
+
+	if (core_if->multiproc_int_enable) {
+		v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->
+				   deachint) & dwc_read_reg32(&core_if->dev_if->
+							      dev_global_regs->
+							      deachintmsk);
+	} else {
+		v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->daint) &
+		    dwc_read_reg32(&core_if->dev_if->dev_global_regs->daintmsk);
+	}
+
+	return ((v & 0xffff0000) >> 16);
+}
+
+/**
+ * This function returns the Device IN EP Interrupt register
+ */
+static inline uint32_t dwc_otg_read_dev_in_ep_intr(dwc_otg_core_if_t * core_if,
+						   dwc_ep_t * ep)
+{
+	dwc_otg_dev_if_t *dev_if = core_if->dev_if;
+	uint32_t v, msk, emp;
+
+	if (core_if->multiproc_int_enable) {
+		msk =
+		    dwc_read_reg32(&dev_if->dev_global_regs->
+				   diepeachintmsk[ep->num]);
+		emp =
+		    dwc_read_reg32(&dev_if->dev_global_regs->
+				   dtknqr4_fifoemptymsk);
+		msk |= ((emp >> ep->num) & 0x1) << 7;
+		v = dwc_read_reg32(&dev_if->in_ep_regs[ep->num]->diepint) & msk;
+	} else {
+		msk = dwc_read_reg32(&dev_if->dev_global_regs->diepmsk);
+		emp =
+		    dwc_read_reg32(&dev_if->dev_global_regs->
+				   dtknqr4_fifoemptymsk);
+		msk |= ((emp >> ep->num) & 0x1) << 7;
+		v = dwc_read_reg32(&dev_if->in_ep_regs[ep->num]->diepint) & msk;
+	}
+
+	return v;
+}
+
+/**
+ * This function returns the Device OUT EP Interrupt register
+ */
+static inline uint32_t dwc_otg_read_dev_out_ep_intr(dwc_otg_core_if_t *
+						    _core_if, dwc_ep_t * _ep)
+{
+	dwc_otg_dev_if_t *dev_if = _core_if->dev_if;
+	uint32_t v;
+	doepmsk_data_t msk = {.d32 = 0 };
+
+	if (_core_if->multiproc_int_enable) {
+		msk.d32 =
+		    dwc_read_reg32(&dev_if->dev_global_regs->
+				   doepeachintmsk[_ep->num]);
+		if (_core_if->pti_enh_enable) {
+			msk.b.pktdrpsts = 1;
+		}
+		v = dwc_read_reg32(&dev_if->out_ep_regs[_ep->num]->
+				   doepint) & msk.d32;
+	} else {
+		msk.d32 = dwc_read_reg32(&dev_if->dev_global_regs->doepmsk);
+		if (_core_if->pti_enh_enable) {
+			msk.b.pktdrpsts = 1;
+		}
+		v = dwc_read_reg32(&dev_if->out_ep_regs[_ep->num]->
+				   doepint) & msk.d32;
+	}
+	return v;
+}
+
+/**
+ * This function returns the Host All Channel Interrupt register
+ */
+static inline uint32_t dwc_otg_read_host_all_channels_intr(dwc_otg_core_if_t *
+							   _core_if)
+{
+	return (dwc_read_reg32(&_core_if->host_if->host_global_regs->haint));
+}
+
+static inline uint32_t dwc_otg_read_host_channel_intr(dwc_otg_core_if_t *
+						      _core_if, dwc_hc_t * _hc)
+{
+	return (dwc_read_reg32
+		(&_core_if->host_if->hc_regs[_hc->hc_num]->hcint));
+}
+
+/**
+ * This function returns the mode of the operation, host or device.
+ *
+ * @return 0 - Device Mode, 1 - Host Mode 
+ */
+static inline uint32_t dwc_otg_mode(dwc_otg_core_if_t * _core_if)
+{
+	return (dwc_read_reg32(&_core_if->core_global_regs->gintsts) & 0x1);
+}
+
+/**@}*/
+
+/**
+ * DWC_otg CIL callback structure.	This structure allows the HCD and
+ * PCD to register functions used for starting and stopping the PCD
+ * and HCD for role change on for a DRD.
+ */
+typedef struct dwc_otg_cil_callbacks {
+	/** Start function for role change */
+	int (*start) (void *_p);
+	/** Stop Function for role change */
+	int (*stop) (void *_p);
+	/** Disconnect Function for role change */
+	int (*disconnect) (void *_p);
+	/** Resume/Remote wakeup Function */
+	int (*resume_wakeup) (void *_p);
+	/** Suspend function */
+	int (*suspend) (void *_p);
+	/** Session Start (SRP) */
+	int (*session_start) (void *_p);
+#ifdef CONFIG_USB_DWC_OTG_LPM
+	/** Sleep (switch to L0 state) */
+	int (*sleep) (void *_p);
+#endif
+	/** Pointer passed to start() and stop() */
+	void *p;
+} dwc_otg_cil_callbacks_t;
+
+extern void dwc_otg_cil_register_pcd_callbacks(dwc_otg_core_if_t * _core_if,
+					       dwc_otg_cil_callbacks_t * _cb,
+					       void *_p);
+extern void dwc_otg_cil_register_hcd_callbacks(dwc_otg_core_if_t * _core_if,
+					       dwc_otg_cil_callbacks_t * _cb,
+					       void *_p);
+
+#endif
diff --git a/drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c b/drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c
new file mode 100644
index 000000000000..b8b2740f992e
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c
@@ -0,0 +1,846 @@
+/* ==========================================================================
+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil_intr.c $
+ * $Revision: #15 $
+ * $Date: 2009/04/15 $
+ * $Change: 1234129 $
+ *
+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+ * otherwise expressly agreed to in writing between Synopsys and you.
+ *
+ * The Software IS NOT an item of Licensed Software or Licensed Product under
+ * any End User Software License Agreement or Agreement for Licensed Product
+ * with Synopsys or any supplement thereto. You are permitted to use and
+ * redistribute this Software in source and binary forms, with or without
+ * modification, provided that redistributions of source code must retain this
+ * notice. You may not view, use, disclose, copy or distribute this file or
+ * any information contained herein except pursuant to this license grant from
+ * Synopsys. If you do not agree with this notice, including the disclaimer
+ * below, then you are not authorized to use the Software.
+ *
+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ * ========================================================================== */
+
+/** @file
+ *
+ * The Core Interface Layer provides basic services for accessing and
+ * managing the DWC_otg hardware. These services are used by both the
+ * Host Controller Driver and the Peripheral Controller Driver.
+ *
+ * This file contains the Common Interrupt handlers.
+ */
+#include "dwc_os.h"
+#include "dwc_otg_regs.h"
+#include "dwc_otg_cil.h"
+
+#ifdef DEBUG
+inline const char *op_state_str(dwc_otg_core_if_t * core_if)
+{
+	return (core_if->op_state == A_HOST ? "a_host" :
+		(core_if->op_state == A_SUSPEND ? "a_suspend" :
+		 (core_if->op_state == A_PERIPHERAL ? "a_peripheral" :
+		  (core_if->op_state == B_PERIPHERAL ? "b_peripheral" :
+		   (core_if->op_state == B_HOST ? "b_host" : "unknown")))));
+}
+#endif
+
+/** This function will log a debug message
+ *
+ * @param core_if Programming view of DWC_otg controller.
+ */
+int32_t dwc_otg_handle_mode_mismatch_intr(dwc_otg_core_if_t * core_if)
+{
+	gintsts_data_t gintsts;
+	DWC_WARN("Mode Mismatch Interrupt: currently in %s mode\n",
+		 dwc_otg_mode(core_if) ? "Host" : "Device");
+
+	/* Clear interrupt */
+	gintsts.d32 = 0;
+	gintsts.b.modemismatch = 1;
+	dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32);
+	return 1;
+}
+
+/** Start the HCD.  Helper function for using the HCD callbacks.
+ *
+ * @param core_if Programming view of DWC_otg controller.
+ */
+static inline void hcd_start(dwc_otg_core_if_t * core_if)
+{
+	if (core_if->hcd_cb && core_if->hcd_cb->start) {
+		core_if->hcd_cb->start(core_if->hcd_cb->p);
+	}
+}
+
+/** Stop the HCD.  Helper function for using the HCD callbacks.
+ *
+ * @param core_if Programming view of DWC_otg controller.
+ */
+static inline void hcd_stop(dwc_otg_core_if_t * core_if)
+{
+	if (core_if->hcd_cb && core_if->hcd_cb->stop) {
+		core_if->hcd_cb->stop(core_if->hcd_cb->p);
+	}
+}
+
+/** Disconnect the HCD.  Helper function for using the HCD callbacks.
+ *
+ * @param core_if Programming view of DWC_otg controller.
+ */
+static inline void hcd_disconnect(dwc_otg_core_if_t * core_if)
+{
+	if (core_if->hcd_cb && core_if->hcd_cb->disconnect) {
+		core_if->hcd_cb->disconnect(core_if->hcd_cb->p);
+	}
+}
+
+/** Inform the HCD the a New Session has begun.  Helper function for
+ * using the HCD callbacks.
+ *
+ * @param core_if Programming view of DWC_otg controller.
+ */
+static inline void hcd_session_start(dwc_otg_core_if_t * core_if)
+{
+	if (core_if->hcd_cb && core_if->hcd_cb->session_start) {
+		core_if->hcd_cb->session_start(core_if->hcd_cb->p);
+	}
+}
+
+#ifdef CONFIG_USB_DWC_OTG_LPM
+/**
+ * Inform the HCD about LPM sleep.
+ * Helper function for using the HCD callbacks.
+ *
+ * @param core_if Programming view of DWC_otg controller.
+ */
+static inline void hcd_sleep(dwc_otg_core_if_t * core_if)
+{
+	if (core_if->hcd_cb && core_if->hcd_cb->sleep) {
+		core_if->hcd_cb->sleep(core_if->hcd_cb->p);
+	}
+}
+#endif
+
+/** Resume the HCD.  Helper function for using the HCD callbacks. 
+ *
+ * @param core_if Programming view of DWC_otg controller.
+ */
+static inline void hcd_resume(dwc_otg_core_if_t * core_if)
+{
+	if (core_if->hcd_cb && core_if->hcd_cb->resume_wakeup) {
+		core_if->hcd_cb->resume_wakeup(core_if->hcd_cb->p);
+	}
+}
+
+/** Start the PCD.  Helper function for using the PCD callbacks.
+ *
+ * @param core_if Programming view of DWC_otg controller.
+ */
+static inline void pcd_start(dwc_otg_core_if_t * core_if)
+{
+	if (core_if->pcd_cb && core_if->pcd_cb->start) {
+		core_if->pcd_cb->start(core_if->pcd_cb->p);
+	}
+}
+
+/** Stop the PCD.  Helper function for using the PCD callbacks. 
+ *
+ * @param core_if Programming view of DWC_otg controller.
+ */
+static inline void pcd_stop(dwc_otg_core_if_t * core_if)
+{
+	if (core_if->pcd_cb && core_if->pcd_cb->stop) {
+		core_if->pcd_cb->stop(core_if->pcd_cb->p);
+	}
+}
+
+/** Suspend the PCD.  Helper function for using the PCD callbacks. 
+ *
+ * @param core_if Programming view of DWC_otg controller.
+ */
+static inline void pcd_suspend(dwc_otg_core_if_t * core_if)
+{
+	if (core_if->pcd_cb && core_if->pcd_cb->suspend) {
+		core_if->pcd_cb->suspend(core_if->pcd_cb->p);
+	}
+}
+
+/** Resume the PCD.  Helper function for using the PCD callbacks. 
+ *
+ * @param core_if Programming view of DWC_otg controller.
+ */
+static inline void pcd_resume(dwc_otg_core_if_t * core_if)
+{
+	if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
+		core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
+	}
+}
+
+/**
+ * This function handles the OTG Interrupts. It reads the OTG
+ * Interrupt Register (GOTGINT) to determine what interrupt has
+ * occurred.
+ *
+ * @param core_if Programming view of DWC_otg controller.
+ */
+int32_t dwc_otg_handle_otg_intr(dwc_otg_core_if_t * core_if)
+{
+	dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
+	gotgint_data_t gotgint;
+	gotgctl_data_t gotgctl;
+	gintmsk_data_t gintmsk;
+
+	gotgint.d32 = dwc_read_reg32(&global_regs->gotgint);
+	gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl);
+	DWC_DEBUGPL(DBG_CIL, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint.d32,
+		    op_state_str(core_if));
+
+	if (gotgint.b.sesenddet) {
+		DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
+			    "Session End Detected++ (%s)\n",
+			    op_state_str(core_if));
+		gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl);
+
+		if (core_if->op_state == B_HOST) {
+			pcd_start(core_if);
+			core_if->op_state = B_PERIPHERAL;
+		} else {
+			/* If not B_HOST and Device HNP still set. HNP
+			 * Did not succeed!*/
+			if (gotgctl.b.devhnpen) {
+				DWC_DEBUGPL(DBG_ANY, "Session End Detected\n");
+				__DWC_ERROR("Device Not Connected/Responding!\n");
+			}
+
+			/* If Session End Detected the B-Cable has
+			 * been disconnected. */
+			/* Reset PCD and Gadget driver to a
+			 * clean state. */
+			core_if->lx_state = DWC_OTG_L0;
+			pcd_stop(core_if);
+		}
+		gotgctl.d32 = 0;
+		gotgctl.b.devhnpen = 1;
+		dwc_modify_reg32(&global_regs->gotgctl, gotgctl.d32, 0);
+	}
+	if (gotgint.b.sesreqsucstschng) {
+		DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
+			    "Session Reqeust Success Status Change++\n");
+		gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl);
+		if (gotgctl.b.sesreqscs) {
+			if ((core_if->core_params->phy_type ==
+			     DWC_PHY_TYPE_PARAM_FS) && (core_if->core_params->i2c_enable)) {
+				core_if->srp_success = 1;
+			} else {
+				pcd_resume(core_if);
+				/* Clear Session Request */
+				gotgctl.d32 = 0;
+				gotgctl.b.sesreq = 1;
+				dwc_modify_reg32(&global_regs->gotgctl,
+						 gotgctl.d32, 0);
+			}
+		}
+	}
+	if (gotgint.b.hstnegsucstschng) {
+		/* Print statements during the HNP interrupt handling
+		 * can cause it to fail.*/
+		gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl);
+		if (gotgctl.b.hstnegscs) {
+			if (dwc_otg_is_host_mode(core_if)) {
+				core_if->op_state = B_HOST;
+				/*
+				 * Need to disable SOF interrupt immediately.
+				 * When switching from device to host, the PCD
+				 * interrupt handler won't handle the
+				 * interrupt if host mode is already set. The
+				 * HCD interrupt handler won't get called if
+				 * the HCD state is HALT. This means that the
+				 * interrupt does not get handled and Linux
+				 * complains loudly.
+				 */
+				gintmsk.d32 = 0;
+				gintmsk.b.sofintr = 1;
+				dwc_modify_reg32(&global_regs->gintmsk,
+						 gintmsk.d32, 0);
+				pcd_stop(core_if);
+				/*
+				 * Initialize the Core for Host mode.
+				 */
+				hcd_start(core_if);
+				core_if->op_state = B_HOST;
+			}
+		} else {
+			gotgctl.d32 = 0;
+			gotgctl.b.hnpreq = 1;
+			gotgctl.b.devhnpen = 1;
+			dwc_modify_reg32(&global_regs->gotgctl, gotgctl.d32, 0);
+			DWC_DEBUGPL(DBG_ANY, "HNP Failed\n");
+			__DWC_ERROR("Device Not Connected/Responding\n");
+		}
+	}
+	if (gotgint.b.hstnegdet) {
+		/* The disconnect interrupt is set at the same time as
+		 * Host Negotiation Detected.  During the mode
+		 * switch all interrupts are cleared so the disconnect
+		 * interrupt handler will not get executed.
+		 */
+		DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
+			    "Host Negotiation Detected++ (%s)\n",
+			    (dwc_otg_is_host_mode(core_if) ? "Host" :
+			     "Device"));
+		if (dwc_otg_is_device_mode(core_if)) {
+			DWC_DEBUGPL(DBG_ANY, "a_suspend->a_peripheral (%d)\n",
+				    core_if->op_state);
+			hcd_disconnect(core_if);
+			pcd_start(core_if);
+			core_if->op_state = A_PERIPHERAL;
+		} else {
+			/*
+			 * Need to disable SOF interrupt immediately. When
+			 * switching from device to host, the PCD interrupt
+			 * handler won't handle the interrupt if host mode is
+			 * already set. The HCD interrupt handler won't get
+			 * called if the HCD state is HALT. This means that
+			 * the interrupt does not get handled and Linux
+			 * complains loudly.
+			 */
+			gintmsk.d32 = 0;
+			gintmsk.b.sofintr = 1;
+			dwc_modify_reg32(&global_regs->gintmsk, gintmsk.d32, 0);
+			pcd_stop(core_if);
+			hcd_start(core_if);
+			core_if->op_state = A_HOST;
+		}
+	}
+	if (gotgint.b.adevtoutchng) {
+		DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
+			    "A-Device Timeout Change++\n");
+	}
+	if (gotgint.b.debdone) {
+		DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " "Debounce Done++\n");
+	}
+
+	/* Clear GOTGINT */
+	dwc_write_reg32(&core_if->core_global_regs->gotgint, gotgint.d32);
+
+	return 1;
+}
+
+void w_conn_id_status_change(void *p)
+{
+	dwc_otg_core_if_t *core_if = p;
+	uint32_t count = 0;
+	gotgctl_data_t gotgctl = {.d32 = 0 };
+
+	gotgctl.d32 = dwc_read_reg32(&core_if->core_global_regs->gotgctl);
+	DWC_DEBUGPL(DBG_CIL, "gotgctl=%0x\n", gotgctl.d32);
+	DWC_DEBUGPL(DBG_CIL, "gotgctl.b.conidsts=%d\n", gotgctl.b.conidsts);
+
+	/* B-Device connector (Device Mode) */
+	if (gotgctl.b.conidsts) {
+		/* Wait for switch to device mode. */
+		while (!dwc_otg_is_device_mode(core_if)) {
+			DWC_PRINTF("Waiting for Peripheral Mode, Mode=%s\n",
+				   (dwc_otg_is_host_mode(core_if) ? "Host" :
+				    "Peripheral"));
+			dwc_mdelay(100);
+			if (++count > 10000)
+				break;
+		}
+		DWC_ASSERT(++count < 10000,
+			   "Connection id status change timed out");
+		core_if->op_state = B_PERIPHERAL;
+		dwc_otg_core_init(core_if);
+		dwc_otg_enable_global_interrupts(core_if);
+		pcd_start(core_if);
+	} else {
+		/* A-Device connector (Host Mode) */
+		while (!dwc_otg_is_host_mode(core_if)) {
+			DWC_PRINTF("Waiting for Host Mode, Mode=%s\n",
+				   (dwc_otg_is_host_mode(core_if) ? "Host" :
+				    "Peripheral"));
+			dwc_mdelay(100);
+			if (++count > 10000)
+				break;
+		}
+		DWC_ASSERT(++count < 10000,
+			   "Connection id status change timed out");
+		core_if->op_state = A_HOST;
+		/*
+		 * Initialize the Core for Host mode.
+		 */
+		dwc_otg_core_init(core_if);
+		dwc_otg_enable_global_interrupts(core_if);
+		hcd_start(core_if);
+	}
+}
+
+/**
+ * This function handles the Connector ID Status Change Interrupt.  It
+ * reads the OTG Interrupt Register (GOTCTL) to determine whether this
+ * is a Device to Host Mode transition or a Host Mode to Device
+ * Transition.  
+ *
+ * This only occurs when the cable is connected/removed from the PHY
+ * connector.
+ *
+ * @param core_if Programming view of DWC_otg controller.
+ */
+int32_t dwc_otg_handle_conn_id_status_change_intr(dwc_otg_core_if_t * core_if)
+{
+
+	/*
+	 * Need to disable SOF interrupt immediately. If switching from device
+	 * to host, the PCD interrupt handler won't handle the interrupt if
+	 * host mode is already set. The HCD interrupt handler won't get
+	 * called if the HCD state is HALT. This means that the interrupt does
+	 * not get handled and Linux complains loudly.
+	 */
+	gintmsk_data_t gintmsk = {.d32 = 0 };
+	gintsts_data_t gintsts = {.d32 = 0 };
+
+	gintmsk.b.sofintr = 1;
+	dwc_modify_reg32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
+
+	DWC_DEBUGPL(DBG_CIL,
+		    " ++Connector ID Status Change Interrupt++  (%s)\n",
+		    (dwc_otg_is_host_mode(core_if) ? "Host" : "Device"));
+
+	/*
+	 * Need to schedule a work, as there are possible DELAY function calls
+	 */
+	DWC_WORKQ_SCHEDULE(core_if->wq_otg, w_conn_id_status_change,
+			   core_if, "connection id status change");
+
+	/* Set flag and clear interrupt */
+	gintsts.b.conidstschng = 1;
+	dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32);
+
+	return 1;
+}
+
+/**
+ * This interrupt indicates that a device is initiating the Session
+ * Request Protocol to request the host to turn on bus power so a new
+ * session can begin. The handler responds by turning on bus power. If
+ * the DWC_otg controller is in low power mode, the handler brings the
+ * controller out of low power mode before turning on bus power.
+ *
+ * @param core_if Programming view of DWC_otg controller.
+ */
+int32_t dwc_otg_handle_session_req_intr(dwc_otg_core_if_t * core_if)
+{
+	hprt0_data_t hprt0;
+	gintsts_data_t gintsts;
+
+#ifndef DWC_HOST_ONLY
+	DWC_DEBUGPL(DBG_ANY, "++Session Request Interrupt++\n");
+
+	if (dwc_otg_is_device_mode(core_if)) {
+		DWC_PRINTF("SRP: Device mode\n");
+	} else {
+		DWC_PRINTF("SRP: Host mode\n");
+
+		/* Turn on the port power bit. */
+		hprt0.d32 = dwc_otg_read_hprt0(core_if);
+		hprt0.b.prtpwr = 1;
+		dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
+
+		/* Start the Connection timer. So a message can be displayed
+		 * if connect does not occur within 10 seconds. */
+		hcd_session_start(core_if);
+	}
+#endif
+
+	/* Clear interrupt */
+	gintsts.d32 = 0;
+	gintsts.b.sessreqintr = 1;
+	dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32);
+
+	return 1;
+}
+
+void w_wakeup_detected(void *p)
+{
+	dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) p;
+	/*
+	 * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
+	 * so that OPT tests pass with all PHYs).
+	 */
+	hprt0_data_t hprt0 = {.d32 = 0 };
+#if 0
+	pcgcctl_data_t pcgcctl = {.d32 = 0 };
+	/* Restart the Phy Clock */
+	pcgcctl.b.stoppclk = 1;
+	dwc_modify_reg32(core_if->pcgcctl, pcgcctl.d32, 0);
+	dwc_udelay(10);
+#endif				//0
+	hprt0.d32 = dwc_otg_read_hprt0(core_if);
+	DWC_DEBUGPL(DBG_ANY, "Resume: HPRT0=%0x\n", hprt0.d32);
+//      dwc_mdelay(70);
+	hprt0.b.prtres = 0;	/* Resume */
+	dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
+	DWC_DEBUGPL(DBG_ANY, "Clear Resume: HPRT0=%0x\n",
+		    dwc_read_reg32(core_if->host_if->hprt0));
+
+	hcd_resume(core_if);
+
+	/** Change to L0 state*/
+	core_if->lx_state = DWC_OTG_L0;
+
+}
+
+/**
+ * This interrupt indicates that the DWC_otg controller has detected a
+ * resume or remote wakeup sequence. If the DWC_otg controller is in
+ * low power mode, the handler must brings the controller out of low
+ * power mode. The controller automatically begins resume
+ * signaling. The handler schedules a time to stop resume signaling.
+ */
+int32_t dwc_otg_handle_wakeup_detected_intr(dwc_otg_core_if_t * core_if)
+{
+	gintsts_data_t gintsts;
+
+	DWC_DEBUGPL(DBG_ANY,
+		    "++Resume and Remote Wakeup Detected Interrupt++\n");
+
+	DWC_PRINTF("%s lxstate = %d\n", __func__, core_if->lx_state);
+
+	if (dwc_otg_is_device_mode(core_if)) {
+		dctl_data_t dctl = {.d32 = 0 };
+		DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n",
+			    dwc_read_reg32(&core_if->dev_if->dev_global_regs->
+					   dsts));
+		if (core_if->lx_state == DWC_OTG_L2) {
+#ifdef PARTIAL_POWER_DOWN
+			if (core_if->hwcfg4.b.power_optimiz) {
+				pcgcctl_data_t power = {.d32 = 0 };
+
+				power.d32 = dwc_read_reg32(core_if->pcgcctl);
+				DWC_DEBUGPL(DBG_CIL, "PCGCCTL=%0x\n",
+					    power.d32);
+
+				power.b.stoppclk = 0;
+				dwc_write_reg32(core_if->pcgcctl, power.d32);
+
+				power.b.pwrclmp = 0;
+				dwc_write_reg32(core_if->pcgcctl, power.d32);
+
+				power.b.rstpdwnmodule = 0;
+				dwc_write_reg32(core_if->pcgcctl, power.d32);
+			}
+#endif
+			/* Clear the Remote Wakeup Signalling */
+			dctl.b.rmtwkupsig = 1;
+			dwc_modify_reg32(&core_if->dev_if->dev_global_regs->
+					 dctl, dctl.d32, 0);
+
+			if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
+				core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->
+							       p);
+			}
+		} else {
+			glpmcfg_data_t lpmcfg;
+			lpmcfg.d32 =
+			    dwc_read_reg32(&core_if->core_global_regs->glpmcfg);
+			lpmcfg.b.hird_thres &= (~(1 << 4));
+			dwc_write_reg32(&core_if->core_global_regs->glpmcfg,
+					lpmcfg.d32);
+		}
+		/** Change to L0 state*/
+		core_if->lx_state = DWC_OTG_L0;
+	} else {
+		if (core_if->lx_state != DWC_OTG_L1) {
+			pcgcctl_data_t pcgcctl = {.d32 = 0 };
+
+			/* Restart the Phy Clock */
+			pcgcctl.b.stoppclk = 1;
+			dwc_modify_reg32(core_if->pcgcctl, pcgcctl.d32, 0);
+
+			DWC_TIMER_SCHEDULE(core_if->wkp_timer, 71);
+		} else {
+			/** Change to L0 state*/
+			core_if->lx_state = DWC_OTG_L0;
+		}
+	}
+
+	/* Clear interrupt */
+	gintsts.d32 = 0;
+	gintsts.b.wkupintr = 1;
+	dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32);
+
+	return 1;
+}
+
+/** 
+ * This interrupt indicates that a device has been disconnected from
+ * the root port. 
+ */
+int32_t dwc_otg_handle_disconnect_intr(dwc_otg_core_if_t * core_if)
+{
+	gintsts_data_t gintsts;
+
+	DWC_DEBUGPL(DBG_ANY, "++Disconnect Detected Interrupt++ (%s) %s\n",
+		    (dwc_otg_is_host_mode(core_if) ? "Host" : "Device"),
+		    op_state_str(core_if));
+
+/** @todo Consolidate this if statement. */
+#ifndef DWC_HOST_ONLY
+	if (core_if->op_state == B_HOST) {
+		/* If in device mode Disconnect and stop the HCD, then
+		 * start the PCD. */
+		hcd_disconnect(core_if);
+		pcd_start(core_if);
+		core_if->op_state = B_PERIPHERAL;
+	} else if (dwc_otg_is_device_mode(core_if)) {
+		gotgctl_data_t gotgctl = {.d32 = 0 };
+		gotgctl.d32 =
+		    dwc_read_reg32(&core_if->core_global_regs->gotgctl);
+		if (gotgctl.b.hstsethnpen == 1) {
+			/* Do nothing, if HNP in process the OTG
+			 * interrupt "Host Negotiation Detected"
+			 * interrupt will do the mode switch.
+			 */
+		} else if (gotgctl.b.devhnpen == 0) {
+			/* If in device mode Disconnect and stop the HCD, then
+			 * start the PCD. */
+			hcd_disconnect(core_if);
+			pcd_start(core_if);
+			core_if->op_state = B_PERIPHERAL;
+		} else {
+			DWC_DEBUGPL(DBG_ANY, "!a_peripheral && !devhnpen\n");
+		}
+	} else {
+		if (core_if->op_state == A_HOST) {
+			/* A-Cable still connected but device disconnected. */
+			hcd_disconnect(core_if);
+		}
+	}
+#endif
+	/* Change to L3(OFF) state */
+	core_if->lx_state = DWC_OTG_L3;
+
+	gintsts.d32 = 0;
+	gintsts.b.disconnect = 1;
+	dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32);
+	return 1;
+}
+
+/**
+ * This interrupt indicates that SUSPEND state has been detected on
+ * the USB.
+ * 
+ * For HNP the USB Suspend interrupt signals the change from
+ * "a_peripheral" to "a_host".
+ *
+ * When power management is enabled the core will be put in low power
+ * mode.
+ */
+int32_t dwc_otg_handle_usb_suspend_intr(dwc_otg_core_if_t * core_if)
+{
+	dsts_data_t dsts;
+	gintsts_data_t gintsts;
+
+	DWC_DEBUGPL(DBG_ANY, "USB SUSPEND\n");
+
+	if (dwc_otg_is_device_mode(core_if)) {
+		/* Check the Device status register to determine if the Suspend
+		 * state is active. */
+		dsts.d32 =
+		    dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
+		DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n", dsts.d32);
+		DWC_DEBUGPL(DBG_PCD, "DSTS.Suspend Status=%d "
+			    "HWCFG4.power Optimize=%d\n",
+			    dsts.b.suspsts, core_if->hwcfg4.b.power_optimiz);
+
+#ifdef PARTIAL_POWER_DOWN
+/** @todo Add a module parameter for power management. */
+
+		if (dsts.b.suspsts && core_if->hwcfg4.b.power_optimiz) {
+			pcgcctl_data_t power = {.d32 = 0 };
+			DWC_DEBUGPL(DBG_CIL, "suspend\n");
+
+			power.b.pwrclmp = 1;
+			dwc_write_reg32(core_if->pcgcctl, power.d32);
+
+			power.b.rstpdwnmodule = 1;
+			dwc_modify_reg32(core_if->pcgcctl, 0, power.d32);
+
+			power.b.stoppclk = 1;
+			dwc_modify_reg32(core_if->pcgcctl, 0, power.d32);
+
+		} else {
+			DWC_DEBUGPL(DBG_ANY, "disconnect?\n");
+		}
+#endif
+		/* PCD callback for suspend. */
+		pcd_suspend(core_if);
+	} else {
+		if (core_if->op_state == A_PERIPHERAL) {
+			DWC_DEBUGPL(DBG_ANY, "a_peripheral->a_host\n");
+			/* Clear the a_peripheral flag, back to a_host. */
+			pcd_stop(core_if);
+			hcd_start(core_if);
+			core_if->op_state = A_HOST;
+		}
+	}
+
+	/* Change to L2(suspend) state */
+	core_if->lx_state = DWC_OTG_L2;
+
+	/* Clear interrupt */
+	gintsts.d32 = 0;
+	gintsts.b.usbsuspend = 1;
+	dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32);
+
+	return 1;
+}
+
+#ifdef CONFIG_USB_DWC_OTG_LPM
+/**
+ * This function hadles LPM transaction received interrupt.
+ */
+static int32_t dwc_otg_handle_lpm_intr(dwc_otg_core_if_t * core_if)
+{
+	glpmcfg_data_t lpmcfg;
+	gintsts_data_t gintsts;
+
+	if (!core_if->core_params->lpm_enable) {
+		DWC_PRINTF("Unexpected LPM interrupt\n");
+	}
+
+	lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg);
+	DWC_PRINTF("LPM config register = 0x%08x\n", lpmcfg.d32);
+
+	if (dwc_otg_is_host_mode(core_if)) {
+		hcd_sleep(core_if);
+	} else {
+		lpmcfg.b.hird_thres |= (1 << 4);
+		dwc_write_reg32(&core_if->core_global_regs->glpmcfg,
+				lpmcfg.d32);
+	}
+
+	/* Examine prt_sleep_sts after TL1TokenTetry period max (10 us) */	
+	dwc_udelay(10);
+	lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg);
+	if (lpmcfg.b.prt_sleep_sts) {
+		/* Save the current state */
+		core_if->lx_state = DWC_OTG_L1;
+	}
+
+	/* Clear interrupt  */
+	gintsts.d32 = 0;
+	gintsts.b.lpmtranrcvd = 1;
+	dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32);
+	return 1;
+}
+#endif				/* CONFIG_USB_DWC_OTG_LPM */
+
+/**
+ * This function returns the Core Interrupt register.
+ */
+static inline uint32_t dwc_otg_read_common_intr(dwc_otg_core_if_t * core_if)
+{
+	gintsts_data_t gintsts;
+	gintmsk_data_t gintmsk;
+	gintmsk_data_t gintmsk_common = {.d32 = 0 };
+	gintmsk_common.b.wkupintr = 1;
+	gintmsk_common.b.sessreqintr = 1;
+	gintmsk_common.b.conidstschng = 1;
+	gintmsk_common.b.otgintr = 1;
+	gintmsk_common.b.modemismatch = 1;
+	gintmsk_common.b.disconnect = 1;
+	gintmsk_common.b.usbsuspend = 1;
+#ifdef CONFIG_USB_DWC_OTG_LPM
+	gintmsk_common.b.lpmtranrcvd = 1;
+#endif
+	/** @todo: The port interrupt occurs while in device 
+         * mode. Added code to CIL to clear the interrupt for now! 
+         */
+	gintmsk_common.b.portintr = 1;
+
+	gintsts.d32 = dwc_read_reg32(&core_if->core_global_regs->gintsts);
+	gintmsk.d32 = dwc_read_reg32(&core_if->core_global_regs->gintmsk);
+#ifdef DEBUG
+	/* if any common interrupts set */
+	if (gintsts.d32 & gintmsk_common.d32) {
+		DWC_DEBUGPL(DBG_ANY, "gintsts=%08x  gintmsk=%08x\n",
+			    gintsts.d32, gintmsk.d32);
+	}
+#endif
+
+	return ((gintsts.d32 & gintmsk.d32) & gintmsk_common.d32);
+
+}
+
+/**
+ * Common interrupt handler.
+ *
+ * The common interrupts are those that occur in both Host and Device mode. 
+ * This handler handles the following interrupts:
+ * - Mode Mismatch Interrupt
+ * - Disconnect Interrupt
+ * - OTG Interrupt
+ * - Connector ID Status Change Interrupt
+ * - Session Request Interrupt.
+ * - Resume / Remote Wakeup Detected Interrupt.
+ * - LPM Transaction Received Interrutp
+ * 
+ */
+int32_t dwc_otg_handle_common_intr(dwc_otg_core_if_t * core_if)
+{
+	int retval = 0;
+	gintsts_data_t gintsts;
+
+	gintsts.d32 = dwc_otg_read_common_intr(core_if);
+
+	if (gintsts.b.modemismatch) {
+		retval |= dwc_otg_handle_mode_mismatch_intr(core_if);
+	}
+	if (gintsts.b.otgintr) {
+		retval |= dwc_otg_handle_otg_intr(core_if);
+	}
+	if (gintsts.b.conidstschng) {
+		retval |= dwc_otg_handle_conn_id_status_change_intr(core_if);
+	}
+	if (gintsts.b.disconnect) {
+		retval |= dwc_otg_handle_disconnect_intr(core_if);
+	}
+	if (gintsts.b.sessreqintr) {
+		retval |= dwc_otg_handle_session_req_intr(core_if);
+	}
+	if (gintsts.b.wkupintr) {
+		retval |= dwc_otg_handle_wakeup_detected_intr(core_if);
+	}
+	if (gintsts.b.usbsuspend) {
+		retval |= dwc_otg_handle_usb_suspend_intr(core_if);
+	}
+#ifdef CONFIG_USB_DWC_OTG_LPM
+	if (gintsts.b.lpmtranrcvd) {
+		retval |= dwc_otg_handle_lpm_intr(core_if);
+	}
+#endif
+
+	if (gintsts.b.portintr && dwc_otg_is_device_mode(core_if)) {
+		/* The port interrupt occurs while in device mode with HPRT0
+		 * Port Enable/Disable.
+		 */
+		gintsts.d32 = 0;
+		gintsts.b.portintr = 1;
+		dwc_write_reg32(&core_if->core_global_regs->gintsts,
+				gintsts.d32);
+		retval |= 1;
+
+	}
+	return retval;
+}
diff --git a/drivers/usb/host/dwc_otg/dwc_otg_core_if.h b/drivers/usb/host/dwc_otg/dwc_otg_core_if.h
new file mode 100644
index 000000000000..4a78b03672f9
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/dwc_otg_core_if.h
@@ -0,0 +1,641 @@
+/* ==========================================================================
+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_core_if.h $
+ * $Revision: #4 $
+ * $Date: 2008/12/18 $
+ * $Change: 1155299 $
+ *
+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+ * otherwise expressly agreed to in writing between Synopsys and you.
+ *
+ * The Software IS NOT an item of Licensed Software or Licensed Product under
+ * any End User Software License Agreement or Agreement for Licensed Product
+ * with Synopsys or any supplement thereto. You are permitted to use and
+ * redistribute this Software in source and binary forms, with or without
+ * modification, provided that redistributions of source code must retain this
+ * notice. You may not view, use, disclose, copy or distribute this file or
+ * any information contained herein except pursuant to this license grant from
+ * Synopsys. If you do not agree with this notice, including the disclaimer
+ * below, then you are not authorized to use the Software.
+ *
+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ * ========================================================================== */
+#if !defined(__DWC_CORE_IF_H__)
+#define __DWC_CORE_IF_H__
+
+#include "dwc_os.h"
+
+/** @file
+ * This file defines DWC_OTG Core API
+ */
+
+struct dwc_otg_core_if;
+typedef struct dwc_otg_core_if dwc_otg_core_if_t;
+
+/** Maximum number of Periodic FIFOs */
+#define MAX_PERIO_FIFOS 15
+/** Maximum number of Periodic FIFOs */
+#define MAX_TX_FIFOS 15
+
+/** Maximum number of Endpoints/HostChannels */
+#define MAX_EPS_CHANNELS 16
+
+extern dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t * _reg_base_addr);
+extern void dwc_otg_core_init(dwc_otg_core_if_t * _core_if);
+extern void dwc_otg_cil_remove(dwc_otg_core_if_t * _core_if);
+
+extern void dwc_otg_enable_global_interrupts(dwc_otg_core_if_t * _core_if);
+extern void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t * _core_if);
+
+extern uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t * _core_if);
+extern uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t * _core_if);
+
+extern uint8_t dwc_otg_is_dma_enable(dwc_otg_core_if_t * core_if);
+
+/** This function should be called on every hardware interrupt. */
+extern int32_t dwc_otg_handle_common_intr(dwc_otg_core_if_t * _core_if);
+
+/** @name OTG Core Parameters */
+/** @{ */
+
+/**
+ * Specifies the OTG capabilities. The driver will automatically
+ * detect the value for this parameter if none is specified.
+ * 0 - HNP and SRP capable (default)
+ * 1 - SRP Only capable
+ * 2 - No HNP/SRP capable
+ */
+extern int dwc_otg_set_param_otg_cap(dwc_otg_core_if_t * core_if, int32_t val);
+extern int32_t dwc_otg_get_param_otg_cap(dwc_otg_core_if_t * core_if);
+#define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE 0
+#define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE 1
+#define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
+#define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE
+
+extern int dwc_otg_set_param_opt(dwc_otg_core_if_t * core_if, int32_t val);
+extern int32_t dwc_otg_get_param_opt(dwc_otg_core_if_t * core_if);
+#define dwc_param_opt_default 1
+
+/**
+ * Specifies whether to use slave or DMA mode for accessing the data
+ * FIFOs. The driver will automatically detect the value for this
+ * parameter if none is specified.
+ * 0 - Slave
+ * 1 - DMA (default, if available)
+ */
+extern int dwc_otg_set_param_dma_enable(dwc_otg_core_if_t * core_if,
+					int32_t val);
+extern int32_t dwc_otg_get_param_dma_enable(dwc_otg_core_if_t * core_if);
+#define dwc_param_dma_enable_default 1
+
+/**
+ * When DMA mode is enabled specifies whether to use
+ * address DMA or DMA Descritor mode for accessing the data
+ * FIFOs in device mode. The driver will automatically detect
+ * the value for this parameter if none is specified.
+ * 0 - address DMA
+ * 1 - DMA Descriptor(default, if available)
+ */
+extern int dwc_otg_set_param_dma_desc_enable(dwc_otg_core_if_t * core_if,
+					     int32_t val);
+extern int32_t dwc_otg_get_param_dma_desc_enable(dwc_otg_core_if_t * core_if);
+//#define dwc_param_dma_desc_enable_default 1
+#define dwc_param_dma_desc_enable_default 0 // Broadcom BCM2708
+
+/** The DMA Burst size (applicable only for External DMA
+ * Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32)
+ */
+extern int dwc_otg_set_param_dma_burst_size(dwc_otg_core_if_t * core_if,
+					    int32_t val);
+extern int32_t dwc_otg_get_param_dma_burst_size(dwc_otg_core_if_t * core_if);
+#define dwc_param_dma_burst_size_default 32
+
+/**
+ * Specifies the maximum speed of operation in host and device mode.
+ * The actual speed depends on the speed of the attached device and
+ * the value of phy_type. The actual speed depends on the speed of the
+ * attached device.
+ * 0 - High Speed (default)
+ * 1 - Full Speed
+ */
+extern int dwc_otg_set_param_speed(dwc_otg_core_if_t * core_if, int32_t val);
+extern int32_t dwc_otg_get_param_speed(dwc_otg_core_if_t * core_if);
+#define dwc_param_speed_default 0
+#define DWC_SPEED_PARAM_HIGH 0
+#define DWC_SPEED_PARAM_FULL 1
+
+/** Specifies whether low power mode is supported when attached
+ *	to a Full Speed or Low Speed device in host mode.
+ * 0 - Don't support low power mode (default)
+ * 1 - Support low power mode
+ */
+extern int dwc_otg_set_param_host_support_fs_ls_low_power(dwc_otg_core_if_t *
+							  core_if, int32_t val);
+extern int32_t dwc_otg_get_param_host_support_fs_ls_low_power(dwc_otg_core_if_t
+							      * core_if);
+#define dwc_param_host_support_fs_ls_low_power_default 0
+
+/** Specifies the PHY clock rate in low power mode when connected to a
+ * Low Speed device in host mode. This parameter is applicable only if
+ * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS
+ * then defaults to 6 MHZ otherwise 48 MHZ.
+ *
+ * 0 - 48 MHz
+ * 1 - 6 MHz
+ */
+extern int dwc_otg_set_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t *
+						       core_if, int32_t val);
+extern int32_t dwc_otg_get_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t *
+							   core_if);
+#define dwc_param_host_ls_low_power_phy_clk_default 0
+#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
+#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
+
+/**
+ * 0 - Use cC FIFO size parameters
+ * 1 - Allow dynamic FIFO sizing (default)
+ */
+extern int dwc_otg_set_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if,
+						 int32_t val);
+extern int32_t dwc_otg_get_param_enable_dynamic_fifo(dwc_otg_core_if_t *
+						     core_if);
+#define dwc_param_enable_dynamic_fifo_default 1
+
+/** Total number of 4-byte words in the data FIFO memory. This
+ * memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic
+ * Tx FIFOs.
+ * 32 to 32768 (default 8192)
+ * Note: The total FIFO memory depth in the FPGA configuration is 8192.
+ */
+extern int dwc_otg_set_param_data_fifo_size(dwc_otg_core_if_t * core_if,
+					    int32_t val);
+extern int32_t dwc_otg_get_param_data_fifo_size(dwc_otg_core_if_t * core_if);
+//#define dwc_param_data_fifo_size_default 8192
+#define dwc_param_data_fifo_size_default 0xFF0 // Broadcom BCM2708
+
+/** Number of 4-byte words in the Rx FIFO in device mode when dynamic
+ * FIFO sizing is enabled.
+ * 16 to 32768 (default 1064)
+ */
+extern int dwc_otg_set_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if,
+					      int32_t val);
+extern int32_t dwc_otg_get_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if);
+#define dwc_param_dev_rx_fifo_size_default 1064
+
+/** Number of 4-byte words in the non-periodic Tx FIFO in device mode
+ * when dynamic FIFO sizing is enabled.
+ * 16 to 32768 (default 1024)
+ */
+extern int dwc_otg_set_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t *
+						     core_if, int32_t val);
+extern int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t *
+							 core_if);
+#define dwc_param_dev_nperio_tx_fifo_size_default 1024
+
+/** Number of 4-byte words in each of the periodic Tx FIFOs in device
+ * mode when dynamic FIFO sizing is enabled.
+ * 4 to 768 (default 256)
+ */
+extern int dwc_otg_set_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
+						    int32_t val, int fifo_num);
+extern int32_t dwc_otg_get_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t *
+							core_if, int fifo_num);
+#define dwc_param_dev_perio_tx_fifo_size_default 256
+
+/** Number of 4-byte words in the Rx FIFO in host mode when dynamic
+ * FIFO sizing is enabled.
+ * 16 to 32768 (default 1024)
+ */
+extern int dwc_otg_set_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if,
+					       int32_t val);
+extern int32_t dwc_otg_get_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if);
+//#define dwc_param_host_rx_fifo_size_default 1024
+#define dwc_param_host_rx_fifo_size_default 774 // Broadcom BCM2708
+
+/** Number of 4-byte words in the non-periodic Tx FIFO in host mode
+ * when Dynamic FIFO sizing is enabled in the core.
+ * 16 to 32768 (default 1024)
+ */
+extern int dwc_otg_set_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t *
+						      core_if, int32_t val);
+extern int32_t dwc_otg_get_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t *
+							  core_if);
+//#define dwc_param_host_nperio_tx_fifo_size_default 1024
+#define dwc_param_host_nperio_tx_fifo_size_default 0x100 // Broadcom BCM2708
+
+/** Number of 4-byte words in the host periodic Tx FIFO when dynamic
+ * FIFO sizing is enabled.
+ * 16 to 32768 (default 1024)
+ */
+extern int dwc_otg_set_param_host_perio_tx_fifo_size(dwc_otg_core_if_t *
+						     core_if, int32_t val);
+extern int32_t dwc_otg_get_param_host_perio_tx_fifo_size(dwc_otg_core_if_t *
+							 core_if);
+//#define dwc_param_host_perio_tx_fifo_size_default 1024
+#define dwc_param_host_perio_tx_fifo_size_default 0x200 // Broadcom BCM2708
+
+/** The maximum transfer size supported in bytes.
+ * 2047 to 65,535  (default 65,535)
+ */
+extern int dwc_otg_set_param_max_transfer_size(dwc_otg_core_if_t * core_if,
+					       int32_t val);
+extern int32_t dwc_otg_get_param_max_transfer_size(dwc_otg_core_if_t * core_if);
+#define dwc_param_max_transfer_size_default 65535
+
+/** The maximum number of packets in a transfer.
+ * 15 to 511  (default 511)
+ */
+extern int dwc_otg_set_param_max_packet_count(dwc_otg_core_if_t * core_if,
+					      int32_t val);
+extern int32_t dwc_otg_get_param_max_packet_count(dwc_otg_core_if_t * core_if);
+#define dwc_param_max_packet_count_default 511
+
+/** The number of host channel registers to use.
+ * 1 to 16 (default 12)
+ * Note: The FPGA configuration supports a maximum of 12 host channels.
+ */
+extern int dwc_otg_set_param_host_channels(dwc_otg_core_if_t * core_if,
+					   int32_t val);
+extern int32_t dwc_otg_get_param_host_channels(dwc_otg_core_if_t * core_if);
+#define dwc_param_host_channels_default 12
+
+/** The number of endpoints in addition to EP0 available for device
+ * mode operations.
+ * 1 to 15 (default 6 IN and OUT)
+ * Note: The FPGA configuration supports a maximum of 6 IN and OUT
+ * endpoints in addition to EP0.
+ */
+extern int dwc_otg_set_param_dev_endpoints(dwc_otg_core_if_t * core_if,
+					   int32_t val);
+extern int32_t dwc_otg_get_param_dev_endpoints(dwc_otg_core_if_t * core_if);
+#define dwc_param_dev_endpoints_default 6
+
+/**
+ * Specifies the type of PHY interface to use. By default, the driver
+ * will automatically detect the phy_type.
+ *
+ * 0 - Full Speed PHY
+ * 1 - UTMI+ (default)
+ * 2 - ULPI
+ */
+extern int dwc_otg_set_param_phy_type(dwc_otg_core_if_t * core_if, int32_t val);
+extern int32_t dwc_otg_get_param_phy_type(dwc_otg_core_if_t * core_if);
+#define DWC_PHY_TYPE_PARAM_FS 0
+#define DWC_PHY_TYPE_PARAM_UTMI 1
+#define DWC_PHY_TYPE_PARAM_ULPI 2
+#define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI
+
+/**
+ * Specifies the UTMI+ Data Width.	This parameter is
+ * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI
+ * PHY_TYPE, this parameter indicates the data width between
+ * the MAC and the ULPI Wrapper.) Also, this parameter is
+ * applicable only if the OTG_HSPHY_WIDTH cC parameter was set
+ * to "8 and 16 bits", meaning that the core has been
+ * configured to work at either data path width.
+ *
+ * 8 or 16 bits (default 16)
+ */
+extern int dwc_otg_set_param_phy_utmi_width(dwc_otg_core_if_t * core_if,
+					    int32_t val);
+extern int32_t dwc_otg_get_param_phy_utmi_width(dwc_otg_core_if_t * core_if);
+//#define dwc_param_phy_utmi_width_default 16
+#define dwc_param_phy_utmi_width_default 8 // Broadcom BCM2708 
+
+/**
+ * Specifies whether the ULPI operates at double or single
+ * data rate. This parameter is only applicable if PHY_TYPE is
+ * ULPI.
+ *
+ * 0 - single data rate ULPI interface with 8 bit wide data
+ * bus (default)
+ * 1 - double data rate ULPI interface with 4 bit wide data
+ * bus
+ */
+extern int dwc_otg_set_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if,
+					  int32_t val);
+extern int32_t dwc_otg_get_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if);
+#define dwc_param_phy_ulpi_ddr_default 0
+
+/**
+ * Specifies whether to use the internal or external supply to
+ * drive the vbus with a ULPI phy.
+ */
+extern int dwc_otg_set_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if,
+					       int32_t val);
+extern int32_t dwc_otg_get_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if);
+#define DWC_PHY_ULPI_INTERNAL_VBUS 0
+#define DWC_PHY_ULPI_EXTERNAL_VBUS 1
+#define dwc_param_phy_ulpi_ext_vbus_default DWC_PHY_ULPI_INTERNAL_VBUS
+
+/**
+ * Specifies whether to use the I2Cinterface for full speed PHY. This
+ * parameter is only applicable if PHY_TYPE is FS.
+ * 0 - No (default)
+ * 1 - Yes
+ */
+extern int dwc_otg_set_param_i2c_enable(dwc_otg_core_if_t * core_if,
+					int32_t val);
+extern int32_t dwc_otg_get_param_i2c_enable(dwc_otg_core_if_t * core_if);
+#define dwc_param_i2c_enable_default 0
+
+extern int dwc_otg_set_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if,
+					int32_t val);
+extern int32_t dwc_otg_get_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if);
+#define dwc_param_ulpi_fs_ls_default 0
+
+extern int dwc_otg_set_param_ts_dline(dwc_otg_core_if_t * core_if, int32_t val);
+extern int32_t dwc_otg_get_param_ts_dline(dwc_otg_core_if_t * core_if);
+#define dwc_param_ts_dline_default 0
+
+/**
+ * Specifies whether dedicated transmit FIFOs are
+ * enabled for non periodic IN endpoints in device mode
+ * 0 - No
+ * 1 - Yes
+ */
+extern int dwc_otg_set_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if,
+						 int32_t val);
+extern int32_t dwc_otg_get_param_en_multiple_tx_fifo(dwc_otg_core_if_t *
+						     core_if);
+#define dwc_param_en_multiple_tx_fifo_default 1
+
+/** Number of 4-byte words in each of the Tx FIFOs in device
+ * mode when dynamic FIFO sizing is enabled.
+ * 4 to 768 (default 256)
+ */
+extern int dwc_otg_set_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if,
+					      int fifo_num, int32_t val);
+extern int32_t dwc_otg_get_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if,
+						  int fifo_num);
+#define dwc_param_dev_tx_fifo_size_default 256
+
+/** Thresholding enable flag-
+ * bit 0 - enable non-ISO Tx thresholding
+ * bit 1 - enable ISO Tx thresholding
+ * bit 2 - enable Rx thresholding
+ */
+extern int dwc_otg_set_param_thr_ctl(dwc_otg_core_if_t * core_if, int32_t val);
+extern int32_t dwc_otg_get_thr_ctl(dwc_otg_core_if_t * core_if, int fifo_num);
+#define dwc_param_thr_ctl_default 0
+
+/** Thresholding length for Tx
+ * FIFOs in 32 bit DWORDs
+ */
+extern int dwc_otg_set_param_tx_thr_length(dwc_otg_core_if_t * core_if,
+					   int32_t val);
+extern int32_t dwc_otg_get_tx_thr_length(dwc_otg_core_if_t * core_if);
+#define dwc_param_tx_thr_length_default 64
+
+/** Thresholding length for Rx
+ *	FIFOs in 32 bit DWORDs
+ */
+extern int dwc_otg_set_param_rx_thr_length(dwc_otg_core_if_t * core_if,
+					   int32_t val);
+extern int32_t dwc_otg_get_rx_thr_length(dwc_otg_core_if_t * core_if);
+#define dwc_param_rx_thr_length_default 64
+
+/**
+ * Specifies whether LPM (Link Power Management) support is enabled
+ */
+extern int dwc_otg_set_param_lpm_enable(dwc_otg_core_if_t * core_if,
+					int32_t val);
+extern int32_t dwc_otg_get_param_lpm_enable(dwc_otg_core_if_t * core_if);
+#define dwc_param_lpm_enable_default 1
+
+/**
+ * Specifies whether PTI enhancement is enabled
+ */
+extern int dwc_otg_set_param_pti_enable(dwc_otg_core_if_t * core_if,
+					int32_t val);
+extern int32_t dwc_otg_get_param_pti_enable(dwc_otg_core_if_t * core_if);
+#define dwc_param_pti_enable_default 0
+
+/**
+ * Specifies whether MPI enhancement is enabled
+ */
+extern int dwc_otg_set_param_mpi_enable(dwc_otg_core_if_t * core_if,
+					int32_t val);
+extern int32_t dwc_otg_get_param_mpi_enable(dwc_otg_core_if_t * core_if);
+#define dwc_param_mpi_enable_default 0
+
+/**
+ * Specifies whether IC_USB capability is enabled
+ */
+extern int dwc_otg_set_param_ic_usb_cap(dwc_otg_core_if_t * core_if,
+					int32_t val);
+extern int32_t dwc_otg_get_param_ic_usb_cap(dwc_otg_core_if_t * core_if);
+#define dwc_param_ic_usb_cap_default 0
+
+extern int dwc_otg_set_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if, int32_t val);
+extern int32_t dwc_otg_get_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if);
+#define dwc_param_ahb_thr_ratio_default 0
+
+/** @} */
+
+/** @name Access to registers and bit-fields */
+
+/**
+ * Dump core registers and SPRAM
+ */
+extern void dwc_otg_dump_dev_registers(dwc_otg_core_if_t * _core_if);
+extern void dwc_otg_dump_spram(dwc_otg_core_if_t * _core_if);
+extern void dwc_otg_dump_host_registers(dwc_otg_core_if_t * _core_if);
+extern void dwc_otg_dump_global_registers(dwc_otg_core_if_t * _core_if);
+
+/**
+ * Get host negotiation status.
+ */
+extern uint32_t dwc_otg_get_hnpstatus(dwc_otg_core_if_t * core_if);
+
+/**
+ * Get srp status
+ */
+extern uint32_t dwc_otg_get_srpstatus(dwc_otg_core_if_t * core_if);
+
+/**
+ * Set hnpreq bit in the GOTGCTL register.
+ */
+extern void dwc_otg_set_hnpreq(dwc_otg_core_if_t * core_if, uint32_t val);
+
+/**
+ * Get Content of SNPSID register.
+ */
+extern uint32_t dwc_otg_get_gsnpsid(dwc_otg_core_if_t * core_if);
+
+/**
+ * Get current mode.
+ * Returns 0 if in device mode, and 1 if in host mode.
+ */
+extern uint32_t dwc_otg_get_mode(dwc_otg_core_if_t * core_if);
+
+/**
+ * Get value of hnpcapable field in the GUSBCFG register
+ */
+extern uint32_t dwc_otg_get_hnpcapable(dwc_otg_core_if_t * core_if);
+/**
+ * Set value of hnpcapable field in the GUSBCFG register
+ */
+extern void dwc_otg_set_hnpcapable(dwc_otg_core_if_t * core_if, uint32_t val);
+
+/**
+ * Get value of srpcapable field in the GUSBCFG register
+ */
+extern uint32_t dwc_otg_get_srpcapable(dwc_otg_core_if_t * core_if);
+/**
+ * Set value of srpcapable field in the GUSBCFG register
+ */
+extern void dwc_otg_set_srpcapable(dwc_otg_core_if_t * core_if, uint32_t val);
+
+/**
+ * Get value of devspeed field in the DCFG register
+ */
+extern uint32_t dwc_otg_get_devspeed(dwc_otg_core_if_t * core_if);
+/**
+ * Set value of devspeed field in the DCFG register
+ */
+extern void dwc_otg_set_devspeed(dwc_otg_core_if_t * core_if, uint32_t val);
+
+/**
+ * Get the value of busconnected field from the HPRT0 register
+ */
+extern uint32_t dwc_otg_get_busconnected(dwc_otg_core_if_t * core_if);
+
+/**
+ * Gets the device enumeration Speed.
+ */
+extern uint32_t dwc_otg_get_enumspeed(dwc_otg_core_if_t * core_if);
+
+/**
+ * Get value of prtpwr field from the HPRT0 register
+ */
+extern uint32_t dwc_otg_get_prtpower(dwc_otg_core_if_t * core_if);
+/**
+ * Set value of prtpwr field from the HPRT0 register
+ */
+extern void dwc_otg_set_prtpower(dwc_otg_core_if_t * core_if, uint32_t val);
+
+/**
+ * Get value of prtsusp field from the HPRT0 regsiter
+ */
+extern uint32_t dwc_otg_get_prtsuspend(dwc_otg_core_if_t * core_if);
+/**
+ * Set value of prtpwr field from the HPRT0 register
+ */
+extern void dwc_otg_set_prtsuspend(dwc_otg_core_if_t * core_if, uint32_t val);
+
+/**
+ * Set value of prtres field from the HPRT0 register
+ *FIXME Remove?
+ */
+extern void dwc_otg_set_prtresume(dwc_otg_core_if_t * core_if, uint32_t val);
+
+/**
+ * Get value of rmtwkupsig bit in DCTL register
+ */
+extern uint32_t dwc_otg_get_remotewakesig(dwc_otg_core_if_t * core_if);
+
+/**
+ * Get value of prt_sleep_sts field from the GLPMCFG register
+ */
+extern uint32_t dwc_otg_get_lpm_portsleepstatus(dwc_otg_core_if_t * core_if);
+
+/**
+ * Get value of rem_wkup_en field from the GLPMCFG register
+ */
+extern uint32_t dwc_otg_get_lpm_remotewakeenabled(dwc_otg_core_if_t * core_if);
+
+/**
+ * Get value of appl_resp field from the GLPMCFG register
+ */
+extern uint32_t dwc_otg_get_lpmresponse(dwc_otg_core_if_t * core_if);
+/**
+ * Set value of appl_resp field from the GLPMCFG register
+ */
+extern void dwc_otg_set_lpmresponse(dwc_otg_core_if_t * core_if, uint32_t val);
+
+/**
+ * Get value of hsic_connect field from the GLPMCFG register
+ */
+extern uint32_t dwc_otg_get_hsic_connect(dwc_otg_core_if_t * core_if);
+/**
+ * Set value of hsic_connect field from the GLPMCFG register
+ */
+extern void dwc_otg_set_hsic_connect(dwc_otg_core_if_t * core_if, uint32_t val);
+
+/**
+ * Get value of inv_sel_hsic field from the GLPMCFG register.
+ */
+extern uint32_t dwc_otg_get_inv_sel_hsic(dwc_otg_core_if_t * core_if);
+/**
+ * Set value of inv_sel_hsic field from the GLPMFG register.
+ */
+extern void dwc_otg_set_inv_sel_hsic(dwc_otg_core_if_t * core_if, uint32_t val);
+
+/*
+ * Some functions for accessing registers
+ */
+
+/**
+ *  GOTGCTL register
+ */
+extern uint32_t dwc_otg_get_gotgctl(dwc_otg_core_if_t * core_if);
+extern void dwc_otg_set_gotgctl(dwc_otg_core_if_t * core_if, uint32_t val);
+
+/**
+ * GUSBCFG register
+ */
+extern uint32_t dwc_otg_get_gusbcfg(dwc_otg_core_if_t * core_if);
+extern void dwc_otg_set_gusbcfg(dwc_otg_core_if_t * core_if, uint32_t val);
+
+/**
+ * GRXFSIZ register
+ */
+extern uint32_t dwc_otg_get_grxfsiz(dwc_otg_core_if_t * core_if);
+extern void dwc_otg_set_grxfsiz(dwc_otg_core_if_t * core_if, uint32_t val);
+
+/**
+ * GNPTXFSIZ register
+ */
+extern uint32_t dwc_otg_get_gnptxfsiz(dwc_otg_core_if_t * core_if);
+extern void dwc_otg_set_gnptxfsiz(dwc_otg_core_if_t * core_if, uint32_t val);
+
+extern uint32_t dwc_otg_get_gpvndctl(dwc_otg_core_if_t * core_if);
+extern void dwc_otg_set_gpvndctl(dwc_otg_core_if_t * core_if, uint32_t val);
+
+/**
+ * GGPIO register
+ */
+extern uint32_t dwc_otg_get_ggpio(dwc_otg_core_if_t * core_if);
+extern void dwc_otg_set_ggpio(dwc_otg_core_if_t * core_if, uint32_t val);
+
+/**
+ * GUID register
+ */
+extern uint32_t dwc_otg_get_guid(dwc_otg_core_if_t * core_if);
+extern void dwc_otg_set_guid(dwc_otg_core_if_t * core_if, uint32_t val);
+
+/**
+ * HPRT0 register
+ */
+extern uint32_t dwc_otg_get_hprt0(dwc_otg_core_if_t * core_if);
+extern void dwc_otg_set_hprt0(dwc_otg_core_if_t * core_if, uint32_t val);
+
+/**
+ * GHPTXFSIZE
+ */
+extern uint32_t dwc_otg_get_hptxfsiz(dwc_otg_core_if_t * core_if);
+
+/** @} */
+
+#endif				/* __DWC_CORE_IF_H__ */
diff --git a/drivers/usb/host/dwc_otg/dwc_otg_dbg.h b/drivers/usb/host/dwc_otg/dwc_otg_dbg.h
new file mode 100644
index 000000000000..e81d0935512e
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/dwc_otg_dbg.h
@@ -0,0 +1,113 @@
+/* ==========================================================================
+ *
+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+ * otherwise expressly agreed to in writing between Synopsys and you.
+ * 
+ * The Software IS NOT an item of Licensed Software or Licensed Product under
+ * any End User Software License Agreement or Agreement for Licensed Product
+ * with Synopsys or any supplement thereto. You are permitted to use and
+ * redistribute this Software in source and binary forms, with or without
+ * modification, provided that redistributions of source code must retain this
+ * notice. You may not view, use, disclose, copy or distribute this file or
+ * any information contained herein except pursuant to this license grant from
+ * Synopsys. If you do not agree with this notice, including the disclaimer
+ * below, then you are not authorized to use the Software.
+ * 
+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ * ========================================================================== */
+
+#ifndef __DWC_OTG_DBG_H__
+#define __DWC_OTG_DBG_H__
+
+/** @file
+ * This file defines debug levels.
+ * Debugging support vanishes in non-debug builds.  
+ */
+
+/**
+ * The Debug Level bit-mask variable.
+ */
+extern uint32_t g_dbg_lvl;
+/**
+ * Set the Debug Level variable.
+ */
+static inline uint32_t SET_DEBUG_LEVEL(const uint32_t new)
+{
+	uint32_t old = g_dbg_lvl;
+	g_dbg_lvl = new;
+	return old;
+}
+
+/** When debug level has the DBG_CIL bit set, display CIL Debug messages. */
+#define DBG_CIL		(0x2)
+/** When debug level has the DBG_CILV bit set, display CIL Verbose debug
+ * messages */
+#define DBG_CILV	(0x20)
+/**  When debug level has the DBG_PCD bit set, display PCD (Device) debug
+ *  messages */
+#define DBG_PCD		(0x4)
+/** When debug level has the DBG_PCDV set, display PCD (Device) Verbose debug
+ * messages */
+#define DBG_PCDV	(0x40)
+/** When debug level has the DBG_HCD bit set, display Host debug messages */
+#define DBG_HCD		(0x8)
+/** When debug level has the DBG_HCDV bit set, display Verbose Host debug
+ * messages */
+#define DBG_HCDV	(0x80)
+/** When debug level has the DBG_HCD_URB bit set, display enqueued URBs in host
+ *  mode. */
+#define DBG_HCD_URB	(0x800)
+
+/** When debug level has any bit set, display debug messages */
+#define DBG_ANY		(0xFF)
+
+/** All debug messages off */
+#define DBG_OFF		0
+
+/** Prefix string for DWC_DEBUG print macros. */
+#define USB_DWC "DWC_otg: "
+
+/** 
+ * Print a debug message when the Global debug level variable contains
+ * the bit defined in <code>lvl</code>.
+ *
+ * @param[in] lvl - Debug level, use one of the DBG_ constants above.
+ * @param[in] x - like printf
+ *
+ *    Example:<p>
+ * <code>
+ *      DWC_DEBUGPL( DBG_ANY, "%s(%p)\n", __func__, _reg_base_addr);
+ * </code>
+ * <br>
+ * results in:<br> 
+ * <code>
+ * usb-DWC_otg: dwc_otg_cil_init(ca867000)
+ * </code>
+ */
+#ifdef DEBUG
+
+# define DWC_DEBUGPL(lvl, x...) do{ if ((lvl)&g_dbg_lvl)__DWC_DEBUG(USB_DWC x ); }while(0)
+# define DWC_DEBUGP(x...)	DWC_DEBUGPL(DBG_ANY, x )
+
+# define CHK_DEBUG_LEVEL(level) ((level) & g_dbg_lvl)
+
+#else
+
+# define DWC_DEBUGPL(lvl, x...) do{}while(0)
+# define DWC_DEBUGP(x...)
+
+# define CHK_DEBUG_LEVEL(level) (0)
+
+#endif /*DEBUG*/
+#endif
diff --git a/drivers/usb/host/dwc_otg/dwc_otg_driver.c b/drivers/usb/host/dwc_otg/dwc_otg_driver.c
new file mode 100644
index 000000000000..0e220137d235
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/dwc_otg_driver.c
@@ -0,0 +1,1577 @@
+/* ==========================================================================
+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.c $
+ * $Revision: #76 $
+ * $Date: 2009/05/03 $
+ * $Change: 1245589 $
+ *
+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+ * otherwise expressly agreed to in writing between Synopsys and you.
+ *
+ * The Software IS NOT an item of Licensed Software or Licensed Product under
+ * any End User Software License Agreement or Agreement for Licensed Product
+ * with Synopsys or any supplement thereto. You are permitted to use and
+ * redistribute this Software in source and binary forms, with or without
+ * modification, provided that redistributions of source code must retain this
+ * notice. You may not view, use, disclose, copy or distribute this file or
+ * any information contained herein except pursuant to this license grant from
+ * Synopsys. If you do not agree with this notice, including the disclaimer
+ * below, then you are not authorized to use the Software.
+ *
+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ * ========================================================================== */
+
+/** @file
+ * The dwc_otg_driver module provides the initialization and cleanup entry
+ * points for the DWC_otg driver. This module will be dynamically installed
+ * after Linux is booted using the insmod command. When the module is
+ * installed, the dwc_otg_driver_init function is called. When the module is
+ * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
+ *
+ * This module also defines a data structure for the dwc_otg_driver, which is
+ * used in conjunction with the standard ARM lm_device structure. These
+ * structures allow the OTG driver to comply with the standard Linux driver
+ * model in which devices and drivers are registered with a bus driver. This
+ * has the benefit that Linux can expose attributes of the driver and device
+ * in its special sysfs file system. Users can then read or write files in
+ * this file system to perform diagnostics on the driver components or the
+ * device.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/types.h>
+#include <linux/stat.h>		/* permission constants */
+#include <linux/version.h>
+#include <linux/interrupt.h>
+
+#ifdef LM_INTERFACE
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30))
+#include <asm/arch/lm.h>
+#include <asm/arch/hardware.h>
+#else
+/* in 2.6.31, at least, we seem to have lost the generic LM infrastructure -
+   here we use definitions stolen from arm-integrator headers
+*/
+#include <mach/lm.h>
+#include <mach/hardware.h>
+#endif
+#include <asm/sizes.h>
+#include <asm/mach/map.h>
+
+#elif defined(PLATFORM_INTERFACE)
+
+#include <linux/platform_device.h>
+#include <asm/mach/map.h>
+
+#endif
+
+# include <linux/irq.h>
+
+#include <asm/io.h>
+
+
+#include "dwc_os.h"
+#include "dwc_otg_dbg.h"
+#include "dwc_otg_driver.h"
+#include "dwc_otg_attr.h"
+#include "dwc_otg_core_if.h"
+#include "dwc_otg_pcd_if.h"
+#include "dwc_otg_hcd_if.h"
+
+#define DWC_DRIVER_VERSION	"2.90b 6-MAY-2010"
+#define DWC_DRIVER_DESC		"HS OTG USB Controller driver"
+
+static const char dwc_driver_name[] = "dwc_otg";
+
+extern int pcd_init(
+#ifdef LM_INTERFACE
+	struct lm_device *_dev
+#elif  defined(PCI_INTERFACE)
+	struct pci_dev *_dev
+#elif  defined(PLATFORM_INTERFACE)
+	struct platform_device *dev
+#endif
+        );
+extern int hcd_init(
+#ifdef LM_INTERFACE
+	struct lm_device *_dev
+#elif  defined(PCI_INTERFACE)
+	struct pci_dev *_dev
+#elif  defined(PLATFORM_INTERFACE)
+	struct platform_device *dev
+#endif
+        );
+
+extern int pcd_remove(
+#ifdef LM_INTERFACE
+	struct lm_device *_dev
+#elif  defined(PCI_INTERFACE)
+	struct pci_dev *_dev
+#elif  defined(PLATFORM_INTERFACE)
+	struct platform_device *_dev
+#endif
+        );
+
+extern void hcd_remove(
+#ifdef LM_INTERFACE
+	struct lm_device *_dev
+#elif  defined(PCI_INTERFACE)
+	struct pci_dev *_dev
+#elif  defined(PLATFORM_INTERFACE)
+	struct platform_device *_dev
+#endif
+        );
+
+/*-------------------------------------------------------------------------*/
+/* Encapsulate the module parameter settings */
+
+struct dwc_otg_driver_module_params {
+	int32_t opt;
+	int32_t otg_cap;
+	int32_t dma_enable;
+	int32_t dma_desc_enable;
+	int32_t dma_burst_size;
+	int32_t speed;
+	int32_t host_support_fs_ls_low_power;
+	int32_t host_ls_low_power_phy_clk;
+	int32_t enable_dynamic_fifo;
+	int32_t data_fifo_size;
+	int32_t dev_rx_fifo_size;
+	int32_t dev_nperio_tx_fifo_size;
+	uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
+	int32_t host_rx_fifo_size;
+	int32_t host_nperio_tx_fifo_size;
+	int32_t host_perio_tx_fifo_size;
+	int32_t max_transfer_size;
+	int32_t max_packet_count;
+	int32_t host_channels;
+	int32_t dev_endpoints;
+	int32_t phy_type;
+	int32_t phy_utmi_width;
+	int32_t phy_ulpi_ddr;
+	int32_t phy_ulpi_ext_vbus;
+	int32_t i2c_enable;
+	int32_t ulpi_fs_ls;
+	int32_t ts_dline;
+	int32_t en_multiple_tx_fifo;
+	uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
+	uint32_t thr_ctl;
+	uint32_t tx_thr_length;
+	uint32_t rx_thr_length;
+	int32_t pti_enable;
+	int32_t mpi_enable;
+	int32_t lpm_enable;
+	int32_t ic_usb_cap;
+	int32_t ahb_thr_ratio;
+};
+
+static struct dwc_otg_driver_module_params dwc_otg_module_params = {
+	.opt = -1,
+	.otg_cap = -1,
+	.dma_enable = -1,
+	.dma_desc_enable = -1,
+	.dma_burst_size = -1,
+	.speed = -1,
+	.host_support_fs_ls_low_power = -1,
+	.host_ls_low_power_phy_clk = -1,
+	.enable_dynamic_fifo = -1,
+	.data_fifo_size = -1,
+	.dev_rx_fifo_size = -1,
+	.dev_nperio_tx_fifo_size = -1,
+	.dev_perio_tx_fifo_size = {
+				   /* dev_perio_tx_fifo_size_1 */
+				   -1,
+				   -1,
+				   -1,
+				   -1,
+				   -1,
+				   -1,
+				   -1,
+				   -1,
+				   -1,
+				   -1,
+				   -1,
+				   -1,
+				   -1,
+				   -1,
+				   -1
+				   /* 15 */
+				   },
+	.host_rx_fifo_size = -1,
+	.host_nperio_tx_fifo_size = -1,
+	.host_perio_tx_fifo_size = -1,
+	.max_transfer_size = -1,
+	.max_packet_count = -1,
+	.host_channels = -1,
+	.dev_endpoints = -1,
+	.phy_type = -1,
+	.phy_utmi_width = -1,
+	.phy_ulpi_ddr = -1,
+	.phy_ulpi_ext_vbus = -1,
+	.i2c_enable = -1,
+	.ulpi_fs_ls = -1,
+	.ts_dline = -1,
+	.en_multiple_tx_fifo = -1,
+	.dev_tx_fifo_size = {
+			     /* dev_tx_fifo_size */
+			     -1,
+			     -1,
+			     -1,
+			     -1,
+			     -1,
+			     -1,
+			     -1,
+			     -1,
+			     -1,
+			     -1,
+			     -1,
+			     -1,
+			     -1,
+			     -1,
+			     -1
+			     /* 15 */
+			     },
+	.thr_ctl = -1,
+	.tx_thr_length = -1,
+	.rx_thr_length = -1,
+	.pti_enable = -1,
+	.mpi_enable = -1,
+	.lpm_enable = -1,
+	.ic_usb_cap = -1,
+	.ahb_thr_ratio = -1,
+};
+
+/**
+ * This function shows the Driver Version.
+ */
+static ssize_t version_show(struct device_driver *dev, char *buf)
+{
+	return snprintf(buf, sizeof(DWC_DRIVER_VERSION) + 2, "%s\n",
+			DWC_DRIVER_VERSION);
+}
+
+static DRIVER_ATTR(version, S_IRUGO, version_show, NULL);
+
+/**
+ * Global Debug Level Mask.
+ */
+uint32_t g_dbg_lvl = 0;		/* OFF */
+
+/**
+ * This function shows the driver Debug Level.
+ */
+static ssize_t dbg_level_show(struct device_driver *drv, char *buf)
+{
+	return sprintf(buf, "0x%0x\n", g_dbg_lvl);
+}
+
+/**
+ * This function stores the driver Debug Level.
+ */
+static ssize_t dbg_level_store(struct device_driver *drv, const char *buf,
+			       size_t count)
+{
+	g_dbg_lvl = simple_strtoul(buf, NULL, 16);
+	return count;
+}
+
+static DRIVER_ATTR(debuglevel, S_IRUGO | S_IWUSR, dbg_level_show,
+		   dbg_level_store);
+
+/**
+ * This function is called during module intialization
+ * to pass module parameters to the DWC_OTG CORE.
+ */
+static int set_parameters(dwc_otg_core_if_t * core_if)
+{
+	int retval = 0;
+	int i;
+
+	if (dwc_otg_module_params.otg_cap != -1) {
+		retval +=
+		    dwc_otg_set_param_otg_cap(core_if,
+					      dwc_otg_module_params.otg_cap);
+	}
+	if (dwc_otg_module_params.dma_enable != -1) {
+		retval +=
+		    dwc_otg_set_param_dma_enable(core_if,
+						 dwc_otg_module_params.
+						 dma_enable);
+	}
+	if (dwc_otg_module_params.dma_desc_enable != -1) {
+		retval +=
+		    dwc_otg_set_param_dma_desc_enable(core_if,
+						      dwc_otg_module_params.
+						      dma_desc_enable);
+	}
+	if (dwc_otg_module_params.opt != -1) {
+		retval +=
+		    dwc_otg_set_param_opt(core_if, dwc_otg_module_params.opt);
+	}
+	if (dwc_otg_module_params.dma_burst_size != -1) {
+		retval +=
+		    dwc_otg_set_param_dma_burst_size(core_if,
+						     dwc_otg_module_params.
+						     dma_burst_size);
+	}
+	if (dwc_otg_module_params.host_support_fs_ls_low_power != -1) {
+		retval +=
+		    dwc_otg_set_param_host_support_fs_ls_low_power(core_if,
+								   dwc_otg_module_params.
+								   host_support_fs_ls_low_power);
+	}
+	if (dwc_otg_module_params.enable_dynamic_fifo != -1) {
+		retval +=
+		    dwc_otg_set_param_enable_dynamic_fifo(core_if,
+							  dwc_otg_module_params.
+							  enable_dynamic_fifo);
+	}
+	if (dwc_otg_module_params.data_fifo_size != -1) {
+		retval +=
+		    dwc_otg_set_param_data_fifo_size(core_if,
+						     dwc_otg_module_params.
+						     data_fifo_size);
+	}
+	if (dwc_otg_module_params.dev_rx_fifo_size != -1) {
+		retval +=
+		    dwc_otg_set_param_dev_rx_fifo_size(core_if,
+						       dwc_otg_module_params.
+						       dev_rx_fifo_size);
+	}
+	if (dwc_otg_module_params.dev_nperio_tx_fifo_size != -1) {
+		retval +=
+		    dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if,
+							      dwc_otg_module_params.
+							      dev_nperio_tx_fifo_size);
+	}
+	if (dwc_otg_module_params.host_rx_fifo_size != -1) {
+		retval +=
+		    dwc_otg_set_param_host_rx_fifo_size(core_if,
+							dwc_otg_module_params.host_rx_fifo_size);
+	}
+	if (dwc_otg_module_params.host_nperio_tx_fifo_size != -1) {
+		retval +=
+		    dwc_otg_set_param_host_nperio_tx_fifo_size(core_if,
+							       dwc_otg_module_params.
+							       host_nperio_tx_fifo_size);
+	}
+	if (dwc_otg_module_params.host_perio_tx_fifo_size != -1) {
+		retval +=
+		    dwc_otg_set_param_host_perio_tx_fifo_size(core_if,
+							      dwc_otg_module_params.
+							      host_perio_tx_fifo_size);
+	}
+	if (dwc_otg_module_params.max_transfer_size != -1) {
+		retval +=
+		    dwc_otg_set_param_max_transfer_size(core_if,
+							dwc_otg_module_params.
+							max_transfer_size);
+	}
+	if (dwc_otg_module_params.max_packet_count != -1) {
+		retval +=
+		    dwc_otg_set_param_max_packet_count(core_if,
+						       dwc_otg_module_params.
+						       max_packet_count);
+	}
+	if (dwc_otg_module_params.host_channels != -1) {
+		retval +=
+		    dwc_otg_set_param_host_channels(core_if,
+						    dwc_otg_module_params.
+						    host_channels);
+	}
+	if (dwc_otg_module_params.dev_endpoints != -1) {
+		retval +=
+		    dwc_otg_set_param_dev_endpoints(core_if,
+						    dwc_otg_module_params.
+						    dev_endpoints);
+	}
+	if (dwc_otg_module_params.phy_type != -1) {
+		retval +=
+		    dwc_otg_set_param_phy_type(core_if,
+					       dwc_otg_module_params.phy_type);
+	}
+	if (dwc_otg_module_params.speed != -1) {
+		retval +=
+		    dwc_otg_set_param_speed(core_if,
+					    dwc_otg_module_params.speed);
+	}
+	if (dwc_otg_module_params.host_ls_low_power_phy_clk != -1) {
+		retval +=
+		    dwc_otg_set_param_host_ls_low_power_phy_clk(core_if,
+								dwc_otg_module_params.
+								host_ls_low_power_phy_clk);
+	}
+	if (dwc_otg_module_params.phy_ulpi_ddr != -1) {
+		retval +=
+		    dwc_otg_set_param_phy_ulpi_ddr(core_if,
+						   dwc_otg_module_params.
+						   phy_ulpi_ddr);
+	}
+	if (dwc_otg_module_params.phy_ulpi_ext_vbus != -1) {
+		retval +=
+		    dwc_otg_set_param_phy_ulpi_ext_vbus(core_if,
+							dwc_otg_module_params.
+							phy_ulpi_ext_vbus);
+	}
+	if (dwc_otg_module_params.phy_utmi_width != -1) {
+		retval +=
+		    dwc_otg_set_param_phy_utmi_width(core_if,
+						     dwc_otg_module_params.
+						     phy_utmi_width);
+	}
+	if (dwc_otg_module_params.ulpi_fs_ls != -1) {
+		retval +=
+		    dwc_otg_set_param_ulpi_fs_ls(core_if, dwc_otg_module_params.ulpi_fs_ls);
+	}
+	if (dwc_otg_module_params.ts_dline != -1) {
+		retval +=
+		    dwc_otg_set_param_ts_dline(core_if,
+					       dwc_otg_module_params.ts_dline);
+	}
+	if (dwc_otg_module_params.i2c_enable != -1) {
+		retval +=
+		    dwc_otg_set_param_i2c_enable(core_if,
+						 dwc_otg_module_params.
+						 i2c_enable);
+	}
+	if (dwc_otg_module_params.en_multiple_tx_fifo != -1) {
+		retval +=
+		    dwc_otg_set_param_en_multiple_tx_fifo(core_if,
+							  dwc_otg_module_params.
+							  en_multiple_tx_fifo);
+	}
+	for (i = 0; i < 15; i++) {
+		if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] != -1) {
+			retval +=
+			    dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
+								     dwc_otg_module_params.
+								     dev_perio_tx_fifo_size
+								     [i], i);
+		}
+	}
+
+	for (i = 0; i < 15; i++) {
+		if (dwc_otg_module_params.dev_tx_fifo_size[i] != -1) {
+			retval += dwc_otg_set_param_dev_tx_fifo_size(core_if,
+								     dwc_otg_module_params.
+								     dev_tx_fifo_size
+								     [i], i);
+		}
+	}
+	if (dwc_otg_module_params.thr_ctl != -1) {
+		retval +=
+		    dwc_otg_set_param_thr_ctl(core_if,
+					      dwc_otg_module_params.thr_ctl);
+	}
+	if (dwc_otg_module_params.mpi_enable != -1) {
+		retval +=
+		    dwc_otg_set_param_mpi_enable(core_if,
+						 dwc_otg_module_params.
+						 mpi_enable);
+	}
+	if (dwc_otg_module_params.pti_enable != -1) {
+		retval +=
+		    dwc_otg_set_param_pti_enable(core_if,
+						 dwc_otg_module_params.
+						 pti_enable);
+	}
+	if (dwc_otg_module_params.lpm_enable != -1) {
+		retval +=
+		    dwc_otg_set_param_lpm_enable(core_if,
+						 dwc_otg_module_params.
+						 lpm_enable);
+	}
+	if (dwc_otg_module_params.ic_usb_cap != -1) {
+		retval +=
+		    dwc_otg_set_param_ic_usb_cap(core_if,
+						 dwc_otg_module_params.
+						 ic_usb_cap);
+	}
+	if (dwc_otg_module_params.tx_thr_length != -1) {
+		retval +=
+		    dwc_otg_set_param_tx_thr_length(core_if,
+						    dwc_otg_module_params.tx_thr_length);
+	}
+	if (dwc_otg_module_params.rx_thr_length != -1) {
+		retval +=
+		    dwc_otg_set_param_rx_thr_length(core_if,
+						    dwc_otg_module_params.
+						    rx_thr_length);
+	}
+	if(dwc_otg_module_params.ahb_thr_ratio != -1) {
+		retval +=
+		    dwc_otg_set_param_ahb_thr_ratio(core_if, dwc_otg_module_params.ahb_thr_ratio);
+	}
+	return retval;
+}
+
+/**
+ * This function is the top level interrupt handler for the Common
+ * (Device and host modes) interrupts.
+ */
+static irqreturn_t dwc_otg_common_irq(int irq, void *dev)
+{
+	dwc_otg_device_t *otg_dev = dev;
+	int32_t retval = IRQ_NONE;
+
+	retval = dwc_otg_handle_common_intr(otg_dev->core_if);
+	if (retval != 0) {
+		S3C2410X_CLEAR_EINTPEND();
+	}
+	return IRQ_RETVAL(retval);
+}
+
+/**
+ * This function is called when a lm_device is unregistered with the
+ * dwc_otg_driver. This happens, for example, when the rmmod command is
+ * executed. The device may or may not be electrically present. If it is
+ * present, the driver stops device processing. Any resources used on behalf
+ * of this device are freed.
+ *
+ * @param _dev
+ */
+#ifdef LM_INTERFACE
+static void dwc_otg_driver_remove(
+     struct lm_device *_dev
+#elif  defined(PCI_INTERFACE)
+static void dwc_otg_driver_remove(
+     struct pci_dev *_dev
+#elif  defined(PLATFORM_INTERFACE)
+static int dwc_otg_driver_remove(
+     struct platform_device *_dev
+#endif
+)
+
+{
+#ifdef LM_INTERFACE
+	dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev);
+#elif  defined(PCI_INTERFACE)
+	dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev);
+#elif  defined(PLATFORM_INTERFACE)
+	dwc_otg_device_t *otg_dev = platform_get_drvdata(_dev);
+#endif
+
+
+	DWC_DEBUGPL(DBG_ANY, "%s(%p) otg_dev %p\n", __func__, _dev, otg_dev);
+
+	if (!otg_dev) {
+		/* Memory allocation for the dwc_otg_device failed. */
+		DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
+#ifdef PLATFORM_INTERFACE
+                return -ENOMEM;
+#else
+		return;
+#endif
+	}
+#ifndef DWC_DEVICE_ONLY
+	if (otg_dev->hcd) {
+		hcd_remove(_dev);
+	} else {
+		DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
+#ifdef PLATFORM_INTERFACE
+                return -EINVAL;
+#else
+		return;
+#endif
+	}
+#endif
+
+#ifndef DWC_HOST_ONLY
+	if (otg_dev->pcd) {
+		pcd_remove(_dev);
+	}
+#endif
+	/*
+	 * Free the IRQ
+	 */
+	if (otg_dev->common_irq_installed) {
+#ifdef PLATFORM_INTERFACE
+		free_irq(platform_get_irq(_dev, 0), otg_dev);
+#else
+		free_irq(_dev->irq, otg_dev);
+#endif
+	}
+
+	if (otg_dev->core_if) {
+		dwc_otg_cil_remove(otg_dev->core_if);
+	}
+
+	/*
+	 * Remove the device attributes
+	 */
+	dwc_otg_attr_remove(_dev);
+
+	/*
+	 * Return the memory.
+	 */
+	if (otg_dev->base) {
+		iounmap(otg_dev->base);
+	}
+	dwc_free(otg_dev);
+
+	/*
+	 * Clear the drvdata pointer.
+	 */
+#ifdef LM_INTERFACE
+	lm_set_drvdata(_dev, 0);
+#elif  defined(PCI_INTERFACE)
+        release_mem_region(otg_dev->rsrc_start, otg_dev->rsrc_len);
+        pci_set_drvdata(_dev, 0);
+#elif  defined(PLATFORM_INTERFACE)
+        platform_set_drvdata(_dev, 0);
+        return 0;
+#endif
+}
+
+/**
+ * This function is called when an lm_device is bound to a
+ * dwc_otg_driver. It creates the driver components required to
+ * control the device (CIL, HCD, and PCD) and it initializes the
+ * device. The driver components are stored in a dwc_otg_device
+ * structure. A reference to the dwc_otg_device is saved in the
+ * lm_device. This allows the driver to access the dwc_otg_device
+ * structure on subsequent calls to driver methods for this device.
+ *
+ * @param _dev Bus device
+ */
+static int dwc_otg_driver_probe(
+#ifdef LM_INTERFACE
+struct lm_device *_dev
+#elif  defined(PCI_INTERFACE)
+struct pci_dev *_dev,  const struct pci_device_id *id
+#elif  defined(PLATFORM_INTERFACE)
+struct platform_device *_dev
+#endif
+)
+{
+	int retval = 0;
+	dwc_otg_device_t *dwc_otg_device;
+        int devirq;
+
+	dev_dbg(&_dev->dev, "dwc_otg_driver_probe(%p)\n", _dev);
+#ifdef LM_INTERFACE
+	dev_dbg(&_dev->dev, "start=0x%08x\n", (unsigned)_dev->resource.start);
+#elif  defined(PCI_INTERFACE)
+	if (!id) {
+                DWC_ERROR("Invalid pci_device_id %p", id);
+		return -EINVAL;
+	}
+
+	if (!_dev || (pci_enable_device(_dev) < 0)) {
+		DWC_ERROR("Invalid pci_device %p", _dev);
+		return -ENODEV;
+	}
+	dev_dbg(&_dev->dev, "start=0x%08x\n", (unsigned)pci_resource_start(_dev,0));
+	/* other stuff needed as well? */
+        
+#elif  defined(PLATFORM_INTERFACE)
+	dev_dbg(&_dev->dev, "start=0x%08x (len 0x%x)\n",
+                (unsigned)_dev->resource->start,
+                (unsigned)(_dev->resource->end - _dev->resource->start));
+#endif
+
+
+	dwc_otg_device = dwc_alloc(sizeof(dwc_otg_device_t));
+
+	if (!dwc_otg_device) {
+		dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
+		retval = -ENOMEM;
+		goto fail;
+	}
+
+	memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
+	dwc_otg_device->reg_offset = 0xFFFFFFFF;
+
+	/*
+	 * Map the DWC_otg Core memory into virtual address space.
+	 */
+#ifdef LM_INTERFACE
+#if 1
+	dwc_otg_device->base = ioremap(_dev->resource.start, SZ_256K);
+#else
+	struct map_desc desc = {
+	    .virtual = IO_ADDRESS((unsigned)_dev->resource.start),
+	    .pfn     = __phys_to_pfn((unsigned)_dev->resource.start),
+	    .length  = SZ_128K,
+	    .type    = MT_DEVICE
+	};
+	iotable_init(&desc, 1);
+	dwc_otg_device->base = (void *)desc.virtual;
+#endif
+
+	if (!dwc_otg_device->base) {
+		dev_err(&_dev->dev, "ioremap() failed\n");
+		retval = -ENOMEM;
+		goto fail;
+	}
+	dev_dbg(&_dev->dev, "base=0x%08x\n", (unsigned)dwc_otg_device->base);
+#elif  defined(PCI_INTERFACE)
+	_dev->current_state = PCI_D0;
+	_dev->dev.power.power_state = PMSG_ON;
+	
+	if (!_dev->irq) {
+                DWC_ERROR("Found HC with no IRQ. Check BIOS/PCI %s setup!", pci_name(_dev));
+                retval = -ENODEV;
+                goto fail;
+        }
+
+        dwc_otg_device->rsrc_start = pci_resource_start(_dev,0);
+        dwc_otg_device->rsrc_len = pci_resource_len(_dev,0);
+        DWC_DEBUGPL(DBG_ANY,"PCI resource: start=%08x, len=%08x\n",
+                    dwc_otg_device->rsrc_start,
+                    dwc_otg_device->rsrc_len);
+        if (!request_mem_region(dwc_otg_device->rsrc_start, dwc_otg_device->rsrc_len, "dwc_otg")) {
+          dev_dbg(&_dev->dev, "error mapping memory\n");
+          retval = -EFAULT;
+          goto fail;
+        }
+
+        dwc_otg_device->base = ioremap_nocache(dwc_otg_device->rsrc_start, dwc_otg_device->rsrc_len);
+        if (dwc_otg_device->base == NULL) {
+                dev_dbg(&_dev->dev, "error mapping memory\n");
+                retval = -EFAULT;
+                goto fail;
+        }
+        dev_dbg(&_dev->dev, "base=0x%p (before adjust) \n", dwc_otg_device->base);
+        dwc_otg_device->base = (char *)dwc_otg_device->base;
+        dev_dbg(&_dev->dev, "base=0x%p (after adjust) \n", dwc_otg_device->base);
+        dev_dbg(&_dev->dev, "%s: mapped PA 0x%x to VA 0x%p\n", __func__,
+                (unsigned)dwc_otg_device->rsrc_start, dwc_otg_device->base);
+        //
+        pci_set_drvdata(_dev, dwc_otg_device); 
+        pci_set_master(_dev);
+#elif defined(PLATFORM_INTERFACE)
+        DWC_DEBUGPL(DBG_ANY,"Platform resource: start=%08x, len=%08x\n",
+                    _dev->resource->start,
+                    _dev->resource->end - _dev->resource->start + 1);
+#if 1
+        if (!request_mem_region(_dev->resource->start,
+                                _dev->resource->end - _dev->resource->start + 1,
+                                "dwc_otg")) {
+          dev_dbg(&_dev->dev, "error reserving mapped memory\n");
+          retval = -EFAULT;
+          goto fail;
+        }
+
+	dwc_otg_device->base = ioremap_nocache(_dev->resource->start,
+                                               _dev->resource->end -
+                                               _dev->resource->start + 1);
+#else
+        {
+                struct map_desc desc = {
+                    .virtual = IO_ADDRESS((unsigned)_dev->resource->start),
+                    .pfn     = __phys_to_pfn((unsigned)_dev->resource->start),
+                    .length  = SZ_128K,
+                    .type    = MT_DEVICE
+                };
+                iotable_init(&desc, 1);
+                dwc_otg_device->base = (void *)desc.virtual;
+        }
+#endif
+	if (!dwc_otg_device->base) {
+		dev_err(&_dev->dev, "ioremap() failed\n");
+		retval = -ENOMEM;
+		goto fail;
+	}
+	dev_dbg(&_dev->dev, "base=0x%08x\n", (unsigned)dwc_otg_device->base);
+#endif
+
+	/*
+	 * Initialize driver data to point to the global DWC_otg
+	 * Device structure.
+	 */
+#ifdef LM_INTERFACE
+	lm_set_drvdata(_dev, dwc_otg_device);
+#elif defined(PLATFORM_INTERFACE)
+	platform_set_drvdata(_dev, dwc_otg_device);
+#endif
+	dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
+
+	dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->base);
+        DWC_DEBUGPL(DBG_HCDV, "probe of device %p given core_if %p\n",
+                    dwc_otg_device, dwc_otg_device->core_if);//GRAYG
+        
+	if (!dwc_otg_device->core_if) {
+		dev_err(&_dev->dev, "CIL initialization failed!\n");
+		retval = -ENOMEM;
+		goto fail;
+	}
+
+	dev_dbg(&_dev->dev, "Calling get_gsnpsid\n");
+	/*
+	 * Attempt to ensure this device is really a DWC_otg Controller.
+	 * Read and verify the SNPSID register contents. The value should be
+	 * 0x45F42XXX, which corresponds to "OT2", as in "OTG version 2.XX".
+	 */
+
+	if ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
+	    0x4F542000) {
+		dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n",
+			dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
+		dwc_otg_cil_remove(dwc_otg_device->core_if);
+		dwc_free(dwc_otg_device);
+		retval = -EINVAL;
+		goto fail;
+	}
+
+	/*
+	 * Validate parameter values.
+	 */
+	dev_dbg(&_dev->dev, "Calling set_parameters\n");
+	if (set_parameters(dwc_otg_device->core_if)) {
+		dwc_otg_cil_remove(dwc_otg_device->core_if);
+		retval = -EINVAL;
+		goto fail;
+	}
+
+	/*
+	 * Create Device Attributes in sysfs
+	 */
+	dev_dbg(&_dev->dev, "Calling attr_create\n");
+	dwc_otg_attr_create(_dev);
+
+	/*
+	 * Disable the global interrupt until all the interrupt
+	 * handlers are installed.
+	 */
+	dev_dbg(&_dev->dev, "Calling disable_global_interrupts\n");
+	dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
+
+	/*
+	 * Install the interrupt handler for the common interrupts before
+	 * enabling common interrupts in core_init below.
+	 */
+#if defined(PLATFORM_INTERFACE)
+        devirq = platform_get_irq(_dev, 0);
+#else
+        devirq = _dev->irq;
+#endif
+	DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n",
+		    devirq);
+	dev_dbg(&_dev->dev, "Calling request_irq(%d)\n", devirq);
+	retval = request_irq(devirq, dwc_otg_common_irq,
+                             IRQF_SHARED,
+                             "dwc_otg", dwc_otg_device);
+	if (retval) {
+		DWC_ERROR("request of irq%d failed\n", devirq);
+		retval = -EBUSY;
+		goto fail;
+	} else {
+		dwc_otg_device->common_irq_installed = 1;
+	}
+
+#ifndef IRQF_TRIGGER_LOW
+#if defined(LM_INTERFACE) || defined(PLATFORM_INTERFACE)
+	dev_dbg(&_dev->dev, "Calling set_irq_type\n");
+	set_irq_type(devirq,
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30))
+                     IRQT_LOW
+#else
+                     IRQ_TYPE_LEVEL_LOW
+#endif
+                    );
+#endif
+#endif /*IRQF_TRIGGER_LOW*/
+
+	/*
+	 * Initialize the DWC_otg core.
+	 */
+	dev_dbg(&_dev->dev, "Calling dwc_otg_core_init\n");
+	dwc_otg_core_init(dwc_otg_device->core_if);
+
+#ifndef DWC_HOST_ONLY
+	/*
+	 * Initialize the PCD
+	 */
+	dev_dbg(&_dev->dev, "Calling pcd_init\n");
+	retval = pcd_init(_dev);
+	if (retval != 0) {
+		DWC_ERROR("pcd_init failed\n");
+		dwc_otg_device->pcd = NULL;
+		goto fail;
+	}
+#endif
+#ifndef DWC_DEVICE_ONLY
+	/*
+	 * Initialize the HCD
+	 */
+	dev_dbg(&_dev->dev, "Calling hcd_init\n");
+	retval = hcd_init(_dev);
+	if (retval != 0) {
+		DWC_ERROR("hcd_init failed\n");
+		dwc_otg_device->hcd = NULL;
+		goto fail;
+	}
+#endif
+        /* Recover from drvdata having been overwritten by hcd_init() */
+#ifdef LM_INTERFACE
+	lm_set_drvdata(_dev, dwc_otg_device);
+#elif defined(PLATFORM_INTERFACE)
+	platform_set_drvdata(_dev, dwc_otg_device);
+#elif defined(PCI_INTERFACE)
+	pci_set_drvdata(_dev, dwc_otg_device);
+#endif
+
+	/*
+	 * Enable the global interrupt after all the interrupt
+	 * handlers are installed.
+	 */
+	dev_dbg(&_dev->dev, "Calling enable_global_interrupts\n");
+	dwc_otg_enable_global_interrupts(dwc_otg_device->core_if);
+	dev_dbg(&_dev->dev, "Done\n");
+
+	return 0;
+
+      fail:
+	dwc_otg_driver_remove(_dev);
+	return retval;
+}
+
+/**
+ * This structure defines the methods to be called by a bus driver
+ * during the lifecycle of a device on that bus. Both drivers and
+ * devices are registered with a bus driver. The bus driver matches
+ * devices to drivers based on information in the device and driver
+ * structures.
+ *
+ * The probe function is called when the bus driver matches a device
+ * to this driver. The remove function is called when a device is
+ * unregistered with the bus driver.
+ */
+#ifdef LM_INTERFACE
+static struct lm_driver dwc_otg_driver = {
+	.drv = {
+		.name = (char *)dwc_driver_name,
+		},
+	.probe = dwc_otg_driver_probe,
+	.remove = dwc_otg_driver_remove,
+        // 'suspend' and 'resume' absent
+};
+#elif defined(PCI_INTERFACE)
+static const struct pci_device_id pci_ids[] = { {
+        PCI_DEVICE(0x16c3, 0xabcd),
+        .driver_data = (unsigned long) 0xdeadbeef,
+        }, { /* end: all zeroes */ }
+};
+MODULE_DEVICE_TABLE(pci, pci_ids);
+
+/* pci driver glue; this is a "new style" PCI driver module */
+static struct pci_driver dwc_otg_driver = {
+        .name =         "dwc_otg",
+        .id_table =     pci_ids,
+
+        .probe =        dwc_otg_driver_probe,
+        .remove =       dwc_otg_driver_remove,
+
+        .driver = {
+                .name   = (char*)dwc_driver_name,
+        },
+};
+#elif defined(PLATFORM_INTERFACE)
+static struct platform_device_id platform_ids[] = {
+        {
+              .name = "bcm2708_usb",
+              .driver_data = (kernel_ulong_t) 0xdeadbeef,
+        },
+        { /* end: all zeroes */ }
+};
+MODULE_DEVICE_TABLE(platform, platform_ids);
+
+static struct platform_driver dwc_otg_driver = {
+	.driver = {
+		.name = (char *)dwc_driver_name,
+		},
+        .id_table = platform_ids,
+                        
+	.probe = dwc_otg_driver_probe,
+	.remove = dwc_otg_driver_remove,
+        // no 'shutdown', 'suspend', 'resume', 'suspend_late' or 'resume_early' 
+};
+#endif
+
+
+/**
+ * This function is called when the dwc_otg_driver is installed with the
+ * insmod command. It registers the dwc_otg_driver structure with the
+ * appropriate bus driver. This will cause the dwc_otg_driver_probe function
+ * to be called. In addition, the bus driver will automatically expose
+ * attributes defined for the device and driver in the special sysfs file
+ * system.
+ *
+ * @return
+ */
+static int __init dwc_otg_driver_init(void)
+{
+	int retval = 0;
+	int error;
+	printk(KERN_INFO "%s: version %s (%s bus)\n", dwc_driver_name,
+	       DWC_DRIVER_VERSION,
+#ifdef LM_INTERFACE
+               "logicmodule");
+	retval = lm_driver_register(&dwc_otg_driver);
+#elif defined(PCI_INTERFACE)
+               "pci");
+	retval = pci_register_driver(&dwc_otg_driver);
+#elif defined(PLATFORM_INTERFACE)
+               "platform");
+	retval = platform_driver_register(&dwc_otg_driver);
+#endif
+	if (retval < 0) {
+		printk(KERN_ERR "%s retval=%d\n", __func__, retval);
+		return retval;
+	}
+#ifdef LM_INTERFACE
+	error = driver_create_file(&dwc_otg_driver.drv, &driver_attr_version);
+	error = driver_create_file(&dwc_otg_driver.drv, &driver_attr_debuglevel);
+#elif defined(PCI_INTERFACE)
+	error = driver_create_file(&dwc_otg_driver.driver,
+                                   &driver_attr_version);
+	error = driver_create_file(&dwc_otg_driver.driver,
+                                   &driver_attr_debuglevel);
+#elif defined(PLATFORM_INTERFACE)
+	error = driver_create_file(&dwc_otg_driver.driver,
+                                   &driver_attr_version);
+	error = driver_create_file(&dwc_otg_driver.driver,
+                                   &driver_attr_debuglevel);
+#endif
+	return retval;
+}
+
+module_init(dwc_otg_driver_init);
+
+/**
+ * This function is called when the driver is removed from the kernel
+ * with the rmmod command. The driver unregisters itself with its bus
+ * driver.
+ *
+ */
+static void __exit dwc_otg_driver_cleanup(void)
+{
+	printk(KERN_DEBUG "dwc_otg_driver_cleanup()\n");
+
+#ifdef LM_INTERFACE
+	driver_remove_file(&dwc_otg_driver.drv, &driver_attr_debuglevel);
+	driver_remove_file(&dwc_otg_driver.drv, &driver_attr_version);
+	lm_driver_unregister(&dwc_otg_driver);
+#elif defined(PCI_INTERFACE)
+	driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
+	driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
+	pci_unregister_driver(&dwc_otg_driver);
+#elif defined(PLATFORM_INTERFACE)
+	driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
+	driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
+	platform_driver_unregister(&dwc_otg_driver);
+#endif
+
+	printk(KERN_INFO "%s module removed\n", dwc_driver_name);
+}
+module_exit(dwc_otg_driver_cleanup);
+
+MODULE_DESCRIPTION(DWC_DRIVER_DESC);
+MODULE_AUTHOR("Synopsys Inc.");
+MODULE_LICENSE("GPL");
+
+module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444);
+MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None");
+module_param_named(opt, dwc_otg_module_params.opt, int, 0444);
+MODULE_PARM_DESC(opt, "OPT Mode");
+module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444);
+MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled");
+
+module_param_named(dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int,
+		   0444);
+MODULE_PARM_DESC(dma_desc_enable,
+		 "DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled");
+
+module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int,
+		   0444);
+MODULE_PARM_DESC(dma_burst_size,
+		 "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256");
+module_param_named(speed, dwc_otg_module_params.speed, int, 0444);
+MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed");
+module_param_named(host_support_fs_ls_low_power,
+		   dwc_otg_module_params.host_support_fs_ls_low_power, int,
+		   0444);
+MODULE_PARM_DESC(host_support_fs_ls_low_power,
+		 "Support Low Power w/FS or LS 0=Support 1=Don't Support");
+module_param_named(host_ls_low_power_phy_clk,
+		   dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444);
+MODULE_PARM_DESC(host_ls_low_power_phy_clk,
+		 "Low Speed Low Power Clock 0=48Mhz 1=6Mhz");
+module_param_named(enable_dynamic_fifo,
+		   dwc_otg_module_params.enable_dynamic_fifo, int, 0444);
+MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing");
+module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int,
+		   0444);
+MODULE_PARM_DESC(data_fifo_size,
+		 "Total number of words in the data FIFO memory 32-32768");
+module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size,
+		   int, 0444);
+MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
+module_param_named(dev_nperio_tx_fifo_size,
+		   dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444);
+MODULE_PARM_DESC(dev_nperio_tx_fifo_size,
+		 "Number of words in the non-periodic Tx FIFO 16-32768");
+module_param_named(dev_perio_tx_fifo_size_1,
+		   dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444);
+MODULE_PARM_DESC(dev_perio_tx_fifo_size_1,
+		 "Number of words in the periodic Tx FIFO 4-768");
+module_param_named(dev_perio_tx_fifo_size_2,
+		   dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444);
+MODULE_PARM_DESC(dev_perio_tx_fifo_size_2,
+		 "Number of words in the periodic Tx FIFO 4-768");
+module_param_named(dev_perio_tx_fifo_size_3,
+		   dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444);
+MODULE_PARM_DESC(dev_perio_tx_fifo_size_3,
+		 "Number of words in the periodic Tx FIFO 4-768");
+module_param_named(dev_perio_tx_fifo_size_4,
+		   dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444);
+MODULE_PARM_DESC(dev_perio_tx_fifo_size_4,
+		 "Number of words in the periodic Tx FIFO 4-768");
+module_param_named(dev_perio_tx_fifo_size_5,
+		   dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444);
+MODULE_PARM_DESC(dev_perio_tx_fifo_size_5,
+		 "Number of words in the periodic Tx FIFO 4-768");
+module_param_named(dev_perio_tx_fifo_size_6,
+		   dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444);
+MODULE_PARM_DESC(dev_perio_tx_fifo_size_6,
+		 "Number of words in the periodic Tx FIFO 4-768");
+module_param_named(dev_perio_tx_fifo_size_7,
+		   dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444);
+MODULE_PARM_DESC(dev_perio_tx_fifo_size_7,
+		 "Number of words in the periodic Tx FIFO 4-768");
+module_param_named(dev_perio_tx_fifo_size_8,
+		   dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444);
+MODULE_PARM_DESC(dev_perio_tx_fifo_size_8,
+		 "Number of words in the periodic Tx FIFO 4-768");
+module_param_named(dev_perio_tx_fifo_size_9,
+		   dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444);
+MODULE_PARM_DESC(dev_perio_tx_fifo_size_9,
+		 "Number of words in the periodic Tx FIFO 4-768");
+module_param_named(dev_perio_tx_fifo_size_10,
+		   dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444);
+MODULE_PARM_DESC(dev_perio_tx_fifo_size_10,
+		 "Number of words in the periodic Tx FIFO 4-768");
+module_param_named(dev_perio_tx_fifo_size_11,
+		   dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444);
+MODULE_PARM_DESC(dev_perio_tx_fifo_size_11,
+		 "Number of words in the periodic Tx FIFO 4-768");
+module_param_named(dev_perio_tx_fifo_size_12,
+		   dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444);
+MODULE_PARM_DESC(dev_perio_tx_fifo_size_12,
+		 "Number of words in the periodic Tx FIFO 4-768");
+module_param_named(dev_perio_tx_fifo_size_13,
+		   dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444);
+MODULE_PARM_DESC(dev_perio_tx_fifo_size_13,
+		 "Number of words in the periodic Tx FIFO 4-768");
+module_param_named(dev_perio_tx_fifo_size_14,
+		   dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444);
+MODULE_PARM_DESC(dev_perio_tx_fifo_size_14,
+		 "Number of words in the periodic Tx FIFO 4-768");
+module_param_named(dev_perio_tx_fifo_size_15,
+		   dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444);
+MODULE_PARM_DESC(dev_perio_tx_fifo_size_15,
+		 "Number of words in the periodic Tx FIFO 4-768");
+module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size,
+		   int, 0444);
+MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
+module_param_named(host_nperio_tx_fifo_size,
+		   dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444);
+MODULE_PARM_DESC(host_nperio_tx_fifo_size,
+		 "Number of words in the non-periodic Tx FIFO 16-32768");
+module_param_named(host_perio_tx_fifo_size,
+		   dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444);
+MODULE_PARM_DESC(host_perio_tx_fifo_size,
+		 "Number of words in the host periodic Tx FIFO 16-32768");
+module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size,
+		   int, 0444);
+/** @todo Set the max to 512K, modify checks */
+MODULE_PARM_DESC(max_transfer_size,
+		 "The maximum transfer size supported in bytes 2047-65535");
+module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count,
+		   int, 0444);
+MODULE_PARM_DESC(max_packet_count,
+		 "The maximum number of packets in a transfer 15-511");
+module_param_named(host_channels, dwc_otg_module_params.host_channels, int,
+		   0444);
+MODULE_PARM_DESC(host_channels,
+		 "The number of host channel registers to use 1-16");
+module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int,
+		   0444);
+MODULE_PARM_DESC(dev_endpoints,
+		 "The number of endpoints in addition to EP0 available for device mode 1-15");
+module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444);
+MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI");
+module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int,
+		   0444);
+MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits");
+module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444);
+MODULE_PARM_DESC(phy_ulpi_ddr,
+		 "ULPI at double or single data rate 0=Single 1=Double");
+module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus,
+		   int, 0444);
+MODULE_PARM_DESC(phy_ulpi_ext_vbus,
+		 "ULPI PHY using internal or external vbus 0=Internal");
+module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444);
+MODULE_PARM_DESC(i2c_enable, "FS PHY Interface");
+module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444);
+MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only");
+module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444);
+MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs");
+module_param_named(debug, g_dbg_lvl, int, 0444);
+MODULE_PARM_DESC(debug, "");
+
+module_param_named(en_multiple_tx_fifo,
+		   dwc_otg_module_params.en_multiple_tx_fifo, int, 0444);
+MODULE_PARM_DESC(en_multiple_tx_fifo,
+		 "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled");
+module_param_named(dev_tx_fifo_size_1,
+		   dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444);
+MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768");
+module_param_named(dev_tx_fifo_size_2,
+		   dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444);
+MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768");
+module_param_named(dev_tx_fifo_size_3,
+		   dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444);
+MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768");
+module_param_named(dev_tx_fifo_size_4,
+		   dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444);
+MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768");
+module_param_named(dev_tx_fifo_size_5,
+		   dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444);
+MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768");
+module_param_named(dev_tx_fifo_size_6,
+		   dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444);
+MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768");
+module_param_named(dev_tx_fifo_size_7,
+		   dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444);
+MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768");
+module_param_named(dev_tx_fifo_size_8,
+		   dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444);
+MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768");
+module_param_named(dev_tx_fifo_size_9,
+		   dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444);
+MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768");
+module_param_named(dev_tx_fifo_size_10,
+		   dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444);
+MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768");
+module_param_named(dev_tx_fifo_size_11,
+		   dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444);
+MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768");
+module_param_named(dev_tx_fifo_size_12,
+		   dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444);
+MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768");
+module_param_named(dev_tx_fifo_size_13,
+		   dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444);
+MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768");
+module_param_named(dev_tx_fifo_size_14,
+		   dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444);
+MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768");
+module_param_named(dev_tx_fifo_size_15,
+		   dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444);
+MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768");
+
+module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444);
+MODULE_PARM_DESC(thr_ctl,
+		 "Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled");
+module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int,
+		   0444);
+MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs");
+module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int,
+		   0444);
+MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs");
+
+module_param_named(pti_enable, dwc_otg_module_params.pti_enable, int, 0444);
+module_param_named(mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444);
+module_param_named(lpm_enable, dwc_otg_module_params.lpm_enable, int, 0444);
+MODULE_PARM_DESC(lpm_enable, "LPM Enable 0=LPM Disabled 1=LPM Enabled");
+module_param_named(ic_usb_cap, dwc_otg_module_params.ic_usb_cap, int, 0444);
+MODULE_PARM_DESC(ic_usb_cap,
+		 "IC_USB Capability 0=IC_USB Disabled 1=IC_USB Enabled");
+module_param_named(ahb_thr_ratio, dwc_otg_module_params.ahb_thr_ratio, int, 0444);
+MODULE_PARM_DESC(ahb_thr_ratio, "AHB Threshold Ratio");
+
+/** @page "Module Parameters"
+ *
+ * The following parameters may be specified when starting the module.
+ * These parameters define how the DWC_otg controller should be
+ * configured. Parameter values are passed to the CIL initialization
+ * function dwc_otg_cil_init
+ *
+ * Example: <code>modprobe dwc_otg speed=1 otg_cap=1</code>
+ *
+
+ <table>
+ <tr><td>Parameter Name</td><td>Meaning</td></tr>
+
+ <tr>
+ <td>otg_cap</td>
+ <td>Specifies the OTG capabilities. The driver will automatically detect the
+ value for this parameter if none is specified.
+ - 0: HNP and SRP capable (default, if available)
+ - 1: SRP Only capable
+ - 2: No HNP/SRP capable
+ </td></tr>
+
+ <tr>
+ <td>dma_enable</td>
+ <td>Specifies whether to use slave or DMA mode for accessing the data FIFOs.
+ The driver will automatically detect the value for this parameter if none is
+ specified.
+ - 0: Slave
+ - 1: DMA (default, if available)
+ </td></tr>
+
+ <tr>
+ <td>dma_burst_size</td>
+ <td>The DMA Burst size (applicable only for External DMA Mode).
+ - Values: 1, 4, 8 16, 32, 64, 128, 256 (default 32)
+ </td></tr>
+
+ <tr>
+ <td>speed</td>
+ <td>Specifies the maximum speed of operation in host and device mode. The
+ actual speed depends on the speed of the attached device and the value of
+ phy_type.
+ - 0: High Speed (default)
+ - 1: Full Speed
+ </td></tr>
+
+ <tr>
+ <td>host_support_fs_ls_low_power</td>
+ <td>Specifies whether low power mode is supported when attached to a Full
+ Speed or Low Speed device in host mode.
+ - 0: Don't support low power mode (default)
+ - 1: Support low power mode
+ </td></tr>
+
+ <tr>
+ <td>host_ls_low_power_phy_clk</td>
+ <td>Specifies the PHY clock rate in low power mode when connected to a Low
+ Speed device in host mode. This parameter is applicable only if
+ HOST_SUPPORT_FS_LS_LOW_POWER is enabled.
+ - 0: 48 MHz (default)
+ - 1: 6 MHz
+ </td></tr>
+
+ <tr>
+ <td>enable_dynamic_fifo</td>
+ <td> Specifies whether FIFOs may be resized by the driver software.
+ - 0: Use cC FIFO size parameters
+ - 1: Allow dynamic FIFO sizing (default)
+ </td></tr>
+
+ <tr>
+ <td>data_fifo_size</td>
+ <td>Total number of 4-byte words in the data FIFO memory. This memory
+ includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs.
+ - Values: 32 to 32768 (default 8192)
+
+ Note: The total FIFO memory depth in the FPGA configuration is 8192.
+ </td></tr>
+
+ <tr>
+ <td>dev_rx_fifo_size</td>
+ <td>Number of 4-byte words in the Rx FIFO in device mode when dynamic
+ FIFO sizing is enabled.
+ - Values: 16 to 32768 (default 1064)
+ </td></tr>
+
+ <tr>
+ <td>dev_nperio_tx_fifo_size</td>
+ <td>Number of 4-byte words in the non-periodic Tx FIFO in device mode when
+ dynamic FIFO sizing is enabled.
+ - Values: 16 to 32768 (default 1024)
+ </td></tr>
+
+ <tr>
+ <td>dev_perio_tx_fifo_size_n (n = 1 to 15)</td>
+ <td>Number of 4-byte words in each of the periodic Tx FIFOs in device mode
+ when dynamic FIFO sizing is enabled.
+ - Values: 4 to 768 (default 256)
+ </td></tr>
+
+ <tr>
+ <td>host_rx_fifo_size</td>
+ <td>Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO
+ sizing is enabled.
+ - Values: 16 to 32768 (default 1024)
+ </td></tr>
+
+ <tr>
+ <td>host_nperio_tx_fifo_size</td>
+ <td>Number of 4-byte words in the non-periodic Tx FIFO in host mode when
+ dynamic FIFO sizing is enabled in the core.
+ - Values: 16 to 32768 (default 1024)
+ </td></tr>
+
+ <tr>
+ <td>host_perio_tx_fifo_size</td>
+ <td>Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO
+ sizing is enabled.
+ - Values: 16 to 32768 (default 1024)
+ </td></tr>
+
+ <tr>
+ <td>max_transfer_size</td>
+ <td>The maximum transfer size supported in bytes.
+ - Values: 2047 to 65,535 (default 65,535)
+ </td></tr>
+
+ <tr>
+ <td>max_packet_count</td>
+ <td>The maximum number of packets in a transfer.
+ - Values: 15 to 511 (default 511)
+ </td></tr>
+
+ <tr>
+ <td>host_channels</td>
+ <td>The number of host channel registers to use.
+ - Values: 1 to 16 (default 12)
+
+ Note: The FPGA configuration supports a maximum of 12 host channels.
+ </td></tr>
+
+ <tr>
+ <td>dev_endpoints</td>
+ <td>The number of endpoints in addition to EP0 available for device mode
+ operations.
+ - Values: 1 to 15 (default 6 IN and OUT)
+
+ Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in
+ addition to EP0.
+ </td></tr>
+
+ <tr>
+ <td>phy_type</td>
+ <td>Specifies the type of PHY interface to use. By default, the driver will
+ automatically detect the phy_type.
+ - 0: Full Speed
+ - 1: UTMI+ (default, if available)
+ - 2: ULPI
+ </td></tr>
+
+ <tr>
+ <td>phy_utmi_width</td>
+ <td>Specifies the UTMI+ Data Width. This parameter is applicable for a
+ phy_type of UTMI+. Also, this parameter is applicable only if the
+ OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the
+ core has been configured to work at either data path width.
+ - Values: 8 or 16 bits (default 16)
+ </td></tr>
+
+ <tr>
+ <td>phy_ulpi_ddr</td>
+ <td>Specifies whether the ULPI operates at double or single data rate. This
+ parameter is only applicable if phy_type is ULPI.
+ - 0: single data rate ULPI interface with 8 bit wide data bus (default)
+ - 1: double data rate ULPI interface with 4 bit wide data bus
+ </td></tr>
+
+ <tr>
+ <td>i2c_enable</td>
+ <td>Specifies whether to use the I2C interface for full speed PHY. This
+ parameter is only applicable if PHY_TYPE is FS.
+ - 0: Disabled (default)
+ - 1: Enabled
+ </td></tr>
+
+ <tr>
+ <td>otg_en_multiple_tx_fifo</td>
+ <td>Specifies whether dedicatedto tx fifos are enabled for non periodic IN EPs.
+ The driver will automatically detect the value for this parameter if none is
+ specified.
+ - 0: Disabled
+ - 1: Enabled (default, if available)
+ </td></tr>
+
+ <tr>
+ <td>dev_tx_fifo_size_n (n = 1 to 15)</td>
+ <td>Number of 4-byte words in each of the Tx FIFOs in device mode
+ when dynamic FIFO sizing is enabled.
+ - Values: 4 to 768 (default 256)
+ </td></tr>
+
+ <tr>
+ <td>tx_thr_length</td>
+ <td>Transmit Threshold length in 32 bit double words
+ - Values: 8 to 128 (default 64)
+ </td></tr>
+
+ <tr>
+ <td>rx_thr_length</td>
+ <td>Receive Threshold length in 32 bit double words
+ - Values: 8 to 128 (default 64)
+ </td></tr>
+
+<tr>
+ <td>thr_ctl</td>
+ <td>Specifies whether to enable Thresholding for Device mode. Bits 0, 1, 2 of this 
+ parmater specifies if thresholding is enabled for non-Iso Tx, Iso Tx and Rx 
+ transfers accordingly. 
+ The driver will automatically detect the value for this parameter if none is
+ specified.
+ - Values: 0 to 7 (default 0)
+ Bit values indicate:
+ - 0: Thresholding disabled
+ - 1: Thresholding enabled
+ </td></tr>
+
+<tr>
+ <td>dma_desc_enable</td>
+ <td>Specifies whether to enable Descriptor DMA mode.
+ The driver will automatically detect the value for this parameter if none is
+ specified.
+ - 0: Descriptor DMA disabled
+ - 1: Descriptor DMA (default, if available)
+ </td></tr>
+
+<tr>
+ <td>mpi_enable</td>
+ <td>Specifies whether to enable MPI enhancement mode.
+ The driver will automatically detect the value for this parameter if none is
+ specified.
+ - 0: MPI disabled (default)
+ - 1: MPI enable 
+ </td></tr>
+
+<tr>
+ <td>pti_enable</td>
+ <td>Specifies whether to enable PTI enhancement support.
+ The driver will automatically detect the value for this parameter if none is
+ specified.
+ - 0: PTI disabled (default)
+ - 1: PTI enable 
+ </td></tr>
+
+<tr>
+ <td>lpm_enable</td>
+ <td>Specifies whether to enable LPM support.
+ The driver will automatically detect the value for this parameter if none is
+ specified.
+ - 0: LPM disabled
+ - 1: LPM enable (default, if available)
+ </td></tr>
+
+ <tr>
+ <td>ahb_thr_ratio</td>
+ <td>Specifies AHB Threshold ratio.
+ - Values: 0 to 3 (default 0)
+ </td></tr>
+
+*/
diff --git a/drivers/usb/host/dwc_otg/dwc_otg_driver.h b/drivers/usb/host/dwc_otg/dwc_otg_driver.h
new file mode 100644
index 000000000000..f37d3ac15d00
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/dwc_otg_driver.h
@@ -0,0 +1,101 @@
+/* ==========================================================================
+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.h $
+ * $Revision: #16 $
+ * $Date: 2009/04/03 $
+ * $Change: 1225160 $
+ *
+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+ * otherwise expressly agreed to in writing between Synopsys and you.
+ * 
+ * The Software IS NOT an item of Licensed Software or Licensed Product under
+ * any End User Software License Agreement or Agreement for Licensed Product
+ * with Synopsys or any supplement thereto. You are permitted to use and
+ * redistribute this Software in source and binary forms, with or without
+ * modification, provided that redistributions of source code must retain this
+ * notice. You may not view, use, disclose, copy or distribute this file or
+ * any information contained herein except pursuant to this license grant from
+ * Synopsys. If you do not agree with this notice, including the disclaimer
+ * below, then you are not authorized to use the Software.
+ * 
+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ * ========================================================================== */
+
+#ifndef __DWC_OTG_DRIVER_H__
+#define __DWC_OTG_DRIVER_H__
+
+/** @file
+ * This file contains the interface to the Linux driver.
+ */
+#include "dwc_otg_core_if.h"
+
+/* Type declarations */
+struct dwc_otg_pcd;
+struct dwc_otg_hcd;
+
+#ifdef  PCI_INTERFACE
+#include <linux/pci.h>
+#endif
+
+
+
+/**
+ * This structure is a wrapper that encapsulates the driver components used to
+ * manage a single DWC_otg controller.
+ */
+typedef struct dwc_otg_device {
+	/** Base address returned from ioremap() */
+	void *base;
+
+#ifdef LM_INTERFACE
+	struct lm_device *lmdev;
+#elif  defined(PCI_INTERFACE)
+	int rsrc_start;
+	int rsrc_len;
+#elif  defined(PLATFORM_INTERFACE)
+	struct platform_device *platformdev;
+#endif
+
+	/** Pointer to the core interface structure. */
+	dwc_otg_core_if_t *core_if;
+
+	/** Register offset for Diagnostic API. */
+	uint32_t reg_offset;
+
+	/** Pointer to the PCD structure. */
+	struct dwc_otg_pcd *pcd;
+
+	/** Pointer to the HCD structure. */
+	struct dwc_otg_hcd *hcd;
+
+	/** Flag to indicate whether the common IRQ handler is installed. */
+	uint8_t common_irq_installed;
+
+} dwc_otg_device_t;
+
+/*We must clear S3C24XX_EINTPEND external interrupt register 
+ * because after clearing in this register trigerred IRQ from 
+ * H/W core in kernel interrupt can be occured again before OTG
+ * handlers clear all IRQ sources of Core registers because of
+ * timing latencies and Low Level IRQ Type.
+ */
+#ifdef CONFIG_MACH_IPMATE
+#define  S3C2410X_CLEAR_EINTPEND()   \
+do { \
+	__raw_writel(1UL << 11,S3C24XX_EINTPEND); \
+} while (0)
+#else
+#define  S3C2410X_CLEAR_EINTPEND()   do { } while (0)
+#endif
+
+#endif
diff --git a/drivers/usb/host/dwc_otg/dwc_otg_hcd.c b/drivers/usb/host/dwc_otg/dwc_otg_hcd.c
new file mode 100644
index 000000000000..223d879cbd5c
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd.c
@@ -0,0 +1,3330 @@
+
+/* ==========================================================================
+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.c $
+ * $Revision: #87 $
+ * $Date: 2009/04/23 $
+ * $Change: 1239143 $
+ *
+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+ * otherwise expressly agreed to in writing between Synopsys and you.
+ *
+ * The Software IS NOT an item of Licensed Software or Licensed Product under
+ * any End User Software License Agreement or Agreement for Licensed Product
+ * with Synopsys or any supplement thereto. You are permitted to use and
+ * redistribute this Software in source and binary forms, with or without
+ * modification, provided that redistributions of source code must retain this
+ * notice. You may not view, use, disclose, copy or distribute this file or
+ * any information contained herein except pursuant to this license grant from
+ * Synopsys. If you do not agree with this notice, including the disclaimer
+ * below, then you are not authorized to use the Software.
+ *
+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ * ========================================================================== */
+#ifndef DWC_DEVICE_ONLY
+
+/** @file
+ * This file implements HCD Core. All code in this file is portable and don't
+ * use any OS specific functions.
+ * Interface provided by HCD Core is defined in <code><hcd_if.h></code>
+ * header file.
+ */
+
+#include "dwc_otg_hcd.h"
+#include "dwc_otg_regs.h"
+
+#ifdef HW2937_WORKAROUND
+//#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#endif
+		
+dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void)
+{
+	return dwc_alloc(sizeof(dwc_otg_hcd_t));
+}
+
+/**
+ * Connection timeout function.  An OTG host is required to display a
+ * message if the device does not connect within 10 seconds.
+ */
+void dwc_otg_hcd_connect_timeout(void *ptr)
+{
+	DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, ptr);
+	DWC_PRINTF("Connect Timeout\n");
+	__DWC_ERROR("Device Not Connected/Responding\n");
+}
+
+#ifdef DEBUG
+static void dump_channel_info(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
+{
+	if (qh->channel != NULL) {
+		dwc_hc_t *hc = qh->channel;
+		dwc_list_link_t *item;
+		dwc_otg_qh_t *qh_item;
+		int num_channels = hcd->core_if->core_params->host_channels;
+		int i;
+
+		dwc_otg_hc_regs_t *hc_regs;
+		hcchar_data_t hcchar;
+		hcsplt_data_t hcsplt;
+		hctsiz_data_t hctsiz;
+		uint32_t hcdma;
+
+		hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num];
+		hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+		hcsplt.d32 = dwc_read_reg32(&hc_regs->hcsplt);
+		hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
+		hcdma = dwc_read_reg32(&hc_regs->hcdma);
+
+		DWC_PRINTF("  Assigned to channel %p:\n", hc);
+		DWC_PRINTF("    hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32,
+			   hcsplt.d32);
+		DWC_PRINTF("    hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32,
+			   hcdma);
+		DWC_PRINTF("    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
+			   hc->dev_addr, hc->ep_num, hc->ep_is_in);
+		DWC_PRINTF("    ep_type: %d\n", hc->ep_type);
+		DWC_PRINTF("    max_packet: %d\n", hc->max_packet);
+		DWC_PRINTF("    data_pid_start: %d\n", hc->data_pid_start);
+		DWC_PRINTF("    xfer_started: %d\n", hc->xfer_started);
+		DWC_PRINTF("    halt_status: %d\n", hc->halt_status);
+		DWC_PRINTF("    xfer_buff: %p\n", hc->xfer_buff);
+		DWC_PRINTF("    xfer_len: %d\n", hc->xfer_len);
+		DWC_PRINTF("    qh: %p\n", hc->qh);
+		DWC_PRINTF("  NP inactive sched:\n");
+		DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_inactive) {
+			qh_item =
+			    DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
+			DWC_PRINTF("    %p\n", qh_item);
+		}
+		DWC_PRINTF("  NP active sched:\n");
+		DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_active) {
+			qh_item =
+			    DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
+			DWC_PRINTF("    %p\n", qh_item);
+		}
+		DWC_PRINTF("  Channels: \n");
+		for (i = 0; i < num_channels; i++) {
+			dwc_hc_t *hc = hcd->hc_ptr_array[i];
+			DWC_PRINTF("    %2d: %p\n", i, hc);
+		}
+	}
+}
+#endif				/* DEBUG */
+
+/**
+ * Work queue function for starting the HCD when A-Cable is connected.
+ * The hcd_start() must be called in a process context.
+ */
+static void hcd_start_func(void *_vp)
+{
+	dwc_otg_hcd_t *hcd = (dwc_otg_hcd_t *) _vp;
+
+	DWC_DEBUGPL(DBG_HCDV, "%s() %p\n", __func__, hcd);
+	if (hcd) {
+		hcd->fops->start(hcd);
+	}
+}
+
+static void del_xfer_timers(dwc_otg_hcd_t * hcd)
+{
+#ifdef DEBUG
+	int i;
+	int num_channels = hcd->core_if->core_params->host_channels;
+	for (i = 0; i < num_channels; i++) {
+		DWC_TIMER_CANCEL(hcd->core_if->hc_xfer_timer[i]);
+	}
+#endif
+}
+
+static void del_timers(dwc_otg_hcd_t * hcd)
+{
+	del_xfer_timers(hcd);
+	DWC_TIMER_CANCEL(hcd->conn_timer);
+}
+
+/**
+ * Processes all the URBs in a single list of QHs. Completes them with
+ * -ETIMEDOUT and frees the QTD.
+ */
+static void kill_urbs_in_qh_list(dwc_otg_hcd_t * hcd, dwc_list_link_t * qh_list)
+{
+	dwc_list_link_t *qh_item;
+	dwc_otg_qh_t *qh;
+	dwc_otg_qtd_t *qtd, *qtd_tmp;
+
+	DWC_LIST_FOREACH(qh_item, qh_list) {
+		qh = DWC_LIST_ENTRY(qh_item, dwc_otg_qh_t, qh_list_entry);
+		DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp,
+					 &qh->qtd_list, qtd_list_entry) {
+			qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
+			if (qtd->urb != NULL) {
+				hcd->fops->complete(hcd, qtd->urb->priv,
+						    qtd->urb,
+						    -DWC_E_TIMEOUT);
+				dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
+			}
+
+		}
+	}
+}
+
+/**
+ * Responds with an error status of ETIMEDOUT to all URBs in the non-periodic
+ * and periodic schedules. The QTD associated with each URB is removed from
+ * the schedule and freed. This function may be called when a disconnect is
+ * detected or when the HCD is being stopped.
+ */
+static void kill_all_urbs(dwc_otg_hcd_t * hcd)
+{
+	kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_inactive);
+	kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_active);
+	kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_inactive);
+	kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_ready);
+	kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_assigned);
+	kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_queued);
+}
+
+/**
+ * Start the connection timer.  An OTG host is required to display a
+ * message if the device does not connect within 10 seconds.  The
+ * timer is deleted if a port connect interrupt occurs before the
+ * timer expires.
+ */
+static void dwc_otg_hcd_start_connect_timer(dwc_otg_hcd_t * hcd)
+{
+	DWC_TIMER_SCHEDULE(hcd->conn_timer, 10000 /* 10 secs */ );
+}
+
+/**
+ * HCD Callback function for disconnect of the HCD.
+ *
+ * @param p void pointer to the <code>struct usb_hcd</code>
+ */
+static int32_t dwc_otg_hcd_session_start_cb(void *p)
+{
+	dwc_otg_hcd_t *dwc_otg_hcd;
+	DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
+	dwc_otg_hcd = p;
+	dwc_otg_hcd_start_connect_timer(dwc_otg_hcd);
+	return 1;
+}
+
+/**
+ * HCD Callback function for starting the HCD when A-Cable is
+ * connected.
+ *
+ * @param p void pointer to the <code>struct usb_hcd</code>
+ */
+static int32_t dwc_otg_hcd_start_cb(void *p)
+{
+	dwc_otg_hcd_t *dwc_otg_hcd = p;
+	dwc_otg_core_if_t *core_if;
+	hprt0_data_t hprt0;
+
+	core_if = dwc_otg_hcd->core_if;
+
+	if (core_if->op_state == B_HOST) {
+		/*
+		 * Reset the port.  During a HNP mode switch the reset
+		 * needs to occur within 1ms and have a duration of at
+		 * least 50ms.
+		 */
+		hprt0.d32 = dwc_otg_read_hprt0(core_if);
+		hprt0.b.prtrst = 1;
+		dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
+	}
+	DWC_WORKQ_SCHEDULE_DELAYED(core_if->wq_otg,
+				   hcd_start_func, dwc_otg_hcd, 50,
+				   "start hcd");
+
+	return 1;
+}
+
+/**
+ * HCD Callback function for disconnect of the HCD.
+ *
+ * @param p void pointer to the <code>struct usb_hcd</code>
+ */
+static int32_t dwc_otg_hcd_disconnect_cb(void *p)
+{
+	gintsts_data_t intr;
+	dwc_otg_hcd_t *dwc_otg_hcd = p;
+
+	/*
+	 * Set status flags for the hub driver.
+	 */
+	dwc_otg_hcd->flags.b.port_connect_status_change = 1;
+	dwc_otg_hcd->flags.b.port_connect_status = 0;
+
+	/*
+	 * Shutdown any transfers in process by clearing the Tx FIFO Empty
+	 * interrupt mask and status bits and disabling subsequent host
+	 * channel interrupts.
+	 */
+	intr.d32 = 0;
+	intr.b.nptxfempty = 1;
+	intr.b.ptxfempty = 1;
+	intr.b.hcintr = 1;
+	dwc_modify_reg32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk,
+			 intr.d32, 0);
+	dwc_modify_reg32(&dwc_otg_hcd->core_if->core_global_regs->gintsts,
+			 intr.d32, 0);
+
+	del_timers(dwc_otg_hcd);
+
+	/*
+	 * Turn off the vbus power only if the core has transitioned to device
+	 * mode. If still in host mode, need to keep power on to detect a
+	 * reconnection.
+	 */
+	if (dwc_otg_is_device_mode(dwc_otg_hcd->core_if)) {
+		if (dwc_otg_hcd->core_if->op_state != A_SUSPEND) {
+			hprt0_data_t hprt0 = {.d32 = 0 };
+			DWC_PRINTF("Disconnect: PortPower off\n");
+			hprt0.b.prtpwr = 0;
+			dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0,
+					hprt0.d32);
+		}
+
+		dwc_otg_disable_host_interrupts(dwc_otg_hcd->core_if);
+	}
+
+	/* Respond with an error status to all URBs in the schedule. */
+	kill_all_urbs(dwc_otg_hcd);
+
+	if (dwc_otg_is_host_mode(dwc_otg_hcd->core_if)) {
+		/* Clean up any host channels that were in use. */
+		int num_channels;
+		int i;
+		dwc_hc_t *channel;
+		dwc_otg_hc_regs_t *hc_regs;
+		hcchar_data_t hcchar;
+
+		num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
+
+		if (!dwc_otg_hcd->core_if->dma_enable) {
+			/* Flush out any channel requests in slave mode. */
+			for (i = 0; i < num_channels; i++) {
+				channel = dwc_otg_hcd->hc_ptr_array[i];
+				if (DWC_CIRCLEQ_EMPTY_ENTRY
+				    (channel, hc_list_entry)) {
+					hc_regs =
+					    dwc_otg_hcd->core_if->host_if->
+					    hc_regs[i];
+					hcchar.d32 =
+					    dwc_read_reg32(&hc_regs->hcchar);
+					if (hcchar.b.chen) {
+						hcchar.b.chen = 0;
+						hcchar.b.chdis = 1;
+						hcchar.b.epdir = 0;
+						dwc_write_reg32(&hc_regs->
+								hcchar,
+								hcchar.d32);
+					}
+				}
+			}
+		}
+
+		for (i = 0; i < num_channels; i++) {
+			channel = dwc_otg_hcd->hc_ptr_array[i];
+			if (DWC_CIRCLEQ_EMPTY_ENTRY(channel, hc_list_entry)) {
+				hc_regs =
+				    dwc_otg_hcd->core_if->host_if->hc_regs[i];
+				hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+				if (hcchar.b.chen) {
+					/* Halt the channel. */
+					hcchar.b.chdis = 1;
+					dwc_write_reg32(&hc_regs->hcchar,
+							hcchar.d32);
+				}
+
+				dwc_otg_hc_cleanup(dwc_otg_hcd->core_if,
+						   channel);
+				DWC_CIRCLEQ_INSERT_TAIL(&dwc_otg_hcd->
+							free_hc_list, channel,
+							hc_list_entry);
+				/* 
+				 * Added for Descriptor DMA to prevent channel double cleanup 
+				 * in release_channel_ddma(). Which called from ep_disable
+				 * when device disconnect.
+				 */			
+				channel->qh = NULL;			
+			}
+		}
+	}
+
+	if (dwc_otg_hcd->fops->disconnect) {
+		dwc_otg_hcd->fops->disconnect(dwc_otg_hcd);
+	}
+
+	return 1;
+}
+
+/**
+ * HCD Callback function for stopping the HCD.
+ *
+ * @param p void pointer to the <code>struct usb_hcd</code>
+ */
+static int32_t dwc_otg_hcd_stop_cb(void *p)
+{
+	dwc_otg_hcd_t *dwc_otg_hcd = p;
+
+	DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
+	dwc_otg_hcd_stop(dwc_otg_hcd);
+	return 1;
+}
+
+#ifdef CONFIG_USB_DWC_OTG_LPM
+/** 
+ * HCD Callback function for sleep of HCD.
+ *
+ * @param p void pointer to the <code>struct usb_hcd</code>
+ */
+static int dwc_otg_hcd_sleep_cb(void *p)
+{
+	dwc_otg_hcd_t *hcd = p;
+
+	dwc_otg_hcd_free_hc_from_lpm(hcd);
+
+	return 0;
+}
+#endif
+
+/**
+ * HCD Callback function for Remote Wakeup.
+ *
+ * @param p void pointer to the <code>struct usb_hcd</code>
+ */
+static int dwc_otg_hcd_rem_wakeup_cb(void *p)
+{
+	dwc_otg_hcd_t *hcd = p;
+
+	if (hcd->core_if->lx_state == DWC_OTG_L2) {
+		hcd->flags.b.port_suspend_change = 1;
+	}
+#ifdef CONFIG_USB_DWC_OTG_LPM
+	else {
+		hcd->flags.b.port_l1_change = 1;
+	}
+#endif
+	return 0;
+}
+
+/**
+ * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
+ * stopped.
+ */
+void dwc_otg_hcd_stop(dwc_otg_hcd_t * hcd)
+{
+	hprt0_data_t hprt0 = {.d32 = 0 };
+
+	DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD STOP\n");
+ 
+	/*
+	 * The root hub should be disconnected before this function is called.
+	 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
+	 * and the QH lists (via ..._hcd_endpoint_disable).
+	 */
+
+	/* Turn off all host-specific interrupts. */
+	dwc_otg_disable_host_interrupts(hcd->core_if);
+
+	/* Turn off the vbus power */
+	DWC_PRINTF("PortPower off\n");
+	hprt0.b.prtpwr = 0;
+	dwc_write_reg32(hcd->core_if->host_if->hprt0, hprt0.d32);
+	dwc_mdelay(1);
+}
+
+int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t * hcd,
+			    dwc_otg_hcd_urb_t * dwc_otg_urb, void **ep_handle)
+{
+	uint64_t flags;
+	int retval = 0;
+	dwc_otg_qtd_t *qtd;
+
+	if (NULL == hcd->core_if) { //GRAYG
+		DWC_ERROR("**** DWC OTG HCD URB Enqueue - HCD has NULL core_if\n");
+		/* No longer connected. */
+		return -DWC_E_INVALID;
+	}
+
+	if (!hcd->flags.b.port_connect_status) {
+		/* No longer connected. */
+		return -DWC_E_NO_DEVICE;
+	}
+
+	qtd = dwc_otg_hcd_qtd_create(dwc_otg_urb);
+	if (qtd == NULL) {
+		DWC_ERROR("DWC OTG HCD URB Enqueue failed creating QTD\n");
+		return -DWC_E_NO_MEMORY;
+	}
+	if (qtd->urb == NULL) { //GRAYG
+		DWC_ERROR("**** DWC OTG HCD URB Enqueue created QTD with no URBs\n");
+		return -DWC_E_NO_MEMORY;
+	}
+	if (qtd->urb->priv == NULL) { //GRAYG
+		DWC_ERROR("**** DWC OTG HCD URB Enqueue created QTD URB with no URB handle\n");
+		return -DWC_E_NO_MEMORY;
+	}
+
+	retval =
+	    dwc_otg_hcd_qtd_add(qtd, hcd, (dwc_otg_qh_t **) ep_handle);
+            // creates a new queue in ep_handle if it doesn't exist already
+	if (retval < 0) {
+		DWC_ERROR("DWC OTG HCD URB Enqueue failed adding QTD. "
+			  "Error status %d\n", retval);
+		dwc_otg_hcd_qtd_free(qtd);
+	} else {
+		qtd->qh = *ep_handle;
+	}
+	
+	if (hcd->core_if->dma_desc_enable && retval == 0) {
+		dwc_otg_transaction_type_e tr_type;	
+		if ((qtd->qh->ep_type == UE_BULK) && !(qtd->urb->flags & URB_GIVEBACK_ASAP)) {
+			/* Do not schedule SG transcations until qtd has URB_GIVEBACK_ASAP set */
+			return 0;
+		}
+		DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
+		tr_type = dwc_otg_hcd_select_transactions(hcd);
+		if (tr_type != DWC_OTG_TRANSACTION_NONE) {
+			dwc_otg_hcd_queue_transactions(hcd, tr_type);
+		}
+		DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
+	}
+
+	return retval;
+}
+
+int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t * hcd,
+			    dwc_otg_hcd_urb_t * dwc_otg_urb)
+{
+	uint64_t flags;
+
+	dwc_otg_qh_t *qh;
+	dwc_otg_qtd_t *urb_qtd;
+
+	DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
+	
+	if (hcd == NULL) { //GRAYG
+		DWC_ERROR("**** DWC OTG HCD URB Dequeue has NULL HCD\n");
+		return -DWC_E_INVALID;
+	}
+	if (dwc_otg_urb == NULL) { //GRAYG
+		DWC_ERROR("**** DWC OTG HCD URB Dequeue has NULL URB\n");
+		return -DWC_E_INVALID;
+	}
+	if (dwc_otg_urb->qtd == NULL) { //GRAYG
+		DWC_ERROR("**** DWC OTG HCD URB Dequeue with NULL QTD\n");
+		return -DWC_E_INVALID;
+	}
+	urb_qtd = dwc_otg_urb->qtd;
+	if (urb_qtd->qh == NULL) { //GRAYG
+		DWC_ERROR("**** DWC OTG HCD URB Dequeue with QTD with NULL Q handler\n");
+		return -DWC_E_INVALID;
+	}
+	qh = urb_qtd->qh;
+#ifdef DEBUG
+	if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
+		if (urb_qtd->in_process) {
+			dump_channel_info(hcd, qh);
+		}
+	}
+#endif
+	if (hcd->core_if == NULL) { //GRAYG
+		DWC_ERROR("**** DWC OTG HCD URB Dequeue HCD has NULL core_if\n");
+		return -DWC_E_INVALID;
+	}
+	if (urb_qtd->in_process && qh->channel) {
+		/* The QTD is in process (it has been assigned to a channel). */
+		if (hcd->flags.b.port_connect_status) {
+			/*
+			 * If still connected (i.e. in host mode), halt the
+			 * channel so it can be used for other transfers. If
+			 * no longer connected, the host registers can't be
+			 * written to halt the channel since the core is in
+			 * device mode.
+			 */
+			dwc_otg_hc_halt(hcd->core_if, qh->channel,
+					DWC_OTG_HC_XFER_URB_DEQUEUE);
+		}
+	}
+
+	/*
+	 * Free the QTD and clean up the associated QH. Leave the QH in the
+	 * schedule if it has any remaining QTDs.
+	 */
+	 
+	DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue - "
+                    "delete %sQueue handler\n",
+                    hcd->core_if->dma_desc_enable?"DMA ":""); //GRAYG
+	if (!hcd->core_if->dma_desc_enable) {
+		uint8_t b = urb_qtd->in_process;	
+		dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh);
+		if (b) {
+			dwc_otg_hcd_qh_deactivate(hcd, qh, 0);
+			qh->channel = NULL;
+		} else if (DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
+			dwc_otg_hcd_qh_remove(hcd, qh);
+		}
+	}
+	else {
+		dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh);
+	}
+	
+	DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
+
+	return 0;
+}
+
+int dwc_otg_hcd_endpoint_disable(dwc_otg_hcd_t * hcd, void *ep_handle,
+				 int retry)
+{
+	dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
+	int retval = 0;
+	uint64_t flags;
+
+	if (retry < 0) {
+		retval = -DWC_E_INVALID;
+		goto done;
+	}
+
+	if (!qh) {
+		goto done;
+	}
+
+	DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
+	
+	while (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list) && retry) {
+		DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
+		retry--;
+		dwc_msleep(5);
+		DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
+	}
+
+	dwc_otg_hcd_qh_remove(hcd, qh);
+	
+	DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
+	/* 
+	 * Split dwc_otg_hcd_qh_remove_and_free() into qh_remove 
+	 * and qh_free to prevent stack dump on dwc_dma_free() with 
+	 * irq_disabled (spinlock_irqsave) in dwc_otg_hcd_desc_list_free() 
+	 * and dwc_otg_hcd_frame_list_alloc().
+	 */
+	dwc_otg_hcd_qh_free(hcd, qh);
+
+      done:
+	return retval;
+}
+
+/**
+ * HCD Callback structure for handling mode switching.
+ */
+static dwc_otg_cil_callbacks_t hcd_cil_callbacks = {
+	.start = dwc_otg_hcd_start_cb,
+	.stop = dwc_otg_hcd_stop_cb,
+	.disconnect = dwc_otg_hcd_disconnect_cb,
+	.session_start = dwc_otg_hcd_session_start_cb,
+	.resume_wakeup = dwc_otg_hcd_rem_wakeup_cb,
+#ifdef CONFIG_USB_DWC_OTG_LPM
+	.sleep = dwc_otg_hcd_sleep_cb,
+#endif
+	.p = 0,
+};
+
+/**
+ * Reset tasklet function
+ */
+static void reset_tasklet_func(void *data)
+{
+	dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t *) data;
+	dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
+	hprt0_data_t hprt0;
+
+	DWC_DEBUGPL(DBG_HCDV, "USB RESET tasklet called\n");
+
+	hprt0.d32 = dwc_otg_read_hprt0(core_if);
+	hprt0.b.prtrst = 1;
+	dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
+	dwc_mdelay(60);
+
+	hprt0.b.prtrst = 0;
+	dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
+	dwc_otg_hcd->flags.b.port_reset_change = 1;
+}
+
+static void qh_list_free(dwc_otg_hcd_t * hcd, dwc_list_link_t * qh_list)
+{
+	dwc_list_link_t *item;
+	dwc_otg_qh_t *qh;
+
+	if (!qh_list->next) {
+		/* The list hasn't been initialized yet. */
+		return;
+	}
+
+	/* Ensure there are no QTDs or URBs left. */
+	kill_urbs_in_qh_list(hcd, qh_list);
+
+	DWC_LIST_FOREACH(item, qh_list) {
+		qh = DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
+		dwc_otg_hcd_qh_remove_and_free(hcd, qh);
+	}
+}
+
+/**
+ * Frees secondary storage associated with the dwc_otg_hcd structure contained
+ * in the struct usb_hcd field.
+ */
+static void dwc_otg_hcd_free(dwc_otg_hcd_t * dwc_otg_hcd)
+{
+	int i;
+
+	DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD FREE\n");
+
+	del_timers(dwc_otg_hcd);
+
+	/* Free memory for QH/QTD lists */
+	qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_inactive);
+	qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_active);
+	qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_inactive);
+	qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_ready);
+	qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_assigned);
+	qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_queued);
+
+	/* Free memory for the host channels. */
+	for (i = 0; i < MAX_EPS_CHANNELS; i++) {
+		dwc_hc_t *hc = dwc_otg_hcd->hc_ptr_array[i];
+
+#ifdef DEBUG
+		if (dwc_otg_hcd->core_if->hc_xfer_timer[i]) {
+			DWC_TIMER_FREE(dwc_otg_hcd->core_if->hc_xfer_timer[i]);
+		}
+#endif
+		if (hc != NULL) {
+			DWC_DEBUGPL(DBG_HCDV, "HCD Free channel #%i, hc=%p\n",
+				    i, hc);
+			dwc_free(hc);
+		}
+	}
+
+	if (dwc_otg_hcd->core_if->dma_enable) {
+		if (dwc_otg_hcd->status_buf_dma) {
+			dwc_dma_free(DWC_OTG_HCD_STATUS_BUF_SIZE,
+				     dwc_otg_hcd->status_buf,
+				     dwc_otg_hcd->status_buf_dma);
+		}
+	} else if (dwc_otg_hcd->status_buf != NULL) {
+		dwc_free(dwc_otg_hcd->status_buf);
+	}
+	DWC_SPINLOCK_FREE(dwc_otg_hcd->lock);
+	DWC_TIMER_FREE(dwc_otg_hcd->conn_timer);
+	DWC_TASK_FREE(dwc_otg_hcd->reset_tasklet);
+	dwc_free(dwc_otg_hcd);
+}
+
+int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if)
+{
+	int retval = 0;
+	int num_channels;
+	int i;
+	dwc_hc_t *channel;
+
+	hcd->lock = DWC_SPINLOCK_ALLOC();
+
+        DWC_DEBUGPL(DBG_HCDV, "init of HCD %p given core_if %p\n",
+                    hcd, core_if);//GRAYG
+        
+	hcd->core_if = core_if;
+	/* Register the HCD CIL Callbacks */
+	dwc_otg_cil_register_hcd_callbacks(hcd->core_if,
+					   &hcd_cil_callbacks, hcd);
+
+	/* Initialize the non-periodic schedule. */
+	DWC_LIST_INIT(&hcd->non_periodic_sched_inactive);
+	DWC_LIST_INIT(&hcd->non_periodic_sched_active);
+
+	/* Initialize the periodic schedule. */
+	DWC_LIST_INIT(&hcd->periodic_sched_inactive);
+	DWC_LIST_INIT(&hcd->periodic_sched_ready);
+	DWC_LIST_INIT(&hcd->periodic_sched_assigned);
+	DWC_LIST_INIT(&hcd->periodic_sched_queued);
+
+	/*
+	 * Create a host channel descriptor for each host channel implemented
+	 * in the controller. Initialize the channel descriptor array.
+	 */
+	DWC_CIRCLEQ_INIT(&hcd->free_hc_list);
+	num_channels = hcd->core_if->core_params->host_channels;
+	DWC_MEMSET(hcd->hc_ptr_array, 0, sizeof(hcd->hc_ptr_array));
+	for (i = 0; i < num_channels; i++) {
+		channel = dwc_alloc(sizeof(dwc_hc_t));
+		if (channel == NULL) {
+			retval = -DWC_E_NO_MEMORY;
+			DWC_ERROR("%s: host channel allocation failed\n",
+				  __func__);
+			dwc_otg_hcd_free(hcd);
+			goto out;
+		}
+		channel->hc_num = i;
+		hcd->hc_ptr_array[i] = channel;
+#ifdef DEBUG
+		hcd->core_if->hc_xfer_timer[i] =
+		    DWC_TIMER_ALLOC("hc timer", hc_xfer_timeout,
+				    &hcd->core_if->hc_xfer_info[i]);
+#endif
+		DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i,
+			    channel);
+	}
+
+	/* Initialize the Connection timeout timer. */
+	hcd->conn_timer = DWC_TIMER_ALLOC("Connection timer",
+					  dwc_otg_hcd_connect_timeout, 0);
+
+	/* Initialize reset tasklet. */
+	hcd->reset_tasklet = DWC_TASK_ALLOC(reset_tasklet_func, hcd);
+
+	/*
+	 * Allocate space for storing data on status transactions. Normally no
+	 * data is sent, but this space acts as a bit bucket. This must be
+	 * done after usb_add_hcd since that function allocates the DMA buffer
+	 * pool.
+	 */
+	if (hcd->core_if->dma_enable) {
+		hcd->status_buf =
+		    dwc_dma_alloc(DWC_OTG_HCD_STATUS_BUF_SIZE,
+				  &hcd->status_buf_dma);
+	} else {
+		hcd->status_buf = dwc_alloc(DWC_OTG_HCD_STATUS_BUF_SIZE);
+	}
+	if (!hcd->status_buf) {
+		retval = -DWC_E_NO_MEMORY;
+		DWC_ERROR("%s: status_buf allocation failed\n", __func__);
+		dwc_otg_hcd_free(hcd);
+		goto out;
+	}
+
+	hcd->otg_port = 1;
+	hcd->frame_list = NULL;
+	hcd->frame_list_dma = 0;
+
+#ifdef HW2937_WORKAROUND
+	hcd->hw2937_xfer_mode = HW2937_XFER_MODE_IDLE;
+	hcd->hw2937_assigned_channels = 0;
+#endif
+
+out:
+	return retval;
+}
+
+void dwc_otg_hcd_remove(dwc_otg_hcd_t * hcd)
+{
+	/* Turn off all host-specific interrupts. */
+	dwc_otg_disable_host_interrupts(hcd->core_if);
+
+	dwc_otg_hcd_free(hcd);
+}
+
+/**
+ * Initializes dynamic portions of the DWC_otg HCD state.
+ */
+static void dwc_otg_hcd_reinit(dwc_otg_hcd_t * hcd)
+{
+	int num_channels;
+	int i;
+	dwc_hc_t *channel;
+	dwc_hc_t *channel_tmp;
+
+	hcd->flags.d32 = 0;
+
+	hcd->non_periodic_qh_ptr = &hcd->non_periodic_sched_active;
+	hcd->non_periodic_channels = 0;
+	hcd->periodic_channels = 0;
+
+	/*
+	 * Put all channels in the free channel list and clean up channel
+	 * states.
+	 */
+	DWC_CIRCLEQ_FOREACH_SAFE(channel, channel_tmp,
+				 &hcd->free_hc_list, hc_list_entry) {
+		DWC_CIRCLEQ_REMOVE(&hcd->free_hc_list, channel, hc_list_entry);
+	}
+
+	num_channels = hcd->core_if->core_params->host_channels;
+	for (i = 0; i < num_channels; i++) {
+		channel = hcd->hc_ptr_array[i];
+		DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, channel,
+					hc_list_entry);
+		dwc_otg_hc_cleanup(hcd->core_if, channel);
+	}
+
+	/* Initialize the DWC core for host mode operation. */
+	dwc_otg_core_host_init(hcd->core_if);
+}
+
+/**
+ * Assigns transactions from a QTD to a free host channel and initializes the
+ * host channel to perform the transactions. The host channel is removed from
+ * the free list.
+ *
+ * @param hcd The HCD state structure.
+ * @param qh Transactions from the first QTD for this QH are selected and
+ * assigned to a free host channel.
+ */
+#ifdef HW2937_WORKAROUND
+static int assign_and_init_hc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
+#else
+static void assign_and_init_hc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
+#endif
+{
+	dwc_hc_t *hc;
+	dwc_otg_qtd_t *qtd;
+	dwc_otg_hcd_urb_t *urb;
+	void* ptr = NULL;
+#ifdef HW2937_WORKAROUND
+	int ep_is_in;
+#endif
+
+	qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
+	
+	urb = qtd->urb;
+
+	DWC_DEBUGPL(DBG_HCDV, "%s(%p,%p) - urb %x, actual_length %d\n", __func__, hcd, qh, (unsigned int)urb, urb->actual_length);
+
+#ifdef HW2937_WORKAROUND
+	ep_is_in = (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) != 0);
+	if (ep_is_in && ((hcd->hw2937_xfer_mode == HW2937_XFER_MODE_OUT) ||
+			 (hcd->hw2937_xfer_mode == HW2937_XFER_MODE_PAUSEIN)))
+		return 0;
+#endif
+
+	hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list);
+
+	/* Remove the host channel from the free list. */
+	DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry);
+	qh->channel = hc;
+	
+	qtd->in_process = 1;
+
+	/*
+	 * Use usb_pipedevice to determine device address. This address is
+	 * 0 before the SET_ADDRESS command and the correct address afterward.
+	 */
+	hc->dev_addr = dwc_otg_hcd_get_dev_addr(&urb->pipe_info);
+	hc->ep_num = dwc_otg_hcd_get_ep_num(&urb->pipe_info);
+	hc->speed = qh->dev_speed;
+	hc->max_packet = dwc_max_packet(qh->maxp);
+
+	hc->xfer_started = 0;
+	hc->halt_status = DWC_OTG_HC_XFER_NO_HALT_STATUS;
+	hc->error_state = (qtd->error_count > 0);
+	hc->halt_on_queue = 0;
+	hc->halt_pending = 0;
+	hc->requests = 0;
+
+	/*
+	 * The following values may be modified in the transfer type section
+	 * below. The xfer_len value may be reduced when the transfer is
+	 * started to accommodate the max widths of the XferSize and PktCnt
+	 * fields in the HCTSIZn register.
+	 */
+	hc->do_ping = qh->ping_state;
+#ifdef HW2937_WORKAROUND
+	hc->ep_is_in = ep_is_in;
+#else
+	hc->ep_is_in = (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) != 0);
+#endif
+	hc->data_pid_start = qh->data_toggle;
+	hc->multi_count = 1;
+
+	if (hcd->core_if->dma_enable) {
+		hc->xfer_buff = (uint8_t *) urb->dma + urb->actual_length;
+	
+		/* For non-dword aligned case */
+		if (((uint32_t)hc->xfer_buff & 0x3) && !hcd->core_if->dma_desc_enable) {
+			ptr = (uint8_t *) urb->buf + urb->actual_length;
+		}
+	} else {
+		hc->xfer_buff = (uint8_t *) urb->buf + urb->actual_length;
+	}
+	hc->xfer_len = urb->length - urb->actual_length;
+	hc->xfer_count = 0;
+
+	/*
+	 * Set the split attributes
+	 */
+	hc->do_split = 0;
+	if (qh->do_split) {
+		uint32_t hub_addr, port_addr;
+		hc->do_split = 1;
+		hc->xact_pos = qtd->isoc_split_pos;
+		hc->complete_split = qtd->complete_split;
+		hcd->fops->hub_info(hcd, urb->priv, &hub_addr, &port_addr);
+		hc->hub_addr = (uint8_t) hub_addr;
+		hc->port_addr = (uint8_t) port_addr;
+	}
+
+	switch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) {
+	case UE_CONTROL:
+		hc->ep_type = DWC_OTG_EP_TYPE_CONTROL;
+		switch (qtd->control_phase) {
+		case DWC_OTG_CONTROL_SETUP:
+			DWC_DEBUGPL(DBG_HCDV, "  Control setup transaction\n");
+			hc->do_ping = 0;
+			hc->ep_is_in = 0;
+			hc->data_pid_start = DWC_OTG_HC_PID_SETUP;
+			if (hcd->core_if->dma_enable) {
+				hc->xfer_buff = (uint8_t *) urb->setup_dma;
+			} else {
+				hc->xfer_buff = (uint8_t *) urb->setup_packet;
+			}
+			hc->xfer_len = 8;
+			ptr = NULL;
+			break;
+		case DWC_OTG_CONTROL_DATA:
+			DWC_DEBUGPL(DBG_HCDV, "  Control data transaction\n");
+			hc->data_pid_start = qtd->data_toggle;
+			break;
+		case DWC_OTG_CONTROL_STATUS:
+			/*
+			 * Direction is opposite of data direction or IN if no
+			 * data.
+			 */
+			DWC_DEBUGPL(DBG_HCDV, "  Control status transaction\n");
+			if (urb->length == 0) {
+				hc->ep_is_in = 1;
+			} else {
+				hc->ep_is_in =
+				    dwc_otg_hcd_is_pipe_out(&urb->pipe_info);
+			}
+			if (hc->ep_is_in) {
+				hc->do_ping = 0;
+			}
+			
+			hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
+
+			hc->xfer_len = 0;
+			if (hcd->core_if->dma_enable) {
+				hc->xfer_buff = (uint8_t *) hcd->status_buf_dma;
+			} else {
+				hc->xfer_buff = (uint8_t *) hcd->status_buf;
+			}
+			ptr = NULL;
+			break;
+		}
+		break;
+	case UE_BULK:
+		hc->ep_type = DWC_OTG_EP_TYPE_BULK;
+		break;
+	case UE_INTERRUPT:
+		hc->ep_type = DWC_OTG_EP_TYPE_INTR;
+		break;
+	case UE_ISOCHRONOUS:
+		{
+			struct dwc_otg_hcd_iso_packet_desc *frame_desc;
+			
+			hc->ep_type = DWC_OTG_EP_TYPE_ISOC;
+			
+			if (hcd->core_if->dma_desc_enable)
+				break;
+				
+			frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
+			
+			frame_desc->status = 0;
+			
+			if (hcd->core_if->dma_enable) {
+				hc->xfer_buff = (uint8_t *) urb->dma;
+			} else {
+				hc->xfer_buff = (uint8_t *) urb->buf;
+			}
+			hc->xfer_buff +=
+			    frame_desc->offset + qtd->isoc_split_offset;
+			hc->xfer_len =
+			    frame_desc->length - qtd->isoc_split_offset;
+
+			/* For non-dword aligned buffers */
+			if (((uint32_t)hc->xfer_buff & 0x3) && hcd->core_if->dma_enable) {
+				ptr = (uint8_t *) urb->buf + frame_desc->offset + qtd->isoc_split_offset;
+			}	
+			else
+			    ptr = NULL;
+			
+			if (hc->xact_pos == DWC_HCSPLIT_XACTPOS_ALL) {
+				if (hc->xfer_len <= 188) {
+					hc->xact_pos = DWC_HCSPLIT_XACTPOS_ALL;
+				} else {
+					hc->xact_pos =
+					    DWC_HCSPLIT_XACTPOS_BEGIN;
+				}
+			}
+		}
+		break;
+	}
+	/* non DWORD-aligned buffer case */	
+	if (ptr) {
+		uint32_t buf_size;
+		if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
+			buf_size = hcd->core_if->core_params->max_transfer_size;
+		} else {				
+			buf_size = 4096;
+		}
+		if (!qh->dw_align_buf) {
+			qh->dw_align_buf =
+                                dwc_dma_alloc_atomic(buf_size,
+                                                     &qh->dw_align_buf_dma);
+			if (!qh->dw_align_buf) {
+				DWC_ERROR("%s: Failed to allocate memory to handle "
+					  "non-dword aligned buffer case\n", __func__);
+#ifdef HW2937_WORKAROUND
+				return 0;
+#else
+				return;
+#endif
+			}
+		}
+		if (!hc->ep_is_in) {
+			dwc_memcpy(qh->dw_align_buf, ptr, hc->xfer_len);
+		}
+		hc->align_buff = qh->dw_align_buf_dma;
+	}
+	else {
+		hc->align_buff = 0;
+	}
+
+	if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
+	    hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
+		/*
+		 * This value may be modified when the transfer is started to
+		 * reflect the actual transfer length.
+		 */
+		hc->multi_count = dwc_hb_mult(qh->maxp);
+	}
+	
+	if (hcd->core_if->dma_desc_enable)
+		hc->desc_list_addr = qh->desc_list_dma;
+	
+	dwc_otg_hc_init(hcd->core_if, hc);
+	hc->qh = qh;
+#ifdef HW2937_WORKAROUND
+	hcd->hw2937_assigned_channels |= (1 << hc->hc_num);
+	DWC_DEBUGPL(DBG_HW2937, " assign %d -> hw2937_ac %x\n", hc->hc_num, hcd->hw2937_assigned_channels);
+	return 1;
+#endif
+}
+
+#ifdef HW2937_WORKAROUND
+
+void debug_halt(void)
+{
+	spinlock_t mr_lock = SPIN_LOCK_UNLOCKED;
+	unsigned long flags;
+	extern void v6_flush_kern_cache_all(void);
+
+	spin_lock_irqsave(&mr_lock, flags);
+#ifdef CONFIG_MACH_BCM2708
+	v6_flush_kern_cache_all();
+#endif
+	while (1) continue;
+}
+
+static
+void dwc_otg_hcd_disable_in_channels(dwc_otg_hcd_t * hcd)
+{
+	int num_channels = hcd->core_if->core_params->host_channels;
+	static int stall_count = 0;
+	static int max_stall_count = 1;
+	static int last_stalled = 0;
+	int stalled = 0;
+	int i;
+
+	DWC_DEBUGPL(DBG_HW2937, "  Disable In Channels(%x)\n", hcd->hw2937_assigned_channels);
+
+	for (i = 0; i < num_channels; i++) {
+		if (hcd->hw2937_assigned_channels & (1 << i)) {
+			dwc_hc_t *hc = hcd->hc_ptr_array[i];
+			if (!hc->halt_pending) {
+				dwc_otg_hc_regs_t *hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num];
+				hctsiz_data_t hctsiz;
+				hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
+				DWC_DEBUGPL(DBG_HW2937, "pktcnt %d, xfersize %x, xfer_len %x\n", hctsiz.b.pktcnt, hctsiz.b.xfersize, hc->xfer_len);
+				if (hctsiz.b.pktcnt == hc->start_pkt_count)
+				{
+					dwc_otg_hc_halt(hcd->core_if, hc, DWC_OTG_HC_XFER_PAUSE_IN);
+				}
+				else
+				{
+					/* Unless a receive is in progress */
+					stalled |= (1<<i);
+				}
+			} else {
+				stalled |= (1<<i);
+			}
+		}
+	}
+
+	if (stalled && (stalled == last_stalled))
+	{
+		stall_count++;
+		if (stall_count > max_stall_count)
+		{
+			max_stall_count = stall_count;
+			DWC_PRINTF( "stall (%x) count -> %d\n", stalled, stall_count);
+			if (stall_count == 10)
+			{
+				debug_halt();
+			}
+		}
+	}
+	else
+	{
+		stall_count = 0;
+		last_stalled = stalled;
+	}
+}
+
+static
+int dwc_otg_hcd_update_transaction_mode(dwc_otg_hcd_t * hcd)
+{
+	dwc_list_link_t *qh_ptr;
+	dwc_otg_qh_t *qh;
+	dwc_otg_qtd_t *qtd;
+	dwc_otg_hcd_urb_t *urb;
+	int found_in = 0;
+
+        /* If there are any existing out transactions, stay in OUT mode */
+	if (hcd->hw2937_xfer_mode == HW2937_XFER_MODE_OUT)
+	{
+		return 1;
+	}
+
+	/* Scan entries in the periodic ready list. */
+	qh_ptr = DWC_LIST_FIRST(&hcd->periodic_sched_ready);
+
+	while (qh_ptr != &hcd->periodic_sched_ready) {
+		qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
+		qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
+		urb = qtd->urb;
+		if (!dwc_otg_hcd_is_pipe_in(&urb->pipe_info)) {
+			/* Switch to OUT mode */
+			switch (hcd->hw2937_xfer_mode)
+			{
+			case HW2937_XFER_MODE_IDLE:
+				DWC_DEBUGPL(DBG_HW2937, "utm -> OUT\n");
+				hcd->hw2937_xfer_mode = HW2937_XFER_MODE_OUT;
+				/* Drop through... */
+			case HW2937_XFER_MODE_OUT:
+				return 1;
+			case HW2937_XFER_MODE_IN:
+				DWC_DEBUGPL(DBG_HW2937, "utm - halting %x INs\n", hcd->hw2937_assigned_channels);
+				/* Disable the channels with outstanding INs */
+				dwc_otg_hcd_disable_in_channels(hcd);
+				
+				DWC_DEBUGPL(DBG_HW2937, "utm -> PAUSEIN\n");
+				hcd->hw2937_xfer_mode = HW2937_XFER_MODE_PAUSEIN;
+				/* Drop through... */
+			case HW2937_XFER_MODE_PAUSEIN:
+				/* Delay until the halt completes */
+				return 0;
+			}
+		}
+		found_in = 1;
+		qh_ptr = DWC_LIST_NEXT(qh_ptr);
+	}
+
+	/*
+	 * Scan entries in the inactive portion of the non-periodic
+	 * schedule.
+	 */
+	qh_ptr = hcd->non_periodic_sched_inactive.next;
+	while (qh_ptr != &hcd->non_periodic_sched_inactive) {
+		qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
+		qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
+		urb = qtd->urb;
+		if (!dwc_otg_hcd_is_pipe_in(&urb->pipe_info)) {
+			/* Switch to OUT mode */
+			switch (hcd->hw2937_xfer_mode)
+			{
+			case HW2937_XFER_MODE_IDLE:
+				DWC_DEBUGPL(DBG_HW2937, "utm -> OUT\n");
+				hcd->hw2937_xfer_mode = HW2937_XFER_MODE_OUT;
+				/* Drop through... */
+			case HW2937_XFER_MODE_OUT:
+				return 1;
+			case HW2937_XFER_MODE_IN:
+				DWC_DEBUGPL(DBG_HW2937, "utm - halting %x INs\n", hcd->hw2937_assigned_channels);
+				/* Disable the channels with outstanding INs */
+				dwc_otg_hcd_disable_in_channels(hcd);
+				
+				DWC_DEBUGPL(DBG_HW2937, "utm -> PAUSEIN\n");
+				hcd->hw2937_xfer_mode = HW2937_XFER_MODE_PAUSEIN;
+				/* Drop through... */
+			case HW2937_XFER_MODE_PAUSEIN:
+				/* Delay until the halt completes */
+				return 0;
+			}
+		}
+		found_in = 1;
+		qh_ptr = DWC_LIST_NEXT(qh_ptr);
+	}
+
+	if (found_in && (hcd->hw2937_xfer_mode == HW2937_XFER_MODE_IDLE))
+	{
+		DWC_DEBUGPL(DBG_HW2937, "utm -> IN\n");
+		hcd->hw2937_xfer_mode = HW2937_XFER_MODE_IN;
+	}
+	return 1;
+}
+
+#endif /* HW2937_WORKAROUND */
+
+/**
+ * This function selects transactions from the HCD transfer schedule and
+ * assigns them to available host channels. It is called from HCD interrupt
+ * handler functions.
+ *
+ * @param hcd The HCD state structure.
+ *
+ * @return The types of new transactions that were assigned to host channels.
+ */
+dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t * hcd)
+{
+	dwc_list_link_t *qh_ptr;
+	dwc_otg_qh_t *qh;
+	int num_channels;
+	dwc_otg_transaction_type_e ret_val = DWC_OTG_TRANSACTION_NONE;
+
+#ifdef DEBUG_SOF
+	DWC_DEBUGPL(DBG_HCD, "  Select Transactions\n");
+#endif
+
+#ifdef HW2937_WORKAROUND
+	if (!dwc_otg_hcd_update_transaction_mode(hcd))
+	{
+		return ret_val;
+	}
+#endif
+
+	/* Process entries in the periodic ready list. */
+	qh_ptr = DWC_LIST_FIRST(&hcd->periodic_sched_ready);
+
+	while (qh_ptr != &hcd->periodic_sched_ready &&
+	       !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
+		qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
+#ifdef HW2937_WORKAROUND
+		if (assign_and_init_hc(hcd, qh)) {
+#else
+		assign_and_init_hc(hcd, qh);
+#endif
+
+		/*
+		 * Move the QH from the periodic ready schedule to the
+		 * periodic assigned schedule.
+		 */
+		qh_ptr = DWC_LIST_NEXT(qh_ptr);
+		DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
+				   &qh->qh_list_entry);
+
+		ret_val = DWC_OTG_TRANSACTION_PERIODIC;
+#ifdef HW2937_WORKAROUND
+		} else {
+			qh_ptr = DWC_LIST_NEXT(qh_ptr);
+		}
+#endif
+	}
+
+	/*
+	 * Process entries in the inactive portion of the non-periodic
+	 * schedule. Some free host channels may not be used if they are
+	 * reserved for periodic transfers.
+	 */
+	qh_ptr = hcd->non_periodic_sched_inactive.next;
+	num_channels = hcd->core_if->core_params->host_channels;
+	while (qh_ptr != &hcd->non_periodic_sched_inactive &&
+	       (hcd->non_periodic_channels <
+		num_channels - hcd->periodic_channels) &&
+	       !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
+
+		qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
+
+#ifdef HW2937_WORKAROUND
+		if (assign_and_init_hc(hcd, qh)) {
+#else
+		assign_and_init_hc(hcd, qh);
+#endif
+
+		/*
+		 * Move the QH from the non-periodic inactive schedule to the
+		 * non-periodic active schedule.
+		 */
+		qh_ptr = DWC_LIST_NEXT(qh_ptr);
+		DWC_LIST_MOVE_HEAD(&hcd->non_periodic_sched_active,
+				   &qh->qh_list_entry);
+
+		if (ret_val == DWC_OTG_TRANSACTION_NONE) {
+			ret_val = DWC_OTG_TRANSACTION_NON_PERIODIC;
+		} else {
+			ret_val = DWC_OTG_TRANSACTION_ALL;
+		}
+
+		hcd->non_periodic_channels++;
+#ifdef HW2937_WORKAROUND
+		} else {
+			qh_ptr = DWC_LIST_NEXT(qh_ptr);
+		}
+#endif
+	}
+
+	return ret_val;
+}
+/**
+ * Attempts to queue a single transaction request for a host channel
+ * associated with either a periodic or non-periodic transfer. This function
+ * assumes that there is space available in the appropriate request queue. For
+ * an OUT transfer or SETUP transaction in Slave mode, it checks whether space
+ * is available in the appropriate Tx FIFO.
+ *
+ * @param hcd The HCD state structure.
+ * @param hc Host channel descriptor associated with either a periodic or
+ * non-periodic transfer.
+ * @param fifo_dwords_avail Number of DWORDs available in the periodic Tx
+ * FIFO for periodic transfers or the non-periodic Tx FIFO for non-periodic
+ * transfers.
+ *
+ * @return 1 if a request is queued and more requests may be needed to
+ * complete the transfer, 0 if no more requests are required for this
+ * transfer, -1 if there is insufficient space in the Tx FIFO.
+ */
+static int queue_transaction(dwc_otg_hcd_t * hcd,
+			     dwc_hc_t * hc, uint16_t fifo_dwords_avail)
+{
+	int retval;
+
+	if (hcd->core_if->dma_enable) {
+		if (hcd->core_if->dma_desc_enable) {
+			if (!hc->xfer_started || (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)) {	
+				dwc_otg_hcd_start_xfer_ddma(hcd, hc->qh);
+				hc->qh->ping_state = 0;
+			}
+		}
+		else if (!hc->xfer_started) {
+			dwc_otg_hc_start_transfer(hcd->core_if, hc);
+			hc->qh->ping_state = 0;
+		}
+		retval = 0;
+	} else if (hc->halt_pending) {
+		/* Don't queue a request if the channel has been halted. */
+		retval = 0;
+	} else if (hc->halt_on_queue) {
+		dwc_otg_hc_halt(hcd->core_if, hc, hc->halt_status);
+		retval = 0;
+	} else if (hc->do_ping) {
+		if (!hc->xfer_started) {
+			dwc_otg_hc_start_transfer(hcd->core_if, hc);
+		}
+		retval = 0;
+	} else if (!hc->ep_is_in || hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
+		if ((fifo_dwords_avail * 4) >= hc->max_packet) {
+			if (!hc->xfer_started) {
+				dwc_otg_hc_start_transfer(hcd->core_if, hc);
+				retval = 1;
+			} else {
+				retval =
+				    dwc_otg_hc_continue_transfer(hcd->core_if,
+								 hc);
+			}
+		} else {
+			retval = -1;
+		}
+	} else {
+		if (!hc->xfer_started) {
+			dwc_otg_hc_start_transfer(hcd->core_if, hc);
+			retval = 1;
+		} else {
+			retval = dwc_otg_hc_continue_transfer(hcd->core_if, hc);
+		}
+	}
+
+	return retval;
+}
+
+/**
+ * Processes periodic channels for the next frame and queues transactions for
+ * these channels to the DWC_otg controller. After queueing transactions, the
+ * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
+ * to queue as Periodic Tx FIFO or request queue space becomes available.
+ * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
+ */
+static void process_periodic_channels(dwc_otg_hcd_t * hcd)
+{
+	hptxsts_data_t tx_status;
+	dwc_list_link_t *qh_ptr;
+	dwc_otg_qh_t *qh;
+	int status;
+	int no_queue_space = 0;
+	int no_fifo_space = 0;
+
+	dwc_otg_host_global_regs_t *host_regs;
+	host_regs = hcd->core_if->host_if->host_global_regs;
+
+	DWC_DEBUGPL(DBG_HCDV, "Queue periodic transactions\n");
+#ifdef DEBUG
+	tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts);
+	DWC_DEBUGPL(DBG_HCDV,
+		    "  P Tx Req Queue Space Avail (before queue): %d\n",
+		    tx_status.b.ptxqspcavail);
+	DWC_DEBUGPL(DBG_HCDV, "  P Tx FIFO Space Avail (before queue): %d\n",
+		    tx_status.b.ptxfspcavail);
+#endif
+
+	qh_ptr = hcd->periodic_sched_assigned.next;
+	while (qh_ptr != &hcd->periodic_sched_assigned) {
+		tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts);
+		if (tx_status.b.ptxqspcavail == 0) {
+			no_queue_space = 1;
+			break;
+		}
+
+		qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
+
+		/*
+		 * Set a flag if we're queuing high-bandwidth in slave mode.
+		 * The flag prevents any halts to get into the request queue in
+		 * the middle of multiple high-bandwidth packets getting queued.
+		 */
+		if (!hcd->core_if->dma_enable && qh->channel->multi_count > 1) {
+			hcd->core_if->queuing_high_bandwidth = 1;
+		}
+		status =
+		    queue_transaction(hcd, qh->channel,
+				      tx_status.b.ptxfspcavail);
+		if (status < 0) {
+			no_fifo_space = 1;
+			break;
+		}
+
+		/*
+		 * In Slave mode, stay on the current transfer until there is
+		 * nothing more to do or the high-bandwidth request count is
+		 * reached. In DMA mode, only need to queue one request. The
+		 * controller automatically handles multiple packets for
+		 * high-bandwidth transfers.
+		 */
+		if (hcd->core_if->dma_enable || status == 0 ||
+		    qh->channel->requests == qh->channel->multi_count) {
+			qh_ptr = qh_ptr->next;
+			/*
+			 * Move the QH from the periodic assigned schedule to
+			 * the periodic queued schedule.
+			 */
+			DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_queued,
+					   &qh->qh_list_entry);
+
+			/* done queuing high bandwidth */
+			hcd->core_if->queuing_high_bandwidth = 0;
+		}
+	}
+
+	if (!hcd->core_if->dma_enable) {
+		dwc_otg_core_global_regs_t *global_regs;
+		gintmsk_data_t intr_mask = {.d32 = 0 };
+
+		global_regs = hcd->core_if->core_global_regs;
+		intr_mask.b.ptxfempty = 1;
+#ifdef DEBUG
+		tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts);
+		DWC_DEBUGPL(DBG_HCDV,
+			    "  P Tx Req Queue Space Avail (after queue): %d\n",
+			    tx_status.b.ptxqspcavail);
+		DWC_DEBUGPL(DBG_HCDV,
+			    "  P Tx FIFO Space Avail (after queue): %d\n",
+			    tx_status.b.ptxfspcavail);
+#endif
+		if (!DWC_LIST_EMPTY(&hcd->periodic_sched_assigned) ||
+		    no_queue_space || no_fifo_space) {
+			/*
+			 * May need to queue more transactions as the request
+			 * queue or Tx FIFO empties. Enable the periodic Tx
+			 * FIFO empty interrupt. (Always use the half-empty
+			 * level to ensure that new requests are loaded as
+			 * soon as possible.)
+			 */
+			dwc_modify_reg32(&global_regs->gintmsk, 0,
+					 intr_mask.d32);
+		} else {
+			/*
+			 * Disable the Tx FIFO empty interrupt since there are
+			 * no more transactions that need to be queued right
+			 * now. This function is called from interrupt
+			 * handlers to queue more transactions as transfer
+			 * states change.
+			 */
+			dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32,
+					 0);
+		}
+	}
+}
+
+/**
+ * Processes active non-periodic channels and queues transactions for these
+ * channels to the DWC_otg controller. After queueing transactions, the NP Tx
+ * FIFO Empty interrupt is enabled if there are more transactions to queue as
+ * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
+ * FIFO Empty interrupt is disabled.
+ */
+static void process_non_periodic_channels(dwc_otg_hcd_t * hcd)
+{
+	gnptxsts_data_t tx_status;
+	dwc_list_link_t *orig_qh_ptr;
+	dwc_otg_qh_t *qh;
+	int status;
+	int no_queue_space = 0;
+	int no_fifo_space = 0;
+	int more_to_do = 0;
+
+	dwc_otg_core_global_regs_t *global_regs =
+	    hcd->core_if->core_global_regs;
+
+	DWC_DEBUGPL(DBG_HCDV, "Queue non-periodic transactions\n");
+#ifdef DEBUG
+	tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts);
+	DWC_DEBUGPL(DBG_HCDV,
+		    "  NP Tx Req Queue Space Avail (before queue): %d\n",
+		    tx_status.b.nptxqspcavail);
+	DWC_DEBUGPL(DBG_HCDV, "  NP Tx FIFO Space Avail (before queue): %d\n",
+		    tx_status.b.nptxfspcavail);
+#endif
+	/*
+	 * Keep track of the starting point. Skip over the start-of-list
+	 * entry.
+	 */
+	if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
+		hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
+	}
+	orig_qh_ptr = hcd->non_periodic_qh_ptr;
+
+	/*
+	 * Process once through the active list or until no more space is
+	 * available in the request queue or the Tx FIFO.
+	 */
+	do {
+		tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts);
+		if (!hcd->core_if->dma_enable && tx_status.b.nptxqspcavail == 0) {
+			no_queue_space = 1;
+			break;
+		}
+
+		qh = DWC_LIST_ENTRY(hcd->non_periodic_qh_ptr, dwc_otg_qh_t,
+				    qh_list_entry);
+		status =
+		    queue_transaction(hcd, qh->channel,
+				      tx_status.b.nptxfspcavail);
+
+		if (status > 0) {
+			more_to_do = 1;
+		} else if (status < 0) {
+			no_fifo_space = 1;
+			break;
+		}
+
+		/* Advance to next QH, skipping start-of-list entry. */
+		hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
+		if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
+			hcd->non_periodic_qh_ptr =
+			    hcd->non_periodic_qh_ptr->next;
+		}
+
+	} while (hcd->non_periodic_qh_ptr != orig_qh_ptr);
+
+	if (!hcd->core_if->dma_enable) {
+		gintmsk_data_t intr_mask = {.d32 = 0 };
+		intr_mask.b.nptxfempty = 1;
+
+#ifdef DEBUG
+		tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts);
+		DWC_DEBUGPL(DBG_HCDV,
+			    "  NP Tx Req Queue Space Avail (after queue): %d\n",
+			    tx_status.b.nptxqspcavail);
+		DWC_DEBUGPL(DBG_HCDV,
+			    "  NP Tx FIFO Space Avail (after queue): %d\n",
+			    tx_status.b.nptxfspcavail);
+#endif
+		if (more_to_do || no_queue_space || no_fifo_space) {
+			/*
+			 * May need to queue more transactions as the request
+			 * queue or Tx FIFO empties. Enable the non-periodic
+			 * Tx FIFO empty interrupt. (Always use the half-empty
+			 * level to ensure that new requests are loaded as
+			 * soon as possible.)
+			 */
+			dwc_modify_reg32(&global_regs->gintmsk, 0,
+					 intr_mask.d32);
+		} else {
+			/*
+			 * Disable the Tx FIFO empty interrupt since there are
+			 * no more transactions that need to be queued right
+			 * now. This function is called from interrupt
+			 * handlers to queue more transactions as transfer
+			 * states change.
+			 */
+			dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32,
+					 0);
+		}
+	}
+}
+
+/**
+ * This function processes the currently active host channels and queues
+ * transactions for these channels to the DWC_otg controller. It is called
+ * from HCD interrupt handler functions.
+ *
+ * @param hcd The HCD state structure.
+ * @param tr_type The type(s) of transactions to queue (non-periodic,
+ * periodic, or both).
+ */
+void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t * hcd,
+					   dwc_otg_transaction_type_e tr_type)
+{
+#ifdef DEBUG_SOF
+	DWC_DEBUGPL(DBG_HCD, "Queue Transactions\n");
+#endif
+	/* Process host channels associated with periodic transfers. */
+	if ((tr_type == DWC_OTG_TRANSACTION_PERIODIC ||
+	     tr_type == DWC_OTG_TRANSACTION_ALL) &&
+	    !DWC_LIST_EMPTY(&hcd->periodic_sched_assigned)) {
+
+		process_periodic_channels(hcd);
+	}
+
+	/* Process host channels associated with non-periodic transfers. */
+	if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC ||
+	    tr_type == DWC_OTG_TRANSACTION_ALL) {
+		if (!DWC_LIST_EMPTY(&hcd->non_periodic_sched_active)) {
+			process_non_periodic_channels(hcd);
+		} else {
+			/*
+			 * Ensure NP Tx FIFO empty interrupt is disabled when
+			 * there are no non-periodic transfers to process.
+			 */
+			gintmsk_data_t gintmsk = {.d32 = 0 };
+			gintmsk.b.nptxfempty = 1;
+			dwc_modify_reg32(&hcd->core_if->core_global_regs->
+					 gintmsk, gintmsk.d32, 0);
+		}
+	}
+}
+ 
+#ifdef DWC_HS_ELECT_TST
+/*
+ * Quick and dirty hack to implement the HS Electrical Test
+ * SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature.
+ *
+ * This code was copied from our userspace app "hset". It sends a
+ * Get Device Descriptor control sequence in two parts, first the
+ * Setup packet by itself, followed some time later by the In and
+ * Ack packets. Rather than trying to figure out how to add this
+ * functionality to the normal driver code, we just hijack the
+ * hardware, using these two function to drive the hardware
+ * directly.
+ */
+
+static dwc_otg_core_global_regs_t *global_regs;
+static dwc_otg_host_global_regs_t *hc_global_regs;
+static dwc_otg_hc_regs_t *hc_regs;
+static uint32_t *data_fifo;
+
+static void do_setup(void)
+{
+	gintsts_data_t gintsts;
+	hctsiz_data_t hctsiz;
+	hcchar_data_t hcchar;
+	haint_data_t haint;
+	hcint_data_t hcint;
+
+	/* Enable HAINTs */
+	dwc_write_reg32(&hc_global_regs->haintmsk, 0x0001);
+
+	/* Enable HCINTs */
+	dwc_write_reg32(&hc_regs->hcintmsk, 0x04a3);
+
+	/* Read GINTSTS */
+	gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
+
+	/* Read HAINT */
+	haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
+
+	/* Read HCINT */
+	hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
+
+	/* Read HCCHAR */
+	hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+
+	/* Clear HCINT */
+	dwc_write_reg32(&hc_regs->hcint, hcint.d32);
+
+	/* Clear HAINT */
+	dwc_write_reg32(&hc_global_regs->haint, haint.d32);
+
+	/* Clear GINTSTS */
+	dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
+
+	/* Read GINTSTS */
+	gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
+
+	/*
+	 * Send Setup packet (Get Device Descriptor)
+	 */
+
+	/* Make sure channel is disabled */
+	hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+	if (hcchar.b.chen) {
+		hcchar.b.chdis = 1;
+//              hcchar.b.chen = 1;
+		dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
+		//sleep(1);
+		dwc_mdelay(1000);
+
+		/* Read GINTSTS */
+		gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
+
+		/* Read HAINT */
+		haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
+
+		/* Read HCINT */
+		hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
+
+		/* Read HCCHAR */
+		hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+
+		/* Clear HCINT */
+		dwc_write_reg32(&hc_regs->hcint, hcint.d32);
+
+		/* Clear HAINT */
+		dwc_write_reg32(&hc_global_regs->haint, haint.d32);
+
+		/* Clear GINTSTS */
+		dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
+
+		hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+	}
+
+	/* Set HCTSIZ */
+	hctsiz.d32 = 0;
+	hctsiz.b.xfersize = 8;
+	hctsiz.b.pktcnt = 1;
+	hctsiz.b.pid = DWC_OTG_HC_PID_SETUP;
+	dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
+
+	/* Set HCCHAR */
+	hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+	hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
+	hcchar.b.epdir = 0;
+	hcchar.b.epnum = 0;
+	hcchar.b.mps = 8;
+	hcchar.b.chen = 1;
+	dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
+
+	/* Fill FIFO with Setup data for Get Device Descriptor */
+	data_fifo = (uint32_t *) ((char *)global_regs + 0x1000);
+	dwc_write_reg32(data_fifo++, 0x01000680);
+	dwc_write_reg32(data_fifo++, 0x00080000);
+
+	gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
+
+	/* Wait for host channel interrupt */
+	do {
+		gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
+	} while (gintsts.b.hcintr == 0);
+
+
+	/* Disable HCINTs */
+	dwc_write_reg32(&hc_regs->hcintmsk, 0x0000);
+
+	/* Disable HAINTs */
+	dwc_write_reg32(&hc_global_regs->haintmsk, 0x0000);
+
+	/* Read HAINT */
+	haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
+
+	/* Read HCINT */
+	hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
+
+	/* Read HCCHAR */
+	hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+
+	/* Clear HCINT */
+	dwc_write_reg32(&hc_regs->hcint, hcint.d32);
+
+	/* Clear HAINT */
+	dwc_write_reg32(&hc_global_regs->haint, haint.d32);
+
+	/* Clear GINTSTS */
+	dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
+
+	/* Read GINTSTS */
+	gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
+}
+
+static void do_in_ack(void)
+{
+	gintsts_data_t gintsts;
+	hctsiz_data_t hctsiz;
+	hcchar_data_t hcchar;
+	haint_data_t haint;
+	hcint_data_t hcint;
+	host_grxsts_data_t grxsts;
+
+	/* Enable HAINTs */
+	dwc_write_reg32(&hc_global_regs->haintmsk, 0x0001);
+
+	/* Enable HCINTs */
+	dwc_write_reg32(&hc_regs->hcintmsk, 0x04a3);
+
+	/* Read GINTSTS */
+	gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
+
+	/* Read HAINT */
+	haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
+
+	/* Read HCINT */
+	hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
+
+	/* Read HCCHAR */
+	hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+
+	/* Clear HCINT */
+	dwc_write_reg32(&hc_regs->hcint, hcint.d32);
+
+	/* Clear HAINT */
+	dwc_write_reg32(&hc_global_regs->haint, haint.d32);
+
+	/* Clear GINTSTS */
+	dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
+
+	/* Read GINTSTS */
+	gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
+
+	/*
+	 * Receive Control In packet
+	 */
+
+	/* Make sure channel is disabled */
+	hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+	if (hcchar.b.chen) {
+		hcchar.b.chdis = 1;
+		hcchar.b.chen = 1;
+		dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
+		//sleep(1);
+		dwc_mdelay(1000);
+
+		/* Read GINTSTS */
+		gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
+
+		/* Read HAINT */
+		haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
+
+		/* Read HCINT */
+		hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
+
+		/* Read HCCHAR */
+		hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+
+		/* Clear HCINT */
+		dwc_write_reg32(&hc_regs->hcint, hcint.d32);
+
+		/* Clear HAINT */
+		dwc_write_reg32(&hc_global_regs->haint, haint.d32);
+
+		/* Clear GINTSTS */
+		dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
+
+		hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+	}
+
+	/* Set HCTSIZ */
+	hctsiz.d32 = 0;
+	hctsiz.b.xfersize = 8;
+	hctsiz.b.pktcnt = 1;
+	hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
+	dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
+
+	/* Set HCCHAR */
+	hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+	hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
+	hcchar.b.epdir = 1;
+	hcchar.b.epnum = 0;
+	hcchar.b.mps = 8;
+	hcchar.b.chen = 1;
+	dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
+
+	gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
+
+	/* Wait for receive status queue interrupt */
+	do {
+		gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
+	} while (gintsts.b.rxstsqlvl == 0);
+
+
+	/* Read RXSTS */
+	grxsts.d32 = dwc_read_reg32(&global_regs->grxstsp);
+
+	/* Clear RXSTSQLVL in GINTSTS */
+	gintsts.d32 = 0;
+	gintsts.b.rxstsqlvl = 1;
+	dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
+
+	switch (grxsts.b.pktsts) {
+	case DWC_GRXSTS_PKTSTS_IN:
+		/* Read the data into the host buffer */
+		if (grxsts.b.bcnt > 0) {
+			int i;
+			int word_count = (grxsts.b.bcnt + 3) / 4;
+
+			data_fifo = (uint32_t *) ((char *)global_regs + 0x1000);
+
+			for (i = 0; i < word_count; i++) {
+				(void)dwc_read_reg32(data_fifo++);
+			}
+		}
+		break;
+
+	default:
+		break;
+	}
+
+	gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
+
+	/* Wait for receive status queue interrupt */
+	do {
+		gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
+	} while (gintsts.b.rxstsqlvl == 0);
+
+
+	/* Read RXSTS */
+	grxsts.d32 = dwc_read_reg32(&global_regs->grxstsp);
+
+	/* Clear RXSTSQLVL in GINTSTS */
+	gintsts.d32 = 0;
+	gintsts.b.rxstsqlvl = 1;
+	dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
+
+	switch (grxsts.b.pktsts) {
+	case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
+		break;
+
+	default:
+		break;
+	}
+
+	gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
+
+	/* Wait for host channel interrupt */
+	do {
+		gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
+	} while (gintsts.b.hcintr == 0);
+
+
+	/* Read HAINT */
+	haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
+
+	/* Read HCINT */
+	hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
+
+	/* Read HCCHAR */
+	hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+
+	/* Clear HCINT */
+	dwc_write_reg32(&hc_regs->hcint, hcint.d32);
+
+	/* Clear HAINT */
+	dwc_write_reg32(&hc_global_regs->haint, haint.d32);
+
+	/* Clear GINTSTS */
+	dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
+
+	/* Read GINTSTS */
+	gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
+
+//      usleep(100000);
+//      mdelay(100);
+	dwc_mdelay(1);
+
+	/*
+	 * Send handshake packet
+	 */
+
+	/* Read HAINT */
+	haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
+
+	/* Read HCINT */
+	hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
+
+	/* Read HCCHAR */
+	hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+
+	/* Clear HCINT */
+	dwc_write_reg32(&hc_regs->hcint, hcint.d32);
+
+	/* Clear HAINT */
+	dwc_write_reg32(&hc_global_regs->haint, haint.d32);
+
+	/* Clear GINTSTS */
+	dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
+
+	/* Read GINTSTS */
+	gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
+
+	/* Make sure channel is disabled */
+	hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+	if (hcchar.b.chen) {
+		hcchar.b.chdis = 1;
+		hcchar.b.chen = 1;
+		dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
+		//sleep(1);
+		dwc_mdelay(1000);
+
+		/* Read GINTSTS */
+		gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
+
+		/* Read HAINT */
+		haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
+
+		/* Read HCINT */
+		hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
+
+		/* Read HCCHAR */
+		hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+
+		/* Clear HCINT */
+		dwc_write_reg32(&hc_regs->hcint, hcint.d32);
+
+		/* Clear HAINT */
+		dwc_write_reg32(&hc_global_regs->haint, haint.d32);
+
+		/* Clear GINTSTS */
+		dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
+
+		hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+	}
+
+	/* Set HCTSIZ */
+	hctsiz.d32 = 0;
+	hctsiz.b.xfersize = 0;
+	hctsiz.b.pktcnt = 1;
+	hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
+	dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
+
+	/* Set HCCHAR */
+	hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+	hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
+	hcchar.b.epdir = 0;
+	hcchar.b.epnum = 0;
+	hcchar.b.mps = 8;
+	hcchar.b.chen = 1;
+	dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
+
+	gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
+
+	/* Wait for host channel interrupt */
+	do {
+		gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
+	} while (gintsts.b.hcintr == 0);
+
+
+	/* Disable HCINTs */
+	dwc_write_reg32(&hc_regs->hcintmsk, 0x0000);
+
+	/* Disable HAINTs */
+	dwc_write_reg32(&hc_global_regs->haintmsk, 0x0000);
+
+	/* Read HAINT */
+	haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
+
+	/* Read HCINT */
+	hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
+
+	/* Read HCCHAR */
+	hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+
+	/* Clear HCINT */
+	dwc_write_reg32(&hc_regs->hcint, hcint.d32);
+
+	/* Clear HAINT */
+	dwc_write_reg32(&hc_global_regs->haint, haint.d32);
+
+	/* Clear GINTSTS */
+	dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
+
+	/* Read GINTSTS */
+	gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
+}
+#endif
+
+/** Handles hub class-specific requests. */
+int dwc_otg_hcd_hub_control(dwc_otg_hcd_t * dwc_otg_hcd,
+			    uint16_t typeReq,
+			    uint16_t wValue,
+			    uint16_t wIndex, uint8_t * buf, uint16_t wLength)
+{
+	int retval = 0;
+
+	dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
+	usb_hub_descriptor_t *hub_desc;
+	hprt0_data_t hprt0 = {.d32 = 0 };
+
+	uint32_t port_status;
+
+	switch (typeReq) {
+	case UCR_CLEAR_HUB_FEATURE:
+		DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
+			    "ClearHubFeature 0x%x\n", wValue);
+		switch (wValue) {
+		case UHF_C_HUB_LOCAL_POWER:
+		case UHF_C_HUB_OVER_CURRENT:
+			/* Nothing required here */
+			break;
+		default:
+			retval = -DWC_E_INVALID;
+			DWC_ERROR("DWC OTG HCD - "
+				  "ClearHubFeature request %xh unknown\n",
+				  wValue);
+		}
+		break;
+	case UCR_CLEAR_PORT_FEATURE:
+#ifdef CONFIG_USB_DWC_OTG_LPM
+		if (wValue != UHF_PORT_L1)
+#endif
+			if (!wIndex || wIndex > 1)
+				goto error;
+
+		switch (wValue) {
+		case UHF_PORT_ENABLE:
+			DWC_DEBUGPL(DBG_ANY, "DWC OTG HCD HUB CONTROL - "
+				    "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
+			hprt0.d32 = dwc_otg_read_hprt0(core_if);
+			hprt0.b.prtena = 1;
+			dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
+			break;
+		case UHF_PORT_SUSPEND:
+			DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
+				    "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
+
+			dwc_write_reg32(core_if->pcgcctl, 0);
+			dwc_mdelay(5);
+
+			hprt0.d32 = dwc_otg_read_hprt0(core_if);
+			hprt0.b.prtres = 1;
+			dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
+			hprt0.b.prtsusp = 0;
+			/* Clear Resume bit */
+			dwc_mdelay(100);
+			hprt0.b.prtres = 0;
+			dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
+			break;
+#ifdef CONFIG_USB_DWC_OTG_LPM
+		case UHF_PORT_L1:
+			{
+				pcgcctl_data_t pcgcctl = {.d32 = 0 };
+				glpmcfg_data_t lpmcfg = {.d32 = 0 };
+
+				lpmcfg.d32 =
+				    dwc_read_reg32(&core_if->core_global_regs->
+						   glpmcfg);
+				lpmcfg.b.en_utmi_sleep = 0;
+				lpmcfg.b.hird_thres &= (~(1 << 4));
+				lpmcfg.b.prt_sleep_sts = 1;
+				dwc_write_reg32(&core_if->core_global_regs->
+						glpmcfg, lpmcfg.d32);
+
+				/* Clear Enbl_L1Gating bit. */
+				pcgcctl.b.enbl_sleep_gating = 1;
+				dwc_modify_reg32(core_if->pcgcctl, pcgcctl.d32,
+						 0);
+
+				dwc_mdelay(5);
+
+				hprt0.d32 = dwc_otg_read_hprt0(core_if);
+				hprt0.b.prtres = 1;
+				dwc_write_reg32(core_if->host_if->hprt0,
+						hprt0.d32);
+				/* This bit will be cleared in wakeup interrupt handle */
+				break;
+			}
+#endif
+		case UHF_PORT_POWER:
+			DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
+				    "ClearPortFeature USB_PORT_FEAT_POWER\n");
+			hprt0.d32 = dwc_otg_read_hprt0(core_if);
+			hprt0.b.prtpwr = 0;
+			dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
+			break;
+		case UHF_PORT_INDICATOR:
+			DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
+				    "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
+			/* Port inidicator not supported */
+			break;
+		case UHF_C_PORT_CONNECTION:
+			/* Clears drivers internal connect status change
+			 * flag */
+			DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
+				    "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
+			dwc_otg_hcd->flags.b.port_connect_status_change = 0;
+			break;
+		case UHF_C_PORT_RESET:
+			/* Clears the driver's internal Port Reset Change
+			 * flag */
+			DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
+				    "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
+			dwc_otg_hcd->flags.b.port_reset_change = 0;
+			break;
+		case UHF_C_PORT_ENABLE:
+			/* Clears the driver's internal Port
+			 * Enable/Disable Change flag */
+			DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
+				    "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
+			dwc_otg_hcd->flags.b.port_enable_change = 0;
+			break;
+		case UHF_C_PORT_SUSPEND:
+			/* Clears the driver's internal Port Suspend
+			 * Change flag, which is set when resume signaling on
+			 * the host port is complete */
+			DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
+				    "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
+			dwc_otg_hcd->flags.b.port_suspend_change = 0;
+			break;
+#ifdef CONFIG_USB_DWC_OTG_LPM
+		case UHF_C_PORT_L1:
+			dwc_otg_hcd->flags.b.port_l1_change = 0;
+			break;
+#endif
+		case UHF_C_PORT_OVER_CURRENT:
+			DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
+				    "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
+			dwc_otg_hcd->flags.b.port_over_current_change = 0;
+			break;
+		default:
+			retval = -DWC_E_INVALID;
+			DWC_ERROR("DWC OTG HCD - "
+				  "ClearPortFeature request %xh "
+				  "unknown or unsupported\n", wValue);
+		}
+		break;
+	case UCR_GET_HUB_DESCRIPTOR:
+		DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
+			    "GetHubDescriptor\n");
+		hub_desc = (usb_hub_descriptor_t *) buf;
+		hub_desc->bDescLength = 9;
+		hub_desc->bDescriptorType = 0x29;
+		hub_desc->bNbrPorts = 1;
+		USETW(hub_desc->wHubCharacteristics, 0x08);
+		hub_desc->bPwrOn2PwrGood = 1;
+		hub_desc->bHubContrCurrent = 0;
+		hub_desc->DeviceRemovable[0] = 0;
+		hub_desc->DeviceRemovable[1] = 0xff;
+		break;
+	case UCR_GET_HUB_STATUS:
+		DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
+			    "GetHubStatus\n");
+		DWC_MEMSET(buf, 0, 4);
+		break;
+	case UCR_GET_PORT_STATUS:
+		DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
+			    "GetPortStatus\n");
+		if (!wIndex || wIndex > 1)
+			goto error;
+
+		port_status = 0;
+
+		if (dwc_otg_hcd->flags.b.port_connect_status_change)
+			port_status |= (1 << UHF_C_PORT_CONNECTION);
+
+		if (dwc_otg_hcd->flags.b.port_enable_change)
+			port_status |= (1 << UHF_C_PORT_ENABLE);
+
+		if (dwc_otg_hcd->flags.b.port_suspend_change)
+			port_status |= (1 << UHF_C_PORT_SUSPEND);
+
+		if (dwc_otg_hcd->flags.b.port_l1_change)
+			port_status |= (1 << UHF_C_PORT_L1);
+
+		if (dwc_otg_hcd->flags.b.port_reset_change) {
+			port_status |= (1 << UHF_C_PORT_RESET);
+		}
+
+		if (dwc_otg_hcd->flags.b.port_over_current_change) {
+			DWC_ERROR("Device Not Supported\n");
+			port_status |= (1 << UHF_C_PORT_OVER_CURRENT);
+		}
+
+		if (!dwc_otg_hcd->flags.b.port_connect_status) {
+			/*
+			 * The port is disconnected, which means the core is
+			 * either in device mode or it soon will be. Just
+			 * return 0's for the remainder of the port status
+			 * since the port register can't be read if the core
+			 * is in device mode.
+			 */
+			*((__le32 *) buf) = dwc_cpu_to_le32(&port_status);
+			break;
+		}
+
+		hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
+		DWC_DEBUGPL(DBG_HCDV, "  HPRT0: 0x%08x\n", hprt0.d32);
+
+		if (hprt0.b.prtconnsts)
+			port_status |= (1 << UHF_PORT_CONNECTION);
+
+		if (hprt0.b.prtena)
+			port_status |= (1 << UHF_PORT_ENABLE);
+
+		if (hprt0.b.prtsusp)
+			port_status |= (1 << UHF_PORT_SUSPEND);
+
+		if (hprt0.b.prtovrcurract)
+			port_status |= (1 << UHF_PORT_OVER_CURRENT);
+
+		if (hprt0.b.prtrst)
+			port_status |= (1 << UHF_PORT_RESET);
+
+		if (hprt0.b.prtpwr)
+			port_status |= (1 << UHF_PORT_POWER);
+
+		if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED)
+			port_status |= (1 << UHF_PORT_HIGH_SPEED);
+		else if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED)
+			port_status |= (1 << UHF_PORT_LOW_SPEED);
+
+		if (hprt0.b.prttstctl)
+			port_status |= (1 << UHF_PORT_TEST);
+		if (dwc_otg_get_lpm_portsleepstatus(dwc_otg_hcd->core_if)) {
+			port_status |= (1 << UHF_PORT_L1);
+		}
+
+		/* USB_PORT_FEAT_INDICATOR unsupported always 0 */
+
+		*((__le32 *) buf) = dwc_cpu_to_le32(&port_status);
+
+		break;
+	case UCR_SET_HUB_FEATURE:
+		DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
+			    "SetHubFeature\n");
+		/* No HUB features supported */
+		break;
+	case UCR_SET_PORT_FEATURE:
+		if (wValue != UHF_PORT_TEST && (!wIndex || wIndex > 1))
+			goto error;
+
+		if (!dwc_otg_hcd->flags.b.port_connect_status) {
+			/*
+			 * The port is disconnected, which means the core is
+			 * either in device mode or it soon will be. Just
+			 * return without doing anything since the port
+			 * register can't be written if the core is in device
+			 * mode.
+			 */
+			break;
+		}
+
+		switch (wValue) {
+		case UHF_PORT_SUSPEND:
+			DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
+				    "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
+			if (dwc_otg_hcd_otg_port(dwc_otg_hcd) == wIndex &&
+			    dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) {
+				gotgctl_data_t gotgctl = {.d32 = 0 };
+				gotgctl.b.hstsethnpen = 1;
+				dwc_modify_reg32(&core_if->core_global_regs->
+						 gotgctl, 0, gotgctl.d32);
+				core_if->op_state = A_SUSPEND;
+			}
+			hprt0.d32 = dwc_otg_read_hprt0(core_if);
+			hprt0.b.prtsusp = 1;
+			dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
+			{
+				uint64_t flags;
+				/* Update lx_state */
+				DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
+				core_if->lx_state = DWC_OTG_L2;
+				DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags);
+			}
+			/* Suspend the Phy Clock */
+			{
+				pcgcctl_data_t pcgcctl = {.d32 = 0 };
+				pcgcctl.b.stoppclk = 1;
+				dwc_modify_reg32(core_if->pcgcctl, 0,
+						 pcgcctl.d32);
+			}
+
+			/* For HNP the bus must be suspended for at least 200ms. */
+			if (dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) {
+				dwc_mdelay(200);
+			}
+			break;
+		case UHF_PORT_POWER:
+			DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
+				    "SetPortFeature - USB_PORT_FEAT_POWER\n");
+			hprt0.d32 = dwc_otg_read_hprt0(core_if);
+			hprt0.b.prtpwr = 1;
+			dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
+			break;
+		case UHF_PORT_RESET:
+			DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
+				    "SetPortFeature - USB_PORT_FEAT_RESET\n");
+			{
+				pcgcctl_data_t pcgcctl = {.d32 = 0 };
+				pcgcctl.b.enbl_sleep_gating = 1;
+				pcgcctl.b.stoppclk = 1;
+				dwc_modify_reg32(core_if->pcgcctl, pcgcctl.d32,
+						 0);
+				dwc_write_reg32(core_if->pcgcctl, 0);
+			}
+#ifdef CONFIG_USB_DWC_OTG_LPM
+			{
+				glpmcfg_data_t lpmcfg;
+				lpmcfg.d32 =
+				    dwc_read_reg32(&core_if->core_global_regs->
+						   glpmcfg);
+				if (lpmcfg.b.prt_sleep_sts) {
+					lpmcfg.b.en_utmi_sleep = 0;
+					lpmcfg.b.hird_thres &= (~(1 << 4));
+					dwc_write_reg32(&core_if->
+							core_global_regs->
+							glpmcfg, lpmcfg.d32);
+					dwc_mdelay(1);
+				}
+			}
+#endif
+			hprt0.d32 = dwc_otg_read_hprt0(core_if);
+			/* When B-Host the Port reset bit is set in
+			 * the Start HCD Callback function, so that
+			 * the reset is started within 1ms of the HNP
+			 * success interrupt. */
+			if (!dwc_otg_hcd_is_b_host(dwc_otg_hcd)) {
+				hprt0.b.prtrst = 1;
+				dwc_write_reg32(core_if->host_if->hprt0,
+						hprt0.d32);
+			}
+			/* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
+			dwc_mdelay(60);
+			hprt0.b.prtrst = 0;
+			dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
+			core_if->lx_state = DWC_OTG_L0;	/* Now back to the on state */
+			break;
+#ifdef DWC_HS_ELECT_TST
+		case UHF_PORT_TEST:
+			{
+				uint32_t t;
+				gintmsk_data_t gintmsk;
+
+				t = (wIndex >> 8);	/* MSB wIndex USB */
+				DWC_DEBUGPL(DBG_HCD,
+					    "DWC OTG HCD HUB CONTROL - "
+					    "SetPortFeature - USB_PORT_FEAT_TEST %d\n",
+					    t);
+				DWC_WARN("USB_PORT_FEAT_TEST %d\n", t);
+				if (t < 6) {
+					hprt0.d32 = dwc_otg_read_hprt0(core_if);
+					hprt0.b.prttstctl = t;
+					dwc_write_reg32(core_if->host_if->hprt0,
+							hprt0.d32);
+				} else {
+					/* Setup global vars with reg addresses (quick and
+					 * dirty hack, should be cleaned up)
+					 */
+					global_regs = core_if->core_global_regs;
+					hc_global_regs =
+					    core_if->host_if->host_global_regs;
+					hc_regs =
+					    (dwc_otg_hc_regs_t *) ((char *)
+								   global_regs +
+								   0x500);
+					data_fifo =
+					    (uint32_t *) ((char *)global_regs +
+							  0x1000);
+
+					if (t == 6) {	/* HS_HOST_PORT_SUSPEND_RESUME */
+						/* Save current interrupt mask */
+						gintmsk.d32 =
+						    dwc_read_reg32
+						    (&global_regs->gintmsk);
+
+						/* Disable all interrupts while we muck with
+						 * the hardware directly
+						 */
+						dwc_write_reg32(&global_regs->
+								gintmsk, 0);
+
+						/* 15 second delay per the test spec */
+						dwc_mdelay(15000);
+
+						/* Drive suspend on the root port */
+						hprt0.d32 =
+						    dwc_otg_read_hprt0(core_if);
+						hprt0.b.prtsusp = 1;
+						hprt0.b.prtres = 0;
+						dwc_write_reg32(core_if->
+								host_if->hprt0,
+								hprt0.d32);
+
+						/* 15 second delay per the test spec */
+						dwc_mdelay(15000);
+
+						/* Drive resume on the root port */
+						hprt0.d32 =
+						    dwc_otg_read_hprt0(core_if);
+						hprt0.b.prtsusp = 0;
+						hprt0.b.prtres = 1;
+						dwc_write_reg32(core_if->
+								host_if->hprt0,
+								hprt0.d32);
+						dwc_mdelay(100);
+
+						/* Clear the resume bit */
+						hprt0.b.prtres = 0;
+						dwc_write_reg32(core_if->
+								host_if->hprt0,
+								hprt0.d32);
+
+						/* Restore interrupts */
+						dwc_write_reg32(&global_regs->
+								gintmsk,
+								gintmsk.d32);
+					} else if (t == 7) {	/* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */
+						/* Save current interrupt mask */
+						gintmsk.d32 =
+						    dwc_read_reg32
+						    (&global_regs->gintmsk);
+
+						/* Disable all interrupts while we muck with
+						 * the hardware directly
+						 */
+						dwc_write_reg32(&global_regs->
+								gintmsk, 0);
+
+						/* 15 second delay per the test spec */
+						dwc_mdelay(15000);
+
+						/* Send the Setup packet */
+						do_setup();
+
+						/* 15 second delay so nothing else happens for awhile */
+						dwc_mdelay(15000);
+
+						/* Restore interrupts */
+						dwc_write_reg32(&global_regs->
+								gintmsk,
+								gintmsk.d32);
+					} else if (t == 8) {	/* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */
+						/* Save current interrupt mask */
+						gintmsk.d32 =
+						    dwc_read_reg32
+						    (&global_regs->gintmsk);
+
+						/* Disable all interrupts while we muck with
+						 * the hardware directly
+						 */
+						dwc_write_reg32(&global_regs->
+								gintmsk, 0);
+
+						/* Send the Setup packet */
+						do_setup();
+
+						/* 15 second delay so nothing else happens for awhile */
+						dwc_mdelay(15000);
+
+						/* Send the In and Ack packets */
+						do_in_ack();
+
+						/* 15 second delay so nothing else happens for awhile */
+						dwc_mdelay(15000);
+
+						/* Restore interrupts */
+						dwc_write_reg32(&global_regs->
+								gintmsk,
+								gintmsk.d32);
+					}
+				}
+				break;
+			}
+#endif				/* DWC_HS_ELECT_TST */
+
+		case UHF_PORT_INDICATOR:
+			DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
+				    "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
+			/* Not supported */
+			break;
+		default:
+			retval = -DWC_E_INVALID;
+			DWC_ERROR("DWC OTG HCD - "
+				  "SetPortFeature request %xh "
+				  "unknown or unsupported\n", wValue);
+			break;
+		}
+		break;
+#ifdef CONFIG_USB_DWC_OTG_LPM
+	case UCR_SET_AND_TEST_PORT_FEATURE:
+		if (wValue != UHF_PORT_L1) {
+			goto error;
+		}
+		{
+			int portnum, hird, devaddr, remwake;
+			glpmcfg_data_t lpmcfg;
+			uint32_t time_usecs;
+			gintsts_data_t gintsts;
+			gintmsk_data_t gintmsk;
+
+			if (!dwc_otg_get_param_lpm_enable(core_if)) {
+				goto error;
+			}
+			if (wValue != UHF_PORT_L1 || wLength != 1) {
+				goto error;
+			}
+			/* Check if the port currently is in SLEEP state */
+			lpmcfg.d32 =
+			    dwc_read_reg32(&core_if->core_global_regs->glpmcfg);
+			if (lpmcfg.b.prt_sleep_sts) {
+				DWC_INFO("Port is already in sleep mode\n");
+				buf[0] = 0;	/* Return success */
+				break;
+			}
+
+			portnum = wIndex & 0xf;
+			hird = (wIndex >> 4) & 0xf;
+			devaddr = (wIndex >> 8) & 0x7f;
+			remwake = (wIndex >> 15);
+
+			if (portnum != 1) {
+				retval = -DWC_E_INVALID;
+				DWC_WARN
+				    ("Wrong port number(%d) in SetandTestPortFeature request\n",
+				     portnum);
+				break;
+			}
+
+			DWC_PRINTF
+			    ("SetandTestPortFeature request: portnum = %d, hird = %d, devaddr = %d, rewake = %d\n",
+			     portnum, hird, devaddr, remwake);
+			/* Disable LPM interrupt */
+			gintmsk.d32 = 0;
+			gintmsk.b.lpmtranrcvd = 1;
+			dwc_modify_reg32(&core_if->core_global_regs->gintmsk,
+					 gintmsk.d32, 0);
+
+			if (dwc_otg_hcd_send_lpm
+			    (dwc_otg_hcd, devaddr, hird, remwake)) {
+				retval = -DWC_E_INVALID;
+				break;
+			}
+
+			time_usecs = 10 * (lpmcfg.b.retry_count + 1);
+			/* We will consider timeout if time_usecs microseconds pass,
+			 * and we don't receive LPM transaction status.
+			 * After receiving non-error responce(ACK/NYET/STALL) from device,
+			 *  core will set lpmtranrcvd bit.
+			 */
+			do {
+				gintsts.d32 =
+				    dwc_read_reg32(&core_if->core_global_regs->
+						   gintsts);
+				if (gintsts.b.lpmtranrcvd) {
+					break;
+				}
+				dwc_udelay(1);
+			} while (--time_usecs);
+			/* lpm_int bit will be cleared in LPM interrupt handler */
+
+			/* Now fill status
+			 * 0x00 - Success
+			 * 0x10 - NYET
+			 * 0x11 - Timeout
+			 */
+			if (!gintsts.b.lpmtranrcvd) {
+				buf[0] = 0x3;	/* Completion code is Timeout */
+				dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd);
+			} else {
+				lpmcfg.d32 =
+				    dwc_read_reg32(&core_if->core_global_regs->
+						   glpmcfg);
+				if (lpmcfg.b.lpm_resp == 0x3) {
+					/* ACK responce from the device */
+					buf[0] = 0x00;	/* Success */
+				} else if (lpmcfg.b.lpm_resp == 0x2) {
+					/* NYET responce from the device */
+					buf[0] = 0x2;
+				} else {
+					/* Otherwise responce with Timeout */
+					buf[0] = 0x3;
+				}
+			}
+			DWC_PRINTF("Device responce to LPM trans is %x\n",
+				   lpmcfg.b.lpm_resp);
+			dwc_modify_reg32(&core_if->core_global_regs->gintmsk, 0,
+					 gintmsk.d32);
+
+			break;
+		}
+#endif				/* CONFIG_USB_DWC_OTG_LPM */
+	default:
+	      error:
+		retval = -DWC_E_INVALID;
+		DWC_WARN("DWC OTG HCD - "
+			 "Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n",
+			 typeReq, wIndex, wValue);
+		break;
+	}
+
+	return retval;
+}
+
+#ifdef CONFIG_USB_DWC_OTG_LPM
+/** Returns index of host channel to perform LPM transaction. */
+int dwc_otg_hcd_get_hc_for_lpm_tran(dwc_otg_hcd_t * hcd, uint8_t devaddr)
+{
+	dwc_otg_core_if_t *core_if = hcd->core_if;
+	dwc_hc_t *hc;
+	hcchar_data_t hcchar;
+	gintmsk_data_t gintmsk = {.d32 = 0 };
+
+	if (DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
+		DWC_PRINTF("No free channel to select for LPM transaction\n");
+		return -1;
+	}
+
+	hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list);
+
+	/* Mask host channel interrupts. */
+	gintmsk.b.hcintr = 1;
+	dwc_modify_reg32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
+
+	/* Fill fields that core needs for LPM transaction */
+	hcchar.b.devaddr = devaddr;
+	hcchar.b.epnum = 0;
+	hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
+	hcchar.b.mps = 64;
+	hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW);
+	hcchar.b.epdir = 0;	/* OUT */
+	dwc_write_reg32(&core_if->host_if->hc_regs[hc->hc_num]->hcchar,
+			hcchar.d32);
+
+	/* Remove the host channel from the free list. */
+	DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry);
+
+	DWC_PRINTF("hcnum = %d devaddr = %d\n", hc->hc_num, devaddr);
+
+	return hc->hc_num;
+}
+
+/** Release hc after performing LPM transaction */
+void dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd_t * hcd)
+{
+	dwc_hc_t *hc;
+	glpmcfg_data_t lpmcfg;
+	uint8_t hc_num;
+
+	lpmcfg.d32 = dwc_read_reg32(&hcd->core_if->core_global_regs->glpmcfg);
+	hc_num = lpmcfg.b.lpm_chan_index;
+
+	hc = hcd->hc_ptr_array[hc_num];
+
+	DWC_PRINTF("Freeing channel %d after LPM\n", hc_num);
+	/* Return host channel to free list */
+	DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
+}
+
+int dwc_otg_hcd_send_lpm(dwc_otg_hcd_t * hcd, uint8_t devaddr, uint8_t hird,
+			 uint8_t bRemoteWake)
+{
+	glpmcfg_data_t lpmcfg;
+	pcgcctl_data_t pcgcctl = {.d32 = 0 };
+	int channel;
+
+	channel = dwc_otg_hcd_get_hc_for_lpm_tran(hcd, devaddr);
+	if (channel < 0) {
+		return channel;
+	}
+
+	pcgcctl.b.enbl_sleep_gating = 1;
+	dwc_modify_reg32(hcd->core_if->pcgcctl, 0, pcgcctl.d32);
+
+	/* Read LPM config register */
+	lpmcfg.d32 = dwc_read_reg32(&hcd->core_if->core_global_regs->glpmcfg);
+
+	/* Program LPM transaction fields */
+	lpmcfg.b.rem_wkup_en = bRemoteWake;
+	lpmcfg.b.hird = hird;
+	lpmcfg.b.hird_thres = 0x1c;
+	lpmcfg.b.lpm_chan_index = channel;
+	lpmcfg.b.en_utmi_sleep = 1;
+	/* Program LPM config register */
+	dwc_write_reg32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32);
+
+	/* Send LPM transaction */
+	lpmcfg.b.send_lpm = 1;
+	dwc_write_reg32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32);
+
+	return 0;
+}
+
+#endif				/* CONFIG_USB_DWC_OTG_LPM */
+
+int dwc_otg_hcd_is_status_changed(dwc_otg_hcd_t * hcd, int port)
+{
+	int retval;
+
+	if (port != 1) {
+		return -DWC_E_INVALID;
+	}
+
+	retval = (hcd->flags.b.port_connect_status_change ||
+		  hcd->flags.b.port_reset_change ||
+		  hcd->flags.b.port_enable_change ||
+		  hcd->flags.b.port_suspend_change ||
+		  hcd->flags.b.port_over_current_change);
+#ifdef DEBUG
+	if (retval) {
+		DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB STATUS DATA:"
+			    " Root port status changed\n");
+		DWC_DEBUGPL(DBG_HCDV, "  port_connect_status_change: %d\n",
+			    hcd->flags.b.port_connect_status_change);
+		DWC_DEBUGPL(DBG_HCDV, "  port_reset_change: %d\n",
+			    hcd->flags.b.port_reset_change);
+		DWC_DEBUGPL(DBG_HCDV, "  port_enable_change: %d\n",
+			    hcd->flags.b.port_enable_change);
+		DWC_DEBUGPL(DBG_HCDV, "  port_suspend_change: %d\n",
+			    hcd->flags.b.port_suspend_change);
+		DWC_DEBUGPL(DBG_HCDV, "  port_over_current_change: %d\n",
+			    hcd->flags.b.port_over_current_change);
+	}
+#endif
+	return retval;
+}
+
+int dwc_otg_hcd_get_frame_number(dwc_otg_hcd_t * dwc_otg_hcd)
+{
+	hfnum_data_t hfnum;
+	hfnum.d32 = dwc_read_reg32(&dwc_otg_hcd->core_if->
+				   host_if->host_global_regs->hfnum);
+
+#ifdef DEBUG_SOF
+	DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD GET FRAME NUMBER %d\n",
+		    hfnum.b.frnum);
+#endif
+	return hfnum.b.frnum;
+}
+
+int dwc_otg_hcd_start(dwc_otg_hcd_t * hcd,
+		      struct dwc_otg_hcd_function_ops *fops)
+{
+	int retval = 0;
+
+	hcd->fops = fops;
+	if (!dwc_otg_is_device_mode(hcd->core_if)) {
+		dwc_otg_hcd_reinit(hcd);
+	} else {
+		retval = -DWC_E_NO_DEVICE;
+	}
+
+	return retval;
+}
+
+void *dwc_otg_hcd_get_priv_data(dwc_otg_hcd_t * hcd)
+{
+	return hcd->priv;
+}
+
+void dwc_otg_hcd_set_priv_data(dwc_otg_hcd_t * hcd, void *priv_data)
+{
+	hcd->priv = priv_data;
+}
+
+uint32_t dwc_otg_hcd_otg_port(dwc_otg_hcd_t * hcd)
+{
+	return hcd->otg_port;
+}
+
+uint32_t dwc_otg_hcd_is_b_host(dwc_otg_hcd_t * hcd)
+{
+	uint32_t is_b_host;
+	if (hcd->core_if->op_state == B_HOST) {
+		is_b_host = 1;
+	} else {
+		is_b_host = 0;
+	}
+
+	return is_b_host;
+}
+
+dwc_otg_hcd_urb_t *dwc_otg_hcd_urb_alloc(dwc_otg_hcd_t * hcd,
+					 int iso_desc_count, int atomic_alloc)
+{
+	dwc_otg_hcd_urb_t *dwc_otg_urb;
+	uint32_t size;
+
+	size =
+	    sizeof(*dwc_otg_urb) +
+	    iso_desc_count * sizeof(struct dwc_otg_hcd_iso_packet_desc);
+	if (atomic_alloc) {
+		dwc_otg_urb = dwc_alloc_atomic(size);
+	} else {
+		dwc_otg_urb = dwc_alloc(size);
+	}
+	dwc_otg_urb->packet_count = iso_desc_count;
+
+	return dwc_otg_urb;
+}
+
+void dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_hcd_urb_t * dwc_otg_urb,
+				  uint8_t dev_addr, uint8_t ep_num,
+				  uint8_t ep_type, uint8_t ep_dir, uint16_t mps)
+{
+	dwc_otg_hcd_fill_pipe(&dwc_otg_urb->pipe_info, dev_addr, ep_num,
+			      ep_type, ep_dir, mps);
+#if 0
+	DWC_PRINTF
+	    ("addr = %d, ep_num = %d, ep_dir = 0x%x, ep_type = 0x%x, mps = %d\n",
+	     dev_addr, ep_num, ep_dir, ep_type, mps);
+#endif
+}
+
+void dwc_otg_hcd_urb_set_params(dwc_otg_hcd_urb_t * dwc_otg_urb,
+				void *urb_handle, void *buf, dwc_dma_t dma,
+				uint32_t buflen, void *setup_packet,
+				dwc_dma_t setup_dma, uint32_t flags,
+				uint16_t interval)
+{
+	dwc_otg_urb->priv = urb_handle;
+	dwc_otg_urb->buf = buf;
+	dwc_otg_urb->dma = dma;
+	dwc_otg_urb->length = buflen;
+	dwc_otg_urb->setup_packet = setup_packet;
+	dwc_otg_urb->setup_dma = setup_dma;
+	dwc_otg_urb->flags = flags;
+	dwc_otg_urb->interval = interval;
+	dwc_otg_urb->status = -DWC_E_IN_PROGRESS;
+}
+
+uint32_t dwc_otg_hcd_urb_get_status(dwc_otg_hcd_urb_t * dwc_otg_urb)
+{
+	return dwc_otg_urb->status;
+}
+
+uint32_t dwc_otg_hcd_urb_get_actual_length(dwc_otg_hcd_urb_t * dwc_otg_urb)
+{
+	return dwc_otg_urb->actual_length;
+}
+
+uint32_t dwc_otg_hcd_urb_get_error_count(dwc_otg_hcd_urb_t * dwc_otg_urb)
+{
+	return dwc_otg_urb->error_count;
+}
+
+void dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_hcd_urb_t * dwc_otg_urb,
+					 int desc_num, uint32_t offset,
+					 uint32_t length)
+{
+	dwc_otg_urb->iso_descs[desc_num].offset = offset;
+	dwc_otg_urb->iso_descs[desc_num].length = length;
+}
+
+uint32_t dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_hcd_urb_t * dwc_otg_urb,
+					     int desc_num)
+{
+	return dwc_otg_urb->iso_descs[desc_num].status;
+}
+
+uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length(dwc_otg_hcd_urb_t *
+						    dwc_otg_urb, int desc_num)
+{
+	return dwc_otg_urb->iso_descs[desc_num].actual_length;
+}
+
+int dwc_otg_hcd_is_bandwidth_allocated(dwc_otg_hcd_t * hcd, void *ep_handle)
+{
+	int allocated = 0;
+	dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
+
+	if (qh) {
+		if (!DWC_LIST_EMPTY(&qh->qh_list_entry)) {
+			allocated = 1;
+		}
+	}
+	return allocated;
+}
+
+int dwc_otg_hcd_is_bandwidth_freed(dwc_otg_hcd_t * hcd, void *ep_handle)
+{
+	dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
+	int freed = 0;
+	DWC_ASSERT(qh, "qh is not allocated\n");
+
+	if (DWC_LIST_EMPTY(&qh->qh_list_entry)) {
+		freed = 1;
+	}
+
+	return freed;
+}
+
+uint8_t dwc_otg_hcd_get_ep_bandwidth(dwc_otg_hcd_t * hcd, void *ep_handle)
+{
+	dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
+	DWC_ASSERT(qh, "qh is not allocated\n");
+	return qh->usecs;
+}
+
+void dwc_otg_hcd_dump_state(dwc_otg_hcd_t * hcd)
+{
+#ifdef DEBUG
+	int num_channels;
+	int i;
+	gnptxsts_data_t np_tx_status;
+	hptxsts_data_t p_tx_status;
+
+	num_channels = hcd->core_if->core_params->host_channels;
+	DWC_PRINTF("\n");
+	DWC_PRINTF
+	    ("************************************************************\n");
+	DWC_PRINTF("HCD State:\n");
+	DWC_PRINTF("  Num channels: %d\n", num_channels);
+	for (i = 0; i < num_channels; i++) {
+		dwc_hc_t *hc = hcd->hc_ptr_array[i];
+		DWC_PRINTF("  Channel %d:\n", i);
+		DWC_PRINTF("    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
+			   hc->dev_addr, hc->ep_num, hc->ep_is_in);
+		DWC_PRINTF("    speed: %d\n", hc->speed);
+		DWC_PRINTF("    ep_type: %d\n", hc->ep_type);
+		DWC_PRINTF("    max_packet: %d\n", hc->max_packet);
+		DWC_PRINTF("    data_pid_start: %d\n", hc->data_pid_start);
+		DWC_PRINTF("    multi_count: %d\n", hc->multi_count);
+		DWC_PRINTF("    xfer_started: %d\n", hc->xfer_started);
+		DWC_PRINTF("    xfer_buff: %p\n", hc->xfer_buff);
+		DWC_PRINTF("    xfer_len: %d\n", hc->xfer_len);
+		DWC_PRINTF("    xfer_count: %d\n", hc->xfer_count);
+		DWC_PRINTF("    halt_on_queue: %d\n", hc->halt_on_queue);
+		DWC_PRINTF("    halt_pending: %d\n", hc->halt_pending);
+		DWC_PRINTF("    halt_status: %d\n", hc->halt_status);
+		DWC_PRINTF("    do_split: %d\n", hc->do_split);
+		DWC_PRINTF("    complete_split: %d\n", hc->complete_split);
+		DWC_PRINTF("    hub_addr: %d\n", hc->hub_addr);
+		DWC_PRINTF("    port_addr: %d\n", hc->port_addr);
+		DWC_PRINTF("    xact_pos: %d\n", hc->xact_pos);
+		DWC_PRINTF("    requests: %d\n", hc->requests);
+		DWC_PRINTF("    qh: %p\n", hc->qh);
+		if (hc->xfer_started) {
+			hfnum_data_t hfnum;
+			hcchar_data_t hcchar;
+			hctsiz_data_t hctsiz;
+			hcint_data_t hcint;
+			hcintmsk_data_t hcintmsk;
+			hfnum.d32 =
+			    dwc_read_reg32(&hcd->core_if->host_if->
+					   host_global_regs->hfnum);
+			hcchar.d32 =
+			    dwc_read_reg32(&hcd->core_if->host_if->hc_regs[i]->
+					   hcchar);
+			hctsiz.d32 =
+			    dwc_read_reg32(&hcd->core_if->host_if->hc_regs[i]->
+					   hctsiz);
+			hcint.d32 =
+			    dwc_read_reg32(&hcd->core_if->host_if->hc_regs[i]->
+					   hcint);
+			hcintmsk.d32 =
+			    dwc_read_reg32(&hcd->core_if->host_if->hc_regs[i]->
+					   hcintmsk);
+			DWC_PRINTF("    hfnum: 0x%08x\n", hfnum.d32);
+			DWC_PRINTF("    hcchar: 0x%08x\n", hcchar.d32);
+			DWC_PRINTF("    hctsiz: 0x%08x\n", hctsiz.d32);
+			DWC_PRINTF("    hcint: 0x%08x\n", hcint.d32);
+			DWC_PRINTF("    hcintmsk: 0x%08x\n", hcintmsk.d32);
+		}
+		if (hc->xfer_started && hc->qh) {
+			dwc_otg_qtd_t *qtd;
+			dwc_otg_hcd_urb_t *urb;
+			
+			DWC_CIRCLEQ_FOREACH(qtd, &hc->qh->qtd_list, qtd_list_entry) {
+				if(!qtd->in_process)
+					break;
+				
+				urb = qtd->urb;
+			DWC_PRINTF("    URB Info:\n");
+			DWC_PRINTF("      qtd: %p, urb: %p\n", qtd, urb);
+			if (urb) {
+				DWC_PRINTF("      Dev: %d, EP: %d %s\n",
+					   dwc_otg_hcd_get_dev_addr(&urb->
+								    pipe_info),
+					   dwc_otg_hcd_get_ep_num(&urb->
+								  pipe_info),
+					   dwc_otg_hcd_is_pipe_in(&urb->
+								  pipe_info) ?
+					   "IN" : "OUT");
+				DWC_PRINTF("      Max packet size: %d\n",
+					   dwc_otg_hcd_get_mps(&urb->
+							       pipe_info));
+				DWC_PRINTF("      transfer_buffer: %p\n",
+					   urb->buf);
+				DWC_PRINTF("      transfer_dma: %p\n",
+					   (void *)urb->dma);
+				DWC_PRINTF("      transfer_buffer_length: %d\n",
+					   urb->length);
+				DWC_PRINTF("      actual_length: %d\n",
+					   urb->actual_length);
+			}
+		}
+	}
+	}
+	DWC_PRINTF("  non_periodic_channels: %d\n", hcd->non_periodic_channels);
+	DWC_PRINTF("  periodic_channels: %d\n", hcd->periodic_channels);
+	DWC_PRINTF("  periodic_usecs: %d\n", hcd->periodic_usecs);
+	np_tx_status.d32 =
+	    dwc_read_reg32(&hcd->core_if->core_global_regs->gnptxsts);
+	DWC_PRINTF("  NP Tx Req Queue Space Avail: %d\n",
+		   np_tx_status.b.nptxqspcavail);
+	DWC_PRINTF("  NP Tx FIFO Space Avail: %d\n",
+		   np_tx_status.b.nptxfspcavail);
+	p_tx_status.d32 =
+	    dwc_read_reg32(&hcd->core_if->host_if->host_global_regs->hptxsts);
+	DWC_PRINTF("  P Tx Req Queue Space Avail: %d\n",
+		   p_tx_status.b.ptxqspcavail);
+	DWC_PRINTF("  P Tx FIFO Space Avail: %d\n", p_tx_status.b.ptxfspcavail);
+	dwc_otg_hcd_dump_frrem(hcd);
+	dwc_otg_dump_global_registers(hcd->core_if);
+	dwc_otg_dump_host_registers(hcd->core_if);
+	DWC_PRINTF
+	    ("************************************************************\n");
+	DWC_PRINTF("\n");
+#endif
+}
+
+#ifdef DEBUG
+void dwc_print_setup_data(uint8_t * setup)
+{
+	int i;
+	if (CHK_DEBUG_LEVEL(DBG_HCD)) {
+		DWC_PRINTF("Setup Data = MSB ");
+		for (i = 7; i >= 0; i--)
+			DWC_PRINTF("%02x ", setup[i]);
+		DWC_PRINTF("\n");
+		DWC_PRINTF("  bmRequestType Tranfer = %s\n",
+			   (setup[0] & 0x80) ? "Device-to-Host" :
+			   "Host-to-Device");
+		DWC_PRINTF("  bmRequestType Type = ");
+		switch ((setup[0] & 0x60) >> 5) {
+		case 0:
+			DWC_PRINTF("Standard\n");
+			break;
+		case 1:
+			DWC_PRINTF("Class\n");
+			break;
+		case 2:
+			DWC_PRINTF("Vendor\n");
+			break;
+		case 3:
+			DWC_PRINTF("Reserved\n");
+			break;
+		}
+		DWC_PRINTF("  bmRequestType Recipient = ");
+		switch (setup[0] & 0x1f) {
+		case 0:
+			DWC_PRINTF("Device\n");
+			break;
+		case 1:
+			DWC_PRINTF("Interface\n");
+			break;
+		case 2:
+			DWC_PRINTF("Endpoint\n");
+			break;
+		case 3:
+			DWC_PRINTF("Other\n");
+			break;
+		default:
+			DWC_PRINTF("Reserved\n");
+			break;
+		}
+		DWC_PRINTF("  bRequest = 0x%0x\n", setup[1]);
+		DWC_PRINTF("  wValue = 0x%0x\n", *((uint16_t *) & setup[2]));
+		DWC_PRINTF("  wIndex = 0x%0x\n", *((uint16_t *) & setup[4]));
+		DWC_PRINTF("  wLength = 0x%0x\n\n", *((uint16_t *) & setup[6]));
+	}
+}
+#endif
+
+void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t * hcd)
+{
+#if 0
+	DWC_PRINTF("Frame remaining at SOF:\n");
+	DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
+		   hcd->frrem_samples, hcd->frrem_accum,
+		   (hcd->frrem_samples > 0) ?
+		   hcd->frrem_accum / hcd->frrem_samples : 0);
+
+	DWC_PRINTF("\n");
+	DWC_PRINTF("Frame remaining at start_transfer (uframe 7):\n");
+	DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
+		   hcd->core_if->hfnum_7_samples,
+		   hcd->core_if->hfnum_7_frrem_accum,
+		   (hcd->core_if->hfnum_7_samples >
+		    0) ? hcd->core_if->hfnum_7_frrem_accum /
+		   hcd->core_if->hfnum_7_samples : 0);
+	DWC_PRINTF("Frame remaining at start_transfer (uframe 0):\n");
+	DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
+		   hcd->core_if->hfnum_0_samples,
+		   hcd->core_if->hfnum_0_frrem_accum,
+		   (hcd->core_if->hfnum_0_samples >
+		    0) ? hcd->core_if->hfnum_0_frrem_accum /
+		   hcd->core_if->hfnum_0_samples : 0);
+	DWC_PRINTF("Frame remaining at start_transfer (uframe 1-6):\n");
+	DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
+		   hcd->core_if->hfnum_other_samples,
+		   hcd->core_if->hfnum_other_frrem_accum,
+		   (hcd->core_if->hfnum_other_samples >
+		    0) ? hcd->core_if->hfnum_other_frrem_accum /
+		   hcd->core_if->hfnum_other_samples : 0);
+
+	DWC_PRINTF("\n");
+	DWC_PRINTF("Frame remaining at sample point A (uframe 7):\n");
+	DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
+		   hcd->hfnum_7_samples_a, hcd->hfnum_7_frrem_accum_a,
+		   (hcd->hfnum_7_samples_a > 0) ?
+		   hcd->hfnum_7_frrem_accum_a / hcd->hfnum_7_samples_a : 0);
+	DWC_PRINTF("Frame remaining at sample point A (uframe 0):\n");
+	DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
+		   hcd->hfnum_0_samples_a, hcd->hfnum_0_frrem_accum_a,
+		   (hcd->hfnum_0_samples_a > 0) ?
+		   hcd->hfnum_0_frrem_accum_a / hcd->hfnum_0_samples_a : 0);
+	DWC_PRINTF("Frame remaining at sample point A (uframe 1-6):\n");
+	DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
+		   hcd->hfnum_other_samples_a, hcd->hfnum_other_frrem_accum_a,
+		   (hcd->hfnum_other_samples_a > 0) ?
+		   hcd->hfnum_other_frrem_accum_a /
+		   hcd->hfnum_other_samples_a : 0);
+
+	DWC_PRINTF("\n");
+	DWC_PRINTF("Frame remaining at sample point B (uframe 7):\n");
+	DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
+		   hcd->hfnum_7_samples_b, hcd->hfnum_7_frrem_accum_b,
+		   (hcd->hfnum_7_samples_b > 0) ?
+		   hcd->hfnum_7_frrem_accum_b / hcd->hfnum_7_samples_b : 0);
+	DWC_PRINTF("Frame remaining at sample point B (uframe 0):\n");
+	DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
+		   hcd->hfnum_0_samples_b, hcd->hfnum_0_frrem_accum_b,
+		   (hcd->hfnum_0_samples_b > 0) ?
+		   hcd->hfnum_0_frrem_accum_b / hcd->hfnum_0_samples_b : 0);
+	DWC_PRINTF("Frame remaining at sample point B (uframe 1-6):\n");
+	DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
+		   hcd->hfnum_other_samples_b, hcd->hfnum_other_frrem_accum_b,
+		   (hcd->hfnum_other_samples_b > 0) ?
+		   hcd->hfnum_other_frrem_accum_b /
+		   hcd->hfnum_other_samples_b : 0);
+#endif
+}
+
+#endif				/* DWC_DEVICE_ONLY */
diff --git a/drivers/usb/host/dwc_otg/dwc_otg_hcd.h b/drivers/usb/host/dwc_otg/dwc_otg_hcd.h
new file mode 100644
index 000000000000..9459c4ccff95
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd.h
@@ -0,0 +1,804 @@
+/* ==========================================================================
+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.h $
+ * $Revision: #52 $
+ * $Date: 2009/04/21 $
+ * $Change: 1237472 $
+ *
+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+ * otherwise expressly agreed to in writing between Synopsys and you.
+ *
+ * The Software IS NOT an item of Licensed Software or Licensed Product under
+ * any End User Software License Agreement or Agreement for Licensed Product
+ * with Synopsys or any supplement thereto. You are permitted to use and
+ * redistribute this Software in source and binary forms, with or without
+ * modification, provided that redistributions of source code must retain this
+ * notice. You may not view, use, disclose, copy or distribute this file or
+ * any information contained herein except pursuant to this license grant from
+ * Synopsys. If you do not agree with this notice, including the disclaimer
+ * below, then you are not authorized to use the Software.
+ *
+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ * ========================================================================== */
+#ifndef DWC_DEVICE_ONLY
+#ifndef __DWC_HCD_H__
+#define __DWC_HCD_H__
+
+#include <usb.h>
+#include "dwc_otg_hcd_if.h"
+#include "dwc_otg_core_if.h"
+#include "dwc_list.h"
+#include "dwc_otg_cil.h"
+
+/**
+ * @file
+ *
+ * This file contains the structures, constants, and interfaces for
+ * the Host Contoller Driver (HCD).
+ *
+ * The Host Controller Driver (HCD) is responsible for translating requests
+ * from the USB Driver into the appropriate actions on the DWC_otg controller.
+ * It isolates the USBD from the specifics of the controller by providing an
+ * API to the USBD.
+ */
+
+struct dwc_otg_hcd_pipe_info {
+	uint8_t dev_addr;
+	uint8_t ep_num;
+	uint8_t pipe_type;
+	uint8_t pipe_dir;
+	uint16_t mps;
+};
+
+struct dwc_otg_hcd_iso_packet_desc {
+	uint32_t offset;
+	uint32_t length;
+	uint32_t actual_length;
+	uint32_t status;
+};
+
+struct dwc_otg_qtd;
+
+struct dwc_otg_hcd_urb {
+	void *priv;
+	struct dwc_otg_qtd *qtd;
+	void *buf;
+	dwc_dma_t dma;
+	void *setup_packet;
+	dwc_dma_t setup_dma;
+	uint32_t length;
+	uint32_t actual_length;
+	uint32_t status;
+	uint32_t error_count;
+	uint32_t packet_count;
+	uint32_t flags;
+	uint16_t interval;
+	struct dwc_otg_hcd_pipe_info pipe_info;
+	struct dwc_otg_hcd_iso_packet_desc iso_descs[0];
+};
+
+static inline uint8_t dwc_otg_hcd_get_ep_num(struct dwc_otg_hcd_pipe_info *pipe)
+{
+	return pipe->ep_num;
+}
+
+static inline uint8_t dwc_otg_hcd_get_pipe_type(struct dwc_otg_hcd_pipe_info
+						*pipe)
+{
+	return pipe->pipe_type;
+}
+
+static inline uint16_t dwc_otg_hcd_get_mps(struct dwc_otg_hcd_pipe_info *pipe)
+{
+	return pipe->mps;
+}
+
+static inline uint8_t dwc_otg_hcd_get_dev_addr(struct dwc_otg_hcd_pipe_info
+					       *pipe)
+{
+	return pipe->dev_addr;
+}
+
+static inline uint8_t dwc_otg_hcd_is_pipe_isoc(struct dwc_otg_hcd_pipe_info
+					       *pipe)
+{
+	return (pipe->pipe_type == UE_ISOCHRONOUS);
+}
+
+static inline uint8_t dwc_otg_hcd_is_pipe_int(struct dwc_otg_hcd_pipe_info
+					      *pipe)
+{
+	return (pipe->pipe_type == UE_INTERRUPT);
+}
+
+static inline uint8_t dwc_otg_hcd_is_pipe_bulk(struct dwc_otg_hcd_pipe_info
+					       *pipe)
+{
+	return (pipe->pipe_type == UE_BULK);
+}
+
+static inline uint8_t dwc_otg_hcd_is_pipe_control(struct dwc_otg_hcd_pipe_info
+						  *pipe)
+{
+	return (pipe->pipe_type == UE_CONTROL);
+}
+
+static inline uint8_t dwc_otg_hcd_is_pipe_in(struct dwc_otg_hcd_pipe_info *pipe)
+{
+	return (pipe->pipe_dir == UE_DIR_IN);
+}
+
+static inline uint8_t dwc_otg_hcd_is_pipe_out(struct dwc_otg_hcd_pipe_info
+					      *pipe)
+{
+	return (!dwc_otg_hcd_is_pipe_in(pipe));
+}
+
+static inline void dwc_otg_hcd_fill_pipe(struct dwc_otg_hcd_pipe_info *pipe,
+					 uint8_t devaddr, uint8_t ep_num,
+					 uint8_t pipe_type, uint8_t pipe_dir,
+					 uint16_t mps)
+{
+	pipe->dev_addr = devaddr;
+	pipe->ep_num = ep_num;
+	pipe->pipe_type = pipe_type;
+	pipe->pipe_dir = pipe_dir;
+	pipe->mps = mps;
+}
+
+/**
+ * Phases for control transfers.
+ */
+typedef enum dwc_otg_control_phase {
+	DWC_OTG_CONTROL_SETUP,
+	DWC_OTG_CONTROL_DATA,
+	DWC_OTG_CONTROL_STATUS
+} dwc_otg_control_phase_e;
+
+/** Transaction types. */
+typedef enum dwc_otg_transaction_type {
+	DWC_OTG_TRANSACTION_NONE,
+	DWC_OTG_TRANSACTION_PERIODIC,
+	DWC_OTG_TRANSACTION_NON_PERIODIC,
+	DWC_OTG_TRANSACTION_ALL
+} dwc_otg_transaction_type_e;
+
+struct dwc_otg_qh;
+
+/**
+ * A Queue Transfer Descriptor (QTD) holds the state of a bulk, control,
+ * interrupt, or isochronous transfer. A single QTD is created for each URB
+ * (of one of these types) submitted to the HCD. The transfer associated with
+ * a QTD may require one or multiple transactions.
+ *
+ * A QTD is linked to a Queue Head, which is entered in either the
+ * non-periodic or periodic schedule for execution. When a QTD is chosen for
+ * execution, some or all of its transactions may be executed. After
+ * execution, the state of the QTD is updated. The QTD may be retired if all
+ * its transactions are complete or if an error occurred. Otherwise, it
+ * remains in the schedule so more transactions can be executed later.
+ */
+typedef struct dwc_otg_qtd {
+	/**
+	 * Determines the PID of the next data packet for the data phase of
+	 * control transfers. Ignored for other transfer types.<br>
+	 * One of the following values:
+	 *	- DWC_OTG_HC_PID_DATA0
+	 *	- DWC_OTG_HC_PID_DATA1
+	 */
+	uint8_t data_toggle;
+
+	/** Current phase for control transfers (Setup, Data, or Status). */
+	dwc_otg_control_phase_e control_phase;
+
+	/** Keep track of the current split type
+	 * for FS/LS endpoints on a HS Hub */
+	uint8_t complete_split;
+
+	/** How many bytes transferred during SSPLIT OUT */
+	uint32_t ssplit_out_xfer_count;
+
+	/**
+	 * Holds the number of bus errors that have occurred for a transaction
+	 * within this transfer.
+	 */
+	uint8_t error_count;
+
+	/**
+	 * Index of the next frame descriptor for an isochronous transfer. A
+	 * frame descriptor describes the buffer position and length of the
+	 * data to be transferred in the next scheduled (micro)frame of an
+	 * isochronous transfer. It also holds status for that transaction.
+	 * The frame index starts at 0.
+	 */
+	uint16_t isoc_frame_index;
+
+	/** Position of the ISOC split on full/low speed */
+	uint8_t isoc_split_pos;
+
+	/** Position of the ISOC split in the buffer for the current frame */
+	uint16_t isoc_split_offset;
+
+	/** URB for this transfer */
+	struct dwc_otg_hcd_urb *urb;
+
+	struct dwc_otg_qh *qh;
+
+	/** This list of QTDs */
+	 DWC_CIRCLEQ_ENTRY(dwc_otg_qtd) qtd_list_entry;
+
+	/** Indicates if this QTD is currently processed by HW. */
+	uint8_t	in_process;
+
+	/** Number of DMA descriptors for this QTD */
+	uint8_t	n_desc;
+	
+	/** 
+	 * Last activated frame(packet) index. 
+	 * Used in Descriptor DMA mode only.
+	 */
+	uint16_t isoc_frame_index_last;
+	
+} dwc_otg_qtd_t;
+
+DWC_CIRCLEQ_HEAD(dwc_otg_qtd_list, dwc_otg_qtd);
+
+/**
+ * A Queue Head (QH) holds the static characteristics of an endpoint and
+ * maintains a list of transfers (QTDs) for that endpoint. A QH structure may
+ * be entered in either the non-periodic or periodic schedule.
+ */
+typedef struct dwc_otg_qh {
+	/**
+	 * Endpoint type.
+	 * One of the following values:
+	 *	- UE_CONTROL
+	 *	- UE_BULK
+	 *	- UE_INTERRUPT
+	 *	- UE_ISOCHRONOUS
+	 */
+	uint8_t ep_type;
+	uint8_t ep_is_in;
+
+	/** wMaxPacketSize Field of Endpoint Descriptor. */
+	uint16_t maxp;
+
+	/**
+	 * Device speed.
+	 * One of the following values:
+	 *	- DWC_OTG_EP_SPEED_LOW
+	 *	- DWC_OTG_EP_SPEED_FULL
+	 *	- DWC_OTG_EP_SPEED_HIGH
+	 */
+	uint8_t dev_speed;
+
+	/**
+	 * Determines the PID of the next data packet for non-control
+	 * transfers. Ignored for control transfers.<br>
+	 * One of the following values:
+	 *	- DWC_OTG_HC_PID_DATA0
+	 *	- DWC_OTG_HC_PID_DATA1
+	 */
+	uint8_t data_toggle;
+
+	/** Ping state if 1. */
+	uint8_t ping_state;
+
+	/**
+	 * List of QTDs for this QH.
+	 */
+	struct dwc_otg_qtd_list qtd_list;
+
+	/** Host channel currently processing transfers for this QH. */
+	struct dwc_hc *channel;
+
+	/** Full/low speed endpoint on high-speed hub requires split. */
+	uint8_t do_split;
+
+	/** @name Periodic schedule information */
+	/** @{ */
+
+	/** Bandwidth in microseconds per (micro)frame. */
+	uint16_t usecs;
+
+	/** Interval between transfers in (micro)frames. */
+	uint16_t interval;
+
+	/**
+	 * (micro)frame to initialize a periodic transfer. The transfer
+	 * executes in the following (micro)frame.
+	 */
+	uint16_t sched_frame;
+
+	/** (micro)frame at which last start split was initialized. */
+	uint16_t start_split_frame;
+
+	/** @} */
+
+	/** 
+	 * Used instead of original buffer if 
+	 * it(physical address) is not dword-aligned.
+	 */
+	uint8_t *dw_align_buf;
+	dwc_dma_t dw_align_buf_dma;
+	
+	/** Entry for QH in either the periodic or non-periodic schedule. */
+	dwc_list_link_t qh_list_entry;
+	
+	/** @name Descriptor DMA support */
+	/** @{ */
+	
+	/** Descriptor List. */
+	dwc_otg_host_dma_desc_t	*desc_list;
+	
+	/** Descriptor List physical address. */
+	dwc_dma_t desc_list_dma;
+	
+	/** 
+	 * Xfer Bytes array.
+	 * Each element corresponds to a descriptor and indicates 
+	 * original XferSize size value for the descriptor.
+	 */
+	uint32_t *n_bytes;
+	
+	/** Actual number of transfer descriptors in a list. */
+	uint16_t ntd;
+	
+	/** First activated isochronous transfer descriptor index. */
+	uint8_t td_first;
+	/** Last activated isochronous transfer descriptor index. */
+	uint8_t td_last;
+	
+	/** @} */
+	
+} dwc_otg_qh_t;
+
+DWC_CIRCLEQ_HEAD(hc_list, dwc_hc);
+
+#ifdef HW2937_WORKAROUND
+
+typedef enum {
+	HW2937_XFER_MODE_IDLE,
+	HW2937_XFER_MODE_IN,
+	HW2937_XFER_MODE_OUT,
+	HW2937_XFER_MODE_PAUSEIN /* Transitioning from IN to IDLE */
+} hw2937_xfer_mode_t;
+#endif
+
+/**
+ * This structure holds the state of the HCD, including the non-periodic and
+ * periodic schedules.
+ */
+struct dwc_otg_hcd {
+	/** DWC OTG Core Interface Layer */
+	dwc_otg_core_if_t *core_if;
+
+	/** Function HCD driver callbacks */
+	struct dwc_otg_hcd_function_ops *fops;
+
+	/** Internal DWC HCD Flags */
+	volatile union dwc_otg_hcd_internal_flags {
+		uint32_t d32;
+		struct {
+			unsigned port_connect_status_change:1;
+			unsigned port_connect_status:1;
+			unsigned port_reset_change:1;
+			unsigned port_enable_change:1;
+			unsigned port_suspend_change:1;
+			unsigned port_over_current_change:1;
+			unsigned port_l1_change:1;
+			unsigned reserved:26;
+		} b;
+	} flags;
+
+	/**
+	 * Inactive items in the non-periodic schedule. This is a list of
+	 * Queue Heads. Transfers associated with these Queue Heads are not
+	 * currently assigned to a host channel.
+	 */
+	dwc_list_link_t non_periodic_sched_inactive;
+
+	/**
+	 * Active items in the non-periodic schedule. This is a list of
+	 * Queue Heads. Transfers associated with these Queue Heads are
+	 * currently assigned to a host channel.
+	 */
+	dwc_list_link_t non_periodic_sched_active;
+
+	/**
+	 * Pointer to the next Queue Head to process in the active
+	 * non-periodic schedule.
+	 */
+	dwc_list_link_t *non_periodic_qh_ptr;
+
+	/**
+	 * Inactive items in the periodic schedule. This is a list of QHs for
+	 * periodic transfers that are _not_ scheduled for the next frame.
+	 * Each QH in the list has an interval counter that determines when it
+	 * needs to be scheduled for execution. This scheduling mechanism
+	 * allows only a simple calculation for periodic bandwidth used (i.e.
+	 * must assume that all periodic transfers may need to execute in the
+	 * same frame). However, it greatly simplifies scheduling and should
+	 * be sufficient for the vast majority of OTG hosts, which need to
+	 * connect to a small number of peripherals at one time.
+	 *
+	 * Items move from this list to periodic_sched_ready when the QH
+	 * interval counter is 0 at SOF.
+	 */
+	dwc_list_link_t periodic_sched_inactive;
+
+	/**
+	 * List of periodic QHs that are ready for execution in the next
+	 * frame, but have not yet been assigned to host channels.
+	 *
+	 * Items move from this list to periodic_sched_assigned as host
+	 * channels become available during the current frame.
+	 */
+	dwc_list_link_t periodic_sched_ready;
+
+	/**
+	 * List of periodic QHs to be executed in the next frame that are
+	 * assigned to host channels.
+	 *
+	 * Items move from this list to periodic_sched_queued as the
+	 * transactions for the QH are queued to the DWC_otg controller.
+	 */
+	dwc_list_link_t periodic_sched_assigned;
+
+	/**
+	 * List of periodic QHs that have been queued for execution.
+	 *
+	 * Items move from this list to either periodic_sched_inactive or
+	 * periodic_sched_ready when the channel associated with the transfer
+	 * is released. If the interval for the QH is 1, the item moves to
+	 * periodic_sched_ready because it must be rescheduled for the next
+	 * frame. Otherwise, the item moves to periodic_sched_inactive.
+	 */
+	dwc_list_link_t periodic_sched_queued;
+
+	/**
+	 * Total bandwidth claimed so far for periodic transfers. This value
+	 * is in microseconds per (micro)frame. The assumption is that all
+	 * periodic transfers may occur in the same (micro)frame.
+	 */
+	uint16_t periodic_usecs;
+
+	/**
+	 * Frame number read from the core at SOF. The value ranges from 0 to
+	 * DWC_HFNUM_MAX_FRNUM.
+	 */
+	uint16_t frame_number;
+
+	/**
+	 * Free host channels in the controller. This is a list of
+	 * dwc_hc_t items.
+	 */
+	struct hc_list free_hc_list;
+	/**
+	 * Number of host channels assigned to periodic transfers. Currently
+	 * assuming that there is a dedicated host channel for each periodic
+	 * transaction and at least one host channel available for
+	 * non-periodic transactions.
+	 */
+	int periodic_channels;
+
+	/**
+	 * Number of host channels assigned to non-periodic transfers.
+	 */
+	int non_periodic_channels;
+
+	/**
+	 * Array of pointers to the host channel descriptors. Allows accessing
+	 * a host channel descriptor given the host channel number. This is
+	 * useful in interrupt handlers.
+	 */
+	struct dwc_hc *hc_ptr_array[MAX_EPS_CHANNELS];
+
+	/**
+	 * Buffer to use for any data received during the status phase of a
+	 * control transfer. Normally no data is transferred during the status
+	 * phase. This buffer is used as a bit bucket.
+	 */
+	uint8_t *status_buf;
+
+	/**
+	 * DMA address for status_buf.
+	 */
+	dma_addr_t status_buf_dma;
+#define DWC_OTG_HCD_STATUS_BUF_SIZE 64
+
+	/**
+	 * Connection timer. An OTG host must display a message if the device
+	 * does not connect. Started when the VBus power is turned on via
+	 * sysfs attribute "buspower".
+	 */
+	dwc_timer_t *conn_timer;
+
+	/* Tasket to do a reset */
+	dwc_tasklet_t *reset_tasklet;
+
+	/*  */
+	dwc_spinlock_t *lock;
+
+	/**
+	 * Private data that could be used by OS wrapper.
+	 */
+	void *priv;
+
+	uint8_t otg_port;
+
+	/** Frame List */
+	uint32_t *frame_list;
+
+	/** Frame List DMA address */
+	dma_addr_t frame_list_dma;
+
+#ifdef HW2937_WORKAROUND
+	/** Current transfer mode (IN, OUT, or IDLE) */
+	hw2937_xfer_mode_t hw2937_xfer_mode;
+
+	/** Mask of channels assigned to the current mode */
+	uint32_t hw2937_assigned_channels;
+#endif
+
+#ifdef DEBUG
+	uint32_t frrem_samples;
+	uint64_t frrem_accum;
+
+	uint32_t hfnum_7_samples_a;
+	uint64_t hfnum_7_frrem_accum_a;
+	uint32_t hfnum_0_samples_a;
+	uint64_t hfnum_0_frrem_accum_a;
+	uint32_t hfnum_other_samples_a;
+	uint64_t hfnum_other_frrem_accum_a;
+
+	uint32_t hfnum_7_samples_b;
+	uint64_t hfnum_7_frrem_accum_b;
+	uint32_t hfnum_0_samples_b;
+	uint64_t hfnum_0_frrem_accum_b;
+	uint32_t hfnum_other_samples_b;
+	uint64_t hfnum_other_frrem_accum_b;
+#endif
+};
+
+/** @name Transaction Execution Functions */
+/** @{ */
+extern dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t
+								  * hcd);
+extern void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t * hcd,
+				    dwc_otg_transaction_type_e tr_type);
+
+/** @} */
+
+/** @name Interrupt Handler Functions */
+/** @{ */
+extern int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd);
+extern int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * dwc_otg_hcd);
+extern int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t *
+							 dwc_otg_hcd);
+extern int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t *
+							dwc_otg_hcd);
+extern int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t *
+							   dwc_otg_hcd);
+extern int32_t dwc_otg_hcd_handle_incomplete_periodic_intr(dwc_otg_hcd_t *
+							   dwc_otg_hcd);
+extern int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t * dwc_otg_hcd);
+extern int32_t dwc_otg_hcd_handle_conn_id_status_change_intr(dwc_otg_hcd_t *
+							     dwc_otg_hcd);
+extern int32_t dwc_otg_hcd_handle_disconnect_intr(dwc_otg_hcd_t * dwc_otg_hcd);
+extern int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t * dwc_otg_hcd);
+extern int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t * dwc_otg_hcd,
+					    uint32_t num);
+extern int32_t dwc_otg_hcd_handle_session_req_intr(dwc_otg_hcd_t * dwc_otg_hcd);
+extern int32_t dwc_otg_hcd_handle_wakeup_detected_intr(dwc_otg_hcd_t *
+						       dwc_otg_hcd);
+/** @} */
+
+/** @name Schedule Queue Functions */
+/** @{ */
+
+/* Implemented in dwc_otg_hcd_queue.c */
+extern dwc_otg_qh_t *dwc_otg_hcd_qh_create(dwc_otg_hcd_t * hcd,
+					   dwc_otg_hcd_urb_t * urb);
+extern void dwc_otg_hcd_qh_free(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
+extern int dwc_otg_hcd_qh_add(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
+extern void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
+extern void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh,
+				      int sched_csplit);
+
+/** Remove and free a QH */
+static inline void dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd_t * hcd,
+						  dwc_otg_qh_t * qh)
+{
+	dwc_otg_hcd_qh_remove(hcd, qh);
+	dwc_otg_hcd_qh_free(hcd, qh);
+}
+
+/** Allocates memory for a QH structure.
+ * @return Returns the memory allocate or NULL on error. */
+static inline dwc_otg_qh_t *dwc_otg_hcd_qh_alloc(void)
+{
+	return (dwc_otg_qh_t *) dwc_alloc(sizeof(dwc_otg_qh_t));
+}
+
+extern dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(dwc_otg_hcd_urb_t * urb);
+extern void dwc_otg_hcd_qtd_init(dwc_otg_qtd_t * qtd, dwc_otg_hcd_urb_t * urb);
+extern int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * qtd, dwc_otg_hcd_t * dwc_otg_hcd,
+			       dwc_otg_qh_t ** qh);
+
+/** Allocates memory for a QTD structure.
+ * @return Returns the memory allocate or NULL on error. */
+static inline dwc_otg_qtd_t *dwc_otg_hcd_qtd_alloc(void)
+{
+	return (dwc_otg_qtd_t *) dwc_alloc(sizeof(dwc_otg_qtd_t));
+}
+
+/** Frees the memory for a QTD structure.  QTD should already be removed from
+ * list.
+ * @param qtd QTD to free.*/
+static inline void dwc_otg_hcd_qtd_free(dwc_otg_qtd_t * qtd)
+{
+	dwc_free(qtd);
+}
+
+/** Removes a QTD from list.
+ * @param hcd HCD instance.
+ * @param qtd QTD to remove from list.
+ * @param qh QTD belongs to.
+ */
+static inline void dwc_otg_hcd_qtd_remove(dwc_otg_hcd_t * hcd,
+					  dwc_otg_qtd_t * qtd,
+					  dwc_otg_qh_t * qh)
+{
+	uint64_t flags;
+	DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
+	DWC_CIRCLEQ_REMOVE(&qh->qtd_list, qtd, qtd_list_entry);
+	DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
+}
+
+/** Remove and free a QTD */
+static inline void dwc_otg_hcd_qtd_remove_and_free(dwc_otg_hcd_t * hcd,
+						   dwc_otg_qtd_t * qtd,
+						   dwc_otg_qh_t * qh)
+{
+	dwc_otg_hcd_qtd_remove(hcd, qtd, qh);
+	dwc_otg_hcd_qtd_free(qtd);
+}
+
+/** @} */
+
+/** @name Descriptor DMA Supporting Functions */
+/** @{ */
+
+extern void dwc_otg_hcd_start_xfer_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
+extern void dwc_otg_hcd_complete_xfer_ddma(dwc_otg_hcd_t * hcd,
+				    	   dwc_hc_t * hc,
+				    	   dwc_otg_hc_regs_t * hc_regs,
+				    	   dwc_otg_halt_status_e halt_status);
+
+extern int dwc_otg_hcd_qh_init_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
+extern void dwc_otg_hcd_qh_free_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
+
+/** @} */
+		
+/** @name Internal Functions */
+/** @{ */
+dwc_otg_qh_t *dwc_urb_to_qh(dwc_otg_hcd_urb_t * urb);
+/** @} */
+
+#ifdef CONFIG_USB_DWC_OTG_LPM
+extern int dwc_otg_hcd_get_hc_for_lpm_tran(dwc_otg_hcd_t * hcd,
+					   uint8_t devaddr);
+extern void dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd_t * hcd);
+#endif
+
+/** Gets the QH that contains the list_head */
+#define dwc_list_to_qh(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qh_t, qh_list_entry)
+
+/** Gets the QTD that contains the list_head */
+#define dwc_list_to_qtd(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qtd_t, qtd_list_entry)
+
+/** Check if QH is non-periodic  */
+#define dwc_qh_is_non_per(_qh_ptr_) ((_qh_ptr_->ep_type == UE_BULK) || \
+				     (_qh_ptr_->ep_type == UE_CONTROL))
+
+/** High bandwidth multiplier as encoded in highspeed endpoint descriptors */
+#define dwc_hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03))
+
+/** Packet size for any kind of endpoint descriptor */
+#define dwc_max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
+
+/**
+ * Returns true if _frame1 is less than or equal to _frame2. The comparison is
+ * done modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the
+ * frame number when the max frame number is reached.
+ */
+static inline int dwc_frame_num_le(uint16_t frame1, uint16_t frame2)
+{
+	return ((frame2 - frame1) & DWC_HFNUM_MAX_FRNUM) <=
+	    (DWC_HFNUM_MAX_FRNUM >> 1);
+}
+
+/**
+ * Returns true if _frame1 is greater than _frame2. The comparison is done
+ * modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the frame
+ * number when the max frame number is reached.
+ */
+static inline int dwc_frame_num_gt(uint16_t frame1, uint16_t frame2)
+{
+	return (frame1 != frame2) &&
+	    (((frame1 - frame2) & DWC_HFNUM_MAX_FRNUM) <
+	     (DWC_HFNUM_MAX_FRNUM >> 1));
+}
+
+/**
+ * Increments _frame by the amount specified by _inc. The addition is done
+ * modulo DWC_HFNUM_MAX_FRNUM. Returns the incremented value.
+ */
+static inline uint16_t dwc_frame_num_inc(uint16_t frame, uint16_t inc)
+{
+	return (frame + inc) & DWC_HFNUM_MAX_FRNUM;
+}
+
+static inline uint16_t dwc_full_frame_num(uint16_t frame)
+{
+	return (frame & DWC_HFNUM_MAX_FRNUM) >> 3;
+}
+
+static inline uint16_t dwc_micro_frame_num(uint16_t frame)
+{
+	return frame & 0x7;
+}
+
+void dwc_otg_hcd_save_data_toggle(dwc_hc_t * hc,
+			     	  dwc_otg_hc_regs_t * hc_regs, 
+			     	  dwc_otg_qtd_t * qtd);
+
+#ifdef DEBUG
+/**
+ * Macro to sample the remaining PHY clocks left in the current frame. This
+ * may be used during debugging to determine the average time it takes to
+ * execute sections of code. There are two possible sample points, "a" and
+ * "b", so the _letter argument must be one of these values.
+ *
+ * To dump the average sample times, read the "hcd_frrem" sysfs attribute. For
+ * example, "cat /sys/devices/lm0/hcd_frrem".
+ */
+#define dwc_sample_frrem(_hcd, _qh, _letter) \
+{ \
+	hfnum_data_t hfnum; \
+	dwc_otg_qtd_t *qtd; \
+	qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); \
+	if (usb_pipeint(qtd->urb->pipe) && _qh->start_split_frame != 0 && !qtd->complete_split) { \
+		hfnum.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hfnum); \
+		switch (hfnum.b.frnum & 0x7) { \
+		case 7: \
+			_hcd->hfnum_7_samples_##_letter++; \
+			_hcd->hfnum_7_frrem_accum_##_letter += hfnum.b.frrem; \
+			break; \
+		case 0: \
+			_hcd->hfnum_0_samples_##_letter++; \
+			_hcd->hfnum_0_frrem_accum_##_letter += hfnum.b.frrem; \
+			break; \
+		default: \
+			_hcd->hfnum_other_samples_##_letter++; \
+			_hcd->hfnum_other_frrem_accum_##_letter += hfnum.b.frrem; \
+			break; \
+		} \
+	} \
+}
+#else
+#define dwc_sample_frrem(_hcd, _qh, _letter)
+#endif
+#endif
+#endif				/* DWC_DEVICE_ONLY */
diff --git a/drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c b/drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c
new file mode 100644
index 000000000000..21d1ab13a126
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c
@@ -0,0 +1,1106 @@
+/*==========================================================================
+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_ddma.c $
+ * $Revision: #2 $
+ * $Date: 2009/04/21 $
+ * $Change: 1237473 $
+ *
+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+ * otherwise expressly agreed to in writing between Synopsys and you.
+ *
+ * The Software IS NOT an item of Licensed Software or Licensed Product under
+ * any End User Software License Agreement or Agreement for Licensed Product
+ * with Synopsys or any supplement thereto. You are permitted to use and
+ * redistribute this Software in source and binary forms, with or without
+ * modification, provided that redistributions of source code must retain this
+ * notice. You may not view, use, disclose, copy or distribute this file or
+ * any information contained herein except pursuant to this license grant from
+ * Synopsys. If you do not agree with this notice, including the disclaimer
+ * below, then you are not authorized to use the Software.
+ *
+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ * ========================================================================== */
+#ifndef DWC_DEVICE_ONLY
+
+/** @file
+ * This file contains Descriptor DMA support implementation for host mode.
+ */
+ 
+#include "dwc_otg_hcd.h"
+#include "dwc_otg_regs.h"
+		
+		
+static inline uint8_t frame_list_idx(uint16_t frame)
+{
+	return (frame & (MAX_FRLIST_EN_NUM - 1));
+}
+
+static inline uint16_t desclist_idx_inc(uint16_t idx, uint16_t inc, uint8_t speed)
+{
+	return (idx + inc) & 
+		(((speed == DWC_OTG_EP_SPEED_HIGH) ? MAX_DMA_DESC_NUM_HS_ISOC : MAX_DMA_DESC_NUM_GENERIC) - 1);
+}
+
+static inline uint16_t desclist_idx_dec(uint16_t idx, uint16_t inc, uint8_t speed)
+{
+	return (idx - inc) & 
+		(((speed == DWC_OTG_EP_SPEED_HIGH) ? MAX_DMA_DESC_NUM_HS_ISOC : MAX_DMA_DESC_NUM_GENERIC) - 1);
+}
+
+static inline uint16_t max_desc_num(dwc_otg_qh_t * qh)
+{
+	return (((qh->ep_type == UE_ISOCHRONOUS) && (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH)) 
+							?
+							MAX_DMA_DESC_NUM_HS_ISOC
+							:
+							MAX_DMA_DESC_NUM_GENERIC);
+}
+static inline uint16_t frame_incr_val(dwc_otg_qh_t * qh)
+{
+	return ((qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) 
+						? ((qh->interval + 8 - 1) / 8)
+						:
+						qh->interval);
+}
+
+static int desc_list_alloc(dwc_otg_qh_t * qh)
+{
+	int retval = 0;
+	
+	qh->desc_list = (dwc_otg_host_dma_desc_t *) 
+				dwc_dma_alloc(sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh),
+				  	      &qh->desc_list_dma
+					      );
+	
+	if (!qh->desc_list) {
+		retval = -DWC_E_NO_MEMORY;
+		DWC_ERROR("%s: DMA descriptor list allocation failed\n", __func__);
+		
+	}
+	
+	dwc_memset(qh->desc_list, 0x00, sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh));
+	 
+
+	qh->n_bytes = (uint32_t *) dwc_alloc(sizeof(uint32_t) * max_desc_num(qh));
+	
+	if (!qh->n_bytes) {
+		retval = -DWC_E_NO_MEMORY;
+		DWC_ERROR("%s: Failed to allocate array for descriptors' size actual values\n",
+			  __func__);
+		
+	}	
+	return retval;
+
+}
+
+static void desc_list_free(dwc_otg_qh_t * qh)
+{
+	if(qh->desc_list) {
+		dwc_dma_free(max_desc_num(qh), qh->desc_list, qh->desc_list_dma);
+		qh->desc_list = NULL;
+	}
+	
+	if (qh->n_bytes) {
+		dwc_free(qh->n_bytes);
+		qh->n_bytes = NULL;
+	}
+}
+
+static int frame_list_alloc(dwc_otg_hcd_t * hcd)
+{
+	int retval = 0;	
+	if (hcd->frame_list)
+		return 0;
+	
+	hcd->frame_list = dwc_dma_alloc(4 * MAX_FRLIST_EN_NUM,
+					&hcd->frame_list_dma
+					);
+	if (!hcd->frame_list) {
+		retval = -DWC_E_NO_MEMORY;
+		DWC_ERROR("%s: Frame List allocation failed\n", __func__);
+	}
+	
+	dwc_memset(hcd->frame_list, 0x00, 4 * MAX_FRLIST_EN_NUM);
+	
+	return retval;
+}
+
+static void frame_list_free(dwc_otg_hcd_t * hcd)
+{
+	if (!hcd->frame_list)
+		return;
+	
+	dwc_dma_free(4 * MAX_FRLIST_EN_NUM, hcd->frame_list, hcd->frame_list_dma);
+	hcd->frame_list = NULL;
+}
+
+static void per_sched_enable(dwc_otg_hcd_t * hcd, uint16_t fr_list_en)
+{
+		
+	hcfg_data_t hcfg;
+
+	hcfg.d32 = dwc_read_reg32(&hcd->core_if->host_if->host_global_regs->hcfg);
+
+	if (hcfg.b.perschedstat) {
+		/* already enabled*/	
+		return;
+	}
+	
+	dwc_write_reg32(&hcd->core_if->host_if->host_global_regs->hflbaddr, hcd->frame_list_dma);
+	
+	switch(fr_list_en) {
+	case 64:
+	    hcfg.b.frlisten = 3;
+    	    break;
+	case 32:
+	    hcfg.b.frlisten = 2;
+	    break;
+	case 16:
+	    hcfg.b.frlisten = 1;    
+  	case 8:
+	    hcfg.b.frlisten = 0;
+  	default:
+	    break;        
+	}
+	
+	hcfg.b.perschedena = 1;
+
+	DWC_DEBUGPL(DBG_HCD, "Enabling Periodic schedule\n");
+	dwc_write_reg32(&hcd->core_if->host_if->host_global_regs->hcfg, hcfg.d32);
+
+}
+ 
+static void per_sched_disable(dwc_otg_hcd_t * hcd)
+{
+	hcfg_data_t hcfg;
+
+	hcfg.d32 = dwc_read_reg32(&hcd->core_if->host_if->host_global_regs->hcfg);
+	
+	if (!hcfg.b.perschedstat) {
+		/* already disabled */	
+		return;
+	}
+	hcfg.b.perschedena = 0;
+	
+	DWC_DEBUGPL(DBG_HCD, "Disabling Periodic schedule\n");
+	dwc_write_reg32(&hcd->core_if->host_if->host_global_regs->hcfg, hcfg.d32);
+}
+
+/* 
+ * Activates/Deactivates FrameList entries for the channel 
+ * based on endpoint servicing period.
+ */
+void update_frame_list(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, uint8_t enable)
+{
+	uint16_t i, j, inc;
+	dwc_hc_t *hc = qh->channel;
+	
+	inc = frame_incr_val(qh);
+	
+	if (qh->ep_type == UE_ISOCHRONOUS)
+		i = frame_list_idx(qh->sched_frame);
+	else
+		i = 0;
+
+	j = i;
+	do {
+		if (enable)
+			hcd->frame_list[j] |= (1 << hc->hc_num);
+		else
+			hcd->frame_list[j] &= ~(1 << hc->hc_num);
+		j = (j + inc) & (MAX_FRLIST_EN_NUM - 1);
+	}
+	while (j != i);
+	
+	if (!enable)
+		return;
+	
+	hc->schinfo = 0;
+	if (qh->channel->speed == DWC_OTG_EP_SPEED_HIGH) {
+		j = 1;
+		for (i = 0 ; i < 8 / qh->interval; i++) {
+			hc->schinfo |= j;
+			j = j << qh->interval;
+		}
+	}
+	else {
+		hc->schinfo = 0xff;
+	}	
+}		
+#if 1
+void dump_frame_list(dwc_otg_hcd_t * hcd)
+{
+	int i = 0;
+	DWC_PRINTF("--FRAME LIST (hex) --\n");		
+	for (i = 0; i < MAX_FRLIST_EN_NUM; i++) {
+    		DWC_PRINTF("%x\t",hcd->frame_list[i]);
+		if (!(i % 8) && i)    
+			DWC_PRINTF("\n");
+	}
+	DWC_PRINTF("\n----\n");
+
+}
+#endif
+
+static void release_channel_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
+{
+	dwc_hc_t *hc = qh->channel;
+	if (dwc_qh_is_non_per(qh)) {
+		hcd->non_periodic_channels--;			
+	}
+	else {
+		update_frame_list(hcd, qh, 0);
+	}
+	/* 
+	 * The condition is added to prevent double cleanup try in case of device
+	 * disconnect. See channel cleanup in dwc_otg_hcd_disconnect_cb().
+	 */
+	if (hc->qh) {	
+		dwc_otg_hc_cleanup(hcd->core_if, hc);
+		DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
+		hc->qh = NULL;
+	}
+	
+	qh->channel = NULL;
+	qh->ntd = 0;
+	
+	if (qh->desc_list) {
+		dwc_memset(qh->desc_list, 0x00, 
+			    sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh));
+	}
+}
+
+/** 
+ * Initializes a QH structure's Descriptor DMA related members.
+ * Allocates memory for descriptor list.
+ * On first periodic QH, allocates memory for FrameList 
+ * and enables periodic scheduling.
+ *
+ * @param hcd The HCD state structure for the DWC OTG controller.
+ * @param qh The QH to init.
+ *
+ * @return 0 if successful, negative error code otherwise.
+ */		
+int dwc_otg_hcd_qh_init_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
+{
+	int retval = 0;
+	
+    	if (qh->do_split) {
+		DWC_ERROR("SPLIT Transfers are not supported in Descriptor DMA.\n");
+    		return -1;
+    	}
+
+	retval = desc_list_alloc(qh);
+	
+	if ((retval == 0) && (qh->ep_type == UE_ISOCHRONOUS || qh->ep_type == UE_INTERRUPT)) {
+		if(!hcd->frame_list) {
+			retval = frame_list_alloc(hcd);	
+			/* Enable periodic schedule on first periodic QH */
+			if (retval == 0)		
+				per_sched_enable(hcd, MAX_FRLIST_EN_NUM);
+		}
+	}
+	
+	qh->ntd = 0;
+	
+	return retval;
+}
+
+/** 
+ * Frees descriptor list memory associated with the QH. 
+ * If QH is periodic and the last, frees FrameList memory 
+ * and disables periodic scheduling. 
+ *
+ * @param hcd The HCD state structure for the DWC OTG controller.
+ * @param qh The QH to init.
+ */
+void dwc_otg_hcd_qh_free_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
+{
+	desc_list_free(qh);
+
+	/* 
+	 * Channel still assigned due to some reasons. 
+	 * Seen on Isoc URB dequeue. Channel halted but no subsequent
+	 * ChHalted interrupt to release the channel. Afterwards
+	 * when it comes here from endpoint disable routine
+	 * channel remains assigned.
+	 */
+	if (qh->channel)
+		release_channel_ddma(hcd, qh);
+
+	if ((qh->ep_type == UE_ISOCHRONOUS || qh->ep_type == UE_INTERRUPT) 
+			&& !hcd->periodic_channels && hcd->frame_list) {
+		
+		per_sched_disable(hcd);	
+		frame_list_free(hcd);	
+	}
+}	
+
+static uint8_t frame_to_desc_idx(dwc_otg_qh_t * qh, uint16_t frame_idx)
+{
+	if (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) {
+		/* 
+		 * Descriptor set(8 descriptors) index
+		 * which is 8-aligned.
+		 */	
+		return (frame_idx & ((MAX_DMA_DESC_NUM_HS_ISOC / 8) - 1)) * 8;
+ 	}
+	else {
+		return (frame_idx & (MAX_DMA_DESC_NUM_GENERIC - 1));
+	}	
+}
+
+/* 
+ * Determine starting frame for Isochronous transfer. 
+ * Few frames skipped to prevent race condition with HC. 
+ */
+static uint8_t calc_starting_frame(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, uint8_t* skip_frames)
+{
+	uint16_t frame = 0;
+	hcd->frame_number = dwc_otg_hcd_get_frame_number(hcd);
+	
+	/* sched_frame is always frame number(not uFrame) both in FS and HS !! */
+	
+	/* 
+	 * skip_frames is used to limit activated descriptors number
+	 * to avoid the situation when HC services the last activated
+	 * descriptor firstly.
+	 * Example for FS:
+	 * Current frame is 1, scheduled frame is 3. Since HC always fetches the descriptor
+	 * corresponding to curr_frame+1, the descriptor corresponding to frame 2
+	 * will be fetched. If the number of descriptors is max=64 (or greather) the list will
+	 * be fully programmed with Active descriptors and it is possible case(rare) that the latest 
+	 * descriptor(considering rollback) corresponding to frame 2 will be serviced first.
+	 * HS case is more probable because, in fact, up to 11 uframes(16 in the code)
+	 * may be skipped.
+	 */
+	if (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) {
+		/* 
+		 * Consider uframe counter also, to start xfer asap.
+		 * If half of the frame elapsed skip 2 frames otherwise
+		 * just 1 frame. 
+		 * Starting descriptor index must be 8-aligned, so
+		 * if the current frame is near to complete the next one
+		 * is skipped as well.
+		 */
+			
+		if (dwc_micro_frame_num(hcd->frame_number)  >= 5) {
+			*skip_frames = 2 * 8;
+		 	frame = dwc_frame_num_inc(hcd->frame_number, *skip_frames);
+		}	
+		else {
+			*skip_frames = 1 * 8;
+			frame = dwc_frame_num_inc(hcd->frame_number, *skip_frames);
+		}	
+				 
+		frame = dwc_full_frame_num(frame); 
+	} else {
+		/* 
+	 	 * Two frames are skipped for FS - the current and the next.
+	 	 * But for descriptor programming, 1 frame(descriptor) is enough,
+	 	 * see example above.
+	 	 */
+	 	*skip_frames = 1;	 
+		frame = dwc_frame_num_inc(hcd->frame_number, 2);
+	}
+	
+	return frame;
+}
+/* 
+ * Calculate initial descriptor index for isochronous transfer
+ * based on scheduled frame. 
+ */
+static uint8_t recalc_initial_desc_idx(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
+{
+	uint16_t frame = 0, fr_idx, fr_idx_tmp;	
+	uint8_t skip_frames = 0 ;
+	/* 
+	 * With current ISOC processing algorithm the channel is being
+	 * released when no more QTDs in the list(qh->ntd == 0).
+	 * Thus this function is called only when qh->ntd == 0 and qh->channel == 0. 
+	 *
+	 * So qh->channel != NULL branch is not used and just not removed from the
+	 * source file. It is required for another possible approach which is,
+	 * do not disable and release the channel when ISOC session completed, 
+	 * just move QH to inactive schedule until new QTD arrives. 
+	 * On new QTD, the QH moved back to 'ready' schedule,
+	 * starting frame and therefore starting desc_index are recalculated.
+	 * In this case channel is released only on ep_disable.
+	 */
+	 
+	/* Calculate starting descriptor index. For INTERRUPT endpoint it is always 0. */
+	if (qh->channel) {
+		frame = calc_starting_frame(hcd, qh, &skip_frames);	
+		/* 
+ 		 * Calculate initial descriptor index based on FrameList current bitmap
+ 		 * and servicing period.
+ 		 */
+		fr_idx_tmp = frame_list_idx(frame);
+		fr_idx = (MAX_FRLIST_EN_NUM + frame_list_idx(qh->sched_frame) - fr_idx_tmp) 
+				% frame_incr_val(qh);
+		fr_idx = (fr_idx + fr_idx_tmp) % MAX_FRLIST_EN_NUM;
+	}
+	else {
+		qh->sched_frame = calc_starting_frame(hcd, qh, &skip_frames);	
+		fr_idx = frame_list_idx(qh->sched_frame);
+	}
+	
+	qh->td_first = qh->td_last =  frame_to_desc_idx(qh, fr_idx);
+	
+	return skip_frames;
+}
+ 
+#define	ISOC_URB_GIVEBACK_ASAP
+ 
+#define MAX_ISOC_XFER_SIZE_FS 1023
+#define MAX_ISOC_XFER_SIZE_HS 3072
+#define DESCNUM_THRESHOLD 4
+
+static void init_isoc_dma_desc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, uint8_t skip_frames)
+{
+	struct dwc_otg_hcd_iso_packet_desc *frame_desc;
+	dwc_otg_qtd_t *qtd;
+	dwc_otg_host_dma_desc_t	*dma_desc;
+	uint16_t idx, inc, n_desc, ntd_max, max_xfer_size;
+	
+	idx = qh->td_last;
+	inc = qh->interval;
+	n_desc = 0;
+	
+	ntd_max = (max_desc_num(qh) + qh->interval - 1) / qh->interval;
+	if (skip_frames && !qh->channel)
+		ntd_max = ntd_max - skip_frames / qh->interval;	
+	
+	max_xfer_size = (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) ? MAX_ISOC_XFER_SIZE_HS 
+								 : MAX_ISOC_XFER_SIZE_FS;
+			
+	DWC_CIRCLEQ_FOREACH(qtd, &qh->qtd_list, qtd_list_entry) {
+		while ((qh->ntd < ntd_max) && (qtd->isoc_frame_index_last < qtd->urb->packet_count)) {
+				
+			dma_desc = &qh->desc_list[idx];
+			dwc_memset(dma_desc, 0x00, sizeof(dwc_otg_host_dma_desc_t));
+
+			frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index_last];
+			
+			if (frame_desc->length > max_xfer_size)
+				qh->n_bytes[idx] = max_xfer_size;
+			else
+				qh->n_bytes[idx] = frame_desc->length;
+			dma_desc->status.b_isoc.n_bytes = qh->n_bytes[idx];
+			dma_desc->status.b_isoc.a = 1;
+			
+			dma_desc->buf = qtd->urb->dma + frame_desc->offset;
+			
+			qh->ntd++;
+
+			qtd->isoc_frame_index_last++;
+			
+		#ifdef	ISOC_URB_GIVEBACK_ASAP
+			/* 
+			 * Set IOC for each descriptor corresponding to the 
+			 * last frame of the URB.
+			 */	
+			if (qtd->isoc_frame_index_last == qtd->urb->packet_count)
+				dma_desc->status.b_isoc.ioc = 1;
+			
+		#endif	
+			idx = desclist_idx_inc(idx, inc, qh->dev_speed);
+			n_desc++;
+			
+		}
+		qtd->in_process = 1;
+	}
+	
+	qh->td_last = idx;
+	
+#ifdef	ISOC_URB_GIVEBACK_ASAP
+	/* Set IOC for the last descriptor if descriptor list is full */	
+	if (qh->ntd == ntd_max) {
+		idx = desclist_idx_dec(qh->td_last, inc, qh->dev_speed);
+		qh->desc_list[idx].status.b_isoc.ioc = 1;
+	}
+#else	
+	/* 
+	 * Set IOC bit only for one descriptor. 
+	 * Always try to be ahead of HW processing,
+	 * i.e. on IOC generation driver activates next descriptors but
+	 * core continues to process descriptors followed the one with IOC set.
+	 */
+
+	if (n_desc > DESCNUM_THRESHOLD) {
+		/* 
+		 * Move IOC "up". Required even if there is only one QTD 
+		 * in the list, cause QTDs migth continue to be queued,
+		 * but during the activation it was only one queued.
+		 * Actually more than one QTD might be in the list if this function called 
+		 * from XferCompletion - QTDs was queued during HW processing of the previous
+		 * descriptor chunk.
+		 */	
+		idx = dwc_desclist_idx_dec(idx, inc * ((qh->ntd + 1) / 2), qh->dev_speed);
+	}
+	else {
+		/* 
+		 * Set the IOC for the latest descriptor
+		 * if either number of descriptor is not greather than threshold
+		 * or no more new descriptors activated.
+		 */	
+		idx = dwc_desclist_idx_dec(qh->td_last, inc, qh->dev_speed);
+	}
+	
+	qh->desc_list[idx].status.b_isoc.ioc = 1;
+#endif
+}
+
+
+static void init_non_isoc_dma_desc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
+{
+
+	dwc_hc_t *hc;
+	dwc_otg_host_dma_desc_t	*dma_desc;
+	dwc_otg_qtd_t *qtd;
+	int	num_packets, len, n_desc = 0;
+	
+	hc =  qh->channel;
+	 
+	/* 
+	 * Start with hc->xfer_buff initialized in 
+	 * assign_and_init_hc(), then if SG transfer consists of multiple URBs,
+	 * this pointer re-assigned to the buffer of the currently processed QTD.
+	 * For non-SG request there is always one QTD active.
+	 */
+	
+	DWC_CIRCLEQ_FOREACH(qtd, &qh->qtd_list, qtd_list_entry) {
+	 		
+	 	if (n_desc) {
+	  		/* SG request - more than 1 QTDs */
+	 		hc->xfer_buff = (uint8_t *)qtd->urb->dma + qtd->urb->actual_length;
+			hc->xfer_len = qtd->urb->length - qtd->urb->actual_length;
+	 	}
+
+		qtd->n_desc = 0;
+		
+		do {
+			dma_desc = &qh->desc_list[n_desc];
+			len = hc->xfer_len;
+			
+
+			if (len > MAX_DMA_DESC_SIZE)
+				len = MAX_DMA_DESC_SIZE - hc->max_packet + 1;
+			
+			if (hc->ep_is_in) {
+				if (len > 0) {
+					num_packets = (len + hc->max_packet - 1) / hc->max_packet;
+				}
+				else {
+					/* Need 1 packet for transfer length of 0. */
+					num_packets = 1;
+				}
+				/* Always program an integral # of max packets for IN transfers. */
+				len = num_packets * hc->max_packet;	
+			}				
+				
+			dma_desc->status.b.n_bytes = len;
+			
+			qh->n_bytes[n_desc] = len;
+			
+
+			if ((qh->ep_type == UE_CONTROL) && (qtd->control_phase == DWC_OTG_CONTROL_SETUP))
+				dma_desc->status.b.sup = 1; /* Setup Packet */
+				
+			dma_desc->status.b.a = 1; /* Active descriptor */
+			
+			dma_desc->buf = (uint32_t) hc->xfer_buff;
+
+			/* 
+			 * Last descriptor(or single) of IN transfer 
+			 * with actual size less than MaxPacket.
+			 */
+			if (len > hc->xfer_len) {
+				hc->xfer_len = 0;
+			}
+			else {
+				hc->xfer_buff += len;
+				hc->xfer_len -= len;
+			}
+			
+			qtd->n_desc++;
+			n_desc++;
+		}
+		while ((hc->xfer_len > 0) && (n_desc != MAX_DMA_DESC_NUM_GENERIC));
+		
+
+		qtd->in_process = 1;
+		
+		if (n_desc == MAX_DMA_DESC_NUM_GENERIC)
+			break;
+	}
+
+	if (n_desc) {
+		/* Request Transfer Complete interrupt for the last descriptor */
+		qh->desc_list[n_desc-1].status.b.ioc = 1;
+		/* End of List indicator */
+		qh->desc_list[n_desc-1].status.b.eol = 1;
+		
+		hc->ntd = n_desc;
+	}
+}
+
+/** 
+ * For Control and Bulk endpoints initializes descriptor list
+ * and starts the transfer.
+ *
+ * For Interrupt and Isochronous endpoints initializes descriptor list
+ * then updates FrameList, marking appropriate entries as active.
+ * In case of Isochronous, the starting descriptor index is calculated based
+ * on the scheduled frame, but only on the first transfer descriptor within a session.
+ * Then starts the transfer via enabling the channel. 
+ * For Isochronous endpoint the channel is not halted on XferComplete 
+ * interrupt so remains assigned to the endpoint(QH) until session is done.
+ *
+ * @param hcd The HCD state structure for the DWC OTG controller.
+ * @param qh The QH to init.
+ *
+ * @return 0 if successful, negative error code otherwise.
+ */
+void dwc_otg_hcd_start_xfer_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
+{
+	/* Channel is already assigned */
+	dwc_hc_t *hc = qh->channel;
+	uint8_t skip_frames = 0;
+	
+	switch (hc->ep_type) {
+	case DWC_OTG_EP_TYPE_CONTROL:
+	case DWC_OTG_EP_TYPE_BULK:
+		init_non_isoc_dma_desc(hcd, qh);
+		
+		dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc);
+		break;
+	case DWC_OTG_EP_TYPE_INTR:
+		init_non_isoc_dma_desc(hcd, qh);
+		
+		update_frame_list(hcd, qh, 1);
+		
+		dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc);
+		break;
+	case DWC_OTG_EP_TYPE_ISOC:
+			
+		if(!qh->ntd)
+			skip_frames = recalc_initial_desc_idx(hcd, qh);
+		
+		init_isoc_dma_desc(hcd, qh, skip_frames);
+
+		if (!hc->xfer_started) {
+
+			update_frame_list(hcd, qh, 1);
+		
+			/* 
+			 * Always set to max, instead of actual size.
+			 * Otherwise ntd will be changed with 
+			 * channel being enabled. Not recommended.
+			 *
+			 */	
+			hc->ntd = max_desc_num(qh);
+			/* Enable channel only once for ISOC */	
+			dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc);
+		}
+		
+		break;
+	default:
+		
+		break;
+	}
+}
+
+static void complete_isoc_xfer_ddma(dwc_otg_hcd_t *hcd,
+				   dwc_hc_t *hc,
+				   dwc_otg_hc_regs_t *hc_regs,
+				   dwc_otg_halt_status_e halt_status)
+{
+	struct dwc_otg_hcd_iso_packet_desc	*frame_desc;		
+	dwc_otg_qtd_t				*qtd, *qtd_tmp;
+	dwc_otg_qh_t				*qh;
+	dwc_otg_host_dma_desc_t			*dma_desc;
+	uint16_t 				idx, remain;
+	uint8_t 				urb_compl;	
+	
+	qh = hc->qh;
+	idx = qh->td_first;
+	
+
+	if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) {
+		DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry)
+			qtd->in_process = 0;
+		return;	
+	}
+	else if ((halt_status == DWC_OTG_HC_XFER_AHB_ERR) || 
+			(halt_status == DWC_OTG_HC_XFER_BABBLE_ERR)) {
+		/* 
+		 * Channel is halted in these error cases.
+		 * Considered as serious issues.
+		 * Complete all URBs marking all frames as failed, 
+		 * irrespective whether some of the descriptors(frames) succeeded or no.
+		 * Pass error code to completion routine as well, to
+		 * update urb->status, some of class drivers might use it to stop
+		 * queing transfer requests.
+		 */	
+		int err = (halt_status == DWC_OTG_HC_XFER_AHB_ERR) 
+							? (-DWC_E_IO)
+							: (-DWC_E_OVERFLOW);
+						
+		DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) {
+			for(idx = 0; idx < qtd->urb->packet_count; idx++) {
+				frame_desc = &qtd->urb->iso_descs[idx];
+				frame_desc->status = err;
+			}
+			hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, err);
+			dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
+		}
+		return;	
+	}
+	
+	
+	DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) {
+		
+		if (!qtd->in_process)
+		    break;
+		
+		urb_compl = 0;
+		
+		do {
+
+			dma_desc = &qh->desc_list[idx];
+			
+			frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
+			remain = hc->ep_is_in ? dma_desc->status.b_isoc.n_bytes : 0;
+	
+			if (dma_desc->status.b_isoc.sts == DMA_DESC_STS_PKTERR) {
+				/* 
+			 	 * XactError or, unable to complete all the transactions 
+	 		 	 * in the scheduled micro-frame/frame, 
+	 		 	 * both indicated by DMA_DESC_STS_PKTERR.
+	 		 	 */	
+				qtd->urb->error_count++;
+				frame_desc->actual_length = qh->n_bytes[idx] - remain;
+				frame_desc->status = -DWC_E_PROTOCOL;
+			}
+			else {
+				/* Success */	
+								
+				frame_desc->actual_length = qh->n_bytes[idx] - remain;
+				frame_desc->status = 0;
+			}
+			
+			if (++qtd->isoc_frame_index == qtd->urb->packet_count) {
+				/*
+				 * urb->status is not used for isoc transfers here.
+				 * The individual frame_desc status are used instead.
+				 */
+
+				hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
+				dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
+				
+				/* 
+				 * This check is necessary because urb_dequeue can be called 
+				 * from urb complete callback(sound driver example).
+				 * All pending URBs are dequeued there, so no need for
+				 * further processing.
+		 		 */
+				if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) {	
+					return;
+				}
+				
+				urb_compl = 1;		
+				
+			}
+			
+			qh->ntd--;
+			
+			/* Stop if IOC requested descriptor reached */
+			if (dma_desc->status.b_isoc.ioc) {
+				idx = desclist_idx_inc(idx, qh->interval, hc->speed);	
+				goto stop_scan;
+			}
+			
+			idx = desclist_idx_inc(idx, qh->interval, hc->speed);
+			
+			if (urb_compl)
+				break;
+		}
+		while(idx != qh->td_first);
+	}
+stop_scan:	
+	qh->td_first = idx;
+}
+	
+uint8_t update_non_isoc_urb_state_ddma(dwc_otg_hcd_t * hcd,
+		      	   dwc_hc_t * hc,
+		      	   dwc_otg_qtd_t * qtd,
+		      	   dwc_otg_host_dma_desc_t * dma_desc,
+		      	   dwc_otg_halt_status_e halt_status,
+		      	   uint32_t n_bytes,
+		      	   uint8_t *xfer_done)
+{
+
+	uint16_t remain = hc->ep_is_in ? dma_desc->status.b.n_bytes : 0;
+	dwc_otg_hcd_urb_t *urb = qtd->urb;
+	
+	
+	if (halt_status == DWC_OTG_HC_XFER_AHB_ERR) {
+		urb->status = -DWC_E_IO;
+		return 1;
+	}
+	if (dma_desc->status.b.sts == DMA_DESC_STS_PKTERR) {
+		switch (halt_status) {
+		case DWC_OTG_HC_XFER_STALL:
+			urb->status = -DWC_E_PIPE;
+			break;
+		case DWC_OTG_HC_XFER_BABBLE_ERR:
+			urb->status = -DWC_E_OVERFLOW;
+			break;
+		case DWC_OTG_HC_XFER_XACT_ERR:
+			urb->status = -DWC_E_PROTOCOL;
+			break;
+		default:	
+			DWC_ERROR("%s: Unhandled descriptor error status (%d)\n", __func__,
+			  	  halt_status);
+			break;
+		}
+		return 1;
+	}
+	
+	if (dma_desc->status.b.a == 1) {
+		DWC_DEBUGPL(DBG_HCDV, "Active descriptor encountered on channel %d\n", hc->hc_num);
+		return 0;
+	}
+	
+	if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL) {
+	    if (qtd->control_phase == DWC_OTG_CONTROL_DATA) {
+		urb->actual_length += n_bytes - remain;
+		if (remain || urb->actual_length == urb->length) {
+			/* 
+			 * For Control Data stage do not set urb->status=0 to prevent
+			 * URB callback. Set it when Status phase done. See below.
+			 */
+			*xfer_done = 1;
+		}		
+	    
+	    }
+	    else if (qtd->control_phase == DWC_OTG_CONTROL_STATUS) {
+		urb->status = 0;
+		*xfer_done = 1;
+	    }
+	    /* No handling for SETUP stage */
+
+	}
+	else { 
+	    /* BULK and INTR */
+	    urb->actual_length += n_bytes - remain;
+	    if (remain || urb->actual_length == urb->length) {
+		urb->status = 0;
+		*xfer_done = 1;
+	    }
+	}
+
+	return 0;
+}
+
+static void complete_non_isoc_xfer_ddma(dwc_otg_hcd_t * hcd,
+				   	dwc_hc_t * hc,
+				   	dwc_otg_hc_regs_t * hc_regs,
+				   	dwc_otg_halt_status_e halt_status)
+{
+	dwc_otg_hcd_urb_t	*urb = NULL;
+	dwc_otg_qtd_t		*qtd, *qtd_tmp;
+	dwc_otg_qh_t		*qh;
+	dwc_otg_host_dma_desc_t	*dma_desc;
+	uint32_t 		n_bytes, n_desc, i;
+	uint8_t			failed = 0, xfer_done;
+	
+	n_desc = 0;
+	
+	qh = hc->qh;
+
+	
+	if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) {
+		DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) {
+			qtd->in_process = 0;
+		}
+		return;
+	}
+	
+	DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) {
+		
+		urb = qtd->urb;
+
+		n_bytes = 0; 
+		xfer_done = 0; 
+		
+		for (i = 0; i < qtd->n_desc; i++) {
+			dma_desc = &qh->desc_list[n_desc];
+		
+			n_bytes = qh->n_bytes[n_desc];
+			
+			
+			failed = update_non_isoc_urb_state_ddma(hcd, hc, qtd, dma_desc, 
+								halt_status, n_bytes, &xfer_done);
+			
+			if (failed || (xfer_done && (urb->status != -DWC_E_IN_PROGRESS))) {
+				
+				hcd->fops->complete(hcd, urb->priv, urb, urb->status);
+				dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
+
+				if (failed)
+					goto stop_scan;
+			}
+			else if (qh->ep_type == UE_CONTROL) {
+				if (qtd->control_phase == DWC_OTG_CONTROL_SETUP) {
+					if (urb->length > 0) {
+						qtd->control_phase = DWC_OTG_CONTROL_DATA;
+					} else {
+						qtd->control_phase = DWC_OTG_CONTROL_STATUS;
+					}
+					DWC_DEBUGPL(DBG_HCDV, "  Control setup transaction done\n");
+				}
+				else if(qtd->control_phase == DWC_OTG_CONTROL_DATA) {
+					if (xfer_done) {
+						qtd->control_phase = DWC_OTG_CONTROL_STATUS;
+						DWC_DEBUGPL(DBG_HCDV, "  Control data transfer done\n");
+					} else if (i+1 == qtd->n_desc){
+						/* 
+						 * Last descriptor for Control data stage which is
+						 * not completed yet.
+						 */	
+						dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
+					}
+				}
+			}
+			
+			n_desc++;
+		}
+		
+	}
+	
+stop_scan:	
+	
+	if (qh->ep_type != UE_CONTROL) {
+		/* 
+		 * Resetting the data toggle for bulk
+		 * and interrupt endpoints in case of stall. See handle_hc_stall_intr() 
+		 */	
+		if (halt_status == DWC_OTG_HC_XFER_STALL) {	
+			qh->data_toggle = DWC_OTG_HC_PID_DATA0;	
+		}
+		else {
+			dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
+		}
+	}
+	
+	if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
+		hcint_data_t hcint;
+		hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
+		if (hcint.b.nyet) {
+			/*
+		 	 * Got a NYET on the last transaction of the transfer. It
+		 	 * means that the endpoint should be in the PING state at the
+		 	 * beginning of the next transfer.
+		 	 */
+			qh->ping_state = 1;
+			clear_hc_int(hc_regs, nyet);
+		}
+
+	}
+
+}
+
+/**
+ * This function is called from interrupt handlers.
+ * Scans the descriptor list, updates URB's status and
+ * calls completion routine for the URB if it's done.
+ * Releases the channel to be used by other transfers.
+ * In case of Isochronous endpoint the channel is not halted until 
+ * the end of the session, i.e. QTD list is empty.
+ * If periodic channel released the FrameList is updated accordingly.
+ *
+ * Calls transaction selection routines to activate pending transfers.
+ *
+ * @param hcd The HCD state structure for the DWC OTG controller.
+ * @param hc Host channel, the transfer is completed on.
+ * @param hc_regs Host channel registers.
+ * @param halt_status Reason the channel is being halted, 
+ *		      or just XferComplete for isochronous transfer
+ */
+void dwc_otg_hcd_complete_xfer_ddma(dwc_otg_hcd_t *hcd,
+			    dwc_hc_t *hc,
+			    dwc_otg_hc_regs_t *hc_regs,
+			    dwc_otg_halt_status_e halt_status)
+{
+	uint8_t continue_isoc_xfer = 0;
+	dwc_otg_transaction_type_e tr_type;
+	dwc_otg_qh_t *qh = hc->qh;
+	
+	if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
+
+		complete_isoc_xfer_ddma(hcd, hc, hc_regs, halt_status);
+		
+		/* Release the channel if halted or session completed */	
+		if (halt_status != DWC_OTG_HC_XFER_COMPLETE ||
+				DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
+
+			/* Halt the channel if session completed */ 	
+			if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
+				dwc_otg_hc_halt(hcd->core_if, hc, halt_status);
+			}	
+			
+			release_channel_ddma(hcd, qh);
+			dwc_otg_hcd_qh_remove(hcd, qh);
+		}
+		else {
+			/* Keep in assigned schedule to continue transfer */
+			DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
+					   &qh->qh_list_entry);
+			continue_isoc_xfer = 1;
+				
+		}
+		/** @todo Consider the case when period exceeds FrameList size.
+		 *  Frame Rollover interrupt should be used. 
+		 */
+	}
+	else {
+		/* Scan descriptor list to complete the URB(s), then release the channel */	
+		complete_non_isoc_xfer_ddma(hcd, hc, hc_regs, halt_status);
+		
+		release_channel_ddma(hcd, qh);
+		
+		dwc_otg_hcd_qh_remove(hcd, qh);
+		
+		if (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
+			/* Add back to inactive non-periodic schedule on normal completion */
+			dwc_otg_hcd_qh_add(hcd, qh);
+		}
+	
+
+	}
+	tr_type = dwc_otg_hcd_select_transactions(hcd);
+	if (tr_type != DWC_OTG_TRANSACTION_NONE || continue_isoc_xfer) {
+		if (continue_isoc_xfer) {
+			if (tr_type == DWC_OTG_TRANSACTION_NONE) {
+				tr_type = DWC_OTG_TRANSACTION_PERIODIC;
+			} else if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC) {
+				tr_type = DWC_OTG_TRANSACTION_ALL;
+			}
+		}
+		dwc_otg_hcd_queue_transactions(hcd, tr_type);
+	}
+}
+	
+#endif	/* DWC_DEVICE_ONLY */
diff --git a/drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h b/drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h
new file mode 100644
index 000000000000..d5a903bae77e
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h
@@ -0,0 +1,393 @@
+/* ==========================================================================
+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_if.h $
+ * $Revision: #6 $
+ * $Date: 2009/04/21 $
+ * $Change: 1237474 $
+ *
+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+ * otherwise expressly agreed to in writing between Synopsys and you.
+ *
+ * The Software IS NOT an item of Licensed Software or Licensed Product under
+ * any End User Software License Agreement or Agreement for Licensed Product
+ * with Synopsys or any supplement thereto. You are permitted to use and
+ * redistribute this Software in source and binary forms, with or without
+ * modification, provided that redistributions of source code must retain this
+ * notice. You may not view, use, disclose, copy or distribute this file or
+ * any information contained herein except pursuant to this license grant from
+ * Synopsys. If you do not agree with this notice, including the disclaimer
+ * below, then you are not authorized to use the Software.
+ *
+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ * ========================================================================== */
+#ifndef DWC_DEVICE_ONLY
+#ifndef __DWC_HCD_IF_H__
+#define __DWC_HCD_IF_H__
+
+#include "dwc_otg_core_if.h"
+
+/** @file
+ * This file defines DWC_OTG HCD Core API.
+ */
+
+struct dwc_otg_hcd;
+typedef struct dwc_otg_hcd dwc_otg_hcd_t;
+
+struct dwc_otg_hcd_urb;
+typedef struct dwc_otg_hcd_urb dwc_otg_hcd_urb_t;
+
+/** @name HCD Function Driver Callbacks */
+/** @{ */
+
+/** This function is called whenever core switches to host mode. */
+typedef int (*dwc_otg_hcd_start_cb_t) (dwc_otg_hcd_t * hcd);
+
+/** This function is called when device has been disconnected */
+typedef int (*dwc_otg_hcd_disconnect_cb_t) (dwc_otg_hcd_t * hcd);
+
+/** Wrapper provides this function to HCD to core, so it can get hub information to which device is connected */
+typedef int (*dwc_otg_hcd_hub_info_from_urb_cb_t) (dwc_otg_hcd_t * hcd,
+						   void *urb_handle,
+						   uint32_t * hub_addr,
+						   uint32_t * port_addr);
+/** Via this function HCD core gets device speed */
+typedef int (*dwc_otg_hcd_speed_from_urb_cb_t) (dwc_otg_hcd_t * hcd,
+						void *urb_handle);
+
+/** This function is called when urb is completed */
+typedef int (*dwc_otg_hcd_complete_urb_cb_t) (dwc_otg_hcd_t * hcd,
+					      void *urb_handle,
+					      dwc_otg_hcd_urb_t * dwc_otg_urb,
+					      int32_t status);
+
+/** Via this function HCD core gets b_hnp_enable parameter */
+typedef int (*dwc_otg_hcd_get_b_hnp_enable) (dwc_otg_hcd_t * hcd);
+
+struct dwc_otg_hcd_function_ops {
+	dwc_otg_hcd_start_cb_t start;
+	dwc_otg_hcd_disconnect_cb_t disconnect;
+	dwc_otg_hcd_hub_info_from_urb_cb_t hub_info;
+	dwc_otg_hcd_speed_from_urb_cb_t speed;
+	dwc_otg_hcd_complete_urb_cb_t complete;
+	dwc_otg_hcd_get_b_hnp_enable get_b_hnp_enable;
+};
+/** @} */
+
+/** @name HCD Core API */
+/** @{ */
+/** This function allocates dwc_otg_hcd structure and returns pointer on it. */
+extern dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void);
+
+/** This function should be called to initiate HCD Core.
+ *
+ * @param hcd The HCD
+ * @param core_if The DWC_OTG Core
+ *
+ * Returns -DWC_E_NO_MEMORY if no enough memory.
+ * Returns 0 on success  
+ */
+extern int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if);
+
+/** Frees HCD
+ *
+ * @param hcd The HCD
+ */
+extern void dwc_otg_hcd_remove(dwc_otg_hcd_t * hcd);
+
+/** This function should be called on every hardware interrupt.
+ *
+ * @param dwc_otg_hcd The HCD
+ *
+ * Returns non zero if interrupt is handled
+ * Return 0 if interrupt is not handled
+ */
+extern int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd);
+
+/**
+ * Returns private data set by
+ * dwc_otg_hcd_set_priv_data function.
+ *
+ * @param hcd The HCD
+ */
+extern void *dwc_otg_hcd_get_priv_data(dwc_otg_hcd_t * hcd);
+
+/**
+ * Set private data.
+ *
+ * @param hcd The HCD
+ * @param priv_data pointer to be stored in private data
+ */
+extern void dwc_otg_hcd_set_priv_data(dwc_otg_hcd_t * hcd, void *priv_data);
+
+/**
+ * This function initializes the HCD Core.
+ *
+ * @param hcd The HCD
+ * @param fops The Function Driver Operations data structure containing pointers to all callbacks.
+ *
+ * Returns -DWC_E_NO_DEVICE if Core is currently is in device mode.
+ * Returns 0 on success
+ */
+extern int dwc_otg_hcd_start(dwc_otg_hcd_t * hcd,
+			     struct dwc_otg_hcd_function_ops *fops);
+
+/**
+ * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
+ * stopped. 
+ *
+ * @param hcd The HCD
+ */
+extern void dwc_otg_hcd_stop(dwc_otg_hcd_t * hcd);
+
+/**
+ * Handles hub class-specific requests.
+ *
+ * @param dwc_otg_hcd The HCD
+ * @param typeReq Request Type
+ * @param wValue wValue from control request
+ * @param wIndex wIndex from control request
+ * @param buf data buffer 
+ * @param wLength data buffer length
+ *
+ * Returns -DWC_E_INVALID if invalid argument is passed
+ * Returns 0 on success
+ */
+extern int dwc_otg_hcd_hub_control(dwc_otg_hcd_t * dwc_otg_hcd,
+				   uint16_t typeReq, uint16_t wValue,
+				   uint16_t wIndex, uint8_t * buf,
+				   uint16_t wLength);
+
+/**
+ * Returns otg port number.
+ *
+ * @param hcd The HCD
+ */
+extern uint32_t dwc_otg_hcd_otg_port(dwc_otg_hcd_t * hcd);
+
+/**
+ * Returns 1 if currently core is acting as B host, and 0 otherwise.
+ *
+ * @param hcd The HCD
+ */
+extern uint32_t dwc_otg_hcd_is_b_host(dwc_otg_hcd_t * hcd);
+
+/**
+ * Returns current frame number.
+ *
+ * @param hcd The HCD
+ */
+extern int dwc_otg_hcd_get_frame_number(dwc_otg_hcd_t * hcd);
+
+/**
+ * Dumps hcd state.
+ *
+ * @param hcd The HCD
+ */
+extern void dwc_otg_hcd_dump_state(dwc_otg_hcd_t * hcd);
+
+/**
+ * Dump the average frame remaining at SOF. This can be used to
+ * determine average interrupt latency. Frame remaining is also shown for
+ * start transfer and two additional sample points.
+ * Currently this function is not implemented.
+ *
+ * @param hcd The HCD
+ */
+extern void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t * hcd);
+
+/**
+ * Sends LPM transaction to the local device.
+ *
+ * @param hcd The HCD
+ * @param devaddr Device Address
+ * @param hird Host initiated resume duration
+ * @param bRemoteWake Value of bRemoteWake field in LPM transaction
+ *
+ * Returns negative value if sending LPM transaction was not succeeded.
+ * Returns 0 on success.
+ */
+extern int dwc_otg_hcd_send_lpm(dwc_otg_hcd_t * hcd, uint8_t devaddr,
+				uint8_t hird, uint8_t bRemoteWake);
+
+/* URB interface */
+
+/**
+ * Allocates memory for dwc_otg_hcd_urb structure.
+ * Allocated memory should be freed by call dwc_free function.
+ *
+ * @param hcd The HCD
+ * @param iso_desc_count Count of ISOC descriptors
+ * @param atomic_alloc Specefies whether to perform atomic allocation.
+ */
+extern dwc_otg_hcd_urb_t *dwc_otg_hcd_urb_alloc(dwc_otg_hcd_t * hcd,
+						int iso_desc_count,
+						int atomic_alloc);
+
+/**
+ * Set pipe information in URB.
+ *
+ * @param hcd_urb DWC_OTG URB
+ * @param devaddr Device Address
+ * @param ep_num Endpoint Number
+ * @param ep_type Endpoint Type
+ * @param ep_dir Endpoint Direction
+ * @param mps Max Packet Size
+ */
+extern void dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_hcd_urb_t * hcd_urb,
+					 uint8_t devaddr, uint8_t ep_num,
+					 uint8_t ep_type, uint8_t ep_dir,
+					 uint16_t mps);
+
+/* Transfer flags */ 
+#define URB_GIVEBACK_ASAP 0x1
+#define URB_SEND_ZERO_PACKET 0x2
+
+/**
+ * Sets dwc_otg_hcd_urb parameters.
+ *
+ * @param urb DWC_OTG URB allocated by dwc_otg_hcd_urb_alloc function.
+ * @param urb_handle Unique handle for request, this will be passed back
+ * to function driver in completion callback.
+ * @param buf The buffer for the data
+ * @param dma The DMA buffer for the data
+ * @param buflen Transfer length
+ * @param sp Buffer for setup data
+ * @param sp_dma DMA address of setup data buffer
+ * @param flags Transfer flags
+ * @param interval Polling interval for interrupt or isochronous transfers.
+ */
+extern void dwc_otg_hcd_urb_set_params(dwc_otg_hcd_urb_t * urb,
+				       void *urb_handle, void *buf,
+				       dwc_dma_t dma, uint32_t buflen, void *sp,
+				       dwc_dma_t sp_dma, uint32_t flags,
+				       uint16_t interval);
+
+/** Gets status from dwc_otg_hcd_urb
+ *
+ * @param dwc_otg_urb DWC_OTG URB
+ */
+extern uint32_t dwc_otg_hcd_urb_get_status(dwc_otg_hcd_urb_t * dwc_otg_urb);
+
+/** Gets actual length from dwc_otg_hcd_urb
+ *
+ * @param dwc_otg_urb DWC_OTG URB
+ */
+extern uint32_t dwc_otg_hcd_urb_get_actual_length(dwc_otg_hcd_urb_t *
+						  dwc_otg_urb);
+
+/** Gets error count from dwc_otg_hcd_urb. Only for ISOC URBs
+ *
+ * @param dwc_otg_urb DWC_OTG URB
+ */
+extern uint32_t dwc_otg_hcd_urb_get_error_count(dwc_otg_hcd_urb_t *
+						dwc_otg_urb);
+
+/** Set ISOC descriptor offset and length
+ *
+ * @param dwc_otg_urb DWC_OTG URB
+ * @param desc_num ISOC descriptor number
+ * @param offset Offset from beginig of buffer.
+ * @param length Transaction length
+ */
+extern void dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_hcd_urb_t * dwc_otg_urb,
+						int desc_num, uint32_t offset,
+						uint32_t length);
+
+/** Get status of ISOC descriptor, specified by desc_num
+ *
+ * @param dwc_otg_urb DWC_OTG URB
+ * @param desc_num ISOC descriptor number 
+ */
+extern uint32_t dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_hcd_urb_t *
+						    dwc_otg_urb, int desc_num);
+
+/** Get actual length of ISOC descriptor, specified by desc_num
+ *
+ * @param dwc_otg_urb DWC_OTG URB
+ * @param desc_num ISOC descriptor number
+ */
+extern uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length(dwc_otg_hcd_urb_t *
+							   dwc_otg_urb,
+							   int desc_num);
+
+/** Queue URB. After transfer is completes, the complete callback will be called with the URB status
+ *
+ * @param dwc_otg_hcd The HCD
+ * @param dwc_otg_urb DWC_OTG URB
+ * @param ep_handle Out parameter for returning endpoint handle
+ *
+ * Returns -DWC_E_NO_DEVICE if no device is connected.
+ * Returns -DWC_E_NO_MEMORY if there is no enough memory.
+ * Returns 0 on success.
+ */
+extern int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t * dwc_otg_hcd,
+				   dwc_otg_hcd_urb_t * dwc_otg_urb,
+				   void **ep_handle);
+
+/** De-queue the specified URB
+ *
+ * @param dwc_otg_hcd The HCD
+ * @param dwc_otg_urb DWC_OTG URB
+ */
+extern int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t * dwc_otg_hcd,
+				   dwc_otg_hcd_urb_t * dwc_otg_urb);
+
+/** Frees resources in the DWC_otg controller related to a given endpoint.
+ * Any URBs for the endpoint must already be dequeued.
+ *
+ * @param hcd The HCD
+ * @param ep_handle Endpoint handle, returned by dwc_otg_hcd_urb_enqueue function
+ * @param retry Number of retries if there are queued transfers.
+ *
+ * Returns -DWC_E_INVALID if invalid arguments are passed.
+ * Returns 0 on success
+ */
+extern int dwc_otg_hcd_endpoint_disable(dwc_otg_hcd_t * hcd, void *ep_handle,
+					int retry);
+
+/** Returns 1 if status of specified port is changed and 0 otherwise.
+ *
+ * @param hcd The HCD
+ * @param port Port number
+ */
+extern int dwc_otg_hcd_is_status_changed(dwc_otg_hcd_t * hcd, int port);
+
+/** Call this function to check if bandwidth was allocated for specified endpoint.
+ * Only for ISOC and INTERRUPT endpoints.
+ *
+ * @param hcd The HCD
+ * @param ep_handle Endpoint handle
+ */
+extern int dwc_otg_hcd_is_bandwidth_allocated(dwc_otg_hcd_t * hcd,
+					      void *ep_handle);
+
+/** Call this function to check if bandwidth was freed for specified endpoint.
+ *
+ * @param hcd The HCD
+ * @param ep_handle Endpoint handle
+ */
+extern int dwc_otg_hcd_is_bandwidth_freed(dwc_otg_hcd_t * hcd, void *ep_handle);
+
+/** Returns bandwidth allocated for specified endpoint in microseconds.
+ * Only for ISOC and INTERRUPT endpoints.
+ *
+ * @param hcd The HCD
+ * @param ep_handle Endpoint handle
+ */
+extern uint8_t dwc_otg_hcd_get_ep_bandwidth(dwc_otg_hcd_t * hcd,
+					    void *ep_handle);
+
+/** @} */
+
+#endif				/* __DWC_HCD_IF_H__ */
+#endif				/* DWC_DEVICE_ONLY */
diff --git a/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c b/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c
new file mode 100644
index 000000000000..6e4bc60b328a
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c
@@ -0,0 +1,2065 @@
+/* ==========================================================================
+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_intr.c $
+ * $Revision: #77 $
+ * $Date: 2009/04/21 $
+ * $Change: 1237475 $
+ *
+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+ * otherwise expressly agreed to in writing between Synopsys and you.
+ *
+ * The Software IS NOT an item of Licensed Software or Licensed Product under
+ * any End User Software License Agreement or Agreement for Licensed Product
+ * with Synopsys or any supplement thereto. You are permitted to use and
+ * redistribute this Software in source and binary forms, with or without
+ * modification, provided that redistributions of source code must retain this
+ * notice. You may not view, use, disclose, copy or distribute this file or
+ * any information contained herein except pursuant to this license grant from
+ * Synopsys. If you do not agree with this notice, including the disclaimer
+ * below, then you are not authorized to use the Software.
+ *
+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ * ========================================================================== */
+#ifndef DWC_DEVICE_ONLY
+
+#include "dwc_otg_hcd.h"
+#include "dwc_otg_regs.h"
+
+/** @file
+ * This file contains the implementation of the HCD Interrupt handlers.
+ */
+
+/** This function handles interrupts for the HCD. */
+int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd)
+{
+	int retval = 0;
+
+	dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
+	gintsts_data_t gintsts;
+#ifdef DEBUG
+	dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
+
+        //GRAYG: debugging
+        if (NULL == global_regs) {
+                DWC_DEBUGPL(DBG_HCD, "**** NULL regs: dwc_otg_hcd=%p "
+                            "core_if=%p\n",
+                            dwc_otg_hcd, global_regs);
+                return retval;
+        }
+#endif
+
+	/* Check if HOST Mode */
+	if (dwc_otg_is_host_mode(core_if)) {
+		gintsts.d32 = dwc_otg_read_core_intr(core_if);
+		if (!gintsts.d32) {
+			return 0;
+		}
+#ifdef DEBUG
+		/* Don't print debug message in the interrupt handler on SOF */
+#ifndef DEBUG_SOF
+		if (gintsts.d32 != DWC_SOF_INTR_MASK)
+#endif
+			DWC_DEBUGPL(DBG_HCD, "\n");
+#endif
+
+#ifdef DEBUG
+#ifndef DEBUG_SOF
+		if (gintsts.d32 != DWC_SOF_INTR_MASK)
+#endif
+			DWC_DEBUGPL(DBG_HCD,
+				    "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x core_if=%p\n",
+				    gintsts.d32, core_if);
+#endif
+
+		if (gintsts.b.sofintr) {
+			retval |= dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd);
+		}
+		if (gintsts.b.rxstsqlvl) {
+			retval |=
+			    dwc_otg_hcd_handle_rx_status_q_level_intr
+			    (dwc_otg_hcd);
+		}
+		if (gintsts.b.nptxfempty) {
+			retval |=
+			    dwc_otg_hcd_handle_np_tx_fifo_empty_intr
+			    (dwc_otg_hcd);
+		}
+		if (gintsts.b.i2cintr) {
+			/** @todo Implement i2cintr handler. */
+		}
+		if (gintsts.b.portintr) {
+			retval |= dwc_otg_hcd_handle_port_intr(dwc_otg_hcd);
+		}
+		if (gintsts.b.hcintr) {
+			retval |= dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd);
+		}
+		if (gintsts.b.ptxfempty) {
+			retval |=
+			    dwc_otg_hcd_handle_perio_tx_fifo_empty_intr
+			    (dwc_otg_hcd);
+		}
+#ifdef DEBUG
+#ifndef DEBUG_SOF
+		if (gintsts.d32 != DWC_SOF_INTR_MASK)
+#endif
+		{
+			DWC_DEBUGPL(DBG_HCD,
+				    "DWC OTG HCD Finished Servicing Interrupts\n");
+			DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintsts=0x%08x\n",
+				    dwc_read_reg32(&global_regs->gintsts));
+			DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintmsk=0x%08x\n",
+				    dwc_read_reg32(&global_regs->gintmsk));
+		}
+#endif
+
+#ifdef DEBUG
+#ifndef DEBUG_SOF
+		if (gintsts.d32 != DWC_SOF_INTR_MASK)
+#endif
+			DWC_DEBUGPL(DBG_HCD, "\n");
+#endif
+
+	}
+
+	return retval;
+}
+
+#ifdef DWC_TRACK_MISSED_SOFS
+#warning Compiling code to track missed SOFs
+#define FRAME_NUM_ARRAY_SIZE 1000
+/**
+ * This function is for debug only.
+ */
+static inline void track_missed_sofs(uint16_t curr_frame_number)
+{
+	static uint16_t frame_num_array[FRAME_NUM_ARRAY_SIZE];
+	static uint16_t last_frame_num_array[FRAME_NUM_ARRAY_SIZE];
+	static int frame_num_idx = 0;
+	static uint16_t last_frame_num = DWC_HFNUM_MAX_FRNUM;
+	static int dumped_frame_num_array = 0;
+
+	if (frame_num_idx < FRAME_NUM_ARRAY_SIZE) {
+		if (((last_frame_num + 1) & DWC_HFNUM_MAX_FRNUM) !=
+		    curr_frame_number) {
+			frame_num_array[frame_num_idx] = curr_frame_number;
+			last_frame_num_array[frame_num_idx++] = last_frame_num;
+		}
+	} else if (!dumped_frame_num_array) {
+		int i;
+		DWC_PRINTF("Frame     Last Frame\n");
+		DWC_PRINTF("-----     ----------\n");
+		for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) {
+			DWC_PRINTF("0x%04x    0x%04x\n",
+				   frame_num_array[i], last_frame_num_array[i]);
+		}
+		dumped_frame_num_array = 1;
+	}
+	last_frame_num = curr_frame_number;
+}
+#endif
+
+/**
+ * Handles the start-of-frame interrupt in host mode. Non-periodic
+ * transactions may be queued to the DWC_otg controller for the current
+ * (micro)frame. Periodic transactions may be queued to the controller for the
+ * next (micro)frame.
+ */
+int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * hcd)
+{
+	hfnum_data_t hfnum;
+	dwc_list_link_t *qh_entry;
+	dwc_otg_qh_t *qh;
+	dwc_otg_transaction_type_e tr_type;
+	gintsts_data_t gintsts = {.d32 = 0 };
+
+	hfnum.d32 =
+	    dwc_read_reg32(&hcd->core_if->host_if->host_global_regs->hfnum);
+
+#ifdef DEBUG_SOF
+	DWC_DEBUGPL(DBG_HCD, "--Start of Frame Interrupt--\n");
+#endif
+	hcd->frame_number = hfnum.b.frnum;
+
+#ifdef DEBUG
+	hcd->frrem_accum += hfnum.b.frrem;
+	hcd->frrem_samples++;
+#endif
+
+#ifdef DWC_TRACK_MISSED_SOFS
+	track_missed_sofs(hcd->frame_number);
+#endif
+	/* Determine whether any periodic QHs should be executed. */
+	qh_entry = DWC_LIST_FIRST(&hcd->periodic_sched_inactive);
+	while (qh_entry != &hcd->periodic_sched_inactive) {
+		qh = DWC_LIST_ENTRY(qh_entry, dwc_otg_qh_t, qh_list_entry);
+		qh_entry = qh_entry->next;
+		if (dwc_frame_num_le(qh->sched_frame, hcd->frame_number)) {
+			/*
+			 * Move QH to the ready list to be executed next
+			 * (micro)frame.
+			 */
+			DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready,
+					   &qh->qh_list_entry);
+		}
+	}
+	tr_type = dwc_otg_hcd_select_transactions(hcd);
+	if (tr_type != DWC_OTG_TRANSACTION_NONE) {
+		dwc_otg_hcd_queue_transactions(hcd, tr_type);
+	}
+
+	/* Clear interrupt */
+	gintsts.b.sofintr = 1;
+	dwc_write_reg32(&hcd->core_if->core_global_regs->gintsts, gintsts.d32);
+
+	return 1;
+}
+
+/** Handles the Rx Status Queue Level Interrupt, which indicates that there is at
+ * least one packet in the Rx FIFO.  The packets are moved from the FIFO to
+ * memory if the DWC_otg controller is operating in Slave mode. */
+int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t * dwc_otg_hcd)
+{
+	host_grxsts_data_t grxsts;
+	dwc_hc_t *hc = NULL;
+
+	DWC_DEBUGPL(DBG_HCD, "--RxStsQ Level Interrupt--\n");
+
+	grxsts.d32 =
+	    dwc_read_reg32(&dwc_otg_hcd->core_if->core_global_regs->grxstsp);
+
+	hc = dwc_otg_hcd->hc_ptr_array[grxsts.b.chnum];
+
+	/* Packet Status */
+	DWC_DEBUGPL(DBG_HCDV, "    Ch num = %d\n", grxsts.b.chnum);
+	DWC_DEBUGPL(DBG_HCDV, "    Count = %d\n", grxsts.b.bcnt);
+	DWC_DEBUGPL(DBG_HCDV, "    DPID = %d, hc.dpid = %d\n", grxsts.b.dpid,
+		    hc->data_pid_start);
+	DWC_DEBUGPL(DBG_HCDV, "    PStatus = %d\n", grxsts.b.pktsts);
+
+	switch (grxsts.b.pktsts) {
+	case DWC_GRXSTS_PKTSTS_IN:
+		/* Read the data into the host buffer. */
+		if (grxsts.b.bcnt > 0) {
+			dwc_otg_read_packet(dwc_otg_hcd->core_if,
+					    hc->xfer_buff, grxsts.b.bcnt);
+
+			/* Update the HC fields for the next packet received. */
+			hc->xfer_count += grxsts.b.bcnt;
+			hc->xfer_buff += grxsts.b.bcnt;
+		}
+
+	case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
+	case DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
+	case DWC_GRXSTS_PKTSTS_CH_HALTED:
+		/* Handled in interrupt, just ignore data */
+		break;
+	default:
+		DWC_ERROR("RX_STS_Q Interrupt: Unknown status %d\n",
+			  grxsts.b.pktsts);
+		break;
+	}
+
+	return 1;
+}
+
+/** This interrupt occurs when the non-periodic Tx FIFO is half-empty. More
+ * data packets may be written to the FIFO for OUT transfers. More requests
+ * may be written to the non-periodic request queue for IN transfers. This
+ * interrupt is enabled only in Slave mode. */
+int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t * dwc_otg_hcd)
+{
+	DWC_DEBUGPL(DBG_HCD, "--Non-Periodic TxFIFO Empty Interrupt--\n");
+	dwc_otg_hcd_queue_transactions(dwc_otg_hcd,
+				       DWC_OTG_TRANSACTION_NON_PERIODIC);
+	return 1;
+}
+
+/** This interrupt occurs when the periodic Tx FIFO is half-empty. More data
+ * packets may be written to the FIFO for OUT transfers. More requests may be
+ * written to the periodic request queue for IN transfers. This interrupt is
+ * enabled only in Slave mode. */
+int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t * dwc_otg_hcd)
+{
+	DWC_DEBUGPL(DBG_HCD, "--Periodic TxFIFO Empty Interrupt--\n");
+	dwc_otg_hcd_queue_transactions(dwc_otg_hcd,
+				       DWC_OTG_TRANSACTION_PERIODIC);
+	return 1;
+}
+
+/** There are multiple conditions that can cause a port interrupt. This function
+ * determines which interrupt conditions have occurred and handles them
+ * appropriately. */
+int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t * dwc_otg_hcd)
+{
+	int retval = 0;
+	hprt0_data_t hprt0;
+	hprt0_data_t hprt0_modify;
+
+	hprt0.d32 = dwc_read_reg32(dwc_otg_hcd->core_if->host_if->hprt0);
+	hprt0_modify.d32 = dwc_read_reg32(dwc_otg_hcd->core_if->host_if->hprt0);
+
+	/* Clear appropriate bits in HPRT0 to clear the interrupt bit in
+	 * GINTSTS */
+
+	hprt0_modify.b.prtena = 0;
+	hprt0_modify.b.prtconndet = 0;
+	hprt0_modify.b.prtenchng = 0;
+	hprt0_modify.b.prtovrcurrchng = 0;
+
+	/* Port Connect Detected
+	 * Set flag and clear if detected */
+	if (hprt0.b.prtconndet) {
+		DWC_DEBUGPL(DBG_HCD, "--Port Interrupt HPRT0=0x%08x "
+			    "Port Connect Detected--\n", hprt0.d32);
+		dwc_otg_hcd->flags.b.port_connect_status_change = 1;
+		dwc_otg_hcd->flags.b.port_connect_status = 1;
+		hprt0_modify.b.prtconndet = 1;
+
+		/* B-Device has connected, Delete the connection timer. */
+		DWC_TIMER_CANCEL(dwc_otg_hcd->conn_timer);
+
+		/* The Hub driver asserts a reset when it sees port connect
+		 * status change flag */
+		retval |= 1;
+	}
+
+	/* Port Enable Changed
+	 * Clear if detected - Set internal flag if disabled */
+	if (hprt0.b.prtenchng) {
+		DWC_DEBUGPL(DBG_HCD, "  --Port Interrupt HPRT0=0x%08x "
+			    "Port Enable Changed--\n", hprt0.d32);
+		hprt0_modify.b.prtenchng = 1;
+		if (hprt0.b.prtena == 1) {
+			int do_reset = 0;
+			dwc_otg_core_params_t *params =
+			    dwc_otg_hcd->core_if->core_params;
+			dwc_otg_core_global_regs_t *global_regs =
+			    dwc_otg_hcd->core_if->core_global_regs;
+			dwc_otg_host_if_t *host_if =
+			    dwc_otg_hcd->core_if->host_if;
+
+			/* Check if we need to adjust the PHY clock speed for
+			 * low power and adjust it */
+			if (params->host_support_fs_ls_low_power) {
+				gusbcfg_data_t usbcfg;
+
+				usbcfg.d32 =
+				    dwc_read_reg32(&global_regs->gusbcfg);
+
+				if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED
+				    || hprt0.b.prtspd ==
+				    DWC_HPRT0_PRTSPD_FULL_SPEED) {
+					/*
+					 * Low power
+					 */
+					hcfg_data_t hcfg;
+					if (usbcfg.b.phylpwrclksel == 0) {
+						/* Set PHY low power clock select for FS/LS devices */
+						usbcfg.b.phylpwrclksel = 1;
+						dwc_write_reg32(&global_regs->
+								gusbcfg,
+								usbcfg.d32);
+						do_reset = 1;
+					}
+
+					hcfg.d32 =
+					    dwc_read_reg32(&host_if->
+							   host_global_regs->hcfg);
+
+					if (hprt0.b.prtspd ==
+					    DWC_HPRT0_PRTSPD_LOW_SPEED
+					    && params->
+					    host_ls_low_power_phy_clk ==
+					    DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ)
+					{
+						/* 6 MHZ */
+						DWC_DEBUGPL(DBG_CIL,
+							    "FS_PHY programming HCFG to 6 MHz (Low Power)\n");
+						if (hcfg.b.fslspclksel !=
+						    DWC_HCFG_6_MHZ) {
+							hcfg.b.fslspclksel =
+							    DWC_HCFG_6_MHZ;
+							dwc_write_reg32
+							    (&host_if->
+							     host_global_regs->
+							     hcfg, hcfg.d32);
+							do_reset = 1;
+						}
+					} else {
+						/* 48 MHZ */
+						DWC_DEBUGPL(DBG_CIL,
+							    "FS_PHY programming HCFG to 48 MHz ()\n");
+						if (hcfg.b.fslspclksel !=
+						    DWC_HCFG_48_MHZ) {
+							hcfg.b.fslspclksel =
+							    DWC_HCFG_48_MHZ;
+							dwc_write_reg32
+							    (&host_if->
+							     host_global_regs->
+							     hcfg, hcfg.d32);
+							do_reset = 1;
+						}
+					}
+				} else {
+					/*
+					 * Not low power
+					 */
+					if (usbcfg.b.phylpwrclksel == 1) {
+						usbcfg.b.phylpwrclksel = 0;
+						dwc_write_reg32(&global_regs->
+								gusbcfg,
+								usbcfg.d32);
+						do_reset = 1;
+					}
+				}
+
+				if (do_reset) {
+					DWC_TASK_SCHEDULE(dwc_otg_hcd->
+							  reset_tasklet);
+				}
+			}
+
+			if (!do_reset) {
+				/* Port has been enabled set the reset change flag */
+				dwc_otg_hcd->flags.b.port_reset_change = 1;
+			}
+		} else {
+			dwc_otg_hcd->flags.b.port_enable_change = 1;
+		}
+		retval |= 1;
+	}
+
+	/** Overcurrent Change Interrupt */
+	if (hprt0.b.prtovrcurrchng) {
+		DWC_DEBUGPL(DBG_HCD, "  --Port Interrupt HPRT0=0x%08x "
+			    "Port Overcurrent Changed--\n", hprt0.d32);
+		dwc_otg_hcd->flags.b.port_over_current_change = 1;
+		hprt0_modify.b.prtovrcurrchng = 1;
+		retval |= 1;
+	}
+
+	/* Clear Port Interrupts */
+	dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32);
+
+	return retval;
+}
+
+/** This interrupt indicates that one or more host channels has a pending
+ * interrupt. There are multiple conditions that can cause each host channel
+ * interrupt. This function determines which conditions have occurred for each
+ * host channel interrupt and handles them appropriately. */
+int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t * dwc_otg_hcd)
+{
+	int i;
+	int retval = 0;
+	haint_data_t haint;
+
+	/* Clear appropriate bits in HCINTn to clear the interrupt bit in
+	 * GINTSTS */
+
+	haint.d32 = dwc_otg_read_host_all_channels_intr(dwc_otg_hcd->core_if);
+
+	for (i = 0; i < dwc_otg_hcd->core_if->core_params->host_channels; i++) {
+		if (haint.b2.chint & (1 << i)) {
+			retval |= dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd, i);
+		}
+	}
+
+	return retval;
+}
+
+
+
+/**
+ * Gets the actual length of a transfer after the transfer halts. _halt_status
+ * holds the reason for the halt.
+ *
+ * For IN transfers where halt_status is DWC_OTG_HC_XFER_COMPLETE,
+ * *short_read is set to 1 upon return if less than the requested
+ * number of bytes were transferred. Otherwise, *short_read is set to 0 upon
+ * return. short_read may also be NULL on entry, in which case it remains
+ * unchanged.
+ */
+static uint32_t get_actual_xfer_length(dwc_hc_t * hc,
+				       dwc_otg_hc_regs_t * hc_regs,
+				       dwc_otg_qtd_t * qtd,
+				       dwc_otg_halt_status_e halt_status,
+				       int *short_read)
+{
+	hctsiz_data_t hctsiz;
+	uint32_t length;
+
+	if (short_read != NULL) {
+		*short_read = 0;
+	}
+	hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
+
+	if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
+		if (hc->ep_is_in) {
+			length = hc->xfer_len - hctsiz.b.xfersize;
+			if (short_read != NULL) {
+				*short_read = (hctsiz.b.xfersize != 0);
+			}
+		} else if (hc->qh->do_split) {
+			length = qtd->ssplit_out_xfer_count;
+		} else {
+			length = hc->xfer_len;
+		}
+	} else {
+		/*
+		 * Must use the hctsiz.pktcnt field to determine how much data
+		 * has been transferred. This field reflects the number of
+		 * packets that have been transferred via the USB. This is
+		 * always an integral number of packets if the transfer was
+		 * halted before its normal completion. (Can't use the
+		 * hctsiz.xfersize field because that reflects the number of
+		 * bytes transferred via the AHB, not the USB).
+		 */
+		length =
+		    (hc->start_pkt_count - hctsiz.b.pktcnt) * hc->max_packet;
+	}
+
+	return length;
+}
+
+/**
+ * Updates the state of the URB after a Transfer Complete interrupt on the
+ * host channel. Updates the actual_length field of the URB based on the
+ * number of bytes transferred via the host channel. Sets the URB status
+ * if the data transfer is finished.
+ *
+ * @return 1 if the data transfer specified by the URB is completely finished,
+ * 0 otherwise.
+ */
+static int update_urb_state_xfer_comp(dwc_hc_t * hc,
+				      dwc_otg_hc_regs_t * hc_regs,
+				      dwc_otg_hcd_urb_t * urb,
+				      dwc_otg_qtd_t * qtd)
+{
+	int xfer_done = 0;
+	int short_read = 0;
+
+	int xfer_length;
+
+	xfer_length = get_actual_xfer_length(hc, hc_regs, qtd,						     
+						     DWC_OTG_HC_XFER_COMPLETE,
+						     &short_read);
+
+
+	/* non DWORD-aligned buffer case handling. */
+	if (hc->align_buff && xfer_length && hc->ep_is_in) {
+		dwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf, xfer_length);
+	}
+
+	urb->actual_length += xfer_length;
+
+	if(xfer_length && (hc->ep_type == DWC_OTG_EP_TYPE_BULK) &&
+	   (urb->flags & URB_SEND_ZERO_PACKET) && (urb->actual_length == urb->length) &&
+	   !(urb->length % hc->max_packet)) {
+		xfer_done = 0;
+	} else if (short_read || urb->actual_length == urb->length) {
+		xfer_done = 1;
+		urb->status = 0;
+	}
+	
+#ifdef DEBUG
+	{
+		hctsiz_data_t hctsiz;
+		hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
+		DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
+			    __func__, (hc->ep_is_in ? "IN" : "OUT"),
+			    hc->hc_num);
+		DWC_DEBUGPL(DBG_HCDV, "  hc->xfer_len %d\n", hc->xfer_len);
+		DWC_DEBUGPL(DBG_HCDV, "  hctsiz.xfersize %d\n",
+			    hctsiz.b.xfersize);
+		DWC_DEBUGPL(DBG_HCDV, "  urb->transfer_buffer_length %d\n",
+			    urb->length);
+		DWC_DEBUGPL(DBG_HCDV, "  urb->actual_length %d\n",
+			    urb->actual_length);
+		DWC_DEBUGPL(DBG_HCDV, "  short_read %d, xfer_done %d\n",
+			    short_read, xfer_done);
+	}
+#endif
+
+	return xfer_done;
+}
+
+/*
+ * Save the starting data toggle for the next transfer. The data toggle is
+ * saved in the QH for non-control transfers and it's saved in the QTD for
+ * control transfers.
+ */
+void dwc_otg_hcd_save_data_toggle(dwc_hc_t * hc,
+			     dwc_otg_hc_regs_t * hc_regs, dwc_otg_qtd_t * qtd)
+{
+	hctsiz_data_t hctsiz;
+	hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
+
+	if (hc->ep_type != DWC_OTG_EP_TYPE_CONTROL) {
+		dwc_otg_qh_t *qh = hc->qh;
+		if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
+			qh->data_toggle = DWC_OTG_HC_PID_DATA0;
+		} else {
+			qh->data_toggle = DWC_OTG_HC_PID_DATA1;
+		}
+	} else {
+		if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
+			qtd->data_toggle = DWC_OTG_HC_PID_DATA0;
+		} else {
+			qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
+		}
+	}
+}
+
+/**
+ * Updates the state of an Isochronous URB when the transfer is stopped for
+ * any reason. The fields of the current entry in the frame descriptor array
+ * are set based on the transfer state and the input _halt_status. Completes
+ * the Isochronous URB if all the URB frames have been completed.
+ *
+ * @return DWC_OTG_HC_XFER_COMPLETE if there are more frames remaining to be
+ * transferred in the URB. Otherwise return DWC_OTG_HC_XFER_URB_COMPLETE.
+ */
+static dwc_otg_halt_status_e
+update_isoc_urb_state(dwc_otg_hcd_t * hcd,
+		      dwc_hc_t * hc,
+		      dwc_otg_hc_regs_t * hc_regs,
+		      dwc_otg_qtd_t * qtd, dwc_otg_halt_status_e halt_status)
+{
+	dwc_otg_hcd_urb_t *urb = qtd->urb;
+	dwc_otg_halt_status_e ret_val = halt_status;
+	struct dwc_otg_hcd_iso_packet_desc *frame_desc;
+
+	frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
+	switch (halt_status) {
+	case DWC_OTG_HC_XFER_COMPLETE:
+		frame_desc->status = 0;
+		frame_desc->actual_length =
+		    get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL);
+		    
+		/* non DWORD-aligned buffer case handling. */
+		if (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) {
+			dwc_memcpy(urb->buf + frame_desc->offset + qtd->isoc_split_offset, 
+				   hc->qh->dw_align_buf, frame_desc->actual_length);
+		}
+		
+		break;
+	case DWC_OTG_HC_XFER_FRAME_OVERRUN:
+		urb->error_count++;
+		if (hc->ep_is_in) {
+			frame_desc->status = -DWC_E_NO_STREAM_RES;
+		} else {
+			frame_desc->status = -DWC_E_COMMUNICATION;
+		}
+		frame_desc->actual_length = 0;
+		break;
+	case DWC_OTG_HC_XFER_BABBLE_ERR:
+		urb->error_count++;
+		frame_desc->status = -DWC_E_OVERFLOW;
+		/* Don't need to update actual_length in this case. */
+		break;
+	case DWC_OTG_HC_XFER_XACT_ERR:
+		urb->error_count++;
+		frame_desc->status = -DWC_E_PROTOCOL;
+		frame_desc->actual_length =
+		    get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL);
+		
+		/* non DWORD-aligned buffer case handling. */
+		if (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) {
+			dwc_memcpy(urb->buf + frame_desc->offset + qtd->isoc_split_offset, 
+				   hc->qh->dw_align_buf, frame_desc->actual_length);
+		}
+		/* Skip whole frame */
+		if (hc->qh->do_split && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) && 
+				hc->ep_is_in && hcd->core_if->dma_enable) {
+			qtd->complete_split = 0;
+			qtd->isoc_split_offset = 0;
+		}
+			
+		break;
+	default:
+		DWC_ASSERT(1, "Unhandled _halt_status (%d)\n", halt_status);
+		break;
+	}
+	if (++qtd->isoc_frame_index == urb->packet_count) {
+		/*
+		 * urb->status is not used for isoc transfers.
+		 * The individual frame_desc statuses are used instead.
+		 */
+		hcd->fops->complete(hcd, urb->priv, urb, 0);
+		ret_val = DWC_OTG_HC_XFER_URB_COMPLETE;
+	} else {
+		ret_val = DWC_OTG_HC_XFER_COMPLETE;
+	}
+	return ret_val;
+}
+
+/**
+ * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic
+ * QHs, removes the QH from the active non-periodic schedule. If any QTDs are
+ * still linked to the QH, the QH is added to the end of the inactive
+ * non-periodic schedule. For periodic QHs, removes the QH from the periodic
+ * schedule if no more QTDs are linked to the QH.
+ */
+static void deactivate_qh(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, int free_qtd)
+{
+	int continue_split = 0;
+	dwc_otg_qtd_t *qtd;
+
+	DWC_DEBUGPL(DBG_HCDV, "  %s(%p,%p,%d)\n", __func__, hcd, qh, free_qtd);
+
+	qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
+
+	if (qtd->complete_split) {
+		continue_split = 1;
+	} else if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_MID ||
+		   qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_END) {
+		continue_split = 1;
+	}
+
+	if (free_qtd) {
+		dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
+		continue_split = 0;
+	}
+
+	qh->channel = NULL;
+	dwc_otg_hcd_qh_deactivate(hcd, qh, continue_split);
+}
+
+/**
+ * Releases a host channel for use by other transfers. Attempts to select and
+ * queue more transactions since at least one host channel is available.
+ *
+ * @param hcd The HCD state structure.
+ * @param hc The host channel to release.
+ * @param qtd The QTD associated with the host channel. This QTD may be freed
+ * if the transfer is complete or an error has occurred.
+ * @param halt_status Reason the channel is being released. This status
+ * determines the actions taken by this function.
+ */
+static void release_channel(dwc_otg_hcd_t * hcd,
+			    dwc_hc_t * hc,
+			    dwc_otg_qtd_t * qtd,
+			    dwc_otg_halt_status_e halt_status)
+{
+	dwc_otg_transaction_type_e tr_type;
+	int free_qtd;
+
+	DWC_DEBUGPL(DBG_HCDV, "  %s: channel %d, halt_status %d, xfer_len %d\n",
+		    __func__, hc->hc_num, halt_status, hc->xfer_len);
+
+#ifdef HW2937_WORKAROUND
+	if (hcd->hw2937_assigned_channels & (1<<hc->hc_num))
+	{
+		if ((hcd->hw2937_assigned_channels &= ~(1<<hc->hc_num)) == 0)
+			hcd->hw2937_xfer_mode = HW2937_XFER_MODE_IDLE;
+		DWC_DEBUGPL(DBG_HW2937, " release %d, hw2937_ac -> %x\n", hc->hc_num, hcd->hw2937_assigned_channels);
+	}
+	else
+	{
+		DWC_DEBUGPL(DBG_ANY, " Unexpected release %d (hw2937_ac = %x)\n", hc->hc_num, hcd->hw2937_assigned_channels);
+	}
+#endif
+
+	switch (halt_status) {
+	case DWC_OTG_HC_XFER_URB_COMPLETE:
+		free_qtd = 1;
+		break;
+	case DWC_OTG_HC_XFER_AHB_ERR:
+	case DWC_OTG_HC_XFER_STALL:
+	case DWC_OTG_HC_XFER_BABBLE_ERR:
+		free_qtd = 1;
+		break;
+	case DWC_OTG_HC_XFER_XACT_ERR:
+		if (qtd->error_count >= 3) {
+			DWC_DEBUGPL(DBG_HCDV,
+				    "  Complete URB with transaction error\n");
+			free_qtd = 1;
+			qtd->urb->status = -DWC_E_PROTOCOL;
+			hcd->fops->complete(hcd, qtd->urb->priv,
+					    qtd->urb, -DWC_E_PROTOCOL);
+		} else {
+			free_qtd = 0;
+		}
+		break;
+	case DWC_OTG_HC_XFER_URB_DEQUEUE:
+		/*
+		 * The QTD has already been removed and the QH has been
+		 * deactivated. Don't want to do anything except release the
+		 * host channel and try to queue more transfers.
+		 */
+		goto cleanup;
+	case DWC_OTG_HC_XFER_NO_HALT_STATUS:
+		free_qtd = 0;
+		break;
+	default:
+		free_qtd = 0;
+		break;
+	}
+
+	deactivate_qh(hcd, hc->qh, free_qtd);
+
+      cleanup:
+	/*
+	 * Release the host channel for use by other transfers. The cleanup
+	 * function clears the channel interrupt enables and conditions, so
+	 * there's no need to clear the Channel Halted interrupt separately.
+	 */
+	dwc_otg_hc_cleanup(hcd->core_if, hc);
+	DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
+
+	switch (hc->ep_type) {
+	case DWC_OTG_EP_TYPE_CONTROL:
+	case DWC_OTG_EP_TYPE_BULK:
+		hcd->non_periodic_channels--;
+		break;
+
+	default:
+		/*
+		 * Don't release reservations for periodic channels here.
+		 * That's done when a periodic transfer is descheduled (i.e.
+		 * when the QH is removed from the periodic schedule).
+		 */
+		break;
+	}
+
+	/* Try to queue more transfers now that there's a free channel. */
+	tr_type = dwc_otg_hcd_select_transactions(hcd);
+	if (tr_type != DWC_OTG_TRANSACTION_NONE) {
+		dwc_otg_hcd_queue_transactions(hcd, tr_type);
+	}
+}
+
+
+/**
+ * Halts a host channel. If the channel cannot be halted immediately because
+ * the request queue is full, this function ensures that the FIFO empty
+ * interrupt for the appropriate queue is enabled so that the halt request can
+ * be queued when there is space in the request queue.
+ *
+ * This function may also be called in DMA mode. In that case, the channel is
+ * simply released since the core always halts the channel automatically in
+ * DMA mode.
+ */
+static void halt_channel(dwc_otg_hcd_t * hcd,
+			 dwc_hc_t * hc,
+			 dwc_otg_qtd_t * qtd, dwc_otg_halt_status_e halt_status)
+{
+	if (hcd->core_if->dma_enable) {
+		release_channel(hcd, hc, qtd, halt_status);
+		return;
+	}
+
+	/* Slave mode processing... */
+	dwc_otg_hc_halt(hcd->core_if, hc, halt_status);
+
+	if (hc->halt_on_queue) {
+		gintmsk_data_t gintmsk = {.d32 = 0 };
+		dwc_otg_core_global_regs_t *global_regs;
+		global_regs = hcd->core_if->core_global_regs;
+
+		if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
+		    hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
+			/*
+			 * Make sure the Non-periodic Tx FIFO empty interrupt
+			 * is enabled so that the non-periodic schedule will
+			 * be processed.
+			 */
+			gintmsk.b.nptxfempty = 1;
+			dwc_modify_reg32(&global_regs->gintmsk, 0, gintmsk.d32);
+		} else {
+			/*
+			 * Move the QH from the periodic queued schedule to
+			 * the periodic assigned schedule. This allows the
+			 * halt to be queued when the periodic schedule is
+			 * processed.
+			 */
+			DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
+					   &hc->qh->qh_list_entry);
+
+			/*
+			 * Make sure the Periodic Tx FIFO Empty interrupt is
+			 * enabled so that the periodic schedule will be
+			 * processed.
+			 */
+			gintmsk.b.ptxfempty = 1;
+			dwc_modify_reg32(&global_regs->gintmsk, 0, gintmsk.d32);
+		}
+	}
+}
+
+/**
+ * Performs common cleanup for non-periodic transfers after a Transfer
+ * Complete interrupt. This function should be called after any endpoint type
+ * specific handling is finished to release the host channel.
+ */
+static void complete_non_periodic_xfer(dwc_otg_hcd_t * hcd,
+				       dwc_hc_t * hc,
+				       dwc_otg_hc_regs_t * hc_regs,
+				       dwc_otg_qtd_t * qtd,
+				       dwc_otg_halt_status_e halt_status)
+{
+	hcint_data_t hcint;
+
+	qtd->error_count = 0;
+
+	hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
+	if (hcint.b.nyet) {
+		/*
+		 * Got a NYET on the last transaction of the transfer. This
+		 * means that the endpoint should be in the PING state at the
+		 * beginning of the next transfer.
+		 */
+		hc->qh->ping_state = 1;
+		clear_hc_int(hc_regs, nyet);
+	}
+
+	/*
+	 * Always halt and release the host channel to make it available for
+	 * more transfers. There may still be more phases for a control
+	 * transfer or more data packets for a bulk transfer at this point,
+	 * but the host channel is still halted. A channel will be reassigned
+	 * to the transfer when the non-periodic schedule is processed after
+	 * the channel is released. This allows transactions to be queued
+	 * properly via dwc_otg_hcd_queue_transactions, which also enables the
+	 * Tx FIFO Empty interrupt if necessary.
+	 */
+	if (hc->ep_is_in) {
+		/*
+		 * IN transfers in Slave mode require an explicit disable to
+		 * halt the channel. (In DMA mode, this call simply releases
+		 * the channel.)
+		 */
+		halt_channel(hcd, hc, qtd, halt_status);
+	} else {
+		/*
+		 * The channel is automatically disabled by the core for OUT
+		 * transfers in Slave mode.
+		 */
+		release_channel(hcd, hc, qtd, halt_status);
+	}
+}
+
+/**
+ * Performs common cleanup for periodic transfers after a Transfer Complete
+ * interrupt. This function should be called after any endpoint type specific
+ * handling is finished to release the host channel.
+ */
+static void complete_periodic_xfer(dwc_otg_hcd_t * hcd,
+				   dwc_hc_t * hc,
+				   dwc_otg_hc_regs_t * hc_regs,
+				   dwc_otg_qtd_t * qtd,
+				   dwc_otg_halt_status_e halt_status)
+{
+	hctsiz_data_t hctsiz;
+	qtd->error_count = 0;
+
+	hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
+	if (!hc->ep_is_in || hctsiz.b.pktcnt == 0) {
+		/* Core halts channel in these cases. */
+		release_channel(hcd, hc, qtd, halt_status);
+	} else {
+		/* Flush any outstanding requests from the Tx queue. */
+		halt_channel(hcd, hc, qtd, halt_status);
+	}
+}
+
+static int32_t handle_xfercomp_isoc_split_in(dwc_otg_hcd_t * hcd,
+				       	     dwc_hc_t * hc,
+				       	     dwc_otg_hc_regs_t * hc_regs,
+				       	     dwc_otg_qtd_t * qtd)
+{
+	uint32_t len;	
+	struct dwc_otg_hcd_iso_packet_desc *frame_desc;
+	frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
+				
+	len = get_actual_xfer_length(hc, hc_regs, qtd,
+			     	     DWC_OTG_HC_XFER_COMPLETE,
+			     	     NULL);
+		     
+	if (!len) {
+		qtd->complete_split = 0;
+		qtd->isoc_split_offset = 0;
+		return 0;
+	}
+	frame_desc->actual_length += len;
+	
+	if (hc->align_buff && len)
+		dwc_memcpy(qtd->urb->buf + frame_desc->offset + qtd->isoc_split_offset, 
+								hc->qh->dw_align_buf, 
+								len);
+	qtd->isoc_split_offset += len;
+	
+	if (frame_desc->length == frame_desc->actual_length) {
+		frame_desc->status = 0;
+		qtd->isoc_frame_index++;
+		qtd->complete_split = 0;
+		qtd->isoc_split_offset = 0;
+	}
+			
+	if (qtd->isoc_frame_index == qtd->urb->packet_count) {
+		hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
+		release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
+	} else {
+		release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
+	}
+	
+	return 1; /* Indicates that channel released */
+}
+/**
+ * Handles a host channel Transfer Complete interrupt. This handler may be
+ * called in either DMA mode or Slave mode.
+ */
+static int32_t handle_hc_xfercomp_intr(dwc_otg_hcd_t * hcd,
+				       dwc_hc_t * hc,
+				       dwc_otg_hc_regs_t * hc_regs,
+				       dwc_otg_qtd_t * qtd)
+{
+	int urb_xfer_done;
+	dwc_otg_halt_status_e halt_status = DWC_OTG_HC_XFER_COMPLETE;
+	dwc_otg_hcd_urb_t *urb = qtd->urb;
+	int pipe_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
+
+	DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
+		    "Transfer Complete--\n", hc->hc_num);
+
+	if (hcd->core_if->dma_desc_enable) {
+		dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, halt_status);
+		if (pipe_type == UE_ISOCHRONOUS) {
+			/* Do not disable the interrupt, just clear it */	
+			clear_hc_int(hc_regs, xfercomp);
+			return 1;
+		}
+		goto handle_xfercomp_done;
+	}
+
+	/*
+	 * Handle xfer complete on CSPLIT.
+	 */
+
+	if (hc->qh->do_split) {
+		if ((hc->ep_type == DWC_OTG_EP_TYPE_ISOC) && hc->ep_is_in && hcd->core_if->dma_enable) {
+			if (qtd->complete_split && handle_xfercomp_isoc_split_in(hcd, hc, hc_regs, qtd))
+				goto handle_xfercomp_done;
+		}
+		else {
+                        qtd->complete_split = 0;
+                }
+	}
+
+	/* Update the QTD and URB states. */
+	switch (pipe_type) {
+	case UE_CONTROL:
+		switch (qtd->control_phase) {
+		case DWC_OTG_CONTROL_SETUP:
+			if (urb->length > 0) {
+				qtd->control_phase = DWC_OTG_CONTROL_DATA;
+			} else {
+				qtd->control_phase = DWC_OTG_CONTROL_STATUS;
+			}
+			DWC_DEBUGPL(DBG_HCDV,
+				    "  Control setup transaction done\n");
+			halt_status = DWC_OTG_HC_XFER_COMPLETE;
+			break;
+		case DWC_OTG_CONTROL_DATA:{
+				urb_xfer_done =
+				    update_urb_state_xfer_comp(hc, hc_regs, urb,
+							       qtd);
+				if (urb_xfer_done) {
+					qtd->control_phase =
+					    DWC_OTG_CONTROL_STATUS;
+					DWC_DEBUGPL(DBG_HCDV,
+						    "  Control data transfer done\n");
+				} else {
+					dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
+				}
+				halt_status = DWC_OTG_HC_XFER_COMPLETE;
+				break;
+			}
+		case DWC_OTG_CONTROL_STATUS:
+			DWC_DEBUGPL(DBG_HCDV, "  Control transfer complete\n");
+			if (urb->status == -DWC_E_IN_PROGRESS) {
+				urb->status = 0;
+			}
+			hcd->fops->complete(hcd, urb->priv, urb, urb->status);
+			halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
+			break;
+		}
+
+		complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
+		break;
+	case UE_BULK:
+		DWC_DEBUGPL(DBG_HCDV, "  Bulk transfer complete\n");
+		urb_xfer_done =
+		    update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
+		if (urb_xfer_done) {
+			hcd->fops->complete(hcd, urb->priv, urb, urb->status);
+			halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
+		} else {
+			halt_status = DWC_OTG_HC_XFER_COMPLETE;
+		}
+
+		dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
+		complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
+		break;
+	case UE_INTERRUPT:
+		DWC_DEBUGPL(DBG_HCDV, "  Interrupt transfer complete\n");
+		update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
+
+		/*
+		 * Interrupt URB is done on the first transfer complete
+		 * interrupt.
+		 */
+		hcd->fops->complete(hcd, urb->priv, urb, urb->status);
+		dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
+		complete_periodic_xfer(hcd, hc, hc_regs, qtd,
+				       DWC_OTG_HC_XFER_URB_COMPLETE);
+		break;
+	case UE_ISOCHRONOUS:
+		DWC_DEBUGPL(DBG_HCDV, "  Isochronous transfer complete\n");
+		if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_ALL) {
+			halt_status =
+			    update_isoc_urb_state(hcd, hc, hc_regs, qtd,
+						  DWC_OTG_HC_XFER_COMPLETE);
+		}
+		complete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
+		break;
+	}
+
+handle_xfercomp_done:
+	disable_hc_int(hc_regs, xfercompl);
+
+	return 1;
+}
+
+/**
+ * Handles a host channel STALL interrupt. This handler may be called in
+ * either DMA mode or Slave mode.
+ */
+static int32_t handle_hc_stall_intr(dwc_otg_hcd_t * hcd,
+				    dwc_hc_t * hc,
+				    dwc_otg_hc_regs_t * hc_regs,
+				    dwc_otg_qtd_t * qtd)
+{
+	dwc_otg_hcd_urb_t *urb = qtd->urb;
+	int pipe_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
+
+	DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
+		    "STALL Received--\n", hc->hc_num);
+
+	if (hcd->core_if->dma_desc_enable) {
+		dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, DWC_OTG_HC_XFER_STALL);
+		goto handle_stall_done;
+	}
+
+	if (pipe_type == UE_CONTROL) {
+		hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_PIPE);
+	}
+
+	if (pipe_type == UE_BULK || pipe_type == UE_INTERRUPT) {
+		hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_PIPE);
+		/*
+		 * USB protocol requires resetting the data toggle for bulk
+		 * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT)
+		 * setup command is issued to the endpoint. Anticipate the
+		 * CLEAR_FEATURE command since a STALL has occurred and reset
+		 * the data toggle now.
+		 */
+		hc->qh->data_toggle = 0;
+	}
+
+	halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_STALL);
+
+handle_stall_done:
+	disable_hc_int(hc_regs, stall);
+
+	return 1;
+}
+
+/*
+ * Updates the state of the URB when a transfer has been stopped due to an
+ * abnormal condition before the transfer completes. Modifies the
+ * actual_length field of the URB to reflect the number of bytes that have
+ * actually been transferred via the host channel.
+ */
+static void update_urb_state_xfer_intr(dwc_hc_t * hc,
+				       dwc_otg_hc_regs_t * hc_regs,
+				       dwc_otg_hcd_urb_t * urb,
+				       dwc_otg_qtd_t * qtd,
+				       dwc_otg_halt_status_e halt_status)
+{
+	uint32_t bytes_transferred = get_actual_xfer_length(hc, hc_regs, qtd,
+							    halt_status, NULL);
+	/* non DWORD-aligned buffer case handling. */
+	if (hc->align_buff && bytes_transferred && hc->ep_is_in) {
+		dwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf, bytes_transferred);
+	}
+	
+	urb->actual_length += bytes_transferred;
+
+#ifdef DEBUG
+	{
+		hctsiz_data_t hctsiz;
+		hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
+		DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
+			    __func__, (hc->ep_is_in ? "IN" : "OUT"),
+			    hc->hc_num);
+		DWC_DEBUGPL(DBG_HCDV, "  hc->start_pkt_count %d\n",
+			    hc->start_pkt_count);
+		DWC_DEBUGPL(DBG_HCDV, "  hctsiz.pktcnt %d\n", hctsiz.b.pktcnt);
+		DWC_DEBUGPL(DBG_HCDV, "  hc->max_packet %d\n", hc->max_packet);
+		DWC_DEBUGPL(DBG_HCDV, "  bytes_transferred %d\n",
+			    bytes_transferred);
+		DWC_DEBUGPL(DBG_HCDV, "  urb->actual_length %d\n",
+			    urb->actual_length);
+		DWC_DEBUGPL(DBG_HCDV, "  urb->transfer_buffer_length %d\n",
+			    urb->length);
+	}
+#endif
+}
+
+/**
+ * Handles a host channel NAK interrupt. This handler may be called in either
+ * DMA mode or Slave mode.
+ */
+static int32_t handle_hc_nak_intr(dwc_otg_hcd_t * hcd,
+				  dwc_hc_t * hc,
+				  dwc_otg_hc_regs_t * hc_regs,
+				  dwc_otg_qtd_t * qtd)
+{
+	DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
+		    "NAK Received--\n", hc->hc_num);
+
+	/*
+	 * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and
+	 * interrupt.  Re-start the SSPLIT transfer.
+	 */
+	if (hc->do_split) {
+		if (hc->complete_split) {
+			qtd->error_count = 0;
+		}
+		qtd->complete_split = 0;
+		halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
+		goto handle_nak_done;
+	}
+
+	switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
+	case UE_CONTROL:
+	case UE_BULK:
+		if (hcd->core_if->dma_enable && hc->ep_is_in) {
+#ifdef HW2937_WORKAROUND
+			if (hc->halt_status == DWC_OTG_HC_XFER_PAUSE_IN) {
+				halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
+			}
+#endif
+			/*
+			 * NAK interrupts are enabled on bulk/control IN
+			 * transfers in DMA mode for the sole purpose of
+			 * resetting the error count after a transaction error
+			 * occurs. The core will continue transferring data.
+			 */
+			qtd->error_count = 0;
+			goto handle_nak_done;
+		}
+
+		/*
+		 * NAK interrupts normally occur during OUT transfers in DMA
+		 * or Slave mode. For IN transfers, more requests will be
+		 * queued as request queue space is available.
+		 */
+		qtd->error_count = 0;
+
+		if (!hc->qh->ping_state) {
+			update_urb_state_xfer_intr(hc, hc_regs,
+						   qtd->urb, qtd,
+						   DWC_OTG_HC_XFER_NAK);
+			dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
+
+			if (hc->speed == DWC_OTG_EP_SPEED_HIGH)
+				hc->qh->ping_state = 1;
+			}
+
+		/*
+		 * Halt the channel so the transfer can be re-started from
+		 * the appropriate point or the PING protocol will
+		 * start/continue.
+		 */
+		halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
+		break;
+	case UE_INTERRUPT:
+		qtd->error_count = 0;
+		halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
+		break;
+	case UE_ISOCHRONOUS:
+#ifdef HW2937_WORKAROUND
+		if (hc->halt_status == DWC_OTG_HC_XFER_PAUSE_IN) {
+			halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
+			break;
+		}
+#endif
+		/* Should never get called for isochronous transfers. */
+		DWC_ASSERT(1, "NACK interrupt for ISOC transfer\n");
+		break;
+	}
+
+      handle_nak_done:
+	disable_hc_int(hc_regs, nak);
+
+	return 1;
+}
+
+/**
+ * Handles a host channel ACK interrupt. This interrupt is enabled when
+ * performing the PING protocol in Slave mode, when errors occur during
+ * either Slave mode or DMA mode, and during Start Split transactions.
+ */
+static int32_t handle_hc_ack_intr(dwc_otg_hcd_t * hcd,
+				  dwc_hc_t * hc,
+				  dwc_otg_hc_regs_t * hc_regs,
+				  dwc_otg_qtd_t * qtd)
+{
+	DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
+		    "ACK Received--\n", hc->hc_num);
+
+	if (hc->do_split) {
+		/*
+		 * Handle ACK on SSPLIT.
+		 * ACK should not occur in CSPLIT.
+		 */
+		if (!hc->ep_is_in && hc->data_pid_start != DWC_OTG_HC_PID_SETUP) {
+			qtd->ssplit_out_xfer_count = hc->xfer_len;
+		}
+		if (!(hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in)) {
+			/* Don't need complete for isochronous out transfers. */
+			qtd->complete_split = 1;
+		}
+
+		/* ISOC OUT */
+		if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
+			switch (hc->xact_pos) {
+			case DWC_HCSPLIT_XACTPOS_ALL:
+				break;
+			case DWC_HCSPLIT_XACTPOS_END:
+				qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
+				qtd->isoc_split_offset = 0;
+				break;
+			case DWC_HCSPLIT_XACTPOS_BEGIN:
+			case DWC_HCSPLIT_XACTPOS_MID:
+				/*
+				 * For BEGIN or MID, calculate the length for
+				 * the next microframe to determine the correct
+				 * SSPLIT token, either MID or END.
+				 */
+				{
+					struct dwc_otg_hcd_iso_packet_desc
+					    *frame_desc;
+
+					frame_desc =
+					    &qtd->urb->iso_descs[qtd->
+									 isoc_frame_index];
+					qtd->isoc_split_offset += 188;
+
+					if ((frame_desc->length -
+					     qtd->isoc_split_offset) <= 188) {
+						qtd->isoc_split_pos =
+						    DWC_HCSPLIT_XACTPOS_END;
+					} else {
+						qtd->isoc_split_pos =
+						    DWC_HCSPLIT_XACTPOS_MID;
+					}
+
+				}
+				break;
+			}
+		} else {
+			halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
+		}
+	} else {
+		qtd->error_count = 0;
+
+		if (hc->qh->ping_state) {
+			hc->qh->ping_state = 0;
+			/*
+			 * Halt the channel so the transfer can be re-started
+			 * from the appropriate point. This only happens in
+			 * Slave mode. In DMA mode, the ping_state is cleared
+			 * when the transfer is started because the core
+			 * automatically executes the PING, then the transfer.
+			 */
+			halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
+		}
+#ifdef HW2937_WORKAROUND
+		else if (hc->halt_status == DWC_OTG_HC_XFER_PAUSE_IN) {
+			dwc_otg_hc_regs_t *hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num];
+			update_urb_state_xfer_intr(hc, hc_regs, qtd->urb, qtd, DWC_OTG_HC_XFER_PAUSE_IN);
+			dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
+			release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_PAUSE_IN);
+		}
+#endif
+	}
+
+	/*
+	 * If the ACK occurred when _not_ in the PING state, let the channel
+	 * continue transferring data after clearing the error count.
+	 */
+
+	disable_hc_int(hc_regs, ack);
+
+	return 1;
+}
+
+/**
+ * Handles a host channel NYET interrupt. This interrupt should only occur on
+ * Bulk and Control OUT endpoints and for complete split transactions. If a
+ * NYET occurs at the same time as a Transfer Complete interrupt, it is
+ * handled in the xfercomp interrupt handler, not here. This handler may be
+ * called in either DMA mode or Slave mode.
+ */
+static int32_t handle_hc_nyet_intr(dwc_otg_hcd_t * hcd,
+				   dwc_hc_t * hc,
+				   dwc_otg_hc_regs_t * hc_regs,
+				   dwc_otg_qtd_t * qtd)
+{
+	DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
+		    "NYET Received--\n", hc->hc_num);
+
+	/*
+	 * NYET on CSPLIT
+	 * re-do the CSPLIT immediately on non-periodic
+	 */
+	if (hc->do_split && hc->complete_split) {
+		if (hc->ep_is_in && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) && hcd->core_if->dma_enable) {	
+			qtd->complete_split = 0;
+			qtd->isoc_split_offset = 0;
+			if (++qtd->isoc_frame_index == qtd->urb->packet_count) {
+				hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
+				release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);	
+			}
+			else
+				release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);	
+			goto handle_nyet_done;
+		}
+		
+		if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
+		    hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
+			int frnum = dwc_otg_hcd_get_frame_number(hcd);
+
+			if (dwc_full_frame_num(frnum) !=
+			    dwc_full_frame_num(hc->qh->sched_frame)) {
+				/*
+				 * No longer in the same full speed frame.
+				 * Treat this as a transaction error.
+				 */
+#if 0
+				/** @todo Fix system performance so this can
+				 * be treated as an error. Right now complete
+				 * splits cannot be scheduled precisely enough
+				 * due to other system activity, so this error
+				 * occurs regularly in Slave mode.
+				 */
+				qtd->error_count++;
+#endif
+				qtd->complete_split = 0;
+				halt_channel(hcd, hc, qtd,
+					     DWC_OTG_HC_XFER_XACT_ERR);
+				/** @todo add support for isoc release */
+				goto handle_nyet_done;
+			}
+		}
+
+		halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);
+		goto handle_nyet_done;
+	}
+
+	hc->qh->ping_state = 1;
+	qtd->error_count = 0;
+
+	update_urb_state_xfer_intr(hc, hc_regs, qtd->urb, qtd,
+				   DWC_OTG_HC_XFER_NYET);
+	dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
+
+	/*
+	 * Halt the channel and re-start the transfer so the PING
+	 * protocol will start.
+	 */
+	halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);
+
+      handle_nyet_done:
+	disable_hc_int(hc_regs, nyet);
+	return 1;
+}
+
+/**
+ * Handles a host channel babble interrupt. This handler may be called in
+ * either DMA mode or Slave mode.
+ */
+static int32_t handle_hc_babble_intr(dwc_otg_hcd_t * hcd,
+				     dwc_hc_t * hc,
+				     dwc_otg_hc_regs_t * hc_regs,
+				     dwc_otg_qtd_t * qtd)
+{
+	DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
+		    "Babble Error--\n", hc->hc_num);
+	
+	if (hcd->core_if->dma_desc_enable) {
+		dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, DWC_OTG_HC_XFER_BABBLE_ERR);
+		goto handle_babble_done;
+	}
+
+	if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
+		hcd->fops->complete(hcd, qtd->urb->priv,
+				    qtd->urb, -DWC_E_OVERFLOW);
+		halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_BABBLE_ERR);
+	} else {
+		dwc_otg_halt_status_e halt_status;
+		halt_status = update_isoc_urb_state(hcd, hc, hc_regs, qtd,
+						    DWC_OTG_HC_XFER_BABBLE_ERR);
+		halt_channel(hcd, hc, qtd, halt_status);
+	}
+	
+handle_babble_done:
+	disable_hc_int(hc_regs, bblerr);
+	return 1;
+}
+
+/**
+ * Handles a host channel AHB error interrupt. This handler is only called in
+ * DMA mode.
+ */
+static int32_t handle_hc_ahberr_intr(dwc_otg_hcd_t * hcd,
+				     dwc_hc_t * hc,
+				     dwc_otg_hc_regs_t * hc_regs,
+				     dwc_otg_qtd_t * qtd)
+{
+	hcchar_data_t hcchar;
+	hcsplt_data_t hcsplt;
+	hctsiz_data_t hctsiz;
+	uint32_t hcdma;
+	char *pipetype, *speed;
+
+	dwc_otg_hcd_urb_t *urb = qtd->urb;
+
+	DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
+		    "AHB Error--\n", hc->hc_num);
+
+	hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+	hcsplt.d32 = dwc_read_reg32(&hc_regs->hcsplt);
+	hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
+	hcdma = dwc_read_reg32(&hc_regs->hcdma);
+
+	DWC_ERROR("AHB ERROR, Channel %d\n", hc->hc_num);
+	DWC_ERROR("  hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32);
+	DWC_ERROR("  hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma);
+	DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Enqueue\n");
+	DWC_ERROR("  Device address: %d\n",
+		  dwc_otg_hcd_get_dev_addr(&urb->pipe_info));
+	DWC_ERROR("  Endpoint: %d, %s\n",
+		  dwc_otg_hcd_get_ep_num(&urb->pipe_info),
+		  (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT"));
+	
+
+	switch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) {
+case UE_CONTROL:
+		pipetype = "CONTROL"; 
+		break; 
+	case UE_BULK:
+		pipetype = "BULK"; 
+		break; 
+	case UE_INTERRUPT:
+		pipetype = "INTERRUPT"; 
+		break; 
+	case UE_ISOCHRONOUS:
+		pipetype = "ISOCHRONOUS"; 
+		break; 
+	default:
+		pipetype = "UNKNOWN"; 
+		break;
+	}
+	
+	DWC_ERROR("  Endpoint type: %s\n", pipetype);
+
+	switch (hc->speed) {
+	case DWC_OTG_EP_SPEED_HIGH:
+		speed = "HIGH"; 
+		break; 
+	case DWC_OTG_EP_SPEED_FULL:
+		speed = "FULL"; 
+		break; 
+	case DWC_OTG_EP_SPEED_LOW:
+		speed = "LOW"; 
+		break; 
+	default:
+		speed = "UNKNOWN"; 
+		break;
+	};	
+
+	DWC_ERROR("  Speed: %s\n", speed);
+	
+	DWC_ERROR("  Max packet size: %d\n",
+		  dwc_otg_hcd_get_mps(&urb->pipe_info));
+	DWC_ERROR("  Data buffer length: %d\n", urb->length);
+	DWC_ERROR("  Transfer buffer: %p, Transfer DMA: %p\n",
+		  urb->buf, (void *)urb->dma);
+	DWC_ERROR("  Setup buffer: %p, Setup DMA: %p\n",
+		  urb->setup_packet, (void *)urb->setup_dma);
+	DWC_ERROR("  Interval: %d\n", urb->interval);
+
+	/* Core haltes the channel for Descriptor DMA mode */
+	if (hcd->core_if->dma_desc_enable) {
+		dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, DWC_OTG_HC_XFER_AHB_ERR);
+		goto handle_ahberr_done;
+	}
+
+	hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_IO);
+
+	/*
+	 * Force a channel halt. Don't call halt_channel because that won't
+	 * write to the HCCHARn register in DMA mode to force the halt.
+	 */
+	dwc_otg_hc_halt(hcd->core_if, hc, DWC_OTG_HC_XFER_AHB_ERR);
+handle_ahberr_done:
+	disable_hc_int(hc_regs, ahberr);
+	return 1;
+}
+
+/**
+ * Handles a host channel transaction error interrupt. This handler may be
+ * called in either DMA mode or Slave mode.
+ */
+static int32_t handle_hc_xacterr_intr(dwc_otg_hcd_t * hcd,
+				      dwc_hc_t * hc,
+				      dwc_otg_hc_regs_t * hc_regs,
+				      dwc_otg_qtd_t * qtd)
+{
+	DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
+		    "Transaction Error--\n", hc->hc_num);
+
+	if (hcd->core_if->dma_desc_enable) {
+		dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, DWC_OTG_HC_XFER_XACT_ERR);
+		goto handle_xacterr_done;
+	}
+
+	switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
+	case UE_CONTROL:
+	case UE_BULK:
+		qtd->error_count++;
+		if (!hc->qh->ping_state) {
+
+			update_urb_state_xfer_intr(hc, hc_regs,
+						   qtd->urb, qtd,
+						   DWC_OTG_HC_XFER_XACT_ERR);
+			dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
+			if (!hc->ep_is_in && hc->speed == DWC_OTG_EP_SPEED_HIGH) {
+				hc->qh->ping_state = 1;
+			}
+		}
+
+		/*
+		 * Halt the channel so the transfer can be re-started from
+		 * the appropriate point or the PING protocol will start.
+		 */
+		halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
+		break;
+	case UE_INTERRUPT:
+		qtd->error_count++;
+		if (hc->do_split && hc->complete_split) {
+			qtd->complete_split = 0;
+		}
+		halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
+		break;
+	case UE_ISOCHRONOUS:
+		{
+			dwc_otg_halt_status_e halt_status;
+			halt_status =
+			    update_isoc_urb_state(hcd, hc, hc_regs, qtd,
+						  DWC_OTG_HC_XFER_XACT_ERR);
+
+			halt_channel(hcd, hc, qtd, halt_status);
+		}
+		break;
+	}
+handle_xacterr_done:
+	disable_hc_int(hc_regs, xacterr);
+
+	return 1;
+}
+
+/**
+ * Handles a host channel frame overrun interrupt. This handler may be called
+ * in either DMA mode or Slave mode.
+ */
+static int32_t handle_hc_frmovrun_intr(dwc_otg_hcd_t * hcd,
+				       dwc_hc_t * hc,
+				       dwc_otg_hc_regs_t * hc_regs,
+				       dwc_otg_qtd_t * qtd)
+{
+	DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
+		    "Frame Overrun--\n", hc->hc_num);
+
+	switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
+	case UE_CONTROL:
+	case UE_BULK:
+		break;
+	case UE_INTERRUPT:
+		halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_FRAME_OVERRUN);
+		break;
+	case UE_ISOCHRONOUS:
+		{
+			dwc_otg_halt_status_e halt_status;
+			halt_status =
+			    update_isoc_urb_state(hcd, hc, hc_regs, qtd,
+						  DWC_OTG_HC_XFER_FRAME_OVERRUN);
+
+			halt_channel(hcd, hc, qtd, halt_status);
+		}
+		break;
+	}
+
+	disable_hc_int(hc_regs, frmovrun);
+
+	return 1;
+}
+
+/**
+ * Handles a host channel data toggle error interrupt. This handler may be
+ * called in either DMA mode or Slave mode.
+ */
+static int32_t handle_hc_datatglerr_intr(dwc_otg_hcd_t * hcd,
+					 dwc_hc_t * hc,
+					 dwc_otg_hc_regs_t * hc_regs,
+					 dwc_otg_qtd_t * qtd)
+{
+	DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
+		    "Data Toggle Error--\n", hc->hc_num);
+
+	if (hc->ep_is_in) {
+		qtd->error_count = 0;
+	} else {
+		DWC_ERROR("Data Toggle Error on OUT transfer,"
+			  "channel %d\n", hc->hc_num);
+	}
+
+	disable_hc_int(hc_regs, datatglerr);
+
+	return 1;
+}
+
+#ifdef DEBUG
+/**
+ * This function is for debug only. It checks that a valid halt status is set
+ * and that HCCHARn.chdis is clear. If there's a problem, corrective action is
+ * taken and a warning is issued.
+ * @return 1 if halt status is ok, 0 otherwise.
+ */
+static inline int halt_status_ok(dwc_otg_hcd_t * hcd,
+				 dwc_hc_t * hc,
+				 dwc_otg_hc_regs_t * hc_regs,
+				 dwc_otg_qtd_t * qtd)
+{
+	hcchar_data_t hcchar;
+	hctsiz_data_t hctsiz;
+	hcint_data_t hcint;
+	hcintmsk_data_t hcintmsk;
+	hcsplt_data_t hcsplt;
+
+	if (hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS) {
+		/*
+		 * This code is here only as a check. This condition should
+		 * never happen. Ignore the halt if it does occur.
+		 */
+		hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+		hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
+		hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
+		hcintmsk.d32 = dwc_read_reg32(&hc_regs->hcintmsk);
+		hcsplt.d32 = dwc_read_reg32(&hc_regs->hcsplt);
+		DWC_WARN
+		    ("%s: hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS, "
+		     "channel %d, hcchar 0x%08x, hctsiz 0x%08x, "
+		     "hcint 0x%08x, hcintmsk 0x%08x, "
+		     "hcsplt 0x%08x, qtd->complete_split %d\n", __func__,
+		     hc->hc_num, hcchar.d32, hctsiz.d32, hcint.d32,
+		     hcintmsk.d32, hcsplt.d32, qtd->complete_split);
+
+		DWC_WARN("%s: no halt status, channel %d, ignoring interrupt\n",
+			 __func__, hc->hc_num);
+		DWC_WARN("\n");
+		clear_hc_int(hc_regs, chhltd);
+		return 0;
+	}
+
+	/*
+	 * This code is here only as a check. hcchar.chdis should
+	 * never be set when the halt interrupt occurs. Halt the
+	 * channel again if it does occur.
+	 */
+	hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+	if (hcchar.b.chdis) {
+		DWC_WARN("%s: hcchar.chdis set unexpectedly, "
+			 "hcchar 0x%08x, trying to halt again\n",
+			 __func__, hcchar.d32);
+		clear_hc_int(hc_regs, chhltd);
+		hc->halt_pending = 0;
+		halt_channel(hcd, hc, qtd, hc->halt_status);
+		return 0;
+	}
+
+	return 1;
+}
+#endif
+
+/**
+ * Handles a host Channel Halted interrupt in DMA mode. This handler
+ * determines the reason the channel halted and proceeds accordingly.
+ */
+static void handle_hc_chhltd_intr_dma(dwc_otg_hcd_t * hcd,
+				      dwc_hc_t * hc,
+				      dwc_otg_hc_regs_t * hc_regs,
+				      dwc_otg_qtd_t * qtd)
+{
+	hcint_data_t hcint;
+	hcintmsk_data_t hcintmsk;
+	int out_nak_enh = 0;
+
+	/* For core with OUT NAK enhancement, the flow for high-
+	 * speed CONTROL/BULK OUT is handled a little differently.
+	 */
+	if (hcd->core_if->snpsid >= OTG_CORE_REV_2_71a) {
+		if (hc->speed == DWC_OTG_EP_SPEED_HIGH && !hc->ep_is_in &&
+		    (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
+		     hc->ep_type == DWC_OTG_EP_TYPE_BULK)) {
+			out_nak_enh = 1;
+		}
+	}
+
+	if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
+	    (hc->halt_status == DWC_OTG_HC_XFER_AHB_ERR && !hcd->core_if->dma_desc_enable)) {
+		/*
+		 * Just release the channel. A dequeue can happen on a
+		 * transfer timeout. In the case of an AHB Error, the channel
+		 * was forced to halt because there's no way to gracefully
+		 * recover.
+		 */
+		if (hcd->core_if->dma_desc_enable)
+			dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, hc->halt_status);
+		else
+			release_channel(hcd, hc, qtd, hc->halt_status);
+		return;
+	}
+
+	/* Read the HCINTn register to determine the cause for the halt. */
+	hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
+	hcintmsk.d32 = dwc_read_reg32(&hc_regs->hcintmsk);
+
+	if (hcint.b.xfercomp) {
+		/** @todo This is here because of a possible hardware bug.  Spec
+		 * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT
+		 * interrupt w/ACK bit set should occur, but I only see the
+		 * XFERCOMP bit, even with it masked out.  This is a workaround
+		 * for that behavior.  Should fix this when hardware is fixed.
+		 */
+		if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
+			handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
+		}
+		handle_hc_xfercomp_intr(hcd, hc, hc_regs, qtd);
+	} else if (hcint.b.stall) {
+		handle_hc_stall_intr(hcd, hc, hc_regs, qtd);
+	} else if (hcint.b.xacterr && !hcd->core_if->dma_desc_enable) {
+		if (out_nak_enh) {
+			if (hcint.b.nyet || hcint.b.nak || hcint.b.ack) {
+				DWC_DEBUG("XactErr with NYET/NAK/ACK\n");
+				qtd->error_count = 0;
+			} else {
+				DWC_DEBUG("XactErr without NYET/NAK/ACK\n");
+			}
+		}
+
+		/*
+		 * Must handle xacterr before nak or ack. Could get a xacterr
+		 * at the same time as either of these on a BULK/CONTROL OUT
+		 * that started with a PING. The xacterr takes precedence.
+		 */
+		handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
+	} else if (hcint.b.xcs_xact && hcd->core_if->dma_desc_enable) {
+		handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
+ 	} else if (hcint.b.ahberr && hcd->core_if->dma_desc_enable) {	 
+		handle_hc_ahberr_intr(hcd, hc, hc_regs, qtd);
+	} else if (hcint.b.bblerr) {
+		handle_hc_babble_intr(hcd, hc, hc_regs, qtd);
+	} else if (hcint.b.frmovrun) {
+		handle_hc_frmovrun_intr(hcd, hc, hc_regs, qtd);
+	} else if (!out_nak_enh) {
+		if (hcint.b.nyet) {
+			/*
+			 * Must handle nyet before nak or ack. Could get a nyet at the
+			 * same time as either of those on a BULK/CONTROL OUT that
+			 * started with a PING. The nyet takes precedence.
+			 */
+			handle_hc_nyet_intr(hcd, hc, hc_regs, qtd);
+		} else if (hcint.b.nak && !hcintmsk.b.nak) {
+			/*
+			 * If nak is not masked, it's because a non-split IN transfer
+			 * is in an error state. In that case, the nak is handled by
+			 * the nak interrupt handler, not here. Handle nak here for
+			 * BULK/CONTROL OUT transfers, which halt on a NAK to allow
+			 * rewinding the buffer pointer.
+			 */
+			handle_hc_nak_intr(hcd, hc, hc_regs, qtd);
+		} else if (hcint.b.ack && !hcintmsk.b.ack) {
+			/*
+			 * If ack is not masked, it's because a non-split IN transfer
+			 * is in an error state. In that case, the ack is handled by
+			 * the ack interrupt handler, not here. Handle ack here for
+			 * split transfers. Start splits halt on ACK.
+			 */
+			handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
+		} else {
+			if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
+			    hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
+				/*
+				 * A periodic transfer halted with no other channel
+				 * interrupts set. Assume it was halted by the core
+				 * because it could not be completed in its scheduled
+				 * (micro)frame.
+				 */
+#ifdef DEBUG
+				DWC_PRINTF
+				    ("%s: Halt channel %d (assume incomplete periodic transfer)\n",
+				     __func__, hc->hc_num);
+#endif
+				halt_channel(hcd, hc, qtd,
+					     DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE);
+			} else {
+				DWC_ERROR
+				    ("%s: Channel %d, DMA Mode -- ChHltd set, but reason "
+				     "for halting is unknown, hcint 0x%08x, intsts 0x%08x\n",
+				     __func__, hc->hc_num, hcint.d32,
+				     dwc_read_reg32(&hcd->core_if->
+						    core_global_regs->gintsts));
+			}
+	
+		}
+	} else {
+		DWC_PRINTF("NYET/NAK/ACK/other in non-error case, 0x%08x\n",
+			   hcint.d32);
+	}
+}
+
+/**
+ * Handles a host channel Channel Halted interrupt.
+ *
+ * In slave mode, this handler is called only when the driver specifically
+ * requests a halt. This occurs during handling other host channel interrupts
+ * (e.g. nak, xacterr, stall, nyet, etc.).
+ *
+ * In DMA mode, this is the interrupt that occurs when the core has finished
+ * processing a transfer on a channel. Other host channel interrupts (except
+ * ahberr) are disabled in DMA mode.
+ */
+static int32_t handle_hc_chhltd_intr(dwc_otg_hcd_t * hcd,
+				     dwc_hc_t * hc,
+				     dwc_otg_hc_regs_t * hc_regs,
+				     dwc_otg_qtd_t * qtd)
+{
+	DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
+		    "Channel Halted--\n", hc->hc_num);
+
+	if (hcd->core_if->dma_enable) {
+		handle_hc_chhltd_intr_dma(hcd, hc, hc_regs, qtd);
+	} else {
+#ifdef DEBUG
+		if (!halt_status_ok(hcd, hc, hc_regs, qtd)) {
+			return 1;
+		}
+#endif
+		release_channel(hcd, hc, qtd, hc->halt_status);
+	}
+
+	return 1;
+}
+
+/** Handles interrupt for a specific Host Channel */
+int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t * dwc_otg_hcd, uint32_t num)
+{
+	int retval = 0;
+	hcint_data_t hcint;
+	hcintmsk_data_t hcintmsk;
+	dwc_hc_t *hc;
+	dwc_otg_hc_regs_t *hc_regs;
+	dwc_otg_qtd_t *qtd;
+
+	DWC_DEBUGPL(DBG_HCDV, "--Host Channel Interrupt--, Channel %d\n", num);
+
+	hc = dwc_otg_hcd->hc_ptr_array[num];
+	hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[num];
+	qtd = DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list);
+
+	hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
+	hcintmsk.d32 = dwc_read_reg32(&hc_regs->hcintmsk);
+	DWC_DEBUGPL(DBG_HCDV,
+		    "  hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
+		    hcint.d32, hcintmsk.d32, (hcint.d32 & hcintmsk.d32));
+	hcint.d32 = hcint.d32 & hcintmsk.d32;
+
+	if (!dwc_otg_hcd->core_if->dma_enable) {
+		if (hcint.b.chhltd && hcint.d32 != 0x2) {
+			hcint.b.chhltd = 0;
+		}
+	}
+
+	if (hcint.b.xfercomp) {
+		retval |=
+		    handle_hc_xfercomp_intr(dwc_otg_hcd, hc, hc_regs, qtd);
+		/*
+		 * If NYET occurred at same time as Xfer Complete, the NYET is
+		 * handled by the Xfer Complete interrupt handler. Don't want
+		 * to call the NYET interrupt handler in this case.
+		 */
+		hcint.b.nyet = 0;
+	}
+	if (hcint.b.chhltd) {
+		retval |= handle_hc_chhltd_intr(dwc_otg_hcd, hc, hc_regs, qtd);
+	}
+	if (hcint.b.ahberr) {
+		retval |= handle_hc_ahberr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
+	}
+	if (hcint.b.stall) {
+		retval |= handle_hc_stall_intr(dwc_otg_hcd, hc, hc_regs, qtd);
+	}
+	if (hcint.b.nak) {
+		retval |= handle_hc_nak_intr(dwc_otg_hcd, hc, hc_regs, qtd);
+	}
+	if (hcint.b.ack) {
+		retval |= handle_hc_ack_intr(dwc_otg_hcd, hc, hc_regs, qtd);
+	}
+	if (hcint.b.nyet) {
+		retval |= handle_hc_nyet_intr(dwc_otg_hcd, hc, hc_regs, qtd);
+	}
+	if (hcint.b.xacterr) {
+		retval |= handle_hc_xacterr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
+	}
+	if (hcint.b.bblerr) {
+		retval |= handle_hc_babble_intr(dwc_otg_hcd, hc, hc_regs, qtd);
+	}
+	if (hcint.b.frmovrun) {
+		retval |=
+		    handle_hc_frmovrun_intr(dwc_otg_hcd, hc, hc_regs, qtd);
+	}
+	if (hcint.b.datatglerr) {
+		retval |=
+		    handle_hc_datatglerr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
+	}
+
+	return retval;
+}
+
+#endif				/* DWC_DEVICE_ONLY */
diff --git a/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c b/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c
new file mode 100644
index 000000000000..a5f8546ea7dd
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c
@@ -0,0 +1,840 @@
+/* ==========================================================================
+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_linux.c $
+ * $Revision: #11 $
+ * $Date: 2009/04/21 $
+ * $Change: 1237476 $
+ *
+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+ * otherwise expressly agreed to in writing between Synopsys and you.
+ *
+ * The Software IS NOT an item of Licensed Software or Licensed Product under
+ * any End User Software License Agreement or Agreement for Licensed Product
+ * with Synopsys or any supplement thereto. You are permitted to use and
+ * redistribute this Software in source and binary forms, with or without
+ * modification, provided that redistributions of source code must retain this
+ * notice. You may not view, use, disclose, copy or distribute this file or
+ * any information contained herein except pursuant to this license grant from
+ * Synopsys. If you do not agree with this notice, including the disclaimer
+ * below, then you are not authorized to use the Software.
+ *
+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ * ========================================================================== */
+#ifndef DWC_DEVICE_ONLY
+
+/**
+ * @file
+ *
+ * This file contains the implementation of the HCD. In Linux, the HCD
+ * implements the hc_driver API.
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/list.h>
+#include <linux/interrupt.h>
+#include <linux/string.h>
+#include <linux/dma-mapping.h>
+#include <linux/version.h>
+#include <asm/io.h>
+
+#ifdef LM_INTERFACE
+//#include <asm/arch/regs-irq.h>
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30))
+#include <asm/arch/lm.h>
+#include <asm/arch/irqs.h>
+#else
+#include <mach/lm.h>
+#include <mach/irqs.h>
+#endif
+#elif defined(PLATFORM_INTERFACE)
+#include <linux/platform_device.h>
+#endif
+
+#include <linux/usb.h>
+#include <linux/usb/hcd.h>
+
+#include "dwc_otg_hcd_if.h"
+#include "dwc_otg_dbg.h"
+#include "dwc_otg_driver.h"
+
+/**
+ * Gets the endpoint number from a _bEndpointAddress argument. The endpoint is
+ * qualified with its direction (possible 32 endpoints per device).
+ */
+#define dwc_ep_addr_to_endpoint(_bEndpointAddress_) ((_bEndpointAddress_ & USB_ENDPOINT_NUMBER_MASK) | \
+						     ((_bEndpointAddress_ & USB_DIR_IN) != 0) << 4)
+
+static const char dwc_otg_hcd_name[] = "dwc_otg_hcd";
+
+/** @name Linux HC Driver API Functions */
+/** @{ */
+/* manage i/o requests, device state */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30))
+static int urb_enqueue(struct usb_hcd *hcd,
+		       struct usb_host_endpoint *ep,
+		       struct urb *urb, gfp_t mem_flags);
+
+static int urb_dequeue(struct usb_hcd *hcd, struct urb *urb);
+#else
+static int urb_enqueue(struct usb_hcd *hcd,
+		       struct urb *urb, gfp_t mem_flags);
+
+static int urb_dequeue(struct usb_hcd *hcd,
+		       struct urb *urb, int status);
+#endif
+
+static void endpoint_disable(struct usb_hcd *hcd, struct usb_host_endpoint *ep);
+
+static irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd);
+extern int hcd_start(struct usb_hcd *hcd);
+extern void hcd_stop(struct usb_hcd *hcd);
+static int get_frame_number(struct usb_hcd *hcd);
+extern int hub_status_data(struct usb_hcd *hcd, char *buf);
+extern int hub_control(struct usb_hcd *hcd,
+		       u16 typeReq,
+		       u16 wValue, u16 wIndex, char *buf, u16 wLength);
+
+struct wrapper_priv_data {
+	dwc_otg_hcd_t *dwc_otg_hcd;
+};
+
+/** @} */
+
+static struct hc_driver dwc_otg_hc_driver = {
+
+	.description = dwc_otg_hcd_name,
+	.product_desc = "DWC OTG Controller",
+	.hcd_priv_size = sizeof(struct wrapper_priv_data),
+
+	.irq = dwc_otg_hcd_irq,
+
+	.flags = HCD_MEMORY | HCD_USB2,
+
+	//.reset =              
+	.start = hcd_start,
+	//.suspend =            
+	//.resume =             
+	.stop = hcd_stop,
+
+	.urb_enqueue = urb_enqueue,
+	.urb_dequeue = urb_dequeue,
+	.endpoint_disable = endpoint_disable,
+
+	.get_frame_number = get_frame_number,
+
+	.hub_status_data = hub_status_data,
+	.hub_control = hub_control,
+	//.bus_suspend =                
+	//.bus_resume =         
+};
+
+/** Gets the dwc_otg_hcd from a struct usb_hcd */
+static inline dwc_otg_hcd_t *hcd_to_dwc_otg_hcd(struct usb_hcd *hcd)
+{
+	struct wrapper_priv_data *p;
+	p = (struct wrapper_priv_data *)(hcd->hcd_priv);
+	return p->dwc_otg_hcd;
+}
+
+/** Gets the struct usb_hcd that contains a dwc_otg_hcd_t. */
+static inline struct usb_hcd *dwc_otg_hcd_to_hcd(dwc_otg_hcd_t * dwc_otg_hcd)
+{
+	return dwc_otg_hcd_get_priv_data(dwc_otg_hcd);
+}
+
+/** Gets the usb_host_endpoint associated with an URB. */
+inline struct usb_host_endpoint *dwc_urb_to_endpoint(struct urb *urb)
+{
+	struct usb_device *dev = urb->dev;
+	int ep_num = usb_pipeendpoint(urb->pipe);
+
+	if (usb_pipein(urb->pipe))
+		return dev->ep_in[ep_num];
+	else
+		return dev->ep_out[ep_num];
+}
+
+static int _disconnect(dwc_otg_hcd_t * hcd)
+{
+	struct usb_hcd *usb_hcd = dwc_otg_hcd_to_hcd(hcd);
+
+	usb_hcd->self.is_b_host = 0;
+	return 0;
+}
+
+static int _start(dwc_otg_hcd_t * hcd)
+{
+	struct usb_hcd *usb_hcd = dwc_otg_hcd_to_hcd(hcd);
+
+	usb_hcd->self.is_b_host = dwc_otg_hcd_is_b_host(hcd);
+	hcd_start(usb_hcd);
+
+	return 0;
+}
+
+static int _hub_info(dwc_otg_hcd_t * hcd, void *urb_handle, uint32_t * hub_addr,
+		     uint32_t * port_addr)
+{
+   struct urb *urb = (struct urb *)urb_handle;
+#if 1 //GRAYG - temporary
+   if (NULL == urb_handle)
+      DWC_ERROR("**** %s - NULL URB handle\n", __func__);//GRAYG
+   if (NULL == urb->dev)
+      DWC_ERROR("**** %s - URB has no device\n", __func__);//GRAYG
+   if (NULL == port_addr)
+      DWC_ERROR("**** %s - NULL port_address\n", __func__);//GRAYG
+#endif
+   if (urb->dev->tt) {
+        if (NULL == urb->dev->tt->hub) {
+                DWC_ERROR("**** %s - (URB's transactor has no TT - giving no hub)\n",
+                           __func__); //GRAYG
+                //*hub_addr = (u8)usb_pipedevice(urb->pipe); //GRAYG
+                *hub_addr = 0; //GRAYG
+                // we probably shouldn't have a transaction translator if
+                // there's no associated hub?
+        } else
+                *hub_addr = urb->dev->tt->hub->devnum;
+   } else {
+        *hub_addr = 0;
+   }
+   *port_addr = urb->dev->ttport;
+   return 0;
+}
+
+static int _speed(dwc_otg_hcd_t * hcd, void *urb_handle)
+{
+	struct urb *urb = (struct urb *)urb_handle;
+	return urb->dev->speed;
+}
+
+static int _get_b_hnp_enable(dwc_otg_hcd_t * hcd)
+{
+	struct usb_hcd *usb_hcd = dwc_otg_hcd_to_hcd(hcd);
+	return usb_hcd->self.b_hnp_enable;
+}
+
+static void allocate_bus_bandwidth(struct usb_hcd *hcd, uint32_t bw,
+				   struct urb *urb)
+{
+	hcd_to_bus(hcd)->bandwidth_allocated += bw / urb->interval;
+	if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
+		hcd_to_bus(hcd)->bandwidth_isoc_reqs++;
+	} else {
+		hcd_to_bus(hcd)->bandwidth_int_reqs++;
+	}
+}
+
+static void free_bus_bandwidth(struct usb_hcd *hcd, uint32_t bw,
+			       struct urb *urb)
+{
+	hcd_to_bus(hcd)->bandwidth_allocated -= bw / urb->interval;
+	if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
+		hcd_to_bus(hcd)->bandwidth_isoc_reqs--;
+	} else {
+		hcd_to_bus(hcd)->bandwidth_int_reqs--;
+	}
+}
+
+/**
+ * Sets the final status of an URB and returns it to the device driver. Any
+ * required cleanup of the URB is performed.
+ */
+static int _complete(dwc_otg_hcd_t * hcd, void *urb_handle,
+		     dwc_otg_hcd_urb_t * dwc_otg_urb, int32_t status)
+{
+	struct urb *urb = (struct urb *)urb_handle;
+#ifdef DEBUG
+	if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
+		DWC_PRINTF("%s: urb %p, device %d, ep %d %s, status=%d\n",
+			   __func__, urb, usb_pipedevice(urb->pipe),
+			   usb_pipeendpoint(urb->pipe),
+			   usb_pipein(urb->pipe) ? "IN" : "OUT", status);
+		if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
+			int i;
+			for (i = 0; i < urb->number_of_packets; i++) {
+				DWC_PRINTF("  ISO Desc %d status: %d\n",
+					   i, urb->iso_frame_desc[i].status);
+			}
+		}
+	}
+#endif
+
+	urb->actual_length = dwc_otg_hcd_urb_get_actual_length(dwc_otg_urb);
+	/* Convert status value. */
+	switch (status) {
+	case -DWC_E_PROTOCOL:
+		status = -EPROTO;
+		break;
+	case -DWC_E_IN_PROGRESS:
+		status = -EINPROGRESS;
+		break;
+	case -DWC_E_PIPE:
+		status = -EPIPE;
+		break;
+	case -DWC_E_IO:
+		status = -EIO;
+		break;
+	case -DWC_E_TIMEOUT:
+		status = -ETIMEDOUT;
+		break;
+	case -DWC_E_OVERFLOW:
+		status = -EOVERFLOW;
+		break;
+	default:
+		if (status) {
+			DWC_PRINTF("Uknown urb status %d\n", status);
+
+		}
+	}
+
+	if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
+		int i;
+
+		urb->error_count = dwc_otg_hcd_urb_get_error_count(dwc_otg_urb);
+		for (i = 0; i < urb->number_of_packets; ++i) {
+			urb->iso_frame_desc[i].actual_length =
+			    dwc_otg_hcd_urb_get_iso_desc_actual_length
+			    (dwc_otg_urb, i);
+			urb->iso_frame_desc[i].status =
+			    dwc_otg_hcd_urb_get_iso_desc_status
+			    (dwc_otg_urb, i);
+		}
+	}
+
+	urb->status = status;
+	urb->hcpriv = NULL;
+	if (!status) {
+		if ((urb->transfer_flags & URB_SHORT_NOT_OK) &&
+		    (urb->actual_length < urb->transfer_buffer_length)) {
+			urb->status = -EREMOTEIO;
+		}
+	}
+
+	if ((usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) ||
+	    (usb_pipetype(urb->pipe) == PIPE_INTERRUPT)) {
+		struct usb_host_endpoint *ep = dwc_urb_to_endpoint(urb);
+		if (ep) {
+			free_bus_bandwidth(dwc_otg_hcd_to_hcd(hcd),
+					   dwc_otg_hcd_get_ep_bandwidth(hcd,
+									ep->
+									hcpriv),
+					   urb);
+		}
+	}
+
+	dwc_free(dwc_otg_urb);
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30))
+	usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(hcd), urb);
+#else
+	usb_hcd_unlink_urb_from_ep(dwc_otg_hcd_to_hcd(hcd), urb);
+	usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(hcd), urb, status);
+#endif
+	return 0;
+}
+
+static struct dwc_otg_hcd_function_ops hcd_fops = {
+	.start = _start,
+	.disconnect = _disconnect,
+	.hub_info = _hub_info,
+	.speed = _speed,
+	.complete = _complete,
+	.get_b_hnp_enable = _get_b_hnp_enable,
+};
+
+/**
+ * Initializes the HCD. This function allocates memory for and initializes the
+ * static parts of the usb_hcd and dwc_otg_hcd structures. It also registers the
+ * USB bus with the core and calls the hc_driver->start() function. It returns
+ * a negative error on failure.
+ */
+int hcd_init(
+#ifdef LM_INTERFACE
+	struct lm_device *_dev
+#elif  defined(PCI_INTERFACE)
+	struct pci_dev *_dev
+#elif  defined(PLATFORM_INTERFACE)
+	struct platform_device *_dev
+#endif
+	)
+{
+	struct usb_hcd *hcd = NULL;
+	dwc_otg_hcd_t *dwc_otg_hcd = NULL;
+#ifdef LM_INTERFACE
+	dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev);
+#elif  defined(PCI_INTERFACE)
+	dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev);
+#elif  defined(PLATFORM_INTERFACE)
+	dwc_otg_device_t *otg_dev = platform_get_drvdata(_dev);
+#endif
+
+	int retval = 0;
+        u64 dmamask;
+
+	DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD INIT otg_dev=%p\n", otg_dev);
+
+	/* Set device flags indicating whether the HCD supports DMA. */
+	if (dwc_otg_is_dma_enable(otg_dev->core_if))
+                dmamask = DMA_BIT_MASK(32);
+        else
+                dmamask = 0;
+              
+#if    defined(LM_INTERFACE) || defined(PLATFORM_INTERFACE)
+        dma_set_mask(&_dev->dev, dmamask);
+        dma_set_coherent_mask(&_dev->dev, dmamask);
+#elif  defined(PCI_INTERFACE)
+        pci_set_dma_mask(_dev, dmamask);
+        pci_set_consistent_dma_mask(_dev, dmamask);
+#endif
+
+	/*
+	 * Allocate memory for the base HCD plus the DWC OTG HCD.
+	 * Initialize the base HCD.
+	 */
+	hcd = usb_create_hcd(&dwc_otg_hc_driver, &_dev->dev,
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30))
+                             _dev->dev.bus_id);
+#else
+                             dev_name(&_dev->dev));
+#endif
+	if (!hcd) {
+		retval = -ENOMEM;
+		goto error1;
+	}
+
+	hcd->regs = otg_dev->base;
+
+	/* Initialize the DWC OTG HCD. */
+	dwc_otg_hcd = dwc_otg_hcd_alloc_hcd();
+	if (!dwc_otg_hcd) {
+		goto error2;
+	}
+	((struct wrapper_priv_data *)(hcd->hcd_priv))->dwc_otg_hcd =
+	    dwc_otg_hcd;
+	otg_dev->hcd = dwc_otg_hcd;
+
+	if (dwc_otg_hcd_init(dwc_otg_hcd, otg_dev->core_if)) {
+		goto error2;
+	}
+
+	hcd->self.otg_port = dwc_otg_hcd_otg_port(dwc_otg_hcd);
+
+	/*
+	 * Finish generic HCD initialization and start the HCD. This function
+	 * allocates the DMA buffer pool, registers the USB bus, requests the
+	 * IRQ line, and calls hcd_start method.
+	 */
+#ifdef PLATFORM_INTERFACE
+	retval = usb_add_hcd(hcd, platform_get_irq(_dev, 0), IRQF_SHARED);
+#else
+	retval = usb_add_hcd(hcd, _dev->irq, IRQF_SHARED);
+#endif
+	if (retval < 0) {
+		goto error2;
+	}
+
+	dwc_otg_hcd_set_priv_data(dwc_otg_hcd, hcd);
+	return 0;
+
+      error2:
+	usb_put_hcd(hcd);
+      error1:
+	return retval;
+}
+
+/**
+ * Removes the HCD.
+ * Frees memory and resources associated with the HCD and deregisters the bus.
+ */
+void hcd_remove(
+#ifdef LM_INTERFACE
+	struct lm_device *_dev
+#elif  defined(PCI_INTERFACE)
+	struct pci_dev *_dev
+#elif  defined(PLATFORM_INTERFACE)
+	struct platform_device *_dev
+#endif
+	)
+{
+#ifdef LM_INTERFACE
+	dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev);
+#elif  defined(PCI_INTERFACE)
+	dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev);
+#elif  defined(PLATFORM_INTERFACE)
+	dwc_otg_device_t *otg_dev = platform_get_drvdata(_dev);
+#endif
+
+	dwc_otg_hcd_t *dwc_otg_hcd;
+	struct usb_hcd *hcd;
+
+	DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD REMOVE otg_dev=%p\n", otg_dev);
+
+	if (!otg_dev) {
+		DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
+		return;
+	}
+
+	dwc_otg_hcd = otg_dev->hcd;
+
+	if (!dwc_otg_hcd) {
+		DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
+		return;
+	}
+
+	hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd);
+
+	if (!hcd) {
+		DWC_DEBUGPL(DBG_ANY,
+			    "%s: dwc_otg_hcd_to_hcd(dwc_otg_hcd) NULL!\n",
+			    __func__);
+		return;
+	}
+	usb_remove_hcd(hcd);
+	dwc_otg_hcd_set_priv_data(dwc_otg_hcd, NULL);
+	dwc_otg_hcd_remove(dwc_otg_hcd);
+	usb_put_hcd(hcd);
+}
+
+/* =========================================================================
+ *  Linux HC Driver Functions
+ * ========================================================================= */
+
+/** Initializes the DWC_otg controller and its root hub and prepares it for host
+ * mode operation. Activates the root port. Returns 0 on success and a negative
+ * error code on failure. */
+int hcd_start(struct usb_hcd *hcd)
+{
+	dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
+	struct usb_bus *bus;
+
+	DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD START\n");
+	bus = hcd_to_bus(hcd);
+
+	hcd->state = HC_STATE_RUNNING;
+	if (dwc_otg_hcd_start(dwc_otg_hcd, &hcd_fops)) {
+		return 0;
+	}
+
+	/* Initialize and connect root hub if one is not already attached */
+	if (bus->root_hub) {
+		DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Has Root Hub\n");
+		/* Inform the HUB driver to resume. */
+		usb_hcd_resume_root_hub(hcd);
+	}
+
+	return 0;
+}
+
+/**
+ * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
+ * stopped.
+ */
+void hcd_stop(struct usb_hcd *hcd)
+{
+	dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
+
+	dwc_otg_hcd_stop(dwc_otg_hcd);
+}
+
+/** Returns the current frame number. */
+static int get_frame_number(struct usb_hcd *hcd)
+{
+	dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
+
+	return dwc_otg_hcd_get_frame_number(dwc_otg_hcd);
+}
+
+#ifdef DEBUG
+static void dump_urb_info(struct urb *urb, char *fn_name)
+{
+	DWC_PRINTF("%s, urb %p\n", fn_name, urb);
+	DWC_PRINTF("  Device address: %d\n", usb_pipedevice(urb->pipe));
+	DWC_PRINTF("  Endpoint: %d, %s\n", usb_pipeendpoint(urb->pipe),
+		   (usb_pipein(urb->pipe) ? "IN" : "OUT"));
+	DWC_PRINTF("  Endpoint type: %s\n", ( {
+					     char *pipetype;
+					     switch (usb_pipetype(urb->pipe)) {
+case PIPE_CONTROL:
+pipetype = "CONTROL"; break; case PIPE_BULK:
+pipetype = "BULK"; break; case PIPE_INTERRUPT:
+pipetype = "INTERRUPT"; break; case PIPE_ISOCHRONOUS:
+pipetype = "ISOCHRONOUS"; break; default:
+					     pipetype = "UNKNOWN"; break;};
+					     pipetype;}
+		   )) ;
+	DWC_PRINTF("  Speed: %s\n", ( {
+				     char *speed; switch (urb->dev->speed) {
+case USB_SPEED_HIGH:
+speed = "HIGH"; break; case USB_SPEED_FULL:
+speed = "FULL"; break; case USB_SPEED_LOW:
+speed = "LOW"; break; default:
+				     speed = "UNKNOWN"; break;};
+				     speed;}
+		   )) ;
+	DWC_PRINTF("  Max packet size: %d\n",
+		   usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
+	DWC_PRINTF("  Data buffer length: %d\n", urb->transfer_buffer_length);
+	DWC_PRINTF("  Transfer buffer: %p, Transfer DMA: %p\n",
+		   urb->transfer_buffer, (void *)urb->transfer_dma);
+	DWC_PRINTF("  Setup buffer: %p, Setup DMA: %p\n",
+		   urb->setup_packet, (void *)urb->setup_dma);
+	DWC_PRINTF("  Interval: %d\n", urb->interval);
+	if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
+		int i;
+		for (i = 0; i < urb->number_of_packets; i++) {
+			DWC_PRINTF("  ISO Desc %d:\n", i);
+			DWC_PRINTF("    offset: %d, length %d\n",
+				   urb->iso_frame_desc[i].offset,
+				   urb->iso_frame_desc[i].length);
+		}
+	}
+}
+
+#endif
+
+/** Starts processing a USB transfer request specified by a USB Request Block
+ * (URB). mem_flags indicates the type of memory allocation to use while
+ * processing this URB. */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30))
+static int urb_enqueue(struct usb_hcd *hcd,
+		       struct usb_host_endpoint *ep,
+		       struct urb *urb, gfp_t mem_flags)
+{
+#else
+static int urb_enqueue(struct usb_hcd *hcd,
+		       struct urb *urb,
+                       gfp_t mem_flags)
+{
+        struct usb_host_endpoint *ep = urb->ep;
+#endif
+        void **ref_ep_hcpriv = &ep->hcpriv;
+	int retval = 0;
+	dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
+	dwc_otg_hcd_urb_t *dwc_otg_urb;
+	int i;
+	int alloc_bandwidth = 0;
+	uint8_t ep_type = 0;
+	uint32_t flags = 0;
+	void *buf;
+
+#ifdef DEBUG
+	if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
+		dump_urb_info(urb, "urb_enqueue");
+	}
+#endif
+
+	if (!urb->transfer_buffer && urb->transfer_buffer_length)
+		return -EINVAL;
+
+	if ((usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
+	    || (usb_pipetype(urb->pipe) == PIPE_INTERRUPT)) {
+		if (!dwc_otg_hcd_is_bandwidth_allocated
+		    (dwc_otg_hcd, ref_ep_hcpriv)) {
+			alloc_bandwidth = 1;
+		}
+	}
+
+	switch (usb_pipetype(urb->pipe)) {
+	case PIPE_CONTROL:
+		ep_type = USB_ENDPOINT_XFER_CONTROL;
+		break;
+	case PIPE_ISOCHRONOUS:
+		ep_type = USB_ENDPOINT_XFER_ISOC;
+		break;
+	case PIPE_BULK:
+		ep_type = USB_ENDPOINT_XFER_BULK;
+		break;
+	case PIPE_INTERRUPT:
+		ep_type = USB_ENDPOINT_XFER_INT;
+		break;
+	default:
+		DWC_WARN("Wrong ep type\n");
+	}
+
+	dwc_otg_urb = dwc_otg_hcd_urb_alloc(dwc_otg_hcd,
+					    urb->number_of_packets,
+					    mem_flags == GFP_ATOMIC ? 1 : 0);
+
+        urb->hcpriv = dwc_otg_urb;
+        
+	dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_urb, usb_pipedevice(urb->pipe),
+				     usb_pipeendpoint(urb->pipe), ep_type,
+				     usb_pipein(urb->pipe),
+				     usb_maxpacket(urb->dev, urb->pipe,
+						   !(usb_pipein(urb->pipe))));
+
+	buf = urb->transfer_buffer;
+	if (hcd->self.uses_dma) {
+		/*
+		 * Calculate virtual address from physical address,
+		 * because some class driver may not fill transfer_buffer.
+		 * In Buffer DMA mode virual address is used,
+		 * when handling non DWORD aligned buffers.
+		 */
+		//buf = phys_to_virt(urb->transfer_dma);
+                // DMA addresses are bus addresses not physical addresses!
+                buf = dma_to_virt(&urb->dev->dev, urb->transfer_dma);
+	}
+	
+	if (!(urb->transfer_flags & URB_NO_INTERRUPT))
+		flags |= URB_GIVEBACK_ASAP;
+	if (urb->transfer_flags & URB_ZERO_PACKET)
+		flags |= URB_SEND_ZERO_PACKET;
+
+	dwc_otg_hcd_urb_set_params(dwc_otg_urb, urb, buf,
+				   urb->transfer_dma,
+				   urb->transfer_buffer_length,
+				   urb->setup_packet, 
+				   urb->setup_dma,
+				   flags,
+				   urb->interval);
+
+	for (i = 0; i < urb->number_of_packets; ++i) {
+		dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_urb, i,
+						    urb->iso_frame_desc[i].
+						    offset,
+						    urb->iso_frame_desc[i].
+						    length);
+	}
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30))
+	retval = usb_hcd_link_urb_to_ep(hcd, urb);
+	if (0 == retval) 
+#endif
+        {
+                retval = dwc_otg_hcd_urb_enqueue(dwc_otg_hcd, dwc_otg_urb,
+                                                 /*(dwc_otg_qh_t **)*/
+                                                 ref_ep_hcpriv);
+                if (0 == retval) {
+                        if (alloc_bandwidth) {
+                                allocate_bus_bandwidth(hcd,
+                                        dwc_otg_hcd_get_ep_bandwidth(
+                                                dwc_otg_hcd, *ref_ep_hcpriv),
+                                                       urb);
+                        }
+                } else {
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30))
+                        usb_hcd_unlink_urb_from_ep(hcd, urb);
+#endif
+                        if (retval == -DWC_E_NO_DEVICE) {
+                                retval = -ENODEV;
+                        }
+                }
+        }
+	return retval;
+}
+
+/** Aborts/cancels a USB transfer request. Always returns 0 to indicate
+ * success.  */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30))
+static int urb_dequeue(struct usb_hcd *hcd, struct urb *urb)
+#else
+static int urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
+#endif
+{
+	dwc_otg_hcd_t *dwc_otg_hcd;
+	DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue\n");
+
+	dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
+
+#ifdef DEBUG
+	if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
+		dump_urb_info(urb, "urb_dequeue");
+	}
+#endif
+	dwc_otg_hcd_urb_dequeue(dwc_otg_hcd, (dwc_otg_hcd_urb_t *)urb->hcpriv);
+
+	dwc_free(urb->hcpriv);
+	urb->hcpriv = NULL;
+
+	/* Higher layer software sets URB status. */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30))
+	usb_hcd_giveback_urb(hcd, urb);
+#else
+	usb_hcd_unlink_urb_from_ep(hcd, urb);
+	usb_hcd_giveback_urb(hcd, urb, status);
+#endif
+	if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
+		DWC_PRINTF("Called usb_hcd_giveback_urb()\n");
+		DWC_PRINTF("  urb->status = %d\n", urb->status);
+	}
+
+	return 0;
+}
+
+/* Frees resources in the DWC_otg controller related to a given endpoint. Also
+ * clears state in the HCD related to the endpoint. Any URBs for the endpoint
+ * must already be dequeued. */
+static void endpoint_disable(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
+{
+	dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
+
+	DWC_DEBUGPL(DBG_HCD,
+		    "DWC OTG HCD EP DISABLE: _bEndpointAddress=0x%02x, "
+		    "endpoint=%d\n", ep->desc.bEndpointAddress,
+		    dwc_ep_addr_to_endpoint(ep->desc.bEndpointAddress));
+	dwc_otg_hcd_endpoint_disable(dwc_otg_hcd, ep->hcpriv, 250);
+	ep->hcpriv = NULL;
+}
+
+/** Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
+ * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
+ * interrupt.
+ *
+ * This function is called by the USB core when an interrupt occurs */
+static irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd)
+{
+	dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
+	int32_t retval = dwc_otg_hcd_handle_intr(dwc_otg_hcd);
+	if (retval != 0) {
+		S3C2410X_CLEAR_EINTPEND();
+	}
+	return IRQ_RETVAL(retval);
+}
+
+/** Creates Status Change bitmap for the root hub and root port. The bitmap is
+ * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
+ * is the status change indicator for the single root port. Returns 1 if either
+ * change indicator is 1, otherwise returns 0. */
+int hub_status_data(struct usb_hcd *hcd, char *buf)
+{
+	dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
+
+	buf[0] = 0;
+	buf[0] |= (dwc_otg_hcd_is_status_changed(dwc_otg_hcd, 1)) << 1;
+
+	return (buf[0] != 0);
+}
+
+/** Handles hub class-specific requests. */
+int hub_control(struct usb_hcd *hcd,
+		u16 typeReq, u16 wValue, u16 wIndex, char *buf, u16 wLength)
+{
+	int retval;
+
+	retval = dwc_otg_hcd_hub_control(hcd_to_dwc_otg_hcd(hcd),
+					 typeReq, wValue, wIndex, buf, wLength);
+
+	switch (retval) {
+	case -DWC_E_INVALID:
+		retval = -EINVAL;
+		break;
+	}
+
+	return retval;
+}
+
+#endif				/* DWC_DEVICE_ONLY */
diff --git a/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c b/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c
new file mode 100644
index 000000000000..cfed8070dc5c
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c
@@ -0,0 +1,732 @@
+/* ==========================================================================
+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_queue.c $
+ * $Revision: #39 $
+ * $Date: 2009/04/21 $
+ * $Change: 1237477 $
+ *
+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+ * otherwise expressly agreed to in writing between Synopsys and you.
+ * 
+ * The Software IS NOT an item of Licensed Software or Licensed Product under
+ * any End User Software License Agreement or Agreement for Licensed Product
+ * with Synopsys or any supplement thereto. You are permitted to use and
+ * redistribute this Software in source and binary forms, with or without
+ * modification, provided that redistributions of source code must retain this
+ * notice. You may not view, use, disclose, copy or distribute this file or
+ * any information contained herein except pursuant to this license grant from
+ * Synopsys. If you do not agree with this notice, including the disclaimer
+ * below, then you are not authorized to use the Software.
+ * 
+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ * ========================================================================== */
+#ifndef DWC_DEVICE_ONLY
+
+/**
+ * @file
+ *
+ * This file contains the functions to manage Queue Heads and Queue
+ * Transfer Descriptors.
+ */
+
+#include "dwc_otg_hcd.h"
+#include "dwc_otg_regs.h"
+
+/** 
+ * Free each QTD in the QH's QTD-list then free the QH.  QH should already be
+ * removed from a list.  QTD list should already be empty if called from URB
+ * Dequeue.
+ *
+ * @param hcd HCD instance.
+ * @param qh The QH to free.
+ */
+void dwc_otg_hcd_qh_free(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
+{
+	dwc_otg_qtd_t *qtd, *qtd_tmp;
+	uint64_t flags;
+
+	/* Free each QTD in the QTD list */
+	DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
+	DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) {
+		DWC_CIRCLEQ_REMOVE(&qh->qtd_list, qtd, qtd_list_entry);
+		dwc_otg_hcd_qtd_free(qtd);
+	}
+	DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
+
+	if (hcd->core_if->dma_desc_enable) {
+		dwc_otg_hcd_qh_free_ddma(hcd, qh);
+	}
+	else if (qh->dw_align_buf) {
+		uint32_t buf_size;
+		if(qh->ep_type == UE_ISOCHRONOUS) {
+			buf_size = 4096;
+		} else {
+			buf_size = hcd->core_if->core_params->max_transfer_size;
+		}
+		dwc_dma_free(buf_size, qh->dw_align_buf, qh->dw_align_buf_dma);
+	}
+	
+	
+	
+	dwc_free(qh);
+	return;
+}
+
+#define BitStuffTime(bytecount)  ((8 * 7* bytecount) / 6)
+#define HS_HOST_DELAY		5	/* nanoseconds */
+#define FS_LS_HOST_DELAY	1000	/* nanoseconds */
+#define HUB_LS_SETUP		333	/* nanoseconds */
+#define NS_TO_US(ns)		((ns + 500) / 1000)
+				/* convert & round nanoseconds to microseconds */
+
+static uint32_t calc_bus_time(int speed, int is_in, int is_isoc,
+					  int bytecount)
+{
+	unsigned long retval;
+
+	switch (speed) {
+	case USB_SPEED_HIGH:
+		if (is_isoc) {
+			retval =
+			    ((38 * 8 * 2083) +
+			     (2083 * (3 + BitStuffTime(bytecount)))) / 1000 +
+			    HS_HOST_DELAY;
+		} else {
+			retval =
+			    ((55 * 8 * 2083) +
+			     (2083 * (3 + BitStuffTime(bytecount)))) / 1000 +
+			    HS_HOST_DELAY;
+		}
+		break;
+	case USB_SPEED_FULL:
+		if (is_isoc) {
+			retval =
+			    (8354 * (31 + 10 * BitStuffTime(bytecount))) / 1000;
+			if (is_in) {
+				retval = 7268 + FS_LS_HOST_DELAY + retval;
+			} else {
+				retval = 6265 + FS_LS_HOST_DELAY + retval;
+			}
+		} else {
+			retval =
+			    (8354 * (31 + 10 * BitStuffTime(bytecount))) / 1000;
+			retval = 9107 + FS_LS_HOST_DELAY + retval;
+		}
+		break;
+	case USB_SPEED_LOW:
+		if (is_in) {
+			retval =
+			    (67667 * (31 + 10 * BitStuffTime(bytecount))) /
+			    1000;
+			retval =
+			    64060 + (2 * HUB_LS_SETUP) + FS_LS_HOST_DELAY +
+			    retval;
+		} else {
+			retval =
+			    (66700 * (31 + 10 * BitStuffTime(bytecount))) /
+			    1000;
+			retval =
+			    64107 + (2 * HUB_LS_SETUP) + FS_LS_HOST_DELAY +
+			    retval;
+		}
+		break;
+	default:
+		DWC_WARN("Unknown device speed\n");
+		retval = -1;
+	}
+	
+	return NS_TO_US(retval);
+}
+
+/** 
+ * Initializes a QH structure.
+ *
+ * @param hcd The HCD state structure for the DWC OTG controller.
+ * @param qh  The QH to init.
+ * @param urb Holds the information about the device/endpoint that we need
+ * 	      to initialize the QH. 
+ */
+#define SCHEDULE_SLOP 10
+void qh_init(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh,
+			 dwc_otg_hcd_urb_t * urb)
+{
+	char *speed, *type;
+	int dev_speed;
+	uint32_t hub_addr, hub_port;
+
+	dwc_memset(qh, 0, sizeof(dwc_otg_qh_t));
+	
+	/* Initialize QH */
+	qh->ep_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
+
+	qh->ep_is_in = dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? 1 : 0;
+
+	qh->data_toggle = DWC_OTG_HC_PID_DATA0;
+	qh->maxp = dwc_otg_hcd_get_mps(&urb->pipe_info);
+	DWC_CIRCLEQ_INIT(&qh->qtd_list);
+	DWC_LIST_INIT(&qh->qh_list_entry);
+	qh->channel = NULL;
+
+	/* FS/LS Enpoint on HS Hub 
+	 * NOT virtual root hub */
+	dev_speed = hcd->fops->speed(hcd, urb->priv);
+	hcd->fops->hub_info(hcd, urb->priv, &hub_addr, &hub_port);
+	qh->do_split = 0;
+	if (((dev_speed == USB_SPEED_LOW) ||
+	     (dev_speed == USB_SPEED_FULL)) &&
+	    (hub_addr != 0 && hub_addr != 1)) {
+		
+		DWC_DEBUGPL(DBG_HCD,
+			    "QH init: EP %d: TT found at hub addr %d, for port %d\n",
+			    dwc_otg_hcd_get_ep_num(&urb->pipe_info), hub_addr,
+			    hub_port);
+		
+		qh->do_split = 1;
+	}
+
+	if (qh->ep_type == UE_INTERRUPT || qh->ep_type == UE_ISOCHRONOUS) {
+		/* Compute scheduling parameters once and save them. */
+		hprt0_data_t hprt;
+
+		/** @todo Account for split transfers in the bus time. */
+		int bytecount =
+		    dwc_hb_mult(qh->maxp) * dwc_max_packet(qh->maxp);
+
+		qh->usecs = calc_bus_time((qh->do_split ? USB_SPEED_HIGH : dev_speed),
+					  qh->ep_is_in,
+					  (qh->ep_type == UE_ISOCHRONOUS),
+					  bytecount);
+		/* Start in a slightly future (micro)frame. */
+		qh->sched_frame = dwc_frame_num_inc(hcd->frame_number,
+						    SCHEDULE_SLOP);
+		qh->interval = urb->interval;
+		
+#if 0
+		/* Increase interrupt polling rate for debugging. */
+		if (qh->ep_type == UE_INTERRUPT) {
+			qh->interval = 8;
+		}
+#endif
+		hprt.d32 = dwc_read_reg32(hcd->core_if->host_if->hprt0);
+		if ((hprt.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) &&
+		    ((dev_speed == USB_SPEED_LOW) ||
+		     (dev_speed == USB_SPEED_FULL))) {
+			qh->interval *= 8;
+			qh->sched_frame |= 0x7;
+			qh->start_split_frame = qh->sched_frame;
+		}
+
+	}
+
+	DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD QH Initialized\n");
+	DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH  - qh = %p\n", qh);
+	DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH  - Device Address = %d\n",
+		    dwc_otg_hcd_get_dev_addr(&urb->pipe_info));
+	DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH  - Endpoint %d, %s\n",
+		    dwc_otg_hcd_get_ep_num(&urb->pipe_info),
+		    dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT");
+	switch (dev_speed) {
+	case USB_SPEED_LOW:
+		qh->dev_speed = DWC_OTG_EP_SPEED_LOW;
+		speed = "low";
+		break;
+	case USB_SPEED_FULL:
+		qh->dev_speed = DWC_OTG_EP_SPEED_FULL;
+		speed = "full";
+		break;
+	case USB_SPEED_HIGH:
+		qh->dev_speed = DWC_OTG_EP_SPEED_HIGH;
+		speed = "high";
+		break;
+	default:
+		speed = "?";
+		break;
+	}
+	DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH  - Speed = %s\n", speed);
+
+	switch (qh->ep_type) {
+	case UE_ISOCHRONOUS:
+		type = "isochronous";
+		break;
+	case UE_INTERRUPT:
+		type = "interrupt";
+		break;
+	case UE_CONTROL:
+		type = "control";
+		break;
+	case UE_BULK:
+		type = "bulk";
+		break;
+	default:
+		type = "?";
+		break;
+	}
+	
+	DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH  - Type = %s\n", type);
+
+#ifdef DEBUG
+	if (qh->ep_type == UE_INTERRUPT) {
+		DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - usecs = %d\n",
+			    qh->usecs);
+		DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - interval = %d\n",
+			    qh->interval);
+	}
+#endif
+
+}
+
+/**
+ * This function allocates and initializes a QH.
+ *
+ * @param hcd The HCD state structure for the DWC OTG controller.
+ * @param urb Holds the information about the device/endpoint that we need
+ * 	      to initialize the QH.
+ *
+ * @return Returns pointer to the newly allocated QH, or NULL on error. */
+dwc_otg_qh_t *dwc_otg_hcd_qh_create(dwc_otg_hcd_t * hcd,
+				    dwc_otg_hcd_urb_t * urb)
+{
+	dwc_otg_qh_t *qh;
+
+	/* Allocate memory */
+	/** @todo add memflags argument */
+	qh = dwc_otg_hcd_qh_alloc();
+	if (qh == NULL) {
+		return NULL;
+	}
+
+	qh_init(hcd, qh, urb);
+	
+	if (hcd->core_if->dma_desc_enable && (dwc_otg_hcd_qh_init_ddma(hcd, qh) < 0)) {
+		dwc_otg_hcd_qh_free(hcd, qh);	
+		return NULL;
+	}
+	
+	return qh;
+}
+
+/**
+ * Checks that a channel is available for a periodic transfer.
+ *
+ * @return 0 if successful, negative error code otherise.
+ */
+static int periodic_channel_available(dwc_otg_hcd_t * hcd)
+{
+	/*
+	 * Currently assuming that there is a dedicated host channnel for each
+	 * periodic transaction plus at least one host channel for
+	 * non-periodic transactions.
+	 */
+	int status;
+	int num_channels;
+
+	num_channels = hcd->core_if->core_params->host_channels;
+	if ((hcd->periodic_channels + hcd->non_periodic_channels < num_channels) &&
+	    (hcd->periodic_channels < num_channels - 1)) {
+		status = 0;
+	} else {
+		DWC_INFO("%s: Total channels: %d, Periodic: %d, Non-periodic: %d\n",
+			__func__, num_channels, hcd->periodic_channels, hcd->non_periodic_channels);	//NOTICE
+		status = -DWC_E_NO_SPACE;
+	}
+
+	return status;
+}
+
+/**
+ * Checks that there is sufficient bandwidth for the specified QH in the
+ * periodic schedule. For simplicity, this calculation assumes that all the
+ * transfers in the periodic schedule may occur in the same (micro)frame.
+ *
+ * @param hcd The HCD state structure for the DWC OTG controller.
+ * @param qh QH containing periodic bandwidth required.
+ *
+ * @return 0 if successful, negative error code otherwise.
+ */
+static int check_periodic_bandwidth(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
+{
+	int status;
+	int16_t max_claimed_usecs;
+
+	status = 0;
+
+	if ((qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) || qh->do_split) {
+		/*
+		 * High speed mode.
+		 * Max periodic usecs is 80% x 125 usec = 100 usec.
+		 */
+
+		max_claimed_usecs = 100 - qh->usecs;
+	} else {
+		/*
+		 * Full speed mode.
+		 * Max periodic usecs is 90% x 1000 usec = 900 usec.
+		 */
+		max_claimed_usecs = 900 - qh->usecs;
+	}
+
+	if (hcd->periodic_usecs > max_claimed_usecs) {
+		DWC_INFO("%s: already claimed usecs %d, required usecs %d\n", __func__, hcd->periodic_usecs, qh->usecs);	//NOTICE
+		status = -DWC_E_NO_SPACE;
+	}
+
+	return status;
+}
+
+/**
+ * Checks that the max transfer size allowed in a host channel is large enough
+ * to handle the maximum data transfer in a single (micro)frame for a periodic
+ * transfer.
+ *
+ * @param hcd The HCD state structure for the DWC OTG controller.
+ * @param qh QH for a periodic endpoint.
+ *
+ * @return 0 if successful, negative error code otherwise.
+ */
+static int check_max_xfer_size(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
+{
+	int status;
+	uint32_t max_xfer_size;
+	uint32_t max_channel_xfer_size;
+
+	status = 0;
+
+	max_xfer_size = dwc_max_packet(qh->maxp) * dwc_hb_mult(qh->maxp);
+	max_channel_xfer_size = hcd->core_if->core_params->max_transfer_size;
+
+	if (max_xfer_size > max_channel_xfer_size) {
+		DWC_INFO("%s: Periodic xfer length %d > " "max xfer length for channel %d\n",
+				__func__, max_xfer_size, max_channel_xfer_size);	//NOTICE
+		status = -DWC_E_NO_SPACE;
+	}
+
+	return status;
+}
+
+/**
+ * Schedules an interrupt or isochronous transfer in the periodic schedule.
+ *
+ * @param hcd The HCD state structure for the DWC OTG controller.
+ * @param qh QH for the periodic transfer. The QH should already contain the
+ * scheduling information.
+ *
+ * @return 0 if successful, negative error code otherwise.
+ */
+static int schedule_periodic(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
+{
+	int status = 0;
+
+	status = periodic_channel_available(hcd);
+	if (status) {
+		DWC_INFO("%s: No host channel available for periodic " "transfer.\n", __func__);	//NOTICE
+		return status;
+	}
+
+	status = check_periodic_bandwidth(hcd, qh);
+	if (status) {
+		DWC_INFO("%s: Insufficient periodic bandwidth for " "periodic transfer.\n", __func__);	//NOTICE
+		return status;
+	}
+
+	status = check_max_xfer_size(hcd, qh);
+	if (status) {
+		DWC_INFO("%s: Channel max transfer size too small " "for periodic transfer.\n", __func__);	//NOTICE
+		return status;
+	}
+
+	if (hcd->core_if->dma_desc_enable) {
+		/* Don't rely on SOF and start in ready schedule */
+		DWC_LIST_INSERT_TAIL(&hcd->periodic_sched_ready, &qh->qh_list_entry);
+	}
+	else {
+	/* Always start in the inactive schedule. */
+	DWC_LIST_INSERT_TAIL(&hcd->periodic_sched_inactive, &qh->qh_list_entry);
+	}
+
+	/* Reserve the periodic channel. */
+	hcd->periodic_channels++;
+
+	/* Update claimed usecs per (micro)frame. */
+	hcd->periodic_usecs += qh->usecs;
+
+	return status;
+}
+
+/**
+ * This function adds a QH to either the non periodic or periodic schedule if
+ * it is not already in the schedule. If the QH is already in the schedule, no
+ * action is taken.
+ *
+ * @return 0 if successful, negative error code otherwise.
+ */
+int dwc_otg_hcd_qh_add(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
+{
+	int status = 0;
+	uint64_t flags;
+
+	DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
+
+	if (!DWC_LIST_EMPTY(&qh->qh_list_entry)) {
+		/* QH already in a schedule. */
+		goto done;
+	}
+
+	/* Add the new QH to the appropriate schedule */
+	if (dwc_qh_is_non_per(qh)) {
+		/* Always start in the inactive schedule. */
+		DWC_LIST_INSERT_TAIL(&hcd->non_periodic_sched_inactive,
+				     &qh->qh_list_entry);
+	} else {
+		status = schedule_periodic(hcd, qh);
+	}
+
+      done:
+	DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
+
+	return status;
+}
+
+/**
+ * Removes an interrupt or isochronous transfer from the periodic schedule.
+ *
+ * @param hcd The HCD state structure for the DWC OTG controller.
+ * @param qh QH for the periodic transfer.
+ */
+static void deschedule_periodic(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
+{
+	DWC_LIST_REMOVE_INIT(&qh->qh_list_entry);
+
+	/* Release the periodic channel reservation. */
+	hcd->periodic_channels--;
+
+	/* Update claimed usecs per (micro)frame. */
+	hcd->periodic_usecs -= qh->usecs;
+}
+
+/** 
+ * Removes a QH from either the non-periodic or periodic schedule.  Memory is
+ * not freed.
+ *
+ * @param hcd The HCD state structure.
+ * @param qh QH to remove from schedule. */
+void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
+{
+	uint64_t flags;
+	DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
+
+	if (DWC_LIST_EMPTY(&qh->qh_list_entry)) {
+		/* QH is not in a schedule. */
+		goto done;
+	}
+
+	if (dwc_qh_is_non_per(qh)) {
+		if (hcd->non_periodic_qh_ptr == &qh->qh_list_entry) {
+			hcd->non_periodic_qh_ptr =
+			    hcd->non_periodic_qh_ptr->next;
+		}
+		DWC_LIST_REMOVE_INIT(&qh->qh_list_entry);
+	} else {
+		deschedule_periodic(hcd, qh);
+	}
+
+      done:
+	DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
+}
+
+/**
+ * Deactivates a QH. For non-periodic QHs, removes the QH from the active
+ * non-periodic schedule. The QH is added to the inactive non-periodic
+ * schedule if any QTDs are still attached to the QH.
+ *
+ * For periodic QHs, the QH is removed from the periodic queued schedule. If
+ * there are any QTDs still attached to the QH, the QH is added to either the
+ * periodic inactive schedule or the periodic ready schedule and its next
+ * scheduled frame is calculated. The QH is placed in the ready schedule if
+ * the scheduled frame has been reached already. Otherwise it's placed in the
+ * inactive schedule. If there are no QTDs attached to the QH, the QH is
+ * completely removed from the periodic schedule.
+ */
+void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh,
+			       int sched_next_periodic_split)
+{
+	uint64_t flags;
+	DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
+
+	if (dwc_qh_is_non_per(qh)) {
+		dwc_otg_hcd_qh_remove(hcd, qh);
+		if (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
+			/* Add back to inactive non-periodic schedule. */
+			dwc_otg_hcd_qh_add(hcd, qh);
+		}
+	} else {
+		uint16_t frame_number = dwc_otg_hcd_get_frame_number(hcd);
+
+		if (qh->do_split) {
+			/* Schedule the next continuing periodic split transfer */
+			if (sched_next_periodic_split) {
+
+				qh->sched_frame = frame_number;
+				if (dwc_frame_num_le(frame_number,
+						     dwc_frame_num_inc(qh->
+								       start_split_frame,
+								       1))) {
+					/*
+					 * Allow one frame to elapse after start
+					 * split microframe before scheduling
+					 * complete split, but DONT if we are
+					 * doing the next start split in the
+					 * same frame for an ISOC out.
+					 */
+					if ((qh->ep_type != UE_ISOCHRONOUS) ||
+					    (qh->ep_is_in != 0)) {
+						qh->sched_frame =
+						    dwc_frame_num_inc(qh->sched_frame, 1);
+					}
+				}
+			} else {
+				qh->sched_frame =
+				    dwc_frame_num_inc(qh->start_split_frame,
+						      qh->interval);
+				if (dwc_frame_num_le
+				    (qh->sched_frame, frame_number)) {
+					qh->sched_frame = frame_number;
+				}
+				qh->sched_frame |= 0x7;
+				qh->start_split_frame = qh->sched_frame;
+			}
+		} else {
+			qh->sched_frame =
+			    dwc_frame_num_inc(qh->sched_frame, qh->interval);
+			if (dwc_frame_num_le(qh->sched_frame, frame_number)) {
+				qh->sched_frame = frame_number;
+			}
+		}
+
+		if (DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
+			dwc_otg_hcd_qh_remove(hcd, qh);
+		} else {
+			/*
+			 * Remove from periodic_sched_queued and move to
+			 * appropriate queue.
+			 */
+			if (qh->sched_frame == frame_number) {
+				DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready,
+						   &qh->qh_list_entry);
+			} else {
+				DWC_LIST_MOVE_HEAD(&hcd->
+						   periodic_sched_inactive,
+						   &qh->qh_list_entry);
+			}
+		}
+	}
+
+	DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
+}
+
+/** 
+ * This function allocates and initializes a QTD. 
+ *
+ * @param urb The URB to create a QTD from.  Each URB-QTD pair will end up
+ * 	      pointing to each other so each pair should have a unique correlation.
+ *
+ * @return Returns pointer to the newly allocated QTD, or NULL on error. */
+dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(dwc_otg_hcd_urb_t * urb)
+{
+	dwc_otg_qtd_t *qtd;
+
+	qtd = dwc_otg_hcd_qtd_alloc();
+	if (qtd == NULL) {
+		return NULL;
+	}
+
+	dwc_otg_hcd_qtd_init(qtd, urb);
+	return qtd;
+}
+
+/** 
+ * Initializes a QTD structure.
+ *
+ * @param qtd The QTD to initialize.
+ * @param urb The URB to use for initialization.  */
+void dwc_otg_hcd_qtd_init(dwc_otg_qtd_t * qtd, dwc_otg_hcd_urb_t * urb)
+{
+	dwc_memset(qtd, 0, sizeof(dwc_otg_qtd_t));
+	qtd->urb = urb;
+	if (dwc_otg_hcd_get_pipe_type(&urb->pipe_info) == UE_CONTROL) {
+		/*
+		 * The only time the QTD data toggle is used is on the data
+		 * phase of control transfers. This phase always starts with
+		 * DATA1.
+		 */
+		qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
+		qtd->control_phase = DWC_OTG_CONTROL_SETUP;
+	}
+
+	/* start split */
+	qtd->complete_split = 0;
+	qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
+	qtd->isoc_split_offset = 0;
+	qtd->in_process = 0;
+
+	/* Store the qtd ptr in the urb to reference what QTD. */
+	urb->qtd = qtd;
+	return;
+}
+
+/**
+ * This function adds a QTD to the QTD-list of a QH.  It will find the correct
+ * QH to place the QTD into.  If it does not find a QH, then it will create a
+ * new QH. If the QH to which the QTD is added is not currently scheduled, it
+ * is placed into the proper schedule based on its EP type.
+ *
+ * @param[in] qtd The QTD to add
+ * @param[in] hcd The DWC HCD structure
+ * @param[out] qh out parameter to return queue head
+ *
+ * @return 0 if successful, negative error code otherwise.
+ */
+int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * qtd,
+			dwc_otg_hcd_t * hcd, dwc_otg_qh_t ** qh)
+{
+	int retval = 0;
+	uint64_t flags;
+
+	dwc_otg_hcd_urb_t *urb = qtd->urb;
+
+	DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
+
+	/*
+	 * Get the QH which holds the QTD-list to insert to. Create QH if it
+	 * doesn't exist.
+	 */
+	if (*qh == NULL) {
+		*qh = dwc_otg_hcd_qh_create(hcd, urb);
+		if (*qh == NULL) {
+			retval = -1;
+			goto done;
+		}
+	}
+
+	retval = dwc_otg_hcd_qh_add(hcd, *qh);
+	if (retval == 0) {
+		DWC_CIRCLEQ_INSERT_TAIL(&((*qh)->qtd_list), qtd,
+					qtd_list_entry);
+	}
+
+      done:
+	DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
+
+	return retval;
+}
+
+#endif				/* DWC_DEVICE_ONLY */
diff --git a/drivers/usb/host/dwc_otg/dwc_otg_pcd.c b/drivers/usb/host/dwc_otg/dwc_otg_pcd.c
new file mode 100644
index 000000000000..6043b99239f4
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/dwc_otg_pcd.c
@@ -0,0 +1,2067 @@
+/* ==========================================================================
+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.c $
+ * $Revision: #79 $
+ * $Date: 2009/04/10 $
+ * $Change: 1230501 $
+ *
+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+ * otherwise expressly agreed to in writing between Synopsys and you.
+ *
+ * The Software IS NOT an item of Licensed Software or Licensed Product under
+ * any End User Software License Agreement or Agreement for Licensed Product
+ * with Synopsys or any supplement thereto. You are permitted to use and
+ * redistribute this Software in source and binary forms, with or without
+ * modification, provided that redistributions of source code must retain this
+ * notice. You may not view, use, disclose, copy or distribute this file or
+ * any information contained herein except pursuant to this license grant from
+ * Synopsys. If you do not agree with this notice, including the disclaimer
+ * below, then you are not authorized to use the Software.
+ *
+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ * ========================================================================== */
+#ifndef DWC_HOST_ONLY
+
+/** @file
+ * This file implements PCD Core. All code in this file is portable and don't
+ * use any OS specific functions.
+ * PCD Core provides Interface, defined in <code><dwc_otg_pcd_if.h></code>
+ * header file, which can be used to implement OS specific PCD interface.
+ *
+ * An important function of the PCD is managing interrupts generated
+ * by the DWC_otg controller. The implementation of the DWC_otg device
+ * mode interrupt service routines is in dwc_otg_pcd_intr.c.
+ *
+ * @todo Add Device Mode test modes (Test J mode, Test K mode, etc).
+ * @todo Does it work when the request size is greater than DEPTSIZ
+ * transfer size
+ *
+ */
+
+#include "dwc_otg_pcd.h"
+
+#ifdef DWC_UTE_CFI
+#include "dwc_otg_cfi.h"
+
+extern int init_cfi(cfiobject_t * cfiobj);
+#endif
+
+static dwc_otg_pcd_ep_t *get_ep_from_handle(dwc_otg_pcd_t * pcd, void *handle)
+{
+	int i;
+	if (pcd->ep0.priv == handle) {
+		return &pcd->ep0;
+	}
+	for (i = 0; i < MAX_EPS_CHANNELS - 1; i++) {
+		if (pcd->in_ep[i].priv == handle)
+			return &pcd->in_ep[i];
+		if (pcd->out_ep[i].priv == handle)
+			return &pcd->out_ep[i];
+	}
+
+	return NULL;
+}
+
+/**
+ * This function completes a request.  It call's the request call back.
+ */
+void dwc_otg_request_done(dwc_otg_pcd_ep_t * ep, dwc_otg_pcd_request_t * req,
+			  int32_t status)
+{
+	unsigned stopped = ep->stopped;
+
+	DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, ep);
+	DWC_CIRCLEQ_REMOVE_INIT(&ep->queue, req, queue_entry);
+
+	/* don't modify queue heads during completion callback */
+	ep->stopped = 1;
+	DWC_SPINUNLOCK(ep->pcd->lock);
+	ep->pcd->fops->complete(ep->pcd, ep->priv, req->priv, status,
+				req->actual);
+	DWC_SPINLOCK(ep->pcd->lock);
+
+	if (ep->pcd->request_pending > 0) {
+		--ep->pcd->request_pending;
+	}
+
+	ep->stopped = stopped;
+	dwc_free(req);
+}
+
+/**
+ * This function terminates all the requsts in the EP request queue.
+ */
+void dwc_otg_request_nuke(dwc_otg_pcd_ep_t * ep)
+{
+	dwc_otg_pcd_request_t *req;
+
+	ep->stopped = 1;
+
+	/* called with irqs blocked?? */
+	while (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
+		req = DWC_CIRCLEQ_FIRST(&ep->queue);
+		dwc_otg_request_done(ep, req, -DWC_E_SHUTDOWN);
+	}
+}
+
+void dwc_otg_pcd_start(dwc_otg_pcd_t * pcd,
+		       const struct dwc_otg_pcd_function_ops *fops)
+{
+	pcd->fops = fops;
+}
+
+/**
+ * PCD Callback function for initializing the PCD when switching to
+ * device mode.
+ *
+ * @param p void pointer to the <code>dwc_otg_pcd_t</code>
+ */
+static int32_t dwc_otg_pcd_start_cb(void *p)
+{
+	dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
+
+	/*
+	 * Initialized the Core for Device mode.
+	 */
+	if (dwc_otg_is_device_mode(GET_CORE_IF(pcd))) {
+		dwc_otg_core_dev_init(GET_CORE_IF(pcd));
+	}
+	return 1;
+}
+
+/** CFI-specific buffer allocation function for EP */
+#ifdef DWC_UTE_CFI
+uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep, dwc_dma_t * addr,
+			      size_t buflen, int flags)
+{
+	dwc_otg_pcd_ep_t *ep;
+	ep = get_ep_from_handle(pcd, pep);
+	return pcd->cfi->ops.ep_alloc_buf(pcd->cfi, pcd, ep, addr, buflen,
+					  flags);
+}
+#else
+uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep, dwc_dma_t * addr,
+			      size_t buflen, int flags);
+#endif
+
+/**
+ * PCD Callback function for notifying the PCD when resuming from
+ * suspend.
+ *
+ * @param p void pointer to the <code>dwc_otg_pcd_t</code>
+ */
+static int32_t dwc_otg_pcd_resume_cb(void *p)
+{
+	dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
+
+	if (pcd->fops->resume) {
+		pcd->fops->resume(pcd);
+	}
+
+	/* Stop the SRP timeout timer. */
+	if ((GET_CORE_IF(pcd)->core_params->phy_type != DWC_PHY_TYPE_PARAM_FS)
+	    || (!GET_CORE_IF(pcd)->core_params->i2c_enable)) {
+		if (GET_CORE_IF(pcd)->srp_timer_started) {
+			GET_CORE_IF(pcd)->srp_timer_started = 0;
+			DWC_TIMER_CANCEL(pcd->srp_timer);
+		}
+	}
+	return 1;
+}
+
+/**
+ * PCD Callback function for notifying the PCD device is suspended.
+ *
+ * @param p void pointer to the <code>dwc_otg_pcd_t</code>
+ */
+static int32_t dwc_otg_pcd_suspend_cb(void *p)
+{
+	dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
+
+	if (pcd->fops->suspend) {
+		pcd->fops->suspend(pcd);
+	}
+
+	return 1;
+}
+
+/**
+ * PCD Callback function for stopping the PCD when switching to Host
+ * mode.
+ *
+ * @param p void pointer to the <code>dwc_otg_pcd_t</code>
+ */
+static int32_t dwc_otg_pcd_stop_cb(void *p)
+{
+	dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
+	extern void dwc_otg_pcd_stop(dwc_otg_pcd_t * _pcd);
+
+	dwc_otg_pcd_stop(pcd);
+	return 1;
+}
+
+/**
+ * PCD Callback structure for handling mode switching.
+ */
+static dwc_otg_cil_callbacks_t pcd_callbacks = {
+	.start = dwc_otg_pcd_start_cb,
+	.stop = dwc_otg_pcd_stop_cb,
+	.suspend = dwc_otg_pcd_suspend_cb,
+	.resume_wakeup = dwc_otg_pcd_resume_cb,
+	.p = 0,			/* Set at registration */
+};
+
+/**
+ * This function allocates a DMA Descriptor chain for the Endpoint 
+ * buffer to be used for a transfer to/from the specified endpoint.
+ */
+dwc_otg_dev_dma_desc_t *dwc_otg_ep_alloc_desc_chain(uint32_t * dma_desc_addr,
+						uint32_t count)
+{
+
+	return dwc_dma_alloc(count * sizeof(dwc_otg_dev_dma_desc_t), dma_desc_addr);
+}
+
+/**
+ * This function frees a DMA Descriptor chain that was allocated by ep_alloc_desc.
+ */
+void dwc_otg_ep_free_desc_chain(dwc_otg_dev_dma_desc_t * desc_addr,
+				uint32_t dma_desc_addr, uint32_t count)
+{
+	dwc_dma_free(count * sizeof(dwc_otg_dev_dma_desc_t), desc_addr,
+		     dma_desc_addr);
+}
+
+#ifdef DWC_EN_ISOC
+
+/**
+ * This function initializes a descriptor chain for Isochronous transfer
+ *
+ * @param core_if Programming view of DWC_otg controller.
+ * @param dwc_ep The EP to start the transfer on.
+ *
+ */
+void dwc_otg_iso_ep_start_ddma_transfer(dwc_otg_core_if_t * core_if,
+					dwc_ep_t * dwc_ep)
+{
+
+	dsts_data_t dsts = {.d32 = 0 };
+	depctl_data_t depctl = {.d32 = 0 };
+	volatile uint32_t *addr;
+	int i, j;
+
+	if (dwc_ep->is_in)
+		dwc_ep->desc_cnt = dwc_ep->buf_proc_intrvl / dwc_ep->bInterval;
+	else
+		dwc_ep->desc_cnt =
+		    dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm /
+		    dwc_ep->bInterval;
+
+	/** Allocate descriptors for double buffering */
+	dwc_ep->iso_desc_addr =
+	    dwc_otg_ep_alloc_desc_chain(&dwc_ep->iso_dma_desc_addr,
+					dwc_ep->desc_cnt * 2);
+	if (dwc_ep->desc_addr) {
+		DWC_WARN("%s, can't allocate DMA descriptor chain\n", __func__);
+		return;
+	}
+
+	dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
+
+	/** ISO OUT EP */
+	if (dwc_ep->is_in == 0) {
+		dev_dma_desc_sts_t sts = {.d32 = 0 };
+		dwc_otg_dev_dma_desc_t *dma_desc = dwc_ep->iso_desc_addr;
+		dma_addr_t dma_ad;
+		uint32_t data_per_desc;
+		dwc_otg_dev_out_ep_regs_t *out_regs =
+		    core_if->dev_if->out_ep_regs[dwc_ep->num];
+		int offset;
+
+		addr = &core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl;
+		dma_ad = (dma_addr_t) dwc_read_reg32(&(out_regs->doepdma));
+
+		/** Buffer 0 descriptors setup */
+		dma_ad = dwc_ep->dma_addr0;
+
+		sts.b_iso_out.bs = BS_HOST_READY;
+		sts.b_iso_out.rxsts = 0;
+		sts.b_iso_out.l = 0;
+		sts.b_iso_out.sp = 0;
+		sts.b_iso_out.ioc = 0;
+		sts.b_iso_out.pid = 0;
+		sts.b_iso_out.framenum = 0;
+
+		offset = 0;
+		for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
+		     i += dwc_ep->pkt_per_frm) {
+
+			for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
+				data_per_desc =
+				    ((j + 1) * dwc_ep->maxpacket >
+				     dwc_ep->data_per_frame) ? dwc_ep->
+				    data_per_frame -
+				    j * dwc_ep->maxpacket : dwc_ep->maxpacket;
+
+				data_per_desc +=
+				    (data_per_desc % 4) ? (4 -
+							   data_per_desc %
+							   4) : 0;
+				sts.b_iso_out.rxbytes = data_per_desc;
+				dma_desc->buf = dma_ad;
+				dma_desc->status.d32 = sts.d32;
+
+				offset += data_per_desc;
+				dma_desc++;
+				dma_ad += data_per_desc;
+			}
+		}
+
+		for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
+			data_per_desc =
+			    ((j + 1) * dwc_ep->maxpacket >
+			     dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
+			    j * dwc_ep->maxpacket : dwc_ep->maxpacket;
+			data_per_desc +=
+			    (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
+			sts.b_iso_out.rxbytes = data_per_desc;
+			dma_desc->buf = dma_ad;
+			dma_desc->status.d32 = sts.d32;
+
+			offset += data_per_desc;
+			dma_desc++;
+			dma_ad += data_per_desc;
+		}
+
+		sts.b_iso_out.ioc = 1;
+		data_per_desc =
+		    ((j + 1) * dwc_ep->maxpacket >
+		     dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
+		    j * dwc_ep->maxpacket : dwc_ep->maxpacket;
+		data_per_desc +=
+		    (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
+		sts.b_iso_out.rxbytes = data_per_desc;
+
+		dma_desc->buf = dma_ad;
+		dma_desc->status.d32 = sts.d32;
+		dma_desc++;
+
+		/** Buffer 1 descriptors setup */
+		sts.b_iso_out.ioc = 0;
+		dma_ad = dwc_ep->dma_addr1;
+
+		offset = 0;
+		for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
+		     i += dwc_ep->pkt_per_frm) {
+			for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
+				data_per_desc =
+				    ((j + 1) * dwc_ep->maxpacket >
+				     dwc_ep->data_per_frame) ? dwc_ep->
+				    data_per_frame -
+				    j * dwc_ep->maxpacket : dwc_ep->maxpacket;
+				data_per_desc +=
+				    (data_per_desc % 4) ? (4 -
+							   data_per_desc %
+							   4) : 0;
+				sts.b_iso_out.rxbytes = data_per_desc;
+				dma_desc->buf = dma_ad;
+				dma_desc->status.d32 = sts.d32;
+
+				offset += data_per_desc;
+				dma_desc++;
+				dma_ad += data_per_desc;
+			}
+		}
+		for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
+			data_per_desc =
+			    ((j + 1) * dwc_ep->maxpacket >
+			     dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
+			    j * dwc_ep->maxpacket : dwc_ep->maxpacket;
+			data_per_desc +=
+			    (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
+			sts.b_iso_out.rxbytes = data_per_desc;
+			dma_desc->buf = dma_ad;
+			dma_desc->status.d32 = sts.d32;
+
+			offset += data_per_desc;
+			dma_desc++;
+			dma_ad += data_per_desc;
+		}
+
+		sts.b_iso_out.ioc = 1;
+		sts.b_iso_out.l = 1;
+		data_per_desc =
+		    ((j + 1) * dwc_ep->maxpacket >
+		     dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
+		    j * dwc_ep->maxpacket : dwc_ep->maxpacket;
+		data_per_desc +=
+		    (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
+		sts.b_iso_out.rxbytes = data_per_desc;
+
+		dma_desc->buf = dma_ad;
+		dma_desc->status.d32 = sts.d32;
+
+		dwc_ep->next_frame = 0;
+
+		/** Write dma_ad into DOEPDMA register */
+		dwc_write_reg32(&(out_regs->doepdma),
+				(uint32_t) dwc_ep->iso_dma_desc_addr);
+
+	}
+	/** ISO IN EP */
+	else {
+		dev_dma_desc_sts_t sts = {.d32 = 0 };
+		dwc_otg_dev_dma_desc_t *dma_desc = dwc_ep->iso_desc_addr;
+		dma_addr_t dma_ad;
+		dwc_otg_dev_in_ep_regs_t *in_regs =
+		    core_if->dev_if->in_ep_regs[dwc_ep->num];
+		unsigned int frmnumber;
+		fifosize_data_t txfifosize, rxfifosize;
+
+		txfifosize.d32 =
+		    dwc_read_reg32(&core_if->dev_if->in_ep_regs[dwc_ep->num]->
+				   dtxfsts);
+		rxfifosize.d32 =
+		    dwc_read_reg32(&core_if->core_global_regs->grxfsiz);
+
+		addr = &core_if->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
+
+		dma_ad = dwc_ep->dma_addr0;
+
+		dsts.d32 =
+		    dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
+
+		sts.b_iso_in.bs = BS_HOST_READY;
+		sts.b_iso_in.txsts = 0;
+		sts.b_iso_in.sp =
+		    (dwc_ep->data_per_frame % dwc_ep->maxpacket) ? 1 : 0;
+		sts.b_iso_in.ioc = 0;
+		sts.b_iso_in.pid = dwc_ep->pkt_per_frm;
+
+		frmnumber = dwc_ep->next_frame;
+
+		sts.b_iso_in.framenum = frmnumber;
+		sts.b_iso_in.txbytes = dwc_ep->data_per_frame;
+		sts.b_iso_in.l = 0;
+
+		/** Buffer 0 descriptors setup */
+		for (i = 0; i < dwc_ep->desc_cnt - 1; i++) {
+			dma_desc->buf = dma_ad;
+			dma_desc->status.d32 = sts.d32;
+			dma_desc++;
+
+			dma_ad += dwc_ep->data_per_frame;
+			sts.b_iso_in.framenum += dwc_ep->bInterval;
+		}
+
+		sts.b_iso_in.ioc = 1;
+		dma_desc->buf = dma_ad;
+		dma_desc->status.d32 = sts.d32;
+		++dma_desc;
+
+		/** Buffer 1 descriptors setup */
+		sts.b_iso_in.ioc = 0;
+		dma_ad = dwc_ep->dma_addr1;
+
+		for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
+		     i += dwc_ep->pkt_per_frm) {
+			dma_desc->buf = dma_ad;
+			dma_desc->status.d32 = sts.d32;
+			dma_desc++;
+
+			dma_ad += dwc_ep->data_per_frame;
+			sts.b_iso_in.framenum += dwc_ep->bInterval;
+
+			sts.b_iso_in.ioc = 0;
+		}
+		sts.b_iso_in.ioc = 1;
+		sts.b_iso_in.l = 1;
+
+		dma_desc->buf = dma_ad;
+		dma_desc->status.d32 = sts.d32;
+
+		dwc_ep->next_frame = sts.b_iso_in.framenum + dwc_ep->bInterval;
+
+		/** Write dma_ad into diepdma register */
+		dwc_write_reg32(&(in_regs->diepdma),
+				(uint32_t) dwc_ep->iso_dma_desc_addr);
+	}
+	/** Enable endpoint, clear nak  */
+	depctl.d32 = 0;
+	depctl.b.epena = 1;
+	depctl.b.usbactep = 1;
+	depctl.b.cnak = 1;
+
+	dwc_modify_reg32(addr, depctl.d32, depctl.d32);
+	depctl.d32 = dwc_read_reg32(addr);
+}
+
+/**
+ * This function initializes a descriptor chain for Isochronous transfer
+ *
+ * @param core_if Programming view of DWC_otg controller.
+ * @param ep The EP to start the transfer on.
+ *
+ */
+
+void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t * core_if,
+				       dwc_ep_t * ep)
+{
+	depctl_data_t depctl = {.d32 = 0 };
+	volatile uint32_t *addr;
+
+	if (ep->is_in) {
+		addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
+	} else {
+		addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
+	}
+
+	if (core_if->dma_enable == 0 || core_if->dma_desc_enable != 0) {
+		return;
+	} else {
+		deptsiz_data_t deptsiz = {.d32 = 0 };
+
+		ep->xfer_len =
+		    ep->data_per_frame * ep->buf_proc_intrvl / ep->bInterval;
+		ep->pkt_cnt =
+		    (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket;
+		ep->xfer_count = 0;
+		ep->xfer_buff =
+		    (ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0;
+		ep->dma_addr =
+		    (ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0;
+
+		if (ep->is_in) {
+			/* Program the transfer size and packet count
+			 *      as follows: xfersize = N * maxpacket +
+			 *      short_packet pktcnt = N + (short_packet
+			 *      exist ? 1 : 0)  
+			 */
+			deptsiz.b.mc = ep->pkt_per_frm;
+			deptsiz.b.xfersize = ep->xfer_len;
+			deptsiz.b.pktcnt =
+			    (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket;
+			dwc_write_reg32(&core_if->dev_if->in_ep_regs[ep->num]->
+					dieptsiz, deptsiz.d32);
+
+			/* Write the DMA register */
+			dwc_write_reg32(&
+					(core_if->dev_if->in_ep_regs[ep->num]->
+					 diepdma), (uint32_t) ep->dma_addr);
+
+		} else {
+			deptsiz.b.pktcnt =
+			    (ep->xfer_len + (ep->maxpacket - 1)) /
+			    ep->maxpacket;
+			deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
+
+			dwc_write_reg32(&core_if->dev_if->out_ep_regs[ep->num]->
+					doeptsiz, deptsiz.d32);
+
+			/* Write the DMA register */
+			dwc_write_reg32(&
+					(core_if->dev_if->out_ep_regs[ep->num]->
+					 doepdma), (uint32_t) ep->dma_addr);
+
+		}
+		/** Enable endpoint, clear nak  */
+		depctl.d32 = 0;
+		dwc_modify_reg32(addr, depctl.d32, depctl.d32);
+
+		depctl.b.epena = 1;
+		depctl.b.cnak = 1;
+
+		dwc_modify_reg32(addr, depctl.d32, depctl.d32);
+	}
+}
+
+/**
+ * This function does the setup for a data transfer for an EP and
+ * starts the transfer.	 For an IN transfer, the packets will be
+ * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers,
+ * the packets are unloaded from the Rx FIFO in the ISR.  the ISR.
+ *
+ * @param core_if Programming view of DWC_otg controller.
+ * @param ep The EP to start the transfer on.
+ */
+
+static void dwc_otg_iso_ep_start_transfer(dwc_otg_core_if_t * core_if,
+					  dwc_ep_t * ep)
+{
+	if (core_if->dma_enable) {
+		if (core_if->dma_desc_enable) {
+			if (ep->is_in) {
+				ep->desc_cnt = ep->pkt_cnt / ep->pkt_per_frm;
+			} else {
+				ep->desc_cnt = ep->pkt_cnt;
+			}
+			dwc_otg_iso_ep_start_ddma_transfer(core_if, ep);
+		} else {
+			if (core_if->pti_enh_enable) {
+				dwc_otg_iso_ep_start_buf_transfer(core_if, ep);
+			} else {
+				ep->cur_pkt_addr =
+				    (ep->proc_buf_num) ? ep->xfer_buff1 : ep->
+				    xfer_buff0;
+				ep->cur_pkt_dma_addr =
+				    (ep->proc_buf_num) ? ep->dma_addr1 : ep->
+				    dma_addr0;
+				dwc_otg_iso_ep_start_frm_transfer(core_if, ep);
+			}
+		}
+	} else {
+		ep->cur_pkt_addr =
+		    (ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0;
+		ep->cur_pkt_dma_addr =
+		    (ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0;
+		dwc_otg_iso_ep_start_frm_transfer(core_if, ep);
+	}
+}
+
+/**
+ * This function does the setup for a data transfer for an EP and
+ * starts the transfer.	 For an IN transfer, the packets will be
+ * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers,
+ * the packets are unloaded from the Rx FIFO in the ISR.  the ISR.
+ *
+ * @param core_if Programming view of DWC_otg controller.
+ * @param ep The EP to start the transfer on.
+ */
+
+void dwc_otg_iso_ep_stop_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
+{
+	depctl_data_t depctl = {.d32 = 0 };
+	volatile uint32_t *addr;
+
+	if (ep->is_in == 1) {
+		addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
+	} else {
+		addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
+	}
+
+	/* disable the ep */
+	depctl.d32 = dwc_read_reg32(addr);
+
+	depctl.b.epdis = 1;
+	depctl.b.snak = 1;
+
+	dwc_write_reg32(addr, depctl.d32);
+
+	if (core_if->dma_desc_enable &&
+	    ep->iso_desc_addr && ep->iso_dma_desc_addr) {
+		dwc_otg_ep_free_desc_chain(ep->iso_desc_addr,
+					   ep->iso_dma_desc_addr,
+					   ep->desc_cnt * 2);
+	}
+
+	/* reset varibales */
+	ep->dma_addr0 = 0;
+	ep->dma_addr1 = 0;
+	ep->xfer_buff0 = 0;
+	ep->xfer_buff1 = 0;
+	ep->data_per_frame = 0;
+	ep->data_pattern_frame = 0;
+	ep->sync_frame = 0;
+	ep->buf_proc_intrvl = 0;
+	ep->bInterval = 0;
+	ep->proc_buf_num = 0;
+	ep->pkt_per_frm = 0;
+	ep->pkt_per_frm = 0;
+	ep->desc_cnt = 0;
+	ep->iso_desc_addr = 0;
+	ep->iso_dma_desc_addr = 0;
+}
+
+int dwc_otg_pcd_iso_ep_start(dwc_otg_pcd_t * pcd, void *ep_handle,
+			     uint8_t * buf0, uint8_t * buf1, dwc_dma_t dma0,
+			     dwc_dma_t dma1, int sync_frame, int dp_frame,
+			     int data_per_frame, int start_frame,
+			     int buf_proc_intrvl, void *req_handle,
+			     int atomic_alloc)
+{
+	dwc_otg_pcd_ep_t *ep;
+	uint64_t flags = 0;
+	dwc_ep_t *dwc_ep;
+	int32_t frm_data;
+	dsts_data_t dsts;
+	dwc_otg_core_if_t *core_if;
+
+	ep = get_ep_from_handle(pcd, ep_handle);
+
+	if (!ep->desc || ep->dwc_ep.num == 0) {
+		DWC_WARN("bad ep\n");
+		return -DWC_E_INVALID;
+	}
+
+	DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
+	core_if = GET_CORE_IF(pcd);
+	dwc_ep = &ep->dwc_ep;
+
+	if (ep->iso_req_handle) {
+		DWC_WARN("ISO request in progress\n");
+	}
+
+	dwc_ep->dma_addr0 = dma0;
+	dwc_ep->dma_addr1 = dma1;
+
+	dwc_ep->xfer_buff0 = buf0;
+	dwc_ep->xfer_buff1 = buf1;
+
+	dwc_ep->data_per_frame = data_per_frame;
+
+	/** @todo - pattern data support is to be implemented in the future */
+	dwc_ep->data_pattern_frame = dp_frame;
+	dwc_ep->sync_frame = sync_frame;
+
+	dwc_ep->buf_proc_intrvl = buf_proc_intrvl;
+
+	dwc_ep->bInterval = 1 << (ep->desc->bInterval - 1);
+
+	dwc_ep->proc_buf_num = 0;
+
+	dwc_ep->pkt_per_frm = 0;
+	frm_data = ep->dwc_ep.data_per_frame;
+	while (frm_data > 0) {
+		dwc_ep->pkt_per_frm++;
+		frm_data -= ep->dwc_ep.maxpacket;
+	}
+
+	dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
+
+	if (start_frame == -1) {
+		dwc_ep->next_frame = dsts.b.soffn + 1;
+		if (dwc_ep->bInterval != 1) {
+			dwc_ep->next_frame =
+			    dwc_ep->next_frame + (dwc_ep->bInterval - 1 -
+						  dwc_ep->next_frame %
+						  dwc_ep->bInterval);
+		}
+	} else {
+		dwc_ep->next_frame = start_frame;
+	}
+
+	if (!core_if->pti_enh_enable) {
+		dwc_ep->pkt_cnt =
+		    dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm /
+		    dwc_ep->bInterval;
+	} else {
+		dwc_ep->pkt_cnt =
+		    (dwc_ep->data_per_frame *
+		     (dwc_ep->buf_proc_intrvl / dwc_ep->bInterval)
+		     - 1 + dwc_ep->maxpacket) / dwc_ep->maxpacket;
+	}
+
+	if (core_if->dma_desc_enable) {
+		dwc_ep->desc_cnt =
+		    dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm /
+		    dwc_ep->bInterval;
+	}
+
+	if (atomic_alloc) {
+		dwc_ep->pkt_info =
+		    dwc_alloc_atomic(sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt);
+	} else {
+		dwc_ep->pkt_info =
+		    dwc_alloc(sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt);
+	}
+	if (!dwc_ep->pkt_info) {
+		DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
+		return -DWC_E_NO_MEMORY;
+	}
+	if (core_if->pti_enh_enable) {
+		dwc_memset(dwc_ep->pkt_info, 0,
+			   sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt);
+	}
+
+	dwc_ep->cur_pkt = 0;
+	ep->iso_req_handle = req_handle;
+
+	DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
+	dwc_otg_iso_ep_start_transfer(core_if, dwc_ep);
+	return 0;
+}
+
+int dwc_otg_pcd_iso_ep_stop(dwc_otg_pcd_t * pcd, void *ep_handle,
+			    void *req_handle)
+{
+	uint64_t flags = 0;
+	dwc_otg_pcd_ep_t *ep;
+	dwc_ep_t *dwc_ep;
+
+	ep = get_ep_from_handle(pcd, ep_handle);
+	if (!ep || !ep->desc || ep->dwc_ep.num == 0) {
+		DWC_WARN("bad ep\n");
+		return -DWC_E_INVALID;
+	}
+	dwc_ep = &ep->dwc_ep;
+
+	dwc_otg_iso_ep_stop_transfer(GET_CORE_IF(pcd), dwc_ep);
+
+	dwc_free(dwc_ep->pkt_info);
+	DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
+	if (ep->iso_req_handle != req_handle) {
+		DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
+		return -DWC_E_INVALID;
+	}
+
+	DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
+
+	ep->iso_req_handle = 0;
+	return 0;
+}
+
+/**
+ * This function is used for perodical data exchnage between PCD and gadget drivers.
+ * for Isochronous EPs
+ *
+ *	- Every time a sync period completes this function is called to 
+ *	  perform data exchange between PCD and gadget
+ */
+void dwc_otg_iso_buffer_done(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep,
+			     void *req_handle)
+{
+	int i;
+	dwc_ep_t *dwc_ep;
+
+	dwc_ep = &ep->dwc_ep;
+
+	DWC_SPINUNLOCK(ep->pcd->lock);
+	pcd->fops->isoc_complete(pcd, ep->priv, ep->iso_req_handle,
+				 dwc_ep->proc_buf_num ^ 0x1);
+	DWC_SPINLOCK(ep->pcd->lock);
+
+	for (i = 0; i < dwc_ep->pkt_cnt; ++i) {
+		dwc_ep->pkt_info[i].status = 0;
+		dwc_ep->pkt_info[i].offset = 0;
+		dwc_ep->pkt_info[i].length = 0;
+	}
+}
+
+int dwc_otg_pcd_get_iso_packet_count(dwc_otg_pcd_t * pcd, void *ep_handle,
+				     void *iso_req_handle)
+{
+	dwc_otg_pcd_ep_t *ep;
+	dwc_ep_t *dwc_ep;
+
+	ep = get_ep_from_handle(pcd, ep_handle);
+	dwc_ep = &ep->dwc_ep;
+
+	return dwc_ep->pkt_cnt;
+}
+
+void dwc_otg_pcd_get_iso_packet_params(dwc_otg_pcd_t * pcd, void *ep_handle,
+				       void *iso_req_handle, int packet,
+				       int *status, int *actual, int *offset)
+{
+	dwc_otg_pcd_ep_t *ep;
+	dwc_ep_t *dwc_ep;
+
+	ep = get_ep_from_handle(pcd, ep_handle);
+	dwc_ep = &ep->dwc_ep;
+
+	*status = dwc_ep->pkt_info[packet].status;
+	*actual = dwc_ep->pkt_info[packet].length;
+	*offset = dwc_ep->pkt_info[packet].offset;
+}
+
+#endif				/* DWC_EN_ISOC */
+
+static void dwc_otg_pcd_init_ep(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * pcd_ep,
+				uint32_t is_in, uint32_t ep_num)
+{
+	/* Init EP structure */
+	pcd_ep->desc = 0;
+	pcd_ep->pcd = pcd;
+	pcd_ep->stopped = 1;
+	pcd_ep->queue_sof = 0;
+
+	/* Init DWC ep structure */
+	pcd_ep->dwc_ep.is_in = is_in;
+	pcd_ep->dwc_ep.num = ep_num;
+	pcd_ep->dwc_ep.active = 0;
+	pcd_ep->dwc_ep.tx_fifo_num = 0;
+	/* Control until ep is actvated */
+	pcd_ep->dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL;
+	pcd_ep->dwc_ep.maxpacket = MAX_PACKET_SIZE;
+	pcd_ep->dwc_ep.dma_addr = 0;
+	pcd_ep->dwc_ep.start_xfer_buff = 0;
+	pcd_ep->dwc_ep.xfer_buff = 0;
+	pcd_ep->dwc_ep.xfer_len = 0;
+	pcd_ep->dwc_ep.xfer_count = 0;
+	pcd_ep->dwc_ep.sent_zlp = 0;
+	pcd_ep->dwc_ep.total_len = 0;
+	pcd_ep->dwc_ep.desc_addr = 0;
+	pcd_ep->dwc_ep.dma_desc_addr = 0;
+	DWC_CIRCLEQ_INIT(&pcd_ep->queue);
+}
+
+/**
+ * Initialise ep's
+ */
+static void dwc_otg_pcd_reinit(dwc_otg_pcd_t * pcd)
+{
+	int i;
+	uint32_t hwcfg1;
+	dwc_otg_pcd_ep_t *ep;
+	int in_ep_cntr, out_ep_cntr;
+	uint32_t num_in_eps = (GET_CORE_IF(pcd))->dev_if->num_in_eps;
+	uint32_t num_out_eps = (GET_CORE_IF(pcd))->dev_if->num_out_eps;
+
+	/**
+	 * Initialize the EP0 structure.
+	 */
+	ep = &pcd->ep0;
+	dwc_otg_pcd_init_ep(pcd, ep, 0, 0);
+
+	in_ep_cntr = 0;
+	hwcfg1 = (GET_CORE_IF(pcd))->hwcfg1.d32 >> 3;
+	for (i = 1; in_ep_cntr < num_in_eps; i++) {
+		if ((hwcfg1 & 0x1) == 0) {
+			dwc_otg_pcd_ep_t *ep = &pcd->in_ep[in_ep_cntr];
+			in_ep_cntr++;
+			/**
+			 * @todo NGS: Add direction to EP, based on contents
+			 * of HWCFG1.  Need a copy of HWCFG1 in pcd structure?
+			 * sprintf(";r
+			 */
+			dwc_otg_pcd_init_ep(pcd, ep, 1 /* IN */ , i);
+
+			DWC_CIRCLEQ_INIT(&ep->queue);
+		}
+		hwcfg1 >>= 2;
+	}
+
+	out_ep_cntr = 0;
+	hwcfg1 = (GET_CORE_IF(pcd))->hwcfg1.d32 >> 2;
+	for (i = 1; out_ep_cntr < num_out_eps; i++) {
+		if ((hwcfg1 & 0x1) == 0) {
+			dwc_otg_pcd_ep_t *ep = &pcd->out_ep[out_ep_cntr];
+			out_ep_cntr++;
+			/**
+			 * @todo NGS: Add direction to EP, based on contents
+			 * of HWCFG1.  Need a copy of HWCFG1 in pcd structure?
+			 * sprintf(";r
+			 */
+			dwc_otg_pcd_init_ep(pcd, ep, 0 /* OUT */ , i);
+			DWC_CIRCLEQ_INIT(&ep->queue);
+		}
+		hwcfg1 >>= 2;
+	}
+
+	pcd->ep0state = EP0_DISCONNECT;
+	pcd->ep0.dwc_ep.maxpacket = MAX_EP0_SIZE;
+	pcd->ep0.dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL;
+}
+
+/**
+ * This function is called when the SRP timer expires.	The SRP should
+ * complete within 6 seconds.
+ */
+static void srp_timeout(void *ptr)
+{
+	gotgctl_data_t gotgctl;
+	dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
+	volatile uint32_t *addr = &core_if->core_global_regs->gotgctl;
+
+	gotgctl.d32 = dwc_read_reg32(addr);
+
+	core_if->srp_timer_started = 0;
+
+	if ((core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS) &&
+	    (core_if->core_params->i2c_enable)) {
+		DWC_PRINTF("SRP Timeout\n");
+
+		if ((core_if->srp_success) && (gotgctl.b.bsesvld)) {
+			if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
+				core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->
+							       p);
+			}
+
+			/* Clear Session Request */
+			gotgctl.d32 = 0;
+			gotgctl.b.sesreq = 1;
+			dwc_modify_reg32(&core_if->core_global_regs->gotgctl,
+					 gotgctl.d32, 0);
+
+			core_if->srp_success = 0;
+		} else {
+			__DWC_ERROR("Device not connected/responding\n");
+			gotgctl.b.sesreq = 0;
+			dwc_write_reg32(addr, gotgctl.d32);
+		}
+	} else if (gotgctl.b.sesreq) {
+		DWC_PRINTF("SRP Timeout\n");
+
+		__DWC_ERROR("Device not connected/responding\n");
+		gotgctl.b.sesreq = 0;
+		dwc_write_reg32(addr, gotgctl.d32);
+	} else {
+		DWC_PRINTF(" SRP GOTGCTL=%0x\n", gotgctl.d32);
+	}
+}
+
+/**
+ * Tasklet
+ *
+ */
+extern void start_next_request(dwc_otg_pcd_ep_t * ep);
+
+static void start_xfer_tasklet_func(void *data)
+{
+	dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) data;
+	dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+
+	int i;
+	depctl_data_t diepctl;
+
+	DWC_DEBUGPL(DBG_PCDV, "Start xfer tasklet\n");
+
+	diepctl.d32 = dwc_read_reg32(&core_if->dev_if->in_ep_regs[0]->diepctl);
+
+	if (pcd->ep0.queue_sof) {
+		pcd->ep0.queue_sof = 0;
+		start_next_request(&pcd->ep0);
+		// break;
+	}
+
+	for (i = 0; i < core_if->dev_if->num_in_eps; i++) {
+		depctl_data_t diepctl;
+		diepctl.d32 =
+		    dwc_read_reg32(&core_if->dev_if->in_ep_regs[i]->diepctl);
+
+		if (pcd->in_ep[i].queue_sof) {
+			pcd->in_ep[i].queue_sof = 0;
+			start_next_request(&pcd->in_ep[i]);
+			// break;
+		}
+	}
+
+	return;
+}
+
+/**
+ * This function initialized the PCD portion of the driver.
+ *
+ */
+dwc_otg_pcd_t *dwc_otg_pcd_init(dwc_otg_core_if_t * core_if)
+{
+	dwc_otg_pcd_t *pcd = 0;
+	dwc_otg_dev_if_t *dev_if;
+
+	/*
+	 * Allocate PCD structure
+	 */
+	pcd = dwc_alloc(sizeof(dwc_otg_pcd_t));
+
+	if (pcd == 0) {
+		return NULL;
+	}
+
+	pcd->lock = DWC_SPINLOCK_ALLOC();
+        DWC_DEBUGPL(DBG_HCDV, "Init of PCD %p given core_if %p\n",
+                    pcd, core_if);//GRAYG
+	pcd->core_if = core_if;
+	if (!pcd->lock) {
+		DWC_ERROR("Could not allocate lock for pcd");
+		dwc_free(pcd);
+		return NULL;
+	}
+	dev_if = core_if->dev_if;
+
+	if (core_if->hwcfg4.b.ded_fifo_en) {
+		DWC_PRINTF("Dedicated Tx FIFOs mode\n");
+	} else {
+		DWC_PRINTF("Shared Tx FIFO mode\n");
+	}
+
+	/*
+	 * Initialized the Core for Device mode.
+	 */
+	if (dwc_otg_is_device_mode(core_if)) {
+		dwc_otg_core_dev_init(core_if);
+	}
+
+	/*
+	 * Register the PCD Callbacks.
+	 */
+	dwc_otg_cil_register_pcd_callbacks(core_if, &pcd_callbacks, pcd);
+
+	/*
+	 * Initialize the DMA buffer for SETUP packets
+	 */
+	if (GET_CORE_IF(pcd)->dma_enable) {
+		pcd->setup_pkt =
+		    dwc_dma_alloc(sizeof(*pcd->setup_pkt) * 5,
+				  &pcd->setup_pkt_dma_handle);
+		if (pcd->setup_pkt == 0) {
+			dwc_free(pcd);
+			return NULL;
+		}
+
+		pcd->status_buf =
+		    dwc_dma_alloc(sizeof(uint16_t),
+				  &pcd->status_buf_dma_handle);
+		if (pcd->status_buf == 0) {
+			dwc_dma_free(sizeof(*pcd->setup_pkt) * 5,
+				     pcd->setup_pkt, pcd->setup_pkt_dma_handle);
+			dwc_free(pcd);
+			return NULL;
+		}
+
+		if (GET_CORE_IF(pcd)->dma_desc_enable) {
+			dev_if->setup_desc_addr[0] =
+			    dwc_otg_ep_alloc_desc_chain(&dev_if->
+							dma_setup_desc_addr[0],
+							1);
+			dev_if->setup_desc_addr[1] =
+			    dwc_otg_ep_alloc_desc_chain(&dev_if->
+							dma_setup_desc_addr[1],
+							1);
+			dev_if->in_desc_addr =
+			    dwc_otg_ep_alloc_desc_chain(&dev_if->
+							dma_in_desc_addr, 1);
+			dev_if->out_desc_addr =
+			    dwc_otg_ep_alloc_desc_chain(&dev_if->
+							dma_out_desc_addr, 1);
+
+			if (dev_if->setup_desc_addr[0] == 0
+			    || dev_if->setup_desc_addr[1] == 0
+			    || dev_if->in_desc_addr == 0
+			    || dev_if->out_desc_addr == 0) {
+
+				if (dev_if->out_desc_addr)
+					dwc_otg_ep_free_desc_chain(dev_if->
+								   out_desc_addr,
+								   dev_if->
+								   dma_out_desc_addr,
+								   1);
+				if (dev_if->in_desc_addr)
+					dwc_otg_ep_free_desc_chain(dev_if->
+								   in_desc_addr,
+								   dev_if->
+								   dma_in_desc_addr,
+								   1);
+				if (dev_if->setup_desc_addr[1])
+					dwc_otg_ep_free_desc_chain(dev_if->
+								   setup_desc_addr
+								   [1],
+								   dev_if->
+								   dma_setup_desc_addr
+								   [1], 1);
+				if (dev_if->setup_desc_addr[0])
+					dwc_otg_ep_free_desc_chain(dev_if->
+								   setup_desc_addr
+								   [0],
+								   dev_if->
+								   dma_setup_desc_addr
+								   [0], 1);
+
+				dwc_dma_free(sizeof(*pcd->setup_pkt) * 5,
+					     pcd->setup_pkt,
+					     pcd->setup_pkt_dma_handle);
+				dwc_dma_free(sizeof(*pcd->status_buf),
+					     pcd->status_buf,
+					     pcd->status_buf_dma_handle);
+
+				dwc_free(pcd);
+
+				return NULL;
+			}
+		}
+	} else {
+		pcd->setup_pkt = dwc_alloc(sizeof(*pcd->setup_pkt) * 5);
+		if (pcd->setup_pkt == 0) {
+			dwc_free(pcd);
+			return NULL;
+		}
+
+		pcd->status_buf = dwc_alloc(sizeof(uint16_t));
+		if (pcd->status_buf == 0) {
+			dwc_free(pcd->setup_pkt);
+			dwc_free(pcd);
+			return NULL;
+		}
+	}
+
+	dwc_otg_pcd_reinit(pcd);
+
+	/* Allocate the cfi object for the PCD */
+#ifdef DWC_UTE_CFI
+	pcd->cfi = dwc_alloc(sizeof(cfiobject_t));
+	if (NULL == pcd->cfi)
+		return NULL;
+	if (init_cfi(pcd->cfi)) {
+		CFI_INFO("%s: Failed to init the CFI object\n", __func__);
+		return NULL;
+	}
+#endif
+
+	/* Initialize tasklets */
+	pcd->start_xfer_tasklet = DWC_TASK_ALLOC(start_xfer_tasklet_func, pcd);
+	pcd->test_mode_tasklet = DWC_TASK_ALLOC(do_test_mode, pcd);
+	/* Initialize timer */
+	pcd->srp_timer = DWC_TIMER_ALLOC("SRP TIMER", srp_timeout, core_if);
+	return pcd;
+}
+
+void dwc_otg_pcd_remove(dwc_otg_pcd_t * pcd)
+{
+	dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
+
+	if (GET_CORE_IF(pcd)->dma_enable) {
+		dwc_dma_free(sizeof(*pcd->setup_pkt) * 5, pcd->setup_pkt,
+			     pcd->setup_pkt_dma_handle);
+		dwc_dma_free(sizeof(uint16_t), pcd->status_buf,
+			     pcd->status_buf_dma_handle);
+		if (GET_CORE_IF(pcd)->dma_desc_enable) {
+			dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[0],
+						   dev_if->
+						   dma_setup_desc_addr[0], 1);
+			dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[1],
+						   dev_if->
+						   dma_setup_desc_addr[1], 1);
+			dwc_otg_ep_free_desc_chain(dev_if->in_desc_addr,
+						   dev_if->dma_in_desc_addr, 1);
+			dwc_otg_ep_free_desc_chain(dev_if->out_desc_addr,
+						   dev_if->dma_out_desc_addr,
+						   1);
+		}
+	} else {
+		dwc_free(pcd->setup_pkt);
+		dwc_free(pcd->status_buf);
+	}
+	DWC_SPINLOCK_FREE(pcd->lock);
+	DWC_TASK_FREE(pcd->start_xfer_tasklet);
+	DWC_TASK_FREE(pcd->test_mode_tasklet);
+	DWC_TIMER_FREE(pcd->srp_timer);
+
+/* Release the CFI object's dynamic memory */
+#ifdef DWC_UTE_CFI
+	if (pcd->cfi->ops.release) {
+		pcd->cfi->ops.release(pcd->cfi);
+	}
+#endif
+
+	dwc_free(pcd);
+}
+
+uint32_t dwc_otg_pcd_is_dualspeed(dwc_otg_pcd_t * pcd)
+{
+	dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+
+	if ((core_if->core_params->speed == DWC_SPEED_PARAM_FULL) ||
+	    ((core_if->hwcfg2.b.hs_phy_type == 2) &&
+	     (core_if->hwcfg2.b.fs_phy_type == 1) &&
+	     (core_if->core_params->ulpi_fs_ls))) {
+		return 0;
+	}
+
+	return 1;
+}
+
+uint32_t dwc_otg_pcd_is_otg(dwc_otg_pcd_t * pcd)
+{
+	dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+	gusbcfg_data_t usbcfg = {.d32 = 0 };
+
+	usbcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->gusbcfg);
+	if (!usbcfg.b.srpcap || !usbcfg.b.hnpcap) {
+		return 0;
+	}
+
+	return 1;
+}
+
+/**
+ * This function assigns periodic Tx FIFO to an periodic EP
+ * in shared Tx FIFO mode
+ */
+static uint32_t assign_tx_fifo(dwc_otg_core_if_t * core_if)
+{
+	uint32_t TxMsk = 1;
+	int i;
+
+	for (i = 0; i < core_if->hwcfg4.b.num_in_eps; ++i) {
+		if ((TxMsk & core_if->tx_msk) == 0) {
+			core_if->tx_msk |= TxMsk;
+			return i + 1;
+		}
+		TxMsk <<= 1;
+	}
+	return 0;
+}
+
+/**
+ * This function assigns periodic Tx FIFO to an periodic EP
+ * in shared Tx FIFO mode
+ */
+static uint32_t assign_perio_tx_fifo(dwc_otg_core_if_t * core_if)
+{
+	uint32_t PerTxMsk = 1;
+	int i;
+	for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; ++i) {
+		if ((PerTxMsk & core_if->p_tx_msk) == 0) {
+			core_if->p_tx_msk |= PerTxMsk;
+			return i + 1;
+		}
+		PerTxMsk <<= 1;
+	}
+	return 0;
+}
+
+/**
+ * This function releases periodic Tx FIFO
+ * in shared Tx FIFO mode
+ */
+static void release_perio_tx_fifo(dwc_otg_core_if_t * core_if,
+				  uint32_t fifo_num)
+{
+	core_if->p_tx_msk =
+	    (core_if->p_tx_msk & (1 << (fifo_num - 1))) ^ core_if->p_tx_msk;
+}
+
+/**
+ * This function releases periodic Tx FIFO
+ * in shared Tx FIFO mode
+ */
+static void release_tx_fifo(dwc_otg_core_if_t * core_if, uint32_t fifo_num)
+{
+	core_if->tx_msk =
+	    (core_if->tx_msk & (1 << (fifo_num - 1))) ^ core_if->tx_msk;
+}
+
+int dwc_otg_pcd_ep_enable(dwc_otg_pcd_t * pcd,
+			  const uint8_t * ep_desc, void *usb_ep)
+{
+	int num, dir;
+	dwc_otg_pcd_ep_t *ep = 0;
+	const usb_endpoint_descriptor_t *desc;
+	uint64_t flags;
+	int retval = 0;
+
+	desc = (const usb_endpoint_descriptor_t *)ep_desc;
+
+	if (!desc) {
+		pcd->ep0.priv = usb_ep;
+		ep = &pcd->ep0;
+		retval = -DWC_E_INVALID;
+		goto out;
+	}
+
+	num = UE_GET_ADDR(desc->bEndpointAddress);
+	dir = UE_GET_DIR(desc->bEndpointAddress);
+
+	if (!desc->wMaxPacketSize) {
+		DWC_WARN("bad maxpacketsize\n");
+		retval = -DWC_E_INVALID;
+		goto out;
+	}
+
+	if (dir == UE_DIR_IN) {
+		ep = &pcd->in_ep[num - 1];
+	} else {
+		ep = &pcd->out_ep[num - 1];
+	}
+
+	DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
+
+	ep->desc = desc;
+	ep->priv = usb_ep;
+
+	/*
+	 * Activate the EP
+	 */
+	ep->stopped = 0;
+
+	ep->dwc_ep.is_in = (dir == UE_DIR_IN);
+	ep->dwc_ep.maxpacket = UGETW(desc->wMaxPacketSize);
+
+	ep->dwc_ep.type = desc->bmAttributes & UE_XFERTYPE;
+
+	if (ep->dwc_ep.is_in) {
+		if (!GET_CORE_IF(pcd)->en_multiple_tx_fifo) {
+			ep->dwc_ep.tx_fifo_num = 0;
+
+			if (ep->dwc_ep.type == UE_ISOCHRONOUS) {
+				/*
+				 * if ISOC EP then assign a Periodic Tx FIFO.
+				 */
+				ep->dwc_ep.tx_fifo_num =
+				    assign_perio_tx_fifo(GET_CORE_IF(pcd));
+			}
+		} else {
+			/*
+			 * if Dedicated FIFOs mode is on then assign a Tx FIFO.
+			 */
+			ep->dwc_ep.tx_fifo_num =
+			    assign_tx_fifo(GET_CORE_IF(pcd));
+
+		}
+	}
+	/* Set initial data PID. */
+	if (ep->dwc_ep.type == UE_BULK) {
+		ep->dwc_ep.data_pid_start = 0;
+	}
+
+	/* Alloc DMA Descriptors */
+	if (GET_CORE_IF(pcd)->dma_desc_enable) {
+		if (ep->dwc_ep.type != UE_ISOCHRONOUS) {
+			ep->dwc_ep.desc_addr =
+			    dwc_otg_ep_alloc_desc_chain(&ep->dwc_ep.
+							dma_desc_addr,
+							MAX_DMA_DESC_CNT);
+			if (!ep->dwc_ep.desc_addr) {
+				DWC_WARN("%s, can't allocate DMA descriptor\n",
+					 __func__);
+				retval = -DWC_E_SHUTDOWN;
+				DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
+				goto out;
+			}
+		}
+	}
+
+	DWC_DEBUGPL(DBG_PCD, "Activate %s: type=%d, mps=%d desc=%p\n",
+		    (ep->dwc_ep.is_in ? "IN" : "OUT"),
+		    ep->dwc_ep.type, ep->dwc_ep.maxpacket, ep->desc);
+
+	dwc_otg_ep_activate(GET_CORE_IF(pcd), &ep->dwc_ep);
+
+#ifdef DWC_UTE_CFI
+	if (pcd->cfi->ops.ep_enable) {
+		pcd->cfi->ops.ep_enable(pcd->cfi, pcd, ep);
+	}
+#endif
+
+	DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
+
+      out:
+	return retval;
+}
+
+int dwc_otg_pcd_ep_disable(dwc_otg_pcd_t * pcd, void *ep_handle)
+{
+	dwc_otg_pcd_ep_t *ep;
+	uint64_t flags;
+	dwc_otg_dev_dma_desc_t *desc_addr;
+	dwc_dma_t dma_desc_addr;
+
+	ep = get_ep_from_handle(pcd, ep_handle);
+
+	if (!ep || !ep->desc) {
+		DWC_DEBUGPL(DBG_PCD, "%s, %d %s not enabled\n", __func__,
+			    ep->dwc_ep.num, ep->dwc_ep.is_in ? "IN" : "OUT");
+		return -DWC_E_INVALID;
+	}
+
+	DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
+
+	dwc_otg_request_nuke(ep);
+
+	dwc_otg_ep_deactivate(GET_CORE_IF(pcd), &ep->dwc_ep);
+	ep->desc = 0;
+	ep->stopped = 1;
+
+	if (ep->dwc_ep.is_in) {
+		dwc_otg_flush_tx_fifo(GET_CORE_IF(pcd), ep->dwc_ep.tx_fifo_num);
+		release_perio_tx_fifo(GET_CORE_IF(pcd), ep->dwc_ep.tx_fifo_num);
+		release_tx_fifo(GET_CORE_IF(pcd), ep->dwc_ep.tx_fifo_num);
+	}
+
+	/* Free DMA Descriptors */
+	if (GET_CORE_IF(pcd)->dma_desc_enable) {
+		if (ep->dwc_ep.type != UE_ISOCHRONOUS) {
+			desc_addr = ep->dwc_ep.desc_addr;
+			dma_desc_addr = ep->dwc_ep.dma_desc_addr;
+
+			/* Cannot call dma_free_coherent() with IRQs disabled */
+			DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
+			dwc_otg_ep_free_desc_chain(desc_addr, dma_desc_addr,
+						   MAX_DMA_DESC_CNT);
+
+			goto out_unlocked;
+		}
+	}
+
+	DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
+
+      out_unlocked:
+	DWC_DEBUGPL(DBG_PCD, "%d %s disabled\n", ep->dwc_ep.num,
+		    ep->dwc_ep.is_in ? "IN" : "OUT");
+	return 0;
+
+}
+
+int dwc_otg_pcd_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,
+			 uint8_t * buf, dwc_dma_t dma_buf, uint32_t buflen,
+			 int zero, void *req_handle, int atomic_alloc)
+{
+	int prevented = 0;
+	uint64_t flags;
+	dwc_otg_pcd_request_t *req;
+	dwc_otg_pcd_ep_t *ep;
+	uint32_t max_transfer;
+
+	ep = get_ep_from_handle(pcd, ep_handle);
+	if ((!ep->desc && ep->dwc_ep.num != 0)) {
+		DWC_WARN("bad ep\n");
+		return -DWC_E_INVALID;
+	}
+
+	if (atomic_alloc) {
+		req = dwc_alloc_atomic(sizeof(*req));
+	} else {
+		req = dwc_alloc(sizeof(*req));
+	}
+
+	if (!req) {
+		return -DWC_E_NO_MEMORY;
+	}
+	DWC_CIRCLEQ_INIT_ENTRY(req, queue_entry);
+	if (!GET_CORE_IF(pcd)->core_params->opt) {
+		if (ep->dwc_ep.num != 0) {
+			DWC_ERROR("queue req %p, len %d buf %p\n",
+				  req_handle, buflen, buf);
+		}
+	}
+
+	req->buf = buf;
+	req->dma = dma_buf;
+	req->length = buflen;
+	req->sent_zlp = zero;
+	req->priv = req_handle;
+
+	DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
+
+	/*
+	 * For EP0 IN without premature status, zlp is required?
+	 */
+	if (ep->dwc_ep.num == 0 && ep->dwc_ep.is_in) {
+		DWC_DEBUGPL(DBG_PCDV, "%d-OUT ZLP\n", ep->dwc_ep.num);
+		//_req->zero = 1;
+	}
+
+	/* Start the transfer */
+	if (DWC_CIRCLEQ_EMPTY(&ep->queue) && !ep->stopped) {
+		/* EP0 Transfer? */
+		if (ep->dwc_ep.num == 0) {
+			switch (pcd->ep0state) {
+			case EP0_IN_DATA_PHASE:
+				DWC_DEBUGPL(DBG_PCD,
+					    "%s ep0: EP0_IN_DATA_PHASE\n",
+					    __func__);
+				break;
+
+			case EP0_OUT_DATA_PHASE:
+				DWC_DEBUGPL(DBG_PCD,
+					    "%s ep0: EP0_OUT_DATA_PHASE\n",
+					    __func__);
+				if (pcd->request_config) {
+					/* Complete STATUS PHASE */
+					ep->dwc_ep.is_in = 1;
+					pcd->ep0state = EP0_IN_STATUS_PHASE;
+				}
+				break;
+
+			case EP0_IN_STATUS_PHASE:
+				DWC_DEBUGPL(DBG_PCD,
+					    "%s ep0: EP0_IN_STATUS_PHASE\n",
+					    __func__);
+				break;
+
+			default:
+				DWC_DEBUGPL(DBG_ANY, "ep0: odd state %d\n",
+					    pcd->ep0state);
+				DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
+				return -DWC_E_SHUTDOWN;
+			}
+
+			ep->dwc_ep.dma_addr = dma_buf;
+			ep->dwc_ep.start_xfer_buff = buf;
+			ep->dwc_ep.xfer_buff = buf;
+			ep->dwc_ep.xfer_len = buflen;
+			ep->dwc_ep.xfer_count = 0;
+			ep->dwc_ep.sent_zlp = 0;
+			ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
+
+			if (zero) {
+				if ((ep->dwc_ep.xfer_len %
+				     ep->dwc_ep.maxpacket == 0)
+				    && (ep->dwc_ep.xfer_len != 0)) {
+					ep->dwc_ep.sent_zlp = 1;
+				}
+
+			}
+
+			dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd),
+						   &ep->dwc_ep);
+		}		// non-ep0 endpoints
+		else {
+#ifdef DWC_UTE_CFI
+			if (ep->dwc_ep.buff_mode != BM_STANDARD) {
+				/* store the request length */
+				ep->dwc_ep.cfi_req_len = buflen;
+				pcd->cfi->ops.build_descriptors(pcd->cfi, pcd,
+								ep, req);
+		} else {
+#endif
+				max_transfer =
+				    GET_CORE_IF(ep->pcd)->core_params->
+				    max_transfer_size;
+
+			/* Setup and start the Transfer */
+			ep->dwc_ep.dma_addr = dma_buf;
+			ep->dwc_ep.start_xfer_buff = buf;
+			ep->dwc_ep.xfer_buff = buf;
+			ep->dwc_ep.xfer_len = 0;
+			ep->dwc_ep.xfer_count = 0;
+			ep->dwc_ep.sent_zlp = 0;
+			ep->dwc_ep.total_len = buflen;
+
+			ep->dwc_ep.maxxfer = max_transfer;
+			if (GET_CORE_IF(pcd)->dma_desc_enable) {
+					uint32_t out_max_xfer =
+					    DDMA_MAX_TRANSFER_SIZE -
+					    (DDMA_MAX_TRANSFER_SIZE % 4);
+				if (ep->dwc_ep.is_in) {
+					if (ep->dwc_ep.maxxfer >
+					    DDMA_MAX_TRANSFER_SIZE) {
+						ep->dwc_ep.maxxfer =
+						    DDMA_MAX_TRANSFER_SIZE;
+					}
+				} else {
+						if (ep->dwc_ep.maxxfer >
+						    out_max_xfer) {
+						ep->dwc_ep.maxxfer =
+						    out_max_xfer;
+					}
+				}
+			}
+			if (ep->dwc_ep.maxxfer < ep->dwc_ep.total_len) {
+				ep->dwc_ep.maxxfer -=
+					    (ep->dwc_ep.maxxfer %
+					     ep->dwc_ep.maxpacket);
+			}
+
+			if (zero) {
+				if ((ep->dwc_ep.total_len %
+					     ep->dwc_ep.maxpacket == 0)
+					    && (ep->dwc_ep.total_len != 0)) {
+					ep->dwc_ep.sent_zlp = 1;
+				}
+			}
+#ifdef DWC_UTE_CFI
+			}
+#endif
+			dwc_otg_ep_start_transfer(GET_CORE_IF(pcd),
+						  &ep->dwc_ep);
+		}
+	}
+
+	if ((req != 0) || prevented) {
+		++pcd->request_pending;
+		DWC_CIRCLEQ_INSERT_TAIL(&ep->queue, req, queue_entry);
+		if (ep->dwc_ep.is_in && ep->stopped
+		    && !(GET_CORE_IF(pcd)->dma_enable)) {
+			/** @todo NGS Create a function for this. */
+			diepmsk_data_t diepmsk = {.d32 = 0 };
+			diepmsk.b.intktxfemp = 1;
+			if (GET_CORE_IF(pcd)->multiproc_int_enable) {
+				dwc_modify_reg32(&GET_CORE_IF(pcd)->dev_if->
+						 dev_global_regs->
+						 diepeachintmsk[ep->dwc_ep.num],
+						 0, diepmsk.d32);
+			} else {
+				dwc_modify_reg32(&GET_CORE_IF(pcd)->dev_if->
+						 dev_global_regs->diepmsk, 0,
+						 diepmsk.d32);
+			}
+
+		}
+	}
+
+	DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
+
+	return 0;
+}
+int dwc_otg_pcd_ep_dequeue(dwc_otg_pcd_t * pcd, void *ep_handle,
+			   void *req_handle)
+{
+	uint64_t flags;
+	dwc_otg_pcd_request_t *req;
+	dwc_otg_pcd_ep_t *ep;
+
+	ep = get_ep_from_handle(pcd, ep_handle);
+	if (!ep->desc && ep->dwc_ep.num != 0) {
+		DWC_WARN("bad argument\n");
+		return -DWC_E_INVALID;
+	}
+
+	DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
+
+	/* make sure it's actually queued on this endpoint */
+	DWC_CIRCLEQ_FOREACH(req, &ep->queue, queue_entry) {
+		if (req->priv == (void *)req_handle) {
+			break;
+		}
+	}
+
+	if (req->priv != (void *)req_handle) {
+		DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
+		return -DWC_E_INVALID;
+	}
+
+	if (!DWC_CIRCLEQ_EMPTY_ENTRY(req, queue_entry)) {
+		dwc_otg_request_done(ep, req, -DWC_E_RESTART);
+	} else {
+		req = 0;
+	}
+
+	DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
+
+	return req ? 0 : -DWC_E_SHUTDOWN;
+
+}
+
+/**
+ * dwc_otg_pcd_ep_wedge - sets the halt feature and ignores clear requests
+ *
+ * Use this to stall an endpoint and ignore CLEAR_FEATURE(HALT_ENDPOINT)
+ * requests. If the gadget driver clears the halt status, it will
+ * automatically unwedge the endpoint.
+ *
+ * Returns zero on success, else negative DWC error code.
+ */
+int dwc_otg_pcd_ep_wedge(dwc_otg_pcd_t * pcd, void *ep_handle)
+{
+	dwc_otg_pcd_ep_t *ep;
+	uint64_t flags;
+	int retval = 0;
+
+	ep = get_ep_from_handle(pcd, ep_handle);
+
+	if ((!ep->desc && ep != &pcd->ep0) ||
+	    (ep->desc && (ep->desc->bmAttributes == UE_ISOCHRONOUS))) {
+		DWC_WARN("%s, bad ep\n", __func__);
+		return -DWC_E_INVALID;
+	}
+
+	DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
+	if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
+		DWC_WARN("%d %s XFer In process\n", ep->dwc_ep.num,
+			 ep->dwc_ep.is_in ? "IN" : "OUT");
+		retval = -DWC_E_AGAIN;
+	} else {
+                /* This code needs to be reviewed */
+		if (ep->dwc_ep.is_in == 1 && GET_CORE_IF(pcd)->dma_desc_enable) {
+			dtxfsts_data_t txstatus;
+			fifosize_data_t txfifosize;
+
+			txfifosize.d32 =
+			    dwc_read_reg32(&GET_CORE_IF(pcd)->core_global_regs->
+					   dptxfsiz_dieptxf[ep->dwc_ep.
+							    tx_fifo_num]);
+			txstatus.d32 =
+			    dwc_read_reg32(&GET_CORE_IF(pcd)->dev_if->
+					   in_ep_regs[ep->dwc_ep.num]->dtxfsts);
+
+			if (txstatus.b.txfspcavail < txfifosize.b.depth) {
+				DWC_WARN("%s() Data In Tx Fifo\n", __func__);
+				retval = -DWC_E_AGAIN;
+			} else {
+				if (ep->dwc_ep.num == 0) {
+					pcd->ep0state = EP0_STALL;
+				}
+
+				ep->stopped = 1;
+				dwc_otg_ep_set_stall(GET_CORE_IF(pcd),
+						     &ep->dwc_ep);
+			}
+		} else {
+			if (ep->dwc_ep.num == 0) {
+				pcd->ep0state = EP0_STALL;
+			}
+
+			ep->stopped = 1;
+			dwc_otg_ep_set_stall(GET_CORE_IF(pcd), &ep->dwc_ep);
+		}
+	}
+
+	DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
+
+	return retval;
+}
+   
+int dwc_otg_pcd_ep_halt(dwc_otg_pcd_t * pcd, void *ep_handle, int value)
+{
+	dwc_otg_pcd_ep_t *ep;
+	uint64_t flags;
+	int retval = 0;
+
+	ep = get_ep_from_handle(pcd, ep_handle);
+
+	if ((!ep->desc && ep != &pcd->ep0) ||
+	    (ep->desc && (ep->desc->bmAttributes == UE_ISOCHRONOUS))) {
+		DWC_WARN("%s, bad ep\n", __func__);
+		return -DWC_E_INVALID;
+	}
+
+	DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
+	if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
+		DWC_WARN("%d %s XFer In process\n", ep->dwc_ep.num,
+			 ep->dwc_ep.is_in ? "IN" : "OUT");
+		retval = -DWC_E_AGAIN;
+	} else if (value == 0) {
+		dwc_otg_ep_clear_stall(GET_CORE_IF(pcd), &ep->dwc_ep);
+	} else if (value == 1) {
+		if (ep->dwc_ep.is_in == 1 && GET_CORE_IF(pcd)->dma_desc_enable) {
+			dtxfsts_data_t txstatus;
+			fifosize_data_t txfifosize;
+
+			txfifosize.d32 =
+			    dwc_read_reg32(&GET_CORE_IF(pcd)->core_global_regs->
+					   dptxfsiz_dieptxf[ep->dwc_ep.
+							    tx_fifo_num]);
+			txstatus.d32 =
+			    dwc_read_reg32(&GET_CORE_IF(pcd)->dev_if->
+					   in_ep_regs[ep->dwc_ep.num]->dtxfsts);
+
+			if (txstatus.b.txfspcavail < txfifosize.b.depth) {
+				DWC_WARN("%s() Data In Tx Fifo\n", __func__);
+				retval = -DWC_E_AGAIN;
+			} else {
+				if (ep->dwc_ep.num == 0) {
+					pcd->ep0state = EP0_STALL;
+				}
+
+				ep->stopped = 1;
+				dwc_otg_ep_set_stall(GET_CORE_IF(pcd),
+						     &ep->dwc_ep);
+			}
+		} else {
+			if (ep->dwc_ep.num == 0) {
+				pcd->ep0state = EP0_STALL;
+			}
+
+			ep->stopped = 1;
+			dwc_otg_ep_set_stall(GET_CORE_IF(pcd), &ep->dwc_ep);
+		}
+	} else if (value == 2) {
+		ep->dwc_ep.stall_clear_flag = 0;
+	} else if (value == 3) {
+		ep->dwc_ep.stall_clear_flag = 1;
+	}
+
+	DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
+
+	return retval;
+}
+
+/**
+ * This function initiates remote wakeup of the host from suspend state.
+ */
+void dwc_otg_pcd_rem_wkup_from_suspend(dwc_otg_pcd_t * pcd, int set)
+{
+	dctl_data_t dctl = { 0 };
+	dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+	dsts_data_t dsts;
+
+	dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
+	if (!dsts.b.suspsts) {
+		DWC_WARN("Remote wakeup while is not in suspend state\n");
+	}
+	/* Check if DEVICE_REMOTE_WAKEUP feature enabled */
+	if (pcd->remote_wakeup_enable) {
+		if (set) {
+			dctl.b.rmtwkupsig = 1;
+			dwc_modify_reg32(&core_if->dev_if->dev_global_regs->
+					 dctl, 0, dctl.d32);
+			DWC_DEBUGPL(DBG_PCD, "Set Remote Wakeup\n");
+			dwc_mdelay(2);
+			dwc_modify_reg32(&core_if->dev_if->dev_global_regs->
+					 dctl, dctl.d32, 0);
+			DWC_DEBUGPL(DBG_PCD, "Clear Remote Wakeup\n");
+		}
+	} else {
+		DWC_DEBUGPL(DBG_PCD, "Remote Wakeup is disabled\n");
+	}
+}
+
+#ifdef CONFIG_USB_DWC_OTG_LPM
+/**
+ * This function initiates remote wakeup of the host from L1 sleep state.
+ */
+void dwc_otg_pcd_rem_wkup_from_sleep(dwc_otg_pcd_t * pcd, int set)
+{
+	glpmcfg_data_t lpmcfg;
+	dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+
+	lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg);
+
+	/* Check if we are in L1 state */
+	if (!lpmcfg.b.prt_sleep_sts) {
+		DWC_DEBUGPL(DBG_PCD, "Device is not in sleep state\n");
+		return;
+	}
+
+	/* Check if host allows remote wakeup */
+	if (!lpmcfg.b.rem_wkup_en) {
+		DWC_DEBUGPL(DBG_PCD, "Host does not allow remote wakeup\n");
+		return;
+	}
+
+	/* Check if Resume OK */
+	if (!lpmcfg.b.sleep_state_resumeok) {
+		DWC_DEBUGPL(DBG_PCD, "Sleep state resume is not OK\n");
+		return;
+	}
+
+	lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg);
+	lpmcfg.b.en_utmi_sleep = 0;
+	lpmcfg.b.hird_thres &= (~(1 << 4));
+	dwc_write_reg32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
+
+	if (set) {
+		dctl_data_t dctl = {.d32 = 0 };
+		dctl.b.rmtwkupsig = 1;
+		/* Set RmtWkUpSig bit to start remote wakup signaling.
+		 * Hardware will automatically clear this bit.
+		 */
+		dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dctl,
+				 0, dctl.d32);
+		DWC_DEBUGPL(DBG_PCD, "Set Remote Wakeup\n");
+	}
+
+}
+#endif
+
+/**
+ * Performs remote wakeup.
+ */
+void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t * pcd, int set)
+{
+	dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+	if (dwc_otg_is_device_mode(core_if)) {
+#ifdef CONFIG_USB_DWC_OTG_LPM
+		if (core_if->lx_state == DWC_OTG_L1) {
+			dwc_otg_pcd_rem_wkup_from_sleep(pcd, set);
+		} else {
+#endif
+			dwc_otg_pcd_rem_wkup_from_suspend(pcd, set);
+#ifdef CONFIG_USB_DWC_OTG_LPM
+		}
+#endif
+	}
+	return;
+}
+
+int dwc_otg_pcd_wakeup(dwc_otg_pcd_t * pcd)
+{
+	dsts_data_t dsts;
+	gotgctl_data_t gotgctl;
+	uint64_t flags;
+
+	DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
+
+	/*
+	 * This function starts the Protocol if no session is in progress. If
+	 * a session is already in progress, but the device is suspended,
+	 * remote wakeup signaling is started.
+	 */
+
+	/* Check if valid session */
+	gotgctl.d32 =
+	    dwc_read_reg32(&(GET_CORE_IF(pcd)->core_global_regs->gotgctl));
+	if (gotgctl.b.bsesvld) {
+		/* Check if suspend state */
+		dsts.d32 =
+		    dwc_read_reg32(&
+				   (GET_CORE_IF(pcd)->dev_if->dev_global_regs->
+				    dsts));
+		if (dsts.b.suspsts) {
+			dwc_otg_pcd_remote_wakeup(pcd, 1);
+		}
+	} else {
+		dwc_otg_pcd_initiate_srp(pcd);
+	}
+
+	DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
+	return 0;
+
+}
+
+/**
+ * Start the SRP timer to detect when the SRP does not complete within
+ * 6 seconds.
+ *
+ * @param pcd the pcd structure.
+ */
+void dwc_otg_pcd_start_srp_timer(dwc_otg_pcd_t * pcd)
+{
+	GET_CORE_IF(pcd)->srp_timer_started = 1;
+	DWC_TIMER_SCHEDULE(pcd->srp_timer, 6000 /* 6 secs */ );
+}
+
+void dwc_otg_pcd_initiate_srp(dwc_otg_pcd_t * pcd)
+{
+	uint32_t *addr =
+	    (uint32_t *) & (GET_CORE_IF(pcd)->core_global_regs->gotgctl);
+	gotgctl_data_t mem;
+	gotgctl_data_t val;
+
+	val.d32 = dwc_read_reg32(addr);
+	if (val.b.sesreq) {
+		DWC_ERROR("Session Request Already active!\n");
+		return;
+	}
+
+	DWC_INFO("Session Request Initated\n");	//NOTICE
+	mem.d32 = dwc_read_reg32(addr);
+	mem.b.sesreq = 1;
+	dwc_write_reg32(addr, mem.d32);
+
+	/* Start the SRP timer */
+	dwc_otg_pcd_start_srp_timer(pcd);
+	return;
+}
+
+int dwc_otg_pcd_get_frame_number(dwc_otg_pcd_t * pcd)
+{
+	return dwc_otg_get_frame_number(GET_CORE_IF(pcd));
+}
+
+int dwc_otg_pcd_is_lpm_enabled(dwc_otg_pcd_t * pcd)
+{
+	return GET_CORE_IF(pcd)->core_params->lpm_enable;
+}
+
+uint32_t get_b_hnp_enable(dwc_otg_pcd_t * pcd)
+{
+	return pcd->b_hnp_enable;
+}
+
+uint32_t get_a_hnp_support(dwc_otg_pcd_t * pcd)
+{
+	return pcd->a_hnp_support;
+}
+
+uint32_t get_a_alt_hnp_support(dwc_otg_pcd_t * pcd)
+{
+	return pcd->a_alt_hnp_support;
+}
+
+int dwc_otg_pcd_get_rmwkup_enable(dwc_otg_pcd_t * pcd)
+{
+	return pcd->remote_wakeup_enable;
+}
+
+#endif				/* DWC_HOST_ONLY */
diff --git a/drivers/usb/host/dwc_otg/dwc_otg_pcd.h b/drivers/usb/host/dwc_otg/dwc_otg_pcd.h
new file mode 100644
index 000000000000..d38e16941ac5
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/dwc_otg_pcd.h
@@ -0,0 +1,216 @@
+/* ==========================================================================
+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.h $
+ * $Revision: #39 $
+ * $Date: 2008/12/16 $
+ * $Change: 1153731 $
+ *
+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+ * otherwise expressly agreed to in writing between Synopsys and you.
+ *
+ * The Software IS NOT an item of Licensed Software or Licensed Product under
+ * any End User Software License Agreement or Agreement for Licensed Product
+ * with Synopsys or any supplement thereto. You are permitted to use and
+ * redistribute this Software in source and binary forms, with or without
+ * modification, provided that redistributions of source code must retain this
+ * notice. You may not view, use, disclose, copy or distribute this file or
+ * any information contained herein except pursuant to this license grant from
+ * Synopsys. If you do not agree with this notice, including the disclaimer
+ * below, then you are not authorized to use the Software.
+ *
+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ * ========================================================================== */
+#ifndef DWC_HOST_ONLY
+#if !defined(__DWC_PCD_H__)
+#define __DWC_PCD_H__
+
+#include "usb.h"
+#include "dwc_otg_cil.h"
+#include "dwc_otg_pcd_if.h"
+struct cfiobject;
+
+/**
+ * @file
+ *
+ * This file contains the structures, constants, and interfaces for
+ * the Perpherial Contoller Driver (PCD).
+ *
+ * The Peripheral Controller Driver (PCD) for Linux will implement the
+ * Gadget API, so that the existing Gadget drivers can be used.	 For
+ * the Mass Storage Function driver the File-backed USB Storage Gadget
+ * (FBS) driver will be used.  The FBS driver supports the
+ * Control-Bulk (CB), Control-Bulk-Interrupt (CBI), and Bulk-Only
+ * transports.
+ *
+ */
+
+/** Max Transfer size for any EP */
+#define DDMA_MAX_TRANSFER_SIZE 65535
+
+/** Max DMA Descriptor count for any EP */
+#define MAX_DMA_DESC_CNT 64
+
+/**
+ * Get the pointer to the core_if from the pcd pointer.
+ */
+#define GET_CORE_IF( _pcd ) (_pcd->core_if)
+
+/**
+ * States of EP0.
+ */
+typedef enum ep0_state {
+	EP0_DISCONNECT,		/* no host */
+	EP0_IDLE,
+	EP0_IN_DATA_PHASE,
+	EP0_OUT_DATA_PHASE,
+	EP0_IN_STATUS_PHASE,
+	EP0_OUT_STATUS_PHASE,
+	EP0_STALL,
+} ep0state_e;
+
+/** Fordward declaration.*/
+struct dwc_otg_pcd;
+
+/** DWC_otg iso request structure.
+ *
+ */
+typedef struct usb_iso_request dwc_otg_pcd_iso_request_t;
+
+/** DWC_otg request structure.
+ * This structure is a list of requests.
+ */
+typedef struct dwc_otg_pcd_request {
+	void *priv;
+	void *buf;
+	dwc_dma_t dma;
+	uint32_t length;
+	uint32_t actual;
+	unsigned sent_zlp:1;
+
+	 DWC_CIRCLEQ_ENTRY(dwc_otg_pcd_request) queue_entry;
+} dwc_otg_pcd_request_t;
+
+DWC_CIRCLEQ_HEAD(req_list, dwc_otg_pcd_request);
+
+/**	  PCD EP structure.
+ * This structure describes an EP, there is an array of EPs in the PCD
+ * structure.
+ */
+typedef struct dwc_otg_pcd_ep {
+	/** USB EP Descriptor */
+	const usb_endpoint_descriptor_t *desc;
+
+	/** queue of dwc_otg_pcd_requests. */
+	struct req_list queue;
+	unsigned stopped:1;
+	unsigned disabling:1;
+	unsigned dma:1;
+	unsigned queue_sof:1;
+
+#ifdef DWC_EN_ISOC
+	/** ISOC req handle passed */
+	void *iso_req_handle;
+#endif				//_EN_ISOC_
+
+	/** DWC_otg ep data. */
+	dwc_ep_t dwc_ep;
+
+	/** Pointer to PCD */
+	struct dwc_otg_pcd *pcd;
+
+	void *priv;
+} dwc_otg_pcd_ep_t;
+
+/** DWC_otg PCD Structure.
+ * This structure encapsulates the data for the dwc_otg PCD.
+ */
+struct dwc_otg_pcd {
+	const struct dwc_otg_pcd_function_ops *fops;
+	/** Core Interface */
+	dwc_otg_core_if_t *core_if;
+	/** State of EP0 */
+	ep0state_e ep0state;
+	/** EP0 Request is pending */
+	unsigned ep0_pending:1;
+	/** Indicates when SET CONFIGURATION Request is in process */
+	unsigned request_config:1;
+	/** The state of the Remote Wakeup Enable. */
+	unsigned remote_wakeup_enable:1;
+	/** The state of the B-Device HNP Enable. */
+	unsigned b_hnp_enable:1;
+	/** The state of A-Device HNP Support. */
+	unsigned a_hnp_support:1;
+	/** The state of the A-Device Alt HNP support. */
+	unsigned a_alt_hnp_support:1;
+	/** Count of pending Requests */
+	unsigned request_pending;
+
+	/** SETUP packet for EP0
+	 * This structure is allocated as a DMA buffer on PCD initialization
+	 * with enough space for up to 3 setup packets.
+	 */
+	union {
+		usb_device_request_t req;
+		uint32_t d32[2];
+	} *setup_pkt;
+
+	dwc_dma_t setup_pkt_dma_handle;
+
+	/** 2-byte dma buffer used to return status from GET_STATUS */
+	uint16_t *status_buf;
+	dwc_dma_t status_buf_dma_handle;
+
+	/** EP0 */
+	dwc_otg_pcd_ep_t ep0;
+
+	/** Array of IN EPs. */
+	dwc_otg_pcd_ep_t in_ep[MAX_EPS_CHANNELS - 1];
+	/** Array of OUT EPs. */
+	dwc_otg_pcd_ep_t out_ep[MAX_EPS_CHANNELS - 1];
+	/** number of valid EPs in the above array. */
+//        unsigned      num_eps : 4;
+	dwc_spinlock_t *lock;
+	/** Timer for SRP. If it expires before SRP is successful
+	 * clear the SRP. */
+	dwc_timer_t *srp_timer;
+
+	/** Tasklet to defer starting of TEST mode transmissions until
+	 *	Status Phase has been completed.
+	 */
+	dwc_tasklet_t *test_mode_tasklet;
+
+	/** Tasklet to delay starting of xfer in DMA mode */
+	dwc_tasklet_t *start_xfer_tasklet;
+
+	/** The test mode to enter when the tasklet is executed. */
+	unsigned test_mode;
+	/** The cfi_api structure that implements most of the CFI API
+	 * and OTG specific core configuration functionality 
+	 */
+#ifdef DWC_UTE_CFI
+	struct cfiobject *cfi;
+#endif
+
+};
+
+//FIXME this functions should be static, and this prototypes should be removed
+extern void dwc_otg_request_nuke(dwc_otg_pcd_ep_t * ep);
+extern void dwc_otg_request_done(dwc_otg_pcd_ep_t * ep,
+				 dwc_otg_pcd_request_t * req, int32_t status);
+
+void dwc_otg_iso_buffer_done(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep,
+			     void *req_handle);
+
+extern void do_test_mode(void *data);
+#endif
+#endif				/* DWC_HOST_ONLY */
diff --git a/drivers/usb/host/dwc_otg/dwc_otg_pcd_if.h b/drivers/usb/host/dwc_otg/dwc_otg_pcd_if.h
new file mode 100644
index 000000000000..66e9db78ccc4
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/dwc_otg_pcd_if.h
@@ -0,0 +1,333 @@
+/* ==========================================================================
+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_if.h $
+ * $Revision: #6 $
+ * $Date: 2009/04/03 $
+ * $Change: 1225059 $
+ *
+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+ * otherwise expressly agreed to in writing between Synopsys and you.
+ *
+ * The Software IS NOT an item of Licensed Software or Licensed Product under
+ * any End User Software License Agreement or Agreement for Licensed Product
+ * with Synopsys or any supplement thereto. You are permitted to use and
+ * redistribute this Software in source and binary forms, with or without
+ * modification, provided that redistributions of source code must retain this
+ * notice. You may not view, use, disclose, copy or distribute this file or
+ * any information contained herein except pursuant to this license grant from
+ * Synopsys. If you do not agree with this notice, including the disclaimer
+ * below, then you are not authorized to use the Software.
+ *
+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ * ========================================================================== */
+#ifndef DWC_HOST_ONLY
+
+#if !defined(__DWC_PCD_IF_H__)
+#define __DWC_PCD_IF_H__
+
+#include "dwc_os.h"
+#include "dwc_otg_core_if.h"
+
+/** @file 
+ * This file defines DWC_OTG PCD Core API.
+ */
+
+struct dwc_otg_pcd;
+typedef struct dwc_otg_pcd dwc_otg_pcd_t;
+
+/** Maxpacket size for EP0 */
+#define MAX_EP0_SIZE	64
+/** Maxpacket size for any EP */
+#define MAX_PACKET_SIZE 1024
+
+/** @name Function Driver Callbacks */
+/** @{ */
+
+/** This function will be called whenever a previously queued request has
+ * completed.  The status value will be set to -DWC_E_SHUTDOWN to indicated a
+ * failed or aborted transfer, or -DWC_E_RESTART to indicate the device was reset,
+ * or -DWC_E_TIMEOUT to indicate it timed out, or -DWC_E_INVALID to indicate invalid
+ * parameters. */
+typedef int (*dwc_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle,
+				    void *req_handle, int32_t status,
+				    uint32_t actual);
+/**
+ * This function will be called whenever a previousle queued ISOC request has
+ * completed. Count of ISOC packets could be read using dwc_otg_pcd_get_iso_packet_count
+ * function.
+ * The status of each ISOC packet could be read using dwc_otg_pcd_get_iso_packet_*
+ * functions.
+ */
+typedef int (*dwc_isoc_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle,
+					 void *req_handle, int proc_buf_num);
+/** This function should handle any SETUP request that cannot be handled by the
+ * PCD Core.  This includes most GET_DESCRIPTORs, SET_CONFIGS, Any
+ * class-specific requests, etc.  The function must non-blocking.
+ *
+ * Returns 0 on success.
+ * Returns -DWC_E_NOT_SUPPORTED if the request is not supported.
+ * Returns -DWC_E_INVALID if the setup request had invalid parameters or bytes.
+ * Returns -DWC_E_SHUTDOWN on any other error. */
+typedef int (*dwc_setup_cb_t) (dwc_otg_pcd_t * pcd, uint8_t * bytes);
+/** This is called whenever the device has been disconnected.  The function
+ * driver should take appropriate action to clean up all pending requests in the
+ * PCD Core, remove all endpoints (except ep0), and initialize back to reset
+ * state. */
+typedef int (*dwc_disconnect_cb_t) (dwc_otg_pcd_t * pcd);
+/** This function is called when device has been connected. */
+typedef int (*dwc_connect_cb_t) (dwc_otg_pcd_t * pcd, int speed);
+/** This function is called when device has been suspended */
+typedef int (*dwc_suspend_cb_t) (dwc_otg_pcd_t * pcd);
+/** This function is called when device has received LPM tokens, i.e.
+ * device has been sent to sleep state. */
+typedef int (*dwc_sleep_cb_t) (dwc_otg_pcd_t * pcd);
+/** This function is called when device has been resumed
+ * from suspend(L2) or L1 sleep state. */
+typedef int (*dwc_resume_cb_t) (dwc_otg_pcd_t * pcd);
+/** This function is called whenever hnp params has been changed.
+ * User can call get_b_hnp_enable, get_a_hnp_support, get_a_alt_hnp_support functions
+ * to get hnp parameters. */
+typedef int (*dwc_hnp_params_changed_cb_t) (dwc_otg_pcd_t * pcd);
+/** This function is called whenever USB RESET is detected. */
+typedef int (*dwc_reset_cb_t) (dwc_otg_pcd_t * pcd);
+
+typedef int (*cfi_setup_cb_t) (dwc_otg_pcd_t * pcd, void *ctrl_req_bytes);
+
+/** Function Driver Ops Data Structure */
+struct dwc_otg_pcd_function_ops {
+	dwc_connect_cb_t connect;
+	dwc_disconnect_cb_t disconnect;
+	dwc_setup_cb_t setup;
+	dwc_completion_cb_t complete;
+	dwc_isoc_completion_cb_t isoc_complete;
+	dwc_suspend_cb_t suspend;
+	dwc_sleep_cb_t sleep;
+	dwc_resume_cb_t resume;
+	dwc_reset_cb_t reset;
+	dwc_hnp_params_changed_cb_t hnp_changed;
+	cfi_setup_cb_t cfi_setup;
+};
+/** @} */
+
+/** @name Function Driver Functions */
+/** @{ */
+
+/** Call this function to get pointer on dwc_otg_pcd_t,
+ * this pointer will be used for all PCD API functions.
+ *
+ * @param core_if The DWC_OTG Core
+ */
+extern dwc_otg_pcd_t *dwc_otg_pcd_init(dwc_otg_core_if_t * core_if);
+
+/** Frees PCD allocated by dwc_otg_pcd_init
+ *
+ * @param pcd The PCD
+ */
+extern void dwc_otg_pcd_remove(dwc_otg_pcd_t * pcd);
+
+/** Call this to bind the function driver to the PCD Core.
+ *
+ * @param pcd Pointer on dwc_otg_pcd_t returned by dwc_otg_pcd_init function.
+ * @param fops The Function Driver Ops data structure containing pointers to all callbacks.
+ */
+extern void dwc_otg_pcd_start(dwc_otg_pcd_t * pcd,
+			      const struct dwc_otg_pcd_function_ops *fops);
+
+/** Enables an endpoint for use.  This function enables an endpoint in
+ * the PCD.  The endpoint is described by the ep_desc which has the
+ * same format as a USB ep descriptor.  The ep_handle parameter is used to refer
+ * to the endpoint from other API functions and in callbacks.  Normally this
+ * should be called after a SET_CONFIGURATION/SET_INTERFACE to configure the
+ * core for that interface.
+ *
+ * Returns -DWC_E_INVALID if invalid parameters were passed.
+ * Returns -DWC_E_SHUTDOWN if any other error ocurred.
+ * Returns 0 on success.
+ *
+ * @param pcd The PCD
+ * @param ep_desc Endpoint descriptor
+ * @param ep_handle Handle on endpoint, that will be used to identify endpoint.
+ */
+extern int dwc_otg_pcd_ep_enable(dwc_otg_pcd_t * pcd,
+				 const uint8_t * ep_desc, void *ep_handle);
+
+/** Disable the endpoint referenced by ep_handle.
+ *
+ * Returns -DWC_E_INVALID if invalid parameters were passed.
+ * Returns -DWC_E_SHUTDOWN if any other error ocurred.
+ * Returns 0 on success. */
+extern int dwc_otg_pcd_ep_disable(dwc_otg_pcd_t * pcd, void *ep_handle);
+
+/** Queue a data transfer request on the endpoint referenced by ep_handle.
+ * After the transfer is completes, the complete callback will be called with
+ * the request status.
+ *
+ * @param pcd The PCD
+ * @param ep_handle The handle of the endpoint
+ * @param buf The buffer for the data
+ * @param dma_buf The DMA buffer for the data
+ * @param buflen The length of the data transfer
+ * @param zero Specifies whether to send zero length last packet.
+ * @param req_handle Set this handle to any value to use to reference this
+ * request in the ep_dequeue function or from the complete callback
+ * @param atomic_alloc If driver need to perform atomic allocations
+ * for internal data structures.
+ *
+ * Returns -DWC_E_INVALID if invalid parameters were passed.
+ * Returns -DWC_E_SHUTDOWN if any other error ocurred.
+ * Returns 0 on success. */
+extern int dwc_otg_pcd_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,
+				uint8_t * buf, dwc_dma_t dma_buf,
+				uint32_t buflen, int zero, void *req_handle,
+				int atomic_alloc);
+
+/** De-queue the specified data transfer that has not yet completed.
+ *
+ * Returns -DWC_E_INVALID if invalid parameters were passed.
+ * Returns -DWC_E_SHUTDOWN if any other error ocurred.
+ * Returns 0 on success. */
+extern int dwc_otg_pcd_ep_dequeue(dwc_otg_pcd_t * pcd, void *ep_handle,
+				  void *req_handle);
+
+/** Halt (STALL) an endpoint or clear it.
+ *
+ * Returns -DWC_E_INVALID if invalid parameters were passed.
+ * Returns -DWC_E_SHUTDOWN if any other error ocurred.
+ * Returns -DWC_E_AGAIN if the STALL cannot be sent and must be tried again later
+ * Returns 0 on success. */
+extern int dwc_otg_pcd_ep_halt(dwc_otg_pcd_t * pcd, void *ep_handle, int value);
+
+/** This function */
+extern int dwc_otg_pcd_ep_wedge(dwc_otg_pcd_t * pcd, void *ep_handle);
+
+/** This function should be called on every hardware interrupt */
+extern int32_t dwc_otg_pcd_handle_intr(dwc_otg_pcd_t * pcd);
+
+/** This function returns current frame number */
+extern int dwc_otg_pcd_get_frame_number(dwc_otg_pcd_t * pcd);
+
+/**
+ * Start isochronous transfers on the endpoint referenced by ep_handle.
+ * For isochronous transfers duble buffering is used.
+ * After processing each of buffers comlete callback will be called with
+ * status for each transaction.
+ *
+ * @param pcd The PCD
+ * @param ep_handle The handle of the endpoint
+ * @param buf0 The virtual address of first data buffer
+ * @param buf1 The virtual address of second data buffer
+ * @param dma0 The DMA address of first data buffer
+ * @param dma1 The DMA address of second data buffer
+ * @param sync_frame Data pattern frame number
+ * @param dp_frame Data size for pattern frame
+ * @param data_per_frame Data size for regular frame
+ * @param start_frame Frame number to start transfers, if -1 then start transfers ASAP.
+ * @param buf_proc_intrvl Interval of ISOC Buffer processing
+ * @param req_handle Handle of ISOC request
+ * @param atomic_alloc Specefies whether to perform atomic allocation for
+ * 			internal data structures.
+ *
+ * Returns -DWC_E_NO_MEMORY if there is no enough memory.
+ * Returns -DWC_E_INVALID if incorrect arguments are passed to the function.
+ * Returns -DW_E_SHUTDOWN for any other error.
+ * Returns 0 on success
+ */
+extern int dwc_otg_pcd_iso_ep_start(dwc_otg_pcd_t * pcd, void *ep_handle,
+				    uint8_t * buf0, uint8_t * buf1,
+				    dwc_dma_t dma0, dwc_dma_t dma1,
+				    int sync_frame, int dp_frame,
+				    int data_per_frame, int start_frame,
+				    int buf_proc_intrvl, void *req_handle,
+				    int atomic_alloc);
+
+/** Stop ISOC transfers on endpoint referenced by ep_handle.
+ *
+ * @param pcd The PCD
+ * @param ep_handle The handle of the endpoint
+ * @param req_handle Handle of ISOC request
+ *
+ * Returns -DWC_E_INVALID if incorrect arguments are passed to the function
+ * Returns 0 on success
+ */
+int dwc_otg_pcd_iso_ep_stop(dwc_otg_pcd_t * pcd, void *ep_handle,
+			    void *req_handle);
+
+/** Get ISOC packet status.
+ *
+ * @param pcd The PCD
+ * @param ep_handle The handle of the endpoint
+ * @param iso_req_handle Isochronoush request handle
+ * @param packet Number of packet
+ * @param status Out parameter for returning status
+ * @param actual Out parameter for returning actual length
+ * @param offset Out parameter for returning offset
+ *
+ */
+extern void dwc_otg_pcd_get_iso_packet_params(dwc_otg_pcd_t * pcd,
+					      void *ep_handle,
+					      void *iso_req_handle, int packet,
+					      int *status, int *actual,
+					      int *offset);
+
+/** Get ISOC packet count.
+ *
+ * @param pcd The PCD
+ * @param ep_handle The handle of the endpoint
+ * @param iso_req_handle
+ */
+extern int dwc_otg_pcd_get_iso_packet_count(dwc_otg_pcd_t * pcd,
+					    void *ep_handle,
+					    void *iso_req_handle);
+
+/** This function starts the SRP Protocol if no session is in progress. If
+ * a session is already in progress, but the device is suspended,
+ * remote wakeup signaling is started.
+ */
+extern int dwc_otg_pcd_wakeup(dwc_otg_pcd_t * pcd);
+
+/** This function returns 1 if LPM support is enabled, and 0 otherwise. */
+extern int dwc_otg_pcd_is_lpm_enabled(dwc_otg_pcd_t * pcd);
+
+/** This function returns 1 if remote wakeup is allowed and 0, otherwise. */
+extern int dwc_otg_pcd_get_rmwkup_enable(dwc_otg_pcd_t * pcd);
+
+/** Initiate SRP */
+extern void dwc_otg_pcd_initiate_srp(dwc_otg_pcd_t * pcd);
+
+/** Starts remote wakeup signaling. */
+extern void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t * pcd, int set);
+
+/** This function returns whether device is dualspeed.*/
+extern uint32_t dwc_otg_pcd_is_dualspeed(dwc_otg_pcd_t * pcd);
+
+/** This function returns whether device is otg. */
+extern uint32_t dwc_otg_pcd_is_otg(dwc_otg_pcd_t * pcd);
+
+/** These functions allow to get hnp parameters */
+extern uint32_t get_b_hnp_enable(dwc_otg_pcd_t * pcd);
+extern uint32_t get_a_hnp_support(dwc_otg_pcd_t * pcd);
+extern uint32_t get_a_alt_hnp_support(dwc_otg_pcd_t * pcd);
+
+/** CFI specific Interface functions */
+/** Allocate a cfi buffer */
+extern uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep,
+				     dwc_dma_t * addr, size_t buflen,
+				     int flags);
+
+/******************************************************************************/
+
+/** @} */
+
+#endif				/* __DWC_PCD_IF_H__ */
+
+#endif				/* DWC_HOST_ONLY */
diff --git a/drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c b/drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c
new file mode 100644
index 000000000000..f89e878eedbf
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c
@@ -0,0 +1,4077 @@
+/* ==========================================================================
+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_intr.c $
+ * $Revision: #93 $
+ * $Date: 2009/04/02 $
+ * $Change: 1224216 $
+ *
+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+ * otherwise expressly agreed to in writing between Synopsys and you.
+ *
+ * The Software IS NOT an item of Licensed Software or Licensed Product under
+ * any End User Software License Agreement or Agreement for Licensed Product
+ * with Synopsys or any supplement thereto. You are permitted to use and
+ * redistribute this Software in source and binary forms, with or without
+ * modification, provided that redistributions of source code must retain this
+ * notice. You may not view, use, disclose, copy or distribute this file or
+ * any information contained herein except pursuant to this license grant from
+ * Synopsys. If you do not agree with this notice, including the disclaimer
+ * below, then you are not authorized to use the Software.
+ *
+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ * ========================================================================== */
+#ifndef DWC_HOST_ONLY
+
+#include "dwc_otg_pcd.h"
+
+#ifdef DWC_UTE_CFI
+#include "dwc_otg_cfi.h"
+#endif
+
+//#define PRINT_CFI_DMA_DESCS
+
+#define DEBUG_EP0
+
+/**
+ * This function updates OTG.
+ */
+static void dwc_otg_pcd_update_otg(dwc_otg_pcd_t * pcd, const unsigned reset)
+{
+
+	if (reset) {
+		pcd->b_hnp_enable = 0;
+		pcd->a_hnp_support = 0;
+		pcd->a_alt_hnp_support = 0;
+	}
+
+	if (pcd->fops->hnp_changed) {
+		pcd->fops->hnp_changed(pcd);
+	}
+}
+
+/** @file
+ * This file contains the implementation of the PCD Interrupt handlers.
+ *
+ * The PCD handles the device interrupts.  Many conditions can cause a
+ * device interrupt. When an interrupt occurs, the device interrupt
+ * service routine determines the cause of the interrupt and
+ * dispatches handling to the appropriate function. These interrupt
+ * handling functions are described below.
+ * All interrupt registers are processed from LSB to MSB.
+ */
+
+/**
+ * This function prints the ep0 state for debug purposes.
+ */
+static inline void print_ep0_state(dwc_otg_pcd_t * pcd)
+{
+#ifdef DEBUG
+	char str[40];
+
+	switch (pcd->ep0state) {
+	case EP0_DISCONNECT:
+		dwc_strcpy(str, "EP0_DISCONNECT");
+		break;
+	case EP0_IDLE:
+		dwc_strcpy(str, "EP0_IDLE");
+		break;
+	case EP0_IN_DATA_PHASE:
+		dwc_strcpy(str, "EP0_IN_DATA_PHASE");
+		break;
+	case EP0_OUT_DATA_PHASE:
+		dwc_strcpy(str, "EP0_OUT_DATA_PHASE");
+		break;
+	case EP0_IN_STATUS_PHASE:
+		dwc_strcpy(str, "EP0_IN_STATUS_PHASE");
+		break;
+	case EP0_OUT_STATUS_PHASE:
+		dwc_strcpy(str, "EP0_OUT_STATUS_PHASE");
+		break;
+	case EP0_STALL:
+		dwc_strcpy(str, "EP0_STALL");
+		break;
+	default:
+		dwc_strcpy(str, "EP0_INVALID");
+	}
+
+	DWC_DEBUGPL(DBG_ANY, "%s(%d)\n", str, pcd->ep0state);
+#endif
+}
+
+#ifdef DWC_UTE_CFI
+static inline void print_desc(struct dwc_otg_dma_desc *ddesc,
+			      const uint8_t * epname, int descnum)
+{
+	CFI_INFO
+	    ("%s DMA_DESC(%d) buf=0x%08x bytes=0x%04x; sp=0x%x; l=0x%x; sts=0x%02x; bs=0x%02x\n",
+	     epname, descnum, ddesc->buf, ddesc->status.b.bytes,
+	     ddesc->status.b.sp, ddesc->status.b.l, ddesc->status.b.sts,
+	     ddesc->status.b.bs);
+}
+#endif
+
+/**
+ * This function returns pointer to in ep struct with number ep_num
+ */
+static inline dwc_otg_pcd_ep_t *get_in_ep(dwc_otg_pcd_t * pcd, uint32_t ep_num)
+{
+	int i;
+	int num_in_eps = GET_CORE_IF(pcd)->dev_if->num_in_eps;
+	if (ep_num == 0) {
+		return &pcd->ep0;
+	} else {
+		for (i = 0; i < num_in_eps; ++i) {
+			if (pcd->in_ep[i].dwc_ep.num == ep_num)
+				return &pcd->in_ep[i];
+		}
+		return 0;
+	}
+}
+
+/**
+ * This function returns pointer to out ep struct with number ep_num
+ */
+static inline dwc_otg_pcd_ep_t *get_out_ep(dwc_otg_pcd_t * pcd, uint32_t ep_num)
+{
+	int i;
+	int num_out_eps = GET_CORE_IF(pcd)->dev_if->num_out_eps;
+	if (ep_num == 0) {
+		return &pcd->ep0;
+	} else {
+		for (i = 0; i < num_out_eps; ++i) {
+			if (pcd->out_ep[i].dwc_ep.num == ep_num)
+				return &pcd->out_ep[i];
+		}
+		return 0;
+	}
+}
+
+/**
+ * This functions gets a pointer to an EP from the wIndex address
+ * value of the control request.
+ */
+dwc_otg_pcd_ep_t *get_ep_by_addr(dwc_otg_pcd_t * pcd, u16 wIndex)
+{
+	dwc_otg_pcd_ep_t *ep;
+	uint32_t ep_num = UE_GET_ADDR(wIndex);
+
+	if (ep_num == 0) {
+		ep = &pcd->ep0;
+	} else if (UE_GET_DIR(wIndex) == UE_DIR_IN) {	/* in ep */
+		ep = &pcd->in_ep[ep_num - 1];
+	} else {
+		ep = &pcd->out_ep[ep_num - 1];
+	}
+
+	return ep;
+}
+
+/**
+ * This function checks the EP request queue, if the queue is not
+ * empty the next request is started.
+ */
+void start_next_request(dwc_otg_pcd_ep_t * ep)
+{
+	dwc_otg_pcd_request_t *req = 0;
+	uint32_t max_transfer =
+	    GET_CORE_IF(ep->pcd)->core_params->max_transfer_size;
+
+#ifdef DWC_UTE_CFI
+	struct dwc_otg_pcd *pcd;
+	pcd = ep->pcd;
+#endif
+
+	if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
+		req = DWC_CIRCLEQ_FIRST(&ep->queue);
+
+#ifdef DWC_UTE_CFI
+		if (ep->dwc_ep.buff_mode != BM_STANDARD) {
+			ep->dwc_ep.cfi_req_len = req->length;
+			pcd->cfi->ops.build_descriptors(pcd->cfi, pcd, ep, req);
+		} else {
+#endif
+		/* Setup and start the Transfer */
+		ep->dwc_ep.dma_addr = req->dma;
+		ep->dwc_ep.start_xfer_buff = req->buf;
+		ep->dwc_ep.xfer_buff = req->buf;
+		ep->dwc_ep.sent_zlp = 0;
+		ep->dwc_ep.total_len = req->length;
+		ep->dwc_ep.xfer_len = 0;
+		ep->dwc_ep.xfer_count = 0;
+
+		ep->dwc_ep.maxxfer = max_transfer;
+		if (GET_CORE_IF(ep->pcd)->dma_desc_enable) {
+			uint32_t out_max_xfer = DDMA_MAX_TRANSFER_SIZE
+			    - (DDMA_MAX_TRANSFER_SIZE % 4);
+			if (ep->dwc_ep.is_in) {
+					if (ep->dwc_ep.maxxfer >
+					    DDMA_MAX_TRANSFER_SIZE) {
+					ep->dwc_ep.maxxfer =
+					    DDMA_MAX_TRANSFER_SIZE;
+				}
+			} else {
+				if (ep->dwc_ep.maxxfer > out_max_xfer) {
+						ep->dwc_ep.maxxfer =
+						    out_max_xfer;
+				}
+			}
+		}
+		if (ep->dwc_ep.maxxfer < ep->dwc_ep.total_len) {
+			ep->dwc_ep.maxxfer -=
+			    (ep->dwc_ep.maxxfer % ep->dwc_ep.maxpacket);
+		}
+		if (req->sent_zlp) {
+				if ((ep->dwc_ep.total_len %
+				     ep->dwc_ep.maxpacket == 0)
+				    && (ep->dwc_ep.total_len != 0)) {
+				ep->dwc_ep.sent_zlp = 1;
+			}
+
+		}
+#ifdef DWC_UTE_CFI
+		}
+#endif
+		dwc_otg_ep_start_transfer(GET_CORE_IF(ep->pcd), &ep->dwc_ep);
+	}
+}
+
+/**
+ * This function handles the SOF Interrupts. At this time the SOF
+ * Interrupt is disabled.
+ */
+int32_t dwc_otg_pcd_handle_sof_intr(dwc_otg_pcd_t * pcd)
+{
+	dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+
+	gintsts_data_t gintsts;
+
+	DWC_DEBUGPL(DBG_PCD, "SOF\n");
+
+	/* Clear interrupt */
+	gintsts.d32 = 0;
+	gintsts.b.sofintr = 1;
+	dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32);
+
+	return 1;
+}
+
+/**
+ * This function handles the Rx Status Queue Level Interrupt, which
+ * indicates that there is a least one packet in the Rx FIFO.  The
+ * packets are moved from the FIFO to memory, where they will be
+ * processed when the Endpoint Interrupt Register indicates Transfer
+ * Complete or SETUP Phase Done.
+ *
+ * Repeat the following until the Rx Status Queue is empty:
+ *	 -# Read the Receive Status Pop Register (GRXSTSP) to get Packet
+ *		info
+ *	 -# If Receive FIFO is empty then skip to step Clear the interrupt
+ *		and exit
+ *	 -# If SETUP Packet call dwc_otg_read_setup_packet to copy the
+ *		SETUP data to the buffer
+ *	 -# If OUT Data Packet call dwc_otg_read_packet to copy the data
+ *		to the destination buffer
+ */
+int32_t dwc_otg_pcd_handle_rx_status_q_level_intr(dwc_otg_pcd_t * pcd)
+{
+	dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+	dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
+	gintmsk_data_t gintmask = {.d32 = 0 };
+	device_grxsts_data_t status;
+	dwc_otg_pcd_ep_t *ep;
+	gintsts_data_t gintsts;
+#ifdef DEBUG
+	static char *dpid_str[] = { "D0", "D2", "D1", "MDATA" };
+#endif
+
+	//DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, _pcd);
+	/* Disable the Rx Status Queue Level interrupt */
+	gintmask.b.rxstsqlvl = 1;
+	dwc_modify_reg32(&global_regs->gintmsk, gintmask.d32, 0);
+
+	/* Get the Status from the top of the FIFO */
+	status.d32 = dwc_read_reg32(&global_regs->grxstsp);
+
+	DWC_DEBUGPL(DBG_PCD, "EP:%d BCnt:%d DPID:%s "
+		    "pktsts:%x Frame:%d(0x%0x)\n",
+		    status.b.epnum, status.b.bcnt,
+		    dpid_str[status.b.dpid],
+		    status.b.pktsts, status.b.fn, status.b.fn);
+	/* Get pointer to EP structure */
+	ep = get_out_ep(pcd, status.b.epnum);
+
+	switch (status.b.pktsts) {
+	case DWC_DSTS_GOUT_NAK:
+		DWC_DEBUGPL(DBG_PCDV, "Global OUT NAK\n");
+		break;
+	case DWC_STS_DATA_UPDT:
+		DWC_DEBUGPL(DBG_PCDV, "OUT Data Packet\n");
+		if (status.b.bcnt && ep->dwc_ep.xfer_buff) {
+			/** @todo NGS Check for buffer overflow? */
+			dwc_otg_read_packet(core_if,
+					    ep->dwc_ep.xfer_buff,
+					    status.b.bcnt);
+			ep->dwc_ep.xfer_count += status.b.bcnt;
+			ep->dwc_ep.xfer_buff += status.b.bcnt;
+		}
+		break;
+	case DWC_STS_XFER_COMP:
+		DWC_DEBUGPL(DBG_PCDV, "OUT Complete\n");
+		break;
+	case DWC_DSTS_SETUP_COMP:
+#ifdef DEBUG_EP0
+		DWC_DEBUGPL(DBG_PCDV, "Setup Complete\n");
+#endif
+		break;
+	case DWC_DSTS_SETUP_UPDT:
+		dwc_otg_read_setup_packet(core_if, pcd->setup_pkt->d32);
+#ifdef DEBUG_EP0
+		DWC_DEBUGPL(DBG_PCD,
+			    "SETUP PKT: %02x.%02x v%04x i%04x l%04x\n",
+			    pcd->setup_pkt->req.bmRequestType,
+			    pcd->setup_pkt->req.bRequest,
+			    UGETW(pcd->setup_pkt->req.wValue),
+			    UGETW(pcd->setup_pkt->req.wIndex),
+			    UGETW(pcd->setup_pkt->req.wLength));
+#endif
+		ep->dwc_ep.xfer_count += status.b.bcnt;
+		break;
+	default:
+		DWC_DEBUGPL(DBG_PCDV, "Invalid Packet Status (0x%0x)\n",
+			    status.b.pktsts);
+		break;
+	}
+
+	/* Enable the Rx Status Queue Level interrupt */
+	dwc_modify_reg32(&global_regs->gintmsk, 0, gintmask.d32);
+	/* Clear interrupt */
+	gintsts.d32 = 0;
+	gintsts.b.rxstsqlvl = 1;
+	dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
+
+	//DWC_DEBUGPL(DBG_PCDV, "EXIT: %s\n", __func__);
+	return 1;
+}
+
+/**
+ * This function examines the Device IN Token Learning Queue to
+ * determine the EP number of the last IN token received.  This
+ * implementation is for the Mass Storage device where there are only
+ * 2 IN EPs (Control-IN and BULK-IN).
+ *
+ * The EP numbers for the first six IN Tokens are in DTKNQR1 and there
+ * are 8 EP Numbers in each of the other possible DTKNQ Registers.
+ *
+ * @param core_if Programming view of DWC_otg controller.
+ *
+ */
+static inline int get_ep_of_last_in_token(dwc_otg_core_if_t * core_if)
+{
+	dwc_otg_device_global_regs_t *dev_global_regs =
+	    core_if->dev_if->dev_global_regs;
+	const uint32_t TOKEN_Q_DEPTH = core_if->hwcfg2.b.dev_token_q_depth;
+	/* Number of Token Queue Registers */
+	const int DTKNQ_REG_CNT = (TOKEN_Q_DEPTH + 7) / 8;
+	dtknq1_data_t dtknqr1;
+	uint32_t in_tkn_epnums[4];
+	int ndx = 0;
+	int i = 0;
+	volatile uint32_t *addr = &dev_global_regs->dtknqr1;
+	int epnum = 0;
+
+	//DWC_DEBUGPL(DBG_PCD,"dev_token_q_depth=%d\n",TOKEN_Q_DEPTH);
+
+	/* Read the DTKNQ Registers */
+	for (i = 0; i < DTKNQ_REG_CNT; i++) {
+		in_tkn_epnums[i] = dwc_read_reg32(addr);
+		DWC_DEBUGPL(DBG_PCDV, "DTKNQR%d=0x%08x\n", i + 1,
+			    in_tkn_epnums[i]);
+		if (addr == &dev_global_regs->dvbusdis) {
+			addr = &dev_global_regs->dtknqr3_dthrctl;
+		} else {
+			++addr;
+		}
+
+	}
+
+	/* Copy the DTKNQR1 data to the bit field. */
+	dtknqr1.d32 = in_tkn_epnums[0];
+	/* Get the EP numbers */
+	in_tkn_epnums[0] = dtknqr1.b.epnums0_5;
+	ndx = dtknqr1.b.intknwptr - 1;
+
+	//DWC_DEBUGPL(DBG_PCDV,"ndx=%d\n",ndx);
+	if (ndx == -1) {
+		/** @todo Find a simpler way to calculate the max
+		 * queue position.*/
+		int cnt = TOKEN_Q_DEPTH;
+		if (TOKEN_Q_DEPTH <= 6) {
+			cnt = TOKEN_Q_DEPTH - 1;
+		} else if (TOKEN_Q_DEPTH <= 14) {
+			cnt = TOKEN_Q_DEPTH - 7;
+		} else if (TOKEN_Q_DEPTH <= 22) {
+			cnt = TOKEN_Q_DEPTH - 15;
+		} else {
+			cnt = TOKEN_Q_DEPTH - 23;
+		}
+		epnum = (in_tkn_epnums[DTKNQ_REG_CNT - 1] >> (cnt * 4)) & 0xF;
+	} else {
+		if (ndx <= 5) {
+			epnum = (in_tkn_epnums[0] >> (ndx * 4)) & 0xF;
+		} else if (ndx <= 13) {
+			ndx -= 6;
+			epnum = (in_tkn_epnums[1] >> (ndx * 4)) & 0xF;
+		} else if (ndx <= 21) {
+			ndx -= 14;
+			epnum = (in_tkn_epnums[2] >> (ndx * 4)) & 0xF;
+		} else if (ndx <= 29) {
+			ndx -= 22;
+			epnum = (in_tkn_epnums[3] >> (ndx * 4)) & 0xF;
+		}
+	}
+	//DWC_DEBUGPL(DBG_PCD,"epnum=%d\n",epnum);
+	return epnum;
+}
+
+/**
+ * This interrupt occurs when the non-periodic Tx FIFO is half-empty.
+ * The active request is checked for the next packet to be loaded into
+ * the non-periodic Tx FIFO.
+ */
+int32_t dwc_otg_pcd_handle_np_tx_fifo_empty_intr(dwc_otg_pcd_t * pcd)
+{
+	dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+	dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
+	dwc_otg_dev_in_ep_regs_t *ep_regs;
+	gnptxsts_data_t txstatus = {.d32 = 0 };
+	gintsts_data_t gintsts;
+
+	int epnum = 0;
+	dwc_otg_pcd_ep_t *ep = 0;
+	uint32_t len = 0;
+	int dwords;
+
+	/* Get the epnum from the IN Token Learning Queue. */
+	epnum = get_ep_of_last_in_token(core_if);
+	ep = get_in_ep(pcd, epnum);
+
+	DWC_DEBUGPL(DBG_PCD, "NP TxFifo Empty: %d \n", epnum);
+
+	ep_regs = core_if->dev_if->in_ep_regs[epnum];
+
+	len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
+	if (len > ep->dwc_ep.maxpacket) {
+		len = ep->dwc_ep.maxpacket;
+	}
+	dwords = (len + 3) / 4;
+
+	/* While there is space in the queue and space in the FIFO and
+	 * More data to tranfer, Write packets to the Tx FIFO */
+	txstatus.d32 = dwc_read_reg32(&global_regs->gnptxsts);
+	DWC_DEBUGPL(DBG_PCDV, "b4 GNPTXSTS=0x%08x\n", txstatus.d32);
+
+	while (txstatus.b.nptxqspcavail > 0 &&
+	       txstatus.b.nptxfspcavail > dwords &&
+	       ep->dwc_ep.xfer_count < ep->dwc_ep.xfer_len) {
+		/* Write the FIFO */
+		dwc_otg_ep_write_packet(core_if, &ep->dwc_ep, 0);
+		len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
+
+		if (len > ep->dwc_ep.maxpacket) {
+			len = ep->dwc_ep.maxpacket;
+		}
+
+		dwords = (len + 3) / 4;
+		txstatus.d32 = dwc_read_reg32(&global_regs->gnptxsts);
+		DWC_DEBUGPL(DBG_PCDV, "GNPTXSTS=0x%08x\n", txstatus.d32);
+	}
+
+	DWC_DEBUGPL(DBG_PCDV, "GNPTXSTS=0x%08x\n",
+		    dwc_read_reg32(&global_regs->gnptxsts));
+
+	/* Clear interrupt */
+	gintsts.d32 = 0;
+	gintsts.b.nptxfempty = 1;
+	dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
+
+	return 1;
+}
+
+/**
+ * This function is called when dedicated Tx FIFO Empty interrupt occurs.
+ * The active request is checked for the next packet to be loaded into
+ * apropriate Tx FIFO.
+ */
+static int32_t write_empty_tx_fifo(dwc_otg_pcd_t * pcd, uint32_t epnum)
+{
+	dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+	dwc_otg_dev_if_t *dev_if = core_if->dev_if;
+	dwc_otg_dev_in_ep_regs_t *ep_regs;
+	dtxfsts_data_t txstatus = {.d32 = 0 };
+	dwc_otg_pcd_ep_t *ep = 0;
+	uint32_t len = 0;
+	int dwords;
+
+	ep = get_in_ep(pcd, epnum);
+
+	DWC_DEBUGPL(DBG_PCD, "Dedicated TxFifo Empty: %d \n", epnum);
+
+	ep_regs = core_if->dev_if->in_ep_regs[epnum];
+
+	len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
+
+	if (len > ep->dwc_ep.maxpacket) {
+		len = ep->dwc_ep.maxpacket;
+	}
+
+	dwords = (len + 3) / 4;
+
+	/* While there is space in the queue and space in the FIFO and
+	 * More data to tranfer, Write packets to the Tx FIFO */
+	txstatus.d32 = dwc_read_reg32(&dev_if->in_ep_regs[epnum]->dtxfsts);
+	DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum, txstatus.d32);
+
+	while (txstatus.b.txfspcavail > dwords &&
+	       ep->dwc_ep.xfer_count < ep->dwc_ep.xfer_len &&
+	       ep->dwc_ep.xfer_len != 0) {
+		/* Write the FIFO */
+		dwc_otg_ep_write_packet(core_if, &ep->dwc_ep, 0);
+
+		len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
+		if (len > ep->dwc_ep.maxpacket) {
+			len = ep->dwc_ep.maxpacket;
+		}
+
+		dwords = (len + 3) / 4;
+		txstatus.d32 =
+		    dwc_read_reg32(&dev_if->in_ep_regs[epnum]->dtxfsts);
+		DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", epnum,
+			    txstatus.d32);
+	}
+
+	DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum,
+		    dwc_read_reg32(&dev_if->in_ep_regs[epnum]->dtxfsts));
+
+	return 1;
+}
+
+/**
+ * This function is called when the Device is disconnected. It stops
+ * any active requests and informs the Gadget driver of the
+ * disconnect.
+ */
+void dwc_otg_pcd_stop(dwc_otg_pcd_t * pcd)
+{
+	int i, num_in_eps, num_out_eps;
+	dwc_otg_pcd_ep_t *ep;
+
+	gintmsk_data_t intr_mask = {.d32 = 0 };
+
+	DWC_SPINLOCK(pcd->lock);
+
+	num_in_eps = GET_CORE_IF(pcd)->dev_if->num_in_eps;
+	num_out_eps = GET_CORE_IF(pcd)->dev_if->num_out_eps;
+
+	DWC_DEBUGPL(DBG_PCDV, "%s() \n", __func__);
+	/* don't disconnect drivers more than once */
+	if (pcd->ep0state == EP0_DISCONNECT) {
+		DWC_DEBUGPL(DBG_ANY, "%s() Already Disconnected\n", __func__);
+		return;
+	}
+	pcd->ep0state = EP0_DISCONNECT;
+
+	/* Reset the OTG state. */
+	dwc_otg_pcd_update_otg(pcd, 1);
+
+	/* Disable the NP Tx Fifo Empty Interrupt. */
+	intr_mask.b.nptxfempty = 1;
+	dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
+			 intr_mask.d32, 0);
+
+	/* Flush the FIFOs */
+	/**@todo NGS Flush Periodic FIFOs */
+	dwc_otg_flush_tx_fifo(GET_CORE_IF(pcd), 0x10);
+	dwc_otg_flush_rx_fifo(GET_CORE_IF(pcd));
+
+	/* prevent new request submissions, kill any outstanding requests  */
+	ep = &pcd->ep0;
+	dwc_otg_request_nuke(ep);
+	/* prevent new request submissions, kill any outstanding requests  */
+	for (i = 0; i < num_in_eps; i++) {
+		dwc_otg_pcd_ep_t *ep = &pcd->in_ep[i];
+		dwc_otg_request_nuke(ep);
+	}
+	/* prevent new request submissions, kill any outstanding requests  */
+	for (i = 0; i < num_out_eps; i++) {
+		dwc_otg_pcd_ep_t *ep = &pcd->out_ep[i];
+		dwc_otg_request_nuke(ep);
+	}
+
+	/* report disconnect; the driver is already quiesced */
+	if (pcd->fops->disconnect) {
+		DWC_SPINUNLOCK(pcd->lock);
+		pcd->fops->disconnect(pcd);
+		DWC_SPINLOCK(pcd->lock);
+	}
+	DWC_SPINUNLOCK(pcd->lock);
+}
+
+/**
+ * This interrupt indicates that ...
+ */
+int32_t dwc_otg_pcd_handle_i2c_intr(dwc_otg_pcd_t * pcd)
+{
+	gintmsk_data_t intr_mask = {.d32 = 0 };
+	gintsts_data_t gintsts;
+
+	DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "i2cintr");
+	intr_mask.b.i2cintr = 1;
+	dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
+			 intr_mask.d32, 0);
+
+	/* Clear interrupt */
+	gintsts.d32 = 0;
+	gintsts.b.i2cintr = 1;
+	dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
+			gintsts.d32);
+	return 1;
+}
+
+/**
+ * This interrupt indicates that ...
+ */
+int32_t dwc_otg_pcd_handle_early_suspend_intr(dwc_otg_pcd_t * pcd)
+{
+	gintsts_data_t gintsts;
+#if defined(VERBOSE)
+	DWC_PRINTF("Early Suspend Detected\n");
+#endif
+	/* Clear interrupt */
+	gintsts.d32 = 0;
+	gintsts.b.erlysuspend = 1;
+	dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
+			gintsts.d32);
+	return 1;
+}
+
+/**
+ * This function configures EPO to receive SETUP packets.
+ *
+ * @todo NGS: Update the comments from the HW FS.
+ *
+ *	-# Program the following fields in the endpoint specific registers
+ *	for Control OUT EP 0, in order to receive a setup packet
+ *	- DOEPTSIZ0.Packet Count = 3 (To receive up to 3 back to back
+ *	  setup packets)
+ *	- DOEPTSIZE0.Transfer Size = 24 Bytes (To receive up to 3 back
+ *	  to back setup packets)
+ *		- In DMA mode, DOEPDMA0 Register with a memory address to
+ *		  store any setup packets received
+ *
+ * @param core_if Programming view of DWC_otg controller.
+ * @param pcd	  Programming view of the PCD.
+ */
+static inline void ep0_out_start(dwc_otg_core_if_t * core_if,
+				 dwc_otg_pcd_t * pcd)
+{
+	dwc_otg_dev_if_t *dev_if = core_if->dev_if;
+	deptsiz0_data_t doeptsize0 = {.d32 = 0 };
+	dwc_otg_dev_dma_desc_t *dma_desc;
+	depctl_data_t doepctl = {.d32 = 0 };
+
+#ifdef VERBOSE
+	DWC_DEBUGPL(DBG_PCDV, "%s() doepctl0=%0x\n", __func__,
+		    dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl));
+#endif
+
+	doeptsize0.b.supcnt = 3;
+	doeptsize0.b.pktcnt = 1;
+	doeptsize0.b.xfersize = 8 * 3;
+
+	if (core_if->dma_enable) {
+		if (!core_if->dma_desc_enable) {
+			/** put here as for Hermes mode deptisz register should not be written */
+			dwc_write_reg32(&dev_if->out_ep_regs[0]->doeptsiz,
+					doeptsize0.d32);
+
+			/** @todo dma needs to handle multiple setup packets (up to 3) */
+			dwc_write_reg32(&dev_if->out_ep_regs[0]->doepdma,
+					pcd->setup_pkt_dma_handle);
+		} else {
+			dev_if->setup_desc_index =
+			    (dev_if->setup_desc_index + 1) & 1;
+			dma_desc =
+			    dev_if->setup_desc_addr[dev_if->setup_desc_index];
+
+			/** DMA Descriptor Setup */
+			dma_desc->status.b.bs = BS_HOST_BUSY;
+			dma_desc->status.b.l = 1;
+			dma_desc->status.b.ioc = 1;
+			dma_desc->status.b.bytes = pcd->ep0.dwc_ep.maxpacket;
+			dma_desc->buf = pcd->setup_pkt_dma_handle;
+			dma_desc->status.b.bs = BS_HOST_READY;
+
+			/** DOEPDMA0 Register write */
+			dwc_write_reg32(&dev_if->out_ep_regs[0]->doepdma,
+					dev_if->dma_setup_desc_addr[dev_if->
+								    setup_desc_index]);
+		}
+
+	} else {
+		/** put here as for Hermes mode deptisz register should not be written */
+		dwc_write_reg32(&dev_if->out_ep_regs[0]->doeptsiz,
+				doeptsize0.d32);
+	}
+
+	/** DOEPCTL0 Register write */
+	doepctl.b.epena = 1;
+	doepctl.b.cnak = 1;
+	dwc_write_reg32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32);
+
+#ifdef VERBOSE
+	DWC_DEBUGPL(DBG_PCDV, "doepctl0=%0x\n",
+		    dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl));
+	DWC_DEBUGPL(DBG_PCDV, "diepctl0=%0x\n",
+		    dwc_read_reg32(&dev_if->in_ep_regs[0]->diepctl));
+#endif
+}
+
+/**
+ * This interrupt occurs when a USB Reset is detected.	When the USB
+ * Reset Interrupt occurs the device state is set to DEFAULT and the
+ * EP0 state is set to IDLE.
+ *	-#	Set the NAK bit for all OUT endpoints (DOEPCTLn.SNAK = 1)
+ *	-#	Unmask the following interrupt bits
+ *		- DAINTMSK.INEP0 = 1 (Control 0 IN endpoint)
+ *	- DAINTMSK.OUTEP0 = 1 (Control 0 OUT endpoint)
+ *	- DOEPMSK.SETUP = 1
+ *	- DOEPMSK.XferCompl = 1
+ *	- DIEPMSK.XferCompl = 1
+ *	- DIEPMSK.TimeOut = 1
+ *	-# Program the following fields in the endpoint specific registers
+ *	for Control OUT EP 0, in order to receive a setup packet
+ *	- DOEPTSIZ0.Packet Count = 3 (To receive up to 3 back to back
+ *	  setup packets)
+ *	- DOEPTSIZE0.Transfer Size = 24 Bytes (To receive up to 3 back
+ *	  to back setup packets)
+ *		- In DMA mode, DOEPDMA0 Register with a memory address to
+ *		  store any setup packets received
+ * At this point, all the required initialization, except for enabling
+ * the control 0 OUT endpoint is done, for receiving SETUP packets.
+ */
+int32_t dwc_otg_pcd_handle_usb_reset_intr(dwc_otg_pcd_t * pcd)
+{
+	dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+	dwc_otg_dev_if_t *dev_if = core_if->dev_if;
+	depctl_data_t doepctl = {.d32 = 0 };
+	daint_data_t daintmsk = {.d32 = 0 };
+	doepmsk_data_t doepmsk = {.d32 = 0 };
+	diepmsk_data_t diepmsk = {.d32 = 0 };
+	dcfg_data_t dcfg = {.d32 = 0 };
+	grstctl_t resetctl = {.d32 = 0 };
+	dctl_data_t dctl = {.d32 = 0 };
+	int i = 0;
+	gintsts_data_t gintsts;
+	pcgcctl_data_t power = {.d32 = 0 };
+
+	power.d32 = dwc_read_reg32(core_if->pcgcctl);
+	if (power.b.stoppclk) {
+		power.d32 = 0;
+		power.b.stoppclk = 1;
+		dwc_modify_reg32(core_if->pcgcctl, power.d32, 0);
+
+		power.b.pwrclmp = 1;
+		dwc_modify_reg32(core_if->pcgcctl, power.d32, 0);
+
+		power.b.rstpdwnmodule = 1;
+		dwc_modify_reg32(core_if->pcgcctl, power.d32, 0);
+	}
+
+	core_if->lx_state = DWC_OTG_L0;
+
+	DWC_PRINTF("USB RESET\n");
+#ifdef DWC_EN_ISOC
+	for (i = 1; i < 16; ++i) {
+		dwc_otg_pcd_ep_t *ep;
+		dwc_ep_t *dwc_ep;
+		ep = get_in_ep(pcd, i);
+		if (ep != 0) {
+			dwc_ep = &ep->dwc_ep;
+			dwc_ep->next_frame = 0xffffffff;
+		}
+	}
+#endif				/* DWC_EN_ISOC */
+
+	/* reset the HNP settings */
+	dwc_otg_pcd_update_otg(pcd, 1);
+
+	/* Clear the Remote Wakeup Signalling */
+	dctl.b.rmtwkupsig = 1;
+	dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, 0);
+
+	/* Set NAK for all OUT EPs */
+	doepctl.b.snak = 1;
+	for (i = 0; i <= dev_if->num_out_eps; i++) {
+		dwc_write_reg32(&dev_if->out_ep_regs[i]->doepctl, doepctl.d32);
+	}
+
+	/* Flush the NP Tx FIFO */
+	dwc_otg_flush_tx_fifo(core_if, 0x10);
+	/* Flush the Learning Queue */
+	resetctl.b.intknqflsh = 1;
+	dwc_write_reg32(&core_if->core_global_regs->grstctl, resetctl.d32);
+
+	if (core_if->multiproc_int_enable) {
+		daintmsk.b.inep0 = 1;
+		daintmsk.b.outep0 = 1;
+		dwc_write_reg32(&dev_if->dev_global_regs->deachintmsk,
+				daintmsk.d32);
+
+		doepmsk.b.setup = 1;
+		doepmsk.b.xfercompl = 1;
+		doepmsk.b.ahberr = 1;
+		doepmsk.b.epdisabled = 1;
+
+		if (core_if->dma_desc_enable) {
+			doepmsk.b.stsphsercvd = 1;
+			doepmsk.b.bna = 1;
+		}
+/*		
+		doepmsk.b.babble = 1;
+		doepmsk.b.nyet = 1;
+		
+		if(core_if->dma_enable) {
+			doepmsk.b.nak = 1;
+		}
+*/
+		dwc_write_reg32(&dev_if->dev_global_regs->doepeachintmsk[0],
+				doepmsk.d32);
+
+		diepmsk.b.xfercompl = 1;
+		diepmsk.b.timeout = 1;
+		diepmsk.b.epdisabled = 1;
+		diepmsk.b.ahberr = 1;
+		diepmsk.b.intknepmis = 1;
+
+		if (core_if->dma_desc_enable) {
+			diepmsk.b.bna = 1;
+		}
+/*		
+		if(core_if->dma_enable) {
+			diepmsk.b.nak = 1;
+		}
+*/
+		dwc_write_reg32(&dev_if->dev_global_regs->diepeachintmsk[0],
+				diepmsk.d32);
+	} else {
+		daintmsk.b.inep0 = 1;
+		daintmsk.b.outep0 = 1;
+		dwc_write_reg32(&dev_if->dev_global_regs->daintmsk,
+				daintmsk.d32);
+
+		doepmsk.b.setup = 1;
+		doepmsk.b.xfercompl = 1;
+		doepmsk.b.ahberr = 1;
+		doepmsk.b.epdisabled = 1;
+
+		if (core_if->dma_desc_enable) {
+			doepmsk.b.stsphsercvd = 1;
+			doepmsk.b.bna = 1;
+		}
+		dwc_write_reg32(&dev_if->dev_global_regs->doepmsk, doepmsk.d32);
+
+		diepmsk.b.xfercompl = 1;
+		diepmsk.b.timeout = 1;
+		diepmsk.b.epdisabled = 1;
+		diepmsk.b.ahberr = 1;
+		diepmsk.b.intknepmis = 1;
+
+		if (core_if->dma_desc_enable) {
+			diepmsk.b.bna = 1;
+		}
+
+		dwc_write_reg32(&dev_if->dev_global_regs->diepmsk, diepmsk.d32);
+	}
+
+	/* Reset Device Address */
+	dcfg.d32 = dwc_read_reg32(&dev_if->dev_global_regs->dcfg);
+	dcfg.b.devaddr = 0;
+	dwc_write_reg32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
+
+	/* setup EP0 to receive SETUP packets */
+	ep0_out_start(core_if, pcd);
+
+	/* Clear interrupt */
+	gintsts.d32 = 0;
+	gintsts.b.usbreset = 1;
+	dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32);
+
+	return 1;
+}
+
+/**
+ * Get the device speed from the device status register and convert it
+ * to USB speed constant.
+ *
+ * @param core_if Programming view of DWC_otg controller.
+ */
+static int get_device_speed(dwc_otg_core_if_t * core_if)
+{
+	dsts_data_t dsts;
+	int speed = 0;
+	dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
+
+	switch (dsts.b.enumspd) {
+	case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
+		speed = USB_SPEED_HIGH;
+		break;
+	case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
+	case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ:
+		speed = USB_SPEED_FULL;
+		break;
+
+	case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ:
+		speed = USB_SPEED_LOW;
+		break;
+	}
+
+	return speed;
+}
+
+/**
+ * Read the device status register and set the device speed in the
+ * data structure.
+ * Set up EP0 to receive SETUP packets by calling dwc_ep0_activate.
+ */
+int32_t dwc_otg_pcd_handle_enum_done_intr(dwc_otg_pcd_t * pcd)
+{
+	dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
+	gintsts_data_t gintsts;
+	gusbcfg_data_t gusbcfg;
+	dwc_otg_core_global_regs_t *global_regs =
+	    GET_CORE_IF(pcd)->core_global_regs;
+	uint8_t utmi16b, utmi8b;
+	int speed;
+	DWC_DEBUGPL(DBG_PCD, "SPEED ENUM\n");
+
+	if (GET_CORE_IF(pcd)->snpsid >= OTG_CORE_REV_2_60a) {
+		utmi16b = 6;
+		utmi8b = 9;
+	} else {
+		utmi16b = 4;
+		utmi8b = 8;
+	}
+	dwc_otg_ep0_activate(GET_CORE_IF(pcd), &ep0->dwc_ep);
+
+#ifdef DEBUG_EP0
+	print_ep0_state(pcd);
+#endif
+
+	if (pcd->ep0state == EP0_DISCONNECT) {
+		pcd->ep0state = EP0_IDLE;
+	} else if (pcd->ep0state == EP0_STALL) {
+		pcd->ep0state = EP0_IDLE;
+	}
+
+	pcd->ep0state = EP0_IDLE;
+
+	ep0->stopped = 0;
+
+	speed = get_device_speed(GET_CORE_IF(pcd));
+	pcd->fops->connect(pcd, speed);
+
+	/* Set USB turnaround time based on device speed and PHY interface. */
+	gusbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
+	if (speed == USB_SPEED_HIGH) {
+		if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type ==
+		    DWC_HWCFG2_HS_PHY_TYPE_ULPI) {
+			/* ULPI interface */
+			gusbcfg.b.usbtrdtim = 9;
+		}
+		if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type ==
+		    DWC_HWCFG2_HS_PHY_TYPE_UTMI) {
+			/* UTMI+ interface */
+			if (GET_CORE_IF(pcd)->hwcfg4.b.utmi_phy_data_width == 0) {
+				gusbcfg.b.usbtrdtim = utmi8b;
+			} else if (GET_CORE_IF(pcd)->hwcfg4.b.
+				   utmi_phy_data_width == 1) {
+				gusbcfg.b.usbtrdtim = utmi16b;
+			} else if (GET_CORE_IF(pcd)->core_params->
+				   phy_utmi_width == 8) {
+				gusbcfg.b.usbtrdtim = utmi8b;
+			} else {
+				gusbcfg.b.usbtrdtim = utmi16b;
+			}
+		}
+		if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type ==
+		    DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI) {
+			/* UTMI+  OR  ULPI interface */
+			if (gusbcfg.b.ulpi_utmi_sel == 1) {
+				/* ULPI interface */
+				gusbcfg.b.usbtrdtim = 9;
+			} else {
+				/* UTMI+ interface */
+				if (GET_CORE_IF(pcd)->core_params->
+				    phy_utmi_width == 16) {
+					gusbcfg.b.usbtrdtim = utmi16b;
+				} else {
+					gusbcfg.b.usbtrdtim = utmi8b;
+				}
+			}
+		}
+	} else {
+		/* Full or low speed */
+		gusbcfg.b.usbtrdtim = 9;
+	}
+	dwc_write_reg32(&global_regs->gusbcfg, gusbcfg.d32);
+
+	/* Clear interrupt */
+	gintsts.d32 = 0;
+	gintsts.b.enumdone = 1;
+	dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
+			gintsts.d32);
+	return 1;
+}
+
+/**
+ * This interrupt indicates that the ISO OUT Packet was dropped due to
+ * Rx FIFO full or Rx Status Queue Full.  If this interrupt occurs
+ * read all the data from the Rx FIFO.
+ */
+int32_t dwc_otg_pcd_handle_isoc_out_packet_dropped_intr(dwc_otg_pcd_t * pcd)
+{
+	gintmsk_data_t intr_mask = {.d32 = 0 };
+	gintsts_data_t gintsts;
+
+	DWC_PRINTF("INTERRUPT Handler not implemented for %s\n",
+		   "ISOC Out Dropped");
+
+	intr_mask.b.isooutdrop = 1;
+	dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
+			 intr_mask.d32, 0);
+
+	/* Clear interrupt */
+	gintsts.d32 = 0;
+	gintsts.b.isooutdrop = 1;
+	dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
+			gintsts.d32);
+
+	return 1;
+}
+
+/**
+ * This interrupt indicates the end of the portion of the micro-frame
+ * for periodic transactions.  If there is a periodic transaction for
+ * the next frame, load the packets into the EP periodic Tx FIFO.
+ */
+int32_t dwc_otg_pcd_handle_end_periodic_frame_intr(dwc_otg_pcd_t * pcd)
+{
+	gintmsk_data_t intr_mask = {.d32 = 0 };
+	gintsts_data_t gintsts;
+	DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "EOP");
+
+	intr_mask.b.eopframe = 1;
+	dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
+			 intr_mask.d32, 0);
+
+	/* Clear interrupt */
+	gintsts.d32 = 0;
+	gintsts.b.eopframe = 1;
+	dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
+			gintsts.d32);
+
+	return 1;
+}
+
+/**
+ * This interrupt indicates that EP of the packet on the top of the
+ * non-periodic Tx FIFO does not match EP of the IN Token received.
+ *
+ * The "Device IN Token Queue" Registers are read to determine the
+ * order the IN Tokens have been received.	The non-periodic Tx FIFO
+ * is flushed, so it can be reloaded in the order seen in the IN Token
+ * Queue.
+ */
+int32_t dwc_otg_pcd_handle_ep_mismatch_intr(dwc_otg_core_if_t * core_if)
+{
+	gintsts_data_t gintsts;
+	DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, core_if);
+
+	/* Clear interrupt */
+	gintsts.d32 = 0;
+	gintsts.b.epmismatch = 1;
+	dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32);
+
+	return 1;
+}
+
+/**
+ * This funcion stalls EP0.
+ */
+static inline void ep0_do_stall(dwc_otg_pcd_t * pcd, const int err_val)
+{
+	dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
+	usb_device_request_t *ctrl = &pcd->setup_pkt->req;
+	DWC_WARN("req %02x.%02x protocol STALL; err %d\n",
+		 ctrl->bmRequestType, ctrl->bRequest, err_val);
+
+	ep0->dwc_ep.is_in = 1;
+	dwc_otg_ep_set_stall(GET_CORE_IF(pcd), &ep0->dwc_ep);
+	pcd->ep0.stopped = 1;
+	pcd->ep0state = EP0_IDLE;
+	ep0_out_start(GET_CORE_IF(pcd), pcd);
+}
+
+/**
+ * This functions delegates the setup command to the gadget driver.
+ */
+static inline void do_gadget_setup(dwc_otg_pcd_t * pcd,
+				   usb_device_request_t * ctrl)
+{
+	int ret = 0;
+	DWC_SPINUNLOCK(pcd->lock);
+	ret = pcd->fops->setup(pcd, (uint8_t *) ctrl);
+	DWC_SPINLOCK(pcd->lock);
+	if (ret < 0) {
+		ep0_do_stall(pcd, ret);
+	}
+
+	/** @todo This is a g_file_storage gadget driver specific
+	 * workaround: a DELAYED_STATUS result from the fsg_setup
+	 * routine will result in the gadget queueing a EP0 IN status
+	 * phase for a two-stage control transfer.	Exactly the same as
+	 * a SET_CONFIGURATION/SET_INTERFACE except that this is a class
+	 * specific request.  Need a generic way to know when the gadget
+	 * driver will queue the status phase.	Can we assume when we
+	 * call the gadget driver setup() function that it will always
+	 * queue and require the following flag?  Need to look into
+	 * this.
+	 */
+
+	if (ret == 256 + 999) {
+		pcd->request_config = 1;
+	}
+}
+
+#ifdef DWC_UTE_CFI
+/**
+ * This functions delegates the CFI setup commands to the gadget driver.
+ * This function will return a negative value to indicate a failure.
+ */
+static inline int cfi_gadget_setup(dwc_otg_pcd_t * pcd,
+				   struct cfi_usb_ctrlrequest *ctrl_req)
+{
+	int ret = 0;
+
+	if (pcd->fops && pcd->fops->cfi_setup) {
+		DWC_SPINUNLOCK(pcd->lock);
+		ret = pcd->fops->cfi_setup(pcd, ctrl_req);
+		DWC_SPINLOCK(pcd->lock);
+		if (ret < 0) {
+			ep0_do_stall(pcd, ret);
+			return ret;
+		}
+	}
+
+	return ret;
+}
+#endif
+
+/**
+ * This function starts the Zero-Length Packet for the IN status phase
+ * of a 2 stage control transfer.
+ */
+static inline void do_setup_in_status_phase(dwc_otg_pcd_t * pcd)
+{
+	dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
+	if (pcd->ep0state == EP0_STALL) {
+		return;
+	}
+
+	pcd->ep0state = EP0_IN_STATUS_PHASE;
+
+	/* Prepare for more SETUP Packets */
+	DWC_DEBUGPL(DBG_PCD, "EP0 IN ZLP\n");
+	ep0->dwc_ep.xfer_len = 0;
+	ep0->dwc_ep.xfer_count = 0;
+	ep0->dwc_ep.is_in = 1;
+	ep0->dwc_ep.dma_addr = pcd->setup_pkt_dma_handle;
+	dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
+
+	/* Prepare for more SETUP Packets */
+	//ep0_out_start(GET_CORE_IF(pcd), pcd);
+}
+
+/**
+ * This function starts the Zero-Length Packet for the OUT status phase
+ * of a 2 stage control transfer.
+ */
+static inline void do_setup_out_status_phase(dwc_otg_pcd_t * pcd)
+{
+	dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
+	if (pcd->ep0state == EP0_STALL) {
+		DWC_DEBUGPL(DBG_PCD, "EP0 STALLED\n");
+		return;
+	}
+	pcd->ep0state = EP0_OUT_STATUS_PHASE;
+
+	DWC_DEBUGPL(DBG_PCD, "EP0 OUT ZLP\n");
+	ep0->dwc_ep.xfer_len = 0;
+	ep0->dwc_ep.xfer_count = 0;
+	ep0->dwc_ep.is_in = 0;
+	ep0->dwc_ep.dma_addr = pcd->setup_pkt_dma_handle;
+	dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
+
+	/* Prepare for more SETUP Packets */
+	if (GET_CORE_IF(pcd)->dma_enable == 0) {
+		ep0_out_start(GET_CORE_IF(pcd), pcd);
+	}
+}
+
+/**
+ * Clear the EP halt (STALL) and if pending requests start the
+ * transfer.
+ */
+static inline void pcd_clear_halt(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep)
+{
+	if (ep->dwc_ep.stall_clear_flag == 0)
+		dwc_otg_ep_clear_stall(GET_CORE_IF(pcd), &ep->dwc_ep);
+
+	/* Reactive the EP */
+	dwc_otg_ep_activate(GET_CORE_IF(pcd), &ep->dwc_ep);
+	if (ep->stopped) {
+		ep->stopped = 0;
+		/* If there is a request in the EP queue start it */
+
+		/** @todo FIXME: this causes an EP mismatch in DMA mode.
+		 * epmismatch not yet implemented. */
+
+		/*
+		 * Above fixme is solved by implmenting a tasklet to call the
+		 * start_next_request(), outside of interrupt context at some
+		 * time after the current time, after a clear-halt setup packet.
+		 * Still need to implement ep mismatch in the future if a gadget
+		 * ever uses more than one endpoint at once
+		 */
+		ep->queue_sof = 1;
+		DWC_TASK_SCHEDULE(pcd->start_xfer_tasklet);
+	}
+	/* Start Control Status Phase */
+	do_setup_in_status_phase(pcd);
+}
+
+/**
+ * This function is called when the SET_FEATURE TEST_MODE Setup packet
+ * is sent from the host.  The Device Control register is written with
+ * the Test Mode bits set to the specified Test Mode.  This is done as
+ * a tasklet so that the "Status" phase of the control transfer
+ * completes before transmitting the TEST packets.
+ *
+ * @todo This has not been tested since the tasklet struct was put
+ * into the PCD struct!
+ *
+ */
+void do_test_mode(void *data)
+{
+	dctl_data_t dctl;
+	dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) data;
+	dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+	int test_mode = pcd->test_mode;
+
+//        DWC_WARN("%s() has not been tested since being rewritten!\n", __func__);
+
+	dctl.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dctl);
+	switch (test_mode) {
+	case 1:		// TEST_J
+		dctl.b.tstctl = 1;
+		break;
+
+	case 2:		// TEST_K
+		dctl.b.tstctl = 2;
+		break;
+
+	case 3:		// TEST_SE0_NAK
+		dctl.b.tstctl = 3;
+		break;
+
+	case 4:		// TEST_PACKET
+		dctl.b.tstctl = 4;
+		break;
+
+	case 5:		// TEST_FORCE_ENABLE
+		dctl.b.tstctl = 5;
+		break;
+	}
+	dwc_write_reg32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
+}
+
+/**
+ * This function process the GET_STATUS Setup Commands.
+ */
+static inline void do_get_status(dwc_otg_pcd_t * pcd)
+{
+	usb_device_request_t ctrl = pcd->setup_pkt->req;
+	dwc_otg_pcd_ep_t *ep;
+	dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
+	uint16_t *status = pcd->status_buf;
+
+#ifdef DEBUG_EP0
+	DWC_DEBUGPL(DBG_PCD,
+		    "GET_STATUS %02x.%02x v%04x i%04x l%04x\n",
+		    ctrl.bmRequestType, ctrl.bRequest,
+		    UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
+		    UGETW(ctrl.wLength));
+#endif
+
+	switch (UT_GET_RECIPIENT(ctrl.bmRequestType)) {
+	case UT_DEVICE:
+		*status = 0x1;	/* Self powered */
+		*status |= pcd->remote_wakeup_enable << 1;
+		break;
+
+	case UT_INTERFACE:
+		*status = 0;
+		break;
+
+	case UT_ENDPOINT:
+		ep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex));
+		if (ep == 0 || UGETW(ctrl.wLength) > 2) {
+			ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
+			return;
+		}
+		/** @todo check for EP stall */
+		*status = ep->stopped;
+		break;
+	}
+	pcd->ep0_pending = 1;
+	ep0->dwc_ep.start_xfer_buff = (uint8_t *) status;
+	ep0->dwc_ep.xfer_buff = (uint8_t *) status;
+	ep0->dwc_ep.dma_addr = pcd->status_buf_dma_handle;
+	ep0->dwc_ep.xfer_len = 2;
+	ep0->dwc_ep.xfer_count = 0;
+	ep0->dwc_ep.total_len = ep0->dwc_ep.xfer_len;
+	dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
+}
+
+/**
+ * This function process the SET_FEATURE Setup Commands.
+ */
+static inline void do_set_feature(dwc_otg_pcd_t * pcd)
+{
+	dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+	dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
+	usb_device_request_t ctrl = pcd->setup_pkt->req;
+	dwc_otg_pcd_ep_t *ep = 0;
+	int32_t otg_cap_param = core_if->core_params->otg_cap;
+	gotgctl_data_t gotgctl = {.d32 = 0 };
+
+	DWC_DEBUGPL(DBG_PCD, "SET_FEATURE:%02x.%02x v%04x i%04x l%04x\n",
+		    ctrl.bmRequestType, ctrl.bRequest,
+		    UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
+		    UGETW(ctrl.wLength));
+	DWC_DEBUGPL(DBG_PCD, "otg_cap=%d\n", otg_cap_param);
+
+	switch (UT_GET_RECIPIENT(ctrl.bmRequestType)) {
+	case UT_DEVICE:
+		switch (UGETW(ctrl.wValue)) {
+		case UF_DEVICE_REMOTE_WAKEUP:
+			pcd->remote_wakeup_enable = 1;
+			break;
+
+		case UF_TEST_MODE:
+			/* Setup the Test Mode tasklet to do the Test
+			 * Packet generation after the SETUP Status
+			 * phase has completed. */
+
+			/** @todo This has not been tested since the
+			 * tasklet struct was put into the PCD
+			 * struct! */
+			pcd->test_mode = UGETW(ctrl.wIndex) >> 8;
+			DWC_TASK_SCHEDULE(pcd->test_mode_tasklet);
+			break;
+
+		case UF_DEVICE_B_HNP_ENABLE:
+			DWC_DEBUGPL(DBG_PCDV,
+				    "SET_FEATURE: USB_DEVICE_B_HNP_ENABLE\n");
+
+			/* dev may initiate HNP */
+			if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
+				pcd->b_hnp_enable = 1;
+				dwc_otg_pcd_update_otg(pcd, 0);
+				DWC_DEBUGPL(DBG_PCD, "Request B HNP\n");
+				/**@todo Is the gotgctl.devhnpen cleared
+				 * by a USB Reset? */
+				gotgctl.b.devhnpen = 1;
+				gotgctl.b.hnpreq = 1;
+				dwc_write_reg32(&global_regs->gotgctl,
+						gotgctl.d32);
+			} else {
+				ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
+			}
+			break;
+
+		case UF_DEVICE_A_HNP_SUPPORT:
+			/* RH port supports HNP */
+			DWC_DEBUGPL(DBG_PCDV,
+				    "SET_FEATURE: USB_DEVICE_A_HNP_SUPPORT\n");
+			if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
+				pcd->a_hnp_support = 1;
+				dwc_otg_pcd_update_otg(pcd, 0);
+			} else {
+				ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
+			}
+			break;
+
+		case UF_DEVICE_A_ALT_HNP_SUPPORT:
+			/* other RH port does */
+			DWC_DEBUGPL(DBG_PCDV,
+				    "SET_FEATURE: USB_DEVICE_A_ALT_HNP_SUPPORT\n");
+			if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
+				pcd->a_alt_hnp_support = 1;
+				dwc_otg_pcd_update_otg(pcd, 0);
+			} else {
+				ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
+			}
+			break;
+		}
+		do_setup_in_status_phase(pcd);
+		break;
+
+	case UT_INTERFACE:
+		do_gadget_setup(pcd, &ctrl);
+		break;
+
+	case UT_ENDPOINT:
+		if (UGETW(ctrl.wValue) == UF_ENDPOINT_HALT) {
+			ep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex));
+			if (ep == 0) {
+				ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
+				return;
+			}
+			ep->stopped = 1;
+			dwc_otg_ep_set_stall(core_if, &ep->dwc_ep);
+		}
+		do_setup_in_status_phase(pcd);
+		break;
+	}
+}
+
+/**
+ * This function process the CLEAR_FEATURE Setup Commands.
+ */
+static inline void do_clear_feature(dwc_otg_pcd_t * pcd)
+{
+	usb_device_request_t ctrl = pcd->setup_pkt->req;
+	dwc_otg_pcd_ep_t *ep = 0;
+
+	DWC_DEBUGPL(DBG_PCD,
+		    "CLEAR_FEATURE:%02x.%02x v%04x i%04x l%04x\n",
+		    ctrl.bmRequestType, ctrl.bRequest,
+		    UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
+		    UGETW(ctrl.wLength));
+
+	switch (UT_GET_RECIPIENT(ctrl.bmRequestType)) {
+	case UT_DEVICE:
+		switch (UGETW(ctrl.wValue)) {
+		case UF_DEVICE_REMOTE_WAKEUP:
+			pcd->remote_wakeup_enable = 0;
+			break;
+
+		case UF_TEST_MODE:
+			/** @todo Add CLEAR_FEATURE for TEST modes. */
+			break;
+		}
+		do_setup_in_status_phase(pcd);
+		break;
+
+	case UT_ENDPOINT:
+		ep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex));
+		if (ep == 0) {
+			ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
+			return;
+		}
+
+		pcd_clear_halt(pcd, ep);
+
+		break;
+	}
+}
+
+/**
+ * This function process the SET_ADDRESS Setup Commands.
+ */
+static inline void do_set_address(dwc_otg_pcd_t * pcd)
+{
+	dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
+	usb_device_request_t ctrl = pcd->setup_pkt->req;
+
+	if (ctrl.bmRequestType == UT_DEVICE) {
+		dcfg_data_t dcfg = {.d32 = 0 };
+
+#ifdef DEBUG_EP0
+//                      DWC_DEBUGPL(DBG_PCDV, "SET_ADDRESS:%d\n", ctrl.wValue);
+#endif
+		dcfg.b.devaddr = UGETW(ctrl.wValue);
+		dwc_modify_reg32(&dev_if->dev_global_regs->dcfg, 0, dcfg.d32);
+		do_setup_in_status_phase(pcd);
+	}
+}
+
+/**
+ *	This function processes SETUP commands.	 In Linux, the USB Command
+ *	processing is done in two places - the first being the PCD and the
+ *	second in the Gadget Driver (for example, the File-Backed Storage
+ *	Gadget Driver).
+ *
+ * <table>
+ * <tr><td>Command	</td><td>Driver </td><td>Description</td></tr>
+ *
+ * <tr><td>GET_STATUS </td><td>PCD </td><td>Command is processed as
+ * defined in chapter 9 of the USB 2.0 Specification chapter 9
+ * </td></tr>
+ *
+ * <tr><td>CLEAR_FEATURE </td><td>PCD </td><td>The Device and Endpoint
+ * requests are the ENDPOINT_HALT feature is procesed, all others the
+ * interface requests are ignored.</td></tr>
+ *
+ * <tr><td>SET_FEATURE </td><td>PCD </td><td>The Device and Endpoint
+ * requests are processed by the PCD.  Interface requests are passed
+ * to the Gadget Driver.</td></tr>
+ *
+ * <tr><td>SET_ADDRESS </td><td>PCD </td><td>Program the DCFG reg,
+ * with device address received </td></tr>
+ *
+ * <tr><td>GET_DESCRIPTOR </td><td>Gadget Driver </td><td>Return the
+ * requested descriptor</td></tr>
+ *
+ * <tr><td>SET_DESCRIPTOR </td><td>Gadget Driver </td><td>Optional -
+ * not implemented by any of the existing Gadget Drivers.</td></tr>
+ *
+ * <tr><td>SET_CONFIGURATION </td><td>Gadget Driver </td><td>Disable
+ * all EPs and enable EPs for new configuration.</td></tr>
+ *
+ * <tr><td>GET_CONFIGURATION </td><td>Gadget Driver </td><td>Return
+ * the current configuration</td></tr>
+ *
+ * <tr><td>SET_INTERFACE </td><td>Gadget Driver </td><td>Disable all
+ * EPs and enable EPs for new configuration.</td></tr>
+ *
+ * <tr><td>GET_INTERFACE </td><td>Gadget Driver </td><td>Return the
+ * current interface.</td></tr>
+ *
+ * <tr><td>SYNC_FRAME </td><td>PCD </td><td>Display debug
+ * message.</td></tr>
+ * </table>
+ *
+ * When the SETUP Phase Done interrupt occurs, the PCD SETUP commands are
+ * processed by pcd_setup. Calling the Function Driver's setup function from
+ * pcd_setup processes the gadget SETUP commands.
+ */
+static inline void pcd_setup(dwc_otg_pcd_t * pcd)
+{
+	dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+	dwc_otg_dev_if_t *dev_if = core_if->dev_if;
+	usb_device_request_t ctrl = pcd->setup_pkt->req;
+	dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
+
+	deptsiz0_data_t doeptsize0 = {.d32 = 0 };
+
+#ifdef DWC_UTE_CFI
+	int retval = 0;
+	struct cfi_usb_ctrlrequest cfi_req;
+#endif
+
+#ifdef DEBUG_EP0
+	DWC_DEBUGPL(DBG_PCD, "SETUP %02x.%02x v%04x i%04x l%04x\n",
+		    ctrl.bmRequestType, ctrl.bRequest,
+		    UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
+		    UGETW(ctrl.wLength));
+#endif
+
+	doeptsize0.d32 = dwc_read_reg32(&dev_if->out_ep_regs[0]->doeptsiz);
+
+	/** @todo handle > 1 setup packet , assert error for now */
+
+	if (core_if->dma_enable && core_if->dma_desc_enable == 0
+	    && (doeptsize0.b.supcnt < 2)) {
+		DWC_ERROR
+		    ("\n\n-----------	 CANNOT handle > 1 setup packet in DMA mode\n\n");
+	}
+
+	/* Clean up the request queue */
+	dwc_otg_request_nuke(ep0);
+	ep0->stopped = 0;
+
+	if (ctrl.bmRequestType & UE_DIR_IN) {
+		ep0->dwc_ep.is_in = 1;
+		pcd->ep0state = EP0_IN_DATA_PHASE;
+	} else {
+		ep0->dwc_ep.is_in = 0;
+		pcd->ep0state = EP0_OUT_DATA_PHASE;
+	}
+
+	if (UGETW(ctrl.wLength) == 0) {
+		ep0->dwc_ep.is_in = 1;
+		pcd->ep0state = EP0_IN_STATUS_PHASE;
+	}
+
+	if (UT_GET_TYPE(ctrl.bmRequestType) != UT_STANDARD) {
+
+#ifdef DWC_UTE_CFI
+		DWC_MEMCPY(&cfi_req, &ctrl, sizeof(usb_device_request_t));
+
+		//printk(KERN_ALERT "CFI: req_type=0x%02x; req=0x%02x\n", ctrl.bRequestType, ctrl.bRequest);
+		if (UT_GET_TYPE(cfi_req.bRequestType) == UT_VENDOR) {
+			if (cfi_req.bRequest > 0xB0 && cfi_req.bRequest < 0xBF) {
+				retval = cfi_setup(pcd, &cfi_req);
+				if (retval < 0) {
+					ep0_do_stall(pcd, retval);
+					pcd->ep0_pending = 0;
+					return;
+				}
+
+				/* if need gadget setup then call it and check the retval */
+				if (pcd->cfi->need_gadget_att) {
+					retval =
+					    cfi_gadget_setup(pcd,
+							     &pcd->cfi->
+							     ctrl_req);
+					if (retval < 0) {
+						pcd->ep0_pending = 0;
+						return;
+					}
+				}
+
+				if (pcd->cfi->need_status_in_complete) {
+					do_setup_in_status_phase(pcd);
+				}
+				return;
+			}
+		}
+#endif
+
+		/* handle non-standard (class/vendor) requests in the gadget driver */
+		do_gadget_setup(pcd, &ctrl);
+		return;
+	}
+
+	/** @todo NGS: Handle bad setup packet? */
+
+///////////////////////////////////////////
+//// --- Standard Request handling --- ////
+
+	switch (ctrl.bRequest) {
+	case UR_GET_STATUS:
+		do_get_status(pcd);
+		break;
+
+	case UR_CLEAR_FEATURE:
+		do_clear_feature(pcd);
+		break;
+
+	case UR_SET_FEATURE:
+		do_set_feature(pcd);
+		break;
+
+	case UR_SET_ADDRESS:
+		do_set_address(pcd);
+		break;
+
+	case UR_SET_INTERFACE:
+	case UR_SET_CONFIG:
+//              _pcd->request_config = 1;       /* Configuration changed */
+		do_gadget_setup(pcd, &ctrl);
+		break;
+
+	case UR_SYNCH_FRAME:
+		do_gadget_setup(pcd, &ctrl);
+		break;
+
+	default:
+		/* Call the Gadget Driver's setup functions */
+		do_gadget_setup(pcd, &ctrl);
+		break;
+	}
+}
+
+/**
+ * This function completes the ep0 control transfer.
+ */
+static int32_t ep0_complete_request(dwc_otg_pcd_ep_t * ep)
+{
+	dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
+	dwc_otg_dev_if_t *dev_if = core_if->dev_if;
+	dwc_otg_dev_in_ep_regs_t *in_ep_regs =
+	    dev_if->in_ep_regs[ep->dwc_ep.num];
+#ifdef DEBUG_EP0
+	dwc_otg_dev_out_ep_regs_t *out_ep_regs =
+	    dev_if->out_ep_regs[ep->dwc_ep.num];
+#endif
+	deptsiz0_data_t deptsiz;
+	dev_dma_desc_sts_t desc_sts;
+	dwc_otg_pcd_request_t *req;
+	int is_last = 0;
+	dwc_otg_pcd_t *pcd = ep->pcd;
+
+#ifdef DWC_UTE_CFI
+	struct cfi_usb_ctrlrequest *ctrlreq;
+	int retval = -DWC_E_NOT_SUPPORTED;
+#endif
+
+	if (pcd->ep0_pending && DWC_CIRCLEQ_EMPTY(&ep->queue)) {
+		if (ep->dwc_ep.is_in) {
+#ifdef DEBUG_EP0
+			DWC_DEBUGPL(DBG_PCDV, "Do setup OUT status phase\n");
+#endif
+			do_setup_out_status_phase(pcd);
+		} else {
+#ifdef DEBUG_EP0
+			DWC_DEBUGPL(DBG_PCDV, "Do setup IN status phase\n");
+#endif
+
+#ifdef DWC_UTE_CFI
+			ctrlreq = &pcd->cfi->ctrl_req;
+
+			if (UT_GET_TYPE(ctrlreq->bRequestType) == UT_VENDOR) {
+				if (ctrlreq->bRequest > 0xB0
+				    && ctrlreq->bRequest < 0xBF) {
+
+					/* Return if the PCD failed to handle the request */
+					if ((retval =
+					     pcd->cfi->ops.
+					     ctrl_write_complete(pcd->cfi,
+								 pcd)) < 0) {
+						CFI_INFO
+						    ("ERROR setting a new value in the PCD(%d)\n",
+						     retval);
+						ep0_do_stall(pcd, retval);
+						pcd->ep0_pending = 0;
+						return 0;
+					}
+
+					/* If the gadget needs to be notified on the request */
+					if (pcd->cfi->need_gadget_att == 1) {
+						//retval = do_gadget_setup(pcd, &pcd->cfi->ctrl_req);
+						retval =
+						    cfi_gadget_setup(pcd,
+								     &pcd->cfi->
+								     ctrl_req);
+
+						/* Return from the function if the gadget failed to process
+						 * the request properly - this should never happen !!!
+						 */
+						if (retval < 0) {
+							CFI_INFO
+							    ("ERROR setting a new value in the gadget(%d)\n",
+							     retval);
+							pcd->ep0_pending = 0;
+							return 0;
+						}
+					}
+
+					CFI_INFO("%s: RETVAL=%d\n", __func__,
+						 retval);
+					/* If we hit here then the PCD and the gadget has properly
+					 * handled the request - so send the ZLP IN to the host.
+					 */
+					/* @todo: MAS - decide whether we need to start the setup
+					 * stage based on the need_setup value of the cfi object
+					 */
+					do_setup_in_status_phase(pcd);
+					pcd->ep0_pending = 0;
+					return 1;
+				}
+			}
+#endif
+
+			do_setup_in_status_phase(pcd);
+		}
+		pcd->ep0_pending = 0;
+		return 1;
+	}
+
+	if (DWC_CIRCLEQ_EMPTY(&ep->queue)) {
+		return 0;
+	}
+	req = DWC_CIRCLEQ_FIRST(&ep->queue);
+
+	if (pcd->ep0state == EP0_OUT_STATUS_PHASE
+	    || pcd->ep0state == EP0_IN_STATUS_PHASE) {
+		is_last = 1;
+	} else if (ep->dwc_ep.is_in) {
+		deptsiz.d32 = dwc_read_reg32(&in_ep_regs->dieptsiz);
+		if (core_if->dma_desc_enable != 0)
+			desc_sts = dev_if->in_desc_addr->status;
+#ifdef DEBUG_EP0
+		DWC_DEBUGPL(DBG_PCDV, "%d len=%d  xfersize=%d pktcnt=%d\n",
+			    ep->dwc_ep.num, ep->dwc_ep.xfer_len,
+			    deptsiz.b.xfersize, deptsiz.b.pktcnt);
+#endif
+
+		if (((core_if->dma_desc_enable == 0)
+		     && (deptsiz.b.xfersize == 0))
+		    || ((core_if->dma_desc_enable != 0)
+			&& (desc_sts.b.bytes == 0))) {
+			req->actual = ep->dwc_ep.xfer_count;
+			/* Is a Zero Len Packet needed? */
+			if (req->sent_zlp) {
+#ifdef DEBUG_EP0
+				DWC_DEBUGPL(DBG_PCD, "Setup Rx ZLP\n");
+#endif
+				req->sent_zlp = 0;
+			}
+			do_setup_out_status_phase(pcd);
+		}
+	} else {
+		/* ep0-OUT */
+#ifdef DEBUG_EP0
+		deptsiz.d32 = dwc_read_reg32(&out_ep_regs->doeptsiz);
+		DWC_DEBUGPL(DBG_PCDV, "%d len=%d xsize=%d pktcnt=%d\n",
+			    ep->dwc_ep.num, ep->dwc_ep.xfer_len,
+			    deptsiz.b.xfersize, deptsiz.b.pktcnt);
+#endif
+		req->actual = ep->dwc_ep.xfer_count;
+
+		/* Is a Zero Len Packet needed? */
+		if (req->sent_zlp) {
+#ifdef DEBUG_EP0
+			DWC_DEBUGPL(DBG_PCDV, "Setup Tx ZLP\n");
+#endif
+			req->sent_zlp = 0;
+		}
+		if (core_if->dma_desc_enable == 0)
+			do_setup_in_status_phase(pcd);
+	}
+
+	/* Complete the request */
+	if (is_last) {
+		dwc_otg_request_done(ep, req, 0);
+		ep->dwc_ep.start_xfer_buff = 0;
+		ep->dwc_ep.xfer_buff = 0;
+		ep->dwc_ep.xfer_len = 0;
+		return 1;
+	}
+	return 0;
+}
+
+#ifdef DWC_UTE_CFI
+/**
+ * This function calculates traverses all the CFI DMA descriptors and
+ * and accumulates the bytes that are left to be transfered.
+ *
+ * @return The total bytes left to transfered, or a negative value as failure
+ */
+static inline int cfi_calc_desc_residue(dwc_otg_pcd_ep_t * ep)
+{
+	int32_t ret = 0;
+	int i;
+	struct dwc_otg_dma_desc *ddesc = NULL;
+	struct cfi_ep *cfiep;
+
+	/* See if the pcd_ep has its respective cfi_ep mapped */
+	cfiep = get_cfi_ep_by_pcd_ep(ep->pcd->cfi, ep);
+	if (!cfiep) {
+		CFI_INFO("%s: Failed to find ep\n", __func__);
+		return -1;
+	}
+
+	ddesc = ep->dwc_ep.descs;
+
+	for (i = 0; (i < cfiep->desc_count) && (i < MAX_DMA_DESCS_PER_EP); i++) {
+
+#if defined(PRINT_CFI_DMA_DESCS)
+		print_desc(ddesc, ep->ep.name, i);
+#endif
+		ret += ddesc->status.b.bytes;
+		ddesc++;
+	}
+
+	if (ret)
+		CFI_INFO("!!!!!!!!!! WARNING (%s) - residue=%d\n", __func__,
+			 ret);
+
+	return ret;
+}
+#endif
+
+/**
+ * This function completes the request for the EP.	If there are
+ * additional requests for the EP in the queue they will be started.
+ */
+static void complete_ep(dwc_otg_pcd_ep_t * ep)
+{
+	dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
+	dwc_otg_dev_if_t *dev_if = core_if->dev_if;
+	dwc_otg_dev_in_ep_regs_t *in_ep_regs =
+	    dev_if->in_ep_regs[ep->dwc_ep.num];
+	deptsiz_data_t deptsiz;
+	dev_dma_desc_sts_t desc_sts;
+	dwc_otg_pcd_request_t *req = 0;
+	dwc_otg_dev_dma_desc_t *dma_desc;
+	uint32_t byte_count = 0;
+	int is_last = 0;
+	int i;
+
+	DWC_DEBUGPL(DBG_PCDV, "%s() %d-%s\n", __func__, ep->dwc_ep.num,
+		    (ep->dwc_ep.is_in ? "IN" : "OUT"));
+
+	/* Get any pending requests */
+	if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
+		req = DWC_CIRCLEQ_FIRST(&ep->queue);
+		if (!req) {
+			DWC_PRINTF("complete_ep 0x%p, req = NULL!\n", ep);
+			return;
+		}
+	} else {
+		DWC_PRINTF("complete_ep 0x%p, ep->queue empty!\n", ep);
+		return;
+	}
+
+	DWC_DEBUGPL(DBG_PCD, "Requests %d\n", ep->pcd->request_pending);
+
+	if (ep->dwc_ep.is_in) {
+		deptsiz.d32 = dwc_read_reg32(&in_ep_regs->dieptsiz);
+
+		if (core_if->dma_enable) {
+			if (core_if->dma_desc_enable == 0) {
+				if (deptsiz.b.xfersize == 0
+				    && deptsiz.b.pktcnt == 0) {
+					byte_count =
+					    ep->dwc_ep.xfer_len -
+					    ep->dwc_ep.xfer_count;
+
+					ep->dwc_ep.xfer_buff += byte_count;
+					ep->dwc_ep.dma_addr += byte_count;
+					ep->dwc_ep.xfer_count += byte_count;
+
+					DWC_DEBUGPL(DBG_PCDV,
+						    "%d-%s len=%d  xfersize=%d pktcnt=%d\n",
+						    ep->dwc_ep.num,
+						    (ep->dwc_ep.
+						     is_in ? "IN" : "OUT"),
+						    ep->dwc_ep.xfer_len,
+						    deptsiz.b.xfersize,
+						    deptsiz.b.pktcnt);
+
+					if (ep->dwc_ep.xfer_len <
+					    ep->dwc_ep.total_len) {
+						dwc_otg_ep_start_transfer
+						    (core_if, &ep->dwc_ep);
+					} else if (ep->dwc_ep.sent_zlp) {
+						/*      
+						 * This fragment of code should initiate 0 
+						 * length trasfer in case if it is queued
+						 * a trasfer with size divisible to EPs max 
+						 * packet size and with usb_request zero field 
+						 * is set, which means that after data is transfered, 
+						 * it is also should be transfered 
+						 * a 0 length packet at the end. For Slave and 
+						 * Buffer DMA modes in this case SW has 
+						 * to initiate 2 transfers one with transfer size, 
+						 * and the second with 0 size. For Desriptor 
+						 * DMA mode SW is able to initiate a transfer, 
+						 * which will handle all the packets including 
+						 * the last  0 legth.
+						 */
+						ep->dwc_ep.sent_zlp = 0;
+						dwc_otg_ep_start_zl_transfer
+						    (core_if, &ep->dwc_ep);
+					} else {
+						is_last = 1;
+					}
+				} else {
+					DWC_WARN
+					    ("Incomplete transfer (%d - %s [siz=%d pkt=%d])\n",
+					     ep->dwc_ep.num,
+					     (ep->dwc_ep.is_in ? "IN" : "OUT"),
+					     deptsiz.b.xfersize,
+					     deptsiz.b.pktcnt);
+				}
+			} else {
+				dma_desc = ep->dwc_ep.desc_addr;
+				byte_count = 0;
+				ep->dwc_ep.sent_zlp = 0;
+
+#ifdef DWC_UTE_CFI
+				CFI_INFO("%s: BUFFER_MODE=%d\n", __func__,
+					 ep->dwc_ep.buff_mode);
+				if (ep->dwc_ep.buff_mode != BM_STANDARD) {
+					int residue;
+
+					residue = cfi_calc_desc_residue(ep);
+					if (residue < 0)
+						return;
+
+					byte_count = residue;
+				} else {
+#endif
+					for (i = 0; i < ep->dwc_ep.desc_cnt;
+					     ++i) {
+					desc_sts = dma_desc->status;
+					byte_count += desc_sts.b.bytes;
+					dma_desc++;
+				}
+#ifdef DWC_UTE_CFI
+				}
+#endif
+				if (byte_count == 0) {
+					ep->dwc_ep.xfer_count =
+					    ep->dwc_ep.total_len;
+					is_last = 1;
+				} else {
+					DWC_WARN("Incomplete transfer\n");
+				}
+			}
+		} else {
+			if (deptsiz.b.xfersize == 0 && deptsiz.b.pktcnt == 0) {
+				DWC_DEBUGPL(DBG_PCDV,
+					    "%d-%s len=%d  xfersize=%d pktcnt=%d\n",
+					    ep->dwc_ep.num,
+					    ep->dwc_ep.is_in ? "IN" : "OUT",
+					    ep->dwc_ep.xfer_len,
+					    deptsiz.b.xfersize,
+					    deptsiz.b.pktcnt);
+
+				/*      Check if the whole transfer was completed,  
+				 *      if no, setup transfer for next portion of data
+				 */
+				if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
+					dwc_otg_ep_start_transfer(core_if,
+								  &ep->dwc_ep);
+				} else if (ep->dwc_ep.sent_zlp) {
+					/*      
+					 * This fragment of code should initiate 0 
+					 * length trasfer in case if it is queued
+					 * a trasfer with size divisible to EPs max 
+					 * packet size and with usb_request zero field 
+					 * is set, which means that after data is transfered, 
+					 * it is also should be transfered 
+					 * a 0 length packet at the end. For Slave and 
+					 * Buffer DMA modes in this case SW has 
+					 * to initiate 2 transfers one with transfer size, 
+					 * and the second with 0 size. For Desriptor 
+					 * DMA mode SW is able to initiate a transfer, 
+					 * which will handle all the packets including 
+					 * the last  0 legth.
+					 */
+					ep->dwc_ep.sent_zlp = 0;
+					dwc_otg_ep_start_zl_transfer(core_if,
+								     &ep->
+								     dwc_ep);
+				} else {
+					is_last = 1;
+				}
+			} else {
+				DWC_WARN
+				    ("Incomplete transfer (%d-%s [siz=%d pkt=%d])\n",
+				     ep->dwc_ep.num,
+				     (ep->dwc_ep.is_in ? "IN" : "OUT"),
+				     deptsiz.b.xfersize, deptsiz.b.pktcnt);
+			}
+		}
+	} else {
+		dwc_otg_dev_out_ep_regs_t *out_ep_regs =
+		    dev_if->out_ep_regs[ep->dwc_ep.num];
+		desc_sts.d32 = 0;
+		if (core_if->dma_enable) {
+			if (core_if->dma_desc_enable) {
+				dma_desc = ep->dwc_ep.desc_addr;
+				byte_count = 0;
+				ep->dwc_ep.sent_zlp = 0;
+
+#ifdef DWC_UTE_CFI
+				CFI_INFO("%s: BUFFER_MODE=%d\n", __func__,
+					 ep->dwc_ep.buff_mode);
+				if (ep->dwc_ep.buff_mode != BM_STANDARD) {
+					int residue;
+					residue = cfi_calc_desc_residue(ep);
+					if (residue < 0)
+						return;
+					byte_count = residue;
+				} else {
+#endif
+
+					for (i = 0; i < ep->dwc_ep.desc_cnt;
+					     ++i) {
+					desc_sts = dma_desc->status;
+					byte_count += desc_sts.b.bytes;
+					dma_desc++;
+				}
+
+#ifdef DWC_UTE_CFI
+				}
+#endif
+				ep->dwc_ep.xfer_count = ep->dwc_ep.total_len
+				    - byte_count +
+				    ((4 - (ep->dwc_ep.total_len & 0x3)) & 0x3);
+				is_last = 1;
+			} else {
+				deptsiz.d32 = 0;
+				deptsiz.d32 =
+				    dwc_read_reg32(&out_ep_regs->doeptsiz);
+
+				byte_count = (ep->dwc_ep.xfer_len -
+					      ep->dwc_ep.xfer_count -
+					      deptsiz.b.xfersize);
+				ep->dwc_ep.xfer_buff += byte_count;
+				ep->dwc_ep.dma_addr += byte_count;
+				ep->dwc_ep.xfer_count += byte_count;
+
+				/*      Check if the whole transfer was completed,  
+				 *      if no, setup transfer for next portion of data
+				 */
+				if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
+					dwc_otg_ep_start_transfer(core_if,
+								  &ep->dwc_ep);
+				} else if (ep->dwc_ep.sent_zlp) {
+					/*      
+					 * This fragment of code should initiate 0 
+					 * length trasfer in case if it is queued
+					 * a trasfer with size divisible to EPs max 
+					 * packet size and with usb_request zero field 
+					 * is set, which means that after data is transfered, 
+					 * it is also should be transfered 
+					 * a 0 length packet at the end. For Slave and 
+					 * Buffer DMA modes in this case SW has 
+					 * to initiate 2 transfers one with transfer size, 
+					 * and the second with 0 size. For Desriptor 
+					 * DMA mode SW is able to initiate a transfer, 
+					 * which will handle all the packets including 
+					 * the last  0 legth.
+					 */
+					ep->dwc_ep.sent_zlp = 0;
+					dwc_otg_ep_start_zl_transfer(core_if,
+								     &ep->
+								     dwc_ep);
+				} else {
+					is_last = 1;
+				}
+			}
+		} else {
+			/*      Check if the whole transfer was completed,  
+			 *      if no, setup transfer for next portion of data
+			 */
+			if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
+				dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep);
+			} else if (ep->dwc_ep.sent_zlp) {
+				/*      
+				 * This fragment of code should initiate 0 
+				 * length trasfer in case if it is queued
+				 * a trasfer with size divisible to EPs max 
+				 * packet size and with usb_request zero field 
+				 * is set, which means that after data is transfered, 
+				 * it is also should be transfered 
+				 * a 0 length packet at the end. For Slave and 
+				 * Buffer DMA modes in this case SW has 
+				 * to initiate 2 transfers one with transfer size, 
+				 * and the second with 0 size. For Desriptor 
+				 * DMA mode SW is able to initiate a transfer, 
+				 * which will handle all the packets including 
+				 * the last  0 legth.
+				 */
+				ep->dwc_ep.sent_zlp = 0;
+				dwc_otg_ep_start_zl_transfer(core_if,
+							     &ep->dwc_ep);
+			} else {
+				is_last = 1;
+			}
+		}
+
+		DWC_DEBUGPL(DBG_PCDV,
+			    "addr %p,	 %d-%s len=%d cnt=%d xsize=%d pktcnt=%d\n",
+			    &out_ep_regs->doeptsiz, ep->dwc_ep.num,
+			    ep->dwc_ep.is_in ? "IN" : "OUT",
+			    ep->dwc_ep.xfer_len, ep->dwc_ep.xfer_count,
+			    deptsiz.b.xfersize, deptsiz.b.pktcnt);
+	}
+
+	/* Complete the request */
+	if (is_last) {
+#ifdef DWC_UTE_CFI
+		if (ep->dwc_ep.buff_mode != BM_STANDARD) {
+			req->actual = ep->dwc_ep.cfi_req_len - byte_count;
+		} else {
+#endif
+		req->actual = ep->dwc_ep.xfer_count;
+#ifdef DWC_UTE_CFI
+		}
+#endif
+
+		dwc_otg_request_done(ep, req, 0);
+
+		ep->dwc_ep.start_xfer_buff = 0;
+		ep->dwc_ep.xfer_buff = 0;
+		ep->dwc_ep.xfer_len = 0;
+
+		/* If there is a request in the queue start it. */
+		start_next_request(ep);
+	}
+}
+
+#ifdef DWC_EN_ISOC
+
+/**
+ * This function BNA interrupt for Isochronous EPs
+ *
+ */
+static void dwc_otg_pcd_handle_iso_bna(dwc_otg_pcd_ep_t * ep)
+{
+	dwc_ep_t *dwc_ep = &ep->dwc_ep;
+	volatile uint32_t *addr;
+	depctl_data_t depctl = {.d32 = 0 };
+	dwc_otg_pcd_t *pcd = ep->pcd;
+	dwc_otg_dev_dma_desc_t *dma_desc;
+	int i;
+
+	dma_desc =
+	    dwc_ep->iso_desc_addr + dwc_ep->desc_cnt * (dwc_ep->proc_buf_num);
+
+	if (dwc_ep->is_in) {
+		dev_dma_desc_sts_t sts = {.d32 = 0 };
+		for (i = 0; i < dwc_ep->desc_cnt; ++i, ++dma_desc) {
+			sts.d32 = dma_desc->status.d32;
+			sts.b_iso_in.bs = BS_HOST_READY;
+			dma_desc->status.d32 = sts.d32;
+		}
+	} else {
+		dev_dma_desc_sts_t sts = {.d32 = 0 };
+		for (i = 0; i < dwc_ep->desc_cnt; ++i, ++dma_desc) {
+			sts.d32 = dma_desc->status.d32;
+			sts.b_iso_out.bs = BS_HOST_READY;
+			dma_desc->status.d32 = sts.d32;
+		}
+	}
+
+	if (dwc_ep->is_in == 0) {
+		addr =
+		    &GET_CORE_IF(pcd)->dev_if->out_ep_regs[dwc_ep->num]->
+		    doepctl;
+	} else {
+		addr =
+		    &GET_CORE_IF(pcd)->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
+	}
+	depctl.b.epena = 1;
+	dwc_modify_reg32(addr, depctl.d32, depctl.d32);
+}
+
+/**
+ * This function sets latest iso packet information(non-PTI mode)
+ *
+ * @param core_if Programming view of DWC_otg controller.
+ * @param ep The EP to start the transfer on.
+ *
+ */
+void set_current_pkt_info(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
+{
+	deptsiz_data_t deptsiz = {.d32 = 0 };
+	dma_addr_t dma_addr;
+	uint32_t offset;
+
+	if (ep->proc_buf_num)
+		dma_addr = ep->dma_addr1;
+	else
+		dma_addr = ep->dma_addr0;
+
+	if (ep->is_in) {
+		deptsiz.d32 =
+		    dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]->
+				   dieptsiz);
+		offset = ep->data_per_frame;
+	} else {
+		deptsiz.d32 =
+		    dwc_read_reg32(&core_if->dev_if->out_ep_regs[ep->num]->
+				   doeptsiz);
+		offset =
+		    ep->data_per_frame +
+		    (0x4 & (0x4 - (ep->data_per_frame & 0x3)));
+	}
+
+	if (!deptsiz.b.xfersize) {
+		ep->pkt_info[ep->cur_pkt].length = ep->data_per_frame;
+		ep->pkt_info[ep->cur_pkt].offset =
+		    ep->cur_pkt_dma_addr - dma_addr;
+		ep->pkt_info[ep->cur_pkt].status = 0;
+	} else {
+		ep->pkt_info[ep->cur_pkt].length = ep->data_per_frame;
+		ep->pkt_info[ep->cur_pkt].offset =
+		    ep->cur_pkt_dma_addr - dma_addr;
+		ep->pkt_info[ep->cur_pkt].status = -DWC_E_NO_DATA;
+	}
+	ep->cur_pkt_addr += offset;
+	ep->cur_pkt_dma_addr += offset;
+	ep->cur_pkt++;
+}
+
+/**
+ * This function sets latest iso packet information(DDMA mode)
+ *
+ * @param core_if Programming view of DWC_otg controller.
+ * @param dwc_ep The EP to start the transfer on.
+ *
+ */
+static void set_ddma_iso_pkts_info(dwc_otg_core_if_t * core_if,
+				   dwc_ep_t * dwc_ep)
+{
+	dwc_otg_dev_dma_desc_t *dma_desc;
+	dev_dma_desc_sts_t sts = {.d32 = 0 };
+	iso_pkt_info_t *iso_packet;
+	uint32_t data_per_desc;
+	uint32_t offset;
+	int i, j;
+
+	iso_packet = dwc_ep->pkt_info;
+
+	/** Reinit closed DMA Descriptors*/
+	/** ISO OUT EP */
+	if (dwc_ep->is_in == 0) {
+		dma_desc =
+		    dwc_ep->iso_desc_addr +
+		    dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
+		offset = 0;
+
+		for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
+		     i += dwc_ep->pkt_per_frm) {
+			for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
+				data_per_desc =
+				    ((j + 1) * dwc_ep->maxpacket >
+				     dwc_ep->data_per_frame) ? dwc_ep->
+				    data_per_frame -
+				    j * dwc_ep->maxpacket : dwc_ep->maxpacket;
+				data_per_desc +=
+				    (data_per_desc % 4) ? (4 -
+							   data_per_desc %
+							   4) : 0;
+
+				sts.d32 = dma_desc->status.d32;
+
+				/* Write status in iso_packet_decsriptor  */
+				iso_packet->status =
+				    sts.b_iso_out.rxsts +
+				    (sts.b_iso_out.bs ^ BS_DMA_DONE);
+				if (iso_packet->status) {
+					iso_packet->status = -DWC_E_NO_DATA;
+				}
+
+				/* Received data length */
+				if (!sts.b_iso_out.rxbytes) {
+					iso_packet->length =
+					    data_per_desc -
+					    sts.b_iso_out.rxbytes;
+				} else {
+					iso_packet->length =
+					    data_per_desc -
+					    sts.b_iso_out.rxbytes + (4 -
+								     dwc_ep->
+								     data_per_frame
+								     % 4);
+				}
+
+				iso_packet->offset = offset;
+
+				offset += data_per_desc;
+				dma_desc++;
+				iso_packet++;
+			}
+		}
+
+		for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
+			data_per_desc =
+			    ((j + 1) * dwc_ep->maxpacket >
+			     dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
+			    j * dwc_ep->maxpacket : dwc_ep->maxpacket;
+			data_per_desc +=
+			    (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
+
+			sts.d32 = dma_desc->status.d32;
+
+			/* Write status in iso_packet_decsriptor  */
+			iso_packet->status =
+			    sts.b_iso_out.rxsts +
+			    (sts.b_iso_out.bs ^ BS_DMA_DONE);
+			if (iso_packet->status) {
+				iso_packet->status = -DWC_E_NO_DATA;
+			}
+
+			/* Received data length */
+			iso_packet->length =
+			    dwc_ep->data_per_frame - sts.b_iso_out.rxbytes;
+
+			iso_packet->offset = offset;
+
+			offset += data_per_desc;
+			iso_packet++;
+			dma_desc++;
+		}
+
+		sts.d32 = dma_desc->status.d32;
+
+		/* Write status in iso_packet_decsriptor  */
+		iso_packet->status =
+		    sts.b_iso_out.rxsts + (sts.b_iso_out.bs ^ BS_DMA_DONE);
+		if (iso_packet->status) {
+			iso_packet->status = -DWC_E_NO_DATA;
+		}
+		/* Received data length */
+		if (!sts.b_iso_out.rxbytes) {
+			iso_packet->length =
+			    dwc_ep->data_per_frame - sts.b_iso_out.rxbytes;
+		} else {
+			iso_packet->length =
+			    dwc_ep->data_per_frame - sts.b_iso_out.rxbytes +
+			    (4 - dwc_ep->data_per_frame % 4);
+		}
+
+		iso_packet->offset = offset;
+	} else {
+/** ISO IN EP */
+
+		dma_desc =
+		    dwc_ep->iso_desc_addr +
+		    dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
+
+		for (i = 0; i < dwc_ep->desc_cnt - 1; i++) {
+			sts.d32 = dma_desc->status.d32;
+
+			/* Write status in iso packet descriptor */
+			iso_packet->status =
+			    sts.b_iso_in.txsts +
+			    (sts.b_iso_in.bs ^ BS_DMA_DONE);
+			if (iso_packet->status != 0) {
+				iso_packet->status = -DWC_E_NO_DATA;
+
+			}
+			/* Bytes has been transfered */
+			iso_packet->length =
+			    dwc_ep->data_per_frame - sts.b_iso_in.txbytes;
+
+			dma_desc++;
+			iso_packet++;
+		}
+
+		sts.d32 = dma_desc->status.d32;
+		while (sts.b_iso_in.bs == BS_DMA_BUSY) {
+			sts.d32 = dma_desc->status.d32;
+		}
+
+		/* Write status in iso packet descriptor ??? do be done with ERROR codes */
+		iso_packet->status =
+		    sts.b_iso_in.txsts + (sts.b_iso_in.bs ^ BS_DMA_DONE);
+		if (iso_packet->status != 0) {
+			iso_packet->status = -DWC_E_NO_DATA;
+		}
+
+		/* Bytes has been transfered */
+		iso_packet->length =
+		    dwc_ep->data_per_frame - sts.b_iso_in.txbytes;
+	}
+}
+
+/**
+ * This function reinitialize DMA Descriptors for Isochronous transfer
+ *
+ * @param core_if Programming view of DWC_otg controller.
+ * @param dwc_ep The EP to start the transfer on.
+ *
+ */
+static void reinit_ddma_iso_xfer(dwc_otg_core_if_t * core_if, dwc_ep_t * dwc_ep)
+{
+	int i, j;
+	dwc_otg_dev_dma_desc_t *dma_desc;
+	dma_addr_t dma_ad;
+	volatile uint32_t *addr;
+	dev_dma_desc_sts_t sts = {.d32 = 0 };
+	uint32_t data_per_desc;
+
+	if (dwc_ep->is_in == 0) {
+		addr = &core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl;
+	} else {
+		addr = &core_if->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
+	}
+
+	if (dwc_ep->proc_buf_num == 0) {
+		/** Buffer 0 descriptors setup */
+		dma_ad = dwc_ep->dma_addr0;
+	} else {
+		/** Buffer 1 descriptors setup */
+		dma_ad = dwc_ep->dma_addr1;
+	}
+
+	/** Reinit closed DMA Descriptors*/
+	/** ISO OUT EP */
+	if (dwc_ep->is_in == 0) {
+		dma_desc =
+		    dwc_ep->iso_desc_addr +
+		    dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
+
+		sts.b_iso_out.bs = BS_HOST_READY;
+		sts.b_iso_out.rxsts = 0;
+		sts.b_iso_out.l = 0;
+		sts.b_iso_out.sp = 0;
+		sts.b_iso_out.ioc = 0;
+		sts.b_iso_out.pid = 0;
+		sts.b_iso_out.framenum = 0;
+
+		for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
+		     i += dwc_ep->pkt_per_frm) {
+			for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
+				data_per_desc =
+				    ((j + 1) * dwc_ep->maxpacket >
+				     dwc_ep->data_per_frame) ? dwc_ep->
+				    data_per_frame -
+				    j * dwc_ep->maxpacket : dwc_ep->maxpacket;
+				data_per_desc +=
+				    (data_per_desc % 4) ? (4 -
+							   data_per_desc %
+							   4) : 0;
+				sts.b_iso_out.rxbytes = data_per_desc;
+				dma_desc->buf = dma_ad;
+				dma_desc->status.d32 = sts.d32;
+
+				dma_ad += data_per_desc;
+				dma_desc++;
+			}
+		}
+
+		for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
+
+			data_per_desc =
+			    ((j + 1) * dwc_ep->maxpacket >
+			     dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
+			    j * dwc_ep->maxpacket : dwc_ep->maxpacket;
+			data_per_desc +=
+			    (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
+			sts.b_iso_out.rxbytes = data_per_desc;
+
+			dma_desc->buf = dma_ad;
+			dma_desc->status.d32 = sts.d32;
+
+			dma_desc++;
+			dma_ad += data_per_desc;
+		}
+
+		sts.b_iso_out.ioc = 1;
+		sts.b_iso_out.l = dwc_ep->proc_buf_num;
+
+		data_per_desc =
+		    ((j + 1) * dwc_ep->maxpacket >
+		     dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
+		    j * dwc_ep->maxpacket : dwc_ep->maxpacket;
+		data_per_desc +=
+		    (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
+		sts.b_iso_out.rxbytes = data_per_desc;
+
+		dma_desc->buf = dma_ad;
+		dma_desc->status.d32 = sts.d32;
+	} else {
+/** ISO IN EP */
+
+		dma_desc =
+		    dwc_ep->iso_desc_addr +
+		    dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
+
+		sts.b_iso_in.bs = BS_HOST_READY;
+		sts.b_iso_in.txsts = 0;
+		sts.b_iso_in.sp = 0;
+		sts.b_iso_in.ioc = 0;
+		sts.b_iso_in.pid = dwc_ep->pkt_per_frm;
+		sts.b_iso_in.framenum = dwc_ep->next_frame;
+		sts.b_iso_in.txbytes = dwc_ep->data_per_frame;
+		sts.b_iso_in.l = 0;
+
+		for (i = 0; i < dwc_ep->desc_cnt - 1; i++) {
+			dma_desc->buf = dma_ad;
+			dma_desc->status.d32 = sts.d32;
+
+			sts.b_iso_in.framenum += dwc_ep->bInterval;
+			dma_ad += dwc_ep->data_per_frame;
+			dma_desc++;
+		}
+
+		sts.b_iso_in.ioc = 1;
+		sts.b_iso_in.l = dwc_ep->proc_buf_num;
+
+		dma_desc->buf = dma_ad;
+		dma_desc->status.d32 = sts.d32;
+
+		dwc_ep->next_frame =
+		    sts.b_iso_in.framenum + dwc_ep->bInterval * 1;
+	}
+	dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1;
+}
+
+/**
+ * This function is to handle Iso EP transfer complete interrupt
+ * in case Iso out packet was dropped
+ *
+ * @param core_if Programming view of DWC_otg controller.
+ * @param dwc_ep The EP for wihich transfer complete was asserted
+ *
+ */
+static uint32_t handle_iso_out_pkt_dropped(dwc_otg_core_if_t * core_if,
+					   dwc_ep_t * dwc_ep)
+{
+	uint32_t dma_addr;
+	uint32_t drp_pkt;
+	uint32_t drp_pkt_cnt;
+	deptsiz_data_t deptsiz = {.d32 = 0 };
+	depctl_data_t depctl = {.d32 = 0 };
+	int i;
+
+	deptsiz.d32 =
+	    dwc_read_reg32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->
+			   doeptsiz);
+
+	drp_pkt = dwc_ep->pkt_cnt - deptsiz.b.pktcnt;
+	drp_pkt_cnt = dwc_ep->pkt_per_frm - (drp_pkt % dwc_ep->pkt_per_frm);
+
+	/* Setting dropped packets status */
+	for (i = 0; i < drp_pkt_cnt; ++i) {
+		dwc_ep->pkt_info[drp_pkt].status = -DWC_E_NO_DATA;
+		drp_pkt++;
+		deptsiz.b.pktcnt--;
+	}
+
+	if (deptsiz.b.pktcnt > 0) {
+		deptsiz.b.xfersize =
+		    dwc_ep->xfer_len - (dwc_ep->pkt_cnt -
+					deptsiz.b.pktcnt) * dwc_ep->maxpacket;
+	} else {
+		deptsiz.b.xfersize = 0;
+		deptsiz.b.pktcnt = 0;
+	}
+
+	dwc_write_reg32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doeptsiz,
+			deptsiz.d32);
+
+	if (deptsiz.b.pktcnt > 0) {
+		if (dwc_ep->proc_buf_num) {
+			dma_addr =
+			    dwc_ep->dma_addr1 + dwc_ep->xfer_len -
+			    deptsiz.b.xfersize;
+		} else {
+			dma_addr =
+			    dwc_ep->dma_addr0 + dwc_ep->xfer_len -
+			    deptsiz.b.xfersize;;
+		}
+
+		dwc_write_reg32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->
+				doepdma, dma_addr);
+
+		/** Re-enable endpoint, clear nak  */
+		depctl.d32 = 0;
+		depctl.b.epena = 1;
+		depctl.b.cnak = 1;
+
+		dwc_modify_reg32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->
+				 doepctl, depctl.d32, depctl.d32);
+		return 0;
+	} else {
+		return 1;
+	}
+}
+
+/**
+ * This function sets iso packets information(PTI mode)
+ *
+ * @param core_if Programming view of DWC_otg controller.
+ * @param ep The EP to start the transfer on.
+ *
+ */
+static uint32_t set_iso_pkts_info(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
+{
+	int i, j;
+	dma_addr_t dma_ad;
+	iso_pkt_info_t *packet_info = ep->pkt_info;
+	uint32_t offset;
+	uint32_t frame_data;
+	deptsiz_data_t deptsiz;
+
+	if (ep->proc_buf_num == 0) {
+		/** Buffer 0 descriptors setup */
+		dma_ad = ep->dma_addr0;
+	} else {
+		/** Buffer 1 descriptors setup */
+		dma_ad = ep->dma_addr1;
+	}
+
+	if (ep->is_in) {
+		deptsiz.d32 =
+		    dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]->
+				   dieptsiz);
+	} else {
+		deptsiz.d32 =
+		    dwc_read_reg32(&core_if->dev_if->out_ep_regs[ep->num]->
+				   doeptsiz);
+	}
+
+	if (!deptsiz.b.xfersize) {
+		offset = 0;
+		for (i = 0; i < ep->pkt_cnt; i += ep->pkt_per_frm) {
+			frame_data = ep->data_per_frame;
+			for (j = 0; j < ep->pkt_per_frm; ++j) {
+
+				/* Packet status - is not set as initially 
+				 * it is set to 0 and if packet was sent 
+				 successfully, status field will remain 0*/
+
+				/* Bytes has been transfered */
+				packet_info->length =
+				    (ep->maxpacket <
+				     frame_data) ? ep->maxpacket : frame_data;
+
+				/* Received packet offset */
+				packet_info->offset = offset;
+				offset += packet_info->length;
+				frame_data -= packet_info->length;
+
+				packet_info++;
+			}
+		}
+		return 1;
+	} else {
+		/* This is a workaround for in case of Transfer Complete with 
+		 * PktDrpSts interrupts merging - in this case Transfer complete 
+		 * interrupt for Isoc Out Endpoint is asserted without PktDrpSts 
+		 * set and with DOEPTSIZ register non zero. Investigations showed,
+		 * that this happens when Out packet is dropped, but because of 
+		 * interrupts merging during first interrupt handling PktDrpSts
+		 * bit is cleared and for next merged interrupts it is not reset.
+		 * In this case SW hadles the interrupt as if PktDrpSts bit is set.
+		 */
+		if (ep->is_in) {
+			return 1;
+		} else {
+			return handle_iso_out_pkt_dropped(core_if, ep);
+		}
+	}
+}
+
+/**
+ * This function is to handle Iso EP transfer complete interrupt
+ *
+ * @param pcd The PCD
+ * @param ep The EP for which transfer complete was asserted
+ *
+ */
+static void complete_iso_ep(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep)
+{
+	dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
+	dwc_ep_t *dwc_ep = &ep->dwc_ep;
+	uint8_t is_last = 0;
+
+	if(ep->dwc_ep.next_frame == 0xffffffff) {
+		DWC_WARN("Next frame is not set!\n");
+		return;
+	}
+
+	if (core_if->dma_enable) {
+		if (core_if->dma_desc_enable) {
+			set_ddma_iso_pkts_info(core_if, dwc_ep);
+			reinit_ddma_iso_xfer(core_if, dwc_ep);
+			is_last = 1;
+		} else {
+			if (core_if->pti_enh_enable) {
+				if (set_iso_pkts_info(core_if, dwc_ep)) {
+					dwc_ep->proc_buf_num =
+					    (dwc_ep->proc_buf_num ^ 1) & 0x1;
+					dwc_otg_iso_ep_start_buf_transfer
+					    (core_if, dwc_ep);
+					is_last = 1;
+				}
+			} else {
+				set_current_pkt_info(core_if, dwc_ep);
+				if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
+					is_last = 1;
+					dwc_ep->cur_pkt = 0;
+					dwc_ep->proc_buf_num =
+					    (dwc_ep->proc_buf_num ^ 1) & 0x1;
+					if (dwc_ep->proc_buf_num) {
+						dwc_ep->cur_pkt_addr =
+						    dwc_ep->xfer_buff1;
+						dwc_ep->cur_pkt_dma_addr =
+						    dwc_ep->dma_addr1;
+					} else {
+						dwc_ep->cur_pkt_addr =
+						    dwc_ep->xfer_buff0;
+						dwc_ep->cur_pkt_dma_addr =
+						    dwc_ep->dma_addr0;
+					}
+
+				}
+				dwc_otg_iso_ep_start_frm_transfer(core_if,
+								  dwc_ep);
+			}
+		}
+	} else {
+		set_current_pkt_info(core_if, dwc_ep);
+		if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
+			is_last = 1;
+			dwc_ep->cur_pkt = 0;
+			dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1;
+			if (dwc_ep->proc_buf_num) {
+				dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff1;
+				dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr1;
+			} else {
+				dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff0;
+				dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr0;
+			}
+
+		}
+		dwc_otg_iso_ep_start_frm_transfer(core_if, dwc_ep);
+	}
+	if (is_last)
+		dwc_otg_iso_buffer_done(pcd, ep, ep->iso_req_handle);
+}
+#endif				/* DWC_EN_ISOC */
+
+/**
+ * This function handles EP0 Control transfers.
+ *
+ * The state of the control tranfers are tracked in
+ * <code>ep0state</code>.
+ */
+static void handle_ep0(dwc_otg_pcd_t * pcd)
+{
+	dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+	dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
+	dev_dma_desc_sts_t desc_sts;
+	deptsiz0_data_t deptsiz;
+	uint32_t byte_count;
+
+#ifdef DEBUG_EP0
+	DWC_DEBUGPL(DBG_PCDV, "%s()\n", __func__);
+	print_ep0_state(pcd);
+#endif
+
+//      DWC_PRINTF("HANDLE EP0\n");
+
+	switch (pcd->ep0state) {
+	case EP0_DISCONNECT:
+		break;
+
+	case EP0_IDLE:
+		pcd->request_config = 0;
+
+		pcd_setup(pcd);
+		break;
+
+	case EP0_IN_DATA_PHASE:
+#ifdef DEBUG_EP0
+		DWC_DEBUGPL(DBG_PCD, "DATA_IN EP%d-%s: type=%d, mps=%d\n",
+			    ep0->dwc_ep.num, (ep0->dwc_ep.is_in ? "IN" : "OUT"),
+			    ep0->dwc_ep.type, ep0->dwc_ep.maxpacket);
+#endif
+
+		if (core_if->dma_enable != 0) {
+			/*
+			 * For EP0 we can only program 1 packet at a time so we
+			 * need to do the make calculations after each complete.
+			 * Call write_packet to make the calculations, as in
+			 * slave mode, and use those values to determine if we
+			 * can complete.
+			 */
+			if (core_if->dma_desc_enable == 0) {
+				deptsiz.d32 =
+				    dwc_read_reg32(&core_if->dev_if->
+						   in_ep_regs[0]->dieptsiz);
+				byte_count =
+				    ep0->dwc_ep.xfer_len - deptsiz.b.xfersize;
+			} else {
+				desc_sts =
+				    core_if->dev_if->in_desc_addr->status;
+				byte_count =
+				    ep0->dwc_ep.xfer_len - desc_sts.b.bytes;
+			}
+			ep0->dwc_ep.xfer_count += byte_count;
+			ep0->dwc_ep.xfer_buff += byte_count;
+			ep0->dwc_ep.dma_addr += byte_count;
+		}
+		if (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len) {
+			dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
+						      &ep0->dwc_ep);
+			DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n");
+		} else if (ep0->dwc_ep.sent_zlp) {
+			dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
+						      &ep0->dwc_ep);
+			ep0->dwc_ep.sent_zlp = 0;
+			DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n");
+		} else {
+			ep0_complete_request(ep0);
+			DWC_DEBUGPL(DBG_PCD, "COMPLETE TRANSFER\n");
+		}
+		break;
+	case EP0_OUT_DATA_PHASE:
+#ifdef DEBUG_EP0
+		DWC_DEBUGPL(DBG_PCD, "DATA_OUT EP%d-%s: type=%d, mps=%d\n",
+			    ep0->dwc_ep.num, (ep0->dwc_ep.is_in ? "IN" : "OUT"),
+			    ep0->dwc_ep.type, ep0->dwc_ep.maxpacket);
+#endif
+		if (core_if->dma_enable != 0) {
+			if (core_if->dma_desc_enable == 0) {
+				deptsiz.d32 =
+				    dwc_read_reg32(&core_if->dev_if->
+						   out_ep_regs[0]->doeptsiz);
+				byte_count =
+				    ep0->dwc_ep.maxpacket - deptsiz.b.xfersize;
+			} else {
+				desc_sts =
+				    core_if->dev_if->out_desc_addr->status;
+				byte_count =
+				    ep0->dwc_ep.maxpacket - desc_sts.b.bytes;
+			}
+			ep0->dwc_ep.xfer_count += byte_count;
+			ep0->dwc_ep.xfer_buff += byte_count;
+			ep0->dwc_ep.dma_addr += byte_count;
+		}
+		if (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len) {
+			dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
+						      &ep0->dwc_ep);
+			DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n");
+		} else if (ep0->dwc_ep.sent_zlp) {
+			dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
+						      &ep0->dwc_ep);
+			ep0->dwc_ep.sent_zlp = 0;
+			DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n");
+		} else {
+			ep0_complete_request(ep0);
+			DWC_DEBUGPL(DBG_PCD, "COMPLETE TRANSFER\n");
+		}
+		break;
+
+	case EP0_IN_STATUS_PHASE:
+	case EP0_OUT_STATUS_PHASE:
+		DWC_DEBUGPL(DBG_PCD, "CASE: EP0_STATUS\n");
+		ep0_complete_request(ep0);
+		pcd->ep0state = EP0_IDLE;
+		ep0->stopped = 1;
+		ep0->dwc_ep.is_in = 0;	/* OUT for next SETUP */
+
+		/* Prepare for more SETUP Packets */
+		if (core_if->dma_enable) {
+			ep0_out_start(core_if, pcd);
+		}
+		break;
+
+	case EP0_STALL:
+		DWC_ERROR("EP0 STALLed, should not get here pcd_setup()\n");
+		break;
+	}
+#ifdef DEBUG_EP0
+	print_ep0_state(pcd);
+#endif
+}
+
+/**
+ * Restart transfer
+ */
+static void restart_transfer(dwc_otg_pcd_t * pcd, const uint32_t epnum)
+{
+	dwc_otg_core_if_t *core_if;
+	dwc_otg_dev_if_t *dev_if;
+	deptsiz_data_t dieptsiz = {.d32 = 0 };
+	dwc_otg_pcd_ep_t *ep;
+
+	ep = get_in_ep(pcd, epnum);
+
+#ifdef DWC_EN_ISOC
+	if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
+		return;
+	}
+#endif				/* DWC_EN_ISOC  */
+
+	core_if = GET_CORE_IF(pcd);
+	dev_if = core_if->dev_if;
+
+	dieptsiz.d32 = dwc_read_reg32(&dev_if->in_ep_regs[epnum]->dieptsiz);
+
+	DWC_DEBUGPL(DBG_PCD, "xfer_buff=%p xfer_count=%0x xfer_len=%0x"
+		    " stopped=%d\n", ep->dwc_ep.xfer_buff,
+		    ep->dwc_ep.xfer_count, ep->dwc_ep.xfer_len, ep->stopped);
+	/*
+	 * If xfersize is 0 and pktcnt in not 0, resend the last packet.
+	 */
+	if (dieptsiz.b.pktcnt && dieptsiz.b.xfersize == 0 &&
+	    ep->dwc_ep.start_xfer_buff != 0) {
+		if (ep->dwc_ep.total_len <= ep->dwc_ep.maxpacket) {
+			ep->dwc_ep.xfer_count = 0;
+			ep->dwc_ep.xfer_buff = ep->dwc_ep.start_xfer_buff;
+			ep->dwc_ep.xfer_len = ep->dwc_ep.xfer_count;
+		} else {
+			ep->dwc_ep.xfer_count -= ep->dwc_ep.maxpacket;
+			/* convert packet size to dwords. */
+			ep->dwc_ep.xfer_buff -= ep->dwc_ep.maxpacket;
+			ep->dwc_ep.xfer_len = ep->dwc_ep.xfer_count;
+		}
+		ep->stopped = 0;
+		DWC_DEBUGPL(DBG_PCD, "xfer_buff=%p xfer_count=%0x "
+			    "xfer_len=%0x stopped=%d\n",
+			    ep->dwc_ep.xfer_buff,
+			    ep->dwc_ep.xfer_count, ep->dwc_ep.xfer_len,
+			    ep->stopped);
+		if (epnum == 0) {
+			dwc_otg_ep0_start_transfer(core_if, &ep->dwc_ep);
+		} else {
+			dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep);
+		}
+	}
+}
+
+/**
+ * handle the IN EP disable interrupt.
+ */
+static inline void handle_in_ep_disable_intr(dwc_otg_pcd_t * pcd,
+					     const uint32_t epnum)
+{
+	dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+	dwc_otg_dev_if_t *dev_if = core_if->dev_if;
+	deptsiz_data_t dieptsiz = {.d32 = 0 };
+	dctl_data_t dctl = {.d32 = 0 };
+	dwc_otg_pcd_ep_t *ep;
+	dwc_ep_t *dwc_ep;
+
+	ep = get_in_ep(pcd, epnum);
+	dwc_ep = &ep->dwc_ep;
+
+	if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
+		dwc_otg_flush_tx_fifo(core_if, dwc_ep->tx_fifo_num);
+		return;
+	}
+
+	DWC_DEBUGPL(DBG_PCD, "diepctl%d=%0x\n", epnum,
+		    dwc_read_reg32(&dev_if->in_ep_regs[epnum]->diepctl));
+	dieptsiz.d32 = dwc_read_reg32(&dev_if->in_ep_regs[epnum]->dieptsiz);
+
+	DWC_DEBUGPL(DBG_ANY, "pktcnt=%d size=%d\n",
+		    dieptsiz.b.pktcnt, dieptsiz.b.xfersize);
+
+	if (ep->stopped) {
+		/* Flush the Tx FIFO */
+		dwc_otg_flush_tx_fifo(core_if, dwc_ep->tx_fifo_num);
+		/* Clear the Global IN NP NAK */
+		dctl.d32 = 0;
+		dctl.b.cgnpinnak = 1;
+		dwc_modify_reg32(&dev_if->dev_global_regs->dctl, dctl.d32, 0);
+		/* Restart the transaction */
+		if (dieptsiz.b.pktcnt != 0 || dieptsiz.b.xfersize != 0) {
+			restart_transfer(pcd, epnum);
+		}
+	} else {
+		/* Restart the transaction */
+		if (dieptsiz.b.pktcnt != 0 || dieptsiz.b.xfersize != 0) {
+			restart_transfer(pcd, epnum);
+		}
+		DWC_DEBUGPL(DBG_ANY, "STOPPED!!!\n");
+	}
+}
+
+/**
+ * Handler for the IN EP timeout handshake interrupt.
+ */
+static inline void handle_in_ep_timeout_intr(dwc_otg_pcd_t * pcd,
+					     const uint32_t epnum)
+{
+	dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+	dwc_otg_dev_if_t *dev_if = core_if->dev_if;
+
+#ifdef DEBUG
+	deptsiz_data_t dieptsiz = {.d32 = 0 };
+	uint32_t num = 0;
+#endif
+	dctl_data_t dctl = {.d32 = 0 };
+	dwc_otg_pcd_ep_t *ep;
+
+	gintmsk_data_t intr_mask = {.d32 = 0 };
+
+	ep = get_in_ep(pcd, epnum);
+
+	/* Disable the NP Tx Fifo Empty Interrrupt */
+	if (!core_if->dma_enable) {
+		intr_mask.b.nptxfempty = 1;
+		dwc_modify_reg32(&core_if->core_global_regs->gintmsk,
+				 intr_mask.d32, 0);
+	}
+	/** @todo NGS Check EP type.
+	 * Implement for Periodic EPs */
+	/*
+	 * Non-periodic EP
+	 */
+	/* Enable the Global IN NAK Effective Interrupt */
+	intr_mask.b.ginnakeff = 1;
+	dwc_modify_reg32(&core_if->core_global_regs->gintmsk, 0, intr_mask.d32);
+
+	/* Set Global IN NAK */
+	dctl.b.sgnpinnak = 1;
+	dwc_modify_reg32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
+
+	ep->stopped = 1;
+
+#ifdef DEBUG
+	dieptsiz.d32 = dwc_read_reg32(&dev_if->in_ep_regs[num]->dieptsiz);
+	DWC_DEBUGPL(DBG_ANY, "pktcnt=%d size=%d\n",
+		    dieptsiz.b.pktcnt, dieptsiz.b.xfersize);
+#endif
+
+#ifdef DISABLE_PERIODIC_EP
+	/*
+	 * Set the NAK bit for this EP to
+	 * start the disable process.
+	 */
+	diepctl.d32 = 0;
+	diepctl.b.snak = 1;
+	dwc_modify_reg32(&dev_if->in_ep_regs[num]->diepctl, diepctl.d32,
+			 diepctl.d32);
+	ep->disabling = 1;
+	ep->stopped = 1;
+#endif
+}
+
+/**
+ * Handler for the IN EP NAK interrupt. 
+ */
+static inline int32_t handle_in_ep_nak_intr(dwc_otg_pcd_t * pcd,
+					    const uint32_t epnum)
+{
+	/** @todo implement ISR */
+	dwc_otg_core_if_t *core_if;
+	diepmsk_data_t intr_mask = {.d32 = 0 };
+
+	DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "IN EP NAK");
+	core_if = GET_CORE_IF(pcd);
+	intr_mask.b.nak = 1;
+
+	if (core_if->multiproc_int_enable) {
+		dwc_modify_reg32(&core_if->dev_if->dev_global_regs->
+				 diepeachintmsk[epnum], intr_mask.d32, 0);
+	} else {
+		dwc_modify_reg32(&core_if->dev_if->dev_global_regs->diepmsk,
+				 intr_mask.d32, 0);
+	}
+
+	return 1;
+}
+
+/**
+ * Handler for the OUT EP Babble interrupt. 
+ */
+static inline int32_t handle_out_ep_babble_intr(dwc_otg_pcd_t * pcd,
+						const uint32_t epnum)
+{
+	/** @todo implement ISR */
+	dwc_otg_core_if_t *core_if;
+	doepmsk_data_t intr_mask = {.d32 = 0 };
+
+	DWC_PRINTF("INTERRUPT Handler not implemented for %s\n",
+		   "OUT EP Babble");
+	core_if = GET_CORE_IF(pcd);
+	intr_mask.b.babble = 1;
+
+	if (core_if->multiproc_int_enable) {
+		dwc_modify_reg32(&core_if->dev_if->dev_global_regs->
+				 doepeachintmsk[epnum], intr_mask.d32, 0);
+	} else {
+		dwc_modify_reg32(&core_if->dev_if->dev_global_regs->doepmsk,
+				 intr_mask.d32, 0);
+	}
+
+	return 1;
+}
+
+/**
+ * Handler for the OUT EP NAK interrupt. 
+ */
+static inline int32_t handle_out_ep_nak_intr(dwc_otg_pcd_t * pcd,
+					     const uint32_t epnum)
+{
+	/** @todo implement ISR */
+	dwc_otg_core_if_t *core_if;
+	doepmsk_data_t intr_mask = {.d32 = 0 };
+
+	DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "OUT EP NAK");
+	core_if = GET_CORE_IF(pcd);
+	intr_mask.b.nak = 1;
+
+	if (core_if->multiproc_int_enable) {
+		dwc_modify_reg32(&core_if->dev_if->dev_global_regs->
+				 doepeachintmsk[epnum], intr_mask.d32, 0);
+	} else {
+		dwc_modify_reg32(&core_if->dev_if->dev_global_regs->doepmsk,
+				 intr_mask.d32, 0);
+	}
+
+	return 1;
+}
+
+/**
+ * Handler for the OUT EP NYET interrupt. 
+ */
+static inline int32_t handle_out_ep_nyet_intr(dwc_otg_pcd_t * pcd,
+					      const uint32_t epnum)
+{
+	/** @todo implement ISR */
+	dwc_otg_core_if_t *core_if;
+	doepmsk_data_t intr_mask = {.d32 = 0 };
+
+	DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "OUT EP NYET");
+	core_if = GET_CORE_IF(pcd);
+	intr_mask.b.nyet = 1;
+
+	if (core_if->multiproc_int_enable) {
+		dwc_modify_reg32(&core_if->dev_if->dev_global_regs->
+				 doepeachintmsk[epnum], intr_mask.d32, 0);
+	} else {
+		dwc_modify_reg32(&core_if->dev_if->dev_global_regs->doepmsk,
+				 intr_mask.d32, 0);
+	}
+
+	return 1;
+}
+
+/**
+ * This interrupt indicates that an IN EP has a pending Interrupt.
+ * The sequence for handling the IN EP interrupt is shown below:
+ * -#	Read the Device All Endpoint Interrupt register
+ * -#	Repeat the following for each IN EP interrupt bit set (from
+ *		LSB to MSB).
+ * -#	Read the Device Endpoint Interrupt (DIEPINTn) register
+ * -#	If "Transfer Complete" call the request complete function
+ * -#	If "Endpoint Disabled" complete the EP disable procedure.
+ * -#	If "AHB Error Interrupt" log error
+ * -#	If "Time-out Handshake" log error
+ * -#	If "IN Token Received when TxFIFO Empty" write packet to Tx
+ *		FIFO.
+ * -#	If "IN Token EP Mismatch" (disable, this is handled by EP
+ *		Mismatch Interrupt)
+ */
+static int32_t dwc_otg_pcd_handle_in_ep_intr(dwc_otg_pcd_t * pcd)
+{
+#define CLEAR_IN_EP_INTR(__core_if,__epnum,__intr) \
+do { \
+		diepint_data_t diepint = {.d32=0}; \
+		diepint.b.__intr = 1; \
+		dwc_write_reg32(&__core_if->dev_if->in_ep_regs[__epnum]->diepint, \
+		diepint.d32); \
+} while (0)
+
+	dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+	dwc_otg_dev_if_t *dev_if = core_if->dev_if;
+	diepint_data_t diepint = {.d32 = 0 };
+	dctl_data_t dctl = {.d32 = 0 };
+	depctl_data_t depctl = {.d32 = 0 };
+	uint32_t ep_intr;
+	uint32_t epnum = 0;
+	dwc_otg_pcd_ep_t *ep;
+	dwc_ep_t *dwc_ep;
+	gintmsk_data_t intr_mask = {.d32 = 0 };
+
+	DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, pcd);
+
+	/* Read in the device interrupt bits */
+	ep_intr = dwc_otg_read_dev_all_in_ep_intr(core_if);
+
+	/* Service the Device IN interrupts for each endpoint */
+	while (ep_intr) {
+		if (ep_intr & 0x1) {
+			uint32_t empty_msk;
+			/* Get EP pointer */
+			ep = get_in_ep(pcd, epnum);
+			dwc_ep = &ep->dwc_ep;
+
+			depctl.d32 =
+			    dwc_read_reg32(&dev_if->in_ep_regs[epnum]->diepctl);
+			empty_msk =
+			    dwc_read_reg32(&dev_if->dev_global_regs->
+					   dtknqr4_fifoemptymsk);
+
+			DWC_DEBUGPL(DBG_PCDV,
+				    "IN EP INTERRUPT - %d\nepmty_msk - %8x  diepctl - %8x\n",
+				    epnum, empty_msk, depctl.d32);
+
+			DWC_DEBUGPL(DBG_PCD,
+				    "EP%d-%s: type=%d, mps=%d\n",
+				    dwc_ep->num, (dwc_ep->is_in ? "IN" : "OUT"),
+				    dwc_ep->type, dwc_ep->maxpacket);
+
+			diepint.d32 =
+			    dwc_otg_read_dev_in_ep_intr(core_if, dwc_ep);
+
+			DWC_DEBUGPL(DBG_PCDV,
+				    "EP %d Interrupt Register - 0x%x\n", epnum,
+				    diepint.d32);
+			/* Transfer complete */
+			if (diepint.b.xfercompl) {
+				/* Disable the NP Tx FIFO Empty
+				 * Interrrupt */
+				if (core_if->en_multiple_tx_fifo == 0) {
+					intr_mask.b.nptxfempty = 1;
+					dwc_modify_reg32(&core_if->
+							 core_global_regs->
+							 gintmsk, intr_mask.d32,
+							 0);
+				} else {
+					/* Disable the Tx FIFO Empty Interrupt for this EP */
+					uint32_t fifoemptymsk =
+					    0x1 << dwc_ep->num;
+					dwc_modify_reg32(&core_if->dev_if->
+							 dev_global_regs->
+							 dtknqr4_fifoemptymsk,
+							 fifoemptymsk, 0);
+				}
+				/* Clear the bit in DIEPINTn for this interrupt */
+				CLEAR_IN_EP_INTR(core_if, epnum, xfercompl);
+
+				/* Complete the transfer */
+				if (epnum == 0) {
+					handle_ep0(pcd);
+				}
+#ifdef DWC_EN_ISOC
+				else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
+					if (!ep->stopped)
+						complete_iso_ep(pcd, ep);
+				}
+#endif				/* DWC_EN_ISOC */
+				else {
+
+					complete_ep(ep);
+				}
+			}
+			/* Endpoint disable      */
+			if (diepint.b.epdisabled) {
+				DWC_DEBUGPL(DBG_ANY, "EP%d IN disabled\n",
+					    epnum);
+				handle_in_ep_disable_intr(pcd, epnum);
+
+				/* Clear the bit in DIEPINTn for this interrupt */
+				CLEAR_IN_EP_INTR(core_if, epnum, epdisabled);
+			}
+			/* AHB Error */
+			if (diepint.b.ahberr) {
+				DWC_DEBUGPL(DBG_ANY, "EP%d IN AHB Error\n",
+					    epnum);
+				/* Clear the bit in DIEPINTn for this interrupt */
+				CLEAR_IN_EP_INTR(core_if, epnum, ahberr);
+			}
+			/* TimeOUT Handshake (non-ISOC IN EPs) */
+			if (diepint.b.timeout) {
+				DWC_DEBUGPL(DBG_ANY, "EP%d IN Time-out\n",
+					    epnum);
+				handle_in_ep_timeout_intr(pcd, epnum);
+
+				CLEAR_IN_EP_INTR(core_if, epnum, timeout);
+			}
+			/** IN Token received with TxF Empty */
+			if (diepint.b.intktxfemp) {
+				DWC_DEBUGPL(DBG_ANY,
+					    "EP%d IN TKN TxFifo Empty\n",
+					    epnum);
+				if (!ep->stopped && epnum != 0) {
+
+					diepmsk_data_t diepmsk = {.d32 = 0 };
+					diepmsk.b.intktxfemp = 1;
+
+					if (core_if->multiproc_int_enable) {
+						dwc_modify_reg32(&dev_if->
+								 dev_global_regs->
+								 diepeachintmsk
+								 [epnum],
+								 diepmsk.d32,
+								 0);
+					} else {
+						dwc_modify_reg32(&dev_if->
+								 dev_global_regs->
+								 diepmsk,
+								 diepmsk.d32,
+								 0);
+					}
+				} else if (core_if->dma_desc_enable
+					   && epnum == 0
+					   && pcd->ep0state ==
+					   EP0_OUT_STATUS_PHASE) {
+					// EP0 IN set STALL
+					depctl.d32 =
+					    dwc_read_reg32(&dev_if->
+							   in_ep_regs[epnum]->
+							   diepctl);
+
+					/* set the disable and stall bits */
+					if (depctl.b.epena) {
+						depctl.b.epdis = 1;
+					}
+					depctl.b.stall = 1;
+					dwc_write_reg32(&dev_if->
+							in_ep_regs[epnum]->
+							diepctl, depctl.d32);
+				}
+				CLEAR_IN_EP_INTR(core_if, epnum, intktxfemp);
+			}
+			/** IN Token Received with EP mismatch */
+			if (diepint.b.intknepmis) {
+				DWC_DEBUGPL(DBG_ANY,
+					    "EP%d IN TKN EP Mismatch\n", epnum);
+				CLEAR_IN_EP_INTR(core_if, epnum, intknepmis);
+			}
+			/** IN Endpoint NAK Effective */
+			if (diepint.b.inepnakeff) {
+				DWC_DEBUGPL(DBG_ANY,
+					    "EP%d IN EP NAK Effective\n",
+					    epnum);
+				/* Periodic EP */
+				if (ep->disabling) {
+					depctl.d32 = 0;
+					depctl.b.snak = 1;
+					depctl.b.epdis = 1;
+					dwc_modify_reg32(&dev_if->
+							 in_ep_regs[epnum]->
+							 diepctl, depctl.d32,
+							 depctl.d32);
+				}
+				CLEAR_IN_EP_INTR(core_if, epnum, inepnakeff);
+
+			}
+
+			/** IN EP Tx FIFO Empty Intr */
+			if (diepint.b.emptyintr) {
+				DWC_DEBUGPL(DBG_ANY,
+					    "EP%d Tx FIFO Empty Intr \n",
+					    epnum);
+				write_empty_tx_fifo(pcd, epnum);
+
+				CLEAR_IN_EP_INTR(core_if, epnum, emptyintr);
+
+			}
+
+			/** IN EP BNA Intr */
+			if (diepint.b.bna) {
+				CLEAR_IN_EP_INTR(core_if, epnum, bna);
+				if (core_if->dma_desc_enable) {
+#ifdef DWC_EN_ISOC
+					if (dwc_ep->type ==
+					    DWC_OTG_EP_TYPE_ISOC) {
+						/*
+						 * This checking is performed to prevent first "false" BNA 
+						 * handling occuring right after reconnect 
+						 */
+						if (dwc_ep->next_frame !=
+						    0xffffffff)
+							dwc_otg_pcd_handle_iso_bna
+							    (ep);
+					} else
+#endif				/* DWC_EN_ISOC */
+					{
+						dctl.d32 =
+						    dwc_read_reg32(&dev_if->
+								   dev_global_regs->
+								   dctl);
+
+						/* If Global Continue on BNA is disabled - disable EP */
+						if (!dctl.b.gcontbna) {
+							depctl.d32 = 0;
+							depctl.b.snak = 1;
+							depctl.b.epdis = 1;
+							dwc_modify_reg32
+							    (&dev_if->
+							     in_ep_regs[epnum]->
+							     diepctl,
+							     depctl.d32,
+							     depctl.d32);
+						} else {
+							start_next_request(ep);
+						}
+					}
+				}
+			}
+			/* NAK Interrutp */
+			if (diepint.b.nak) {
+				DWC_DEBUGPL(DBG_ANY, "EP%d IN NAK Interrupt\n",
+					    epnum);
+				handle_in_ep_nak_intr(pcd, epnum);
+
+				CLEAR_IN_EP_INTR(core_if, epnum, nak);
+			}
+		}
+		epnum++;
+		ep_intr >>= 1;
+	}
+
+	return 1;
+#undef CLEAR_IN_EP_INTR
+}
+
+/**
+ * This interrupt indicates that an OUT EP has a pending Interrupt.
+ * The sequence for handling the OUT EP interrupt is shown below:
+ * -#	Read the Device All Endpoint Interrupt register
+ * -#	Repeat the following for each OUT EP interrupt bit set (from
+ *		LSB to MSB).
+ * -#	Read the Device Endpoint Interrupt (DOEPINTn) register
+ * -#	If "Transfer Complete" call the request complete function
+ * -#	If "Endpoint Disabled" complete the EP disable procedure.
+ * -#	If "AHB Error Interrupt" log error
+ * -#	If "Setup Phase Done" process Setup Packet (See Standard USB
+ *		Command Processing)
+ */
+static int32_t dwc_otg_pcd_handle_out_ep_intr(dwc_otg_pcd_t * pcd)
+{
+#define CLEAR_OUT_EP_INTR(__core_if,__epnum,__intr) \
+do { \
+		doepint_data_t doepint = {.d32=0}; \
+		doepint.b.__intr = 1; \
+		dwc_write_reg32(&__core_if->dev_if->out_ep_regs[__epnum]->doepint, \
+		doepint.d32); \
+} while (0)
+
+	dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+	dwc_otg_dev_if_t *dev_if = core_if->dev_if;
+	uint32_t ep_intr;
+	doepint_data_t doepint = {.d32 = 0 };
+	dctl_data_t dctl = {.d32 = 0 };
+	depctl_data_t doepctl = {.d32 = 0 };
+	uint32_t epnum = 0;
+	dwc_otg_pcd_ep_t *ep;
+	dwc_ep_t *dwc_ep;
+
+	DWC_DEBUGPL(DBG_PCDV, "%s()\n", __func__);
+
+	/* Read in the device interrupt bits */
+	ep_intr = dwc_otg_read_dev_all_out_ep_intr(core_if);
+
+	while (ep_intr) {
+		if (ep_intr & 0x1) {
+			/* Get EP pointer */
+			ep = get_out_ep(pcd, epnum);
+			dwc_ep = &ep->dwc_ep;
+
+#ifdef VERBOSE
+			DWC_DEBUGPL(DBG_PCDV,
+				    "EP%d-%s: type=%d, mps=%d\n",
+				    dwc_ep->num, (dwc_ep->is_in ? "IN" : "OUT"),
+				    dwc_ep->type, dwc_ep->maxpacket);
+#endif
+			doepint.d32 =
+			    dwc_otg_read_dev_out_ep_intr(core_if, dwc_ep);
+
+			/* Transfer complete */
+			if (doepint.b.xfercompl) {
+
+				if (epnum == 0) {
+					/* Clear the bit in DOEPINTn for this interrupt */
+					CLEAR_OUT_EP_INTR(core_if, epnum,
+							  xfercompl);
+					if (core_if->dma_desc_enable == 0
+					    || pcd->ep0state != EP0_IDLE)
+						handle_ep0(pcd);
+#ifdef DWC_EN_ISOC
+				} else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
+					if (doepint.b.pktdrpsts == 0) {
+						/* Clear the bit in DOEPINTn for this interrupt */
+						CLEAR_OUT_EP_INTR(core_if,
+								  epnum,
+								  xfercompl);
+						complete_iso_ep(pcd, ep);
+					} else {
+
+						doepint_data_t doepint = {.d32 =
+							    0 };
+						doepint.b.xfercompl = 1;
+						doepint.b.pktdrpsts = 1;
+						dwc_write_reg32(&core_if->
+								dev_if->
+								out_ep_regs
+								[epnum]->
+								doepint,
+								doepint.d32);
+						if (handle_iso_out_pkt_dropped
+						    (core_if, dwc_ep)) {
+							complete_iso_ep(pcd,
+									ep);
+						}
+					}
+#endif				/* DWC_EN_ISOC */
+				} else {
+					/* Clear the bit in DOEPINTn for this interrupt */
+					CLEAR_OUT_EP_INTR(core_if, epnum,
+							  xfercompl);
+					complete_ep(ep);
+				}
+
+			}
+
+			/* Endpoint disable      */
+			if (doepint.b.epdisabled) {
+
+				/* Clear the bit in DOEPINTn for this interrupt */
+				CLEAR_OUT_EP_INTR(core_if, epnum, epdisabled);
+			}
+			/* AHB Error */
+			if (doepint.b.ahberr) {
+				DWC_DEBUGPL(DBG_PCD, "EP%d OUT AHB Error\n",
+					    epnum);
+				DWC_DEBUGPL(DBG_PCD, "EP DMA REG	 %d \n",
+					    core_if->dev_if->
+					    out_ep_regs[epnum]->doepdma);
+				CLEAR_OUT_EP_INTR(core_if, epnum, ahberr);
+			}
+			/* Setup Phase Done (contorl EPs) */
+			if (doepint.b.setup) {
+#ifdef DEBUG_EP0
+				DWC_DEBUGPL(DBG_PCD, "EP%d SETUP Done\n",
+					    epnum);
+#endif
+				CLEAR_OUT_EP_INTR(core_if, epnum, setup);
+
+				handle_ep0(pcd);
+			}
+
+			/** OUT EP BNA Intr */
+			if (doepint.b.bna) {
+				CLEAR_OUT_EP_INTR(core_if, epnum, bna);
+				if (core_if->dma_desc_enable) {
+#ifdef DWC_EN_ISOC
+					if (dwc_ep->type ==
+					    DWC_OTG_EP_TYPE_ISOC) {
+						/*
+						 * This checking is performed to prevent first "false" BNA 
+						 * handling occuring right after reconnect 
+						 */
+						if (dwc_ep->next_frame !=
+						    0xffffffff)
+							dwc_otg_pcd_handle_iso_bna
+							    (ep);
+					} else
+#endif				/* DWC_EN_ISOC */
+					{
+						dctl.d32 =
+						    dwc_read_reg32(&dev_if->
+								   dev_global_regs->
+								   dctl);
+
+						/* If Global Continue on BNA is disabled - disable EP */
+						if (!dctl.b.gcontbna) {
+							doepctl.d32 = 0;
+							doepctl.b.snak = 1;
+							doepctl.b.epdis = 1;
+							dwc_modify_reg32
+							    (&dev_if->
+							     out_ep_regs
+							     [epnum]->doepctl,
+							     doepctl.d32,
+							     doepctl.d32);
+						} else {
+							start_next_request(ep);
+						}
+					}
+				}
+			}
+			if (doepint.b.stsphsercvd) {
+				CLEAR_OUT_EP_INTR(core_if, epnum, stsphsercvd);
+				if (core_if->dma_desc_enable) {
+					do_setup_in_status_phase(pcd);
+				}
+			}
+			/* Babble Interrutp */
+			if (doepint.b.babble) {
+				DWC_DEBUGPL(DBG_ANY, "EP%d OUT Babble\n",
+					    epnum);
+				handle_out_ep_babble_intr(pcd, epnum);
+
+				CLEAR_OUT_EP_INTR(core_if, epnum, babble);
+			}
+			/* NAK Interrutp */
+			if (doepint.b.nak) {
+				DWC_DEBUGPL(DBG_ANY, "EP%d OUT NAK\n", epnum);
+				handle_out_ep_nak_intr(pcd, epnum);
+
+				CLEAR_OUT_EP_INTR(core_if, epnum, nak);
+			}
+			/* NYET Interrutp */
+			if (doepint.b.nyet) {
+				DWC_DEBUGPL(DBG_ANY, "EP%d OUT NYET\n", epnum);
+				handle_out_ep_nyet_intr(pcd, epnum);
+
+				CLEAR_OUT_EP_INTR(core_if, epnum, nyet);
+			}
+		}
+
+		epnum++;
+		ep_intr >>= 1;
+	}
+
+	return 1;
+
+#undef CLEAR_OUT_EP_INTR
+}
+
+/**
+ * Incomplete ISO IN Transfer Interrupt.
+ * This interrupt indicates one of the following conditions occurred
+ * while transmitting an ISOC transaction.
+ * - Corrupted IN Token for ISOC EP.
+ * - Packet not complete in FIFO.
+ * The follow actions will be taken:
+ *	-#	Determine the EP
+ *	-#	Set incomplete flag in dwc_ep structure
+ *	-#	Disable EP; when "Endpoint Disabled" interrupt is received
+ *		Flush FIFO
+ */
+int32_t dwc_otg_pcd_handle_incomplete_isoc_in_intr(dwc_otg_pcd_t * pcd)
+{
+	gintsts_data_t gintsts;
+
+#ifdef DWC_EN_ISOC
+	dwc_otg_dev_if_t *dev_if;
+	deptsiz_data_t deptsiz = {.d32 = 0 };
+	depctl_data_t depctl = {.d32 = 0 };
+	dsts_data_t dsts = {.d32 = 0 };
+	dwc_ep_t *dwc_ep;
+	int i;
+
+	dev_if = GET_CORE_IF(pcd)->dev_if;
+
+	for (i = 1; i <= dev_if->num_in_eps; ++i) {
+		dwc_ep = &pcd->in_ep[i].dwc_ep;
+		if (dwc_ep->active && dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
+			deptsiz.d32 =
+			    dwc_read_reg32(&dev_if->in_ep_regs[i]->dieptsiz);
+			depctl.d32 =
+			    dwc_read_reg32(&dev_if->in_ep_regs[i]->diepctl);
+
+			if (depctl.b.epdis && deptsiz.d32) {
+				set_current_pkt_info(GET_CORE_IF(pcd), dwc_ep);
+				if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
+					dwc_ep->cur_pkt = 0;
+					dwc_ep->proc_buf_num =
+					    (dwc_ep->proc_buf_num ^ 1) & 0x1;
+
+					if (dwc_ep->proc_buf_num) {
+						dwc_ep->cur_pkt_addr =
+						    dwc_ep->xfer_buff1;
+						dwc_ep->cur_pkt_dma_addr =
+						    dwc_ep->dma_addr1;
+					} else {
+						dwc_ep->cur_pkt_addr =
+						    dwc_ep->xfer_buff0;
+						dwc_ep->cur_pkt_dma_addr =
+						    dwc_ep->dma_addr0;
+					}
+
+				}
+
+				dsts.d32 =
+				    dwc_read_reg32(&GET_CORE_IF(pcd)->dev_if->
+						   dev_global_regs->dsts);
+				dwc_ep->next_frame = dsts.b.soffn;
+
+				dwc_otg_iso_ep_start_frm_transfer(GET_CORE_IF
+								  (pcd),
+								  dwc_ep);
+			}
+		}
+	}
+
+#else
+	gintmsk_data_t intr_mask = {.d32 = 0 };
+	DWC_PRINTF("INTERRUPT Handler not implemented for %s\n",
+		   "IN ISOC Incomplete");
+
+	intr_mask.b.incomplisoin = 1;
+	dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
+			 intr_mask.d32, 0);
+#endif				//DWC_EN_ISOC
+
+	/* Clear interrupt */
+	gintsts.d32 = 0;
+	gintsts.b.incomplisoin = 1;
+	dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
+			gintsts.d32);
+
+	return 1;
+}
+
+/**
+ * Incomplete ISO OUT Transfer Interrupt.
+ *
+ * This interrupt indicates that the core has dropped an ISO OUT
+ * packet.	The following conditions can be the cause:
+ * - FIFO Full, the entire packet would not fit in the FIFO.
+ * - CRC Error
+ * - Corrupted Token
+ * The follow actions will be taken:
+ *	-#	Determine the EP
+ *	-#	Set incomplete flag in dwc_ep structure
+ *	-#	Read any data from the FIFO
+ *	-#	Disable EP.	 when "Endpoint Disabled" interrupt is received
+ *		re-enable EP.
+ */
+int32_t dwc_otg_pcd_handle_incomplete_isoc_out_intr(dwc_otg_pcd_t * pcd)
+{
+
+	gintsts_data_t gintsts;
+
+#ifdef DWC_EN_ISOC
+	dwc_otg_dev_if_t *dev_if;
+	deptsiz_data_t deptsiz = {.d32 = 0 };
+	depctl_data_t depctl = {.d32 = 0 };
+	dsts_data_t dsts = {.d32 = 0 };
+	dwc_ep_t *dwc_ep;
+	int i;
+
+	dev_if = GET_CORE_IF(pcd)->dev_if;
+
+	for (i = 1; i <= dev_if->num_out_eps; ++i) {
+		dwc_ep = &pcd->in_ep[i].dwc_ep;
+		if (pcd->out_ep[i].dwc_ep.active &&
+		    pcd->out_ep[i].dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
+			deptsiz.d32 =
+			    dwc_read_reg32(&dev_if->out_ep_regs[i]->doeptsiz);
+			depctl.d32 =
+			    dwc_read_reg32(&dev_if->out_ep_regs[i]->doepctl);
+
+			if (depctl.b.epdis && deptsiz.d32) {
+				set_current_pkt_info(GET_CORE_IF(pcd),
+						     &pcd->out_ep[i].dwc_ep);
+				if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
+					dwc_ep->cur_pkt = 0;
+					dwc_ep->proc_buf_num =
+					    (dwc_ep->proc_buf_num ^ 1) & 0x1;
+
+					if (dwc_ep->proc_buf_num) {
+						dwc_ep->cur_pkt_addr =
+						    dwc_ep->xfer_buff1;
+						dwc_ep->cur_pkt_dma_addr =
+						    dwc_ep->dma_addr1;
+					} else {
+						dwc_ep->cur_pkt_addr =
+						    dwc_ep->xfer_buff0;
+						dwc_ep->cur_pkt_dma_addr =
+						    dwc_ep->dma_addr0;
+					}
+
+				}
+
+				dsts.d32 =
+				    dwc_read_reg32(&GET_CORE_IF(pcd)->dev_if->
+						   dev_global_regs->dsts);
+				dwc_ep->next_frame = dsts.b.soffn;
+
+				dwc_otg_iso_ep_start_frm_transfer(GET_CORE_IF
+								  (pcd),
+								  dwc_ep);
+			}
+		}
+	}
+#else
+	/** @todo implement ISR */
+	gintmsk_data_t intr_mask = {.d32 = 0 };
+
+	DWC_PRINTF("INTERRUPT Handler not implemented for %s\n",
+		   "OUT ISOC Incomplete");
+
+	intr_mask.b.incomplisoout = 1;
+	dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
+			 intr_mask.d32, 0);
+
+#endif				/* DWC_EN_ISOC */
+
+	/* Clear interrupt */
+	gintsts.d32 = 0;
+	gintsts.b.incomplisoout = 1;
+	dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
+			gintsts.d32);
+
+	return 1;
+}
+
+/**
+ * This function handles the Global IN NAK Effective interrupt.
+ *
+ */
+int32_t dwc_otg_pcd_handle_in_nak_effective(dwc_otg_pcd_t * pcd)
+{
+	dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
+	depctl_data_t diepctl = {.d32 = 0 };
+	depctl_data_t diepctl_rd = {.d32 = 0 };
+	gintmsk_data_t intr_mask = {.d32 = 0 };
+	gintsts_data_t gintsts;
+	int i;
+
+	DWC_DEBUGPL(DBG_PCD, "Global IN NAK Effective\n");
+
+	/* Disable all active IN EPs */
+	diepctl.b.epdis = 1;
+	diepctl.b.snak = 1;
+
+	for (i = 0; i <= dev_if->num_in_eps; i++) {
+		diepctl_rd.d32 =
+		    dwc_read_reg32(&dev_if->in_ep_regs[i]->diepctl);
+		if (diepctl_rd.b.epena) {
+			dwc_write_reg32(&dev_if->in_ep_regs[i]->diepctl,
+					diepctl.d32);
+		}
+	}
+	/* Disable the Global IN NAK Effective Interrupt */
+	intr_mask.b.ginnakeff = 1;
+	dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
+			 intr_mask.d32, 0);
+
+	/* Clear interrupt */
+	gintsts.d32 = 0;
+	gintsts.b.ginnakeff = 1;
+	dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
+			gintsts.d32);
+
+	return 1;
+}
+
+/**
+ * OUT NAK Effective.
+ *
+ */
+int32_t dwc_otg_pcd_handle_out_nak_effective(dwc_otg_pcd_t * pcd)
+{
+	gintmsk_data_t intr_mask = {.d32 = 0 };
+	gintsts_data_t gintsts;
+
+	DWC_PRINTF("INTERRUPT Handler not implemented for %s\n",
+		   "Global IN NAK Effective\n");
+	/* Disable the Global IN NAK Effective Interrupt */
+	intr_mask.b.goutnakeff = 1;
+	dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
+			 intr_mask.d32, 0);
+
+	/* Clear interrupt */
+	gintsts.d32 = 0;
+	gintsts.b.goutnakeff = 1;
+	dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
+			gintsts.d32);
+
+	return 1;
+}
+
+/**
+ * PCD interrupt handler.
+ *
+ * The PCD handles the device interrupts.  Many conditions can cause a
+ * device interrupt. When an interrupt occurs, the device interrupt
+ * service routine determines the cause of the interrupt and
+ * dispatches handling to the appropriate function. These interrupt
+ * handling functions are described below.
+ *
+ * All interrupt registers are processed from LSB to MSB.
+ *
+ */
+int32_t dwc_otg_pcd_handle_intr(dwc_otg_pcd_t * pcd)
+{
+	dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+#ifdef VERBOSE
+	dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
+#endif
+	gintsts_data_t gintr_status;
+	int32_t retval = 0;
+
+#ifdef VERBOSE
+	DWC_DEBUGPL(DBG_ANY, "%s() gintsts=%08x	 gintmsk=%08x\n",
+		    __func__,
+		    dwc_read_reg32(&global_regs->gintsts),
+		    dwc_read_reg32(&global_regs->gintmsk));
+#endif
+
+	if (dwc_otg_is_device_mode(core_if)) {
+		DWC_SPINLOCK(pcd->lock);
+#ifdef VERBOSE
+		DWC_DEBUGPL(DBG_PCDV, "%s() gintsts=%08x  gintmsk=%08x\n",
+			    __func__,
+			    dwc_read_reg32(&global_regs->gintsts),
+			    dwc_read_reg32(&global_regs->gintmsk));
+#endif
+
+		gintr_status.d32 = dwc_otg_read_core_intr(core_if);
+
+		DWC_DEBUGPL(DBG_PCDV, "%s: gintsts&gintmsk=%08x\n",
+			    __func__, gintr_status.d32);
+
+		if (gintr_status.b.sofintr) {
+			retval |= dwc_otg_pcd_handle_sof_intr(pcd);
+		}
+		if (gintr_status.b.rxstsqlvl) {
+			retval |=
+			    dwc_otg_pcd_handle_rx_status_q_level_intr(pcd);
+		}
+		if (gintr_status.b.nptxfempty) {
+			retval |= dwc_otg_pcd_handle_np_tx_fifo_empty_intr(pcd);
+		}
+		if (gintr_status.b.ginnakeff) {
+			retval |= dwc_otg_pcd_handle_in_nak_effective(pcd);
+		}
+		if (gintr_status.b.goutnakeff) {
+			retval |= dwc_otg_pcd_handle_out_nak_effective(pcd);
+		}
+		if (gintr_status.b.i2cintr) {
+			retval |= dwc_otg_pcd_handle_i2c_intr(pcd);
+		}
+		if (gintr_status.b.erlysuspend) {
+			retval |= dwc_otg_pcd_handle_early_suspend_intr(pcd);
+		}
+		if (gintr_status.b.usbreset) {
+			retval |= dwc_otg_pcd_handle_usb_reset_intr(pcd);
+		}
+		if (gintr_status.b.enumdone) {
+			retval |= dwc_otg_pcd_handle_enum_done_intr(pcd);
+		}
+		if (gintr_status.b.isooutdrop) {
+			retval |=
+			    dwc_otg_pcd_handle_isoc_out_packet_dropped_intr
+			    (pcd);
+		}
+		if (gintr_status.b.eopframe) {
+			retval |=
+			    dwc_otg_pcd_handle_end_periodic_frame_intr(pcd);
+		}
+		if (gintr_status.b.epmismatch) {
+			retval |= dwc_otg_pcd_handle_ep_mismatch_intr(core_if);
+		}
+		if (gintr_status.b.inepint) {
+			if (!core_if->multiproc_int_enable) {
+				retval |= dwc_otg_pcd_handle_in_ep_intr(pcd);
+			}
+		}
+		if (gintr_status.b.outepintr) {
+			if (!core_if->multiproc_int_enable) {
+				retval |= dwc_otg_pcd_handle_out_ep_intr(pcd);
+			}
+		}
+		if (gintr_status.b.incomplisoin) {
+			retval |=
+			    dwc_otg_pcd_handle_incomplete_isoc_in_intr(pcd);
+		}
+		if (gintr_status.b.incomplisoout) {
+			retval |=
+			    dwc_otg_pcd_handle_incomplete_isoc_out_intr(pcd);
+		}
+
+		/* In MPI mode De vice Endpoints intterrupts are asserted 
+		 * without setting outepintr and inepint bits set, so these
+		 * Interrupt handlers are called without checking these bit-fields
+		 */
+		if (core_if->multiproc_int_enable) {
+			retval |= dwc_otg_pcd_handle_in_ep_intr(pcd);
+			retval |= dwc_otg_pcd_handle_out_ep_intr(pcd);
+		}
+#ifdef VERBOSE
+		DWC_DEBUGPL(DBG_PCDV, "%s() gintsts=%0x\n", __func__,
+			    dwc_read_reg32(&global_regs->gintsts));
+#endif
+		DWC_SPINUNLOCK(pcd->lock);
+	}
+	return retval;
+}
+
+#endif				/* DWC_HOST_ONLY */
diff --git a/drivers/usb/host/dwc_otg/dwc_otg_pcd_linux.c b/drivers/usb/host/dwc_otg/dwc_otg_pcd_linux.c
new file mode 100644
index 000000000000..aae78a717f7e
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/dwc_otg_pcd_linux.c
@@ -0,0 +1,1288 @@
+ /* ==========================================================================
+  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_linux.c $
+  * $Revision: #7 $
+  * $Date: 2009/04/03 $
+  * $Change: 1225160 $
+  *
+  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+  * otherwise expressly agreed to in writing between Synopsys and you.
+  *
+  * The Software IS NOT an item of Licensed Software or Licensed Product under
+  * any End User Software License Agreement or Agreement for Licensed Product
+  * with Synopsys or any supplement thereto. You are permitted to use and
+  * redistribute this Software in source and binary forms, with or without
+  * modification, provided that redistributions of source code must retain this
+  * notice. You may not view, use, disclose, copy or distribute this file or
+  * any information contained herein except pursuant to this license grant from
+  * Synopsys. If you do not agree with this notice, including the disclaimer
+  * below, then you are not authorized to use the Software.
+  *
+  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+  * DAMAGE.
+  * ========================================================================== */
+#ifndef DWC_HOST_ONLY
+
+/** @file
+ * This file implements the Peripheral Controller Driver.
+ *
+ * The Peripheral Controller Driver (PCD) is responsible for
+ * translating requests from the Function Driver into the appropriate
+ * actions on the DWC_otg controller. It isolates the Function Driver
+ * from the specifics of the controller by providing an API to the
+ * Function Driver.
+ *
+ * The Peripheral Controller Driver for Linux will implement the
+ * Gadget API, so that the existing Gadget drivers can be used.
+ * (Gadget Driver is the Linux terminology for a Function Driver.)
+ *
+ * The Linux Gadget API is defined in the header file
+ * <code><linux/usb_gadget.h></code>.  The USB EP operations API is
+ * defined in the structure <code>usb_ep_ops</code> and the USB
+ * Controller API is defined in the structure
+ * <code>usb_gadget_ops</code>.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/list.h>
+#include <linux/interrupt.h>
+#include <linux/string.h>
+#include <linux/dma-mapping.h>
+#include <linux/version.h>
+
+#if defined(LM_INTERFACE)
+//# include <asm/arch/regs-irq.h>
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30))
+#include <asm/arch/lm.h>
+#else
+/* by 2.6.31, at least, the location of some headers has changed
+*/
+#include <mach/lm.h>
+#endif
+
+#elif defined(PLATFORM_INTERFACE)
+#include <linux/platform_device.h>
+#endif
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30))
+#include <asm/arch/irqs.h>
+#include <linux/usb_ch9.h>
+#include <linux/usb_gadget.h>
+#else
+/* by 2.6.31, at least, the location of some headers has changed
+*/
+#include <mach/irqs.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#endif
+
+#include <asm/io.h>
+
+#include "dwc_otg_pcd_if.h"
+#include "dwc_otg_driver.h"
+#include "dwc_otg_dbg.h"
+
+static struct gadget_wrapper {
+	dwc_otg_pcd_t *pcd;
+
+	struct usb_gadget gadget;
+	struct usb_gadget_driver *driver;
+
+	struct usb_ep ep0;
+	struct usb_ep in_ep[16];
+	struct usb_ep out_ep[16];
+
+} *gadget_wrapper;
+
+/* Display the contents of the buffer */
+extern void dump_msg(const u8 * buf, unsigned int length);
+
+/* USB Endpoint Operations */
+/*
+ * The following sections briefly describe the behavior of the Gadget
+ * API endpoint operations implemented in the DWC_otg driver
+ * software. Detailed descriptions of the generic behavior of each of
+ * these functions can be found in the Linux header file
+ * include/linux/usb_gadget.h.
+ *
+ * The Gadget API provides wrapper functions for each of the function
+ * pointers defined in usb_ep_ops. The Gadget Driver calls the wrapper
+ * function, which then calls the underlying PCD function. The
+ * following sections are named according to the wrapper
+ * functions. Within each section, the corresponding DWC_otg PCD
+ * function name is specified.
+ *
+ */
+
+/**
+ * This function is called by the Gadget Driver for each EP to be
+ * configured for the current configuration (SET_CONFIGURATION).
+ *
+ * This function initializes the dwc_otg_ep_t data structure, and then
+ * calls dwc_otg_ep_activate.
+ */
+static int ep_enable(struct usb_ep *usb_ep,
+		     const struct usb_endpoint_descriptor *ep_desc)
+{
+	int retval;
+
+	DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p)\n", __func__, usb_ep, ep_desc);
+
+	if (!usb_ep || !ep_desc || ep_desc->bDescriptorType != USB_DT_ENDPOINT) {
+		DWC_WARN("%s, bad ep or descriptor\n", __func__);
+		return -EINVAL;
+	}
+	if (usb_ep == &gadget_wrapper->ep0) {
+		DWC_WARN("%s, bad ep(0)\n", __func__);
+		return -EINVAL;
+	}
+
+	/* Check FIFO size? */
+	if (!ep_desc->wMaxPacketSize) {
+		DWC_WARN("%s, bad %s maxpacket\n", __func__, usb_ep->name);
+		return -ERANGE;
+	}
+
+	if (!gadget_wrapper->driver ||
+	    gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {
+		DWC_WARN("%s, bogus device state\n", __func__);
+		return -ESHUTDOWN;
+	}
+
+	retval = dwc_otg_pcd_ep_enable(gadget_wrapper->pcd,
+				       (const uint8_t *)ep_desc,
+				       (void *)usb_ep);
+	if (retval) {
+		DWC_WARN("dwc_otg_pcd_ep_enable failed\n");
+		return -EINVAL;
+	}
+
+	usb_ep->maxpacket = le16_to_cpu(ep_desc->wMaxPacketSize);
+
+	return 0;
+}
+
+/**
+ * This function is called when an EP is disabled due to disconnect or
+ * change in configuration. Any pending requests will terminate with a
+ * status of -ESHUTDOWN.
+ *
+ * This function modifies the dwc_otg_ep_t data structure for this EP,
+ * and then calls dwc_otg_ep_deactivate.
+ */
+static int ep_disable(struct usb_ep *usb_ep)
+{
+	int retval;
+
+	DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, usb_ep);
+	if (!usb_ep) {
+		DWC_DEBUGPL(DBG_PCD, "%s, %s not enabled\n", __func__,
+			    usb_ep ? usb_ep->name : NULL);
+		return -EINVAL;
+	}
+
+	retval = dwc_otg_pcd_ep_disable(gadget_wrapper->pcd, usb_ep);
+	if (retval) {
+		retval = -EINVAL;
+	}
+
+	return retval;
+}
+
+/**
+ * This function allocates a request object to use with the specified
+ * endpoint.
+ *
+ * @param ep The endpoint to be used with with the request
+ * @param gfp_flags the GFP_* flags to use.
+ */
+static struct usb_request *dwc_otg_pcd_alloc_request(struct usb_ep *ep,
+						     gfp_t gfp_flags)
+{
+	struct usb_request *usb_req;
+
+	DWC_DEBUGPL(DBG_PCDV, "%s(%p,%d)\n", __func__, ep, gfp_flags);
+	if (0 == ep) {
+		DWC_WARN("%s() %s\n", __func__, "Invalid EP!\n");
+		return 0;
+	}
+	usb_req = kmalloc(sizeof(*usb_req), gfp_flags);
+	if (0 == usb_req) {
+		DWC_WARN("%s() %s\n", __func__, "request allocation failed!\n");
+		return 0;
+	}
+	memset(usb_req, 0, sizeof(*usb_req));
+	usb_req->dma = DWC_INVALID_DMA_ADDR;
+
+	return usb_req;
+}
+
+/**
+ * This function frees a request object.
+ *
+ * @param ep The endpoint associated with the request
+ * @param req The request being freed
+ */
+static void dwc_otg_pcd_free_request(struct usb_ep *ep, struct usb_request *req)
+{
+	DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p)\n", __func__, ep, req);
+
+	if (0 == ep || 0 == req) {
+		DWC_WARN("%s() %s\n", __func__,
+			 "Invalid ep or req argument!\n");
+		return;
+	}
+
+	kfree(req);
+}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30))
+/**
+ * This function allocates an I/O buffer to be used for a transfer
+ * to/from the specified endpoint.
+ *
+ * @param usb_ep The endpoint to be used with with the request
+ * @param bytes The desired number of bytes for the buffer
+ * @param dma Pointer to the buffer's DMA address; must be valid
+ * @param gfp_flags the GFP_* flags to use.
+ * @return address of a new buffer or null is buffer could not be allocated.
+ */
+static void *dwc_otg_pcd_alloc_buffer(struct usb_ep *usb_ep, unsigned bytes,
+				      dma_addr_t * dma, gfp_t gfp_flags)
+{
+	void *buf;
+	dwc_otg_pcd_t *pcd = 0;
+
+	pcd = gadget_wrapper->pcd;
+
+	DWC_DEBUGPL(DBG_PCDV, "%s(%p,%d,%p,%0x)\n", __func__, usb_ep, bytes,
+		    dma, gfp_flags);
+
+	/* Check dword alignment */
+	if ((bytes & 0x3UL) != 0) {
+		DWC_WARN("%s() Buffer size is not a multiple of"
+			 "DWORD size (%d)", __func__, bytes);
+	}
+
+	buf = dma_alloc_coherent(NULL, bytes, dma, gfp_flags);
+
+	/* Check dword alignment */
+	if (((int)buf & 0x3UL) != 0) {
+		DWC_WARN("%s() Buffer is not DWORD aligned (%p)",
+			 __func__, buf);
+	}
+
+	return buf;
+}
+
+/**
+ * This function frees an I/O buffer that was allocated by alloc_buffer.
+ *
+ * @param usb_ep the endpoint associated with the buffer
+ * @param buf address of the buffer
+ * @param dma The buffer's DMA address
+ * @param bytes The number of bytes of the buffer
+ */
+static void dwc_otg_pcd_free_buffer(struct usb_ep *usb_ep, void *buf,
+				    dma_addr_t dma, unsigned bytes)
+{
+	dwc_otg_pcd_t *pcd = 0;
+
+	pcd = gadget_wrapper->pcd;
+
+	DWC_DEBUGPL(DBG_PCDV, "%s(%p,%0x,%d)\n", __func__, buf, dma, bytes);
+
+	dma_free_coherent(NULL, bytes, buf, dma);
+}
+#endif
+
+/**
+ * This function is used to submit an I/O Request to an EP.
+ *
+ *	- When the request completes the request's completion callback
+ *	  is called to return the request to the driver.
+ *	- An EP, except control EPs, may have multiple requests
+ *	  pending.
+ *	- Once submitted the request cannot be examined or modified.
+ *	- Each request is turned into one or more packets.
+ *	- A BULK EP can queue any amount of data; the transfer is
+ *	  packetized.
+ *	- Zero length Packets are specified with the request 'zero'
+ *	  flag.
+ */
+static int ep_queue(struct usb_ep *usb_ep, struct usb_request *usb_req,
+		    gfp_t gfp_flags)
+{
+	dwc_otg_pcd_t *pcd;
+	int retval;
+
+	DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p,%d)\n",
+		    __func__, usb_ep, usb_req, gfp_flags);
+
+	if (!usb_req || !usb_req->complete || !usb_req->buf) {
+		DWC_WARN("bad params\n");
+		return -EINVAL;
+	}
+
+	if (!usb_ep) {
+		DWC_WARN("bad ep\n");
+		return -EINVAL;
+	}
+
+	pcd = gadget_wrapper->pcd;
+	if (!gadget_wrapper->driver ||
+	    gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {
+		DWC_DEBUGPL(DBG_PCDV, "gadget.speed=%d\n",
+			    gadget_wrapper->gadget.speed);
+		DWC_WARN("bogus device state\n");
+		return -ESHUTDOWN;
+	}
+
+	DWC_DEBUGPL(DBG_PCD, "%s queue req %p, len %d buf %p\n",
+		    usb_ep->name, usb_req, usb_req->length, usb_req->buf);
+
+	usb_req->status = -EINPROGRESS;
+	usb_req->actual = 0;
+
+	retval = dwc_otg_pcd_ep_queue(pcd, usb_ep, usb_req->buf, usb_req->dma,
+				      usb_req->length, usb_req->zero, usb_req,
+				      gfp_flags == GFP_ATOMIC ? 1 : 0);
+	if (retval) {
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+/**
+ * This function cancels an I/O request from an EP.
+ */
+static int ep_dequeue(struct usb_ep *usb_ep, struct usb_request *usb_req)
+{
+	DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p)\n", __func__, usb_ep, usb_req);
+
+	if (!usb_ep || !usb_req) {
+		DWC_WARN("bad argument\n");
+		return -EINVAL;
+	}
+	if (!gadget_wrapper->driver ||
+	    gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {
+		DWC_WARN("bogus device state\n");
+		return -ESHUTDOWN;
+	}
+	if (dwc_otg_pcd_ep_dequeue(gadget_wrapper->pcd, usb_ep, usb_req)) {
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+/**
+ * usb_ep_set_halt stalls an endpoint.
+ *
+ * usb_ep_clear_halt clears an endpoint halt and resets its data
+ * toggle.
+ *
+ * Both of these functions are implemented with the same underlying
+ * function. The behavior depends on the value argument.
+ *
+ * @param[in] usb_ep the Endpoint to halt or clear halt.
+ * @param[in] value
+ *	- 0 means clear_halt.
+ *	- 1 means set_halt,
+ *	- 2 means clear stall lock flag.
+ *	- 3 means set  stall lock flag.
+ */
+static int ep_halt(struct usb_ep *usb_ep, int value)
+{
+	int retval = 0;
+
+	DWC_DEBUGPL(DBG_PCD, "HALT %s %d\n", usb_ep->name, value);
+
+	if (!usb_ep) {
+		DWC_WARN("bad ep\n");
+		return -EINVAL;
+	}
+
+	retval = dwc_otg_pcd_ep_halt(gadget_wrapper->pcd, usb_ep, value);
+	if (retval == -DWC_E_AGAIN) {
+		return -EAGAIN;
+	} else if (retval) {
+		retval = -EINVAL;
+	}
+
+	return retval;
+}
+
+//#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30))
+#if 0
+/**
+ * ep_wedge: sets the halt feature and ignores clear requests
+ *
+ * @usb_ep: the endpoint being wedged
+ *
+ * Use this to stall an endpoint and ignore CLEAR_FEATURE(HALT_ENDPOINT)
+ * requests. If the gadget driver clears the halt status, it will
+ * automatically unwedge the endpoint.
+ *
+ * Returns zero on success, else negative errno. *
+ * Check usb_ep_set_wedge() at "usb_gadget.h" for details
+ */
+static int ep_wedge(struct usb_ep *usb_ep)
+{
+	int retval = 0;
+
+	DWC_DEBUGPL(DBG_PCD, "WEDGE %s\n", usb_ep->name);
+
+	if (!usb_ep) {
+		DWC_WARN("bad ep\n");
+		return -EINVAL;
+	}
+
+	retval = dwc_otg_pcd_ep_wedge(gadget_wrapper->pcd, usb_ep);
+	if (retval == -DWC_E_AGAIN) {
+		retval = -EAGAIN;
+	} else if (retval) {
+		retval = -EINVAL;
+	}
+
+	return retval;
+}
+#endif
+
+#ifdef DWC_EN_ISOC
+/**
+ * This function is used to submit an ISOC Transfer Request to an EP.
+ *
+ *	- Every time a sync period completes the request's completion callback
+ *	  is called to provide data to the gadget driver.
+ *	- Once submitted the request cannot be modified.
+ *	- Each request is turned into periodic data packets untill ISO
+ *	  Transfer is stopped..
+ */
+static int iso_ep_start(struct usb_ep *usb_ep, struct usb_iso_request *req,
+			gfp_t gfp_flags)
+{
+	int retval = 0;
+
+	if (!req || !req->process_buffer || !req->buf0 || !req->buf1) {
+		DWC_WARN("bad params\n");
+		return -EINVAL;
+	}
+
+	if (!usb_ep) {
+		DWC_PRINTF("bad params\n");
+		return -EINVAL;
+	}
+
+	req->status = -EINPROGRESS;
+
+	retval =
+	    dwc_otg_pcd_iso_ep_start(gadget_wrapper->pcd, usb_ep, req->buf0,
+				     req->buf1, req->dma0, req->dma1,
+				     req->sync_frame, req->data_pattern_frame,
+				     req->data_per_frame,
+				     req->flags & USB_REQ_ISO_ASAP ? -1 : req->
+				     start_frame, req->buf_proc_intrvl, req,
+				     gfp_flags == GFP_ATOMIC ? 1 : 0);
+
+	if (retval) {
+		return -EINVAL;
+	}
+
+	return retval;
+}
+
+/**
+ * This function stops ISO EP Periodic Data Transfer.
+ */
+static int iso_ep_stop(struct usb_ep *usb_ep, struct usb_iso_request *req)
+{
+	int retval = 0;
+	if (!usb_ep) {
+		DWC_WARN("bad ep\n");
+	}
+
+	if (!gadget_wrapper->driver ||
+	    gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {
+		DWC_DEBUGPL(DBG_PCDV, "gadget.speed=%d\n",
+			    gadget_wrapper->gadget.speed);
+		DWC_WARN("bogus device state\n");
+	}
+
+	dwc_otg_pcd_iso_ep_stop(gadget_wrapper->pcd, usb_ep, req);
+	if (retval) {
+		retval = -EINVAL;
+	}
+
+	return retval;
+}
+
+static struct usb_iso_request *alloc_iso_request(struct usb_ep *ep,
+						 int packets, gfp_t gfp_flags)
+{
+	struct usb_iso_request *pReq = NULL;
+	uint32_t req_size;
+
+	req_size = sizeof(struct usb_iso_request);
+	req_size +=
+	    (2 * packets * (sizeof(struct usb_gadget_iso_packet_descriptor)));
+
+	pReq = kmalloc(req_size, gfp_flags);
+	if (!pReq) {
+		DWC_WARN("Can't allocate Iso Request\n");
+		return 0;
+	}
+	pReq->iso_packet_desc0 = (void *)(pReq + 1);
+
+	pReq->iso_packet_desc1 = pReq->iso_packet_desc0 + packets;
+
+	return pReq;
+}
+
+static void free_iso_request(struct usb_ep *ep, struct usb_iso_request *req)
+{
+	kfree(req);
+}
+
+static struct usb_isoc_ep_ops dwc_otg_pcd_ep_ops = {
+	.ep_ops = {
+		   .enable = ep_enable,
+		   .disable = ep_disable,
+
+		   .alloc_request = dwc_otg_pcd_alloc_request,
+		   .free_request = dwc_otg_pcd_free_request,
+
+		   .alloc_buffer = dwc_otg_pcd_alloc_buffer,
+		   .free_buffer = dwc_otg_pcd_free_buffer,
+
+		   .queue = ep_queue,
+		   .dequeue = ep_dequeue,
+
+		   .set_halt = ep_halt,
+		   .fifo_status = 0,
+		   .fifo_flush = 0,
+		   },
+	.iso_ep_start = iso_ep_start,
+	.iso_ep_stop = iso_ep_stop,
+	.alloc_iso_request = alloc_iso_request,
+	.free_iso_request = free_iso_request,
+};
+
+#else
+
+	int (*enable) (struct usb_ep *ep,
+		const struct usb_endpoint_descriptor *desc);
+	int (*disable) (struct usb_ep *ep);
+
+	struct usb_request *(*alloc_request) (struct usb_ep *ep,
+		gfp_t gfp_flags);
+	void (*free_request) (struct usb_ep *ep, struct usb_request *req);
+
+	int (*queue) (struct usb_ep *ep, struct usb_request *req,
+		gfp_t gfp_flags);
+	int (*dequeue) (struct usb_ep *ep, struct usb_request *req);
+
+	int (*set_halt) (struct usb_ep *ep, int value);
+	int (*set_wedge) (struct usb_ep *ep);
+
+	int (*fifo_status) (struct usb_ep *ep);
+	void (*fifo_flush) (struct usb_ep *ep);
+static struct usb_ep_ops dwc_otg_pcd_ep_ops = {
+	.enable = ep_enable,
+	.disable = ep_disable,
+
+	.alloc_request = dwc_otg_pcd_alloc_request,
+	.free_request = dwc_otg_pcd_free_request,
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30))
+	.alloc_buffer = dwc_otg_pcd_alloc_buffer,
+	.free_buffer = dwc_otg_pcd_free_buffer,
+#else
+	/* .set_wedge = ep_wedge, */
+        .set_wedge = NULL, /* uses set_halt instead */
+#endif
+        
+	.queue = ep_queue,
+	.dequeue = ep_dequeue,
+
+	.set_halt = ep_halt,
+	.fifo_status = 0,
+	.fifo_flush = 0,
+
+};
+
+#endif				/* _EN_ISOC_ */
+/*	Gadget Operations */
+/**
+ * The following gadget operations will be implemented in the DWC_otg
+ * PCD. Functions in the API that are not described below are not
+ * implemented.
+ *
+ * The Gadget API provides wrapper functions for each of the function
+ * pointers defined in usb_gadget_ops. The Gadget Driver calls the
+ * wrapper function, which then calls the underlying PCD function. The
+ * following sections are named according to the wrapper functions
+ * (except for ioctl, which doesn't have a wrapper function). Within
+ * each section, the corresponding DWC_otg PCD function name is
+ * specified.
+ *
+ */
+
+/**
+ *Gets the USB Frame number of the last SOF.
+ */
+static int get_frame_number(struct usb_gadget *gadget)
+{
+	struct gadget_wrapper *d;
+
+	DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, gadget);
+
+	if (gadget == 0) {
+		return -ENODEV;
+	}
+
+	d = container_of(gadget, struct gadget_wrapper, gadget);
+	return dwc_otg_pcd_get_frame_number(d->pcd);
+}
+
+#ifdef CONFIG_USB_DWC_OTG_LPM
+static int test_lpm_enabled(struct usb_gadget *gadget)
+{
+	struct gadget_wrapper *d;
+
+	d = container_of(gadget, struct gadget_wrapper, gadget);
+
+	return dwc_otg_pcd_is_lpm_enabled(d->pcd);
+}
+#endif
+
+/**
+ * Initiates Session Request Protocol (SRP) to wakeup the host if no
+ * session is in progress. If a session is already in progress, but
+ * the device is suspended, remote wakeup signaling is started.
+ *
+ */
+static int wakeup(struct usb_gadget *gadget)
+{
+	struct gadget_wrapper *d;
+
+	DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, gadget);
+
+	if (gadget == 0) {
+		return -ENODEV;
+	} else {
+		d = container_of(gadget, struct gadget_wrapper, gadget);
+	}
+	dwc_otg_pcd_wakeup(d->pcd);
+	return 0;
+}
+
+static const struct usb_gadget_ops dwc_otg_pcd_ops = {
+	.get_frame = get_frame_number,
+	.wakeup = wakeup,
+#ifdef CONFIG_USB_DWC_OTG_LPM
+	.lpm_support = test_lpm_enabled,
+#endif
+	// current versions must always be self-powered
+};
+
+static int _setup(dwc_otg_pcd_t * pcd, uint8_t * bytes)
+{
+	int retval = -DWC_E_NOT_SUPPORTED;
+	if (gadget_wrapper->driver && gadget_wrapper->driver->setup) {
+		retval = gadget_wrapper->driver->setup(&gadget_wrapper->gadget,
+						       (struct usb_ctrlrequest
+							*)bytes);
+	}
+
+	if (retval == -ENOTSUPP) {
+		retval = -DWC_E_NOT_SUPPORTED;
+	} else if (retval < 0) {
+		retval = -DWC_E_INVALID;
+	}
+
+	return retval;
+}
+
+#ifdef DWC_EN_ISOC
+static int _isoc_complete(dwc_otg_pcd_t * pcd, void *ep_handle,
+			  void *req_handle, int proc_buf_num)
+{
+	int i, packet_count;
+	struct usb_gadget_iso_packet_descriptor *iso_packet = 0;
+	struct usb_iso_request *iso_req = req_handle;
+
+	if (proc_buf_num) {
+		iso_packet = iso_req->iso_packet_desc1;
+	} else {
+		iso_packet = iso_req->iso_packet_desc0;
+	}
+	packet_count =
+	    dwc_otg_pcd_get_iso_packet_count(pcd, ep_handle, req_handle);
+	for (i = 0; i < packet_count; ++i) {
+		int status;
+		int actual;
+		int offset;
+		dwc_otg_pcd_get_iso_packet_params(pcd, ep_handle, req_handle,
+						  i, &status, &actual, &offset);
+		switch (status) {
+		case -DWC_E_NO_DATA:
+			status = -ENODATA;
+			break;
+		default:
+			if (status) {
+				DWC_PRINTF("unknown status in isoc packet\n");
+			}
+
+		}
+		iso_packet[i].status = status;
+		iso_packet[i].offset = offset;
+		iso_packet[i].actual_length = actual;
+	}
+
+	iso_req->status = 0;
+	iso_req->process_buffer(ep_handle, iso_req);
+
+	return 0;
+}
+#endif				/* DWC_EN_ISOC */
+
+static int _complete(dwc_otg_pcd_t * pcd, void *ep_handle,
+		     void *req_handle, int32_t status, uint32_t actual)
+{
+	struct usb_request *req = (struct usb_request *)req_handle;
+
+	if (req && req->complete) {
+		switch (status) {
+		case -DWC_E_SHUTDOWN:
+			req->status = -ESHUTDOWN;
+			break;
+		case -DWC_E_RESTART:
+			req->status = -ECONNRESET;
+			break;
+		case -DWC_E_INVALID:
+			req->status = -EINVAL;
+			break;
+		case -DWC_E_TIMEOUT:
+			req->status = -ETIMEDOUT;
+			break;
+		default:
+			req->status = status;
+
+		}
+		req->actual = actual;
+		req->complete(ep_handle, req);
+	}
+
+	return 0;
+}
+
+static int _connect(dwc_otg_pcd_t * pcd, int speed)
+{
+	gadget_wrapper->gadget.speed = speed;
+	return 0;
+}
+
+static int _disconnect(dwc_otg_pcd_t * pcd)
+{
+	if (gadget_wrapper->driver && gadget_wrapper->driver->disconnect) {
+		gadget_wrapper->driver->disconnect(&gadget_wrapper->gadget);
+	}
+	return 0;
+}
+
+static int _resume(dwc_otg_pcd_t * pcd)
+{
+	if (gadget_wrapper->driver && gadget_wrapper->driver->resume) {
+		gadget_wrapper->driver->resume(&gadget_wrapper->gadget);
+	}
+
+	return 0;
+}
+
+static int _suspend(dwc_otg_pcd_t * pcd)
+{
+	if (gadget_wrapper->driver && gadget_wrapper->driver->suspend) {
+		gadget_wrapper->driver->suspend(&gadget_wrapper->gadget);
+	}
+	return 0;
+}
+
+/**
+ * This function updates the otg values in the gadget structure.
+ */
+static int _hnp_changed(dwc_otg_pcd_t * pcd)
+{
+
+	if (!gadget_wrapper->gadget.is_otg)
+		return 0;
+
+	gadget_wrapper->gadget.b_hnp_enable = get_b_hnp_enable(pcd);
+	gadget_wrapper->gadget.a_hnp_support = get_a_hnp_support(pcd);
+	gadget_wrapper->gadget.a_alt_hnp_support = get_a_alt_hnp_support(pcd);
+	return 0;
+}
+
+static int _reset(dwc_otg_pcd_t * pcd)
+{
+	return 0;
+}
+
+#ifdef DWC_UTE_CFI
+static int _cfi_setup(dwc_otg_pcd_t * pcd, void *cfi_req)
+{
+	int retval = -DWC_E_INVALID;
+	if (gadget_wrapper->driver->cfi_feature_setup) {
+		retval =
+		    gadget_wrapper->driver->cfi_feature_setup(&gadget_wrapper->
+							      gadget,
+							      (struct
+							       cfi_usb_ctrlrequest
+							       *)cfi_req);
+	}
+
+	return retval;
+}
+#endif
+
+static const struct dwc_otg_pcd_function_ops fops = {
+	.complete = _complete,
+#ifdef DWC_EN_ISOC
+	.isoc_complete = _isoc_complete,
+#endif
+	.setup = _setup,
+	.disconnect = _disconnect,
+	.connect = _connect,
+	.resume = _resume,
+	.suspend = _suspend,
+	.hnp_changed = _hnp_changed,
+	.reset = _reset,
+#ifdef DWC_UTE_CFI
+	.cfi_setup = _cfi_setup,
+#endif
+};
+
+/**
+ * This function is the top level PCD interrupt handler.
+ */
+static irqreturn_t dwc_otg_pcd_irq(int irq, void *dev)
+{
+	dwc_otg_pcd_t *pcd = dev;
+	int32_t retval = IRQ_NONE;
+
+	retval = dwc_otg_pcd_handle_intr(pcd);
+	if (retval != 0) {
+		S3C2410X_CLEAR_EINTPEND();
+	}
+	return IRQ_RETVAL(retval);
+}
+
+/**
+ * This function initialized the usb_ep structures to there default
+ * state.
+ *
+ * @param d Pointer on gadget_wrapper.
+ */
+void gadget_add_eps(struct gadget_wrapper *d)
+{
+	static const char *names[] = {
+
+		"ep0",
+		"ep1in",
+		"ep2in",
+		"ep3in",
+		"ep4in",
+		"ep5in",
+		"ep6in",
+		"ep7in",
+		"ep8in",
+		"ep9in",
+		"ep10in",
+		"ep11in",
+		"ep12in",
+		"ep13in",
+		"ep14in",
+		"ep15in",
+		"ep1out",
+		"ep2out",
+		"ep3out",
+		"ep4out",
+		"ep5out",
+		"ep6out",
+		"ep7out",
+		"ep8out",
+		"ep9out",
+		"ep10out",
+		"ep11out",
+		"ep12out",
+		"ep13out",
+		"ep14out",
+		"ep15out"
+	};
+
+	int i;
+	struct usb_ep *ep;
+
+	DWC_DEBUGPL(DBG_PCDV, "%s\n", __func__);
+
+	INIT_LIST_HEAD(&d->gadget.ep_list);
+	d->gadget.ep0 = &d->ep0;
+	d->gadget.speed = USB_SPEED_UNKNOWN;
+
+	INIT_LIST_HEAD(&d->gadget.ep0->ep_list);
+
+	/**
+	 * Initialize the EP0 structure.
+	 */
+	ep = &d->ep0;
+
+	/* Init the usb_ep structure. */
+	ep->name = names[0];
+	ep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops;
+
+	/**
+	 * @todo NGS: What should the max packet size be set to
+	 * here?  Before EP type is set?
+	 */
+	ep->maxpacket = MAX_PACKET_SIZE;
+	dwc_otg_pcd_ep_enable(d->pcd, NULL, ep);
+
+	list_add_tail(&ep->ep_list, &d->gadget.ep_list);
+
+	/**
+	 * Initialize the EP structures.
+	 */
+
+	for (i = 0; i < 15; i++) {
+		ep = &d->in_ep[i];
+
+		/* Init the usb_ep structure. */
+		ep->name = names[i + 1];
+		ep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops;
+
+		/**
+		 * @todo NGS: What should the max packet size be set to
+		 * here?  Before EP type is set?
+		 */
+		ep->maxpacket = MAX_PACKET_SIZE;
+		list_add_tail(&ep->ep_list, &d->gadget.ep_list);
+	}
+
+	for (i = 0; i < 15; i++) {
+		ep = &d->out_ep[i];
+
+		/* Init the usb_ep structure. */
+		ep->name = names[15 + i + 1];
+		ep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops;
+
+		/**
+		 * @todo NGS: What should the max packet size be set to
+		 * here?  Before EP type is set?
+		 */
+		ep->maxpacket = MAX_PACKET_SIZE;
+
+		list_add_tail(&ep->ep_list, &d->gadget.ep_list);
+	}
+
+	/* remove ep0 from the list.  There is a ep0 pointer. */
+	list_del_init(&d->ep0.ep_list);
+
+	d->ep0.maxpacket = MAX_EP0_SIZE;
+}
+
+/**
+ * This function releases the Gadget device.
+ * required by device_unregister().
+ *
+ * @todo Should this do something?	Should it free the PCD?
+ */
+static void dwc_otg_pcd_gadget_release(struct device *dev)
+{
+	DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, dev);
+}
+
+static struct gadget_wrapper *alloc_wrapper(
+#ifdef LM_INTERFACE
+	struct lm_device *_dev
+#elif  defined(PCI_INTERFACE)
+	struct pci_dev *_dev
+#elif  defined(PLATFORM_INTERFACE)
+	struct platform_device *_dev
+#endif
+	)
+{
+#ifdef LM_INTERFACE
+	dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev);
+#elif defined(PCI_INTERFACE)
+	dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev);
+#elif defined(PLATFORM_INTERFACE)
+	dwc_otg_device_t *otg_dev = platform_get_drvdata(_dev);
+#endif
+	static char pcd_name[] = "dwc_otg_pcd";
+
+	struct gadget_wrapper *d;
+	int retval;
+
+	d = dwc_alloc(sizeof(*d));
+	if (d == NULL) {
+		return NULL;
+	}
+
+	memset(d, 0, sizeof(*d));
+
+	d->gadget.name = pcd_name;
+	d->pcd = otg_dev->pcd;
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30))
+	strcpy(d->gadget.dev.bus_id, "gadget");
+#else
+	/*d->gadget.dev.bus = NULL;*/
+        d->gadget.dev.init_name = "gadget";
+#endif
+	d->gadget.dev.parent = &_dev->dev;
+	d->gadget.dev.release = dwc_otg_pcd_gadget_release;
+	d->gadget.ops = &dwc_otg_pcd_ops;
+	d->gadget.is_dualspeed = dwc_otg_pcd_is_dualspeed(otg_dev->pcd);
+	d->gadget.is_otg = dwc_otg_pcd_is_otg(otg_dev->pcd);
+
+	d->driver = 0;
+	/* Register the gadget device */
+	retval = device_register(&d->gadget.dev);
+	if (retval != 0) {
+		DWC_ERROR("device_register failed\n");
+		dwc_free(d);
+		return NULL;
+	}
+
+	return d;
+}
+
+static void free_wrapper(struct gadget_wrapper *d)
+{
+	if (d->driver) {
+		/* should have been done already by driver model core */
+		DWC_WARN("driver '%s' is still registered\n",
+			 d->driver->driver.name);
+		usb_gadget_unregister_driver(d->driver);
+	}
+
+	device_unregister(&d->gadget.dev);
+	dwc_free(d);
+}
+
+/**
+ * This function initialized the PCD portion of the driver.
+ *
+ */
+int pcd_init(
+#ifdef LM_INTERFACE
+	struct lm_device *_dev
+#elif  defined(PCI_INTERFACE)
+	struct pci_dev *_dev
+#elif  defined(PLATFORM_INTERFACE)
+	struct platform_device *_dev
+#endif
+	)
+
+{
+#ifdef LM_INTERFACE
+        dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev);
+#elif  defined(PCI_INTERFACE)
+        dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev);
+#elif  defined(PLATFORM_INTERFACE)
+        dwc_otg_device_t *otg_dev = platform_get_drvdata(_dev);
+#endif
+        int devirq;
+
+	int retval = 0;
+
+	DWC_DEBUGPL(DBG_PCDV, "%s(%p) otg_dev=%p\n", __func__, _dev, otg_dev);
+
+	otg_dev->pcd = dwc_otg_pcd_init(otg_dev->core_if);
+
+	if (!otg_dev->pcd) {
+		DWC_ERROR("dwc_otg_pcd_init failed\n");
+		return -ENOMEM;
+	}
+
+	gadget_wrapper = alloc_wrapper(_dev);
+
+	/*
+	 * Initialize EP structures
+	 */
+	gadget_add_eps(gadget_wrapper);
+
+	/*
+	 * Setup interupt handler
+	 */
+#ifdef PLATFORM_INTERFACE
+        devirq = platform_get_irq(_dev, 0);
+#else
+        devirq = _dev->irq;
+#endif
+	DWC_DEBUGPL(DBG_ANY, "registering handler for irq%d\n", devirq);
+	retval = request_irq(devirq, dwc_otg_pcd_irq,
+			     IRQF_SHARED, gadget_wrapper->gadget.name,
+			     otg_dev->pcd);
+	if (retval != 0) {
+                DWC_ERROR("request of irq%d failed\n", devirq);
+		free_wrapper(gadget_wrapper);
+		return -EBUSY;
+	}
+
+	dwc_otg_pcd_start(gadget_wrapper->pcd, &fops);
+
+	return retval;
+}
+
+/**
+ * Cleanup the PCD.
+ */
+void pcd_remove(
+#ifdef LM_INTERFACE
+	struct lm_device *_dev
+#elif  defined(PCI_INTERFACE)
+	struct pci_dev *_dev
+#elif  defined(PLATFORM_INTERFACE)
+	struct platform_device *_dev
+#endif
+	)
+{
+#ifdef LM_INTERFACE
+	dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev);
+#elif  defined(PCI_INTERFACE)
+	dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev);
+#elif  defined(PLATFORM_INTERFACE)
+	dwc_otg_device_t *otg_dev = platform_get_drvdata(_dev);
+#endif
+	dwc_otg_pcd_t *pcd = otg_dev->pcd;
+
+	DWC_DEBUGPL(DBG_PCDV, "%s(%p) otg_dev %p\n", __func__, _dev, otg_dev);
+
+	/*
+	 * Free the IRQ
+	 */
+#ifdef PLATFORM_INTERFACE
+	free_irq(platform_get_irq(_dev, 0), pcd);
+#else
+	free_irq(_dev->irq, pcd);
+#endif
+	dwc_otg_pcd_remove(otg_dev->pcd);
+	free_wrapper(gadget_wrapper);
+	otg_dev->pcd = 0;
+}
+
+/**
+ * This function registers a gadget driver with the PCD.
+ *
+ * When a driver is successfully registered, it will receive control
+ * requests including set_configuration(), which enables non-control
+ * requests.  then usb traffic follows until a disconnect is reported.
+ * then a host may connect again, or the driver might get unbound.
+ *
+ * @param driver The driver being registered
+ */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,37)
+int usb_gadget_register_driver(struct usb_gadget_driver *driver)
+#else
+int usb_gadget_probe_driver(struct usb_gadget_driver *driver,
+		int (*bind)(struct usb_gadget *))
+#endif
+{
+	int retval;
+
+	DWC_DEBUGPL(DBG_PCD, "registering gadget driver '%s'\n",
+		    driver->driver.name);
+
+	if (!driver || driver->speed == USB_SPEED_UNKNOWN ||
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,37)
+	    !driver->bind ||
+#else
+            !bind ||
+#endif
+	    !driver->unbind || !driver->disconnect || !driver->setup) {
+		DWC_DEBUGPL(DBG_PCDV, "EINVAL\n");
+		return -EINVAL;
+	}
+	if (gadget_wrapper == 0) {
+		DWC_DEBUGPL(DBG_PCDV, "ENODEV\n");
+		return -ENODEV;
+	}
+	if (gadget_wrapper->driver != 0) {
+		DWC_DEBUGPL(DBG_PCDV, "EBUSY (%p)\n", gadget_wrapper->driver);
+		return -EBUSY;
+	}
+
+	/* hook up the driver */
+	gadget_wrapper->driver = driver;
+	gadget_wrapper->gadget.dev.driver = &driver->driver;
+
+	DWC_DEBUGPL(DBG_PCD, "bind to driver %s\n", driver->driver.name);
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,37)
+	retval = driver->bind(&gadget_wrapper->gadget);
+#else
+	retval = bind(&gadget_wrapper->gadget);
+#endif
+	if (retval) {
+		DWC_ERROR("bind to driver %s --> error %d\n",
+			  driver->driver.name, retval);
+		gadget_wrapper->driver = 0;
+		gadget_wrapper->gadget.dev.driver = 0;
+		return retval;
+	}
+	DWC_DEBUGPL(DBG_ANY, "registered gadget driver '%s'\n",
+		    driver->driver.name);
+	return 0;
+}
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,37)
+EXPORT_SYMBOL(usb_gadget_register_driver);
+#else
+EXPORT_SYMBOL(usb_gadget_probe_driver);
+#endif
+
+/**
+ * This function unregisters a gadget driver
+ *
+ * @param driver The driver being unregistered
+ */
+int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
+{
+	//DWC_DEBUGPL(DBG_PCDV,"%s(%p)\n", __func__, _driver);
+
+	if (gadget_wrapper == 0) {
+		DWC_DEBUGPL(DBG_ANY, "%s Return(%d): s_pcd==0\n", __func__,
+			    -ENODEV);
+		return -ENODEV;
+	}
+	if (driver == 0 || driver != gadget_wrapper->driver) {
+		DWC_DEBUGPL(DBG_ANY, "%s Return(%d): driver?\n", __func__,
+			    -EINVAL);
+		return -EINVAL;
+	}
+
+	driver->unbind(&gadget_wrapper->gadget);
+	gadget_wrapper->driver = 0;
+
+	DWC_DEBUGPL(DBG_ANY, "unregistered driver '%s'\n", driver->driver.name);
+	return 0;
+}
+
+EXPORT_SYMBOL(usb_gadget_unregister_driver);
+
+#endif				/* DWC_HOST_ONLY */
diff --git a/drivers/usb/host/dwc_otg/dwc_otg_regs.h b/drivers/usb/host/dwc_otg/dwc_otg_regs.h
new file mode 100644
index 000000000000..e8220ad04784
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/dwc_otg_regs.h
@@ -0,0 +1,2237 @@
+/* ==========================================================================
+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_regs.h $
+ * $Revision: #76 $
+ * $Date: 2009/04/02 $
+ * $Change: 1224216 $
+ *
+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+ * otherwise expressly agreed to in writing between Synopsys and you.
+ * 
+ * The Software IS NOT an item of Licensed Software or Licensed Product under
+ * any End User Software License Agreement or Agreement for Licensed Product
+ * with Synopsys or any supplement thereto. You are permitted to use and
+ * redistribute this Software in source and binary forms, with or without
+ * modification, provided that redistributions of source code must retain this
+ * notice. You may not view, use, disclose, copy or distribute this file or
+ * any information contained herein except pursuant to this license grant from
+ * Synopsys. If you do not agree with this notice, including the disclaimer
+ * below, then you are not authorized to use the Software.
+ * 
+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ * ========================================================================== */
+
+#ifndef __DWC_OTG_REGS_H__
+#define __DWC_OTG_REGS_H__
+
+#include "dwc_otg_core_if.h"
+
+/**
+ * @file
+ *
+ * This file contains the data structures for accessing the DWC_otg core registers.
+ *
+ * The application interfaces with the HS OTG core by reading from and
+ * writing to the Control and Status Register (CSR) space through the
+ * AHB Slave interface. These registers are 32 bits wide, and the
+ * addresses are 32-bit-block aligned.
+ * CSRs are classified as follows:
+ * - Core Global Registers
+ * - Device Mode Registers
+ * - Device Global Registers
+ * - Device Endpoint Specific Registers
+ * - Host Mode Registers
+ * - Host Global Registers
+ * - Host Port CSRs
+ * - Host Channel Specific Registers
+ *
+ * Only the Core Global registers can be accessed in both Device and
+ * Host modes. When the HS OTG core is operating in one mode, either
+ * Device or Host, the application must not access registers from the
+ * other mode. When the core switches from one mode to another, the
+ * registers in the new mode of operation must be reprogrammed as they
+ * would be after a power-on reset.
+ */
+
+/****************************************************************************/
+/** DWC_otg Core registers .  
+ * The dwc_otg_core_global_regs structure defines the size
+ * and relative field offsets for the Core Global registers.
+ */
+typedef struct dwc_otg_core_global_regs {
+	/** OTG Control and Status Register.  <i>Offset: 000h</i> */
+	volatile uint32_t gotgctl;
+	/** OTG Interrupt Register.	 <i>Offset: 004h</i> */
+	volatile uint32_t gotgint;
+	/**Core AHB Configuration Register.	 <i>Offset: 008h</i> */
+	volatile uint32_t gahbcfg;
+
+#define DWC_GLBINTRMASK		0x0001
+#define DWC_DMAENABLE		0x0020
+#define DWC_NPTXEMPTYLVL_EMPTY	0x0080
+#define DWC_NPTXEMPTYLVL_HALFEMPTY	0x0000
+#define DWC_PTXEMPTYLVL_EMPTY	0x0100
+#define DWC_PTXEMPTYLVL_HALFEMPTY	0x0000
+
+	/**Core USB Configuration Register.	 <i>Offset: 00Ch</i> */
+	volatile uint32_t gusbcfg;
+	/**Core Reset Register.	 <i>Offset: 010h</i> */
+	volatile uint32_t grstctl;
+	/**Core Interrupt Register.	 <i>Offset: 014h</i> */
+	volatile uint32_t gintsts;
+	/**Core Interrupt Mask Register.  <i>Offset: 018h</i> */
+	volatile uint32_t gintmsk;
+	/**Receive Status Queue Read Register (Read Only).	<i>Offset: 01Ch</i> */
+	volatile uint32_t grxstsr;
+	/**Receive Status Queue Read & POP Register (Read Only).  <i>Offset: 020h</i>*/
+	volatile uint32_t grxstsp;
+	/**Receive FIFO Size Register.	<i>Offset: 024h</i> */
+	volatile uint32_t grxfsiz;
+	/**Non Periodic Transmit FIFO Size Register.  <i>Offset: 028h</i> */
+	volatile uint32_t gnptxfsiz;
+	/**Non Periodic Transmit FIFO/Queue Status Register (Read
+	 * Only). <i>Offset: 02Ch</i> */
+	volatile uint32_t gnptxsts;
+	/**I2C Access Register.	 <i>Offset: 030h</i> */
+	volatile uint32_t gi2cctl;
+	/**PHY Vendor Control Register.	 <i>Offset: 034h</i> */
+	volatile uint32_t gpvndctl;
+	/**General Purpose Input/Output Register.  <i>Offset: 038h</i> */
+	volatile uint32_t ggpio;
+	/**User ID Register.  <i>Offset: 03Ch</i> */
+	volatile uint32_t guid;
+	/**Synopsys ID Register (Read Only).  <i>Offset: 040h</i> */
+	volatile uint32_t gsnpsid;
+	/**User HW Config1 Register (Read Only).  <i>Offset: 044h</i> */
+	volatile uint32_t ghwcfg1;
+	/**User HW Config2 Register (Read Only).  <i>Offset: 048h</i> */
+	volatile uint32_t ghwcfg2;
+#define DWC_SLAVE_ONLY_ARCH 0
+#define DWC_EXT_DMA_ARCH 1
+#define DWC_INT_DMA_ARCH 2
+
+#define DWC_MODE_HNP_SRP_CAPABLE	0
+#define DWC_MODE_SRP_ONLY_CAPABLE	1
+#define DWC_MODE_NO_HNP_SRP_CAPABLE		2
+#define DWC_MODE_SRP_CAPABLE_DEVICE		3
+#define DWC_MODE_NO_SRP_CAPABLE_DEVICE	4
+#define DWC_MODE_SRP_CAPABLE_HOST	5
+#define DWC_MODE_NO_SRP_CAPABLE_HOST	6
+
+	/**User HW Config3 Register (Read Only).  <i>Offset: 04Ch</i> */
+	volatile uint32_t ghwcfg3;
+	/**User HW Config4 Register (Read Only).  <i>Offset: 050h</i>*/
+	volatile uint32_t ghwcfg4;
+	/** Core LPM Configuration register */
+	volatile uint32_t glpmcfg;
+	/** Reserved  <i>Offset: 058h-0FFh</i> */
+	volatile uint32_t reserved[42];
+	/** Host Periodic Transmit FIFO Size Register. <i>Offset: 100h</i> */
+	volatile uint32_t hptxfsiz;
+	/** Device Periodic Transmit FIFO#n Register if dedicated fifos are disabled, 
+		otherwise Device Transmit FIFO#n Register. 
+	 * <i>Offset: 104h + (FIFO_Number-1)*04h, 1 <= FIFO Number <= 15 (1<=n<=15).</i> */
+	volatile uint32_t dptxfsiz_dieptxf[15];
+} dwc_otg_core_global_regs_t;
+
+/**
+ * This union represents the bit fields of the Core OTG Control
+ * and Status Register (GOTGCTL).  Set the bits using the bit 
+ * fields then write the <i>d32</i> value to the register.
+ */
+typedef union gotgctl_data {
+	/** raw register data */
+	uint32_t d32;
+	/** register bits */
+	struct {
+		unsigned sesreqscs:1;
+		unsigned sesreq:1;
+		unsigned reserved2_7:6;
+		unsigned hstnegscs:1;
+		unsigned hnpreq:1;
+		unsigned hstsethnpen:1;
+		unsigned devhnpen:1;
+		unsigned reserved12_15:4;
+		unsigned conidsts:1;
+		unsigned reserved17:1;
+		unsigned asesvld:1;
+		unsigned bsesvld:1;
+		unsigned currmod:1;
+		unsigned reserved21_31:11;
+	} b;
+} gotgctl_data_t;
+
+/**
+ * This union represents the bit fields of the Core OTG Interrupt Register
+ * (GOTGINT).  Set/clear the bits using the bit fields then write the <i>d32</i>
+ * value to the register.
+ */
+typedef union gotgint_data {
+	/** raw register data */
+	uint32_t d32;
+	/** register bits */
+	struct {
+		/** Current Mode */
+		unsigned reserved0_1:2;
+
+		/** Session End Detected */
+		unsigned sesenddet:1;
+
+		unsigned reserved3_7:5;
+
+		/** Session Request Success Status Change */
+		unsigned sesreqsucstschng:1;
+		/** Host Negotiation Success Status Change */
+		unsigned hstnegsucstschng:1;
+
+		unsigned reserver10_16:7;
+
+		/** Host Negotiation Detected */
+		unsigned hstnegdet:1;
+		/** A-Device Timeout Change */
+		unsigned adevtoutchng:1;
+		/** Debounce Done */
+		unsigned debdone:1;
+
+		unsigned reserved31_20:12;
+
+	} b;
+} gotgint_data_t;
+
+/**
+ * This union represents the bit fields of the Core AHB Configuration
+ * Register (GAHBCFG).	Set/clear the bits using the bit fields then
+ * write the <i>d32</i> value to the register.
+ */
+typedef union gahbcfg_data {
+	/** raw register data */
+	uint32_t d32;
+	/** register bits */
+	struct {
+		unsigned glblintrmsk:1;
+#define DWC_GAHBCFG_GLBINT_ENABLE		1
+
+		unsigned hburstlen:4;
+#define DWC_GAHBCFG_INT_DMA_BURST_SINGLE	0
+#define DWC_GAHBCFG_INT_DMA_BURST_INCR		1
+#define DWC_GAHBCFG_INT_DMA_BURST_INCR4		3
+#define DWC_GAHBCFG_INT_DMA_BURST_INCR8		5
+#define DWC_GAHBCFG_INT_DMA_BURST_INCR16	7
+
+		unsigned dmaenable:1;
+#define DWC_GAHBCFG_DMAENABLE			1
+		unsigned reserved:1;
+		unsigned nptxfemplvl_txfemplvl:1;
+		unsigned ptxfemplvl:1;
+#define DWC_GAHBCFG_TXFEMPTYLVL_EMPTY		1
+#define DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY	0
+		unsigned reserved9_31:23;
+	} b;
+} gahbcfg_data_t;
+
+/**
+ * This union represents the bit fields of the Core USB Configuration
+ * Register (GUSBCFG).	Set the bits using the bit fields then write
+ * the <i>d32</i> value to the register.
+ */
+typedef union gusbcfg_data {
+	/** raw register data */
+	uint32_t d32;
+	/** register bits */
+	struct {
+		unsigned toutcal:3;
+		unsigned phyif:1;
+		unsigned ulpi_utmi_sel:1;
+		unsigned fsintf:1;
+		unsigned physel:1;
+		unsigned ddrsel:1;
+		unsigned srpcap:1;
+		unsigned hnpcap:1;
+		unsigned usbtrdtim:4;
+		unsigned nptxfrwnden:1;
+		unsigned phylpwrclksel:1;
+		unsigned otgutmifssel:1;
+		unsigned ulpi_fsls:1;
+		unsigned ulpi_auto_res:1;
+		unsigned ulpi_clk_sus_m:1;
+		unsigned ulpi_ext_vbus_drv:1;
+		unsigned ulpi_int_vbus_indicator:1;
+		unsigned term_sel_dl_pulse:1;
+		unsigned reserved23_25:3;
+		unsigned ic_usb_cap:1;
+		unsigned ic_traffic_pull_remove:1;
+		unsigned tx_end_delay:1;
+		unsigned reserved29_31:3;
+	} b;
+} gusbcfg_data_t;
+
+/**
+ * This union represents the bit fields of the Core LPM Configuration 
+ * Register (GLPMCFG). Set the bits using bit fields then write
+ * the <i>d32</i> value to the register.
+ */
+typedef union glpmctl_data {
+	/** raw register data */
+	uint32_t d32;
+	/** register bits */
+	struct {
+		/** LPM-Capable (LPMCap) (Device and Host)
+		 * The application uses this bit to control 
+		 * the DWC_otg core LPM capabilities.
+		 */
+		unsigned lpm_cap_en:1;
+		/** LPM response programmed by application (AppL1Res) (Device)
+		 * Handshake response to LPM token pre-programmed 
+		 * by device application software.
+		 */
+		unsigned appl_resp:1;
+		/** Host Initiated Resume Duration (HIRD) (Device and Host)
+		 * In Host mode this field indicates the value of HIRD 
+		 * to be sent in an LPM transaction.
+		 * In Device mode this field is updated with the 
+		 * Received LPM Token HIRD bmAttribute 
+		 * when an ACK/NYET/STALL response is sent 
+		 * to an LPM transaction.
+		 */
+		unsigned hird:4;
+		/** RemoteWakeEnable (bRemoteWake) (Device and Host)
+		 * In Host mode this bit indicates the value of remote 
+		 * wake up to be sent in wIndex field of LPM transaction.
+		 * In Device mode this field is updated with the 
+		 * Received LPM Token bRemoteWake bmAttribute 
+		 * when an ACK/NYET/STALL response is sent 
+		 * to an LPM transaction.
+		 */
+		unsigned rem_wkup_en:1;
+		/** Enable utmi_sleep_n (EnblSlpM) (Device and Host)
+		 * The application uses this bit to control 
+		 * the utmi_sleep_n assertion to the PHY when in L1 state.
+		 */
+		unsigned en_utmi_sleep:1;
+		/** HIRD Threshold (HIRD_Thres) (Device and Host)
+		 */
+		unsigned hird_thres:5;
+		/** LPM Response (CoreL1Res) (Device and Host)
+		 * In Host mode this bit contains handsake response to 
+		 * LPM transaction.
+		 * In Device mode the response of the core to 
+		 * LPM transaction received is reflected in these two bits.
+		 	- 0x0 : ERROR (No handshake response)
+			- 0x1 : STALL
+			- 0x2 : NYET
+			- 0x3 : ACK			
+		 */
+		unsigned lpm_resp:2;
+		/** Port Sleep Status (SlpSts) (Device and Host)
+		 * This bit is set as long as a Sleep condition 
+		 * is present on the USB bus.
+		 */
+		unsigned prt_sleep_sts:1;
+		/** Sleep State Resume OK (L1ResumeOK) (Device and Host)
+		 * Indicates that the application or host 
+		 * can start resume from Sleep state.
+		 */
+		unsigned sleep_state_resumeok:1;
+		/** LPM channel Index (LPM_Chnl_Indx) (Host)
+		 * The channel number on which the LPM transaction 
+		 * has to be applied while sending 
+		 * an LPM transaction to the local device.
+		 */
+		unsigned lpm_chan_index:4;
+		/** LPM Retry Count (LPM_Retry_Cnt) (Host)
+		 * Number host retries that would be performed
+		 * if the device response was not valid response.
+		 */
+		unsigned retry_count:3;
+		/** Send LPM Transaction (SndLPM) (Host)
+		 * When set by application software, 
+		 * an LPM transaction containing two tokens 
+		 * is sent.
+		 */
+		unsigned send_lpm:1;
+		/** LPM Retry status (LPM_RetryCnt_Sts) (Host)
+		 * Number of LPM Host Retries still remaining 
+		 * to be transmitted for the current LPM sequence
+		 */
+		unsigned retry_count_sts:3;
+		unsigned reserved28_29:2;
+		/** In host mode once this bit is set, the host
+		 * configures to drive the HSIC Idle state on the bus. 
+		 * It then waits for the  device to initiate the Connect sequence.
+		 * In device mode once this bit is set, the device waits for 
+		 * the HSIC Idle line state on the bus. Upon receving the Idle 
+		 * line state, it initiates the HSIC Connect sequence.
+		 */
+		unsigned hsic_connect:1;
+		/** This bit overrides and functionally inverts 
+		 * the if_select_hsic input port signal.
+		 */
+		unsigned inv_sel_hsic:1;
+	} b;
+} glpmcfg_data_t;
+
+/**
+ * This union represents the bit fields of the Core Reset Register
+ * (GRSTCTL).  Set/clear the bits using the bit fields then write the
+ * <i>d32</i> value to the register.
+ */
+typedef union grstctl_data {
+	/** raw register data */
+	uint32_t d32;
+	/** register bits */
+	struct {
+		/** Core Soft Reset (CSftRst) (Device and Host)
+		 *
+		 * The application can flush the control logic in the
+		 * entire core using this bit. This bit resets the
+		 * pipelines in the AHB Clock domain as well as the
+		 * PHY Clock domain.
+		 *
+		 * The state machines are reset to an IDLE state, the
+		 * control bits in the CSRs are cleared, all the
+		 * transmit FIFOs and the receive FIFO are flushed.
+		 *
+		 * The status mask bits that control the generation of
+		 * the interrupt, are cleared, to clear the
+		 * interrupt. The interrupt status bits are not
+		 * cleared, so the application can get the status of
+		 * any events that occurred in the core after it has
+		 * set this bit.
+		 *
+		 * Any transactions on the AHB are terminated as soon
+		 * as possible following the protocol. Any
+		 * transactions on the USB are terminated immediately.
+		 *
+		 * The configuration settings in the CSRs are
+		 * unchanged, so the software doesn't have to
+		 * reprogram these registers (Device
+		 * Configuration/Host Configuration/Core System
+		 * Configuration/Core PHY Configuration).
+		 *
+		 * The application can write to this bit, any time it
+		 * wants to reset the core. This is a self clearing
+		 * bit and the core clears this bit after all the
+		 * necessary logic is reset in the core, which may
+		 * take several clocks, depending on the current state
+		 * of the core.
+		 */
+		unsigned csftrst:1;
+		/** Hclk Soft Reset
+		 *
+		 * The application uses this bit to reset the control logic in
+		 * the AHB clock domain. Only AHB clock domain pipelines are
+		 * reset.
+		 */
+		unsigned hsftrst:1;
+		/** Host Frame Counter Reset (Host Only)<br>
+		 * 
+		 * The application can reset the (micro)frame number
+		 * counter inside the core, using this bit. When the
+		 * (micro)frame counter is reset, the subsequent SOF
+		 * sent out by the core, will have a (micro)frame
+		 * number of 0.
+		 */
+		unsigned hstfrm:1;
+		/** In Token Sequence Learning Queue Flush
+		 * (INTknQFlsh) (Device Only)
+		 */
+		unsigned intknqflsh:1;
+		/** RxFIFO Flush (RxFFlsh) (Device and Host)
+		 *
+		 * The application can flush the entire Receive FIFO
+		 * using this bit.	<p>The application must first
+		 * ensure that the core is not in the middle of a
+		 * transaction.	 <p>The application should write into
+		 * this bit, only after making sure that neither the
+		 * DMA engine is reading from the RxFIFO nor the MAC
+		 * is writing the data in to the FIFO.	<p>The
+		 * application should wait until the bit is cleared
+		 * before performing any other operations. This bit
+		 * will takes 8 clocks (slowest of PHY or AHB clock)
+		 * to clear.
+		 */
+		unsigned rxfflsh:1;
+		/** TxFIFO Flush (TxFFlsh) (Device and Host).  
+		 *
+		 * This bit is used to selectively flush a single or
+		 * all transmit FIFOs.	The application must first
+		 * ensure that the core is not in the middle of a
+		 * transaction.	 <p>The application should write into
+		 * this bit, only after making sure that neither the
+		 * DMA engine is writing into the TxFIFO nor the MAC
+		 * is reading the data out of the FIFO.	 <p>The
+		 * application should wait until the core clears this
+		 * bit, before performing any operations. This bit
+		 * will takes 8 clocks (slowest of PHY or AHB clock)
+		 * to clear.
+		 */
+		unsigned txfflsh:1;
+
+		/** TxFIFO Number (TxFNum) (Device and Host).
+		 * 
+		 * This is the FIFO number which needs to be flushed,
+		 * using the TxFIFO Flush bit. This field should not
+		 * be changed until the TxFIFO Flush bit is cleared by
+		 * the core.
+		 *	 - 0x0 : Non Periodic TxFIFO Flush
+		 *	 - 0x1 : Periodic TxFIFO #1 Flush in device mode
+		 *	   or Periodic TxFIFO in host mode
+		 *	 - 0x2 : Periodic TxFIFO #2 Flush in device mode.
+		 *	 - ...
+		 *	 - 0xF : Periodic TxFIFO #15 Flush in device mode
+		 *	 - 0x10: Flush all the Transmit NonPeriodic and
+		 *	   Transmit Periodic FIFOs in the core
+		 */
+		unsigned txfnum:5;
+		/** Reserved */
+		unsigned reserved11_29:19;
+		/** DMA Request Signal.	 Indicated DMA request is in
+		 * probress.  Used for debug purpose. */
+		unsigned dmareq:1;
+		/** AHB Master Idle.  Indicates the AHB Master State
+		 * Machine is in IDLE condition. */
+		unsigned ahbidle:1;
+	} b;
+} grstctl_t;
+
+/**
+ * This union represents the bit fields of the Core Interrupt Mask
+ * Register (GINTMSK).	Set/clear the bits using the bit fields then
+ * write the <i>d32</i> value to the register.
+ */
+typedef union gintmsk_data {
+	/** raw register data */
+	uint32_t d32;
+	/** register bits */
+	struct {
+		unsigned reserved0:1;
+		unsigned modemismatch:1;
+		unsigned otgintr:1;
+		unsigned sofintr:1;
+		unsigned rxstsqlvl:1;
+		unsigned nptxfempty:1;
+		unsigned ginnakeff:1;
+		unsigned goutnakeff:1;
+		unsigned reserved8:1;
+		unsigned i2cintr:1;
+		unsigned erlysuspend:1;
+		unsigned usbsuspend:1;
+		unsigned usbreset:1;
+		unsigned enumdone:1;
+		unsigned isooutdrop:1;
+		unsigned eopframe:1;
+		unsigned reserved16:1;
+		unsigned epmismatch:1;
+		unsigned inepintr:1;
+		unsigned outepintr:1;
+		unsigned incomplisoin:1;
+		unsigned incomplisoout:1;
+		unsigned reserved22_23:2;
+		unsigned portintr:1;
+		unsigned hcintr:1;
+		unsigned ptxfempty:1;
+		unsigned lpmtranrcvd:1;
+		unsigned conidstschng:1;
+		unsigned disconnect:1;
+		unsigned sessreqintr:1;
+		unsigned wkupintr:1;
+	} b;
+} gintmsk_data_t;
+/**
+ * This union represents the bit fields of the Core Interrupt Register
+ * (GINTSTS).  Set/clear the bits using the bit fields then write the
+ * <i>d32</i> value to the register.
+ */
+typedef union gintsts_data {
+	/** raw register data */
+	uint32_t d32;
+#define DWC_SOF_INTR_MASK 0x0008
+	/** register bits */
+	struct {
+#define DWC_HOST_MODE 1
+		unsigned curmode:1;
+		unsigned modemismatch:1;
+		unsigned otgintr:1;
+		unsigned sofintr:1;
+		unsigned rxstsqlvl:1;
+		unsigned nptxfempty:1;
+		unsigned ginnakeff:1;
+		unsigned goutnakeff:1;
+		unsigned reserved8:1;
+		unsigned i2cintr:1;
+		unsigned erlysuspend:1;
+		unsigned usbsuspend:1;
+		unsigned usbreset:1;
+		unsigned enumdone:1;
+		unsigned isooutdrop:1;
+		unsigned eopframe:1;
+		unsigned intokenrx:1;
+		unsigned epmismatch:1;
+		unsigned inepint:1;
+		unsigned outepintr:1;
+		unsigned incomplisoin:1;
+		unsigned incomplisoout:1;
+		unsigned reserved22_23:2;
+		unsigned portintr:1;
+		unsigned hcintr:1;
+		unsigned ptxfempty:1;
+		unsigned lpmtranrcvd:1;
+		unsigned conidstschng:1;
+		unsigned disconnect:1;
+		unsigned sessreqintr:1;
+		unsigned wkupintr:1;
+	} b;
+} gintsts_data_t;
+
+/**
+ * This union represents the bit fields in the Device Receive Status Read and 
+ * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <i>d32</i> 
+ * element then read out the bits using the <i>b</i>it elements.
+ */
+typedef union device_grxsts_data {
+	/** raw register data */
+	uint32_t d32;
+	/** register bits */
+	struct {
+		unsigned epnum:4;
+		unsigned bcnt:11;
+		unsigned dpid:2;
+
+#define DWC_STS_DATA_UPDT		0x2	// OUT Data Packet
+#define DWC_STS_XFER_COMP		0x3	// OUT Data Transfer Complete
+
+#define DWC_DSTS_GOUT_NAK		0x1	// Global OUT NAK
+#define DWC_DSTS_SETUP_COMP		0x4	// Setup Phase Complete
+#define DWC_DSTS_SETUP_UPDT 0x6	// SETUP Packet
+		unsigned pktsts:4;
+		unsigned fn:4;
+		unsigned reserved:7;
+	} b;
+} device_grxsts_data_t;
+
+/**
+ * This union represents the bit fields in the Host Receive Status Read and 
+ * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <i>d32</i> 
+ * element then read out the bits using the <i>b</i>it elements.
+ */
+typedef union host_grxsts_data {
+	/** raw register data */
+	uint32_t d32;
+	/** register bits */
+	struct {
+		unsigned chnum:4;
+		unsigned bcnt:11;
+		unsigned dpid:2;
+
+		unsigned pktsts:4;
+#define DWC_GRXSTS_PKTSTS_IN			  0x2
+#define DWC_GRXSTS_PKTSTS_IN_XFER_COMP	  0x3
+#define DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR 0x5
+#define DWC_GRXSTS_PKTSTS_CH_HALTED		  0x7
+
+		unsigned reserved:11;
+	} b;
+} host_grxsts_data_t;
+
+/**
+ * This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ,
+ * GNPTXFSIZ, DPTXFSIZn, DIEPTXFn). Read the register into the <i>d32</i> element then
+ * read out the bits using the <i>b</i>it elements.
+ */
+typedef union fifosize_data {
+	/** raw register data */
+	uint32_t d32;
+	/** register bits */
+	struct {
+		unsigned startaddr:16;
+		unsigned depth:16;
+	} b;
+} fifosize_data_t;
+
+/**
+ * This union represents the bit fields in the Non-Periodic Transmit
+ * FIFO/Queue Status Register (GNPTXSTS). Read the register into the
+ * <i>d32</i> element then read out the bits using the <i>b</i>it
+ * elements.
+ */
+typedef union gnptxsts_data {
+	/** raw register data */
+	uint32_t d32;
+	/** register bits */
+	struct {
+		unsigned nptxfspcavail:16;
+		unsigned nptxqspcavail:8;
+		/** Top of the Non-Periodic Transmit Request Queue 
+		 *	- bit 24 - Terminate (Last entry for the selected
+		 *	  channel/EP)
+		 *	- bits 26:25 - Token Type 
+		 *	  - 2'b00 - IN/OUT
+		 *	  - 2'b01 - Zero Length OUT
+		 *	  - 2'b10 - PING/Complete Split
+		 *	  - 2'b11 - Channel Halt
+		 *	- bits 30:27 - Channel/EP Number
+		 */
+		unsigned nptxqtop_terminate:1;
+		unsigned nptxqtop_token:2;
+		unsigned nptxqtop_chnep:4;
+		unsigned reserved:1;
+	} b;
+} gnptxsts_data_t;
+
+/**
+ * This union represents the bit fields in the Transmit
+ * FIFO Status Register (DTXFSTS). Read the register into the
+ * <i>d32</i> element then read out the bits using the <i>b</i>it
+ * elements.
+ */
+typedef union dtxfsts_data {
+	/** raw register data */
+	uint32_t d32;
+	/** register bits */
+	struct {
+		unsigned txfspcavail:16;
+		unsigned reserved:16;
+	} b;
+} dtxfsts_data_t;
+
+/**
+ * This union represents the bit fields in the I2C Control Register
+ * (I2CCTL). Read the register into the <i>d32</i> element then read out the
+ * bits using the <i>b</i>it elements.
+ */
+typedef union gi2cctl_data {
+	/** raw register data */
+	uint32_t d32;
+	/** register bits */
+	struct {
+		unsigned rwdata:8;
+		unsigned regaddr:8;
+		unsigned addr:7;
+		unsigned i2cen:1;
+		unsigned ack:1;
+		unsigned i2csuspctl:1;
+		unsigned i2cdevaddr:2;
+		unsigned reserved:2;
+		unsigned rw:1;
+		unsigned bsydne:1;
+	} b;
+} gi2cctl_data_t;
+
+/**
+ * This union represents the bit fields in the User HW Config1
+ * Register.  Read the register into the <i>d32</i> element then read
+ * out the bits using the <i>b</i>it elements.
+ */
+typedef union hwcfg1_data {
+	/** raw register data */
+	uint32_t d32;
+	/** register bits */
+	struct {
+		unsigned ep_dir0:2;
+		unsigned ep_dir1:2;
+		unsigned ep_dir2:2;
+		unsigned ep_dir3:2;
+		unsigned ep_dir4:2;
+		unsigned ep_dir5:2;
+		unsigned ep_dir6:2;
+		unsigned ep_dir7:2;
+		unsigned ep_dir8:2;
+		unsigned ep_dir9:2;
+		unsigned ep_dir10:2;
+		unsigned ep_dir11:2;
+		unsigned ep_dir12:2;
+		unsigned ep_dir13:2;
+		unsigned ep_dir14:2;
+		unsigned ep_dir15:2;
+	} b;
+} hwcfg1_data_t;
+
+/**
+ * This union represents the bit fields in the User HW Config2
+ * Register.  Read the register into the <i>d32</i> element then read
+ * out the bits using the <i>b</i>it elements.
+ */
+typedef union hwcfg2_data {
+	/** raw register data */
+	uint32_t d32;
+	/** register bits */
+	struct {
+		/* GHWCFG2 */
+		unsigned op_mode:3;
+#define DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG 0
+#define DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG 1
+#define DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG 2
+#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3
+#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4
+#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST 5
+#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6
+
+		unsigned architecture:2;
+		unsigned point2point:1;
+		unsigned hs_phy_type:2;
+#define DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0
+#define DWC_HWCFG2_HS_PHY_TYPE_UTMI 1
+#define DWC_HWCFG2_HS_PHY_TYPE_ULPI 2
+#define DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI 3
+
+		unsigned fs_phy_type:2;
+		unsigned num_dev_ep:4;
+		unsigned num_host_chan:4;
+		unsigned perio_ep_supported:1;
+		unsigned dynamic_fifo:1;
+		unsigned multi_proc_int:1;
+		unsigned reserved21:1;
+		unsigned nonperio_tx_q_depth:2;
+		unsigned host_perio_tx_q_depth:2;
+		unsigned dev_token_q_depth:5;
+		unsigned reserved31:1;
+	} b;
+} hwcfg2_data_t;
+
+/**
+ * This union represents the bit fields in the User HW Config3
+ * Register.  Read the register into the <i>d32</i> element then read
+ * out the bits using the <i>b</i>it elements.
+ */
+typedef union hwcfg3_data {
+	/** raw register data */
+	uint32_t d32;
+	/** register bits */
+	struct {
+		/* GHWCFG3 */
+		unsigned xfer_size_cntr_width:4;
+		unsigned packet_size_cntr_width:3;
+		unsigned otg_func:1;
+		unsigned i2c:1;
+		unsigned vendor_ctrl_if:1;
+		unsigned optional_features:1;
+		unsigned synch_reset_type:1;
+		unsigned otg_enable_ic_usb:1;
+		unsigned otg_enable_hsic:1;
+		unsigned reserved14:1;
+		unsigned otg_lpm_en:1;
+		unsigned dfifo_depth:16;
+	} b;
+} hwcfg3_data_t;
+
+/**
+ * This union represents the bit fields in the User HW Config4
+ * Register.  Read the register into the <i>d32</i> element then read
+ * out the bits using the <i>b</i>it elements.
+ */
+typedef union hwcfg4_data {
+	/** raw register data */
+	uint32_t d32;
+	/** register bits */
+	struct {
+		unsigned num_dev_perio_in_ep:4;
+		unsigned power_optimiz:1;
+		unsigned min_ahb_freq:9;
+		unsigned utmi_phy_data_width:2;
+		unsigned num_dev_mode_ctrl_ep:4;
+		unsigned iddig_filt_en:1;
+		unsigned vbus_valid_filt_en:1;
+		unsigned a_valid_filt_en:1;
+		unsigned b_valid_filt_en:1;
+		unsigned session_end_filt_en:1;
+		unsigned ded_fifo_en:1;
+		unsigned num_in_eps:4;
+		unsigned desc_dma:1;
+		unsigned desc_dma_dyn:1;
+	} b;
+} hwcfg4_data_t;
+
+////////////////////////////////////////////
+// Device Registers
+/**
+ * Device Global Registers. <i>Offsets 800h-BFFh</i>
+ *
+ * The following structures define the size and relative field offsets
+ * for the Device Mode Registers.
+ *
+ * <i>These registers are visible only in Device mode and must not be
+ * accessed in Host mode, as the results are unknown.</i>
+ */
+typedef struct dwc_otg_dev_global_regs {
+	/** Device Configuration Register. <i>Offset 800h</i> */
+	volatile uint32_t dcfg;
+	/** Device Control Register. <i>Offset: 804h</i> */
+	volatile uint32_t dctl;
+	/** Device Status Register (Read Only). <i>Offset: 808h</i> */
+	volatile uint32_t dsts;
+	/** Reserved. <i>Offset: 80Ch</i> */
+	uint32_t unused;
+	/** Device IN Endpoint Common Interrupt Mask
+	 * Register. <i>Offset: 810h</i> */
+	volatile uint32_t diepmsk;
+	/** Device OUT Endpoint Common Interrupt Mask
+	 * Register. <i>Offset: 814h</i> */
+	volatile uint32_t doepmsk;
+	/** Device All Endpoints Interrupt Register.  <i>Offset: 818h</i> */
+	volatile uint32_t daint;
+	/** Device All Endpoints Interrupt Mask Register.  <i>Offset:
+	 * 81Ch</i> */
+	volatile uint32_t daintmsk;
+	/** Device IN Token Queue Read Register-1 (Read Only).
+	 * <i>Offset: 820h</i> */
+	volatile uint32_t dtknqr1;
+	/** Device IN Token Queue Read Register-2 (Read Only).
+	 * <i>Offset: 824h</i> */
+	volatile uint32_t dtknqr2;
+	/** Device VBUS	 discharge Register.  <i>Offset: 828h</i> */
+	volatile uint32_t dvbusdis;
+	/** Device VBUS Pulse Register.	 <i>Offset: 82Ch</i> */
+	volatile uint32_t dvbuspulse;
+	/** Device IN Token Queue Read Register-3 (Read Only). /
+	 *	Device Thresholding control register (Read/Write)
+	 * <i>Offset: 830h</i> */
+	volatile uint32_t dtknqr3_dthrctl;
+	/** Device IN Token Queue Read Register-4 (Read Only). /
+	 *	Device IN EPs empty Inr. Mask Register (Read/Write)
+	 * <i>Offset: 834h</i> */
+	volatile uint32_t dtknqr4_fifoemptymsk;
+	/** Device Each Endpoint Interrupt Register (Read Only). /
+	 * <i>Offset: 838h</i> */
+	volatile uint32_t deachint;
+	/** Device Each Endpoint Interrupt mask Register (Read/Write). /
+	 * <i>Offset: 83Ch</i> */
+	volatile uint32_t deachintmsk;
+	/** Device Each In Endpoint Interrupt mask Register (Read/Write). /
+	 * <i>Offset: 840h</i> */
+	volatile uint32_t diepeachintmsk[MAX_EPS_CHANNELS];
+	/** Device Each Out Endpoint Interrupt mask Register (Read/Write). /
+	 * <i>Offset: 880h</i> */
+	volatile uint32_t doepeachintmsk[MAX_EPS_CHANNELS];
+} dwc_otg_device_global_regs_t;
+
+/**
+ * This union represents the bit fields in the Device Configuration
+ * Register.  Read the register into the <i>d32</i> member then
+ * set/clear the bits using the <i>b</i>it elements.  Write the
+ * <i>d32</i> member to the dcfg register.
+ */
+typedef union dcfg_data {
+	/** raw register data */
+	uint32_t d32;
+	/** register bits */
+	struct {
+		/** Device Speed */
+		unsigned devspd:2;
+		/** Non Zero Length Status OUT Handshake */
+		unsigned nzstsouthshk:1;
+#define DWC_DCFG_SEND_STALL 1
+
+		unsigned reserved3:1;
+		/** Device Addresses */
+		unsigned devaddr:7;
+		/** Periodic Frame Interval */
+		unsigned perfrint:2;
+#define DWC_DCFG_FRAME_INTERVAL_80 0
+#define DWC_DCFG_FRAME_INTERVAL_85 1
+#define DWC_DCFG_FRAME_INTERVAL_90 2
+#define DWC_DCFG_FRAME_INTERVAL_95 3
+
+		unsigned reserved13_17:5;
+		/** In Endpoint Mis-match count */
+		unsigned epmscnt:5;
+		/** Enable Descriptor DMA in Device mode */
+		unsigned descdma:1;
+	} b;
+} dcfg_data_t;
+
+/**
+ * This union represents the bit fields in the Device Control
+ * Register.  Read the register into the <i>d32</i> member then
+ * set/clear the bits using the <i>b</i>it elements.
+ */
+typedef union dctl_data {
+	/** raw register data */
+	uint32_t d32;
+	/** register bits */
+	struct {
+		/** Remote Wakeup */
+		unsigned rmtwkupsig:1;
+		/** Soft Disconnect */
+		unsigned sftdiscon:1;
+		/** Global Non-Periodic IN NAK Status */
+		unsigned gnpinnaksts:1;
+		/** Global OUT NAK Status */
+		unsigned goutnaksts:1;
+		/** Test Control */
+		unsigned tstctl:3;
+		/** Set Global Non-Periodic IN NAK */
+		unsigned sgnpinnak:1;
+		/** Clear Global Non-Periodic IN NAK */
+		unsigned cgnpinnak:1;
+		/** Set Global OUT NAK */
+		unsigned sgoutnak:1;
+		/** Clear Global OUT NAK */
+		unsigned cgoutnak:1;
+
+		/** Power-On Programming Done */
+		unsigned pwronprgdone:1;
+		/** Global Continue on BNA */
+		unsigned gcontbna:1;
+		/** Global Multi Count */
+		unsigned gmc:2;
+		/** Ignore Frame Number for ISOC EPs */
+		unsigned ifrmnum:1;
+		/** NAK on Babble */
+		unsigned nakonbble:1;
+
+		unsigned reserved17_31:15;
+	} b;
+} dctl_data_t;
+
+/**
+ * This union represents the bit fields in the Device Status
+ * Register.  Read the register into the <i>d32</i> member then
+ * set/clear the bits using the <i>b</i>it elements.
+ */
+typedef union dsts_data {
+	/** raw register data */
+	uint32_t d32;
+	/** register bits */
+	struct {
+		/** Suspend Status */
+		unsigned suspsts:1;
+		/** Enumerated Speed */
+		unsigned enumspd:2;
+#define DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0
+#define DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1
+#define DWC_DSTS_ENUMSPD_LS_PHY_6MHZ		   2
+#define DWC_DSTS_ENUMSPD_FS_PHY_48MHZ		   3
+		/** Erratic Error */
+		unsigned errticerr:1;
+		unsigned reserved4_7:4;
+		/** Frame or Microframe Number of the received SOF */
+		unsigned soffn:14;
+		unsigned reserved22_31:10;
+	} b;
+} dsts_data_t;
+
+/**
+ * This union represents the bit fields in the Device IN EP Interrupt
+ * Register and the Device IN EP Common Mask Register.
+ *
+ * - Read the register into the <i>d32</i> member then set/clear the
+ *	 bits using the <i>b</i>it elements.
+ */
+typedef union diepint_data {
+	/** raw register data */
+	uint32_t d32;
+	/** register bits */
+	struct {
+		/** Transfer complete mask */
+		unsigned xfercompl:1;
+		/** Endpoint disable mask */
+		unsigned epdisabled:1;
+		/** AHB Error mask */
+		unsigned ahberr:1;
+		/** TimeOUT Handshake mask (non-ISOC EPs) */
+		unsigned timeout:1;
+		/** IN Token received with TxF Empty mask */
+		unsigned intktxfemp:1;
+		/** IN Token Received with EP mismatch mask */
+		unsigned intknepmis:1;
+		/** IN Endpoint HAK Effective mask */
+		unsigned inepnakeff:1;
+		/** IN Endpoint HAK Effective mask */
+		unsigned emptyintr:1;
+
+		unsigned txfifoundrn:1;
+
+		/** BNA Interrupt mask */
+		unsigned bna:1;
+
+		unsigned reserved10_12:3;
+		/** BNA Interrupt mask */
+		unsigned nak:1;
+
+		unsigned reserved14_31:18;
+	} b;
+} diepint_data_t;
+
+/**
+ * This union represents the bit fields in the Device IN EP 
+ * Common/Dedicated Interrupt Mask Register.
+ */
+typedef union diepint_data diepmsk_data_t;
+
+/**
+ * This union represents the bit fields in the Device OUT EP Interrupt
+ * Registerand Device OUT EP Common Interrupt Mask Register.
+ *
+ * - Read the register into the <i>d32</i> member then set/clear the
+ *	 bits using the <i>b</i>it elements.
+ */
+typedef union doepint_data {
+	/** raw register data */
+	uint32_t d32;
+	/** register bits */
+	struct {
+		/** Transfer complete */
+		unsigned xfercompl:1;
+		/** Endpoint disable  */
+		unsigned epdisabled:1;
+		/** AHB Error */
+		unsigned ahberr:1;
+		/** Setup Phase Done (contorl EPs) */
+		unsigned setup:1;
+		/** OUT Token Received when Endpoint Disabled */
+		unsigned outtknepdis:1;
+
+		unsigned stsphsercvd:1;
+		/** Back-to-Back SETUP Packets Received */
+		unsigned back2backsetup:1;
+
+		unsigned reserved7:1;
+		/** OUT packet Error */
+		unsigned outpkterr:1;
+		/** BNA Interrupt */
+		unsigned bna:1;
+
+		unsigned reserved10:1;
+		/** Packet Drop Status */
+		unsigned pktdrpsts:1;
+		/** Babble Interrupt */
+		unsigned babble:1;
+		/** NAK Interrupt */
+		unsigned nak:1;
+		/** NYET Interrupt */
+		unsigned nyet:1;
+
+		unsigned reserved15_31:17;
+	} b;
+} doepint_data_t;
+
+/**
+ * This union represents the bit fields in the Device OUT EP 
+ * Common/Dedicated Interrupt Mask Register.
+ */
+typedef union doepint_data doepmsk_data_t;
+
+/**
+ * This union represents the bit fields in the Device All EP Interrupt
+ * and Mask Registers.
+ * - Read the register into the <i>d32</i> member then set/clear the
+ *	 bits using the <i>b</i>it elements.
+ */
+typedef union daint_data {
+	/** raw register data */
+	uint32_t d32;
+	/** register bits */
+	struct {
+		/** IN Endpoint bits */
+		unsigned in:16;
+		/** OUT Endpoint bits */
+		unsigned out:16;
+	} ep;
+	struct {
+		/** IN Endpoint bits */
+		unsigned inep0:1;
+		unsigned inep1:1;
+		unsigned inep2:1;
+		unsigned inep3:1;
+		unsigned inep4:1;
+		unsigned inep5:1;
+		unsigned inep6:1;
+		unsigned inep7:1;
+		unsigned inep8:1;
+		unsigned inep9:1;
+		unsigned inep10:1;
+		unsigned inep11:1;
+		unsigned inep12:1;
+		unsigned inep13:1;
+		unsigned inep14:1;
+		unsigned inep15:1;
+		/** OUT Endpoint bits */
+		unsigned outep0:1;
+		unsigned outep1:1;
+		unsigned outep2:1;
+		unsigned outep3:1;
+		unsigned outep4:1;
+		unsigned outep5:1;
+		unsigned outep6:1;
+		unsigned outep7:1;
+		unsigned outep8:1;
+		unsigned outep9:1;
+		unsigned outep10:1;
+		unsigned outep11:1;
+		unsigned outep12:1;
+		unsigned outep13:1;
+		unsigned outep14:1;
+		unsigned outep15:1;
+	} b;
+} daint_data_t;
+
+/**
+ * This union represents the bit fields in the Device IN Token Queue
+ * Read Registers.
+ * - Read the register into the <i>d32</i> member.
+ * - READ-ONLY Register
+ */
+typedef union dtknq1_data {
+	/** raw register data */
+	uint32_t d32;
+	/** register bits */
+	struct {
+		/** In Token Queue Write Pointer */
+		unsigned intknwptr:5;
+		/** Reserved */
+		unsigned reserved05_06:2;
+		/** write pointer has wrapped. */
+		unsigned wrap_bit:1;
+		/** EP Numbers of IN Tokens 0 ... 4 */
+		unsigned epnums0_5:24;
+	} b;
+} dtknq1_data_t;
+
+/**
+ * This union represents Threshold control Register
+ * - Read and write the register into the <i>d32</i> member.
+ * - READ-WRITABLE Register
+ */
+typedef union dthrctl_data {
+	/** raw register data */
+	uint32_t d32;
+	/** register bits */
+	struct {
+		/** non ISO Tx Thr. Enable */
+		unsigned non_iso_thr_en:1;
+		/** ISO Tx Thr. Enable */
+		unsigned iso_thr_en:1;
+		/** Tx Thr. Length */
+		unsigned tx_thr_len:9;
+		/** AHB Threshold ratio */
+		unsigned ahb_thr_ratio:2;
+		/** Reserved */
+		unsigned reserved13_15:3;
+		/** Rx Thr. Enable */
+		unsigned rx_thr_en:1;
+		/** Rx Thr. Length */
+		unsigned rx_thr_len:9;
+		/** Reserved */
+		unsigned reserved26_31:6;
+	} b;
+} dthrctl_data_t;
+
+/**
+ * Device Logical IN Endpoint-Specific Registers. <i>Offsets
+ * 900h-AFCh</i>
+ *
+ * There will be one set of endpoint registers per logical endpoint
+ * implemented.
+ *
+ * <i>These registers are visible only in Device mode and must not be
+ * accessed in Host mode, as the results are unknown.</i>
+ */
+typedef struct dwc_otg_dev_in_ep_regs {
+	/** Device IN Endpoint Control Register. <i>Offset:900h +
+	 * (ep_num * 20h) + 00h</i> */
+	volatile uint32_t diepctl;
+	/** Reserved. <i>Offset:900h + (ep_num * 20h) + 04h</i> */
+	uint32_t reserved04;
+	/** Device IN Endpoint Interrupt Register. <i>Offset:900h +
+	 * (ep_num * 20h) + 08h</i> */
+	volatile uint32_t diepint;
+	/** Reserved. <i>Offset:900h + (ep_num * 20h) + 0Ch</i> */
+	uint32_t reserved0C;
+	/** Device IN Endpoint Transfer Size
+	 * Register. <i>Offset:900h + (ep_num * 20h) + 10h</i> */
+	volatile uint32_t dieptsiz;
+	/** Device IN Endpoint DMA Address Register. <i>Offset:900h +
+	 * (ep_num * 20h) + 14h</i> */
+	volatile uint32_t diepdma;
+	/** Device IN Endpoint Transmit FIFO Status Register. <i>Offset:900h +
+	 * (ep_num * 20h) + 18h</i> */
+	volatile uint32_t dtxfsts;
+	/** Device IN Endpoint DMA Buffer Register. <i>Offset:900h +
+	 * (ep_num * 20h) + 1Ch</i> */
+	volatile uint32_t diepdmab;
+} dwc_otg_dev_in_ep_regs_t;
+
+/**
+ * Device Logical OUT Endpoint-Specific Registers. <i>Offsets:
+ * B00h-CFCh</i>
+ *
+ * There will be one set of endpoint registers per logical endpoint
+ * implemented.
+ *
+ * <i>These registers are visible only in Device mode and must not be
+ * accessed in Host mode, as the results are unknown.</i>
+ */
+typedef struct dwc_otg_dev_out_ep_regs {
+	/** Device OUT Endpoint Control Register. <i>Offset:B00h +
+	 * (ep_num * 20h) + 00h</i> */
+	volatile uint32_t doepctl;
+	/** Device OUT Endpoint Frame number Register.	<i>Offset:
+	 * B00h + (ep_num * 20h) + 04h</i> */
+	volatile uint32_t doepfn;
+	/** Device OUT Endpoint Interrupt Register. <i>Offset:B00h +
+	 * (ep_num * 20h) + 08h</i> */
+	volatile uint32_t doepint;
+	/** Reserved. <i>Offset:B00h + (ep_num * 20h) + 0Ch</i> */
+	uint32_t reserved0C;
+	/** Device OUT Endpoint Transfer Size Register. <i>Offset:
+	 * B00h + (ep_num * 20h) + 10h</i> */
+	volatile uint32_t doeptsiz;
+	/** Device OUT Endpoint DMA Address Register. <i>Offset:B00h
+	 * + (ep_num * 20h) + 14h</i> */
+	volatile uint32_t doepdma;
+	/** Reserved. <i>Offset:B00h + 	 * (ep_num * 20h) + 18h</i> */
+	uint32_t unused;
+	/** Device OUT Endpoint DMA Buffer Register. <i>Offset:B00h
+	 * + (ep_num * 20h) + 1Ch</i> */
+	uint32_t doepdmab;
+} dwc_otg_dev_out_ep_regs_t;
+
+/**
+ * This union represents the bit fields in the Device EP Control
+ * Register.  Read the register into the <i>d32</i> member then
+ * set/clear the bits using the <i>b</i>it elements.
+ */
+typedef union depctl_data {
+	/** raw register data */
+	uint32_t d32;
+	/** register bits */
+	struct {
+		/** Maximum Packet Size 
+		 * IN/OUT EPn
+		 * IN/OUT EP0 - 2 bits
+		 *	 2'b00: 64 Bytes
+		 *	 2'b01: 32
+		 *	 2'b10: 16
+		 *	 2'b11: 8 */
+		unsigned mps:11;
+#define DWC_DEP0CTL_MPS_64	 0
+#define DWC_DEP0CTL_MPS_32	 1
+#define DWC_DEP0CTL_MPS_16	 2
+#define DWC_DEP0CTL_MPS_8	 3
+
+		/** Next Endpoint 
+		 * IN EPn/IN EP0 
+		 * OUT EPn/OUT EP0 - reserved */
+		unsigned nextep:4;
+
+		/** USB Active Endpoint */
+		unsigned usbactep:1;
+
+		/** Endpoint DPID (INTR/Bulk IN and OUT endpoints)
+		 * This field contains the PID of the packet going to
+		 * be received or transmitted on this endpoint. The
+		 * application should program the PID of the first
+		 * packet going to be received or transmitted on this
+		 * endpoint , after the endpoint is
+		 * activated. Application use the SetD1PID and
+		 * SetD0PID fields of this register to program either
+		 * D0 or D1 PID.
+		 * 
+		 * The encoding for this field is
+		 *	 - 0: D0
+		 *	 - 1: D1
+		 */
+		unsigned dpid:1;
+
+		/** NAK Status */
+		unsigned naksts:1;
+
+		/** Endpoint Type 
+		 *	2'b00: Control
+		 *	2'b01: Isochronous
+		 *	2'b10: Bulk
+		 *	2'b11: Interrupt */
+		unsigned eptype:2;
+
+		/** Snoop Mode 
+		 * OUT EPn/OUT EP0
+		 * IN EPn/IN EP0 - reserved */
+		unsigned snp:1;
+
+		/** Stall Handshake */
+		unsigned stall:1;
+
+		/** Tx Fifo Number 
+		 * IN EPn/IN EP0
+		 * OUT EPn/OUT EP0 - reserved */
+		unsigned txfnum:4;
+
+		/** Clear NAK */
+		unsigned cnak:1;
+		/** Set NAK */
+		unsigned snak:1;
+		/** Set DATA0 PID (INTR/Bulk IN and OUT endpoints)
+		 * Writing to this field sets the Endpoint DPID (DPID)
+		 * field in this register to DATA0. Set Even
+		 * (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints)
+		 * Writing to this field sets the Even/Odd
+		 * (micro)frame (EO_FrNum) field to even (micro)
+		 * frame.
+		 */
+		unsigned setd0pid:1;
+		/** Set DATA1 PID (INTR/Bulk IN and OUT endpoints)
+		 * Writing to this field sets the Endpoint DPID (DPID)
+		 * field in this register to DATA1 Set Odd
+		 * (micro)frame (SetOddFr) (ISO IN and OUT Endpoints)
+		 * Writing to this field sets the Even/Odd
+		 * (micro)frame (EO_FrNum) field to odd (micro) frame.
+		 */
+		unsigned setd1pid:1;
+
+		/** Endpoint Disable */
+		unsigned epdis:1;
+		/** Endpoint Enable */
+		unsigned epena:1;
+	} b;
+} depctl_data_t;
+
+/**
+ * This union represents the bit fields in the Device EP Transfer
+ * Size Register.  Read the register into the <i>d32</i> member then
+ * set/clear the bits using the <i>b</i>it elements.
+ */
+typedef union deptsiz_data {
+		/** raw register data */
+	uint32_t d32;
+		/** register bits */
+	struct {
+		/** Transfer size */
+		unsigned xfersize:19;
+		/** Packet Count */
+		unsigned pktcnt:10;
+		/** Multi Count - Periodic IN endpoints */
+		unsigned mc:2;
+		unsigned reserved:1;
+	} b;
+} deptsiz_data_t;
+
+/**
+ * This union represents the bit fields in the Device EP 0 Transfer
+ * Size Register.  Read the register into the <i>d32</i> member then
+ * set/clear the bits using the <i>b</i>it elements.
+ */
+typedef union deptsiz0_data {
+		/** raw register data */
+	uint32_t d32;
+		/** register bits */
+	struct {
+		/** Transfer size */
+		unsigned xfersize:7;
+				/** Reserved */
+		unsigned reserved7_18:12;
+		/** Packet Count */
+		unsigned pktcnt:1;
+				/** Reserved */
+		unsigned reserved20_28:9;
+				/**Setup Packet Count (DOEPTSIZ0 Only) */
+		unsigned supcnt:2;
+		unsigned reserved31;
+	} b;
+} deptsiz0_data_t;
+
+/////////////////////////////////////////////////
+// DMA Descriptor Specific Structures
+//
+
+/** Buffer status definitions */
+
+#define BS_HOST_READY	0x0
+#define BS_DMA_BUSY		0x1
+#define BS_DMA_DONE		0x2
+#define BS_HOST_BUSY	0x3
+
+/** Receive/Transmit status definitions */
+
+#define RTS_SUCCESS		0x0
+#define RTS_BUFFLUSH	0x1
+#define RTS_RESERVED	0x2
+#define RTS_BUFERR		0x3
+
+/**
+ * This union represents the bit fields in the DMA Descriptor
+ * status quadlet. Read the quadlet into the <i>d32</i> member then
+ * set/clear the bits using the <i>b</i>it, <i>b_iso_out</i> and 
+ * <i>b_iso_in</i> elements.
+ */
+typedef union dev_dma_desc_sts {
+		/** raw register data */
+	uint32_t d32;
+		/** quadlet bits */
+	struct {
+		/** Received number of bytes */
+		unsigned bytes:16;
+
+		unsigned reserved16_22:7;
+		/** Multiple Transfer - only for OUT EPs */
+		unsigned mtrf:1;
+		/** Setup Packet received - only for OUT EPs */
+		unsigned sr:1;
+		/** Interrupt On Complete */
+		unsigned ioc:1;
+		/** Short Packet */
+		unsigned sp:1;
+		/** Last */
+		unsigned l:1;
+		/** Receive Status */
+		unsigned sts:2;
+		/** Buffer Status */
+		unsigned bs:2;
+	} b;
+
+#ifdef DWC_EN_ISOC
+		/** iso out quadlet bits */
+	struct {
+		/** Received number of bytes */
+		unsigned rxbytes:11;
+
+		unsigned reserved11:1;
+		/** Frame Number */
+		unsigned framenum:11;
+		/** Received ISO Data PID */
+		unsigned pid:2;
+		/** Interrupt On Complete */
+		unsigned ioc:1;
+		/** Short Packet */
+		unsigned sp:1;
+		/** Last */
+		unsigned l:1;
+		/** Receive Status */
+		unsigned rxsts:2;
+		/** Buffer Status */
+		unsigned bs:2;
+	} b_iso_out;
+
+		/** iso in quadlet bits */
+	struct {
+		/** Transmited number of bytes */
+		unsigned txbytes:12;
+		/** Frame Number */
+		unsigned framenum:11;
+		/** Transmited ISO Data PID */
+		unsigned pid:2;
+		/** Interrupt On Complete */
+		unsigned ioc:1;
+		/** Short Packet */
+		unsigned sp:1;
+		/** Last */
+		unsigned l:1;
+		/** Transmit Status */
+		unsigned txsts:2;
+		/** Buffer Status */
+		unsigned bs:2;
+	} b_iso_in;
+#endif				/* DWC_EN_ISOC */
+} dev_dma_desc_sts_t;
+
+/** 
+ * DMA Descriptor structure 
+ *
+ * DMA Descriptor structure contains two quadlets:
+ * Status quadlet and Data buffer pointer.
+ */
+typedef struct dwc_otg_dev_dma_desc {
+	/** DMA Descriptor status quadlet */
+	dev_dma_desc_sts_t status;
+	/** DMA Descriptor data buffer pointer */
+	uint32_t buf;
+} dwc_otg_dev_dma_desc_t;
+
+/**
+ * The dwc_otg_dev_if structure contains information needed to manage
+ * the DWC_otg controller acting in device mode. It represents the
+ * programming view of the device-specific aspects of the controller.
+ */
+typedef struct dwc_otg_dev_if {
+	/** Pointer to device Global registers.
+	 * Device Global Registers starting at offset 800h
+	 */
+	dwc_otg_device_global_regs_t *dev_global_regs;
+#define DWC_DEV_GLOBAL_REG_OFFSET 0x800
+
+	/** 
+	 * Device Logical IN Endpoint-Specific Registers 900h-AFCh 
+	 */
+	dwc_otg_dev_in_ep_regs_t *in_ep_regs[MAX_EPS_CHANNELS];
+#define DWC_DEV_IN_EP_REG_OFFSET 0x900
+#define DWC_EP_REG_OFFSET 0x20
+
+	/** Device Logical OUT Endpoint-Specific Registers B00h-CFCh */
+	dwc_otg_dev_out_ep_regs_t *out_ep_regs[MAX_EPS_CHANNELS];
+#define DWC_DEV_OUT_EP_REG_OFFSET 0xB00
+
+	/* Device configuration information */
+	uint8_t speed;				 /**< Device Speed	0: Unknown, 1: LS, 2:FS, 3: HS */
+	uint8_t num_in_eps;		 /**< Number # of Tx EP range: 0-15 exept ep0 */
+	uint8_t num_out_eps;		 /**< Number # of Rx EP range: 0-15 exept ep 0*/
+
+	/** Size of periodic FIFOs (Bytes) */
+	uint16_t perio_tx_fifo_size[MAX_PERIO_FIFOS];
+
+	/** Size of Tx FIFOs (Bytes) */
+	uint16_t tx_fifo_size[MAX_TX_FIFOS];
+
+	/** Thresholding enable flags and length varaiables **/
+	uint16_t rx_thr_en;
+	uint16_t iso_tx_thr_en;
+	uint16_t non_iso_tx_thr_en;
+
+	uint16_t rx_thr_length;
+	uint16_t tx_thr_length;
+
+	/**
+	 * Pointers to the DMA Descriptors for EP0 Control
+	 * transfers (virtual and physical)
+	 */
+
+	/** 2 descriptors for SETUP packets */
+	dwc_dma_t dma_setup_desc_addr[2];
+	dwc_otg_dev_dma_desc_t *setup_desc_addr[2];
+
+	/** Pointer to Descriptor with latest SETUP packet */
+	dwc_otg_dev_dma_desc_t *psetup;
+
+	/** Index of current SETUP handler descriptor */
+	uint32_t setup_desc_index;
+
+	/** Descriptor for Data In or Status In phases */
+	dwc_dma_t dma_in_desc_addr;
+	dwc_otg_dev_dma_desc_t *in_desc_addr;
+
+	/** Descriptor for Data Out or Status Out phases */
+	dwc_dma_t dma_out_desc_addr;
+	dwc_otg_dev_dma_desc_t *out_desc_addr;
+
+	/** Setup Packet Detected - if set clear NAK when queueing */
+	uint32_t spd;
+
+} dwc_otg_dev_if_t;
+
+/////////////////////////////////////////////////
+// Host Mode Register Structures
+//
+/**
+ * The Host Global Registers structure defines the size and relative
+ * field offsets for the Host Mode Global Registers.  Host Global
+ * Registers offsets 400h-7FFh.
+*/
+typedef struct dwc_otg_host_global_regs {
+	/** Host Configuration Register.   <i>Offset: 400h</i> */
+	volatile uint32_t hcfg;
+	/** Host Frame Interval Register.	<i>Offset: 404h</i> */
+	volatile uint32_t hfir;
+	/** Host Frame Number / Frame Remaining Register. <i>Offset: 408h</i> */
+	volatile uint32_t hfnum;
+	/** Reserved.	<i>Offset: 40Ch</i> */
+	uint32_t reserved40C;
+	/** Host Periodic Transmit FIFO/ Queue Status Register. <i>Offset: 410h</i> */
+	volatile uint32_t hptxsts;
+	/** Host All Channels Interrupt Register. <i>Offset: 414h</i> */
+	volatile uint32_t haint;
+	/** Host All Channels Interrupt Mask Register. <i>Offset: 418h</i> */
+	volatile uint32_t haintmsk;
+	/** Host Frame List Base Address Register . <i>Offset: 41Ch</i> */
+	volatile uint32_t hflbaddr;
+} dwc_otg_host_global_regs_t;
+
+
+/**
+ * This union represents the bit fields in the Host Configuration Register.
+ * Read the register into the <i>d32</i> member then set/clear the bits using
+ * the <i>b</i>it elements. Write the <i>d32</i> member to the hcfg register.
+ */
+typedef union hcfg_data
+{
+	/** raw register data */
+	uint32_t d32;
+
+	/** register bits */
+	struct 
+	{
+		/** FS/LS Phy Clock Select */
+		unsigned fslspclksel:2;
+#define DWC_HCFG_30_60_MHZ 0
+#define DWC_HCFG_48_MHZ	   1
+#define DWC_HCFG_6_MHZ	   2
+
+		/** FS/LS Only Support */
+		unsigned fslssupp:1;
+		unsigned reserved3_22 : 20;
+		/** Enable Scatter/gather DMA in Host mode */
+		unsigned descdma : 1;
+		/** Frame List Entries */
+		unsigned frlisten: 2;
+		/** Enable Periodic Scheduling */
+		unsigned perschedena: 1;
+		/** Periodic Scheduling Enabled Status */
+		unsigned perschedstat: 1;
+	} b;
+} hcfg_data_t;
+
+/**
+ * This union represents the bit fields in the Host Frame Remaing/Number
+ * Register.  
+ */
+typedef union hfir_data {
+	/** raw register data */
+	uint32_t d32;
+
+	/** register bits */
+	struct {
+		unsigned frint:16;
+		unsigned reserved:16;
+	} b;
+} hfir_data_t;
+
+/**
+ * This union represents the bit fields in the Host Frame Remaing/Number
+ * Register.  
+ */
+typedef union hfnum_data {
+	/** raw register data */
+	uint32_t d32;
+
+	/** register bits */
+	struct {
+		unsigned frnum:16;
+#define DWC_HFNUM_MAX_FRNUM 0x3FFF
+		unsigned frrem:16;
+	} b;
+} hfnum_data_t;
+
+typedef union hptxsts_data {
+	/** raw register data */
+	uint32_t d32;
+
+	/** register bits */
+	struct {
+		unsigned ptxfspcavail:16;
+		unsigned ptxqspcavail:8;
+		/** Top of the Periodic Transmit Request Queue
+		 *	- bit 24 - Terminate (last entry for the selected channel)
+		 *	- bits 26:25 - Token Type
+		 *	  - 2'b00 - Zero length
+		 *	  - 2'b01 - Ping
+		 *	  - 2'b10 - Disable
+		 *	- bits 30:27 - Channel Number
+		 *	- bit 31 - Odd/even microframe
+		 */
+		unsigned ptxqtop_terminate:1;
+		unsigned ptxqtop_token:2;
+		unsigned ptxqtop_chnum:4;
+		unsigned ptxqtop_odd:1;
+	} b;
+} hptxsts_data_t;
+
+/**
+ * This union represents the bit fields in the Host Port Control and Status
+ * Register. Read the register into the <i>d32</i> member then set/clear the
+ * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
+ * hprt0 register.
+ */
+typedef union hprt0_data {
+	/** raw register data */
+	uint32_t d32;
+	/** register bits */
+	struct {
+		unsigned prtconnsts:1;
+		unsigned prtconndet:1;
+		unsigned prtena:1;
+		unsigned prtenchng:1;
+		unsigned prtovrcurract:1;
+		unsigned prtovrcurrchng:1;
+		unsigned prtres:1;
+		unsigned prtsusp:1;
+		unsigned prtrst:1;
+		unsigned reserved9:1;
+		unsigned prtlnsts:2;
+		unsigned prtpwr:1;
+		unsigned prttstctl:4;
+		unsigned prtspd:2;
+#define DWC_HPRT0_PRTSPD_HIGH_SPEED 0
+#define DWC_HPRT0_PRTSPD_FULL_SPEED 1
+#define DWC_HPRT0_PRTSPD_LOW_SPEED	2
+		unsigned reserved19_31:13;
+	} b;
+} hprt0_data_t;
+
+/**
+ * This union represents the bit fields in the Host All Interrupt 
+ * Register.  
+ */
+typedef union haint_data {
+	/** raw register data */
+	uint32_t d32;
+	/** register bits */
+	struct {
+		unsigned ch0:1;
+		unsigned ch1:1;
+		unsigned ch2:1;
+		unsigned ch3:1;
+		unsigned ch4:1;
+		unsigned ch5:1;
+		unsigned ch6:1;
+		unsigned ch7:1;
+		unsigned ch8:1;
+		unsigned ch9:1;
+		unsigned ch10:1;
+		unsigned ch11:1;
+		unsigned ch12:1;
+		unsigned ch13:1;
+		unsigned ch14:1;
+		unsigned ch15:1;
+		unsigned reserved:16;
+	} b;
+
+	struct {
+		unsigned chint:16;
+		unsigned reserved:16;
+	} b2;
+} haint_data_t;
+
+/**
+ * This union represents the bit fields in the Host All Interrupt 
+ * Register.  
+ */
+typedef union haintmsk_data {
+	/** raw register data */
+	uint32_t d32;
+	/** register bits */
+	struct {
+		unsigned ch0:1;
+		unsigned ch1:1;
+		unsigned ch2:1;
+		unsigned ch3:1;
+		unsigned ch4:1;
+		unsigned ch5:1;
+		unsigned ch6:1;
+		unsigned ch7:1;
+		unsigned ch8:1;
+		unsigned ch9:1;
+		unsigned ch10:1;
+		unsigned ch11:1;
+		unsigned ch12:1;
+		unsigned ch13:1;
+		unsigned ch14:1;
+		unsigned ch15:1;
+		unsigned reserved:16;
+	} b;
+
+	struct {
+		unsigned chint:16;
+		unsigned reserved:16;
+	} b2;
+} haintmsk_data_t;
+
+/** 
+ * Host Channel Specific Registers. <i>500h-5FCh</i>
+ */
+typedef struct dwc_otg_hc_regs 
+{
+	/** Host Channel 0 Characteristic Register. <i>Offset: 500h + (chan_num * 20h) + 00h</i> */
+	volatile uint32_t hcchar;
+	/** Host Channel 0 Split Control Register. <i>Offset: 500h + (chan_num * 20h) + 04h</i> */
+	volatile uint32_t hcsplt;
+	/** Host Channel 0 Interrupt Register. <i>Offset: 500h + (chan_num * 20h) + 08h</i> */
+	volatile uint32_t hcint;
+	/** Host Channel 0 Interrupt Mask Register. <i>Offset: 500h + (chan_num * 20h) + 0Ch</i> */
+	volatile uint32_t hcintmsk;
+	/** Host Channel 0 Transfer Size Register. <i>Offset: 500h + (chan_num * 20h) + 10h</i> */
+	volatile uint32_t hctsiz;
+	/** Host Channel 0 DMA Address Register. <i>Offset: 500h + (chan_num * 20h) + 14h</i> */
+	volatile uint32_t hcdma;
+	volatile uint32_t reserved;
+	/** Host Channel 0 DMA Buffer Address Register. <i>Offset: 500h + (chan_num * 20h) + 1Ch</i> */
+	volatile uint32_t hcdmab;
+} dwc_otg_hc_regs_t;
+
+/**
+ * This union represents the bit fields in the Host Channel Characteristics
+ * Register. Read the register into the <i>d32</i> member then set/clear the
+ * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
+ * hcchar register.
+ */
+typedef union hcchar_data {
+	/** raw register data */
+	uint32_t d32;
+
+	/** register bits */
+	struct {
+		/** Maximum packet size in bytes */
+		unsigned mps:11;
+
+		/** Endpoint number */
+		unsigned epnum:4;
+
+		/** 0: OUT, 1: IN */
+		unsigned epdir:1;
+
+		unsigned reserved:1;
+
+		/** 0: Full/high speed device, 1: Low speed device */
+		unsigned lspddev:1;
+
+		/** 0: Control, 1: Isoc, 2: Bulk, 3: Intr */
+		unsigned eptype:2;
+
+		/** Packets per frame for periodic transfers. 0 is reserved. */
+		unsigned multicnt:2;
+
+		/** Device address */
+		unsigned devaddr:7;
+
+		/**
+		 * Frame to transmit periodic transaction.
+		 * 0: even, 1: odd
+		 */
+		unsigned oddfrm:1;
+
+		/** Channel disable */
+		unsigned chdis:1;
+
+		/** Channel enable */
+		unsigned chen:1;
+	} b;
+} hcchar_data_t;
+
+typedef union hcsplt_data {
+	/** raw register data */
+	uint32_t d32;
+
+	/** register bits */
+	struct {
+		/** Port Address */
+		unsigned prtaddr:7;
+
+		/** Hub Address */
+		unsigned hubaddr:7;
+
+		/** Transaction Position */
+		unsigned xactpos:2;
+#define DWC_HCSPLIT_XACTPOS_MID 0
+#define DWC_HCSPLIT_XACTPOS_END 1
+#define DWC_HCSPLIT_XACTPOS_BEGIN 2
+#define DWC_HCSPLIT_XACTPOS_ALL 3
+
+		/** Do Complete Split */
+		unsigned compsplt:1;
+
+		/** Reserved */
+		unsigned reserved:14;
+
+		/** Split Enble */
+		unsigned spltena:1;
+	} b;
+} hcsplt_data_t;
+
+/**
+ * This union represents the bit fields in the Host All Interrupt 
+ * Register.  
+ */
+typedef union hcint_data
+{
+	/** raw register data */
+	uint32_t d32;
+	/** register bits */
+	struct 
+	{
+		/** Transfer Complete */
+		unsigned xfercomp:1;
+		/** Channel Halted */
+		unsigned chhltd:1;
+		/** AHB Error */
+		unsigned ahberr:1;
+		/** STALL Response Received */
+		unsigned stall:1;
+		/** NAK Response Received */
+		unsigned nak:1;
+		/** ACK Response Received */
+		unsigned ack:1;
+		/** NYET Response Received */
+		unsigned nyet:1;
+		/** Transaction Err */
+		unsigned xacterr:1;
+		/** Babble Error */
+		unsigned bblerr:1;
+		/** Frame Overrun */
+		unsigned frmovrun:1;
+		/** Data Toggle Error */
+		unsigned datatglerr:1;
+		/** Buffer Not Available (only for DDMA mode) */
+		unsigned bna : 1;
+		/** Exessive transaction error (only for DDMA mode) */
+		unsigned xcs_xact : 1;
+		/** Frame List Rollover interrupt */
+		unsigned frm_list_roll : 1;
+		/** Reserved */
+		unsigned reserved14_31 : 18;
+	} b;
+} hcint_data_t;
+
+/**
+ * This union represents the bit fields in the Host Channel Interrupt Mask
+ * Register. Read the register into the <i>d32</i> member then set/clear the
+ * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
+ * hcintmsk register.
+ */
+typedef union hcintmsk_data
+{
+	/** raw register data */
+	uint32_t d32;
+
+	/** register bits */
+	struct 
+	{
+		unsigned xfercompl : 1;
+		unsigned chhltd : 1;
+		unsigned ahberr : 1;
+		unsigned stall : 1;
+		unsigned nak : 1;
+		unsigned ack : 1;
+		unsigned nyet : 1;
+		unsigned xacterr : 1;
+		unsigned bblerr : 1;
+		unsigned frmovrun : 1;
+		unsigned datatglerr : 1;
+		unsigned bna : 1;
+		unsigned xcs_xact : 1;
+		unsigned frm_list_roll : 1;
+		unsigned reserved14_31 : 18;
+	} b;
+} hcintmsk_data_t;
+
+/**
+ * This union represents the bit fields in the Host Channel Transfer Size
+ * Register. Read the register into the <i>d32</i> member then set/clear the
+ * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
+ * hcchar register.
+ */
+
+typedef union hctsiz_data
+{
+	/** raw register data */
+	uint32_t d32;
+
+	/** register bits */
+	struct 
+	{
+		/** Total transfer size in bytes */
+		unsigned xfersize:19;
+
+		/** Data packets to transfer */
+		unsigned pktcnt:10;
+
+		/**
+		 * Packet ID for next data packet
+		 * 0: DATA0
+		 * 1: DATA2
+		 * 2: DATA1
+		 * 3: MDATA (non-Control), SETUP (Control)
+		 */
+		unsigned pid:2;
+#define DWC_HCTSIZ_DATA0 0
+#define DWC_HCTSIZ_DATA1 2
+#define DWC_HCTSIZ_DATA2 1
+#define DWC_HCTSIZ_MDATA 3
+#define DWC_HCTSIZ_SETUP 3
+
+		/** Do PING protocol when 1 */
+		unsigned dopng:1;
+	} b;
+	
+	/** register bits */
+	struct 
+	{
+		/** Scheduling information */
+		unsigned schinfo : 8;
+		
+		/** Number of transfer descriptors. 
+		 * Max value:
+		 * 64 in general, 
+		 * 256 only for HS isochronous endpoint.
+		 */
+		unsigned ntd : 8;
+
+		/** Data packets to transfer */
+		unsigned reserved16_28 : 13;
+
+		/**
+		 * Packet ID for next data packet
+		 * 0: DATA0
+		 * 1: DATA2
+		 * 2: DATA1
+		 * 3: MDATA (non-Control)
+		 */
+		unsigned pid : 2;
+
+		/** Do PING protocol when 1 */
+		unsigned dopng : 1;
+	} b_ddma;
+} hctsiz_data_t;
+
+
+/**
+ * This union represents the bit fields in the Host DMA Address  
+ * Register used in Descriptor DMA mode.
+ */
+typedef union hcdma_data
+{
+	/** raw register data */
+	uint32_t d32;
+	/** register bits */
+	struct 
+	{
+		unsigned reserved0_2 : 3;
+		/** Current Transfer Descriptor. Not used for ISOC */
+		unsigned ctd : 8;
+		/** Start Address of Descriptor List */
+		unsigned dma_addr : 21;
+	} b;
+} hcdma_data_t;
+
+/**
+ * This union represents the bit fields in the DMA Descriptor
+ * status quadlet for host mode. Read the quadlet into the <i>d32</i> member then
+ * set/clear the bits using the <i>b</i>it elements.
+ */
+typedef union host_dma_desc_sts
+{
+	/** raw register data */
+	uint32_t d32;
+	/** quadlet bits */
+
+	/* for non-isochronous  */
+	struct {
+		/** Number of bytes */
+		unsigned n_bytes : 17;
+		/** QTD offset to jump when Short Packet received - only for IN EPs */
+		unsigned qtd_offset : 6;
+		/** 
+		 * Set to request the core to jump to alternate QTD if 
+		 * Short Packet received - only for IN EPs 
+		 */
+		unsigned a_qtd : 1;
+		 /** 
+		  * Setup Packet bit. When set indicates that buffer contains
+		  * setup packet. 
+		  */
+		unsigned sup : 1;
+		/** Interrupt On Complete */
+		unsigned ioc : 1;
+		/** End of List */
+		unsigned eol : 1;
+		unsigned reserved27 : 1;
+		/** Rx/Tx Status */
+		unsigned sts : 2;
+	#define DMA_DESC_STS_PKTERR	1
+		unsigned reserved30 : 1;
+		/** Active Bit */
+		unsigned a : 1;
+	} b;
+	/* for isochronous */
+	struct {
+		/** Number of bytes */
+		unsigned n_bytes : 12;
+		unsigned reserved12_24 : 13;
+		/** Interrupt On Complete */
+		unsigned ioc : 1;
+		unsigned reserved26_27 : 2;
+		/** Rx/Tx Status */
+		unsigned sts : 2;
+		unsigned reserved30 : 1;
+		/** Active Bit */
+		unsigned a : 1;
+	} b_isoc;
+} host_dma_desc_sts_t;
+
+#define	MAX_DMA_DESC_SIZE		131071
+#define MAX_DMA_DESC_NUM_GENERIC	64
+#define MAX_DMA_DESC_NUM_HS_ISOC	256
+#define MAX_FRLIST_EN_NUM		64
+/** 
+ * Host-mode DMA Descriptor structure 
+ *
+ * DMA Descriptor structure contains two quadlets:
+ * Status quadlet and Data buffer pointer.
+ */
+typedef struct dwc_otg_host_dma_desc
+{
+	/** DMA Descriptor status quadlet */
+	host_dma_desc_sts_t	status;
+	/** DMA Descriptor data buffer pointer */
+ 	uint32_t	buf;
+} dwc_otg_host_dma_desc_t;
+
+/** OTG Host Interface Structure.
+ *
+ * The OTG Host Interface Structure structure contains information
+ * needed to manage the DWC_otg controller acting in host mode. It
+ * represents the programming view of the host-specific aspects of the
+ * controller.
+ */
+typedef struct dwc_otg_host_if {
+	/** Host Global Registers starting at offset 400h.*/
+	dwc_otg_host_global_regs_t *host_global_regs;
+#define DWC_OTG_HOST_GLOBAL_REG_OFFSET 0x400
+
+	/** Host Port 0 Control and Status Register */
+	volatile uint32_t *hprt0;
+#define DWC_OTG_HOST_PORT_REGS_OFFSET 0x440
+
+	/** Host Channel Specific Registers at offsets 500h-5FCh. */
+	dwc_otg_hc_regs_t *hc_regs[MAX_EPS_CHANNELS];
+#define DWC_OTG_HOST_CHAN_REGS_OFFSET 0x500
+#define DWC_OTG_CHAN_REGS_OFFSET 0x20
+
+	/* Host configuration information */
+	/** Number of Host Channels (range: 1-16) */
+	uint8_t num_host_channels;
+	/** Periodic EPs supported (0: no, 1: yes) */
+	uint8_t perio_eps_supported;
+	/** Periodic Tx FIFO Size (Only 1 host periodic Tx FIFO) */
+	uint16_t perio_tx_fifo_size;
+
+} dwc_otg_host_if_t;
+
+/**
+ * This union represents the bit fields in the Power and Clock Gating Control
+ * Register. Read the register into the <i>d32</i> member then set/clear the
+ * bits using the <i>b</i>it elements. 
+ */
+typedef union pcgcctl_data {
+	/** raw register data */
+	uint32_t d32;
+
+	/** register bits */
+	struct {
+		/** Stop Pclk */
+		unsigned stoppclk:1;
+		/** Gate Hclk */
+		unsigned gatehclk:1;
+		/** Power Clamp */
+		unsigned pwrclmp:1;
+		/** Reset Power Down Modules */
+		unsigned rstpdwnmodule:1;
+		/** PHY Suspended */
+		unsigned physuspended:1;
+		/** Enable Sleep Clock Gating (Enbl_L1Gating) */
+		unsigned enbl_sleep_gating:1;
+		/** PHY In Sleep (PhySleep) */
+		unsigned phy_in_sleep:1;
+		/** Deep Sleep*/
+		unsigned deep_sleep:1;
+
+		unsigned reserved31_8:24;
+	} b;
+} pcgcctl_data_t;
+
+#endif
diff --git a/drivers/usb/host/dwc_otg/test/Makefile b/drivers/usb/host/dwc_otg/test/Makefile
new file mode 100644
index 000000000000..fc453759dea3
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/test/Makefile
@@ -0,0 +1,16 @@
+
+PERL=/usr/bin/perl
+PL_TESTS=test_sysfs.pl test_mod_param.pl
+
+.PHONY : test
+test : perl_tests
+
+perl_tests :
+	@echo
+	@echo Running perl tests
+	@for test in $(PL_TESTS); do \
+	  if $(PERL) ./$$test ; then \
+	    echo "=======> $$test, PASSED" ; \
+	  else echo "=======> $$test, FAILED" ; \
+	  fi \
+	done
diff --git a/drivers/usb/host/dwc_otg/test/dwc_otg_test.pm b/drivers/usb/host/dwc_otg/test/dwc_otg_test.pm
new file mode 100644
index 000000000000..233b04ad870c
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/test/dwc_otg_test.pm
@@ -0,0 +1,337 @@
+package dwc_otg_test;
+
+use strict;
+use Exporter ();
+
+use vars qw(@ISA @EXPORT
+$sysfsdir $paramdir $errors $params 
+);
+
+@ISA = qw(Exporter);
+
+#
+# Globals
+#
+$sysfsdir = "/sys/devices/lm0";
+$paramdir = "/sys/module/dwc_otg";
+$errors = 0;
+
+$params = [
+	   {
+	    NAME => "otg_cap",
+	    DEFAULT => 0,
+	    ENUM => [],
+	    LOW => 0,
+	    HIGH => 2
+	   },
+	   {
+	    NAME => "dma_enable",
+	    DEFAULT => 0,
+	    ENUM => [],
+	    LOW => 0,
+	    HIGH => 1
+	   },
+	   { 
+	    NAME => "dma_burst_size",
+	    DEFAULT => 32,
+	    ENUM => [1, 4, 8, 16, 32, 64, 128, 256],
+	    LOW => 1,
+	    HIGH => 256
+	   },
+	   { 
+	    NAME => "host_speed",
+	    DEFAULT => 0,
+	    ENUM => [],
+	    LOW => 0,
+	    HIGH => 1
+	   },
+	   { 
+	    NAME => "host_support_fs_ls_low_power",
+	    DEFAULT => 0,
+	    ENUM => [],
+	    LOW => 0,
+	    HIGH => 1
+	   },
+	   { 
+	    NAME => "host_ls_low_power_phy_clk",
+	    DEFAULT => 0,
+	    ENUM => [],
+	    LOW => 0,
+	    HIGH => 1
+	   },
+	   { 
+	    NAME => "dev_speed",
+	    DEFAULT => 0,
+	    ENUM => [],
+	    LOW => 0,
+	    HIGH => 1
+	   },
+	   { 
+	    NAME => "enable_dynamic_fifo",
+	    DEFAULT => 1,
+	    ENUM => [],
+	    LOW => 0,
+	    HIGH => 1
+	   },
+	   { 
+	    NAME => "data_fifo_size",
+	    DEFAULT => 8192,
+	    ENUM => [],
+	    LOW => 32,
+	    HIGH => 32768
+	   },
+	   { 
+	    NAME => "dev_rx_fifo_size",
+	    DEFAULT => 1064,
+	    ENUM => [],
+	    LOW => 16,
+	    HIGH => 32768
+	   },
+	   { 
+	    NAME => "dev_nperio_tx_fifo_size",
+	    DEFAULT => 1024,
+	    ENUM => [],
+	    LOW => 16,
+	    HIGH => 32768
+	   },
+	   { 
+	    NAME => "dev_perio_tx_fifo_size_1",
+	    DEFAULT => 256,
+	    ENUM => [],
+	    LOW => 4,
+	    HIGH => 768
+	   },
+	   { 
+	    NAME => "dev_perio_tx_fifo_size_2",
+	    DEFAULT => 256,
+	    ENUM => [],
+	    LOW => 4,
+	    HIGH => 768
+	   },
+	   { 
+	    NAME => "dev_perio_tx_fifo_size_3",
+	    DEFAULT => 256,
+	    ENUM => [],
+	    LOW => 4,
+	    HIGH => 768
+	   },
+	   { 
+	    NAME => "dev_perio_tx_fifo_size_4",
+	    DEFAULT => 256,
+	    ENUM => [],
+	    LOW => 4,
+	    HIGH => 768
+	   },
+	   { 
+	    NAME => "dev_perio_tx_fifo_size_5",
+	    DEFAULT => 256,
+	    ENUM => [],
+	    LOW => 4,
+	    HIGH => 768
+	   },
+	   { 
+	    NAME => "dev_perio_tx_fifo_size_6",
+	    DEFAULT => 256,
+	    ENUM => [],
+	    LOW => 4,
+	    HIGH => 768
+	   },
+	   { 
+	    NAME => "dev_perio_tx_fifo_size_7",
+	    DEFAULT => 256,
+	    ENUM => [],
+	    LOW => 4,
+	    HIGH => 768
+	   },
+	   { 
+	    NAME => "dev_perio_tx_fifo_size_8",
+	    DEFAULT => 256,
+	    ENUM => [],
+	    LOW => 4,
+	    HIGH => 768
+	   },
+	   { 
+	    NAME => "dev_perio_tx_fifo_size_9",
+	    DEFAULT => 256,
+	    ENUM => [],
+	    LOW => 4,
+	    HIGH => 768
+	   },
+	   { 
+	    NAME => "dev_perio_tx_fifo_size_10",
+	    DEFAULT => 256,
+	    ENUM => [],
+	    LOW => 4,
+	    HIGH => 768
+	   },
+	   { 
+	    NAME => "dev_perio_tx_fifo_size_11",
+	    DEFAULT => 256,
+	    ENUM => [],
+	    LOW => 4,
+	    HIGH => 768
+	   },
+	   { 
+	    NAME => "dev_perio_tx_fifo_size_12",
+	    DEFAULT => 256,
+	    ENUM => [],
+	    LOW => 4,
+	    HIGH => 768
+	   },
+	   { 
+	    NAME => "dev_perio_tx_fifo_size_13",
+	    DEFAULT => 256,
+	    ENUM => [],
+	    LOW => 4,
+	    HIGH => 768
+	   },
+	   { 
+	    NAME => "dev_perio_tx_fifo_size_14",
+	    DEFAULT => 256,
+	    ENUM => [],
+	    LOW => 4,
+	    HIGH => 768
+	   },
+	   { 
+	    NAME => "dev_perio_tx_fifo_size_15",
+	    DEFAULT => 256,
+	    ENUM => [],
+	    LOW => 4,
+	    HIGH => 768
+	   },
+	   { 
+	    NAME => "host_rx_fifo_size",
+	    DEFAULT => 1024,
+	    ENUM => [],
+	    LOW => 16,
+	    HIGH => 32768
+	   },
+	   { 
+	    NAME => "host_nperio_tx_fifo_size",
+	    DEFAULT => 1024,
+	    ENUM => [],
+	    LOW => 16,
+	    HIGH => 32768
+	   },
+	   { 
+	    NAME => "host_perio_tx_fifo_size",
+	    DEFAULT => 1024,
+	    ENUM => [],
+	    LOW => 16,
+	    HIGH => 32768
+	   },
+	   { 
+	    NAME => "max_transfer_size",
+	    DEFAULT => 65535,
+	    ENUM => [],
+	    LOW => 2047,
+	    HIGH => 65535
+	   },
+	   { 
+	    NAME => "max_packet_count",
+	    DEFAULT => 511,
+	    ENUM => [],
+	    LOW => 15,
+	    HIGH => 511
+	   },
+	   { 
+	    NAME => "host_channels",
+	    DEFAULT => 12,
+	    ENUM => [],
+	    LOW => 1,
+	    HIGH => 16
+	   },
+	   { 
+	    NAME => "dev_endpoints",
+	    DEFAULT => 6,
+	    ENUM => [],
+	    LOW => 1,
+	    HIGH => 15
+	   },
+	   { 
+	    NAME => "phy_type",
+	    DEFAULT => 1,
+	    ENUM => [],
+	    LOW => 0,
+	    HIGH => 2
+	   },
+	   { 
+	    NAME => "phy_utmi_width",
+	    DEFAULT => 16,
+	    ENUM => [8, 16],
+	    LOW => 8,
+	    HIGH => 16
+	   },
+	   { 
+	    NAME => "phy_ulpi_ddr",
+	    DEFAULT => 0,
+	    ENUM => [],
+	    LOW => 0,
+	    HIGH => 1
+	   },
+	  ];
+
+
+#
+#
+sub check_arch {
+  $_ = `uname -m`;
+  chomp;
+  unless (m/armv4tl/) {
+    warn "# \n# Can't execute on $_.  Run on integrator platform.\n# \n";
+    return 0;
+  }
+  return 1;
+}
+
+#
+#
+sub load_module {
+  my $params = shift;
+  print "\nRemoving Module\n";
+  system "rmmod dwc_otg";
+  print "Loading Module\n";
+  if ($params ne "") {
+    print "Module Parameters: $params\n";
+  }
+  if (system("modprobe dwc_otg $params")) { 
+    warn "Unable to load module\n";
+    return 0; 
+  }
+  return 1;
+}
+
+#
+#
+sub test_status {
+  my $arg = shift;
+
+  print "\n";
+
+  if (defined $arg) {
+    warn "WARNING: $arg\n";
+  }
+  
+  if ($errors > 0) {
+    warn "TEST FAILED with $errors errors\n";
+    return 0;
+  } else {
+    print "TEST PASSED\n";
+    return 0 if (defined $arg);
+  }
+  return 1;
+}
+
+#
+#
+@EXPORT = qw(
+$sysfsdir
+$paramdir
+$params
+$errors
+check_arch
+load_module
+test_status
+);
+
+1;
diff --git a/drivers/usb/host/dwc_otg/test/test_mod_param.pl b/drivers/usb/host/dwc_otg/test/test_mod_param.pl
new file mode 100644
index 000000000000..e887dce5bc1e
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/test/test_mod_param.pl
@@ -0,0 +1,133 @@
+#!/usr/bin/perl -w
+# 
+# Run this program on the integrator.
+#
+# - Tests module parameter default values.
+# - Tests setting of valid module parameter values via modprobe.
+# - Tests invalid module parameter values.
+# -----------------------------------------------------------------------------
+use strict;
+use dwc_otg_test;
+
+check_arch() or die;
+
+#
+#
+sub test {
+  my ($param,$expected) = @_;
+  my $value = get($param);
+
+  if ($value == $expected) {
+    print "$param = $value, okay\n";
+  }
+
+  else {
+    warn "ERROR: value of $param != $expected, $value\n";
+    $errors ++;
+  }
+}
+
+#
+#
+sub get {
+  my $param = shift;
+  my $tmp = `cat $paramdir/$param`;
+  chomp $tmp;
+  return $tmp;
+}
+
+#
+#
+sub test_main {
+
+  print "\nTesting Module Parameters\n";
+
+  load_module("") or die;
+
+  # Test initial values
+  print "\nTesting Default Values\n";
+  foreach (@{$params}) {
+    test ($_->{NAME}, $_->{DEFAULT});
+  }
+
+  # Test low value
+  print "\nTesting Low Value\n";
+  my $cmd_params = "";
+  foreach (@{$params}) {
+    $cmd_params = $cmd_params . "$_->{NAME}=$_->{LOW} ";
+  }
+  load_module($cmd_params) or die;
+
+  foreach (@{$params}) {
+    test ($_->{NAME}, $_->{LOW});
+  }
+
+  # Test high value
+  print "\nTesting High Value\n";
+  $cmd_params = "";
+  foreach (@{$params}) {
+    $cmd_params = $cmd_params . "$_->{NAME}=$_->{HIGH} ";
+  }
+  load_module($cmd_params) or die;
+
+  foreach (@{$params}) {
+    test ($_->{NAME}, $_->{HIGH});
+  }
+
+  # Test Enum
+  print "\nTesting Enumerated\n";
+  foreach (@{$params}) {
+    if (defined $_->{ENUM}) {
+      my $value;
+      foreach $value (@{$_->{ENUM}}) {
+	$cmd_params = "$_->{NAME}=$value";
+	load_module($cmd_params) or die;
+	test ($_->{NAME}, $value);
+      }
+    }
+  }
+
+  # Test Invalid Values
+  print "\nTesting Invalid Values\n";
+  $cmd_params = "";
+  foreach (@{$params}) {
+    $cmd_params = $cmd_params . sprintf "$_->{NAME}=%d ", $_->{LOW}-1;
+  }
+  load_module($cmd_params) or die;
+
+  foreach (@{$params}) {
+    test ($_->{NAME}, $_->{DEFAULT});
+  }
+
+  $cmd_params = "";
+  foreach (@{$params}) {
+    $cmd_params = $cmd_params . sprintf "$_->{NAME}=%d ", $_->{HIGH}+1;
+  }
+  load_module($cmd_params) or die;
+
+  foreach (@{$params}) {
+    test ($_->{NAME}, $_->{DEFAULT});
+  }
+
+  print "\nTesting Enumerated\n";
+  foreach (@{$params}) {
+    if (defined $_->{ENUM}) {
+      my $value;
+      foreach $value (@{$_->{ENUM}}) {
+	$value = $value + 1;
+	$cmd_params = "$_->{NAME}=$value";
+	load_module($cmd_params) or die;
+	test ($_->{NAME}, $_->{DEFAULT});
+	$value = $value - 2;
+	$cmd_params = "$_->{NAME}=$value";
+	load_module($cmd_params) or die;
+	test ($_->{NAME}, $_->{DEFAULT});
+      }
+    }
+  }
+
+  test_status() or die;
+}
+
+test_main();
+0;
diff --git a/drivers/usb/host/dwc_otg/test/test_sysfs.pl b/drivers/usb/host/dwc_otg/test/test_sysfs.pl
new file mode 100644
index 000000000000..abcf284fecf9
--- /dev/null
+++ b/drivers/usb/host/dwc_otg/test/test_sysfs.pl
@@ -0,0 +1,193 @@
+#!/usr/bin/perl -w
+# 
+# Run this program on the integrator
+# - Tests select sysfs attributes.
+# - Todo ... test more attributes, hnp/srp, buspower/bussuspend, etc.
+# -----------------------------------------------------------------------------
+use strict;
+use dwc_otg_test;
+
+check_arch() or die;
+
+#
+#
+sub test {
+  my ($attr,$expected) = @_;
+  my $string = get($attr);
+
+  if ($string eq $expected) {
+    printf("$attr = $string, okay\n");
+  }
+  else {
+    warn "ERROR: value of $attr != $expected, $string\n";
+    $errors ++;
+  }
+}
+
+#
+#
+sub set {
+  my ($reg, $value) = @_;
+  system "echo $value > $sysfsdir/$reg";
+}
+
+#
+#
+sub get {
+  my $attr = shift;
+  my $string = `cat $sysfsdir/$attr`;
+  chomp $string;
+  if ($string =~ m/\s\=\s/) {
+    my $tmp;
+    ($tmp, $string) = split /\s=\s/, $string;
+  }
+  return $string;
+}
+
+#
+#
+sub test_main {
+  print("\nTesting Sysfs Attributes\n");
+
+  load_module("") or die;
+
+  # Test initial values of regoffset/regvalue/guid/gsnpsid
+  print("\nTesting Default Values\n");
+
+  test("regoffset", "0xffffffff");
+  test("regvalue", "invalid offset");
+  test("guid", "0x12345678");	# this will fail if it has been changed
+  test("gsnpsid", "0x4f54200a");
+
+  # Test operation of regoffset/regvalue
+  print("\nTesting regoffset\n");
+  set('regoffset', '5a5a5a5a');
+  test("regoffset", "0xffffffff");
+
+  set('regoffset', '0');
+  test("regoffset", "0x00000000");
+
+  set('regoffset', '40000');
+  test("regoffset", "0x00000000");
+
+  set('regoffset', '3ffff');
+  test("regoffset", "0x0003ffff");
+
+  set('regoffset', '1');
+  test("regoffset", "0x00000001");
+
+  print("\nTesting regvalue\n");
+  set('regoffset', '3c');
+  test("regvalue", "0x12345678");
+  set('regvalue', '5a5a5a5a');
+  test("regvalue", "0x5a5a5a5a");
+  set('regvalue','a5a5a5a5');
+  test("regvalue", "0xa5a5a5a5");
+  set('guid','12345678');
+
+  # Test HNP Capable
+  print("\nTesting HNP Capable bit\n");
+  set('hnpcapable', '1');
+  test("hnpcapable", "0x1");
+  set('hnpcapable','0');
+  test("hnpcapable", "0x0");
+
+  set('regoffset','0c');
+
+  my $old = get('gusbcfg');
+  print("setting hnpcapable\n");
+  set('hnpcapable', '1');
+  test("hnpcapable", "0x1");
+  test('gusbcfg', sprintf "0x%08x", (oct ($old) | (1<<9)));
+  test('regvalue', sprintf "0x%08x", (oct ($old) | (1<<9)));
+
+  $old = get('gusbcfg');
+  print("clearing hnpcapable\n");
+  set('hnpcapable', '0');
+  test("hnpcapable", "0x0");
+  test ('gusbcfg', sprintf "0x%08x", oct ($old) & (~(1<<9)));
+  test ('regvalue', sprintf "0x%08x", oct ($old) & (~(1<<9)));
+
+  # Test SRP Capable
+  print("\nTesting SRP Capable bit\n");
+  set('srpcapable', '1');
+  test("srpcapable", "0x1");
+  set('srpcapable','0');
+  test("srpcapable", "0x0");
+
+  set('regoffset','0c');
+
+  $old = get('gusbcfg');
+  print("setting srpcapable\n");
+  set('srpcapable', '1');
+  test("srpcapable", "0x1");
+  test('gusbcfg', sprintf "0x%08x", (oct ($old) | (1<<8)));
+  test('regvalue', sprintf "0x%08x", (oct ($old) | (1<<8)));
+
+  $old = get('gusbcfg');
+  print("clearing srpcapable\n");
+  set('srpcapable', '0');
+  test("srpcapable", "0x0");
+  test('gusbcfg', sprintf "0x%08x", oct ($old) & (~(1<<8)));
+  test('regvalue', sprintf "0x%08x", oct ($old) & (~(1<<8)));
+
+  # Test GGPIO
+  print("\nTesting GGPIO\n");
+  set('ggpio','5a5a5a5a');
+  test('ggpio','0x5a5a0000');
+  set('ggpio','a5a5a5a5');
+  test('ggpio','0xa5a50000');
+  set('ggpio','11110000');
+  test('ggpio','0x11110000');
+  set('ggpio','00001111');
+  test('ggpio','0x00000000');
+
+  # Test DEVSPEED
+  print("\nTesting DEVSPEED\n");
+  set('regoffset','800');
+  $old = get('regvalue');
+  set('devspeed','0');
+  test('devspeed','0x0');
+  test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3)));
+  set('devspeed','1');
+  test('devspeed','0x1');
+  test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3) | 1));
+  set('devspeed','2');
+  test('devspeed','0x2');
+  test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3) | 2));
+  set('devspeed','3');
+  test('devspeed','0x3');
+  test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3) | 3));
+  set('devspeed','4');
+  test('devspeed','0x0');
+  test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3)));
+  set('devspeed','5');
+  test('devspeed','0x1');
+  test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3) | 1));
+
+
+  #  mode	Returns the current mode:0 for device mode1 for host mode	Read
+  #  hnp	Initiate the Host Negotiation Protocol.  Read returns the status.	Read/Write
+  #  srp	Initiate the Session Request Protocol.  Read returns the status.	Read/Write
+  #  buspower	Get or Set the Power State of the bus (0 - Off or 1 - On) 	Read/Write
+  #  bussuspend	Suspend the USB bus.	Read/Write
+  #  busconnected	Get the connection status of the bus 	Read
+
+  #  gotgctl	Get or set the Core Control Status Register.	Read/Write
+  ##  gusbcfg	Get or set the Core USB Configuration Register	Read/Write
+  #  grxfsiz	Get or set the Receive FIFO Size Register	Read/Write
+  #  gnptxfsiz	Get or set the non-periodic Transmit Size Register	Read/Write
+  #  gpvndctl	Get or set the PHY Vendor Control Register	Read/Write
+  ##  ggpio	Get the value in the lower 16-bits of the General Purpose IO Register or Set the upper 16 bits.	Read/Write
+  ##  guid	Get or set the value of the User ID Register	Read/Write
+  ##  gsnpsid	Get the value of the Synopsys ID Regester	Read
+  ##  devspeed	Get or set the device speed setting in the DCFG register	Read/Write
+  #  enumspeed	Gets the device enumeration Speed.	Read
+  #  hptxfsiz	Get the value of the Host Periodic Transmit FIFO	Read
+  #  hprt0	Get or Set the value in the Host Port Control and Status Register	Read/Write
+
+  test_status("TEST NYI") or die;
+}
+
+test_main();
+0;
-- 
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