Loading drivers/net/fec.c +0 −42 Original line number Diff line number Diff line Loading @@ -43,17 +43,9 @@ #include <asm/pgtable.h> #include <asm/cacheflush.h> #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || \ defined(CONFIG_M5272) || defined(CONFIG_M528x) || \ defined(CONFIG_M520x) || defined(CONFIG_M532x) #include <asm/coldfire.h> #include <asm/mcfsim.h> #include "fec.h" #else #include <asm/8xx_immap.h> #include <asm/mpc8xx.h> #include "commproc.h" #endif #if defined(CONFIG_FEC2) #define FEC_MAX_PORTS 2 Loading Loading @@ -1229,14 +1221,9 @@ static phy_info_t const * const phy_info[] = { /* ------------------------------------------------------------------------- */ #ifdef HAVE_mii_link_interrupt #ifdef CONFIG_RPXCLASSIC static void mii_link_interrupt(void *dev_id); #else static irqreturn_t mii_link_interrupt(int irq, void * dev_id); #endif #endif #if defined(CONFIG_M5272) /* Loading Loading @@ -1789,20 +1776,6 @@ static void __inline__ fec_request_intrs(struct net_device *dev) if (request_8xxirq(FEC_INTERRUPT, fec_enet_interrupt, 0, "fec", dev) != 0) panic("Could not allocate FEC IRQ!"); #ifdef CONFIG_RPXCLASSIC /* Make Port C, bit 15 an input that causes interrupts. */ immap->im_ioport.iop_pcpar &= ~0x0001; immap->im_ioport.iop_pcdir &= ~0x0001; immap->im_ioport.iop_pcso &= ~0x0001; immap->im_ioport.iop_pcint |= 0x0001; cpm_install_handler(CPMVEC_PIO_PC15, mii_link_interrupt, dev); /* Make LEDS reflect Link status. */ *((uint *) RPX_CSR_ADDR) &= ~BCSR2_FETHLEDMODE; #endif } static void __inline__ fec_get_mac(struct net_device *dev) Loading @@ -1811,16 +1784,6 @@ static void __inline__ fec_get_mac(struct net_device *dev) bd = (bd_t *)__res; memcpy(dev->dev_addr, bd->bi_enetaddr, ETH_ALEN); #ifdef CONFIG_RPXCLASSIC /* The Embedded Planet boards have only one MAC address in * the EEPROM, but can have two Ethernet ports. For the * FEC port, we create another address by setting one of * the address bits above something that would have (up to * now) been allocated. */ dev->dev_adrd[3] |= 0x80; #endif } static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep) Loading Loading @@ -2099,13 +2062,8 @@ mii_discover_phy(uint mii_reg, struct net_device *dev) /* This interrupt occurs when the PHY detects a link change. */ #ifdef HAVE_mii_link_interrupt #ifdef CONFIG_RPXCLASSIC static void mii_link_interrupt(void *dev_id) #else static irqreturn_t mii_link_interrupt(int irq, void * dev_id) #endif { struct net_device *dev = dev_id; struct fec_enet_private *fep = netdev_priv(dev); Loading include/asm-m68knommu/commproc.h +0 −19 Original line number Diff line number Diff line Loading @@ -519,25 +519,6 @@ typedef struct scc_enet { #define SICR_ENET_CLKRT ((uint)0x00002c00) #endif #ifdef CONFIG_RPXCLASSIC /* Bits in parallel I/O port registers that have to be set/cleared * to configure the pins for SCC1 use. */ #define PA_ENET_RXD ((ushort)0x0001) #define PA_ENET_TXD ((ushort)0x0002) #define PA_ENET_TCLK ((ushort)0x0200) #define PA_ENET_RCLK ((ushort)0x0800) #define PB_ENET_TENA ((uint)0x00001000) #define PC_ENET_CLSN ((ushort)0x0010) #define PC_ENET_RENA ((ushort)0x0020) /* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. */ #define SICR_ENET_MASK ((uint)0x000000ff) #define SICR_ENET_CLKRT ((uint)0x0000003d) #endif /* SCC Event register as used by Ethernet. */ #define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ Loading Loading
drivers/net/fec.c +0 −42 Original line number Diff line number Diff line Loading @@ -43,17 +43,9 @@ #include <asm/pgtable.h> #include <asm/cacheflush.h> #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || \ defined(CONFIG_M5272) || defined(CONFIG_M528x) || \ defined(CONFIG_M520x) || defined(CONFIG_M532x) #include <asm/coldfire.h> #include <asm/mcfsim.h> #include "fec.h" #else #include <asm/8xx_immap.h> #include <asm/mpc8xx.h> #include "commproc.h" #endif #if defined(CONFIG_FEC2) #define FEC_MAX_PORTS 2 Loading Loading @@ -1229,14 +1221,9 @@ static phy_info_t const * const phy_info[] = { /* ------------------------------------------------------------------------- */ #ifdef HAVE_mii_link_interrupt #ifdef CONFIG_RPXCLASSIC static void mii_link_interrupt(void *dev_id); #else static irqreturn_t mii_link_interrupt(int irq, void * dev_id); #endif #endif #if defined(CONFIG_M5272) /* Loading Loading @@ -1789,20 +1776,6 @@ static void __inline__ fec_request_intrs(struct net_device *dev) if (request_8xxirq(FEC_INTERRUPT, fec_enet_interrupt, 0, "fec", dev) != 0) panic("Could not allocate FEC IRQ!"); #ifdef CONFIG_RPXCLASSIC /* Make Port C, bit 15 an input that causes interrupts. */ immap->im_ioport.iop_pcpar &= ~0x0001; immap->im_ioport.iop_pcdir &= ~0x0001; immap->im_ioport.iop_pcso &= ~0x0001; immap->im_ioport.iop_pcint |= 0x0001; cpm_install_handler(CPMVEC_PIO_PC15, mii_link_interrupt, dev); /* Make LEDS reflect Link status. */ *((uint *) RPX_CSR_ADDR) &= ~BCSR2_FETHLEDMODE; #endif } static void __inline__ fec_get_mac(struct net_device *dev) Loading @@ -1811,16 +1784,6 @@ static void __inline__ fec_get_mac(struct net_device *dev) bd = (bd_t *)__res; memcpy(dev->dev_addr, bd->bi_enetaddr, ETH_ALEN); #ifdef CONFIG_RPXCLASSIC /* The Embedded Planet boards have only one MAC address in * the EEPROM, but can have two Ethernet ports. For the * FEC port, we create another address by setting one of * the address bits above something that would have (up to * now) been allocated. */ dev->dev_adrd[3] |= 0x80; #endif } static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep) Loading Loading @@ -2099,13 +2062,8 @@ mii_discover_phy(uint mii_reg, struct net_device *dev) /* This interrupt occurs when the PHY detects a link change. */ #ifdef HAVE_mii_link_interrupt #ifdef CONFIG_RPXCLASSIC static void mii_link_interrupt(void *dev_id) #else static irqreturn_t mii_link_interrupt(int irq, void * dev_id) #endif { struct net_device *dev = dev_id; struct fec_enet_private *fep = netdev_priv(dev); Loading
include/asm-m68knommu/commproc.h +0 −19 Original line number Diff line number Diff line Loading @@ -519,25 +519,6 @@ typedef struct scc_enet { #define SICR_ENET_CLKRT ((uint)0x00002c00) #endif #ifdef CONFIG_RPXCLASSIC /* Bits in parallel I/O port registers that have to be set/cleared * to configure the pins for SCC1 use. */ #define PA_ENET_RXD ((ushort)0x0001) #define PA_ENET_TXD ((ushort)0x0002) #define PA_ENET_TCLK ((ushort)0x0200) #define PA_ENET_RCLK ((ushort)0x0800) #define PB_ENET_TENA ((uint)0x00001000) #define PC_ENET_CLSN ((ushort)0x0010) #define PC_ENET_RENA ((ushort)0x0020) /* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. */ #define SICR_ENET_MASK ((uint)0x000000ff) #define SICR_ENET_CLKRT ((uint)0x0000003d) #endif /* SCC Event register as used by Ethernet. */ #define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ Loading