Commit c0a639ad authored by Borislav Petkov's avatar Borislav Petkov Committed by H. Peter Anvin
Browse files

x86, Intel: Convert to the new bit access MSR accessors 



... and save some lines of code.

Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Link: http://lkml.kernel.org/r/1394384725-10796-4-git-send-email-bp@alien8.de


Signed-off-by: default avatarH. Peter Anvin <hpa@linux.intel.com>
parent 8f86a737

arch/x86/include/uapi/asm/msr-index.h

+6 −3
Original line number Diff line number Diff line
@@ -368,14 +368,16 @@ 
#define THERM_LOG_THRESHOLD1           (1 << 9)



/* MISC_ENABLE bits: architectural */

#define MSR_IA32_MISC_ENABLE_FAST_STRING	(1ULL << 0)

#define MSR_BIT_FAST_STRING				0

#define MSR_IA32_MISC_ENABLE_FAST_STRING	(1ULL << MSR_BIT_FAST_STRING)

#define MSR_IA32_MISC_ENABLE_TCC		(1ULL << 1)

#define MSR_IA32_MISC_ENABLE_EMON		(1ULL << 7)

#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL	(1ULL << 11)

#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL	(1ULL << 12)

#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP	(1ULL << 16)

#define MSR_IA32_MISC_ENABLE_MWAIT		(1ULL << 18)

#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID	(1ULL << 22)

#define MSR_BIT_LIMIT_CPUID				22

#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID	(1ULL << MSR_BIT_LIMIT_CPUID);

#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE	(1ULL << 23)

#define MSR_IA32_MISC_ENABLE_XD_DISABLE		(1ULL << 34)
@@ -385,7 +387,8 @@ 
#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE	(1ULL << 4)

#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE	(1ULL << 6)

#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK	(1ULL << 8)

#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE	(1ULL << 9)

#define MSR_BIT_PRF_DIS				9

#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE	(1ULL << MSR_BIT_PRF_DIS)

#define MSR_IA32_MISC_ENABLE_FERR		(1ULL << 10)

#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX	(1ULL << 10)

#define MSR_IA32_MISC_ENABLE_TM2		(1ULL << 13)

arch/x86/kernel/cpu/intel.c

+7 −23
Original line number Diff line number Diff line
@@ -31,11 +31,7 @@ static void early_init_intel(struct cpuinfo_x86 *c) 


	/* Unmask CPUID levels if masked: */

	if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {

		rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);



		if (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID) {

			misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID;

			wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);

		if (msr_clear_bit(MSR_IA32_MISC_ENABLE, MSR_BIT_LIMIT_CPUID) > 0) {

			c->cpuid_level = cpuid_eax(0);

			get_cpu_cap(c);

		}
@@ -129,16 +125,9 @@ static void early_init_intel(struct cpuinfo_x86 *c) 
	 * Ingo Molnar reported a Pentium D (model 6) and a Xeon

	 * (model 2) with the same problem.

	 */

	if (c->x86 == 15) {

		rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);



		if (misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING) {

			printk(KERN_INFO "kmemcheck: Disabling fast string operations\n");



			misc_enable &= ~MSR_IA32_MISC_ENABLE_FAST_STRING;

			wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);

		}

	}

	if (c->x86 == 15)

		if (msr_clear_bit(MSR_IA32_MISC_ENABLE, MSR_BIT_FAST_STRING) > 0)

			pr_info("kmemcheck: Disabling fast string operations\n");

#endif



	/*
@@ -197,8 +186,6 @@ static void intel_smp_check(struct cpuinfo_x86 *c) 


static void intel_workarounds(struct cpuinfo_x86 *c)

{

	unsigned long lo, hi;



#ifdef CONFIG_X86_F00F_BUG

	/*

	 * All current models of Pentium and Pentium with MMX technology CPUs
@@ -229,12 +216,9 @@ static void intel_workarounds(struct cpuinfo_x86 *c) 
	 * Hardware prefetcher may cause stale data to be loaded into the cache.

	 */

	if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {

		rdmsr(MSR_IA32_MISC_ENABLE, lo, hi);

		if ((lo & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE) == 0) {

			printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");

			printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");

			lo |= MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE;

			wrmsr(MSR_IA32_MISC_ENABLE, lo, hi);

		if (msr_set_bit(MSR_IA32_MISC_ENABLE, MSR_BIT_PRF_DIS) > 0) {

			pr_info("CPU: C0 stepping P4 Xeon detected.\n");

			pr_info("CPU: Disabling hardware prefetching (Errata 037)\n");

		}

	}