Commit bc2dcc1a authored by Shawn Lin's avatar Shawn Lin Committed by Ulf Hansson
Browse files

mmc: dw_mmc: improve dw_mci_reset a bit 



Too much condition iteration makes the code
less readable. Slightly improve it.

Signed-off-by: default avatarShawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: default avatarJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent 4dba18de

drivers/mmc/host/dw_mmc.c

+20 −18
Original line number Diff line number Diff line
@@ -1699,6 +1699,7 @@ static bool dw_mci_reset(struct dw_mci *host) 
{

	u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;

	bool ret = false;

	u32 status = 0;



	/*

	 * Resetting generates a block interrupt, hence setting
@@ -1714,21 +1715,23 @@ static bool dw_mci_reset(struct dw_mci *host) 


	if (dw_mci_ctrl_reset(host, flags)) {

		/*

		 * In all cases we clear the RAWINTS register to clear any

		 * interrupts.

		 * In all cases we clear the RAWINTS

		 * register to clear any interrupts.

		 */

		mci_writel(host, RINTSTS, 0xFFFFFFFF);



		/* if using dma we wait for dma_req to clear */

		if (host->use_dma) {

			u32 status;

		if (!host->use_dma) {

			ret = true;

			goto ciu_out;

		}



		/* Wait for dma_req to be cleared */

		if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS,

					      status,

					      !(status & SDMMC_STATUS_DMA_REQ),

					      1, 500 * USEC_PER_MSEC)) {

			dev_err(host->dev,

					"%s: Timeout waiting for dma_req to clear during reset\n",

				"%s: Timeout waiting for dma_req to be cleared\n",

				__func__);

			goto ciu_out;

		}
@@ -1736,7 +1739,6 @@ static bool dw_mci_reset(struct dw_mci *host) 
		/* when using DMA next we reset the fifo again */

		if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))

			goto ciu_out;

		}

	} else {

		/* if the controller reset bit did clear, then set clock regs */

		if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {