Loading arch/ia64/sn/pci/pcibr/pcibr_reg.c +24 −24 Original line number Diff line number Diff line Loading @@ -25,7 +25,7 @@ union br_ptr { */ void pcireg_control_bit_clr(struct pcibus_info *pcibus_info, uint64_t bits) { union br_ptr *ptr = (union br_ptr *)pcibus_info->pbi_buscommon.bs_base; union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base; if (pcibus_info) { switch (pcibus_info->pbi_bridge_type) { Loading @@ -38,14 +38,14 @@ void pcireg_control_bit_clr(struct pcibus_info *pcibus_info, uint64_t bits) default: panic ("pcireg_control_bit_clr: unknown bridgetype bridge 0x%p", (void *)ptr); ptr); } } } void pcireg_control_bit_set(struct pcibus_info *pcibus_info, uint64_t bits) { union br_ptr *ptr = (union br_ptr *)pcibus_info->pbi_buscommon.bs_base; union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base; if (pcibus_info) { switch (pcibus_info->pbi_bridge_type) { Loading @@ -58,7 +58,7 @@ void pcireg_control_bit_set(struct pcibus_info *pcibus_info, uint64_t bits) default: panic ("pcireg_control_bit_set: unknown bridgetype bridge 0x%p", (void *)ptr); ptr); } } } Loading @@ -68,7 +68,7 @@ void pcireg_control_bit_set(struct pcibus_info *pcibus_info, uint64_t bits) */ uint64_t pcireg_tflush_get(struct pcibus_info *pcibus_info) { union br_ptr *ptr = (union br_ptr *)pcibus_info->pbi_buscommon.bs_base; union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base; uint64_t ret = 0; if (pcibus_info) { Loading @@ -82,7 +82,7 @@ uint64_t pcireg_tflush_get(struct pcibus_info *pcibus_info) default: panic ("pcireg_tflush_get: unknown bridgetype bridge 0x%p", (void *)ptr); ptr); } } Loading @@ -98,7 +98,7 @@ uint64_t pcireg_tflush_get(struct pcibus_info *pcibus_info) */ uint64_t pcireg_intr_status_get(struct pcibus_info * pcibus_info) { union br_ptr *ptr = (union br_ptr *)pcibus_info->pbi_buscommon.bs_base; union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base; uint64_t ret = 0; if (pcibus_info) { Loading @@ -112,7 +112,7 @@ uint64_t pcireg_intr_status_get(struct pcibus_info * pcibus_info) default: panic ("pcireg_intr_status_get: unknown bridgetype bridge 0x%p", (void *)ptr); ptr); } } return ret; Loading @@ -123,7 +123,7 @@ uint64_t pcireg_intr_status_get(struct pcibus_info * pcibus_info) */ void pcireg_intr_enable_bit_clr(struct pcibus_info *pcibus_info, uint64_t bits) { union br_ptr *ptr = (union br_ptr *)pcibus_info->pbi_buscommon.bs_base; union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base; if (pcibus_info) { switch (pcibus_info->pbi_bridge_type) { Loading @@ -136,14 +136,14 @@ void pcireg_intr_enable_bit_clr(struct pcibus_info *pcibus_info, uint64_t bits) default: panic ("pcireg_intr_enable_bit_clr: unknown bridgetype bridge 0x%p", (void *)ptr); ptr); } } } void pcireg_intr_enable_bit_set(struct pcibus_info *pcibus_info, uint64_t bits) { union br_ptr *ptr = (union br_ptr *)pcibus_info->pbi_buscommon.bs_base; union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base; if (pcibus_info) { switch (pcibus_info->pbi_bridge_type) { Loading @@ -156,7 +156,7 @@ void pcireg_intr_enable_bit_set(struct pcibus_info *pcibus_info, uint64_t bits) default: panic ("pcireg_intr_enable_bit_set: unknown bridgetype bridge 0x%p", (void *)ptr); ptr); } } } Loading @@ -167,7 +167,7 @@ void pcireg_intr_enable_bit_set(struct pcibus_info *pcibus_info, uint64_t bits) void pcireg_intr_addr_addr_set(struct pcibus_info *pcibus_info, int int_n, uint64_t addr) { union br_ptr *ptr = (union br_ptr *)pcibus_info->pbi_buscommon.bs_base; union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base; if (pcibus_info) { switch (pcibus_info->pbi_bridge_type) { Loading @@ -186,7 +186,7 @@ void pcireg_intr_addr_addr_set(struct pcibus_info *pcibus_info, int int_n, default: panic ("pcireg_intr_addr_addr_get: unknown bridgetype bridge 0x%p", (void *)ptr); ptr); } } } Loading @@ -196,7 +196,7 @@ void pcireg_intr_addr_addr_set(struct pcibus_info *pcibus_info, int int_n, */ void pcireg_force_intr_set(struct pcibus_info *pcibus_info, int int_n) { union br_ptr *ptr = (union br_ptr *)pcibus_info->pbi_buscommon.bs_base; union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base; if (pcibus_info) { switch (pcibus_info->pbi_bridge_type) { Loading @@ -209,7 +209,7 @@ void pcireg_force_intr_set(struct pcibus_info *pcibus_info, int int_n) default: panic ("pcireg_force_intr_set: unknown bridgetype bridge 0x%p", (void *)ptr); ptr); } } } Loading @@ -219,7 +219,7 @@ void pcireg_force_intr_set(struct pcibus_info *pcibus_info, int int_n) */ uint64_t pcireg_wrb_flush_get(struct pcibus_info *pcibus_info, int device) { union br_ptr *ptr = (union br_ptr *)pcibus_info->pbi_buscommon.bs_base; union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base; uint64_t ret = 0; if (pcibus_info) { Loading @@ -233,7 +233,7 @@ uint64_t pcireg_wrb_flush_get(struct pcibus_info *pcibus_info, int device) __sn_readq_relaxed(&ptr->pic.p_wr_req_buf[device]); break; default: panic("pcireg_wrb_flush_get: unknown bridgetype bridge 0x%p", (void *)ptr); panic("pcireg_wrb_flush_get: unknown bridgetype bridge 0x%p", ptr); } } Loading @@ -244,7 +244,7 @@ uint64_t pcireg_wrb_flush_get(struct pcibus_info *pcibus_info, int device) void pcireg_int_ate_set(struct pcibus_info *pcibus_info, int ate_index, uint64_t val) { union br_ptr *ptr = (union br_ptr *)pcibus_info->pbi_buscommon.bs_base; union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base; if (pcibus_info) { switch (pcibus_info->pbi_bridge_type) { Loading @@ -257,15 +257,15 @@ void pcireg_int_ate_set(struct pcibus_info *pcibus_info, int ate_index, default: panic ("pcireg_int_ate_set: unknown bridgetype bridge 0x%p", (void *)ptr); ptr); } } } uint64_t *pcireg_int_ate_addr(struct pcibus_info *pcibus_info, int ate_index) uint64_t __iomem *pcireg_int_ate_addr(struct pcibus_info *pcibus_info, int ate_index) { union br_ptr *ptr = (union br_ptr *)pcibus_info->pbi_buscommon.bs_base; uint64_t *ret = (uint64_t *) 0; union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base; uint64_t __iomem *ret = NULL; if (pcibus_info) { switch (pcibus_info->pbi_bridge_type) { Loading @@ -278,7 +278,7 @@ uint64_t *pcireg_int_ate_addr(struct pcibus_info *pcibus_info, int ate_index) default: panic ("pcireg_int_ate_addr: unknown bridgetype bridge 0x%p", (void *)ptr); ptr); } } return ret; Loading arch/ia64/sn/pci/tioca_provider.c +6 −6 Original line number Diff line number Diff line Loading @@ -38,10 +38,10 @@ tioca_gart_init(struct tioca_kernel *tioca_kern) uint64_t offset; struct page *tmp; struct tioca_common *tioca_common; struct tioca *ca_base; struct tioca __iomem *ca_base; tioca_common = tioca_kern->ca_common; ca_base = (struct tioca *)tioca_common->ca_common.bs_base; ca_base = (struct tioca __iomem *)tioca_common->ca_common.bs_base; if (list_empty(tioca_kern->ca_devices)) return 0; Loading Loading @@ -215,7 +215,7 @@ tioca_fastwrite_enable(struct tioca_kernel *tioca_kern) { int cap_ptr; uint32_t reg; struct tioca *tioca_base; struct tioca __iomem *tioca_base; struct pci_dev *pdev; struct tioca_common *common; Loading Loading @@ -257,7 +257,7 @@ tioca_fastwrite_enable(struct tioca_kernel *tioca_kern) * Set ca's fw to match */ tioca_base = (struct tioca *)common->ca_common.bs_base; tioca_base = (struct tioca __iomem*)common->ca_common.bs_base; __sn_setq_relaxed(&tioca_base->ca_control1, CA_AGP_FW_ENABLE); } Loading Loading @@ -322,7 +322,7 @@ static uint64_t tioca_dma_d48(struct pci_dev *pdev, uint64_t paddr) { struct tioca_common *tioca_common; struct tioca *ca_base; struct tioca __iomem *ca_base; uint64_t ct_addr; dma_addr_t bus_addr; uint32_t node_upper; Loading @@ -330,7 +330,7 @@ tioca_dma_d48(struct pci_dev *pdev, uint64_t paddr) struct pcidev_info *pcidev_info = SN_PCIDEV_INFO(pdev); tioca_common = (struct tioca_common *)pcidev_info->pdi_pcibus_info; ca_base = (struct tioca *)tioca_common->ca_common.bs_base; ca_base = (struct tioca __iomem *)tioca_common->ca_common.bs_base; ct_addr = PHYS_TO_TIODMA(paddr); if (!ct_addr) Loading Loading
arch/ia64/sn/pci/pcibr/pcibr_reg.c +24 −24 Original line number Diff line number Diff line Loading @@ -25,7 +25,7 @@ union br_ptr { */ void pcireg_control_bit_clr(struct pcibus_info *pcibus_info, uint64_t bits) { union br_ptr *ptr = (union br_ptr *)pcibus_info->pbi_buscommon.bs_base; union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base; if (pcibus_info) { switch (pcibus_info->pbi_bridge_type) { Loading @@ -38,14 +38,14 @@ void pcireg_control_bit_clr(struct pcibus_info *pcibus_info, uint64_t bits) default: panic ("pcireg_control_bit_clr: unknown bridgetype bridge 0x%p", (void *)ptr); ptr); } } } void pcireg_control_bit_set(struct pcibus_info *pcibus_info, uint64_t bits) { union br_ptr *ptr = (union br_ptr *)pcibus_info->pbi_buscommon.bs_base; union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base; if (pcibus_info) { switch (pcibus_info->pbi_bridge_type) { Loading @@ -58,7 +58,7 @@ void pcireg_control_bit_set(struct pcibus_info *pcibus_info, uint64_t bits) default: panic ("pcireg_control_bit_set: unknown bridgetype bridge 0x%p", (void *)ptr); ptr); } } } Loading @@ -68,7 +68,7 @@ void pcireg_control_bit_set(struct pcibus_info *pcibus_info, uint64_t bits) */ uint64_t pcireg_tflush_get(struct pcibus_info *pcibus_info) { union br_ptr *ptr = (union br_ptr *)pcibus_info->pbi_buscommon.bs_base; union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base; uint64_t ret = 0; if (pcibus_info) { Loading @@ -82,7 +82,7 @@ uint64_t pcireg_tflush_get(struct pcibus_info *pcibus_info) default: panic ("pcireg_tflush_get: unknown bridgetype bridge 0x%p", (void *)ptr); ptr); } } Loading @@ -98,7 +98,7 @@ uint64_t pcireg_tflush_get(struct pcibus_info *pcibus_info) */ uint64_t pcireg_intr_status_get(struct pcibus_info * pcibus_info) { union br_ptr *ptr = (union br_ptr *)pcibus_info->pbi_buscommon.bs_base; union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base; uint64_t ret = 0; if (pcibus_info) { Loading @@ -112,7 +112,7 @@ uint64_t pcireg_intr_status_get(struct pcibus_info * pcibus_info) default: panic ("pcireg_intr_status_get: unknown bridgetype bridge 0x%p", (void *)ptr); ptr); } } return ret; Loading @@ -123,7 +123,7 @@ uint64_t pcireg_intr_status_get(struct pcibus_info * pcibus_info) */ void pcireg_intr_enable_bit_clr(struct pcibus_info *pcibus_info, uint64_t bits) { union br_ptr *ptr = (union br_ptr *)pcibus_info->pbi_buscommon.bs_base; union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base; if (pcibus_info) { switch (pcibus_info->pbi_bridge_type) { Loading @@ -136,14 +136,14 @@ void pcireg_intr_enable_bit_clr(struct pcibus_info *pcibus_info, uint64_t bits) default: panic ("pcireg_intr_enable_bit_clr: unknown bridgetype bridge 0x%p", (void *)ptr); ptr); } } } void pcireg_intr_enable_bit_set(struct pcibus_info *pcibus_info, uint64_t bits) { union br_ptr *ptr = (union br_ptr *)pcibus_info->pbi_buscommon.bs_base; union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base; if (pcibus_info) { switch (pcibus_info->pbi_bridge_type) { Loading @@ -156,7 +156,7 @@ void pcireg_intr_enable_bit_set(struct pcibus_info *pcibus_info, uint64_t bits) default: panic ("pcireg_intr_enable_bit_set: unknown bridgetype bridge 0x%p", (void *)ptr); ptr); } } } Loading @@ -167,7 +167,7 @@ void pcireg_intr_enable_bit_set(struct pcibus_info *pcibus_info, uint64_t bits) void pcireg_intr_addr_addr_set(struct pcibus_info *pcibus_info, int int_n, uint64_t addr) { union br_ptr *ptr = (union br_ptr *)pcibus_info->pbi_buscommon.bs_base; union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base; if (pcibus_info) { switch (pcibus_info->pbi_bridge_type) { Loading @@ -186,7 +186,7 @@ void pcireg_intr_addr_addr_set(struct pcibus_info *pcibus_info, int int_n, default: panic ("pcireg_intr_addr_addr_get: unknown bridgetype bridge 0x%p", (void *)ptr); ptr); } } } Loading @@ -196,7 +196,7 @@ void pcireg_intr_addr_addr_set(struct pcibus_info *pcibus_info, int int_n, */ void pcireg_force_intr_set(struct pcibus_info *pcibus_info, int int_n) { union br_ptr *ptr = (union br_ptr *)pcibus_info->pbi_buscommon.bs_base; union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base; if (pcibus_info) { switch (pcibus_info->pbi_bridge_type) { Loading @@ -209,7 +209,7 @@ void pcireg_force_intr_set(struct pcibus_info *pcibus_info, int int_n) default: panic ("pcireg_force_intr_set: unknown bridgetype bridge 0x%p", (void *)ptr); ptr); } } } Loading @@ -219,7 +219,7 @@ void pcireg_force_intr_set(struct pcibus_info *pcibus_info, int int_n) */ uint64_t pcireg_wrb_flush_get(struct pcibus_info *pcibus_info, int device) { union br_ptr *ptr = (union br_ptr *)pcibus_info->pbi_buscommon.bs_base; union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base; uint64_t ret = 0; if (pcibus_info) { Loading @@ -233,7 +233,7 @@ uint64_t pcireg_wrb_flush_get(struct pcibus_info *pcibus_info, int device) __sn_readq_relaxed(&ptr->pic.p_wr_req_buf[device]); break; default: panic("pcireg_wrb_flush_get: unknown bridgetype bridge 0x%p", (void *)ptr); panic("pcireg_wrb_flush_get: unknown bridgetype bridge 0x%p", ptr); } } Loading @@ -244,7 +244,7 @@ uint64_t pcireg_wrb_flush_get(struct pcibus_info *pcibus_info, int device) void pcireg_int_ate_set(struct pcibus_info *pcibus_info, int ate_index, uint64_t val) { union br_ptr *ptr = (union br_ptr *)pcibus_info->pbi_buscommon.bs_base; union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base; if (pcibus_info) { switch (pcibus_info->pbi_bridge_type) { Loading @@ -257,15 +257,15 @@ void pcireg_int_ate_set(struct pcibus_info *pcibus_info, int ate_index, default: panic ("pcireg_int_ate_set: unknown bridgetype bridge 0x%p", (void *)ptr); ptr); } } } uint64_t *pcireg_int_ate_addr(struct pcibus_info *pcibus_info, int ate_index) uint64_t __iomem *pcireg_int_ate_addr(struct pcibus_info *pcibus_info, int ate_index) { union br_ptr *ptr = (union br_ptr *)pcibus_info->pbi_buscommon.bs_base; uint64_t *ret = (uint64_t *) 0; union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base; uint64_t __iomem *ret = NULL; if (pcibus_info) { switch (pcibus_info->pbi_bridge_type) { Loading @@ -278,7 +278,7 @@ uint64_t *pcireg_int_ate_addr(struct pcibus_info *pcibus_info, int ate_index) default: panic ("pcireg_int_ate_addr: unknown bridgetype bridge 0x%p", (void *)ptr); ptr); } } return ret; Loading
arch/ia64/sn/pci/tioca_provider.c +6 −6 Original line number Diff line number Diff line Loading @@ -38,10 +38,10 @@ tioca_gart_init(struct tioca_kernel *tioca_kern) uint64_t offset; struct page *tmp; struct tioca_common *tioca_common; struct tioca *ca_base; struct tioca __iomem *ca_base; tioca_common = tioca_kern->ca_common; ca_base = (struct tioca *)tioca_common->ca_common.bs_base; ca_base = (struct tioca __iomem *)tioca_common->ca_common.bs_base; if (list_empty(tioca_kern->ca_devices)) return 0; Loading Loading @@ -215,7 +215,7 @@ tioca_fastwrite_enable(struct tioca_kernel *tioca_kern) { int cap_ptr; uint32_t reg; struct tioca *tioca_base; struct tioca __iomem *tioca_base; struct pci_dev *pdev; struct tioca_common *common; Loading Loading @@ -257,7 +257,7 @@ tioca_fastwrite_enable(struct tioca_kernel *tioca_kern) * Set ca's fw to match */ tioca_base = (struct tioca *)common->ca_common.bs_base; tioca_base = (struct tioca __iomem*)common->ca_common.bs_base; __sn_setq_relaxed(&tioca_base->ca_control1, CA_AGP_FW_ENABLE); } Loading Loading @@ -322,7 +322,7 @@ static uint64_t tioca_dma_d48(struct pci_dev *pdev, uint64_t paddr) { struct tioca_common *tioca_common; struct tioca *ca_base; struct tioca __iomem *ca_base; uint64_t ct_addr; dma_addr_t bus_addr; uint32_t node_upper; Loading @@ -330,7 +330,7 @@ tioca_dma_d48(struct pci_dev *pdev, uint64_t paddr) struct pcidev_info *pcidev_info = SN_PCIDEV_INFO(pdev); tioca_common = (struct tioca_common *)pcidev_info->pdi_pcibus_info; ca_base = (struct tioca *)tioca_common->ca_common.bs_base; ca_base = (struct tioca __iomem *)tioca_common->ca_common.bs_base; ct_addr = PHYS_TO_TIODMA(paddr); if (!ct_addr) Loading