Commit ace1297f authored by Haojian Zhuang's avatar Haojian Zhuang
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Documentation: update docs for mmp dt 



Append interrupt controller and timer document for mmp. Updates
documents for gpio and i2c.

Signed-off-by: default avatarHaojian Zhuang <haojian.zhuang@gmail.com>
Acked-by: default avatarArnd Bergmann <arnd@arndb.de>
parent ff290fc3

Documentation/devicetree/bindings/arm/mrvl/intc.txt

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* Marvell MMP Interrupt controller



Required properties:

- compatible : Should be "mrvl,mmp-intc", "mrvl,mmp2-intc" or

  "mrvl,mmp2-mux-intc"

- reg : Address and length of the register set of the interrupt controller.

  If the interrupt controller is intc, address and length means the range

  of the whold interrupt controller. If the interrupt controller is mux-intc,

  address and length means one register. Since address of mux-intc is in the

  range of intc. mux-intc is secondary interrupt controller.

- reg-names : Name of the register set of the interrupt controller. It's

  only required in mux-intc interrupt controller.

- interrupts : Should be the port interrupt shared by mux interrupts. It's

  only required in mux-intc interrupt controller.

- interrupt-controller : Identifies the node as an interrupt controller.

- #interrupt-cells : Specifies the number of cells needed to encode an

  interrupt source.

- mrvl,intc-nr-irqs : Specifies the number of interrupts in the interrupt

  controller.

- mrvl,clr-mfp-irq : Specifies the interrupt that needs to clear MFP edge

  detection first.



Example:

	intc: interrupt-controller@d4282000 {

		compatible = "mrvl,mmp2-intc";

		interrupt-controller;

		#interrupt-cells = <1>;

		reg = <0xd4282000 0x1000>;

		mrvl,intc-nr-irqs = <64>;

	};



	intcmux4@d4282150 {

		compatible = "mrvl,mmp2-mux-intc";

		interrupts = <4>;

		interrupt-controller;

		#interrupt-cells = <1>;

		reg = <0x150 0x4>, <0x168 0x4>;

		reg-names = "mux status", "mux mask";

		mrvl,intc-nr-irqs = <2>;

	};

Documentation/devicetree/bindings/arm/mrvl.txt→Documentation/devicetree/bindings/arm/mrvl/mrvl.txt

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@@ -4,3 +4,11 @@ Marvell Platforms Device Tree Bindings 
PXA168 Aspenite Board

Required root node properties:

	- compatible = "mrvl,pxa168-aspenite", "mrvl,pxa168";



PXA910 DKB Board

Required root node properties:

	- compatible = "mrvl,pxa910-dkb";



MMP2 Brownstone Board

Required root node properties:

	- compatible = "mrvl,mmp2-brownstone";

Documentation/devicetree/bindings/arm/mrvl/timer.txt

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* Marvell MMP Timer controller



Required properties:

- compatible : Should be "mrvl,mmp-timer".

- reg : Address and length of the register set of timer controller.

- interrupts : Should be the interrupt number.



Example:

	timer0: timer@d4014000 {

		compatible = "mrvl,mmp-timer";

		reg = <0xd4014000 0x100>;

		interrupts = <13>;

	};

Documentation/devicetree/bindings/gpio/mrvl-gpio.txt

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@@ -3,19 +3,25 @@ 
Required properties:

- compatible : Should be "mrvl,pxa-gpio" or "mrvl,mmp-gpio"

- reg : Address and length of the register set for the device

- interrupts : Should be the port interrupt shared by all gpio pins, if

- interrupt-name : Should be the name of irq resource.

  one number.

- interrupts : Should be the port interrupt shared by all gpio pins.

  There're three gpio interrupts in arch-pxa, and they're gpio0,

  gpio1 and gpio_mux. There're only one gpio interrupt in arch-mmp,

  gpio_mux.

- interrupt-name : Should be the name of irq resource. Each interrupt

  binds its interrupt-name.

- interrupt-controller : Identifies the node as an interrupt controller.

- #interrupt-cells: Specifies the number of cells needed to encode an

  interrupt source.

- gpio-controller : Marks the device node as a gpio controller.

- #gpio-cells : Should be one.  It is the pin number.



Example:



	gpio: gpio@d4019000 {

		compatible = "mrvl,mmp-gpio", "mrvl,pxa-gpio";

		compatible = "mrvl,mmp-gpio";

		reg = <0xd4019000 0x1000>;

		interrupts = <49>, <17>, <18>;

		interrupt-name = "gpio_mux", "gpio0", "gpio1";

		interrupts = <49>;

		interrupt-name = "gpio_mux";

		gpio-controller;

		#gpio-cells = <1>;

		interrupt-controller;

Documentation/devicetree/bindings/i2c/mrvl-i2c.txt

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@@ -3,34 +3,31 @@ 
Required properties :



 - reg : Offset and length of the register set for the device

 - compatible : should be "mrvl,mmp-twsi" where CHIP is the name of a

 - compatible : should be "mrvl,mmp-twsi" where mmp is the name of a

   compatible processor, e.g. pxa168, pxa910, mmp2, mmp3.

   For the pxa2xx/pxa3xx, an additional node "mrvl,pxa-i2c" is required

   as shown in the example below.



Recommended properties :



 - interrupts : <a b> where a is the interrupt number and b is a

   field that represents an encoding of the sense and level

   information for the interrupt.  This should be encoded based on

   the information in section 2) depending on the type of interrupt

   controller you have.

 - interrupts : the interrupt number

 - interrupt-parent : the phandle for the interrupt controller that

   services interrupts for this device.

   services interrupts for this device. If the parent is the default

   interrupt controller in device tree, it could be ignored.

 - mrvl,i2c-polling : Disable interrupt of i2c controller. Polling

   status register of i2c controller instead.

 - mrvl,i2c-fast-mode : Enable fast mode of i2c controller.



Examples:

	twsi1: i2c@d4011000 {

		compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c";

		compatible = "mrvl,mmp-twsi";

		reg = <0xd4011000 0x1000>;

		interrupts = <7>;

		mrvl,i2c-fast-mode;

	};

	

	twsi2: i2c@d4025000 {

		compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c";

		compatible = "mrvl,mmp-twsi";

		reg = <0xd4025000 0x1000>;

		interrupts = <58>;

	};