Loading drivers/gpu/drm/nouveau/Makefile +1 −0 Original line number Diff line number Diff line Loading @@ -165,6 +165,7 @@ nouveau-y += core/engine/disp/hdanvd0.o nouveau-y += core/engine/disp/hdminv84.o nouveau-y += core/engine/disp/hdminva3.o nouveau-y += core/engine/disp/hdminvd0.o nouveau-y += core/engine/disp/piornv50.o nouveau-y += core/engine/disp/sornv50.o nouveau-y += core/engine/disp/sornv94.o nouveau-y += core/engine/disp/sornvd0.o Loading drivers/gpu/drm/nouveau/core/engine/disp/dport.h +1 −0 Original line number Diff line number Diff line Loading @@ -70,6 +70,7 @@ struct nouveau_dp_func { extern const struct nouveau_dp_func nv94_sor_dp_func; extern const struct nouveau_dp_func nvd0_sor_dp_func; extern const struct nouveau_dp_func nv50_pior_dp_func; int nouveau_dp_train(struct nouveau_disp *, const struct nouveau_dp_func *, struct dcb_output *, int, u32); Loading drivers/gpu/drm/nouveau/core/engine/disp/nv50.c +6 −0 Original line number Diff line number Diff line Loading @@ -678,6 +678,9 @@ nv50_disp_base_omthds[] = { { SOR_MTHD(NV50_DISP_SOR_LVDS_SCRIPT) , nv50_sor_mthd }, { DAC_MTHD(NV50_DISP_DAC_PWR) , nv50_dac_mthd }, { DAC_MTHD(NV50_DISP_DAC_LOAD) , nv50_dac_mthd }, { PIOR_MTHD(NV50_DISP_PIOR_PWR) , nv50_pior_mthd }, { PIOR_MTHD(NV50_DISP_PIOR_TMDS_PWR) , nv50_pior_mthd }, { PIOR_MTHD(NV50_DISP_PIOR_DP_PWR) , nv50_pior_mthd }, {}, }; Loading Loading @@ -1227,9 +1230,12 @@ nv50_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, priv->head.nr = 2; priv->dac.nr = 3; priv->sor.nr = 2; priv->pior.nr = 3; priv->dac.power = nv50_dac_power; priv->dac.sense = nv50_dac_sense; priv->sor.power = nv50_sor_power; priv->pior.power = nv50_pior_power; priv->pior.dp = &nv50_pior_dp_func; return 0; } Loading drivers/gpu/drm/nouveau/core/engine/disp/nv50.h +11 −0 Original line number Diff line number Diff line Loading @@ -35,6 +35,12 @@ struct nv50_disp_priv { u32 lvdsconf; const struct nouveau_dp_func *dp; } sor; struct { int nr; int (*power)(struct nv50_disp_priv *, int ext, u32 data); u8 type[3]; const struct nouveau_dp_func *dp; } pior; }; #define DAC_MTHD(n) (n), (n) + 0x03 Loading Loading @@ -73,6 +79,11 @@ int nvd0_sor_dp_lnkctl(struct nv50_disp_priv *, int, int, int, u16, u16, u32, int nvd0_sor_dp_drvctl(struct nv50_disp_priv *, int, int, int, u16, u16, u32, struct dcb_output *); #define PIOR_MTHD(n) (n), (n) + 0x03 int nv50_pior_mthd(struct nouveau_object *, u32, void *, u32); int nv50_pior_power(struct nv50_disp_priv *, int, u32); struct nv50_disp_base { struct nouveau_parent base; struct nouveau_ramht *ramht; Loading drivers/gpu/drm/nouveau/core/engine/disp/nv84.c +6 −0 Original line number Diff line number Diff line Loading @@ -46,6 +46,9 @@ nv84_disp_base_omthds[] = { { SOR_MTHD(NV50_DISP_SOR_LVDS_SCRIPT) , nv50_sor_mthd }, { DAC_MTHD(NV50_DISP_DAC_PWR) , nv50_dac_mthd }, { DAC_MTHD(NV50_DISP_DAC_LOAD) , nv50_dac_mthd }, { PIOR_MTHD(NV50_DISP_PIOR_PWR) , nv50_pior_mthd }, { PIOR_MTHD(NV50_DISP_PIOR_TMDS_PWR) , nv50_pior_mthd }, { PIOR_MTHD(NV50_DISP_PIOR_DP_PWR) , nv50_pior_mthd }, {}, }; Loading Loading @@ -77,10 +80,13 @@ nv84_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, priv->head.nr = 2; priv->dac.nr = 3; priv->sor.nr = 2; priv->pior.nr = 3; priv->dac.power = nv50_dac_power; priv->dac.sense = nv50_dac_sense; priv->sor.power = nv50_sor_power; priv->sor.hdmi = nv84_hdmi_ctrl; priv->pior.power = nv50_pior_power; priv->pior.dp = &nv50_pior_dp_func; return 0; } Loading Loading
drivers/gpu/drm/nouveau/Makefile +1 −0 Original line number Diff line number Diff line Loading @@ -165,6 +165,7 @@ nouveau-y += core/engine/disp/hdanvd0.o nouveau-y += core/engine/disp/hdminv84.o nouveau-y += core/engine/disp/hdminva3.o nouveau-y += core/engine/disp/hdminvd0.o nouveau-y += core/engine/disp/piornv50.o nouveau-y += core/engine/disp/sornv50.o nouveau-y += core/engine/disp/sornv94.o nouveau-y += core/engine/disp/sornvd0.o Loading
drivers/gpu/drm/nouveau/core/engine/disp/dport.h +1 −0 Original line number Diff line number Diff line Loading @@ -70,6 +70,7 @@ struct nouveau_dp_func { extern const struct nouveau_dp_func nv94_sor_dp_func; extern const struct nouveau_dp_func nvd0_sor_dp_func; extern const struct nouveau_dp_func nv50_pior_dp_func; int nouveau_dp_train(struct nouveau_disp *, const struct nouveau_dp_func *, struct dcb_output *, int, u32); Loading
drivers/gpu/drm/nouveau/core/engine/disp/nv50.c +6 −0 Original line number Diff line number Diff line Loading @@ -678,6 +678,9 @@ nv50_disp_base_omthds[] = { { SOR_MTHD(NV50_DISP_SOR_LVDS_SCRIPT) , nv50_sor_mthd }, { DAC_MTHD(NV50_DISP_DAC_PWR) , nv50_dac_mthd }, { DAC_MTHD(NV50_DISP_DAC_LOAD) , nv50_dac_mthd }, { PIOR_MTHD(NV50_DISP_PIOR_PWR) , nv50_pior_mthd }, { PIOR_MTHD(NV50_DISP_PIOR_TMDS_PWR) , nv50_pior_mthd }, { PIOR_MTHD(NV50_DISP_PIOR_DP_PWR) , nv50_pior_mthd }, {}, }; Loading Loading @@ -1227,9 +1230,12 @@ nv50_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, priv->head.nr = 2; priv->dac.nr = 3; priv->sor.nr = 2; priv->pior.nr = 3; priv->dac.power = nv50_dac_power; priv->dac.sense = nv50_dac_sense; priv->sor.power = nv50_sor_power; priv->pior.power = nv50_pior_power; priv->pior.dp = &nv50_pior_dp_func; return 0; } Loading
drivers/gpu/drm/nouveau/core/engine/disp/nv50.h +11 −0 Original line number Diff line number Diff line Loading @@ -35,6 +35,12 @@ struct nv50_disp_priv { u32 lvdsconf; const struct nouveau_dp_func *dp; } sor; struct { int nr; int (*power)(struct nv50_disp_priv *, int ext, u32 data); u8 type[3]; const struct nouveau_dp_func *dp; } pior; }; #define DAC_MTHD(n) (n), (n) + 0x03 Loading Loading @@ -73,6 +79,11 @@ int nvd0_sor_dp_lnkctl(struct nv50_disp_priv *, int, int, int, u16, u16, u32, int nvd0_sor_dp_drvctl(struct nv50_disp_priv *, int, int, int, u16, u16, u32, struct dcb_output *); #define PIOR_MTHD(n) (n), (n) + 0x03 int nv50_pior_mthd(struct nouveau_object *, u32, void *, u32); int nv50_pior_power(struct nv50_disp_priv *, int, u32); struct nv50_disp_base { struct nouveau_parent base; struct nouveau_ramht *ramht; Loading
drivers/gpu/drm/nouveau/core/engine/disp/nv84.c +6 −0 Original line number Diff line number Diff line Loading @@ -46,6 +46,9 @@ nv84_disp_base_omthds[] = { { SOR_MTHD(NV50_DISP_SOR_LVDS_SCRIPT) , nv50_sor_mthd }, { DAC_MTHD(NV50_DISP_DAC_PWR) , nv50_dac_mthd }, { DAC_MTHD(NV50_DISP_DAC_LOAD) , nv50_dac_mthd }, { PIOR_MTHD(NV50_DISP_PIOR_PWR) , nv50_pior_mthd }, { PIOR_MTHD(NV50_DISP_PIOR_TMDS_PWR) , nv50_pior_mthd }, { PIOR_MTHD(NV50_DISP_PIOR_DP_PWR) , nv50_pior_mthd }, {}, }; Loading Loading @@ -77,10 +80,13 @@ nv84_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, priv->head.nr = 2; priv->dac.nr = 3; priv->sor.nr = 2; priv->pior.nr = 3; priv->dac.power = nv50_dac_power; priv->dac.sense = nv50_dac_sense; priv->sor.power = nv50_sor_power; priv->sor.hdmi = nv84_hdmi_ctrl; priv->pior.power = nv50_pior_power; priv->pior.dp = &nv50_pior_dp_func; return 0; } Loading