Commit 9ba87450 authored by Tony Lindgren's avatar Tony Lindgren
Browse files

Merge branch 'for_2.6.34_4f4e65_a' of git://git.pwsan.com/linux-2.6 into omap-for-linus

parents 4f4e65d2 98fa3d8a

arch/arm/mach-omap1/clock.c

+0 −6
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@@ -52,12 +52,6 @@ const struct clkops clkops_dummy = { 
	.disable	= clk_omap1_dummy_disable,

};



/* XXX can be replaced with a fixed_divisor_recalc */

unsigned long omap1_watchdog_recalc(struct clk *clk)

{

	return clk->parent->rate / 14;

}



unsigned long omap1_uart_recalc(struct clk *clk)

{

	unsigned int val = __raw_readl(clk->enable_reg);

arch/arm/mach-omap1/clock_data.c

+2 −1
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@@ -149,7 +149,8 @@ static struct arm_idlect1_clk armwdt_ck = { 
		.flags		= CLOCK_IDLE_CONTROL,

		.enable_reg	= OMAP1_IO_ADDRESS(ARM_IDLECT2),

		.enable_bit	= EN_WDTCK,

		.recalc		= &omap1_watchdog_recalc,

		.fixed_div	= 14,

		.recalc		= &omap_fixed_divisor_recalc,

	},

	.idlect_shift	= 0,

};

arch/arm/mach-omap2/Makefile

+14 −6
Original line number Diff line number Diff line
@@ -6,14 +6,22 @@ 
obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o



omap-2-3-common				= irq.o sdrc.o omap_hwmod.o

omap-3-4-common				= dpll.o

omap-3-4-common				= dpll3xxx.o

prcm-common				= prcm.o powerdomain.o

clock-common				= clock.o clock_common_data.o clockdomain.o



obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(clock-common)

clock-common				= clock.o clock_common_data.o \

					  clockdomain.o clkt_dpll.o \

					  clkt_clksel.o

clock-omap2xxx				= clkt2xxx_dpllcore.o \

					  clkt2xxx_virt_prcm_set.o \

					  clkt2xxx_apll.o clkt2xxx_osc.o \

					  clkt2xxx_sys.o

clock-omap3xxx				= clkt34xx_dpll3m2.o



obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(clock-common) \

			    $(clock-omap2xxx)

obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(clock-common) \

			    $(omap-3-4-common)

obj-$(CONFIG_ARCH_OMAP4) += $(omap-3-4-common) prcm.o clock.o

			    $(omap-3-4-common) $(clock-omap3xxx)

obj-$(CONFIG_ARCH_OMAP4) += $(omap-3-4-common) $(prcm-common) $(clock-common)



obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o

arch/arm/mach-omap2/clkt2xxx_apll.c

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/*

 * OMAP2xxx APLL clock control functions

 *

 * Copyright (C) 2005-2008 Texas Instruments, Inc.

 * Copyright (C) 2004-2010 Nokia Corporation

 *

 * Contacts:

 * Richard Woodruff <r-woodruff2@ti.com>

 * Paul Walmsley

 *

 * Based on earlier work by Tuukka Tikkanen, Tony Lindgren,

 * Gordon McNutt and RidgeRun, Inc.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 */

#undef DEBUG



#include <linux/kernel.h>

#include <linux/clk.h>

#include <linux/io.h>



#include <plat/clock.h>

#include <plat/prcm.h>



#include "clock.h"

#include "clock2xxx.h"

#include "cm.h"

#include "cm-regbits-24xx.h"



/* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */

#define EN_APLL_STOPPED			0

#define EN_APLL_LOCKED			3



/* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */

#define APLLS_CLKIN_19_2MHZ		0

#define APLLS_CLKIN_13MHZ		2

#define APLLS_CLKIN_12MHZ		3



/* Private functions */



/* Enable an APLL if off */

static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask)

{

	u32 cval, apll_mask;



	apll_mask = EN_APLL_LOCKED << clk->enable_bit;



	cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);



	if ((cval & apll_mask) == apll_mask)

		return 0;   /* apll already enabled */



	cval &= ~apll_mask;

	cval |= apll_mask;

	cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);



	omap2_cm_wait_idlest(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), status_mask,

			     clk->name);



	/*

	 * REVISIT: Should we return an error code if omap2_wait_clock_ready()

	 * fails?

	 */

	return 0;

}



static int omap2_clk_apll96_enable(struct clk *clk)

{

	return omap2_clk_apll_enable(clk, OMAP24XX_ST_96M_APLL);

}



static int omap2_clk_apll54_enable(struct clk *clk)

{

	return omap2_clk_apll_enable(clk, OMAP24XX_ST_54M_APLL);

}



/* Stop APLL */

static void omap2_clk_apll_disable(struct clk *clk)

{

	u32 cval;



	cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);

	cval &= ~(EN_APLL_LOCKED << clk->enable_bit);

	cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);

}



/* Public data */



const struct clkops clkops_apll96 = {

	.enable		= omap2_clk_apll96_enable,

	.disable	= omap2_clk_apll_disable,

};



const struct clkops clkops_apll54 = {

	.enable		= omap2_clk_apll54_enable,

	.disable	= omap2_clk_apll_disable,

};



/* Public functions */



u32 omap2xxx_get_apll_clkin(void)

{

	u32 aplls, srate = 0;



	aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);

	aplls &= OMAP24XX_APLLS_CLKIN_MASK;

	aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;



	if (aplls == APLLS_CLKIN_19_2MHZ)

		srate = 19200000;

	else if (aplls == APLLS_CLKIN_13MHZ)

		srate = 13000000;

	else if (aplls == APLLS_CLKIN_12MHZ)

		srate = 12000000;



	return srate;

}

arch/arm/mach-omap2/clkt2xxx_dpllcore.c

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/*

 * DPLL + CORE_CLK composite clock functions

 *

 * Copyright (C) 2005-2008 Texas Instruments, Inc.

 * Copyright (C) 2004-2010 Nokia Corporation

 *

 * Contacts:

 * Richard Woodruff <r-woodruff2@ti.com>

 * Paul Walmsley

 *

 * Based on earlier work by Tuukka Tikkanen, Tony Lindgren,

 * Gordon McNutt and RidgeRun, Inc.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 *

 * XXX The DPLL and CORE clocks should be split into two separate clock

 * types.

 */

#undef DEBUG



#include <linux/kernel.h>

#include <linux/errno.h>

#include <linux/clk.h>

#include <linux/io.h>



#include <plat/clock.h>

#include <plat/sram.h>

#include <plat/sdrc.h>



#include "clock.h"

#include "clock2xxx.h"

#include "opp2xxx.h"

#include "cm.h"

#include "cm-regbits-24xx.h"



/* #define DOWN_VARIABLE_DPLL 1 */		/* Experimental */



/**

 * omap2xxx_clk_get_core_rate - return the CORE_CLK rate

 * @clk: pointer to the combined dpll_ck + core_ck (currently "dpll_ck")

 *

 * Returns the CORE_CLK rate.  CORE_CLK can have one of three rate

 * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz

 * (the latter is unusual).  This currently should be called with

 * struct clk *dpll_ck, which is a composite clock of dpll_ck and

 * core_ck.

 */

unsigned long omap2xxx_clk_get_core_rate(struct clk *clk)

{

	long long core_clk;

	u32 v;



	core_clk = omap2_get_dpll_rate(clk);



	v = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);

	v &= OMAP24XX_CORE_CLK_SRC_MASK;



	if (v == CORE_CLK_SRC_32K)

		core_clk = 32768;

	else

		core_clk *= v;



	return core_clk;

}



/*

 * Uses the current prcm set to tell if a rate is valid.

 * You can go slower, but not faster within a given rate set.

 */

static long omap2_dpllcore_round_rate(unsigned long target_rate)

{

	u32 high, low, core_clk_src;



	core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);

	core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;



	if (core_clk_src == CORE_CLK_SRC_DPLL) {	/* DPLL clockout */

		high = curr_prcm_set->dpll_speed * 2;

		low = curr_prcm_set->dpll_speed;

	} else {				/* DPLL clockout x 2 */

		high = curr_prcm_set->dpll_speed;

		low = curr_prcm_set->dpll_speed / 2;

	}



#ifdef DOWN_VARIABLE_DPLL

	if (target_rate > high)

		return high;

	else

		return target_rate;

#else

	if (target_rate > low)

		return high;

	else

		return low;

#endif



}



unsigned long omap2_dpllcore_recalc(struct clk *clk)

{

	return omap2xxx_clk_get_core_rate(clk);

}



int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)

{

	u32 cur_rate, low, mult, div, valid_rate, done_rate;

	u32 bypass = 0;

	struct prcm_config tmpset;

	const struct dpll_data *dd;



	cur_rate = omap2xxx_clk_get_core_rate(dclk);

	mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);

	mult &= OMAP24XX_CORE_CLK_SRC_MASK;



	if ((rate == (cur_rate / 2)) && (mult == 2)) {

		omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);

	} else if ((rate == (cur_rate * 2)) && (mult == 1)) {

		omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);

	} else if (rate != cur_rate) {

		valid_rate = omap2_dpllcore_round_rate(rate);

		if (valid_rate != rate)

			return -EINVAL;



		if (mult == 1)

			low = curr_prcm_set->dpll_speed;

		else

			low = curr_prcm_set->dpll_speed / 2;



		dd = clk->dpll_data;

		if (!dd)

			return -EINVAL;



		tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg);

		tmpset.cm_clksel1_pll &= ~(dd->mult_mask |

					   dd->div1_mask);

		div = ((curr_prcm_set->xtal_speed / 1000000) - 1);

		tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);

		tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;

		if (rate > low) {

			tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2;

			mult = ((rate / 2) / 1000000);

			done_rate = CORE_CLK_SRC_DPLL_X2;

		} else {

			tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL;

			mult = (rate / 1000000);

			done_rate = CORE_CLK_SRC_DPLL;

		}

		tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask));

		tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask));



		/* Worst case */

		tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS;



		if (rate == curr_prcm_set->xtal_speed)	/* If asking for 1-1 */

			bypass = 1;



		/* For omap2xxx_sdrc_init_params() */

		omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);



		/* Force dll lock mode */

		omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,

			       bypass);



		/* Errata: ret dll entry state */

		omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());

		omap2xxx_sdrc_reprogram(done_rate, 0);

	}



	return 0;

}