Commit 8e1c072f authored by Igor Russkikh's avatar Igor Russkikh Committed by David S. Miller
Browse files

net: aquantia: Prepend hw access functions declarations with prefix 



Internal functions for registers and HW access were not prefixed.
This introduce noise in global kernel symbols. Here we add explicit prefix
'hw_atl' to all the HW access layer functions.
Alignment and styling were fixed as well.

Signed-off-by: default avatarIgor Russkikh <igor.russkikh@aquantia.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 3230d011

drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c

+161 −152
Original line number Diff line number Diff line
@@ -62,24 +62,24 @@ static int hw_atl_a0_hw_reset(struct aq_hw_s *self) 
{

	int err = 0;



	glb_glb_reg_res_dis_set(self, 1U);

	pci_pci_reg_res_dis_set(self, 0U);

	rx_rx_reg_res_dis_set(self, 0U);

	tx_tx_reg_res_dis_set(self, 0U);

	hw_atl_glb_glb_reg_res_dis_set(self, 1U);

	hw_atl_pci_pci_reg_res_dis_set(self, 0U);

	hw_atl_rx_rx_reg_res_dis_set(self, 0U);

	hw_atl_tx_tx_reg_res_dis_set(self, 0U);



	HW_ATL_FLUSH();

	glb_soft_res_set(self, 1);

	hw_atl_glb_soft_res_set(self, 1);



	/* check 10 times by 1ms */

	AQ_HW_WAIT_FOR(glb_soft_res_get(self) == 0, 1000U, 10U);

	AQ_HW_WAIT_FOR(hw_atl_glb_soft_res_get(self) == 0, 1000U, 10U);

	if (err < 0)

		goto err_exit;



	itr_irq_reg_res_dis_set(self, 0U);

	itr_res_irq_set(self, 1U);

	hw_atl_itr_irq_reg_res_dis_set(self, 0U);

	hw_atl_itr_res_irq_set(self, 1U);



	/* check 10 times by 1ms */

	AQ_HW_WAIT_FOR(itr_res_irq_get(self) == 0, 1000U, 10U);

	AQ_HW_WAIT_FOR(hw_atl_itr_res_irq_get(self) == 0, 1000U, 10U);

	if (err < 0)

		goto err_exit;
@@ -99,30 +99,32 @@ static int hw_atl_a0_hw_qos_set(struct aq_hw_s *self) 
	bool is_rx_flow_control = false;



	/* TPS Descriptor rate init */

	tps_tx_pkt_shed_desc_rate_curr_time_res_set(self, 0x0U);

	tps_tx_pkt_shed_desc_rate_lim_set(self, 0xA);

	hw_atl_tps_tx_pkt_shed_desc_rate_curr_time_res_set(self, 0x0U);

	hw_atl_tps_tx_pkt_shed_desc_rate_lim_set(self, 0xA);



	/* TPS VM init */

	tps_tx_pkt_shed_desc_vm_arb_mode_set(self, 0U);

	hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(self, 0U);



	/* TPS TC credits init */

	tps_tx_pkt_shed_desc_tc_arb_mode_set(self, 0U);

	tps_tx_pkt_shed_data_arb_mode_set(self, 0U);

	hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(self, 0U);

	hw_atl_tps_tx_pkt_shed_data_arb_mode_set(self, 0U);



	tps_tx_pkt_shed_tc_data_max_credit_set(self, 0xFFF, 0U);

	tps_tx_pkt_shed_tc_data_weight_set(self, 0x64, 0U);

	tps_tx_pkt_shed_desc_tc_max_credit_set(self, 0x50, 0U);

	tps_tx_pkt_shed_desc_tc_weight_set(self, 0x1E, 0U);

	hw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(self, 0xFFF, 0U);

	hw_atl_tps_tx_pkt_shed_tc_data_weight_set(self, 0x64, 0U);

	hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(self, 0x50, 0U);

	hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(self, 0x1E, 0U);



	/* Tx buf size */

	buff_size = HW_ATL_A0_TXBUF_MAX;



	tpb_tx_pkt_buff_size_per_tc_set(self, buff_size, tc);

	tpb_tx_buff_hi_threshold_per_tc_set(self,

					    (buff_size * (1024 / 32U) * 66U) /

	hw_atl_tpb_tx_pkt_buff_size_per_tc_set(self, buff_size, tc);

	hw_atl_tpb_tx_buff_hi_threshold_per_tc_set(self,

						   (buff_size *

						   (1024 / 32U) * 66U) /

						   100U, tc);

	tpb_tx_buff_lo_threshold_per_tc_set(self,

					    (buff_size * (1024 / 32U) * 50U) /

	hw_atl_tpb_tx_buff_lo_threshold_per_tc_set(self,

						   (buff_size *

						   (1024 / 32U) * 50U) /

						   100U, tc);



	/* QoS Rx buf size per TC */
@@ -130,20 +132,20 @@ static int hw_atl_a0_hw_qos_set(struct aq_hw_s *self) 
	is_rx_flow_control = (AQ_NIC_FC_RX & self->aq_nic_cfg->flow_control);

	buff_size = HW_ATL_A0_RXBUF_MAX;



	rpb_rx_pkt_buff_size_per_tc_set(self, buff_size, tc);

	rpb_rx_buff_hi_threshold_per_tc_set(self,

	hw_atl_rpb_rx_pkt_buff_size_per_tc_set(self, buff_size, tc);

	hw_atl_rpb_rx_buff_hi_threshold_per_tc_set(self,

						   (buff_size *

						   (1024U / 32U) * 66U) /

						   100U, tc);

	rpb_rx_buff_lo_threshold_per_tc_set(self,

	hw_atl_rpb_rx_buff_lo_threshold_per_tc_set(self,

						   (buff_size *

						   (1024U / 32U) * 50U) /

						   100U, tc);

	rpb_rx_xoff_en_per_tc_set(self, is_rx_flow_control ? 1U : 0U, tc);

	hw_atl_rpb_rx_xoff_en_per_tc_set(self, is_rx_flow_control ? 1U : 0U, tc);



	/* QoS 802.1p priority -> TC mapping */

	for (i_priority = 8U; i_priority--;)

		rpf_rpb_user_priority_tc_map_set(self, i_priority, 0U);

		hw_atl_rpf_rpb_user_priority_tc_map_set(self, i_priority, 0U);



	return aq_hw_err_from_flags(self);

}
@@ -159,10 +161,11 @@ static int hw_atl_a0_hw_rss_hash_set(struct aq_hw_s *self, 
	for (i = 10, addr = 0U; i--; ++addr) {

		u32 key_data = cfg->is_rss ?

			__swab32(rss_params->hash_secret_key[i]) : 0U;

		rpf_rss_key_wr_data_set(self, key_data);

		rpf_rss_key_addr_set(self, addr);

		rpf_rss_key_wr_en_set(self, 1U);

		AQ_HW_WAIT_FOR(rpf_rss_key_wr_en_get(self) == 0, 1000U, 10U);

		hw_atl_rpf_rss_key_wr_data_set(self, key_data);

		hw_atl_rpf_rss_key_addr_set(self, addr);

		hw_atl_rpf_rss_key_wr_en_set(self, 1U);

		AQ_HW_WAIT_FOR(hw_atl_rpf_rss_key_wr_en_get(self) == 0,

			       1000U, 10U);

		if (err < 0)

			goto err_exit;

	}
@@ -192,10 +195,11 @@ static int hw_atl_a0_hw_rss_set(struct aq_hw_s *self, 
	}



	for (i = ARRAY_SIZE(bitary); i--;) {

		rpf_rss_redir_tbl_wr_data_set(self, bitary[i]);

		rpf_rss_redir_tbl_addr_set(self, i);

		rpf_rss_redir_wr_en_set(self, 1U);

		AQ_HW_WAIT_FOR(rpf_rss_redir_wr_en_get(self) == 0, 1000U, 10U);

		hw_atl_rpf_rss_redir_tbl_wr_data_set(self, bitary[i]);

		hw_atl_rpf_rss_redir_tbl_addr_set(self, i);

		hw_atl_rpf_rss_redir_wr_en_set(self, 1U);

		AQ_HW_WAIT_FOR(hw_atl_rpf_rss_redir_wr_en_get(self) == 0,

			       1000U, 10U);

		if (err < 0)

			goto err_exit;

	}
@@ -210,35 +214,35 @@ static int hw_atl_a0_hw_offload_set(struct aq_hw_s *self, 
				    struct aq_nic_cfg_s *aq_nic_cfg)

{

	/* TX checksums offloads*/

	tpo_ipv4header_crc_offload_en_set(self, 1);

	tpo_tcp_udp_crc_offload_en_set(self, 1);

	hw_atl_tpo_ipv4header_crc_offload_en_set(self, 1);

	hw_atl_tpo_tcp_udp_crc_offload_en_set(self, 1);



	/* RX checksums offloads*/

	rpo_ipv4header_crc_offload_en_set(self, 1);

	rpo_tcp_udp_crc_offload_en_set(self, 1);

	hw_atl_rpo_ipv4header_crc_offload_en_set(self, 1);

	hw_atl_rpo_tcp_udp_crc_offload_en_set(self, 1);



	/* LSO offloads*/

	tdm_large_send_offload_en_set(self, 0xFFFFFFFFU);

	hw_atl_tdm_large_send_offload_en_set(self, 0xFFFFFFFFU);



	return aq_hw_err_from_flags(self);

}



static int hw_atl_a0_hw_init_tx_path(struct aq_hw_s *self)

{

	thm_lso_tcp_flag_of_first_pkt_set(self, 0x0FF6U);

	thm_lso_tcp_flag_of_middle_pkt_set(self, 0x0FF6U);

	thm_lso_tcp_flag_of_last_pkt_set(self, 0x0F7FU);

	hw_atl_thm_lso_tcp_flag_of_first_pkt_set(self, 0x0FF6U);

	hw_atl_thm_lso_tcp_flag_of_middle_pkt_set(self, 0x0FF6U);

	hw_atl_thm_lso_tcp_flag_of_last_pkt_set(self, 0x0F7FU);



	/* Tx interrupts */

	tdm_tx_desc_wr_wb_irq_en_set(self, 1U);

	hw_atl_tdm_tx_desc_wr_wb_irq_en_set(self, 1U);



	/* misc */

	aq_hw_write_reg(self, 0x00007040U, IS_CHIP_FEATURE(TPO2) ?

			0x00010000U : 0x00000000U);

	tdm_tx_dca_en_set(self, 0U);

	tdm_tx_dca_mode_set(self, 0U);

	hw_atl_tdm_tx_dca_en_set(self, 0U);

	hw_atl_tdm_tx_dca_mode_set(self, 0U);



	tpb_tx_path_scp_ins_en_set(self, 1U);

	hw_atl_tpb_tx_path_scp_ins_en_set(self, 1U);



	return aq_hw_err_from_flags(self);

}
@@ -249,38 +253,38 @@ static int hw_atl_a0_hw_init_rx_path(struct aq_hw_s *self) 
	int i;



	/* Rx TC/RSS number config */

	rpb_rpf_rx_traf_class_mode_set(self, 1U);

	hw_atl_rpb_rpf_rx_traf_class_mode_set(self, 1U);



	/* Rx flow control */

	rpb_rx_flow_ctl_mode_set(self, 1U);

	hw_atl_rpb_rx_flow_ctl_mode_set(self, 1U);



	/* RSS Ring selection */

	reg_rx_flr_rss_control1set(self, cfg->is_rss ?

	hw_atl_reg_rx_flr_rss_control1set(self, cfg->is_rss ?

					0xB3333333U : 0x00000000U);



	/* Multicast filters */

	for (i = HW_ATL_A0_MAC_MAX; i--;) {

		rpfl2_uc_flr_en_set(self, (i == 0U) ? 1U : 0U, i);

		rpfl2unicast_flr_act_set(self, 1U, i);

		hw_atl_rpfl2_uc_flr_en_set(self, (i == 0U) ? 1U : 0U, i);

		hw_atl_rpfl2unicast_flr_act_set(self, 1U, i);

	}



	reg_rx_flr_mcst_flr_msk_set(self, 0x00000000U);

	reg_rx_flr_mcst_flr_set(self, 0x00010FFFU, 0U);

	hw_atl_reg_rx_flr_mcst_flr_msk_set(self, 0x00000000U);

	hw_atl_reg_rx_flr_mcst_flr_set(self, 0x00010FFFU, 0U);



	/* Vlan filters */

	rpf_vlan_outer_etht_set(self, 0x88A8U);

	rpf_vlan_inner_etht_set(self, 0x8100U);

	rpf_vlan_prom_mode_en_set(self, 1);

	hw_atl_rpf_vlan_outer_etht_set(self, 0x88A8U);

	hw_atl_rpf_vlan_inner_etht_set(self, 0x8100U);

	hw_atl_rpf_vlan_prom_mode_en_set(self, 1);



	/* Rx Interrupts */

	rdm_rx_desc_wr_wb_irq_en_set(self, 1U);

	hw_atl_rdm_rx_desc_wr_wb_irq_en_set(self, 1U);



	/* misc */

	rpfl2broadcast_flr_act_set(self, 1U);

	rpfl2broadcast_count_threshold_set(self, 0xFFFFU & (~0U / 256U));

	hw_atl_rpfl2broadcast_flr_act_set(self, 1U);

	hw_atl_rpfl2broadcast_count_threshold_set(self, 0xFFFFU & (~0U / 256U));



	rdm_rx_dca_en_set(self, 0U);

	rdm_rx_dca_mode_set(self, 0U);

	hw_atl_rdm_rx_dca_en_set(self, 0U);

	hw_atl_rdm_rx_dca_mode_set(self, 0U);



	return aq_hw_err_from_flags(self);

}
@@ -299,10 +303,10 @@ static int hw_atl_a0_hw_mac_addr_set(struct aq_hw_s *self, u8 *mac_addr) 
	l = (mac_addr[2] << 24) | (mac_addr[3] << 16) |

		(mac_addr[4] << 8) | mac_addr[5];



	rpfl2_uc_flr_en_set(self, 0U, HW_ATL_A0_MAC);

	rpfl2unicast_dest_addresslsw_set(self, l, HW_ATL_A0_MAC);

	rpfl2unicast_dest_addressmsw_set(self, h, HW_ATL_A0_MAC);

	rpfl2_uc_flr_en_set(self, 1U, HW_ATL_A0_MAC);

	hw_atl_rpfl2_uc_flr_en_set(self, 0U, HW_ATL_A0_MAC);

	hw_atl_rpfl2unicast_dest_addresslsw_set(self, l, HW_ATL_A0_MAC);

	hw_atl_rpfl2unicast_dest_addressmsw_set(self, h, HW_ATL_A0_MAC);

	hw_atl_rpfl2_uc_flr_en_set(self, 1U, HW_ATL_A0_MAC);



	err = aq_hw_err_from_flags(self);
@@ -330,8 +334,8 @@ static int hw_atl_a0_hw_init(struct aq_hw_s *self, u8 *mac_addr) 


	hw_atl_utils_mpi_set(self, MPI_INIT, aq_nic_cfg->link_speed_msk);



	reg_tx_dma_debug_ctl_set(self, 0x800000b8U);

	reg_tx_dma_debug_ctl_set(self, 0x000000b8U);

	hw_atl_reg_tx_dma_debug_ctl_set(self, 0x800000b8U);

	hw_atl_reg_tx_dma_debug_ctl_set(self, 0x000000b8U);



	hw_atl_a0_hw_qos_set(self);

	hw_atl_a0_hw_rss_set(self, &aq_nic_cfg->aq_rss);
@@ -346,15 +350,14 @@ static int hw_atl_a0_hw_init(struct aq_hw_s *self, u8 *mac_addr) 
		goto err_exit;



	/* Interrupts */

	reg_irq_glb_ctl_set(self,

	hw_atl_reg_irq_glb_ctl_set(self,

				   aq_hw_atl_igcr_table_[aq_nic_cfg->irq_type]

						 [(aq_nic_cfg->vecs > 1U) ?

						 1 : 0]);

					[(aq_nic_cfg->vecs > 1U) ? 1 : 0]);



	itr_irq_auto_masklsw_set(self, aq_nic_cfg->aq_hw_caps->irq_mask);

	hw_atl_itr_irq_auto_masklsw_set(self, aq_nic_cfg->aq_hw_caps->irq_mask);



	/* Interrupts */

	reg_gen_irq_map_set(self,

	hw_atl_reg_gen_irq_map_set(self,

				   ((HW_ATL_A0_ERR_INT << 0x18) | (1U << 0x1F)) |

				   ((HW_ATL_A0_ERR_INT << 0x10) | (1U << 0x17)) |

				   ((HW_ATL_A0_ERR_INT << 8) | (1U << 0xF)) |
@@ -369,28 +372,28 @@ err_exit: 
static int hw_atl_a0_hw_ring_tx_start(struct aq_hw_s *self,

				      struct aq_ring_s *ring)

{

	tdm_tx_desc_en_set(self, 1, ring->idx);

	hw_atl_tdm_tx_desc_en_set(self, 1, ring->idx);

	return aq_hw_err_from_flags(self);

}



static int hw_atl_a0_hw_ring_rx_start(struct aq_hw_s *self,

				      struct aq_ring_s *ring)

{

	rdm_rx_desc_en_set(self, 1, ring->idx);

	hw_atl_rdm_rx_desc_en_set(self, 1, ring->idx);

	return aq_hw_err_from_flags(self);

}



static int hw_atl_a0_hw_start(struct aq_hw_s *self)

{

	tpb_tx_buff_en_set(self, 1);

	rpb_rx_buff_en_set(self, 1);

	hw_atl_tpb_tx_buff_en_set(self, 1);

	hw_atl_rpb_rx_buff_en_set(self, 1);

	return aq_hw_err_from_flags(self);

}



static int hw_atl_a0_hw_tx_ring_tail_update(struct aq_hw_s *self,

					    struct aq_ring_s *ring)

{

	reg_tx_dma_desc_tail_ptr_set(self, ring->sw_tail, ring->idx);

	hw_atl_reg_tx_dma_desc_tail_ptr_set(self, ring->sw_tail, ring->idx);

	return 0;

}
@@ -476,36 +479,37 @@ static int hw_atl_a0_hw_ring_rx_init(struct aq_hw_s *self, 
	u32 dma_desc_addr_lsw = (u32)aq_ring->dx_ring_pa;

	u32 dma_desc_addr_msw = (u32)(((u64)aq_ring->dx_ring_pa) >> 32);



	rdm_rx_desc_en_set(self, false, aq_ring->idx);

	hw_atl_rdm_rx_desc_en_set(self, false, aq_ring->idx);



	rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx);

	hw_atl_rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx);



	reg_rx_dma_desc_base_addresslswset(self, dma_desc_addr_lsw,

	hw_atl_reg_rx_dma_desc_base_addresslswset(self, dma_desc_addr_lsw,

						  aq_ring->idx);



	reg_rx_dma_desc_base_addressmswset(self,

					   dma_desc_addr_msw, aq_ring->idx);

	hw_atl_reg_rx_dma_desc_base_addressmswset(self,

						  dma_desc_addr_msw,

						  aq_ring->idx);



	rdm_rx_desc_len_set(self, aq_ring->size / 8U, aq_ring->idx);

	hw_atl_rdm_rx_desc_len_set(self, aq_ring->size / 8U, aq_ring->idx);



	rdm_rx_desc_data_buff_size_set(self,

	hw_atl_rdm_rx_desc_data_buff_size_set(self,

					      AQ_CFG_RX_FRAME_MAX / 1024U,

				       aq_ring->idx);



	rdm_rx_desc_head_buff_size_set(self, 0U, aq_ring->idx);

	rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx);

	rpo_rx_desc_vlan_stripping_set(self, 0U, aq_ring->idx);

	hw_atl_rdm_rx_desc_head_buff_size_set(self, 0U, aq_ring->idx);

	hw_atl_rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx);

	hw_atl_rpo_rx_desc_vlan_stripping_set(self, 0U, aq_ring->idx);



	/* Rx ring set mode */



	/* Mapping interrupt vector */

	itr_irq_map_rx_set(self, aq_ring_param->vec_idx, aq_ring->idx);

	itr_irq_map_en_rx_set(self, true, aq_ring->idx);

	hw_atl_itr_irq_map_rx_set(self, aq_ring_param->vec_idx, aq_ring->idx);

	hw_atl_itr_irq_map_en_rx_set(self, true, aq_ring->idx);



	rdm_cpu_id_set(self, aq_ring_param->cpu, aq_ring->idx);

	rdm_rx_desc_dca_en_set(self, 0U, aq_ring->idx);

	rdm_rx_head_dca_en_set(self, 0U, aq_ring->idx);

	rdm_rx_pld_dca_en_set(self, 0U, aq_ring->idx);

	hw_atl_rdm_cpu_id_set(self, aq_ring_param->cpu, aq_ring->idx);

	hw_atl_rdm_rx_desc_dca_en_set(self, 0U, aq_ring->idx);

	hw_atl_rdm_rx_head_dca_en_set(self, 0U, aq_ring->idx);

	hw_atl_rdm_rx_pld_dca_en_set(self, 0U, aq_ring->idx);



	return aq_hw_err_from_flags(self);

}
@@ -517,25 +521,25 @@ static int hw_atl_a0_hw_ring_tx_init(struct aq_hw_s *self, 
	u32 dma_desc_lsw_addr = (u32)aq_ring->dx_ring_pa;

	u32 dma_desc_msw_addr = (u32)(((u64)aq_ring->dx_ring_pa) >> 32);



	reg_tx_dma_desc_base_addresslswset(self, dma_desc_lsw_addr,

	hw_atl_reg_tx_dma_desc_base_addresslswset(self, dma_desc_lsw_addr,

						  aq_ring->idx);



	reg_tx_dma_desc_base_addressmswset(self, dma_desc_msw_addr,

	hw_atl_reg_tx_dma_desc_base_addressmswset(self, dma_desc_msw_addr,

						  aq_ring->idx);



	tdm_tx_desc_len_set(self, aq_ring->size / 8U, aq_ring->idx);

	hw_atl_tdm_tx_desc_len_set(self, aq_ring->size / 8U, aq_ring->idx);



	hw_atl_a0_hw_tx_ring_tail_update(self, aq_ring);



	/* Set Tx threshold */

	tdm_tx_desc_wr_wb_threshold_set(self, 0U, aq_ring->idx);

	hw_atl_tdm_tx_desc_wr_wb_threshold_set(self, 0U, aq_ring->idx);



	/* Mapping interrupt vector */

	itr_irq_map_tx_set(self, aq_ring_param->vec_idx, aq_ring->idx);

	itr_irq_map_en_tx_set(self, true, aq_ring->idx);

	hw_atl_itr_irq_map_tx_set(self, aq_ring_param->vec_idx, aq_ring->idx);

	hw_atl_itr_irq_map_en_tx_set(self, true, aq_ring->idx);



	tdm_cpu_id_set(self, aq_ring_param->cpu, aq_ring->idx);

	tdm_tx_desc_dca_en_set(self, 0U, aq_ring->idx);

	hw_atl_tdm_cpu_id_set(self, aq_ring_param->cpu, aq_ring->idx);

	hw_atl_tdm_tx_desc_dca_en_set(self, 0U, aq_ring->idx);



	return aq_hw_err_from_flags(self);

}
@@ -556,7 +560,7 @@ static int hw_atl_a0_hw_ring_rx_fill(struct aq_hw_s *self, 
		rxd->hdr_addr = 0U;

	}



	reg_rx_dma_desc_tail_ptr_set(self, sw_tail_old, ring->idx);

	hw_atl_reg_rx_dma_desc_tail_ptr_set(self, sw_tail_old, ring->idx);



	return aq_hw_err_from_flags(self);

}
@@ -565,13 +569,13 @@ static int hw_atl_a0_hw_ring_tx_head_update(struct aq_hw_s *self, 
					    struct aq_ring_s *ring)

{

	int err = 0;

	unsigned int hw_head_ = tdm_tx_desc_head_ptr_get(self, ring->idx);

	unsigned int hw_head = hw_atl_tdm_tx_desc_head_ptr_get(self, ring->idx);



	if (aq_utils_obj_test(&self->flags, AQ_HW_FLAG_ERR_UNPLUG)) {

		err = -ENXIO;

		goto err_exit;

	}

	ring->hw_head = hw_head_;

	ring->hw_head = hw_head;

	err = aq_hw_err_from_flags(self);



err_exit:
@@ -595,15 +599,16 @@ static int hw_atl_a0_hw_ring_rx_receive(struct aq_hw_s *self, 


		if (!(rxd_wb->status & 0x5U)) { /* RxD is not done */

			if ((1U << 4) &

				reg_rx_dma_desc_status_get(self, ring->idx)) {

			rdm_rx_desc_en_set(self, false, ring->idx);

			rdm_rx_desc_res_set(self, true, ring->idx);

			rdm_rx_desc_res_set(self, false, ring->idx);

			rdm_rx_desc_en_set(self, true, ring->idx);

			hw_atl_reg_rx_dma_desc_status_get(self, ring->idx)) {

				hw_atl_rdm_rx_desc_en_set(self, false, ring->idx);

				hw_atl_rdm_rx_desc_res_set(self, true, ring->idx);

				hw_atl_rdm_rx_desc_res_set(self, false, ring->idx);

				hw_atl_rdm_rx_desc_en_set(self, true, ring->idx);

			}



			if (ring->hw_head ||

			    (rdm_rx_desc_head_ptr_get(self, ring->idx) < 2U)) {

			    (hw_atl_rdm_rx_desc_head_ptr_get(self,

							     ring->idx) < 2U)) {

				break;

			} else if (!(rxd_wb->status & 0x1U)) {

				struct hw_atl_rxd_wb_s *rxd_wb1 =
@@ -686,17 +691,17 @@ static int hw_atl_a0_hw_ring_rx_receive(struct aq_hw_s *self, 


static int hw_atl_a0_hw_irq_enable(struct aq_hw_s *self, u64 mask)

{

	itr_irq_msk_setlsw_set(self, LODWORD(mask) |

	hw_atl_itr_irq_msk_setlsw_set(self, LODWORD(mask) |

			       (1U << HW_ATL_A0_ERR_INT));

	return aq_hw_err_from_flags(self);

}



static int hw_atl_a0_hw_irq_disable(struct aq_hw_s *self, u64 mask)

{

	itr_irq_msk_clearlsw_set(self, LODWORD(mask));

	itr_irq_status_clearlsw_set(self, LODWORD(mask));

	hw_atl_itr_irq_msk_clearlsw_set(self, LODWORD(mask));

	hw_atl_itr_irq_status_clearlsw_set(self, LODWORD(mask));



	if ((1U << 16) & reg_gen_irq_status_get(self))

	if ((1U << 16) & hw_atl_reg_gen_irq_status_get(self))

		atomic_inc(&self->dpc);



	return aq_hw_err_from_flags(self);
@@ -704,7 +709,7 @@ static int hw_atl_a0_hw_irq_disable(struct aq_hw_s *self, u64 mask) 


static int hw_atl_a0_hw_irq_read(struct aq_hw_s *self, u64 *mask)

{

	*mask = itr_irq_statuslsw_get(self);

	*mask = hw_atl_itr_irq_statuslsw_get(self);

	return aq_hw_err_from_flags(self);

}
@@ -715,15 +720,17 @@ static int hw_atl_a0_hw_packet_filter_set(struct aq_hw_s *self, 
{

	unsigned int i = 0U;



	rpfl2promiscuous_mode_en_set(self, IS_FILTER_ENABLED(IFF_PROMISC));

	rpfl2multicast_flr_en_set(self, IS_FILTER_ENABLED(IFF_MULTICAST), 0);

	rpfl2broadcast_en_set(self, IS_FILTER_ENABLED(IFF_BROADCAST));

	hw_atl_rpfl2promiscuous_mode_en_set(self,

					    IS_FILTER_ENABLED(IFF_PROMISC));

	hw_atl_rpfl2multicast_flr_en_set(self,

					 IS_FILTER_ENABLED(IFF_MULTICAST), 0);

	hw_atl_rpfl2broadcast_en_set(self, IS_FILTER_ENABLED(IFF_BROADCAST));



	self->aq_nic_cfg->is_mc_list_enabled =

			IS_FILTER_ENABLED(IFF_MULTICAST);



	for (i = HW_ATL_A0_MAC_MIN; i < HW_ATL_A0_MAC_MAX; ++i)

		rpfl2_uc_flr_en_set(self,

		hw_atl_rpfl2_uc_flr_en_set(self,

					   (self->aq_nic_cfg->is_mc_list_enabled &&

					   (i <= self->aq_nic_cfg->mc_list_count)) ?

					    1U : 0U, i);
@@ -753,15 +760,17 @@ static int hw_atl_a0_hw_multicast_list_set(struct aq_hw_s *self, 
		u32 l = (ar_mac[i][2] << 24) | (ar_mac[i][3] << 16) |

					(ar_mac[i][4] << 8) | ar_mac[i][5];



		rpfl2_uc_flr_en_set(self, 0U, HW_ATL_A0_MAC_MIN + i);

		hw_atl_rpfl2_uc_flr_en_set(self, 0U, HW_ATL_A0_MAC_MIN + i);



		rpfl2unicast_dest_addresslsw_set(self,

						 l, HW_ATL_A0_MAC_MIN + i);

		hw_atl_rpfl2unicast_dest_addresslsw_set(self,

							l,

							HW_ATL_A0_MAC_MIN + i);



		rpfl2unicast_dest_addressmsw_set(self,

						 h, HW_ATL_A0_MAC_MIN + i);

		hw_atl_rpfl2unicast_dest_addressmsw_set(self,

							h,

							HW_ATL_A0_MAC_MIN + i);



		rpfl2_uc_flr_en_set(self,

		hw_atl_rpfl2_uc_flr_en_set(self,

					   (self->aq_nic_cfg->is_mc_list_enabled),

					   HW_ATL_A0_MAC_MIN + i);

	}
@@ -815,7 +824,7 @@ static int hw_atl_a0_hw_interrupt_moderation_set(struct aq_hw_s *self) 
	}



	for (i = HW_ATL_A0_RINGS_MAX; i--;)

		reg_irq_thr_set(self, itr_rx, i);

		hw_atl_reg_irq_thr_set(self, itr_rx, i);



	return aq_hw_err_from_flags(self);

}
@@ -829,14 +838,14 @@ static int hw_atl_a0_hw_stop(struct aq_hw_s *self) 
static int hw_atl_a0_hw_ring_tx_stop(struct aq_hw_s *self,

				     struct aq_ring_s *ring)

{

	tdm_tx_desc_en_set(self, 0U, ring->idx);

	hw_atl_tdm_tx_desc_en_set(self, 0U, ring->idx);

	return aq_hw_err_from_flags(self);

}



static int hw_atl_a0_hw_ring_rx_stop(struct aq_hw_s *self,

				     struct aq_ring_s *ring)

{

	rdm_rx_desc_en_set(self, 0U, ring->idx);

	hw_atl_rdm_rx_desc_en_set(self, 0U, ring->idx);

	return aq_hw_err_from_flags(self);

}

drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c

+169 −164

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c

+293 −249

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.h

+284 −260

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c

+15 −15
Original line number Diff line number Diff line
@@ -35,15 +35,15 @@ static int hw_atl_utils_fw_downld_dwords(struct aq_hw_s *self, u32 a, 
{

	int err = 0;



	AQ_HW_WAIT_FOR(reg_glb_cpu_sem_get(self,

	AQ_HW_WAIT_FOR(hw_atl_reg_glb_cpu_sem_get(self,

						  HW_ATL_FW_SM_RAM) == 1U,

						  1U, 10000U);



	if (err < 0) {

		bool is_locked;



		reg_glb_cpu_sem_set(self, 1U, HW_ATL_FW_SM_RAM);

		is_locked = reg_glb_cpu_sem_get(self, HW_ATL_FW_SM_RAM);

		hw_atl_reg_glb_cpu_sem_set(self, 1U, HW_ATL_FW_SM_RAM);

		is_locked = hw_atl_reg_glb_cpu_sem_get(self, HW_ATL_FW_SM_RAM);

		if (!is_locked) {

			err = -ETIME;

			goto err_exit;
@@ -64,7 +64,7 @@ static int hw_atl_utils_fw_downld_dwords(struct aq_hw_s *self, u32 a, 
		*(p++) = aq_hw_read_reg(self, 0x0000020CU);

	}



	reg_glb_cpu_sem_set(self, 1U, HW_ATL_FW_SM_RAM);

	hw_atl_reg_glb_cpu_sem_set(self, 1U, HW_ATL_FW_SM_RAM);



err_exit:

	return err;
@@ -76,7 +76,7 @@ static int hw_atl_utils_fw_upload_dwords(struct aq_hw_s *self, u32 a, u32 *p, 
	int err = 0;

	bool is_locked;



	is_locked = reg_glb_cpu_sem_get(self, HW_ATL_FW_SM_RAM);

	is_locked = hw_atl_reg_glb_cpu_sem_get(self, HW_ATL_FW_SM_RAM);

	if (!is_locked) {

		err = -ETIME;

		goto err_exit;
@@ -95,7 +95,7 @@ static int hw_atl_utils_fw_upload_dwords(struct aq_hw_s *self, u32 a, u32 *p, 
		}

	}



	reg_glb_cpu_sem_set(self, 1U, HW_ATL_FW_SM_RAM);

	hw_atl_reg_glb_cpu_sem_set(self, 1U, HW_ATL_FW_SM_RAM);



err_exit:

	return err;
@@ -131,7 +131,7 @@ static int hw_atl_utils_init_ucp(struct aq_hw_s *self, 
		aq_hw_write_reg(self, HW_ATL_UCP_0X370_REG, ucp_0x370);

	}



	reg_glb_cpu_scratch_scp_set(self, 0x00000000U, 25U);

	hw_atl_reg_glb_cpu_scratch_scp_set(self, 0x00000000U, 25U);



	/* check 10 times by 1ms */

	AQ_HW_WAIT_FOR(0U != (self->mbox_addr =
@@ -280,7 +280,7 @@ void hw_atl_utils_mpi_read_stats(struct aq_hw_s *self, 
		pmbox->stats.ubtc = pmbox->stats.uptc * mtu;

		pmbox->stats.dpc = atomic_read(&self->dpc);

	} else {

		pmbox->stats.dpc = reg_rx_dma_stat_counter7get(self);

		pmbox->stats.dpc = hw_atl_reg_rx_dma_stat_counter7get(self);

	}



err_exit:;
@@ -461,7 +461,7 @@ unsigned int hw_atl_utils_mbps_2_speed_index(unsigned int mbps) 
void hw_atl_utils_hw_chip_features_init(struct aq_hw_s *self, u32 *p)

{

	u32 chip_features = 0U;

	u32 val = reg_glb_mif_id_get(self);

	u32 val = hw_atl_reg_glb_mif_id_get(self);

	u32 mif_rev = val & 0xFFU;



	if ((3U & mif_rev) == 1U) {
@@ -523,10 +523,10 @@ int hw_atl_utils_update_stats(struct aq_hw_s *self) 
		AQ_SDELTA(dpc);

	}

#undef AQ_SDELTA

	self->curr_stats.dma_pkt_rc = stats_rx_dma_good_pkt_counterlsw_get(self);

	self->curr_stats.dma_pkt_tc = stats_tx_dma_good_pkt_counterlsw_get(self);

	self->curr_stats.dma_oct_rc = stats_rx_dma_good_octet_counterlsw_get(self);

	self->curr_stats.dma_oct_tc = stats_tx_dma_good_octet_counterlsw_get(self);

	self->curr_stats.dma_pkt_rc = hw_atl_stats_rx_dma_good_pkt_counterlsw_get(self);

	self->curr_stats.dma_pkt_tc = hw_atl_stats_tx_dma_good_pkt_counterlsw_get(self);

	self->curr_stats.dma_oct_rc = hw_atl_stats_rx_dma_good_octet_counterlsw_get(self);

	self->curr_stats.dma_oct_tc = hw_atl_stats_tx_dma_good_octet_counterlsw_get(self);



	memcpy(&self->last_stats, &mbox.stats, sizeof(mbox.stats));