Loading Documentation/m68k/README.buddha +1 −1 Original line number Diff line number Diff line Loading @@ -29,7 +29,7 @@ address is written to $4a, then the whole Byte is written to $48, while it doesn't matter how often you're writing to $4a as long as $48 is not touched. After $48 has been written, the whole card disappears from $e8 and is mapped to the new address just written. Make shure $4a is written before $48, address just written. Make sure $4a is written before $48, otherwise your chance is only 1:16 to find the board :-). The local memory-map is even active when mapped to $e8: Loading Documentation/networking/ifenslave.c +1 −1 Original line number Diff line number Diff line Loading @@ -87,7 +87,7 @@ * would fail and generate an error message in the system log. * - For opt_c: slave should not be set to the master's setting * while it is running. It was already set during enslave. To * simplify things, it is now handeled separately. * simplify things, it is now handled separately. * * - 2003/12/01 - Shmulik Hen <shmulik.hen at intel dot com> * - Code cleanup and style changes Loading arch/arm/lib/copy_template.S +1 −1 Original line number Diff line number Diff line Loading @@ -236,7 +236,7 @@ /* * Abort preanble and completion macros. * Abort preamble and completion macros. * If a fixup handler is required then those macros must surround it. * It is assumed that the fixup code will handle the private part of * the exit macro. Loading drivers/char/mxser.h +1 −1 Original line number Diff line number Diff line Loading @@ -118,7 +118,7 @@ // enable CTS interrupt #define MOXA_MUST_IER_ECTSI 0x80 // eanble RTS interrupt // enable RTS interrupt #define MOXA_MUST_IER_ERTSI 0x40 // enable Xon/Xoff interrupt #define MOXA_MUST_IER_XINT 0x20 Loading drivers/char/synclink.c +1 −1 Original line number Diff line number Diff line Loading @@ -5996,7 +5996,7 @@ static void usc_set_async_mode( struct mgsl_struct *info ) * <15..8> ? RxFIFO IRQ Request Level * * Note: For async mode the receive FIFO level must be set * to 0 to aviod the situation where the FIFO contains fewer bytes * to 0 to avoid the situation where the FIFO contains fewer bytes * than the trigger level and no more data is expected. * * <7> 0 Exited Hunt IA (Interrupt Arm) Loading Loading
Documentation/m68k/README.buddha +1 −1 Original line number Diff line number Diff line Loading @@ -29,7 +29,7 @@ address is written to $4a, then the whole Byte is written to $48, while it doesn't matter how often you're writing to $4a as long as $48 is not touched. After $48 has been written, the whole card disappears from $e8 and is mapped to the new address just written. Make shure $4a is written before $48, address just written. Make sure $4a is written before $48, otherwise your chance is only 1:16 to find the board :-). The local memory-map is even active when mapped to $e8: Loading
Documentation/networking/ifenslave.c +1 −1 Original line number Diff line number Diff line Loading @@ -87,7 +87,7 @@ * would fail and generate an error message in the system log. * - For opt_c: slave should not be set to the master's setting * while it is running. It was already set during enslave. To * simplify things, it is now handeled separately. * simplify things, it is now handled separately. * * - 2003/12/01 - Shmulik Hen <shmulik.hen at intel dot com> * - Code cleanup and style changes Loading
arch/arm/lib/copy_template.S +1 −1 Original line number Diff line number Diff line Loading @@ -236,7 +236,7 @@ /* * Abort preanble and completion macros. * Abort preamble and completion macros. * If a fixup handler is required then those macros must surround it. * It is assumed that the fixup code will handle the private part of * the exit macro. Loading
drivers/char/mxser.h +1 −1 Original line number Diff line number Diff line Loading @@ -118,7 +118,7 @@ // enable CTS interrupt #define MOXA_MUST_IER_ECTSI 0x80 // eanble RTS interrupt // enable RTS interrupt #define MOXA_MUST_IER_ERTSI 0x40 // enable Xon/Xoff interrupt #define MOXA_MUST_IER_XINT 0x20 Loading
drivers/char/synclink.c +1 −1 Original line number Diff line number Diff line Loading @@ -5996,7 +5996,7 @@ static void usc_set_async_mode( struct mgsl_struct *info ) * <15..8> ? RxFIFO IRQ Request Level * * Note: For async mode the receive FIFO level must be set * to 0 to aviod the situation where the FIFO contains fewer bytes * to 0 to avoid the situation where the FIFO contains fewer bytes * than the trigger level and no more data is expected. * * <7> 0 Exited Hunt IA (Interrupt Arm) Loading