Commit 6d68e517 authored by popcornmix's avatar popcornmix
Browse files

Merge remote-tracking branch 'stable/linux-4.14.y' into rpi-4.14.y

parents 5fa970b0 592f5569

Makefile

+1 −1
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

VERSION = 4

PATCHLEVEL = 14

SUBLEVEL = 89

SUBLEVEL = 90

EXTRAVERSION =

NAME = Petit Gorille

arch/arc/include/asm/io.h

+72 −0
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ 
#include <linux/types.h>

#include <asm/byteorder.h>

#include <asm/page.h>

#include <asm/unaligned.h>



#ifdef CONFIG_ISA_ARCV2

#include <asm/barrier.h>
@@ -94,6 +95,42 @@ static inline u32 __raw_readl(const volatile void __iomem *addr) 
	return w;

}



/*

 * {read,write}s{b,w,l}() repeatedly access the same IO address in

 * native endianness in 8-, 16-, 32-bit chunks {into,from} memory,

 * @count times

 */

#define __raw_readsx(t,f) \

static inline void __raw_reads##f(const volatile void __iomem *addr,	\

				  void *ptr, unsigned int count)	\

{									\

	bool is_aligned = ((unsigned long)ptr % ((t) / 8)) == 0;	\

	u##t *buf = ptr;						\

									\

	if (!count)							\

		return;							\

									\

	/* Some ARC CPU's don't support unaligned accesses */		\

	if (is_aligned) {						\

		do {							\

			u##t x = __raw_read##f(addr);			\

			*buf++ = x;					\

		} while (--count);					\

	} else {							\

		do {							\

			u##t x = __raw_read##f(addr);			\

			put_unaligned(x, buf++);			\

		} while (--count);					\

	}								\

}



#define __raw_readsb __raw_readsb

__raw_readsx(8, b)

#define __raw_readsw __raw_readsw

__raw_readsx(16, w)

#define __raw_readsl __raw_readsl

__raw_readsx(32, l)



#define __raw_writeb __raw_writeb

static inline void __raw_writeb(u8 b, volatile void __iomem *addr)

{
@@ -126,6 +163,35 @@ static inline void __raw_writel(u32 w, volatile void __iomem *addr) 


}



#define __raw_writesx(t,f)						\

static inline void __raw_writes##f(volatile void __iomem *addr, 	\

				   const void *ptr, unsigned int count)	\

{									\

	bool is_aligned = ((unsigned long)ptr % ((t) / 8)) == 0;	\

	const u##t *buf = ptr;						\

									\

	if (!count)							\

		return;							\

									\

	/* Some ARC CPU's don't support unaligned accesses */		\

	if (is_aligned) {						\

		do {							\

			__raw_write##f(*buf++, addr);			\

		} while (--count);					\

	} else {							\

		do {							\

			__raw_write##f(get_unaligned(buf++), addr);	\

		} while (--count);					\

	}								\

}



#define __raw_writesb __raw_writesb

__raw_writesx(8, b)

#define __raw_writesw __raw_writesw

__raw_writesx(16, w)

#define __raw_writesl __raw_writesl

__raw_writesx(32, l)



/*

 * MMIO can also get buffered/optimized in micro-arch, so barriers needed

 * Based on ARM model for the typical use case
@@ -141,10 +207,16 @@ static inline void __raw_writel(u32 w, volatile void __iomem *addr) 
#define readb(c)		({ u8  __v = readb_relaxed(c); __iormb(); __v; })

#define readw(c)		({ u16 __v = readw_relaxed(c); __iormb(); __v; })

#define readl(c)		({ u32 __v = readl_relaxed(c); __iormb(); __v; })

#define readsb(p,d,l)		({ __raw_readsb(p,d,l); __iormb(); })

#define readsw(p,d,l)		({ __raw_readsw(p,d,l); __iormb(); })

#define readsl(p,d,l)		({ __raw_readsl(p,d,l); __iormb(); })



#define writeb(v,c)		({ __iowmb(); writeb_relaxed(v,c); })

#define writew(v,c)		({ __iowmb(); writew_relaxed(v,c); })

#define writel(v,c)		({ __iowmb(); writel_relaxed(v,c); })

#define writesb(p,d,l)		({ __iowmb(); __raw_writesb(p,d,l); })

#define writesw(p,d,l)		({ __iowmb(); __raw_writesw(p,d,l); })

#define writesl(p,d,l)		({ __iowmb(); __raw_writesl(p,d,l); })



/*

 * Relaxed API for drivers which can handle barrier ordering themselves

arch/arm/mach-mmp/cputype.h

+4 −2
Original line number Diff line number Diff line
@@ -44,10 +44,12 @@ static inline int cpu_is_pxa910(void) 
#define cpu_is_pxa910()	(0)

#endif



#ifdef CONFIG_CPU_MMP2

#if defined(CONFIG_CPU_MMP2) || defined(CONFIG_MACH_MMP2_DT)

static inline int cpu_is_mmp2(void)

{

	return (((read_cpuid_id() >> 8) & 0xff) == 0x58);

	return (((read_cpuid_id() >> 8) & 0xff) == 0x58) &&

		(((mmp_chip_id & 0xfff) == 0x410) ||

		 ((mmp_chip_id & 0xfff) == 0x610));

}

#else

#define cpu_is_mmp2()	(0)

arch/arm/mm/cache-v7.S

+5 −3
Original line number Diff line number Diff line
@@ -359,14 +359,16 @@ ENTRY(v7_dma_inv_range) 
	ALT_UP(W(nop))

#endif

	mcrne	p15, 0, r0, c7, c14, 1		@ clean & invalidate D / U line

	addne	r0, r0, r2



	tst	r1, r3

	bic	r1, r1, r3

	mcrne	p15, 0, r1, c7, c14, 1		@ clean & invalidate D / U line

1:

	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D / U line

	add	r0, r0, r2

	cmp	r0, r1

1:

	mcrlo	p15, 0, r0, c7, c6, 1		@ invalidate D / U line

	addlo	r0, r0, r2

	cmplo	r0, r1

	blo	1b

	dsb	st

	ret	lr

arch/arm/mm/cache-v7m.S

+9 −5
Original line number Diff line number Diff line
@@ -73,9 +73,11 @@ 
/*

 * dcimvac: Invalidate data cache line by MVA to PoC

 */

.macro dcimvac, rt, tmp

	v7m_cacheop \rt, \tmp, V7M_SCB_DCIMVAC

.irp    c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo

.macro dcimvac\c, rt, tmp

	v7m_cacheop \rt, \tmp, V7M_SCB_DCIMVAC, \c

.endm

.endr



/*

 * dccmvau: Clean data cache line by MVA to PoU
@@ -369,14 +371,16 @@ v7m_dma_inv_range: 
	tst	r0, r3

	bic	r0, r0, r3

	dccimvacne r0, r3

	addne	r0, r0, r2

	subne	r3, r2, #1	@ restore r3, corrupted by v7m's dccimvac

	tst	r1, r3

	bic	r1, r1, r3

	dccimvacne r1, r3

1:

	dcimvac r0, r3

	add	r0, r0, r2

	cmp	r0, r1

1:

	dcimvaclo r0, r3

	addlo	r0, r0, r2

	cmplo	r0, r1

	blo	1b

	dsb	st

	ret	lr