Loading arch/arm/include/asm/outercache.h +0 −1 Original line number Diff line number Diff line Loading @@ -35,7 +35,6 @@ struct outer_cache_fns { void (*resume)(void); /* This is an ARM L2C thing */ void (*set_debug)(unsigned long); void (*write_sec)(unsigned long, unsigned); }; Loading arch/arm/mm/cache-l2x0.c +2 −19 Original line number Diff line number Diff line Loading @@ -81,9 +81,6 @@ static void l2c_write_sec(unsigned long val, void __iomem *base, unsigned reg) */ static inline void l2c_set_debug(void __iomem *base, unsigned long val) { if (outer_cache.set_debug) outer_cache.set_debug(val); else l2c_write_sec(val, base, L2X0_DEBUG_CTRL); } Loading Loading @@ -155,7 +152,6 @@ static inline void cache_sync(void) #if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915) static inline void debug_writel(unsigned long val) { if (outer_cache.set_debug || outer_cache.write_sec) l2c_set_debug(l2x0_base, val); } #else Loading Loading @@ -514,11 +510,6 @@ static const struct l2c_init_data l2c220_data = { * Affects: store buffer * store buffer is not automatically drained. */ static void l2c310_set_debug(unsigned long val) { writel_relaxed(val, l2x0_base + L2X0_DEBUG_CTRL); } static void l2c310_inv_range_erratum(unsigned long start, unsigned long end) { void __iomem *base = l2x0_base; Loading Loading @@ -695,10 +686,6 @@ static void __init l2c310_fixup(void __iomem *base, u32 cache_id, const char *errata[8]; unsigned n = 0; /* For compatibility */ if (revision <= L310_CACHE_ID_RTL_R3P0) fns->set_debug = l2c310_set_debug; if (IS_ENABLED(CONFIG_PL310_ERRATA_588369) && revision < L310_CACHE_ID_RTL_R2P0 && /* For bcm compatibility */ Loading Loading @@ -759,7 +746,6 @@ static const struct l2c_init_data l2c310_init_fns __initconst = { .flush_all = l2c210_flush_all, .disable = l2c_disable, .sync = l2c210_sync, .set_debug = l2c310_set_debug, .resume = l2c310_resume, }, }; Loading Loading @@ -819,8 +805,6 @@ static void __init __l2c_init(const struct l2c_init_data *data, fns.write_sec = outer_cache.write_sec; if (data->fixup) data->fixup(l2x0_base, cache_id, &fns); if (fns.write_sec) fns.set_debug = NULL; /* * Check if l2x0 controller is already enabled. If we are booting Loading Loading @@ -1000,7 +984,6 @@ static const struct l2c_init_data of_l2c310_data __initconst = { .flush_all = l2c210_flush_all, .disable = l2c_disable, .sync = l2c210_sync, .set_debug = l2c310_set_debug, .resume = l2c310_resume, }, }; Loading Loading
arch/arm/include/asm/outercache.h +0 −1 Original line number Diff line number Diff line Loading @@ -35,7 +35,6 @@ struct outer_cache_fns { void (*resume)(void); /* This is an ARM L2C thing */ void (*set_debug)(unsigned long); void (*write_sec)(unsigned long, unsigned); }; Loading
arch/arm/mm/cache-l2x0.c +2 −19 Original line number Diff line number Diff line Loading @@ -81,9 +81,6 @@ static void l2c_write_sec(unsigned long val, void __iomem *base, unsigned reg) */ static inline void l2c_set_debug(void __iomem *base, unsigned long val) { if (outer_cache.set_debug) outer_cache.set_debug(val); else l2c_write_sec(val, base, L2X0_DEBUG_CTRL); } Loading Loading @@ -155,7 +152,6 @@ static inline void cache_sync(void) #if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915) static inline void debug_writel(unsigned long val) { if (outer_cache.set_debug || outer_cache.write_sec) l2c_set_debug(l2x0_base, val); } #else Loading Loading @@ -514,11 +510,6 @@ static const struct l2c_init_data l2c220_data = { * Affects: store buffer * store buffer is not automatically drained. */ static void l2c310_set_debug(unsigned long val) { writel_relaxed(val, l2x0_base + L2X0_DEBUG_CTRL); } static void l2c310_inv_range_erratum(unsigned long start, unsigned long end) { void __iomem *base = l2x0_base; Loading Loading @@ -695,10 +686,6 @@ static void __init l2c310_fixup(void __iomem *base, u32 cache_id, const char *errata[8]; unsigned n = 0; /* For compatibility */ if (revision <= L310_CACHE_ID_RTL_R3P0) fns->set_debug = l2c310_set_debug; if (IS_ENABLED(CONFIG_PL310_ERRATA_588369) && revision < L310_CACHE_ID_RTL_R2P0 && /* For bcm compatibility */ Loading Loading @@ -759,7 +746,6 @@ static const struct l2c_init_data l2c310_init_fns __initconst = { .flush_all = l2c210_flush_all, .disable = l2c_disable, .sync = l2c210_sync, .set_debug = l2c310_set_debug, .resume = l2c310_resume, }, }; Loading Loading @@ -819,8 +805,6 @@ static void __init __l2c_init(const struct l2c_init_data *data, fns.write_sec = outer_cache.write_sec; if (data->fixup) data->fixup(l2x0_base, cache_id, &fns); if (fns.write_sec) fns.set_debug = NULL; /* * Check if l2x0 controller is already enabled. If we are booting Loading Loading @@ -1000,7 +984,6 @@ static const struct l2c_init_data of_l2c310_data __initconst = { .flush_all = l2c210_flush_all, .disable = l2c_disable, .sync = l2c210_sync, .set_debug = l2c310_set_debug, .resume = l2c310_resume, }, }; Loading