Loading drivers/gpu/drm/nouveau/core/engine/disp/nv50.c +12 −10 Original line number Diff line number Diff line Loading @@ -940,7 +940,6 @@ nv50_disp_intr_unk10(struct nv50_disp_priv *priv, u32 super) exec_script(priv, head, 1); } nv_wr32(priv, 0x610024, 0x00000010); nv_wr32(priv, 0x610030, 0x80000000); } Loading Loading @@ -1097,7 +1096,6 @@ nv50_disp_intr_unk20(struct nv50_disp_priv *priv, u32 super) } } nv_wr32(priv, 0x610024, 0x00000020); nv_wr32(priv, 0x610030, 0x80000000); } Loading Loading @@ -1136,22 +1134,23 @@ nv50_disp_intr_unk40(struct nv50_disp_priv *priv, u32 super) } } nv_wr32(priv, 0x610024, 0x00000040); nv_wr32(priv, 0x610030, 0x80000000); } static void nv50_disp_intr_super(struct nv50_disp_priv *priv, u32 intr1) void nv50_disp_intr_supervisor(struct work_struct *work) { struct nv50_disp_priv *priv = container_of(work, struct nv50_disp_priv, supervisor); u32 super = nv_rd32(priv, 0x610030); nv_debug(priv, "supervisor 0x%08x 0x%08x\n", intr1, super); nv_debug(priv, "supervisor 0x%08x 0x%08x\n", priv->super, super); if (intr1 & 0x00000010) if (priv->super & 0x00000010) nv50_disp_intr_unk10(priv, super); if (intr1 & 0x00000020) if (priv->super & 0x00000020) nv50_disp_intr_unk20(priv, super); if (intr1 & 0x00000040) if (priv->super & 0x00000040) nv50_disp_intr_unk40(priv, super); } Loading Loading @@ -1180,7 +1179,9 @@ nv50_disp_intr(struct nouveau_subdev *subdev) } if (intr1 & 0x00000070) { nv50_disp_intr_super(priv, intr1); priv->super = (intr1 & 0x00000070); schedule_work(&priv->supervisor); nv_wr32(priv, 0x610024, priv->super); intr1 &= ~0x00000070; } } Loading @@ -1202,6 +1203,7 @@ nv50_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, nv_engine(priv)->sclass = nv50_disp_base_oclass; nv_engine(priv)->cclass = &nv50_disp_cclass; nv_subdev(priv)->intr = nv50_disp_intr; INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor); priv->sclass = nv50_disp_sclass; priv->head.nr = 2; priv->dac.nr = 3; Loading drivers/gpu/drm/nouveau/core/engine/disp/nv50.h +6 −0 Original line number Diff line number Diff line Loading @@ -15,6 +15,10 @@ struct dcb_output; struct nv50_disp_priv { struct nouveau_disp base; struct nouveau_oclass *sclass; struct work_struct supervisor; u32 super; struct { int nr; } head; Loading Loading @@ -126,6 +130,7 @@ extern struct nouveau_ofuncs nv50_disp_oimm_ofuncs; extern struct nouveau_ofuncs nv50_disp_curs_ofuncs; extern struct nouveau_ofuncs nv50_disp_base_ofuncs; extern struct nouveau_oclass nv50_disp_cclass; void nv50_disp_intr_supervisor(struct work_struct *); void nv50_disp_intr(struct nouveau_subdev *); extern struct nouveau_omthds nv84_disp_base_omthds[]; Loading @@ -139,6 +144,7 @@ extern struct nouveau_ofuncs nvd0_disp_oimm_ofuncs; extern struct nouveau_ofuncs nvd0_disp_curs_ofuncs; extern struct nouveau_ofuncs nvd0_disp_base_ofuncs; extern struct nouveau_oclass nvd0_disp_cclass; void nvd0_disp_intr_supervisor(struct work_struct *); void nvd0_disp_intr(struct nouveau_subdev *); #endif drivers/gpu/drm/nouveau/core/engine/disp/nv84.c +1 −0 Original line number Diff line number Diff line Loading @@ -72,6 +72,7 @@ nv84_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, nv_engine(priv)->sclass = nv84_disp_base_oclass; nv_engine(priv)->cclass = &nv50_disp_cclass; nv_subdev(priv)->intr = nv50_disp_intr; INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor); priv->sclass = nv84_disp_sclass; priv->head.nr = 2; priv->dac.nr = 3; Loading drivers/gpu/drm/nouveau/core/engine/disp/nv94.c +1 −0 Original line number Diff line number Diff line Loading @@ -78,6 +78,7 @@ nv94_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, nv_engine(priv)->sclass = nv94_disp_base_oclass; nv_engine(priv)->cclass = &nv50_disp_cclass; nv_subdev(priv)->intr = nv50_disp_intr; INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor); priv->sclass = nv94_disp_sclass; priv->head.nr = 2; priv->dac.nr = 3; Loading drivers/gpu/drm/nouveau/core/engine/disp/nva0.c +1 −0 Original line number Diff line number Diff line Loading @@ -62,6 +62,7 @@ nva0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, nv_engine(priv)->sclass = nva0_disp_base_oclass; nv_engine(priv)->cclass = &nv50_disp_cclass; nv_subdev(priv)->intr = nv50_disp_intr; INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor); priv->sclass = nva0_disp_sclass; priv->head.nr = 2; priv->dac.nr = 3; Loading Loading
drivers/gpu/drm/nouveau/core/engine/disp/nv50.c +12 −10 Original line number Diff line number Diff line Loading @@ -940,7 +940,6 @@ nv50_disp_intr_unk10(struct nv50_disp_priv *priv, u32 super) exec_script(priv, head, 1); } nv_wr32(priv, 0x610024, 0x00000010); nv_wr32(priv, 0x610030, 0x80000000); } Loading Loading @@ -1097,7 +1096,6 @@ nv50_disp_intr_unk20(struct nv50_disp_priv *priv, u32 super) } } nv_wr32(priv, 0x610024, 0x00000020); nv_wr32(priv, 0x610030, 0x80000000); } Loading Loading @@ -1136,22 +1134,23 @@ nv50_disp_intr_unk40(struct nv50_disp_priv *priv, u32 super) } } nv_wr32(priv, 0x610024, 0x00000040); nv_wr32(priv, 0x610030, 0x80000000); } static void nv50_disp_intr_super(struct nv50_disp_priv *priv, u32 intr1) void nv50_disp_intr_supervisor(struct work_struct *work) { struct nv50_disp_priv *priv = container_of(work, struct nv50_disp_priv, supervisor); u32 super = nv_rd32(priv, 0x610030); nv_debug(priv, "supervisor 0x%08x 0x%08x\n", intr1, super); nv_debug(priv, "supervisor 0x%08x 0x%08x\n", priv->super, super); if (intr1 & 0x00000010) if (priv->super & 0x00000010) nv50_disp_intr_unk10(priv, super); if (intr1 & 0x00000020) if (priv->super & 0x00000020) nv50_disp_intr_unk20(priv, super); if (intr1 & 0x00000040) if (priv->super & 0x00000040) nv50_disp_intr_unk40(priv, super); } Loading Loading @@ -1180,7 +1179,9 @@ nv50_disp_intr(struct nouveau_subdev *subdev) } if (intr1 & 0x00000070) { nv50_disp_intr_super(priv, intr1); priv->super = (intr1 & 0x00000070); schedule_work(&priv->supervisor); nv_wr32(priv, 0x610024, priv->super); intr1 &= ~0x00000070; } } Loading @@ -1202,6 +1203,7 @@ nv50_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, nv_engine(priv)->sclass = nv50_disp_base_oclass; nv_engine(priv)->cclass = &nv50_disp_cclass; nv_subdev(priv)->intr = nv50_disp_intr; INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor); priv->sclass = nv50_disp_sclass; priv->head.nr = 2; priv->dac.nr = 3; Loading
drivers/gpu/drm/nouveau/core/engine/disp/nv50.h +6 −0 Original line number Diff line number Diff line Loading @@ -15,6 +15,10 @@ struct dcb_output; struct nv50_disp_priv { struct nouveau_disp base; struct nouveau_oclass *sclass; struct work_struct supervisor; u32 super; struct { int nr; } head; Loading Loading @@ -126,6 +130,7 @@ extern struct nouveau_ofuncs nv50_disp_oimm_ofuncs; extern struct nouveau_ofuncs nv50_disp_curs_ofuncs; extern struct nouveau_ofuncs nv50_disp_base_ofuncs; extern struct nouveau_oclass nv50_disp_cclass; void nv50_disp_intr_supervisor(struct work_struct *); void nv50_disp_intr(struct nouveau_subdev *); extern struct nouveau_omthds nv84_disp_base_omthds[]; Loading @@ -139,6 +144,7 @@ extern struct nouveau_ofuncs nvd0_disp_oimm_ofuncs; extern struct nouveau_ofuncs nvd0_disp_curs_ofuncs; extern struct nouveau_ofuncs nvd0_disp_base_ofuncs; extern struct nouveau_oclass nvd0_disp_cclass; void nvd0_disp_intr_supervisor(struct work_struct *); void nvd0_disp_intr(struct nouveau_subdev *); #endif
drivers/gpu/drm/nouveau/core/engine/disp/nv84.c +1 −0 Original line number Diff line number Diff line Loading @@ -72,6 +72,7 @@ nv84_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, nv_engine(priv)->sclass = nv84_disp_base_oclass; nv_engine(priv)->cclass = &nv50_disp_cclass; nv_subdev(priv)->intr = nv50_disp_intr; INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor); priv->sclass = nv84_disp_sclass; priv->head.nr = 2; priv->dac.nr = 3; Loading
drivers/gpu/drm/nouveau/core/engine/disp/nv94.c +1 −0 Original line number Diff line number Diff line Loading @@ -78,6 +78,7 @@ nv94_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, nv_engine(priv)->sclass = nv94_disp_base_oclass; nv_engine(priv)->cclass = &nv50_disp_cclass; nv_subdev(priv)->intr = nv50_disp_intr; INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor); priv->sclass = nv94_disp_sclass; priv->head.nr = 2; priv->dac.nr = 3; Loading
drivers/gpu/drm/nouveau/core/engine/disp/nva0.c +1 −0 Original line number Diff line number Diff line Loading @@ -62,6 +62,7 @@ nva0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, nv_engine(priv)->sclass = nva0_disp_base_oclass; nv_engine(priv)->cclass = &nv50_disp_cclass; nv_subdev(priv)->intr = nv50_disp_intr; INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor); priv->sclass = nva0_disp_sclass; priv->head.nr = 2; priv->dac.nr = 3; Loading