Commit 58eb131c authored by popcornmix's avatar popcornmix
Browse files

Merge remote-tracking branch 'stable/linux-4.14.y' into rpi-4.14.y

parents 4fca48b7 2c6025eb

Documentation/devicetree/bindings/clock/sunxi-ccu.txt

+4 −0
Original line number Diff line number Diff line
@@ -20,6 +20,7 @@ Required properties : 
		- "allwinner,sun50i-a64-ccu"

		- "allwinner,sun50i-a64-r-ccu"

		- "allwinner,sun50i-h5-ccu"

		- "allwinner,sun50i-h6-ccu"

		- "nextthing,gr8-ccu"



- reg: Must contain the registers base address and length
@@ -31,6 +32,9 @@ Required properties : 
- #clock-cells : must contain 1

- #reset-cells : must contain 1



For the main CCU on H6, one more clock is needed:

- "iosc": the SoC's internal frequency oscillator



For the PRCM CCUs on A83T/H3/A64, two more clocks are needed:

- "pll-periph": the SoC's peripheral PLL from the main CCU

- "iosc": the SoC's internal frequency oscillator

Documentation/devicetree/bindings/dma/mv-xor-v2.txt

+5 −1
Original line number Diff line number Diff line
@@ -11,7 +11,11 @@ Required properties: 
  interrupts.



Optional properties:

- clocks: Optional reference to the clock used by the XOR engine.

- clocks: Optional reference to the clocks used by the XOR engine.

- clock-names: mandatory if there is a second clock, in this case the

   name must be "core" for the first clock and "reg" for the second

   one





Example:

Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt

+3 −2
Original line number Diff line number Diff line
@@ -20,7 +20,8 @@ Required subnode-properties: 
		gpio: cpuclkoutgrp0, udlclkoutgrp0, i2c1grp0, i2c2grp0,

		      i2c3grp0, i2s0grp0, i2s1grp0, i2srefclkgrp0, spi0grp0,

		      spi1grp0, pciedebuggrp0, uart0grp0, uart0grp1, uart1grp0,

		      uart2grp0, uart2grp1, uart3grp0, uart4grp0, uart5grp0

		      uart2grp0, uart2grp1, uart3grp0, uart4grp0, uart5grp0,

		      uart5nocts

		cpuclkout: cpuclkoutgrp0

		udlclkout: udlclkoutgrp0

		i2c1: i2c1grp0
@@ -37,7 +38,7 @@ Required subnode-properties: 
		uart2: uart2grp0, uart2grp1

		uart3: uart3grp0

		uart4: uart4grp0

		uart5: uart5grp0

		uart5: uart5grp0, uart5nocts

		nand: nandgrp0

		sdio0: sdio0grp0

		sdio1: sdio1grp0

Makefile

+2 −8
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

VERSION = 4

PATCHLEVEL = 14

SUBLEVEL = 44

SUBLEVEL = 48

EXTRAVERSION =

NAME = Petit Gorille
@@ -369,11 +369,6 @@ HOSTCXXFLAGS := -O2 $(HOST_LFS_CFLAGS) 
HOSTLDFLAGS  := $(HOST_LFS_LDFLAGS)

HOST_LOADLIBES := $(HOST_LFS_LIBS)



ifeq ($(shell $(HOSTCC) -v 2>&1 | grep -c "clang version"), 1)

HOSTCFLAGS  += -Wno-unused-value -Wno-unused-parameter \

		-Wno-missing-field-initializers -fno-delete-null-pointer-checks

endif



# Make variables (CC, etc...)

AS		= $(CROSS_COMPILE)as

LD		= $(CROSS_COMPILE)ld
@@ -711,7 +706,6 @@ KBUILD_CFLAGS += $(stackp-flag) 


ifeq ($(cc-name),clang)

KBUILD_CPPFLAGS += $(call cc-option,-Qunused-arguments,)

KBUILD_CFLAGS += $(call cc-disable-warning, unused-variable)

KBUILD_CFLAGS += $(call cc-disable-warning, format-invalid-specifier)

KBUILD_CFLAGS += $(call cc-disable-warning, gnu)

KBUILD_CFLAGS += $(call cc-disable-warning, address-of-packed-member)
@@ -729,9 +723,9 @@ else 
# These warnings generated too much noise in a regular build.

# Use make W=1 to enable them (see scripts/Makefile.extrawarn)

KBUILD_CFLAGS += $(call cc-disable-warning, unused-but-set-variable)

KBUILD_CFLAGS += $(call cc-disable-warning, unused-const-variable)

endif



KBUILD_CFLAGS += $(call cc-disable-warning, unused-const-variable)

ifdef CONFIG_FRAME_POINTER

KBUILD_CFLAGS	+= -fno-omit-frame-pointer -fno-optimize-sibling-calls

else

arch/alpha/include/asm/xchg.h

+22 −8
Original line number Diff line number Diff line
@@ -12,6 +12,10 @@ 
 * Atomic exchange.

 * Since it can be used to implement critical sections

 * it must clobber "memory" (also for interrupts in UP).

 *

 * The leading and the trailing memory barriers guarantee that these

 * operations are fully ordered.

 *

 */



static inline unsigned long
@@ -19,6 +23,7 @@ ____xchg(_u8, volatile char *m, unsigned long val) 
{

	unsigned long ret, tmp, addr64;



	smp_mb();

	__asm__ __volatile__(

	"	andnot	%4,7,%3\n"

	"	insbl	%1,%4,%1\n"
@@ -43,6 +48,7 @@ ____xchg(_u16, volatile short *m, unsigned long val) 
{

	unsigned long ret, tmp, addr64;



	smp_mb();

	__asm__ __volatile__(

	"	andnot	%4,7,%3\n"

	"	inswl	%1,%4,%1\n"
@@ -67,6 +73,7 @@ ____xchg(_u32, volatile int *m, unsigned long val) 
{

	unsigned long dummy;



	smp_mb();

	__asm__ __volatile__(

	"1:	ldl_l %0,%4\n"

	"	bis $31,%3,%1\n"
@@ -87,6 +94,7 @@ ____xchg(_u64, volatile long *m, unsigned long val) 
{

	unsigned long dummy;



	smp_mb();

	__asm__ __volatile__(

	"1:	ldq_l %0,%4\n"

	"	bis $31,%3,%1\n"
@@ -128,10 +136,12 @@ ____xchg(, volatile void *ptr, unsigned long x, int size) 
 * store NEW in MEM.  Return the initial value in MEM.  Success is

 * indicated by comparing RETURN with OLD.

 *

 * The memory barrier should be placed in SMP only when we actually

 * make the change. If we don't change anything (so if the returned

 * prev is equal to old) then we aren't acquiring anything new and

 * we don't need any memory barrier as far I can tell.

 * The leading and the trailing memory barriers guarantee that these

 * operations are fully ordered.

 *

 * The trailing memory barrier is placed in SMP unconditionally, in

 * order to guarantee that dependency ordering is preserved when a

 * dependency is headed by an unsuccessful operation.

 */



static inline unsigned long
@@ -139,6 +149,7 @@ ____cmpxchg(_u8, volatile char *m, unsigned char old, unsigned char new) 
{

	unsigned long prev, tmp, cmp, addr64;



	smp_mb();

	__asm__ __volatile__(

	"	andnot	%5,7,%4\n"

	"	insbl	%1,%5,%1\n"
@@ -150,8 +161,8 @@ ____cmpxchg(_u8, volatile char *m, unsigned char old, unsigned char new) 
	"	or	%1,%2,%2\n"

	"	stq_c	%2,0(%4)\n"

	"	beq	%2,3f\n"

		__ASM__MB

	"2:\n"

		__ASM__MB

	".subsection 2\n"

	"3:	br	1b\n"

	".previous"
@@ -166,6 +177,7 @@ ____cmpxchg(_u16, volatile short *m, unsigned short old, unsigned short new) 
{

	unsigned long prev, tmp, cmp, addr64;



	smp_mb();

	__asm__ __volatile__(

	"	andnot	%5,7,%4\n"

	"	inswl	%1,%5,%1\n"
@@ -177,8 +189,8 @@ ____cmpxchg(_u16, volatile short *m, unsigned short old, unsigned short new) 
	"	or	%1,%2,%2\n"

	"	stq_c	%2,0(%4)\n"

	"	beq	%2,3f\n"

		__ASM__MB

	"2:\n"

		__ASM__MB

	".subsection 2\n"

	"3:	br	1b\n"

	".previous"
@@ -193,6 +205,7 @@ ____cmpxchg(_u32, volatile int *m, int old, int new) 
{

	unsigned long prev, cmp;



	smp_mb();

	__asm__ __volatile__(

	"1:	ldl_l %0,%5\n"

	"	cmpeq %0,%3,%1\n"
@@ -200,8 +213,8 @@ ____cmpxchg(_u32, volatile int *m, int old, int new) 
	"	mov %4,%1\n"

	"	stl_c %1,%2\n"

	"	beq %1,3f\n"

		__ASM__MB

	"2:\n"

		__ASM__MB

	".subsection 2\n"

	"3:	br 1b\n"

	".previous"
@@ -216,6 +229,7 @@ ____cmpxchg(_u64, volatile long *m, unsigned long old, unsigned long new) 
{

	unsigned long prev, cmp;



	smp_mb();

	__asm__ __volatile__(

	"1:	ldq_l %0,%5\n"

	"	cmpeq %0,%3,%1\n"
@@ -223,8 +237,8 @@ ____cmpxchg(_u64, volatile long *m, unsigned long old, unsigned long new) 
	"	mov %4,%1\n"

	"	stq_c %1,%2\n"

	"	beq %1,3f\n"

		__ASM__MB

	"2:\n"

		__ASM__MB

	".subsection 2\n"

	"3:	br 1b\n"

	".previous"